eFPGA ver3
diff --git a/gds/eFPGA_top.gds b/gds/eFPGA_top.gds
new file mode 100644
index 0000000..9847607
--- /dev/null
+++ b/gds/eFPGA_top.gds
Binary files differ
diff --git a/lef/eFPGA_top.lef b/lef/eFPGA_top.lef
new file mode 100644
index 0000000..33e1539
--- /dev/null
+++ b/lef/eFPGA_top.lef
@@ -0,0 +1,124177 @@
+##
+## LEF for PtnCells ;
+## created by Innovus v19.11-s128_1 on Mon Nov 15 19:56:37 2021
+##
+
+VERSION 5.7 ;
+
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO eFPGA_top
+ CLASS BLOCK ;
+ SIZE 2840.040000 BY 3439.780000 ;
+ FOREIGN eFPGA_top 0.000000 0.000000 ;
+ ORIGIN 0 0 ;
+ SYMMETRY X Y R90 ;
+ PIN wb_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 24.8534 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 123.683 LAYER met2 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.318 LAYER met2 ;
+ ANTENNAMAXAREACAR 86.5085 LAYER met2 ;
+ ANTENNAMAXSIDEAREACAR 418.009 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAMAXCUTCAR 0.772327 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.814 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 4.808 LAYER met3 ;
+ ANTENNAGATEAREA 0.318 LAYER met3 ;
+ ANTENNAMAXAREACAR 89.0682 LAYER met3 ;
+ ANTENNAMAXSIDEAREACAR 433.129 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAMAXCUTCAR 0.898113 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 198.252 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 1059.7 LAYER met4 ;
+ ANTENNAGATEAREA 8.283 LAYER met4 ;
+ ANTENNAMAXAREACAR 113.003 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 561.065 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.967925 LAYER via4 ;
+ PORT
+ LAYER met2 ;
+ RECT 10.280000 0.000000 10.420000 0.485000 ;
+ END
+ END wb_clk_i
+ PIN wbs_stb_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 36.500000 0.000000 36.640000 0.485000 ;
+ END
+ END wbs_stb_i
+ PIN wbs_cyc_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 62.720000 0.000000 62.860000 0.485000 ;
+ END
+ END wbs_cyc_i
+ PIN wbs_we_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 89.400000 0.000000 89.540000 0.485000 ;
+ END
+ END wbs_we_i
+ PIN wbs_dat_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 115.620000 0.000000 115.760000 0.485000 ;
+ END
+ END wbs_dat_i[31]
+ PIN wbs_dat_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 142.300000 0.000000 142.440000 0.485000 ;
+ END
+ END wbs_dat_i[30]
+ PIN wbs_dat_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 168.520000 0.000000 168.660000 0.485000 ;
+ END
+ END wbs_dat_i[29]
+ PIN wbs_dat_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 195.200000 0.000000 195.340000 0.485000 ;
+ END
+ END wbs_dat_i[28]
+ PIN wbs_dat_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 221.420000 0.000000 221.560000 0.485000 ;
+ END
+ END wbs_dat_i[27]
+ PIN wbs_dat_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 248.100000 0.000000 248.240000 0.485000 ;
+ END
+ END wbs_dat_i[26]
+ PIN wbs_dat_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 274.320000 0.000000 274.460000 0.485000 ;
+ END
+ END wbs_dat_i[25]
+ PIN wbs_dat_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 301.000000 0.000000 301.140000 0.485000 ;
+ END
+ END wbs_dat_i[24]
+ PIN wbs_dat_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 327.220000 0.000000 327.360000 0.485000 ;
+ END
+ END wbs_dat_i[23]
+ PIN wbs_dat_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 353.900000 0.000000 354.040000 0.485000 ;
+ END
+ END wbs_dat_i[22]
+ PIN wbs_dat_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 380.120000 0.000000 380.260000 0.485000 ;
+ END
+ END wbs_dat_i[21]
+ PIN wbs_dat_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 406.800000 0.000000 406.940000 0.485000 ;
+ END
+ END wbs_dat_i[20]
+ PIN wbs_dat_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 433.020000 0.000000 433.160000 0.485000 ;
+ END
+ END wbs_dat_i[19]
+ PIN wbs_dat_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 459.700000 0.000000 459.840000 0.485000 ;
+ END
+ END wbs_dat_i[18]
+ PIN wbs_dat_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 485.920000 0.000000 486.060000 0.485000 ;
+ END
+ END wbs_dat_i[17]
+ PIN wbs_dat_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 512.600000 0.000000 512.740000 0.485000 ;
+ END
+ END wbs_dat_i[16]
+ PIN wbs_dat_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 538.820000 0.000000 538.960000 0.485000 ;
+ END
+ END wbs_dat_i[15]
+ PIN wbs_dat_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 565.500000 0.000000 565.640000 0.485000 ;
+ END
+ END wbs_dat_i[14]
+ PIN wbs_dat_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 591.720000 0.000000 591.860000 0.485000 ;
+ END
+ END wbs_dat_i[13]
+ PIN wbs_dat_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 618.400000 0.000000 618.540000 0.485000 ;
+ END
+ END wbs_dat_i[12]
+ PIN wbs_dat_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 644.620000 0.000000 644.760000 0.485000 ;
+ END
+ END wbs_dat_i[11]
+ PIN wbs_dat_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 671.300000 0.000000 671.440000 0.485000 ;
+ END
+ END wbs_dat_i[10]
+ PIN wbs_dat_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 697.520000 0.000000 697.660000 0.485000 ;
+ END
+ END wbs_dat_i[9]
+ PIN wbs_dat_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 724.200000 0.000000 724.340000 0.485000 ;
+ END
+ END wbs_dat_i[8]
+ PIN wbs_dat_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 750.420000 0.000000 750.560000 0.485000 ;
+ END
+ END wbs_dat_i[7]
+ PIN wbs_dat_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 777.100000 0.000000 777.240000 0.485000 ;
+ END
+ END wbs_dat_i[6]
+ PIN wbs_dat_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 803.320000 0.000000 803.460000 0.485000 ;
+ END
+ END wbs_dat_i[5]
+ PIN wbs_dat_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 830.000000 0.000000 830.140000 0.485000 ;
+ END
+ END wbs_dat_i[4]
+ PIN wbs_dat_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 856.220000 0.000000 856.360000 0.485000 ;
+ END
+ END wbs_dat_i[3]
+ PIN wbs_dat_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 882.900000 0.000000 883.040000 0.485000 ;
+ END
+ END wbs_dat_i[2]
+ PIN wbs_dat_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 909.120000 0.000000 909.260000 0.485000 ;
+ END
+ END wbs_dat_i[1]
+ PIN wbs_dat_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 935.800000 0.000000 935.940000 0.485000 ;
+ END
+ END wbs_dat_i[0]
+ PIN wbs_adr_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 962.020000 0.000000 962.160000 0.485000 ;
+ END
+ END wbs_adr_i[31]
+ PIN wbs_adr_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 988.240000 0.000000 988.380000 0.485000 ;
+ END
+ END wbs_adr_i[30]
+ PIN wbs_adr_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1014.920000 0.000000 1015.060000 0.485000 ;
+ END
+ END wbs_adr_i[29]
+ PIN wbs_adr_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1041.140000 0.000000 1041.280000 0.485000 ;
+ END
+ END wbs_adr_i[28]
+ PIN wbs_adr_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1067.820000 0.000000 1067.960000 0.485000 ;
+ END
+ END wbs_adr_i[27]
+ PIN wbs_adr_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1094.040000 0.000000 1094.180000 0.485000 ;
+ END
+ END wbs_adr_i[26]
+ PIN wbs_adr_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1120.720000 0.000000 1120.860000 0.485000 ;
+ END
+ END wbs_adr_i[25]
+ PIN wbs_adr_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1146.940000 0.000000 1147.080000 0.485000 ;
+ END
+ END wbs_adr_i[24]
+ PIN wbs_adr_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1173.620000 0.000000 1173.760000 0.485000 ;
+ END
+ END wbs_adr_i[23]
+ PIN wbs_adr_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1199.840000 0.000000 1199.980000 0.485000 ;
+ END
+ END wbs_adr_i[22]
+ PIN wbs_adr_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1226.520000 0.000000 1226.660000 0.485000 ;
+ END
+ END wbs_adr_i[21]
+ PIN wbs_adr_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1252.740000 0.000000 1252.880000 0.485000 ;
+ END
+ END wbs_adr_i[20]
+ PIN wbs_adr_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1279.420000 0.000000 1279.560000 0.485000 ;
+ END
+ END wbs_adr_i[19]
+ PIN wbs_adr_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1305.640000 0.000000 1305.780000 0.485000 ;
+ END
+ END wbs_adr_i[18]
+ PIN wbs_adr_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1332.320000 0.000000 1332.460000 0.485000 ;
+ END
+ END wbs_adr_i[17]
+ PIN wbs_adr_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1358.540000 0.000000 1358.680000 0.485000 ;
+ END
+ END wbs_adr_i[16]
+ PIN wbs_adr_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1385.220000 0.000000 1385.360000 0.485000 ;
+ END
+ END wbs_adr_i[15]
+ PIN wbs_adr_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1411.440000 0.000000 1411.580000 0.485000 ;
+ END
+ END wbs_adr_i[14]
+ PIN wbs_adr_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1438.120000 0.000000 1438.260000 0.485000 ;
+ END
+ END wbs_adr_i[13]
+ PIN wbs_adr_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1464.340000 0.000000 1464.480000 0.485000 ;
+ END
+ END wbs_adr_i[12]
+ PIN wbs_adr_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1491.020000 0.000000 1491.160000 0.485000 ;
+ END
+ END wbs_adr_i[11]
+ PIN wbs_adr_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1517.240000 0.000000 1517.380000 0.485000 ;
+ END
+ END wbs_adr_i[10]
+ PIN wbs_adr_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1543.920000 0.000000 1544.060000 0.485000 ;
+ END
+ END wbs_adr_i[9]
+ PIN wbs_adr_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1570.140000 0.000000 1570.280000 0.485000 ;
+ END
+ END wbs_adr_i[8]
+ PIN wbs_adr_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1596.820000 0.000000 1596.960000 0.485000 ;
+ END
+ END wbs_adr_i[7]
+ PIN wbs_adr_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1623.040000 0.000000 1623.180000 0.485000 ;
+ END
+ END wbs_adr_i[6]
+ PIN wbs_adr_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1649.720000 0.000000 1649.860000 0.485000 ;
+ END
+ END wbs_adr_i[5]
+ PIN wbs_adr_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1675.940000 0.000000 1676.080000 0.485000 ;
+ END
+ END wbs_adr_i[4]
+ PIN wbs_adr_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1702.620000 0.000000 1702.760000 0.485000 ;
+ END
+ END wbs_adr_i[3]
+ PIN wbs_adr_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1728.840000 0.000000 1728.980000 0.485000 ;
+ END
+ END wbs_adr_i[2]
+ PIN wbs_adr_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1755.520000 0.000000 1755.660000 0.485000 ;
+ END
+ END wbs_adr_i[1]
+ PIN wbs_adr_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 1781.740000 0.000000 1781.880000 0.485000 ;
+ END
+ END wbs_adr_i[0]
+ PIN wbs_dat_o[31]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 1808.420000 0.000000 1808.560000 0.485000 ;
+ END
+ END wbs_dat_o[31]
+ PIN wbs_dat_o[30]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5266 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.623 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 1834.640000 0.000000 1834.780000 0.485000 ;
+ END
+ END wbs_dat_o[30]
+ PIN wbs_dat_o[29]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5266 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.623 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 1861.320000 0.000000 1861.460000 0.485000 ;
+ END
+ END wbs_dat_o[29]
+ PIN wbs_dat_o[28]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 1887.540000 0.000000 1887.680000 0.485000 ;
+ END
+ END wbs_dat_o[28]
+ PIN wbs_dat_o[27]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 1913.760000 0.000000 1913.900000 0.485000 ;
+ END
+ END wbs_dat_o[27]
+ PIN wbs_dat_o[26]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5266 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.623 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 1940.440000 0.000000 1940.580000 0.485000 ;
+ END
+ END wbs_dat_o[26]
+ PIN wbs_dat_o[25]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 1966.660000 0.000000 1966.800000 0.485000 ;
+ END
+ END wbs_dat_o[25]
+ PIN wbs_dat_o[24]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 1993.340000 0.000000 1993.480000 0.485000 ;
+ END
+ END wbs_dat_o[24]
+ PIN wbs_dat_o[23]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.479 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.385 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2019.560000 0.000000 2019.700000 0.485000 ;
+ END
+ END wbs_dat_o[23]
+ PIN wbs_dat_o[22]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2046.240000 0.000000 2046.380000 0.485000 ;
+ END
+ END wbs_dat_o[22]
+ PIN wbs_dat_o[21]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2072.460000 0.000000 2072.600000 0.485000 ;
+ END
+ END wbs_dat_o[21]
+ PIN wbs_dat_o[20]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.6386 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 8.183 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2099.140000 0.000000 2099.280000 0.485000 ;
+ END
+ END wbs_dat_o[20]
+ PIN wbs_dat_o[19]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2125.360000 0.000000 2125.500000 0.485000 ;
+ END
+ END wbs_dat_o[19]
+ PIN wbs_dat_o[18]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2152.040000 0.000000 2152.180000 0.485000 ;
+ END
+ END wbs_dat_o[18]
+ PIN wbs_dat_o[17]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.6386 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 8.183 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2178.260000 0.000000 2178.400000 0.485000 ;
+ END
+ END wbs_dat_o[17]
+ PIN wbs_dat_o[16]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2204.940000 0.000000 2205.080000 0.485000 ;
+ END
+ END wbs_dat_o[16]
+ PIN wbs_dat_o[15]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2231.160000 0.000000 2231.300000 0.485000 ;
+ END
+ END wbs_dat_o[15]
+ PIN wbs_dat_o[14]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2257.840000 0.000000 2257.980000 0.485000 ;
+ END
+ END wbs_dat_o[14]
+ PIN wbs_dat_o[13]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2284.060000 0.000000 2284.200000 0.485000 ;
+ END
+ END wbs_dat_o[13]
+ PIN wbs_dat_o[12]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2310.740000 0.000000 2310.880000 0.485000 ;
+ END
+ END wbs_dat_o[12]
+ PIN wbs_dat_o[11]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.479 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.385 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2336.960000 0.000000 2337.100000 0.485000 ;
+ END
+ END wbs_dat_o[11]
+ PIN wbs_dat_o[10]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2363.640000 0.000000 2363.780000 0.485000 ;
+ END
+ END wbs_dat_o[10]
+ PIN wbs_dat_o[9]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2389.860000 0.000000 2390.000000 0.485000 ;
+ END
+ END wbs_dat_o[9]
+ PIN wbs_dat_o[8]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2416.540000 0.000000 2416.680000 0.485000 ;
+ END
+ END wbs_dat_o[8]
+ PIN wbs_dat_o[7]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.6386 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 8.183 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2442.760000 0.000000 2442.900000 0.485000 ;
+ END
+ END wbs_dat_o[7]
+ PIN wbs_dat_o[6]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2469.440000 0.000000 2469.580000 0.485000 ;
+ END
+ END wbs_dat_o[6]
+ PIN wbs_dat_o[5]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.479 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.385 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2495.660000 0.000000 2495.800000 0.485000 ;
+ END
+ END wbs_dat_o[5]
+ PIN wbs_dat_o[4]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2522.340000 0.000000 2522.480000 0.485000 ;
+ END
+ END wbs_dat_o[4]
+ PIN wbs_dat_o[3]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2548.560000 0.000000 2548.700000 0.485000 ;
+ END
+ END wbs_dat_o[3]
+ PIN wbs_dat_o[2]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2575.240000 0.000000 2575.380000 0.485000 ;
+ END
+ END wbs_dat_o[2]
+ PIN wbs_dat_o[1]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5742 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.861 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2601.460000 0.000000 2601.600000 0.485000 ;
+ END
+ END wbs_dat_o[1]
+ PIN wbs_dat_o[0]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.5266 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.623 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2628.140000 0.000000 2628.280000 0.485000 ;
+ END
+ END wbs_dat_o[0]
+ PIN la_data_out[6]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 279.959 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1399.52 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 5.8308 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 31.312 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 2654.360000 0.000000 2654.500000 0.485000 ;
+ END
+ END la_data_out[6]
+ PIN la_data_out[5]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 223.518 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1117.19 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 7.6848 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 41.2 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 2681.040000 0.000000 2681.180000 0.485000 ;
+ END
+ END la_data_out[5]
+ PIN la_data_out[4]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 90.2072 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 450.639 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 2.9917 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 16.896 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 4.1448 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 22.576 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.252 LAYER met4 ;
+ ANTENNAMAXAREACAR 62.9222 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 319.089 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.680159 LAYER via4 ;
+ PORT
+ LAYER met2 ;
+ RECT 2707.260000 0.000000 2707.400000 0.485000 ;
+ END
+ END la_data_out[4]
+ PIN la_data_out[3]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 12.725 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 63.497 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2733.940000 0.000000 2734.080000 0.485000 ;
+ END
+ END la_data_out[3]
+ PIN la_data_out[2]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 1.8598 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 9.289 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2760.160000 0.000000 2760.300000 0.485000 ;
+ END
+ END la_data_out[2]
+ PIN la_data_out[1]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 2.1677 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 10.6575 LAYER met2 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.7425 LAYER met2 ;
+ ANTENNAMAXAREACAR 4.3336 LAYER met2 ;
+ ANTENNAMAXSIDEAREACAR 20.134 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAMAXCUTCAR 0.153401 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.255 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3 ;
+ ANTENNAGATEAREA 0.7425 LAYER met3 ;
+ ANTENNAMAXAREACAR 4.67704 LAYER met3 ;
+ ANTENNAMAXSIDEAREACAR 22.569 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAMAXCUTCAR 0.207273 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 1.9488 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 10.864 LAYER met4 ;
+ ANTENNAGATEAREA 0.7425 LAYER met4 ;
+ ANTENNAMAXAREACAR 7.30168 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 37.2007 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.207273 LAYER via4 ;
+ PORT
+ LAYER met2 ;
+ RECT 2786.840000 0.000000 2786.980000 0.485000 ;
+ END
+ END la_data_out[1]
+ PIN la_data_out[0]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met2 ;
+ ANTENNAPARTIALMETALAREA 23.1494 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 115.619 LAYER met2 ;
+ PORT
+ LAYER met2 ;
+ RECT 2813.060000 0.000000 2813.200000 0.485000 ;
+ END
+ END la_data_out[0]
+ PIN io_in[37]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 0.4347 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 29.2344 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 158.008 LAYER met3 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met3 ;
+ ANTENNAMAXAREACAR 49.1469 LAYER met3 ;
+ ANTENNAMAXSIDEAREACAR 243.702 LAYER met3 ;
+ ANTENNAMAXCUTCAR 0.574843 LAYER via3 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 10.490000 0.800000 10.790000 ;
+ END
+ END io_in[37]
+ PIN io_in[36]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 0.4347 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 70.3944 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 379.88 LAYER met3 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met3 ;
+ ANTENNAMAXAREACAR 75.5212 LAYER met3 ;
+ ANTENNAMAXSIDEAREACAR 385.545 LAYER met3 ;
+ ANTENNAMAXCUTCAR 0.766688 LAYER via3 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 261.200000 0.800000 261.500000 ;
+ END
+ END io_in[36]
+ PIN io_in[35]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 41.2246 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 219.856 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 734.738 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 3919.07 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 542.849 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 2876.46 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.601839 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 511.910000 0.800000 512.210000 ;
+ END
+ END io_in[35]
+ PIN io_in[34]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 33.3346 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 177.776 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 543.542 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 2900.3 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 413.718 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 2187.99 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.793684 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 763.230000 0.800000 763.530000 ;
+ END
+ END io_in[34]
+ PIN io_in[33]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 44.6146 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 237.936 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 523.961 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 2794.93 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 400.105 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 2115.16 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.601839 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1013.940000 0.800000 1014.240000 ;
+ END
+ END io_in[33]
+ PIN io_in[32]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 8.3116 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 44.32 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 396.179 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 2113.42 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 330.897 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 1745.65 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.793684 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1264.650000 0.800000 1264.950000 ;
+ END
+ END io_in[32]
+ PIN io_in[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 43.0156 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 229.408 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 311.585 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 1662.26 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 256.351 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 1348.48 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.601839 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1515.970000 0.800000 1516.270000 ;
+ END
+ END io_in[31]
+ PIN io_in[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 44.2816 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 236.16 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 184.583 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 984.912 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 163.756 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 854.228 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.793684 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1766.680000 0.800000 1766.980000 ;
+ END
+ END io_in[30]
+ PIN io_in[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 9.5296 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 50.816 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 100.769 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 537.904 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 137.133 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 712.645 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.601839 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2017.390000 0.800000 2017.690000 ;
+ END
+ END io_in[29]
+ PIN io_in[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 0.2386 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.264 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 26.7018 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 142.88 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 87.3765 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 446.869 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.793684 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2268.710000 0.800000 2269.010000 ;
+ END
+ END io_in[28]
+ PIN io_in[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 34.3216 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 183.04 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 110.086 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 588.064 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 121.605 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 630.145 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.601839 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2519.420000 0.800000 2519.720000 ;
+ END
+ END io_in[27]
+ PIN io_in[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 15.3256 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 81.728 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 236.738 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 1263.07 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 218.452 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 1145.94 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.793684 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2770.740000 0.800000 2771.040000 ;
+ END
+ END io_in[26]
+ PIN io_in[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 45.8896 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 244.736 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 0.4347 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 321.818 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 1716.83 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.4817 LAYER met4 ;
+ ANTENNAMAXAREACAR 261.186 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 1374.26 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.601839 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 3021.450000 0.800000 3021.750000 ;
+ END
+ END io_in[25]
+ PIN io_in[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 14.5216 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 77.44 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 4.6134 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 26.016 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.126 LAYER met4 ;
+ ANTENNAMAXAREACAR 103.594 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 533.389 LAYER met4 ;
+ ANTENNAMAXCUTCAR 1.04286 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 3272.160000 0.800000 3272.460000 ;
+ END
+ END io_in[24]
+ PIN io_in[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 1.337 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 6.524 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.255 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 4.5108 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 24.528 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.126 LAYER met4 ;
+ ANTENNAMAXAREACAR 111.511 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 564.135 LAYER met4 ;
+ ANTENNAMAXCUTCAR 1.04286 LAYER via4 ;
+ PORT
+ LAYER met2 ;
+ RECT 227.860000 3439.295000 228.000000 3439.780000 ;
+ END
+ END io_in[23]
+ PIN io_in[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 189.534 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 947.156 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 1.6176 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 9.568 LAYER met3 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.126 LAYER met3 ;
+ ANTENNAMAXAREACAR 114.182 LAYER met3 ;
+ ANTENNAMAXSIDEAREACAR 570.278 LAYER met3 ;
+ ANTENNAMAXCUTCAR 0.725397 LAYER via3 ;
+ PORT
+ LAYER met2 ;
+ RECT 554.000000 3439.295000 554.140000 3439.780000 ;
+ END
+ END io_in[22]
+ PIN io_in[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 7.0919 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 35.1155 LAYER met2 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.126 LAYER met2 ;
+ ANTENNAMAXAREACAR 68.3631 LAYER met2 ;
+ ANTENNAMAXSIDEAREACAR 328.064 LAYER met2 ;
+ ANTENNAMAXCUTCAR 0.407937 LAYER via2 ;
+ PORT
+ LAYER met2 ;
+ RECT 880.600000 3439.295000 880.740000 3439.780000 ;
+ END
+ END io_in[21]
+ PIN io_in[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 7.4366 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 36.904 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.255 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 2.3148 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 12.816 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.126 LAYER met4 ;
+ ANTENNAMAXAREACAR 61.0345 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 321.556 LAYER met4 ;
+ ANTENNAMAXCUTCAR 1.04286 LAYER via4 ;
+ PORT
+ LAYER met2 ;
+ RECT 1207.200000 3439.295000 1207.340000 3439.780000 ;
+ END
+ END io_in[20]
+ PIN io_in[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 8.4992 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 42.217 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.255 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 3.7788 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 20.624 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.126 LAYER met4 ;
+ ANTENNAMAXAREACAR 62.7282 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 318.929 LAYER met4 ;
+ ANTENNAMAXCUTCAR 1.04286 LAYER via4 ;
+ PORT
+ LAYER met2 ;
+ RECT 1533.800000 3439.295000 1533.940000 3439.780000 ;
+ END
+ END io_in[19]
+ PIN io_in[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 9.5296 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 47.369 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.2509 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 3.9618 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 21.6 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.126 LAYER met4 ;
+ ANTENNAMAXAREACAR 81.5591 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 413.73 LAYER met4 ;
+ ANTENNAMAXCUTCAR 1.04286 LAYER via4 ;
+ PORT
+ LAYER met2 ;
+ RECT 1859.940000 3439.295000 1860.080000 3439.780000 ;
+ END
+ END io_in[18]
+ PIN io_in[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 45.0504 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 224.973 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.255 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 8.1708 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 44.048 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.495 LAYER met4 ;
+ ANTENNAMAXAREACAR 24.2418 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 127.774 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.265455 LAYER via4 ;
+ PORT
+ LAYER met2 ;
+ RECT 2186.540000 3439.295000 2186.680000 3439.780000 ;
+ END
+ END io_in[17]
+ PIN io_in[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 78.9976 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 394.709 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.255 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 4.5588 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 24.784 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.495 LAYER met4 ;
+ ANTENNAMAXAREACAR 16.1463 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 84.7273 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.265455 LAYER via4 ;
+ PORT
+ LAYER met2 ;
+ RECT 2513.140000 3439.295000 2513.280000 3439.780000 ;
+ END
+ END io_in[16]
+ PIN io_in[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 69.1444 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 345.443 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.2509 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.808 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 9.0858 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 48.928 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.495 LAYER met4 ;
+ ANTENNAMAXAREACAR 26.7764 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 139.077 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.265455 LAYER via4 ;
+ PORT
+ LAYER met2 ;
+ RECT 2839.280000 3439.295000 2839.420000 3439.780000 ;
+ END
+ END io_in[15]
+ PIN io_in[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 28.1574 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 150.616 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 8.4018 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 45.28 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.495 LAYER met4 ;
+ ANTENNAMAXAREACAR 58.6634 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 298.01 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.265455 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 3283.750000 2840.040000 3284.050000 ;
+ END
+ END io_in[14]
+ PIN io_in[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 16.1443 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 86.568 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 3.9618 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 21.6 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.495 LAYER met4 ;
+ ANTENNAMAXAREACAR 13.5404 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 71.3374 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.265455 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 3050.120000 2840.040000 3050.420000 ;
+ END
+ END io_in[13]
+ PIN io_in[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 0.4674 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 2.936 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 3.7788 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 20.624 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 1.485 LAYER met4 ;
+ ANTENNAMAXAREACAR 3.82135 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 18.7677 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.0884848 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2815.880000 2840.040000 2816.180000 ;
+ END
+ END io_in[12]
+ PIN io_in[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 0.5574 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 3.416 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 4.5588 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 24.784 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.495 LAYER met4 ;
+ ANTENNAMAXAREACAR 16.1285 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 84.1616 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.265455 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2582.250000 2840.040000 2582.550000 ;
+ END
+ END io_in[11]
+ PIN io_in[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 5.3833 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 29.176 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 3.9618 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 21.6 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.99 LAYER met4 ;
+ ANTENNAMAXAREACAR 10.9512 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 54.3535 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.132727 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2348.620000 2840.040000 2348.920000 ;
+ END
+ END io_in[10]
+ PIN io_in[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 0.5574 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 3.416 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 2.1318 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 11.84 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.99 LAYER met4 ;
+ ANTENNAMAXAREACAR 6.92141 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 34.4091 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.132727 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2114.380000 2840.040000 2114.680000 ;
+ END
+ END io_in[9]
+ PIN io_in[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 0.4224 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 2.728 LAYER met3 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.99 LAYER met3 ;
+ ANTENNAMAXAREACAR 37.1426 LAYER met3 ;
+ ANTENNAMAXSIDEAREACAR 184.287 LAYER met3 ;
+ ANTENNAMAXCUTCAR 0.0923232 LAYER via3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1880.750000 2840.040000 1881.050000 ;
+ END
+ END io_in[8]
+ PIN io_in[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 3.0222 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 17.032 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 4.3758 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 23.808 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.99 LAYER met4 ;
+ ANTENNAMAXAREACAR 14.7414 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 73.9182 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.132727 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1647.120000 2840.040000 1647.420000 ;
+ END
+ END io_in[7]
+ PIN io_in[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1412.880000 2840.040000 1413.180000 ;
+ END
+ END io_in[6]
+ PIN io_in[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 17.5314 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 93.944 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 1.9488 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 10.864 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.7425 LAYER met4 ;
+ ANTENNAMAXAREACAR 2.62465 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 14.6316 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1179.250000 2840.040000 1179.550000 ;
+ END
+ END io_in[5]
+ PIN io_in[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 3.4513 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 18.872 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 3.2298 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 17.696 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.1965 LAYER met4 ;
+ ANTENNAMAXAREACAR 27.1349 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 138.906 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.668702 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 945.620000 2840.040000 945.920000 ;
+ END
+ END io_in[4]
+ PIN io_in[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 13.3873 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 71.864 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 3.2298 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 17.696 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.1965 LAYER met4 ;
+ ANTENNAMAXAREACAR 26.2422 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 136.957 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.668702 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 711.380000 2840.040000 711.680000 ;
+ END
+ END io_in[3]
+ PIN io_in[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 0.5604 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 3.464 LAYER met3 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.495 LAYER met3 ;
+ ANTENNAMAXAREACAR 17.2141 LAYER met3 ;
+ ANTENNAMAXSIDEAREACAR 85.703 LAYER met3 ;
+ ANTENNAMAXCUTCAR 0.184646 LAYER via3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 477.750000 2840.040000 478.050000 ;
+ END
+ END io_in[2]
+ PIN io_in[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 38.5144 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 205.872 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 9.6894 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 53.088 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.495 LAYER met4 ;
+ ANTENNAMAXAREACAR 23.5216 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 126.96 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.265455 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 244.120000 2840.040000 244.420000 ;
+ END
+ END io_in[1]
+ PIN io_in[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 0.5574 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 3.416 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNAPARTIALMETALAREA 3.9618 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 21.6 LAYER met4 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 0.495 LAYER met4 ;
+ ANTENNAMAXAREACAR 10.6469 LAYER met4 ;
+ ANTENNAMAXSIDEAREACAR 56.8283 LAYER met4 ;
+ ANTENNAMAXCUTCAR 0.265455 LAYER via4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 9.880000 2840.040000 10.180000 ;
+ END
+ END io_in[0]
+ PIN io_out[37]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 33.9316 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 180.96 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 928.937 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 4954.8 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 94.060000 0.800000 94.360000 ;
+ END
+ END io_out[37]
+ PIN io_out[36]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 10.1506 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 54.128 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 794.363 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 4237.07 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 344.770000 0.800000 345.070000 ;
+ END
+ END io_out[36]
+ PIN io_out[35]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 52.0092 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 277.592 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 595.480000 0.800000 595.780000 ;
+ END
+ END io_out[35]
+ PIN io_out[34]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 1.4806 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.888 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 584.826 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 3121.42 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 846.800000 0.800000 847.100000 ;
+ END
+ END io_out[34]
+ PIN io_out[33]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 43.3654 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 231.744 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 497.903 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 2655.95 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1097.510000 0.800000 1097.810000 ;
+ END
+ END io_out[33]
+ PIN io_out[32]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 36.1846 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 192.976 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 376.919 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 2010.7 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1348.220000 0.800000 1348.520000 ;
+ END
+ END io_out[32]
+ PIN io_out[31]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 51.9792 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 277.432 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1599.540000 0.800000 1599.840000 ;
+ END
+ END io_out[31]
+ PIN io_out[30]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 48.2532 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 257.56 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1850.250000 0.800000 1850.550000 ;
+ END
+ END io_out[30]
+ PIN io_out[29]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 20.7076 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 110.432 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 77.8938 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 415.904 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2101.570000 0.800000 2101.870000 ;
+ END
+ END io_out[29]
+ PIN io_out[28]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 2.0296 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 10.816 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 48.9798 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 261.696 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2352.280000 0.800000 2352.580000 ;
+ END
+ END io_out[28]
+ PIN io_out[27]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 3.3436 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 17.824 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 133.558 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 713.248 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2602.990000 0.800000 2603.290000 ;
+ END
+ END io_out[27]
+ PIN io_out[26]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 40.1656 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 214.208 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 258.881 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 1381.17 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2854.310000 0.800000 2854.610000 ;
+ END
+ END io_out[26]
+ PIN io_out[25]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 23.7886 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 126.864 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 344.653 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 1839.09 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 3105.020000 0.800000 3105.320000 ;
+ END
+ END io_out[25]
+ PIN io_out[24]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 22.7776 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 121.472 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 469.88 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 2506.5 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 3355.730000 0.800000 3356.030000 ;
+ END
+ END io_out[24]
+ PIN io_out[23]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 34.3868 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 171.773 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.4 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 2.6 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 65.1798 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 348.096 LAYER met4 ;
+ PORT
+ LAYER met2 ;
+ RECT 118.840000 3439.295000 118.980000 3439.780000 ;
+ END
+ END io_out[23]
+ PIN io_out[22]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 259.411 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1296.78 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 4.3338 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 23.328 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 445.440000 3439.295000 445.580000 3439.780000 ;
+ END
+ END io_out[22]
+ PIN io_out[21]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 246.339 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1231.3 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 8.2938 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 44.448 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 772.040000 3439.295000 772.180000 3439.780000 ;
+ END
+ END io_out[21]
+ PIN io_out[20]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 261.483 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1307.02 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 4.9878 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 26.816 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 1098.180000 3439.295000 1098.320000 3439.780000 ;
+ END
+ END io_out[20]
+ PIN io_out[19]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 215.28 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1076.01 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 8.8548 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 47.44 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 1424.780000 3439.295000 1424.920000 3439.780000 ;
+ END
+ END io_out[19]
+ PIN io_out[18]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 7.5906 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 37.674 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.26895 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.832 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 171.455 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 914.896 LAYER met4 ;
+ PORT
+ LAYER met2 ;
+ RECT 1751.380000 3439.295000 1751.520000 3439.780000 ;
+ END
+ END io_out[18]
+ PIN io_out[17]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 23.0438 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 114.94 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 0.883 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 5.176 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 131.513 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 701.872 LAYER met4 ;
+ PORT
+ LAYER met2 ;
+ RECT 2077.520000 3439.295000 2077.660000 3439.780000 ;
+ END
+ END io_out[17]
+ PIN io_out[16]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 267.663 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1337.92 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 2.1978 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 11.936 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 2404.120000 3439.295000 2404.260000 3439.780000 ;
+ END
+ END io_out[16]
+ PIN io_out[15]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 25.922 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 129.213 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 6.2028 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 33.296 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 2730.720000 3439.295000 2730.860000 3439.780000 ;
+ END
+ END io_out[15]
+ PIN io_out[14]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 15.9402 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 85.224 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 3361.830000 2840.040000 3362.130000 ;
+ END
+ END io_out[14]
+ PIN io_out[13]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 22.2912 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 119.096 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 3127.590000 2840.040000 3127.890000 ;
+ END
+ END io_out[13]
+ PIN io_out[12]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 33.1062 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 176.776 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2893.960000 2840.040000 2894.260000 ;
+ END
+ END io_out[12]
+ PIN io_out[11]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 2.6082 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 14.824 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 152.24 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 812.416 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2660.330000 2840.040000 2660.630000 ;
+ END
+ END io_out[11]
+ PIN io_out[10]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 4.9996 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 26.656 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 717.32 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 3826.18 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2426.090000 2840.040000 2426.390000 ;
+ END
+ END io_out[10]
+ PIN io_out[9]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 9.7542 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 52.232 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2192.460000 2840.040000 2192.760000 ;
+ END
+ END io_out[9]
+ PIN io_out[8]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 13.9302 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 74.504 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1958.830000 2840.040000 1959.130000 ;
+ END
+ END io_out[8]
+ PIN io_out[7]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 14.9854 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 80.384 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 16.2708 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 87.248 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1724.590000 2840.040000 1724.890000 ;
+ END
+ END io_out[7]
+ PIN io_out[6]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 4.1484 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 22.6 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1490.960000 2840.040000 1491.260000 ;
+ END
+ END io_out[6]
+ PIN io_out[5]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 10.6344 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 57.192 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1257.330000 2840.040000 1257.630000 ;
+ END
+ END io_out[5]
+ PIN io_out[4]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 3.5964 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 19.656 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1023.700000 2840.040000 1024.000000 ;
+ END
+ END io_out[4]
+ PIN io_out[3]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 4.4244 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 24.072 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 789.460000 2840.040000 789.760000 ;
+ END
+ END io_out[3]
+ PIN io_out[2]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 1.3884 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 7.88 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 555.830000 2840.040000 556.130000 ;
+ END
+ END io_out[2]
+ PIN io_out[1]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 4.9764 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 27.016 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 322.200000 2840.040000 322.500000 ;
+ END
+ END io_out[1]
+ PIN io_out[0]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 4.8384 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 26.28 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 87.960000 2840.040000 88.260000 ;
+ END
+ END io_out[0]
+ PIN io_oeb[37]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 35.3086 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 188.304 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 904.073 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 4822.19 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 177.630000 0.800000 177.930000 ;
+ END
+ END io_oeb[37]
+ PIN io_oeb[36]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 35.1496 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 187.456 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 780.128 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 4161.15 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 428.340000 0.800000 428.640000 ;
+ END
+ END io_oeb[36]
+ PIN io_oeb[35]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 49.1232 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 262.2 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 679.050000 0.800000 679.350000 ;
+ END
+ END io_oeb[35]
+ PIN io_oeb[34]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 0.2386 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.264 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 506.281 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 2701.1 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 930.370000 0.800000 930.670000 ;
+ END
+ END io_oeb[34]
+ PIN io_oeb[33]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 42.6286 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 227.344 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 473.174 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 2524.06 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1181.080000 0.800000 1181.380000 ;
+ END
+ END io_oeb[33]
+ PIN io_oeb[32]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 24.8476 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 132.512 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 346.769 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 1849.9 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1432.400000 0.800000 1432.700000 ;
+ END
+ END io_oeb[32]
+ PIN io_oeb[31]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 49.8822 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 266.248 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1683.110000 0.800000 1683.410000 ;
+ END
+ END io_oeb[31]
+ PIN io_oeb[30]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 48.7128 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 260.016 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 1933.820000 0.800000 1934.120000 ;
+ END
+ END io_oeb[30]
+ PIN io_oeb[29]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 2.9056 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 15.488 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 51.7488 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 276.464 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2185.140000 0.800000 2185.440000 ;
+ END
+ END io_oeb[29]
+ PIN io_oeb[28]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 33.3106 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 177.648 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 76.1358 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 406.528 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2435.850000 0.800000 2436.150000 ;
+ END
+ END io_oeb[28]
+ PIN io_oeb[27]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 49.4592 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 263.992 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2686.560000 0.800000 2686.860000 ;
+ END
+ END io_oeb[27]
+ PIN io_oeb[26]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 47.5534 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 254.08 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 1.7658 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 9.888 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 2937.880000 0.800000 2938.180000 ;
+ END
+ END io_oeb[26]
+ PIN io_oeb[25]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 39.1546 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 208.816 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 370.193 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 1974.83 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 3188.590000 0.800000 3188.890000 ;
+ END
+ END io_oeb[25]
+ PIN io_oeb[24]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 14.9386 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 79.664 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 496.964 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 2650.94 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000000 3439.300000 0.800000 3439.600000 ;
+ END
+ END io_oeb[24]
+ PIN io_oeb[23]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 235.697 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1178.32 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 45.9828 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 245.456 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 10.280000 3439.295000 10.420000 3439.780000 ;
+ END
+ END io_oeb[23]
+ PIN io_oeb[22]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 16.4902 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 82.054 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 2.8644 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 15.496 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 336.420000 3439.295000 336.560000 3439.780000 ;
+ END
+ END io_oeb[22]
+ PIN io_oeb[21]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 237.503 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1187.12 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 4.5468 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 24.464 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 663.020000 3439.295000 663.160000 3439.780000 ;
+ END
+ END io_oeb[21]
+ PIN io_oeb[20]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 12.1336 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 60.389 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 11.9142 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 64.232 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 989.620000 3439.295000 989.760000 3439.780000 ;
+ END
+ END io_oeb[20]
+ PIN io_oeb[19]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 292.103 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1460.23 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 4.0008 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 21.552 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 1315.760000 3439.295000 1315.900000 3439.780000 ;
+ END
+ END io_oeb[19]
+ PIN io_oeb[18]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 3.9424 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 19.551 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 72.4378 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 387.272 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 172.625 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 921.136 LAYER met4 ;
+ PORT
+ LAYER met2 ;
+ RECT 1642.360000 3439.295000 1642.500000 3439.780000 ;
+ END
+ END io_oeb[18]
+ PIN io_oeb[17]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 249.732 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 1248.26 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 6.6318 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 35.584 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 1968.960000 3439.295000 1969.100000 3439.780000 ;
+ END
+ END io_oeb[17]
+ PIN io_oeb[16]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 11.7444 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 58.443 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 5.161 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 27.992 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 62.1558 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 331.968 LAYER met4 ;
+ PORT
+ LAYER met2 ;
+ RECT 2295.560000 3439.295000 2295.700000 3439.780000 ;
+ END
+ END io_oeb[16]
+ PIN io_oeb[15]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 64.555 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 322.378 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 5.8578 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 31.456 LAYER met3 ;
+ PORT
+ LAYER met2 ;
+ RECT 2621.700000 3439.295000 2621.840000 3439.780000 ;
+ END
+ END io_oeb[15]
+ PIN io_oeb[14]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 15.8058 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 84.512 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 3439.300000 2840.040000 3439.600000 ;
+ END
+ END io_oeb[14]
+ PIN io_oeb[13]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 18.0642 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 96.552 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 3205.670000 2840.040000 3205.970000 ;
+ END
+ END io_oeb[13]
+ PIN io_oeb[12]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 36.4668 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 194.704 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2972.040000 2840.040000 2972.340000 ;
+ END
+ END io_oeb[12]
+ PIN io_oeb[11]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 37.1152 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 198.88 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 130.415 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 696.016 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2738.410000 2840.040000 2738.710000 ;
+ END
+ END io_oeb[11]
+ PIN io_oeb[10]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 0.2386 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.264 LAYER met3 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via3 ;
+ ANTENNADIFFAREA 1.782 LAYER met4 ;
+ ANTENNAPARTIALMETALAREA 806.314 LAYER met4 ;
+ ANTENNAPARTIALMETALSIDEAREA 4301.28 LAYER met4 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2504.170000 2840.040000 2504.470000 ;
+ END
+ END io_oeb[10]
+ PIN io_oeb[9]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 15.2982 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 81.8 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2270.540000 2840.040000 2270.840000 ;
+ END
+ END io_oeb[9]
+ PIN io_oeb[8]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 23.0868 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 123.344 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 2036.910000 2840.040000 2037.210000 ;
+ END
+ END io_oeb[8]
+ PIN io_oeb[7]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 22.4742 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 120.072 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1802.670000 2840.040000 1802.970000 ;
+ END
+ END io_oeb[7]
+ PIN io_oeb[6]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 0.2844 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 1.992 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1569.040000 2840.040000 1569.340000 ;
+ END
+ END io_oeb[6]
+ PIN io_oeb[5]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 11.7384 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 63.08 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1335.410000 2840.040000 1335.710000 ;
+ END
+ END io_oeb[5]
+ PIN io_oeb[4]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 8.0124 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 43.208 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 1101.170000 2840.040000 1101.470000 ;
+ END
+ END io_oeb[4]
+ PIN io_oeb[3]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 11.6004 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 62.344 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 867.540000 2840.040000 867.840000 ;
+ END
+ END io_oeb[3]
+ PIN io_oeb[2]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 7.4604 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 40.264 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 633.910000 2840.040000 634.210000 ;
+ END
+ END io_oeb[2]
+ PIN io_oeb[1]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 9.9444 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 53.512 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 399.670000 2840.040000 399.970000 ;
+ END
+ END io_oeb[1]
+ PIN io_oeb[0]
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ ANTENNADIFFAREA 1.782 LAYER met3 ;
+ ANTENNAPARTIALMETALAREA 4.0104 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 21.864 LAYER met3 ;
+ PORT
+ LAYER met3 ;
+ RECT 2839.240000 166.040000 2840.040000 166.340000 ;
+ END
+ END io_oeb[0]
+ PIN user_clock2
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ ANTENNAPARTIALMETALAREA 3.4636 LAYER met2 ;
+ ANTENNAPARTIALMETALSIDEAREA 17.157 LAYER met2 ;
+ ANTENNAPARTIALCUTAREA 0.04 LAYER via2 ;
+ ANTENNAPARTIALMETALAREA 18.8868 LAYER met3 ;
+ ANTENNAPARTIALMETALSIDEAREA 101.2 LAYER met3 ;
+ ANTENNAMODEL OXIDE1 ;
+ ANTENNAGATEAREA 4.608 LAYER met3 ;
+ ANTENNAMAXAREACAR 4.57194 LAYER met3 ;
+ ANTENNAMAXSIDEAREACAR 23.5418 LAYER met3 ;
+ ANTENNAMAXCUTCAR 0.0386502 LAYER via3 ;
+ PORT
+ LAYER met2 ;
+ RECT 2839.740000 0.000000 2839.880000 0.485000 ;
+ END
+ END user_clock2
+ PIN vssd1
+ DIRECTION INOUT ;
+ USE GROUND ;
+
+# P/G power stripe data as pin
+ PORT
+ LAYER met3 ;
+ RECT 2.000000 2.000000 2838.040000 5.000000 ;
+ RECT 156.120000 111.240000 2188.000000 112.240000 ;
+ RECT 156.120000 142.740000 640.860000 143.740000 ;
+ RECT 156.120000 142.740000 840.960000 143.740000 ;
+ RECT 156.120000 142.740000 1041.060000 143.740000 ;
+ RECT 156.120000 142.740000 1241.160000 143.740000 ;
+ RECT 156.120000 116.490000 1241.160000 117.490000 ;
+ RECT 156.120000 116.490000 640.860000 117.490000 ;
+ RECT 156.120000 116.490000 840.960000 117.490000 ;
+ RECT 156.120000 116.490000 1041.060000 117.490000 ;
+ RECT 156.120000 116.490000 440.760000 117.490000 ;
+ RECT 156.120000 142.740000 440.760000 143.740000 ;
+ RECT 156.120000 142.740000 240.660000 143.740000 ;
+ RECT 156.120000 146.750000 160.620000 147.750000 ;
+ RECT 238.970000 116.490000 240.660000 117.490000 ;
+ RECT 441.790000 116.630000 442.790000 117.630000 ;
+ RECT 441.790000 116.490000 442.790000 117.130000 ;
+ RECT 439.760000 116.490000 442.790000 117.490000 ;
+ RECT 441.790000 142.740000 442.790000 143.740000 ;
+ RECT 439.760000 142.740000 442.290000 143.740000 ;
+ RECT 156.120000 347.150000 162.150000 348.150000 ;
+ RECT 156.120000 342.050000 162.150000 343.050000 ;
+ RECT 156.120000 342.320000 160.620000 343.320000 ;
+ RECT 156.120000 347.010000 160.620000 348.010000 ;
+ RECT 161.650000 342.050000 162.650000 343.050000 ;
+ RECT 161.650000 347.150000 162.650000 348.150000 ;
+ RECT 239.160000 342.320000 239.660000 343.320000 ;
+ RECT 239.160000 347.010000 239.660000 348.010000 ;
+ RECT 156.120000 547.410000 162.150000 548.410000 ;
+ RECT 156.120000 542.310000 162.150000 543.310000 ;
+ RECT 156.120000 547.270000 160.620000 548.270000 ;
+ RECT 156.120000 542.580000 160.620000 543.580000 ;
+ RECT 161.650000 542.310000 162.650000 543.310000 ;
+ RECT 161.650000 547.410000 162.650000 548.410000 ;
+ RECT 239.160000 542.580000 239.660000 543.580000 ;
+ RECT 239.160000 547.270000 239.660000 548.270000 ;
+ RECT 156.120000 747.630000 162.150000 748.630000 ;
+ RECT 156.120000 742.750000 162.150000 743.750000 ;
+ RECT 156.120000 747.530000 160.620000 748.530000 ;
+ RECT 156.120000 742.840000 160.620000 743.840000 ;
+ RECT 161.650000 742.750000 162.650000 743.750000 ;
+ RECT 161.650000 747.630000 162.650000 748.630000 ;
+ RECT 239.160000 747.530000 239.660000 748.530000 ;
+ RECT 239.160000 742.840000 239.660000 743.840000 ;
+ RECT 641.890000 116.630000 642.890000 117.630000 ;
+ RECT 641.890000 116.490000 642.890000 117.130000 ;
+ RECT 639.860000 116.490000 642.890000 117.490000 ;
+ RECT 641.890000 142.740000 642.890000 143.740000 ;
+ RECT 639.860000 142.740000 642.390000 143.740000 ;
+ RECT 839.960000 116.490000 842.990000 117.490000 ;
+ RECT 841.990000 116.630000 842.990000 117.630000 ;
+ RECT 841.990000 116.490000 842.990000 117.130000 ;
+ RECT 841.990000 142.740000 842.990000 143.740000 ;
+ RECT 839.960000 142.740000 842.490000 143.740000 ;
+ RECT 1040.060000 142.740000 1042.590000 143.740000 ;
+ RECT 1042.090000 142.740000 1043.090000 143.740000 ;
+ RECT 1242.190000 116.630000 1243.190000 117.630000 ;
+ RECT 1242.190000 116.490000 1243.190000 117.130000 ;
+ RECT 1240.160000 116.490000 1243.190000 117.490000 ;
+ RECT 1242.190000 142.740000 1243.190000 143.740000 ;
+ RECT 1240.160000 142.740000 1242.690000 143.740000 ;
+ RECT 156.120000 947.930000 162.150000 948.930000 ;
+ RECT 156.120000 942.830000 162.150000 943.830000 ;
+ RECT 156.120000 947.790000 160.620000 948.790000 ;
+ RECT 156.120000 943.100000 160.620000 944.100000 ;
+ RECT 161.650000 942.830000 162.650000 943.830000 ;
+ RECT 161.650000 947.930000 162.650000 948.930000 ;
+ RECT 239.160000 943.100000 239.660000 944.100000 ;
+ RECT 239.160000 947.790000 239.660000 948.790000 ;
+ RECT 156.120000 1143.170000 238.430000 1143.650000 ;
+ RECT 156.120000 1148.190000 162.150000 1149.190000 ;
+ RECT 156.120000 1143.090000 162.150000 1144.090000 ;
+ RECT 156.120000 1148.050000 160.620000 1149.050000 ;
+ RECT 156.120000 1143.360000 160.620000 1144.360000 ;
+ RECT 161.650000 1143.090000 162.650000 1144.090000 ;
+ RECT 161.650000 1148.190000 162.650000 1149.190000 ;
+ RECT 239.160000 1148.050000 239.660000 1149.050000 ;
+ RECT 239.160000 1143.360000 239.660000 1144.360000 ;
+ RECT 238.190000 1143.160000 238.670000 1143.660000 ;
+ RECT 156.120000 1343.610000 238.430000 1344.090000 ;
+ RECT 156.120000 1343.620000 160.620000 1344.620000 ;
+ RECT 156.120000 1343.600000 162.150000 1344.600000 ;
+ RECT 161.650000 1343.600000 162.650000 1344.600000 ;
+ RECT 156.120000 1348.450000 162.150000 1349.450000 ;
+ RECT 156.120000 1348.310000 160.620000 1349.310000 ;
+ RECT 161.650000 1348.450000 162.650000 1349.450000 ;
+ RECT 239.160000 1343.620000 239.660000 1344.620000 ;
+ RECT 239.160000 1348.310000 239.660000 1349.310000 ;
+ RECT 238.190000 1343.600000 238.670000 1344.100000 ;
+ RECT 156.120000 1543.870000 238.430000 1544.350000 ;
+ RECT 156.120000 1548.710000 162.150000 1549.710000 ;
+ RECT 156.120000 1543.680000 162.150000 1544.680000 ;
+ RECT 156.120000 1548.570000 160.620000 1549.570000 ;
+ RECT 156.120000 1543.880000 160.620000 1544.880000 ;
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+ LAYER met4 ;
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+ RECT 161.350000 1743.870000 162.350000 1748.080000 ;
+ RECT 161.350000 1743.870000 162.150000 1744.870000 ;
+ RECT 161.350000 1748.970000 162.150000 1749.970000 ;
+ RECT 161.350000 1747.080000 162.350000 1749.970000 ;
+ RECT 238.190000 1740.100000 238.670000 1744.260000 ;
+ RECT 161.350000 1949.230000 162.150000 1950.230000 ;
+ RECT 161.350000 1947.340000 162.350000 1950.230000 ;
+ RECT 161.350000 1944.130000 162.150000 1945.130000 ;
+ RECT 161.350000 1944.130000 162.350000 1948.340000 ;
+ RECT 238.190000 1940.360000 238.670000 1944.630000 ;
+ RECT 161.350000 2144.530000 162.150000 2145.530000 ;
+ RECT 161.350000 2144.530000 162.350000 2148.600000 ;
+ RECT 238.190000 2140.620000 238.670000 2144.890000 ;
+ RECT 161.350000 2349.750000 162.150000 2350.750000 ;
+ RECT 161.350000 2347.860000 162.350000 2350.750000 ;
+ RECT 161.350000 2344.650000 162.150000 2345.650000 ;
+ RECT 161.350000 2344.650000 162.350000 2348.860000 ;
+ RECT 238.190000 2340.880000 238.670000 2345.110000 ;
+ RECT 161.350000 2550.010000 162.150000 2551.010000 ;
+ RECT 161.350000 2548.120000 162.350000 2551.010000 ;
+ RECT 161.350000 2544.910000 162.150000 2545.910000 ;
+ RECT 161.350000 2544.910000 162.350000 2549.120000 ;
+ RECT 238.190000 2541.140000 238.670000 2545.190000 ;
+ RECT 237.930000 2735.960000 238.930000 3437.780000 ;
+ RECT 237.930000 2936.220000 238.930000 3437.780000 ;
+ RECT 237.930000 2748.380000 238.930000 3437.780000 ;
+ RECT 237.930000 2948.640000 238.930000 3437.780000 ;
+ RECT 161.350000 2745.380000 162.150000 2746.380000 ;
+ RECT 161.350000 2750.260000 162.150000 2751.260000 ;
+ RECT 161.350000 2748.380000 162.350000 2751.260000 ;
+ RECT 161.350000 2745.380000 162.350000 2749.380000 ;
+ RECT 161.350000 2950.530000 162.150000 2951.530000 ;
+ RECT 161.350000 2948.640000 162.350000 2951.530000 ;
+ RECT 161.350000 2945.460000 162.150000 2946.460000 ;
+ RECT 161.350000 2945.460000 162.350000 2949.640000 ;
+ RECT 237.930000 3136.480000 238.930000 3437.780000 ;
+ RECT 237.930000 3148.900000 238.930000 3437.780000 ;
+ RECT 161.350000 3150.790000 162.150000 3151.790000 ;
+ RECT 161.350000 3148.900000 162.350000 3151.790000 ;
+ RECT 161.350000 3145.690000 162.150000 3146.690000 ;
+ RECT 161.350000 3145.690000 162.350000 3149.900000 ;
+ RECT 161.350000 3349.160000 162.350000 3350.530000 ;
+ RECT 237.930000 3349.160000 238.930000 3437.780000 ;
+ RECT 241.390000 3373.800000 242.390000 3437.780000 ;
+ RECT 241.390000 3379.420000 242.390000 3437.780000 ;
+ RECT 237.930000 3336.740000 238.930000 3437.780000 ;
+ RECT 241.390000 3345.950000 242.190000 3346.950000 ;
+ RECT 241.390000 3345.950000 242.390000 3350.160000 ;
+ RECT 441.790000 3377.660000 442.790000 3437.780000 ;
+ RECT 441.490000 3379.420000 442.490000 3437.780000 ;
+ RECT 441.490000 3373.800000 442.490000 3437.780000 ;
+ RECT 438.030000 3379.420000 439.030000 3437.780000 ;
+ RECT 441.490000 3350.160000 442.490000 3350.660000 ;
+ RECT 641.890000 3351.550000 642.890000 3437.780000 ;
+ RECT 641.890000 3377.660000 642.890000 3437.780000 ;
+ RECT 641.590000 3379.420000 642.590000 3437.780000 ;
+ RECT 638.130000 3379.420000 639.130000 3437.780000 ;
+ RECT 641.590000 3373.800000 642.590000 3437.780000 ;
+ RECT 641.590000 3350.160000 642.590000 3350.660000 ;
+ RECT 841.990000 3377.660000 842.990000 3437.780000 ;
+ RECT 838.230000 3379.420000 839.230000 3437.780000 ;
+ RECT 841.690000 3373.800000 842.690000 3437.780000 ;
+ RECT 841.690000 3379.420000 842.690000 3437.780000 ;
+ RECT 841.690000 3350.160000 842.690000 3350.660000 ;
+ RECT 1042.090000 3377.660000 1043.090000 3437.780000 ;
+ RECT 1041.790000 3379.420000 1042.790000 3437.780000 ;
+ RECT 1038.330000 3379.420000 1039.330000 3437.780000 ;
+ RECT 1041.790000 3373.800000 1042.790000 3437.780000 ;
+ RECT 1041.790000 3350.160000 1042.790000 3350.660000 ;
+ RECT 1242.190000 3377.660000 1243.190000 3437.780000 ;
+ RECT 1238.430000 3379.420000 1239.430000 3437.780000 ;
+ RECT 1241.890000 3379.420000 1242.890000 3437.780000 ;
+ RECT 1241.890000 3350.160000 1242.890000 3350.660000 ;
+ RECT 1438.530000 3379.420000 1439.530000 3437.780000 ;
+ RECT 1446.990000 3379.420000 1447.990000 3437.780000 ;
+ RECT 1438.530000 3373.800000 1439.530000 3437.780000 ;
+ RECT 1446.990000 3350.160000 1447.990000 3350.660000 ;
+ RECT 1649.290000 3351.410000 1650.290000 3437.780000 ;
+ RECT 1649.290000 3377.660000 1650.290000 3437.780000 ;
+ RECT 1643.630000 3379.420000 1644.630000 3437.780000 ;
+ RECT 1652.090000 3379.420000 1653.090000 3437.780000 ;
+ RECT 1643.630000 3373.800000 1644.630000 3437.780000 ;
+ RECT 1848.700000 3351.110000 1849.700000 3437.780000 ;
+ RECT 1848.730000 3379.420000 1849.730000 3437.780000 ;
+ RECT 1848.730000 3373.800000 1849.730000 3437.780000 ;
+ RECT 1848.470000 3351.110000 1849.700000 3352.110000 ;
+ RECT 1848.470000 3351.550000 1849.470000 3352.110000 ;
+ RECT 1848.730000 3350.160000 1849.730000 3350.660000 ;
+ RECT 1852.190000 3379.420000 1853.190000 3437.780000 ;
+ RECT 2048.800000 3351.110000 2049.800000 3437.780000 ;
+ RECT 2048.830000 3379.420000 2049.830000 3437.780000 ;
+ RECT 2052.290000 3379.420000 2053.290000 3437.780000 ;
+ RECT 2048.830000 3373.800000 2049.830000 3437.780000 ;
+ RECT 2048.570000 3351.110000 2049.800000 3352.110000 ;
+ RECT 2048.570000 3351.550000 2049.570000 3352.110000 ;
+ RECT 2048.830000 3350.160000 2049.830000 3350.660000 ;
+ RECT 2158.770000 3379.420000 2159.770000 3437.780000 ;
+ RECT 2158.770000 3373.800000 2159.770000 3437.780000 ;
+ RECT 2159.010000 3345.950000 2159.770000 3346.950000 ;
+ RECT 2158.770000 3345.950000 2159.770000 3350.160000 ;
+ RECT 2192.430000 3399.780000 2193.230000 3437.780000 ;
+ RECT 2718.690000 2977.070000 2719.490000 2980.340000 ;
+ RECT 2697.740000 3387.850000 2699.480000 3437.780000 ;
+ RECT 2718.690000 3390.320000 2719.490000 3437.780000 ;
+ RECT 2718.690000 3399.780000 2719.490000 3437.780000 ;
+ RECT 161.350000 153.080000 162.350000 153.560000 ;
+ RECT 241.390000 122.820000 242.390000 123.300000 ;
+ RECT 441.490000 122.820000 442.490000 123.300000 ;
+ RECT 441.490000 111.240000 442.790000 112.240000 ;
+ RECT 441.790000 142.740000 442.790000 143.740000 ;
+ RECT 161.650000 347.150000 162.650000 348.150000 ;
+ RECT 161.650000 342.050000 162.650000 343.050000 ;
+ RECT 161.650000 547.410000 162.650000 548.410000 ;
+ RECT 161.650000 542.310000 162.650000 543.310000 ;
+ RECT 161.650000 747.630000 162.650000 748.630000 ;
+ RECT 161.650000 742.750000 162.650000 743.750000 ;
+ RECT 641.590000 111.240000 642.890000 112.240000 ;
+ RECT 641.590000 122.820000 642.590000 123.300000 ;
+ RECT 641.890000 142.740000 642.890000 143.740000 ;
+ RECT 841.690000 111.240000 842.990000 112.240000 ;
+ RECT 841.690000 122.820000 842.690000 123.300000 ;
+ RECT 841.990000 142.740000 842.990000 143.740000 ;
+ RECT 1042.090000 142.740000 1043.090000 143.740000 ;
+ RECT 1041.790000 122.820000 1042.790000 123.300000 ;
+ RECT 1041.790000 111.240000 1043.090000 112.240000 ;
+ RECT 1241.890000 111.240000 1243.190000 112.240000 ;
+ RECT 1242.190000 142.740000 1243.190000 143.740000 ;
+ RECT 161.650000 942.830000 162.650000 943.830000 ;
+ RECT 161.650000 947.930000 162.650000 948.930000 ;
+ RECT 161.650000 1148.190000 162.650000 1149.190000 ;
+ RECT 161.650000 1143.090000 162.650000 1144.090000 ;
+ RECT 161.650000 1343.600000 162.650000 1344.600000 ;
+ RECT 161.650000 1348.450000 162.650000 1349.450000 ;
+ RECT 161.650000 1543.680000 162.650000 1544.680000 ;
+ RECT 161.650000 1548.710000 162.650000 1549.710000 ;
+ RECT 1444.360000 142.740000 1445.360000 143.740000 ;
+ RECT 1441.370000 142.740000 1442.370000 143.740000 ;
+ RECT 1649.290000 142.740000 1650.290000 143.740000 ;
+ RECT 1848.470000 142.740000 1849.470000 143.740000 ;
+ RECT 1848.470000 111.240000 1849.730000 112.240000 ;
+ RECT 1848.730000 122.820000 1849.730000 123.300000 ;
+ RECT 2048.570000 111.240000 2049.830000 112.240000 ;
+ RECT 2048.830000 122.820000 2049.830000 123.300000 ;
+ RECT 2048.570000 142.740000 2049.570000 143.740000 ;
+ RECT 2158.510000 146.890000 2159.510000 147.890000 ;
+ RECT 2718.690000 460.130000 2719.490000 460.930000 ;
+ RECT 161.650000 2149.410000 162.650000 2150.410000 ;
+ RECT 161.650000 1743.870000 162.650000 1744.870000 ;
+ RECT 161.650000 1748.970000 162.650000 1749.970000 ;
+ RECT 161.650000 1949.230000 162.650000 1950.230000 ;
+ RECT 161.650000 1944.130000 162.650000 1945.130000 ;
+ RECT 161.650000 2144.530000 162.650000 2145.530000 ;
+ RECT 161.650000 2349.750000 162.650000 2350.750000 ;
+ RECT 161.650000 2344.650000 162.650000 2345.650000 ;
+ RECT 161.650000 2550.010000 162.650000 2551.010000 ;
+ RECT 161.650000 2544.910000 162.650000 2545.910000 ;
+ RECT 161.650000 2750.260000 162.650000 2751.260000 ;
+ RECT 161.650000 2745.380000 162.650000 2746.380000 ;
+ RECT 161.650000 2950.530000 162.650000 2951.530000 ;
+ RECT 161.650000 2945.460000 162.650000 2946.460000 ;
+ RECT 161.650000 3150.790000 162.650000 3151.790000 ;
+ RECT 161.650000 3145.690000 162.650000 3146.690000 ;
+ RECT 161.350000 3350.030000 162.350000 3351.030000 ;
+ RECT 241.390000 3373.560000 242.390000 3374.040000 ;
+ RECT 241.690000 3345.950000 242.690000 3346.950000 ;
+ RECT 441.490000 3373.560000 442.490000 3374.040000 ;
+ RECT 441.790000 3377.160000 442.790000 3378.160000 ;
+ RECT 441.490000 3396.020000 442.790000 3396.500000 ;
+ RECT 441.490000 3390.580000 442.790000 3391.060000 ;
+ RECT 441.490000 3401.460000 442.790000 3401.940000 ;
+ RECT 441.490000 3406.900000 442.790000 3407.380000 ;
+ RECT 441.490000 3412.340000 442.790000 3412.820000 ;
+ RECT 441.490000 3423.220000 442.790000 3423.700000 ;
+ RECT 441.490000 3417.780000 442.790000 3418.260000 ;
+ RECT 441.490000 3428.660000 442.790000 3429.140000 ;
+ RECT 441.490000 3434.780000 442.790000 3437.780000 ;
+ RECT 641.590000 3373.560000 642.590000 3374.040000 ;
+ RECT 641.890000 3351.050000 642.890000 3352.050000 ;
+ RECT 641.590000 3390.580000 642.890000 3391.060000 ;
+ RECT 641.590000 3396.020000 642.890000 3396.500000 ;
+ RECT 641.590000 3401.460000 642.890000 3401.940000 ;
+ RECT 641.590000 3406.900000 642.890000 3407.380000 ;
+ RECT 641.590000 3412.340000 642.890000 3412.820000 ;
+ RECT 641.590000 3428.660000 642.890000 3429.140000 ;
+ RECT 641.590000 3423.220000 642.890000 3423.700000 ;
+ RECT 641.590000 3434.780000 642.890000 3437.780000 ;
+ RECT 641.590000 3417.780000 642.890000 3418.260000 ;
+ RECT 841.690000 3373.560000 842.690000 3374.040000 ;
+ RECT 841.990000 3377.160000 842.990000 3378.160000 ;
+ RECT 841.690000 3396.020000 842.990000 3396.500000 ;
+ RECT 841.690000 3390.580000 842.990000 3391.060000 ;
+ RECT 841.690000 3412.340000 842.990000 3412.820000 ;
+ RECT 841.690000 3406.900000 842.990000 3407.380000 ;
+ RECT 841.690000 3401.460000 842.990000 3401.940000 ;
+ RECT 841.690000 3423.220000 842.990000 3423.700000 ;
+ RECT 841.690000 3417.780000 842.990000 3418.260000 ;
+ RECT 841.690000 3428.660000 842.990000 3429.140000 ;
+ RECT 841.690000 3434.780000 842.990000 3437.780000 ;
+ RECT 1041.790000 3373.560000 1042.790000 3374.040000 ;
+ RECT 1042.090000 3377.160000 1043.090000 3378.160000 ;
+ RECT 1041.790000 3396.020000 1043.090000 3396.500000 ;
+ RECT 1041.790000 3390.580000 1043.090000 3391.060000 ;
+ RECT 1041.790000 3412.340000 1043.090000 3412.820000 ;
+ RECT 1041.790000 3406.900000 1043.090000 3407.380000 ;
+ RECT 1041.790000 3401.460000 1043.090000 3401.940000 ;
+ RECT 1041.790000 3423.220000 1043.090000 3423.700000 ;
+ RECT 1041.790000 3417.780000 1043.090000 3418.260000 ;
+ RECT 1041.790000 3434.780000 1043.090000 3437.780000 ;
+ RECT 1041.790000 3428.660000 1043.090000 3429.140000 ;
+ RECT 1242.190000 3377.160000 1243.190000 3378.160000 ;
+ RECT 1241.890000 3396.020000 1243.190000 3396.500000 ;
+ RECT 1241.890000 3390.580000 1243.190000 3391.060000 ;
+ RECT 1241.890000 3401.460000 1243.190000 3401.940000 ;
+ RECT 1241.890000 3406.900000 1243.190000 3407.380000 ;
+ RECT 1241.890000 3412.340000 1243.190000 3412.820000 ;
+ RECT 1241.890000 3423.220000 1243.190000 3423.700000 ;
+ RECT 1241.890000 3417.780000 1243.190000 3418.260000 ;
+ RECT 1241.890000 3428.660000 1243.190000 3429.140000 ;
+ RECT 1241.890000 3434.780000 1243.190000 3437.780000 ;
+ RECT 1438.530000 3373.560000 1439.530000 3374.040000 ;
+ RECT 1649.290000 3350.910000 1650.290000 3351.910000 ;
+ RECT 1643.630000 3373.560000 1644.630000 3374.040000 ;
+ RECT 1848.730000 3373.560000 1849.730000 3374.040000 ;
+ RECT 1848.470000 3351.050000 1849.470000 3352.050000 ;
+ RECT 1848.700000 3390.580000 1849.730000 3391.060000 ;
+ RECT 1848.700000 3396.020000 1849.730000 3396.500000 ;
+ RECT 1848.700000 3401.460000 1849.730000 3401.940000 ;
+ RECT 1848.700000 3406.900000 1849.730000 3407.380000 ;
+ RECT 1848.700000 3412.340000 1849.730000 3412.820000 ;
+ RECT 1848.700000 3428.660000 1849.730000 3429.140000 ;
+ RECT 1848.700000 3423.220000 1849.730000 3423.700000 ;
+ RECT 1848.700000 3417.780000 1849.730000 3418.260000 ;
+ RECT 1848.700000 3434.780000 1849.730000 3437.780000 ;
+ RECT 2048.570000 3351.050000 2049.570000 3352.050000 ;
+ RECT 2048.830000 3373.560000 2049.830000 3374.040000 ;
+ RECT 2048.800000 3396.020000 2049.830000 3396.500000 ;
+ RECT 2048.800000 3390.580000 2049.830000 3391.060000 ;
+ RECT 2048.800000 3412.340000 2049.830000 3412.820000 ;
+ RECT 2048.800000 3401.460000 2049.830000 3401.940000 ;
+ RECT 2048.800000 3406.900000 2049.830000 3407.380000 ;
+ RECT 2048.800000 3423.220000 2049.830000 3423.700000 ;
+ RECT 2048.800000 3417.780000 2049.830000 3418.260000 ;
+ RECT 2048.800000 3428.660000 2049.830000 3429.140000 ;
+ RECT 2048.800000 3434.780000 2049.830000 3437.780000 ;
+ RECT 2158.770000 3373.560000 2159.770000 3374.040000 ;
+ RECT 2158.510000 3345.950000 2159.510000 3346.950000 ;
+ RECT 2718.690000 2976.670000 2719.490000 2977.470000 ;
+ RECT 2718.690000 3390.080000 2719.490000 3390.560000 ;
+ END
+# end of P/G power stripe data as pin
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2222.420000 52.260000 2224.160000 447.040000 ;
+ LAYER met3 ;
+ RECT 2222.420000 445.300000 2699.480000 447.040000 ;
+ LAYER met3 ;
+ RECT 2222.420000 52.260000 2699.480000 54.000000 ;
+ LAYER met4 ;
+ RECT 2697.740000 52.260000 2699.480000 447.040000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 38.260000 2193.230000 458.500000 ;
+ RECT 2718.690000 38.260000 2719.490000 458.500000 ;
+ LAYER met3 ;
+ RECT 2718.690000 448.400000 2719.490000 448.880000 ;
+ RECT 2718.690000 442.960000 2719.490000 443.440000 ;
+ RECT 2718.690000 437.520000 2719.490000 438.000000 ;
+ RECT 2718.690000 432.080000 2719.490000 432.560000 ;
+ RECT 2718.690000 426.640000 2719.490000 427.120000 ;
+ RECT 2718.690000 421.200000 2719.490000 421.680000 ;
+ RECT 2718.690000 415.760000 2719.490000 416.240000 ;
+ RECT 2718.690000 410.320000 2719.490000 410.800000 ;
+ RECT 2718.690000 404.880000 2719.490000 405.360000 ;
+ RECT 2718.690000 399.440000 2719.490000 399.920000 ;
+ RECT 2718.690000 394.000000 2719.490000 394.480000 ;
+ RECT 2718.690000 388.560000 2719.490000 389.040000 ;
+ RECT 2718.690000 383.120000 2719.490000 383.600000 ;
+ RECT 2718.690000 366.800000 2719.490000 367.280000 ;
+ RECT 2718.690000 372.240000 2719.490000 372.720000 ;
+ RECT 2718.690000 377.680000 2719.490000 378.160000 ;
+ RECT 2718.690000 361.360000 2719.490000 361.840000 ;
+ RECT 2718.690000 355.920000 2719.490000 356.400000 ;
+ RECT 2718.690000 350.480000 2719.490000 350.960000 ;
+ RECT 2718.690000 345.040000 2719.490000 345.520000 ;
+ RECT 2718.690000 339.600000 2719.490000 340.080000 ;
+ RECT 2718.690000 334.160000 2719.490000 334.640000 ;
+ RECT 2718.690000 328.720000 2719.490000 329.200000 ;
+ RECT 2718.690000 323.280000 2719.490000 323.760000 ;
+ RECT 2718.690000 317.840000 2719.490000 318.320000 ;
+ RECT 2718.690000 312.400000 2719.490000 312.880000 ;
+ RECT 2718.690000 306.960000 2719.490000 307.440000 ;
+ RECT 2718.690000 301.520000 2719.490000 302.000000 ;
+ RECT 2718.690000 296.080000 2719.490000 296.560000 ;
+ RECT 2718.690000 290.640000 2719.490000 291.120000 ;
+ RECT 2718.690000 285.200000 2719.490000 285.680000 ;
+ RECT 2718.690000 279.760000 2719.490000 280.240000 ;
+ RECT 2718.690000 274.320000 2719.490000 274.800000 ;
+ RECT 2718.690000 268.880000 2719.490000 269.360000 ;
+ RECT 2718.690000 263.440000 2719.490000 263.920000 ;
+ RECT 2718.690000 258.000000 2719.490000 258.480000 ;
+ RECT 2718.690000 252.560000 2719.490000 253.040000 ;
+ RECT 2192.430000 448.400000 2193.230000 448.880000 ;
+ RECT 2192.430000 442.960000 2193.230000 443.440000 ;
+ RECT 2192.430000 437.520000 2193.230000 438.000000 ;
+ RECT 2192.430000 432.080000 2193.230000 432.560000 ;
+ RECT 2192.430000 426.640000 2193.230000 427.120000 ;
+ RECT 2192.430000 421.200000 2193.230000 421.680000 ;
+ RECT 2192.430000 415.760000 2193.230000 416.240000 ;
+ RECT 2192.430000 410.320000 2193.230000 410.800000 ;
+ RECT 2192.430000 404.880000 2193.230000 405.360000 ;
+ RECT 2192.430000 399.440000 2193.230000 399.920000 ;
+ RECT 2192.430000 394.000000 2193.230000 394.480000 ;
+ RECT 2192.430000 388.560000 2193.230000 389.040000 ;
+ RECT 2192.430000 383.120000 2193.230000 383.600000 ;
+ RECT 2192.430000 366.800000 2193.230000 367.280000 ;
+ RECT 2192.430000 372.240000 2193.230000 372.720000 ;
+ RECT 2192.430000 377.680000 2193.230000 378.160000 ;
+ RECT 2192.430000 361.360000 2193.230000 361.840000 ;
+ RECT 2192.430000 355.920000 2193.230000 356.400000 ;
+ RECT 2192.430000 350.480000 2193.230000 350.960000 ;
+ RECT 2192.430000 345.040000 2193.230000 345.520000 ;
+ RECT 2192.430000 339.600000 2193.230000 340.080000 ;
+ RECT 2192.430000 334.160000 2193.230000 334.640000 ;
+ RECT 2192.430000 328.720000 2193.230000 329.200000 ;
+ RECT 2192.430000 323.280000 2193.230000 323.760000 ;
+ RECT 2192.430000 317.840000 2193.230000 318.320000 ;
+ RECT 2192.430000 312.400000 2193.230000 312.880000 ;
+ RECT 2192.430000 306.960000 2193.230000 307.440000 ;
+ RECT 2192.430000 301.520000 2193.230000 302.000000 ;
+ RECT 2192.430000 296.080000 2193.230000 296.560000 ;
+ RECT 2192.430000 290.640000 2193.230000 291.120000 ;
+ RECT 2192.430000 285.200000 2193.230000 285.680000 ;
+ RECT 2192.430000 279.760000 2193.230000 280.240000 ;
+ RECT 2192.430000 274.320000 2193.230000 274.800000 ;
+ RECT 2192.430000 268.880000 2193.230000 269.360000 ;
+ RECT 2192.430000 263.440000 2193.230000 263.920000 ;
+ RECT 2192.430000 258.000000 2193.230000 258.480000 ;
+ RECT 2192.430000 252.560000 2193.230000 253.040000 ;
+ RECT 2718.690000 247.120000 2719.490000 247.600000 ;
+ RECT 2718.690000 241.680000 2719.490000 242.160000 ;
+ RECT 2718.690000 236.240000 2719.490000 236.720000 ;
+ RECT 2718.690000 230.800000 2719.490000 231.280000 ;
+ RECT 2718.690000 225.360000 2719.490000 225.840000 ;
+ RECT 2718.690000 219.920000 2719.490000 220.400000 ;
+ RECT 2718.690000 214.480000 2719.490000 214.960000 ;
+ RECT 2718.690000 209.040000 2719.490000 209.520000 ;
+ RECT 2718.690000 203.600000 2719.490000 204.080000 ;
+ RECT 2718.690000 198.160000 2719.490000 198.640000 ;
+ RECT 2718.690000 192.720000 2719.490000 193.200000 ;
+ RECT 2718.690000 187.280000 2719.490000 187.760000 ;
+ RECT 2718.690000 170.960000 2719.490000 171.440000 ;
+ RECT 2718.690000 176.400000 2719.490000 176.880000 ;
+ RECT 2718.690000 160.080000 2719.490000 160.560000 ;
+ RECT 2718.690000 154.640000 2719.490000 155.120000 ;
+ RECT 2718.690000 149.200000 2719.490000 149.680000 ;
+ RECT 2718.690000 165.520000 2719.490000 166.000000 ;
+ RECT 2718.690000 143.760000 2719.490000 144.240000 ;
+ RECT 2718.690000 138.320000 2719.490000 138.800000 ;
+ RECT 2718.690000 132.880000 2719.490000 133.360000 ;
+ RECT 2718.690000 127.440000 2719.490000 127.920000 ;
+ RECT 2718.690000 122.000000 2719.490000 122.480000 ;
+ RECT 2718.690000 116.560000 2719.490000 117.040000 ;
+ RECT 2718.690000 181.840000 2719.490000 182.320000 ;
+ RECT 2718.690000 111.120000 2719.490000 111.600000 ;
+ RECT 2718.690000 105.680000 2719.490000 106.160000 ;
+ RECT 2718.690000 100.240000 2719.490000 100.720000 ;
+ RECT 2718.690000 94.800000 2719.490000 95.280000 ;
+ RECT 2718.690000 89.360000 2719.490000 89.840000 ;
+ RECT 2718.690000 83.920000 2719.490000 84.400000 ;
+ RECT 2718.690000 78.480000 2719.490000 78.960000 ;
+ RECT 2718.690000 73.040000 2719.490000 73.520000 ;
+ RECT 2718.690000 67.600000 2719.490000 68.080000 ;
+ RECT 2718.690000 62.160000 2719.490000 62.640000 ;
+ RECT 2718.690000 56.720000 2719.490000 57.200000 ;
+ RECT 2718.690000 51.280000 2719.490000 51.760000 ;
+ RECT 2718.690000 45.840000 2719.490000 46.320000 ;
+ RECT 2192.430000 241.680000 2193.230000 242.160000 ;
+ RECT 2192.430000 236.240000 2193.230000 236.720000 ;
+ RECT 2192.430000 247.120000 2193.230000 247.600000 ;
+ RECT 2192.430000 230.800000 2193.230000 231.280000 ;
+ RECT 2192.430000 225.360000 2193.230000 225.840000 ;
+ RECT 2192.430000 219.920000 2193.230000 220.400000 ;
+ RECT 2192.430000 214.480000 2193.230000 214.960000 ;
+ RECT 2192.430000 209.040000 2193.230000 209.520000 ;
+ RECT 2192.430000 203.600000 2193.230000 204.080000 ;
+ RECT 2192.430000 198.160000 2193.230000 198.640000 ;
+ RECT 2192.430000 192.720000 2193.230000 193.200000 ;
+ RECT 2192.430000 187.280000 2193.230000 187.760000 ;
+ RECT 2192.430000 170.960000 2193.230000 171.440000 ;
+ RECT 2192.430000 176.400000 2193.230000 176.880000 ;
+ RECT 2192.430000 160.080000 2193.230000 160.560000 ;
+ RECT 2192.430000 154.640000 2193.230000 155.120000 ;
+ RECT 2192.430000 149.200000 2193.230000 149.680000 ;
+ RECT 2192.430000 165.520000 2193.230000 166.000000 ;
+ RECT 2192.430000 138.320000 2193.230000 138.800000 ;
+ RECT 2192.430000 132.880000 2193.230000 133.360000 ;
+ RECT 2192.430000 143.760000 2193.230000 144.240000 ;
+ RECT 2192.430000 127.440000 2193.230000 127.920000 ;
+ RECT 2192.430000 122.000000 2193.230000 122.480000 ;
+ RECT 2192.430000 116.560000 2193.230000 117.040000 ;
+ RECT 2192.430000 181.840000 2193.230000 182.320000 ;
+ RECT 2192.430000 111.120000 2193.230000 111.600000 ;
+ RECT 2192.430000 105.680000 2193.230000 106.160000 ;
+ RECT 2192.430000 100.240000 2193.230000 100.720000 ;
+ RECT 2192.430000 83.920000 2193.230000 84.400000 ;
+ RECT 2192.430000 94.800000 2193.230000 95.280000 ;
+ RECT 2192.430000 89.360000 2193.230000 89.840000 ;
+ RECT 2192.430000 78.480000 2193.230000 78.960000 ;
+ RECT 2192.430000 73.040000 2193.230000 73.520000 ;
+ RECT 2192.430000 67.600000 2193.230000 68.080000 ;
+ RECT 2192.430000 62.160000 2193.230000 62.640000 ;
+ RECT 2192.430000 56.720000 2193.230000 57.200000 ;
+ RECT 2192.430000 51.280000 2193.230000 51.760000 ;
+ RECT 2192.430000 45.840000 2193.230000 46.320000 ;
+ RECT 2192.430000 455.230000 2720.920000 456.030000 ;
+ RECT 2192.430000 39.710000 2720.920000 40.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 38.260000 2193.230000 39.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 457.700000 2193.230000 458.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 38.260000 2719.490000 39.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 457.700000 2719.490000 458.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 39.710000 2720.920000 40.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 455.230000 2720.920000 456.030000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2222.420000 472.500000 2224.160000 867.280000 ;
+ LAYER met3 ;
+ RECT 2222.420000 865.540000 2699.480000 867.280000 ;
+ LAYER met3 ;
+ RECT 2222.420000 472.500000 2699.480000 474.240000 ;
+ LAYER met4 ;
+ RECT 2697.740000 472.500000 2699.480000 867.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 458.500000 2193.230000 878.740000 ;
+ RECT 2718.690000 458.500000 2719.490000 878.740000 ;
+ LAYER met3 ;
+ RECT 2718.690000 868.640000 2719.490000 869.120000 ;
+ RECT 2718.690000 863.200000 2719.490000 863.680000 ;
+ RECT 2718.690000 857.760000 2719.490000 858.240000 ;
+ RECT 2718.690000 852.320000 2719.490000 852.800000 ;
+ RECT 2718.690000 846.880000 2719.490000 847.360000 ;
+ RECT 2718.690000 841.440000 2719.490000 841.920000 ;
+ RECT 2718.690000 836.000000 2719.490000 836.480000 ;
+ RECT 2718.690000 830.560000 2719.490000 831.040000 ;
+ RECT 2718.690000 825.120000 2719.490000 825.600000 ;
+ RECT 2718.690000 819.680000 2719.490000 820.160000 ;
+ RECT 2718.690000 814.240000 2719.490000 814.720000 ;
+ RECT 2718.690000 808.800000 2719.490000 809.280000 ;
+ RECT 2718.690000 803.360000 2719.490000 803.840000 ;
+ RECT 2718.690000 787.040000 2719.490000 787.520000 ;
+ RECT 2718.690000 792.480000 2719.490000 792.960000 ;
+ RECT 2718.690000 797.920000 2719.490000 798.400000 ;
+ RECT 2718.690000 781.600000 2719.490000 782.080000 ;
+ RECT 2718.690000 776.160000 2719.490000 776.640000 ;
+ RECT 2718.690000 770.720000 2719.490000 771.200000 ;
+ RECT 2718.690000 765.280000 2719.490000 765.760000 ;
+ RECT 2718.690000 759.840000 2719.490000 760.320000 ;
+ RECT 2718.690000 754.400000 2719.490000 754.880000 ;
+ RECT 2718.690000 748.960000 2719.490000 749.440000 ;
+ RECT 2718.690000 743.520000 2719.490000 744.000000 ;
+ RECT 2718.690000 738.080000 2719.490000 738.560000 ;
+ RECT 2718.690000 732.640000 2719.490000 733.120000 ;
+ RECT 2718.690000 727.200000 2719.490000 727.680000 ;
+ RECT 2718.690000 721.760000 2719.490000 722.240000 ;
+ RECT 2718.690000 716.320000 2719.490000 716.800000 ;
+ RECT 2718.690000 710.880000 2719.490000 711.360000 ;
+ RECT 2718.690000 705.440000 2719.490000 705.920000 ;
+ RECT 2718.690000 700.000000 2719.490000 700.480000 ;
+ RECT 2718.690000 694.560000 2719.490000 695.040000 ;
+ RECT 2718.690000 689.120000 2719.490000 689.600000 ;
+ RECT 2718.690000 683.680000 2719.490000 684.160000 ;
+ RECT 2718.690000 678.240000 2719.490000 678.720000 ;
+ RECT 2718.690000 672.800000 2719.490000 673.280000 ;
+ RECT 2192.430000 868.640000 2193.230000 869.120000 ;
+ RECT 2192.430000 863.200000 2193.230000 863.680000 ;
+ RECT 2192.430000 857.760000 2193.230000 858.240000 ;
+ RECT 2192.430000 852.320000 2193.230000 852.800000 ;
+ RECT 2192.430000 846.880000 2193.230000 847.360000 ;
+ RECT 2192.430000 841.440000 2193.230000 841.920000 ;
+ RECT 2192.430000 836.000000 2193.230000 836.480000 ;
+ RECT 2192.430000 830.560000 2193.230000 831.040000 ;
+ RECT 2192.430000 825.120000 2193.230000 825.600000 ;
+ RECT 2192.430000 819.680000 2193.230000 820.160000 ;
+ RECT 2192.430000 814.240000 2193.230000 814.720000 ;
+ RECT 2192.430000 808.800000 2193.230000 809.280000 ;
+ RECT 2192.430000 803.360000 2193.230000 803.840000 ;
+ RECT 2192.430000 787.040000 2193.230000 787.520000 ;
+ RECT 2192.430000 792.480000 2193.230000 792.960000 ;
+ RECT 2192.430000 797.920000 2193.230000 798.400000 ;
+ RECT 2192.430000 781.600000 2193.230000 782.080000 ;
+ RECT 2192.430000 776.160000 2193.230000 776.640000 ;
+ RECT 2192.430000 770.720000 2193.230000 771.200000 ;
+ RECT 2192.430000 765.280000 2193.230000 765.760000 ;
+ RECT 2192.430000 759.840000 2193.230000 760.320000 ;
+ RECT 2192.430000 754.400000 2193.230000 754.880000 ;
+ RECT 2192.430000 748.960000 2193.230000 749.440000 ;
+ RECT 2192.430000 743.520000 2193.230000 744.000000 ;
+ RECT 2192.430000 738.080000 2193.230000 738.560000 ;
+ RECT 2192.430000 732.640000 2193.230000 733.120000 ;
+ RECT 2192.430000 727.200000 2193.230000 727.680000 ;
+ RECT 2192.430000 721.760000 2193.230000 722.240000 ;
+ RECT 2192.430000 716.320000 2193.230000 716.800000 ;
+ RECT 2192.430000 710.880000 2193.230000 711.360000 ;
+ RECT 2192.430000 705.440000 2193.230000 705.920000 ;
+ RECT 2192.430000 700.000000 2193.230000 700.480000 ;
+ RECT 2192.430000 694.560000 2193.230000 695.040000 ;
+ RECT 2192.430000 689.120000 2193.230000 689.600000 ;
+ RECT 2192.430000 683.680000 2193.230000 684.160000 ;
+ RECT 2192.430000 678.240000 2193.230000 678.720000 ;
+ RECT 2192.430000 672.800000 2193.230000 673.280000 ;
+ RECT 2718.690000 667.360000 2719.490000 667.840000 ;
+ RECT 2718.690000 661.920000 2719.490000 662.400000 ;
+ RECT 2718.690000 656.480000 2719.490000 656.960000 ;
+ RECT 2718.690000 651.040000 2719.490000 651.520000 ;
+ RECT 2718.690000 645.600000 2719.490000 646.080000 ;
+ RECT 2718.690000 640.160000 2719.490000 640.640000 ;
+ RECT 2718.690000 634.720000 2719.490000 635.200000 ;
+ RECT 2718.690000 629.280000 2719.490000 629.760000 ;
+ RECT 2718.690000 623.840000 2719.490000 624.320000 ;
+ RECT 2718.690000 618.400000 2719.490000 618.880000 ;
+ RECT 2718.690000 612.960000 2719.490000 613.440000 ;
+ RECT 2718.690000 607.520000 2719.490000 608.000000 ;
+ RECT 2718.690000 591.200000 2719.490000 591.680000 ;
+ RECT 2718.690000 596.640000 2719.490000 597.120000 ;
+ RECT 2718.690000 580.320000 2719.490000 580.800000 ;
+ RECT 2718.690000 574.880000 2719.490000 575.360000 ;
+ RECT 2718.690000 569.440000 2719.490000 569.920000 ;
+ RECT 2718.690000 585.760000 2719.490000 586.240000 ;
+ RECT 2718.690000 564.000000 2719.490000 564.480000 ;
+ RECT 2718.690000 558.560000 2719.490000 559.040000 ;
+ RECT 2718.690000 553.120000 2719.490000 553.600000 ;
+ RECT 2718.690000 547.680000 2719.490000 548.160000 ;
+ RECT 2718.690000 542.240000 2719.490000 542.720000 ;
+ RECT 2718.690000 536.800000 2719.490000 537.280000 ;
+ RECT 2718.690000 602.080000 2719.490000 602.560000 ;
+ RECT 2718.690000 531.360000 2719.490000 531.840000 ;
+ RECT 2718.690000 525.920000 2719.490000 526.400000 ;
+ RECT 2718.690000 520.480000 2719.490000 520.960000 ;
+ RECT 2718.690000 515.040000 2719.490000 515.520000 ;
+ RECT 2718.690000 509.600000 2719.490000 510.080000 ;
+ RECT 2718.690000 504.160000 2719.490000 504.640000 ;
+ RECT 2718.690000 498.720000 2719.490000 499.200000 ;
+ RECT 2718.690000 493.280000 2719.490000 493.760000 ;
+ RECT 2718.690000 487.840000 2719.490000 488.320000 ;
+ RECT 2718.690000 482.400000 2719.490000 482.880000 ;
+ RECT 2718.690000 476.960000 2719.490000 477.440000 ;
+ RECT 2718.690000 471.520000 2719.490000 472.000000 ;
+ RECT 2718.690000 466.080000 2719.490000 466.560000 ;
+ RECT 2192.430000 661.920000 2193.230000 662.400000 ;
+ RECT 2192.430000 656.480000 2193.230000 656.960000 ;
+ RECT 2192.430000 667.360000 2193.230000 667.840000 ;
+ RECT 2192.430000 651.040000 2193.230000 651.520000 ;
+ RECT 2192.430000 645.600000 2193.230000 646.080000 ;
+ RECT 2192.430000 640.160000 2193.230000 640.640000 ;
+ RECT 2192.430000 634.720000 2193.230000 635.200000 ;
+ RECT 2192.430000 629.280000 2193.230000 629.760000 ;
+ RECT 2192.430000 623.840000 2193.230000 624.320000 ;
+ RECT 2192.430000 618.400000 2193.230000 618.880000 ;
+ RECT 2192.430000 612.960000 2193.230000 613.440000 ;
+ RECT 2192.430000 607.520000 2193.230000 608.000000 ;
+ RECT 2192.430000 591.200000 2193.230000 591.680000 ;
+ RECT 2192.430000 596.640000 2193.230000 597.120000 ;
+ RECT 2192.430000 580.320000 2193.230000 580.800000 ;
+ RECT 2192.430000 574.880000 2193.230000 575.360000 ;
+ RECT 2192.430000 569.440000 2193.230000 569.920000 ;
+ RECT 2192.430000 585.760000 2193.230000 586.240000 ;
+ RECT 2192.430000 558.560000 2193.230000 559.040000 ;
+ RECT 2192.430000 553.120000 2193.230000 553.600000 ;
+ RECT 2192.430000 564.000000 2193.230000 564.480000 ;
+ RECT 2192.430000 547.680000 2193.230000 548.160000 ;
+ RECT 2192.430000 542.240000 2193.230000 542.720000 ;
+ RECT 2192.430000 536.800000 2193.230000 537.280000 ;
+ RECT 2192.430000 602.080000 2193.230000 602.560000 ;
+ RECT 2192.430000 531.360000 2193.230000 531.840000 ;
+ RECT 2192.430000 525.920000 2193.230000 526.400000 ;
+ RECT 2192.430000 520.480000 2193.230000 520.960000 ;
+ RECT 2192.430000 504.160000 2193.230000 504.640000 ;
+ RECT 2192.430000 515.040000 2193.230000 515.520000 ;
+ RECT 2192.430000 509.600000 2193.230000 510.080000 ;
+ RECT 2192.430000 498.720000 2193.230000 499.200000 ;
+ RECT 2192.430000 493.280000 2193.230000 493.760000 ;
+ RECT 2192.430000 487.840000 2193.230000 488.320000 ;
+ RECT 2192.430000 482.400000 2193.230000 482.880000 ;
+ RECT 2192.430000 476.960000 2193.230000 477.440000 ;
+ RECT 2192.430000 471.520000 2193.230000 472.000000 ;
+ RECT 2192.430000 466.080000 2193.230000 466.560000 ;
+ RECT 2192.430000 875.470000 2720.920000 876.270000 ;
+ RECT 2192.430000 459.950000 2720.920000 460.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 458.500000 2193.230000 459.300000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 877.940000 2193.230000 878.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 458.500000 2719.490000 459.300000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 877.940000 2719.490000 878.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 459.950000 2720.920000 460.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 875.470000 2720.920000 876.270000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2222.420000 892.740000 2224.160000 1287.520000 ;
+ LAYER met3 ;
+ RECT 2222.420000 1285.780000 2699.480000 1287.520000 ;
+ LAYER met3 ;
+ RECT 2222.420000 892.740000 2699.480000 894.480000 ;
+ LAYER met4 ;
+ RECT 2697.740000 892.740000 2699.480000 1287.520000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 878.740000 2193.230000 1298.980000 ;
+ RECT 2718.690000 878.740000 2719.490000 1298.980000 ;
+ LAYER met3 ;
+ RECT 2718.690000 1288.880000 2719.490000 1289.360000 ;
+ RECT 2718.690000 1283.440000 2719.490000 1283.920000 ;
+ RECT 2718.690000 1278.000000 2719.490000 1278.480000 ;
+ RECT 2718.690000 1272.560000 2719.490000 1273.040000 ;
+ RECT 2718.690000 1267.120000 2719.490000 1267.600000 ;
+ RECT 2718.690000 1261.680000 2719.490000 1262.160000 ;
+ RECT 2718.690000 1256.240000 2719.490000 1256.720000 ;
+ RECT 2718.690000 1250.800000 2719.490000 1251.280000 ;
+ RECT 2718.690000 1245.360000 2719.490000 1245.840000 ;
+ RECT 2718.690000 1239.920000 2719.490000 1240.400000 ;
+ RECT 2718.690000 1234.480000 2719.490000 1234.960000 ;
+ RECT 2718.690000 1229.040000 2719.490000 1229.520000 ;
+ RECT 2718.690000 1223.600000 2719.490000 1224.080000 ;
+ RECT 2718.690000 1207.280000 2719.490000 1207.760000 ;
+ RECT 2718.690000 1212.720000 2719.490000 1213.200000 ;
+ RECT 2718.690000 1218.160000 2719.490000 1218.640000 ;
+ RECT 2718.690000 1201.840000 2719.490000 1202.320000 ;
+ RECT 2718.690000 1196.400000 2719.490000 1196.880000 ;
+ RECT 2718.690000 1190.960000 2719.490000 1191.440000 ;
+ RECT 2718.690000 1185.520000 2719.490000 1186.000000 ;
+ RECT 2718.690000 1180.080000 2719.490000 1180.560000 ;
+ RECT 2718.690000 1174.640000 2719.490000 1175.120000 ;
+ RECT 2718.690000 1169.200000 2719.490000 1169.680000 ;
+ RECT 2718.690000 1163.760000 2719.490000 1164.240000 ;
+ RECT 2718.690000 1158.320000 2719.490000 1158.800000 ;
+ RECT 2718.690000 1152.880000 2719.490000 1153.360000 ;
+ RECT 2718.690000 1147.440000 2719.490000 1147.920000 ;
+ RECT 2718.690000 1142.000000 2719.490000 1142.480000 ;
+ RECT 2718.690000 1136.560000 2719.490000 1137.040000 ;
+ RECT 2718.690000 1131.120000 2719.490000 1131.600000 ;
+ RECT 2718.690000 1125.680000 2719.490000 1126.160000 ;
+ RECT 2718.690000 1120.240000 2719.490000 1120.720000 ;
+ RECT 2718.690000 1114.800000 2719.490000 1115.280000 ;
+ RECT 2718.690000 1109.360000 2719.490000 1109.840000 ;
+ RECT 2718.690000 1103.920000 2719.490000 1104.400000 ;
+ RECT 2718.690000 1098.480000 2719.490000 1098.960000 ;
+ RECT 2718.690000 1093.040000 2719.490000 1093.520000 ;
+ RECT 2192.430000 1288.880000 2193.230000 1289.360000 ;
+ RECT 2192.430000 1283.440000 2193.230000 1283.920000 ;
+ RECT 2192.430000 1278.000000 2193.230000 1278.480000 ;
+ RECT 2192.430000 1272.560000 2193.230000 1273.040000 ;
+ RECT 2192.430000 1267.120000 2193.230000 1267.600000 ;
+ RECT 2192.430000 1261.680000 2193.230000 1262.160000 ;
+ RECT 2192.430000 1256.240000 2193.230000 1256.720000 ;
+ RECT 2192.430000 1250.800000 2193.230000 1251.280000 ;
+ RECT 2192.430000 1245.360000 2193.230000 1245.840000 ;
+ RECT 2192.430000 1239.920000 2193.230000 1240.400000 ;
+ RECT 2192.430000 1234.480000 2193.230000 1234.960000 ;
+ RECT 2192.430000 1229.040000 2193.230000 1229.520000 ;
+ RECT 2192.430000 1223.600000 2193.230000 1224.080000 ;
+ RECT 2192.430000 1207.280000 2193.230000 1207.760000 ;
+ RECT 2192.430000 1212.720000 2193.230000 1213.200000 ;
+ RECT 2192.430000 1218.160000 2193.230000 1218.640000 ;
+ RECT 2192.430000 1201.840000 2193.230000 1202.320000 ;
+ RECT 2192.430000 1196.400000 2193.230000 1196.880000 ;
+ RECT 2192.430000 1190.960000 2193.230000 1191.440000 ;
+ RECT 2192.430000 1185.520000 2193.230000 1186.000000 ;
+ RECT 2192.430000 1180.080000 2193.230000 1180.560000 ;
+ RECT 2192.430000 1174.640000 2193.230000 1175.120000 ;
+ RECT 2192.430000 1169.200000 2193.230000 1169.680000 ;
+ RECT 2192.430000 1163.760000 2193.230000 1164.240000 ;
+ RECT 2192.430000 1158.320000 2193.230000 1158.800000 ;
+ RECT 2192.430000 1152.880000 2193.230000 1153.360000 ;
+ RECT 2192.430000 1147.440000 2193.230000 1147.920000 ;
+ RECT 2192.430000 1142.000000 2193.230000 1142.480000 ;
+ RECT 2192.430000 1136.560000 2193.230000 1137.040000 ;
+ RECT 2192.430000 1131.120000 2193.230000 1131.600000 ;
+ RECT 2192.430000 1125.680000 2193.230000 1126.160000 ;
+ RECT 2192.430000 1120.240000 2193.230000 1120.720000 ;
+ RECT 2192.430000 1114.800000 2193.230000 1115.280000 ;
+ RECT 2192.430000 1109.360000 2193.230000 1109.840000 ;
+ RECT 2192.430000 1103.920000 2193.230000 1104.400000 ;
+ RECT 2192.430000 1098.480000 2193.230000 1098.960000 ;
+ RECT 2192.430000 1093.040000 2193.230000 1093.520000 ;
+ RECT 2718.690000 1087.600000 2719.490000 1088.080000 ;
+ RECT 2718.690000 1082.160000 2719.490000 1082.640000 ;
+ RECT 2718.690000 1076.720000 2719.490000 1077.200000 ;
+ RECT 2718.690000 1071.280000 2719.490000 1071.760000 ;
+ RECT 2718.690000 1065.840000 2719.490000 1066.320000 ;
+ RECT 2718.690000 1060.400000 2719.490000 1060.880000 ;
+ RECT 2718.690000 1054.960000 2719.490000 1055.440000 ;
+ RECT 2718.690000 1049.520000 2719.490000 1050.000000 ;
+ RECT 2718.690000 1044.080000 2719.490000 1044.560000 ;
+ RECT 2718.690000 1038.640000 2719.490000 1039.120000 ;
+ RECT 2718.690000 1033.200000 2719.490000 1033.680000 ;
+ RECT 2718.690000 1027.760000 2719.490000 1028.240000 ;
+ RECT 2718.690000 1011.440000 2719.490000 1011.920000 ;
+ RECT 2718.690000 1016.880000 2719.490000 1017.360000 ;
+ RECT 2718.690000 1000.560000 2719.490000 1001.040000 ;
+ RECT 2718.690000 995.120000 2719.490000 995.600000 ;
+ RECT 2718.690000 989.680000 2719.490000 990.160000 ;
+ RECT 2718.690000 1006.000000 2719.490000 1006.480000 ;
+ RECT 2718.690000 984.240000 2719.490000 984.720000 ;
+ RECT 2718.690000 978.800000 2719.490000 979.280000 ;
+ RECT 2718.690000 973.360000 2719.490000 973.840000 ;
+ RECT 2718.690000 967.920000 2719.490000 968.400000 ;
+ RECT 2718.690000 962.480000 2719.490000 962.960000 ;
+ RECT 2718.690000 957.040000 2719.490000 957.520000 ;
+ RECT 2718.690000 1022.320000 2719.490000 1022.800000 ;
+ RECT 2718.690000 951.600000 2719.490000 952.080000 ;
+ RECT 2718.690000 946.160000 2719.490000 946.640000 ;
+ RECT 2718.690000 940.720000 2719.490000 941.200000 ;
+ RECT 2718.690000 935.280000 2719.490000 935.760000 ;
+ RECT 2718.690000 929.840000 2719.490000 930.320000 ;
+ RECT 2718.690000 924.400000 2719.490000 924.880000 ;
+ RECT 2718.690000 918.960000 2719.490000 919.440000 ;
+ RECT 2718.690000 913.520000 2719.490000 914.000000 ;
+ RECT 2718.690000 908.080000 2719.490000 908.560000 ;
+ RECT 2718.690000 902.640000 2719.490000 903.120000 ;
+ RECT 2718.690000 897.200000 2719.490000 897.680000 ;
+ RECT 2718.690000 891.760000 2719.490000 892.240000 ;
+ RECT 2718.690000 886.320000 2719.490000 886.800000 ;
+ RECT 2192.430000 1082.160000 2193.230000 1082.640000 ;
+ RECT 2192.430000 1076.720000 2193.230000 1077.200000 ;
+ RECT 2192.430000 1087.600000 2193.230000 1088.080000 ;
+ RECT 2192.430000 1071.280000 2193.230000 1071.760000 ;
+ RECT 2192.430000 1065.840000 2193.230000 1066.320000 ;
+ RECT 2192.430000 1060.400000 2193.230000 1060.880000 ;
+ RECT 2192.430000 1054.960000 2193.230000 1055.440000 ;
+ RECT 2192.430000 1049.520000 2193.230000 1050.000000 ;
+ RECT 2192.430000 1044.080000 2193.230000 1044.560000 ;
+ RECT 2192.430000 1038.640000 2193.230000 1039.120000 ;
+ RECT 2192.430000 1033.200000 2193.230000 1033.680000 ;
+ RECT 2192.430000 1027.760000 2193.230000 1028.240000 ;
+ RECT 2192.430000 1011.440000 2193.230000 1011.920000 ;
+ RECT 2192.430000 1016.880000 2193.230000 1017.360000 ;
+ RECT 2192.430000 1000.560000 2193.230000 1001.040000 ;
+ RECT 2192.430000 995.120000 2193.230000 995.600000 ;
+ RECT 2192.430000 989.680000 2193.230000 990.160000 ;
+ RECT 2192.430000 1006.000000 2193.230000 1006.480000 ;
+ RECT 2192.430000 978.800000 2193.230000 979.280000 ;
+ RECT 2192.430000 973.360000 2193.230000 973.840000 ;
+ RECT 2192.430000 984.240000 2193.230000 984.720000 ;
+ RECT 2192.430000 967.920000 2193.230000 968.400000 ;
+ RECT 2192.430000 962.480000 2193.230000 962.960000 ;
+ RECT 2192.430000 957.040000 2193.230000 957.520000 ;
+ RECT 2192.430000 1022.320000 2193.230000 1022.800000 ;
+ RECT 2192.430000 951.600000 2193.230000 952.080000 ;
+ RECT 2192.430000 946.160000 2193.230000 946.640000 ;
+ RECT 2192.430000 940.720000 2193.230000 941.200000 ;
+ RECT 2192.430000 924.400000 2193.230000 924.880000 ;
+ RECT 2192.430000 935.280000 2193.230000 935.760000 ;
+ RECT 2192.430000 929.840000 2193.230000 930.320000 ;
+ RECT 2192.430000 918.960000 2193.230000 919.440000 ;
+ RECT 2192.430000 913.520000 2193.230000 914.000000 ;
+ RECT 2192.430000 908.080000 2193.230000 908.560000 ;
+ RECT 2192.430000 902.640000 2193.230000 903.120000 ;
+ RECT 2192.430000 897.200000 2193.230000 897.680000 ;
+ RECT 2192.430000 891.760000 2193.230000 892.240000 ;
+ RECT 2192.430000 886.320000 2193.230000 886.800000 ;
+ RECT 2192.430000 1295.710000 2720.920000 1296.510000 ;
+ RECT 2192.430000 880.190000 2720.920000 880.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 878.740000 2193.230000 879.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 1298.180000 2193.230000 1298.980000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 878.740000 2719.490000 879.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 1298.180000 2719.490000 1298.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 880.190000 2720.920000 880.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 1295.710000 2720.920000 1296.510000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2222.420000 1312.980000 2224.160000 1707.760000 ;
+ LAYER met3 ;
+ RECT 2222.420000 1706.020000 2699.480000 1707.760000 ;
+ LAYER met3 ;
+ RECT 2222.420000 1312.980000 2699.480000 1314.720000 ;
+ LAYER met4 ;
+ RECT 2697.740000 1312.980000 2699.480000 1707.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 1298.980000 2193.230000 1719.220000 ;
+ RECT 2718.690000 1298.980000 2719.490000 1719.220000 ;
+ LAYER met3 ;
+ RECT 2718.690000 1709.120000 2719.490000 1709.600000 ;
+ RECT 2718.690000 1703.680000 2719.490000 1704.160000 ;
+ RECT 2718.690000 1698.240000 2719.490000 1698.720000 ;
+ RECT 2718.690000 1692.800000 2719.490000 1693.280000 ;
+ RECT 2718.690000 1687.360000 2719.490000 1687.840000 ;
+ RECT 2718.690000 1681.920000 2719.490000 1682.400000 ;
+ RECT 2718.690000 1676.480000 2719.490000 1676.960000 ;
+ RECT 2718.690000 1671.040000 2719.490000 1671.520000 ;
+ RECT 2718.690000 1665.600000 2719.490000 1666.080000 ;
+ RECT 2718.690000 1660.160000 2719.490000 1660.640000 ;
+ RECT 2718.690000 1654.720000 2719.490000 1655.200000 ;
+ RECT 2718.690000 1649.280000 2719.490000 1649.760000 ;
+ RECT 2718.690000 1643.840000 2719.490000 1644.320000 ;
+ RECT 2718.690000 1627.520000 2719.490000 1628.000000 ;
+ RECT 2718.690000 1632.960000 2719.490000 1633.440000 ;
+ RECT 2718.690000 1638.400000 2719.490000 1638.880000 ;
+ RECT 2718.690000 1622.080000 2719.490000 1622.560000 ;
+ RECT 2718.690000 1616.640000 2719.490000 1617.120000 ;
+ RECT 2718.690000 1611.200000 2719.490000 1611.680000 ;
+ RECT 2718.690000 1605.760000 2719.490000 1606.240000 ;
+ RECT 2718.690000 1600.320000 2719.490000 1600.800000 ;
+ RECT 2718.690000 1594.880000 2719.490000 1595.360000 ;
+ RECT 2718.690000 1589.440000 2719.490000 1589.920000 ;
+ RECT 2718.690000 1584.000000 2719.490000 1584.480000 ;
+ RECT 2718.690000 1578.560000 2719.490000 1579.040000 ;
+ RECT 2718.690000 1573.120000 2719.490000 1573.600000 ;
+ RECT 2718.690000 1567.680000 2719.490000 1568.160000 ;
+ RECT 2718.690000 1562.240000 2719.490000 1562.720000 ;
+ RECT 2718.690000 1556.800000 2719.490000 1557.280000 ;
+ RECT 2718.690000 1551.360000 2719.490000 1551.840000 ;
+ RECT 2718.690000 1545.920000 2719.490000 1546.400000 ;
+ RECT 2718.690000 1540.480000 2719.490000 1540.960000 ;
+ RECT 2718.690000 1535.040000 2719.490000 1535.520000 ;
+ RECT 2718.690000 1529.600000 2719.490000 1530.080000 ;
+ RECT 2718.690000 1524.160000 2719.490000 1524.640000 ;
+ RECT 2718.690000 1518.720000 2719.490000 1519.200000 ;
+ RECT 2718.690000 1513.280000 2719.490000 1513.760000 ;
+ RECT 2192.430000 1709.120000 2193.230000 1709.600000 ;
+ RECT 2192.430000 1703.680000 2193.230000 1704.160000 ;
+ RECT 2192.430000 1698.240000 2193.230000 1698.720000 ;
+ RECT 2192.430000 1692.800000 2193.230000 1693.280000 ;
+ RECT 2192.430000 1687.360000 2193.230000 1687.840000 ;
+ RECT 2192.430000 1681.920000 2193.230000 1682.400000 ;
+ RECT 2192.430000 1676.480000 2193.230000 1676.960000 ;
+ RECT 2192.430000 1671.040000 2193.230000 1671.520000 ;
+ RECT 2192.430000 1665.600000 2193.230000 1666.080000 ;
+ RECT 2192.430000 1660.160000 2193.230000 1660.640000 ;
+ RECT 2192.430000 1654.720000 2193.230000 1655.200000 ;
+ RECT 2192.430000 1649.280000 2193.230000 1649.760000 ;
+ RECT 2192.430000 1643.840000 2193.230000 1644.320000 ;
+ RECT 2192.430000 1627.520000 2193.230000 1628.000000 ;
+ RECT 2192.430000 1632.960000 2193.230000 1633.440000 ;
+ RECT 2192.430000 1638.400000 2193.230000 1638.880000 ;
+ RECT 2192.430000 1622.080000 2193.230000 1622.560000 ;
+ RECT 2192.430000 1616.640000 2193.230000 1617.120000 ;
+ RECT 2192.430000 1611.200000 2193.230000 1611.680000 ;
+ RECT 2192.430000 1605.760000 2193.230000 1606.240000 ;
+ RECT 2192.430000 1600.320000 2193.230000 1600.800000 ;
+ RECT 2192.430000 1594.880000 2193.230000 1595.360000 ;
+ RECT 2192.430000 1589.440000 2193.230000 1589.920000 ;
+ RECT 2192.430000 1584.000000 2193.230000 1584.480000 ;
+ RECT 2192.430000 1578.560000 2193.230000 1579.040000 ;
+ RECT 2192.430000 1573.120000 2193.230000 1573.600000 ;
+ RECT 2192.430000 1567.680000 2193.230000 1568.160000 ;
+ RECT 2192.430000 1562.240000 2193.230000 1562.720000 ;
+ RECT 2192.430000 1556.800000 2193.230000 1557.280000 ;
+ RECT 2192.430000 1551.360000 2193.230000 1551.840000 ;
+ RECT 2192.430000 1545.920000 2193.230000 1546.400000 ;
+ RECT 2192.430000 1540.480000 2193.230000 1540.960000 ;
+ RECT 2192.430000 1535.040000 2193.230000 1535.520000 ;
+ RECT 2192.430000 1529.600000 2193.230000 1530.080000 ;
+ RECT 2192.430000 1524.160000 2193.230000 1524.640000 ;
+ RECT 2192.430000 1518.720000 2193.230000 1519.200000 ;
+ RECT 2192.430000 1513.280000 2193.230000 1513.760000 ;
+ RECT 2718.690000 1507.840000 2719.490000 1508.320000 ;
+ RECT 2718.690000 1502.400000 2719.490000 1502.880000 ;
+ RECT 2718.690000 1496.960000 2719.490000 1497.440000 ;
+ RECT 2718.690000 1491.520000 2719.490000 1492.000000 ;
+ RECT 2718.690000 1486.080000 2719.490000 1486.560000 ;
+ RECT 2718.690000 1480.640000 2719.490000 1481.120000 ;
+ RECT 2718.690000 1475.200000 2719.490000 1475.680000 ;
+ RECT 2718.690000 1469.760000 2719.490000 1470.240000 ;
+ RECT 2718.690000 1464.320000 2719.490000 1464.800000 ;
+ RECT 2718.690000 1458.880000 2719.490000 1459.360000 ;
+ RECT 2718.690000 1453.440000 2719.490000 1453.920000 ;
+ RECT 2718.690000 1448.000000 2719.490000 1448.480000 ;
+ RECT 2718.690000 1431.680000 2719.490000 1432.160000 ;
+ RECT 2718.690000 1437.120000 2719.490000 1437.600000 ;
+ RECT 2718.690000 1420.800000 2719.490000 1421.280000 ;
+ RECT 2718.690000 1415.360000 2719.490000 1415.840000 ;
+ RECT 2718.690000 1409.920000 2719.490000 1410.400000 ;
+ RECT 2718.690000 1426.240000 2719.490000 1426.720000 ;
+ RECT 2718.690000 1404.480000 2719.490000 1404.960000 ;
+ RECT 2718.690000 1399.040000 2719.490000 1399.520000 ;
+ RECT 2718.690000 1393.600000 2719.490000 1394.080000 ;
+ RECT 2718.690000 1388.160000 2719.490000 1388.640000 ;
+ RECT 2718.690000 1382.720000 2719.490000 1383.200000 ;
+ RECT 2718.690000 1377.280000 2719.490000 1377.760000 ;
+ RECT 2718.690000 1442.560000 2719.490000 1443.040000 ;
+ RECT 2718.690000 1371.840000 2719.490000 1372.320000 ;
+ RECT 2718.690000 1366.400000 2719.490000 1366.880000 ;
+ RECT 2718.690000 1360.960000 2719.490000 1361.440000 ;
+ RECT 2718.690000 1355.520000 2719.490000 1356.000000 ;
+ RECT 2718.690000 1350.080000 2719.490000 1350.560000 ;
+ RECT 2718.690000 1344.640000 2719.490000 1345.120000 ;
+ RECT 2718.690000 1339.200000 2719.490000 1339.680000 ;
+ RECT 2718.690000 1333.760000 2719.490000 1334.240000 ;
+ RECT 2718.690000 1328.320000 2719.490000 1328.800000 ;
+ RECT 2718.690000 1322.880000 2719.490000 1323.360000 ;
+ RECT 2718.690000 1317.440000 2719.490000 1317.920000 ;
+ RECT 2718.690000 1312.000000 2719.490000 1312.480000 ;
+ RECT 2718.690000 1306.560000 2719.490000 1307.040000 ;
+ RECT 2192.430000 1502.400000 2193.230000 1502.880000 ;
+ RECT 2192.430000 1496.960000 2193.230000 1497.440000 ;
+ RECT 2192.430000 1507.840000 2193.230000 1508.320000 ;
+ RECT 2192.430000 1491.520000 2193.230000 1492.000000 ;
+ RECT 2192.430000 1486.080000 2193.230000 1486.560000 ;
+ RECT 2192.430000 1480.640000 2193.230000 1481.120000 ;
+ RECT 2192.430000 1475.200000 2193.230000 1475.680000 ;
+ RECT 2192.430000 1469.760000 2193.230000 1470.240000 ;
+ RECT 2192.430000 1464.320000 2193.230000 1464.800000 ;
+ RECT 2192.430000 1458.880000 2193.230000 1459.360000 ;
+ RECT 2192.430000 1453.440000 2193.230000 1453.920000 ;
+ RECT 2192.430000 1448.000000 2193.230000 1448.480000 ;
+ RECT 2192.430000 1431.680000 2193.230000 1432.160000 ;
+ RECT 2192.430000 1437.120000 2193.230000 1437.600000 ;
+ RECT 2192.430000 1420.800000 2193.230000 1421.280000 ;
+ RECT 2192.430000 1415.360000 2193.230000 1415.840000 ;
+ RECT 2192.430000 1409.920000 2193.230000 1410.400000 ;
+ RECT 2192.430000 1426.240000 2193.230000 1426.720000 ;
+ RECT 2192.430000 1399.040000 2193.230000 1399.520000 ;
+ RECT 2192.430000 1393.600000 2193.230000 1394.080000 ;
+ RECT 2192.430000 1404.480000 2193.230000 1404.960000 ;
+ RECT 2192.430000 1388.160000 2193.230000 1388.640000 ;
+ RECT 2192.430000 1382.720000 2193.230000 1383.200000 ;
+ RECT 2192.430000 1377.280000 2193.230000 1377.760000 ;
+ RECT 2192.430000 1442.560000 2193.230000 1443.040000 ;
+ RECT 2192.430000 1371.840000 2193.230000 1372.320000 ;
+ RECT 2192.430000 1366.400000 2193.230000 1366.880000 ;
+ RECT 2192.430000 1360.960000 2193.230000 1361.440000 ;
+ RECT 2192.430000 1344.640000 2193.230000 1345.120000 ;
+ RECT 2192.430000 1355.520000 2193.230000 1356.000000 ;
+ RECT 2192.430000 1350.080000 2193.230000 1350.560000 ;
+ RECT 2192.430000 1339.200000 2193.230000 1339.680000 ;
+ RECT 2192.430000 1333.760000 2193.230000 1334.240000 ;
+ RECT 2192.430000 1328.320000 2193.230000 1328.800000 ;
+ RECT 2192.430000 1322.880000 2193.230000 1323.360000 ;
+ RECT 2192.430000 1317.440000 2193.230000 1317.920000 ;
+ RECT 2192.430000 1312.000000 2193.230000 1312.480000 ;
+ RECT 2192.430000 1306.560000 2193.230000 1307.040000 ;
+ RECT 2192.430000 1715.950000 2720.920000 1716.750000 ;
+ RECT 2192.430000 1300.430000 2720.920000 1301.230000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 1298.980000 2193.230000 1299.780000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 1718.420000 2193.230000 1719.220000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 1298.980000 2719.490000 1299.780000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 1718.420000 2719.490000 1719.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 1300.430000 2720.920000 1301.230000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 1715.950000 2720.920000 1716.750000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2222.420000 1733.220000 2224.160000 2128.000000 ;
+ LAYER met3 ;
+ RECT 2222.420000 2126.260000 2699.480000 2128.000000 ;
+ LAYER met3 ;
+ RECT 2222.420000 1733.220000 2699.480000 1734.960000 ;
+ LAYER met4 ;
+ RECT 2697.740000 1733.220000 2699.480000 2128.000000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 1719.220000 2193.230000 2139.460000 ;
+ RECT 2718.690000 1719.220000 2719.490000 2139.460000 ;
+ LAYER met3 ;
+ RECT 2718.690000 2129.360000 2719.490000 2129.840000 ;
+ RECT 2718.690000 2123.920000 2719.490000 2124.400000 ;
+ RECT 2718.690000 2118.480000 2719.490000 2118.960000 ;
+ RECT 2718.690000 2113.040000 2719.490000 2113.520000 ;
+ RECT 2718.690000 2107.600000 2719.490000 2108.080000 ;
+ RECT 2718.690000 2102.160000 2719.490000 2102.640000 ;
+ RECT 2718.690000 2096.720000 2719.490000 2097.200000 ;
+ RECT 2718.690000 2091.280000 2719.490000 2091.760000 ;
+ RECT 2718.690000 2085.840000 2719.490000 2086.320000 ;
+ RECT 2718.690000 2080.400000 2719.490000 2080.880000 ;
+ RECT 2718.690000 2074.960000 2719.490000 2075.440000 ;
+ RECT 2718.690000 2069.520000 2719.490000 2070.000000 ;
+ RECT 2718.690000 2064.080000 2719.490000 2064.560000 ;
+ RECT 2718.690000 2047.760000 2719.490000 2048.240000 ;
+ RECT 2718.690000 2053.200000 2719.490000 2053.680000 ;
+ RECT 2718.690000 2058.640000 2719.490000 2059.120000 ;
+ RECT 2718.690000 2042.320000 2719.490000 2042.800000 ;
+ RECT 2718.690000 2036.880000 2719.490000 2037.360000 ;
+ RECT 2718.690000 2031.440000 2719.490000 2031.920000 ;
+ RECT 2718.690000 2026.000000 2719.490000 2026.480000 ;
+ RECT 2718.690000 2020.560000 2719.490000 2021.040000 ;
+ RECT 2718.690000 2015.120000 2719.490000 2015.600000 ;
+ RECT 2718.690000 2009.680000 2719.490000 2010.160000 ;
+ RECT 2718.690000 2004.240000 2719.490000 2004.720000 ;
+ RECT 2718.690000 1998.800000 2719.490000 1999.280000 ;
+ RECT 2718.690000 1993.360000 2719.490000 1993.840000 ;
+ RECT 2718.690000 1987.920000 2719.490000 1988.400000 ;
+ RECT 2718.690000 1982.480000 2719.490000 1982.960000 ;
+ RECT 2718.690000 1977.040000 2719.490000 1977.520000 ;
+ RECT 2718.690000 1971.600000 2719.490000 1972.080000 ;
+ RECT 2718.690000 1966.160000 2719.490000 1966.640000 ;
+ RECT 2718.690000 1960.720000 2719.490000 1961.200000 ;
+ RECT 2718.690000 1955.280000 2719.490000 1955.760000 ;
+ RECT 2718.690000 1949.840000 2719.490000 1950.320000 ;
+ RECT 2718.690000 1944.400000 2719.490000 1944.880000 ;
+ RECT 2718.690000 1938.960000 2719.490000 1939.440000 ;
+ RECT 2718.690000 1933.520000 2719.490000 1934.000000 ;
+ RECT 2192.430000 2129.360000 2193.230000 2129.840000 ;
+ RECT 2192.430000 2123.920000 2193.230000 2124.400000 ;
+ RECT 2192.430000 2118.480000 2193.230000 2118.960000 ;
+ RECT 2192.430000 2113.040000 2193.230000 2113.520000 ;
+ RECT 2192.430000 2107.600000 2193.230000 2108.080000 ;
+ RECT 2192.430000 2102.160000 2193.230000 2102.640000 ;
+ RECT 2192.430000 2096.720000 2193.230000 2097.200000 ;
+ RECT 2192.430000 2091.280000 2193.230000 2091.760000 ;
+ RECT 2192.430000 2085.840000 2193.230000 2086.320000 ;
+ RECT 2192.430000 2080.400000 2193.230000 2080.880000 ;
+ RECT 2192.430000 2074.960000 2193.230000 2075.440000 ;
+ RECT 2192.430000 2069.520000 2193.230000 2070.000000 ;
+ RECT 2192.430000 2064.080000 2193.230000 2064.560000 ;
+ RECT 2192.430000 2047.760000 2193.230000 2048.240000 ;
+ RECT 2192.430000 2053.200000 2193.230000 2053.680000 ;
+ RECT 2192.430000 2058.640000 2193.230000 2059.120000 ;
+ RECT 2192.430000 2042.320000 2193.230000 2042.800000 ;
+ RECT 2192.430000 2036.880000 2193.230000 2037.360000 ;
+ RECT 2192.430000 2031.440000 2193.230000 2031.920000 ;
+ RECT 2192.430000 2026.000000 2193.230000 2026.480000 ;
+ RECT 2192.430000 2020.560000 2193.230000 2021.040000 ;
+ RECT 2192.430000 2015.120000 2193.230000 2015.600000 ;
+ RECT 2192.430000 2009.680000 2193.230000 2010.160000 ;
+ RECT 2192.430000 2004.240000 2193.230000 2004.720000 ;
+ RECT 2192.430000 1998.800000 2193.230000 1999.280000 ;
+ RECT 2192.430000 1993.360000 2193.230000 1993.840000 ;
+ RECT 2192.430000 1987.920000 2193.230000 1988.400000 ;
+ RECT 2192.430000 1982.480000 2193.230000 1982.960000 ;
+ RECT 2192.430000 1977.040000 2193.230000 1977.520000 ;
+ RECT 2192.430000 1971.600000 2193.230000 1972.080000 ;
+ RECT 2192.430000 1966.160000 2193.230000 1966.640000 ;
+ RECT 2192.430000 1960.720000 2193.230000 1961.200000 ;
+ RECT 2192.430000 1955.280000 2193.230000 1955.760000 ;
+ RECT 2192.430000 1949.840000 2193.230000 1950.320000 ;
+ RECT 2192.430000 1944.400000 2193.230000 1944.880000 ;
+ RECT 2192.430000 1938.960000 2193.230000 1939.440000 ;
+ RECT 2192.430000 1933.520000 2193.230000 1934.000000 ;
+ RECT 2718.690000 1928.080000 2719.490000 1928.560000 ;
+ RECT 2718.690000 1922.640000 2719.490000 1923.120000 ;
+ RECT 2718.690000 1917.200000 2719.490000 1917.680000 ;
+ RECT 2718.690000 1911.760000 2719.490000 1912.240000 ;
+ RECT 2718.690000 1906.320000 2719.490000 1906.800000 ;
+ RECT 2718.690000 1900.880000 2719.490000 1901.360000 ;
+ RECT 2718.690000 1895.440000 2719.490000 1895.920000 ;
+ RECT 2718.690000 1890.000000 2719.490000 1890.480000 ;
+ RECT 2718.690000 1884.560000 2719.490000 1885.040000 ;
+ RECT 2718.690000 1879.120000 2719.490000 1879.600000 ;
+ RECT 2718.690000 1873.680000 2719.490000 1874.160000 ;
+ RECT 2718.690000 1868.240000 2719.490000 1868.720000 ;
+ RECT 2718.690000 1851.920000 2719.490000 1852.400000 ;
+ RECT 2718.690000 1857.360000 2719.490000 1857.840000 ;
+ RECT 2718.690000 1841.040000 2719.490000 1841.520000 ;
+ RECT 2718.690000 1835.600000 2719.490000 1836.080000 ;
+ RECT 2718.690000 1830.160000 2719.490000 1830.640000 ;
+ RECT 2718.690000 1846.480000 2719.490000 1846.960000 ;
+ RECT 2718.690000 1824.720000 2719.490000 1825.200000 ;
+ RECT 2718.690000 1819.280000 2719.490000 1819.760000 ;
+ RECT 2718.690000 1813.840000 2719.490000 1814.320000 ;
+ RECT 2718.690000 1808.400000 2719.490000 1808.880000 ;
+ RECT 2718.690000 1802.960000 2719.490000 1803.440000 ;
+ RECT 2718.690000 1797.520000 2719.490000 1798.000000 ;
+ RECT 2718.690000 1862.800000 2719.490000 1863.280000 ;
+ RECT 2718.690000 1792.080000 2719.490000 1792.560000 ;
+ RECT 2718.690000 1786.640000 2719.490000 1787.120000 ;
+ RECT 2718.690000 1781.200000 2719.490000 1781.680000 ;
+ RECT 2718.690000 1775.760000 2719.490000 1776.240000 ;
+ RECT 2718.690000 1770.320000 2719.490000 1770.800000 ;
+ RECT 2718.690000 1764.880000 2719.490000 1765.360000 ;
+ RECT 2718.690000 1759.440000 2719.490000 1759.920000 ;
+ RECT 2718.690000 1754.000000 2719.490000 1754.480000 ;
+ RECT 2718.690000 1748.560000 2719.490000 1749.040000 ;
+ RECT 2718.690000 1743.120000 2719.490000 1743.600000 ;
+ RECT 2718.690000 1737.680000 2719.490000 1738.160000 ;
+ RECT 2718.690000 1732.240000 2719.490000 1732.720000 ;
+ RECT 2718.690000 1726.800000 2719.490000 1727.280000 ;
+ RECT 2192.430000 1922.640000 2193.230000 1923.120000 ;
+ RECT 2192.430000 1917.200000 2193.230000 1917.680000 ;
+ RECT 2192.430000 1928.080000 2193.230000 1928.560000 ;
+ RECT 2192.430000 1911.760000 2193.230000 1912.240000 ;
+ RECT 2192.430000 1906.320000 2193.230000 1906.800000 ;
+ RECT 2192.430000 1900.880000 2193.230000 1901.360000 ;
+ RECT 2192.430000 1895.440000 2193.230000 1895.920000 ;
+ RECT 2192.430000 1890.000000 2193.230000 1890.480000 ;
+ RECT 2192.430000 1884.560000 2193.230000 1885.040000 ;
+ RECT 2192.430000 1879.120000 2193.230000 1879.600000 ;
+ RECT 2192.430000 1873.680000 2193.230000 1874.160000 ;
+ RECT 2192.430000 1868.240000 2193.230000 1868.720000 ;
+ RECT 2192.430000 1851.920000 2193.230000 1852.400000 ;
+ RECT 2192.430000 1857.360000 2193.230000 1857.840000 ;
+ RECT 2192.430000 1841.040000 2193.230000 1841.520000 ;
+ RECT 2192.430000 1835.600000 2193.230000 1836.080000 ;
+ RECT 2192.430000 1830.160000 2193.230000 1830.640000 ;
+ RECT 2192.430000 1846.480000 2193.230000 1846.960000 ;
+ RECT 2192.430000 1819.280000 2193.230000 1819.760000 ;
+ RECT 2192.430000 1813.840000 2193.230000 1814.320000 ;
+ RECT 2192.430000 1824.720000 2193.230000 1825.200000 ;
+ RECT 2192.430000 1808.400000 2193.230000 1808.880000 ;
+ RECT 2192.430000 1802.960000 2193.230000 1803.440000 ;
+ RECT 2192.430000 1797.520000 2193.230000 1798.000000 ;
+ RECT 2192.430000 1862.800000 2193.230000 1863.280000 ;
+ RECT 2192.430000 1792.080000 2193.230000 1792.560000 ;
+ RECT 2192.430000 1786.640000 2193.230000 1787.120000 ;
+ RECT 2192.430000 1781.200000 2193.230000 1781.680000 ;
+ RECT 2192.430000 1764.880000 2193.230000 1765.360000 ;
+ RECT 2192.430000 1775.760000 2193.230000 1776.240000 ;
+ RECT 2192.430000 1770.320000 2193.230000 1770.800000 ;
+ RECT 2192.430000 1759.440000 2193.230000 1759.920000 ;
+ RECT 2192.430000 1754.000000 2193.230000 1754.480000 ;
+ RECT 2192.430000 1748.560000 2193.230000 1749.040000 ;
+ RECT 2192.430000 1743.120000 2193.230000 1743.600000 ;
+ RECT 2192.430000 1737.680000 2193.230000 1738.160000 ;
+ RECT 2192.430000 1732.240000 2193.230000 1732.720000 ;
+ RECT 2192.430000 1726.800000 2193.230000 1727.280000 ;
+ RECT 2192.430000 2136.190000 2720.920000 2136.990000 ;
+ RECT 2192.430000 1720.670000 2720.920000 1721.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 1719.220000 2193.230000 1720.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 2138.660000 2193.230000 2139.460000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 1719.220000 2719.490000 1720.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 2138.660000 2719.490000 2139.460000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 1720.670000 2720.920000 1721.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2136.190000 2720.920000 2136.990000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2222.420000 2153.460000 2224.160000 2548.240000 ;
+ LAYER met3 ;
+ RECT 2222.420000 2546.500000 2699.480000 2548.240000 ;
+ LAYER met3 ;
+ RECT 2222.420000 2153.460000 2699.480000 2155.200000 ;
+ LAYER met4 ;
+ RECT 2697.740000 2153.460000 2699.480000 2548.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 2139.460000 2193.230000 2559.700000 ;
+ RECT 2718.690000 2139.460000 2719.490000 2559.700000 ;
+ LAYER met3 ;
+ RECT 2718.690000 2549.600000 2719.490000 2550.080000 ;
+ RECT 2718.690000 2544.160000 2719.490000 2544.640000 ;
+ RECT 2718.690000 2538.720000 2719.490000 2539.200000 ;
+ RECT 2718.690000 2533.280000 2719.490000 2533.760000 ;
+ RECT 2718.690000 2527.840000 2719.490000 2528.320000 ;
+ RECT 2718.690000 2522.400000 2719.490000 2522.880000 ;
+ RECT 2718.690000 2516.960000 2719.490000 2517.440000 ;
+ RECT 2718.690000 2511.520000 2719.490000 2512.000000 ;
+ RECT 2718.690000 2506.080000 2719.490000 2506.560000 ;
+ RECT 2718.690000 2500.640000 2719.490000 2501.120000 ;
+ RECT 2718.690000 2495.200000 2719.490000 2495.680000 ;
+ RECT 2718.690000 2489.760000 2719.490000 2490.240000 ;
+ RECT 2718.690000 2484.320000 2719.490000 2484.800000 ;
+ RECT 2718.690000 2468.000000 2719.490000 2468.480000 ;
+ RECT 2718.690000 2473.440000 2719.490000 2473.920000 ;
+ RECT 2718.690000 2478.880000 2719.490000 2479.360000 ;
+ RECT 2718.690000 2462.560000 2719.490000 2463.040000 ;
+ RECT 2718.690000 2457.120000 2719.490000 2457.600000 ;
+ RECT 2718.690000 2451.680000 2719.490000 2452.160000 ;
+ RECT 2718.690000 2446.240000 2719.490000 2446.720000 ;
+ RECT 2718.690000 2440.800000 2719.490000 2441.280000 ;
+ RECT 2718.690000 2435.360000 2719.490000 2435.840000 ;
+ RECT 2718.690000 2429.920000 2719.490000 2430.400000 ;
+ RECT 2718.690000 2424.480000 2719.490000 2424.960000 ;
+ RECT 2718.690000 2419.040000 2719.490000 2419.520000 ;
+ RECT 2718.690000 2413.600000 2719.490000 2414.080000 ;
+ RECT 2718.690000 2408.160000 2719.490000 2408.640000 ;
+ RECT 2718.690000 2402.720000 2719.490000 2403.200000 ;
+ RECT 2718.690000 2397.280000 2719.490000 2397.760000 ;
+ RECT 2718.690000 2391.840000 2719.490000 2392.320000 ;
+ RECT 2718.690000 2386.400000 2719.490000 2386.880000 ;
+ RECT 2718.690000 2380.960000 2719.490000 2381.440000 ;
+ RECT 2718.690000 2375.520000 2719.490000 2376.000000 ;
+ RECT 2718.690000 2370.080000 2719.490000 2370.560000 ;
+ RECT 2718.690000 2364.640000 2719.490000 2365.120000 ;
+ RECT 2718.690000 2359.200000 2719.490000 2359.680000 ;
+ RECT 2718.690000 2353.760000 2719.490000 2354.240000 ;
+ RECT 2192.430000 2549.600000 2193.230000 2550.080000 ;
+ RECT 2192.430000 2544.160000 2193.230000 2544.640000 ;
+ RECT 2192.430000 2538.720000 2193.230000 2539.200000 ;
+ RECT 2192.430000 2533.280000 2193.230000 2533.760000 ;
+ RECT 2192.430000 2527.840000 2193.230000 2528.320000 ;
+ RECT 2192.430000 2522.400000 2193.230000 2522.880000 ;
+ RECT 2192.430000 2516.960000 2193.230000 2517.440000 ;
+ RECT 2192.430000 2511.520000 2193.230000 2512.000000 ;
+ RECT 2192.430000 2506.080000 2193.230000 2506.560000 ;
+ RECT 2192.430000 2500.640000 2193.230000 2501.120000 ;
+ RECT 2192.430000 2495.200000 2193.230000 2495.680000 ;
+ RECT 2192.430000 2489.760000 2193.230000 2490.240000 ;
+ RECT 2192.430000 2484.320000 2193.230000 2484.800000 ;
+ RECT 2192.430000 2468.000000 2193.230000 2468.480000 ;
+ RECT 2192.430000 2473.440000 2193.230000 2473.920000 ;
+ RECT 2192.430000 2478.880000 2193.230000 2479.360000 ;
+ RECT 2192.430000 2462.560000 2193.230000 2463.040000 ;
+ RECT 2192.430000 2457.120000 2193.230000 2457.600000 ;
+ RECT 2192.430000 2451.680000 2193.230000 2452.160000 ;
+ RECT 2192.430000 2446.240000 2193.230000 2446.720000 ;
+ RECT 2192.430000 2440.800000 2193.230000 2441.280000 ;
+ RECT 2192.430000 2435.360000 2193.230000 2435.840000 ;
+ RECT 2192.430000 2429.920000 2193.230000 2430.400000 ;
+ RECT 2192.430000 2424.480000 2193.230000 2424.960000 ;
+ RECT 2192.430000 2419.040000 2193.230000 2419.520000 ;
+ RECT 2192.430000 2413.600000 2193.230000 2414.080000 ;
+ RECT 2192.430000 2408.160000 2193.230000 2408.640000 ;
+ RECT 2192.430000 2402.720000 2193.230000 2403.200000 ;
+ RECT 2192.430000 2397.280000 2193.230000 2397.760000 ;
+ RECT 2192.430000 2391.840000 2193.230000 2392.320000 ;
+ RECT 2192.430000 2386.400000 2193.230000 2386.880000 ;
+ RECT 2192.430000 2380.960000 2193.230000 2381.440000 ;
+ RECT 2192.430000 2375.520000 2193.230000 2376.000000 ;
+ RECT 2192.430000 2370.080000 2193.230000 2370.560000 ;
+ RECT 2192.430000 2364.640000 2193.230000 2365.120000 ;
+ RECT 2192.430000 2359.200000 2193.230000 2359.680000 ;
+ RECT 2192.430000 2353.760000 2193.230000 2354.240000 ;
+ RECT 2718.690000 2348.320000 2719.490000 2348.800000 ;
+ RECT 2718.690000 2342.880000 2719.490000 2343.360000 ;
+ RECT 2718.690000 2337.440000 2719.490000 2337.920000 ;
+ RECT 2718.690000 2332.000000 2719.490000 2332.480000 ;
+ RECT 2718.690000 2326.560000 2719.490000 2327.040000 ;
+ RECT 2718.690000 2321.120000 2719.490000 2321.600000 ;
+ RECT 2718.690000 2315.680000 2719.490000 2316.160000 ;
+ RECT 2718.690000 2310.240000 2719.490000 2310.720000 ;
+ RECT 2718.690000 2304.800000 2719.490000 2305.280000 ;
+ RECT 2718.690000 2299.360000 2719.490000 2299.840000 ;
+ RECT 2718.690000 2293.920000 2719.490000 2294.400000 ;
+ RECT 2718.690000 2288.480000 2719.490000 2288.960000 ;
+ RECT 2718.690000 2272.160000 2719.490000 2272.640000 ;
+ RECT 2718.690000 2277.600000 2719.490000 2278.080000 ;
+ RECT 2718.690000 2261.280000 2719.490000 2261.760000 ;
+ RECT 2718.690000 2255.840000 2719.490000 2256.320000 ;
+ RECT 2718.690000 2250.400000 2719.490000 2250.880000 ;
+ RECT 2718.690000 2266.720000 2719.490000 2267.200000 ;
+ RECT 2718.690000 2244.960000 2719.490000 2245.440000 ;
+ RECT 2718.690000 2239.520000 2719.490000 2240.000000 ;
+ RECT 2718.690000 2234.080000 2719.490000 2234.560000 ;
+ RECT 2718.690000 2228.640000 2719.490000 2229.120000 ;
+ RECT 2718.690000 2223.200000 2719.490000 2223.680000 ;
+ RECT 2718.690000 2217.760000 2719.490000 2218.240000 ;
+ RECT 2718.690000 2283.040000 2719.490000 2283.520000 ;
+ RECT 2718.690000 2212.320000 2719.490000 2212.800000 ;
+ RECT 2718.690000 2206.880000 2719.490000 2207.360000 ;
+ RECT 2718.690000 2201.440000 2719.490000 2201.920000 ;
+ RECT 2718.690000 2196.000000 2719.490000 2196.480000 ;
+ RECT 2718.690000 2190.560000 2719.490000 2191.040000 ;
+ RECT 2718.690000 2185.120000 2719.490000 2185.600000 ;
+ RECT 2718.690000 2179.680000 2719.490000 2180.160000 ;
+ RECT 2718.690000 2174.240000 2719.490000 2174.720000 ;
+ RECT 2718.690000 2168.800000 2719.490000 2169.280000 ;
+ RECT 2718.690000 2163.360000 2719.490000 2163.840000 ;
+ RECT 2718.690000 2157.920000 2719.490000 2158.400000 ;
+ RECT 2718.690000 2152.480000 2719.490000 2152.960000 ;
+ RECT 2718.690000 2147.040000 2719.490000 2147.520000 ;
+ RECT 2192.430000 2342.880000 2193.230000 2343.360000 ;
+ RECT 2192.430000 2337.440000 2193.230000 2337.920000 ;
+ RECT 2192.430000 2348.320000 2193.230000 2348.800000 ;
+ RECT 2192.430000 2332.000000 2193.230000 2332.480000 ;
+ RECT 2192.430000 2326.560000 2193.230000 2327.040000 ;
+ RECT 2192.430000 2321.120000 2193.230000 2321.600000 ;
+ RECT 2192.430000 2315.680000 2193.230000 2316.160000 ;
+ RECT 2192.430000 2310.240000 2193.230000 2310.720000 ;
+ RECT 2192.430000 2304.800000 2193.230000 2305.280000 ;
+ RECT 2192.430000 2299.360000 2193.230000 2299.840000 ;
+ RECT 2192.430000 2293.920000 2193.230000 2294.400000 ;
+ RECT 2192.430000 2288.480000 2193.230000 2288.960000 ;
+ RECT 2192.430000 2272.160000 2193.230000 2272.640000 ;
+ RECT 2192.430000 2277.600000 2193.230000 2278.080000 ;
+ RECT 2192.430000 2261.280000 2193.230000 2261.760000 ;
+ RECT 2192.430000 2255.840000 2193.230000 2256.320000 ;
+ RECT 2192.430000 2250.400000 2193.230000 2250.880000 ;
+ RECT 2192.430000 2266.720000 2193.230000 2267.200000 ;
+ RECT 2192.430000 2239.520000 2193.230000 2240.000000 ;
+ RECT 2192.430000 2234.080000 2193.230000 2234.560000 ;
+ RECT 2192.430000 2244.960000 2193.230000 2245.440000 ;
+ RECT 2192.430000 2228.640000 2193.230000 2229.120000 ;
+ RECT 2192.430000 2223.200000 2193.230000 2223.680000 ;
+ RECT 2192.430000 2217.760000 2193.230000 2218.240000 ;
+ RECT 2192.430000 2283.040000 2193.230000 2283.520000 ;
+ RECT 2192.430000 2212.320000 2193.230000 2212.800000 ;
+ RECT 2192.430000 2206.880000 2193.230000 2207.360000 ;
+ RECT 2192.430000 2201.440000 2193.230000 2201.920000 ;
+ RECT 2192.430000 2185.120000 2193.230000 2185.600000 ;
+ RECT 2192.430000 2196.000000 2193.230000 2196.480000 ;
+ RECT 2192.430000 2190.560000 2193.230000 2191.040000 ;
+ RECT 2192.430000 2179.680000 2193.230000 2180.160000 ;
+ RECT 2192.430000 2174.240000 2193.230000 2174.720000 ;
+ RECT 2192.430000 2168.800000 2193.230000 2169.280000 ;
+ RECT 2192.430000 2163.360000 2193.230000 2163.840000 ;
+ RECT 2192.430000 2157.920000 2193.230000 2158.400000 ;
+ RECT 2192.430000 2152.480000 2193.230000 2152.960000 ;
+ RECT 2192.430000 2147.040000 2193.230000 2147.520000 ;
+ RECT 2192.430000 2556.430000 2720.920000 2557.230000 ;
+ RECT 2192.430000 2140.910000 2720.920000 2141.710000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 2139.460000 2193.230000 2140.260000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 2558.900000 2193.230000 2559.700000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 2139.460000 2719.490000 2140.260000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 2558.900000 2719.490000 2559.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2140.910000 2720.920000 2141.710000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2556.430000 2720.920000 2557.230000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2222.420000 2573.700000 2224.160000 2968.480000 ;
+ LAYER met3 ;
+ RECT 2222.420000 2966.740000 2699.480000 2968.480000 ;
+ LAYER met3 ;
+ RECT 2222.420000 2573.700000 2699.480000 2575.440000 ;
+ LAYER met4 ;
+ RECT 2697.740000 2573.700000 2699.480000 2968.480000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 2559.700000 2193.230000 2979.940000 ;
+ RECT 2718.690000 2559.700000 2719.490000 2979.940000 ;
+ LAYER met3 ;
+ RECT 2718.690000 2969.840000 2719.490000 2970.320000 ;
+ RECT 2718.690000 2964.400000 2719.490000 2964.880000 ;
+ RECT 2718.690000 2958.960000 2719.490000 2959.440000 ;
+ RECT 2718.690000 2953.520000 2719.490000 2954.000000 ;
+ RECT 2718.690000 2948.080000 2719.490000 2948.560000 ;
+ RECT 2718.690000 2942.640000 2719.490000 2943.120000 ;
+ RECT 2718.690000 2937.200000 2719.490000 2937.680000 ;
+ RECT 2718.690000 2931.760000 2719.490000 2932.240000 ;
+ RECT 2718.690000 2926.320000 2719.490000 2926.800000 ;
+ RECT 2718.690000 2920.880000 2719.490000 2921.360000 ;
+ RECT 2718.690000 2915.440000 2719.490000 2915.920000 ;
+ RECT 2718.690000 2910.000000 2719.490000 2910.480000 ;
+ RECT 2718.690000 2904.560000 2719.490000 2905.040000 ;
+ RECT 2718.690000 2888.240000 2719.490000 2888.720000 ;
+ RECT 2718.690000 2893.680000 2719.490000 2894.160000 ;
+ RECT 2718.690000 2899.120000 2719.490000 2899.600000 ;
+ RECT 2718.690000 2882.800000 2719.490000 2883.280000 ;
+ RECT 2718.690000 2877.360000 2719.490000 2877.840000 ;
+ RECT 2718.690000 2871.920000 2719.490000 2872.400000 ;
+ RECT 2718.690000 2866.480000 2719.490000 2866.960000 ;
+ RECT 2718.690000 2861.040000 2719.490000 2861.520000 ;
+ RECT 2718.690000 2855.600000 2719.490000 2856.080000 ;
+ RECT 2718.690000 2850.160000 2719.490000 2850.640000 ;
+ RECT 2718.690000 2844.720000 2719.490000 2845.200000 ;
+ RECT 2718.690000 2839.280000 2719.490000 2839.760000 ;
+ RECT 2718.690000 2833.840000 2719.490000 2834.320000 ;
+ RECT 2718.690000 2828.400000 2719.490000 2828.880000 ;
+ RECT 2718.690000 2822.960000 2719.490000 2823.440000 ;
+ RECT 2718.690000 2817.520000 2719.490000 2818.000000 ;
+ RECT 2718.690000 2812.080000 2719.490000 2812.560000 ;
+ RECT 2718.690000 2806.640000 2719.490000 2807.120000 ;
+ RECT 2718.690000 2801.200000 2719.490000 2801.680000 ;
+ RECT 2718.690000 2795.760000 2719.490000 2796.240000 ;
+ RECT 2718.690000 2790.320000 2719.490000 2790.800000 ;
+ RECT 2718.690000 2784.880000 2719.490000 2785.360000 ;
+ RECT 2718.690000 2779.440000 2719.490000 2779.920000 ;
+ RECT 2718.690000 2774.000000 2719.490000 2774.480000 ;
+ RECT 2192.430000 2969.840000 2193.230000 2970.320000 ;
+ RECT 2192.430000 2964.400000 2193.230000 2964.880000 ;
+ RECT 2192.430000 2958.960000 2193.230000 2959.440000 ;
+ RECT 2192.430000 2953.520000 2193.230000 2954.000000 ;
+ RECT 2192.430000 2948.080000 2193.230000 2948.560000 ;
+ RECT 2192.430000 2942.640000 2193.230000 2943.120000 ;
+ RECT 2192.430000 2937.200000 2193.230000 2937.680000 ;
+ RECT 2192.430000 2931.760000 2193.230000 2932.240000 ;
+ RECT 2192.430000 2926.320000 2193.230000 2926.800000 ;
+ RECT 2192.430000 2920.880000 2193.230000 2921.360000 ;
+ RECT 2192.430000 2915.440000 2193.230000 2915.920000 ;
+ RECT 2192.430000 2910.000000 2193.230000 2910.480000 ;
+ RECT 2192.430000 2904.560000 2193.230000 2905.040000 ;
+ RECT 2192.430000 2888.240000 2193.230000 2888.720000 ;
+ RECT 2192.430000 2893.680000 2193.230000 2894.160000 ;
+ RECT 2192.430000 2899.120000 2193.230000 2899.600000 ;
+ RECT 2192.430000 2882.800000 2193.230000 2883.280000 ;
+ RECT 2192.430000 2877.360000 2193.230000 2877.840000 ;
+ RECT 2192.430000 2871.920000 2193.230000 2872.400000 ;
+ RECT 2192.430000 2866.480000 2193.230000 2866.960000 ;
+ RECT 2192.430000 2861.040000 2193.230000 2861.520000 ;
+ RECT 2192.430000 2855.600000 2193.230000 2856.080000 ;
+ RECT 2192.430000 2850.160000 2193.230000 2850.640000 ;
+ RECT 2192.430000 2844.720000 2193.230000 2845.200000 ;
+ RECT 2192.430000 2839.280000 2193.230000 2839.760000 ;
+ RECT 2192.430000 2833.840000 2193.230000 2834.320000 ;
+ RECT 2192.430000 2828.400000 2193.230000 2828.880000 ;
+ RECT 2192.430000 2822.960000 2193.230000 2823.440000 ;
+ RECT 2192.430000 2817.520000 2193.230000 2818.000000 ;
+ RECT 2192.430000 2812.080000 2193.230000 2812.560000 ;
+ RECT 2192.430000 2806.640000 2193.230000 2807.120000 ;
+ RECT 2192.430000 2801.200000 2193.230000 2801.680000 ;
+ RECT 2192.430000 2795.760000 2193.230000 2796.240000 ;
+ RECT 2192.430000 2790.320000 2193.230000 2790.800000 ;
+ RECT 2192.430000 2784.880000 2193.230000 2785.360000 ;
+ RECT 2192.430000 2779.440000 2193.230000 2779.920000 ;
+ RECT 2192.430000 2774.000000 2193.230000 2774.480000 ;
+ RECT 2718.690000 2768.560000 2719.490000 2769.040000 ;
+ RECT 2718.690000 2763.120000 2719.490000 2763.600000 ;
+ RECT 2718.690000 2757.680000 2719.490000 2758.160000 ;
+ RECT 2718.690000 2752.240000 2719.490000 2752.720000 ;
+ RECT 2718.690000 2746.800000 2719.490000 2747.280000 ;
+ RECT 2718.690000 2741.360000 2719.490000 2741.840000 ;
+ RECT 2718.690000 2735.920000 2719.490000 2736.400000 ;
+ RECT 2718.690000 2730.480000 2719.490000 2730.960000 ;
+ RECT 2718.690000 2725.040000 2719.490000 2725.520000 ;
+ RECT 2718.690000 2719.600000 2719.490000 2720.080000 ;
+ RECT 2718.690000 2714.160000 2719.490000 2714.640000 ;
+ RECT 2718.690000 2708.720000 2719.490000 2709.200000 ;
+ RECT 2718.690000 2692.400000 2719.490000 2692.880000 ;
+ RECT 2718.690000 2697.840000 2719.490000 2698.320000 ;
+ RECT 2718.690000 2681.520000 2719.490000 2682.000000 ;
+ RECT 2718.690000 2676.080000 2719.490000 2676.560000 ;
+ RECT 2718.690000 2670.640000 2719.490000 2671.120000 ;
+ RECT 2718.690000 2686.960000 2719.490000 2687.440000 ;
+ RECT 2718.690000 2665.200000 2719.490000 2665.680000 ;
+ RECT 2718.690000 2659.760000 2719.490000 2660.240000 ;
+ RECT 2718.690000 2654.320000 2719.490000 2654.800000 ;
+ RECT 2718.690000 2648.880000 2719.490000 2649.360000 ;
+ RECT 2718.690000 2643.440000 2719.490000 2643.920000 ;
+ RECT 2718.690000 2638.000000 2719.490000 2638.480000 ;
+ RECT 2718.690000 2703.280000 2719.490000 2703.760000 ;
+ RECT 2718.690000 2632.560000 2719.490000 2633.040000 ;
+ RECT 2718.690000 2627.120000 2719.490000 2627.600000 ;
+ RECT 2718.690000 2621.680000 2719.490000 2622.160000 ;
+ RECT 2718.690000 2616.240000 2719.490000 2616.720000 ;
+ RECT 2718.690000 2610.800000 2719.490000 2611.280000 ;
+ RECT 2718.690000 2605.360000 2719.490000 2605.840000 ;
+ RECT 2718.690000 2599.920000 2719.490000 2600.400000 ;
+ RECT 2718.690000 2594.480000 2719.490000 2594.960000 ;
+ RECT 2718.690000 2589.040000 2719.490000 2589.520000 ;
+ RECT 2718.690000 2583.600000 2719.490000 2584.080000 ;
+ RECT 2718.690000 2578.160000 2719.490000 2578.640000 ;
+ RECT 2718.690000 2572.720000 2719.490000 2573.200000 ;
+ RECT 2718.690000 2567.280000 2719.490000 2567.760000 ;
+ RECT 2192.430000 2763.120000 2193.230000 2763.600000 ;
+ RECT 2192.430000 2757.680000 2193.230000 2758.160000 ;
+ RECT 2192.430000 2768.560000 2193.230000 2769.040000 ;
+ RECT 2192.430000 2752.240000 2193.230000 2752.720000 ;
+ RECT 2192.430000 2746.800000 2193.230000 2747.280000 ;
+ RECT 2192.430000 2741.360000 2193.230000 2741.840000 ;
+ RECT 2192.430000 2735.920000 2193.230000 2736.400000 ;
+ RECT 2192.430000 2730.480000 2193.230000 2730.960000 ;
+ RECT 2192.430000 2725.040000 2193.230000 2725.520000 ;
+ RECT 2192.430000 2719.600000 2193.230000 2720.080000 ;
+ RECT 2192.430000 2714.160000 2193.230000 2714.640000 ;
+ RECT 2192.430000 2708.720000 2193.230000 2709.200000 ;
+ RECT 2192.430000 2692.400000 2193.230000 2692.880000 ;
+ RECT 2192.430000 2697.840000 2193.230000 2698.320000 ;
+ RECT 2192.430000 2681.520000 2193.230000 2682.000000 ;
+ RECT 2192.430000 2676.080000 2193.230000 2676.560000 ;
+ RECT 2192.430000 2670.640000 2193.230000 2671.120000 ;
+ RECT 2192.430000 2686.960000 2193.230000 2687.440000 ;
+ RECT 2192.430000 2659.760000 2193.230000 2660.240000 ;
+ RECT 2192.430000 2654.320000 2193.230000 2654.800000 ;
+ RECT 2192.430000 2665.200000 2193.230000 2665.680000 ;
+ RECT 2192.430000 2648.880000 2193.230000 2649.360000 ;
+ RECT 2192.430000 2643.440000 2193.230000 2643.920000 ;
+ RECT 2192.430000 2638.000000 2193.230000 2638.480000 ;
+ RECT 2192.430000 2703.280000 2193.230000 2703.760000 ;
+ RECT 2192.430000 2632.560000 2193.230000 2633.040000 ;
+ RECT 2192.430000 2627.120000 2193.230000 2627.600000 ;
+ RECT 2192.430000 2621.680000 2193.230000 2622.160000 ;
+ RECT 2192.430000 2605.360000 2193.230000 2605.840000 ;
+ RECT 2192.430000 2616.240000 2193.230000 2616.720000 ;
+ RECT 2192.430000 2610.800000 2193.230000 2611.280000 ;
+ RECT 2192.430000 2599.920000 2193.230000 2600.400000 ;
+ RECT 2192.430000 2594.480000 2193.230000 2594.960000 ;
+ RECT 2192.430000 2589.040000 2193.230000 2589.520000 ;
+ RECT 2192.430000 2583.600000 2193.230000 2584.080000 ;
+ RECT 2192.430000 2578.160000 2193.230000 2578.640000 ;
+ RECT 2192.430000 2572.720000 2193.230000 2573.200000 ;
+ RECT 2192.430000 2567.280000 2193.230000 2567.760000 ;
+ RECT 2192.430000 2976.670000 2720.920000 2977.470000 ;
+ RECT 2192.430000 2561.150000 2720.920000 2561.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 2559.700000 2193.230000 2560.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 2979.140000 2193.230000 2979.940000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 2559.700000 2719.490000 2560.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 2979.140000 2719.490000 2979.940000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2561.150000 2720.920000 2561.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2976.670000 2720.920000 2977.470000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2222.420000 2993.940000 2224.160000 3388.720000 ;
+ LAYER met3 ;
+ RECT 2222.420000 3386.980000 2699.480000 3388.720000 ;
+ LAYER met3 ;
+ RECT 2222.420000 2993.940000 2699.480000 2995.680000 ;
+ LAYER met4 ;
+ RECT 2697.740000 2993.940000 2699.480000 3388.720000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 2979.940000 2193.230000 3400.180000 ;
+ RECT 2718.690000 2979.940000 2719.490000 3400.180000 ;
+ LAYER met3 ;
+ RECT 2718.690000 3390.080000 2719.490000 3390.560000 ;
+ RECT 2718.690000 3384.640000 2719.490000 3385.120000 ;
+ RECT 2718.690000 3379.200000 2719.490000 3379.680000 ;
+ RECT 2718.690000 3373.760000 2719.490000 3374.240000 ;
+ RECT 2718.690000 3368.320000 2719.490000 3368.800000 ;
+ RECT 2718.690000 3362.880000 2719.490000 3363.360000 ;
+ RECT 2718.690000 3357.440000 2719.490000 3357.920000 ;
+ RECT 2718.690000 3352.000000 2719.490000 3352.480000 ;
+ RECT 2718.690000 3346.560000 2719.490000 3347.040000 ;
+ RECT 2718.690000 3341.120000 2719.490000 3341.600000 ;
+ RECT 2718.690000 3335.680000 2719.490000 3336.160000 ;
+ RECT 2718.690000 3330.240000 2719.490000 3330.720000 ;
+ RECT 2718.690000 3324.800000 2719.490000 3325.280000 ;
+ RECT 2718.690000 3308.480000 2719.490000 3308.960000 ;
+ RECT 2718.690000 3313.920000 2719.490000 3314.400000 ;
+ RECT 2718.690000 3319.360000 2719.490000 3319.840000 ;
+ RECT 2718.690000 3303.040000 2719.490000 3303.520000 ;
+ RECT 2718.690000 3297.600000 2719.490000 3298.080000 ;
+ RECT 2718.690000 3292.160000 2719.490000 3292.640000 ;
+ RECT 2718.690000 3286.720000 2719.490000 3287.200000 ;
+ RECT 2718.690000 3281.280000 2719.490000 3281.760000 ;
+ RECT 2718.690000 3275.840000 2719.490000 3276.320000 ;
+ RECT 2718.690000 3270.400000 2719.490000 3270.880000 ;
+ RECT 2718.690000 3264.960000 2719.490000 3265.440000 ;
+ RECT 2718.690000 3259.520000 2719.490000 3260.000000 ;
+ RECT 2718.690000 3254.080000 2719.490000 3254.560000 ;
+ RECT 2718.690000 3248.640000 2719.490000 3249.120000 ;
+ RECT 2718.690000 3243.200000 2719.490000 3243.680000 ;
+ RECT 2718.690000 3237.760000 2719.490000 3238.240000 ;
+ RECT 2718.690000 3232.320000 2719.490000 3232.800000 ;
+ RECT 2718.690000 3226.880000 2719.490000 3227.360000 ;
+ RECT 2718.690000 3221.440000 2719.490000 3221.920000 ;
+ RECT 2718.690000 3216.000000 2719.490000 3216.480000 ;
+ RECT 2718.690000 3210.560000 2719.490000 3211.040000 ;
+ RECT 2718.690000 3205.120000 2719.490000 3205.600000 ;
+ RECT 2718.690000 3199.680000 2719.490000 3200.160000 ;
+ RECT 2718.690000 3194.240000 2719.490000 3194.720000 ;
+ RECT 2192.430000 3390.080000 2193.230000 3390.560000 ;
+ RECT 2192.430000 3384.640000 2193.230000 3385.120000 ;
+ RECT 2192.430000 3379.200000 2193.230000 3379.680000 ;
+ RECT 2192.430000 3373.760000 2193.230000 3374.240000 ;
+ RECT 2192.430000 3368.320000 2193.230000 3368.800000 ;
+ RECT 2192.430000 3362.880000 2193.230000 3363.360000 ;
+ RECT 2192.430000 3357.440000 2193.230000 3357.920000 ;
+ RECT 2192.430000 3352.000000 2193.230000 3352.480000 ;
+ RECT 2192.430000 3346.560000 2193.230000 3347.040000 ;
+ RECT 2192.430000 3341.120000 2193.230000 3341.600000 ;
+ RECT 2192.430000 3335.680000 2193.230000 3336.160000 ;
+ RECT 2192.430000 3330.240000 2193.230000 3330.720000 ;
+ RECT 2192.430000 3324.800000 2193.230000 3325.280000 ;
+ RECT 2192.430000 3308.480000 2193.230000 3308.960000 ;
+ RECT 2192.430000 3313.920000 2193.230000 3314.400000 ;
+ RECT 2192.430000 3319.360000 2193.230000 3319.840000 ;
+ RECT 2192.430000 3303.040000 2193.230000 3303.520000 ;
+ RECT 2192.430000 3297.600000 2193.230000 3298.080000 ;
+ RECT 2192.430000 3292.160000 2193.230000 3292.640000 ;
+ RECT 2192.430000 3286.720000 2193.230000 3287.200000 ;
+ RECT 2192.430000 3281.280000 2193.230000 3281.760000 ;
+ RECT 2192.430000 3275.840000 2193.230000 3276.320000 ;
+ RECT 2192.430000 3270.400000 2193.230000 3270.880000 ;
+ RECT 2192.430000 3264.960000 2193.230000 3265.440000 ;
+ RECT 2192.430000 3259.520000 2193.230000 3260.000000 ;
+ RECT 2192.430000 3254.080000 2193.230000 3254.560000 ;
+ RECT 2192.430000 3248.640000 2193.230000 3249.120000 ;
+ RECT 2192.430000 3243.200000 2193.230000 3243.680000 ;
+ RECT 2192.430000 3237.760000 2193.230000 3238.240000 ;
+ RECT 2192.430000 3232.320000 2193.230000 3232.800000 ;
+ RECT 2192.430000 3226.880000 2193.230000 3227.360000 ;
+ RECT 2192.430000 3221.440000 2193.230000 3221.920000 ;
+ RECT 2192.430000 3216.000000 2193.230000 3216.480000 ;
+ RECT 2192.430000 3210.560000 2193.230000 3211.040000 ;
+ RECT 2192.430000 3205.120000 2193.230000 3205.600000 ;
+ RECT 2192.430000 3199.680000 2193.230000 3200.160000 ;
+ RECT 2192.430000 3194.240000 2193.230000 3194.720000 ;
+ RECT 2718.690000 3188.800000 2719.490000 3189.280000 ;
+ RECT 2718.690000 3183.360000 2719.490000 3183.840000 ;
+ RECT 2718.690000 3177.920000 2719.490000 3178.400000 ;
+ RECT 2718.690000 3172.480000 2719.490000 3172.960000 ;
+ RECT 2718.690000 3167.040000 2719.490000 3167.520000 ;
+ RECT 2718.690000 3161.600000 2719.490000 3162.080000 ;
+ RECT 2718.690000 3156.160000 2719.490000 3156.640000 ;
+ RECT 2718.690000 3150.720000 2719.490000 3151.200000 ;
+ RECT 2718.690000 3145.280000 2719.490000 3145.760000 ;
+ RECT 2718.690000 3139.840000 2719.490000 3140.320000 ;
+ RECT 2718.690000 3134.400000 2719.490000 3134.880000 ;
+ RECT 2718.690000 3128.960000 2719.490000 3129.440000 ;
+ RECT 2718.690000 3112.640000 2719.490000 3113.120000 ;
+ RECT 2718.690000 3118.080000 2719.490000 3118.560000 ;
+ RECT 2718.690000 3101.760000 2719.490000 3102.240000 ;
+ RECT 2718.690000 3096.320000 2719.490000 3096.800000 ;
+ RECT 2718.690000 3090.880000 2719.490000 3091.360000 ;
+ RECT 2718.690000 3107.200000 2719.490000 3107.680000 ;
+ RECT 2718.690000 3085.440000 2719.490000 3085.920000 ;
+ RECT 2718.690000 3080.000000 2719.490000 3080.480000 ;
+ RECT 2718.690000 3074.560000 2719.490000 3075.040000 ;
+ RECT 2718.690000 3069.120000 2719.490000 3069.600000 ;
+ RECT 2718.690000 3063.680000 2719.490000 3064.160000 ;
+ RECT 2718.690000 3058.240000 2719.490000 3058.720000 ;
+ RECT 2718.690000 3123.520000 2719.490000 3124.000000 ;
+ RECT 2718.690000 3052.800000 2719.490000 3053.280000 ;
+ RECT 2718.690000 3047.360000 2719.490000 3047.840000 ;
+ RECT 2718.690000 3041.920000 2719.490000 3042.400000 ;
+ RECT 2718.690000 3036.480000 2719.490000 3036.960000 ;
+ RECT 2718.690000 3031.040000 2719.490000 3031.520000 ;
+ RECT 2718.690000 3025.600000 2719.490000 3026.080000 ;
+ RECT 2718.690000 3020.160000 2719.490000 3020.640000 ;
+ RECT 2718.690000 3014.720000 2719.490000 3015.200000 ;
+ RECT 2718.690000 3009.280000 2719.490000 3009.760000 ;
+ RECT 2718.690000 3003.840000 2719.490000 3004.320000 ;
+ RECT 2718.690000 2998.400000 2719.490000 2998.880000 ;
+ RECT 2718.690000 2992.960000 2719.490000 2993.440000 ;
+ RECT 2718.690000 2987.520000 2719.490000 2988.000000 ;
+ RECT 2192.430000 3183.360000 2193.230000 3183.840000 ;
+ RECT 2192.430000 3177.920000 2193.230000 3178.400000 ;
+ RECT 2192.430000 3188.800000 2193.230000 3189.280000 ;
+ RECT 2192.430000 3172.480000 2193.230000 3172.960000 ;
+ RECT 2192.430000 3167.040000 2193.230000 3167.520000 ;
+ RECT 2192.430000 3161.600000 2193.230000 3162.080000 ;
+ RECT 2192.430000 3156.160000 2193.230000 3156.640000 ;
+ RECT 2192.430000 3150.720000 2193.230000 3151.200000 ;
+ RECT 2192.430000 3145.280000 2193.230000 3145.760000 ;
+ RECT 2192.430000 3139.840000 2193.230000 3140.320000 ;
+ RECT 2192.430000 3134.400000 2193.230000 3134.880000 ;
+ RECT 2192.430000 3128.960000 2193.230000 3129.440000 ;
+ RECT 2192.430000 3112.640000 2193.230000 3113.120000 ;
+ RECT 2192.430000 3118.080000 2193.230000 3118.560000 ;
+ RECT 2192.430000 3101.760000 2193.230000 3102.240000 ;
+ RECT 2192.430000 3096.320000 2193.230000 3096.800000 ;
+ RECT 2192.430000 3090.880000 2193.230000 3091.360000 ;
+ RECT 2192.430000 3107.200000 2193.230000 3107.680000 ;
+ RECT 2192.430000 3080.000000 2193.230000 3080.480000 ;
+ RECT 2192.430000 3074.560000 2193.230000 3075.040000 ;
+ RECT 2192.430000 3085.440000 2193.230000 3085.920000 ;
+ RECT 2192.430000 3069.120000 2193.230000 3069.600000 ;
+ RECT 2192.430000 3063.680000 2193.230000 3064.160000 ;
+ RECT 2192.430000 3058.240000 2193.230000 3058.720000 ;
+ RECT 2192.430000 3123.520000 2193.230000 3124.000000 ;
+ RECT 2192.430000 3052.800000 2193.230000 3053.280000 ;
+ RECT 2192.430000 3047.360000 2193.230000 3047.840000 ;
+ RECT 2192.430000 3041.920000 2193.230000 3042.400000 ;
+ RECT 2192.430000 3025.600000 2193.230000 3026.080000 ;
+ RECT 2192.430000 3036.480000 2193.230000 3036.960000 ;
+ RECT 2192.430000 3031.040000 2193.230000 3031.520000 ;
+ RECT 2192.430000 3020.160000 2193.230000 3020.640000 ;
+ RECT 2192.430000 3014.720000 2193.230000 3015.200000 ;
+ RECT 2192.430000 3009.280000 2193.230000 3009.760000 ;
+ RECT 2192.430000 3003.840000 2193.230000 3004.320000 ;
+ RECT 2192.430000 2998.400000 2193.230000 2998.880000 ;
+ RECT 2192.430000 2992.960000 2193.230000 2993.440000 ;
+ RECT 2192.430000 2987.520000 2193.230000 2988.000000 ;
+ RECT 2192.430000 3396.910000 2720.920000 3397.710000 ;
+ RECT 2192.430000 2981.390000 2720.920000 2982.190000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 2979.940000 2193.230000 2980.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2192.430000 3399.380000 2193.230000 3400.180000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 2979.940000 2719.490000 2980.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2718.690000 3399.380000 2719.490000 3400.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2981.390000 2720.920000 2982.190000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 3396.910000 2720.920000 3397.710000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 1539.600000 166.280000 1540.080000 ;
+ RECT 165.015000 1523.280000 166.280000 1523.760000 ;
+ RECT 165.015000 1528.720000 166.280000 1529.200000 ;
+ RECT 165.015000 1534.160000 166.280000 1534.640000 ;
+ RECT 165.015000 1517.840000 166.280000 1518.320000 ;
+ RECT 165.015000 1512.400000 166.280000 1512.880000 ;
+ RECT 165.015000 1506.960000 166.280000 1507.440000 ;
+ RECT 165.015000 1501.520000 166.280000 1502.000000 ;
+ RECT 165.015000 1485.200000 166.280000 1485.680000 ;
+ RECT 165.015000 1490.640000 166.280000 1491.120000 ;
+ RECT 165.015000 1496.080000 166.280000 1496.560000 ;
+ RECT 165.015000 1479.760000 166.280000 1480.240000 ;
+ RECT 165.015000 1474.320000 166.280000 1474.800000 ;
+ RECT 165.015000 1468.880000 166.280000 1469.360000 ;
+ RECT 165.015000 1463.440000 166.280000 1463.920000 ;
+ RECT 165.015000 1458.000000 166.280000 1458.480000 ;
+ RECT 165.015000 1452.560000 166.280000 1453.040000 ;
+ RECT 165.015000 1441.680000 166.280000 1442.160000 ;
+ RECT 165.015000 1436.240000 166.280000 1436.720000 ;
+ RECT 165.015000 1430.800000 166.280000 1431.280000 ;
+ RECT 165.015000 1425.360000 166.280000 1425.840000 ;
+ RECT 165.015000 1419.920000 166.280000 1420.400000 ;
+ RECT 165.015000 1414.480000 166.280000 1414.960000 ;
+ RECT 165.015000 1398.160000 166.280000 1398.640000 ;
+ RECT 165.015000 1403.600000 166.280000 1404.080000 ;
+ RECT 165.015000 1409.040000 166.280000 1409.520000 ;
+ RECT 165.015000 1392.720000 166.280000 1393.200000 ;
+ RECT 165.015000 1387.280000 166.280000 1387.760000 ;
+ RECT 165.015000 1381.840000 166.280000 1382.320000 ;
+ RECT 165.015000 1376.400000 166.280000 1376.880000 ;
+ RECT 165.015000 1360.080000 166.280000 1360.560000 ;
+ RECT 165.015000 1365.520000 166.280000 1366.000000 ;
+ RECT 165.015000 1370.960000 166.280000 1371.440000 ;
+ RECT 165.015000 1354.640000 166.280000 1355.120000 ;
+ RECT 165.015000 1447.120000 166.280000 1447.600000 ;
+ RECT 161.350000 1347.060000 162.350000 1547.320000 ;
+ RECT 237.930000 1347.060000 238.930000 1547.320000 ;
+ RECT 165.180000 1348.310000 166.280000 1544.880000 ;
+ RECT 210.180000 1348.310000 211.280000 1544.880000 ;
+ LAYER met3 ;
+ RECT 237.930000 1539.600000 238.930000 1540.080000 ;
+ RECT 237.930000 1534.160000 238.930000 1534.640000 ;
+ RECT 237.930000 1528.720000 238.930000 1529.200000 ;
+ RECT 237.930000 1523.280000 238.930000 1523.760000 ;
+ RECT 210.180000 1539.600000 211.280000 1540.080000 ;
+ RECT 210.180000 1534.160000 211.280000 1534.640000 ;
+ RECT 210.180000 1528.720000 211.280000 1529.200000 ;
+ RECT 210.180000 1523.280000 211.280000 1523.760000 ;
+ RECT 237.930000 1512.400000 238.930000 1512.880000 ;
+ RECT 237.930000 1517.840000 238.930000 1518.320000 ;
+ RECT 237.930000 1506.960000 238.930000 1507.440000 ;
+ RECT 237.930000 1501.520000 238.930000 1502.000000 ;
+ RECT 210.180000 1517.840000 211.280000 1518.320000 ;
+ RECT 210.180000 1512.400000 211.280000 1512.880000 ;
+ RECT 210.180000 1506.960000 211.280000 1507.440000 ;
+ RECT 210.180000 1501.520000 211.280000 1502.000000 ;
+ RECT 237.930000 1490.640000 238.930000 1491.120000 ;
+ RECT 237.930000 1485.200000 238.930000 1485.680000 ;
+ RECT 237.930000 1496.080000 238.930000 1496.560000 ;
+ RECT 237.930000 1479.760000 238.930000 1480.240000 ;
+ RECT 237.930000 1474.320000 238.930000 1474.800000 ;
+ RECT 210.180000 1496.080000 211.280000 1496.560000 ;
+ RECT 210.180000 1490.640000 211.280000 1491.120000 ;
+ RECT 210.180000 1485.200000 211.280000 1485.680000 ;
+ RECT 210.180000 1479.760000 211.280000 1480.240000 ;
+ RECT 210.180000 1474.320000 211.280000 1474.800000 ;
+ RECT 237.930000 1463.440000 238.930000 1463.920000 ;
+ RECT 237.930000 1468.880000 238.930000 1469.360000 ;
+ RECT 237.930000 1458.000000 238.930000 1458.480000 ;
+ RECT 237.930000 1452.560000 238.930000 1453.040000 ;
+ RECT 210.180000 1468.880000 211.280000 1469.360000 ;
+ RECT 210.180000 1463.440000 211.280000 1463.920000 ;
+ RECT 210.180000 1452.560000 211.280000 1453.040000 ;
+ RECT 210.180000 1458.000000 211.280000 1458.480000 ;
+ RECT 161.350000 1539.600000 162.350000 1540.080000 ;
+ RECT 165.015000 1539.600000 166.280000 1540.080000 ;
+ RECT 165.015000 1523.280000 166.280000 1523.760000 ;
+ RECT 165.015000 1528.720000 166.280000 1529.200000 ;
+ RECT 165.015000 1534.160000 166.280000 1534.640000 ;
+ RECT 161.350000 1523.280000 162.350000 1523.760000 ;
+ RECT 161.350000 1528.720000 162.350000 1529.200000 ;
+ RECT 161.350000 1534.160000 162.350000 1534.640000 ;
+ RECT 165.015000 1517.840000 166.280000 1518.320000 ;
+ RECT 165.015000 1512.400000 166.280000 1512.880000 ;
+ RECT 161.350000 1517.840000 162.350000 1518.320000 ;
+ RECT 161.350000 1512.400000 162.350000 1512.880000 ;
+ RECT 165.015000 1506.960000 166.280000 1507.440000 ;
+ RECT 165.015000 1501.520000 166.280000 1502.000000 ;
+ RECT 161.350000 1506.960000 162.350000 1507.440000 ;
+ RECT 161.350000 1501.520000 162.350000 1502.000000 ;
+ RECT 165.015000 1485.200000 166.280000 1485.680000 ;
+ RECT 165.015000 1490.640000 166.280000 1491.120000 ;
+ RECT 165.015000 1496.080000 166.280000 1496.560000 ;
+ RECT 161.350000 1485.200000 162.350000 1485.680000 ;
+ RECT 161.350000 1490.640000 162.350000 1491.120000 ;
+ RECT 161.350000 1496.080000 162.350000 1496.560000 ;
+ RECT 165.015000 1479.760000 166.280000 1480.240000 ;
+ RECT 165.015000 1474.320000 166.280000 1474.800000 ;
+ RECT 161.350000 1479.760000 162.350000 1480.240000 ;
+ RECT 161.350000 1474.320000 162.350000 1474.800000 ;
+ RECT 165.015000 1468.880000 166.280000 1469.360000 ;
+ RECT 165.015000 1463.440000 166.280000 1463.920000 ;
+ RECT 161.350000 1463.440000 162.350000 1463.920000 ;
+ RECT 161.350000 1468.880000 162.350000 1469.360000 ;
+ RECT 165.015000 1458.000000 166.280000 1458.480000 ;
+ RECT 165.015000 1452.560000 166.280000 1453.040000 ;
+ RECT 161.350000 1458.000000 162.350000 1458.480000 ;
+ RECT 161.350000 1452.560000 162.350000 1453.040000 ;
+ RECT 237.930000 1436.240000 238.930000 1436.720000 ;
+ RECT 237.930000 1441.680000 238.930000 1442.160000 ;
+ RECT 237.930000 1430.800000 238.930000 1431.280000 ;
+ RECT 237.930000 1425.360000 238.930000 1425.840000 ;
+ RECT 210.180000 1441.680000 211.280000 1442.160000 ;
+ RECT 210.180000 1436.240000 211.280000 1436.720000 ;
+ RECT 210.180000 1430.800000 211.280000 1431.280000 ;
+ RECT 210.180000 1425.360000 211.280000 1425.840000 ;
+ RECT 237.930000 1414.480000 238.930000 1414.960000 ;
+ RECT 237.930000 1419.920000 238.930000 1420.400000 ;
+ RECT 237.930000 1409.040000 238.930000 1409.520000 ;
+ RECT 237.930000 1403.600000 238.930000 1404.080000 ;
+ RECT 237.930000 1398.160000 238.930000 1398.640000 ;
+ RECT 210.180000 1419.920000 211.280000 1420.400000 ;
+ RECT 210.180000 1414.480000 211.280000 1414.960000 ;
+ RECT 210.180000 1409.040000 211.280000 1409.520000 ;
+ RECT 210.180000 1398.160000 211.280000 1398.640000 ;
+ RECT 210.180000 1403.600000 211.280000 1404.080000 ;
+ RECT 237.930000 1387.280000 238.930000 1387.760000 ;
+ RECT 237.930000 1392.720000 238.930000 1393.200000 ;
+ RECT 237.930000 1381.840000 238.930000 1382.320000 ;
+ RECT 237.930000 1376.400000 238.930000 1376.880000 ;
+ RECT 210.180000 1392.720000 211.280000 1393.200000 ;
+ RECT 210.180000 1387.280000 211.280000 1387.760000 ;
+ RECT 210.180000 1381.840000 211.280000 1382.320000 ;
+ RECT 210.180000 1376.400000 211.280000 1376.880000 ;
+ RECT 237.930000 1365.520000 238.930000 1366.000000 ;
+ RECT 237.930000 1360.080000 238.930000 1360.560000 ;
+ RECT 237.930000 1370.960000 238.930000 1371.440000 ;
+ RECT 237.930000 1354.640000 238.930000 1355.120000 ;
+ RECT 210.180000 1370.960000 211.280000 1371.440000 ;
+ RECT 210.180000 1365.520000 211.280000 1366.000000 ;
+ RECT 210.180000 1360.080000 211.280000 1360.560000 ;
+ RECT 210.180000 1354.640000 211.280000 1355.120000 ;
+ RECT 165.015000 1441.680000 166.280000 1442.160000 ;
+ RECT 165.015000 1436.240000 166.280000 1436.720000 ;
+ RECT 161.350000 1441.680000 162.350000 1442.160000 ;
+ RECT 161.350000 1436.240000 162.350000 1436.720000 ;
+ RECT 165.015000 1430.800000 166.280000 1431.280000 ;
+ RECT 165.015000 1425.360000 166.280000 1425.840000 ;
+ RECT 161.350000 1425.360000 162.350000 1425.840000 ;
+ RECT 161.350000 1430.800000 162.350000 1431.280000 ;
+ RECT 165.015000 1419.920000 166.280000 1420.400000 ;
+ RECT 165.015000 1414.480000 166.280000 1414.960000 ;
+ RECT 161.350000 1419.920000 162.350000 1420.400000 ;
+ RECT 161.350000 1414.480000 162.350000 1414.960000 ;
+ RECT 165.015000 1398.160000 166.280000 1398.640000 ;
+ RECT 165.015000 1403.600000 166.280000 1404.080000 ;
+ RECT 165.015000 1409.040000 166.280000 1409.520000 ;
+ RECT 161.350000 1398.160000 162.350000 1398.640000 ;
+ RECT 161.350000 1403.600000 162.350000 1404.080000 ;
+ RECT 161.350000 1409.040000 162.350000 1409.520000 ;
+ RECT 165.015000 1392.720000 166.280000 1393.200000 ;
+ RECT 165.015000 1387.280000 166.280000 1387.760000 ;
+ RECT 161.350000 1392.720000 162.350000 1393.200000 ;
+ RECT 161.350000 1387.280000 162.350000 1387.760000 ;
+ RECT 165.015000 1381.840000 166.280000 1382.320000 ;
+ RECT 165.015000 1376.400000 166.280000 1376.880000 ;
+ RECT 161.350000 1381.840000 162.350000 1382.320000 ;
+ RECT 161.350000 1376.400000 162.350000 1376.880000 ;
+ RECT 165.015000 1360.080000 166.280000 1360.560000 ;
+ RECT 165.015000 1365.520000 166.280000 1366.000000 ;
+ RECT 165.015000 1370.960000 166.280000 1371.440000 ;
+ RECT 161.350000 1360.080000 162.350000 1360.560000 ;
+ RECT 161.350000 1365.520000 162.350000 1366.000000 ;
+ RECT 161.350000 1370.960000 162.350000 1371.440000 ;
+ RECT 161.350000 1354.640000 162.350000 1355.120000 ;
+ RECT 165.015000 1354.640000 166.280000 1355.120000 ;
+ RECT 210.180000 1447.120000 211.280000 1447.600000 ;
+ RECT 161.350000 1447.120000 162.350000 1447.600000 ;
+ RECT 165.015000 1447.120000 166.280000 1447.600000 ;
+ RECT 237.930000 1447.120000 238.930000 1447.600000 ;
+ RECT 160.120000 1543.880000 240.160000 1544.880000 ;
+ RECT 160.120000 1348.310000 240.160000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 1347.060000 162.350000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 1546.320000 162.350000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 1347.060000 238.930000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 1546.320000 238.930000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1348.310000 161.120000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1348.310000 240.160000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1543.880000 161.120000 1544.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1543.880000 240.160000 1544.880000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 1339.340000 166.280000 1339.820000 ;
+ RECT 165.015000 1323.020000 166.280000 1323.500000 ;
+ RECT 165.015000 1328.460000 166.280000 1328.940000 ;
+ RECT 165.015000 1333.900000 166.280000 1334.380000 ;
+ RECT 165.015000 1317.580000 166.280000 1318.060000 ;
+ RECT 165.015000 1312.140000 166.280000 1312.620000 ;
+ RECT 165.015000 1306.700000 166.280000 1307.180000 ;
+ RECT 165.015000 1301.260000 166.280000 1301.740000 ;
+ RECT 165.015000 1284.940000 166.280000 1285.420000 ;
+ RECT 165.015000 1290.380000 166.280000 1290.860000 ;
+ RECT 165.015000 1295.820000 166.280000 1296.300000 ;
+ RECT 165.015000 1279.500000 166.280000 1279.980000 ;
+ RECT 165.015000 1274.060000 166.280000 1274.540000 ;
+ RECT 165.015000 1268.620000 166.280000 1269.100000 ;
+ RECT 165.015000 1263.180000 166.280000 1263.660000 ;
+ RECT 165.015000 1257.740000 166.280000 1258.220000 ;
+ RECT 165.015000 1252.300000 166.280000 1252.780000 ;
+ RECT 165.015000 1241.420000 166.280000 1241.900000 ;
+ RECT 165.015000 1235.980000 166.280000 1236.460000 ;
+ RECT 165.015000 1230.540000 166.280000 1231.020000 ;
+ RECT 165.015000 1225.100000 166.280000 1225.580000 ;
+ RECT 165.015000 1219.660000 166.280000 1220.140000 ;
+ RECT 165.015000 1214.220000 166.280000 1214.700000 ;
+ RECT 165.015000 1197.900000 166.280000 1198.380000 ;
+ RECT 165.015000 1203.340000 166.280000 1203.820000 ;
+ RECT 165.015000 1208.780000 166.280000 1209.260000 ;
+ RECT 165.015000 1192.460000 166.280000 1192.940000 ;
+ RECT 165.015000 1187.020000 166.280000 1187.500000 ;
+ RECT 165.015000 1181.580000 166.280000 1182.060000 ;
+ RECT 165.015000 1176.140000 166.280000 1176.620000 ;
+ RECT 165.015000 1159.820000 166.280000 1160.300000 ;
+ RECT 165.015000 1165.260000 166.280000 1165.740000 ;
+ RECT 165.015000 1170.700000 166.280000 1171.180000 ;
+ RECT 165.015000 1154.380000 166.280000 1154.860000 ;
+ RECT 165.015000 1246.860000 166.280000 1247.340000 ;
+ RECT 161.350000 1146.800000 162.350000 1347.060000 ;
+ RECT 237.930000 1146.800000 238.930000 1347.060000 ;
+ RECT 165.180000 1148.050000 166.280000 1344.620000 ;
+ RECT 210.180000 1148.050000 211.280000 1344.620000 ;
+ LAYER met3 ;
+ RECT 237.930000 1339.340000 238.930000 1339.820000 ;
+ RECT 237.930000 1333.900000 238.930000 1334.380000 ;
+ RECT 237.930000 1328.460000 238.930000 1328.940000 ;
+ RECT 237.930000 1323.020000 238.930000 1323.500000 ;
+ RECT 210.180000 1339.340000 211.280000 1339.820000 ;
+ RECT 210.180000 1333.900000 211.280000 1334.380000 ;
+ RECT 210.180000 1328.460000 211.280000 1328.940000 ;
+ RECT 210.180000 1323.020000 211.280000 1323.500000 ;
+ RECT 237.930000 1312.140000 238.930000 1312.620000 ;
+ RECT 237.930000 1317.580000 238.930000 1318.060000 ;
+ RECT 237.930000 1306.700000 238.930000 1307.180000 ;
+ RECT 237.930000 1301.260000 238.930000 1301.740000 ;
+ RECT 210.180000 1317.580000 211.280000 1318.060000 ;
+ RECT 210.180000 1312.140000 211.280000 1312.620000 ;
+ RECT 210.180000 1306.700000 211.280000 1307.180000 ;
+ RECT 210.180000 1301.260000 211.280000 1301.740000 ;
+ RECT 237.930000 1290.380000 238.930000 1290.860000 ;
+ RECT 237.930000 1284.940000 238.930000 1285.420000 ;
+ RECT 237.930000 1295.820000 238.930000 1296.300000 ;
+ RECT 237.930000 1279.500000 238.930000 1279.980000 ;
+ RECT 237.930000 1274.060000 238.930000 1274.540000 ;
+ RECT 210.180000 1295.820000 211.280000 1296.300000 ;
+ RECT 210.180000 1290.380000 211.280000 1290.860000 ;
+ RECT 210.180000 1284.940000 211.280000 1285.420000 ;
+ RECT 210.180000 1279.500000 211.280000 1279.980000 ;
+ RECT 210.180000 1274.060000 211.280000 1274.540000 ;
+ RECT 237.930000 1263.180000 238.930000 1263.660000 ;
+ RECT 237.930000 1268.620000 238.930000 1269.100000 ;
+ RECT 237.930000 1257.740000 238.930000 1258.220000 ;
+ RECT 237.930000 1252.300000 238.930000 1252.780000 ;
+ RECT 210.180000 1268.620000 211.280000 1269.100000 ;
+ RECT 210.180000 1263.180000 211.280000 1263.660000 ;
+ RECT 210.180000 1252.300000 211.280000 1252.780000 ;
+ RECT 210.180000 1257.740000 211.280000 1258.220000 ;
+ RECT 161.350000 1339.340000 162.350000 1339.820000 ;
+ RECT 165.015000 1339.340000 166.280000 1339.820000 ;
+ RECT 165.015000 1323.020000 166.280000 1323.500000 ;
+ RECT 165.015000 1328.460000 166.280000 1328.940000 ;
+ RECT 165.015000 1333.900000 166.280000 1334.380000 ;
+ RECT 161.350000 1323.020000 162.350000 1323.500000 ;
+ RECT 161.350000 1328.460000 162.350000 1328.940000 ;
+ RECT 161.350000 1333.900000 162.350000 1334.380000 ;
+ RECT 165.015000 1317.580000 166.280000 1318.060000 ;
+ RECT 165.015000 1312.140000 166.280000 1312.620000 ;
+ RECT 161.350000 1317.580000 162.350000 1318.060000 ;
+ RECT 161.350000 1312.140000 162.350000 1312.620000 ;
+ RECT 165.015000 1306.700000 166.280000 1307.180000 ;
+ RECT 165.015000 1301.260000 166.280000 1301.740000 ;
+ RECT 161.350000 1306.700000 162.350000 1307.180000 ;
+ RECT 161.350000 1301.260000 162.350000 1301.740000 ;
+ RECT 165.015000 1284.940000 166.280000 1285.420000 ;
+ RECT 165.015000 1290.380000 166.280000 1290.860000 ;
+ RECT 165.015000 1295.820000 166.280000 1296.300000 ;
+ RECT 161.350000 1284.940000 162.350000 1285.420000 ;
+ RECT 161.350000 1290.380000 162.350000 1290.860000 ;
+ RECT 161.350000 1295.820000 162.350000 1296.300000 ;
+ RECT 165.015000 1279.500000 166.280000 1279.980000 ;
+ RECT 165.015000 1274.060000 166.280000 1274.540000 ;
+ RECT 161.350000 1279.500000 162.350000 1279.980000 ;
+ RECT 161.350000 1274.060000 162.350000 1274.540000 ;
+ RECT 165.015000 1268.620000 166.280000 1269.100000 ;
+ RECT 165.015000 1263.180000 166.280000 1263.660000 ;
+ RECT 161.350000 1263.180000 162.350000 1263.660000 ;
+ RECT 161.350000 1268.620000 162.350000 1269.100000 ;
+ RECT 165.015000 1257.740000 166.280000 1258.220000 ;
+ RECT 165.015000 1252.300000 166.280000 1252.780000 ;
+ RECT 161.350000 1257.740000 162.350000 1258.220000 ;
+ RECT 161.350000 1252.300000 162.350000 1252.780000 ;
+ RECT 237.930000 1235.980000 238.930000 1236.460000 ;
+ RECT 237.930000 1241.420000 238.930000 1241.900000 ;
+ RECT 237.930000 1230.540000 238.930000 1231.020000 ;
+ RECT 237.930000 1225.100000 238.930000 1225.580000 ;
+ RECT 210.180000 1241.420000 211.280000 1241.900000 ;
+ RECT 210.180000 1235.980000 211.280000 1236.460000 ;
+ RECT 210.180000 1230.540000 211.280000 1231.020000 ;
+ RECT 210.180000 1225.100000 211.280000 1225.580000 ;
+ RECT 237.930000 1214.220000 238.930000 1214.700000 ;
+ RECT 237.930000 1219.660000 238.930000 1220.140000 ;
+ RECT 237.930000 1208.780000 238.930000 1209.260000 ;
+ RECT 237.930000 1203.340000 238.930000 1203.820000 ;
+ RECT 237.930000 1197.900000 238.930000 1198.380000 ;
+ RECT 210.180000 1219.660000 211.280000 1220.140000 ;
+ RECT 210.180000 1214.220000 211.280000 1214.700000 ;
+ RECT 210.180000 1208.780000 211.280000 1209.260000 ;
+ RECT 210.180000 1197.900000 211.280000 1198.380000 ;
+ RECT 210.180000 1203.340000 211.280000 1203.820000 ;
+ RECT 237.930000 1187.020000 238.930000 1187.500000 ;
+ RECT 237.930000 1192.460000 238.930000 1192.940000 ;
+ RECT 237.930000 1181.580000 238.930000 1182.060000 ;
+ RECT 237.930000 1176.140000 238.930000 1176.620000 ;
+ RECT 210.180000 1192.460000 211.280000 1192.940000 ;
+ RECT 210.180000 1187.020000 211.280000 1187.500000 ;
+ RECT 210.180000 1181.580000 211.280000 1182.060000 ;
+ RECT 210.180000 1176.140000 211.280000 1176.620000 ;
+ RECT 237.930000 1165.260000 238.930000 1165.740000 ;
+ RECT 237.930000 1159.820000 238.930000 1160.300000 ;
+ RECT 237.930000 1170.700000 238.930000 1171.180000 ;
+ RECT 237.930000 1154.380000 238.930000 1154.860000 ;
+ RECT 210.180000 1170.700000 211.280000 1171.180000 ;
+ RECT 210.180000 1165.260000 211.280000 1165.740000 ;
+ RECT 210.180000 1159.820000 211.280000 1160.300000 ;
+ RECT 210.180000 1154.380000 211.280000 1154.860000 ;
+ RECT 165.015000 1241.420000 166.280000 1241.900000 ;
+ RECT 165.015000 1235.980000 166.280000 1236.460000 ;
+ RECT 161.350000 1241.420000 162.350000 1241.900000 ;
+ RECT 161.350000 1235.980000 162.350000 1236.460000 ;
+ RECT 165.015000 1230.540000 166.280000 1231.020000 ;
+ RECT 165.015000 1225.100000 166.280000 1225.580000 ;
+ RECT 161.350000 1225.100000 162.350000 1225.580000 ;
+ RECT 161.350000 1230.540000 162.350000 1231.020000 ;
+ RECT 165.015000 1219.660000 166.280000 1220.140000 ;
+ RECT 165.015000 1214.220000 166.280000 1214.700000 ;
+ RECT 161.350000 1219.660000 162.350000 1220.140000 ;
+ RECT 161.350000 1214.220000 162.350000 1214.700000 ;
+ RECT 165.015000 1197.900000 166.280000 1198.380000 ;
+ RECT 165.015000 1203.340000 166.280000 1203.820000 ;
+ RECT 165.015000 1208.780000 166.280000 1209.260000 ;
+ RECT 161.350000 1197.900000 162.350000 1198.380000 ;
+ RECT 161.350000 1203.340000 162.350000 1203.820000 ;
+ RECT 161.350000 1208.780000 162.350000 1209.260000 ;
+ RECT 165.015000 1192.460000 166.280000 1192.940000 ;
+ RECT 165.015000 1187.020000 166.280000 1187.500000 ;
+ RECT 161.350000 1192.460000 162.350000 1192.940000 ;
+ RECT 161.350000 1187.020000 162.350000 1187.500000 ;
+ RECT 165.015000 1181.580000 166.280000 1182.060000 ;
+ RECT 165.015000 1176.140000 166.280000 1176.620000 ;
+ RECT 161.350000 1181.580000 162.350000 1182.060000 ;
+ RECT 161.350000 1176.140000 162.350000 1176.620000 ;
+ RECT 165.015000 1159.820000 166.280000 1160.300000 ;
+ RECT 165.015000 1165.260000 166.280000 1165.740000 ;
+ RECT 165.015000 1170.700000 166.280000 1171.180000 ;
+ RECT 161.350000 1159.820000 162.350000 1160.300000 ;
+ RECT 161.350000 1165.260000 162.350000 1165.740000 ;
+ RECT 161.350000 1170.700000 162.350000 1171.180000 ;
+ RECT 161.350000 1154.380000 162.350000 1154.860000 ;
+ RECT 165.015000 1154.380000 166.280000 1154.860000 ;
+ RECT 210.180000 1246.860000 211.280000 1247.340000 ;
+ RECT 161.350000 1246.860000 162.350000 1247.340000 ;
+ RECT 165.015000 1246.860000 166.280000 1247.340000 ;
+ RECT 237.930000 1246.860000 238.930000 1247.340000 ;
+ RECT 160.120000 1343.620000 240.160000 1344.620000 ;
+ RECT 160.120000 1148.050000 240.160000 1149.050000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 1146.800000 162.350000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 1346.060000 162.350000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 1146.800000 238.930000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 1346.060000 238.930000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1148.050000 161.120000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1148.050000 240.160000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1343.620000 161.120000 1344.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1343.620000 240.160000 1344.620000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 1139.080000 166.280000 1139.560000 ;
+ RECT 165.015000 1122.760000 166.280000 1123.240000 ;
+ RECT 165.015000 1128.200000 166.280000 1128.680000 ;
+ RECT 165.015000 1133.640000 166.280000 1134.120000 ;
+ RECT 165.015000 1117.320000 166.280000 1117.800000 ;
+ RECT 165.015000 1111.880000 166.280000 1112.360000 ;
+ RECT 165.015000 1106.440000 166.280000 1106.920000 ;
+ RECT 165.015000 1101.000000 166.280000 1101.480000 ;
+ RECT 165.015000 1084.680000 166.280000 1085.160000 ;
+ RECT 165.015000 1090.120000 166.280000 1090.600000 ;
+ RECT 165.015000 1095.560000 166.280000 1096.040000 ;
+ RECT 165.015000 1079.240000 166.280000 1079.720000 ;
+ RECT 165.015000 1073.800000 166.280000 1074.280000 ;
+ RECT 165.015000 1068.360000 166.280000 1068.840000 ;
+ RECT 165.015000 1062.920000 166.280000 1063.400000 ;
+ RECT 165.015000 1057.480000 166.280000 1057.960000 ;
+ RECT 165.015000 1052.040000 166.280000 1052.520000 ;
+ RECT 165.015000 1041.160000 166.280000 1041.640000 ;
+ RECT 165.015000 1035.720000 166.280000 1036.200000 ;
+ RECT 165.015000 1030.280000 166.280000 1030.760000 ;
+ RECT 165.015000 1024.840000 166.280000 1025.320000 ;
+ RECT 165.015000 1019.400000 166.280000 1019.880000 ;
+ RECT 165.015000 1013.960000 166.280000 1014.440000 ;
+ RECT 165.015000 997.640000 166.280000 998.120000 ;
+ RECT 165.015000 1003.080000 166.280000 1003.560000 ;
+ RECT 165.015000 1008.520000 166.280000 1009.000000 ;
+ RECT 165.015000 992.200000 166.280000 992.680000 ;
+ RECT 165.015000 986.760000 166.280000 987.240000 ;
+ RECT 165.015000 981.320000 166.280000 981.800000 ;
+ RECT 165.015000 975.880000 166.280000 976.360000 ;
+ RECT 165.015000 959.560000 166.280000 960.040000 ;
+ RECT 165.015000 965.000000 166.280000 965.480000 ;
+ RECT 165.015000 970.440000 166.280000 970.920000 ;
+ RECT 165.015000 954.120000 166.280000 954.600000 ;
+ RECT 165.015000 1046.600000 166.280000 1047.080000 ;
+ RECT 161.350000 946.540000 162.350000 1146.800000 ;
+ RECT 237.930000 946.540000 238.930000 1146.800000 ;
+ RECT 165.180000 947.790000 166.280000 1144.360000 ;
+ RECT 210.180000 947.790000 211.280000 1144.360000 ;
+ LAYER met3 ;
+ RECT 237.930000 1139.080000 238.930000 1139.560000 ;
+ RECT 237.930000 1133.640000 238.930000 1134.120000 ;
+ RECT 237.930000 1128.200000 238.930000 1128.680000 ;
+ RECT 237.930000 1122.760000 238.930000 1123.240000 ;
+ RECT 210.180000 1139.080000 211.280000 1139.560000 ;
+ RECT 210.180000 1133.640000 211.280000 1134.120000 ;
+ RECT 210.180000 1128.200000 211.280000 1128.680000 ;
+ RECT 210.180000 1122.760000 211.280000 1123.240000 ;
+ RECT 237.930000 1111.880000 238.930000 1112.360000 ;
+ RECT 237.930000 1117.320000 238.930000 1117.800000 ;
+ RECT 237.930000 1106.440000 238.930000 1106.920000 ;
+ RECT 237.930000 1101.000000 238.930000 1101.480000 ;
+ RECT 210.180000 1117.320000 211.280000 1117.800000 ;
+ RECT 210.180000 1111.880000 211.280000 1112.360000 ;
+ RECT 210.180000 1106.440000 211.280000 1106.920000 ;
+ RECT 210.180000 1101.000000 211.280000 1101.480000 ;
+ RECT 237.930000 1090.120000 238.930000 1090.600000 ;
+ RECT 237.930000 1084.680000 238.930000 1085.160000 ;
+ RECT 237.930000 1095.560000 238.930000 1096.040000 ;
+ RECT 237.930000 1079.240000 238.930000 1079.720000 ;
+ RECT 237.930000 1073.800000 238.930000 1074.280000 ;
+ RECT 210.180000 1095.560000 211.280000 1096.040000 ;
+ RECT 210.180000 1090.120000 211.280000 1090.600000 ;
+ RECT 210.180000 1084.680000 211.280000 1085.160000 ;
+ RECT 210.180000 1079.240000 211.280000 1079.720000 ;
+ RECT 210.180000 1073.800000 211.280000 1074.280000 ;
+ RECT 237.930000 1062.920000 238.930000 1063.400000 ;
+ RECT 237.930000 1068.360000 238.930000 1068.840000 ;
+ RECT 237.930000 1057.480000 238.930000 1057.960000 ;
+ RECT 237.930000 1052.040000 238.930000 1052.520000 ;
+ RECT 210.180000 1068.360000 211.280000 1068.840000 ;
+ RECT 210.180000 1062.920000 211.280000 1063.400000 ;
+ RECT 210.180000 1052.040000 211.280000 1052.520000 ;
+ RECT 210.180000 1057.480000 211.280000 1057.960000 ;
+ RECT 161.350000 1139.080000 162.350000 1139.560000 ;
+ RECT 165.015000 1139.080000 166.280000 1139.560000 ;
+ RECT 165.015000 1122.760000 166.280000 1123.240000 ;
+ RECT 165.015000 1128.200000 166.280000 1128.680000 ;
+ RECT 165.015000 1133.640000 166.280000 1134.120000 ;
+ RECT 161.350000 1122.760000 162.350000 1123.240000 ;
+ RECT 161.350000 1128.200000 162.350000 1128.680000 ;
+ RECT 161.350000 1133.640000 162.350000 1134.120000 ;
+ RECT 165.015000 1117.320000 166.280000 1117.800000 ;
+ RECT 165.015000 1111.880000 166.280000 1112.360000 ;
+ RECT 161.350000 1117.320000 162.350000 1117.800000 ;
+ RECT 161.350000 1111.880000 162.350000 1112.360000 ;
+ RECT 165.015000 1106.440000 166.280000 1106.920000 ;
+ RECT 165.015000 1101.000000 166.280000 1101.480000 ;
+ RECT 161.350000 1106.440000 162.350000 1106.920000 ;
+ RECT 161.350000 1101.000000 162.350000 1101.480000 ;
+ RECT 165.015000 1084.680000 166.280000 1085.160000 ;
+ RECT 165.015000 1090.120000 166.280000 1090.600000 ;
+ RECT 165.015000 1095.560000 166.280000 1096.040000 ;
+ RECT 161.350000 1084.680000 162.350000 1085.160000 ;
+ RECT 161.350000 1090.120000 162.350000 1090.600000 ;
+ RECT 161.350000 1095.560000 162.350000 1096.040000 ;
+ RECT 165.015000 1079.240000 166.280000 1079.720000 ;
+ RECT 165.015000 1073.800000 166.280000 1074.280000 ;
+ RECT 161.350000 1079.240000 162.350000 1079.720000 ;
+ RECT 161.350000 1073.800000 162.350000 1074.280000 ;
+ RECT 165.015000 1068.360000 166.280000 1068.840000 ;
+ RECT 165.015000 1062.920000 166.280000 1063.400000 ;
+ RECT 161.350000 1062.920000 162.350000 1063.400000 ;
+ RECT 161.350000 1068.360000 162.350000 1068.840000 ;
+ RECT 165.015000 1057.480000 166.280000 1057.960000 ;
+ RECT 165.015000 1052.040000 166.280000 1052.520000 ;
+ RECT 161.350000 1057.480000 162.350000 1057.960000 ;
+ RECT 161.350000 1052.040000 162.350000 1052.520000 ;
+ RECT 237.930000 1035.720000 238.930000 1036.200000 ;
+ RECT 237.930000 1041.160000 238.930000 1041.640000 ;
+ RECT 237.930000 1030.280000 238.930000 1030.760000 ;
+ RECT 237.930000 1024.840000 238.930000 1025.320000 ;
+ RECT 210.180000 1041.160000 211.280000 1041.640000 ;
+ RECT 210.180000 1035.720000 211.280000 1036.200000 ;
+ RECT 210.180000 1030.280000 211.280000 1030.760000 ;
+ RECT 210.180000 1024.840000 211.280000 1025.320000 ;
+ RECT 237.930000 1013.960000 238.930000 1014.440000 ;
+ RECT 237.930000 1019.400000 238.930000 1019.880000 ;
+ RECT 237.930000 1008.520000 238.930000 1009.000000 ;
+ RECT 237.930000 1003.080000 238.930000 1003.560000 ;
+ RECT 237.930000 997.640000 238.930000 998.120000 ;
+ RECT 210.180000 1019.400000 211.280000 1019.880000 ;
+ RECT 210.180000 1013.960000 211.280000 1014.440000 ;
+ RECT 210.180000 1008.520000 211.280000 1009.000000 ;
+ RECT 210.180000 997.640000 211.280000 998.120000 ;
+ RECT 210.180000 1003.080000 211.280000 1003.560000 ;
+ RECT 237.930000 986.760000 238.930000 987.240000 ;
+ RECT 237.930000 992.200000 238.930000 992.680000 ;
+ RECT 237.930000 981.320000 238.930000 981.800000 ;
+ RECT 237.930000 975.880000 238.930000 976.360000 ;
+ RECT 210.180000 992.200000 211.280000 992.680000 ;
+ RECT 210.180000 986.760000 211.280000 987.240000 ;
+ RECT 210.180000 981.320000 211.280000 981.800000 ;
+ RECT 210.180000 975.880000 211.280000 976.360000 ;
+ RECT 237.930000 965.000000 238.930000 965.480000 ;
+ RECT 237.930000 959.560000 238.930000 960.040000 ;
+ RECT 237.930000 970.440000 238.930000 970.920000 ;
+ RECT 237.930000 954.120000 238.930000 954.600000 ;
+ RECT 210.180000 970.440000 211.280000 970.920000 ;
+ RECT 210.180000 965.000000 211.280000 965.480000 ;
+ RECT 210.180000 959.560000 211.280000 960.040000 ;
+ RECT 210.180000 954.120000 211.280000 954.600000 ;
+ RECT 165.015000 1041.160000 166.280000 1041.640000 ;
+ RECT 165.015000 1035.720000 166.280000 1036.200000 ;
+ RECT 161.350000 1041.160000 162.350000 1041.640000 ;
+ RECT 161.350000 1035.720000 162.350000 1036.200000 ;
+ RECT 165.015000 1030.280000 166.280000 1030.760000 ;
+ RECT 165.015000 1024.840000 166.280000 1025.320000 ;
+ RECT 161.350000 1024.840000 162.350000 1025.320000 ;
+ RECT 161.350000 1030.280000 162.350000 1030.760000 ;
+ RECT 165.015000 1019.400000 166.280000 1019.880000 ;
+ RECT 165.015000 1013.960000 166.280000 1014.440000 ;
+ RECT 161.350000 1019.400000 162.350000 1019.880000 ;
+ RECT 161.350000 1013.960000 162.350000 1014.440000 ;
+ RECT 165.015000 997.640000 166.280000 998.120000 ;
+ RECT 165.015000 1003.080000 166.280000 1003.560000 ;
+ RECT 165.015000 1008.520000 166.280000 1009.000000 ;
+ RECT 161.350000 997.640000 162.350000 998.120000 ;
+ RECT 161.350000 1003.080000 162.350000 1003.560000 ;
+ RECT 161.350000 1008.520000 162.350000 1009.000000 ;
+ RECT 165.015000 992.200000 166.280000 992.680000 ;
+ RECT 165.015000 986.760000 166.280000 987.240000 ;
+ RECT 161.350000 992.200000 162.350000 992.680000 ;
+ RECT 161.350000 986.760000 162.350000 987.240000 ;
+ RECT 165.015000 981.320000 166.280000 981.800000 ;
+ RECT 165.015000 975.880000 166.280000 976.360000 ;
+ RECT 161.350000 981.320000 162.350000 981.800000 ;
+ RECT 161.350000 975.880000 162.350000 976.360000 ;
+ RECT 165.015000 959.560000 166.280000 960.040000 ;
+ RECT 165.015000 965.000000 166.280000 965.480000 ;
+ RECT 165.015000 970.440000 166.280000 970.920000 ;
+ RECT 161.350000 959.560000 162.350000 960.040000 ;
+ RECT 161.350000 965.000000 162.350000 965.480000 ;
+ RECT 161.350000 970.440000 162.350000 970.920000 ;
+ RECT 161.350000 954.120000 162.350000 954.600000 ;
+ RECT 165.015000 954.120000 166.280000 954.600000 ;
+ RECT 210.180000 1046.600000 211.280000 1047.080000 ;
+ RECT 161.350000 1046.600000 162.350000 1047.080000 ;
+ RECT 165.015000 1046.600000 166.280000 1047.080000 ;
+ RECT 237.930000 1046.600000 238.930000 1047.080000 ;
+ RECT 160.120000 1143.360000 240.160000 1144.360000 ;
+ RECT 160.120000 947.790000 240.160000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 946.540000 162.350000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 1145.800000 162.350000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 946.540000 238.930000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 1145.800000 238.930000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 947.790000 161.120000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 947.790000 240.160000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1143.360000 161.120000 1144.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1143.360000 240.160000 1144.360000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 938.820000 166.280000 939.300000 ;
+ RECT 165.015000 922.500000 166.280000 922.980000 ;
+ RECT 165.015000 927.940000 166.280000 928.420000 ;
+ RECT 165.015000 933.380000 166.280000 933.860000 ;
+ RECT 165.015000 917.060000 166.280000 917.540000 ;
+ RECT 165.015000 911.620000 166.280000 912.100000 ;
+ RECT 165.015000 906.180000 166.280000 906.660000 ;
+ RECT 165.015000 900.740000 166.280000 901.220000 ;
+ RECT 165.015000 884.420000 166.280000 884.900000 ;
+ RECT 165.015000 889.860000 166.280000 890.340000 ;
+ RECT 165.015000 895.300000 166.280000 895.780000 ;
+ RECT 165.015000 878.980000 166.280000 879.460000 ;
+ RECT 165.015000 873.540000 166.280000 874.020000 ;
+ RECT 165.015000 868.100000 166.280000 868.580000 ;
+ RECT 165.015000 862.660000 166.280000 863.140000 ;
+ RECT 165.015000 857.220000 166.280000 857.700000 ;
+ RECT 165.015000 851.780000 166.280000 852.260000 ;
+ RECT 165.015000 840.900000 166.280000 841.380000 ;
+ RECT 165.015000 835.460000 166.280000 835.940000 ;
+ RECT 165.015000 830.020000 166.280000 830.500000 ;
+ RECT 165.015000 824.580000 166.280000 825.060000 ;
+ RECT 165.015000 819.140000 166.280000 819.620000 ;
+ RECT 165.015000 813.700000 166.280000 814.180000 ;
+ RECT 165.015000 797.380000 166.280000 797.860000 ;
+ RECT 165.015000 802.820000 166.280000 803.300000 ;
+ RECT 165.015000 808.260000 166.280000 808.740000 ;
+ RECT 165.015000 791.940000 166.280000 792.420000 ;
+ RECT 165.015000 786.500000 166.280000 786.980000 ;
+ RECT 165.015000 781.060000 166.280000 781.540000 ;
+ RECT 165.015000 775.620000 166.280000 776.100000 ;
+ RECT 165.015000 759.300000 166.280000 759.780000 ;
+ RECT 165.015000 764.740000 166.280000 765.220000 ;
+ RECT 165.015000 770.180000 166.280000 770.660000 ;
+ RECT 165.015000 753.860000 166.280000 754.340000 ;
+ RECT 165.015000 846.340000 166.280000 846.820000 ;
+ RECT 161.350000 746.280000 162.350000 946.540000 ;
+ RECT 237.930000 746.280000 238.930000 946.540000 ;
+ RECT 165.180000 747.530000 166.280000 944.100000 ;
+ RECT 210.180000 747.530000 211.280000 944.100000 ;
+ LAYER met3 ;
+ RECT 237.930000 938.820000 238.930000 939.300000 ;
+ RECT 237.930000 933.380000 238.930000 933.860000 ;
+ RECT 237.930000 927.940000 238.930000 928.420000 ;
+ RECT 237.930000 922.500000 238.930000 922.980000 ;
+ RECT 210.180000 938.820000 211.280000 939.300000 ;
+ RECT 210.180000 933.380000 211.280000 933.860000 ;
+ RECT 210.180000 927.940000 211.280000 928.420000 ;
+ RECT 210.180000 922.500000 211.280000 922.980000 ;
+ RECT 237.930000 911.620000 238.930000 912.100000 ;
+ RECT 237.930000 917.060000 238.930000 917.540000 ;
+ RECT 237.930000 906.180000 238.930000 906.660000 ;
+ RECT 237.930000 900.740000 238.930000 901.220000 ;
+ RECT 210.180000 917.060000 211.280000 917.540000 ;
+ RECT 210.180000 911.620000 211.280000 912.100000 ;
+ RECT 210.180000 906.180000 211.280000 906.660000 ;
+ RECT 210.180000 900.740000 211.280000 901.220000 ;
+ RECT 237.930000 889.860000 238.930000 890.340000 ;
+ RECT 237.930000 884.420000 238.930000 884.900000 ;
+ RECT 237.930000 895.300000 238.930000 895.780000 ;
+ RECT 237.930000 878.980000 238.930000 879.460000 ;
+ RECT 237.930000 873.540000 238.930000 874.020000 ;
+ RECT 210.180000 895.300000 211.280000 895.780000 ;
+ RECT 210.180000 889.860000 211.280000 890.340000 ;
+ RECT 210.180000 884.420000 211.280000 884.900000 ;
+ RECT 210.180000 878.980000 211.280000 879.460000 ;
+ RECT 210.180000 873.540000 211.280000 874.020000 ;
+ RECT 237.930000 862.660000 238.930000 863.140000 ;
+ RECT 237.930000 868.100000 238.930000 868.580000 ;
+ RECT 237.930000 857.220000 238.930000 857.700000 ;
+ RECT 237.930000 851.780000 238.930000 852.260000 ;
+ RECT 210.180000 868.100000 211.280000 868.580000 ;
+ RECT 210.180000 862.660000 211.280000 863.140000 ;
+ RECT 210.180000 851.780000 211.280000 852.260000 ;
+ RECT 210.180000 857.220000 211.280000 857.700000 ;
+ RECT 161.350000 938.820000 162.350000 939.300000 ;
+ RECT 165.015000 938.820000 166.280000 939.300000 ;
+ RECT 165.015000 922.500000 166.280000 922.980000 ;
+ RECT 165.015000 927.940000 166.280000 928.420000 ;
+ RECT 165.015000 933.380000 166.280000 933.860000 ;
+ RECT 161.350000 922.500000 162.350000 922.980000 ;
+ RECT 161.350000 927.940000 162.350000 928.420000 ;
+ RECT 161.350000 933.380000 162.350000 933.860000 ;
+ RECT 165.015000 917.060000 166.280000 917.540000 ;
+ RECT 165.015000 911.620000 166.280000 912.100000 ;
+ RECT 161.350000 917.060000 162.350000 917.540000 ;
+ RECT 161.350000 911.620000 162.350000 912.100000 ;
+ RECT 165.015000 906.180000 166.280000 906.660000 ;
+ RECT 165.015000 900.740000 166.280000 901.220000 ;
+ RECT 161.350000 906.180000 162.350000 906.660000 ;
+ RECT 161.350000 900.740000 162.350000 901.220000 ;
+ RECT 165.015000 884.420000 166.280000 884.900000 ;
+ RECT 165.015000 889.860000 166.280000 890.340000 ;
+ RECT 165.015000 895.300000 166.280000 895.780000 ;
+ RECT 161.350000 884.420000 162.350000 884.900000 ;
+ RECT 161.350000 889.860000 162.350000 890.340000 ;
+ RECT 161.350000 895.300000 162.350000 895.780000 ;
+ RECT 165.015000 878.980000 166.280000 879.460000 ;
+ RECT 165.015000 873.540000 166.280000 874.020000 ;
+ RECT 161.350000 878.980000 162.350000 879.460000 ;
+ RECT 161.350000 873.540000 162.350000 874.020000 ;
+ RECT 165.015000 868.100000 166.280000 868.580000 ;
+ RECT 165.015000 862.660000 166.280000 863.140000 ;
+ RECT 161.350000 862.660000 162.350000 863.140000 ;
+ RECT 161.350000 868.100000 162.350000 868.580000 ;
+ RECT 165.015000 857.220000 166.280000 857.700000 ;
+ RECT 165.015000 851.780000 166.280000 852.260000 ;
+ RECT 161.350000 857.220000 162.350000 857.700000 ;
+ RECT 161.350000 851.780000 162.350000 852.260000 ;
+ RECT 237.930000 835.460000 238.930000 835.940000 ;
+ RECT 237.930000 840.900000 238.930000 841.380000 ;
+ RECT 237.930000 830.020000 238.930000 830.500000 ;
+ RECT 237.930000 824.580000 238.930000 825.060000 ;
+ RECT 210.180000 840.900000 211.280000 841.380000 ;
+ RECT 210.180000 835.460000 211.280000 835.940000 ;
+ RECT 210.180000 830.020000 211.280000 830.500000 ;
+ RECT 210.180000 824.580000 211.280000 825.060000 ;
+ RECT 237.930000 813.700000 238.930000 814.180000 ;
+ RECT 237.930000 819.140000 238.930000 819.620000 ;
+ RECT 237.930000 808.260000 238.930000 808.740000 ;
+ RECT 237.930000 802.820000 238.930000 803.300000 ;
+ RECT 237.930000 797.380000 238.930000 797.860000 ;
+ RECT 210.180000 819.140000 211.280000 819.620000 ;
+ RECT 210.180000 813.700000 211.280000 814.180000 ;
+ RECT 210.180000 808.260000 211.280000 808.740000 ;
+ RECT 210.180000 797.380000 211.280000 797.860000 ;
+ RECT 210.180000 802.820000 211.280000 803.300000 ;
+ RECT 237.930000 786.500000 238.930000 786.980000 ;
+ RECT 237.930000 791.940000 238.930000 792.420000 ;
+ RECT 237.930000 781.060000 238.930000 781.540000 ;
+ RECT 237.930000 775.620000 238.930000 776.100000 ;
+ RECT 210.180000 791.940000 211.280000 792.420000 ;
+ RECT 210.180000 786.500000 211.280000 786.980000 ;
+ RECT 210.180000 781.060000 211.280000 781.540000 ;
+ RECT 210.180000 775.620000 211.280000 776.100000 ;
+ RECT 237.930000 764.740000 238.930000 765.220000 ;
+ RECT 237.930000 759.300000 238.930000 759.780000 ;
+ RECT 237.930000 770.180000 238.930000 770.660000 ;
+ RECT 237.930000 753.860000 238.930000 754.340000 ;
+ RECT 210.180000 770.180000 211.280000 770.660000 ;
+ RECT 210.180000 764.740000 211.280000 765.220000 ;
+ RECT 210.180000 759.300000 211.280000 759.780000 ;
+ RECT 210.180000 753.860000 211.280000 754.340000 ;
+ RECT 165.015000 840.900000 166.280000 841.380000 ;
+ RECT 165.015000 835.460000 166.280000 835.940000 ;
+ RECT 161.350000 840.900000 162.350000 841.380000 ;
+ RECT 161.350000 835.460000 162.350000 835.940000 ;
+ RECT 165.015000 830.020000 166.280000 830.500000 ;
+ RECT 165.015000 824.580000 166.280000 825.060000 ;
+ RECT 161.350000 824.580000 162.350000 825.060000 ;
+ RECT 161.350000 830.020000 162.350000 830.500000 ;
+ RECT 165.015000 819.140000 166.280000 819.620000 ;
+ RECT 165.015000 813.700000 166.280000 814.180000 ;
+ RECT 161.350000 819.140000 162.350000 819.620000 ;
+ RECT 161.350000 813.700000 162.350000 814.180000 ;
+ RECT 165.015000 797.380000 166.280000 797.860000 ;
+ RECT 165.015000 802.820000 166.280000 803.300000 ;
+ RECT 165.015000 808.260000 166.280000 808.740000 ;
+ RECT 161.350000 797.380000 162.350000 797.860000 ;
+ RECT 161.350000 802.820000 162.350000 803.300000 ;
+ RECT 161.350000 808.260000 162.350000 808.740000 ;
+ RECT 165.015000 791.940000 166.280000 792.420000 ;
+ RECT 165.015000 786.500000 166.280000 786.980000 ;
+ RECT 161.350000 791.940000 162.350000 792.420000 ;
+ RECT 161.350000 786.500000 162.350000 786.980000 ;
+ RECT 165.015000 781.060000 166.280000 781.540000 ;
+ RECT 165.015000 775.620000 166.280000 776.100000 ;
+ RECT 161.350000 781.060000 162.350000 781.540000 ;
+ RECT 161.350000 775.620000 162.350000 776.100000 ;
+ RECT 165.015000 759.300000 166.280000 759.780000 ;
+ RECT 165.015000 764.740000 166.280000 765.220000 ;
+ RECT 165.015000 770.180000 166.280000 770.660000 ;
+ RECT 161.350000 759.300000 162.350000 759.780000 ;
+ RECT 161.350000 764.740000 162.350000 765.220000 ;
+ RECT 161.350000 770.180000 162.350000 770.660000 ;
+ RECT 161.350000 753.860000 162.350000 754.340000 ;
+ RECT 165.015000 753.860000 166.280000 754.340000 ;
+ RECT 210.180000 846.340000 211.280000 846.820000 ;
+ RECT 161.350000 846.340000 162.350000 846.820000 ;
+ RECT 165.015000 846.340000 166.280000 846.820000 ;
+ RECT 237.930000 846.340000 238.930000 846.820000 ;
+ RECT 160.120000 943.100000 240.160000 944.100000 ;
+ RECT 160.120000 747.530000 240.160000 748.530000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 746.280000 162.350000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 945.540000 162.350000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 746.280000 238.930000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 945.540000 238.930000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 747.530000 161.120000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 747.530000 240.160000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 943.100000 161.120000 944.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 943.100000 240.160000 944.100000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 738.560000 166.280000 739.040000 ;
+ RECT 165.015000 722.240000 166.280000 722.720000 ;
+ RECT 165.015000 727.680000 166.280000 728.160000 ;
+ RECT 165.015000 733.120000 166.280000 733.600000 ;
+ RECT 165.015000 716.800000 166.280000 717.280000 ;
+ RECT 165.015000 711.360000 166.280000 711.840000 ;
+ RECT 165.015000 705.920000 166.280000 706.400000 ;
+ RECT 165.015000 700.480000 166.280000 700.960000 ;
+ RECT 165.015000 684.160000 166.280000 684.640000 ;
+ RECT 165.015000 689.600000 166.280000 690.080000 ;
+ RECT 165.015000 695.040000 166.280000 695.520000 ;
+ RECT 165.015000 678.720000 166.280000 679.200000 ;
+ RECT 165.015000 673.280000 166.280000 673.760000 ;
+ RECT 165.015000 667.840000 166.280000 668.320000 ;
+ RECT 165.015000 662.400000 166.280000 662.880000 ;
+ RECT 165.015000 656.960000 166.280000 657.440000 ;
+ RECT 165.015000 651.520000 166.280000 652.000000 ;
+ RECT 165.015000 640.640000 166.280000 641.120000 ;
+ RECT 165.015000 635.200000 166.280000 635.680000 ;
+ RECT 165.015000 629.760000 166.280000 630.240000 ;
+ RECT 165.015000 624.320000 166.280000 624.800000 ;
+ RECT 165.015000 618.880000 166.280000 619.360000 ;
+ RECT 165.015000 613.440000 166.280000 613.920000 ;
+ RECT 165.015000 597.120000 166.280000 597.600000 ;
+ RECT 165.015000 602.560000 166.280000 603.040000 ;
+ RECT 165.015000 608.000000 166.280000 608.480000 ;
+ RECT 165.015000 591.680000 166.280000 592.160000 ;
+ RECT 165.015000 586.240000 166.280000 586.720000 ;
+ RECT 165.015000 580.800000 166.280000 581.280000 ;
+ RECT 165.015000 575.360000 166.280000 575.840000 ;
+ RECT 165.015000 559.040000 166.280000 559.520000 ;
+ RECT 165.015000 564.480000 166.280000 564.960000 ;
+ RECT 165.015000 569.920000 166.280000 570.400000 ;
+ RECT 165.015000 553.600000 166.280000 554.080000 ;
+ RECT 165.015000 646.080000 166.280000 646.560000 ;
+ RECT 161.350000 546.020000 162.350000 746.280000 ;
+ RECT 237.930000 546.020000 238.930000 746.280000 ;
+ RECT 165.180000 547.270000 166.280000 743.840000 ;
+ RECT 210.180000 547.270000 211.280000 743.840000 ;
+ LAYER met3 ;
+ RECT 237.930000 738.560000 238.930000 739.040000 ;
+ RECT 237.930000 733.120000 238.930000 733.600000 ;
+ RECT 237.930000 727.680000 238.930000 728.160000 ;
+ RECT 237.930000 722.240000 238.930000 722.720000 ;
+ RECT 210.180000 738.560000 211.280000 739.040000 ;
+ RECT 210.180000 733.120000 211.280000 733.600000 ;
+ RECT 210.180000 727.680000 211.280000 728.160000 ;
+ RECT 210.180000 722.240000 211.280000 722.720000 ;
+ RECT 237.930000 711.360000 238.930000 711.840000 ;
+ RECT 237.930000 716.800000 238.930000 717.280000 ;
+ RECT 237.930000 705.920000 238.930000 706.400000 ;
+ RECT 237.930000 700.480000 238.930000 700.960000 ;
+ RECT 210.180000 716.800000 211.280000 717.280000 ;
+ RECT 210.180000 711.360000 211.280000 711.840000 ;
+ RECT 210.180000 705.920000 211.280000 706.400000 ;
+ RECT 210.180000 700.480000 211.280000 700.960000 ;
+ RECT 237.930000 689.600000 238.930000 690.080000 ;
+ RECT 237.930000 684.160000 238.930000 684.640000 ;
+ RECT 237.930000 695.040000 238.930000 695.520000 ;
+ RECT 237.930000 678.720000 238.930000 679.200000 ;
+ RECT 237.930000 673.280000 238.930000 673.760000 ;
+ RECT 210.180000 695.040000 211.280000 695.520000 ;
+ RECT 210.180000 689.600000 211.280000 690.080000 ;
+ RECT 210.180000 684.160000 211.280000 684.640000 ;
+ RECT 210.180000 678.720000 211.280000 679.200000 ;
+ RECT 210.180000 673.280000 211.280000 673.760000 ;
+ RECT 237.930000 662.400000 238.930000 662.880000 ;
+ RECT 237.930000 667.840000 238.930000 668.320000 ;
+ RECT 237.930000 656.960000 238.930000 657.440000 ;
+ RECT 237.930000 651.520000 238.930000 652.000000 ;
+ RECT 210.180000 667.840000 211.280000 668.320000 ;
+ RECT 210.180000 662.400000 211.280000 662.880000 ;
+ RECT 210.180000 651.520000 211.280000 652.000000 ;
+ RECT 210.180000 656.960000 211.280000 657.440000 ;
+ RECT 161.350000 738.560000 162.350000 739.040000 ;
+ RECT 165.015000 738.560000 166.280000 739.040000 ;
+ RECT 165.015000 722.240000 166.280000 722.720000 ;
+ RECT 165.015000 727.680000 166.280000 728.160000 ;
+ RECT 165.015000 733.120000 166.280000 733.600000 ;
+ RECT 161.350000 722.240000 162.350000 722.720000 ;
+ RECT 161.350000 727.680000 162.350000 728.160000 ;
+ RECT 161.350000 733.120000 162.350000 733.600000 ;
+ RECT 165.015000 716.800000 166.280000 717.280000 ;
+ RECT 165.015000 711.360000 166.280000 711.840000 ;
+ RECT 161.350000 716.800000 162.350000 717.280000 ;
+ RECT 161.350000 711.360000 162.350000 711.840000 ;
+ RECT 165.015000 705.920000 166.280000 706.400000 ;
+ RECT 165.015000 700.480000 166.280000 700.960000 ;
+ RECT 161.350000 705.920000 162.350000 706.400000 ;
+ RECT 161.350000 700.480000 162.350000 700.960000 ;
+ RECT 165.015000 684.160000 166.280000 684.640000 ;
+ RECT 165.015000 689.600000 166.280000 690.080000 ;
+ RECT 165.015000 695.040000 166.280000 695.520000 ;
+ RECT 161.350000 684.160000 162.350000 684.640000 ;
+ RECT 161.350000 689.600000 162.350000 690.080000 ;
+ RECT 161.350000 695.040000 162.350000 695.520000 ;
+ RECT 165.015000 678.720000 166.280000 679.200000 ;
+ RECT 165.015000 673.280000 166.280000 673.760000 ;
+ RECT 161.350000 678.720000 162.350000 679.200000 ;
+ RECT 161.350000 673.280000 162.350000 673.760000 ;
+ RECT 165.015000 667.840000 166.280000 668.320000 ;
+ RECT 165.015000 662.400000 166.280000 662.880000 ;
+ RECT 161.350000 662.400000 162.350000 662.880000 ;
+ RECT 161.350000 667.840000 162.350000 668.320000 ;
+ RECT 165.015000 656.960000 166.280000 657.440000 ;
+ RECT 165.015000 651.520000 166.280000 652.000000 ;
+ RECT 161.350000 656.960000 162.350000 657.440000 ;
+ RECT 161.350000 651.520000 162.350000 652.000000 ;
+ RECT 237.930000 635.200000 238.930000 635.680000 ;
+ RECT 237.930000 640.640000 238.930000 641.120000 ;
+ RECT 237.930000 629.760000 238.930000 630.240000 ;
+ RECT 237.930000 624.320000 238.930000 624.800000 ;
+ RECT 210.180000 640.640000 211.280000 641.120000 ;
+ RECT 210.180000 635.200000 211.280000 635.680000 ;
+ RECT 210.180000 629.760000 211.280000 630.240000 ;
+ RECT 210.180000 624.320000 211.280000 624.800000 ;
+ RECT 237.930000 613.440000 238.930000 613.920000 ;
+ RECT 237.930000 618.880000 238.930000 619.360000 ;
+ RECT 237.930000 608.000000 238.930000 608.480000 ;
+ RECT 237.930000 602.560000 238.930000 603.040000 ;
+ RECT 237.930000 597.120000 238.930000 597.600000 ;
+ RECT 210.180000 618.880000 211.280000 619.360000 ;
+ RECT 210.180000 613.440000 211.280000 613.920000 ;
+ RECT 210.180000 608.000000 211.280000 608.480000 ;
+ RECT 210.180000 597.120000 211.280000 597.600000 ;
+ RECT 210.180000 602.560000 211.280000 603.040000 ;
+ RECT 237.930000 586.240000 238.930000 586.720000 ;
+ RECT 237.930000 591.680000 238.930000 592.160000 ;
+ RECT 237.930000 580.800000 238.930000 581.280000 ;
+ RECT 237.930000 575.360000 238.930000 575.840000 ;
+ RECT 210.180000 591.680000 211.280000 592.160000 ;
+ RECT 210.180000 586.240000 211.280000 586.720000 ;
+ RECT 210.180000 580.800000 211.280000 581.280000 ;
+ RECT 210.180000 575.360000 211.280000 575.840000 ;
+ RECT 237.930000 564.480000 238.930000 564.960000 ;
+ RECT 237.930000 559.040000 238.930000 559.520000 ;
+ RECT 237.930000 569.920000 238.930000 570.400000 ;
+ RECT 237.930000 553.600000 238.930000 554.080000 ;
+ RECT 210.180000 569.920000 211.280000 570.400000 ;
+ RECT 210.180000 564.480000 211.280000 564.960000 ;
+ RECT 210.180000 559.040000 211.280000 559.520000 ;
+ RECT 210.180000 553.600000 211.280000 554.080000 ;
+ RECT 165.015000 640.640000 166.280000 641.120000 ;
+ RECT 165.015000 635.200000 166.280000 635.680000 ;
+ RECT 161.350000 640.640000 162.350000 641.120000 ;
+ RECT 161.350000 635.200000 162.350000 635.680000 ;
+ RECT 165.015000 629.760000 166.280000 630.240000 ;
+ RECT 165.015000 624.320000 166.280000 624.800000 ;
+ RECT 161.350000 624.320000 162.350000 624.800000 ;
+ RECT 161.350000 629.760000 162.350000 630.240000 ;
+ RECT 165.015000 618.880000 166.280000 619.360000 ;
+ RECT 165.015000 613.440000 166.280000 613.920000 ;
+ RECT 161.350000 618.880000 162.350000 619.360000 ;
+ RECT 161.350000 613.440000 162.350000 613.920000 ;
+ RECT 165.015000 597.120000 166.280000 597.600000 ;
+ RECT 165.015000 602.560000 166.280000 603.040000 ;
+ RECT 165.015000 608.000000 166.280000 608.480000 ;
+ RECT 161.350000 597.120000 162.350000 597.600000 ;
+ RECT 161.350000 602.560000 162.350000 603.040000 ;
+ RECT 161.350000 608.000000 162.350000 608.480000 ;
+ RECT 165.015000 591.680000 166.280000 592.160000 ;
+ RECT 165.015000 586.240000 166.280000 586.720000 ;
+ RECT 161.350000 591.680000 162.350000 592.160000 ;
+ RECT 161.350000 586.240000 162.350000 586.720000 ;
+ RECT 165.015000 580.800000 166.280000 581.280000 ;
+ RECT 165.015000 575.360000 166.280000 575.840000 ;
+ RECT 161.350000 580.800000 162.350000 581.280000 ;
+ RECT 161.350000 575.360000 162.350000 575.840000 ;
+ RECT 165.015000 559.040000 166.280000 559.520000 ;
+ RECT 165.015000 564.480000 166.280000 564.960000 ;
+ RECT 165.015000 569.920000 166.280000 570.400000 ;
+ RECT 161.350000 559.040000 162.350000 559.520000 ;
+ RECT 161.350000 564.480000 162.350000 564.960000 ;
+ RECT 161.350000 569.920000 162.350000 570.400000 ;
+ RECT 161.350000 553.600000 162.350000 554.080000 ;
+ RECT 165.015000 553.600000 166.280000 554.080000 ;
+ RECT 210.180000 646.080000 211.280000 646.560000 ;
+ RECT 161.350000 646.080000 162.350000 646.560000 ;
+ RECT 165.015000 646.080000 166.280000 646.560000 ;
+ RECT 237.930000 646.080000 238.930000 646.560000 ;
+ RECT 160.120000 742.840000 240.160000 743.840000 ;
+ RECT 160.120000 547.270000 240.160000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 546.020000 162.350000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 745.280000 162.350000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 546.020000 238.930000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 745.280000 238.930000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 547.270000 161.120000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 547.270000 240.160000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 742.840000 161.120000 743.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 742.840000 240.160000 743.840000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 538.300000 166.280000 538.780000 ;
+ RECT 165.015000 521.980000 166.280000 522.460000 ;
+ RECT 165.015000 527.420000 166.280000 527.900000 ;
+ RECT 165.015000 532.860000 166.280000 533.340000 ;
+ RECT 165.015000 516.540000 166.280000 517.020000 ;
+ RECT 165.015000 511.100000 166.280000 511.580000 ;
+ RECT 165.015000 505.660000 166.280000 506.140000 ;
+ RECT 165.015000 500.220000 166.280000 500.700000 ;
+ RECT 165.015000 483.900000 166.280000 484.380000 ;
+ RECT 165.015000 489.340000 166.280000 489.820000 ;
+ RECT 165.015000 494.780000 166.280000 495.260000 ;
+ RECT 165.015000 478.460000 166.280000 478.940000 ;
+ RECT 165.015000 473.020000 166.280000 473.500000 ;
+ RECT 165.015000 467.580000 166.280000 468.060000 ;
+ RECT 165.015000 462.140000 166.280000 462.620000 ;
+ RECT 165.015000 456.700000 166.280000 457.180000 ;
+ RECT 165.015000 451.260000 166.280000 451.740000 ;
+ RECT 165.015000 440.380000 166.280000 440.860000 ;
+ RECT 165.015000 434.940000 166.280000 435.420000 ;
+ RECT 165.015000 429.500000 166.280000 429.980000 ;
+ RECT 165.015000 424.060000 166.280000 424.540000 ;
+ RECT 165.015000 418.620000 166.280000 419.100000 ;
+ RECT 165.015000 413.180000 166.280000 413.660000 ;
+ RECT 165.015000 396.860000 166.280000 397.340000 ;
+ RECT 165.015000 402.300000 166.280000 402.780000 ;
+ RECT 165.015000 407.740000 166.280000 408.220000 ;
+ RECT 165.015000 391.420000 166.280000 391.900000 ;
+ RECT 165.015000 385.980000 166.280000 386.460000 ;
+ RECT 165.015000 380.540000 166.280000 381.020000 ;
+ RECT 165.015000 375.100000 166.280000 375.580000 ;
+ RECT 165.015000 358.780000 166.280000 359.260000 ;
+ RECT 165.015000 364.220000 166.280000 364.700000 ;
+ RECT 165.015000 369.660000 166.280000 370.140000 ;
+ RECT 165.015000 353.340000 166.280000 353.820000 ;
+ RECT 165.015000 445.820000 166.280000 446.300000 ;
+ RECT 161.350000 345.760000 162.350000 546.020000 ;
+ RECT 237.930000 345.760000 238.930000 546.020000 ;
+ RECT 165.180000 347.010000 166.280000 543.580000 ;
+ RECT 210.180000 347.010000 211.280000 543.580000 ;
+ LAYER met3 ;
+ RECT 237.930000 538.300000 238.930000 538.780000 ;
+ RECT 237.930000 532.860000 238.930000 533.340000 ;
+ RECT 237.930000 527.420000 238.930000 527.900000 ;
+ RECT 237.930000 521.980000 238.930000 522.460000 ;
+ RECT 210.180000 538.300000 211.280000 538.780000 ;
+ RECT 210.180000 532.860000 211.280000 533.340000 ;
+ RECT 210.180000 527.420000 211.280000 527.900000 ;
+ RECT 210.180000 521.980000 211.280000 522.460000 ;
+ RECT 237.930000 511.100000 238.930000 511.580000 ;
+ RECT 237.930000 516.540000 238.930000 517.020000 ;
+ RECT 237.930000 505.660000 238.930000 506.140000 ;
+ RECT 237.930000 500.220000 238.930000 500.700000 ;
+ RECT 210.180000 516.540000 211.280000 517.020000 ;
+ RECT 210.180000 511.100000 211.280000 511.580000 ;
+ RECT 210.180000 505.660000 211.280000 506.140000 ;
+ RECT 210.180000 500.220000 211.280000 500.700000 ;
+ RECT 237.930000 489.340000 238.930000 489.820000 ;
+ RECT 237.930000 483.900000 238.930000 484.380000 ;
+ RECT 237.930000 494.780000 238.930000 495.260000 ;
+ RECT 237.930000 478.460000 238.930000 478.940000 ;
+ RECT 237.930000 473.020000 238.930000 473.500000 ;
+ RECT 210.180000 494.780000 211.280000 495.260000 ;
+ RECT 210.180000 489.340000 211.280000 489.820000 ;
+ RECT 210.180000 483.900000 211.280000 484.380000 ;
+ RECT 210.180000 478.460000 211.280000 478.940000 ;
+ RECT 210.180000 473.020000 211.280000 473.500000 ;
+ RECT 237.930000 462.140000 238.930000 462.620000 ;
+ RECT 237.930000 467.580000 238.930000 468.060000 ;
+ RECT 237.930000 456.700000 238.930000 457.180000 ;
+ RECT 237.930000 451.260000 238.930000 451.740000 ;
+ RECT 210.180000 467.580000 211.280000 468.060000 ;
+ RECT 210.180000 462.140000 211.280000 462.620000 ;
+ RECT 210.180000 451.260000 211.280000 451.740000 ;
+ RECT 210.180000 456.700000 211.280000 457.180000 ;
+ RECT 161.350000 538.300000 162.350000 538.780000 ;
+ RECT 165.015000 538.300000 166.280000 538.780000 ;
+ RECT 165.015000 521.980000 166.280000 522.460000 ;
+ RECT 165.015000 527.420000 166.280000 527.900000 ;
+ RECT 165.015000 532.860000 166.280000 533.340000 ;
+ RECT 161.350000 521.980000 162.350000 522.460000 ;
+ RECT 161.350000 527.420000 162.350000 527.900000 ;
+ RECT 161.350000 532.860000 162.350000 533.340000 ;
+ RECT 165.015000 516.540000 166.280000 517.020000 ;
+ RECT 165.015000 511.100000 166.280000 511.580000 ;
+ RECT 161.350000 516.540000 162.350000 517.020000 ;
+ RECT 161.350000 511.100000 162.350000 511.580000 ;
+ RECT 165.015000 505.660000 166.280000 506.140000 ;
+ RECT 165.015000 500.220000 166.280000 500.700000 ;
+ RECT 161.350000 505.660000 162.350000 506.140000 ;
+ RECT 161.350000 500.220000 162.350000 500.700000 ;
+ RECT 165.015000 483.900000 166.280000 484.380000 ;
+ RECT 165.015000 489.340000 166.280000 489.820000 ;
+ RECT 165.015000 494.780000 166.280000 495.260000 ;
+ RECT 161.350000 483.900000 162.350000 484.380000 ;
+ RECT 161.350000 489.340000 162.350000 489.820000 ;
+ RECT 161.350000 494.780000 162.350000 495.260000 ;
+ RECT 165.015000 478.460000 166.280000 478.940000 ;
+ RECT 165.015000 473.020000 166.280000 473.500000 ;
+ RECT 161.350000 478.460000 162.350000 478.940000 ;
+ RECT 161.350000 473.020000 162.350000 473.500000 ;
+ RECT 165.015000 467.580000 166.280000 468.060000 ;
+ RECT 165.015000 462.140000 166.280000 462.620000 ;
+ RECT 161.350000 462.140000 162.350000 462.620000 ;
+ RECT 161.350000 467.580000 162.350000 468.060000 ;
+ RECT 165.015000 456.700000 166.280000 457.180000 ;
+ RECT 165.015000 451.260000 166.280000 451.740000 ;
+ RECT 161.350000 456.700000 162.350000 457.180000 ;
+ RECT 161.350000 451.260000 162.350000 451.740000 ;
+ RECT 237.930000 434.940000 238.930000 435.420000 ;
+ RECT 237.930000 440.380000 238.930000 440.860000 ;
+ RECT 237.930000 429.500000 238.930000 429.980000 ;
+ RECT 237.930000 424.060000 238.930000 424.540000 ;
+ RECT 210.180000 440.380000 211.280000 440.860000 ;
+ RECT 210.180000 434.940000 211.280000 435.420000 ;
+ RECT 210.180000 429.500000 211.280000 429.980000 ;
+ RECT 210.180000 424.060000 211.280000 424.540000 ;
+ RECT 237.930000 413.180000 238.930000 413.660000 ;
+ RECT 237.930000 418.620000 238.930000 419.100000 ;
+ RECT 237.930000 407.740000 238.930000 408.220000 ;
+ RECT 237.930000 402.300000 238.930000 402.780000 ;
+ RECT 237.930000 396.860000 238.930000 397.340000 ;
+ RECT 210.180000 418.620000 211.280000 419.100000 ;
+ RECT 210.180000 413.180000 211.280000 413.660000 ;
+ RECT 210.180000 407.740000 211.280000 408.220000 ;
+ RECT 210.180000 396.860000 211.280000 397.340000 ;
+ RECT 210.180000 402.300000 211.280000 402.780000 ;
+ RECT 237.930000 385.980000 238.930000 386.460000 ;
+ RECT 237.930000 391.420000 238.930000 391.900000 ;
+ RECT 237.930000 380.540000 238.930000 381.020000 ;
+ RECT 237.930000 375.100000 238.930000 375.580000 ;
+ RECT 210.180000 391.420000 211.280000 391.900000 ;
+ RECT 210.180000 385.980000 211.280000 386.460000 ;
+ RECT 210.180000 380.540000 211.280000 381.020000 ;
+ RECT 210.180000 375.100000 211.280000 375.580000 ;
+ RECT 237.930000 364.220000 238.930000 364.700000 ;
+ RECT 237.930000 358.780000 238.930000 359.260000 ;
+ RECT 237.930000 369.660000 238.930000 370.140000 ;
+ RECT 237.930000 353.340000 238.930000 353.820000 ;
+ RECT 210.180000 369.660000 211.280000 370.140000 ;
+ RECT 210.180000 364.220000 211.280000 364.700000 ;
+ RECT 210.180000 358.780000 211.280000 359.260000 ;
+ RECT 210.180000 353.340000 211.280000 353.820000 ;
+ RECT 165.015000 440.380000 166.280000 440.860000 ;
+ RECT 165.015000 434.940000 166.280000 435.420000 ;
+ RECT 161.350000 440.380000 162.350000 440.860000 ;
+ RECT 161.350000 434.940000 162.350000 435.420000 ;
+ RECT 165.015000 429.500000 166.280000 429.980000 ;
+ RECT 165.015000 424.060000 166.280000 424.540000 ;
+ RECT 161.350000 424.060000 162.350000 424.540000 ;
+ RECT 161.350000 429.500000 162.350000 429.980000 ;
+ RECT 165.015000 418.620000 166.280000 419.100000 ;
+ RECT 165.015000 413.180000 166.280000 413.660000 ;
+ RECT 161.350000 418.620000 162.350000 419.100000 ;
+ RECT 161.350000 413.180000 162.350000 413.660000 ;
+ RECT 165.015000 396.860000 166.280000 397.340000 ;
+ RECT 165.015000 402.300000 166.280000 402.780000 ;
+ RECT 165.015000 407.740000 166.280000 408.220000 ;
+ RECT 161.350000 396.860000 162.350000 397.340000 ;
+ RECT 161.350000 402.300000 162.350000 402.780000 ;
+ RECT 161.350000 407.740000 162.350000 408.220000 ;
+ RECT 165.015000 391.420000 166.280000 391.900000 ;
+ RECT 165.015000 385.980000 166.280000 386.460000 ;
+ RECT 161.350000 391.420000 162.350000 391.900000 ;
+ RECT 161.350000 385.980000 162.350000 386.460000 ;
+ RECT 165.015000 380.540000 166.280000 381.020000 ;
+ RECT 165.015000 375.100000 166.280000 375.580000 ;
+ RECT 161.350000 380.540000 162.350000 381.020000 ;
+ RECT 161.350000 375.100000 162.350000 375.580000 ;
+ RECT 165.015000 358.780000 166.280000 359.260000 ;
+ RECT 165.015000 364.220000 166.280000 364.700000 ;
+ RECT 165.015000 369.660000 166.280000 370.140000 ;
+ RECT 161.350000 358.780000 162.350000 359.260000 ;
+ RECT 161.350000 364.220000 162.350000 364.700000 ;
+ RECT 161.350000 369.660000 162.350000 370.140000 ;
+ RECT 161.350000 353.340000 162.350000 353.820000 ;
+ RECT 165.015000 353.340000 166.280000 353.820000 ;
+ RECT 210.180000 445.820000 211.280000 446.300000 ;
+ RECT 161.350000 445.820000 162.350000 446.300000 ;
+ RECT 165.015000 445.820000 166.280000 446.300000 ;
+ RECT 237.930000 445.820000 238.930000 446.300000 ;
+ RECT 160.120000 542.580000 240.160000 543.580000 ;
+ RECT 160.120000 347.010000 240.160000 348.010000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 345.760000 162.350000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 545.020000 162.350000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 345.760000 238.930000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 545.020000 238.930000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 347.010000 161.120000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 347.010000 240.160000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 542.580000 161.120000 543.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 542.580000 240.160000 543.580000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 338.040000 166.280000 338.520000 ;
+ RECT 165.015000 321.720000 166.280000 322.200000 ;
+ RECT 165.015000 327.160000 166.280000 327.640000 ;
+ RECT 165.015000 332.600000 166.280000 333.080000 ;
+ RECT 165.015000 316.280000 166.280000 316.760000 ;
+ RECT 165.015000 310.840000 166.280000 311.320000 ;
+ RECT 165.015000 305.400000 166.280000 305.880000 ;
+ RECT 165.015000 299.960000 166.280000 300.440000 ;
+ RECT 165.015000 283.640000 166.280000 284.120000 ;
+ RECT 165.015000 289.080000 166.280000 289.560000 ;
+ RECT 165.015000 294.520000 166.280000 295.000000 ;
+ RECT 165.015000 278.200000 166.280000 278.680000 ;
+ RECT 165.015000 272.760000 166.280000 273.240000 ;
+ RECT 165.015000 267.320000 166.280000 267.800000 ;
+ RECT 165.015000 261.880000 166.280000 262.360000 ;
+ RECT 165.015000 256.440000 166.280000 256.920000 ;
+ RECT 165.015000 251.000000 166.280000 251.480000 ;
+ RECT 165.015000 240.120000 166.280000 240.600000 ;
+ RECT 165.015000 234.680000 166.280000 235.160000 ;
+ RECT 165.015000 229.240000 166.280000 229.720000 ;
+ RECT 165.015000 223.800000 166.280000 224.280000 ;
+ RECT 165.015000 218.360000 166.280000 218.840000 ;
+ RECT 165.015000 212.920000 166.280000 213.400000 ;
+ RECT 165.015000 196.600000 166.280000 197.080000 ;
+ RECT 165.015000 202.040000 166.280000 202.520000 ;
+ RECT 165.015000 207.480000 166.280000 207.960000 ;
+ RECT 165.015000 191.160000 166.280000 191.640000 ;
+ RECT 165.015000 185.720000 166.280000 186.200000 ;
+ RECT 165.015000 180.280000 166.280000 180.760000 ;
+ RECT 165.015000 174.840000 166.280000 175.320000 ;
+ RECT 165.015000 158.520000 166.280000 159.000000 ;
+ RECT 165.015000 163.960000 166.280000 164.440000 ;
+ RECT 165.015000 169.400000 166.280000 169.880000 ;
+ RECT 165.015000 153.080000 166.280000 153.560000 ;
+ RECT 165.015000 245.560000 166.280000 246.040000 ;
+ RECT 161.350000 145.500000 162.350000 345.760000 ;
+ RECT 237.930000 145.500000 238.930000 345.760000 ;
+ RECT 165.180000 146.750000 166.280000 343.320000 ;
+ RECT 210.180000 146.750000 211.280000 343.320000 ;
+ LAYER met3 ;
+ RECT 237.930000 338.040000 238.930000 338.520000 ;
+ RECT 237.930000 332.600000 238.930000 333.080000 ;
+ RECT 237.930000 327.160000 238.930000 327.640000 ;
+ RECT 237.930000 321.720000 238.930000 322.200000 ;
+ RECT 210.180000 338.040000 211.280000 338.520000 ;
+ RECT 210.180000 332.600000 211.280000 333.080000 ;
+ RECT 210.180000 327.160000 211.280000 327.640000 ;
+ RECT 210.180000 321.720000 211.280000 322.200000 ;
+ RECT 237.930000 310.840000 238.930000 311.320000 ;
+ RECT 237.930000 316.280000 238.930000 316.760000 ;
+ RECT 237.930000 305.400000 238.930000 305.880000 ;
+ RECT 237.930000 299.960000 238.930000 300.440000 ;
+ RECT 210.180000 316.280000 211.280000 316.760000 ;
+ RECT 210.180000 310.840000 211.280000 311.320000 ;
+ RECT 210.180000 305.400000 211.280000 305.880000 ;
+ RECT 210.180000 299.960000 211.280000 300.440000 ;
+ RECT 237.930000 289.080000 238.930000 289.560000 ;
+ RECT 237.930000 283.640000 238.930000 284.120000 ;
+ RECT 237.930000 294.520000 238.930000 295.000000 ;
+ RECT 237.930000 278.200000 238.930000 278.680000 ;
+ RECT 237.930000 272.760000 238.930000 273.240000 ;
+ RECT 210.180000 294.520000 211.280000 295.000000 ;
+ RECT 210.180000 289.080000 211.280000 289.560000 ;
+ RECT 210.180000 283.640000 211.280000 284.120000 ;
+ RECT 210.180000 278.200000 211.280000 278.680000 ;
+ RECT 210.180000 272.760000 211.280000 273.240000 ;
+ RECT 237.930000 261.880000 238.930000 262.360000 ;
+ RECT 237.930000 267.320000 238.930000 267.800000 ;
+ RECT 237.930000 256.440000 238.930000 256.920000 ;
+ RECT 237.930000 251.000000 238.930000 251.480000 ;
+ RECT 210.180000 267.320000 211.280000 267.800000 ;
+ RECT 210.180000 261.880000 211.280000 262.360000 ;
+ RECT 210.180000 251.000000 211.280000 251.480000 ;
+ RECT 210.180000 256.440000 211.280000 256.920000 ;
+ RECT 161.350000 338.040000 162.350000 338.520000 ;
+ RECT 165.015000 338.040000 166.280000 338.520000 ;
+ RECT 165.015000 321.720000 166.280000 322.200000 ;
+ RECT 165.015000 327.160000 166.280000 327.640000 ;
+ RECT 165.015000 332.600000 166.280000 333.080000 ;
+ RECT 161.350000 321.720000 162.350000 322.200000 ;
+ RECT 161.350000 327.160000 162.350000 327.640000 ;
+ RECT 161.350000 332.600000 162.350000 333.080000 ;
+ RECT 165.015000 316.280000 166.280000 316.760000 ;
+ RECT 165.015000 310.840000 166.280000 311.320000 ;
+ RECT 161.350000 316.280000 162.350000 316.760000 ;
+ RECT 161.350000 310.840000 162.350000 311.320000 ;
+ RECT 165.015000 305.400000 166.280000 305.880000 ;
+ RECT 165.015000 299.960000 166.280000 300.440000 ;
+ RECT 161.350000 305.400000 162.350000 305.880000 ;
+ RECT 161.350000 299.960000 162.350000 300.440000 ;
+ RECT 165.015000 283.640000 166.280000 284.120000 ;
+ RECT 165.015000 289.080000 166.280000 289.560000 ;
+ RECT 165.015000 294.520000 166.280000 295.000000 ;
+ RECT 161.350000 283.640000 162.350000 284.120000 ;
+ RECT 161.350000 289.080000 162.350000 289.560000 ;
+ RECT 161.350000 294.520000 162.350000 295.000000 ;
+ RECT 165.015000 278.200000 166.280000 278.680000 ;
+ RECT 165.015000 272.760000 166.280000 273.240000 ;
+ RECT 161.350000 278.200000 162.350000 278.680000 ;
+ RECT 161.350000 272.760000 162.350000 273.240000 ;
+ RECT 165.015000 267.320000 166.280000 267.800000 ;
+ RECT 165.015000 261.880000 166.280000 262.360000 ;
+ RECT 161.350000 261.880000 162.350000 262.360000 ;
+ RECT 161.350000 267.320000 162.350000 267.800000 ;
+ RECT 165.015000 256.440000 166.280000 256.920000 ;
+ RECT 165.015000 251.000000 166.280000 251.480000 ;
+ RECT 161.350000 256.440000 162.350000 256.920000 ;
+ RECT 161.350000 251.000000 162.350000 251.480000 ;
+ RECT 237.930000 234.680000 238.930000 235.160000 ;
+ RECT 237.930000 240.120000 238.930000 240.600000 ;
+ RECT 237.930000 229.240000 238.930000 229.720000 ;
+ RECT 237.930000 223.800000 238.930000 224.280000 ;
+ RECT 210.180000 240.120000 211.280000 240.600000 ;
+ RECT 210.180000 234.680000 211.280000 235.160000 ;
+ RECT 210.180000 229.240000 211.280000 229.720000 ;
+ RECT 210.180000 223.800000 211.280000 224.280000 ;
+ RECT 237.930000 212.920000 238.930000 213.400000 ;
+ RECT 237.930000 218.360000 238.930000 218.840000 ;
+ RECT 237.930000 207.480000 238.930000 207.960000 ;
+ RECT 237.930000 202.040000 238.930000 202.520000 ;
+ RECT 237.930000 196.600000 238.930000 197.080000 ;
+ RECT 210.180000 218.360000 211.280000 218.840000 ;
+ RECT 210.180000 212.920000 211.280000 213.400000 ;
+ RECT 210.180000 207.480000 211.280000 207.960000 ;
+ RECT 210.180000 196.600000 211.280000 197.080000 ;
+ RECT 210.180000 202.040000 211.280000 202.520000 ;
+ RECT 237.930000 185.720000 238.930000 186.200000 ;
+ RECT 237.930000 191.160000 238.930000 191.640000 ;
+ RECT 237.930000 180.280000 238.930000 180.760000 ;
+ RECT 237.930000 174.840000 238.930000 175.320000 ;
+ RECT 210.180000 191.160000 211.280000 191.640000 ;
+ RECT 210.180000 185.720000 211.280000 186.200000 ;
+ RECT 210.180000 180.280000 211.280000 180.760000 ;
+ RECT 210.180000 174.840000 211.280000 175.320000 ;
+ RECT 237.930000 163.960000 238.930000 164.440000 ;
+ RECT 237.930000 158.520000 238.930000 159.000000 ;
+ RECT 237.930000 169.400000 238.930000 169.880000 ;
+ RECT 237.930000 153.080000 238.930000 153.560000 ;
+ RECT 210.180000 169.400000 211.280000 169.880000 ;
+ RECT 210.180000 163.960000 211.280000 164.440000 ;
+ RECT 210.180000 158.520000 211.280000 159.000000 ;
+ RECT 210.180000 153.080000 211.280000 153.560000 ;
+ RECT 165.015000 240.120000 166.280000 240.600000 ;
+ RECT 165.015000 234.680000 166.280000 235.160000 ;
+ RECT 161.350000 240.120000 162.350000 240.600000 ;
+ RECT 161.350000 234.680000 162.350000 235.160000 ;
+ RECT 165.015000 229.240000 166.280000 229.720000 ;
+ RECT 165.015000 223.800000 166.280000 224.280000 ;
+ RECT 161.350000 223.800000 162.350000 224.280000 ;
+ RECT 161.350000 229.240000 162.350000 229.720000 ;
+ RECT 165.015000 218.360000 166.280000 218.840000 ;
+ RECT 165.015000 212.920000 166.280000 213.400000 ;
+ RECT 161.350000 218.360000 162.350000 218.840000 ;
+ RECT 161.350000 212.920000 162.350000 213.400000 ;
+ RECT 165.015000 196.600000 166.280000 197.080000 ;
+ RECT 165.015000 202.040000 166.280000 202.520000 ;
+ RECT 165.015000 207.480000 166.280000 207.960000 ;
+ RECT 161.350000 196.600000 162.350000 197.080000 ;
+ RECT 161.350000 202.040000 162.350000 202.520000 ;
+ RECT 161.350000 207.480000 162.350000 207.960000 ;
+ RECT 165.015000 191.160000 166.280000 191.640000 ;
+ RECT 165.015000 185.720000 166.280000 186.200000 ;
+ RECT 161.350000 191.160000 162.350000 191.640000 ;
+ RECT 161.350000 185.720000 162.350000 186.200000 ;
+ RECT 165.015000 180.280000 166.280000 180.760000 ;
+ RECT 165.015000 174.840000 166.280000 175.320000 ;
+ RECT 161.350000 180.280000 162.350000 180.760000 ;
+ RECT 161.350000 174.840000 162.350000 175.320000 ;
+ RECT 165.015000 158.520000 166.280000 159.000000 ;
+ RECT 165.015000 163.960000 166.280000 164.440000 ;
+ RECT 165.015000 169.400000 166.280000 169.880000 ;
+ RECT 161.350000 158.520000 162.350000 159.000000 ;
+ RECT 161.350000 163.960000 162.350000 164.440000 ;
+ RECT 161.350000 169.400000 162.350000 169.880000 ;
+ RECT 161.350000 153.080000 162.350000 153.560000 ;
+ RECT 165.015000 153.080000 166.280000 153.560000 ;
+ RECT 210.180000 245.560000 211.280000 246.040000 ;
+ RECT 161.350000 245.560000 162.350000 246.040000 ;
+ RECT 165.015000 245.560000 166.280000 246.040000 ;
+ RECT 237.930000 245.560000 238.930000 246.040000 ;
+ RECT 160.120000 342.320000 240.160000 343.320000 ;
+ RECT 160.120000 146.750000 240.160000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 145.500000 162.350000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 344.760000 162.350000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 145.500000 238.930000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 344.760000 238.930000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 146.750000 161.120000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 146.750000 240.160000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 342.320000 161.120000 343.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 342.320000 240.160000 343.320000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 3341.940000 166.280000 3342.420000 ;
+ RECT 165.015000 3325.620000 166.280000 3326.100000 ;
+ RECT 165.015000 3331.060000 166.280000 3331.540000 ;
+ RECT 165.015000 3336.500000 166.280000 3336.980000 ;
+ RECT 165.015000 3320.180000 166.280000 3320.660000 ;
+ RECT 165.015000 3314.740000 166.280000 3315.220000 ;
+ RECT 165.015000 3309.300000 166.280000 3309.780000 ;
+ RECT 165.015000 3303.860000 166.280000 3304.340000 ;
+ RECT 165.015000 3287.540000 166.280000 3288.020000 ;
+ RECT 165.015000 3292.980000 166.280000 3293.460000 ;
+ RECT 165.015000 3298.420000 166.280000 3298.900000 ;
+ RECT 165.015000 3282.100000 166.280000 3282.580000 ;
+ RECT 165.015000 3276.660000 166.280000 3277.140000 ;
+ RECT 165.015000 3271.220000 166.280000 3271.700000 ;
+ RECT 165.015000 3265.780000 166.280000 3266.260000 ;
+ RECT 165.015000 3260.340000 166.280000 3260.820000 ;
+ RECT 165.015000 3254.900000 166.280000 3255.380000 ;
+ RECT 165.015000 3244.020000 166.280000 3244.500000 ;
+ RECT 165.015000 3238.580000 166.280000 3239.060000 ;
+ RECT 165.015000 3233.140000 166.280000 3233.620000 ;
+ RECT 165.015000 3227.700000 166.280000 3228.180000 ;
+ RECT 165.015000 3222.260000 166.280000 3222.740000 ;
+ RECT 165.015000 3216.820000 166.280000 3217.300000 ;
+ RECT 165.015000 3200.500000 166.280000 3200.980000 ;
+ RECT 165.015000 3205.940000 166.280000 3206.420000 ;
+ RECT 165.015000 3211.380000 166.280000 3211.860000 ;
+ RECT 165.015000 3195.060000 166.280000 3195.540000 ;
+ RECT 165.015000 3189.620000 166.280000 3190.100000 ;
+ RECT 165.015000 3184.180000 166.280000 3184.660000 ;
+ RECT 165.015000 3178.740000 166.280000 3179.220000 ;
+ RECT 165.015000 3162.420000 166.280000 3162.900000 ;
+ RECT 165.015000 3167.860000 166.280000 3168.340000 ;
+ RECT 165.015000 3173.300000 166.280000 3173.780000 ;
+ RECT 165.015000 3156.980000 166.280000 3157.460000 ;
+ RECT 165.015000 3249.460000 166.280000 3249.940000 ;
+ RECT 161.350000 3149.400000 162.350000 3349.660000 ;
+ RECT 237.930000 3149.400000 238.930000 3349.660000 ;
+ RECT 165.180000 3150.650000 166.280000 3347.220000 ;
+ RECT 210.180000 3150.650000 211.280000 3347.220000 ;
+ LAYER met3 ;
+ RECT 237.930000 3341.940000 238.930000 3342.420000 ;
+ RECT 237.930000 3336.500000 238.930000 3336.980000 ;
+ RECT 237.930000 3331.060000 238.930000 3331.540000 ;
+ RECT 237.930000 3325.620000 238.930000 3326.100000 ;
+ RECT 210.180000 3341.940000 211.280000 3342.420000 ;
+ RECT 210.180000 3336.500000 211.280000 3336.980000 ;
+ RECT 210.180000 3331.060000 211.280000 3331.540000 ;
+ RECT 210.180000 3325.620000 211.280000 3326.100000 ;
+ RECT 237.930000 3314.740000 238.930000 3315.220000 ;
+ RECT 237.930000 3320.180000 238.930000 3320.660000 ;
+ RECT 237.930000 3309.300000 238.930000 3309.780000 ;
+ RECT 237.930000 3303.860000 238.930000 3304.340000 ;
+ RECT 210.180000 3320.180000 211.280000 3320.660000 ;
+ RECT 210.180000 3314.740000 211.280000 3315.220000 ;
+ RECT 210.180000 3309.300000 211.280000 3309.780000 ;
+ RECT 210.180000 3303.860000 211.280000 3304.340000 ;
+ RECT 237.930000 3292.980000 238.930000 3293.460000 ;
+ RECT 237.930000 3287.540000 238.930000 3288.020000 ;
+ RECT 237.930000 3298.420000 238.930000 3298.900000 ;
+ RECT 237.930000 3282.100000 238.930000 3282.580000 ;
+ RECT 237.930000 3276.660000 238.930000 3277.140000 ;
+ RECT 210.180000 3298.420000 211.280000 3298.900000 ;
+ RECT 210.180000 3292.980000 211.280000 3293.460000 ;
+ RECT 210.180000 3287.540000 211.280000 3288.020000 ;
+ RECT 210.180000 3282.100000 211.280000 3282.580000 ;
+ RECT 210.180000 3276.660000 211.280000 3277.140000 ;
+ RECT 237.930000 3265.780000 238.930000 3266.260000 ;
+ RECT 237.930000 3271.220000 238.930000 3271.700000 ;
+ RECT 237.930000 3260.340000 238.930000 3260.820000 ;
+ RECT 237.930000 3254.900000 238.930000 3255.380000 ;
+ RECT 210.180000 3271.220000 211.280000 3271.700000 ;
+ RECT 210.180000 3265.780000 211.280000 3266.260000 ;
+ RECT 210.180000 3254.900000 211.280000 3255.380000 ;
+ RECT 210.180000 3260.340000 211.280000 3260.820000 ;
+ RECT 161.350000 3341.940000 162.350000 3342.420000 ;
+ RECT 165.015000 3341.940000 166.280000 3342.420000 ;
+ RECT 165.015000 3325.620000 166.280000 3326.100000 ;
+ RECT 165.015000 3331.060000 166.280000 3331.540000 ;
+ RECT 165.015000 3336.500000 166.280000 3336.980000 ;
+ RECT 161.350000 3325.620000 162.350000 3326.100000 ;
+ RECT 161.350000 3331.060000 162.350000 3331.540000 ;
+ RECT 161.350000 3336.500000 162.350000 3336.980000 ;
+ RECT 165.015000 3320.180000 166.280000 3320.660000 ;
+ RECT 165.015000 3314.740000 166.280000 3315.220000 ;
+ RECT 161.350000 3320.180000 162.350000 3320.660000 ;
+ RECT 161.350000 3314.740000 162.350000 3315.220000 ;
+ RECT 165.015000 3309.300000 166.280000 3309.780000 ;
+ RECT 165.015000 3303.860000 166.280000 3304.340000 ;
+ RECT 161.350000 3309.300000 162.350000 3309.780000 ;
+ RECT 161.350000 3303.860000 162.350000 3304.340000 ;
+ RECT 165.015000 3287.540000 166.280000 3288.020000 ;
+ RECT 165.015000 3292.980000 166.280000 3293.460000 ;
+ RECT 165.015000 3298.420000 166.280000 3298.900000 ;
+ RECT 161.350000 3287.540000 162.350000 3288.020000 ;
+ RECT 161.350000 3292.980000 162.350000 3293.460000 ;
+ RECT 161.350000 3298.420000 162.350000 3298.900000 ;
+ RECT 165.015000 3282.100000 166.280000 3282.580000 ;
+ RECT 165.015000 3276.660000 166.280000 3277.140000 ;
+ RECT 161.350000 3282.100000 162.350000 3282.580000 ;
+ RECT 161.350000 3276.660000 162.350000 3277.140000 ;
+ RECT 165.015000 3271.220000 166.280000 3271.700000 ;
+ RECT 165.015000 3265.780000 166.280000 3266.260000 ;
+ RECT 161.350000 3265.780000 162.350000 3266.260000 ;
+ RECT 161.350000 3271.220000 162.350000 3271.700000 ;
+ RECT 165.015000 3260.340000 166.280000 3260.820000 ;
+ RECT 165.015000 3254.900000 166.280000 3255.380000 ;
+ RECT 161.350000 3260.340000 162.350000 3260.820000 ;
+ RECT 161.350000 3254.900000 162.350000 3255.380000 ;
+ RECT 237.930000 3238.580000 238.930000 3239.060000 ;
+ RECT 237.930000 3244.020000 238.930000 3244.500000 ;
+ RECT 237.930000 3233.140000 238.930000 3233.620000 ;
+ RECT 237.930000 3227.700000 238.930000 3228.180000 ;
+ RECT 210.180000 3244.020000 211.280000 3244.500000 ;
+ RECT 210.180000 3238.580000 211.280000 3239.060000 ;
+ RECT 210.180000 3233.140000 211.280000 3233.620000 ;
+ RECT 210.180000 3227.700000 211.280000 3228.180000 ;
+ RECT 237.930000 3216.820000 238.930000 3217.300000 ;
+ RECT 237.930000 3222.260000 238.930000 3222.740000 ;
+ RECT 237.930000 3211.380000 238.930000 3211.860000 ;
+ RECT 237.930000 3205.940000 238.930000 3206.420000 ;
+ RECT 237.930000 3200.500000 238.930000 3200.980000 ;
+ RECT 210.180000 3222.260000 211.280000 3222.740000 ;
+ RECT 210.180000 3216.820000 211.280000 3217.300000 ;
+ RECT 210.180000 3211.380000 211.280000 3211.860000 ;
+ RECT 210.180000 3200.500000 211.280000 3200.980000 ;
+ RECT 210.180000 3205.940000 211.280000 3206.420000 ;
+ RECT 237.930000 3189.620000 238.930000 3190.100000 ;
+ RECT 237.930000 3195.060000 238.930000 3195.540000 ;
+ RECT 237.930000 3184.180000 238.930000 3184.660000 ;
+ RECT 237.930000 3178.740000 238.930000 3179.220000 ;
+ RECT 210.180000 3195.060000 211.280000 3195.540000 ;
+ RECT 210.180000 3189.620000 211.280000 3190.100000 ;
+ RECT 210.180000 3184.180000 211.280000 3184.660000 ;
+ RECT 210.180000 3178.740000 211.280000 3179.220000 ;
+ RECT 237.930000 3167.860000 238.930000 3168.340000 ;
+ RECT 237.930000 3162.420000 238.930000 3162.900000 ;
+ RECT 237.930000 3173.300000 238.930000 3173.780000 ;
+ RECT 237.930000 3156.980000 238.930000 3157.460000 ;
+ RECT 210.180000 3173.300000 211.280000 3173.780000 ;
+ RECT 210.180000 3167.860000 211.280000 3168.340000 ;
+ RECT 210.180000 3162.420000 211.280000 3162.900000 ;
+ RECT 210.180000 3156.980000 211.280000 3157.460000 ;
+ RECT 165.015000 3244.020000 166.280000 3244.500000 ;
+ RECT 165.015000 3238.580000 166.280000 3239.060000 ;
+ RECT 161.350000 3244.020000 162.350000 3244.500000 ;
+ RECT 161.350000 3238.580000 162.350000 3239.060000 ;
+ RECT 165.015000 3233.140000 166.280000 3233.620000 ;
+ RECT 165.015000 3227.700000 166.280000 3228.180000 ;
+ RECT 161.350000 3227.700000 162.350000 3228.180000 ;
+ RECT 161.350000 3233.140000 162.350000 3233.620000 ;
+ RECT 165.015000 3222.260000 166.280000 3222.740000 ;
+ RECT 165.015000 3216.820000 166.280000 3217.300000 ;
+ RECT 161.350000 3222.260000 162.350000 3222.740000 ;
+ RECT 161.350000 3216.820000 162.350000 3217.300000 ;
+ RECT 165.015000 3200.500000 166.280000 3200.980000 ;
+ RECT 165.015000 3205.940000 166.280000 3206.420000 ;
+ RECT 165.015000 3211.380000 166.280000 3211.860000 ;
+ RECT 161.350000 3200.500000 162.350000 3200.980000 ;
+ RECT 161.350000 3205.940000 162.350000 3206.420000 ;
+ RECT 161.350000 3211.380000 162.350000 3211.860000 ;
+ RECT 165.015000 3195.060000 166.280000 3195.540000 ;
+ RECT 165.015000 3189.620000 166.280000 3190.100000 ;
+ RECT 161.350000 3195.060000 162.350000 3195.540000 ;
+ RECT 161.350000 3189.620000 162.350000 3190.100000 ;
+ RECT 165.015000 3184.180000 166.280000 3184.660000 ;
+ RECT 165.015000 3178.740000 166.280000 3179.220000 ;
+ RECT 161.350000 3184.180000 162.350000 3184.660000 ;
+ RECT 161.350000 3178.740000 162.350000 3179.220000 ;
+ RECT 165.015000 3162.420000 166.280000 3162.900000 ;
+ RECT 165.015000 3167.860000 166.280000 3168.340000 ;
+ RECT 165.015000 3173.300000 166.280000 3173.780000 ;
+ RECT 161.350000 3162.420000 162.350000 3162.900000 ;
+ RECT 161.350000 3167.860000 162.350000 3168.340000 ;
+ RECT 161.350000 3173.300000 162.350000 3173.780000 ;
+ RECT 161.350000 3156.980000 162.350000 3157.460000 ;
+ RECT 165.015000 3156.980000 166.280000 3157.460000 ;
+ RECT 210.180000 3249.460000 211.280000 3249.940000 ;
+ RECT 161.350000 3249.460000 162.350000 3249.940000 ;
+ RECT 165.015000 3249.460000 166.280000 3249.940000 ;
+ RECT 237.930000 3249.460000 238.930000 3249.940000 ;
+ RECT 160.120000 3346.220000 240.160000 3347.220000 ;
+ RECT 160.120000 3150.650000 240.160000 3151.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 3149.400000 162.350000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 3348.660000 162.350000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 3149.400000 238.930000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 3348.660000 238.930000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 3150.650000 161.120000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 3150.650000 240.160000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 3346.220000 161.120000 3347.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 3346.220000 240.160000 3347.220000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 3141.680000 166.280000 3142.160000 ;
+ RECT 165.015000 3125.360000 166.280000 3125.840000 ;
+ RECT 165.015000 3130.800000 166.280000 3131.280000 ;
+ RECT 165.015000 3136.240000 166.280000 3136.720000 ;
+ RECT 165.015000 3119.920000 166.280000 3120.400000 ;
+ RECT 165.015000 3114.480000 166.280000 3114.960000 ;
+ RECT 165.015000 3109.040000 166.280000 3109.520000 ;
+ RECT 165.015000 3103.600000 166.280000 3104.080000 ;
+ RECT 165.015000 3087.280000 166.280000 3087.760000 ;
+ RECT 165.015000 3092.720000 166.280000 3093.200000 ;
+ RECT 165.015000 3098.160000 166.280000 3098.640000 ;
+ RECT 165.015000 3081.840000 166.280000 3082.320000 ;
+ RECT 165.015000 3076.400000 166.280000 3076.880000 ;
+ RECT 165.015000 3070.960000 166.280000 3071.440000 ;
+ RECT 165.015000 3065.520000 166.280000 3066.000000 ;
+ RECT 165.015000 3060.080000 166.280000 3060.560000 ;
+ RECT 165.015000 3054.640000 166.280000 3055.120000 ;
+ RECT 165.015000 3043.760000 166.280000 3044.240000 ;
+ RECT 165.015000 3038.320000 166.280000 3038.800000 ;
+ RECT 165.015000 3032.880000 166.280000 3033.360000 ;
+ RECT 165.015000 3027.440000 166.280000 3027.920000 ;
+ RECT 165.015000 3022.000000 166.280000 3022.480000 ;
+ RECT 165.015000 3016.560000 166.280000 3017.040000 ;
+ RECT 165.015000 3000.240000 166.280000 3000.720000 ;
+ RECT 165.015000 3005.680000 166.280000 3006.160000 ;
+ RECT 165.015000 3011.120000 166.280000 3011.600000 ;
+ RECT 165.015000 2994.800000 166.280000 2995.280000 ;
+ RECT 165.015000 2989.360000 166.280000 2989.840000 ;
+ RECT 165.015000 2983.920000 166.280000 2984.400000 ;
+ RECT 165.015000 2978.480000 166.280000 2978.960000 ;
+ RECT 165.015000 2962.160000 166.280000 2962.640000 ;
+ RECT 165.015000 2967.600000 166.280000 2968.080000 ;
+ RECT 165.015000 2973.040000 166.280000 2973.520000 ;
+ RECT 165.015000 2956.720000 166.280000 2957.200000 ;
+ RECT 165.015000 3049.200000 166.280000 3049.680000 ;
+ RECT 161.350000 2949.140000 162.350000 3149.400000 ;
+ RECT 237.930000 2949.140000 238.930000 3149.400000 ;
+ RECT 165.180000 2950.390000 166.280000 3146.960000 ;
+ RECT 210.180000 2950.390000 211.280000 3146.960000 ;
+ LAYER met3 ;
+ RECT 237.930000 3141.680000 238.930000 3142.160000 ;
+ RECT 237.930000 3136.240000 238.930000 3136.720000 ;
+ RECT 237.930000 3130.800000 238.930000 3131.280000 ;
+ RECT 237.930000 3125.360000 238.930000 3125.840000 ;
+ RECT 210.180000 3141.680000 211.280000 3142.160000 ;
+ RECT 210.180000 3136.240000 211.280000 3136.720000 ;
+ RECT 210.180000 3130.800000 211.280000 3131.280000 ;
+ RECT 210.180000 3125.360000 211.280000 3125.840000 ;
+ RECT 237.930000 3114.480000 238.930000 3114.960000 ;
+ RECT 237.930000 3119.920000 238.930000 3120.400000 ;
+ RECT 237.930000 3109.040000 238.930000 3109.520000 ;
+ RECT 237.930000 3103.600000 238.930000 3104.080000 ;
+ RECT 210.180000 3119.920000 211.280000 3120.400000 ;
+ RECT 210.180000 3114.480000 211.280000 3114.960000 ;
+ RECT 210.180000 3109.040000 211.280000 3109.520000 ;
+ RECT 210.180000 3103.600000 211.280000 3104.080000 ;
+ RECT 237.930000 3092.720000 238.930000 3093.200000 ;
+ RECT 237.930000 3087.280000 238.930000 3087.760000 ;
+ RECT 237.930000 3098.160000 238.930000 3098.640000 ;
+ RECT 237.930000 3081.840000 238.930000 3082.320000 ;
+ RECT 237.930000 3076.400000 238.930000 3076.880000 ;
+ RECT 210.180000 3098.160000 211.280000 3098.640000 ;
+ RECT 210.180000 3092.720000 211.280000 3093.200000 ;
+ RECT 210.180000 3087.280000 211.280000 3087.760000 ;
+ RECT 210.180000 3081.840000 211.280000 3082.320000 ;
+ RECT 210.180000 3076.400000 211.280000 3076.880000 ;
+ RECT 237.930000 3065.520000 238.930000 3066.000000 ;
+ RECT 237.930000 3070.960000 238.930000 3071.440000 ;
+ RECT 237.930000 3060.080000 238.930000 3060.560000 ;
+ RECT 237.930000 3054.640000 238.930000 3055.120000 ;
+ RECT 210.180000 3070.960000 211.280000 3071.440000 ;
+ RECT 210.180000 3065.520000 211.280000 3066.000000 ;
+ RECT 210.180000 3054.640000 211.280000 3055.120000 ;
+ RECT 210.180000 3060.080000 211.280000 3060.560000 ;
+ RECT 161.350000 3141.680000 162.350000 3142.160000 ;
+ RECT 165.015000 3141.680000 166.280000 3142.160000 ;
+ RECT 165.015000 3125.360000 166.280000 3125.840000 ;
+ RECT 165.015000 3130.800000 166.280000 3131.280000 ;
+ RECT 165.015000 3136.240000 166.280000 3136.720000 ;
+ RECT 161.350000 3125.360000 162.350000 3125.840000 ;
+ RECT 161.350000 3130.800000 162.350000 3131.280000 ;
+ RECT 161.350000 3136.240000 162.350000 3136.720000 ;
+ RECT 165.015000 3119.920000 166.280000 3120.400000 ;
+ RECT 165.015000 3114.480000 166.280000 3114.960000 ;
+ RECT 161.350000 3119.920000 162.350000 3120.400000 ;
+ RECT 161.350000 3114.480000 162.350000 3114.960000 ;
+ RECT 165.015000 3109.040000 166.280000 3109.520000 ;
+ RECT 165.015000 3103.600000 166.280000 3104.080000 ;
+ RECT 161.350000 3109.040000 162.350000 3109.520000 ;
+ RECT 161.350000 3103.600000 162.350000 3104.080000 ;
+ RECT 165.015000 3087.280000 166.280000 3087.760000 ;
+ RECT 165.015000 3092.720000 166.280000 3093.200000 ;
+ RECT 165.015000 3098.160000 166.280000 3098.640000 ;
+ RECT 161.350000 3087.280000 162.350000 3087.760000 ;
+ RECT 161.350000 3092.720000 162.350000 3093.200000 ;
+ RECT 161.350000 3098.160000 162.350000 3098.640000 ;
+ RECT 165.015000 3081.840000 166.280000 3082.320000 ;
+ RECT 165.015000 3076.400000 166.280000 3076.880000 ;
+ RECT 161.350000 3081.840000 162.350000 3082.320000 ;
+ RECT 161.350000 3076.400000 162.350000 3076.880000 ;
+ RECT 165.015000 3070.960000 166.280000 3071.440000 ;
+ RECT 165.015000 3065.520000 166.280000 3066.000000 ;
+ RECT 161.350000 3065.520000 162.350000 3066.000000 ;
+ RECT 161.350000 3070.960000 162.350000 3071.440000 ;
+ RECT 165.015000 3060.080000 166.280000 3060.560000 ;
+ RECT 165.015000 3054.640000 166.280000 3055.120000 ;
+ RECT 161.350000 3060.080000 162.350000 3060.560000 ;
+ RECT 161.350000 3054.640000 162.350000 3055.120000 ;
+ RECT 237.930000 3038.320000 238.930000 3038.800000 ;
+ RECT 237.930000 3043.760000 238.930000 3044.240000 ;
+ RECT 237.930000 3032.880000 238.930000 3033.360000 ;
+ RECT 237.930000 3027.440000 238.930000 3027.920000 ;
+ RECT 210.180000 3043.760000 211.280000 3044.240000 ;
+ RECT 210.180000 3038.320000 211.280000 3038.800000 ;
+ RECT 210.180000 3032.880000 211.280000 3033.360000 ;
+ RECT 210.180000 3027.440000 211.280000 3027.920000 ;
+ RECT 237.930000 3016.560000 238.930000 3017.040000 ;
+ RECT 237.930000 3022.000000 238.930000 3022.480000 ;
+ RECT 237.930000 3011.120000 238.930000 3011.600000 ;
+ RECT 237.930000 3005.680000 238.930000 3006.160000 ;
+ RECT 237.930000 3000.240000 238.930000 3000.720000 ;
+ RECT 210.180000 3022.000000 211.280000 3022.480000 ;
+ RECT 210.180000 3016.560000 211.280000 3017.040000 ;
+ RECT 210.180000 3011.120000 211.280000 3011.600000 ;
+ RECT 210.180000 3000.240000 211.280000 3000.720000 ;
+ RECT 210.180000 3005.680000 211.280000 3006.160000 ;
+ RECT 237.930000 2989.360000 238.930000 2989.840000 ;
+ RECT 237.930000 2994.800000 238.930000 2995.280000 ;
+ RECT 237.930000 2983.920000 238.930000 2984.400000 ;
+ RECT 237.930000 2978.480000 238.930000 2978.960000 ;
+ RECT 210.180000 2994.800000 211.280000 2995.280000 ;
+ RECT 210.180000 2989.360000 211.280000 2989.840000 ;
+ RECT 210.180000 2983.920000 211.280000 2984.400000 ;
+ RECT 210.180000 2978.480000 211.280000 2978.960000 ;
+ RECT 237.930000 2967.600000 238.930000 2968.080000 ;
+ RECT 237.930000 2962.160000 238.930000 2962.640000 ;
+ RECT 237.930000 2973.040000 238.930000 2973.520000 ;
+ RECT 237.930000 2956.720000 238.930000 2957.200000 ;
+ RECT 210.180000 2973.040000 211.280000 2973.520000 ;
+ RECT 210.180000 2967.600000 211.280000 2968.080000 ;
+ RECT 210.180000 2962.160000 211.280000 2962.640000 ;
+ RECT 210.180000 2956.720000 211.280000 2957.200000 ;
+ RECT 165.015000 3043.760000 166.280000 3044.240000 ;
+ RECT 165.015000 3038.320000 166.280000 3038.800000 ;
+ RECT 161.350000 3043.760000 162.350000 3044.240000 ;
+ RECT 161.350000 3038.320000 162.350000 3038.800000 ;
+ RECT 165.015000 3032.880000 166.280000 3033.360000 ;
+ RECT 165.015000 3027.440000 166.280000 3027.920000 ;
+ RECT 161.350000 3027.440000 162.350000 3027.920000 ;
+ RECT 161.350000 3032.880000 162.350000 3033.360000 ;
+ RECT 165.015000 3022.000000 166.280000 3022.480000 ;
+ RECT 165.015000 3016.560000 166.280000 3017.040000 ;
+ RECT 161.350000 3022.000000 162.350000 3022.480000 ;
+ RECT 161.350000 3016.560000 162.350000 3017.040000 ;
+ RECT 165.015000 3000.240000 166.280000 3000.720000 ;
+ RECT 165.015000 3005.680000 166.280000 3006.160000 ;
+ RECT 165.015000 3011.120000 166.280000 3011.600000 ;
+ RECT 161.350000 3000.240000 162.350000 3000.720000 ;
+ RECT 161.350000 3005.680000 162.350000 3006.160000 ;
+ RECT 161.350000 3011.120000 162.350000 3011.600000 ;
+ RECT 165.015000 2994.800000 166.280000 2995.280000 ;
+ RECT 165.015000 2989.360000 166.280000 2989.840000 ;
+ RECT 161.350000 2994.800000 162.350000 2995.280000 ;
+ RECT 161.350000 2989.360000 162.350000 2989.840000 ;
+ RECT 165.015000 2983.920000 166.280000 2984.400000 ;
+ RECT 165.015000 2978.480000 166.280000 2978.960000 ;
+ RECT 161.350000 2983.920000 162.350000 2984.400000 ;
+ RECT 161.350000 2978.480000 162.350000 2978.960000 ;
+ RECT 165.015000 2962.160000 166.280000 2962.640000 ;
+ RECT 165.015000 2967.600000 166.280000 2968.080000 ;
+ RECT 165.015000 2973.040000 166.280000 2973.520000 ;
+ RECT 161.350000 2962.160000 162.350000 2962.640000 ;
+ RECT 161.350000 2967.600000 162.350000 2968.080000 ;
+ RECT 161.350000 2973.040000 162.350000 2973.520000 ;
+ RECT 161.350000 2956.720000 162.350000 2957.200000 ;
+ RECT 165.015000 2956.720000 166.280000 2957.200000 ;
+ RECT 210.180000 3049.200000 211.280000 3049.680000 ;
+ RECT 161.350000 3049.200000 162.350000 3049.680000 ;
+ RECT 165.015000 3049.200000 166.280000 3049.680000 ;
+ RECT 237.930000 3049.200000 238.930000 3049.680000 ;
+ RECT 160.120000 3145.960000 240.160000 3146.960000 ;
+ RECT 160.120000 2950.390000 240.160000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 2949.140000 162.350000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 3148.400000 162.350000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 2949.140000 238.930000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 3148.400000 238.930000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2950.390000 161.120000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2950.390000 240.160000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 3145.960000 161.120000 3146.960000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 3145.960000 240.160000 3146.960000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 2941.420000 166.280000 2941.900000 ;
+ RECT 165.015000 2925.100000 166.280000 2925.580000 ;
+ RECT 165.015000 2930.540000 166.280000 2931.020000 ;
+ RECT 165.015000 2935.980000 166.280000 2936.460000 ;
+ RECT 165.015000 2919.660000 166.280000 2920.140000 ;
+ RECT 165.015000 2914.220000 166.280000 2914.700000 ;
+ RECT 165.015000 2908.780000 166.280000 2909.260000 ;
+ RECT 165.015000 2903.340000 166.280000 2903.820000 ;
+ RECT 165.015000 2887.020000 166.280000 2887.500000 ;
+ RECT 165.015000 2892.460000 166.280000 2892.940000 ;
+ RECT 165.015000 2897.900000 166.280000 2898.380000 ;
+ RECT 165.015000 2881.580000 166.280000 2882.060000 ;
+ RECT 165.015000 2876.140000 166.280000 2876.620000 ;
+ RECT 165.015000 2870.700000 166.280000 2871.180000 ;
+ RECT 165.015000 2865.260000 166.280000 2865.740000 ;
+ RECT 165.015000 2859.820000 166.280000 2860.300000 ;
+ RECT 165.015000 2854.380000 166.280000 2854.860000 ;
+ RECT 165.015000 2843.500000 166.280000 2843.980000 ;
+ RECT 165.015000 2838.060000 166.280000 2838.540000 ;
+ RECT 165.015000 2832.620000 166.280000 2833.100000 ;
+ RECT 165.015000 2827.180000 166.280000 2827.660000 ;
+ RECT 165.015000 2821.740000 166.280000 2822.220000 ;
+ RECT 165.015000 2816.300000 166.280000 2816.780000 ;
+ RECT 165.015000 2799.980000 166.280000 2800.460000 ;
+ RECT 165.015000 2805.420000 166.280000 2805.900000 ;
+ RECT 165.015000 2810.860000 166.280000 2811.340000 ;
+ RECT 165.015000 2794.540000 166.280000 2795.020000 ;
+ RECT 165.015000 2789.100000 166.280000 2789.580000 ;
+ RECT 165.015000 2783.660000 166.280000 2784.140000 ;
+ RECT 165.015000 2778.220000 166.280000 2778.700000 ;
+ RECT 165.015000 2761.900000 166.280000 2762.380000 ;
+ RECT 165.015000 2767.340000 166.280000 2767.820000 ;
+ RECT 165.015000 2772.780000 166.280000 2773.260000 ;
+ RECT 165.015000 2756.460000 166.280000 2756.940000 ;
+ RECT 165.015000 2848.940000 166.280000 2849.420000 ;
+ RECT 161.350000 2748.880000 162.350000 2949.140000 ;
+ RECT 237.930000 2748.880000 238.930000 2949.140000 ;
+ RECT 165.180000 2750.130000 166.280000 2946.700000 ;
+ RECT 210.180000 2750.130000 211.280000 2946.700000 ;
+ LAYER met3 ;
+ RECT 237.930000 2941.420000 238.930000 2941.900000 ;
+ RECT 237.930000 2935.980000 238.930000 2936.460000 ;
+ RECT 237.930000 2930.540000 238.930000 2931.020000 ;
+ RECT 237.930000 2925.100000 238.930000 2925.580000 ;
+ RECT 210.180000 2941.420000 211.280000 2941.900000 ;
+ RECT 210.180000 2935.980000 211.280000 2936.460000 ;
+ RECT 210.180000 2930.540000 211.280000 2931.020000 ;
+ RECT 210.180000 2925.100000 211.280000 2925.580000 ;
+ RECT 237.930000 2914.220000 238.930000 2914.700000 ;
+ RECT 237.930000 2919.660000 238.930000 2920.140000 ;
+ RECT 237.930000 2908.780000 238.930000 2909.260000 ;
+ RECT 237.930000 2903.340000 238.930000 2903.820000 ;
+ RECT 210.180000 2919.660000 211.280000 2920.140000 ;
+ RECT 210.180000 2914.220000 211.280000 2914.700000 ;
+ RECT 210.180000 2908.780000 211.280000 2909.260000 ;
+ RECT 210.180000 2903.340000 211.280000 2903.820000 ;
+ RECT 237.930000 2892.460000 238.930000 2892.940000 ;
+ RECT 237.930000 2887.020000 238.930000 2887.500000 ;
+ RECT 237.930000 2897.900000 238.930000 2898.380000 ;
+ RECT 237.930000 2881.580000 238.930000 2882.060000 ;
+ RECT 237.930000 2876.140000 238.930000 2876.620000 ;
+ RECT 210.180000 2897.900000 211.280000 2898.380000 ;
+ RECT 210.180000 2892.460000 211.280000 2892.940000 ;
+ RECT 210.180000 2887.020000 211.280000 2887.500000 ;
+ RECT 210.180000 2881.580000 211.280000 2882.060000 ;
+ RECT 210.180000 2876.140000 211.280000 2876.620000 ;
+ RECT 237.930000 2865.260000 238.930000 2865.740000 ;
+ RECT 237.930000 2870.700000 238.930000 2871.180000 ;
+ RECT 237.930000 2859.820000 238.930000 2860.300000 ;
+ RECT 237.930000 2854.380000 238.930000 2854.860000 ;
+ RECT 210.180000 2870.700000 211.280000 2871.180000 ;
+ RECT 210.180000 2865.260000 211.280000 2865.740000 ;
+ RECT 210.180000 2854.380000 211.280000 2854.860000 ;
+ RECT 210.180000 2859.820000 211.280000 2860.300000 ;
+ RECT 161.350000 2941.420000 162.350000 2941.900000 ;
+ RECT 165.015000 2941.420000 166.280000 2941.900000 ;
+ RECT 165.015000 2925.100000 166.280000 2925.580000 ;
+ RECT 165.015000 2930.540000 166.280000 2931.020000 ;
+ RECT 165.015000 2935.980000 166.280000 2936.460000 ;
+ RECT 161.350000 2925.100000 162.350000 2925.580000 ;
+ RECT 161.350000 2930.540000 162.350000 2931.020000 ;
+ RECT 161.350000 2935.980000 162.350000 2936.460000 ;
+ RECT 165.015000 2919.660000 166.280000 2920.140000 ;
+ RECT 165.015000 2914.220000 166.280000 2914.700000 ;
+ RECT 161.350000 2919.660000 162.350000 2920.140000 ;
+ RECT 161.350000 2914.220000 162.350000 2914.700000 ;
+ RECT 165.015000 2908.780000 166.280000 2909.260000 ;
+ RECT 165.015000 2903.340000 166.280000 2903.820000 ;
+ RECT 161.350000 2908.780000 162.350000 2909.260000 ;
+ RECT 161.350000 2903.340000 162.350000 2903.820000 ;
+ RECT 165.015000 2887.020000 166.280000 2887.500000 ;
+ RECT 165.015000 2892.460000 166.280000 2892.940000 ;
+ RECT 165.015000 2897.900000 166.280000 2898.380000 ;
+ RECT 161.350000 2887.020000 162.350000 2887.500000 ;
+ RECT 161.350000 2892.460000 162.350000 2892.940000 ;
+ RECT 161.350000 2897.900000 162.350000 2898.380000 ;
+ RECT 165.015000 2881.580000 166.280000 2882.060000 ;
+ RECT 165.015000 2876.140000 166.280000 2876.620000 ;
+ RECT 161.350000 2881.580000 162.350000 2882.060000 ;
+ RECT 161.350000 2876.140000 162.350000 2876.620000 ;
+ RECT 165.015000 2870.700000 166.280000 2871.180000 ;
+ RECT 165.015000 2865.260000 166.280000 2865.740000 ;
+ RECT 161.350000 2865.260000 162.350000 2865.740000 ;
+ RECT 161.350000 2870.700000 162.350000 2871.180000 ;
+ RECT 165.015000 2859.820000 166.280000 2860.300000 ;
+ RECT 165.015000 2854.380000 166.280000 2854.860000 ;
+ RECT 161.350000 2859.820000 162.350000 2860.300000 ;
+ RECT 161.350000 2854.380000 162.350000 2854.860000 ;
+ RECT 237.930000 2838.060000 238.930000 2838.540000 ;
+ RECT 237.930000 2843.500000 238.930000 2843.980000 ;
+ RECT 237.930000 2832.620000 238.930000 2833.100000 ;
+ RECT 237.930000 2827.180000 238.930000 2827.660000 ;
+ RECT 210.180000 2843.500000 211.280000 2843.980000 ;
+ RECT 210.180000 2838.060000 211.280000 2838.540000 ;
+ RECT 210.180000 2832.620000 211.280000 2833.100000 ;
+ RECT 210.180000 2827.180000 211.280000 2827.660000 ;
+ RECT 237.930000 2816.300000 238.930000 2816.780000 ;
+ RECT 237.930000 2821.740000 238.930000 2822.220000 ;
+ RECT 237.930000 2810.860000 238.930000 2811.340000 ;
+ RECT 237.930000 2805.420000 238.930000 2805.900000 ;
+ RECT 237.930000 2799.980000 238.930000 2800.460000 ;
+ RECT 210.180000 2821.740000 211.280000 2822.220000 ;
+ RECT 210.180000 2816.300000 211.280000 2816.780000 ;
+ RECT 210.180000 2810.860000 211.280000 2811.340000 ;
+ RECT 210.180000 2799.980000 211.280000 2800.460000 ;
+ RECT 210.180000 2805.420000 211.280000 2805.900000 ;
+ RECT 237.930000 2789.100000 238.930000 2789.580000 ;
+ RECT 237.930000 2794.540000 238.930000 2795.020000 ;
+ RECT 237.930000 2783.660000 238.930000 2784.140000 ;
+ RECT 237.930000 2778.220000 238.930000 2778.700000 ;
+ RECT 210.180000 2794.540000 211.280000 2795.020000 ;
+ RECT 210.180000 2789.100000 211.280000 2789.580000 ;
+ RECT 210.180000 2783.660000 211.280000 2784.140000 ;
+ RECT 210.180000 2778.220000 211.280000 2778.700000 ;
+ RECT 237.930000 2767.340000 238.930000 2767.820000 ;
+ RECT 237.930000 2761.900000 238.930000 2762.380000 ;
+ RECT 237.930000 2772.780000 238.930000 2773.260000 ;
+ RECT 237.930000 2756.460000 238.930000 2756.940000 ;
+ RECT 210.180000 2772.780000 211.280000 2773.260000 ;
+ RECT 210.180000 2767.340000 211.280000 2767.820000 ;
+ RECT 210.180000 2761.900000 211.280000 2762.380000 ;
+ RECT 210.180000 2756.460000 211.280000 2756.940000 ;
+ RECT 165.015000 2843.500000 166.280000 2843.980000 ;
+ RECT 165.015000 2838.060000 166.280000 2838.540000 ;
+ RECT 161.350000 2843.500000 162.350000 2843.980000 ;
+ RECT 161.350000 2838.060000 162.350000 2838.540000 ;
+ RECT 165.015000 2832.620000 166.280000 2833.100000 ;
+ RECT 165.015000 2827.180000 166.280000 2827.660000 ;
+ RECT 161.350000 2827.180000 162.350000 2827.660000 ;
+ RECT 161.350000 2832.620000 162.350000 2833.100000 ;
+ RECT 165.015000 2821.740000 166.280000 2822.220000 ;
+ RECT 165.015000 2816.300000 166.280000 2816.780000 ;
+ RECT 161.350000 2821.740000 162.350000 2822.220000 ;
+ RECT 161.350000 2816.300000 162.350000 2816.780000 ;
+ RECT 165.015000 2799.980000 166.280000 2800.460000 ;
+ RECT 165.015000 2805.420000 166.280000 2805.900000 ;
+ RECT 165.015000 2810.860000 166.280000 2811.340000 ;
+ RECT 161.350000 2799.980000 162.350000 2800.460000 ;
+ RECT 161.350000 2805.420000 162.350000 2805.900000 ;
+ RECT 161.350000 2810.860000 162.350000 2811.340000 ;
+ RECT 165.015000 2794.540000 166.280000 2795.020000 ;
+ RECT 165.015000 2789.100000 166.280000 2789.580000 ;
+ RECT 161.350000 2794.540000 162.350000 2795.020000 ;
+ RECT 161.350000 2789.100000 162.350000 2789.580000 ;
+ RECT 165.015000 2783.660000 166.280000 2784.140000 ;
+ RECT 165.015000 2778.220000 166.280000 2778.700000 ;
+ RECT 161.350000 2783.660000 162.350000 2784.140000 ;
+ RECT 161.350000 2778.220000 162.350000 2778.700000 ;
+ RECT 165.015000 2761.900000 166.280000 2762.380000 ;
+ RECT 165.015000 2767.340000 166.280000 2767.820000 ;
+ RECT 165.015000 2772.780000 166.280000 2773.260000 ;
+ RECT 161.350000 2761.900000 162.350000 2762.380000 ;
+ RECT 161.350000 2767.340000 162.350000 2767.820000 ;
+ RECT 161.350000 2772.780000 162.350000 2773.260000 ;
+ RECT 161.350000 2756.460000 162.350000 2756.940000 ;
+ RECT 165.015000 2756.460000 166.280000 2756.940000 ;
+ RECT 210.180000 2848.940000 211.280000 2849.420000 ;
+ RECT 161.350000 2848.940000 162.350000 2849.420000 ;
+ RECT 165.015000 2848.940000 166.280000 2849.420000 ;
+ RECT 237.930000 2848.940000 238.930000 2849.420000 ;
+ RECT 160.120000 2945.700000 240.160000 2946.700000 ;
+ RECT 160.120000 2750.130000 240.160000 2751.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 2748.880000 162.350000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 2948.140000 162.350000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 2748.880000 238.930000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 2948.140000 238.930000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2750.130000 161.120000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2750.130000 240.160000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2945.700000 161.120000 2946.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2945.700000 240.160000 2946.700000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 2741.160000 166.280000 2741.640000 ;
+ RECT 165.015000 2724.840000 166.280000 2725.320000 ;
+ RECT 165.015000 2730.280000 166.280000 2730.760000 ;
+ RECT 165.015000 2735.720000 166.280000 2736.200000 ;
+ RECT 165.015000 2719.400000 166.280000 2719.880000 ;
+ RECT 165.015000 2713.960000 166.280000 2714.440000 ;
+ RECT 165.015000 2708.520000 166.280000 2709.000000 ;
+ RECT 165.015000 2703.080000 166.280000 2703.560000 ;
+ RECT 165.015000 2686.760000 166.280000 2687.240000 ;
+ RECT 165.015000 2692.200000 166.280000 2692.680000 ;
+ RECT 165.015000 2697.640000 166.280000 2698.120000 ;
+ RECT 165.015000 2681.320000 166.280000 2681.800000 ;
+ RECT 165.015000 2675.880000 166.280000 2676.360000 ;
+ RECT 165.015000 2670.440000 166.280000 2670.920000 ;
+ RECT 165.015000 2665.000000 166.280000 2665.480000 ;
+ RECT 165.015000 2659.560000 166.280000 2660.040000 ;
+ RECT 165.015000 2654.120000 166.280000 2654.600000 ;
+ RECT 165.015000 2643.240000 166.280000 2643.720000 ;
+ RECT 165.015000 2637.800000 166.280000 2638.280000 ;
+ RECT 165.015000 2632.360000 166.280000 2632.840000 ;
+ RECT 165.015000 2626.920000 166.280000 2627.400000 ;
+ RECT 165.015000 2621.480000 166.280000 2621.960000 ;
+ RECT 165.015000 2616.040000 166.280000 2616.520000 ;
+ RECT 165.015000 2599.720000 166.280000 2600.200000 ;
+ RECT 165.015000 2605.160000 166.280000 2605.640000 ;
+ RECT 165.015000 2610.600000 166.280000 2611.080000 ;
+ RECT 165.015000 2594.280000 166.280000 2594.760000 ;
+ RECT 165.015000 2588.840000 166.280000 2589.320000 ;
+ RECT 165.015000 2583.400000 166.280000 2583.880000 ;
+ RECT 165.015000 2577.960000 166.280000 2578.440000 ;
+ RECT 165.015000 2561.640000 166.280000 2562.120000 ;
+ RECT 165.015000 2567.080000 166.280000 2567.560000 ;
+ RECT 165.015000 2572.520000 166.280000 2573.000000 ;
+ RECT 165.015000 2556.200000 166.280000 2556.680000 ;
+ RECT 165.015000 2648.680000 166.280000 2649.160000 ;
+ RECT 161.350000 2548.620000 162.350000 2748.880000 ;
+ RECT 237.930000 2548.620000 238.930000 2748.880000 ;
+ RECT 165.180000 2549.870000 166.280000 2746.440000 ;
+ RECT 210.180000 2549.870000 211.280000 2746.440000 ;
+ LAYER met3 ;
+ RECT 237.930000 2741.160000 238.930000 2741.640000 ;
+ RECT 237.930000 2735.720000 238.930000 2736.200000 ;
+ RECT 237.930000 2730.280000 238.930000 2730.760000 ;
+ RECT 237.930000 2724.840000 238.930000 2725.320000 ;
+ RECT 210.180000 2741.160000 211.280000 2741.640000 ;
+ RECT 210.180000 2735.720000 211.280000 2736.200000 ;
+ RECT 210.180000 2730.280000 211.280000 2730.760000 ;
+ RECT 210.180000 2724.840000 211.280000 2725.320000 ;
+ RECT 237.930000 2713.960000 238.930000 2714.440000 ;
+ RECT 237.930000 2719.400000 238.930000 2719.880000 ;
+ RECT 237.930000 2708.520000 238.930000 2709.000000 ;
+ RECT 237.930000 2703.080000 238.930000 2703.560000 ;
+ RECT 210.180000 2719.400000 211.280000 2719.880000 ;
+ RECT 210.180000 2713.960000 211.280000 2714.440000 ;
+ RECT 210.180000 2708.520000 211.280000 2709.000000 ;
+ RECT 210.180000 2703.080000 211.280000 2703.560000 ;
+ RECT 237.930000 2692.200000 238.930000 2692.680000 ;
+ RECT 237.930000 2686.760000 238.930000 2687.240000 ;
+ RECT 237.930000 2697.640000 238.930000 2698.120000 ;
+ RECT 237.930000 2681.320000 238.930000 2681.800000 ;
+ RECT 237.930000 2675.880000 238.930000 2676.360000 ;
+ RECT 210.180000 2697.640000 211.280000 2698.120000 ;
+ RECT 210.180000 2692.200000 211.280000 2692.680000 ;
+ RECT 210.180000 2686.760000 211.280000 2687.240000 ;
+ RECT 210.180000 2681.320000 211.280000 2681.800000 ;
+ RECT 210.180000 2675.880000 211.280000 2676.360000 ;
+ RECT 237.930000 2665.000000 238.930000 2665.480000 ;
+ RECT 237.930000 2670.440000 238.930000 2670.920000 ;
+ RECT 237.930000 2659.560000 238.930000 2660.040000 ;
+ RECT 237.930000 2654.120000 238.930000 2654.600000 ;
+ RECT 210.180000 2670.440000 211.280000 2670.920000 ;
+ RECT 210.180000 2665.000000 211.280000 2665.480000 ;
+ RECT 210.180000 2654.120000 211.280000 2654.600000 ;
+ RECT 210.180000 2659.560000 211.280000 2660.040000 ;
+ RECT 161.350000 2741.160000 162.350000 2741.640000 ;
+ RECT 165.015000 2741.160000 166.280000 2741.640000 ;
+ RECT 165.015000 2724.840000 166.280000 2725.320000 ;
+ RECT 165.015000 2730.280000 166.280000 2730.760000 ;
+ RECT 165.015000 2735.720000 166.280000 2736.200000 ;
+ RECT 161.350000 2724.840000 162.350000 2725.320000 ;
+ RECT 161.350000 2730.280000 162.350000 2730.760000 ;
+ RECT 161.350000 2735.720000 162.350000 2736.200000 ;
+ RECT 165.015000 2719.400000 166.280000 2719.880000 ;
+ RECT 165.015000 2713.960000 166.280000 2714.440000 ;
+ RECT 161.350000 2719.400000 162.350000 2719.880000 ;
+ RECT 161.350000 2713.960000 162.350000 2714.440000 ;
+ RECT 165.015000 2708.520000 166.280000 2709.000000 ;
+ RECT 165.015000 2703.080000 166.280000 2703.560000 ;
+ RECT 161.350000 2708.520000 162.350000 2709.000000 ;
+ RECT 161.350000 2703.080000 162.350000 2703.560000 ;
+ RECT 165.015000 2686.760000 166.280000 2687.240000 ;
+ RECT 165.015000 2692.200000 166.280000 2692.680000 ;
+ RECT 165.015000 2697.640000 166.280000 2698.120000 ;
+ RECT 161.350000 2686.760000 162.350000 2687.240000 ;
+ RECT 161.350000 2692.200000 162.350000 2692.680000 ;
+ RECT 161.350000 2697.640000 162.350000 2698.120000 ;
+ RECT 165.015000 2681.320000 166.280000 2681.800000 ;
+ RECT 165.015000 2675.880000 166.280000 2676.360000 ;
+ RECT 161.350000 2681.320000 162.350000 2681.800000 ;
+ RECT 161.350000 2675.880000 162.350000 2676.360000 ;
+ RECT 165.015000 2670.440000 166.280000 2670.920000 ;
+ RECT 165.015000 2665.000000 166.280000 2665.480000 ;
+ RECT 161.350000 2665.000000 162.350000 2665.480000 ;
+ RECT 161.350000 2670.440000 162.350000 2670.920000 ;
+ RECT 165.015000 2659.560000 166.280000 2660.040000 ;
+ RECT 165.015000 2654.120000 166.280000 2654.600000 ;
+ RECT 161.350000 2659.560000 162.350000 2660.040000 ;
+ RECT 161.350000 2654.120000 162.350000 2654.600000 ;
+ RECT 237.930000 2637.800000 238.930000 2638.280000 ;
+ RECT 237.930000 2643.240000 238.930000 2643.720000 ;
+ RECT 237.930000 2632.360000 238.930000 2632.840000 ;
+ RECT 237.930000 2626.920000 238.930000 2627.400000 ;
+ RECT 210.180000 2643.240000 211.280000 2643.720000 ;
+ RECT 210.180000 2637.800000 211.280000 2638.280000 ;
+ RECT 210.180000 2632.360000 211.280000 2632.840000 ;
+ RECT 210.180000 2626.920000 211.280000 2627.400000 ;
+ RECT 237.930000 2616.040000 238.930000 2616.520000 ;
+ RECT 237.930000 2621.480000 238.930000 2621.960000 ;
+ RECT 237.930000 2610.600000 238.930000 2611.080000 ;
+ RECT 237.930000 2605.160000 238.930000 2605.640000 ;
+ RECT 237.930000 2599.720000 238.930000 2600.200000 ;
+ RECT 210.180000 2621.480000 211.280000 2621.960000 ;
+ RECT 210.180000 2616.040000 211.280000 2616.520000 ;
+ RECT 210.180000 2610.600000 211.280000 2611.080000 ;
+ RECT 210.180000 2599.720000 211.280000 2600.200000 ;
+ RECT 210.180000 2605.160000 211.280000 2605.640000 ;
+ RECT 237.930000 2588.840000 238.930000 2589.320000 ;
+ RECT 237.930000 2594.280000 238.930000 2594.760000 ;
+ RECT 237.930000 2583.400000 238.930000 2583.880000 ;
+ RECT 237.930000 2577.960000 238.930000 2578.440000 ;
+ RECT 210.180000 2594.280000 211.280000 2594.760000 ;
+ RECT 210.180000 2588.840000 211.280000 2589.320000 ;
+ RECT 210.180000 2583.400000 211.280000 2583.880000 ;
+ RECT 210.180000 2577.960000 211.280000 2578.440000 ;
+ RECT 237.930000 2567.080000 238.930000 2567.560000 ;
+ RECT 237.930000 2561.640000 238.930000 2562.120000 ;
+ RECT 237.930000 2572.520000 238.930000 2573.000000 ;
+ RECT 237.930000 2556.200000 238.930000 2556.680000 ;
+ RECT 210.180000 2572.520000 211.280000 2573.000000 ;
+ RECT 210.180000 2567.080000 211.280000 2567.560000 ;
+ RECT 210.180000 2561.640000 211.280000 2562.120000 ;
+ RECT 210.180000 2556.200000 211.280000 2556.680000 ;
+ RECT 165.015000 2643.240000 166.280000 2643.720000 ;
+ RECT 165.015000 2637.800000 166.280000 2638.280000 ;
+ RECT 161.350000 2643.240000 162.350000 2643.720000 ;
+ RECT 161.350000 2637.800000 162.350000 2638.280000 ;
+ RECT 165.015000 2632.360000 166.280000 2632.840000 ;
+ RECT 165.015000 2626.920000 166.280000 2627.400000 ;
+ RECT 161.350000 2626.920000 162.350000 2627.400000 ;
+ RECT 161.350000 2632.360000 162.350000 2632.840000 ;
+ RECT 165.015000 2621.480000 166.280000 2621.960000 ;
+ RECT 165.015000 2616.040000 166.280000 2616.520000 ;
+ RECT 161.350000 2621.480000 162.350000 2621.960000 ;
+ RECT 161.350000 2616.040000 162.350000 2616.520000 ;
+ RECT 165.015000 2599.720000 166.280000 2600.200000 ;
+ RECT 165.015000 2605.160000 166.280000 2605.640000 ;
+ RECT 165.015000 2610.600000 166.280000 2611.080000 ;
+ RECT 161.350000 2599.720000 162.350000 2600.200000 ;
+ RECT 161.350000 2605.160000 162.350000 2605.640000 ;
+ RECT 161.350000 2610.600000 162.350000 2611.080000 ;
+ RECT 165.015000 2594.280000 166.280000 2594.760000 ;
+ RECT 165.015000 2588.840000 166.280000 2589.320000 ;
+ RECT 161.350000 2594.280000 162.350000 2594.760000 ;
+ RECT 161.350000 2588.840000 162.350000 2589.320000 ;
+ RECT 165.015000 2583.400000 166.280000 2583.880000 ;
+ RECT 165.015000 2577.960000 166.280000 2578.440000 ;
+ RECT 161.350000 2583.400000 162.350000 2583.880000 ;
+ RECT 161.350000 2577.960000 162.350000 2578.440000 ;
+ RECT 165.015000 2561.640000 166.280000 2562.120000 ;
+ RECT 165.015000 2567.080000 166.280000 2567.560000 ;
+ RECT 165.015000 2572.520000 166.280000 2573.000000 ;
+ RECT 161.350000 2561.640000 162.350000 2562.120000 ;
+ RECT 161.350000 2567.080000 162.350000 2567.560000 ;
+ RECT 161.350000 2572.520000 162.350000 2573.000000 ;
+ RECT 161.350000 2556.200000 162.350000 2556.680000 ;
+ RECT 165.015000 2556.200000 166.280000 2556.680000 ;
+ RECT 210.180000 2648.680000 211.280000 2649.160000 ;
+ RECT 161.350000 2648.680000 162.350000 2649.160000 ;
+ RECT 165.015000 2648.680000 166.280000 2649.160000 ;
+ RECT 237.930000 2648.680000 238.930000 2649.160000 ;
+ RECT 160.120000 2745.440000 240.160000 2746.440000 ;
+ RECT 160.120000 2549.870000 240.160000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 2548.620000 162.350000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 2747.880000 162.350000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 2548.620000 238.930000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 2747.880000 238.930000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2549.870000 161.120000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2549.870000 240.160000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2745.440000 161.120000 2746.440000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2745.440000 240.160000 2746.440000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 2540.900000 166.280000 2541.380000 ;
+ RECT 165.015000 2524.580000 166.280000 2525.060000 ;
+ RECT 165.015000 2530.020000 166.280000 2530.500000 ;
+ RECT 165.015000 2535.460000 166.280000 2535.940000 ;
+ RECT 165.015000 2519.140000 166.280000 2519.620000 ;
+ RECT 165.015000 2513.700000 166.280000 2514.180000 ;
+ RECT 165.015000 2508.260000 166.280000 2508.740000 ;
+ RECT 165.015000 2502.820000 166.280000 2503.300000 ;
+ RECT 165.015000 2486.500000 166.280000 2486.980000 ;
+ RECT 165.015000 2491.940000 166.280000 2492.420000 ;
+ RECT 165.015000 2497.380000 166.280000 2497.860000 ;
+ RECT 165.015000 2481.060000 166.280000 2481.540000 ;
+ RECT 165.015000 2475.620000 166.280000 2476.100000 ;
+ RECT 165.015000 2470.180000 166.280000 2470.660000 ;
+ RECT 165.015000 2464.740000 166.280000 2465.220000 ;
+ RECT 165.015000 2459.300000 166.280000 2459.780000 ;
+ RECT 165.015000 2453.860000 166.280000 2454.340000 ;
+ RECT 165.015000 2442.980000 166.280000 2443.460000 ;
+ RECT 165.015000 2437.540000 166.280000 2438.020000 ;
+ RECT 165.015000 2432.100000 166.280000 2432.580000 ;
+ RECT 165.015000 2426.660000 166.280000 2427.140000 ;
+ RECT 165.015000 2421.220000 166.280000 2421.700000 ;
+ RECT 165.015000 2415.780000 166.280000 2416.260000 ;
+ RECT 165.015000 2399.460000 166.280000 2399.940000 ;
+ RECT 165.015000 2404.900000 166.280000 2405.380000 ;
+ RECT 165.015000 2410.340000 166.280000 2410.820000 ;
+ RECT 165.015000 2394.020000 166.280000 2394.500000 ;
+ RECT 165.015000 2388.580000 166.280000 2389.060000 ;
+ RECT 165.015000 2383.140000 166.280000 2383.620000 ;
+ RECT 165.015000 2377.700000 166.280000 2378.180000 ;
+ RECT 165.015000 2361.380000 166.280000 2361.860000 ;
+ RECT 165.015000 2366.820000 166.280000 2367.300000 ;
+ RECT 165.015000 2372.260000 166.280000 2372.740000 ;
+ RECT 165.015000 2355.940000 166.280000 2356.420000 ;
+ RECT 165.015000 2448.420000 166.280000 2448.900000 ;
+ RECT 161.350000 2348.360000 162.350000 2548.620000 ;
+ RECT 237.930000 2348.360000 238.930000 2548.620000 ;
+ RECT 165.180000 2349.610000 166.280000 2546.180000 ;
+ RECT 210.180000 2349.610000 211.280000 2546.180000 ;
+ LAYER met3 ;
+ RECT 237.930000 2540.900000 238.930000 2541.380000 ;
+ RECT 237.930000 2535.460000 238.930000 2535.940000 ;
+ RECT 237.930000 2530.020000 238.930000 2530.500000 ;
+ RECT 237.930000 2524.580000 238.930000 2525.060000 ;
+ RECT 210.180000 2540.900000 211.280000 2541.380000 ;
+ RECT 210.180000 2535.460000 211.280000 2535.940000 ;
+ RECT 210.180000 2530.020000 211.280000 2530.500000 ;
+ RECT 210.180000 2524.580000 211.280000 2525.060000 ;
+ RECT 237.930000 2513.700000 238.930000 2514.180000 ;
+ RECT 237.930000 2519.140000 238.930000 2519.620000 ;
+ RECT 237.930000 2508.260000 238.930000 2508.740000 ;
+ RECT 237.930000 2502.820000 238.930000 2503.300000 ;
+ RECT 210.180000 2519.140000 211.280000 2519.620000 ;
+ RECT 210.180000 2513.700000 211.280000 2514.180000 ;
+ RECT 210.180000 2508.260000 211.280000 2508.740000 ;
+ RECT 210.180000 2502.820000 211.280000 2503.300000 ;
+ RECT 237.930000 2491.940000 238.930000 2492.420000 ;
+ RECT 237.930000 2486.500000 238.930000 2486.980000 ;
+ RECT 237.930000 2497.380000 238.930000 2497.860000 ;
+ RECT 237.930000 2481.060000 238.930000 2481.540000 ;
+ RECT 237.930000 2475.620000 238.930000 2476.100000 ;
+ RECT 210.180000 2497.380000 211.280000 2497.860000 ;
+ RECT 210.180000 2491.940000 211.280000 2492.420000 ;
+ RECT 210.180000 2486.500000 211.280000 2486.980000 ;
+ RECT 210.180000 2481.060000 211.280000 2481.540000 ;
+ RECT 210.180000 2475.620000 211.280000 2476.100000 ;
+ RECT 237.930000 2464.740000 238.930000 2465.220000 ;
+ RECT 237.930000 2470.180000 238.930000 2470.660000 ;
+ RECT 237.930000 2459.300000 238.930000 2459.780000 ;
+ RECT 237.930000 2453.860000 238.930000 2454.340000 ;
+ RECT 210.180000 2470.180000 211.280000 2470.660000 ;
+ RECT 210.180000 2464.740000 211.280000 2465.220000 ;
+ RECT 210.180000 2453.860000 211.280000 2454.340000 ;
+ RECT 210.180000 2459.300000 211.280000 2459.780000 ;
+ RECT 161.350000 2540.900000 162.350000 2541.380000 ;
+ RECT 165.015000 2540.900000 166.280000 2541.380000 ;
+ RECT 165.015000 2524.580000 166.280000 2525.060000 ;
+ RECT 165.015000 2530.020000 166.280000 2530.500000 ;
+ RECT 165.015000 2535.460000 166.280000 2535.940000 ;
+ RECT 161.350000 2524.580000 162.350000 2525.060000 ;
+ RECT 161.350000 2530.020000 162.350000 2530.500000 ;
+ RECT 161.350000 2535.460000 162.350000 2535.940000 ;
+ RECT 165.015000 2519.140000 166.280000 2519.620000 ;
+ RECT 165.015000 2513.700000 166.280000 2514.180000 ;
+ RECT 161.350000 2519.140000 162.350000 2519.620000 ;
+ RECT 161.350000 2513.700000 162.350000 2514.180000 ;
+ RECT 165.015000 2508.260000 166.280000 2508.740000 ;
+ RECT 165.015000 2502.820000 166.280000 2503.300000 ;
+ RECT 161.350000 2508.260000 162.350000 2508.740000 ;
+ RECT 161.350000 2502.820000 162.350000 2503.300000 ;
+ RECT 165.015000 2486.500000 166.280000 2486.980000 ;
+ RECT 165.015000 2491.940000 166.280000 2492.420000 ;
+ RECT 165.015000 2497.380000 166.280000 2497.860000 ;
+ RECT 161.350000 2486.500000 162.350000 2486.980000 ;
+ RECT 161.350000 2491.940000 162.350000 2492.420000 ;
+ RECT 161.350000 2497.380000 162.350000 2497.860000 ;
+ RECT 165.015000 2481.060000 166.280000 2481.540000 ;
+ RECT 165.015000 2475.620000 166.280000 2476.100000 ;
+ RECT 161.350000 2481.060000 162.350000 2481.540000 ;
+ RECT 161.350000 2475.620000 162.350000 2476.100000 ;
+ RECT 165.015000 2470.180000 166.280000 2470.660000 ;
+ RECT 165.015000 2464.740000 166.280000 2465.220000 ;
+ RECT 161.350000 2464.740000 162.350000 2465.220000 ;
+ RECT 161.350000 2470.180000 162.350000 2470.660000 ;
+ RECT 165.015000 2459.300000 166.280000 2459.780000 ;
+ RECT 165.015000 2453.860000 166.280000 2454.340000 ;
+ RECT 161.350000 2459.300000 162.350000 2459.780000 ;
+ RECT 161.350000 2453.860000 162.350000 2454.340000 ;
+ RECT 237.930000 2437.540000 238.930000 2438.020000 ;
+ RECT 237.930000 2442.980000 238.930000 2443.460000 ;
+ RECT 237.930000 2432.100000 238.930000 2432.580000 ;
+ RECT 237.930000 2426.660000 238.930000 2427.140000 ;
+ RECT 210.180000 2442.980000 211.280000 2443.460000 ;
+ RECT 210.180000 2437.540000 211.280000 2438.020000 ;
+ RECT 210.180000 2432.100000 211.280000 2432.580000 ;
+ RECT 210.180000 2426.660000 211.280000 2427.140000 ;
+ RECT 237.930000 2415.780000 238.930000 2416.260000 ;
+ RECT 237.930000 2421.220000 238.930000 2421.700000 ;
+ RECT 237.930000 2410.340000 238.930000 2410.820000 ;
+ RECT 237.930000 2404.900000 238.930000 2405.380000 ;
+ RECT 237.930000 2399.460000 238.930000 2399.940000 ;
+ RECT 210.180000 2421.220000 211.280000 2421.700000 ;
+ RECT 210.180000 2415.780000 211.280000 2416.260000 ;
+ RECT 210.180000 2410.340000 211.280000 2410.820000 ;
+ RECT 210.180000 2399.460000 211.280000 2399.940000 ;
+ RECT 210.180000 2404.900000 211.280000 2405.380000 ;
+ RECT 237.930000 2388.580000 238.930000 2389.060000 ;
+ RECT 237.930000 2394.020000 238.930000 2394.500000 ;
+ RECT 237.930000 2383.140000 238.930000 2383.620000 ;
+ RECT 237.930000 2377.700000 238.930000 2378.180000 ;
+ RECT 210.180000 2394.020000 211.280000 2394.500000 ;
+ RECT 210.180000 2388.580000 211.280000 2389.060000 ;
+ RECT 210.180000 2383.140000 211.280000 2383.620000 ;
+ RECT 210.180000 2377.700000 211.280000 2378.180000 ;
+ RECT 237.930000 2366.820000 238.930000 2367.300000 ;
+ RECT 237.930000 2361.380000 238.930000 2361.860000 ;
+ RECT 237.930000 2372.260000 238.930000 2372.740000 ;
+ RECT 237.930000 2355.940000 238.930000 2356.420000 ;
+ RECT 210.180000 2372.260000 211.280000 2372.740000 ;
+ RECT 210.180000 2366.820000 211.280000 2367.300000 ;
+ RECT 210.180000 2361.380000 211.280000 2361.860000 ;
+ RECT 210.180000 2355.940000 211.280000 2356.420000 ;
+ RECT 165.015000 2442.980000 166.280000 2443.460000 ;
+ RECT 165.015000 2437.540000 166.280000 2438.020000 ;
+ RECT 161.350000 2442.980000 162.350000 2443.460000 ;
+ RECT 161.350000 2437.540000 162.350000 2438.020000 ;
+ RECT 165.015000 2432.100000 166.280000 2432.580000 ;
+ RECT 165.015000 2426.660000 166.280000 2427.140000 ;
+ RECT 161.350000 2426.660000 162.350000 2427.140000 ;
+ RECT 161.350000 2432.100000 162.350000 2432.580000 ;
+ RECT 165.015000 2421.220000 166.280000 2421.700000 ;
+ RECT 165.015000 2415.780000 166.280000 2416.260000 ;
+ RECT 161.350000 2421.220000 162.350000 2421.700000 ;
+ RECT 161.350000 2415.780000 162.350000 2416.260000 ;
+ RECT 165.015000 2399.460000 166.280000 2399.940000 ;
+ RECT 165.015000 2404.900000 166.280000 2405.380000 ;
+ RECT 165.015000 2410.340000 166.280000 2410.820000 ;
+ RECT 161.350000 2399.460000 162.350000 2399.940000 ;
+ RECT 161.350000 2404.900000 162.350000 2405.380000 ;
+ RECT 161.350000 2410.340000 162.350000 2410.820000 ;
+ RECT 165.015000 2394.020000 166.280000 2394.500000 ;
+ RECT 165.015000 2388.580000 166.280000 2389.060000 ;
+ RECT 161.350000 2394.020000 162.350000 2394.500000 ;
+ RECT 161.350000 2388.580000 162.350000 2389.060000 ;
+ RECT 165.015000 2383.140000 166.280000 2383.620000 ;
+ RECT 165.015000 2377.700000 166.280000 2378.180000 ;
+ RECT 161.350000 2383.140000 162.350000 2383.620000 ;
+ RECT 161.350000 2377.700000 162.350000 2378.180000 ;
+ RECT 165.015000 2361.380000 166.280000 2361.860000 ;
+ RECT 165.015000 2366.820000 166.280000 2367.300000 ;
+ RECT 165.015000 2372.260000 166.280000 2372.740000 ;
+ RECT 161.350000 2361.380000 162.350000 2361.860000 ;
+ RECT 161.350000 2366.820000 162.350000 2367.300000 ;
+ RECT 161.350000 2372.260000 162.350000 2372.740000 ;
+ RECT 161.350000 2355.940000 162.350000 2356.420000 ;
+ RECT 165.015000 2355.940000 166.280000 2356.420000 ;
+ RECT 210.180000 2448.420000 211.280000 2448.900000 ;
+ RECT 161.350000 2448.420000 162.350000 2448.900000 ;
+ RECT 165.015000 2448.420000 166.280000 2448.900000 ;
+ RECT 237.930000 2448.420000 238.930000 2448.900000 ;
+ RECT 160.120000 2545.180000 240.160000 2546.180000 ;
+ RECT 160.120000 2349.610000 240.160000 2350.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 2348.360000 162.350000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 2547.620000 162.350000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 2348.360000 238.930000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 2547.620000 238.930000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2349.610000 161.120000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2349.610000 240.160000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2545.180000 161.120000 2546.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2545.180000 240.160000 2546.180000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 2340.640000 166.280000 2341.120000 ;
+ RECT 165.015000 2324.320000 166.280000 2324.800000 ;
+ RECT 165.015000 2329.760000 166.280000 2330.240000 ;
+ RECT 165.015000 2335.200000 166.280000 2335.680000 ;
+ RECT 165.015000 2318.880000 166.280000 2319.360000 ;
+ RECT 165.015000 2313.440000 166.280000 2313.920000 ;
+ RECT 165.015000 2308.000000 166.280000 2308.480000 ;
+ RECT 165.015000 2302.560000 166.280000 2303.040000 ;
+ RECT 165.015000 2286.240000 166.280000 2286.720000 ;
+ RECT 165.015000 2291.680000 166.280000 2292.160000 ;
+ RECT 165.015000 2297.120000 166.280000 2297.600000 ;
+ RECT 165.015000 2280.800000 166.280000 2281.280000 ;
+ RECT 165.015000 2275.360000 166.280000 2275.840000 ;
+ RECT 165.015000 2269.920000 166.280000 2270.400000 ;
+ RECT 165.015000 2264.480000 166.280000 2264.960000 ;
+ RECT 165.015000 2259.040000 166.280000 2259.520000 ;
+ RECT 165.015000 2253.600000 166.280000 2254.080000 ;
+ RECT 165.015000 2242.720000 166.280000 2243.200000 ;
+ RECT 165.015000 2237.280000 166.280000 2237.760000 ;
+ RECT 165.015000 2231.840000 166.280000 2232.320000 ;
+ RECT 165.015000 2226.400000 166.280000 2226.880000 ;
+ RECT 165.015000 2220.960000 166.280000 2221.440000 ;
+ RECT 165.015000 2215.520000 166.280000 2216.000000 ;
+ RECT 165.015000 2199.200000 166.280000 2199.680000 ;
+ RECT 165.015000 2204.640000 166.280000 2205.120000 ;
+ RECT 165.015000 2210.080000 166.280000 2210.560000 ;
+ RECT 165.015000 2193.760000 166.280000 2194.240000 ;
+ RECT 165.015000 2188.320000 166.280000 2188.800000 ;
+ RECT 165.015000 2182.880000 166.280000 2183.360000 ;
+ RECT 165.015000 2177.440000 166.280000 2177.920000 ;
+ RECT 165.015000 2161.120000 166.280000 2161.600000 ;
+ RECT 165.015000 2166.560000 166.280000 2167.040000 ;
+ RECT 165.015000 2172.000000 166.280000 2172.480000 ;
+ RECT 165.015000 2155.680000 166.280000 2156.160000 ;
+ RECT 165.015000 2248.160000 166.280000 2248.640000 ;
+ RECT 161.350000 2148.100000 162.350000 2348.360000 ;
+ RECT 237.930000 2148.100000 238.930000 2348.360000 ;
+ RECT 165.180000 2149.350000 166.280000 2345.920000 ;
+ RECT 210.180000 2149.350000 211.280000 2345.920000 ;
+ LAYER met3 ;
+ RECT 237.930000 2340.640000 238.930000 2341.120000 ;
+ RECT 237.930000 2335.200000 238.930000 2335.680000 ;
+ RECT 237.930000 2329.760000 238.930000 2330.240000 ;
+ RECT 237.930000 2324.320000 238.930000 2324.800000 ;
+ RECT 210.180000 2340.640000 211.280000 2341.120000 ;
+ RECT 210.180000 2335.200000 211.280000 2335.680000 ;
+ RECT 210.180000 2329.760000 211.280000 2330.240000 ;
+ RECT 210.180000 2324.320000 211.280000 2324.800000 ;
+ RECT 237.930000 2313.440000 238.930000 2313.920000 ;
+ RECT 237.930000 2318.880000 238.930000 2319.360000 ;
+ RECT 237.930000 2308.000000 238.930000 2308.480000 ;
+ RECT 237.930000 2302.560000 238.930000 2303.040000 ;
+ RECT 210.180000 2318.880000 211.280000 2319.360000 ;
+ RECT 210.180000 2313.440000 211.280000 2313.920000 ;
+ RECT 210.180000 2308.000000 211.280000 2308.480000 ;
+ RECT 210.180000 2302.560000 211.280000 2303.040000 ;
+ RECT 237.930000 2291.680000 238.930000 2292.160000 ;
+ RECT 237.930000 2286.240000 238.930000 2286.720000 ;
+ RECT 237.930000 2297.120000 238.930000 2297.600000 ;
+ RECT 237.930000 2280.800000 238.930000 2281.280000 ;
+ RECT 237.930000 2275.360000 238.930000 2275.840000 ;
+ RECT 210.180000 2297.120000 211.280000 2297.600000 ;
+ RECT 210.180000 2291.680000 211.280000 2292.160000 ;
+ RECT 210.180000 2286.240000 211.280000 2286.720000 ;
+ RECT 210.180000 2280.800000 211.280000 2281.280000 ;
+ RECT 210.180000 2275.360000 211.280000 2275.840000 ;
+ RECT 237.930000 2264.480000 238.930000 2264.960000 ;
+ RECT 237.930000 2269.920000 238.930000 2270.400000 ;
+ RECT 237.930000 2259.040000 238.930000 2259.520000 ;
+ RECT 237.930000 2253.600000 238.930000 2254.080000 ;
+ RECT 210.180000 2269.920000 211.280000 2270.400000 ;
+ RECT 210.180000 2264.480000 211.280000 2264.960000 ;
+ RECT 210.180000 2253.600000 211.280000 2254.080000 ;
+ RECT 210.180000 2259.040000 211.280000 2259.520000 ;
+ RECT 161.350000 2340.640000 162.350000 2341.120000 ;
+ RECT 165.015000 2340.640000 166.280000 2341.120000 ;
+ RECT 165.015000 2324.320000 166.280000 2324.800000 ;
+ RECT 165.015000 2329.760000 166.280000 2330.240000 ;
+ RECT 165.015000 2335.200000 166.280000 2335.680000 ;
+ RECT 161.350000 2324.320000 162.350000 2324.800000 ;
+ RECT 161.350000 2329.760000 162.350000 2330.240000 ;
+ RECT 161.350000 2335.200000 162.350000 2335.680000 ;
+ RECT 165.015000 2318.880000 166.280000 2319.360000 ;
+ RECT 165.015000 2313.440000 166.280000 2313.920000 ;
+ RECT 161.350000 2318.880000 162.350000 2319.360000 ;
+ RECT 161.350000 2313.440000 162.350000 2313.920000 ;
+ RECT 165.015000 2308.000000 166.280000 2308.480000 ;
+ RECT 165.015000 2302.560000 166.280000 2303.040000 ;
+ RECT 161.350000 2308.000000 162.350000 2308.480000 ;
+ RECT 161.350000 2302.560000 162.350000 2303.040000 ;
+ RECT 165.015000 2286.240000 166.280000 2286.720000 ;
+ RECT 165.015000 2291.680000 166.280000 2292.160000 ;
+ RECT 165.015000 2297.120000 166.280000 2297.600000 ;
+ RECT 161.350000 2286.240000 162.350000 2286.720000 ;
+ RECT 161.350000 2291.680000 162.350000 2292.160000 ;
+ RECT 161.350000 2297.120000 162.350000 2297.600000 ;
+ RECT 165.015000 2280.800000 166.280000 2281.280000 ;
+ RECT 165.015000 2275.360000 166.280000 2275.840000 ;
+ RECT 161.350000 2280.800000 162.350000 2281.280000 ;
+ RECT 161.350000 2275.360000 162.350000 2275.840000 ;
+ RECT 165.015000 2269.920000 166.280000 2270.400000 ;
+ RECT 165.015000 2264.480000 166.280000 2264.960000 ;
+ RECT 161.350000 2264.480000 162.350000 2264.960000 ;
+ RECT 161.350000 2269.920000 162.350000 2270.400000 ;
+ RECT 165.015000 2259.040000 166.280000 2259.520000 ;
+ RECT 165.015000 2253.600000 166.280000 2254.080000 ;
+ RECT 161.350000 2259.040000 162.350000 2259.520000 ;
+ RECT 161.350000 2253.600000 162.350000 2254.080000 ;
+ RECT 237.930000 2237.280000 238.930000 2237.760000 ;
+ RECT 237.930000 2242.720000 238.930000 2243.200000 ;
+ RECT 237.930000 2231.840000 238.930000 2232.320000 ;
+ RECT 237.930000 2226.400000 238.930000 2226.880000 ;
+ RECT 210.180000 2242.720000 211.280000 2243.200000 ;
+ RECT 210.180000 2237.280000 211.280000 2237.760000 ;
+ RECT 210.180000 2231.840000 211.280000 2232.320000 ;
+ RECT 210.180000 2226.400000 211.280000 2226.880000 ;
+ RECT 237.930000 2215.520000 238.930000 2216.000000 ;
+ RECT 237.930000 2220.960000 238.930000 2221.440000 ;
+ RECT 237.930000 2210.080000 238.930000 2210.560000 ;
+ RECT 237.930000 2204.640000 238.930000 2205.120000 ;
+ RECT 237.930000 2199.200000 238.930000 2199.680000 ;
+ RECT 210.180000 2220.960000 211.280000 2221.440000 ;
+ RECT 210.180000 2215.520000 211.280000 2216.000000 ;
+ RECT 210.180000 2210.080000 211.280000 2210.560000 ;
+ RECT 210.180000 2199.200000 211.280000 2199.680000 ;
+ RECT 210.180000 2204.640000 211.280000 2205.120000 ;
+ RECT 237.930000 2188.320000 238.930000 2188.800000 ;
+ RECT 237.930000 2193.760000 238.930000 2194.240000 ;
+ RECT 237.930000 2182.880000 238.930000 2183.360000 ;
+ RECT 237.930000 2177.440000 238.930000 2177.920000 ;
+ RECT 210.180000 2193.760000 211.280000 2194.240000 ;
+ RECT 210.180000 2188.320000 211.280000 2188.800000 ;
+ RECT 210.180000 2182.880000 211.280000 2183.360000 ;
+ RECT 210.180000 2177.440000 211.280000 2177.920000 ;
+ RECT 237.930000 2166.560000 238.930000 2167.040000 ;
+ RECT 237.930000 2161.120000 238.930000 2161.600000 ;
+ RECT 237.930000 2172.000000 238.930000 2172.480000 ;
+ RECT 237.930000 2155.680000 238.930000 2156.160000 ;
+ RECT 210.180000 2172.000000 211.280000 2172.480000 ;
+ RECT 210.180000 2166.560000 211.280000 2167.040000 ;
+ RECT 210.180000 2161.120000 211.280000 2161.600000 ;
+ RECT 210.180000 2155.680000 211.280000 2156.160000 ;
+ RECT 165.015000 2242.720000 166.280000 2243.200000 ;
+ RECT 165.015000 2237.280000 166.280000 2237.760000 ;
+ RECT 161.350000 2242.720000 162.350000 2243.200000 ;
+ RECT 161.350000 2237.280000 162.350000 2237.760000 ;
+ RECT 165.015000 2231.840000 166.280000 2232.320000 ;
+ RECT 165.015000 2226.400000 166.280000 2226.880000 ;
+ RECT 161.350000 2226.400000 162.350000 2226.880000 ;
+ RECT 161.350000 2231.840000 162.350000 2232.320000 ;
+ RECT 165.015000 2220.960000 166.280000 2221.440000 ;
+ RECT 165.015000 2215.520000 166.280000 2216.000000 ;
+ RECT 161.350000 2220.960000 162.350000 2221.440000 ;
+ RECT 161.350000 2215.520000 162.350000 2216.000000 ;
+ RECT 165.015000 2199.200000 166.280000 2199.680000 ;
+ RECT 165.015000 2204.640000 166.280000 2205.120000 ;
+ RECT 165.015000 2210.080000 166.280000 2210.560000 ;
+ RECT 161.350000 2199.200000 162.350000 2199.680000 ;
+ RECT 161.350000 2204.640000 162.350000 2205.120000 ;
+ RECT 161.350000 2210.080000 162.350000 2210.560000 ;
+ RECT 165.015000 2193.760000 166.280000 2194.240000 ;
+ RECT 165.015000 2188.320000 166.280000 2188.800000 ;
+ RECT 161.350000 2193.760000 162.350000 2194.240000 ;
+ RECT 161.350000 2188.320000 162.350000 2188.800000 ;
+ RECT 165.015000 2182.880000 166.280000 2183.360000 ;
+ RECT 165.015000 2177.440000 166.280000 2177.920000 ;
+ RECT 161.350000 2182.880000 162.350000 2183.360000 ;
+ RECT 161.350000 2177.440000 162.350000 2177.920000 ;
+ RECT 165.015000 2161.120000 166.280000 2161.600000 ;
+ RECT 165.015000 2166.560000 166.280000 2167.040000 ;
+ RECT 165.015000 2172.000000 166.280000 2172.480000 ;
+ RECT 161.350000 2161.120000 162.350000 2161.600000 ;
+ RECT 161.350000 2166.560000 162.350000 2167.040000 ;
+ RECT 161.350000 2172.000000 162.350000 2172.480000 ;
+ RECT 161.350000 2155.680000 162.350000 2156.160000 ;
+ RECT 165.015000 2155.680000 166.280000 2156.160000 ;
+ RECT 210.180000 2248.160000 211.280000 2248.640000 ;
+ RECT 161.350000 2248.160000 162.350000 2248.640000 ;
+ RECT 165.015000 2248.160000 166.280000 2248.640000 ;
+ RECT 237.930000 2248.160000 238.930000 2248.640000 ;
+ RECT 160.120000 2344.920000 240.160000 2345.920000 ;
+ RECT 160.120000 2149.350000 240.160000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 2148.100000 162.350000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 2347.360000 162.350000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 2148.100000 238.930000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 2347.360000 238.930000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2149.350000 161.120000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2149.350000 240.160000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2344.920000 161.120000 2345.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2344.920000 240.160000 2345.920000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 2140.380000 166.280000 2140.860000 ;
+ RECT 165.015000 2124.060000 166.280000 2124.540000 ;
+ RECT 165.015000 2129.500000 166.280000 2129.980000 ;
+ RECT 165.015000 2134.940000 166.280000 2135.420000 ;
+ RECT 165.015000 2118.620000 166.280000 2119.100000 ;
+ RECT 165.015000 2113.180000 166.280000 2113.660000 ;
+ RECT 165.015000 2107.740000 166.280000 2108.220000 ;
+ RECT 165.015000 2102.300000 166.280000 2102.780000 ;
+ RECT 165.015000 2085.980000 166.280000 2086.460000 ;
+ RECT 165.015000 2091.420000 166.280000 2091.900000 ;
+ RECT 165.015000 2096.860000 166.280000 2097.340000 ;
+ RECT 165.015000 2080.540000 166.280000 2081.020000 ;
+ RECT 165.015000 2075.100000 166.280000 2075.580000 ;
+ RECT 165.015000 2069.660000 166.280000 2070.140000 ;
+ RECT 165.015000 2064.220000 166.280000 2064.700000 ;
+ RECT 165.015000 2058.780000 166.280000 2059.260000 ;
+ RECT 165.015000 2053.340000 166.280000 2053.820000 ;
+ RECT 165.015000 2042.460000 166.280000 2042.940000 ;
+ RECT 165.015000 2037.020000 166.280000 2037.500000 ;
+ RECT 165.015000 2031.580000 166.280000 2032.060000 ;
+ RECT 165.015000 2026.140000 166.280000 2026.620000 ;
+ RECT 165.015000 2020.700000 166.280000 2021.180000 ;
+ RECT 165.015000 2015.260000 166.280000 2015.740000 ;
+ RECT 165.015000 1998.940000 166.280000 1999.420000 ;
+ RECT 165.015000 2004.380000 166.280000 2004.860000 ;
+ RECT 165.015000 2009.820000 166.280000 2010.300000 ;
+ RECT 165.015000 1993.500000 166.280000 1993.980000 ;
+ RECT 165.015000 1988.060000 166.280000 1988.540000 ;
+ RECT 165.015000 1982.620000 166.280000 1983.100000 ;
+ RECT 165.015000 1977.180000 166.280000 1977.660000 ;
+ RECT 165.015000 1960.860000 166.280000 1961.340000 ;
+ RECT 165.015000 1966.300000 166.280000 1966.780000 ;
+ RECT 165.015000 1971.740000 166.280000 1972.220000 ;
+ RECT 165.015000 1955.420000 166.280000 1955.900000 ;
+ RECT 165.015000 2047.900000 166.280000 2048.380000 ;
+ RECT 161.350000 1947.840000 162.350000 2148.100000 ;
+ RECT 237.930000 1947.840000 238.930000 2148.100000 ;
+ RECT 165.180000 1949.090000 166.280000 2145.660000 ;
+ RECT 210.180000 1949.090000 211.280000 2145.660000 ;
+ LAYER met3 ;
+ RECT 237.930000 2140.380000 238.930000 2140.860000 ;
+ RECT 237.930000 2134.940000 238.930000 2135.420000 ;
+ RECT 237.930000 2129.500000 238.930000 2129.980000 ;
+ RECT 237.930000 2124.060000 238.930000 2124.540000 ;
+ RECT 210.180000 2140.380000 211.280000 2140.860000 ;
+ RECT 210.180000 2134.940000 211.280000 2135.420000 ;
+ RECT 210.180000 2129.500000 211.280000 2129.980000 ;
+ RECT 210.180000 2124.060000 211.280000 2124.540000 ;
+ RECT 237.930000 2113.180000 238.930000 2113.660000 ;
+ RECT 237.930000 2118.620000 238.930000 2119.100000 ;
+ RECT 237.930000 2107.740000 238.930000 2108.220000 ;
+ RECT 237.930000 2102.300000 238.930000 2102.780000 ;
+ RECT 210.180000 2118.620000 211.280000 2119.100000 ;
+ RECT 210.180000 2113.180000 211.280000 2113.660000 ;
+ RECT 210.180000 2107.740000 211.280000 2108.220000 ;
+ RECT 210.180000 2102.300000 211.280000 2102.780000 ;
+ RECT 237.930000 2091.420000 238.930000 2091.900000 ;
+ RECT 237.930000 2085.980000 238.930000 2086.460000 ;
+ RECT 237.930000 2096.860000 238.930000 2097.340000 ;
+ RECT 237.930000 2080.540000 238.930000 2081.020000 ;
+ RECT 237.930000 2075.100000 238.930000 2075.580000 ;
+ RECT 210.180000 2096.860000 211.280000 2097.340000 ;
+ RECT 210.180000 2091.420000 211.280000 2091.900000 ;
+ RECT 210.180000 2085.980000 211.280000 2086.460000 ;
+ RECT 210.180000 2080.540000 211.280000 2081.020000 ;
+ RECT 210.180000 2075.100000 211.280000 2075.580000 ;
+ RECT 237.930000 2064.220000 238.930000 2064.700000 ;
+ RECT 237.930000 2069.660000 238.930000 2070.140000 ;
+ RECT 237.930000 2058.780000 238.930000 2059.260000 ;
+ RECT 237.930000 2053.340000 238.930000 2053.820000 ;
+ RECT 210.180000 2069.660000 211.280000 2070.140000 ;
+ RECT 210.180000 2064.220000 211.280000 2064.700000 ;
+ RECT 210.180000 2053.340000 211.280000 2053.820000 ;
+ RECT 210.180000 2058.780000 211.280000 2059.260000 ;
+ RECT 161.350000 2140.380000 162.350000 2140.860000 ;
+ RECT 165.015000 2140.380000 166.280000 2140.860000 ;
+ RECT 165.015000 2124.060000 166.280000 2124.540000 ;
+ RECT 165.015000 2129.500000 166.280000 2129.980000 ;
+ RECT 165.015000 2134.940000 166.280000 2135.420000 ;
+ RECT 161.350000 2124.060000 162.350000 2124.540000 ;
+ RECT 161.350000 2129.500000 162.350000 2129.980000 ;
+ RECT 161.350000 2134.940000 162.350000 2135.420000 ;
+ RECT 165.015000 2118.620000 166.280000 2119.100000 ;
+ RECT 165.015000 2113.180000 166.280000 2113.660000 ;
+ RECT 161.350000 2118.620000 162.350000 2119.100000 ;
+ RECT 161.350000 2113.180000 162.350000 2113.660000 ;
+ RECT 165.015000 2107.740000 166.280000 2108.220000 ;
+ RECT 165.015000 2102.300000 166.280000 2102.780000 ;
+ RECT 161.350000 2107.740000 162.350000 2108.220000 ;
+ RECT 161.350000 2102.300000 162.350000 2102.780000 ;
+ RECT 165.015000 2085.980000 166.280000 2086.460000 ;
+ RECT 165.015000 2091.420000 166.280000 2091.900000 ;
+ RECT 165.015000 2096.860000 166.280000 2097.340000 ;
+ RECT 161.350000 2085.980000 162.350000 2086.460000 ;
+ RECT 161.350000 2091.420000 162.350000 2091.900000 ;
+ RECT 161.350000 2096.860000 162.350000 2097.340000 ;
+ RECT 165.015000 2080.540000 166.280000 2081.020000 ;
+ RECT 165.015000 2075.100000 166.280000 2075.580000 ;
+ RECT 161.350000 2080.540000 162.350000 2081.020000 ;
+ RECT 161.350000 2075.100000 162.350000 2075.580000 ;
+ RECT 165.015000 2069.660000 166.280000 2070.140000 ;
+ RECT 165.015000 2064.220000 166.280000 2064.700000 ;
+ RECT 161.350000 2064.220000 162.350000 2064.700000 ;
+ RECT 161.350000 2069.660000 162.350000 2070.140000 ;
+ RECT 165.015000 2058.780000 166.280000 2059.260000 ;
+ RECT 165.015000 2053.340000 166.280000 2053.820000 ;
+ RECT 161.350000 2058.780000 162.350000 2059.260000 ;
+ RECT 161.350000 2053.340000 162.350000 2053.820000 ;
+ RECT 237.930000 2037.020000 238.930000 2037.500000 ;
+ RECT 237.930000 2042.460000 238.930000 2042.940000 ;
+ RECT 237.930000 2031.580000 238.930000 2032.060000 ;
+ RECT 237.930000 2026.140000 238.930000 2026.620000 ;
+ RECT 210.180000 2042.460000 211.280000 2042.940000 ;
+ RECT 210.180000 2037.020000 211.280000 2037.500000 ;
+ RECT 210.180000 2031.580000 211.280000 2032.060000 ;
+ RECT 210.180000 2026.140000 211.280000 2026.620000 ;
+ RECT 237.930000 2015.260000 238.930000 2015.740000 ;
+ RECT 237.930000 2020.700000 238.930000 2021.180000 ;
+ RECT 237.930000 2009.820000 238.930000 2010.300000 ;
+ RECT 237.930000 2004.380000 238.930000 2004.860000 ;
+ RECT 237.930000 1998.940000 238.930000 1999.420000 ;
+ RECT 210.180000 2020.700000 211.280000 2021.180000 ;
+ RECT 210.180000 2015.260000 211.280000 2015.740000 ;
+ RECT 210.180000 2009.820000 211.280000 2010.300000 ;
+ RECT 210.180000 1998.940000 211.280000 1999.420000 ;
+ RECT 210.180000 2004.380000 211.280000 2004.860000 ;
+ RECT 237.930000 1988.060000 238.930000 1988.540000 ;
+ RECT 237.930000 1993.500000 238.930000 1993.980000 ;
+ RECT 237.930000 1982.620000 238.930000 1983.100000 ;
+ RECT 237.930000 1977.180000 238.930000 1977.660000 ;
+ RECT 210.180000 1993.500000 211.280000 1993.980000 ;
+ RECT 210.180000 1988.060000 211.280000 1988.540000 ;
+ RECT 210.180000 1982.620000 211.280000 1983.100000 ;
+ RECT 210.180000 1977.180000 211.280000 1977.660000 ;
+ RECT 237.930000 1966.300000 238.930000 1966.780000 ;
+ RECT 237.930000 1960.860000 238.930000 1961.340000 ;
+ RECT 237.930000 1971.740000 238.930000 1972.220000 ;
+ RECT 237.930000 1955.420000 238.930000 1955.900000 ;
+ RECT 210.180000 1971.740000 211.280000 1972.220000 ;
+ RECT 210.180000 1966.300000 211.280000 1966.780000 ;
+ RECT 210.180000 1960.860000 211.280000 1961.340000 ;
+ RECT 210.180000 1955.420000 211.280000 1955.900000 ;
+ RECT 165.015000 2042.460000 166.280000 2042.940000 ;
+ RECT 165.015000 2037.020000 166.280000 2037.500000 ;
+ RECT 161.350000 2042.460000 162.350000 2042.940000 ;
+ RECT 161.350000 2037.020000 162.350000 2037.500000 ;
+ RECT 165.015000 2031.580000 166.280000 2032.060000 ;
+ RECT 165.015000 2026.140000 166.280000 2026.620000 ;
+ RECT 161.350000 2026.140000 162.350000 2026.620000 ;
+ RECT 161.350000 2031.580000 162.350000 2032.060000 ;
+ RECT 165.015000 2020.700000 166.280000 2021.180000 ;
+ RECT 165.015000 2015.260000 166.280000 2015.740000 ;
+ RECT 161.350000 2020.700000 162.350000 2021.180000 ;
+ RECT 161.350000 2015.260000 162.350000 2015.740000 ;
+ RECT 165.015000 1998.940000 166.280000 1999.420000 ;
+ RECT 165.015000 2004.380000 166.280000 2004.860000 ;
+ RECT 165.015000 2009.820000 166.280000 2010.300000 ;
+ RECT 161.350000 1998.940000 162.350000 1999.420000 ;
+ RECT 161.350000 2004.380000 162.350000 2004.860000 ;
+ RECT 161.350000 2009.820000 162.350000 2010.300000 ;
+ RECT 165.015000 1993.500000 166.280000 1993.980000 ;
+ RECT 165.015000 1988.060000 166.280000 1988.540000 ;
+ RECT 161.350000 1993.500000 162.350000 1993.980000 ;
+ RECT 161.350000 1988.060000 162.350000 1988.540000 ;
+ RECT 165.015000 1982.620000 166.280000 1983.100000 ;
+ RECT 165.015000 1977.180000 166.280000 1977.660000 ;
+ RECT 161.350000 1982.620000 162.350000 1983.100000 ;
+ RECT 161.350000 1977.180000 162.350000 1977.660000 ;
+ RECT 165.015000 1960.860000 166.280000 1961.340000 ;
+ RECT 165.015000 1966.300000 166.280000 1966.780000 ;
+ RECT 165.015000 1971.740000 166.280000 1972.220000 ;
+ RECT 161.350000 1960.860000 162.350000 1961.340000 ;
+ RECT 161.350000 1966.300000 162.350000 1966.780000 ;
+ RECT 161.350000 1971.740000 162.350000 1972.220000 ;
+ RECT 161.350000 1955.420000 162.350000 1955.900000 ;
+ RECT 165.015000 1955.420000 166.280000 1955.900000 ;
+ RECT 210.180000 2047.900000 211.280000 2048.380000 ;
+ RECT 161.350000 2047.900000 162.350000 2048.380000 ;
+ RECT 165.015000 2047.900000 166.280000 2048.380000 ;
+ RECT 237.930000 2047.900000 238.930000 2048.380000 ;
+ RECT 160.120000 2144.660000 240.160000 2145.660000 ;
+ RECT 160.120000 1949.090000 240.160000 1950.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 1947.840000 162.350000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 2147.100000 162.350000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 1947.840000 238.930000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 2147.100000 238.930000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1949.090000 161.120000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1949.090000 240.160000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2144.660000 161.120000 2145.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2144.660000 240.160000 2145.660000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 1940.120000 166.280000 1940.600000 ;
+ RECT 165.015000 1923.800000 166.280000 1924.280000 ;
+ RECT 165.015000 1929.240000 166.280000 1929.720000 ;
+ RECT 165.015000 1934.680000 166.280000 1935.160000 ;
+ RECT 165.015000 1918.360000 166.280000 1918.840000 ;
+ RECT 165.015000 1912.920000 166.280000 1913.400000 ;
+ RECT 165.015000 1907.480000 166.280000 1907.960000 ;
+ RECT 165.015000 1902.040000 166.280000 1902.520000 ;
+ RECT 165.015000 1885.720000 166.280000 1886.200000 ;
+ RECT 165.015000 1891.160000 166.280000 1891.640000 ;
+ RECT 165.015000 1896.600000 166.280000 1897.080000 ;
+ RECT 165.015000 1880.280000 166.280000 1880.760000 ;
+ RECT 165.015000 1874.840000 166.280000 1875.320000 ;
+ RECT 165.015000 1869.400000 166.280000 1869.880000 ;
+ RECT 165.015000 1863.960000 166.280000 1864.440000 ;
+ RECT 165.015000 1858.520000 166.280000 1859.000000 ;
+ RECT 165.015000 1853.080000 166.280000 1853.560000 ;
+ RECT 165.015000 1842.200000 166.280000 1842.680000 ;
+ RECT 165.015000 1836.760000 166.280000 1837.240000 ;
+ RECT 165.015000 1831.320000 166.280000 1831.800000 ;
+ RECT 165.015000 1825.880000 166.280000 1826.360000 ;
+ RECT 165.015000 1820.440000 166.280000 1820.920000 ;
+ RECT 165.015000 1815.000000 166.280000 1815.480000 ;
+ RECT 165.015000 1798.680000 166.280000 1799.160000 ;
+ RECT 165.015000 1804.120000 166.280000 1804.600000 ;
+ RECT 165.015000 1809.560000 166.280000 1810.040000 ;
+ RECT 165.015000 1793.240000 166.280000 1793.720000 ;
+ RECT 165.015000 1787.800000 166.280000 1788.280000 ;
+ RECT 165.015000 1782.360000 166.280000 1782.840000 ;
+ RECT 165.015000 1776.920000 166.280000 1777.400000 ;
+ RECT 165.015000 1760.600000 166.280000 1761.080000 ;
+ RECT 165.015000 1766.040000 166.280000 1766.520000 ;
+ RECT 165.015000 1771.480000 166.280000 1771.960000 ;
+ RECT 165.015000 1755.160000 166.280000 1755.640000 ;
+ RECT 165.015000 1847.640000 166.280000 1848.120000 ;
+ RECT 161.350000 1747.580000 162.350000 1947.840000 ;
+ RECT 237.930000 1747.580000 238.930000 1947.840000 ;
+ RECT 165.180000 1748.830000 166.280000 1945.400000 ;
+ RECT 210.180000 1748.830000 211.280000 1945.400000 ;
+ LAYER met3 ;
+ RECT 237.930000 1940.120000 238.930000 1940.600000 ;
+ RECT 237.930000 1934.680000 238.930000 1935.160000 ;
+ RECT 237.930000 1929.240000 238.930000 1929.720000 ;
+ RECT 237.930000 1923.800000 238.930000 1924.280000 ;
+ RECT 210.180000 1940.120000 211.280000 1940.600000 ;
+ RECT 210.180000 1934.680000 211.280000 1935.160000 ;
+ RECT 210.180000 1929.240000 211.280000 1929.720000 ;
+ RECT 210.180000 1923.800000 211.280000 1924.280000 ;
+ RECT 237.930000 1912.920000 238.930000 1913.400000 ;
+ RECT 237.930000 1918.360000 238.930000 1918.840000 ;
+ RECT 237.930000 1907.480000 238.930000 1907.960000 ;
+ RECT 237.930000 1902.040000 238.930000 1902.520000 ;
+ RECT 210.180000 1918.360000 211.280000 1918.840000 ;
+ RECT 210.180000 1912.920000 211.280000 1913.400000 ;
+ RECT 210.180000 1907.480000 211.280000 1907.960000 ;
+ RECT 210.180000 1902.040000 211.280000 1902.520000 ;
+ RECT 237.930000 1891.160000 238.930000 1891.640000 ;
+ RECT 237.930000 1885.720000 238.930000 1886.200000 ;
+ RECT 237.930000 1896.600000 238.930000 1897.080000 ;
+ RECT 237.930000 1880.280000 238.930000 1880.760000 ;
+ RECT 237.930000 1874.840000 238.930000 1875.320000 ;
+ RECT 210.180000 1896.600000 211.280000 1897.080000 ;
+ RECT 210.180000 1891.160000 211.280000 1891.640000 ;
+ RECT 210.180000 1885.720000 211.280000 1886.200000 ;
+ RECT 210.180000 1880.280000 211.280000 1880.760000 ;
+ RECT 210.180000 1874.840000 211.280000 1875.320000 ;
+ RECT 237.930000 1863.960000 238.930000 1864.440000 ;
+ RECT 237.930000 1869.400000 238.930000 1869.880000 ;
+ RECT 237.930000 1858.520000 238.930000 1859.000000 ;
+ RECT 237.930000 1853.080000 238.930000 1853.560000 ;
+ RECT 210.180000 1869.400000 211.280000 1869.880000 ;
+ RECT 210.180000 1863.960000 211.280000 1864.440000 ;
+ RECT 210.180000 1853.080000 211.280000 1853.560000 ;
+ RECT 210.180000 1858.520000 211.280000 1859.000000 ;
+ RECT 161.350000 1940.120000 162.350000 1940.600000 ;
+ RECT 165.015000 1940.120000 166.280000 1940.600000 ;
+ RECT 165.015000 1923.800000 166.280000 1924.280000 ;
+ RECT 165.015000 1929.240000 166.280000 1929.720000 ;
+ RECT 165.015000 1934.680000 166.280000 1935.160000 ;
+ RECT 161.350000 1923.800000 162.350000 1924.280000 ;
+ RECT 161.350000 1929.240000 162.350000 1929.720000 ;
+ RECT 161.350000 1934.680000 162.350000 1935.160000 ;
+ RECT 165.015000 1918.360000 166.280000 1918.840000 ;
+ RECT 165.015000 1912.920000 166.280000 1913.400000 ;
+ RECT 161.350000 1918.360000 162.350000 1918.840000 ;
+ RECT 161.350000 1912.920000 162.350000 1913.400000 ;
+ RECT 165.015000 1907.480000 166.280000 1907.960000 ;
+ RECT 165.015000 1902.040000 166.280000 1902.520000 ;
+ RECT 161.350000 1907.480000 162.350000 1907.960000 ;
+ RECT 161.350000 1902.040000 162.350000 1902.520000 ;
+ RECT 165.015000 1885.720000 166.280000 1886.200000 ;
+ RECT 165.015000 1891.160000 166.280000 1891.640000 ;
+ RECT 165.015000 1896.600000 166.280000 1897.080000 ;
+ RECT 161.350000 1885.720000 162.350000 1886.200000 ;
+ RECT 161.350000 1891.160000 162.350000 1891.640000 ;
+ RECT 161.350000 1896.600000 162.350000 1897.080000 ;
+ RECT 165.015000 1880.280000 166.280000 1880.760000 ;
+ RECT 165.015000 1874.840000 166.280000 1875.320000 ;
+ RECT 161.350000 1880.280000 162.350000 1880.760000 ;
+ RECT 161.350000 1874.840000 162.350000 1875.320000 ;
+ RECT 165.015000 1869.400000 166.280000 1869.880000 ;
+ RECT 165.015000 1863.960000 166.280000 1864.440000 ;
+ RECT 161.350000 1863.960000 162.350000 1864.440000 ;
+ RECT 161.350000 1869.400000 162.350000 1869.880000 ;
+ RECT 165.015000 1858.520000 166.280000 1859.000000 ;
+ RECT 165.015000 1853.080000 166.280000 1853.560000 ;
+ RECT 161.350000 1858.520000 162.350000 1859.000000 ;
+ RECT 161.350000 1853.080000 162.350000 1853.560000 ;
+ RECT 237.930000 1836.760000 238.930000 1837.240000 ;
+ RECT 237.930000 1842.200000 238.930000 1842.680000 ;
+ RECT 237.930000 1831.320000 238.930000 1831.800000 ;
+ RECT 237.930000 1825.880000 238.930000 1826.360000 ;
+ RECT 210.180000 1842.200000 211.280000 1842.680000 ;
+ RECT 210.180000 1836.760000 211.280000 1837.240000 ;
+ RECT 210.180000 1831.320000 211.280000 1831.800000 ;
+ RECT 210.180000 1825.880000 211.280000 1826.360000 ;
+ RECT 237.930000 1815.000000 238.930000 1815.480000 ;
+ RECT 237.930000 1820.440000 238.930000 1820.920000 ;
+ RECT 237.930000 1809.560000 238.930000 1810.040000 ;
+ RECT 237.930000 1804.120000 238.930000 1804.600000 ;
+ RECT 237.930000 1798.680000 238.930000 1799.160000 ;
+ RECT 210.180000 1820.440000 211.280000 1820.920000 ;
+ RECT 210.180000 1815.000000 211.280000 1815.480000 ;
+ RECT 210.180000 1809.560000 211.280000 1810.040000 ;
+ RECT 210.180000 1798.680000 211.280000 1799.160000 ;
+ RECT 210.180000 1804.120000 211.280000 1804.600000 ;
+ RECT 237.930000 1787.800000 238.930000 1788.280000 ;
+ RECT 237.930000 1793.240000 238.930000 1793.720000 ;
+ RECT 237.930000 1782.360000 238.930000 1782.840000 ;
+ RECT 237.930000 1776.920000 238.930000 1777.400000 ;
+ RECT 210.180000 1793.240000 211.280000 1793.720000 ;
+ RECT 210.180000 1787.800000 211.280000 1788.280000 ;
+ RECT 210.180000 1782.360000 211.280000 1782.840000 ;
+ RECT 210.180000 1776.920000 211.280000 1777.400000 ;
+ RECT 237.930000 1766.040000 238.930000 1766.520000 ;
+ RECT 237.930000 1760.600000 238.930000 1761.080000 ;
+ RECT 237.930000 1771.480000 238.930000 1771.960000 ;
+ RECT 237.930000 1755.160000 238.930000 1755.640000 ;
+ RECT 210.180000 1771.480000 211.280000 1771.960000 ;
+ RECT 210.180000 1766.040000 211.280000 1766.520000 ;
+ RECT 210.180000 1760.600000 211.280000 1761.080000 ;
+ RECT 210.180000 1755.160000 211.280000 1755.640000 ;
+ RECT 165.015000 1842.200000 166.280000 1842.680000 ;
+ RECT 165.015000 1836.760000 166.280000 1837.240000 ;
+ RECT 161.350000 1842.200000 162.350000 1842.680000 ;
+ RECT 161.350000 1836.760000 162.350000 1837.240000 ;
+ RECT 165.015000 1831.320000 166.280000 1831.800000 ;
+ RECT 165.015000 1825.880000 166.280000 1826.360000 ;
+ RECT 161.350000 1825.880000 162.350000 1826.360000 ;
+ RECT 161.350000 1831.320000 162.350000 1831.800000 ;
+ RECT 165.015000 1820.440000 166.280000 1820.920000 ;
+ RECT 165.015000 1815.000000 166.280000 1815.480000 ;
+ RECT 161.350000 1820.440000 162.350000 1820.920000 ;
+ RECT 161.350000 1815.000000 162.350000 1815.480000 ;
+ RECT 165.015000 1798.680000 166.280000 1799.160000 ;
+ RECT 165.015000 1804.120000 166.280000 1804.600000 ;
+ RECT 165.015000 1809.560000 166.280000 1810.040000 ;
+ RECT 161.350000 1798.680000 162.350000 1799.160000 ;
+ RECT 161.350000 1804.120000 162.350000 1804.600000 ;
+ RECT 161.350000 1809.560000 162.350000 1810.040000 ;
+ RECT 165.015000 1793.240000 166.280000 1793.720000 ;
+ RECT 165.015000 1787.800000 166.280000 1788.280000 ;
+ RECT 161.350000 1793.240000 162.350000 1793.720000 ;
+ RECT 161.350000 1787.800000 162.350000 1788.280000 ;
+ RECT 165.015000 1782.360000 166.280000 1782.840000 ;
+ RECT 165.015000 1776.920000 166.280000 1777.400000 ;
+ RECT 161.350000 1782.360000 162.350000 1782.840000 ;
+ RECT 161.350000 1776.920000 162.350000 1777.400000 ;
+ RECT 165.015000 1760.600000 166.280000 1761.080000 ;
+ RECT 165.015000 1766.040000 166.280000 1766.520000 ;
+ RECT 165.015000 1771.480000 166.280000 1771.960000 ;
+ RECT 161.350000 1760.600000 162.350000 1761.080000 ;
+ RECT 161.350000 1766.040000 162.350000 1766.520000 ;
+ RECT 161.350000 1771.480000 162.350000 1771.960000 ;
+ RECT 161.350000 1755.160000 162.350000 1755.640000 ;
+ RECT 165.015000 1755.160000 166.280000 1755.640000 ;
+ RECT 210.180000 1847.640000 211.280000 1848.120000 ;
+ RECT 161.350000 1847.640000 162.350000 1848.120000 ;
+ RECT 165.015000 1847.640000 166.280000 1848.120000 ;
+ RECT 237.930000 1847.640000 238.930000 1848.120000 ;
+ RECT 160.120000 1944.400000 240.160000 1945.400000 ;
+ RECT 160.120000 1748.830000 240.160000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 1747.580000 162.350000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 1946.840000 162.350000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 1747.580000 238.930000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 1946.840000 238.930000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1748.830000 161.120000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1748.830000 240.160000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1944.400000 161.120000 1945.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1944.400000 240.160000 1945.400000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 165.015000 1739.860000 166.280000 1740.340000 ;
+ RECT 165.015000 1723.540000 166.280000 1724.020000 ;
+ RECT 165.015000 1728.980000 166.280000 1729.460000 ;
+ RECT 165.015000 1734.420000 166.280000 1734.900000 ;
+ RECT 165.015000 1718.100000 166.280000 1718.580000 ;
+ RECT 165.015000 1712.660000 166.280000 1713.140000 ;
+ RECT 165.015000 1707.220000 166.280000 1707.700000 ;
+ RECT 165.015000 1701.780000 166.280000 1702.260000 ;
+ RECT 165.015000 1685.460000 166.280000 1685.940000 ;
+ RECT 165.015000 1690.900000 166.280000 1691.380000 ;
+ RECT 165.015000 1696.340000 166.280000 1696.820000 ;
+ RECT 165.015000 1680.020000 166.280000 1680.500000 ;
+ RECT 165.015000 1674.580000 166.280000 1675.060000 ;
+ RECT 165.015000 1669.140000 166.280000 1669.620000 ;
+ RECT 165.015000 1663.700000 166.280000 1664.180000 ;
+ RECT 165.015000 1658.260000 166.280000 1658.740000 ;
+ RECT 165.015000 1652.820000 166.280000 1653.300000 ;
+ RECT 165.015000 1641.940000 166.280000 1642.420000 ;
+ RECT 165.015000 1636.500000 166.280000 1636.980000 ;
+ RECT 165.015000 1631.060000 166.280000 1631.540000 ;
+ RECT 165.015000 1625.620000 166.280000 1626.100000 ;
+ RECT 165.015000 1620.180000 166.280000 1620.660000 ;
+ RECT 165.015000 1614.740000 166.280000 1615.220000 ;
+ RECT 165.015000 1598.420000 166.280000 1598.900000 ;
+ RECT 165.015000 1603.860000 166.280000 1604.340000 ;
+ RECT 165.015000 1609.300000 166.280000 1609.780000 ;
+ RECT 165.015000 1592.980000 166.280000 1593.460000 ;
+ RECT 165.015000 1587.540000 166.280000 1588.020000 ;
+ RECT 165.015000 1582.100000 166.280000 1582.580000 ;
+ RECT 165.015000 1576.660000 166.280000 1577.140000 ;
+ RECT 165.015000 1560.340000 166.280000 1560.820000 ;
+ RECT 165.015000 1565.780000 166.280000 1566.260000 ;
+ RECT 165.015000 1571.220000 166.280000 1571.700000 ;
+ RECT 165.015000 1554.900000 166.280000 1555.380000 ;
+ RECT 165.015000 1647.380000 166.280000 1647.860000 ;
+ RECT 161.350000 1547.320000 162.350000 1747.580000 ;
+ RECT 237.930000 1547.320000 238.930000 1747.580000 ;
+ RECT 165.180000 1548.570000 166.280000 1745.140000 ;
+ RECT 210.180000 1548.570000 211.280000 1745.140000 ;
+ LAYER met3 ;
+ RECT 237.930000 1739.860000 238.930000 1740.340000 ;
+ RECT 237.930000 1734.420000 238.930000 1734.900000 ;
+ RECT 237.930000 1728.980000 238.930000 1729.460000 ;
+ RECT 237.930000 1723.540000 238.930000 1724.020000 ;
+ RECT 210.180000 1739.860000 211.280000 1740.340000 ;
+ RECT 210.180000 1734.420000 211.280000 1734.900000 ;
+ RECT 210.180000 1728.980000 211.280000 1729.460000 ;
+ RECT 210.180000 1723.540000 211.280000 1724.020000 ;
+ RECT 237.930000 1712.660000 238.930000 1713.140000 ;
+ RECT 237.930000 1718.100000 238.930000 1718.580000 ;
+ RECT 237.930000 1707.220000 238.930000 1707.700000 ;
+ RECT 237.930000 1701.780000 238.930000 1702.260000 ;
+ RECT 210.180000 1718.100000 211.280000 1718.580000 ;
+ RECT 210.180000 1712.660000 211.280000 1713.140000 ;
+ RECT 210.180000 1707.220000 211.280000 1707.700000 ;
+ RECT 210.180000 1701.780000 211.280000 1702.260000 ;
+ RECT 237.930000 1690.900000 238.930000 1691.380000 ;
+ RECT 237.930000 1685.460000 238.930000 1685.940000 ;
+ RECT 237.930000 1696.340000 238.930000 1696.820000 ;
+ RECT 237.930000 1680.020000 238.930000 1680.500000 ;
+ RECT 237.930000 1674.580000 238.930000 1675.060000 ;
+ RECT 210.180000 1696.340000 211.280000 1696.820000 ;
+ RECT 210.180000 1690.900000 211.280000 1691.380000 ;
+ RECT 210.180000 1685.460000 211.280000 1685.940000 ;
+ RECT 210.180000 1680.020000 211.280000 1680.500000 ;
+ RECT 210.180000 1674.580000 211.280000 1675.060000 ;
+ RECT 237.930000 1663.700000 238.930000 1664.180000 ;
+ RECT 237.930000 1669.140000 238.930000 1669.620000 ;
+ RECT 237.930000 1658.260000 238.930000 1658.740000 ;
+ RECT 237.930000 1652.820000 238.930000 1653.300000 ;
+ RECT 210.180000 1669.140000 211.280000 1669.620000 ;
+ RECT 210.180000 1663.700000 211.280000 1664.180000 ;
+ RECT 210.180000 1652.820000 211.280000 1653.300000 ;
+ RECT 210.180000 1658.260000 211.280000 1658.740000 ;
+ RECT 161.350000 1739.860000 162.350000 1740.340000 ;
+ RECT 165.015000 1739.860000 166.280000 1740.340000 ;
+ RECT 165.015000 1723.540000 166.280000 1724.020000 ;
+ RECT 165.015000 1728.980000 166.280000 1729.460000 ;
+ RECT 165.015000 1734.420000 166.280000 1734.900000 ;
+ RECT 161.350000 1723.540000 162.350000 1724.020000 ;
+ RECT 161.350000 1728.980000 162.350000 1729.460000 ;
+ RECT 161.350000 1734.420000 162.350000 1734.900000 ;
+ RECT 165.015000 1718.100000 166.280000 1718.580000 ;
+ RECT 165.015000 1712.660000 166.280000 1713.140000 ;
+ RECT 161.350000 1718.100000 162.350000 1718.580000 ;
+ RECT 161.350000 1712.660000 162.350000 1713.140000 ;
+ RECT 165.015000 1707.220000 166.280000 1707.700000 ;
+ RECT 165.015000 1701.780000 166.280000 1702.260000 ;
+ RECT 161.350000 1707.220000 162.350000 1707.700000 ;
+ RECT 161.350000 1701.780000 162.350000 1702.260000 ;
+ RECT 165.015000 1685.460000 166.280000 1685.940000 ;
+ RECT 165.015000 1690.900000 166.280000 1691.380000 ;
+ RECT 165.015000 1696.340000 166.280000 1696.820000 ;
+ RECT 161.350000 1685.460000 162.350000 1685.940000 ;
+ RECT 161.350000 1690.900000 162.350000 1691.380000 ;
+ RECT 161.350000 1696.340000 162.350000 1696.820000 ;
+ RECT 165.015000 1680.020000 166.280000 1680.500000 ;
+ RECT 165.015000 1674.580000 166.280000 1675.060000 ;
+ RECT 161.350000 1680.020000 162.350000 1680.500000 ;
+ RECT 161.350000 1674.580000 162.350000 1675.060000 ;
+ RECT 165.015000 1669.140000 166.280000 1669.620000 ;
+ RECT 165.015000 1663.700000 166.280000 1664.180000 ;
+ RECT 161.350000 1663.700000 162.350000 1664.180000 ;
+ RECT 161.350000 1669.140000 162.350000 1669.620000 ;
+ RECT 165.015000 1658.260000 166.280000 1658.740000 ;
+ RECT 165.015000 1652.820000 166.280000 1653.300000 ;
+ RECT 161.350000 1658.260000 162.350000 1658.740000 ;
+ RECT 161.350000 1652.820000 162.350000 1653.300000 ;
+ RECT 237.930000 1636.500000 238.930000 1636.980000 ;
+ RECT 237.930000 1641.940000 238.930000 1642.420000 ;
+ RECT 237.930000 1631.060000 238.930000 1631.540000 ;
+ RECT 237.930000 1625.620000 238.930000 1626.100000 ;
+ RECT 210.180000 1641.940000 211.280000 1642.420000 ;
+ RECT 210.180000 1636.500000 211.280000 1636.980000 ;
+ RECT 210.180000 1631.060000 211.280000 1631.540000 ;
+ RECT 210.180000 1625.620000 211.280000 1626.100000 ;
+ RECT 237.930000 1614.740000 238.930000 1615.220000 ;
+ RECT 237.930000 1620.180000 238.930000 1620.660000 ;
+ RECT 237.930000 1609.300000 238.930000 1609.780000 ;
+ RECT 237.930000 1603.860000 238.930000 1604.340000 ;
+ RECT 237.930000 1598.420000 238.930000 1598.900000 ;
+ RECT 210.180000 1620.180000 211.280000 1620.660000 ;
+ RECT 210.180000 1614.740000 211.280000 1615.220000 ;
+ RECT 210.180000 1609.300000 211.280000 1609.780000 ;
+ RECT 210.180000 1598.420000 211.280000 1598.900000 ;
+ RECT 210.180000 1603.860000 211.280000 1604.340000 ;
+ RECT 237.930000 1587.540000 238.930000 1588.020000 ;
+ RECT 237.930000 1592.980000 238.930000 1593.460000 ;
+ RECT 237.930000 1582.100000 238.930000 1582.580000 ;
+ RECT 237.930000 1576.660000 238.930000 1577.140000 ;
+ RECT 210.180000 1592.980000 211.280000 1593.460000 ;
+ RECT 210.180000 1587.540000 211.280000 1588.020000 ;
+ RECT 210.180000 1582.100000 211.280000 1582.580000 ;
+ RECT 210.180000 1576.660000 211.280000 1577.140000 ;
+ RECT 237.930000 1565.780000 238.930000 1566.260000 ;
+ RECT 237.930000 1560.340000 238.930000 1560.820000 ;
+ RECT 237.930000 1571.220000 238.930000 1571.700000 ;
+ RECT 237.930000 1554.900000 238.930000 1555.380000 ;
+ RECT 210.180000 1571.220000 211.280000 1571.700000 ;
+ RECT 210.180000 1565.780000 211.280000 1566.260000 ;
+ RECT 210.180000 1560.340000 211.280000 1560.820000 ;
+ RECT 210.180000 1554.900000 211.280000 1555.380000 ;
+ RECT 165.015000 1641.940000 166.280000 1642.420000 ;
+ RECT 165.015000 1636.500000 166.280000 1636.980000 ;
+ RECT 161.350000 1641.940000 162.350000 1642.420000 ;
+ RECT 161.350000 1636.500000 162.350000 1636.980000 ;
+ RECT 165.015000 1631.060000 166.280000 1631.540000 ;
+ RECT 165.015000 1625.620000 166.280000 1626.100000 ;
+ RECT 161.350000 1625.620000 162.350000 1626.100000 ;
+ RECT 161.350000 1631.060000 162.350000 1631.540000 ;
+ RECT 165.015000 1620.180000 166.280000 1620.660000 ;
+ RECT 165.015000 1614.740000 166.280000 1615.220000 ;
+ RECT 161.350000 1620.180000 162.350000 1620.660000 ;
+ RECT 161.350000 1614.740000 162.350000 1615.220000 ;
+ RECT 165.015000 1598.420000 166.280000 1598.900000 ;
+ RECT 165.015000 1603.860000 166.280000 1604.340000 ;
+ RECT 165.015000 1609.300000 166.280000 1609.780000 ;
+ RECT 161.350000 1598.420000 162.350000 1598.900000 ;
+ RECT 161.350000 1603.860000 162.350000 1604.340000 ;
+ RECT 161.350000 1609.300000 162.350000 1609.780000 ;
+ RECT 165.015000 1592.980000 166.280000 1593.460000 ;
+ RECT 165.015000 1587.540000 166.280000 1588.020000 ;
+ RECT 161.350000 1592.980000 162.350000 1593.460000 ;
+ RECT 161.350000 1587.540000 162.350000 1588.020000 ;
+ RECT 165.015000 1582.100000 166.280000 1582.580000 ;
+ RECT 165.015000 1576.660000 166.280000 1577.140000 ;
+ RECT 161.350000 1582.100000 162.350000 1582.580000 ;
+ RECT 161.350000 1576.660000 162.350000 1577.140000 ;
+ RECT 165.015000 1560.340000 166.280000 1560.820000 ;
+ RECT 165.015000 1565.780000 166.280000 1566.260000 ;
+ RECT 165.015000 1571.220000 166.280000 1571.700000 ;
+ RECT 161.350000 1560.340000 162.350000 1560.820000 ;
+ RECT 161.350000 1565.780000 162.350000 1566.260000 ;
+ RECT 161.350000 1571.220000 162.350000 1571.700000 ;
+ RECT 161.350000 1554.900000 162.350000 1555.380000 ;
+ RECT 165.015000 1554.900000 166.280000 1555.380000 ;
+ RECT 210.180000 1647.380000 211.280000 1647.860000 ;
+ RECT 161.350000 1647.380000 162.350000 1647.860000 ;
+ RECT 165.015000 1647.380000 166.280000 1647.860000 ;
+ RECT 237.930000 1647.380000 238.930000 1647.860000 ;
+ RECT 160.120000 1744.140000 240.160000 1745.140000 ;
+ RECT 160.120000 1548.570000 240.160000 1549.570000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 1547.320000 162.350000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 161.350000 1746.580000 162.350000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 1547.320000 238.930000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 237.930000 1746.580000 238.930000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1548.570000 161.120000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1548.570000 240.160000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1744.140000 161.120000 1745.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1744.140000 240.160000 1745.140000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'N_term_RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 3373.560000 2057.220000 3374.040000 ;
+ RECT 2055.955000 3368.120000 2057.220000 3368.600000 ;
+ RECT 2055.955000 3362.680000 2057.220000 3363.160000 ;
+ RECT 2055.955000 3357.240000 2057.220000 3357.720000 ;
+ RECT 2052.290000 3349.660000 2053.290000 3379.920000 ;
+ RECT 2158.770000 3349.660000 2159.770000 3379.920000 ;
+ RECT 2056.120000 3350.910000 2057.220000 3378.160000 ;
+ RECT 2101.120000 3350.910000 2102.220000 3378.160000 ;
+ RECT 2146.120000 3350.910000 2147.220000 3378.160000 ;
+ LAYER met3 ;
+ RECT 2158.770000 3373.560000 2159.770000 3374.040000 ;
+ RECT 2158.770000 3368.120000 2159.770000 3368.600000 ;
+ RECT 2146.120000 3373.560000 2147.220000 3374.040000 ;
+ RECT 2146.120000 3368.120000 2147.220000 3368.600000 ;
+ RECT 2101.120000 3368.120000 2102.220000 3368.600000 ;
+ RECT 2101.120000 3373.560000 2102.220000 3374.040000 ;
+ RECT 2052.290000 3373.560000 2053.290000 3374.040000 ;
+ RECT 2055.955000 3373.560000 2057.220000 3374.040000 ;
+ RECT 2055.955000 3368.120000 2057.220000 3368.600000 ;
+ RECT 2052.290000 3368.120000 2053.290000 3368.600000 ;
+ RECT 2158.770000 3362.680000 2159.770000 3363.160000 ;
+ RECT 2158.770000 3357.240000 2159.770000 3357.720000 ;
+ RECT 2146.120000 3362.680000 2147.220000 3363.160000 ;
+ RECT 2146.120000 3357.240000 2147.220000 3357.720000 ;
+ RECT 2101.120000 3357.240000 2102.220000 3357.720000 ;
+ RECT 2101.120000 3362.680000 2102.220000 3363.160000 ;
+ RECT 2055.955000 3362.680000 2057.220000 3363.160000 ;
+ RECT 2052.290000 3362.680000 2053.290000 3363.160000 ;
+ RECT 2055.955000 3357.240000 2057.220000 3357.720000 ;
+ RECT 2052.290000 3357.240000 2053.290000 3357.720000 ;
+ RECT 2051.060000 3377.160000 2161.000000 3378.160000 ;
+ RECT 2051.060000 3350.910000 2161.000000 3351.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 3349.660000 2053.290000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 3378.920000 2053.290000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 3349.660000 2159.770000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 3378.920000 2159.770000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 3350.910000 2052.060000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 3350.910000 2161.000000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 3377.160000 2052.060000 3378.160000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 3377.160000 2161.000000 3378.160000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 1534.160000 2057.220000 1534.640000 ;
+ RECT 2055.955000 1528.720000 2057.220000 1529.200000 ;
+ RECT 2055.955000 1523.280000 2057.220000 1523.760000 ;
+ RECT 2055.955000 1539.600000 2057.220000 1540.080000 ;
+ RECT 2055.955000 1517.840000 2057.220000 1518.320000 ;
+ RECT 2055.955000 1512.400000 2057.220000 1512.880000 ;
+ RECT 2055.955000 1506.960000 2057.220000 1507.440000 ;
+ RECT 2055.955000 1501.520000 2057.220000 1502.000000 ;
+ RECT 2055.955000 1485.200000 2057.220000 1485.680000 ;
+ RECT 2055.955000 1479.760000 2057.220000 1480.240000 ;
+ RECT 2055.955000 1474.320000 2057.220000 1474.800000 ;
+ RECT 2055.955000 1490.640000 2057.220000 1491.120000 ;
+ RECT 2055.955000 1496.080000 2057.220000 1496.560000 ;
+ RECT 2055.955000 1468.880000 2057.220000 1469.360000 ;
+ RECT 2055.955000 1463.440000 2057.220000 1463.920000 ;
+ RECT 2055.955000 1458.000000 2057.220000 1458.480000 ;
+ RECT 2055.955000 1452.560000 2057.220000 1453.040000 ;
+ RECT 2055.955000 1430.800000 2057.220000 1431.280000 ;
+ RECT 2055.955000 1425.360000 2057.220000 1425.840000 ;
+ RECT 2055.955000 1436.240000 2057.220000 1436.720000 ;
+ RECT 2055.955000 1441.680000 2057.220000 1442.160000 ;
+ RECT 2055.955000 1419.920000 2057.220000 1420.400000 ;
+ RECT 2055.955000 1414.480000 2057.220000 1414.960000 ;
+ RECT 2055.955000 1409.040000 2057.220000 1409.520000 ;
+ RECT 2055.955000 1403.600000 2057.220000 1404.080000 ;
+ RECT 2055.955000 1398.160000 2057.220000 1398.640000 ;
+ RECT 2055.955000 1387.280000 2057.220000 1387.760000 ;
+ RECT 2055.955000 1381.840000 2057.220000 1382.320000 ;
+ RECT 2055.955000 1376.400000 2057.220000 1376.880000 ;
+ RECT 2055.955000 1392.720000 2057.220000 1393.200000 ;
+ RECT 2055.955000 1370.960000 2057.220000 1371.440000 ;
+ RECT 2055.955000 1365.520000 2057.220000 1366.000000 ;
+ RECT 2055.955000 1360.080000 2057.220000 1360.560000 ;
+ RECT 2055.955000 1354.640000 2057.220000 1355.120000 ;
+ RECT 2055.955000 1447.120000 2057.220000 1447.600000 ;
+ RECT 2052.290000 1347.060000 2053.290000 1547.320000 ;
+ RECT 2158.770000 1347.060000 2159.770000 1547.320000 ;
+ RECT 2056.120000 1348.310000 2057.220000 1544.880000 ;
+ RECT 2101.120000 1348.310000 2102.220000 1544.880000 ;
+ RECT 2146.120000 1348.310000 2147.220000 1544.880000 ;
+ LAYER met3 ;
+ RECT 2158.770000 1523.280000 2159.770000 1523.760000 ;
+ RECT 2158.770000 1528.720000 2159.770000 1529.200000 ;
+ RECT 2158.770000 1534.160000 2159.770000 1534.640000 ;
+ RECT 2158.770000 1539.600000 2159.770000 1540.080000 ;
+ RECT 2158.770000 1506.960000 2159.770000 1507.440000 ;
+ RECT 2158.770000 1501.520000 2159.770000 1502.000000 ;
+ RECT 2158.770000 1512.400000 2159.770000 1512.880000 ;
+ RECT 2158.770000 1517.840000 2159.770000 1518.320000 ;
+ RECT 2146.120000 1523.280000 2147.220000 1523.760000 ;
+ RECT 2146.120000 1528.720000 2147.220000 1529.200000 ;
+ RECT 2146.120000 1534.160000 2147.220000 1534.640000 ;
+ RECT 2146.120000 1539.600000 2147.220000 1540.080000 ;
+ RECT 2146.120000 1506.960000 2147.220000 1507.440000 ;
+ RECT 2146.120000 1501.520000 2147.220000 1502.000000 ;
+ RECT 2146.120000 1512.400000 2147.220000 1512.880000 ;
+ RECT 2146.120000 1517.840000 2147.220000 1518.320000 ;
+ RECT 2158.770000 1474.320000 2159.770000 1474.800000 ;
+ RECT 2158.770000 1479.760000 2159.770000 1480.240000 ;
+ RECT 2158.770000 1485.200000 2159.770000 1485.680000 ;
+ RECT 2158.770000 1490.640000 2159.770000 1491.120000 ;
+ RECT 2158.770000 1496.080000 2159.770000 1496.560000 ;
+ RECT 2158.770000 1452.560000 2159.770000 1453.040000 ;
+ RECT 2158.770000 1458.000000 2159.770000 1458.480000 ;
+ RECT 2158.770000 1463.440000 2159.770000 1463.920000 ;
+ RECT 2158.770000 1468.880000 2159.770000 1469.360000 ;
+ RECT 2146.120000 1474.320000 2147.220000 1474.800000 ;
+ RECT 2146.120000 1479.760000 2147.220000 1480.240000 ;
+ RECT 2146.120000 1485.200000 2147.220000 1485.680000 ;
+ RECT 2146.120000 1490.640000 2147.220000 1491.120000 ;
+ RECT 2146.120000 1496.080000 2147.220000 1496.560000 ;
+ RECT 2146.120000 1458.000000 2147.220000 1458.480000 ;
+ RECT 2146.120000 1452.560000 2147.220000 1453.040000 ;
+ RECT 2146.120000 1463.440000 2147.220000 1463.920000 ;
+ RECT 2146.120000 1468.880000 2147.220000 1469.360000 ;
+ RECT 2101.120000 1528.720000 2102.220000 1529.200000 ;
+ RECT 2101.120000 1523.280000 2102.220000 1523.760000 ;
+ RECT 2101.120000 1534.160000 2102.220000 1534.640000 ;
+ RECT 2101.120000 1539.600000 2102.220000 1540.080000 ;
+ RECT 2101.120000 1501.520000 2102.220000 1502.000000 ;
+ RECT 2101.120000 1506.960000 2102.220000 1507.440000 ;
+ RECT 2101.120000 1512.400000 2102.220000 1512.880000 ;
+ RECT 2101.120000 1517.840000 2102.220000 1518.320000 ;
+ RECT 2052.290000 1523.280000 2053.290000 1523.760000 ;
+ RECT 2052.290000 1528.720000 2053.290000 1529.200000 ;
+ RECT 2052.290000 1534.160000 2053.290000 1534.640000 ;
+ RECT 2052.290000 1539.600000 2053.290000 1540.080000 ;
+ RECT 2052.290000 1506.960000 2053.290000 1507.440000 ;
+ RECT 2052.290000 1501.520000 2053.290000 1502.000000 ;
+ RECT 2052.290000 1512.400000 2053.290000 1512.880000 ;
+ RECT 2052.290000 1517.840000 2053.290000 1518.320000 ;
+ RECT 2055.955000 1534.160000 2057.220000 1534.640000 ;
+ RECT 2055.955000 1528.720000 2057.220000 1529.200000 ;
+ RECT 2055.955000 1523.280000 2057.220000 1523.760000 ;
+ RECT 2055.955000 1539.600000 2057.220000 1540.080000 ;
+ RECT 2055.955000 1517.840000 2057.220000 1518.320000 ;
+ RECT 2055.955000 1512.400000 2057.220000 1512.880000 ;
+ RECT 2055.955000 1506.960000 2057.220000 1507.440000 ;
+ RECT 2055.955000 1501.520000 2057.220000 1502.000000 ;
+ RECT 2101.120000 1474.320000 2102.220000 1474.800000 ;
+ RECT 2101.120000 1479.760000 2102.220000 1480.240000 ;
+ RECT 2101.120000 1485.200000 2102.220000 1485.680000 ;
+ RECT 2101.120000 1490.640000 2102.220000 1491.120000 ;
+ RECT 2101.120000 1496.080000 2102.220000 1496.560000 ;
+ RECT 2101.120000 1452.560000 2102.220000 1453.040000 ;
+ RECT 2101.120000 1458.000000 2102.220000 1458.480000 ;
+ RECT 2101.120000 1463.440000 2102.220000 1463.920000 ;
+ RECT 2101.120000 1468.880000 2102.220000 1469.360000 ;
+ RECT 2052.290000 1474.320000 2053.290000 1474.800000 ;
+ RECT 2052.290000 1479.760000 2053.290000 1480.240000 ;
+ RECT 2052.290000 1485.200000 2053.290000 1485.680000 ;
+ RECT 2052.290000 1490.640000 2053.290000 1491.120000 ;
+ RECT 2052.290000 1496.080000 2053.290000 1496.560000 ;
+ RECT 2052.290000 1452.560000 2053.290000 1453.040000 ;
+ RECT 2052.290000 1458.000000 2053.290000 1458.480000 ;
+ RECT 2052.290000 1463.440000 2053.290000 1463.920000 ;
+ RECT 2052.290000 1468.880000 2053.290000 1469.360000 ;
+ RECT 2055.955000 1485.200000 2057.220000 1485.680000 ;
+ RECT 2055.955000 1479.760000 2057.220000 1480.240000 ;
+ RECT 2055.955000 1474.320000 2057.220000 1474.800000 ;
+ RECT 2055.955000 1490.640000 2057.220000 1491.120000 ;
+ RECT 2055.955000 1496.080000 2057.220000 1496.560000 ;
+ RECT 2055.955000 1468.880000 2057.220000 1469.360000 ;
+ RECT 2055.955000 1463.440000 2057.220000 1463.920000 ;
+ RECT 2055.955000 1458.000000 2057.220000 1458.480000 ;
+ RECT 2055.955000 1452.560000 2057.220000 1453.040000 ;
+ RECT 2158.770000 1425.360000 2159.770000 1425.840000 ;
+ RECT 2158.770000 1430.800000 2159.770000 1431.280000 ;
+ RECT 2158.770000 1436.240000 2159.770000 1436.720000 ;
+ RECT 2158.770000 1441.680000 2159.770000 1442.160000 ;
+ RECT 2158.770000 1398.160000 2159.770000 1398.640000 ;
+ RECT 2158.770000 1403.600000 2159.770000 1404.080000 ;
+ RECT 2158.770000 1409.040000 2159.770000 1409.520000 ;
+ RECT 2158.770000 1414.480000 2159.770000 1414.960000 ;
+ RECT 2158.770000 1419.920000 2159.770000 1420.400000 ;
+ RECT 2146.120000 1425.360000 2147.220000 1425.840000 ;
+ RECT 2146.120000 1430.800000 2147.220000 1431.280000 ;
+ RECT 2146.120000 1436.240000 2147.220000 1436.720000 ;
+ RECT 2146.120000 1441.680000 2147.220000 1442.160000 ;
+ RECT 2146.120000 1403.600000 2147.220000 1404.080000 ;
+ RECT 2146.120000 1398.160000 2147.220000 1398.640000 ;
+ RECT 2146.120000 1409.040000 2147.220000 1409.520000 ;
+ RECT 2146.120000 1414.480000 2147.220000 1414.960000 ;
+ RECT 2146.120000 1419.920000 2147.220000 1420.400000 ;
+ RECT 2158.770000 1376.400000 2159.770000 1376.880000 ;
+ RECT 2158.770000 1381.840000 2159.770000 1382.320000 ;
+ RECT 2158.770000 1387.280000 2159.770000 1387.760000 ;
+ RECT 2158.770000 1392.720000 2159.770000 1393.200000 ;
+ RECT 2158.770000 1354.640000 2159.770000 1355.120000 ;
+ RECT 2158.770000 1360.080000 2159.770000 1360.560000 ;
+ RECT 2158.770000 1365.520000 2159.770000 1366.000000 ;
+ RECT 2158.770000 1370.960000 2159.770000 1371.440000 ;
+ RECT 2146.120000 1376.400000 2147.220000 1376.880000 ;
+ RECT 2146.120000 1381.840000 2147.220000 1382.320000 ;
+ RECT 2146.120000 1387.280000 2147.220000 1387.760000 ;
+ RECT 2146.120000 1392.720000 2147.220000 1393.200000 ;
+ RECT 2146.120000 1354.640000 2147.220000 1355.120000 ;
+ RECT 2146.120000 1360.080000 2147.220000 1360.560000 ;
+ RECT 2146.120000 1365.520000 2147.220000 1366.000000 ;
+ RECT 2146.120000 1370.960000 2147.220000 1371.440000 ;
+ RECT 2101.120000 1425.360000 2102.220000 1425.840000 ;
+ RECT 2101.120000 1430.800000 2102.220000 1431.280000 ;
+ RECT 2101.120000 1436.240000 2102.220000 1436.720000 ;
+ RECT 2101.120000 1441.680000 2102.220000 1442.160000 ;
+ RECT 2101.120000 1398.160000 2102.220000 1398.640000 ;
+ RECT 2101.120000 1403.600000 2102.220000 1404.080000 ;
+ RECT 2101.120000 1409.040000 2102.220000 1409.520000 ;
+ RECT 2101.120000 1414.480000 2102.220000 1414.960000 ;
+ RECT 2101.120000 1419.920000 2102.220000 1420.400000 ;
+ RECT 2052.290000 1425.360000 2053.290000 1425.840000 ;
+ RECT 2052.290000 1430.800000 2053.290000 1431.280000 ;
+ RECT 2052.290000 1436.240000 2053.290000 1436.720000 ;
+ RECT 2052.290000 1441.680000 2053.290000 1442.160000 ;
+ RECT 2052.290000 1398.160000 2053.290000 1398.640000 ;
+ RECT 2052.290000 1403.600000 2053.290000 1404.080000 ;
+ RECT 2052.290000 1409.040000 2053.290000 1409.520000 ;
+ RECT 2052.290000 1414.480000 2053.290000 1414.960000 ;
+ RECT 2052.290000 1419.920000 2053.290000 1420.400000 ;
+ RECT 2055.955000 1430.800000 2057.220000 1431.280000 ;
+ RECT 2055.955000 1425.360000 2057.220000 1425.840000 ;
+ RECT 2055.955000 1436.240000 2057.220000 1436.720000 ;
+ RECT 2055.955000 1441.680000 2057.220000 1442.160000 ;
+ RECT 2055.955000 1419.920000 2057.220000 1420.400000 ;
+ RECT 2055.955000 1414.480000 2057.220000 1414.960000 ;
+ RECT 2055.955000 1409.040000 2057.220000 1409.520000 ;
+ RECT 2055.955000 1403.600000 2057.220000 1404.080000 ;
+ RECT 2055.955000 1398.160000 2057.220000 1398.640000 ;
+ RECT 2101.120000 1376.400000 2102.220000 1376.880000 ;
+ RECT 2101.120000 1381.840000 2102.220000 1382.320000 ;
+ RECT 2101.120000 1387.280000 2102.220000 1387.760000 ;
+ RECT 2101.120000 1392.720000 2102.220000 1393.200000 ;
+ RECT 2101.120000 1354.640000 2102.220000 1355.120000 ;
+ RECT 2101.120000 1360.080000 2102.220000 1360.560000 ;
+ RECT 2101.120000 1365.520000 2102.220000 1366.000000 ;
+ RECT 2101.120000 1370.960000 2102.220000 1371.440000 ;
+ RECT 2052.290000 1376.400000 2053.290000 1376.880000 ;
+ RECT 2052.290000 1381.840000 2053.290000 1382.320000 ;
+ RECT 2052.290000 1387.280000 2053.290000 1387.760000 ;
+ RECT 2052.290000 1392.720000 2053.290000 1393.200000 ;
+ RECT 2052.290000 1354.640000 2053.290000 1355.120000 ;
+ RECT 2052.290000 1360.080000 2053.290000 1360.560000 ;
+ RECT 2052.290000 1365.520000 2053.290000 1366.000000 ;
+ RECT 2052.290000 1370.960000 2053.290000 1371.440000 ;
+ RECT 2055.955000 1387.280000 2057.220000 1387.760000 ;
+ RECT 2055.955000 1381.840000 2057.220000 1382.320000 ;
+ RECT 2055.955000 1376.400000 2057.220000 1376.880000 ;
+ RECT 2055.955000 1392.720000 2057.220000 1393.200000 ;
+ RECT 2055.955000 1370.960000 2057.220000 1371.440000 ;
+ RECT 2055.955000 1365.520000 2057.220000 1366.000000 ;
+ RECT 2055.955000 1360.080000 2057.220000 1360.560000 ;
+ RECT 2055.955000 1354.640000 2057.220000 1355.120000 ;
+ RECT 2146.120000 1447.120000 2147.220000 1447.600000 ;
+ RECT 2101.120000 1447.120000 2102.220000 1447.600000 ;
+ RECT 2052.290000 1447.120000 2053.290000 1447.600000 ;
+ RECT 2055.955000 1447.120000 2057.220000 1447.600000 ;
+ RECT 2158.770000 1447.120000 2159.770000 1447.600000 ;
+ RECT 2051.060000 1543.880000 2161.000000 1544.880000 ;
+ RECT 2051.060000 1348.310000 2161.000000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 1347.060000 2053.290000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 1546.320000 2053.290000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 1347.060000 2159.770000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 1546.320000 2159.770000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1348.310000 2052.060000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1348.310000 2161.000000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1543.880000 2052.060000 1544.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1543.880000 2161.000000 1544.880000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 1333.900000 2057.220000 1334.380000 ;
+ RECT 2055.955000 1328.460000 2057.220000 1328.940000 ;
+ RECT 2055.955000 1323.020000 2057.220000 1323.500000 ;
+ RECT 2055.955000 1339.340000 2057.220000 1339.820000 ;
+ RECT 2055.955000 1317.580000 2057.220000 1318.060000 ;
+ RECT 2055.955000 1312.140000 2057.220000 1312.620000 ;
+ RECT 2055.955000 1306.700000 2057.220000 1307.180000 ;
+ RECT 2055.955000 1301.260000 2057.220000 1301.740000 ;
+ RECT 2055.955000 1284.940000 2057.220000 1285.420000 ;
+ RECT 2055.955000 1279.500000 2057.220000 1279.980000 ;
+ RECT 2055.955000 1274.060000 2057.220000 1274.540000 ;
+ RECT 2055.955000 1290.380000 2057.220000 1290.860000 ;
+ RECT 2055.955000 1295.820000 2057.220000 1296.300000 ;
+ RECT 2055.955000 1268.620000 2057.220000 1269.100000 ;
+ RECT 2055.955000 1263.180000 2057.220000 1263.660000 ;
+ RECT 2055.955000 1257.740000 2057.220000 1258.220000 ;
+ RECT 2055.955000 1252.300000 2057.220000 1252.780000 ;
+ RECT 2055.955000 1230.540000 2057.220000 1231.020000 ;
+ RECT 2055.955000 1225.100000 2057.220000 1225.580000 ;
+ RECT 2055.955000 1235.980000 2057.220000 1236.460000 ;
+ RECT 2055.955000 1241.420000 2057.220000 1241.900000 ;
+ RECT 2055.955000 1219.660000 2057.220000 1220.140000 ;
+ RECT 2055.955000 1214.220000 2057.220000 1214.700000 ;
+ RECT 2055.955000 1208.780000 2057.220000 1209.260000 ;
+ RECT 2055.955000 1203.340000 2057.220000 1203.820000 ;
+ RECT 2055.955000 1197.900000 2057.220000 1198.380000 ;
+ RECT 2055.955000 1187.020000 2057.220000 1187.500000 ;
+ RECT 2055.955000 1181.580000 2057.220000 1182.060000 ;
+ RECT 2055.955000 1176.140000 2057.220000 1176.620000 ;
+ RECT 2055.955000 1192.460000 2057.220000 1192.940000 ;
+ RECT 2055.955000 1170.700000 2057.220000 1171.180000 ;
+ RECT 2055.955000 1165.260000 2057.220000 1165.740000 ;
+ RECT 2055.955000 1159.820000 2057.220000 1160.300000 ;
+ RECT 2055.955000 1154.380000 2057.220000 1154.860000 ;
+ RECT 2055.955000 1246.860000 2057.220000 1247.340000 ;
+ RECT 2052.290000 1146.800000 2053.290000 1347.060000 ;
+ RECT 2158.770000 1146.800000 2159.770000 1347.060000 ;
+ RECT 2056.120000 1148.050000 2057.220000 1344.620000 ;
+ RECT 2101.120000 1148.050000 2102.220000 1344.620000 ;
+ RECT 2146.120000 1148.050000 2147.220000 1344.620000 ;
+ LAYER met3 ;
+ RECT 2158.770000 1323.020000 2159.770000 1323.500000 ;
+ RECT 2158.770000 1328.460000 2159.770000 1328.940000 ;
+ RECT 2158.770000 1333.900000 2159.770000 1334.380000 ;
+ RECT 2158.770000 1339.340000 2159.770000 1339.820000 ;
+ RECT 2158.770000 1306.700000 2159.770000 1307.180000 ;
+ RECT 2158.770000 1301.260000 2159.770000 1301.740000 ;
+ RECT 2158.770000 1312.140000 2159.770000 1312.620000 ;
+ RECT 2158.770000 1317.580000 2159.770000 1318.060000 ;
+ RECT 2146.120000 1323.020000 2147.220000 1323.500000 ;
+ RECT 2146.120000 1328.460000 2147.220000 1328.940000 ;
+ RECT 2146.120000 1333.900000 2147.220000 1334.380000 ;
+ RECT 2146.120000 1339.340000 2147.220000 1339.820000 ;
+ RECT 2146.120000 1306.700000 2147.220000 1307.180000 ;
+ RECT 2146.120000 1301.260000 2147.220000 1301.740000 ;
+ RECT 2146.120000 1312.140000 2147.220000 1312.620000 ;
+ RECT 2146.120000 1317.580000 2147.220000 1318.060000 ;
+ RECT 2158.770000 1274.060000 2159.770000 1274.540000 ;
+ RECT 2158.770000 1279.500000 2159.770000 1279.980000 ;
+ RECT 2158.770000 1284.940000 2159.770000 1285.420000 ;
+ RECT 2158.770000 1290.380000 2159.770000 1290.860000 ;
+ RECT 2158.770000 1295.820000 2159.770000 1296.300000 ;
+ RECT 2158.770000 1252.300000 2159.770000 1252.780000 ;
+ RECT 2158.770000 1257.740000 2159.770000 1258.220000 ;
+ RECT 2158.770000 1263.180000 2159.770000 1263.660000 ;
+ RECT 2158.770000 1268.620000 2159.770000 1269.100000 ;
+ RECT 2146.120000 1274.060000 2147.220000 1274.540000 ;
+ RECT 2146.120000 1279.500000 2147.220000 1279.980000 ;
+ RECT 2146.120000 1284.940000 2147.220000 1285.420000 ;
+ RECT 2146.120000 1290.380000 2147.220000 1290.860000 ;
+ RECT 2146.120000 1295.820000 2147.220000 1296.300000 ;
+ RECT 2146.120000 1257.740000 2147.220000 1258.220000 ;
+ RECT 2146.120000 1252.300000 2147.220000 1252.780000 ;
+ RECT 2146.120000 1263.180000 2147.220000 1263.660000 ;
+ RECT 2146.120000 1268.620000 2147.220000 1269.100000 ;
+ RECT 2101.120000 1328.460000 2102.220000 1328.940000 ;
+ RECT 2101.120000 1323.020000 2102.220000 1323.500000 ;
+ RECT 2101.120000 1333.900000 2102.220000 1334.380000 ;
+ RECT 2101.120000 1339.340000 2102.220000 1339.820000 ;
+ RECT 2101.120000 1301.260000 2102.220000 1301.740000 ;
+ RECT 2101.120000 1306.700000 2102.220000 1307.180000 ;
+ RECT 2101.120000 1312.140000 2102.220000 1312.620000 ;
+ RECT 2101.120000 1317.580000 2102.220000 1318.060000 ;
+ RECT 2052.290000 1323.020000 2053.290000 1323.500000 ;
+ RECT 2052.290000 1328.460000 2053.290000 1328.940000 ;
+ RECT 2052.290000 1333.900000 2053.290000 1334.380000 ;
+ RECT 2052.290000 1339.340000 2053.290000 1339.820000 ;
+ RECT 2052.290000 1306.700000 2053.290000 1307.180000 ;
+ RECT 2052.290000 1301.260000 2053.290000 1301.740000 ;
+ RECT 2052.290000 1312.140000 2053.290000 1312.620000 ;
+ RECT 2052.290000 1317.580000 2053.290000 1318.060000 ;
+ RECT 2055.955000 1333.900000 2057.220000 1334.380000 ;
+ RECT 2055.955000 1328.460000 2057.220000 1328.940000 ;
+ RECT 2055.955000 1323.020000 2057.220000 1323.500000 ;
+ RECT 2055.955000 1339.340000 2057.220000 1339.820000 ;
+ RECT 2055.955000 1317.580000 2057.220000 1318.060000 ;
+ RECT 2055.955000 1312.140000 2057.220000 1312.620000 ;
+ RECT 2055.955000 1306.700000 2057.220000 1307.180000 ;
+ RECT 2055.955000 1301.260000 2057.220000 1301.740000 ;
+ RECT 2101.120000 1274.060000 2102.220000 1274.540000 ;
+ RECT 2101.120000 1279.500000 2102.220000 1279.980000 ;
+ RECT 2101.120000 1284.940000 2102.220000 1285.420000 ;
+ RECT 2101.120000 1290.380000 2102.220000 1290.860000 ;
+ RECT 2101.120000 1295.820000 2102.220000 1296.300000 ;
+ RECT 2101.120000 1252.300000 2102.220000 1252.780000 ;
+ RECT 2101.120000 1257.740000 2102.220000 1258.220000 ;
+ RECT 2101.120000 1263.180000 2102.220000 1263.660000 ;
+ RECT 2101.120000 1268.620000 2102.220000 1269.100000 ;
+ RECT 2052.290000 1274.060000 2053.290000 1274.540000 ;
+ RECT 2052.290000 1279.500000 2053.290000 1279.980000 ;
+ RECT 2052.290000 1284.940000 2053.290000 1285.420000 ;
+ RECT 2052.290000 1290.380000 2053.290000 1290.860000 ;
+ RECT 2052.290000 1295.820000 2053.290000 1296.300000 ;
+ RECT 2052.290000 1252.300000 2053.290000 1252.780000 ;
+ RECT 2052.290000 1257.740000 2053.290000 1258.220000 ;
+ RECT 2052.290000 1263.180000 2053.290000 1263.660000 ;
+ RECT 2052.290000 1268.620000 2053.290000 1269.100000 ;
+ RECT 2055.955000 1284.940000 2057.220000 1285.420000 ;
+ RECT 2055.955000 1279.500000 2057.220000 1279.980000 ;
+ RECT 2055.955000 1274.060000 2057.220000 1274.540000 ;
+ RECT 2055.955000 1290.380000 2057.220000 1290.860000 ;
+ RECT 2055.955000 1295.820000 2057.220000 1296.300000 ;
+ RECT 2055.955000 1268.620000 2057.220000 1269.100000 ;
+ RECT 2055.955000 1263.180000 2057.220000 1263.660000 ;
+ RECT 2055.955000 1257.740000 2057.220000 1258.220000 ;
+ RECT 2055.955000 1252.300000 2057.220000 1252.780000 ;
+ RECT 2158.770000 1225.100000 2159.770000 1225.580000 ;
+ RECT 2158.770000 1230.540000 2159.770000 1231.020000 ;
+ RECT 2158.770000 1235.980000 2159.770000 1236.460000 ;
+ RECT 2158.770000 1241.420000 2159.770000 1241.900000 ;
+ RECT 2158.770000 1197.900000 2159.770000 1198.380000 ;
+ RECT 2158.770000 1203.340000 2159.770000 1203.820000 ;
+ RECT 2158.770000 1208.780000 2159.770000 1209.260000 ;
+ RECT 2158.770000 1214.220000 2159.770000 1214.700000 ;
+ RECT 2158.770000 1219.660000 2159.770000 1220.140000 ;
+ RECT 2146.120000 1225.100000 2147.220000 1225.580000 ;
+ RECT 2146.120000 1230.540000 2147.220000 1231.020000 ;
+ RECT 2146.120000 1235.980000 2147.220000 1236.460000 ;
+ RECT 2146.120000 1241.420000 2147.220000 1241.900000 ;
+ RECT 2146.120000 1203.340000 2147.220000 1203.820000 ;
+ RECT 2146.120000 1197.900000 2147.220000 1198.380000 ;
+ RECT 2146.120000 1208.780000 2147.220000 1209.260000 ;
+ RECT 2146.120000 1214.220000 2147.220000 1214.700000 ;
+ RECT 2146.120000 1219.660000 2147.220000 1220.140000 ;
+ RECT 2158.770000 1176.140000 2159.770000 1176.620000 ;
+ RECT 2158.770000 1181.580000 2159.770000 1182.060000 ;
+ RECT 2158.770000 1187.020000 2159.770000 1187.500000 ;
+ RECT 2158.770000 1192.460000 2159.770000 1192.940000 ;
+ RECT 2158.770000 1154.380000 2159.770000 1154.860000 ;
+ RECT 2158.770000 1159.820000 2159.770000 1160.300000 ;
+ RECT 2158.770000 1165.260000 2159.770000 1165.740000 ;
+ RECT 2158.770000 1170.700000 2159.770000 1171.180000 ;
+ RECT 2146.120000 1176.140000 2147.220000 1176.620000 ;
+ RECT 2146.120000 1181.580000 2147.220000 1182.060000 ;
+ RECT 2146.120000 1187.020000 2147.220000 1187.500000 ;
+ RECT 2146.120000 1192.460000 2147.220000 1192.940000 ;
+ RECT 2146.120000 1154.380000 2147.220000 1154.860000 ;
+ RECT 2146.120000 1159.820000 2147.220000 1160.300000 ;
+ RECT 2146.120000 1165.260000 2147.220000 1165.740000 ;
+ RECT 2146.120000 1170.700000 2147.220000 1171.180000 ;
+ RECT 2101.120000 1225.100000 2102.220000 1225.580000 ;
+ RECT 2101.120000 1230.540000 2102.220000 1231.020000 ;
+ RECT 2101.120000 1235.980000 2102.220000 1236.460000 ;
+ RECT 2101.120000 1241.420000 2102.220000 1241.900000 ;
+ RECT 2101.120000 1197.900000 2102.220000 1198.380000 ;
+ RECT 2101.120000 1203.340000 2102.220000 1203.820000 ;
+ RECT 2101.120000 1208.780000 2102.220000 1209.260000 ;
+ RECT 2101.120000 1214.220000 2102.220000 1214.700000 ;
+ RECT 2101.120000 1219.660000 2102.220000 1220.140000 ;
+ RECT 2052.290000 1225.100000 2053.290000 1225.580000 ;
+ RECT 2052.290000 1230.540000 2053.290000 1231.020000 ;
+ RECT 2052.290000 1235.980000 2053.290000 1236.460000 ;
+ RECT 2052.290000 1241.420000 2053.290000 1241.900000 ;
+ RECT 2052.290000 1197.900000 2053.290000 1198.380000 ;
+ RECT 2052.290000 1203.340000 2053.290000 1203.820000 ;
+ RECT 2052.290000 1208.780000 2053.290000 1209.260000 ;
+ RECT 2052.290000 1214.220000 2053.290000 1214.700000 ;
+ RECT 2052.290000 1219.660000 2053.290000 1220.140000 ;
+ RECT 2055.955000 1230.540000 2057.220000 1231.020000 ;
+ RECT 2055.955000 1225.100000 2057.220000 1225.580000 ;
+ RECT 2055.955000 1235.980000 2057.220000 1236.460000 ;
+ RECT 2055.955000 1241.420000 2057.220000 1241.900000 ;
+ RECT 2055.955000 1219.660000 2057.220000 1220.140000 ;
+ RECT 2055.955000 1214.220000 2057.220000 1214.700000 ;
+ RECT 2055.955000 1208.780000 2057.220000 1209.260000 ;
+ RECT 2055.955000 1203.340000 2057.220000 1203.820000 ;
+ RECT 2055.955000 1197.900000 2057.220000 1198.380000 ;
+ RECT 2101.120000 1176.140000 2102.220000 1176.620000 ;
+ RECT 2101.120000 1181.580000 2102.220000 1182.060000 ;
+ RECT 2101.120000 1187.020000 2102.220000 1187.500000 ;
+ RECT 2101.120000 1192.460000 2102.220000 1192.940000 ;
+ RECT 2101.120000 1154.380000 2102.220000 1154.860000 ;
+ RECT 2101.120000 1159.820000 2102.220000 1160.300000 ;
+ RECT 2101.120000 1165.260000 2102.220000 1165.740000 ;
+ RECT 2101.120000 1170.700000 2102.220000 1171.180000 ;
+ RECT 2052.290000 1176.140000 2053.290000 1176.620000 ;
+ RECT 2052.290000 1181.580000 2053.290000 1182.060000 ;
+ RECT 2052.290000 1187.020000 2053.290000 1187.500000 ;
+ RECT 2052.290000 1192.460000 2053.290000 1192.940000 ;
+ RECT 2052.290000 1154.380000 2053.290000 1154.860000 ;
+ RECT 2052.290000 1159.820000 2053.290000 1160.300000 ;
+ RECT 2052.290000 1165.260000 2053.290000 1165.740000 ;
+ RECT 2052.290000 1170.700000 2053.290000 1171.180000 ;
+ RECT 2055.955000 1187.020000 2057.220000 1187.500000 ;
+ RECT 2055.955000 1181.580000 2057.220000 1182.060000 ;
+ RECT 2055.955000 1176.140000 2057.220000 1176.620000 ;
+ RECT 2055.955000 1192.460000 2057.220000 1192.940000 ;
+ RECT 2055.955000 1170.700000 2057.220000 1171.180000 ;
+ RECT 2055.955000 1165.260000 2057.220000 1165.740000 ;
+ RECT 2055.955000 1159.820000 2057.220000 1160.300000 ;
+ RECT 2055.955000 1154.380000 2057.220000 1154.860000 ;
+ RECT 2146.120000 1246.860000 2147.220000 1247.340000 ;
+ RECT 2101.120000 1246.860000 2102.220000 1247.340000 ;
+ RECT 2052.290000 1246.860000 2053.290000 1247.340000 ;
+ RECT 2055.955000 1246.860000 2057.220000 1247.340000 ;
+ RECT 2158.770000 1246.860000 2159.770000 1247.340000 ;
+ RECT 2051.060000 1343.620000 2161.000000 1344.620000 ;
+ RECT 2051.060000 1148.050000 2161.000000 1149.050000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 1146.800000 2053.290000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 1346.060000 2053.290000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 1146.800000 2159.770000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 1346.060000 2159.770000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1148.050000 2052.060000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1148.050000 2161.000000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1343.620000 2052.060000 1344.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1343.620000 2161.000000 1344.620000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 1133.640000 2057.220000 1134.120000 ;
+ RECT 2055.955000 1128.200000 2057.220000 1128.680000 ;
+ RECT 2055.955000 1122.760000 2057.220000 1123.240000 ;
+ RECT 2055.955000 1139.080000 2057.220000 1139.560000 ;
+ RECT 2055.955000 1117.320000 2057.220000 1117.800000 ;
+ RECT 2055.955000 1111.880000 2057.220000 1112.360000 ;
+ RECT 2055.955000 1106.440000 2057.220000 1106.920000 ;
+ RECT 2055.955000 1101.000000 2057.220000 1101.480000 ;
+ RECT 2055.955000 1084.680000 2057.220000 1085.160000 ;
+ RECT 2055.955000 1079.240000 2057.220000 1079.720000 ;
+ RECT 2055.955000 1073.800000 2057.220000 1074.280000 ;
+ RECT 2055.955000 1090.120000 2057.220000 1090.600000 ;
+ RECT 2055.955000 1095.560000 2057.220000 1096.040000 ;
+ RECT 2055.955000 1068.360000 2057.220000 1068.840000 ;
+ RECT 2055.955000 1062.920000 2057.220000 1063.400000 ;
+ RECT 2055.955000 1057.480000 2057.220000 1057.960000 ;
+ RECT 2055.955000 1052.040000 2057.220000 1052.520000 ;
+ RECT 2055.955000 1030.280000 2057.220000 1030.760000 ;
+ RECT 2055.955000 1024.840000 2057.220000 1025.320000 ;
+ RECT 2055.955000 1035.720000 2057.220000 1036.200000 ;
+ RECT 2055.955000 1041.160000 2057.220000 1041.640000 ;
+ RECT 2055.955000 1019.400000 2057.220000 1019.880000 ;
+ RECT 2055.955000 1013.960000 2057.220000 1014.440000 ;
+ RECT 2055.955000 1008.520000 2057.220000 1009.000000 ;
+ RECT 2055.955000 1003.080000 2057.220000 1003.560000 ;
+ RECT 2055.955000 997.640000 2057.220000 998.120000 ;
+ RECT 2055.955000 986.760000 2057.220000 987.240000 ;
+ RECT 2055.955000 981.320000 2057.220000 981.800000 ;
+ RECT 2055.955000 975.880000 2057.220000 976.360000 ;
+ RECT 2055.955000 992.200000 2057.220000 992.680000 ;
+ RECT 2055.955000 970.440000 2057.220000 970.920000 ;
+ RECT 2055.955000 965.000000 2057.220000 965.480000 ;
+ RECT 2055.955000 959.560000 2057.220000 960.040000 ;
+ RECT 2055.955000 954.120000 2057.220000 954.600000 ;
+ RECT 2055.955000 1046.600000 2057.220000 1047.080000 ;
+ RECT 2052.290000 946.540000 2053.290000 1146.800000 ;
+ RECT 2158.770000 946.540000 2159.770000 1146.800000 ;
+ RECT 2056.120000 947.790000 2057.220000 1144.360000 ;
+ RECT 2101.120000 947.790000 2102.220000 1144.360000 ;
+ RECT 2146.120000 947.790000 2147.220000 1144.360000 ;
+ LAYER met3 ;
+ RECT 2158.770000 1122.760000 2159.770000 1123.240000 ;
+ RECT 2158.770000 1128.200000 2159.770000 1128.680000 ;
+ RECT 2158.770000 1133.640000 2159.770000 1134.120000 ;
+ RECT 2158.770000 1139.080000 2159.770000 1139.560000 ;
+ RECT 2158.770000 1106.440000 2159.770000 1106.920000 ;
+ RECT 2158.770000 1101.000000 2159.770000 1101.480000 ;
+ RECT 2158.770000 1111.880000 2159.770000 1112.360000 ;
+ RECT 2158.770000 1117.320000 2159.770000 1117.800000 ;
+ RECT 2146.120000 1122.760000 2147.220000 1123.240000 ;
+ RECT 2146.120000 1128.200000 2147.220000 1128.680000 ;
+ RECT 2146.120000 1133.640000 2147.220000 1134.120000 ;
+ RECT 2146.120000 1139.080000 2147.220000 1139.560000 ;
+ RECT 2146.120000 1106.440000 2147.220000 1106.920000 ;
+ RECT 2146.120000 1101.000000 2147.220000 1101.480000 ;
+ RECT 2146.120000 1111.880000 2147.220000 1112.360000 ;
+ RECT 2146.120000 1117.320000 2147.220000 1117.800000 ;
+ RECT 2158.770000 1073.800000 2159.770000 1074.280000 ;
+ RECT 2158.770000 1079.240000 2159.770000 1079.720000 ;
+ RECT 2158.770000 1084.680000 2159.770000 1085.160000 ;
+ RECT 2158.770000 1090.120000 2159.770000 1090.600000 ;
+ RECT 2158.770000 1095.560000 2159.770000 1096.040000 ;
+ RECT 2158.770000 1052.040000 2159.770000 1052.520000 ;
+ RECT 2158.770000 1057.480000 2159.770000 1057.960000 ;
+ RECT 2158.770000 1062.920000 2159.770000 1063.400000 ;
+ RECT 2158.770000 1068.360000 2159.770000 1068.840000 ;
+ RECT 2146.120000 1073.800000 2147.220000 1074.280000 ;
+ RECT 2146.120000 1079.240000 2147.220000 1079.720000 ;
+ RECT 2146.120000 1084.680000 2147.220000 1085.160000 ;
+ RECT 2146.120000 1090.120000 2147.220000 1090.600000 ;
+ RECT 2146.120000 1095.560000 2147.220000 1096.040000 ;
+ RECT 2146.120000 1057.480000 2147.220000 1057.960000 ;
+ RECT 2146.120000 1052.040000 2147.220000 1052.520000 ;
+ RECT 2146.120000 1062.920000 2147.220000 1063.400000 ;
+ RECT 2146.120000 1068.360000 2147.220000 1068.840000 ;
+ RECT 2101.120000 1128.200000 2102.220000 1128.680000 ;
+ RECT 2101.120000 1122.760000 2102.220000 1123.240000 ;
+ RECT 2101.120000 1133.640000 2102.220000 1134.120000 ;
+ RECT 2101.120000 1139.080000 2102.220000 1139.560000 ;
+ RECT 2101.120000 1101.000000 2102.220000 1101.480000 ;
+ RECT 2101.120000 1106.440000 2102.220000 1106.920000 ;
+ RECT 2101.120000 1111.880000 2102.220000 1112.360000 ;
+ RECT 2101.120000 1117.320000 2102.220000 1117.800000 ;
+ RECT 2052.290000 1122.760000 2053.290000 1123.240000 ;
+ RECT 2052.290000 1128.200000 2053.290000 1128.680000 ;
+ RECT 2052.290000 1133.640000 2053.290000 1134.120000 ;
+ RECT 2052.290000 1139.080000 2053.290000 1139.560000 ;
+ RECT 2052.290000 1106.440000 2053.290000 1106.920000 ;
+ RECT 2052.290000 1101.000000 2053.290000 1101.480000 ;
+ RECT 2052.290000 1111.880000 2053.290000 1112.360000 ;
+ RECT 2052.290000 1117.320000 2053.290000 1117.800000 ;
+ RECT 2055.955000 1133.640000 2057.220000 1134.120000 ;
+ RECT 2055.955000 1128.200000 2057.220000 1128.680000 ;
+ RECT 2055.955000 1122.760000 2057.220000 1123.240000 ;
+ RECT 2055.955000 1139.080000 2057.220000 1139.560000 ;
+ RECT 2055.955000 1117.320000 2057.220000 1117.800000 ;
+ RECT 2055.955000 1111.880000 2057.220000 1112.360000 ;
+ RECT 2055.955000 1106.440000 2057.220000 1106.920000 ;
+ RECT 2055.955000 1101.000000 2057.220000 1101.480000 ;
+ RECT 2101.120000 1073.800000 2102.220000 1074.280000 ;
+ RECT 2101.120000 1079.240000 2102.220000 1079.720000 ;
+ RECT 2101.120000 1084.680000 2102.220000 1085.160000 ;
+ RECT 2101.120000 1090.120000 2102.220000 1090.600000 ;
+ RECT 2101.120000 1095.560000 2102.220000 1096.040000 ;
+ RECT 2101.120000 1052.040000 2102.220000 1052.520000 ;
+ RECT 2101.120000 1057.480000 2102.220000 1057.960000 ;
+ RECT 2101.120000 1062.920000 2102.220000 1063.400000 ;
+ RECT 2101.120000 1068.360000 2102.220000 1068.840000 ;
+ RECT 2052.290000 1073.800000 2053.290000 1074.280000 ;
+ RECT 2052.290000 1079.240000 2053.290000 1079.720000 ;
+ RECT 2052.290000 1084.680000 2053.290000 1085.160000 ;
+ RECT 2052.290000 1090.120000 2053.290000 1090.600000 ;
+ RECT 2052.290000 1095.560000 2053.290000 1096.040000 ;
+ RECT 2052.290000 1052.040000 2053.290000 1052.520000 ;
+ RECT 2052.290000 1057.480000 2053.290000 1057.960000 ;
+ RECT 2052.290000 1062.920000 2053.290000 1063.400000 ;
+ RECT 2052.290000 1068.360000 2053.290000 1068.840000 ;
+ RECT 2055.955000 1084.680000 2057.220000 1085.160000 ;
+ RECT 2055.955000 1079.240000 2057.220000 1079.720000 ;
+ RECT 2055.955000 1073.800000 2057.220000 1074.280000 ;
+ RECT 2055.955000 1090.120000 2057.220000 1090.600000 ;
+ RECT 2055.955000 1095.560000 2057.220000 1096.040000 ;
+ RECT 2055.955000 1068.360000 2057.220000 1068.840000 ;
+ RECT 2055.955000 1062.920000 2057.220000 1063.400000 ;
+ RECT 2055.955000 1057.480000 2057.220000 1057.960000 ;
+ RECT 2055.955000 1052.040000 2057.220000 1052.520000 ;
+ RECT 2158.770000 1024.840000 2159.770000 1025.320000 ;
+ RECT 2158.770000 1030.280000 2159.770000 1030.760000 ;
+ RECT 2158.770000 1035.720000 2159.770000 1036.200000 ;
+ RECT 2158.770000 1041.160000 2159.770000 1041.640000 ;
+ RECT 2158.770000 997.640000 2159.770000 998.120000 ;
+ RECT 2158.770000 1003.080000 2159.770000 1003.560000 ;
+ RECT 2158.770000 1008.520000 2159.770000 1009.000000 ;
+ RECT 2158.770000 1013.960000 2159.770000 1014.440000 ;
+ RECT 2158.770000 1019.400000 2159.770000 1019.880000 ;
+ RECT 2146.120000 1024.840000 2147.220000 1025.320000 ;
+ RECT 2146.120000 1030.280000 2147.220000 1030.760000 ;
+ RECT 2146.120000 1035.720000 2147.220000 1036.200000 ;
+ RECT 2146.120000 1041.160000 2147.220000 1041.640000 ;
+ RECT 2146.120000 1003.080000 2147.220000 1003.560000 ;
+ RECT 2146.120000 997.640000 2147.220000 998.120000 ;
+ RECT 2146.120000 1008.520000 2147.220000 1009.000000 ;
+ RECT 2146.120000 1013.960000 2147.220000 1014.440000 ;
+ RECT 2146.120000 1019.400000 2147.220000 1019.880000 ;
+ RECT 2158.770000 975.880000 2159.770000 976.360000 ;
+ RECT 2158.770000 981.320000 2159.770000 981.800000 ;
+ RECT 2158.770000 986.760000 2159.770000 987.240000 ;
+ RECT 2158.770000 992.200000 2159.770000 992.680000 ;
+ RECT 2158.770000 954.120000 2159.770000 954.600000 ;
+ RECT 2158.770000 959.560000 2159.770000 960.040000 ;
+ RECT 2158.770000 965.000000 2159.770000 965.480000 ;
+ RECT 2158.770000 970.440000 2159.770000 970.920000 ;
+ RECT 2146.120000 975.880000 2147.220000 976.360000 ;
+ RECT 2146.120000 981.320000 2147.220000 981.800000 ;
+ RECT 2146.120000 986.760000 2147.220000 987.240000 ;
+ RECT 2146.120000 992.200000 2147.220000 992.680000 ;
+ RECT 2146.120000 954.120000 2147.220000 954.600000 ;
+ RECT 2146.120000 959.560000 2147.220000 960.040000 ;
+ RECT 2146.120000 965.000000 2147.220000 965.480000 ;
+ RECT 2146.120000 970.440000 2147.220000 970.920000 ;
+ RECT 2101.120000 1024.840000 2102.220000 1025.320000 ;
+ RECT 2101.120000 1030.280000 2102.220000 1030.760000 ;
+ RECT 2101.120000 1035.720000 2102.220000 1036.200000 ;
+ RECT 2101.120000 1041.160000 2102.220000 1041.640000 ;
+ RECT 2101.120000 997.640000 2102.220000 998.120000 ;
+ RECT 2101.120000 1003.080000 2102.220000 1003.560000 ;
+ RECT 2101.120000 1008.520000 2102.220000 1009.000000 ;
+ RECT 2101.120000 1013.960000 2102.220000 1014.440000 ;
+ RECT 2101.120000 1019.400000 2102.220000 1019.880000 ;
+ RECT 2052.290000 1024.840000 2053.290000 1025.320000 ;
+ RECT 2052.290000 1030.280000 2053.290000 1030.760000 ;
+ RECT 2052.290000 1035.720000 2053.290000 1036.200000 ;
+ RECT 2052.290000 1041.160000 2053.290000 1041.640000 ;
+ RECT 2052.290000 997.640000 2053.290000 998.120000 ;
+ RECT 2052.290000 1003.080000 2053.290000 1003.560000 ;
+ RECT 2052.290000 1008.520000 2053.290000 1009.000000 ;
+ RECT 2052.290000 1013.960000 2053.290000 1014.440000 ;
+ RECT 2052.290000 1019.400000 2053.290000 1019.880000 ;
+ RECT 2055.955000 1030.280000 2057.220000 1030.760000 ;
+ RECT 2055.955000 1024.840000 2057.220000 1025.320000 ;
+ RECT 2055.955000 1035.720000 2057.220000 1036.200000 ;
+ RECT 2055.955000 1041.160000 2057.220000 1041.640000 ;
+ RECT 2055.955000 1019.400000 2057.220000 1019.880000 ;
+ RECT 2055.955000 1013.960000 2057.220000 1014.440000 ;
+ RECT 2055.955000 1008.520000 2057.220000 1009.000000 ;
+ RECT 2055.955000 1003.080000 2057.220000 1003.560000 ;
+ RECT 2055.955000 997.640000 2057.220000 998.120000 ;
+ RECT 2101.120000 975.880000 2102.220000 976.360000 ;
+ RECT 2101.120000 981.320000 2102.220000 981.800000 ;
+ RECT 2101.120000 986.760000 2102.220000 987.240000 ;
+ RECT 2101.120000 992.200000 2102.220000 992.680000 ;
+ RECT 2101.120000 954.120000 2102.220000 954.600000 ;
+ RECT 2101.120000 959.560000 2102.220000 960.040000 ;
+ RECT 2101.120000 965.000000 2102.220000 965.480000 ;
+ RECT 2101.120000 970.440000 2102.220000 970.920000 ;
+ RECT 2052.290000 975.880000 2053.290000 976.360000 ;
+ RECT 2052.290000 981.320000 2053.290000 981.800000 ;
+ RECT 2052.290000 986.760000 2053.290000 987.240000 ;
+ RECT 2052.290000 992.200000 2053.290000 992.680000 ;
+ RECT 2052.290000 954.120000 2053.290000 954.600000 ;
+ RECT 2052.290000 959.560000 2053.290000 960.040000 ;
+ RECT 2052.290000 965.000000 2053.290000 965.480000 ;
+ RECT 2052.290000 970.440000 2053.290000 970.920000 ;
+ RECT 2055.955000 986.760000 2057.220000 987.240000 ;
+ RECT 2055.955000 981.320000 2057.220000 981.800000 ;
+ RECT 2055.955000 975.880000 2057.220000 976.360000 ;
+ RECT 2055.955000 992.200000 2057.220000 992.680000 ;
+ RECT 2055.955000 970.440000 2057.220000 970.920000 ;
+ RECT 2055.955000 965.000000 2057.220000 965.480000 ;
+ RECT 2055.955000 959.560000 2057.220000 960.040000 ;
+ RECT 2055.955000 954.120000 2057.220000 954.600000 ;
+ RECT 2146.120000 1046.600000 2147.220000 1047.080000 ;
+ RECT 2101.120000 1046.600000 2102.220000 1047.080000 ;
+ RECT 2052.290000 1046.600000 2053.290000 1047.080000 ;
+ RECT 2055.955000 1046.600000 2057.220000 1047.080000 ;
+ RECT 2158.770000 1046.600000 2159.770000 1047.080000 ;
+ RECT 2051.060000 1143.360000 2161.000000 1144.360000 ;
+ RECT 2051.060000 947.790000 2161.000000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 946.540000 2053.290000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 1145.800000 2053.290000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 946.540000 2159.770000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 1145.800000 2159.770000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 947.790000 2052.060000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 947.790000 2161.000000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1143.360000 2052.060000 1144.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1143.360000 2161.000000 1144.360000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 933.380000 2057.220000 933.860000 ;
+ RECT 2055.955000 927.940000 2057.220000 928.420000 ;
+ RECT 2055.955000 922.500000 2057.220000 922.980000 ;
+ RECT 2055.955000 938.820000 2057.220000 939.300000 ;
+ RECT 2055.955000 917.060000 2057.220000 917.540000 ;
+ RECT 2055.955000 911.620000 2057.220000 912.100000 ;
+ RECT 2055.955000 906.180000 2057.220000 906.660000 ;
+ RECT 2055.955000 900.740000 2057.220000 901.220000 ;
+ RECT 2055.955000 884.420000 2057.220000 884.900000 ;
+ RECT 2055.955000 878.980000 2057.220000 879.460000 ;
+ RECT 2055.955000 873.540000 2057.220000 874.020000 ;
+ RECT 2055.955000 889.860000 2057.220000 890.340000 ;
+ RECT 2055.955000 895.300000 2057.220000 895.780000 ;
+ RECT 2055.955000 868.100000 2057.220000 868.580000 ;
+ RECT 2055.955000 862.660000 2057.220000 863.140000 ;
+ RECT 2055.955000 857.220000 2057.220000 857.700000 ;
+ RECT 2055.955000 851.780000 2057.220000 852.260000 ;
+ RECT 2055.955000 830.020000 2057.220000 830.500000 ;
+ RECT 2055.955000 824.580000 2057.220000 825.060000 ;
+ RECT 2055.955000 835.460000 2057.220000 835.940000 ;
+ RECT 2055.955000 840.900000 2057.220000 841.380000 ;
+ RECT 2055.955000 819.140000 2057.220000 819.620000 ;
+ RECT 2055.955000 813.700000 2057.220000 814.180000 ;
+ RECT 2055.955000 808.260000 2057.220000 808.740000 ;
+ RECT 2055.955000 802.820000 2057.220000 803.300000 ;
+ RECT 2055.955000 797.380000 2057.220000 797.860000 ;
+ RECT 2055.955000 786.500000 2057.220000 786.980000 ;
+ RECT 2055.955000 781.060000 2057.220000 781.540000 ;
+ RECT 2055.955000 775.620000 2057.220000 776.100000 ;
+ RECT 2055.955000 791.940000 2057.220000 792.420000 ;
+ RECT 2055.955000 770.180000 2057.220000 770.660000 ;
+ RECT 2055.955000 764.740000 2057.220000 765.220000 ;
+ RECT 2055.955000 759.300000 2057.220000 759.780000 ;
+ RECT 2055.955000 753.860000 2057.220000 754.340000 ;
+ RECT 2055.955000 846.340000 2057.220000 846.820000 ;
+ RECT 2052.290000 746.280000 2053.290000 946.540000 ;
+ RECT 2158.770000 746.280000 2159.770000 946.540000 ;
+ RECT 2056.120000 747.530000 2057.220000 944.100000 ;
+ RECT 2101.120000 747.530000 2102.220000 944.100000 ;
+ RECT 2146.120000 747.530000 2147.220000 944.100000 ;
+ LAYER met3 ;
+ RECT 2158.770000 922.500000 2159.770000 922.980000 ;
+ RECT 2158.770000 927.940000 2159.770000 928.420000 ;
+ RECT 2158.770000 933.380000 2159.770000 933.860000 ;
+ RECT 2158.770000 938.820000 2159.770000 939.300000 ;
+ RECT 2158.770000 906.180000 2159.770000 906.660000 ;
+ RECT 2158.770000 900.740000 2159.770000 901.220000 ;
+ RECT 2158.770000 911.620000 2159.770000 912.100000 ;
+ RECT 2158.770000 917.060000 2159.770000 917.540000 ;
+ RECT 2146.120000 922.500000 2147.220000 922.980000 ;
+ RECT 2146.120000 927.940000 2147.220000 928.420000 ;
+ RECT 2146.120000 933.380000 2147.220000 933.860000 ;
+ RECT 2146.120000 938.820000 2147.220000 939.300000 ;
+ RECT 2146.120000 906.180000 2147.220000 906.660000 ;
+ RECT 2146.120000 900.740000 2147.220000 901.220000 ;
+ RECT 2146.120000 911.620000 2147.220000 912.100000 ;
+ RECT 2146.120000 917.060000 2147.220000 917.540000 ;
+ RECT 2158.770000 873.540000 2159.770000 874.020000 ;
+ RECT 2158.770000 878.980000 2159.770000 879.460000 ;
+ RECT 2158.770000 884.420000 2159.770000 884.900000 ;
+ RECT 2158.770000 889.860000 2159.770000 890.340000 ;
+ RECT 2158.770000 895.300000 2159.770000 895.780000 ;
+ RECT 2158.770000 851.780000 2159.770000 852.260000 ;
+ RECT 2158.770000 857.220000 2159.770000 857.700000 ;
+ RECT 2158.770000 862.660000 2159.770000 863.140000 ;
+ RECT 2158.770000 868.100000 2159.770000 868.580000 ;
+ RECT 2146.120000 873.540000 2147.220000 874.020000 ;
+ RECT 2146.120000 878.980000 2147.220000 879.460000 ;
+ RECT 2146.120000 884.420000 2147.220000 884.900000 ;
+ RECT 2146.120000 889.860000 2147.220000 890.340000 ;
+ RECT 2146.120000 895.300000 2147.220000 895.780000 ;
+ RECT 2146.120000 857.220000 2147.220000 857.700000 ;
+ RECT 2146.120000 851.780000 2147.220000 852.260000 ;
+ RECT 2146.120000 862.660000 2147.220000 863.140000 ;
+ RECT 2146.120000 868.100000 2147.220000 868.580000 ;
+ RECT 2101.120000 927.940000 2102.220000 928.420000 ;
+ RECT 2101.120000 922.500000 2102.220000 922.980000 ;
+ RECT 2101.120000 933.380000 2102.220000 933.860000 ;
+ RECT 2101.120000 938.820000 2102.220000 939.300000 ;
+ RECT 2101.120000 900.740000 2102.220000 901.220000 ;
+ RECT 2101.120000 906.180000 2102.220000 906.660000 ;
+ RECT 2101.120000 911.620000 2102.220000 912.100000 ;
+ RECT 2101.120000 917.060000 2102.220000 917.540000 ;
+ RECT 2052.290000 922.500000 2053.290000 922.980000 ;
+ RECT 2052.290000 927.940000 2053.290000 928.420000 ;
+ RECT 2052.290000 933.380000 2053.290000 933.860000 ;
+ RECT 2052.290000 938.820000 2053.290000 939.300000 ;
+ RECT 2052.290000 906.180000 2053.290000 906.660000 ;
+ RECT 2052.290000 900.740000 2053.290000 901.220000 ;
+ RECT 2052.290000 911.620000 2053.290000 912.100000 ;
+ RECT 2052.290000 917.060000 2053.290000 917.540000 ;
+ RECT 2055.955000 933.380000 2057.220000 933.860000 ;
+ RECT 2055.955000 927.940000 2057.220000 928.420000 ;
+ RECT 2055.955000 922.500000 2057.220000 922.980000 ;
+ RECT 2055.955000 938.820000 2057.220000 939.300000 ;
+ RECT 2055.955000 917.060000 2057.220000 917.540000 ;
+ RECT 2055.955000 911.620000 2057.220000 912.100000 ;
+ RECT 2055.955000 906.180000 2057.220000 906.660000 ;
+ RECT 2055.955000 900.740000 2057.220000 901.220000 ;
+ RECT 2101.120000 873.540000 2102.220000 874.020000 ;
+ RECT 2101.120000 878.980000 2102.220000 879.460000 ;
+ RECT 2101.120000 884.420000 2102.220000 884.900000 ;
+ RECT 2101.120000 889.860000 2102.220000 890.340000 ;
+ RECT 2101.120000 895.300000 2102.220000 895.780000 ;
+ RECT 2101.120000 851.780000 2102.220000 852.260000 ;
+ RECT 2101.120000 857.220000 2102.220000 857.700000 ;
+ RECT 2101.120000 862.660000 2102.220000 863.140000 ;
+ RECT 2101.120000 868.100000 2102.220000 868.580000 ;
+ RECT 2052.290000 873.540000 2053.290000 874.020000 ;
+ RECT 2052.290000 878.980000 2053.290000 879.460000 ;
+ RECT 2052.290000 884.420000 2053.290000 884.900000 ;
+ RECT 2052.290000 889.860000 2053.290000 890.340000 ;
+ RECT 2052.290000 895.300000 2053.290000 895.780000 ;
+ RECT 2052.290000 851.780000 2053.290000 852.260000 ;
+ RECT 2052.290000 857.220000 2053.290000 857.700000 ;
+ RECT 2052.290000 862.660000 2053.290000 863.140000 ;
+ RECT 2052.290000 868.100000 2053.290000 868.580000 ;
+ RECT 2055.955000 884.420000 2057.220000 884.900000 ;
+ RECT 2055.955000 878.980000 2057.220000 879.460000 ;
+ RECT 2055.955000 873.540000 2057.220000 874.020000 ;
+ RECT 2055.955000 889.860000 2057.220000 890.340000 ;
+ RECT 2055.955000 895.300000 2057.220000 895.780000 ;
+ RECT 2055.955000 868.100000 2057.220000 868.580000 ;
+ RECT 2055.955000 862.660000 2057.220000 863.140000 ;
+ RECT 2055.955000 857.220000 2057.220000 857.700000 ;
+ RECT 2055.955000 851.780000 2057.220000 852.260000 ;
+ RECT 2158.770000 824.580000 2159.770000 825.060000 ;
+ RECT 2158.770000 830.020000 2159.770000 830.500000 ;
+ RECT 2158.770000 835.460000 2159.770000 835.940000 ;
+ RECT 2158.770000 840.900000 2159.770000 841.380000 ;
+ RECT 2158.770000 797.380000 2159.770000 797.860000 ;
+ RECT 2158.770000 802.820000 2159.770000 803.300000 ;
+ RECT 2158.770000 808.260000 2159.770000 808.740000 ;
+ RECT 2158.770000 813.700000 2159.770000 814.180000 ;
+ RECT 2158.770000 819.140000 2159.770000 819.620000 ;
+ RECT 2146.120000 824.580000 2147.220000 825.060000 ;
+ RECT 2146.120000 830.020000 2147.220000 830.500000 ;
+ RECT 2146.120000 835.460000 2147.220000 835.940000 ;
+ RECT 2146.120000 840.900000 2147.220000 841.380000 ;
+ RECT 2146.120000 802.820000 2147.220000 803.300000 ;
+ RECT 2146.120000 797.380000 2147.220000 797.860000 ;
+ RECT 2146.120000 808.260000 2147.220000 808.740000 ;
+ RECT 2146.120000 813.700000 2147.220000 814.180000 ;
+ RECT 2146.120000 819.140000 2147.220000 819.620000 ;
+ RECT 2158.770000 775.620000 2159.770000 776.100000 ;
+ RECT 2158.770000 781.060000 2159.770000 781.540000 ;
+ RECT 2158.770000 786.500000 2159.770000 786.980000 ;
+ RECT 2158.770000 791.940000 2159.770000 792.420000 ;
+ RECT 2158.770000 753.860000 2159.770000 754.340000 ;
+ RECT 2158.770000 759.300000 2159.770000 759.780000 ;
+ RECT 2158.770000 764.740000 2159.770000 765.220000 ;
+ RECT 2158.770000 770.180000 2159.770000 770.660000 ;
+ RECT 2146.120000 775.620000 2147.220000 776.100000 ;
+ RECT 2146.120000 781.060000 2147.220000 781.540000 ;
+ RECT 2146.120000 786.500000 2147.220000 786.980000 ;
+ RECT 2146.120000 791.940000 2147.220000 792.420000 ;
+ RECT 2146.120000 753.860000 2147.220000 754.340000 ;
+ RECT 2146.120000 759.300000 2147.220000 759.780000 ;
+ RECT 2146.120000 764.740000 2147.220000 765.220000 ;
+ RECT 2146.120000 770.180000 2147.220000 770.660000 ;
+ RECT 2101.120000 824.580000 2102.220000 825.060000 ;
+ RECT 2101.120000 830.020000 2102.220000 830.500000 ;
+ RECT 2101.120000 835.460000 2102.220000 835.940000 ;
+ RECT 2101.120000 840.900000 2102.220000 841.380000 ;
+ RECT 2101.120000 797.380000 2102.220000 797.860000 ;
+ RECT 2101.120000 802.820000 2102.220000 803.300000 ;
+ RECT 2101.120000 808.260000 2102.220000 808.740000 ;
+ RECT 2101.120000 813.700000 2102.220000 814.180000 ;
+ RECT 2101.120000 819.140000 2102.220000 819.620000 ;
+ RECT 2052.290000 824.580000 2053.290000 825.060000 ;
+ RECT 2052.290000 830.020000 2053.290000 830.500000 ;
+ RECT 2052.290000 835.460000 2053.290000 835.940000 ;
+ RECT 2052.290000 840.900000 2053.290000 841.380000 ;
+ RECT 2052.290000 797.380000 2053.290000 797.860000 ;
+ RECT 2052.290000 802.820000 2053.290000 803.300000 ;
+ RECT 2052.290000 808.260000 2053.290000 808.740000 ;
+ RECT 2052.290000 813.700000 2053.290000 814.180000 ;
+ RECT 2052.290000 819.140000 2053.290000 819.620000 ;
+ RECT 2055.955000 830.020000 2057.220000 830.500000 ;
+ RECT 2055.955000 824.580000 2057.220000 825.060000 ;
+ RECT 2055.955000 835.460000 2057.220000 835.940000 ;
+ RECT 2055.955000 840.900000 2057.220000 841.380000 ;
+ RECT 2055.955000 819.140000 2057.220000 819.620000 ;
+ RECT 2055.955000 813.700000 2057.220000 814.180000 ;
+ RECT 2055.955000 808.260000 2057.220000 808.740000 ;
+ RECT 2055.955000 802.820000 2057.220000 803.300000 ;
+ RECT 2055.955000 797.380000 2057.220000 797.860000 ;
+ RECT 2101.120000 775.620000 2102.220000 776.100000 ;
+ RECT 2101.120000 781.060000 2102.220000 781.540000 ;
+ RECT 2101.120000 786.500000 2102.220000 786.980000 ;
+ RECT 2101.120000 791.940000 2102.220000 792.420000 ;
+ RECT 2101.120000 753.860000 2102.220000 754.340000 ;
+ RECT 2101.120000 759.300000 2102.220000 759.780000 ;
+ RECT 2101.120000 764.740000 2102.220000 765.220000 ;
+ RECT 2101.120000 770.180000 2102.220000 770.660000 ;
+ RECT 2052.290000 775.620000 2053.290000 776.100000 ;
+ RECT 2052.290000 781.060000 2053.290000 781.540000 ;
+ RECT 2052.290000 786.500000 2053.290000 786.980000 ;
+ RECT 2052.290000 791.940000 2053.290000 792.420000 ;
+ RECT 2052.290000 753.860000 2053.290000 754.340000 ;
+ RECT 2052.290000 759.300000 2053.290000 759.780000 ;
+ RECT 2052.290000 764.740000 2053.290000 765.220000 ;
+ RECT 2052.290000 770.180000 2053.290000 770.660000 ;
+ RECT 2055.955000 786.500000 2057.220000 786.980000 ;
+ RECT 2055.955000 781.060000 2057.220000 781.540000 ;
+ RECT 2055.955000 775.620000 2057.220000 776.100000 ;
+ RECT 2055.955000 791.940000 2057.220000 792.420000 ;
+ RECT 2055.955000 770.180000 2057.220000 770.660000 ;
+ RECT 2055.955000 764.740000 2057.220000 765.220000 ;
+ RECT 2055.955000 759.300000 2057.220000 759.780000 ;
+ RECT 2055.955000 753.860000 2057.220000 754.340000 ;
+ RECT 2146.120000 846.340000 2147.220000 846.820000 ;
+ RECT 2101.120000 846.340000 2102.220000 846.820000 ;
+ RECT 2052.290000 846.340000 2053.290000 846.820000 ;
+ RECT 2055.955000 846.340000 2057.220000 846.820000 ;
+ RECT 2158.770000 846.340000 2159.770000 846.820000 ;
+ RECT 2051.060000 943.100000 2161.000000 944.100000 ;
+ RECT 2051.060000 747.530000 2161.000000 748.530000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 746.280000 2053.290000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 945.540000 2053.290000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 746.280000 2159.770000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 945.540000 2159.770000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 747.530000 2052.060000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 747.530000 2161.000000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 943.100000 2052.060000 944.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 943.100000 2161.000000 944.100000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 733.120000 2057.220000 733.600000 ;
+ RECT 2055.955000 727.680000 2057.220000 728.160000 ;
+ RECT 2055.955000 722.240000 2057.220000 722.720000 ;
+ RECT 2055.955000 738.560000 2057.220000 739.040000 ;
+ RECT 2055.955000 716.800000 2057.220000 717.280000 ;
+ RECT 2055.955000 711.360000 2057.220000 711.840000 ;
+ RECT 2055.955000 705.920000 2057.220000 706.400000 ;
+ RECT 2055.955000 700.480000 2057.220000 700.960000 ;
+ RECT 2055.955000 684.160000 2057.220000 684.640000 ;
+ RECT 2055.955000 678.720000 2057.220000 679.200000 ;
+ RECT 2055.955000 673.280000 2057.220000 673.760000 ;
+ RECT 2055.955000 689.600000 2057.220000 690.080000 ;
+ RECT 2055.955000 695.040000 2057.220000 695.520000 ;
+ RECT 2055.955000 667.840000 2057.220000 668.320000 ;
+ RECT 2055.955000 662.400000 2057.220000 662.880000 ;
+ RECT 2055.955000 656.960000 2057.220000 657.440000 ;
+ RECT 2055.955000 651.520000 2057.220000 652.000000 ;
+ RECT 2055.955000 629.760000 2057.220000 630.240000 ;
+ RECT 2055.955000 624.320000 2057.220000 624.800000 ;
+ RECT 2055.955000 635.200000 2057.220000 635.680000 ;
+ RECT 2055.955000 640.640000 2057.220000 641.120000 ;
+ RECT 2055.955000 618.880000 2057.220000 619.360000 ;
+ RECT 2055.955000 613.440000 2057.220000 613.920000 ;
+ RECT 2055.955000 608.000000 2057.220000 608.480000 ;
+ RECT 2055.955000 602.560000 2057.220000 603.040000 ;
+ RECT 2055.955000 597.120000 2057.220000 597.600000 ;
+ RECT 2055.955000 586.240000 2057.220000 586.720000 ;
+ RECT 2055.955000 580.800000 2057.220000 581.280000 ;
+ RECT 2055.955000 575.360000 2057.220000 575.840000 ;
+ RECT 2055.955000 591.680000 2057.220000 592.160000 ;
+ RECT 2055.955000 569.920000 2057.220000 570.400000 ;
+ RECT 2055.955000 564.480000 2057.220000 564.960000 ;
+ RECT 2055.955000 559.040000 2057.220000 559.520000 ;
+ RECT 2055.955000 553.600000 2057.220000 554.080000 ;
+ RECT 2055.955000 646.080000 2057.220000 646.560000 ;
+ RECT 2052.290000 546.020000 2053.290000 746.280000 ;
+ RECT 2158.770000 546.020000 2159.770000 746.280000 ;
+ RECT 2056.120000 547.270000 2057.220000 743.840000 ;
+ RECT 2101.120000 547.270000 2102.220000 743.840000 ;
+ RECT 2146.120000 547.270000 2147.220000 743.840000 ;
+ LAYER met3 ;
+ RECT 2158.770000 722.240000 2159.770000 722.720000 ;
+ RECT 2158.770000 727.680000 2159.770000 728.160000 ;
+ RECT 2158.770000 733.120000 2159.770000 733.600000 ;
+ RECT 2158.770000 738.560000 2159.770000 739.040000 ;
+ RECT 2158.770000 705.920000 2159.770000 706.400000 ;
+ RECT 2158.770000 700.480000 2159.770000 700.960000 ;
+ RECT 2158.770000 711.360000 2159.770000 711.840000 ;
+ RECT 2158.770000 716.800000 2159.770000 717.280000 ;
+ RECT 2146.120000 722.240000 2147.220000 722.720000 ;
+ RECT 2146.120000 727.680000 2147.220000 728.160000 ;
+ RECT 2146.120000 733.120000 2147.220000 733.600000 ;
+ RECT 2146.120000 738.560000 2147.220000 739.040000 ;
+ RECT 2146.120000 705.920000 2147.220000 706.400000 ;
+ RECT 2146.120000 700.480000 2147.220000 700.960000 ;
+ RECT 2146.120000 711.360000 2147.220000 711.840000 ;
+ RECT 2146.120000 716.800000 2147.220000 717.280000 ;
+ RECT 2158.770000 673.280000 2159.770000 673.760000 ;
+ RECT 2158.770000 678.720000 2159.770000 679.200000 ;
+ RECT 2158.770000 684.160000 2159.770000 684.640000 ;
+ RECT 2158.770000 689.600000 2159.770000 690.080000 ;
+ RECT 2158.770000 695.040000 2159.770000 695.520000 ;
+ RECT 2158.770000 651.520000 2159.770000 652.000000 ;
+ RECT 2158.770000 656.960000 2159.770000 657.440000 ;
+ RECT 2158.770000 662.400000 2159.770000 662.880000 ;
+ RECT 2158.770000 667.840000 2159.770000 668.320000 ;
+ RECT 2146.120000 673.280000 2147.220000 673.760000 ;
+ RECT 2146.120000 678.720000 2147.220000 679.200000 ;
+ RECT 2146.120000 684.160000 2147.220000 684.640000 ;
+ RECT 2146.120000 689.600000 2147.220000 690.080000 ;
+ RECT 2146.120000 695.040000 2147.220000 695.520000 ;
+ RECT 2146.120000 656.960000 2147.220000 657.440000 ;
+ RECT 2146.120000 651.520000 2147.220000 652.000000 ;
+ RECT 2146.120000 662.400000 2147.220000 662.880000 ;
+ RECT 2146.120000 667.840000 2147.220000 668.320000 ;
+ RECT 2101.120000 727.680000 2102.220000 728.160000 ;
+ RECT 2101.120000 722.240000 2102.220000 722.720000 ;
+ RECT 2101.120000 733.120000 2102.220000 733.600000 ;
+ RECT 2101.120000 738.560000 2102.220000 739.040000 ;
+ RECT 2101.120000 700.480000 2102.220000 700.960000 ;
+ RECT 2101.120000 705.920000 2102.220000 706.400000 ;
+ RECT 2101.120000 711.360000 2102.220000 711.840000 ;
+ RECT 2101.120000 716.800000 2102.220000 717.280000 ;
+ RECT 2052.290000 722.240000 2053.290000 722.720000 ;
+ RECT 2052.290000 727.680000 2053.290000 728.160000 ;
+ RECT 2052.290000 733.120000 2053.290000 733.600000 ;
+ RECT 2052.290000 738.560000 2053.290000 739.040000 ;
+ RECT 2052.290000 705.920000 2053.290000 706.400000 ;
+ RECT 2052.290000 700.480000 2053.290000 700.960000 ;
+ RECT 2052.290000 711.360000 2053.290000 711.840000 ;
+ RECT 2052.290000 716.800000 2053.290000 717.280000 ;
+ RECT 2055.955000 733.120000 2057.220000 733.600000 ;
+ RECT 2055.955000 727.680000 2057.220000 728.160000 ;
+ RECT 2055.955000 722.240000 2057.220000 722.720000 ;
+ RECT 2055.955000 738.560000 2057.220000 739.040000 ;
+ RECT 2055.955000 716.800000 2057.220000 717.280000 ;
+ RECT 2055.955000 711.360000 2057.220000 711.840000 ;
+ RECT 2055.955000 705.920000 2057.220000 706.400000 ;
+ RECT 2055.955000 700.480000 2057.220000 700.960000 ;
+ RECT 2101.120000 673.280000 2102.220000 673.760000 ;
+ RECT 2101.120000 678.720000 2102.220000 679.200000 ;
+ RECT 2101.120000 684.160000 2102.220000 684.640000 ;
+ RECT 2101.120000 689.600000 2102.220000 690.080000 ;
+ RECT 2101.120000 695.040000 2102.220000 695.520000 ;
+ RECT 2101.120000 651.520000 2102.220000 652.000000 ;
+ RECT 2101.120000 656.960000 2102.220000 657.440000 ;
+ RECT 2101.120000 662.400000 2102.220000 662.880000 ;
+ RECT 2101.120000 667.840000 2102.220000 668.320000 ;
+ RECT 2052.290000 673.280000 2053.290000 673.760000 ;
+ RECT 2052.290000 678.720000 2053.290000 679.200000 ;
+ RECT 2052.290000 684.160000 2053.290000 684.640000 ;
+ RECT 2052.290000 689.600000 2053.290000 690.080000 ;
+ RECT 2052.290000 695.040000 2053.290000 695.520000 ;
+ RECT 2052.290000 651.520000 2053.290000 652.000000 ;
+ RECT 2052.290000 656.960000 2053.290000 657.440000 ;
+ RECT 2052.290000 662.400000 2053.290000 662.880000 ;
+ RECT 2052.290000 667.840000 2053.290000 668.320000 ;
+ RECT 2055.955000 684.160000 2057.220000 684.640000 ;
+ RECT 2055.955000 678.720000 2057.220000 679.200000 ;
+ RECT 2055.955000 673.280000 2057.220000 673.760000 ;
+ RECT 2055.955000 689.600000 2057.220000 690.080000 ;
+ RECT 2055.955000 695.040000 2057.220000 695.520000 ;
+ RECT 2055.955000 667.840000 2057.220000 668.320000 ;
+ RECT 2055.955000 662.400000 2057.220000 662.880000 ;
+ RECT 2055.955000 656.960000 2057.220000 657.440000 ;
+ RECT 2055.955000 651.520000 2057.220000 652.000000 ;
+ RECT 2158.770000 624.320000 2159.770000 624.800000 ;
+ RECT 2158.770000 629.760000 2159.770000 630.240000 ;
+ RECT 2158.770000 635.200000 2159.770000 635.680000 ;
+ RECT 2158.770000 640.640000 2159.770000 641.120000 ;
+ RECT 2158.770000 597.120000 2159.770000 597.600000 ;
+ RECT 2158.770000 602.560000 2159.770000 603.040000 ;
+ RECT 2158.770000 608.000000 2159.770000 608.480000 ;
+ RECT 2158.770000 613.440000 2159.770000 613.920000 ;
+ RECT 2158.770000 618.880000 2159.770000 619.360000 ;
+ RECT 2146.120000 624.320000 2147.220000 624.800000 ;
+ RECT 2146.120000 629.760000 2147.220000 630.240000 ;
+ RECT 2146.120000 635.200000 2147.220000 635.680000 ;
+ RECT 2146.120000 640.640000 2147.220000 641.120000 ;
+ RECT 2146.120000 602.560000 2147.220000 603.040000 ;
+ RECT 2146.120000 597.120000 2147.220000 597.600000 ;
+ RECT 2146.120000 608.000000 2147.220000 608.480000 ;
+ RECT 2146.120000 613.440000 2147.220000 613.920000 ;
+ RECT 2146.120000 618.880000 2147.220000 619.360000 ;
+ RECT 2158.770000 575.360000 2159.770000 575.840000 ;
+ RECT 2158.770000 580.800000 2159.770000 581.280000 ;
+ RECT 2158.770000 586.240000 2159.770000 586.720000 ;
+ RECT 2158.770000 591.680000 2159.770000 592.160000 ;
+ RECT 2158.770000 553.600000 2159.770000 554.080000 ;
+ RECT 2158.770000 559.040000 2159.770000 559.520000 ;
+ RECT 2158.770000 564.480000 2159.770000 564.960000 ;
+ RECT 2158.770000 569.920000 2159.770000 570.400000 ;
+ RECT 2146.120000 575.360000 2147.220000 575.840000 ;
+ RECT 2146.120000 580.800000 2147.220000 581.280000 ;
+ RECT 2146.120000 586.240000 2147.220000 586.720000 ;
+ RECT 2146.120000 591.680000 2147.220000 592.160000 ;
+ RECT 2146.120000 553.600000 2147.220000 554.080000 ;
+ RECT 2146.120000 559.040000 2147.220000 559.520000 ;
+ RECT 2146.120000 564.480000 2147.220000 564.960000 ;
+ RECT 2146.120000 569.920000 2147.220000 570.400000 ;
+ RECT 2101.120000 624.320000 2102.220000 624.800000 ;
+ RECT 2101.120000 629.760000 2102.220000 630.240000 ;
+ RECT 2101.120000 635.200000 2102.220000 635.680000 ;
+ RECT 2101.120000 640.640000 2102.220000 641.120000 ;
+ RECT 2101.120000 597.120000 2102.220000 597.600000 ;
+ RECT 2101.120000 602.560000 2102.220000 603.040000 ;
+ RECT 2101.120000 608.000000 2102.220000 608.480000 ;
+ RECT 2101.120000 613.440000 2102.220000 613.920000 ;
+ RECT 2101.120000 618.880000 2102.220000 619.360000 ;
+ RECT 2052.290000 624.320000 2053.290000 624.800000 ;
+ RECT 2052.290000 629.760000 2053.290000 630.240000 ;
+ RECT 2052.290000 635.200000 2053.290000 635.680000 ;
+ RECT 2052.290000 640.640000 2053.290000 641.120000 ;
+ RECT 2052.290000 597.120000 2053.290000 597.600000 ;
+ RECT 2052.290000 602.560000 2053.290000 603.040000 ;
+ RECT 2052.290000 608.000000 2053.290000 608.480000 ;
+ RECT 2052.290000 613.440000 2053.290000 613.920000 ;
+ RECT 2052.290000 618.880000 2053.290000 619.360000 ;
+ RECT 2055.955000 629.760000 2057.220000 630.240000 ;
+ RECT 2055.955000 624.320000 2057.220000 624.800000 ;
+ RECT 2055.955000 635.200000 2057.220000 635.680000 ;
+ RECT 2055.955000 640.640000 2057.220000 641.120000 ;
+ RECT 2055.955000 618.880000 2057.220000 619.360000 ;
+ RECT 2055.955000 613.440000 2057.220000 613.920000 ;
+ RECT 2055.955000 608.000000 2057.220000 608.480000 ;
+ RECT 2055.955000 602.560000 2057.220000 603.040000 ;
+ RECT 2055.955000 597.120000 2057.220000 597.600000 ;
+ RECT 2101.120000 575.360000 2102.220000 575.840000 ;
+ RECT 2101.120000 580.800000 2102.220000 581.280000 ;
+ RECT 2101.120000 586.240000 2102.220000 586.720000 ;
+ RECT 2101.120000 591.680000 2102.220000 592.160000 ;
+ RECT 2101.120000 553.600000 2102.220000 554.080000 ;
+ RECT 2101.120000 559.040000 2102.220000 559.520000 ;
+ RECT 2101.120000 564.480000 2102.220000 564.960000 ;
+ RECT 2101.120000 569.920000 2102.220000 570.400000 ;
+ RECT 2052.290000 575.360000 2053.290000 575.840000 ;
+ RECT 2052.290000 580.800000 2053.290000 581.280000 ;
+ RECT 2052.290000 586.240000 2053.290000 586.720000 ;
+ RECT 2052.290000 591.680000 2053.290000 592.160000 ;
+ RECT 2052.290000 553.600000 2053.290000 554.080000 ;
+ RECT 2052.290000 559.040000 2053.290000 559.520000 ;
+ RECT 2052.290000 564.480000 2053.290000 564.960000 ;
+ RECT 2052.290000 569.920000 2053.290000 570.400000 ;
+ RECT 2055.955000 586.240000 2057.220000 586.720000 ;
+ RECT 2055.955000 580.800000 2057.220000 581.280000 ;
+ RECT 2055.955000 575.360000 2057.220000 575.840000 ;
+ RECT 2055.955000 591.680000 2057.220000 592.160000 ;
+ RECT 2055.955000 569.920000 2057.220000 570.400000 ;
+ RECT 2055.955000 564.480000 2057.220000 564.960000 ;
+ RECT 2055.955000 559.040000 2057.220000 559.520000 ;
+ RECT 2055.955000 553.600000 2057.220000 554.080000 ;
+ RECT 2146.120000 646.080000 2147.220000 646.560000 ;
+ RECT 2101.120000 646.080000 2102.220000 646.560000 ;
+ RECT 2052.290000 646.080000 2053.290000 646.560000 ;
+ RECT 2055.955000 646.080000 2057.220000 646.560000 ;
+ RECT 2158.770000 646.080000 2159.770000 646.560000 ;
+ RECT 2051.060000 742.840000 2161.000000 743.840000 ;
+ RECT 2051.060000 547.270000 2161.000000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 546.020000 2053.290000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 745.280000 2053.290000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 546.020000 2159.770000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 745.280000 2159.770000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 547.270000 2052.060000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 547.270000 2161.000000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 742.840000 2052.060000 743.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 742.840000 2161.000000 743.840000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 532.860000 2057.220000 533.340000 ;
+ RECT 2055.955000 527.420000 2057.220000 527.900000 ;
+ RECT 2055.955000 521.980000 2057.220000 522.460000 ;
+ RECT 2055.955000 538.300000 2057.220000 538.780000 ;
+ RECT 2055.955000 516.540000 2057.220000 517.020000 ;
+ RECT 2055.955000 511.100000 2057.220000 511.580000 ;
+ RECT 2055.955000 505.660000 2057.220000 506.140000 ;
+ RECT 2055.955000 500.220000 2057.220000 500.700000 ;
+ RECT 2055.955000 483.900000 2057.220000 484.380000 ;
+ RECT 2055.955000 478.460000 2057.220000 478.940000 ;
+ RECT 2055.955000 473.020000 2057.220000 473.500000 ;
+ RECT 2055.955000 489.340000 2057.220000 489.820000 ;
+ RECT 2055.955000 494.780000 2057.220000 495.260000 ;
+ RECT 2055.955000 467.580000 2057.220000 468.060000 ;
+ RECT 2055.955000 462.140000 2057.220000 462.620000 ;
+ RECT 2055.955000 456.700000 2057.220000 457.180000 ;
+ RECT 2055.955000 451.260000 2057.220000 451.740000 ;
+ RECT 2055.955000 429.500000 2057.220000 429.980000 ;
+ RECT 2055.955000 424.060000 2057.220000 424.540000 ;
+ RECT 2055.955000 434.940000 2057.220000 435.420000 ;
+ RECT 2055.955000 440.380000 2057.220000 440.860000 ;
+ RECT 2055.955000 418.620000 2057.220000 419.100000 ;
+ RECT 2055.955000 413.180000 2057.220000 413.660000 ;
+ RECT 2055.955000 407.740000 2057.220000 408.220000 ;
+ RECT 2055.955000 402.300000 2057.220000 402.780000 ;
+ RECT 2055.955000 396.860000 2057.220000 397.340000 ;
+ RECT 2055.955000 385.980000 2057.220000 386.460000 ;
+ RECT 2055.955000 380.540000 2057.220000 381.020000 ;
+ RECT 2055.955000 375.100000 2057.220000 375.580000 ;
+ RECT 2055.955000 391.420000 2057.220000 391.900000 ;
+ RECT 2055.955000 369.660000 2057.220000 370.140000 ;
+ RECT 2055.955000 364.220000 2057.220000 364.700000 ;
+ RECT 2055.955000 358.780000 2057.220000 359.260000 ;
+ RECT 2055.955000 353.340000 2057.220000 353.820000 ;
+ RECT 2055.955000 445.820000 2057.220000 446.300000 ;
+ RECT 2052.290000 345.760000 2053.290000 546.020000 ;
+ RECT 2158.770000 345.760000 2159.770000 546.020000 ;
+ RECT 2056.120000 347.010000 2057.220000 543.580000 ;
+ RECT 2101.120000 347.010000 2102.220000 543.580000 ;
+ RECT 2146.120000 347.010000 2147.220000 543.580000 ;
+ LAYER met3 ;
+ RECT 2158.770000 521.980000 2159.770000 522.460000 ;
+ RECT 2158.770000 527.420000 2159.770000 527.900000 ;
+ RECT 2158.770000 532.860000 2159.770000 533.340000 ;
+ RECT 2158.770000 538.300000 2159.770000 538.780000 ;
+ RECT 2158.770000 505.660000 2159.770000 506.140000 ;
+ RECT 2158.770000 500.220000 2159.770000 500.700000 ;
+ RECT 2158.770000 511.100000 2159.770000 511.580000 ;
+ RECT 2158.770000 516.540000 2159.770000 517.020000 ;
+ RECT 2146.120000 521.980000 2147.220000 522.460000 ;
+ RECT 2146.120000 527.420000 2147.220000 527.900000 ;
+ RECT 2146.120000 532.860000 2147.220000 533.340000 ;
+ RECT 2146.120000 538.300000 2147.220000 538.780000 ;
+ RECT 2146.120000 505.660000 2147.220000 506.140000 ;
+ RECT 2146.120000 500.220000 2147.220000 500.700000 ;
+ RECT 2146.120000 511.100000 2147.220000 511.580000 ;
+ RECT 2146.120000 516.540000 2147.220000 517.020000 ;
+ RECT 2158.770000 473.020000 2159.770000 473.500000 ;
+ RECT 2158.770000 478.460000 2159.770000 478.940000 ;
+ RECT 2158.770000 483.900000 2159.770000 484.380000 ;
+ RECT 2158.770000 489.340000 2159.770000 489.820000 ;
+ RECT 2158.770000 494.780000 2159.770000 495.260000 ;
+ RECT 2158.770000 451.260000 2159.770000 451.740000 ;
+ RECT 2158.770000 456.700000 2159.770000 457.180000 ;
+ RECT 2158.770000 462.140000 2159.770000 462.620000 ;
+ RECT 2158.770000 467.580000 2159.770000 468.060000 ;
+ RECT 2146.120000 473.020000 2147.220000 473.500000 ;
+ RECT 2146.120000 478.460000 2147.220000 478.940000 ;
+ RECT 2146.120000 483.900000 2147.220000 484.380000 ;
+ RECT 2146.120000 489.340000 2147.220000 489.820000 ;
+ RECT 2146.120000 494.780000 2147.220000 495.260000 ;
+ RECT 2146.120000 456.700000 2147.220000 457.180000 ;
+ RECT 2146.120000 451.260000 2147.220000 451.740000 ;
+ RECT 2146.120000 462.140000 2147.220000 462.620000 ;
+ RECT 2146.120000 467.580000 2147.220000 468.060000 ;
+ RECT 2101.120000 527.420000 2102.220000 527.900000 ;
+ RECT 2101.120000 521.980000 2102.220000 522.460000 ;
+ RECT 2101.120000 532.860000 2102.220000 533.340000 ;
+ RECT 2101.120000 538.300000 2102.220000 538.780000 ;
+ RECT 2101.120000 500.220000 2102.220000 500.700000 ;
+ RECT 2101.120000 505.660000 2102.220000 506.140000 ;
+ RECT 2101.120000 511.100000 2102.220000 511.580000 ;
+ RECT 2101.120000 516.540000 2102.220000 517.020000 ;
+ RECT 2052.290000 521.980000 2053.290000 522.460000 ;
+ RECT 2052.290000 527.420000 2053.290000 527.900000 ;
+ RECT 2052.290000 532.860000 2053.290000 533.340000 ;
+ RECT 2052.290000 538.300000 2053.290000 538.780000 ;
+ RECT 2052.290000 505.660000 2053.290000 506.140000 ;
+ RECT 2052.290000 500.220000 2053.290000 500.700000 ;
+ RECT 2052.290000 511.100000 2053.290000 511.580000 ;
+ RECT 2052.290000 516.540000 2053.290000 517.020000 ;
+ RECT 2055.955000 532.860000 2057.220000 533.340000 ;
+ RECT 2055.955000 527.420000 2057.220000 527.900000 ;
+ RECT 2055.955000 521.980000 2057.220000 522.460000 ;
+ RECT 2055.955000 538.300000 2057.220000 538.780000 ;
+ RECT 2055.955000 516.540000 2057.220000 517.020000 ;
+ RECT 2055.955000 511.100000 2057.220000 511.580000 ;
+ RECT 2055.955000 505.660000 2057.220000 506.140000 ;
+ RECT 2055.955000 500.220000 2057.220000 500.700000 ;
+ RECT 2101.120000 473.020000 2102.220000 473.500000 ;
+ RECT 2101.120000 478.460000 2102.220000 478.940000 ;
+ RECT 2101.120000 483.900000 2102.220000 484.380000 ;
+ RECT 2101.120000 489.340000 2102.220000 489.820000 ;
+ RECT 2101.120000 494.780000 2102.220000 495.260000 ;
+ RECT 2101.120000 451.260000 2102.220000 451.740000 ;
+ RECT 2101.120000 456.700000 2102.220000 457.180000 ;
+ RECT 2101.120000 462.140000 2102.220000 462.620000 ;
+ RECT 2101.120000 467.580000 2102.220000 468.060000 ;
+ RECT 2052.290000 473.020000 2053.290000 473.500000 ;
+ RECT 2052.290000 478.460000 2053.290000 478.940000 ;
+ RECT 2052.290000 483.900000 2053.290000 484.380000 ;
+ RECT 2052.290000 489.340000 2053.290000 489.820000 ;
+ RECT 2052.290000 494.780000 2053.290000 495.260000 ;
+ RECT 2052.290000 451.260000 2053.290000 451.740000 ;
+ RECT 2052.290000 456.700000 2053.290000 457.180000 ;
+ RECT 2052.290000 462.140000 2053.290000 462.620000 ;
+ RECT 2052.290000 467.580000 2053.290000 468.060000 ;
+ RECT 2055.955000 483.900000 2057.220000 484.380000 ;
+ RECT 2055.955000 478.460000 2057.220000 478.940000 ;
+ RECT 2055.955000 473.020000 2057.220000 473.500000 ;
+ RECT 2055.955000 489.340000 2057.220000 489.820000 ;
+ RECT 2055.955000 494.780000 2057.220000 495.260000 ;
+ RECT 2055.955000 467.580000 2057.220000 468.060000 ;
+ RECT 2055.955000 462.140000 2057.220000 462.620000 ;
+ RECT 2055.955000 456.700000 2057.220000 457.180000 ;
+ RECT 2055.955000 451.260000 2057.220000 451.740000 ;
+ RECT 2158.770000 424.060000 2159.770000 424.540000 ;
+ RECT 2158.770000 429.500000 2159.770000 429.980000 ;
+ RECT 2158.770000 434.940000 2159.770000 435.420000 ;
+ RECT 2158.770000 440.380000 2159.770000 440.860000 ;
+ RECT 2158.770000 396.860000 2159.770000 397.340000 ;
+ RECT 2158.770000 402.300000 2159.770000 402.780000 ;
+ RECT 2158.770000 407.740000 2159.770000 408.220000 ;
+ RECT 2158.770000 413.180000 2159.770000 413.660000 ;
+ RECT 2158.770000 418.620000 2159.770000 419.100000 ;
+ RECT 2146.120000 424.060000 2147.220000 424.540000 ;
+ RECT 2146.120000 429.500000 2147.220000 429.980000 ;
+ RECT 2146.120000 434.940000 2147.220000 435.420000 ;
+ RECT 2146.120000 440.380000 2147.220000 440.860000 ;
+ RECT 2146.120000 402.300000 2147.220000 402.780000 ;
+ RECT 2146.120000 396.860000 2147.220000 397.340000 ;
+ RECT 2146.120000 407.740000 2147.220000 408.220000 ;
+ RECT 2146.120000 413.180000 2147.220000 413.660000 ;
+ RECT 2146.120000 418.620000 2147.220000 419.100000 ;
+ RECT 2158.770000 375.100000 2159.770000 375.580000 ;
+ RECT 2158.770000 380.540000 2159.770000 381.020000 ;
+ RECT 2158.770000 385.980000 2159.770000 386.460000 ;
+ RECT 2158.770000 391.420000 2159.770000 391.900000 ;
+ RECT 2158.770000 353.340000 2159.770000 353.820000 ;
+ RECT 2158.770000 358.780000 2159.770000 359.260000 ;
+ RECT 2158.770000 364.220000 2159.770000 364.700000 ;
+ RECT 2158.770000 369.660000 2159.770000 370.140000 ;
+ RECT 2146.120000 375.100000 2147.220000 375.580000 ;
+ RECT 2146.120000 380.540000 2147.220000 381.020000 ;
+ RECT 2146.120000 385.980000 2147.220000 386.460000 ;
+ RECT 2146.120000 391.420000 2147.220000 391.900000 ;
+ RECT 2146.120000 353.340000 2147.220000 353.820000 ;
+ RECT 2146.120000 358.780000 2147.220000 359.260000 ;
+ RECT 2146.120000 364.220000 2147.220000 364.700000 ;
+ RECT 2146.120000 369.660000 2147.220000 370.140000 ;
+ RECT 2101.120000 424.060000 2102.220000 424.540000 ;
+ RECT 2101.120000 429.500000 2102.220000 429.980000 ;
+ RECT 2101.120000 434.940000 2102.220000 435.420000 ;
+ RECT 2101.120000 440.380000 2102.220000 440.860000 ;
+ RECT 2101.120000 396.860000 2102.220000 397.340000 ;
+ RECT 2101.120000 402.300000 2102.220000 402.780000 ;
+ RECT 2101.120000 407.740000 2102.220000 408.220000 ;
+ RECT 2101.120000 413.180000 2102.220000 413.660000 ;
+ RECT 2101.120000 418.620000 2102.220000 419.100000 ;
+ RECT 2052.290000 424.060000 2053.290000 424.540000 ;
+ RECT 2052.290000 429.500000 2053.290000 429.980000 ;
+ RECT 2052.290000 434.940000 2053.290000 435.420000 ;
+ RECT 2052.290000 440.380000 2053.290000 440.860000 ;
+ RECT 2052.290000 396.860000 2053.290000 397.340000 ;
+ RECT 2052.290000 402.300000 2053.290000 402.780000 ;
+ RECT 2052.290000 407.740000 2053.290000 408.220000 ;
+ RECT 2052.290000 413.180000 2053.290000 413.660000 ;
+ RECT 2052.290000 418.620000 2053.290000 419.100000 ;
+ RECT 2055.955000 429.500000 2057.220000 429.980000 ;
+ RECT 2055.955000 424.060000 2057.220000 424.540000 ;
+ RECT 2055.955000 434.940000 2057.220000 435.420000 ;
+ RECT 2055.955000 440.380000 2057.220000 440.860000 ;
+ RECT 2055.955000 418.620000 2057.220000 419.100000 ;
+ RECT 2055.955000 413.180000 2057.220000 413.660000 ;
+ RECT 2055.955000 407.740000 2057.220000 408.220000 ;
+ RECT 2055.955000 402.300000 2057.220000 402.780000 ;
+ RECT 2055.955000 396.860000 2057.220000 397.340000 ;
+ RECT 2101.120000 375.100000 2102.220000 375.580000 ;
+ RECT 2101.120000 380.540000 2102.220000 381.020000 ;
+ RECT 2101.120000 385.980000 2102.220000 386.460000 ;
+ RECT 2101.120000 391.420000 2102.220000 391.900000 ;
+ RECT 2101.120000 353.340000 2102.220000 353.820000 ;
+ RECT 2101.120000 358.780000 2102.220000 359.260000 ;
+ RECT 2101.120000 364.220000 2102.220000 364.700000 ;
+ RECT 2101.120000 369.660000 2102.220000 370.140000 ;
+ RECT 2052.290000 375.100000 2053.290000 375.580000 ;
+ RECT 2052.290000 380.540000 2053.290000 381.020000 ;
+ RECT 2052.290000 385.980000 2053.290000 386.460000 ;
+ RECT 2052.290000 391.420000 2053.290000 391.900000 ;
+ RECT 2052.290000 353.340000 2053.290000 353.820000 ;
+ RECT 2052.290000 358.780000 2053.290000 359.260000 ;
+ RECT 2052.290000 364.220000 2053.290000 364.700000 ;
+ RECT 2052.290000 369.660000 2053.290000 370.140000 ;
+ RECT 2055.955000 385.980000 2057.220000 386.460000 ;
+ RECT 2055.955000 380.540000 2057.220000 381.020000 ;
+ RECT 2055.955000 375.100000 2057.220000 375.580000 ;
+ RECT 2055.955000 391.420000 2057.220000 391.900000 ;
+ RECT 2055.955000 369.660000 2057.220000 370.140000 ;
+ RECT 2055.955000 364.220000 2057.220000 364.700000 ;
+ RECT 2055.955000 358.780000 2057.220000 359.260000 ;
+ RECT 2055.955000 353.340000 2057.220000 353.820000 ;
+ RECT 2146.120000 445.820000 2147.220000 446.300000 ;
+ RECT 2101.120000 445.820000 2102.220000 446.300000 ;
+ RECT 2052.290000 445.820000 2053.290000 446.300000 ;
+ RECT 2055.955000 445.820000 2057.220000 446.300000 ;
+ RECT 2158.770000 445.820000 2159.770000 446.300000 ;
+ RECT 2051.060000 542.580000 2161.000000 543.580000 ;
+ RECT 2051.060000 347.010000 2161.000000 348.010000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 345.760000 2053.290000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 545.020000 2053.290000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 345.760000 2159.770000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 545.020000 2159.770000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 347.010000 2052.060000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 347.010000 2161.000000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 542.580000 2052.060000 543.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 542.580000 2161.000000 543.580000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 332.600000 2057.220000 333.080000 ;
+ RECT 2055.955000 327.160000 2057.220000 327.640000 ;
+ RECT 2055.955000 321.720000 2057.220000 322.200000 ;
+ RECT 2055.955000 338.040000 2057.220000 338.520000 ;
+ RECT 2055.955000 316.280000 2057.220000 316.760000 ;
+ RECT 2055.955000 310.840000 2057.220000 311.320000 ;
+ RECT 2055.955000 305.400000 2057.220000 305.880000 ;
+ RECT 2055.955000 299.960000 2057.220000 300.440000 ;
+ RECT 2055.955000 283.640000 2057.220000 284.120000 ;
+ RECT 2055.955000 278.200000 2057.220000 278.680000 ;
+ RECT 2055.955000 272.760000 2057.220000 273.240000 ;
+ RECT 2055.955000 289.080000 2057.220000 289.560000 ;
+ RECT 2055.955000 294.520000 2057.220000 295.000000 ;
+ RECT 2055.955000 267.320000 2057.220000 267.800000 ;
+ RECT 2055.955000 261.880000 2057.220000 262.360000 ;
+ RECT 2055.955000 256.440000 2057.220000 256.920000 ;
+ RECT 2055.955000 251.000000 2057.220000 251.480000 ;
+ RECT 2055.955000 229.240000 2057.220000 229.720000 ;
+ RECT 2055.955000 223.800000 2057.220000 224.280000 ;
+ RECT 2055.955000 234.680000 2057.220000 235.160000 ;
+ RECT 2055.955000 240.120000 2057.220000 240.600000 ;
+ RECT 2055.955000 218.360000 2057.220000 218.840000 ;
+ RECT 2055.955000 212.920000 2057.220000 213.400000 ;
+ RECT 2055.955000 207.480000 2057.220000 207.960000 ;
+ RECT 2055.955000 202.040000 2057.220000 202.520000 ;
+ RECT 2055.955000 196.600000 2057.220000 197.080000 ;
+ RECT 2055.955000 185.720000 2057.220000 186.200000 ;
+ RECT 2055.955000 180.280000 2057.220000 180.760000 ;
+ RECT 2055.955000 174.840000 2057.220000 175.320000 ;
+ RECT 2055.955000 191.160000 2057.220000 191.640000 ;
+ RECT 2055.955000 169.400000 2057.220000 169.880000 ;
+ RECT 2055.955000 163.960000 2057.220000 164.440000 ;
+ RECT 2055.955000 158.520000 2057.220000 159.000000 ;
+ RECT 2055.955000 153.080000 2057.220000 153.560000 ;
+ RECT 2055.955000 245.560000 2057.220000 246.040000 ;
+ RECT 2052.290000 145.500000 2053.290000 345.760000 ;
+ RECT 2158.770000 145.500000 2159.770000 345.760000 ;
+ RECT 2056.120000 146.750000 2057.220000 343.320000 ;
+ RECT 2101.120000 146.750000 2102.220000 343.320000 ;
+ RECT 2146.120000 146.750000 2147.220000 343.320000 ;
+ LAYER met3 ;
+ RECT 2158.770000 321.720000 2159.770000 322.200000 ;
+ RECT 2158.770000 327.160000 2159.770000 327.640000 ;
+ RECT 2158.770000 332.600000 2159.770000 333.080000 ;
+ RECT 2158.770000 338.040000 2159.770000 338.520000 ;
+ RECT 2158.770000 305.400000 2159.770000 305.880000 ;
+ RECT 2158.770000 299.960000 2159.770000 300.440000 ;
+ RECT 2158.770000 310.840000 2159.770000 311.320000 ;
+ RECT 2158.770000 316.280000 2159.770000 316.760000 ;
+ RECT 2146.120000 321.720000 2147.220000 322.200000 ;
+ RECT 2146.120000 327.160000 2147.220000 327.640000 ;
+ RECT 2146.120000 332.600000 2147.220000 333.080000 ;
+ RECT 2146.120000 338.040000 2147.220000 338.520000 ;
+ RECT 2146.120000 305.400000 2147.220000 305.880000 ;
+ RECT 2146.120000 299.960000 2147.220000 300.440000 ;
+ RECT 2146.120000 310.840000 2147.220000 311.320000 ;
+ RECT 2146.120000 316.280000 2147.220000 316.760000 ;
+ RECT 2158.770000 272.760000 2159.770000 273.240000 ;
+ RECT 2158.770000 278.200000 2159.770000 278.680000 ;
+ RECT 2158.770000 283.640000 2159.770000 284.120000 ;
+ RECT 2158.770000 289.080000 2159.770000 289.560000 ;
+ RECT 2158.770000 294.520000 2159.770000 295.000000 ;
+ RECT 2158.770000 251.000000 2159.770000 251.480000 ;
+ RECT 2158.770000 256.440000 2159.770000 256.920000 ;
+ RECT 2158.770000 261.880000 2159.770000 262.360000 ;
+ RECT 2158.770000 267.320000 2159.770000 267.800000 ;
+ RECT 2146.120000 272.760000 2147.220000 273.240000 ;
+ RECT 2146.120000 278.200000 2147.220000 278.680000 ;
+ RECT 2146.120000 283.640000 2147.220000 284.120000 ;
+ RECT 2146.120000 289.080000 2147.220000 289.560000 ;
+ RECT 2146.120000 294.520000 2147.220000 295.000000 ;
+ RECT 2146.120000 256.440000 2147.220000 256.920000 ;
+ RECT 2146.120000 251.000000 2147.220000 251.480000 ;
+ RECT 2146.120000 261.880000 2147.220000 262.360000 ;
+ RECT 2146.120000 267.320000 2147.220000 267.800000 ;
+ RECT 2101.120000 327.160000 2102.220000 327.640000 ;
+ RECT 2101.120000 321.720000 2102.220000 322.200000 ;
+ RECT 2101.120000 332.600000 2102.220000 333.080000 ;
+ RECT 2101.120000 338.040000 2102.220000 338.520000 ;
+ RECT 2101.120000 299.960000 2102.220000 300.440000 ;
+ RECT 2101.120000 305.400000 2102.220000 305.880000 ;
+ RECT 2101.120000 310.840000 2102.220000 311.320000 ;
+ RECT 2101.120000 316.280000 2102.220000 316.760000 ;
+ RECT 2052.290000 321.720000 2053.290000 322.200000 ;
+ RECT 2052.290000 327.160000 2053.290000 327.640000 ;
+ RECT 2052.290000 332.600000 2053.290000 333.080000 ;
+ RECT 2052.290000 338.040000 2053.290000 338.520000 ;
+ RECT 2052.290000 305.400000 2053.290000 305.880000 ;
+ RECT 2052.290000 299.960000 2053.290000 300.440000 ;
+ RECT 2052.290000 310.840000 2053.290000 311.320000 ;
+ RECT 2052.290000 316.280000 2053.290000 316.760000 ;
+ RECT 2055.955000 332.600000 2057.220000 333.080000 ;
+ RECT 2055.955000 327.160000 2057.220000 327.640000 ;
+ RECT 2055.955000 321.720000 2057.220000 322.200000 ;
+ RECT 2055.955000 338.040000 2057.220000 338.520000 ;
+ RECT 2055.955000 316.280000 2057.220000 316.760000 ;
+ RECT 2055.955000 310.840000 2057.220000 311.320000 ;
+ RECT 2055.955000 305.400000 2057.220000 305.880000 ;
+ RECT 2055.955000 299.960000 2057.220000 300.440000 ;
+ RECT 2101.120000 272.760000 2102.220000 273.240000 ;
+ RECT 2101.120000 278.200000 2102.220000 278.680000 ;
+ RECT 2101.120000 283.640000 2102.220000 284.120000 ;
+ RECT 2101.120000 289.080000 2102.220000 289.560000 ;
+ RECT 2101.120000 294.520000 2102.220000 295.000000 ;
+ RECT 2101.120000 251.000000 2102.220000 251.480000 ;
+ RECT 2101.120000 256.440000 2102.220000 256.920000 ;
+ RECT 2101.120000 261.880000 2102.220000 262.360000 ;
+ RECT 2101.120000 267.320000 2102.220000 267.800000 ;
+ RECT 2052.290000 272.760000 2053.290000 273.240000 ;
+ RECT 2052.290000 278.200000 2053.290000 278.680000 ;
+ RECT 2052.290000 283.640000 2053.290000 284.120000 ;
+ RECT 2052.290000 289.080000 2053.290000 289.560000 ;
+ RECT 2052.290000 294.520000 2053.290000 295.000000 ;
+ RECT 2052.290000 251.000000 2053.290000 251.480000 ;
+ RECT 2052.290000 256.440000 2053.290000 256.920000 ;
+ RECT 2052.290000 261.880000 2053.290000 262.360000 ;
+ RECT 2052.290000 267.320000 2053.290000 267.800000 ;
+ RECT 2055.955000 283.640000 2057.220000 284.120000 ;
+ RECT 2055.955000 278.200000 2057.220000 278.680000 ;
+ RECT 2055.955000 272.760000 2057.220000 273.240000 ;
+ RECT 2055.955000 289.080000 2057.220000 289.560000 ;
+ RECT 2055.955000 294.520000 2057.220000 295.000000 ;
+ RECT 2055.955000 267.320000 2057.220000 267.800000 ;
+ RECT 2055.955000 261.880000 2057.220000 262.360000 ;
+ RECT 2055.955000 256.440000 2057.220000 256.920000 ;
+ RECT 2055.955000 251.000000 2057.220000 251.480000 ;
+ RECT 2158.770000 223.800000 2159.770000 224.280000 ;
+ RECT 2158.770000 229.240000 2159.770000 229.720000 ;
+ RECT 2158.770000 234.680000 2159.770000 235.160000 ;
+ RECT 2158.770000 240.120000 2159.770000 240.600000 ;
+ RECT 2158.770000 196.600000 2159.770000 197.080000 ;
+ RECT 2158.770000 202.040000 2159.770000 202.520000 ;
+ RECT 2158.770000 207.480000 2159.770000 207.960000 ;
+ RECT 2158.770000 212.920000 2159.770000 213.400000 ;
+ RECT 2158.770000 218.360000 2159.770000 218.840000 ;
+ RECT 2146.120000 223.800000 2147.220000 224.280000 ;
+ RECT 2146.120000 229.240000 2147.220000 229.720000 ;
+ RECT 2146.120000 234.680000 2147.220000 235.160000 ;
+ RECT 2146.120000 240.120000 2147.220000 240.600000 ;
+ RECT 2146.120000 202.040000 2147.220000 202.520000 ;
+ RECT 2146.120000 196.600000 2147.220000 197.080000 ;
+ RECT 2146.120000 207.480000 2147.220000 207.960000 ;
+ RECT 2146.120000 212.920000 2147.220000 213.400000 ;
+ RECT 2146.120000 218.360000 2147.220000 218.840000 ;
+ RECT 2158.770000 174.840000 2159.770000 175.320000 ;
+ RECT 2158.770000 180.280000 2159.770000 180.760000 ;
+ RECT 2158.770000 185.720000 2159.770000 186.200000 ;
+ RECT 2158.770000 191.160000 2159.770000 191.640000 ;
+ RECT 2158.770000 153.080000 2159.770000 153.560000 ;
+ RECT 2158.770000 158.520000 2159.770000 159.000000 ;
+ RECT 2158.770000 163.960000 2159.770000 164.440000 ;
+ RECT 2158.770000 169.400000 2159.770000 169.880000 ;
+ RECT 2146.120000 174.840000 2147.220000 175.320000 ;
+ RECT 2146.120000 180.280000 2147.220000 180.760000 ;
+ RECT 2146.120000 185.720000 2147.220000 186.200000 ;
+ RECT 2146.120000 191.160000 2147.220000 191.640000 ;
+ RECT 2146.120000 153.080000 2147.220000 153.560000 ;
+ RECT 2146.120000 158.520000 2147.220000 159.000000 ;
+ RECT 2146.120000 163.960000 2147.220000 164.440000 ;
+ RECT 2146.120000 169.400000 2147.220000 169.880000 ;
+ RECT 2101.120000 223.800000 2102.220000 224.280000 ;
+ RECT 2101.120000 229.240000 2102.220000 229.720000 ;
+ RECT 2101.120000 234.680000 2102.220000 235.160000 ;
+ RECT 2101.120000 240.120000 2102.220000 240.600000 ;
+ RECT 2101.120000 196.600000 2102.220000 197.080000 ;
+ RECT 2101.120000 202.040000 2102.220000 202.520000 ;
+ RECT 2101.120000 207.480000 2102.220000 207.960000 ;
+ RECT 2101.120000 212.920000 2102.220000 213.400000 ;
+ RECT 2101.120000 218.360000 2102.220000 218.840000 ;
+ RECT 2052.290000 223.800000 2053.290000 224.280000 ;
+ RECT 2052.290000 229.240000 2053.290000 229.720000 ;
+ RECT 2052.290000 234.680000 2053.290000 235.160000 ;
+ RECT 2052.290000 240.120000 2053.290000 240.600000 ;
+ RECT 2052.290000 196.600000 2053.290000 197.080000 ;
+ RECT 2052.290000 202.040000 2053.290000 202.520000 ;
+ RECT 2052.290000 207.480000 2053.290000 207.960000 ;
+ RECT 2052.290000 212.920000 2053.290000 213.400000 ;
+ RECT 2052.290000 218.360000 2053.290000 218.840000 ;
+ RECT 2055.955000 229.240000 2057.220000 229.720000 ;
+ RECT 2055.955000 223.800000 2057.220000 224.280000 ;
+ RECT 2055.955000 234.680000 2057.220000 235.160000 ;
+ RECT 2055.955000 240.120000 2057.220000 240.600000 ;
+ RECT 2055.955000 218.360000 2057.220000 218.840000 ;
+ RECT 2055.955000 212.920000 2057.220000 213.400000 ;
+ RECT 2055.955000 207.480000 2057.220000 207.960000 ;
+ RECT 2055.955000 202.040000 2057.220000 202.520000 ;
+ RECT 2055.955000 196.600000 2057.220000 197.080000 ;
+ RECT 2101.120000 174.840000 2102.220000 175.320000 ;
+ RECT 2101.120000 180.280000 2102.220000 180.760000 ;
+ RECT 2101.120000 185.720000 2102.220000 186.200000 ;
+ RECT 2101.120000 191.160000 2102.220000 191.640000 ;
+ RECT 2101.120000 153.080000 2102.220000 153.560000 ;
+ RECT 2101.120000 158.520000 2102.220000 159.000000 ;
+ RECT 2101.120000 163.960000 2102.220000 164.440000 ;
+ RECT 2101.120000 169.400000 2102.220000 169.880000 ;
+ RECT 2052.290000 174.840000 2053.290000 175.320000 ;
+ RECT 2052.290000 180.280000 2053.290000 180.760000 ;
+ RECT 2052.290000 185.720000 2053.290000 186.200000 ;
+ RECT 2052.290000 191.160000 2053.290000 191.640000 ;
+ RECT 2052.290000 153.080000 2053.290000 153.560000 ;
+ RECT 2052.290000 158.520000 2053.290000 159.000000 ;
+ RECT 2052.290000 163.960000 2053.290000 164.440000 ;
+ RECT 2052.290000 169.400000 2053.290000 169.880000 ;
+ RECT 2055.955000 185.720000 2057.220000 186.200000 ;
+ RECT 2055.955000 180.280000 2057.220000 180.760000 ;
+ RECT 2055.955000 174.840000 2057.220000 175.320000 ;
+ RECT 2055.955000 191.160000 2057.220000 191.640000 ;
+ RECT 2055.955000 169.400000 2057.220000 169.880000 ;
+ RECT 2055.955000 163.960000 2057.220000 164.440000 ;
+ RECT 2055.955000 158.520000 2057.220000 159.000000 ;
+ RECT 2055.955000 153.080000 2057.220000 153.560000 ;
+ RECT 2146.120000 245.560000 2147.220000 246.040000 ;
+ RECT 2101.120000 245.560000 2102.220000 246.040000 ;
+ RECT 2052.290000 245.560000 2053.290000 246.040000 ;
+ RECT 2055.955000 245.560000 2057.220000 246.040000 ;
+ RECT 2158.770000 245.560000 2159.770000 246.040000 ;
+ RECT 2051.060000 342.320000 2161.000000 343.320000 ;
+ RECT 2051.060000 146.750000 2161.000000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 145.500000 2053.290000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 344.760000 2053.290000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 145.500000 2159.770000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 344.760000 2159.770000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 146.750000 2052.060000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 146.750000 2161.000000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 342.320000 2052.060000 343.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 342.320000 2161.000000 343.320000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'S_term_RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 139.140000 2057.220000 139.620000 ;
+ RECT 2055.955000 133.700000 2057.220000 134.180000 ;
+ RECT 2055.955000 128.260000 2057.220000 128.740000 ;
+ RECT 2055.955000 122.820000 2057.220000 123.300000 ;
+ RECT 2052.290000 115.240000 2053.290000 145.500000 ;
+ RECT 2158.770000 115.240000 2159.770000 145.500000 ;
+ RECT 2056.120000 116.490000 2057.220000 143.740000 ;
+ RECT 2101.120000 116.490000 2102.220000 143.740000 ;
+ RECT 2146.120000 116.490000 2147.220000 143.740000 ;
+ LAYER met3 ;
+ RECT 2158.770000 139.140000 2159.770000 139.620000 ;
+ RECT 2158.770000 133.700000 2159.770000 134.180000 ;
+ RECT 2146.120000 139.140000 2147.220000 139.620000 ;
+ RECT 2146.120000 133.700000 2147.220000 134.180000 ;
+ RECT 2101.120000 133.700000 2102.220000 134.180000 ;
+ RECT 2101.120000 139.140000 2102.220000 139.620000 ;
+ RECT 2052.290000 139.140000 2053.290000 139.620000 ;
+ RECT 2055.955000 139.140000 2057.220000 139.620000 ;
+ RECT 2055.955000 133.700000 2057.220000 134.180000 ;
+ RECT 2052.290000 133.700000 2053.290000 134.180000 ;
+ RECT 2158.770000 128.260000 2159.770000 128.740000 ;
+ RECT 2158.770000 122.820000 2159.770000 123.300000 ;
+ RECT 2146.120000 128.260000 2147.220000 128.740000 ;
+ RECT 2146.120000 122.820000 2147.220000 123.300000 ;
+ RECT 2101.120000 122.820000 2102.220000 123.300000 ;
+ RECT 2101.120000 128.260000 2102.220000 128.740000 ;
+ RECT 2055.955000 128.260000 2057.220000 128.740000 ;
+ RECT 2052.290000 128.260000 2053.290000 128.740000 ;
+ RECT 2055.955000 122.820000 2057.220000 123.300000 ;
+ RECT 2052.290000 122.820000 2053.290000 123.300000 ;
+ RECT 2051.060000 142.740000 2161.000000 143.740000 ;
+ RECT 2051.060000 116.490000 2161.000000 117.490000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 115.240000 2053.290000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 144.500000 2053.290000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 115.240000 2159.770000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 144.500000 2159.770000 145.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 116.490000 2052.060000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 116.490000 2161.000000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 142.740000 2052.060000 143.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 142.740000 2161.000000 143.740000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 3336.500000 2057.220000 3336.980000 ;
+ RECT 2055.955000 3331.060000 2057.220000 3331.540000 ;
+ RECT 2055.955000 3325.620000 2057.220000 3326.100000 ;
+ RECT 2055.955000 3341.940000 2057.220000 3342.420000 ;
+ RECT 2055.955000 3320.180000 2057.220000 3320.660000 ;
+ RECT 2055.955000 3314.740000 2057.220000 3315.220000 ;
+ RECT 2055.955000 3309.300000 2057.220000 3309.780000 ;
+ RECT 2055.955000 3303.860000 2057.220000 3304.340000 ;
+ RECT 2055.955000 3287.540000 2057.220000 3288.020000 ;
+ RECT 2055.955000 3282.100000 2057.220000 3282.580000 ;
+ RECT 2055.955000 3276.660000 2057.220000 3277.140000 ;
+ RECT 2055.955000 3292.980000 2057.220000 3293.460000 ;
+ RECT 2055.955000 3298.420000 2057.220000 3298.900000 ;
+ RECT 2055.955000 3271.220000 2057.220000 3271.700000 ;
+ RECT 2055.955000 3265.780000 2057.220000 3266.260000 ;
+ RECT 2055.955000 3260.340000 2057.220000 3260.820000 ;
+ RECT 2055.955000 3254.900000 2057.220000 3255.380000 ;
+ RECT 2055.955000 3233.140000 2057.220000 3233.620000 ;
+ RECT 2055.955000 3227.700000 2057.220000 3228.180000 ;
+ RECT 2055.955000 3238.580000 2057.220000 3239.060000 ;
+ RECT 2055.955000 3244.020000 2057.220000 3244.500000 ;
+ RECT 2055.955000 3222.260000 2057.220000 3222.740000 ;
+ RECT 2055.955000 3216.820000 2057.220000 3217.300000 ;
+ RECT 2055.955000 3211.380000 2057.220000 3211.860000 ;
+ RECT 2055.955000 3205.940000 2057.220000 3206.420000 ;
+ RECT 2055.955000 3200.500000 2057.220000 3200.980000 ;
+ RECT 2055.955000 3189.620000 2057.220000 3190.100000 ;
+ RECT 2055.955000 3184.180000 2057.220000 3184.660000 ;
+ RECT 2055.955000 3178.740000 2057.220000 3179.220000 ;
+ RECT 2055.955000 3195.060000 2057.220000 3195.540000 ;
+ RECT 2055.955000 3173.300000 2057.220000 3173.780000 ;
+ RECT 2055.955000 3167.860000 2057.220000 3168.340000 ;
+ RECT 2055.955000 3162.420000 2057.220000 3162.900000 ;
+ RECT 2055.955000 3156.980000 2057.220000 3157.460000 ;
+ RECT 2055.955000 3249.460000 2057.220000 3249.940000 ;
+ RECT 2052.290000 3149.400000 2053.290000 3349.660000 ;
+ RECT 2158.770000 3149.400000 2159.770000 3349.660000 ;
+ RECT 2056.120000 3150.650000 2057.220000 3347.220000 ;
+ RECT 2101.120000 3150.650000 2102.220000 3347.220000 ;
+ RECT 2146.120000 3150.650000 2147.220000 3347.220000 ;
+ LAYER met3 ;
+ RECT 2158.770000 3325.620000 2159.770000 3326.100000 ;
+ RECT 2158.770000 3331.060000 2159.770000 3331.540000 ;
+ RECT 2158.770000 3336.500000 2159.770000 3336.980000 ;
+ RECT 2158.770000 3341.940000 2159.770000 3342.420000 ;
+ RECT 2158.770000 3309.300000 2159.770000 3309.780000 ;
+ RECT 2158.770000 3303.860000 2159.770000 3304.340000 ;
+ RECT 2158.770000 3314.740000 2159.770000 3315.220000 ;
+ RECT 2158.770000 3320.180000 2159.770000 3320.660000 ;
+ RECT 2146.120000 3325.620000 2147.220000 3326.100000 ;
+ RECT 2146.120000 3331.060000 2147.220000 3331.540000 ;
+ RECT 2146.120000 3336.500000 2147.220000 3336.980000 ;
+ RECT 2146.120000 3341.940000 2147.220000 3342.420000 ;
+ RECT 2146.120000 3309.300000 2147.220000 3309.780000 ;
+ RECT 2146.120000 3303.860000 2147.220000 3304.340000 ;
+ RECT 2146.120000 3314.740000 2147.220000 3315.220000 ;
+ RECT 2146.120000 3320.180000 2147.220000 3320.660000 ;
+ RECT 2158.770000 3276.660000 2159.770000 3277.140000 ;
+ RECT 2158.770000 3282.100000 2159.770000 3282.580000 ;
+ RECT 2158.770000 3287.540000 2159.770000 3288.020000 ;
+ RECT 2158.770000 3292.980000 2159.770000 3293.460000 ;
+ RECT 2158.770000 3298.420000 2159.770000 3298.900000 ;
+ RECT 2158.770000 3254.900000 2159.770000 3255.380000 ;
+ RECT 2158.770000 3260.340000 2159.770000 3260.820000 ;
+ RECT 2158.770000 3265.780000 2159.770000 3266.260000 ;
+ RECT 2158.770000 3271.220000 2159.770000 3271.700000 ;
+ RECT 2146.120000 3276.660000 2147.220000 3277.140000 ;
+ RECT 2146.120000 3282.100000 2147.220000 3282.580000 ;
+ RECT 2146.120000 3287.540000 2147.220000 3288.020000 ;
+ RECT 2146.120000 3292.980000 2147.220000 3293.460000 ;
+ RECT 2146.120000 3298.420000 2147.220000 3298.900000 ;
+ RECT 2146.120000 3260.340000 2147.220000 3260.820000 ;
+ RECT 2146.120000 3254.900000 2147.220000 3255.380000 ;
+ RECT 2146.120000 3265.780000 2147.220000 3266.260000 ;
+ RECT 2146.120000 3271.220000 2147.220000 3271.700000 ;
+ RECT 2101.120000 3331.060000 2102.220000 3331.540000 ;
+ RECT 2101.120000 3325.620000 2102.220000 3326.100000 ;
+ RECT 2101.120000 3336.500000 2102.220000 3336.980000 ;
+ RECT 2101.120000 3341.940000 2102.220000 3342.420000 ;
+ RECT 2101.120000 3303.860000 2102.220000 3304.340000 ;
+ RECT 2101.120000 3309.300000 2102.220000 3309.780000 ;
+ RECT 2101.120000 3314.740000 2102.220000 3315.220000 ;
+ RECT 2101.120000 3320.180000 2102.220000 3320.660000 ;
+ RECT 2052.290000 3325.620000 2053.290000 3326.100000 ;
+ RECT 2052.290000 3331.060000 2053.290000 3331.540000 ;
+ RECT 2052.290000 3336.500000 2053.290000 3336.980000 ;
+ RECT 2052.290000 3341.940000 2053.290000 3342.420000 ;
+ RECT 2052.290000 3309.300000 2053.290000 3309.780000 ;
+ RECT 2052.290000 3303.860000 2053.290000 3304.340000 ;
+ RECT 2052.290000 3314.740000 2053.290000 3315.220000 ;
+ RECT 2052.290000 3320.180000 2053.290000 3320.660000 ;
+ RECT 2055.955000 3336.500000 2057.220000 3336.980000 ;
+ RECT 2055.955000 3331.060000 2057.220000 3331.540000 ;
+ RECT 2055.955000 3325.620000 2057.220000 3326.100000 ;
+ RECT 2055.955000 3341.940000 2057.220000 3342.420000 ;
+ RECT 2055.955000 3320.180000 2057.220000 3320.660000 ;
+ RECT 2055.955000 3314.740000 2057.220000 3315.220000 ;
+ RECT 2055.955000 3309.300000 2057.220000 3309.780000 ;
+ RECT 2055.955000 3303.860000 2057.220000 3304.340000 ;
+ RECT 2101.120000 3276.660000 2102.220000 3277.140000 ;
+ RECT 2101.120000 3282.100000 2102.220000 3282.580000 ;
+ RECT 2101.120000 3287.540000 2102.220000 3288.020000 ;
+ RECT 2101.120000 3292.980000 2102.220000 3293.460000 ;
+ RECT 2101.120000 3298.420000 2102.220000 3298.900000 ;
+ RECT 2101.120000 3254.900000 2102.220000 3255.380000 ;
+ RECT 2101.120000 3260.340000 2102.220000 3260.820000 ;
+ RECT 2101.120000 3265.780000 2102.220000 3266.260000 ;
+ RECT 2101.120000 3271.220000 2102.220000 3271.700000 ;
+ RECT 2052.290000 3276.660000 2053.290000 3277.140000 ;
+ RECT 2052.290000 3282.100000 2053.290000 3282.580000 ;
+ RECT 2052.290000 3287.540000 2053.290000 3288.020000 ;
+ RECT 2052.290000 3292.980000 2053.290000 3293.460000 ;
+ RECT 2052.290000 3298.420000 2053.290000 3298.900000 ;
+ RECT 2052.290000 3254.900000 2053.290000 3255.380000 ;
+ RECT 2052.290000 3260.340000 2053.290000 3260.820000 ;
+ RECT 2052.290000 3265.780000 2053.290000 3266.260000 ;
+ RECT 2052.290000 3271.220000 2053.290000 3271.700000 ;
+ RECT 2055.955000 3287.540000 2057.220000 3288.020000 ;
+ RECT 2055.955000 3282.100000 2057.220000 3282.580000 ;
+ RECT 2055.955000 3276.660000 2057.220000 3277.140000 ;
+ RECT 2055.955000 3292.980000 2057.220000 3293.460000 ;
+ RECT 2055.955000 3298.420000 2057.220000 3298.900000 ;
+ RECT 2055.955000 3271.220000 2057.220000 3271.700000 ;
+ RECT 2055.955000 3265.780000 2057.220000 3266.260000 ;
+ RECT 2055.955000 3260.340000 2057.220000 3260.820000 ;
+ RECT 2055.955000 3254.900000 2057.220000 3255.380000 ;
+ RECT 2158.770000 3227.700000 2159.770000 3228.180000 ;
+ RECT 2158.770000 3233.140000 2159.770000 3233.620000 ;
+ RECT 2158.770000 3238.580000 2159.770000 3239.060000 ;
+ RECT 2158.770000 3244.020000 2159.770000 3244.500000 ;
+ RECT 2158.770000 3200.500000 2159.770000 3200.980000 ;
+ RECT 2158.770000 3205.940000 2159.770000 3206.420000 ;
+ RECT 2158.770000 3211.380000 2159.770000 3211.860000 ;
+ RECT 2158.770000 3216.820000 2159.770000 3217.300000 ;
+ RECT 2158.770000 3222.260000 2159.770000 3222.740000 ;
+ RECT 2146.120000 3227.700000 2147.220000 3228.180000 ;
+ RECT 2146.120000 3233.140000 2147.220000 3233.620000 ;
+ RECT 2146.120000 3238.580000 2147.220000 3239.060000 ;
+ RECT 2146.120000 3244.020000 2147.220000 3244.500000 ;
+ RECT 2146.120000 3205.940000 2147.220000 3206.420000 ;
+ RECT 2146.120000 3200.500000 2147.220000 3200.980000 ;
+ RECT 2146.120000 3211.380000 2147.220000 3211.860000 ;
+ RECT 2146.120000 3216.820000 2147.220000 3217.300000 ;
+ RECT 2146.120000 3222.260000 2147.220000 3222.740000 ;
+ RECT 2158.770000 3178.740000 2159.770000 3179.220000 ;
+ RECT 2158.770000 3184.180000 2159.770000 3184.660000 ;
+ RECT 2158.770000 3189.620000 2159.770000 3190.100000 ;
+ RECT 2158.770000 3195.060000 2159.770000 3195.540000 ;
+ RECT 2158.770000 3156.980000 2159.770000 3157.460000 ;
+ RECT 2158.770000 3162.420000 2159.770000 3162.900000 ;
+ RECT 2158.770000 3167.860000 2159.770000 3168.340000 ;
+ RECT 2158.770000 3173.300000 2159.770000 3173.780000 ;
+ RECT 2146.120000 3178.740000 2147.220000 3179.220000 ;
+ RECT 2146.120000 3184.180000 2147.220000 3184.660000 ;
+ RECT 2146.120000 3189.620000 2147.220000 3190.100000 ;
+ RECT 2146.120000 3195.060000 2147.220000 3195.540000 ;
+ RECT 2146.120000 3156.980000 2147.220000 3157.460000 ;
+ RECT 2146.120000 3162.420000 2147.220000 3162.900000 ;
+ RECT 2146.120000 3167.860000 2147.220000 3168.340000 ;
+ RECT 2146.120000 3173.300000 2147.220000 3173.780000 ;
+ RECT 2101.120000 3227.700000 2102.220000 3228.180000 ;
+ RECT 2101.120000 3233.140000 2102.220000 3233.620000 ;
+ RECT 2101.120000 3238.580000 2102.220000 3239.060000 ;
+ RECT 2101.120000 3244.020000 2102.220000 3244.500000 ;
+ RECT 2101.120000 3200.500000 2102.220000 3200.980000 ;
+ RECT 2101.120000 3205.940000 2102.220000 3206.420000 ;
+ RECT 2101.120000 3211.380000 2102.220000 3211.860000 ;
+ RECT 2101.120000 3216.820000 2102.220000 3217.300000 ;
+ RECT 2101.120000 3222.260000 2102.220000 3222.740000 ;
+ RECT 2052.290000 3227.700000 2053.290000 3228.180000 ;
+ RECT 2052.290000 3233.140000 2053.290000 3233.620000 ;
+ RECT 2052.290000 3238.580000 2053.290000 3239.060000 ;
+ RECT 2052.290000 3244.020000 2053.290000 3244.500000 ;
+ RECT 2052.290000 3200.500000 2053.290000 3200.980000 ;
+ RECT 2052.290000 3205.940000 2053.290000 3206.420000 ;
+ RECT 2052.290000 3211.380000 2053.290000 3211.860000 ;
+ RECT 2052.290000 3216.820000 2053.290000 3217.300000 ;
+ RECT 2052.290000 3222.260000 2053.290000 3222.740000 ;
+ RECT 2055.955000 3233.140000 2057.220000 3233.620000 ;
+ RECT 2055.955000 3227.700000 2057.220000 3228.180000 ;
+ RECT 2055.955000 3238.580000 2057.220000 3239.060000 ;
+ RECT 2055.955000 3244.020000 2057.220000 3244.500000 ;
+ RECT 2055.955000 3222.260000 2057.220000 3222.740000 ;
+ RECT 2055.955000 3216.820000 2057.220000 3217.300000 ;
+ RECT 2055.955000 3211.380000 2057.220000 3211.860000 ;
+ RECT 2055.955000 3205.940000 2057.220000 3206.420000 ;
+ RECT 2055.955000 3200.500000 2057.220000 3200.980000 ;
+ RECT 2101.120000 3178.740000 2102.220000 3179.220000 ;
+ RECT 2101.120000 3184.180000 2102.220000 3184.660000 ;
+ RECT 2101.120000 3189.620000 2102.220000 3190.100000 ;
+ RECT 2101.120000 3195.060000 2102.220000 3195.540000 ;
+ RECT 2101.120000 3156.980000 2102.220000 3157.460000 ;
+ RECT 2101.120000 3162.420000 2102.220000 3162.900000 ;
+ RECT 2101.120000 3167.860000 2102.220000 3168.340000 ;
+ RECT 2101.120000 3173.300000 2102.220000 3173.780000 ;
+ RECT 2052.290000 3178.740000 2053.290000 3179.220000 ;
+ RECT 2052.290000 3184.180000 2053.290000 3184.660000 ;
+ RECT 2052.290000 3189.620000 2053.290000 3190.100000 ;
+ RECT 2052.290000 3195.060000 2053.290000 3195.540000 ;
+ RECT 2052.290000 3156.980000 2053.290000 3157.460000 ;
+ RECT 2052.290000 3162.420000 2053.290000 3162.900000 ;
+ RECT 2052.290000 3167.860000 2053.290000 3168.340000 ;
+ RECT 2052.290000 3173.300000 2053.290000 3173.780000 ;
+ RECT 2055.955000 3189.620000 2057.220000 3190.100000 ;
+ RECT 2055.955000 3184.180000 2057.220000 3184.660000 ;
+ RECT 2055.955000 3178.740000 2057.220000 3179.220000 ;
+ RECT 2055.955000 3195.060000 2057.220000 3195.540000 ;
+ RECT 2055.955000 3173.300000 2057.220000 3173.780000 ;
+ RECT 2055.955000 3167.860000 2057.220000 3168.340000 ;
+ RECT 2055.955000 3162.420000 2057.220000 3162.900000 ;
+ RECT 2055.955000 3156.980000 2057.220000 3157.460000 ;
+ RECT 2146.120000 3249.460000 2147.220000 3249.940000 ;
+ RECT 2101.120000 3249.460000 2102.220000 3249.940000 ;
+ RECT 2052.290000 3249.460000 2053.290000 3249.940000 ;
+ RECT 2055.955000 3249.460000 2057.220000 3249.940000 ;
+ RECT 2158.770000 3249.460000 2159.770000 3249.940000 ;
+ RECT 2051.060000 3346.220000 2161.000000 3347.220000 ;
+ RECT 2051.060000 3150.650000 2161.000000 3151.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 3149.400000 2053.290000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 3348.660000 2053.290000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 3149.400000 2159.770000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 3348.660000 2159.770000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 3150.650000 2052.060000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 3150.650000 2161.000000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 3346.220000 2052.060000 3347.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 3346.220000 2161.000000 3347.220000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 3136.240000 2057.220000 3136.720000 ;
+ RECT 2055.955000 3130.800000 2057.220000 3131.280000 ;
+ RECT 2055.955000 3125.360000 2057.220000 3125.840000 ;
+ RECT 2055.955000 3141.680000 2057.220000 3142.160000 ;
+ RECT 2055.955000 3119.920000 2057.220000 3120.400000 ;
+ RECT 2055.955000 3114.480000 2057.220000 3114.960000 ;
+ RECT 2055.955000 3109.040000 2057.220000 3109.520000 ;
+ RECT 2055.955000 3103.600000 2057.220000 3104.080000 ;
+ RECT 2055.955000 3087.280000 2057.220000 3087.760000 ;
+ RECT 2055.955000 3081.840000 2057.220000 3082.320000 ;
+ RECT 2055.955000 3076.400000 2057.220000 3076.880000 ;
+ RECT 2055.955000 3092.720000 2057.220000 3093.200000 ;
+ RECT 2055.955000 3098.160000 2057.220000 3098.640000 ;
+ RECT 2055.955000 3070.960000 2057.220000 3071.440000 ;
+ RECT 2055.955000 3065.520000 2057.220000 3066.000000 ;
+ RECT 2055.955000 3060.080000 2057.220000 3060.560000 ;
+ RECT 2055.955000 3054.640000 2057.220000 3055.120000 ;
+ RECT 2055.955000 3032.880000 2057.220000 3033.360000 ;
+ RECT 2055.955000 3027.440000 2057.220000 3027.920000 ;
+ RECT 2055.955000 3038.320000 2057.220000 3038.800000 ;
+ RECT 2055.955000 3043.760000 2057.220000 3044.240000 ;
+ RECT 2055.955000 3022.000000 2057.220000 3022.480000 ;
+ RECT 2055.955000 3016.560000 2057.220000 3017.040000 ;
+ RECT 2055.955000 3011.120000 2057.220000 3011.600000 ;
+ RECT 2055.955000 3005.680000 2057.220000 3006.160000 ;
+ RECT 2055.955000 3000.240000 2057.220000 3000.720000 ;
+ RECT 2055.955000 2989.360000 2057.220000 2989.840000 ;
+ RECT 2055.955000 2983.920000 2057.220000 2984.400000 ;
+ RECT 2055.955000 2978.480000 2057.220000 2978.960000 ;
+ RECT 2055.955000 2994.800000 2057.220000 2995.280000 ;
+ RECT 2055.955000 2973.040000 2057.220000 2973.520000 ;
+ RECT 2055.955000 2967.600000 2057.220000 2968.080000 ;
+ RECT 2055.955000 2962.160000 2057.220000 2962.640000 ;
+ RECT 2055.955000 2956.720000 2057.220000 2957.200000 ;
+ RECT 2055.955000 3049.200000 2057.220000 3049.680000 ;
+ RECT 2052.290000 2949.140000 2053.290000 3149.400000 ;
+ RECT 2158.770000 2949.140000 2159.770000 3149.400000 ;
+ RECT 2056.120000 2950.390000 2057.220000 3146.960000 ;
+ RECT 2101.120000 2950.390000 2102.220000 3146.960000 ;
+ RECT 2146.120000 2950.390000 2147.220000 3146.960000 ;
+ LAYER met3 ;
+ RECT 2158.770000 3125.360000 2159.770000 3125.840000 ;
+ RECT 2158.770000 3130.800000 2159.770000 3131.280000 ;
+ RECT 2158.770000 3136.240000 2159.770000 3136.720000 ;
+ RECT 2158.770000 3141.680000 2159.770000 3142.160000 ;
+ RECT 2158.770000 3109.040000 2159.770000 3109.520000 ;
+ RECT 2158.770000 3103.600000 2159.770000 3104.080000 ;
+ RECT 2158.770000 3114.480000 2159.770000 3114.960000 ;
+ RECT 2158.770000 3119.920000 2159.770000 3120.400000 ;
+ RECT 2146.120000 3125.360000 2147.220000 3125.840000 ;
+ RECT 2146.120000 3130.800000 2147.220000 3131.280000 ;
+ RECT 2146.120000 3136.240000 2147.220000 3136.720000 ;
+ RECT 2146.120000 3141.680000 2147.220000 3142.160000 ;
+ RECT 2146.120000 3109.040000 2147.220000 3109.520000 ;
+ RECT 2146.120000 3103.600000 2147.220000 3104.080000 ;
+ RECT 2146.120000 3114.480000 2147.220000 3114.960000 ;
+ RECT 2146.120000 3119.920000 2147.220000 3120.400000 ;
+ RECT 2158.770000 3076.400000 2159.770000 3076.880000 ;
+ RECT 2158.770000 3081.840000 2159.770000 3082.320000 ;
+ RECT 2158.770000 3087.280000 2159.770000 3087.760000 ;
+ RECT 2158.770000 3092.720000 2159.770000 3093.200000 ;
+ RECT 2158.770000 3098.160000 2159.770000 3098.640000 ;
+ RECT 2158.770000 3054.640000 2159.770000 3055.120000 ;
+ RECT 2158.770000 3060.080000 2159.770000 3060.560000 ;
+ RECT 2158.770000 3065.520000 2159.770000 3066.000000 ;
+ RECT 2158.770000 3070.960000 2159.770000 3071.440000 ;
+ RECT 2146.120000 3076.400000 2147.220000 3076.880000 ;
+ RECT 2146.120000 3081.840000 2147.220000 3082.320000 ;
+ RECT 2146.120000 3087.280000 2147.220000 3087.760000 ;
+ RECT 2146.120000 3092.720000 2147.220000 3093.200000 ;
+ RECT 2146.120000 3098.160000 2147.220000 3098.640000 ;
+ RECT 2146.120000 3060.080000 2147.220000 3060.560000 ;
+ RECT 2146.120000 3054.640000 2147.220000 3055.120000 ;
+ RECT 2146.120000 3065.520000 2147.220000 3066.000000 ;
+ RECT 2146.120000 3070.960000 2147.220000 3071.440000 ;
+ RECT 2101.120000 3130.800000 2102.220000 3131.280000 ;
+ RECT 2101.120000 3125.360000 2102.220000 3125.840000 ;
+ RECT 2101.120000 3136.240000 2102.220000 3136.720000 ;
+ RECT 2101.120000 3141.680000 2102.220000 3142.160000 ;
+ RECT 2101.120000 3103.600000 2102.220000 3104.080000 ;
+ RECT 2101.120000 3109.040000 2102.220000 3109.520000 ;
+ RECT 2101.120000 3114.480000 2102.220000 3114.960000 ;
+ RECT 2101.120000 3119.920000 2102.220000 3120.400000 ;
+ RECT 2052.290000 3125.360000 2053.290000 3125.840000 ;
+ RECT 2052.290000 3130.800000 2053.290000 3131.280000 ;
+ RECT 2052.290000 3136.240000 2053.290000 3136.720000 ;
+ RECT 2052.290000 3141.680000 2053.290000 3142.160000 ;
+ RECT 2052.290000 3109.040000 2053.290000 3109.520000 ;
+ RECT 2052.290000 3103.600000 2053.290000 3104.080000 ;
+ RECT 2052.290000 3114.480000 2053.290000 3114.960000 ;
+ RECT 2052.290000 3119.920000 2053.290000 3120.400000 ;
+ RECT 2055.955000 3136.240000 2057.220000 3136.720000 ;
+ RECT 2055.955000 3130.800000 2057.220000 3131.280000 ;
+ RECT 2055.955000 3125.360000 2057.220000 3125.840000 ;
+ RECT 2055.955000 3141.680000 2057.220000 3142.160000 ;
+ RECT 2055.955000 3119.920000 2057.220000 3120.400000 ;
+ RECT 2055.955000 3114.480000 2057.220000 3114.960000 ;
+ RECT 2055.955000 3109.040000 2057.220000 3109.520000 ;
+ RECT 2055.955000 3103.600000 2057.220000 3104.080000 ;
+ RECT 2101.120000 3076.400000 2102.220000 3076.880000 ;
+ RECT 2101.120000 3081.840000 2102.220000 3082.320000 ;
+ RECT 2101.120000 3087.280000 2102.220000 3087.760000 ;
+ RECT 2101.120000 3092.720000 2102.220000 3093.200000 ;
+ RECT 2101.120000 3098.160000 2102.220000 3098.640000 ;
+ RECT 2101.120000 3054.640000 2102.220000 3055.120000 ;
+ RECT 2101.120000 3060.080000 2102.220000 3060.560000 ;
+ RECT 2101.120000 3065.520000 2102.220000 3066.000000 ;
+ RECT 2101.120000 3070.960000 2102.220000 3071.440000 ;
+ RECT 2052.290000 3076.400000 2053.290000 3076.880000 ;
+ RECT 2052.290000 3081.840000 2053.290000 3082.320000 ;
+ RECT 2052.290000 3087.280000 2053.290000 3087.760000 ;
+ RECT 2052.290000 3092.720000 2053.290000 3093.200000 ;
+ RECT 2052.290000 3098.160000 2053.290000 3098.640000 ;
+ RECT 2052.290000 3054.640000 2053.290000 3055.120000 ;
+ RECT 2052.290000 3060.080000 2053.290000 3060.560000 ;
+ RECT 2052.290000 3065.520000 2053.290000 3066.000000 ;
+ RECT 2052.290000 3070.960000 2053.290000 3071.440000 ;
+ RECT 2055.955000 3087.280000 2057.220000 3087.760000 ;
+ RECT 2055.955000 3081.840000 2057.220000 3082.320000 ;
+ RECT 2055.955000 3076.400000 2057.220000 3076.880000 ;
+ RECT 2055.955000 3092.720000 2057.220000 3093.200000 ;
+ RECT 2055.955000 3098.160000 2057.220000 3098.640000 ;
+ RECT 2055.955000 3070.960000 2057.220000 3071.440000 ;
+ RECT 2055.955000 3065.520000 2057.220000 3066.000000 ;
+ RECT 2055.955000 3060.080000 2057.220000 3060.560000 ;
+ RECT 2055.955000 3054.640000 2057.220000 3055.120000 ;
+ RECT 2158.770000 3027.440000 2159.770000 3027.920000 ;
+ RECT 2158.770000 3032.880000 2159.770000 3033.360000 ;
+ RECT 2158.770000 3038.320000 2159.770000 3038.800000 ;
+ RECT 2158.770000 3043.760000 2159.770000 3044.240000 ;
+ RECT 2158.770000 3000.240000 2159.770000 3000.720000 ;
+ RECT 2158.770000 3005.680000 2159.770000 3006.160000 ;
+ RECT 2158.770000 3011.120000 2159.770000 3011.600000 ;
+ RECT 2158.770000 3016.560000 2159.770000 3017.040000 ;
+ RECT 2158.770000 3022.000000 2159.770000 3022.480000 ;
+ RECT 2146.120000 3027.440000 2147.220000 3027.920000 ;
+ RECT 2146.120000 3032.880000 2147.220000 3033.360000 ;
+ RECT 2146.120000 3038.320000 2147.220000 3038.800000 ;
+ RECT 2146.120000 3043.760000 2147.220000 3044.240000 ;
+ RECT 2146.120000 3005.680000 2147.220000 3006.160000 ;
+ RECT 2146.120000 3000.240000 2147.220000 3000.720000 ;
+ RECT 2146.120000 3011.120000 2147.220000 3011.600000 ;
+ RECT 2146.120000 3016.560000 2147.220000 3017.040000 ;
+ RECT 2146.120000 3022.000000 2147.220000 3022.480000 ;
+ RECT 2158.770000 2978.480000 2159.770000 2978.960000 ;
+ RECT 2158.770000 2983.920000 2159.770000 2984.400000 ;
+ RECT 2158.770000 2989.360000 2159.770000 2989.840000 ;
+ RECT 2158.770000 2994.800000 2159.770000 2995.280000 ;
+ RECT 2158.770000 2956.720000 2159.770000 2957.200000 ;
+ RECT 2158.770000 2962.160000 2159.770000 2962.640000 ;
+ RECT 2158.770000 2967.600000 2159.770000 2968.080000 ;
+ RECT 2158.770000 2973.040000 2159.770000 2973.520000 ;
+ RECT 2146.120000 2978.480000 2147.220000 2978.960000 ;
+ RECT 2146.120000 2983.920000 2147.220000 2984.400000 ;
+ RECT 2146.120000 2989.360000 2147.220000 2989.840000 ;
+ RECT 2146.120000 2994.800000 2147.220000 2995.280000 ;
+ RECT 2146.120000 2956.720000 2147.220000 2957.200000 ;
+ RECT 2146.120000 2962.160000 2147.220000 2962.640000 ;
+ RECT 2146.120000 2967.600000 2147.220000 2968.080000 ;
+ RECT 2146.120000 2973.040000 2147.220000 2973.520000 ;
+ RECT 2101.120000 3027.440000 2102.220000 3027.920000 ;
+ RECT 2101.120000 3032.880000 2102.220000 3033.360000 ;
+ RECT 2101.120000 3038.320000 2102.220000 3038.800000 ;
+ RECT 2101.120000 3043.760000 2102.220000 3044.240000 ;
+ RECT 2101.120000 3000.240000 2102.220000 3000.720000 ;
+ RECT 2101.120000 3005.680000 2102.220000 3006.160000 ;
+ RECT 2101.120000 3011.120000 2102.220000 3011.600000 ;
+ RECT 2101.120000 3016.560000 2102.220000 3017.040000 ;
+ RECT 2101.120000 3022.000000 2102.220000 3022.480000 ;
+ RECT 2052.290000 3027.440000 2053.290000 3027.920000 ;
+ RECT 2052.290000 3032.880000 2053.290000 3033.360000 ;
+ RECT 2052.290000 3038.320000 2053.290000 3038.800000 ;
+ RECT 2052.290000 3043.760000 2053.290000 3044.240000 ;
+ RECT 2052.290000 3000.240000 2053.290000 3000.720000 ;
+ RECT 2052.290000 3005.680000 2053.290000 3006.160000 ;
+ RECT 2052.290000 3011.120000 2053.290000 3011.600000 ;
+ RECT 2052.290000 3016.560000 2053.290000 3017.040000 ;
+ RECT 2052.290000 3022.000000 2053.290000 3022.480000 ;
+ RECT 2055.955000 3032.880000 2057.220000 3033.360000 ;
+ RECT 2055.955000 3027.440000 2057.220000 3027.920000 ;
+ RECT 2055.955000 3038.320000 2057.220000 3038.800000 ;
+ RECT 2055.955000 3043.760000 2057.220000 3044.240000 ;
+ RECT 2055.955000 3022.000000 2057.220000 3022.480000 ;
+ RECT 2055.955000 3016.560000 2057.220000 3017.040000 ;
+ RECT 2055.955000 3011.120000 2057.220000 3011.600000 ;
+ RECT 2055.955000 3005.680000 2057.220000 3006.160000 ;
+ RECT 2055.955000 3000.240000 2057.220000 3000.720000 ;
+ RECT 2101.120000 2978.480000 2102.220000 2978.960000 ;
+ RECT 2101.120000 2983.920000 2102.220000 2984.400000 ;
+ RECT 2101.120000 2989.360000 2102.220000 2989.840000 ;
+ RECT 2101.120000 2994.800000 2102.220000 2995.280000 ;
+ RECT 2101.120000 2956.720000 2102.220000 2957.200000 ;
+ RECT 2101.120000 2962.160000 2102.220000 2962.640000 ;
+ RECT 2101.120000 2967.600000 2102.220000 2968.080000 ;
+ RECT 2101.120000 2973.040000 2102.220000 2973.520000 ;
+ RECT 2052.290000 2978.480000 2053.290000 2978.960000 ;
+ RECT 2052.290000 2983.920000 2053.290000 2984.400000 ;
+ RECT 2052.290000 2989.360000 2053.290000 2989.840000 ;
+ RECT 2052.290000 2994.800000 2053.290000 2995.280000 ;
+ RECT 2052.290000 2956.720000 2053.290000 2957.200000 ;
+ RECT 2052.290000 2962.160000 2053.290000 2962.640000 ;
+ RECT 2052.290000 2967.600000 2053.290000 2968.080000 ;
+ RECT 2052.290000 2973.040000 2053.290000 2973.520000 ;
+ RECT 2055.955000 2989.360000 2057.220000 2989.840000 ;
+ RECT 2055.955000 2983.920000 2057.220000 2984.400000 ;
+ RECT 2055.955000 2978.480000 2057.220000 2978.960000 ;
+ RECT 2055.955000 2994.800000 2057.220000 2995.280000 ;
+ RECT 2055.955000 2973.040000 2057.220000 2973.520000 ;
+ RECT 2055.955000 2967.600000 2057.220000 2968.080000 ;
+ RECT 2055.955000 2962.160000 2057.220000 2962.640000 ;
+ RECT 2055.955000 2956.720000 2057.220000 2957.200000 ;
+ RECT 2146.120000 3049.200000 2147.220000 3049.680000 ;
+ RECT 2101.120000 3049.200000 2102.220000 3049.680000 ;
+ RECT 2052.290000 3049.200000 2053.290000 3049.680000 ;
+ RECT 2055.955000 3049.200000 2057.220000 3049.680000 ;
+ RECT 2158.770000 3049.200000 2159.770000 3049.680000 ;
+ RECT 2051.060000 3145.960000 2161.000000 3146.960000 ;
+ RECT 2051.060000 2950.390000 2161.000000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 2949.140000 2053.290000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 3148.400000 2053.290000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 2949.140000 2159.770000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 3148.400000 2159.770000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2950.390000 2052.060000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2950.390000 2161.000000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 3145.960000 2052.060000 3146.960000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 3145.960000 2161.000000 3146.960000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 2935.980000 2057.220000 2936.460000 ;
+ RECT 2055.955000 2930.540000 2057.220000 2931.020000 ;
+ RECT 2055.955000 2925.100000 2057.220000 2925.580000 ;
+ RECT 2055.955000 2941.420000 2057.220000 2941.900000 ;
+ RECT 2055.955000 2919.660000 2057.220000 2920.140000 ;
+ RECT 2055.955000 2914.220000 2057.220000 2914.700000 ;
+ RECT 2055.955000 2908.780000 2057.220000 2909.260000 ;
+ RECT 2055.955000 2903.340000 2057.220000 2903.820000 ;
+ RECT 2055.955000 2887.020000 2057.220000 2887.500000 ;
+ RECT 2055.955000 2881.580000 2057.220000 2882.060000 ;
+ RECT 2055.955000 2876.140000 2057.220000 2876.620000 ;
+ RECT 2055.955000 2892.460000 2057.220000 2892.940000 ;
+ RECT 2055.955000 2897.900000 2057.220000 2898.380000 ;
+ RECT 2055.955000 2870.700000 2057.220000 2871.180000 ;
+ RECT 2055.955000 2865.260000 2057.220000 2865.740000 ;
+ RECT 2055.955000 2859.820000 2057.220000 2860.300000 ;
+ RECT 2055.955000 2854.380000 2057.220000 2854.860000 ;
+ RECT 2055.955000 2832.620000 2057.220000 2833.100000 ;
+ RECT 2055.955000 2827.180000 2057.220000 2827.660000 ;
+ RECT 2055.955000 2838.060000 2057.220000 2838.540000 ;
+ RECT 2055.955000 2843.500000 2057.220000 2843.980000 ;
+ RECT 2055.955000 2821.740000 2057.220000 2822.220000 ;
+ RECT 2055.955000 2816.300000 2057.220000 2816.780000 ;
+ RECT 2055.955000 2810.860000 2057.220000 2811.340000 ;
+ RECT 2055.955000 2805.420000 2057.220000 2805.900000 ;
+ RECT 2055.955000 2799.980000 2057.220000 2800.460000 ;
+ RECT 2055.955000 2789.100000 2057.220000 2789.580000 ;
+ RECT 2055.955000 2783.660000 2057.220000 2784.140000 ;
+ RECT 2055.955000 2778.220000 2057.220000 2778.700000 ;
+ RECT 2055.955000 2794.540000 2057.220000 2795.020000 ;
+ RECT 2055.955000 2772.780000 2057.220000 2773.260000 ;
+ RECT 2055.955000 2767.340000 2057.220000 2767.820000 ;
+ RECT 2055.955000 2761.900000 2057.220000 2762.380000 ;
+ RECT 2055.955000 2756.460000 2057.220000 2756.940000 ;
+ RECT 2055.955000 2848.940000 2057.220000 2849.420000 ;
+ RECT 2052.290000 2748.880000 2053.290000 2949.140000 ;
+ RECT 2158.770000 2748.880000 2159.770000 2949.140000 ;
+ RECT 2056.120000 2750.130000 2057.220000 2946.700000 ;
+ RECT 2101.120000 2750.130000 2102.220000 2946.700000 ;
+ RECT 2146.120000 2750.130000 2147.220000 2946.700000 ;
+ LAYER met3 ;
+ RECT 2158.770000 2925.100000 2159.770000 2925.580000 ;
+ RECT 2158.770000 2930.540000 2159.770000 2931.020000 ;
+ RECT 2158.770000 2935.980000 2159.770000 2936.460000 ;
+ RECT 2158.770000 2941.420000 2159.770000 2941.900000 ;
+ RECT 2158.770000 2908.780000 2159.770000 2909.260000 ;
+ RECT 2158.770000 2903.340000 2159.770000 2903.820000 ;
+ RECT 2158.770000 2914.220000 2159.770000 2914.700000 ;
+ RECT 2158.770000 2919.660000 2159.770000 2920.140000 ;
+ RECT 2146.120000 2925.100000 2147.220000 2925.580000 ;
+ RECT 2146.120000 2930.540000 2147.220000 2931.020000 ;
+ RECT 2146.120000 2935.980000 2147.220000 2936.460000 ;
+ RECT 2146.120000 2941.420000 2147.220000 2941.900000 ;
+ RECT 2146.120000 2908.780000 2147.220000 2909.260000 ;
+ RECT 2146.120000 2903.340000 2147.220000 2903.820000 ;
+ RECT 2146.120000 2914.220000 2147.220000 2914.700000 ;
+ RECT 2146.120000 2919.660000 2147.220000 2920.140000 ;
+ RECT 2158.770000 2876.140000 2159.770000 2876.620000 ;
+ RECT 2158.770000 2881.580000 2159.770000 2882.060000 ;
+ RECT 2158.770000 2887.020000 2159.770000 2887.500000 ;
+ RECT 2158.770000 2892.460000 2159.770000 2892.940000 ;
+ RECT 2158.770000 2897.900000 2159.770000 2898.380000 ;
+ RECT 2158.770000 2854.380000 2159.770000 2854.860000 ;
+ RECT 2158.770000 2859.820000 2159.770000 2860.300000 ;
+ RECT 2158.770000 2865.260000 2159.770000 2865.740000 ;
+ RECT 2158.770000 2870.700000 2159.770000 2871.180000 ;
+ RECT 2146.120000 2876.140000 2147.220000 2876.620000 ;
+ RECT 2146.120000 2881.580000 2147.220000 2882.060000 ;
+ RECT 2146.120000 2887.020000 2147.220000 2887.500000 ;
+ RECT 2146.120000 2892.460000 2147.220000 2892.940000 ;
+ RECT 2146.120000 2897.900000 2147.220000 2898.380000 ;
+ RECT 2146.120000 2859.820000 2147.220000 2860.300000 ;
+ RECT 2146.120000 2854.380000 2147.220000 2854.860000 ;
+ RECT 2146.120000 2865.260000 2147.220000 2865.740000 ;
+ RECT 2146.120000 2870.700000 2147.220000 2871.180000 ;
+ RECT 2101.120000 2930.540000 2102.220000 2931.020000 ;
+ RECT 2101.120000 2925.100000 2102.220000 2925.580000 ;
+ RECT 2101.120000 2935.980000 2102.220000 2936.460000 ;
+ RECT 2101.120000 2941.420000 2102.220000 2941.900000 ;
+ RECT 2101.120000 2903.340000 2102.220000 2903.820000 ;
+ RECT 2101.120000 2908.780000 2102.220000 2909.260000 ;
+ RECT 2101.120000 2914.220000 2102.220000 2914.700000 ;
+ RECT 2101.120000 2919.660000 2102.220000 2920.140000 ;
+ RECT 2052.290000 2925.100000 2053.290000 2925.580000 ;
+ RECT 2052.290000 2930.540000 2053.290000 2931.020000 ;
+ RECT 2052.290000 2935.980000 2053.290000 2936.460000 ;
+ RECT 2052.290000 2941.420000 2053.290000 2941.900000 ;
+ RECT 2052.290000 2908.780000 2053.290000 2909.260000 ;
+ RECT 2052.290000 2903.340000 2053.290000 2903.820000 ;
+ RECT 2052.290000 2914.220000 2053.290000 2914.700000 ;
+ RECT 2052.290000 2919.660000 2053.290000 2920.140000 ;
+ RECT 2055.955000 2935.980000 2057.220000 2936.460000 ;
+ RECT 2055.955000 2930.540000 2057.220000 2931.020000 ;
+ RECT 2055.955000 2925.100000 2057.220000 2925.580000 ;
+ RECT 2055.955000 2941.420000 2057.220000 2941.900000 ;
+ RECT 2055.955000 2919.660000 2057.220000 2920.140000 ;
+ RECT 2055.955000 2914.220000 2057.220000 2914.700000 ;
+ RECT 2055.955000 2908.780000 2057.220000 2909.260000 ;
+ RECT 2055.955000 2903.340000 2057.220000 2903.820000 ;
+ RECT 2101.120000 2876.140000 2102.220000 2876.620000 ;
+ RECT 2101.120000 2881.580000 2102.220000 2882.060000 ;
+ RECT 2101.120000 2887.020000 2102.220000 2887.500000 ;
+ RECT 2101.120000 2892.460000 2102.220000 2892.940000 ;
+ RECT 2101.120000 2897.900000 2102.220000 2898.380000 ;
+ RECT 2101.120000 2854.380000 2102.220000 2854.860000 ;
+ RECT 2101.120000 2859.820000 2102.220000 2860.300000 ;
+ RECT 2101.120000 2865.260000 2102.220000 2865.740000 ;
+ RECT 2101.120000 2870.700000 2102.220000 2871.180000 ;
+ RECT 2052.290000 2876.140000 2053.290000 2876.620000 ;
+ RECT 2052.290000 2881.580000 2053.290000 2882.060000 ;
+ RECT 2052.290000 2887.020000 2053.290000 2887.500000 ;
+ RECT 2052.290000 2892.460000 2053.290000 2892.940000 ;
+ RECT 2052.290000 2897.900000 2053.290000 2898.380000 ;
+ RECT 2052.290000 2854.380000 2053.290000 2854.860000 ;
+ RECT 2052.290000 2859.820000 2053.290000 2860.300000 ;
+ RECT 2052.290000 2865.260000 2053.290000 2865.740000 ;
+ RECT 2052.290000 2870.700000 2053.290000 2871.180000 ;
+ RECT 2055.955000 2887.020000 2057.220000 2887.500000 ;
+ RECT 2055.955000 2881.580000 2057.220000 2882.060000 ;
+ RECT 2055.955000 2876.140000 2057.220000 2876.620000 ;
+ RECT 2055.955000 2892.460000 2057.220000 2892.940000 ;
+ RECT 2055.955000 2897.900000 2057.220000 2898.380000 ;
+ RECT 2055.955000 2870.700000 2057.220000 2871.180000 ;
+ RECT 2055.955000 2865.260000 2057.220000 2865.740000 ;
+ RECT 2055.955000 2859.820000 2057.220000 2860.300000 ;
+ RECT 2055.955000 2854.380000 2057.220000 2854.860000 ;
+ RECT 2158.770000 2827.180000 2159.770000 2827.660000 ;
+ RECT 2158.770000 2832.620000 2159.770000 2833.100000 ;
+ RECT 2158.770000 2838.060000 2159.770000 2838.540000 ;
+ RECT 2158.770000 2843.500000 2159.770000 2843.980000 ;
+ RECT 2158.770000 2799.980000 2159.770000 2800.460000 ;
+ RECT 2158.770000 2805.420000 2159.770000 2805.900000 ;
+ RECT 2158.770000 2810.860000 2159.770000 2811.340000 ;
+ RECT 2158.770000 2816.300000 2159.770000 2816.780000 ;
+ RECT 2158.770000 2821.740000 2159.770000 2822.220000 ;
+ RECT 2146.120000 2827.180000 2147.220000 2827.660000 ;
+ RECT 2146.120000 2832.620000 2147.220000 2833.100000 ;
+ RECT 2146.120000 2838.060000 2147.220000 2838.540000 ;
+ RECT 2146.120000 2843.500000 2147.220000 2843.980000 ;
+ RECT 2146.120000 2805.420000 2147.220000 2805.900000 ;
+ RECT 2146.120000 2799.980000 2147.220000 2800.460000 ;
+ RECT 2146.120000 2810.860000 2147.220000 2811.340000 ;
+ RECT 2146.120000 2816.300000 2147.220000 2816.780000 ;
+ RECT 2146.120000 2821.740000 2147.220000 2822.220000 ;
+ RECT 2158.770000 2778.220000 2159.770000 2778.700000 ;
+ RECT 2158.770000 2783.660000 2159.770000 2784.140000 ;
+ RECT 2158.770000 2789.100000 2159.770000 2789.580000 ;
+ RECT 2158.770000 2794.540000 2159.770000 2795.020000 ;
+ RECT 2158.770000 2756.460000 2159.770000 2756.940000 ;
+ RECT 2158.770000 2761.900000 2159.770000 2762.380000 ;
+ RECT 2158.770000 2767.340000 2159.770000 2767.820000 ;
+ RECT 2158.770000 2772.780000 2159.770000 2773.260000 ;
+ RECT 2146.120000 2778.220000 2147.220000 2778.700000 ;
+ RECT 2146.120000 2783.660000 2147.220000 2784.140000 ;
+ RECT 2146.120000 2789.100000 2147.220000 2789.580000 ;
+ RECT 2146.120000 2794.540000 2147.220000 2795.020000 ;
+ RECT 2146.120000 2756.460000 2147.220000 2756.940000 ;
+ RECT 2146.120000 2761.900000 2147.220000 2762.380000 ;
+ RECT 2146.120000 2767.340000 2147.220000 2767.820000 ;
+ RECT 2146.120000 2772.780000 2147.220000 2773.260000 ;
+ RECT 2101.120000 2827.180000 2102.220000 2827.660000 ;
+ RECT 2101.120000 2832.620000 2102.220000 2833.100000 ;
+ RECT 2101.120000 2838.060000 2102.220000 2838.540000 ;
+ RECT 2101.120000 2843.500000 2102.220000 2843.980000 ;
+ RECT 2101.120000 2799.980000 2102.220000 2800.460000 ;
+ RECT 2101.120000 2805.420000 2102.220000 2805.900000 ;
+ RECT 2101.120000 2810.860000 2102.220000 2811.340000 ;
+ RECT 2101.120000 2816.300000 2102.220000 2816.780000 ;
+ RECT 2101.120000 2821.740000 2102.220000 2822.220000 ;
+ RECT 2052.290000 2827.180000 2053.290000 2827.660000 ;
+ RECT 2052.290000 2832.620000 2053.290000 2833.100000 ;
+ RECT 2052.290000 2838.060000 2053.290000 2838.540000 ;
+ RECT 2052.290000 2843.500000 2053.290000 2843.980000 ;
+ RECT 2052.290000 2799.980000 2053.290000 2800.460000 ;
+ RECT 2052.290000 2805.420000 2053.290000 2805.900000 ;
+ RECT 2052.290000 2810.860000 2053.290000 2811.340000 ;
+ RECT 2052.290000 2816.300000 2053.290000 2816.780000 ;
+ RECT 2052.290000 2821.740000 2053.290000 2822.220000 ;
+ RECT 2055.955000 2832.620000 2057.220000 2833.100000 ;
+ RECT 2055.955000 2827.180000 2057.220000 2827.660000 ;
+ RECT 2055.955000 2838.060000 2057.220000 2838.540000 ;
+ RECT 2055.955000 2843.500000 2057.220000 2843.980000 ;
+ RECT 2055.955000 2821.740000 2057.220000 2822.220000 ;
+ RECT 2055.955000 2816.300000 2057.220000 2816.780000 ;
+ RECT 2055.955000 2810.860000 2057.220000 2811.340000 ;
+ RECT 2055.955000 2805.420000 2057.220000 2805.900000 ;
+ RECT 2055.955000 2799.980000 2057.220000 2800.460000 ;
+ RECT 2101.120000 2778.220000 2102.220000 2778.700000 ;
+ RECT 2101.120000 2783.660000 2102.220000 2784.140000 ;
+ RECT 2101.120000 2789.100000 2102.220000 2789.580000 ;
+ RECT 2101.120000 2794.540000 2102.220000 2795.020000 ;
+ RECT 2101.120000 2756.460000 2102.220000 2756.940000 ;
+ RECT 2101.120000 2761.900000 2102.220000 2762.380000 ;
+ RECT 2101.120000 2767.340000 2102.220000 2767.820000 ;
+ RECT 2101.120000 2772.780000 2102.220000 2773.260000 ;
+ RECT 2052.290000 2778.220000 2053.290000 2778.700000 ;
+ RECT 2052.290000 2783.660000 2053.290000 2784.140000 ;
+ RECT 2052.290000 2789.100000 2053.290000 2789.580000 ;
+ RECT 2052.290000 2794.540000 2053.290000 2795.020000 ;
+ RECT 2052.290000 2756.460000 2053.290000 2756.940000 ;
+ RECT 2052.290000 2761.900000 2053.290000 2762.380000 ;
+ RECT 2052.290000 2767.340000 2053.290000 2767.820000 ;
+ RECT 2052.290000 2772.780000 2053.290000 2773.260000 ;
+ RECT 2055.955000 2789.100000 2057.220000 2789.580000 ;
+ RECT 2055.955000 2783.660000 2057.220000 2784.140000 ;
+ RECT 2055.955000 2778.220000 2057.220000 2778.700000 ;
+ RECT 2055.955000 2794.540000 2057.220000 2795.020000 ;
+ RECT 2055.955000 2772.780000 2057.220000 2773.260000 ;
+ RECT 2055.955000 2767.340000 2057.220000 2767.820000 ;
+ RECT 2055.955000 2761.900000 2057.220000 2762.380000 ;
+ RECT 2055.955000 2756.460000 2057.220000 2756.940000 ;
+ RECT 2146.120000 2848.940000 2147.220000 2849.420000 ;
+ RECT 2101.120000 2848.940000 2102.220000 2849.420000 ;
+ RECT 2052.290000 2848.940000 2053.290000 2849.420000 ;
+ RECT 2055.955000 2848.940000 2057.220000 2849.420000 ;
+ RECT 2158.770000 2848.940000 2159.770000 2849.420000 ;
+ RECT 2051.060000 2945.700000 2161.000000 2946.700000 ;
+ RECT 2051.060000 2750.130000 2161.000000 2751.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 2748.880000 2053.290000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 2948.140000 2053.290000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 2748.880000 2159.770000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 2948.140000 2159.770000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2750.130000 2052.060000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2750.130000 2161.000000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2945.700000 2052.060000 2946.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2945.700000 2161.000000 2946.700000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 2735.720000 2057.220000 2736.200000 ;
+ RECT 2055.955000 2730.280000 2057.220000 2730.760000 ;
+ RECT 2055.955000 2724.840000 2057.220000 2725.320000 ;
+ RECT 2055.955000 2741.160000 2057.220000 2741.640000 ;
+ RECT 2055.955000 2719.400000 2057.220000 2719.880000 ;
+ RECT 2055.955000 2713.960000 2057.220000 2714.440000 ;
+ RECT 2055.955000 2708.520000 2057.220000 2709.000000 ;
+ RECT 2055.955000 2703.080000 2057.220000 2703.560000 ;
+ RECT 2055.955000 2686.760000 2057.220000 2687.240000 ;
+ RECT 2055.955000 2681.320000 2057.220000 2681.800000 ;
+ RECT 2055.955000 2675.880000 2057.220000 2676.360000 ;
+ RECT 2055.955000 2692.200000 2057.220000 2692.680000 ;
+ RECT 2055.955000 2697.640000 2057.220000 2698.120000 ;
+ RECT 2055.955000 2670.440000 2057.220000 2670.920000 ;
+ RECT 2055.955000 2665.000000 2057.220000 2665.480000 ;
+ RECT 2055.955000 2659.560000 2057.220000 2660.040000 ;
+ RECT 2055.955000 2654.120000 2057.220000 2654.600000 ;
+ RECT 2055.955000 2632.360000 2057.220000 2632.840000 ;
+ RECT 2055.955000 2626.920000 2057.220000 2627.400000 ;
+ RECT 2055.955000 2637.800000 2057.220000 2638.280000 ;
+ RECT 2055.955000 2643.240000 2057.220000 2643.720000 ;
+ RECT 2055.955000 2621.480000 2057.220000 2621.960000 ;
+ RECT 2055.955000 2616.040000 2057.220000 2616.520000 ;
+ RECT 2055.955000 2610.600000 2057.220000 2611.080000 ;
+ RECT 2055.955000 2605.160000 2057.220000 2605.640000 ;
+ RECT 2055.955000 2599.720000 2057.220000 2600.200000 ;
+ RECT 2055.955000 2588.840000 2057.220000 2589.320000 ;
+ RECT 2055.955000 2583.400000 2057.220000 2583.880000 ;
+ RECT 2055.955000 2577.960000 2057.220000 2578.440000 ;
+ RECT 2055.955000 2594.280000 2057.220000 2594.760000 ;
+ RECT 2055.955000 2572.520000 2057.220000 2573.000000 ;
+ RECT 2055.955000 2567.080000 2057.220000 2567.560000 ;
+ RECT 2055.955000 2561.640000 2057.220000 2562.120000 ;
+ RECT 2055.955000 2556.200000 2057.220000 2556.680000 ;
+ RECT 2055.955000 2648.680000 2057.220000 2649.160000 ;
+ RECT 2052.290000 2548.620000 2053.290000 2748.880000 ;
+ RECT 2158.770000 2548.620000 2159.770000 2748.880000 ;
+ RECT 2056.120000 2549.870000 2057.220000 2746.440000 ;
+ RECT 2101.120000 2549.870000 2102.220000 2746.440000 ;
+ RECT 2146.120000 2549.870000 2147.220000 2746.440000 ;
+ LAYER met3 ;
+ RECT 2158.770000 2724.840000 2159.770000 2725.320000 ;
+ RECT 2158.770000 2730.280000 2159.770000 2730.760000 ;
+ RECT 2158.770000 2735.720000 2159.770000 2736.200000 ;
+ RECT 2158.770000 2741.160000 2159.770000 2741.640000 ;
+ RECT 2158.770000 2708.520000 2159.770000 2709.000000 ;
+ RECT 2158.770000 2703.080000 2159.770000 2703.560000 ;
+ RECT 2158.770000 2713.960000 2159.770000 2714.440000 ;
+ RECT 2158.770000 2719.400000 2159.770000 2719.880000 ;
+ RECT 2146.120000 2724.840000 2147.220000 2725.320000 ;
+ RECT 2146.120000 2730.280000 2147.220000 2730.760000 ;
+ RECT 2146.120000 2735.720000 2147.220000 2736.200000 ;
+ RECT 2146.120000 2741.160000 2147.220000 2741.640000 ;
+ RECT 2146.120000 2708.520000 2147.220000 2709.000000 ;
+ RECT 2146.120000 2703.080000 2147.220000 2703.560000 ;
+ RECT 2146.120000 2713.960000 2147.220000 2714.440000 ;
+ RECT 2146.120000 2719.400000 2147.220000 2719.880000 ;
+ RECT 2158.770000 2675.880000 2159.770000 2676.360000 ;
+ RECT 2158.770000 2681.320000 2159.770000 2681.800000 ;
+ RECT 2158.770000 2686.760000 2159.770000 2687.240000 ;
+ RECT 2158.770000 2692.200000 2159.770000 2692.680000 ;
+ RECT 2158.770000 2697.640000 2159.770000 2698.120000 ;
+ RECT 2158.770000 2654.120000 2159.770000 2654.600000 ;
+ RECT 2158.770000 2659.560000 2159.770000 2660.040000 ;
+ RECT 2158.770000 2665.000000 2159.770000 2665.480000 ;
+ RECT 2158.770000 2670.440000 2159.770000 2670.920000 ;
+ RECT 2146.120000 2675.880000 2147.220000 2676.360000 ;
+ RECT 2146.120000 2681.320000 2147.220000 2681.800000 ;
+ RECT 2146.120000 2686.760000 2147.220000 2687.240000 ;
+ RECT 2146.120000 2692.200000 2147.220000 2692.680000 ;
+ RECT 2146.120000 2697.640000 2147.220000 2698.120000 ;
+ RECT 2146.120000 2659.560000 2147.220000 2660.040000 ;
+ RECT 2146.120000 2654.120000 2147.220000 2654.600000 ;
+ RECT 2146.120000 2665.000000 2147.220000 2665.480000 ;
+ RECT 2146.120000 2670.440000 2147.220000 2670.920000 ;
+ RECT 2101.120000 2730.280000 2102.220000 2730.760000 ;
+ RECT 2101.120000 2724.840000 2102.220000 2725.320000 ;
+ RECT 2101.120000 2735.720000 2102.220000 2736.200000 ;
+ RECT 2101.120000 2741.160000 2102.220000 2741.640000 ;
+ RECT 2101.120000 2703.080000 2102.220000 2703.560000 ;
+ RECT 2101.120000 2708.520000 2102.220000 2709.000000 ;
+ RECT 2101.120000 2713.960000 2102.220000 2714.440000 ;
+ RECT 2101.120000 2719.400000 2102.220000 2719.880000 ;
+ RECT 2052.290000 2724.840000 2053.290000 2725.320000 ;
+ RECT 2052.290000 2730.280000 2053.290000 2730.760000 ;
+ RECT 2052.290000 2735.720000 2053.290000 2736.200000 ;
+ RECT 2052.290000 2741.160000 2053.290000 2741.640000 ;
+ RECT 2052.290000 2708.520000 2053.290000 2709.000000 ;
+ RECT 2052.290000 2703.080000 2053.290000 2703.560000 ;
+ RECT 2052.290000 2713.960000 2053.290000 2714.440000 ;
+ RECT 2052.290000 2719.400000 2053.290000 2719.880000 ;
+ RECT 2055.955000 2735.720000 2057.220000 2736.200000 ;
+ RECT 2055.955000 2730.280000 2057.220000 2730.760000 ;
+ RECT 2055.955000 2724.840000 2057.220000 2725.320000 ;
+ RECT 2055.955000 2741.160000 2057.220000 2741.640000 ;
+ RECT 2055.955000 2719.400000 2057.220000 2719.880000 ;
+ RECT 2055.955000 2713.960000 2057.220000 2714.440000 ;
+ RECT 2055.955000 2708.520000 2057.220000 2709.000000 ;
+ RECT 2055.955000 2703.080000 2057.220000 2703.560000 ;
+ RECT 2101.120000 2675.880000 2102.220000 2676.360000 ;
+ RECT 2101.120000 2681.320000 2102.220000 2681.800000 ;
+ RECT 2101.120000 2686.760000 2102.220000 2687.240000 ;
+ RECT 2101.120000 2692.200000 2102.220000 2692.680000 ;
+ RECT 2101.120000 2697.640000 2102.220000 2698.120000 ;
+ RECT 2101.120000 2654.120000 2102.220000 2654.600000 ;
+ RECT 2101.120000 2659.560000 2102.220000 2660.040000 ;
+ RECT 2101.120000 2665.000000 2102.220000 2665.480000 ;
+ RECT 2101.120000 2670.440000 2102.220000 2670.920000 ;
+ RECT 2052.290000 2675.880000 2053.290000 2676.360000 ;
+ RECT 2052.290000 2681.320000 2053.290000 2681.800000 ;
+ RECT 2052.290000 2686.760000 2053.290000 2687.240000 ;
+ RECT 2052.290000 2692.200000 2053.290000 2692.680000 ;
+ RECT 2052.290000 2697.640000 2053.290000 2698.120000 ;
+ RECT 2052.290000 2654.120000 2053.290000 2654.600000 ;
+ RECT 2052.290000 2659.560000 2053.290000 2660.040000 ;
+ RECT 2052.290000 2665.000000 2053.290000 2665.480000 ;
+ RECT 2052.290000 2670.440000 2053.290000 2670.920000 ;
+ RECT 2055.955000 2686.760000 2057.220000 2687.240000 ;
+ RECT 2055.955000 2681.320000 2057.220000 2681.800000 ;
+ RECT 2055.955000 2675.880000 2057.220000 2676.360000 ;
+ RECT 2055.955000 2692.200000 2057.220000 2692.680000 ;
+ RECT 2055.955000 2697.640000 2057.220000 2698.120000 ;
+ RECT 2055.955000 2670.440000 2057.220000 2670.920000 ;
+ RECT 2055.955000 2665.000000 2057.220000 2665.480000 ;
+ RECT 2055.955000 2659.560000 2057.220000 2660.040000 ;
+ RECT 2055.955000 2654.120000 2057.220000 2654.600000 ;
+ RECT 2158.770000 2626.920000 2159.770000 2627.400000 ;
+ RECT 2158.770000 2632.360000 2159.770000 2632.840000 ;
+ RECT 2158.770000 2637.800000 2159.770000 2638.280000 ;
+ RECT 2158.770000 2643.240000 2159.770000 2643.720000 ;
+ RECT 2158.770000 2599.720000 2159.770000 2600.200000 ;
+ RECT 2158.770000 2605.160000 2159.770000 2605.640000 ;
+ RECT 2158.770000 2610.600000 2159.770000 2611.080000 ;
+ RECT 2158.770000 2616.040000 2159.770000 2616.520000 ;
+ RECT 2158.770000 2621.480000 2159.770000 2621.960000 ;
+ RECT 2146.120000 2626.920000 2147.220000 2627.400000 ;
+ RECT 2146.120000 2632.360000 2147.220000 2632.840000 ;
+ RECT 2146.120000 2637.800000 2147.220000 2638.280000 ;
+ RECT 2146.120000 2643.240000 2147.220000 2643.720000 ;
+ RECT 2146.120000 2605.160000 2147.220000 2605.640000 ;
+ RECT 2146.120000 2599.720000 2147.220000 2600.200000 ;
+ RECT 2146.120000 2610.600000 2147.220000 2611.080000 ;
+ RECT 2146.120000 2616.040000 2147.220000 2616.520000 ;
+ RECT 2146.120000 2621.480000 2147.220000 2621.960000 ;
+ RECT 2158.770000 2577.960000 2159.770000 2578.440000 ;
+ RECT 2158.770000 2583.400000 2159.770000 2583.880000 ;
+ RECT 2158.770000 2588.840000 2159.770000 2589.320000 ;
+ RECT 2158.770000 2594.280000 2159.770000 2594.760000 ;
+ RECT 2158.770000 2556.200000 2159.770000 2556.680000 ;
+ RECT 2158.770000 2561.640000 2159.770000 2562.120000 ;
+ RECT 2158.770000 2567.080000 2159.770000 2567.560000 ;
+ RECT 2158.770000 2572.520000 2159.770000 2573.000000 ;
+ RECT 2146.120000 2577.960000 2147.220000 2578.440000 ;
+ RECT 2146.120000 2583.400000 2147.220000 2583.880000 ;
+ RECT 2146.120000 2588.840000 2147.220000 2589.320000 ;
+ RECT 2146.120000 2594.280000 2147.220000 2594.760000 ;
+ RECT 2146.120000 2556.200000 2147.220000 2556.680000 ;
+ RECT 2146.120000 2561.640000 2147.220000 2562.120000 ;
+ RECT 2146.120000 2567.080000 2147.220000 2567.560000 ;
+ RECT 2146.120000 2572.520000 2147.220000 2573.000000 ;
+ RECT 2101.120000 2626.920000 2102.220000 2627.400000 ;
+ RECT 2101.120000 2632.360000 2102.220000 2632.840000 ;
+ RECT 2101.120000 2637.800000 2102.220000 2638.280000 ;
+ RECT 2101.120000 2643.240000 2102.220000 2643.720000 ;
+ RECT 2101.120000 2599.720000 2102.220000 2600.200000 ;
+ RECT 2101.120000 2605.160000 2102.220000 2605.640000 ;
+ RECT 2101.120000 2610.600000 2102.220000 2611.080000 ;
+ RECT 2101.120000 2616.040000 2102.220000 2616.520000 ;
+ RECT 2101.120000 2621.480000 2102.220000 2621.960000 ;
+ RECT 2052.290000 2626.920000 2053.290000 2627.400000 ;
+ RECT 2052.290000 2632.360000 2053.290000 2632.840000 ;
+ RECT 2052.290000 2637.800000 2053.290000 2638.280000 ;
+ RECT 2052.290000 2643.240000 2053.290000 2643.720000 ;
+ RECT 2052.290000 2599.720000 2053.290000 2600.200000 ;
+ RECT 2052.290000 2605.160000 2053.290000 2605.640000 ;
+ RECT 2052.290000 2610.600000 2053.290000 2611.080000 ;
+ RECT 2052.290000 2616.040000 2053.290000 2616.520000 ;
+ RECT 2052.290000 2621.480000 2053.290000 2621.960000 ;
+ RECT 2055.955000 2632.360000 2057.220000 2632.840000 ;
+ RECT 2055.955000 2626.920000 2057.220000 2627.400000 ;
+ RECT 2055.955000 2637.800000 2057.220000 2638.280000 ;
+ RECT 2055.955000 2643.240000 2057.220000 2643.720000 ;
+ RECT 2055.955000 2621.480000 2057.220000 2621.960000 ;
+ RECT 2055.955000 2616.040000 2057.220000 2616.520000 ;
+ RECT 2055.955000 2610.600000 2057.220000 2611.080000 ;
+ RECT 2055.955000 2605.160000 2057.220000 2605.640000 ;
+ RECT 2055.955000 2599.720000 2057.220000 2600.200000 ;
+ RECT 2101.120000 2577.960000 2102.220000 2578.440000 ;
+ RECT 2101.120000 2583.400000 2102.220000 2583.880000 ;
+ RECT 2101.120000 2588.840000 2102.220000 2589.320000 ;
+ RECT 2101.120000 2594.280000 2102.220000 2594.760000 ;
+ RECT 2101.120000 2556.200000 2102.220000 2556.680000 ;
+ RECT 2101.120000 2561.640000 2102.220000 2562.120000 ;
+ RECT 2101.120000 2567.080000 2102.220000 2567.560000 ;
+ RECT 2101.120000 2572.520000 2102.220000 2573.000000 ;
+ RECT 2052.290000 2577.960000 2053.290000 2578.440000 ;
+ RECT 2052.290000 2583.400000 2053.290000 2583.880000 ;
+ RECT 2052.290000 2588.840000 2053.290000 2589.320000 ;
+ RECT 2052.290000 2594.280000 2053.290000 2594.760000 ;
+ RECT 2052.290000 2556.200000 2053.290000 2556.680000 ;
+ RECT 2052.290000 2561.640000 2053.290000 2562.120000 ;
+ RECT 2052.290000 2567.080000 2053.290000 2567.560000 ;
+ RECT 2052.290000 2572.520000 2053.290000 2573.000000 ;
+ RECT 2055.955000 2588.840000 2057.220000 2589.320000 ;
+ RECT 2055.955000 2583.400000 2057.220000 2583.880000 ;
+ RECT 2055.955000 2577.960000 2057.220000 2578.440000 ;
+ RECT 2055.955000 2594.280000 2057.220000 2594.760000 ;
+ RECT 2055.955000 2572.520000 2057.220000 2573.000000 ;
+ RECT 2055.955000 2567.080000 2057.220000 2567.560000 ;
+ RECT 2055.955000 2561.640000 2057.220000 2562.120000 ;
+ RECT 2055.955000 2556.200000 2057.220000 2556.680000 ;
+ RECT 2146.120000 2648.680000 2147.220000 2649.160000 ;
+ RECT 2101.120000 2648.680000 2102.220000 2649.160000 ;
+ RECT 2052.290000 2648.680000 2053.290000 2649.160000 ;
+ RECT 2055.955000 2648.680000 2057.220000 2649.160000 ;
+ RECT 2158.770000 2648.680000 2159.770000 2649.160000 ;
+ RECT 2051.060000 2745.440000 2161.000000 2746.440000 ;
+ RECT 2051.060000 2549.870000 2161.000000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 2548.620000 2053.290000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 2747.880000 2053.290000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 2548.620000 2159.770000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 2747.880000 2159.770000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2549.870000 2052.060000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2549.870000 2161.000000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2745.440000 2052.060000 2746.440000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2745.440000 2161.000000 2746.440000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 2535.460000 2057.220000 2535.940000 ;
+ RECT 2055.955000 2530.020000 2057.220000 2530.500000 ;
+ RECT 2055.955000 2524.580000 2057.220000 2525.060000 ;
+ RECT 2055.955000 2540.900000 2057.220000 2541.380000 ;
+ RECT 2055.955000 2519.140000 2057.220000 2519.620000 ;
+ RECT 2055.955000 2513.700000 2057.220000 2514.180000 ;
+ RECT 2055.955000 2508.260000 2057.220000 2508.740000 ;
+ RECT 2055.955000 2502.820000 2057.220000 2503.300000 ;
+ RECT 2055.955000 2486.500000 2057.220000 2486.980000 ;
+ RECT 2055.955000 2481.060000 2057.220000 2481.540000 ;
+ RECT 2055.955000 2475.620000 2057.220000 2476.100000 ;
+ RECT 2055.955000 2491.940000 2057.220000 2492.420000 ;
+ RECT 2055.955000 2497.380000 2057.220000 2497.860000 ;
+ RECT 2055.955000 2470.180000 2057.220000 2470.660000 ;
+ RECT 2055.955000 2464.740000 2057.220000 2465.220000 ;
+ RECT 2055.955000 2459.300000 2057.220000 2459.780000 ;
+ RECT 2055.955000 2453.860000 2057.220000 2454.340000 ;
+ RECT 2055.955000 2432.100000 2057.220000 2432.580000 ;
+ RECT 2055.955000 2426.660000 2057.220000 2427.140000 ;
+ RECT 2055.955000 2437.540000 2057.220000 2438.020000 ;
+ RECT 2055.955000 2442.980000 2057.220000 2443.460000 ;
+ RECT 2055.955000 2421.220000 2057.220000 2421.700000 ;
+ RECT 2055.955000 2415.780000 2057.220000 2416.260000 ;
+ RECT 2055.955000 2410.340000 2057.220000 2410.820000 ;
+ RECT 2055.955000 2404.900000 2057.220000 2405.380000 ;
+ RECT 2055.955000 2399.460000 2057.220000 2399.940000 ;
+ RECT 2055.955000 2388.580000 2057.220000 2389.060000 ;
+ RECT 2055.955000 2383.140000 2057.220000 2383.620000 ;
+ RECT 2055.955000 2377.700000 2057.220000 2378.180000 ;
+ RECT 2055.955000 2394.020000 2057.220000 2394.500000 ;
+ RECT 2055.955000 2372.260000 2057.220000 2372.740000 ;
+ RECT 2055.955000 2366.820000 2057.220000 2367.300000 ;
+ RECT 2055.955000 2361.380000 2057.220000 2361.860000 ;
+ RECT 2055.955000 2355.940000 2057.220000 2356.420000 ;
+ RECT 2055.955000 2448.420000 2057.220000 2448.900000 ;
+ RECT 2052.290000 2348.360000 2053.290000 2548.620000 ;
+ RECT 2158.770000 2348.360000 2159.770000 2548.620000 ;
+ RECT 2056.120000 2349.610000 2057.220000 2546.180000 ;
+ RECT 2101.120000 2349.610000 2102.220000 2546.180000 ;
+ RECT 2146.120000 2349.610000 2147.220000 2546.180000 ;
+ LAYER met3 ;
+ RECT 2158.770000 2524.580000 2159.770000 2525.060000 ;
+ RECT 2158.770000 2530.020000 2159.770000 2530.500000 ;
+ RECT 2158.770000 2535.460000 2159.770000 2535.940000 ;
+ RECT 2158.770000 2540.900000 2159.770000 2541.380000 ;
+ RECT 2158.770000 2508.260000 2159.770000 2508.740000 ;
+ RECT 2158.770000 2502.820000 2159.770000 2503.300000 ;
+ RECT 2158.770000 2513.700000 2159.770000 2514.180000 ;
+ RECT 2158.770000 2519.140000 2159.770000 2519.620000 ;
+ RECT 2146.120000 2524.580000 2147.220000 2525.060000 ;
+ RECT 2146.120000 2530.020000 2147.220000 2530.500000 ;
+ RECT 2146.120000 2535.460000 2147.220000 2535.940000 ;
+ RECT 2146.120000 2540.900000 2147.220000 2541.380000 ;
+ RECT 2146.120000 2508.260000 2147.220000 2508.740000 ;
+ RECT 2146.120000 2502.820000 2147.220000 2503.300000 ;
+ RECT 2146.120000 2513.700000 2147.220000 2514.180000 ;
+ RECT 2146.120000 2519.140000 2147.220000 2519.620000 ;
+ RECT 2158.770000 2475.620000 2159.770000 2476.100000 ;
+ RECT 2158.770000 2481.060000 2159.770000 2481.540000 ;
+ RECT 2158.770000 2486.500000 2159.770000 2486.980000 ;
+ RECT 2158.770000 2491.940000 2159.770000 2492.420000 ;
+ RECT 2158.770000 2497.380000 2159.770000 2497.860000 ;
+ RECT 2158.770000 2453.860000 2159.770000 2454.340000 ;
+ RECT 2158.770000 2459.300000 2159.770000 2459.780000 ;
+ RECT 2158.770000 2464.740000 2159.770000 2465.220000 ;
+ RECT 2158.770000 2470.180000 2159.770000 2470.660000 ;
+ RECT 2146.120000 2475.620000 2147.220000 2476.100000 ;
+ RECT 2146.120000 2481.060000 2147.220000 2481.540000 ;
+ RECT 2146.120000 2486.500000 2147.220000 2486.980000 ;
+ RECT 2146.120000 2491.940000 2147.220000 2492.420000 ;
+ RECT 2146.120000 2497.380000 2147.220000 2497.860000 ;
+ RECT 2146.120000 2459.300000 2147.220000 2459.780000 ;
+ RECT 2146.120000 2453.860000 2147.220000 2454.340000 ;
+ RECT 2146.120000 2464.740000 2147.220000 2465.220000 ;
+ RECT 2146.120000 2470.180000 2147.220000 2470.660000 ;
+ RECT 2101.120000 2530.020000 2102.220000 2530.500000 ;
+ RECT 2101.120000 2524.580000 2102.220000 2525.060000 ;
+ RECT 2101.120000 2535.460000 2102.220000 2535.940000 ;
+ RECT 2101.120000 2540.900000 2102.220000 2541.380000 ;
+ RECT 2101.120000 2502.820000 2102.220000 2503.300000 ;
+ RECT 2101.120000 2508.260000 2102.220000 2508.740000 ;
+ RECT 2101.120000 2513.700000 2102.220000 2514.180000 ;
+ RECT 2101.120000 2519.140000 2102.220000 2519.620000 ;
+ RECT 2052.290000 2524.580000 2053.290000 2525.060000 ;
+ RECT 2052.290000 2530.020000 2053.290000 2530.500000 ;
+ RECT 2052.290000 2535.460000 2053.290000 2535.940000 ;
+ RECT 2052.290000 2540.900000 2053.290000 2541.380000 ;
+ RECT 2052.290000 2508.260000 2053.290000 2508.740000 ;
+ RECT 2052.290000 2502.820000 2053.290000 2503.300000 ;
+ RECT 2052.290000 2513.700000 2053.290000 2514.180000 ;
+ RECT 2052.290000 2519.140000 2053.290000 2519.620000 ;
+ RECT 2055.955000 2535.460000 2057.220000 2535.940000 ;
+ RECT 2055.955000 2530.020000 2057.220000 2530.500000 ;
+ RECT 2055.955000 2524.580000 2057.220000 2525.060000 ;
+ RECT 2055.955000 2540.900000 2057.220000 2541.380000 ;
+ RECT 2055.955000 2519.140000 2057.220000 2519.620000 ;
+ RECT 2055.955000 2513.700000 2057.220000 2514.180000 ;
+ RECT 2055.955000 2508.260000 2057.220000 2508.740000 ;
+ RECT 2055.955000 2502.820000 2057.220000 2503.300000 ;
+ RECT 2101.120000 2475.620000 2102.220000 2476.100000 ;
+ RECT 2101.120000 2481.060000 2102.220000 2481.540000 ;
+ RECT 2101.120000 2486.500000 2102.220000 2486.980000 ;
+ RECT 2101.120000 2491.940000 2102.220000 2492.420000 ;
+ RECT 2101.120000 2497.380000 2102.220000 2497.860000 ;
+ RECT 2101.120000 2453.860000 2102.220000 2454.340000 ;
+ RECT 2101.120000 2459.300000 2102.220000 2459.780000 ;
+ RECT 2101.120000 2464.740000 2102.220000 2465.220000 ;
+ RECT 2101.120000 2470.180000 2102.220000 2470.660000 ;
+ RECT 2052.290000 2475.620000 2053.290000 2476.100000 ;
+ RECT 2052.290000 2481.060000 2053.290000 2481.540000 ;
+ RECT 2052.290000 2486.500000 2053.290000 2486.980000 ;
+ RECT 2052.290000 2491.940000 2053.290000 2492.420000 ;
+ RECT 2052.290000 2497.380000 2053.290000 2497.860000 ;
+ RECT 2052.290000 2453.860000 2053.290000 2454.340000 ;
+ RECT 2052.290000 2459.300000 2053.290000 2459.780000 ;
+ RECT 2052.290000 2464.740000 2053.290000 2465.220000 ;
+ RECT 2052.290000 2470.180000 2053.290000 2470.660000 ;
+ RECT 2055.955000 2486.500000 2057.220000 2486.980000 ;
+ RECT 2055.955000 2481.060000 2057.220000 2481.540000 ;
+ RECT 2055.955000 2475.620000 2057.220000 2476.100000 ;
+ RECT 2055.955000 2491.940000 2057.220000 2492.420000 ;
+ RECT 2055.955000 2497.380000 2057.220000 2497.860000 ;
+ RECT 2055.955000 2470.180000 2057.220000 2470.660000 ;
+ RECT 2055.955000 2464.740000 2057.220000 2465.220000 ;
+ RECT 2055.955000 2459.300000 2057.220000 2459.780000 ;
+ RECT 2055.955000 2453.860000 2057.220000 2454.340000 ;
+ RECT 2158.770000 2426.660000 2159.770000 2427.140000 ;
+ RECT 2158.770000 2432.100000 2159.770000 2432.580000 ;
+ RECT 2158.770000 2437.540000 2159.770000 2438.020000 ;
+ RECT 2158.770000 2442.980000 2159.770000 2443.460000 ;
+ RECT 2158.770000 2399.460000 2159.770000 2399.940000 ;
+ RECT 2158.770000 2404.900000 2159.770000 2405.380000 ;
+ RECT 2158.770000 2410.340000 2159.770000 2410.820000 ;
+ RECT 2158.770000 2415.780000 2159.770000 2416.260000 ;
+ RECT 2158.770000 2421.220000 2159.770000 2421.700000 ;
+ RECT 2146.120000 2426.660000 2147.220000 2427.140000 ;
+ RECT 2146.120000 2432.100000 2147.220000 2432.580000 ;
+ RECT 2146.120000 2437.540000 2147.220000 2438.020000 ;
+ RECT 2146.120000 2442.980000 2147.220000 2443.460000 ;
+ RECT 2146.120000 2404.900000 2147.220000 2405.380000 ;
+ RECT 2146.120000 2399.460000 2147.220000 2399.940000 ;
+ RECT 2146.120000 2410.340000 2147.220000 2410.820000 ;
+ RECT 2146.120000 2415.780000 2147.220000 2416.260000 ;
+ RECT 2146.120000 2421.220000 2147.220000 2421.700000 ;
+ RECT 2158.770000 2377.700000 2159.770000 2378.180000 ;
+ RECT 2158.770000 2383.140000 2159.770000 2383.620000 ;
+ RECT 2158.770000 2388.580000 2159.770000 2389.060000 ;
+ RECT 2158.770000 2394.020000 2159.770000 2394.500000 ;
+ RECT 2158.770000 2355.940000 2159.770000 2356.420000 ;
+ RECT 2158.770000 2361.380000 2159.770000 2361.860000 ;
+ RECT 2158.770000 2366.820000 2159.770000 2367.300000 ;
+ RECT 2158.770000 2372.260000 2159.770000 2372.740000 ;
+ RECT 2146.120000 2377.700000 2147.220000 2378.180000 ;
+ RECT 2146.120000 2383.140000 2147.220000 2383.620000 ;
+ RECT 2146.120000 2388.580000 2147.220000 2389.060000 ;
+ RECT 2146.120000 2394.020000 2147.220000 2394.500000 ;
+ RECT 2146.120000 2355.940000 2147.220000 2356.420000 ;
+ RECT 2146.120000 2361.380000 2147.220000 2361.860000 ;
+ RECT 2146.120000 2366.820000 2147.220000 2367.300000 ;
+ RECT 2146.120000 2372.260000 2147.220000 2372.740000 ;
+ RECT 2101.120000 2426.660000 2102.220000 2427.140000 ;
+ RECT 2101.120000 2432.100000 2102.220000 2432.580000 ;
+ RECT 2101.120000 2437.540000 2102.220000 2438.020000 ;
+ RECT 2101.120000 2442.980000 2102.220000 2443.460000 ;
+ RECT 2101.120000 2399.460000 2102.220000 2399.940000 ;
+ RECT 2101.120000 2404.900000 2102.220000 2405.380000 ;
+ RECT 2101.120000 2410.340000 2102.220000 2410.820000 ;
+ RECT 2101.120000 2415.780000 2102.220000 2416.260000 ;
+ RECT 2101.120000 2421.220000 2102.220000 2421.700000 ;
+ RECT 2052.290000 2426.660000 2053.290000 2427.140000 ;
+ RECT 2052.290000 2432.100000 2053.290000 2432.580000 ;
+ RECT 2052.290000 2437.540000 2053.290000 2438.020000 ;
+ RECT 2052.290000 2442.980000 2053.290000 2443.460000 ;
+ RECT 2052.290000 2399.460000 2053.290000 2399.940000 ;
+ RECT 2052.290000 2404.900000 2053.290000 2405.380000 ;
+ RECT 2052.290000 2410.340000 2053.290000 2410.820000 ;
+ RECT 2052.290000 2415.780000 2053.290000 2416.260000 ;
+ RECT 2052.290000 2421.220000 2053.290000 2421.700000 ;
+ RECT 2055.955000 2432.100000 2057.220000 2432.580000 ;
+ RECT 2055.955000 2426.660000 2057.220000 2427.140000 ;
+ RECT 2055.955000 2437.540000 2057.220000 2438.020000 ;
+ RECT 2055.955000 2442.980000 2057.220000 2443.460000 ;
+ RECT 2055.955000 2421.220000 2057.220000 2421.700000 ;
+ RECT 2055.955000 2415.780000 2057.220000 2416.260000 ;
+ RECT 2055.955000 2410.340000 2057.220000 2410.820000 ;
+ RECT 2055.955000 2404.900000 2057.220000 2405.380000 ;
+ RECT 2055.955000 2399.460000 2057.220000 2399.940000 ;
+ RECT 2101.120000 2377.700000 2102.220000 2378.180000 ;
+ RECT 2101.120000 2383.140000 2102.220000 2383.620000 ;
+ RECT 2101.120000 2388.580000 2102.220000 2389.060000 ;
+ RECT 2101.120000 2394.020000 2102.220000 2394.500000 ;
+ RECT 2101.120000 2355.940000 2102.220000 2356.420000 ;
+ RECT 2101.120000 2361.380000 2102.220000 2361.860000 ;
+ RECT 2101.120000 2366.820000 2102.220000 2367.300000 ;
+ RECT 2101.120000 2372.260000 2102.220000 2372.740000 ;
+ RECT 2052.290000 2377.700000 2053.290000 2378.180000 ;
+ RECT 2052.290000 2383.140000 2053.290000 2383.620000 ;
+ RECT 2052.290000 2388.580000 2053.290000 2389.060000 ;
+ RECT 2052.290000 2394.020000 2053.290000 2394.500000 ;
+ RECT 2052.290000 2355.940000 2053.290000 2356.420000 ;
+ RECT 2052.290000 2361.380000 2053.290000 2361.860000 ;
+ RECT 2052.290000 2366.820000 2053.290000 2367.300000 ;
+ RECT 2052.290000 2372.260000 2053.290000 2372.740000 ;
+ RECT 2055.955000 2388.580000 2057.220000 2389.060000 ;
+ RECT 2055.955000 2383.140000 2057.220000 2383.620000 ;
+ RECT 2055.955000 2377.700000 2057.220000 2378.180000 ;
+ RECT 2055.955000 2394.020000 2057.220000 2394.500000 ;
+ RECT 2055.955000 2372.260000 2057.220000 2372.740000 ;
+ RECT 2055.955000 2366.820000 2057.220000 2367.300000 ;
+ RECT 2055.955000 2361.380000 2057.220000 2361.860000 ;
+ RECT 2055.955000 2355.940000 2057.220000 2356.420000 ;
+ RECT 2146.120000 2448.420000 2147.220000 2448.900000 ;
+ RECT 2101.120000 2448.420000 2102.220000 2448.900000 ;
+ RECT 2052.290000 2448.420000 2053.290000 2448.900000 ;
+ RECT 2055.955000 2448.420000 2057.220000 2448.900000 ;
+ RECT 2158.770000 2448.420000 2159.770000 2448.900000 ;
+ RECT 2051.060000 2545.180000 2161.000000 2546.180000 ;
+ RECT 2051.060000 2349.610000 2161.000000 2350.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 2348.360000 2053.290000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 2547.620000 2053.290000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 2348.360000 2159.770000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 2547.620000 2159.770000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2349.610000 2052.060000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2349.610000 2161.000000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2545.180000 2052.060000 2546.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2545.180000 2161.000000 2546.180000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 2335.200000 2057.220000 2335.680000 ;
+ RECT 2055.955000 2329.760000 2057.220000 2330.240000 ;
+ RECT 2055.955000 2324.320000 2057.220000 2324.800000 ;
+ RECT 2055.955000 2340.640000 2057.220000 2341.120000 ;
+ RECT 2055.955000 2318.880000 2057.220000 2319.360000 ;
+ RECT 2055.955000 2313.440000 2057.220000 2313.920000 ;
+ RECT 2055.955000 2308.000000 2057.220000 2308.480000 ;
+ RECT 2055.955000 2302.560000 2057.220000 2303.040000 ;
+ RECT 2055.955000 2286.240000 2057.220000 2286.720000 ;
+ RECT 2055.955000 2280.800000 2057.220000 2281.280000 ;
+ RECT 2055.955000 2275.360000 2057.220000 2275.840000 ;
+ RECT 2055.955000 2291.680000 2057.220000 2292.160000 ;
+ RECT 2055.955000 2297.120000 2057.220000 2297.600000 ;
+ RECT 2055.955000 2269.920000 2057.220000 2270.400000 ;
+ RECT 2055.955000 2264.480000 2057.220000 2264.960000 ;
+ RECT 2055.955000 2259.040000 2057.220000 2259.520000 ;
+ RECT 2055.955000 2253.600000 2057.220000 2254.080000 ;
+ RECT 2055.955000 2231.840000 2057.220000 2232.320000 ;
+ RECT 2055.955000 2226.400000 2057.220000 2226.880000 ;
+ RECT 2055.955000 2237.280000 2057.220000 2237.760000 ;
+ RECT 2055.955000 2242.720000 2057.220000 2243.200000 ;
+ RECT 2055.955000 2220.960000 2057.220000 2221.440000 ;
+ RECT 2055.955000 2215.520000 2057.220000 2216.000000 ;
+ RECT 2055.955000 2210.080000 2057.220000 2210.560000 ;
+ RECT 2055.955000 2204.640000 2057.220000 2205.120000 ;
+ RECT 2055.955000 2199.200000 2057.220000 2199.680000 ;
+ RECT 2055.955000 2188.320000 2057.220000 2188.800000 ;
+ RECT 2055.955000 2182.880000 2057.220000 2183.360000 ;
+ RECT 2055.955000 2177.440000 2057.220000 2177.920000 ;
+ RECT 2055.955000 2193.760000 2057.220000 2194.240000 ;
+ RECT 2055.955000 2172.000000 2057.220000 2172.480000 ;
+ RECT 2055.955000 2166.560000 2057.220000 2167.040000 ;
+ RECT 2055.955000 2161.120000 2057.220000 2161.600000 ;
+ RECT 2055.955000 2155.680000 2057.220000 2156.160000 ;
+ RECT 2055.955000 2248.160000 2057.220000 2248.640000 ;
+ RECT 2052.290000 2148.100000 2053.290000 2348.360000 ;
+ RECT 2158.770000 2148.100000 2159.770000 2348.360000 ;
+ RECT 2056.120000 2149.350000 2057.220000 2345.920000 ;
+ RECT 2101.120000 2149.350000 2102.220000 2345.920000 ;
+ RECT 2146.120000 2149.350000 2147.220000 2345.920000 ;
+ LAYER met3 ;
+ RECT 2158.770000 2324.320000 2159.770000 2324.800000 ;
+ RECT 2158.770000 2329.760000 2159.770000 2330.240000 ;
+ RECT 2158.770000 2335.200000 2159.770000 2335.680000 ;
+ RECT 2158.770000 2340.640000 2159.770000 2341.120000 ;
+ RECT 2158.770000 2308.000000 2159.770000 2308.480000 ;
+ RECT 2158.770000 2302.560000 2159.770000 2303.040000 ;
+ RECT 2158.770000 2313.440000 2159.770000 2313.920000 ;
+ RECT 2158.770000 2318.880000 2159.770000 2319.360000 ;
+ RECT 2146.120000 2324.320000 2147.220000 2324.800000 ;
+ RECT 2146.120000 2329.760000 2147.220000 2330.240000 ;
+ RECT 2146.120000 2335.200000 2147.220000 2335.680000 ;
+ RECT 2146.120000 2340.640000 2147.220000 2341.120000 ;
+ RECT 2146.120000 2308.000000 2147.220000 2308.480000 ;
+ RECT 2146.120000 2302.560000 2147.220000 2303.040000 ;
+ RECT 2146.120000 2313.440000 2147.220000 2313.920000 ;
+ RECT 2146.120000 2318.880000 2147.220000 2319.360000 ;
+ RECT 2158.770000 2275.360000 2159.770000 2275.840000 ;
+ RECT 2158.770000 2280.800000 2159.770000 2281.280000 ;
+ RECT 2158.770000 2286.240000 2159.770000 2286.720000 ;
+ RECT 2158.770000 2291.680000 2159.770000 2292.160000 ;
+ RECT 2158.770000 2297.120000 2159.770000 2297.600000 ;
+ RECT 2158.770000 2253.600000 2159.770000 2254.080000 ;
+ RECT 2158.770000 2259.040000 2159.770000 2259.520000 ;
+ RECT 2158.770000 2264.480000 2159.770000 2264.960000 ;
+ RECT 2158.770000 2269.920000 2159.770000 2270.400000 ;
+ RECT 2146.120000 2275.360000 2147.220000 2275.840000 ;
+ RECT 2146.120000 2280.800000 2147.220000 2281.280000 ;
+ RECT 2146.120000 2286.240000 2147.220000 2286.720000 ;
+ RECT 2146.120000 2291.680000 2147.220000 2292.160000 ;
+ RECT 2146.120000 2297.120000 2147.220000 2297.600000 ;
+ RECT 2146.120000 2259.040000 2147.220000 2259.520000 ;
+ RECT 2146.120000 2253.600000 2147.220000 2254.080000 ;
+ RECT 2146.120000 2264.480000 2147.220000 2264.960000 ;
+ RECT 2146.120000 2269.920000 2147.220000 2270.400000 ;
+ RECT 2101.120000 2329.760000 2102.220000 2330.240000 ;
+ RECT 2101.120000 2324.320000 2102.220000 2324.800000 ;
+ RECT 2101.120000 2335.200000 2102.220000 2335.680000 ;
+ RECT 2101.120000 2340.640000 2102.220000 2341.120000 ;
+ RECT 2101.120000 2302.560000 2102.220000 2303.040000 ;
+ RECT 2101.120000 2308.000000 2102.220000 2308.480000 ;
+ RECT 2101.120000 2313.440000 2102.220000 2313.920000 ;
+ RECT 2101.120000 2318.880000 2102.220000 2319.360000 ;
+ RECT 2052.290000 2324.320000 2053.290000 2324.800000 ;
+ RECT 2052.290000 2329.760000 2053.290000 2330.240000 ;
+ RECT 2052.290000 2335.200000 2053.290000 2335.680000 ;
+ RECT 2052.290000 2340.640000 2053.290000 2341.120000 ;
+ RECT 2052.290000 2308.000000 2053.290000 2308.480000 ;
+ RECT 2052.290000 2302.560000 2053.290000 2303.040000 ;
+ RECT 2052.290000 2313.440000 2053.290000 2313.920000 ;
+ RECT 2052.290000 2318.880000 2053.290000 2319.360000 ;
+ RECT 2055.955000 2335.200000 2057.220000 2335.680000 ;
+ RECT 2055.955000 2329.760000 2057.220000 2330.240000 ;
+ RECT 2055.955000 2324.320000 2057.220000 2324.800000 ;
+ RECT 2055.955000 2340.640000 2057.220000 2341.120000 ;
+ RECT 2055.955000 2318.880000 2057.220000 2319.360000 ;
+ RECT 2055.955000 2313.440000 2057.220000 2313.920000 ;
+ RECT 2055.955000 2308.000000 2057.220000 2308.480000 ;
+ RECT 2055.955000 2302.560000 2057.220000 2303.040000 ;
+ RECT 2101.120000 2275.360000 2102.220000 2275.840000 ;
+ RECT 2101.120000 2280.800000 2102.220000 2281.280000 ;
+ RECT 2101.120000 2286.240000 2102.220000 2286.720000 ;
+ RECT 2101.120000 2291.680000 2102.220000 2292.160000 ;
+ RECT 2101.120000 2297.120000 2102.220000 2297.600000 ;
+ RECT 2101.120000 2253.600000 2102.220000 2254.080000 ;
+ RECT 2101.120000 2259.040000 2102.220000 2259.520000 ;
+ RECT 2101.120000 2264.480000 2102.220000 2264.960000 ;
+ RECT 2101.120000 2269.920000 2102.220000 2270.400000 ;
+ RECT 2052.290000 2275.360000 2053.290000 2275.840000 ;
+ RECT 2052.290000 2280.800000 2053.290000 2281.280000 ;
+ RECT 2052.290000 2286.240000 2053.290000 2286.720000 ;
+ RECT 2052.290000 2291.680000 2053.290000 2292.160000 ;
+ RECT 2052.290000 2297.120000 2053.290000 2297.600000 ;
+ RECT 2052.290000 2253.600000 2053.290000 2254.080000 ;
+ RECT 2052.290000 2259.040000 2053.290000 2259.520000 ;
+ RECT 2052.290000 2264.480000 2053.290000 2264.960000 ;
+ RECT 2052.290000 2269.920000 2053.290000 2270.400000 ;
+ RECT 2055.955000 2286.240000 2057.220000 2286.720000 ;
+ RECT 2055.955000 2280.800000 2057.220000 2281.280000 ;
+ RECT 2055.955000 2275.360000 2057.220000 2275.840000 ;
+ RECT 2055.955000 2291.680000 2057.220000 2292.160000 ;
+ RECT 2055.955000 2297.120000 2057.220000 2297.600000 ;
+ RECT 2055.955000 2269.920000 2057.220000 2270.400000 ;
+ RECT 2055.955000 2264.480000 2057.220000 2264.960000 ;
+ RECT 2055.955000 2259.040000 2057.220000 2259.520000 ;
+ RECT 2055.955000 2253.600000 2057.220000 2254.080000 ;
+ RECT 2158.770000 2226.400000 2159.770000 2226.880000 ;
+ RECT 2158.770000 2231.840000 2159.770000 2232.320000 ;
+ RECT 2158.770000 2237.280000 2159.770000 2237.760000 ;
+ RECT 2158.770000 2242.720000 2159.770000 2243.200000 ;
+ RECT 2158.770000 2199.200000 2159.770000 2199.680000 ;
+ RECT 2158.770000 2204.640000 2159.770000 2205.120000 ;
+ RECT 2158.770000 2210.080000 2159.770000 2210.560000 ;
+ RECT 2158.770000 2215.520000 2159.770000 2216.000000 ;
+ RECT 2158.770000 2220.960000 2159.770000 2221.440000 ;
+ RECT 2146.120000 2226.400000 2147.220000 2226.880000 ;
+ RECT 2146.120000 2231.840000 2147.220000 2232.320000 ;
+ RECT 2146.120000 2237.280000 2147.220000 2237.760000 ;
+ RECT 2146.120000 2242.720000 2147.220000 2243.200000 ;
+ RECT 2146.120000 2204.640000 2147.220000 2205.120000 ;
+ RECT 2146.120000 2199.200000 2147.220000 2199.680000 ;
+ RECT 2146.120000 2210.080000 2147.220000 2210.560000 ;
+ RECT 2146.120000 2215.520000 2147.220000 2216.000000 ;
+ RECT 2146.120000 2220.960000 2147.220000 2221.440000 ;
+ RECT 2158.770000 2177.440000 2159.770000 2177.920000 ;
+ RECT 2158.770000 2182.880000 2159.770000 2183.360000 ;
+ RECT 2158.770000 2188.320000 2159.770000 2188.800000 ;
+ RECT 2158.770000 2193.760000 2159.770000 2194.240000 ;
+ RECT 2158.770000 2155.680000 2159.770000 2156.160000 ;
+ RECT 2158.770000 2161.120000 2159.770000 2161.600000 ;
+ RECT 2158.770000 2166.560000 2159.770000 2167.040000 ;
+ RECT 2158.770000 2172.000000 2159.770000 2172.480000 ;
+ RECT 2146.120000 2177.440000 2147.220000 2177.920000 ;
+ RECT 2146.120000 2182.880000 2147.220000 2183.360000 ;
+ RECT 2146.120000 2188.320000 2147.220000 2188.800000 ;
+ RECT 2146.120000 2193.760000 2147.220000 2194.240000 ;
+ RECT 2146.120000 2155.680000 2147.220000 2156.160000 ;
+ RECT 2146.120000 2161.120000 2147.220000 2161.600000 ;
+ RECT 2146.120000 2166.560000 2147.220000 2167.040000 ;
+ RECT 2146.120000 2172.000000 2147.220000 2172.480000 ;
+ RECT 2101.120000 2226.400000 2102.220000 2226.880000 ;
+ RECT 2101.120000 2231.840000 2102.220000 2232.320000 ;
+ RECT 2101.120000 2237.280000 2102.220000 2237.760000 ;
+ RECT 2101.120000 2242.720000 2102.220000 2243.200000 ;
+ RECT 2101.120000 2199.200000 2102.220000 2199.680000 ;
+ RECT 2101.120000 2204.640000 2102.220000 2205.120000 ;
+ RECT 2101.120000 2210.080000 2102.220000 2210.560000 ;
+ RECT 2101.120000 2215.520000 2102.220000 2216.000000 ;
+ RECT 2101.120000 2220.960000 2102.220000 2221.440000 ;
+ RECT 2052.290000 2226.400000 2053.290000 2226.880000 ;
+ RECT 2052.290000 2231.840000 2053.290000 2232.320000 ;
+ RECT 2052.290000 2237.280000 2053.290000 2237.760000 ;
+ RECT 2052.290000 2242.720000 2053.290000 2243.200000 ;
+ RECT 2052.290000 2199.200000 2053.290000 2199.680000 ;
+ RECT 2052.290000 2204.640000 2053.290000 2205.120000 ;
+ RECT 2052.290000 2210.080000 2053.290000 2210.560000 ;
+ RECT 2052.290000 2215.520000 2053.290000 2216.000000 ;
+ RECT 2052.290000 2220.960000 2053.290000 2221.440000 ;
+ RECT 2055.955000 2231.840000 2057.220000 2232.320000 ;
+ RECT 2055.955000 2226.400000 2057.220000 2226.880000 ;
+ RECT 2055.955000 2237.280000 2057.220000 2237.760000 ;
+ RECT 2055.955000 2242.720000 2057.220000 2243.200000 ;
+ RECT 2055.955000 2220.960000 2057.220000 2221.440000 ;
+ RECT 2055.955000 2215.520000 2057.220000 2216.000000 ;
+ RECT 2055.955000 2210.080000 2057.220000 2210.560000 ;
+ RECT 2055.955000 2204.640000 2057.220000 2205.120000 ;
+ RECT 2055.955000 2199.200000 2057.220000 2199.680000 ;
+ RECT 2101.120000 2177.440000 2102.220000 2177.920000 ;
+ RECT 2101.120000 2182.880000 2102.220000 2183.360000 ;
+ RECT 2101.120000 2188.320000 2102.220000 2188.800000 ;
+ RECT 2101.120000 2193.760000 2102.220000 2194.240000 ;
+ RECT 2101.120000 2155.680000 2102.220000 2156.160000 ;
+ RECT 2101.120000 2161.120000 2102.220000 2161.600000 ;
+ RECT 2101.120000 2166.560000 2102.220000 2167.040000 ;
+ RECT 2101.120000 2172.000000 2102.220000 2172.480000 ;
+ RECT 2052.290000 2177.440000 2053.290000 2177.920000 ;
+ RECT 2052.290000 2182.880000 2053.290000 2183.360000 ;
+ RECT 2052.290000 2188.320000 2053.290000 2188.800000 ;
+ RECT 2052.290000 2193.760000 2053.290000 2194.240000 ;
+ RECT 2052.290000 2155.680000 2053.290000 2156.160000 ;
+ RECT 2052.290000 2161.120000 2053.290000 2161.600000 ;
+ RECT 2052.290000 2166.560000 2053.290000 2167.040000 ;
+ RECT 2052.290000 2172.000000 2053.290000 2172.480000 ;
+ RECT 2055.955000 2188.320000 2057.220000 2188.800000 ;
+ RECT 2055.955000 2182.880000 2057.220000 2183.360000 ;
+ RECT 2055.955000 2177.440000 2057.220000 2177.920000 ;
+ RECT 2055.955000 2193.760000 2057.220000 2194.240000 ;
+ RECT 2055.955000 2172.000000 2057.220000 2172.480000 ;
+ RECT 2055.955000 2166.560000 2057.220000 2167.040000 ;
+ RECT 2055.955000 2161.120000 2057.220000 2161.600000 ;
+ RECT 2055.955000 2155.680000 2057.220000 2156.160000 ;
+ RECT 2146.120000 2248.160000 2147.220000 2248.640000 ;
+ RECT 2101.120000 2248.160000 2102.220000 2248.640000 ;
+ RECT 2052.290000 2248.160000 2053.290000 2248.640000 ;
+ RECT 2055.955000 2248.160000 2057.220000 2248.640000 ;
+ RECT 2158.770000 2248.160000 2159.770000 2248.640000 ;
+ RECT 2051.060000 2344.920000 2161.000000 2345.920000 ;
+ RECT 2051.060000 2149.350000 2161.000000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 2148.100000 2053.290000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 2347.360000 2053.290000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 2148.100000 2159.770000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 2347.360000 2159.770000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2149.350000 2052.060000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2149.350000 2161.000000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2344.920000 2052.060000 2345.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2344.920000 2161.000000 2345.920000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 2134.940000 2057.220000 2135.420000 ;
+ RECT 2055.955000 2129.500000 2057.220000 2129.980000 ;
+ RECT 2055.955000 2124.060000 2057.220000 2124.540000 ;
+ RECT 2055.955000 2140.380000 2057.220000 2140.860000 ;
+ RECT 2055.955000 2118.620000 2057.220000 2119.100000 ;
+ RECT 2055.955000 2113.180000 2057.220000 2113.660000 ;
+ RECT 2055.955000 2107.740000 2057.220000 2108.220000 ;
+ RECT 2055.955000 2102.300000 2057.220000 2102.780000 ;
+ RECT 2055.955000 2085.980000 2057.220000 2086.460000 ;
+ RECT 2055.955000 2080.540000 2057.220000 2081.020000 ;
+ RECT 2055.955000 2075.100000 2057.220000 2075.580000 ;
+ RECT 2055.955000 2091.420000 2057.220000 2091.900000 ;
+ RECT 2055.955000 2096.860000 2057.220000 2097.340000 ;
+ RECT 2055.955000 2069.660000 2057.220000 2070.140000 ;
+ RECT 2055.955000 2064.220000 2057.220000 2064.700000 ;
+ RECT 2055.955000 2058.780000 2057.220000 2059.260000 ;
+ RECT 2055.955000 2053.340000 2057.220000 2053.820000 ;
+ RECT 2055.955000 2031.580000 2057.220000 2032.060000 ;
+ RECT 2055.955000 2026.140000 2057.220000 2026.620000 ;
+ RECT 2055.955000 2037.020000 2057.220000 2037.500000 ;
+ RECT 2055.955000 2042.460000 2057.220000 2042.940000 ;
+ RECT 2055.955000 2020.700000 2057.220000 2021.180000 ;
+ RECT 2055.955000 2015.260000 2057.220000 2015.740000 ;
+ RECT 2055.955000 2009.820000 2057.220000 2010.300000 ;
+ RECT 2055.955000 2004.380000 2057.220000 2004.860000 ;
+ RECT 2055.955000 1998.940000 2057.220000 1999.420000 ;
+ RECT 2055.955000 1988.060000 2057.220000 1988.540000 ;
+ RECT 2055.955000 1982.620000 2057.220000 1983.100000 ;
+ RECT 2055.955000 1977.180000 2057.220000 1977.660000 ;
+ RECT 2055.955000 1993.500000 2057.220000 1993.980000 ;
+ RECT 2055.955000 1971.740000 2057.220000 1972.220000 ;
+ RECT 2055.955000 1966.300000 2057.220000 1966.780000 ;
+ RECT 2055.955000 1960.860000 2057.220000 1961.340000 ;
+ RECT 2055.955000 1955.420000 2057.220000 1955.900000 ;
+ RECT 2055.955000 2047.900000 2057.220000 2048.380000 ;
+ RECT 2052.290000 1947.840000 2053.290000 2148.100000 ;
+ RECT 2158.770000 1947.840000 2159.770000 2148.100000 ;
+ RECT 2056.120000 1949.090000 2057.220000 2145.660000 ;
+ RECT 2101.120000 1949.090000 2102.220000 2145.660000 ;
+ RECT 2146.120000 1949.090000 2147.220000 2145.660000 ;
+ LAYER met3 ;
+ RECT 2158.770000 2124.060000 2159.770000 2124.540000 ;
+ RECT 2158.770000 2129.500000 2159.770000 2129.980000 ;
+ RECT 2158.770000 2134.940000 2159.770000 2135.420000 ;
+ RECT 2158.770000 2140.380000 2159.770000 2140.860000 ;
+ RECT 2158.770000 2107.740000 2159.770000 2108.220000 ;
+ RECT 2158.770000 2102.300000 2159.770000 2102.780000 ;
+ RECT 2158.770000 2113.180000 2159.770000 2113.660000 ;
+ RECT 2158.770000 2118.620000 2159.770000 2119.100000 ;
+ RECT 2146.120000 2124.060000 2147.220000 2124.540000 ;
+ RECT 2146.120000 2129.500000 2147.220000 2129.980000 ;
+ RECT 2146.120000 2134.940000 2147.220000 2135.420000 ;
+ RECT 2146.120000 2140.380000 2147.220000 2140.860000 ;
+ RECT 2146.120000 2107.740000 2147.220000 2108.220000 ;
+ RECT 2146.120000 2102.300000 2147.220000 2102.780000 ;
+ RECT 2146.120000 2113.180000 2147.220000 2113.660000 ;
+ RECT 2146.120000 2118.620000 2147.220000 2119.100000 ;
+ RECT 2158.770000 2075.100000 2159.770000 2075.580000 ;
+ RECT 2158.770000 2080.540000 2159.770000 2081.020000 ;
+ RECT 2158.770000 2085.980000 2159.770000 2086.460000 ;
+ RECT 2158.770000 2091.420000 2159.770000 2091.900000 ;
+ RECT 2158.770000 2096.860000 2159.770000 2097.340000 ;
+ RECT 2158.770000 2053.340000 2159.770000 2053.820000 ;
+ RECT 2158.770000 2058.780000 2159.770000 2059.260000 ;
+ RECT 2158.770000 2064.220000 2159.770000 2064.700000 ;
+ RECT 2158.770000 2069.660000 2159.770000 2070.140000 ;
+ RECT 2146.120000 2075.100000 2147.220000 2075.580000 ;
+ RECT 2146.120000 2080.540000 2147.220000 2081.020000 ;
+ RECT 2146.120000 2085.980000 2147.220000 2086.460000 ;
+ RECT 2146.120000 2091.420000 2147.220000 2091.900000 ;
+ RECT 2146.120000 2096.860000 2147.220000 2097.340000 ;
+ RECT 2146.120000 2058.780000 2147.220000 2059.260000 ;
+ RECT 2146.120000 2053.340000 2147.220000 2053.820000 ;
+ RECT 2146.120000 2064.220000 2147.220000 2064.700000 ;
+ RECT 2146.120000 2069.660000 2147.220000 2070.140000 ;
+ RECT 2101.120000 2129.500000 2102.220000 2129.980000 ;
+ RECT 2101.120000 2124.060000 2102.220000 2124.540000 ;
+ RECT 2101.120000 2134.940000 2102.220000 2135.420000 ;
+ RECT 2101.120000 2140.380000 2102.220000 2140.860000 ;
+ RECT 2101.120000 2102.300000 2102.220000 2102.780000 ;
+ RECT 2101.120000 2107.740000 2102.220000 2108.220000 ;
+ RECT 2101.120000 2113.180000 2102.220000 2113.660000 ;
+ RECT 2101.120000 2118.620000 2102.220000 2119.100000 ;
+ RECT 2052.290000 2124.060000 2053.290000 2124.540000 ;
+ RECT 2052.290000 2129.500000 2053.290000 2129.980000 ;
+ RECT 2052.290000 2134.940000 2053.290000 2135.420000 ;
+ RECT 2052.290000 2140.380000 2053.290000 2140.860000 ;
+ RECT 2052.290000 2107.740000 2053.290000 2108.220000 ;
+ RECT 2052.290000 2102.300000 2053.290000 2102.780000 ;
+ RECT 2052.290000 2113.180000 2053.290000 2113.660000 ;
+ RECT 2052.290000 2118.620000 2053.290000 2119.100000 ;
+ RECT 2055.955000 2134.940000 2057.220000 2135.420000 ;
+ RECT 2055.955000 2129.500000 2057.220000 2129.980000 ;
+ RECT 2055.955000 2124.060000 2057.220000 2124.540000 ;
+ RECT 2055.955000 2140.380000 2057.220000 2140.860000 ;
+ RECT 2055.955000 2118.620000 2057.220000 2119.100000 ;
+ RECT 2055.955000 2113.180000 2057.220000 2113.660000 ;
+ RECT 2055.955000 2107.740000 2057.220000 2108.220000 ;
+ RECT 2055.955000 2102.300000 2057.220000 2102.780000 ;
+ RECT 2101.120000 2075.100000 2102.220000 2075.580000 ;
+ RECT 2101.120000 2080.540000 2102.220000 2081.020000 ;
+ RECT 2101.120000 2085.980000 2102.220000 2086.460000 ;
+ RECT 2101.120000 2091.420000 2102.220000 2091.900000 ;
+ RECT 2101.120000 2096.860000 2102.220000 2097.340000 ;
+ RECT 2101.120000 2053.340000 2102.220000 2053.820000 ;
+ RECT 2101.120000 2058.780000 2102.220000 2059.260000 ;
+ RECT 2101.120000 2064.220000 2102.220000 2064.700000 ;
+ RECT 2101.120000 2069.660000 2102.220000 2070.140000 ;
+ RECT 2052.290000 2075.100000 2053.290000 2075.580000 ;
+ RECT 2052.290000 2080.540000 2053.290000 2081.020000 ;
+ RECT 2052.290000 2085.980000 2053.290000 2086.460000 ;
+ RECT 2052.290000 2091.420000 2053.290000 2091.900000 ;
+ RECT 2052.290000 2096.860000 2053.290000 2097.340000 ;
+ RECT 2052.290000 2053.340000 2053.290000 2053.820000 ;
+ RECT 2052.290000 2058.780000 2053.290000 2059.260000 ;
+ RECT 2052.290000 2064.220000 2053.290000 2064.700000 ;
+ RECT 2052.290000 2069.660000 2053.290000 2070.140000 ;
+ RECT 2055.955000 2085.980000 2057.220000 2086.460000 ;
+ RECT 2055.955000 2080.540000 2057.220000 2081.020000 ;
+ RECT 2055.955000 2075.100000 2057.220000 2075.580000 ;
+ RECT 2055.955000 2091.420000 2057.220000 2091.900000 ;
+ RECT 2055.955000 2096.860000 2057.220000 2097.340000 ;
+ RECT 2055.955000 2069.660000 2057.220000 2070.140000 ;
+ RECT 2055.955000 2064.220000 2057.220000 2064.700000 ;
+ RECT 2055.955000 2058.780000 2057.220000 2059.260000 ;
+ RECT 2055.955000 2053.340000 2057.220000 2053.820000 ;
+ RECT 2158.770000 2026.140000 2159.770000 2026.620000 ;
+ RECT 2158.770000 2031.580000 2159.770000 2032.060000 ;
+ RECT 2158.770000 2037.020000 2159.770000 2037.500000 ;
+ RECT 2158.770000 2042.460000 2159.770000 2042.940000 ;
+ RECT 2158.770000 1998.940000 2159.770000 1999.420000 ;
+ RECT 2158.770000 2004.380000 2159.770000 2004.860000 ;
+ RECT 2158.770000 2009.820000 2159.770000 2010.300000 ;
+ RECT 2158.770000 2015.260000 2159.770000 2015.740000 ;
+ RECT 2158.770000 2020.700000 2159.770000 2021.180000 ;
+ RECT 2146.120000 2026.140000 2147.220000 2026.620000 ;
+ RECT 2146.120000 2031.580000 2147.220000 2032.060000 ;
+ RECT 2146.120000 2037.020000 2147.220000 2037.500000 ;
+ RECT 2146.120000 2042.460000 2147.220000 2042.940000 ;
+ RECT 2146.120000 2004.380000 2147.220000 2004.860000 ;
+ RECT 2146.120000 1998.940000 2147.220000 1999.420000 ;
+ RECT 2146.120000 2009.820000 2147.220000 2010.300000 ;
+ RECT 2146.120000 2015.260000 2147.220000 2015.740000 ;
+ RECT 2146.120000 2020.700000 2147.220000 2021.180000 ;
+ RECT 2158.770000 1977.180000 2159.770000 1977.660000 ;
+ RECT 2158.770000 1982.620000 2159.770000 1983.100000 ;
+ RECT 2158.770000 1988.060000 2159.770000 1988.540000 ;
+ RECT 2158.770000 1993.500000 2159.770000 1993.980000 ;
+ RECT 2158.770000 1955.420000 2159.770000 1955.900000 ;
+ RECT 2158.770000 1960.860000 2159.770000 1961.340000 ;
+ RECT 2158.770000 1966.300000 2159.770000 1966.780000 ;
+ RECT 2158.770000 1971.740000 2159.770000 1972.220000 ;
+ RECT 2146.120000 1977.180000 2147.220000 1977.660000 ;
+ RECT 2146.120000 1982.620000 2147.220000 1983.100000 ;
+ RECT 2146.120000 1988.060000 2147.220000 1988.540000 ;
+ RECT 2146.120000 1993.500000 2147.220000 1993.980000 ;
+ RECT 2146.120000 1955.420000 2147.220000 1955.900000 ;
+ RECT 2146.120000 1960.860000 2147.220000 1961.340000 ;
+ RECT 2146.120000 1966.300000 2147.220000 1966.780000 ;
+ RECT 2146.120000 1971.740000 2147.220000 1972.220000 ;
+ RECT 2101.120000 2026.140000 2102.220000 2026.620000 ;
+ RECT 2101.120000 2031.580000 2102.220000 2032.060000 ;
+ RECT 2101.120000 2037.020000 2102.220000 2037.500000 ;
+ RECT 2101.120000 2042.460000 2102.220000 2042.940000 ;
+ RECT 2101.120000 1998.940000 2102.220000 1999.420000 ;
+ RECT 2101.120000 2004.380000 2102.220000 2004.860000 ;
+ RECT 2101.120000 2009.820000 2102.220000 2010.300000 ;
+ RECT 2101.120000 2015.260000 2102.220000 2015.740000 ;
+ RECT 2101.120000 2020.700000 2102.220000 2021.180000 ;
+ RECT 2052.290000 2026.140000 2053.290000 2026.620000 ;
+ RECT 2052.290000 2031.580000 2053.290000 2032.060000 ;
+ RECT 2052.290000 2037.020000 2053.290000 2037.500000 ;
+ RECT 2052.290000 2042.460000 2053.290000 2042.940000 ;
+ RECT 2052.290000 1998.940000 2053.290000 1999.420000 ;
+ RECT 2052.290000 2004.380000 2053.290000 2004.860000 ;
+ RECT 2052.290000 2009.820000 2053.290000 2010.300000 ;
+ RECT 2052.290000 2015.260000 2053.290000 2015.740000 ;
+ RECT 2052.290000 2020.700000 2053.290000 2021.180000 ;
+ RECT 2055.955000 2031.580000 2057.220000 2032.060000 ;
+ RECT 2055.955000 2026.140000 2057.220000 2026.620000 ;
+ RECT 2055.955000 2037.020000 2057.220000 2037.500000 ;
+ RECT 2055.955000 2042.460000 2057.220000 2042.940000 ;
+ RECT 2055.955000 2020.700000 2057.220000 2021.180000 ;
+ RECT 2055.955000 2015.260000 2057.220000 2015.740000 ;
+ RECT 2055.955000 2009.820000 2057.220000 2010.300000 ;
+ RECT 2055.955000 2004.380000 2057.220000 2004.860000 ;
+ RECT 2055.955000 1998.940000 2057.220000 1999.420000 ;
+ RECT 2101.120000 1977.180000 2102.220000 1977.660000 ;
+ RECT 2101.120000 1982.620000 2102.220000 1983.100000 ;
+ RECT 2101.120000 1988.060000 2102.220000 1988.540000 ;
+ RECT 2101.120000 1993.500000 2102.220000 1993.980000 ;
+ RECT 2101.120000 1955.420000 2102.220000 1955.900000 ;
+ RECT 2101.120000 1960.860000 2102.220000 1961.340000 ;
+ RECT 2101.120000 1966.300000 2102.220000 1966.780000 ;
+ RECT 2101.120000 1971.740000 2102.220000 1972.220000 ;
+ RECT 2052.290000 1977.180000 2053.290000 1977.660000 ;
+ RECT 2052.290000 1982.620000 2053.290000 1983.100000 ;
+ RECT 2052.290000 1988.060000 2053.290000 1988.540000 ;
+ RECT 2052.290000 1993.500000 2053.290000 1993.980000 ;
+ RECT 2052.290000 1955.420000 2053.290000 1955.900000 ;
+ RECT 2052.290000 1960.860000 2053.290000 1961.340000 ;
+ RECT 2052.290000 1966.300000 2053.290000 1966.780000 ;
+ RECT 2052.290000 1971.740000 2053.290000 1972.220000 ;
+ RECT 2055.955000 1988.060000 2057.220000 1988.540000 ;
+ RECT 2055.955000 1982.620000 2057.220000 1983.100000 ;
+ RECT 2055.955000 1977.180000 2057.220000 1977.660000 ;
+ RECT 2055.955000 1993.500000 2057.220000 1993.980000 ;
+ RECT 2055.955000 1971.740000 2057.220000 1972.220000 ;
+ RECT 2055.955000 1966.300000 2057.220000 1966.780000 ;
+ RECT 2055.955000 1960.860000 2057.220000 1961.340000 ;
+ RECT 2055.955000 1955.420000 2057.220000 1955.900000 ;
+ RECT 2146.120000 2047.900000 2147.220000 2048.380000 ;
+ RECT 2101.120000 2047.900000 2102.220000 2048.380000 ;
+ RECT 2052.290000 2047.900000 2053.290000 2048.380000 ;
+ RECT 2055.955000 2047.900000 2057.220000 2048.380000 ;
+ RECT 2158.770000 2047.900000 2159.770000 2048.380000 ;
+ RECT 2051.060000 2144.660000 2161.000000 2145.660000 ;
+ RECT 2051.060000 1949.090000 2161.000000 1950.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 1947.840000 2053.290000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 2147.100000 2053.290000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 1947.840000 2159.770000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 2147.100000 2159.770000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1949.090000 2052.060000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1949.090000 2161.000000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2144.660000 2052.060000 2145.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2144.660000 2161.000000 2145.660000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 1934.680000 2057.220000 1935.160000 ;
+ RECT 2055.955000 1929.240000 2057.220000 1929.720000 ;
+ RECT 2055.955000 1923.800000 2057.220000 1924.280000 ;
+ RECT 2055.955000 1940.120000 2057.220000 1940.600000 ;
+ RECT 2055.955000 1918.360000 2057.220000 1918.840000 ;
+ RECT 2055.955000 1912.920000 2057.220000 1913.400000 ;
+ RECT 2055.955000 1907.480000 2057.220000 1907.960000 ;
+ RECT 2055.955000 1902.040000 2057.220000 1902.520000 ;
+ RECT 2055.955000 1885.720000 2057.220000 1886.200000 ;
+ RECT 2055.955000 1880.280000 2057.220000 1880.760000 ;
+ RECT 2055.955000 1874.840000 2057.220000 1875.320000 ;
+ RECT 2055.955000 1891.160000 2057.220000 1891.640000 ;
+ RECT 2055.955000 1896.600000 2057.220000 1897.080000 ;
+ RECT 2055.955000 1869.400000 2057.220000 1869.880000 ;
+ RECT 2055.955000 1863.960000 2057.220000 1864.440000 ;
+ RECT 2055.955000 1858.520000 2057.220000 1859.000000 ;
+ RECT 2055.955000 1853.080000 2057.220000 1853.560000 ;
+ RECT 2055.955000 1831.320000 2057.220000 1831.800000 ;
+ RECT 2055.955000 1825.880000 2057.220000 1826.360000 ;
+ RECT 2055.955000 1836.760000 2057.220000 1837.240000 ;
+ RECT 2055.955000 1842.200000 2057.220000 1842.680000 ;
+ RECT 2055.955000 1820.440000 2057.220000 1820.920000 ;
+ RECT 2055.955000 1815.000000 2057.220000 1815.480000 ;
+ RECT 2055.955000 1809.560000 2057.220000 1810.040000 ;
+ RECT 2055.955000 1804.120000 2057.220000 1804.600000 ;
+ RECT 2055.955000 1798.680000 2057.220000 1799.160000 ;
+ RECT 2055.955000 1787.800000 2057.220000 1788.280000 ;
+ RECT 2055.955000 1782.360000 2057.220000 1782.840000 ;
+ RECT 2055.955000 1776.920000 2057.220000 1777.400000 ;
+ RECT 2055.955000 1793.240000 2057.220000 1793.720000 ;
+ RECT 2055.955000 1771.480000 2057.220000 1771.960000 ;
+ RECT 2055.955000 1766.040000 2057.220000 1766.520000 ;
+ RECT 2055.955000 1760.600000 2057.220000 1761.080000 ;
+ RECT 2055.955000 1755.160000 2057.220000 1755.640000 ;
+ RECT 2055.955000 1847.640000 2057.220000 1848.120000 ;
+ RECT 2052.290000 1747.580000 2053.290000 1947.840000 ;
+ RECT 2158.770000 1747.580000 2159.770000 1947.840000 ;
+ RECT 2056.120000 1748.830000 2057.220000 1945.400000 ;
+ RECT 2101.120000 1748.830000 2102.220000 1945.400000 ;
+ RECT 2146.120000 1748.830000 2147.220000 1945.400000 ;
+ LAYER met3 ;
+ RECT 2158.770000 1923.800000 2159.770000 1924.280000 ;
+ RECT 2158.770000 1929.240000 2159.770000 1929.720000 ;
+ RECT 2158.770000 1934.680000 2159.770000 1935.160000 ;
+ RECT 2158.770000 1940.120000 2159.770000 1940.600000 ;
+ RECT 2158.770000 1907.480000 2159.770000 1907.960000 ;
+ RECT 2158.770000 1902.040000 2159.770000 1902.520000 ;
+ RECT 2158.770000 1912.920000 2159.770000 1913.400000 ;
+ RECT 2158.770000 1918.360000 2159.770000 1918.840000 ;
+ RECT 2146.120000 1923.800000 2147.220000 1924.280000 ;
+ RECT 2146.120000 1929.240000 2147.220000 1929.720000 ;
+ RECT 2146.120000 1934.680000 2147.220000 1935.160000 ;
+ RECT 2146.120000 1940.120000 2147.220000 1940.600000 ;
+ RECT 2146.120000 1907.480000 2147.220000 1907.960000 ;
+ RECT 2146.120000 1902.040000 2147.220000 1902.520000 ;
+ RECT 2146.120000 1912.920000 2147.220000 1913.400000 ;
+ RECT 2146.120000 1918.360000 2147.220000 1918.840000 ;
+ RECT 2158.770000 1874.840000 2159.770000 1875.320000 ;
+ RECT 2158.770000 1880.280000 2159.770000 1880.760000 ;
+ RECT 2158.770000 1885.720000 2159.770000 1886.200000 ;
+ RECT 2158.770000 1891.160000 2159.770000 1891.640000 ;
+ RECT 2158.770000 1896.600000 2159.770000 1897.080000 ;
+ RECT 2158.770000 1853.080000 2159.770000 1853.560000 ;
+ RECT 2158.770000 1858.520000 2159.770000 1859.000000 ;
+ RECT 2158.770000 1863.960000 2159.770000 1864.440000 ;
+ RECT 2158.770000 1869.400000 2159.770000 1869.880000 ;
+ RECT 2146.120000 1874.840000 2147.220000 1875.320000 ;
+ RECT 2146.120000 1880.280000 2147.220000 1880.760000 ;
+ RECT 2146.120000 1885.720000 2147.220000 1886.200000 ;
+ RECT 2146.120000 1891.160000 2147.220000 1891.640000 ;
+ RECT 2146.120000 1896.600000 2147.220000 1897.080000 ;
+ RECT 2146.120000 1858.520000 2147.220000 1859.000000 ;
+ RECT 2146.120000 1853.080000 2147.220000 1853.560000 ;
+ RECT 2146.120000 1863.960000 2147.220000 1864.440000 ;
+ RECT 2146.120000 1869.400000 2147.220000 1869.880000 ;
+ RECT 2101.120000 1929.240000 2102.220000 1929.720000 ;
+ RECT 2101.120000 1923.800000 2102.220000 1924.280000 ;
+ RECT 2101.120000 1934.680000 2102.220000 1935.160000 ;
+ RECT 2101.120000 1940.120000 2102.220000 1940.600000 ;
+ RECT 2101.120000 1902.040000 2102.220000 1902.520000 ;
+ RECT 2101.120000 1907.480000 2102.220000 1907.960000 ;
+ RECT 2101.120000 1912.920000 2102.220000 1913.400000 ;
+ RECT 2101.120000 1918.360000 2102.220000 1918.840000 ;
+ RECT 2052.290000 1923.800000 2053.290000 1924.280000 ;
+ RECT 2052.290000 1929.240000 2053.290000 1929.720000 ;
+ RECT 2052.290000 1934.680000 2053.290000 1935.160000 ;
+ RECT 2052.290000 1940.120000 2053.290000 1940.600000 ;
+ RECT 2052.290000 1907.480000 2053.290000 1907.960000 ;
+ RECT 2052.290000 1902.040000 2053.290000 1902.520000 ;
+ RECT 2052.290000 1912.920000 2053.290000 1913.400000 ;
+ RECT 2052.290000 1918.360000 2053.290000 1918.840000 ;
+ RECT 2055.955000 1934.680000 2057.220000 1935.160000 ;
+ RECT 2055.955000 1929.240000 2057.220000 1929.720000 ;
+ RECT 2055.955000 1923.800000 2057.220000 1924.280000 ;
+ RECT 2055.955000 1940.120000 2057.220000 1940.600000 ;
+ RECT 2055.955000 1918.360000 2057.220000 1918.840000 ;
+ RECT 2055.955000 1912.920000 2057.220000 1913.400000 ;
+ RECT 2055.955000 1907.480000 2057.220000 1907.960000 ;
+ RECT 2055.955000 1902.040000 2057.220000 1902.520000 ;
+ RECT 2101.120000 1874.840000 2102.220000 1875.320000 ;
+ RECT 2101.120000 1880.280000 2102.220000 1880.760000 ;
+ RECT 2101.120000 1885.720000 2102.220000 1886.200000 ;
+ RECT 2101.120000 1891.160000 2102.220000 1891.640000 ;
+ RECT 2101.120000 1896.600000 2102.220000 1897.080000 ;
+ RECT 2101.120000 1853.080000 2102.220000 1853.560000 ;
+ RECT 2101.120000 1858.520000 2102.220000 1859.000000 ;
+ RECT 2101.120000 1863.960000 2102.220000 1864.440000 ;
+ RECT 2101.120000 1869.400000 2102.220000 1869.880000 ;
+ RECT 2052.290000 1874.840000 2053.290000 1875.320000 ;
+ RECT 2052.290000 1880.280000 2053.290000 1880.760000 ;
+ RECT 2052.290000 1885.720000 2053.290000 1886.200000 ;
+ RECT 2052.290000 1891.160000 2053.290000 1891.640000 ;
+ RECT 2052.290000 1896.600000 2053.290000 1897.080000 ;
+ RECT 2052.290000 1853.080000 2053.290000 1853.560000 ;
+ RECT 2052.290000 1858.520000 2053.290000 1859.000000 ;
+ RECT 2052.290000 1863.960000 2053.290000 1864.440000 ;
+ RECT 2052.290000 1869.400000 2053.290000 1869.880000 ;
+ RECT 2055.955000 1885.720000 2057.220000 1886.200000 ;
+ RECT 2055.955000 1880.280000 2057.220000 1880.760000 ;
+ RECT 2055.955000 1874.840000 2057.220000 1875.320000 ;
+ RECT 2055.955000 1891.160000 2057.220000 1891.640000 ;
+ RECT 2055.955000 1896.600000 2057.220000 1897.080000 ;
+ RECT 2055.955000 1869.400000 2057.220000 1869.880000 ;
+ RECT 2055.955000 1863.960000 2057.220000 1864.440000 ;
+ RECT 2055.955000 1858.520000 2057.220000 1859.000000 ;
+ RECT 2055.955000 1853.080000 2057.220000 1853.560000 ;
+ RECT 2158.770000 1825.880000 2159.770000 1826.360000 ;
+ RECT 2158.770000 1831.320000 2159.770000 1831.800000 ;
+ RECT 2158.770000 1836.760000 2159.770000 1837.240000 ;
+ RECT 2158.770000 1842.200000 2159.770000 1842.680000 ;
+ RECT 2158.770000 1798.680000 2159.770000 1799.160000 ;
+ RECT 2158.770000 1804.120000 2159.770000 1804.600000 ;
+ RECT 2158.770000 1809.560000 2159.770000 1810.040000 ;
+ RECT 2158.770000 1815.000000 2159.770000 1815.480000 ;
+ RECT 2158.770000 1820.440000 2159.770000 1820.920000 ;
+ RECT 2146.120000 1825.880000 2147.220000 1826.360000 ;
+ RECT 2146.120000 1831.320000 2147.220000 1831.800000 ;
+ RECT 2146.120000 1836.760000 2147.220000 1837.240000 ;
+ RECT 2146.120000 1842.200000 2147.220000 1842.680000 ;
+ RECT 2146.120000 1804.120000 2147.220000 1804.600000 ;
+ RECT 2146.120000 1798.680000 2147.220000 1799.160000 ;
+ RECT 2146.120000 1809.560000 2147.220000 1810.040000 ;
+ RECT 2146.120000 1815.000000 2147.220000 1815.480000 ;
+ RECT 2146.120000 1820.440000 2147.220000 1820.920000 ;
+ RECT 2158.770000 1776.920000 2159.770000 1777.400000 ;
+ RECT 2158.770000 1782.360000 2159.770000 1782.840000 ;
+ RECT 2158.770000 1787.800000 2159.770000 1788.280000 ;
+ RECT 2158.770000 1793.240000 2159.770000 1793.720000 ;
+ RECT 2158.770000 1755.160000 2159.770000 1755.640000 ;
+ RECT 2158.770000 1760.600000 2159.770000 1761.080000 ;
+ RECT 2158.770000 1766.040000 2159.770000 1766.520000 ;
+ RECT 2158.770000 1771.480000 2159.770000 1771.960000 ;
+ RECT 2146.120000 1776.920000 2147.220000 1777.400000 ;
+ RECT 2146.120000 1782.360000 2147.220000 1782.840000 ;
+ RECT 2146.120000 1787.800000 2147.220000 1788.280000 ;
+ RECT 2146.120000 1793.240000 2147.220000 1793.720000 ;
+ RECT 2146.120000 1755.160000 2147.220000 1755.640000 ;
+ RECT 2146.120000 1760.600000 2147.220000 1761.080000 ;
+ RECT 2146.120000 1766.040000 2147.220000 1766.520000 ;
+ RECT 2146.120000 1771.480000 2147.220000 1771.960000 ;
+ RECT 2101.120000 1825.880000 2102.220000 1826.360000 ;
+ RECT 2101.120000 1831.320000 2102.220000 1831.800000 ;
+ RECT 2101.120000 1836.760000 2102.220000 1837.240000 ;
+ RECT 2101.120000 1842.200000 2102.220000 1842.680000 ;
+ RECT 2101.120000 1798.680000 2102.220000 1799.160000 ;
+ RECT 2101.120000 1804.120000 2102.220000 1804.600000 ;
+ RECT 2101.120000 1809.560000 2102.220000 1810.040000 ;
+ RECT 2101.120000 1815.000000 2102.220000 1815.480000 ;
+ RECT 2101.120000 1820.440000 2102.220000 1820.920000 ;
+ RECT 2052.290000 1825.880000 2053.290000 1826.360000 ;
+ RECT 2052.290000 1831.320000 2053.290000 1831.800000 ;
+ RECT 2052.290000 1836.760000 2053.290000 1837.240000 ;
+ RECT 2052.290000 1842.200000 2053.290000 1842.680000 ;
+ RECT 2052.290000 1798.680000 2053.290000 1799.160000 ;
+ RECT 2052.290000 1804.120000 2053.290000 1804.600000 ;
+ RECT 2052.290000 1809.560000 2053.290000 1810.040000 ;
+ RECT 2052.290000 1815.000000 2053.290000 1815.480000 ;
+ RECT 2052.290000 1820.440000 2053.290000 1820.920000 ;
+ RECT 2055.955000 1831.320000 2057.220000 1831.800000 ;
+ RECT 2055.955000 1825.880000 2057.220000 1826.360000 ;
+ RECT 2055.955000 1836.760000 2057.220000 1837.240000 ;
+ RECT 2055.955000 1842.200000 2057.220000 1842.680000 ;
+ RECT 2055.955000 1820.440000 2057.220000 1820.920000 ;
+ RECT 2055.955000 1815.000000 2057.220000 1815.480000 ;
+ RECT 2055.955000 1809.560000 2057.220000 1810.040000 ;
+ RECT 2055.955000 1804.120000 2057.220000 1804.600000 ;
+ RECT 2055.955000 1798.680000 2057.220000 1799.160000 ;
+ RECT 2101.120000 1776.920000 2102.220000 1777.400000 ;
+ RECT 2101.120000 1782.360000 2102.220000 1782.840000 ;
+ RECT 2101.120000 1787.800000 2102.220000 1788.280000 ;
+ RECT 2101.120000 1793.240000 2102.220000 1793.720000 ;
+ RECT 2101.120000 1755.160000 2102.220000 1755.640000 ;
+ RECT 2101.120000 1760.600000 2102.220000 1761.080000 ;
+ RECT 2101.120000 1766.040000 2102.220000 1766.520000 ;
+ RECT 2101.120000 1771.480000 2102.220000 1771.960000 ;
+ RECT 2052.290000 1776.920000 2053.290000 1777.400000 ;
+ RECT 2052.290000 1782.360000 2053.290000 1782.840000 ;
+ RECT 2052.290000 1787.800000 2053.290000 1788.280000 ;
+ RECT 2052.290000 1793.240000 2053.290000 1793.720000 ;
+ RECT 2052.290000 1755.160000 2053.290000 1755.640000 ;
+ RECT 2052.290000 1760.600000 2053.290000 1761.080000 ;
+ RECT 2052.290000 1766.040000 2053.290000 1766.520000 ;
+ RECT 2052.290000 1771.480000 2053.290000 1771.960000 ;
+ RECT 2055.955000 1787.800000 2057.220000 1788.280000 ;
+ RECT 2055.955000 1782.360000 2057.220000 1782.840000 ;
+ RECT 2055.955000 1776.920000 2057.220000 1777.400000 ;
+ RECT 2055.955000 1793.240000 2057.220000 1793.720000 ;
+ RECT 2055.955000 1771.480000 2057.220000 1771.960000 ;
+ RECT 2055.955000 1766.040000 2057.220000 1766.520000 ;
+ RECT 2055.955000 1760.600000 2057.220000 1761.080000 ;
+ RECT 2055.955000 1755.160000 2057.220000 1755.640000 ;
+ RECT 2146.120000 1847.640000 2147.220000 1848.120000 ;
+ RECT 2101.120000 1847.640000 2102.220000 1848.120000 ;
+ RECT 2052.290000 1847.640000 2053.290000 1848.120000 ;
+ RECT 2055.955000 1847.640000 2057.220000 1848.120000 ;
+ RECT 2158.770000 1847.640000 2159.770000 1848.120000 ;
+ RECT 2051.060000 1944.400000 2161.000000 1945.400000 ;
+ RECT 2051.060000 1748.830000 2161.000000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 1747.580000 2053.290000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 1946.840000 2053.290000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 1747.580000 2159.770000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 1946.840000 2159.770000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1748.830000 2052.060000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1748.830000 2161.000000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1944.400000 2052.060000 1945.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1944.400000 2161.000000 1945.400000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2055.955000 1734.420000 2057.220000 1734.900000 ;
+ RECT 2055.955000 1728.980000 2057.220000 1729.460000 ;
+ RECT 2055.955000 1723.540000 2057.220000 1724.020000 ;
+ RECT 2055.955000 1739.860000 2057.220000 1740.340000 ;
+ RECT 2055.955000 1718.100000 2057.220000 1718.580000 ;
+ RECT 2055.955000 1712.660000 2057.220000 1713.140000 ;
+ RECT 2055.955000 1707.220000 2057.220000 1707.700000 ;
+ RECT 2055.955000 1701.780000 2057.220000 1702.260000 ;
+ RECT 2055.955000 1685.460000 2057.220000 1685.940000 ;
+ RECT 2055.955000 1680.020000 2057.220000 1680.500000 ;
+ RECT 2055.955000 1674.580000 2057.220000 1675.060000 ;
+ RECT 2055.955000 1690.900000 2057.220000 1691.380000 ;
+ RECT 2055.955000 1696.340000 2057.220000 1696.820000 ;
+ RECT 2055.955000 1669.140000 2057.220000 1669.620000 ;
+ RECT 2055.955000 1663.700000 2057.220000 1664.180000 ;
+ RECT 2055.955000 1658.260000 2057.220000 1658.740000 ;
+ RECT 2055.955000 1652.820000 2057.220000 1653.300000 ;
+ RECT 2055.955000 1631.060000 2057.220000 1631.540000 ;
+ RECT 2055.955000 1625.620000 2057.220000 1626.100000 ;
+ RECT 2055.955000 1636.500000 2057.220000 1636.980000 ;
+ RECT 2055.955000 1641.940000 2057.220000 1642.420000 ;
+ RECT 2055.955000 1620.180000 2057.220000 1620.660000 ;
+ RECT 2055.955000 1614.740000 2057.220000 1615.220000 ;
+ RECT 2055.955000 1609.300000 2057.220000 1609.780000 ;
+ RECT 2055.955000 1603.860000 2057.220000 1604.340000 ;
+ RECT 2055.955000 1598.420000 2057.220000 1598.900000 ;
+ RECT 2055.955000 1587.540000 2057.220000 1588.020000 ;
+ RECT 2055.955000 1582.100000 2057.220000 1582.580000 ;
+ RECT 2055.955000 1576.660000 2057.220000 1577.140000 ;
+ RECT 2055.955000 1592.980000 2057.220000 1593.460000 ;
+ RECT 2055.955000 1571.220000 2057.220000 1571.700000 ;
+ RECT 2055.955000 1565.780000 2057.220000 1566.260000 ;
+ RECT 2055.955000 1560.340000 2057.220000 1560.820000 ;
+ RECT 2055.955000 1554.900000 2057.220000 1555.380000 ;
+ RECT 2055.955000 1647.380000 2057.220000 1647.860000 ;
+ RECT 2052.290000 1547.320000 2053.290000 1747.580000 ;
+ RECT 2158.770000 1547.320000 2159.770000 1747.580000 ;
+ RECT 2056.120000 1548.570000 2057.220000 1745.140000 ;
+ RECT 2101.120000 1548.570000 2102.220000 1745.140000 ;
+ RECT 2146.120000 1548.570000 2147.220000 1745.140000 ;
+ LAYER met3 ;
+ RECT 2158.770000 1723.540000 2159.770000 1724.020000 ;
+ RECT 2158.770000 1728.980000 2159.770000 1729.460000 ;
+ RECT 2158.770000 1734.420000 2159.770000 1734.900000 ;
+ RECT 2158.770000 1739.860000 2159.770000 1740.340000 ;
+ RECT 2158.770000 1707.220000 2159.770000 1707.700000 ;
+ RECT 2158.770000 1701.780000 2159.770000 1702.260000 ;
+ RECT 2158.770000 1712.660000 2159.770000 1713.140000 ;
+ RECT 2158.770000 1718.100000 2159.770000 1718.580000 ;
+ RECT 2146.120000 1723.540000 2147.220000 1724.020000 ;
+ RECT 2146.120000 1728.980000 2147.220000 1729.460000 ;
+ RECT 2146.120000 1734.420000 2147.220000 1734.900000 ;
+ RECT 2146.120000 1739.860000 2147.220000 1740.340000 ;
+ RECT 2146.120000 1707.220000 2147.220000 1707.700000 ;
+ RECT 2146.120000 1701.780000 2147.220000 1702.260000 ;
+ RECT 2146.120000 1712.660000 2147.220000 1713.140000 ;
+ RECT 2146.120000 1718.100000 2147.220000 1718.580000 ;
+ RECT 2158.770000 1674.580000 2159.770000 1675.060000 ;
+ RECT 2158.770000 1680.020000 2159.770000 1680.500000 ;
+ RECT 2158.770000 1685.460000 2159.770000 1685.940000 ;
+ RECT 2158.770000 1690.900000 2159.770000 1691.380000 ;
+ RECT 2158.770000 1696.340000 2159.770000 1696.820000 ;
+ RECT 2158.770000 1652.820000 2159.770000 1653.300000 ;
+ RECT 2158.770000 1658.260000 2159.770000 1658.740000 ;
+ RECT 2158.770000 1663.700000 2159.770000 1664.180000 ;
+ RECT 2158.770000 1669.140000 2159.770000 1669.620000 ;
+ RECT 2146.120000 1674.580000 2147.220000 1675.060000 ;
+ RECT 2146.120000 1680.020000 2147.220000 1680.500000 ;
+ RECT 2146.120000 1685.460000 2147.220000 1685.940000 ;
+ RECT 2146.120000 1690.900000 2147.220000 1691.380000 ;
+ RECT 2146.120000 1696.340000 2147.220000 1696.820000 ;
+ RECT 2146.120000 1658.260000 2147.220000 1658.740000 ;
+ RECT 2146.120000 1652.820000 2147.220000 1653.300000 ;
+ RECT 2146.120000 1663.700000 2147.220000 1664.180000 ;
+ RECT 2146.120000 1669.140000 2147.220000 1669.620000 ;
+ RECT 2101.120000 1728.980000 2102.220000 1729.460000 ;
+ RECT 2101.120000 1723.540000 2102.220000 1724.020000 ;
+ RECT 2101.120000 1734.420000 2102.220000 1734.900000 ;
+ RECT 2101.120000 1739.860000 2102.220000 1740.340000 ;
+ RECT 2101.120000 1701.780000 2102.220000 1702.260000 ;
+ RECT 2101.120000 1707.220000 2102.220000 1707.700000 ;
+ RECT 2101.120000 1712.660000 2102.220000 1713.140000 ;
+ RECT 2101.120000 1718.100000 2102.220000 1718.580000 ;
+ RECT 2052.290000 1723.540000 2053.290000 1724.020000 ;
+ RECT 2052.290000 1728.980000 2053.290000 1729.460000 ;
+ RECT 2052.290000 1734.420000 2053.290000 1734.900000 ;
+ RECT 2052.290000 1739.860000 2053.290000 1740.340000 ;
+ RECT 2052.290000 1707.220000 2053.290000 1707.700000 ;
+ RECT 2052.290000 1701.780000 2053.290000 1702.260000 ;
+ RECT 2052.290000 1712.660000 2053.290000 1713.140000 ;
+ RECT 2052.290000 1718.100000 2053.290000 1718.580000 ;
+ RECT 2055.955000 1734.420000 2057.220000 1734.900000 ;
+ RECT 2055.955000 1728.980000 2057.220000 1729.460000 ;
+ RECT 2055.955000 1723.540000 2057.220000 1724.020000 ;
+ RECT 2055.955000 1739.860000 2057.220000 1740.340000 ;
+ RECT 2055.955000 1718.100000 2057.220000 1718.580000 ;
+ RECT 2055.955000 1712.660000 2057.220000 1713.140000 ;
+ RECT 2055.955000 1707.220000 2057.220000 1707.700000 ;
+ RECT 2055.955000 1701.780000 2057.220000 1702.260000 ;
+ RECT 2101.120000 1674.580000 2102.220000 1675.060000 ;
+ RECT 2101.120000 1680.020000 2102.220000 1680.500000 ;
+ RECT 2101.120000 1685.460000 2102.220000 1685.940000 ;
+ RECT 2101.120000 1690.900000 2102.220000 1691.380000 ;
+ RECT 2101.120000 1696.340000 2102.220000 1696.820000 ;
+ RECT 2101.120000 1652.820000 2102.220000 1653.300000 ;
+ RECT 2101.120000 1658.260000 2102.220000 1658.740000 ;
+ RECT 2101.120000 1663.700000 2102.220000 1664.180000 ;
+ RECT 2101.120000 1669.140000 2102.220000 1669.620000 ;
+ RECT 2052.290000 1674.580000 2053.290000 1675.060000 ;
+ RECT 2052.290000 1680.020000 2053.290000 1680.500000 ;
+ RECT 2052.290000 1685.460000 2053.290000 1685.940000 ;
+ RECT 2052.290000 1690.900000 2053.290000 1691.380000 ;
+ RECT 2052.290000 1696.340000 2053.290000 1696.820000 ;
+ RECT 2052.290000 1652.820000 2053.290000 1653.300000 ;
+ RECT 2052.290000 1658.260000 2053.290000 1658.740000 ;
+ RECT 2052.290000 1663.700000 2053.290000 1664.180000 ;
+ RECT 2052.290000 1669.140000 2053.290000 1669.620000 ;
+ RECT 2055.955000 1685.460000 2057.220000 1685.940000 ;
+ RECT 2055.955000 1680.020000 2057.220000 1680.500000 ;
+ RECT 2055.955000 1674.580000 2057.220000 1675.060000 ;
+ RECT 2055.955000 1690.900000 2057.220000 1691.380000 ;
+ RECT 2055.955000 1696.340000 2057.220000 1696.820000 ;
+ RECT 2055.955000 1669.140000 2057.220000 1669.620000 ;
+ RECT 2055.955000 1663.700000 2057.220000 1664.180000 ;
+ RECT 2055.955000 1658.260000 2057.220000 1658.740000 ;
+ RECT 2055.955000 1652.820000 2057.220000 1653.300000 ;
+ RECT 2158.770000 1625.620000 2159.770000 1626.100000 ;
+ RECT 2158.770000 1631.060000 2159.770000 1631.540000 ;
+ RECT 2158.770000 1636.500000 2159.770000 1636.980000 ;
+ RECT 2158.770000 1641.940000 2159.770000 1642.420000 ;
+ RECT 2158.770000 1598.420000 2159.770000 1598.900000 ;
+ RECT 2158.770000 1603.860000 2159.770000 1604.340000 ;
+ RECT 2158.770000 1609.300000 2159.770000 1609.780000 ;
+ RECT 2158.770000 1614.740000 2159.770000 1615.220000 ;
+ RECT 2158.770000 1620.180000 2159.770000 1620.660000 ;
+ RECT 2146.120000 1625.620000 2147.220000 1626.100000 ;
+ RECT 2146.120000 1631.060000 2147.220000 1631.540000 ;
+ RECT 2146.120000 1636.500000 2147.220000 1636.980000 ;
+ RECT 2146.120000 1641.940000 2147.220000 1642.420000 ;
+ RECT 2146.120000 1603.860000 2147.220000 1604.340000 ;
+ RECT 2146.120000 1598.420000 2147.220000 1598.900000 ;
+ RECT 2146.120000 1609.300000 2147.220000 1609.780000 ;
+ RECT 2146.120000 1614.740000 2147.220000 1615.220000 ;
+ RECT 2146.120000 1620.180000 2147.220000 1620.660000 ;
+ RECT 2158.770000 1576.660000 2159.770000 1577.140000 ;
+ RECT 2158.770000 1582.100000 2159.770000 1582.580000 ;
+ RECT 2158.770000 1587.540000 2159.770000 1588.020000 ;
+ RECT 2158.770000 1592.980000 2159.770000 1593.460000 ;
+ RECT 2158.770000 1554.900000 2159.770000 1555.380000 ;
+ RECT 2158.770000 1560.340000 2159.770000 1560.820000 ;
+ RECT 2158.770000 1565.780000 2159.770000 1566.260000 ;
+ RECT 2158.770000 1571.220000 2159.770000 1571.700000 ;
+ RECT 2146.120000 1576.660000 2147.220000 1577.140000 ;
+ RECT 2146.120000 1582.100000 2147.220000 1582.580000 ;
+ RECT 2146.120000 1587.540000 2147.220000 1588.020000 ;
+ RECT 2146.120000 1592.980000 2147.220000 1593.460000 ;
+ RECT 2146.120000 1554.900000 2147.220000 1555.380000 ;
+ RECT 2146.120000 1560.340000 2147.220000 1560.820000 ;
+ RECT 2146.120000 1565.780000 2147.220000 1566.260000 ;
+ RECT 2146.120000 1571.220000 2147.220000 1571.700000 ;
+ RECT 2101.120000 1625.620000 2102.220000 1626.100000 ;
+ RECT 2101.120000 1631.060000 2102.220000 1631.540000 ;
+ RECT 2101.120000 1636.500000 2102.220000 1636.980000 ;
+ RECT 2101.120000 1641.940000 2102.220000 1642.420000 ;
+ RECT 2101.120000 1598.420000 2102.220000 1598.900000 ;
+ RECT 2101.120000 1603.860000 2102.220000 1604.340000 ;
+ RECT 2101.120000 1609.300000 2102.220000 1609.780000 ;
+ RECT 2101.120000 1614.740000 2102.220000 1615.220000 ;
+ RECT 2101.120000 1620.180000 2102.220000 1620.660000 ;
+ RECT 2052.290000 1625.620000 2053.290000 1626.100000 ;
+ RECT 2052.290000 1631.060000 2053.290000 1631.540000 ;
+ RECT 2052.290000 1636.500000 2053.290000 1636.980000 ;
+ RECT 2052.290000 1641.940000 2053.290000 1642.420000 ;
+ RECT 2052.290000 1598.420000 2053.290000 1598.900000 ;
+ RECT 2052.290000 1603.860000 2053.290000 1604.340000 ;
+ RECT 2052.290000 1609.300000 2053.290000 1609.780000 ;
+ RECT 2052.290000 1614.740000 2053.290000 1615.220000 ;
+ RECT 2052.290000 1620.180000 2053.290000 1620.660000 ;
+ RECT 2055.955000 1631.060000 2057.220000 1631.540000 ;
+ RECT 2055.955000 1625.620000 2057.220000 1626.100000 ;
+ RECT 2055.955000 1636.500000 2057.220000 1636.980000 ;
+ RECT 2055.955000 1641.940000 2057.220000 1642.420000 ;
+ RECT 2055.955000 1620.180000 2057.220000 1620.660000 ;
+ RECT 2055.955000 1614.740000 2057.220000 1615.220000 ;
+ RECT 2055.955000 1609.300000 2057.220000 1609.780000 ;
+ RECT 2055.955000 1603.860000 2057.220000 1604.340000 ;
+ RECT 2055.955000 1598.420000 2057.220000 1598.900000 ;
+ RECT 2101.120000 1576.660000 2102.220000 1577.140000 ;
+ RECT 2101.120000 1582.100000 2102.220000 1582.580000 ;
+ RECT 2101.120000 1587.540000 2102.220000 1588.020000 ;
+ RECT 2101.120000 1592.980000 2102.220000 1593.460000 ;
+ RECT 2101.120000 1554.900000 2102.220000 1555.380000 ;
+ RECT 2101.120000 1560.340000 2102.220000 1560.820000 ;
+ RECT 2101.120000 1565.780000 2102.220000 1566.260000 ;
+ RECT 2101.120000 1571.220000 2102.220000 1571.700000 ;
+ RECT 2052.290000 1576.660000 2053.290000 1577.140000 ;
+ RECT 2052.290000 1582.100000 2053.290000 1582.580000 ;
+ RECT 2052.290000 1587.540000 2053.290000 1588.020000 ;
+ RECT 2052.290000 1592.980000 2053.290000 1593.460000 ;
+ RECT 2052.290000 1554.900000 2053.290000 1555.380000 ;
+ RECT 2052.290000 1560.340000 2053.290000 1560.820000 ;
+ RECT 2052.290000 1565.780000 2053.290000 1566.260000 ;
+ RECT 2052.290000 1571.220000 2053.290000 1571.700000 ;
+ RECT 2055.955000 1587.540000 2057.220000 1588.020000 ;
+ RECT 2055.955000 1582.100000 2057.220000 1582.580000 ;
+ RECT 2055.955000 1576.660000 2057.220000 1577.140000 ;
+ RECT 2055.955000 1592.980000 2057.220000 1593.460000 ;
+ RECT 2055.955000 1571.220000 2057.220000 1571.700000 ;
+ RECT 2055.955000 1565.780000 2057.220000 1566.260000 ;
+ RECT 2055.955000 1560.340000 2057.220000 1560.820000 ;
+ RECT 2055.955000 1554.900000 2057.220000 1555.380000 ;
+ RECT 2146.120000 1647.380000 2147.220000 1647.860000 ;
+ RECT 2101.120000 1647.380000 2102.220000 1647.860000 ;
+ RECT 2052.290000 1647.380000 2053.290000 1647.860000 ;
+ RECT 2055.955000 1647.380000 2057.220000 1647.860000 ;
+ RECT 2158.770000 1647.380000 2159.770000 1647.860000 ;
+ RECT 2051.060000 1744.140000 2161.000000 1745.140000 ;
+ RECT 2051.060000 1548.570000 2161.000000 1549.570000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 1547.320000 2053.290000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2052.290000 1746.580000 2053.290000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 1547.320000 2159.770000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2158.770000 1746.580000 2159.770000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1548.570000 2052.060000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1548.570000 2161.000000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1744.140000 2052.060000 1745.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1744.140000 2161.000000 1745.140000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 3373.560000 246.320000 3374.040000 ;
+ RECT 245.055000 3368.120000 246.320000 3368.600000 ;
+ RECT 245.055000 3362.680000 246.320000 3363.160000 ;
+ RECT 245.055000 3357.240000 246.320000 3357.720000 ;
+ RECT 241.390000 3349.660000 242.390000 3379.920000 ;
+ RECT 438.030000 3349.660000 439.030000 3379.920000 ;
+ RECT 245.220000 3350.910000 246.320000 3378.160000 ;
+ RECT 290.220000 3350.910000 291.320000 3378.160000 ;
+ RECT 335.220000 3350.910000 336.320000 3378.160000 ;
+ RECT 380.220000 3350.910000 381.320000 3378.160000 ;
+ RECT 425.220000 3350.910000 426.320000 3378.160000 ;
+ LAYER met3 ;
+ RECT 438.030000 3373.560000 439.030000 3374.040000 ;
+ RECT 438.030000 3368.120000 439.030000 3368.600000 ;
+ RECT 425.220000 3373.560000 426.320000 3374.040000 ;
+ RECT 425.220000 3368.120000 426.320000 3368.600000 ;
+ RECT 380.220000 3368.120000 381.320000 3368.600000 ;
+ RECT 380.220000 3373.560000 381.320000 3374.040000 ;
+ RECT 335.220000 3368.120000 336.320000 3368.600000 ;
+ RECT 290.220000 3368.120000 291.320000 3368.600000 ;
+ RECT 335.220000 3373.560000 336.320000 3374.040000 ;
+ RECT 290.220000 3373.560000 291.320000 3374.040000 ;
+ RECT 245.055000 3373.560000 246.320000 3374.040000 ;
+ RECT 241.390000 3373.560000 242.390000 3374.040000 ;
+ RECT 245.055000 3368.120000 246.320000 3368.600000 ;
+ RECT 241.390000 3368.120000 242.390000 3368.600000 ;
+ RECT 438.030000 3362.680000 439.030000 3363.160000 ;
+ RECT 438.030000 3357.240000 439.030000 3357.720000 ;
+ RECT 425.220000 3362.680000 426.320000 3363.160000 ;
+ RECT 425.220000 3357.240000 426.320000 3357.720000 ;
+ RECT 380.220000 3357.240000 381.320000 3357.720000 ;
+ RECT 380.220000 3362.680000 381.320000 3363.160000 ;
+ RECT 335.220000 3357.240000 336.320000 3357.720000 ;
+ RECT 290.220000 3357.240000 291.320000 3357.720000 ;
+ RECT 335.220000 3362.680000 336.320000 3363.160000 ;
+ RECT 290.220000 3362.680000 291.320000 3363.160000 ;
+ RECT 245.055000 3362.680000 246.320000 3363.160000 ;
+ RECT 241.390000 3362.680000 242.390000 3363.160000 ;
+ RECT 245.055000 3357.240000 246.320000 3357.720000 ;
+ RECT 241.390000 3357.240000 242.390000 3357.720000 ;
+ RECT 240.160000 3377.160000 440.260000 3378.160000 ;
+ RECT 240.160000 3350.910000 440.260000 3351.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 3349.660000 242.390000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 3378.920000 242.390000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 3349.660000 439.030000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 3378.920000 439.030000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 3350.910000 241.160000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 3350.910000 440.260000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 3377.160000 241.160000 3378.160000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 3377.160000 440.260000 3378.160000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 1539.600000 246.320000 1540.080000 ;
+ RECT 245.055000 1528.720000 246.320000 1529.200000 ;
+ RECT 245.055000 1534.160000 246.320000 1534.640000 ;
+ RECT 245.055000 1523.280000 246.320000 1523.760000 ;
+ RECT 245.055000 1517.840000 246.320000 1518.320000 ;
+ RECT 245.055000 1512.400000 246.320000 1512.880000 ;
+ RECT 245.055000 1506.960000 246.320000 1507.440000 ;
+ RECT 245.055000 1501.520000 246.320000 1502.000000 ;
+ RECT 245.055000 1496.080000 246.320000 1496.560000 ;
+ RECT 245.055000 1485.200000 246.320000 1485.680000 ;
+ RECT 245.055000 1490.640000 246.320000 1491.120000 ;
+ RECT 245.055000 1479.760000 246.320000 1480.240000 ;
+ RECT 245.055000 1474.320000 246.320000 1474.800000 ;
+ RECT 245.055000 1468.880000 246.320000 1469.360000 ;
+ RECT 245.055000 1463.440000 246.320000 1463.920000 ;
+ RECT 245.055000 1458.000000 246.320000 1458.480000 ;
+ RECT 245.055000 1452.560000 246.320000 1453.040000 ;
+ RECT 245.055000 1441.680000 246.320000 1442.160000 ;
+ RECT 245.055000 1436.240000 246.320000 1436.720000 ;
+ RECT 245.055000 1430.800000 246.320000 1431.280000 ;
+ RECT 245.055000 1425.360000 246.320000 1425.840000 ;
+ RECT 245.055000 1419.920000 246.320000 1420.400000 ;
+ RECT 245.055000 1414.480000 246.320000 1414.960000 ;
+ RECT 245.055000 1403.600000 246.320000 1404.080000 ;
+ RECT 245.055000 1409.040000 246.320000 1409.520000 ;
+ RECT 245.055000 1398.160000 246.320000 1398.640000 ;
+ RECT 245.055000 1392.720000 246.320000 1393.200000 ;
+ RECT 245.055000 1387.280000 246.320000 1387.760000 ;
+ RECT 245.055000 1381.840000 246.320000 1382.320000 ;
+ RECT 245.055000 1376.400000 246.320000 1376.880000 ;
+ RECT 245.055000 1370.960000 246.320000 1371.440000 ;
+ RECT 245.055000 1360.080000 246.320000 1360.560000 ;
+ RECT 245.055000 1365.520000 246.320000 1366.000000 ;
+ RECT 245.055000 1354.640000 246.320000 1355.120000 ;
+ RECT 245.055000 1447.120000 246.320000 1447.600000 ;
+ RECT 425.220000 1348.310000 426.320000 1544.880000 ;
+ RECT 380.220000 1348.310000 381.320000 1544.880000 ;
+ RECT 438.030000 1347.060000 439.030000 1547.320000 ;
+ RECT 335.220000 1348.310000 336.320000 1544.880000 ;
+ RECT 290.220000 1348.310000 291.320000 1544.880000 ;
+ RECT 245.220000 1348.310000 246.320000 1544.880000 ;
+ RECT 241.390000 1347.060000 242.390000 1547.320000 ;
+ LAYER met3 ;
+ RECT 425.220000 1539.600000 426.320000 1540.080000 ;
+ RECT 438.030000 1539.600000 439.030000 1540.080000 ;
+ RECT 438.030000 1528.720000 439.030000 1529.200000 ;
+ RECT 438.030000 1523.280000 439.030000 1523.760000 ;
+ RECT 438.030000 1534.160000 439.030000 1534.640000 ;
+ RECT 425.220000 1534.160000 426.320000 1534.640000 ;
+ RECT 425.220000 1528.720000 426.320000 1529.200000 ;
+ RECT 425.220000 1523.280000 426.320000 1523.760000 ;
+ RECT 425.220000 1512.400000 426.320000 1512.880000 ;
+ RECT 425.220000 1517.840000 426.320000 1518.320000 ;
+ RECT 438.030000 1512.400000 439.030000 1512.880000 ;
+ RECT 438.030000 1517.840000 439.030000 1518.320000 ;
+ RECT 425.220000 1501.520000 426.320000 1502.000000 ;
+ RECT 425.220000 1506.960000 426.320000 1507.440000 ;
+ RECT 438.030000 1501.520000 439.030000 1502.000000 ;
+ RECT 438.030000 1506.960000 439.030000 1507.440000 ;
+ RECT 380.220000 1523.280000 381.320000 1523.760000 ;
+ RECT 380.220000 1528.720000 381.320000 1529.200000 ;
+ RECT 380.220000 1534.160000 381.320000 1534.640000 ;
+ RECT 380.220000 1539.600000 381.320000 1540.080000 ;
+ RECT 380.220000 1506.960000 381.320000 1507.440000 ;
+ RECT 380.220000 1501.520000 381.320000 1502.000000 ;
+ RECT 380.220000 1512.400000 381.320000 1512.880000 ;
+ RECT 380.220000 1517.840000 381.320000 1518.320000 ;
+ RECT 438.030000 1490.640000 439.030000 1491.120000 ;
+ RECT 438.030000 1485.200000 439.030000 1485.680000 ;
+ RECT 438.030000 1496.080000 439.030000 1496.560000 ;
+ RECT 425.220000 1496.080000 426.320000 1496.560000 ;
+ RECT 425.220000 1490.640000 426.320000 1491.120000 ;
+ RECT 425.220000 1485.200000 426.320000 1485.680000 ;
+ RECT 425.220000 1474.320000 426.320000 1474.800000 ;
+ RECT 425.220000 1479.760000 426.320000 1480.240000 ;
+ RECT 438.030000 1474.320000 439.030000 1474.800000 ;
+ RECT 438.030000 1479.760000 439.030000 1480.240000 ;
+ RECT 438.030000 1463.440000 439.030000 1463.920000 ;
+ RECT 438.030000 1468.880000 439.030000 1469.360000 ;
+ RECT 425.220000 1468.880000 426.320000 1469.360000 ;
+ RECT 425.220000 1463.440000 426.320000 1463.920000 ;
+ RECT 425.220000 1452.560000 426.320000 1453.040000 ;
+ RECT 425.220000 1458.000000 426.320000 1458.480000 ;
+ RECT 438.030000 1452.560000 439.030000 1453.040000 ;
+ RECT 438.030000 1458.000000 439.030000 1458.480000 ;
+ RECT 380.220000 1474.320000 381.320000 1474.800000 ;
+ RECT 380.220000 1479.760000 381.320000 1480.240000 ;
+ RECT 380.220000 1485.200000 381.320000 1485.680000 ;
+ RECT 380.220000 1490.640000 381.320000 1491.120000 ;
+ RECT 380.220000 1496.080000 381.320000 1496.560000 ;
+ RECT 380.220000 1452.560000 381.320000 1453.040000 ;
+ RECT 380.220000 1458.000000 381.320000 1458.480000 ;
+ RECT 380.220000 1463.440000 381.320000 1463.920000 ;
+ RECT 380.220000 1468.880000 381.320000 1469.360000 ;
+ RECT 335.220000 1528.720000 336.320000 1529.200000 ;
+ RECT 335.220000 1523.280000 336.320000 1523.760000 ;
+ RECT 335.220000 1534.160000 336.320000 1534.640000 ;
+ RECT 335.220000 1539.600000 336.320000 1540.080000 ;
+ RECT 290.220000 1523.280000 291.320000 1523.760000 ;
+ RECT 290.220000 1528.720000 291.320000 1529.200000 ;
+ RECT 290.220000 1534.160000 291.320000 1534.640000 ;
+ RECT 290.220000 1539.600000 291.320000 1540.080000 ;
+ RECT 335.220000 1501.520000 336.320000 1502.000000 ;
+ RECT 335.220000 1506.960000 336.320000 1507.440000 ;
+ RECT 335.220000 1512.400000 336.320000 1512.880000 ;
+ RECT 335.220000 1517.840000 336.320000 1518.320000 ;
+ RECT 290.220000 1501.520000 291.320000 1502.000000 ;
+ RECT 290.220000 1506.960000 291.320000 1507.440000 ;
+ RECT 290.220000 1512.400000 291.320000 1512.880000 ;
+ RECT 290.220000 1517.840000 291.320000 1518.320000 ;
+ RECT 241.390000 1539.600000 242.390000 1540.080000 ;
+ RECT 245.055000 1539.600000 246.320000 1540.080000 ;
+ RECT 241.390000 1528.720000 242.390000 1529.200000 ;
+ RECT 245.055000 1528.720000 246.320000 1529.200000 ;
+ RECT 241.390000 1534.160000 242.390000 1534.640000 ;
+ RECT 245.055000 1534.160000 246.320000 1534.640000 ;
+ RECT 241.390000 1523.280000 242.390000 1523.760000 ;
+ RECT 245.055000 1523.280000 246.320000 1523.760000 ;
+ RECT 241.390000 1517.840000 242.390000 1518.320000 ;
+ RECT 245.055000 1517.840000 246.320000 1518.320000 ;
+ RECT 241.390000 1512.400000 242.390000 1512.880000 ;
+ RECT 245.055000 1512.400000 246.320000 1512.880000 ;
+ RECT 241.390000 1506.960000 242.390000 1507.440000 ;
+ RECT 245.055000 1506.960000 246.320000 1507.440000 ;
+ RECT 241.390000 1501.520000 242.390000 1502.000000 ;
+ RECT 245.055000 1501.520000 246.320000 1502.000000 ;
+ RECT 335.220000 1474.320000 336.320000 1474.800000 ;
+ RECT 335.220000 1479.760000 336.320000 1480.240000 ;
+ RECT 335.220000 1485.200000 336.320000 1485.680000 ;
+ RECT 335.220000 1490.640000 336.320000 1491.120000 ;
+ RECT 335.220000 1496.080000 336.320000 1496.560000 ;
+ RECT 290.220000 1474.320000 291.320000 1474.800000 ;
+ RECT 290.220000 1479.760000 291.320000 1480.240000 ;
+ RECT 290.220000 1485.200000 291.320000 1485.680000 ;
+ RECT 290.220000 1490.640000 291.320000 1491.120000 ;
+ RECT 290.220000 1496.080000 291.320000 1496.560000 ;
+ RECT 335.220000 1452.560000 336.320000 1453.040000 ;
+ RECT 335.220000 1458.000000 336.320000 1458.480000 ;
+ RECT 335.220000 1463.440000 336.320000 1463.920000 ;
+ RECT 335.220000 1468.880000 336.320000 1469.360000 ;
+ RECT 290.220000 1452.560000 291.320000 1453.040000 ;
+ RECT 290.220000 1458.000000 291.320000 1458.480000 ;
+ RECT 290.220000 1463.440000 291.320000 1463.920000 ;
+ RECT 290.220000 1468.880000 291.320000 1469.360000 ;
+ RECT 241.390000 1496.080000 242.390000 1496.560000 ;
+ RECT 245.055000 1496.080000 246.320000 1496.560000 ;
+ RECT 241.390000 1485.200000 242.390000 1485.680000 ;
+ RECT 245.055000 1485.200000 246.320000 1485.680000 ;
+ RECT 241.390000 1490.640000 242.390000 1491.120000 ;
+ RECT 245.055000 1490.640000 246.320000 1491.120000 ;
+ RECT 241.390000 1479.760000 242.390000 1480.240000 ;
+ RECT 245.055000 1479.760000 246.320000 1480.240000 ;
+ RECT 241.390000 1474.320000 242.390000 1474.800000 ;
+ RECT 245.055000 1474.320000 246.320000 1474.800000 ;
+ RECT 241.390000 1468.880000 242.390000 1469.360000 ;
+ RECT 245.055000 1468.880000 246.320000 1469.360000 ;
+ RECT 241.390000 1463.440000 242.390000 1463.920000 ;
+ RECT 245.055000 1463.440000 246.320000 1463.920000 ;
+ RECT 241.390000 1458.000000 242.390000 1458.480000 ;
+ RECT 245.055000 1458.000000 246.320000 1458.480000 ;
+ RECT 241.390000 1452.560000 242.390000 1453.040000 ;
+ RECT 245.055000 1452.560000 246.320000 1453.040000 ;
+ RECT 425.220000 1436.240000 426.320000 1436.720000 ;
+ RECT 425.220000 1441.680000 426.320000 1442.160000 ;
+ RECT 438.030000 1436.240000 439.030000 1436.720000 ;
+ RECT 438.030000 1441.680000 439.030000 1442.160000 ;
+ RECT 438.030000 1425.360000 439.030000 1425.840000 ;
+ RECT 438.030000 1430.800000 439.030000 1431.280000 ;
+ RECT 425.220000 1430.800000 426.320000 1431.280000 ;
+ RECT 425.220000 1425.360000 426.320000 1425.840000 ;
+ RECT 425.220000 1414.480000 426.320000 1414.960000 ;
+ RECT 425.220000 1419.920000 426.320000 1420.400000 ;
+ RECT 438.030000 1414.480000 439.030000 1414.960000 ;
+ RECT 438.030000 1419.920000 439.030000 1420.400000 ;
+ RECT 438.030000 1403.600000 439.030000 1404.080000 ;
+ RECT 438.030000 1398.160000 439.030000 1398.640000 ;
+ RECT 438.030000 1409.040000 439.030000 1409.520000 ;
+ RECT 425.220000 1409.040000 426.320000 1409.520000 ;
+ RECT 425.220000 1403.600000 426.320000 1404.080000 ;
+ RECT 425.220000 1398.160000 426.320000 1398.640000 ;
+ RECT 380.220000 1425.360000 381.320000 1425.840000 ;
+ RECT 380.220000 1430.800000 381.320000 1431.280000 ;
+ RECT 380.220000 1436.240000 381.320000 1436.720000 ;
+ RECT 380.220000 1441.680000 381.320000 1442.160000 ;
+ RECT 380.220000 1398.160000 381.320000 1398.640000 ;
+ RECT 380.220000 1403.600000 381.320000 1404.080000 ;
+ RECT 380.220000 1409.040000 381.320000 1409.520000 ;
+ RECT 380.220000 1414.480000 381.320000 1414.960000 ;
+ RECT 380.220000 1419.920000 381.320000 1420.400000 ;
+ RECT 425.220000 1387.280000 426.320000 1387.760000 ;
+ RECT 425.220000 1392.720000 426.320000 1393.200000 ;
+ RECT 438.030000 1387.280000 439.030000 1387.760000 ;
+ RECT 438.030000 1392.720000 439.030000 1393.200000 ;
+ RECT 425.220000 1376.400000 426.320000 1376.880000 ;
+ RECT 425.220000 1381.840000 426.320000 1382.320000 ;
+ RECT 438.030000 1376.400000 439.030000 1376.880000 ;
+ RECT 438.030000 1381.840000 439.030000 1382.320000 ;
+ RECT 438.030000 1365.520000 439.030000 1366.000000 ;
+ RECT 438.030000 1360.080000 439.030000 1360.560000 ;
+ RECT 438.030000 1370.960000 439.030000 1371.440000 ;
+ RECT 425.220000 1370.960000 426.320000 1371.440000 ;
+ RECT 425.220000 1365.520000 426.320000 1366.000000 ;
+ RECT 425.220000 1360.080000 426.320000 1360.560000 ;
+ RECT 425.220000 1354.640000 426.320000 1355.120000 ;
+ RECT 438.030000 1354.640000 439.030000 1355.120000 ;
+ RECT 380.220000 1376.400000 381.320000 1376.880000 ;
+ RECT 380.220000 1381.840000 381.320000 1382.320000 ;
+ RECT 380.220000 1387.280000 381.320000 1387.760000 ;
+ RECT 380.220000 1392.720000 381.320000 1393.200000 ;
+ RECT 380.220000 1354.640000 381.320000 1355.120000 ;
+ RECT 380.220000 1360.080000 381.320000 1360.560000 ;
+ RECT 380.220000 1365.520000 381.320000 1366.000000 ;
+ RECT 380.220000 1370.960000 381.320000 1371.440000 ;
+ RECT 335.220000 1425.360000 336.320000 1425.840000 ;
+ RECT 335.220000 1430.800000 336.320000 1431.280000 ;
+ RECT 335.220000 1436.240000 336.320000 1436.720000 ;
+ RECT 335.220000 1441.680000 336.320000 1442.160000 ;
+ RECT 290.220000 1425.360000 291.320000 1425.840000 ;
+ RECT 290.220000 1430.800000 291.320000 1431.280000 ;
+ RECT 290.220000 1436.240000 291.320000 1436.720000 ;
+ RECT 290.220000 1441.680000 291.320000 1442.160000 ;
+ RECT 335.220000 1398.160000 336.320000 1398.640000 ;
+ RECT 335.220000 1403.600000 336.320000 1404.080000 ;
+ RECT 335.220000 1409.040000 336.320000 1409.520000 ;
+ RECT 335.220000 1414.480000 336.320000 1414.960000 ;
+ RECT 335.220000 1419.920000 336.320000 1420.400000 ;
+ RECT 290.220000 1398.160000 291.320000 1398.640000 ;
+ RECT 290.220000 1403.600000 291.320000 1404.080000 ;
+ RECT 290.220000 1409.040000 291.320000 1409.520000 ;
+ RECT 290.220000 1414.480000 291.320000 1414.960000 ;
+ RECT 290.220000 1419.920000 291.320000 1420.400000 ;
+ RECT 241.390000 1441.680000 242.390000 1442.160000 ;
+ RECT 245.055000 1441.680000 246.320000 1442.160000 ;
+ RECT 241.390000 1436.240000 242.390000 1436.720000 ;
+ RECT 245.055000 1436.240000 246.320000 1436.720000 ;
+ RECT 241.390000 1430.800000 242.390000 1431.280000 ;
+ RECT 245.055000 1430.800000 246.320000 1431.280000 ;
+ RECT 241.390000 1425.360000 242.390000 1425.840000 ;
+ RECT 245.055000 1425.360000 246.320000 1425.840000 ;
+ RECT 241.390000 1419.920000 242.390000 1420.400000 ;
+ RECT 245.055000 1419.920000 246.320000 1420.400000 ;
+ RECT 241.390000 1414.480000 242.390000 1414.960000 ;
+ RECT 245.055000 1414.480000 246.320000 1414.960000 ;
+ RECT 241.390000 1403.600000 242.390000 1404.080000 ;
+ RECT 245.055000 1403.600000 246.320000 1404.080000 ;
+ RECT 241.390000 1409.040000 242.390000 1409.520000 ;
+ RECT 245.055000 1409.040000 246.320000 1409.520000 ;
+ RECT 241.390000 1398.160000 242.390000 1398.640000 ;
+ RECT 245.055000 1398.160000 246.320000 1398.640000 ;
+ RECT 335.220000 1376.400000 336.320000 1376.880000 ;
+ RECT 335.220000 1381.840000 336.320000 1382.320000 ;
+ RECT 335.220000 1387.280000 336.320000 1387.760000 ;
+ RECT 335.220000 1392.720000 336.320000 1393.200000 ;
+ RECT 290.220000 1376.400000 291.320000 1376.880000 ;
+ RECT 290.220000 1381.840000 291.320000 1382.320000 ;
+ RECT 290.220000 1387.280000 291.320000 1387.760000 ;
+ RECT 290.220000 1392.720000 291.320000 1393.200000 ;
+ RECT 335.220000 1354.640000 336.320000 1355.120000 ;
+ RECT 335.220000 1360.080000 336.320000 1360.560000 ;
+ RECT 335.220000 1365.520000 336.320000 1366.000000 ;
+ RECT 335.220000 1370.960000 336.320000 1371.440000 ;
+ RECT 290.220000 1354.640000 291.320000 1355.120000 ;
+ RECT 290.220000 1360.080000 291.320000 1360.560000 ;
+ RECT 290.220000 1365.520000 291.320000 1366.000000 ;
+ RECT 290.220000 1370.960000 291.320000 1371.440000 ;
+ RECT 241.390000 1392.720000 242.390000 1393.200000 ;
+ RECT 245.055000 1392.720000 246.320000 1393.200000 ;
+ RECT 241.390000 1387.280000 242.390000 1387.760000 ;
+ RECT 245.055000 1387.280000 246.320000 1387.760000 ;
+ RECT 241.390000 1381.840000 242.390000 1382.320000 ;
+ RECT 245.055000 1381.840000 246.320000 1382.320000 ;
+ RECT 241.390000 1376.400000 242.390000 1376.880000 ;
+ RECT 245.055000 1376.400000 246.320000 1376.880000 ;
+ RECT 241.390000 1370.960000 242.390000 1371.440000 ;
+ RECT 245.055000 1370.960000 246.320000 1371.440000 ;
+ RECT 241.390000 1360.080000 242.390000 1360.560000 ;
+ RECT 245.055000 1360.080000 246.320000 1360.560000 ;
+ RECT 241.390000 1365.520000 242.390000 1366.000000 ;
+ RECT 245.055000 1365.520000 246.320000 1366.000000 ;
+ RECT 241.390000 1354.640000 242.390000 1355.120000 ;
+ RECT 245.055000 1354.640000 246.320000 1355.120000 ;
+ RECT 380.220000 1447.120000 381.320000 1447.600000 ;
+ RECT 425.220000 1447.120000 426.320000 1447.600000 ;
+ RECT 438.030000 1447.120000 439.030000 1447.600000 ;
+ RECT 290.220000 1447.120000 291.320000 1447.600000 ;
+ RECT 335.220000 1447.120000 336.320000 1447.600000 ;
+ RECT 241.390000 1447.120000 242.390000 1447.600000 ;
+ RECT 245.055000 1447.120000 246.320000 1447.600000 ;
+ RECT 240.160000 1543.880000 440.260000 1544.880000 ;
+ RECT 240.160000 1348.310000 440.260000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 1347.060000 242.390000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 1546.320000 242.390000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 1347.060000 439.030000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 1546.320000 439.030000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1348.310000 241.160000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1348.310000 440.260000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1543.880000 241.160000 1544.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1543.880000 440.260000 1544.880000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 1339.340000 246.320000 1339.820000 ;
+ RECT 245.055000 1328.460000 246.320000 1328.940000 ;
+ RECT 245.055000 1333.900000 246.320000 1334.380000 ;
+ RECT 245.055000 1323.020000 246.320000 1323.500000 ;
+ RECT 245.055000 1317.580000 246.320000 1318.060000 ;
+ RECT 245.055000 1312.140000 246.320000 1312.620000 ;
+ RECT 245.055000 1306.700000 246.320000 1307.180000 ;
+ RECT 245.055000 1301.260000 246.320000 1301.740000 ;
+ RECT 245.055000 1295.820000 246.320000 1296.300000 ;
+ RECT 245.055000 1284.940000 246.320000 1285.420000 ;
+ RECT 245.055000 1290.380000 246.320000 1290.860000 ;
+ RECT 245.055000 1279.500000 246.320000 1279.980000 ;
+ RECT 245.055000 1274.060000 246.320000 1274.540000 ;
+ RECT 245.055000 1268.620000 246.320000 1269.100000 ;
+ RECT 245.055000 1263.180000 246.320000 1263.660000 ;
+ RECT 245.055000 1257.740000 246.320000 1258.220000 ;
+ RECT 245.055000 1252.300000 246.320000 1252.780000 ;
+ RECT 245.055000 1241.420000 246.320000 1241.900000 ;
+ RECT 245.055000 1235.980000 246.320000 1236.460000 ;
+ RECT 245.055000 1230.540000 246.320000 1231.020000 ;
+ RECT 245.055000 1225.100000 246.320000 1225.580000 ;
+ RECT 245.055000 1219.660000 246.320000 1220.140000 ;
+ RECT 245.055000 1214.220000 246.320000 1214.700000 ;
+ RECT 245.055000 1203.340000 246.320000 1203.820000 ;
+ RECT 245.055000 1208.780000 246.320000 1209.260000 ;
+ RECT 245.055000 1197.900000 246.320000 1198.380000 ;
+ RECT 245.055000 1192.460000 246.320000 1192.940000 ;
+ RECT 245.055000 1187.020000 246.320000 1187.500000 ;
+ RECT 245.055000 1181.580000 246.320000 1182.060000 ;
+ RECT 245.055000 1176.140000 246.320000 1176.620000 ;
+ RECT 245.055000 1170.700000 246.320000 1171.180000 ;
+ RECT 245.055000 1159.820000 246.320000 1160.300000 ;
+ RECT 245.055000 1165.260000 246.320000 1165.740000 ;
+ RECT 245.055000 1154.380000 246.320000 1154.860000 ;
+ RECT 245.055000 1246.860000 246.320000 1247.340000 ;
+ RECT 425.220000 1148.050000 426.320000 1344.620000 ;
+ RECT 380.220000 1148.050000 381.320000 1344.620000 ;
+ RECT 438.030000 1146.800000 439.030000 1347.060000 ;
+ RECT 335.220000 1148.050000 336.320000 1344.620000 ;
+ RECT 290.220000 1148.050000 291.320000 1344.620000 ;
+ RECT 245.220000 1148.050000 246.320000 1344.620000 ;
+ RECT 241.390000 1146.800000 242.390000 1347.060000 ;
+ LAYER met3 ;
+ RECT 425.220000 1339.340000 426.320000 1339.820000 ;
+ RECT 438.030000 1339.340000 439.030000 1339.820000 ;
+ RECT 438.030000 1328.460000 439.030000 1328.940000 ;
+ RECT 438.030000 1323.020000 439.030000 1323.500000 ;
+ RECT 438.030000 1333.900000 439.030000 1334.380000 ;
+ RECT 425.220000 1333.900000 426.320000 1334.380000 ;
+ RECT 425.220000 1328.460000 426.320000 1328.940000 ;
+ RECT 425.220000 1323.020000 426.320000 1323.500000 ;
+ RECT 425.220000 1312.140000 426.320000 1312.620000 ;
+ RECT 425.220000 1317.580000 426.320000 1318.060000 ;
+ RECT 438.030000 1312.140000 439.030000 1312.620000 ;
+ RECT 438.030000 1317.580000 439.030000 1318.060000 ;
+ RECT 425.220000 1301.260000 426.320000 1301.740000 ;
+ RECT 425.220000 1306.700000 426.320000 1307.180000 ;
+ RECT 438.030000 1301.260000 439.030000 1301.740000 ;
+ RECT 438.030000 1306.700000 439.030000 1307.180000 ;
+ RECT 380.220000 1323.020000 381.320000 1323.500000 ;
+ RECT 380.220000 1328.460000 381.320000 1328.940000 ;
+ RECT 380.220000 1333.900000 381.320000 1334.380000 ;
+ RECT 380.220000 1339.340000 381.320000 1339.820000 ;
+ RECT 380.220000 1306.700000 381.320000 1307.180000 ;
+ RECT 380.220000 1301.260000 381.320000 1301.740000 ;
+ RECT 380.220000 1312.140000 381.320000 1312.620000 ;
+ RECT 380.220000 1317.580000 381.320000 1318.060000 ;
+ RECT 438.030000 1290.380000 439.030000 1290.860000 ;
+ RECT 438.030000 1284.940000 439.030000 1285.420000 ;
+ RECT 438.030000 1295.820000 439.030000 1296.300000 ;
+ RECT 425.220000 1295.820000 426.320000 1296.300000 ;
+ RECT 425.220000 1290.380000 426.320000 1290.860000 ;
+ RECT 425.220000 1284.940000 426.320000 1285.420000 ;
+ RECT 425.220000 1274.060000 426.320000 1274.540000 ;
+ RECT 425.220000 1279.500000 426.320000 1279.980000 ;
+ RECT 438.030000 1274.060000 439.030000 1274.540000 ;
+ RECT 438.030000 1279.500000 439.030000 1279.980000 ;
+ RECT 438.030000 1263.180000 439.030000 1263.660000 ;
+ RECT 438.030000 1268.620000 439.030000 1269.100000 ;
+ RECT 425.220000 1268.620000 426.320000 1269.100000 ;
+ RECT 425.220000 1263.180000 426.320000 1263.660000 ;
+ RECT 425.220000 1252.300000 426.320000 1252.780000 ;
+ RECT 425.220000 1257.740000 426.320000 1258.220000 ;
+ RECT 438.030000 1252.300000 439.030000 1252.780000 ;
+ RECT 438.030000 1257.740000 439.030000 1258.220000 ;
+ RECT 380.220000 1274.060000 381.320000 1274.540000 ;
+ RECT 380.220000 1279.500000 381.320000 1279.980000 ;
+ RECT 380.220000 1284.940000 381.320000 1285.420000 ;
+ RECT 380.220000 1290.380000 381.320000 1290.860000 ;
+ RECT 380.220000 1295.820000 381.320000 1296.300000 ;
+ RECT 380.220000 1252.300000 381.320000 1252.780000 ;
+ RECT 380.220000 1257.740000 381.320000 1258.220000 ;
+ RECT 380.220000 1263.180000 381.320000 1263.660000 ;
+ RECT 380.220000 1268.620000 381.320000 1269.100000 ;
+ RECT 335.220000 1328.460000 336.320000 1328.940000 ;
+ RECT 335.220000 1323.020000 336.320000 1323.500000 ;
+ RECT 335.220000 1333.900000 336.320000 1334.380000 ;
+ RECT 335.220000 1339.340000 336.320000 1339.820000 ;
+ RECT 290.220000 1323.020000 291.320000 1323.500000 ;
+ RECT 290.220000 1328.460000 291.320000 1328.940000 ;
+ RECT 290.220000 1333.900000 291.320000 1334.380000 ;
+ RECT 290.220000 1339.340000 291.320000 1339.820000 ;
+ RECT 335.220000 1301.260000 336.320000 1301.740000 ;
+ RECT 335.220000 1306.700000 336.320000 1307.180000 ;
+ RECT 335.220000 1312.140000 336.320000 1312.620000 ;
+ RECT 335.220000 1317.580000 336.320000 1318.060000 ;
+ RECT 290.220000 1301.260000 291.320000 1301.740000 ;
+ RECT 290.220000 1306.700000 291.320000 1307.180000 ;
+ RECT 290.220000 1312.140000 291.320000 1312.620000 ;
+ RECT 290.220000 1317.580000 291.320000 1318.060000 ;
+ RECT 241.390000 1339.340000 242.390000 1339.820000 ;
+ RECT 245.055000 1339.340000 246.320000 1339.820000 ;
+ RECT 241.390000 1328.460000 242.390000 1328.940000 ;
+ RECT 245.055000 1328.460000 246.320000 1328.940000 ;
+ RECT 241.390000 1333.900000 242.390000 1334.380000 ;
+ RECT 245.055000 1333.900000 246.320000 1334.380000 ;
+ RECT 241.390000 1323.020000 242.390000 1323.500000 ;
+ RECT 245.055000 1323.020000 246.320000 1323.500000 ;
+ RECT 241.390000 1317.580000 242.390000 1318.060000 ;
+ RECT 245.055000 1317.580000 246.320000 1318.060000 ;
+ RECT 241.390000 1312.140000 242.390000 1312.620000 ;
+ RECT 245.055000 1312.140000 246.320000 1312.620000 ;
+ RECT 241.390000 1306.700000 242.390000 1307.180000 ;
+ RECT 245.055000 1306.700000 246.320000 1307.180000 ;
+ RECT 241.390000 1301.260000 242.390000 1301.740000 ;
+ RECT 245.055000 1301.260000 246.320000 1301.740000 ;
+ RECT 335.220000 1274.060000 336.320000 1274.540000 ;
+ RECT 335.220000 1279.500000 336.320000 1279.980000 ;
+ RECT 335.220000 1284.940000 336.320000 1285.420000 ;
+ RECT 335.220000 1290.380000 336.320000 1290.860000 ;
+ RECT 335.220000 1295.820000 336.320000 1296.300000 ;
+ RECT 290.220000 1274.060000 291.320000 1274.540000 ;
+ RECT 290.220000 1279.500000 291.320000 1279.980000 ;
+ RECT 290.220000 1284.940000 291.320000 1285.420000 ;
+ RECT 290.220000 1290.380000 291.320000 1290.860000 ;
+ RECT 290.220000 1295.820000 291.320000 1296.300000 ;
+ RECT 335.220000 1252.300000 336.320000 1252.780000 ;
+ RECT 335.220000 1257.740000 336.320000 1258.220000 ;
+ RECT 335.220000 1263.180000 336.320000 1263.660000 ;
+ RECT 335.220000 1268.620000 336.320000 1269.100000 ;
+ RECT 290.220000 1252.300000 291.320000 1252.780000 ;
+ RECT 290.220000 1257.740000 291.320000 1258.220000 ;
+ RECT 290.220000 1263.180000 291.320000 1263.660000 ;
+ RECT 290.220000 1268.620000 291.320000 1269.100000 ;
+ RECT 241.390000 1295.820000 242.390000 1296.300000 ;
+ RECT 245.055000 1295.820000 246.320000 1296.300000 ;
+ RECT 241.390000 1284.940000 242.390000 1285.420000 ;
+ RECT 245.055000 1284.940000 246.320000 1285.420000 ;
+ RECT 241.390000 1290.380000 242.390000 1290.860000 ;
+ RECT 245.055000 1290.380000 246.320000 1290.860000 ;
+ RECT 241.390000 1279.500000 242.390000 1279.980000 ;
+ RECT 245.055000 1279.500000 246.320000 1279.980000 ;
+ RECT 241.390000 1274.060000 242.390000 1274.540000 ;
+ RECT 245.055000 1274.060000 246.320000 1274.540000 ;
+ RECT 241.390000 1268.620000 242.390000 1269.100000 ;
+ RECT 245.055000 1268.620000 246.320000 1269.100000 ;
+ RECT 241.390000 1263.180000 242.390000 1263.660000 ;
+ RECT 245.055000 1263.180000 246.320000 1263.660000 ;
+ RECT 241.390000 1257.740000 242.390000 1258.220000 ;
+ RECT 245.055000 1257.740000 246.320000 1258.220000 ;
+ RECT 241.390000 1252.300000 242.390000 1252.780000 ;
+ RECT 245.055000 1252.300000 246.320000 1252.780000 ;
+ RECT 425.220000 1235.980000 426.320000 1236.460000 ;
+ RECT 425.220000 1241.420000 426.320000 1241.900000 ;
+ RECT 438.030000 1235.980000 439.030000 1236.460000 ;
+ RECT 438.030000 1241.420000 439.030000 1241.900000 ;
+ RECT 438.030000 1225.100000 439.030000 1225.580000 ;
+ RECT 438.030000 1230.540000 439.030000 1231.020000 ;
+ RECT 425.220000 1230.540000 426.320000 1231.020000 ;
+ RECT 425.220000 1225.100000 426.320000 1225.580000 ;
+ RECT 425.220000 1214.220000 426.320000 1214.700000 ;
+ RECT 425.220000 1219.660000 426.320000 1220.140000 ;
+ RECT 438.030000 1214.220000 439.030000 1214.700000 ;
+ RECT 438.030000 1219.660000 439.030000 1220.140000 ;
+ RECT 438.030000 1203.340000 439.030000 1203.820000 ;
+ RECT 438.030000 1197.900000 439.030000 1198.380000 ;
+ RECT 438.030000 1208.780000 439.030000 1209.260000 ;
+ RECT 425.220000 1208.780000 426.320000 1209.260000 ;
+ RECT 425.220000 1203.340000 426.320000 1203.820000 ;
+ RECT 425.220000 1197.900000 426.320000 1198.380000 ;
+ RECT 380.220000 1225.100000 381.320000 1225.580000 ;
+ RECT 380.220000 1230.540000 381.320000 1231.020000 ;
+ RECT 380.220000 1235.980000 381.320000 1236.460000 ;
+ RECT 380.220000 1241.420000 381.320000 1241.900000 ;
+ RECT 380.220000 1197.900000 381.320000 1198.380000 ;
+ RECT 380.220000 1203.340000 381.320000 1203.820000 ;
+ RECT 380.220000 1208.780000 381.320000 1209.260000 ;
+ RECT 380.220000 1214.220000 381.320000 1214.700000 ;
+ RECT 380.220000 1219.660000 381.320000 1220.140000 ;
+ RECT 425.220000 1187.020000 426.320000 1187.500000 ;
+ RECT 425.220000 1192.460000 426.320000 1192.940000 ;
+ RECT 438.030000 1187.020000 439.030000 1187.500000 ;
+ RECT 438.030000 1192.460000 439.030000 1192.940000 ;
+ RECT 425.220000 1176.140000 426.320000 1176.620000 ;
+ RECT 425.220000 1181.580000 426.320000 1182.060000 ;
+ RECT 438.030000 1176.140000 439.030000 1176.620000 ;
+ RECT 438.030000 1181.580000 439.030000 1182.060000 ;
+ RECT 438.030000 1165.260000 439.030000 1165.740000 ;
+ RECT 438.030000 1159.820000 439.030000 1160.300000 ;
+ RECT 438.030000 1170.700000 439.030000 1171.180000 ;
+ RECT 425.220000 1170.700000 426.320000 1171.180000 ;
+ RECT 425.220000 1165.260000 426.320000 1165.740000 ;
+ RECT 425.220000 1159.820000 426.320000 1160.300000 ;
+ RECT 425.220000 1154.380000 426.320000 1154.860000 ;
+ RECT 438.030000 1154.380000 439.030000 1154.860000 ;
+ RECT 380.220000 1176.140000 381.320000 1176.620000 ;
+ RECT 380.220000 1181.580000 381.320000 1182.060000 ;
+ RECT 380.220000 1187.020000 381.320000 1187.500000 ;
+ RECT 380.220000 1192.460000 381.320000 1192.940000 ;
+ RECT 380.220000 1154.380000 381.320000 1154.860000 ;
+ RECT 380.220000 1159.820000 381.320000 1160.300000 ;
+ RECT 380.220000 1165.260000 381.320000 1165.740000 ;
+ RECT 380.220000 1170.700000 381.320000 1171.180000 ;
+ RECT 335.220000 1225.100000 336.320000 1225.580000 ;
+ RECT 335.220000 1230.540000 336.320000 1231.020000 ;
+ RECT 335.220000 1235.980000 336.320000 1236.460000 ;
+ RECT 335.220000 1241.420000 336.320000 1241.900000 ;
+ RECT 290.220000 1225.100000 291.320000 1225.580000 ;
+ RECT 290.220000 1230.540000 291.320000 1231.020000 ;
+ RECT 290.220000 1235.980000 291.320000 1236.460000 ;
+ RECT 290.220000 1241.420000 291.320000 1241.900000 ;
+ RECT 335.220000 1197.900000 336.320000 1198.380000 ;
+ RECT 335.220000 1203.340000 336.320000 1203.820000 ;
+ RECT 335.220000 1208.780000 336.320000 1209.260000 ;
+ RECT 335.220000 1214.220000 336.320000 1214.700000 ;
+ RECT 335.220000 1219.660000 336.320000 1220.140000 ;
+ RECT 290.220000 1197.900000 291.320000 1198.380000 ;
+ RECT 290.220000 1203.340000 291.320000 1203.820000 ;
+ RECT 290.220000 1208.780000 291.320000 1209.260000 ;
+ RECT 290.220000 1214.220000 291.320000 1214.700000 ;
+ RECT 290.220000 1219.660000 291.320000 1220.140000 ;
+ RECT 241.390000 1241.420000 242.390000 1241.900000 ;
+ RECT 245.055000 1241.420000 246.320000 1241.900000 ;
+ RECT 241.390000 1235.980000 242.390000 1236.460000 ;
+ RECT 245.055000 1235.980000 246.320000 1236.460000 ;
+ RECT 241.390000 1230.540000 242.390000 1231.020000 ;
+ RECT 245.055000 1230.540000 246.320000 1231.020000 ;
+ RECT 241.390000 1225.100000 242.390000 1225.580000 ;
+ RECT 245.055000 1225.100000 246.320000 1225.580000 ;
+ RECT 241.390000 1219.660000 242.390000 1220.140000 ;
+ RECT 245.055000 1219.660000 246.320000 1220.140000 ;
+ RECT 241.390000 1214.220000 242.390000 1214.700000 ;
+ RECT 245.055000 1214.220000 246.320000 1214.700000 ;
+ RECT 241.390000 1203.340000 242.390000 1203.820000 ;
+ RECT 245.055000 1203.340000 246.320000 1203.820000 ;
+ RECT 241.390000 1208.780000 242.390000 1209.260000 ;
+ RECT 245.055000 1208.780000 246.320000 1209.260000 ;
+ RECT 241.390000 1197.900000 242.390000 1198.380000 ;
+ RECT 245.055000 1197.900000 246.320000 1198.380000 ;
+ RECT 335.220000 1176.140000 336.320000 1176.620000 ;
+ RECT 335.220000 1181.580000 336.320000 1182.060000 ;
+ RECT 335.220000 1187.020000 336.320000 1187.500000 ;
+ RECT 335.220000 1192.460000 336.320000 1192.940000 ;
+ RECT 290.220000 1176.140000 291.320000 1176.620000 ;
+ RECT 290.220000 1181.580000 291.320000 1182.060000 ;
+ RECT 290.220000 1187.020000 291.320000 1187.500000 ;
+ RECT 290.220000 1192.460000 291.320000 1192.940000 ;
+ RECT 335.220000 1154.380000 336.320000 1154.860000 ;
+ RECT 335.220000 1159.820000 336.320000 1160.300000 ;
+ RECT 335.220000 1165.260000 336.320000 1165.740000 ;
+ RECT 335.220000 1170.700000 336.320000 1171.180000 ;
+ RECT 290.220000 1154.380000 291.320000 1154.860000 ;
+ RECT 290.220000 1159.820000 291.320000 1160.300000 ;
+ RECT 290.220000 1165.260000 291.320000 1165.740000 ;
+ RECT 290.220000 1170.700000 291.320000 1171.180000 ;
+ RECT 241.390000 1192.460000 242.390000 1192.940000 ;
+ RECT 245.055000 1192.460000 246.320000 1192.940000 ;
+ RECT 241.390000 1187.020000 242.390000 1187.500000 ;
+ RECT 245.055000 1187.020000 246.320000 1187.500000 ;
+ RECT 241.390000 1181.580000 242.390000 1182.060000 ;
+ RECT 245.055000 1181.580000 246.320000 1182.060000 ;
+ RECT 241.390000 1176.140000 242.390000 1176.620000 ;
+ RECT 245.055000 1176.140000 246.320000 1176.620000 ;
+ RECT 241.390000 1170.700000 242.390000 1171.180000 ;
+ RECT 245.055000 1170.700000 246.320000 1171.180000 ;
+ RECT 241.390000 1159.820000 242.390000 1160.300000 ;
+ RECT 245.055000 1159.820000 246.320000 1160.300000 ;
+ RECT 241.390000 1165.260000 242.390000 1165.740000 ;
+ RECT 245.055000 1165.260000 246.320000 1165.740000 ;
+ RECT 241.390000 1154.380000 242.390000 1154.860000 ;
+ RECT 245.055000 1154.380000 246.320000 1154.860000 ;
+ RECT 380.220000 1246.860000 381.320000 1247.340000 ;
+ RECT 425.220000 1246.860000 426.320000 1247.340000 ;
+ RECT 438.030000 1246.860000 439.030000 1247.340000 ;
+ RECT 290.220000 1246.860000 291.320000 1247.340000 ;
+ RECT 335.220000 1246.860000 336.320000 1247.340000 ;
+ RECT 241.390000 1246.860000 242.390000 1247.340000 ;
+ RECT 245.055000 1246.860000 246.320000 1247.340000 ;
+ RECT 240.160000 1343.620000 440.260000 1344.620000 ;
+ RECT 240.160000 1148.050000 440.260000 1149.050000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 1146.800000 242.390000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 1346.060000 242.390000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 1146.800000 439.030000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 1346.060000 439.030000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1148.050000 241.160000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1148.050000 440.260000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1343.620000 241.160000 1344.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1343.620000 440.260000 1344.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 1139.080000 246.320000 1139.560000 ;
+ RECT 245.055000 1128.200000 246.320000 1128.680000 ;
+ RECT 245.055000 1133.640000 246.320000 1134.120000 ;
+ RECT 245.055000 1122.760000 246.320000 1123.240000 ;
+ RECT 245.055000 1117.320000 246.320000 1117.800000 ;
+ RECT 245.055000 1111.880000 246.320000 1112.360000 ;
+ RECT 245.055000 1106.440000 246.320000 1106.920000 ;
+ RECT 245.055000 1101.000000 246.320000 1101.480000 ;
+ RECT 245.055000 1095.560000 246.320000 1096.040000 ;
+ RECT 245.055000 1084.680000 246.320000 1085.160000 ;
+ RECT 245.055000 1090.120000 246.320000 1090.600000 ;
+ RECT 245.055000 1079.240000 246.320000 1079.720000 ;
+ RECT 245.055000 1073.800000 246.320000 1074.280000 ;
+ RECT 245.055000 1068.360000 246.320000 1068.840000 ;
+ RECT 245.055000 1062.920000 246.320000 1063.400000 ;
+ RECT 245.055000 1057.480000 246.320000 1057.960000 ;
+ RECT 245.055000 1052.040000 246.320000 1052.520000 ;
+ RECT 245.055000 1041.160000 246.320000 1041.640000 ;
+ RECT 245.055000 1035.720000 246.320000 1036.200000 ;
+ RECT 245.055000 1030.280000 246.320000 1030.760000 ;
+ RECT 245.055000 1024.840000 246.320000 1025.320000 ;
+ RECT 245.055000 1019.400000 246.320000 1019.880000 ;
+ RECT 245.055000 1013.960000 246.320000 1014.440000 ;
+ RECT 245.055000 1003.080000 246.320000 1003.560000 ;
+ RECT 245.055000 1008.520000 246.320000 1009.000000 ;
+ RECT 245.055000 997.640000 246.320000 998.120000 ;
+ RECT 245.055000 992.200000 246.320000 992.680000 ;
+ RECT 245.055000 986.760000 246.320000 987.240000 ;
+ RECT 245.055000 981.320000 246.320000 981.800000 ;
+ RECT 245.055000 975.880000 246.320000 976.360000 ;
+ RECT 245.055000 970.440000 246.320000 970.920000 ;
+ RECT 245.055000 959.560000 246.320000 960.040000 ;
+ RECT 245.055000 965.000000 246.320000 965.480000 ;
+ RECT 245.055000 954.120000 246.320000 954.600000 ;
+ RECT 245.055000 1046.600000 246.320000 1047.080000 ;
+ RECT 425.220000 947.790000 426.320000 1144.360000 ;
+ RECT 380.220000 947.790000 381.320000 1144.360000 ;
+ RECT 438.030000 946.540000 439.030000 1146.800000 ;
+ RECT 335.220000 947.790000 336.320000 1144.360000 ;
+ RECT 290.220000 947.790000 291.320000 1144.360000 ;
+ RECT 245.220000 947.790000 246.320000 1144.360000 ;
+ RECT 241.390000 946.540000 242.390000 1146.800000 ;
+ LAYER met3 ;
+ RECT 425.220000 1139.080000 426.320000 1139.560000 ;
+ RECT 438.030000 1139.080000 439.030000 1139.560000 ;
+ RECT 438.030000 1128.200000 439.030000 1128.680000 ;
+ RECT 438.030000 1122.760000 439.030000 1123.240000 ;
+ RECT 438.030000 1133.640000 439.030000 1134.120000 ;
+ RECT 425.220000 1133.640000 426.320000 1134.120000 ;
+ RECT 425.220000 1128.200000 426.320000 1128.680000 ;
+ RECT 425.220000 1122.760000 426.320000 1123.240000 ;
+ RECT 425.220000 1111.880000 426.320000 1112.360000 ;
+ RECT 425.220000 1117.320000 426.320000 1117.800000 ;
+ RECT 438.030000 1111.880000 439.030000 1112.360000 ;
+ RECT 438.030000 1117.320000 439.030000 1117.800000 ;
+ RECT 425.220000 1101.000000 426.320000 1101.480000 ;
+ RECT 425.220000 1106.440000 426.320000 1106.920000 ;
+ RECT 438.030000 1101.000000 439.030000 1101.480000 ;
+ RECT 438.030000 1106.440000 439.030000 1106.920000 ;
+ RECT 380.220000 1122.760000 381.320000 1123.240000 ;
+ RECT 380.220000 1128.200000 381.320000 1128.680000 ;
+ RECT 380.220000 1133.640000 381.320000 1134.120000 ;
+ RECT 380.220000 1139.080000 381.320000 1139.560000 ;
+ RECT 380.220000 1106.440000 381.320000 1106.920000 ;
+ RECT 380.220000 1101.000000 381.320000 1101.480000 ;
+ RECT 380.220000 1111.880000 381.320000 1112.360000 ;
+ RECT 380.220000 1117.320000 381.320000 1117.800000 ;
+ RECT 438.030000 1090.120000 439.030000 1090.600000 ;
+ RECT 438.030000 1084.680000 439.030000 1085.160000 ;
+ RECT 438.030000 1095.560000 439.030000 1096.040000 ;
+ RECT 425.220000 1095.560000 426.320000 1096.040000 ;
+ RECT 425.220000 1090.120000 426.320000 1090.600000 ;
+ RECT 425.220000 1084.680000 426.320000 1085.160000 ;
+ RECT 425.220000 1073.800000 426.320000 1074.280000 ;
+ RECT 425.220000 1079.240000 426.320000 1079.720000 ;
+ RECT 438.030000 1073.800000 439.030000 1074.280000 ;
+ RECT 438.030000 1079.240000 439.030000 1079.720000 ;
+ RECT 438.030000 1062.920000 439.030000 1063.400000 ;
+ RECT 438.030000 1068.360000 439.030000 1068.840000 ;
+ RECT 425.220000 1068.360000 426.320000 1068.840000 ;
+ RECT 425.220000 1062.920000 426.320000 1063.400000 ;
+ RECT 425.220000 1052.040000 426.320000 1052.520000 ;
+ RECT 425.220000 1057.480000 426.320000 1057.960000 ;
+ RECT 438.030000 1052.040000 439.030000 1052.520000 ;
+ RECT 438.030000 1057.480000 439.030000 1057.960000 ;
+ RECT 380.220000 1073.800000 381.320000 1074.280000 ;
+ RECT 380.220000 1079.240000 381.320000 1079.720000 ;
+ RECT 380.220000 1084.680000 381.320000 1085.160000 ;
+ RECT 380.220000 1090.120000 381.320000 1090.600000 ;
+ RECT 380.220000 1095.560000 381.320000 1096.040000 ;
+ RECT 380.220000 1052.040000 381.320000 1052.520000 ;
+ RECT 380.220000 1057.480000 381.320000 1057.960000 ;
+ RECT 380.220000 1062.920000 381.320000 1063.400000 ;
+ RECT 380.220000 1068.360000 381.320000 1068.840000 ;
+ RECT 335.220000 1128.200000 336.320000 1128.680000 ;
+ RECT 335.220000 1122.760000 336.320000 1123.240000 ;
+ RECT 335.220000 1133.640000 336.320000 1134.120000 ;
+ RECT 335.220000 1139.080000 336.320000 1139.560000 ;
+ RECT 290.220000 1122.760000 291.320000 1123.240000 ;
+ RECT 290.220000 1128.200000 291.320000 1128.680000 ;
+ RECT 290.220000 1133.640000 291.320000 1134.120000 ;
+ RECT 290.220000 1139.080000 291.320000 1139.560000 ;
+ RECT 335.220000 1101.000000 336.320000 1101.480000 ;
+ RECT 335.220000 1106.440000 336.320000 1106.920000 ;
+ RECT 335.220000 1111.880000 336.320000 1112.360000 ;
+ RECT 335.220000 1117.320000 336.320000 1117.800000 ;
+ RECT 290.220000 1101.000000 291.320000 1101.480000 ;
+ RECT 290.220000 1106.440000 291.320000 1106.920000 ;
+ RECT 290.220000 1111.880000 291.320000 1112.360000 ;
+ RECT 290.220000 1117.320000 291.320000 1117.800000 ;
+ RECT 241.390000 1139.080000 242.390000 1139.560000 ;
+ RECT 245.055000 1139.080000 246.320000 1139.560000 ;
+ RECT 241.390000 1128.200000 242.390000 1128.680000 ;
+ RECT 245.055000 1128.200000 246.320000 1128.680000 ;
+ RECT 241.390000 1133.640000 242.390000 1134.120000 ;
+ RECT 245.055000 1133.640000 246.320000 1134.120000 ;
+ RECT 241.390000 1122.760000 242.390000 1123.240000 ;
+ RECT 245.055000 1122.760000 246.320000 1123.240000 ;
+ RECT 241.390000 1117.320000 242.390000 1117.800000 ;
+ RECT 245.055000 1117.320000 246.320000 1117.800000 ;
+ RECT 241.390000 1111.880000 242.390000 1112.360000 ;
+ RECT 245.055000 1111.880000 246.320000 1112.360000 ;
+ RECT 241.390000 1106.440000 242.390000 1106.920000 ;
+ RECT 245.055000 1106.440000 246.320000 1106.920000 ;
+ RECT 241.390000 1101.000000 242.390000 1101.480000 ;
+ RECT 245.055000 1101.000000 246.320000 1101.480000 ;
+ RECT 335.220000 1073.800000 336.320000 1074.280000 ;
+ RECT 335.220000 1079.240000 336.320000 1079.720000 ;
+ RECT 335.220000 1084.680000 336.320000 1085.160000 ;
+ RECT 335.220000 1090.120000 336.320000 1090.600000 ;
+ RECT 335.220000 1095.560000 336.320000 1096.040000 ;
+ RECT 290.220000 1073.800000 291.320000 1074.280000 ;
+ RECT 290.220000 1079.240000 291.320000 1079.720000 ;
+ RECT 290.220000 1084.680000 291.320000 1085.160000 ;
+ RECT 290.220000 1090.120000 291.320000 1090.600000 ;
+ RECT 290.220000 1095.560000 291.320000 1096.040000 ;
+ RECT 335.220000 1052.040000 336.320000 1052.520000 ;
+ RECT 335.220000 1057.480000 336.320000 1057.960000 ;
+ RECT 335.220000 1062.920000 336.320000 1063.400000 ;
+ RECT 335.220000 1068.360000 336.320000 1068.840000 ;
+ RECT 290.220000 1052.040000 291.320000 1052.520000 ;
+ RECT 290.220000 1057.480000 291.320000 1057.960000 ;
+ RECT 290.220000 1062.920000 291.320000 1063.400000 ;
+ RECT 290.220000 1068.360000 291.320000 1068.840000 ;
+ RECT 241.390000 1095.560000 242.390000 1096.040000 ;
+ RECT 245.055000 1095.560000 246.320000 1096.040000 ;
+ RECT 241.390000 1084.680000 242.390000 1085.160000 ;
+ RECT 245.055000 1084.680000 246.320000 1085.160000 ;
+ RECT 241.390000 1090.120000 242.390000 1090.600000 ;
+ RECT 245.055000 1090.120000 246.320000 1090.600000 ;
+ RECT 241.390000 1079.240000 242.390000 1079.720000 ;
+ RECT 245.055000 1079.240000 246.320000 1079.720000 ;
+ RECT 241.390000 1073.800000 242.390000 1074.280000 ;
+ RECT 245.055000 1073.800000 246.320000 1074.280000 ;
+ RECT 241.390000 1068.360000 242.390000 1068.840000 ;
+ RECT 245.055000 1068.360000 246.320000 1068.840000 ;
+ RECT 241.390000 1062.920000 242.390000 1063.400000 ;
+ RECT 245.055000 1062.920000 246.320000 1063.400000 ;
+ RECT 241.390000 1057.480000 242.390000 1057.960000 ;
+ RECT 245.055000 1057.480000 246.320000 1057.960000 ;
+ RECT 241.390000 1052.040000 242.390000 1052.520000 ;
+ RECT 245.055000 1052.040000 246.320000 1052.520000 ;
+ RECT 425.220000 1035.720000 426.320000 1036.200000 ;
+ RECT 425.220000 1041.160000 426.320000 1041.640000 ;
+ RECT 438.030000 1035.720000 439.030000 1036.200000 ;
+ RECT 438.030000 1041.160000 439.030000 1041.640000 ;
+ RECT 438.030000 1024.840000 439.030000 1025.320000 ;
+ RECT 438.030000 1030.280000 439.030000 1030.760000 ;
+ RECT 425.220000 1030.280000 426.320000 1030.760000 ;
+ RECT 425.220000 1024.840000 426.320000 1025.320000 ;
+ RECT 425.220000 1013.960000 426.320000 1014.440000 ;
+ RECT 425.220000 1019.400000 426.320000 1019.880000 ;
+ RECT 438.030000 1013.960000 439.030000 1014.440000 ;
+ RECT 438.030000 1019.400000 439.030000 1019.880000 ;
+ RECT 438.030000 1003.080000 439.030000 1003.560000 ;
+ RECT 438.030000 997.640000 439.030000 998.120000 ;
+ RECT 438.030000 1008.520000 439.030000 1009.000000 ;
+ RECT 425.220000 1008.520000 426.320000 1009.000000 ;
+ RECT 425.220000 1003.080000 426.320000 1003.560000 ;
+ RECT 425.220000 997.640000 426.320000 998.120000 ;
+ RECT 380.220000 1024.840000 381.320000 1025.320000 ;
+ RECT 380.220000 1030.280000 381.320000 1030.760000 ;
+ RECT 380.220000 1035.720000 381.320000 1036.200000 ;
+ RECT 380.220000 1041.160000 381.320000 1041.640000 ;
+ RECT 380.220000 997.640000 381.320000 998.120000 ;
+ RECT 380.220000 1003.080000 381.320000 1003.560000 ;
+ RECT 380.220000 1008.520000 381.320000 1009.000000 ;
+ RECT 380.220000 1013.960000 381.320000 1014.440000 ;
+ RECT 380.220000 1019.400000 381.320000 1019.880000 ;
+ RECT 425.220000 986.760000 426.320000 987.240000 ;
+ RECT 425.220000 992.200000 426.320000 992.680000 ;
+ RECT 438.030000 986.760000 439.030000 987.240000 ;
+ RECT 438.030000 992.200000 439.030000 992.680000 ;
+ RECT 425.220000 975.880000 426.320000 976.360000 ;
+ RECT 425.220000 981.320000 426.320000 981.800000 ;
+ RECT 438.030000 975.880000 439.030000 976.360000 ;
+ RECT 438.030000 981.320000 439.030000 981.800000 ;
+ RECT 438.030000 965.000000 439.030000 965.480000 ;
+ RECT 438.030000 959.560000 439.030000 960.040000 ;
+ RECT 438.030000 970.440000 439.030000 970.920000 ;
+ RECT 425.220000 970.440000 426.320000 970.920000 ;
+ RECT 425.220000 965.000000 426.320000 965.480000 ;
+ RECT 425.220000 959.560000 426.320000 960.040000 ;
+ RECT 425.220000 954.120000 426.320000 954.600000 ;
+ RECT 438.030000 954.120000 439.030000 954.600000 ;
+ RECT 380.220000 975.880000 381.320000 976.360000 ;
+ RECT 380.220000 981.320000 381.320000 981.800000 ;
+ RECT 380.220000 986.760000 381.320000 987.240000 ;
+ RECT 380.220000 992.200000 381.320000 992.680000 ;
+ RECT 380.220000 954.120000 381.320000 954.600000 ;
+ RECT 380.220000 959.560000 381.320000 960.040000 ;
+ RECT 380.220000 965.000000 381.320000 965.480000 ;
+ RECT 380.220000 970.440000 381.320000 970.920000 ;
+ RECT 335.220000 1024.840000 336.320000 1025.320000 ;
+ RECT 335.220000 1030.280000 336.320000 1030.760000 ;
+ RECT 335.220000 1035.720000 336.320000 1036.200000 ;
+ RECT 335.220000 1041.160000 336.320000 1041.640000 ;
+ RECT 290.220000 1024.840000 291.320000 1025.320000 ;
+ RECT 290.220000 1030.280000 291.320000 1030.760000 ;
+ RECT 290.220000 1035.720000 291.320000 1036.200000 ;
+ RECT 290.220000 1041.160000 291.320000 1041.640000 ;
+ RECT 335.220000 997.640000 336.320000 998.120000 ;
+ RECT 335.220000 1003.080000 336.320000 1003.560000 ;
+ RECT 335.220000 1008.520000 336.320000 1009.000000 ;
+ RECT 335.220000 1013.960000 336.320000 1014.440000 ;
+ RECT 335.220000 1019.400000 336.320000 1019.880000 ;
+ RECT 290.220000 997.640000 291.320000 998.120000 ;
+ RECT 290.220000 1003.080000 291.320000 1003.560000 ;
+ RECT 290.220000 1008.520000 291.320000 1009.000000 ;
+ RECT 290.220000 1013.960000 291.320000 1014.440000 ;
+ RECT 290.220000 1019.400000 291.320000 1019.880000 ;
+ RECT 241.390000 1041.160000 242.390000 1041.640000 ;
+ RECT 245.055000 1041.160000 246.320000 1041.640000 ;
+ RECT 241.390000 1035.720000 242.390000 1036.200000 ;
+ RECT 245.055000 1035.720000 246.320000 1036.200000 ;
+ RECT 241.390000 1030.280000 242.390000 1030.760000 ;
+ RECT 245.055000 1030.280000 246.320000 1030.760000 ;
+ RECT 241.390000 1024.840000 242.390000 1025.320000 ;
+ RECT 245.055000 1024.840000 246.320000 1025.320000 ;
+ RECT 241.390000 1019.400000 242.390000 1019.880000 ;
+ RECT 245.055000 1019.400000 246.320000 1019.880000 ;
+ RECT 241.390000 1013.960000 242.390000 1014.440000 ;
+ RECT 245.055000 1013.960000 246.320000 1014.440000 ;
+ RECT 241.390000 1003.080000 242.390000 1003.560000 ;
+ RECT 245.055000 1003.080000 246.320000 1003.560000 ;
+ RECT 241.390000 1008.520000 242.390000 1009.000000 ;
+ RECT 245.055000 1008.520000 246.320000 1009.000000 ;
+ RECT 241.390000 997.640000 242.390000 998.120000 ;
+ RECT 245.055000 997.640000 246.320000 998.120000 ;
+ RECT 335.220000 975.880000 336.320000 976.360000 ;
+ RECT 335.220000 981.320000 336.320000 981.800000 ;
+ RECT 335.220000 986.760000 336.320000 987.240000 ;
+ RECT 335.220000 992.200000 336.320000 992.680000 ;
+ RECT 290.220000 975.880000 291.320000 976.360000 ;
+ RECT 290.220000 981.320000 291.320000 981.800000 ;
+ RECT 290.220000 986.760000 291.320000 987.240000 ;
+ RECT 290.220000 992.200000 291.320000 992.680000 ;
+ RECT 335.220000 954.120000 336.320000 954.600000 ;
+ RECT 335.220000 959.560000 336.320000 960.040000 ;
+ RECT 335.220000 965.000000 336.320000 965.480000 ;
+ RECT 335.220000 970.440000 336.320000 970.920000 ;
+ RECT 290.220000 954.120000 291.320000 954.600000 ;
+ RECT 290.220000 959.560000 291.320000 960.040000 ;
+ RECT 290.220000 965.000000 291.320000 965.480000 ;
+ RECT 290.220000 970.440000 291.320000 970.920000 ;
+ RECT 241.390000 992.200000 242.390000 992.680000 ;
+ RECT 245.055000 992.200000 246.320000 992.680000 ;
+ RECT 241.390000 986.760000 242.390000 987.240000 ;
+ RECT 245.055000 986.760000 246.320000 987.240000 ;
+ RECT 241.390000 981.320000 242.390000 981.800000 ;
+ RECT 245.055000 981.320000 246.320000 981.800000 ;
+ RECT 241.390000 975.880000 242.390000 976.360000 ;
+ RECT 245.055000 975.880000 246.320000 976.360000 ;
+ RECT 241.390000 970.440000 242.390000 970.920000 ;
+ RECT 245.055000 970.440000 246.320000 970.920000 ;
+ RECT 241.390000 959.560000 242.390000 960.040000 ;
+ RECT 245.055000 959.560000 246.320000 960.040000 ;
+ RECT 241.390000 965.000000 242.390000 965.480000 ;
+ RECT 245.055000 965.000000 246.320000 965.480000 ;
+ RECT 241.390000 954.120000 242.390000 954.600000 ;
+ RECT 245.055000 954.120000 246.320000 954.600000 ;
+ RECT 380.220000 1046.600000 381.320000 1047.080000 ;
+ RECT 425.220000 1046.600000 426.320000 1047.080000 ;
+ RECT 438.030000 1046.600000 439.030000 1047.080000 ;
+ RECT 290.220000 1046.600000 291.320000 1047.080000 ;
+ RECT 335.220000 1046.600000 336.320000 1047.080000 ;
+ RECT 241.390000 1046.600000 242.390000 1047.080000 ;
+ RECT 245.055000 1046.600000 246.320000 1047.080000 ;
+ RECT 240.160000 1143.360000 440.260000 1144.360000 ;
+ RECT 240.160000 947.790000 440.260000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 946.540000 242.390000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 1145.800000 242.390000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 946.540000 439.030000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 1145.800000 439.030000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 947.790000 241.160000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 947.790000 440.260000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1143.360000 241.160000 1144.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1143.360000 440.260000 1144.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 938.820000 246.320000 939.300000 ;
+ RECT 245.055000 927.940000 246.320000 928.420000 ;
+ RECT 245.055000 933.380000 246.320000 933.860000 ;
+ RECT 245.055000 922.500000 246.320000 922.980000 ;
+ RECT 245.055000 917.060000 246.320000 917.540000 ;
+ RECT 245.055000 911.620000 246.320000 912.100000 ;
+ RECT 245.055000 906.180000 246.320000 906.660000 ;
+ RECT 245.055000 900.740000 246.320000 901.220000 ;
+ RECT 245.055000 895.300000 246.320000 895.780000 ;
+ RECT 245.055000 884.420000 246.320000 884.900000 ;
+ RECT 245.055000 889.860000 246.320000 890.340000 ;
+ RECT 245.055000 878.980000 246.320000 879.460000 ;
+ RECT 245.055000 873.540000 246.320000 874.020000 ;
+ RECT 245.055000 868.100000 246.320000 868.580000 ;
+ RECT 245.055000 862.660000 246.320000 863.140000 ;
+ RECT 245.055000 857.220000 246.320000 857.700000 ;
+ RECT 245.055000 851.780000 246.320000 852.260000 ;
+ RECT 245.055000 840.900000 246.320000 841.380000 ;
+ RECT 245.055000 835.460000 246.320000 835.940000 ;
+ RECT 245.055000 830.020000 246.320000 830.500000 ;
+ RECT 245.055000 824.580000 246.320000 825.060000 ;
+ RECT 245.055000 819.140000 246.320000 819.620000 ;
+ RECT 245.055000 813.700000 246.320000 814.180000 ;
+ RECT 245.055000 802.820000 246.320000 803.300000 ;
+ RECT 245.055000 808.260000 246.320000 808.740000 ;
+ RECT 245.055000 797.380000 246.320000 797.860000 ;
+ RECT 245.055000 791.940000 246.320000 792.420000 ;
+ RECT 245.055000 786.500000 246.320000 786.980000 ;
+ RECT 245.055000 781.060000 246.320000 781.540000 ;
+ RECT 245.055000 775.620000 246.320000 776.100000 ;
+ RECT 245.055000 770.180000 246.320000 770.660000 ;
+ RECT 245.055000 759.300000 246.320000 759.780000 ;
+ RECT 245.055000 764.740000 246.320000 765.220000 ;
+ RECT 245.055000 753.860000 246.320000 754.340000 ;
+ RECT 245.055000 846.340000 246.320000 846.820000 ;
+ RECT 425.220000 747.530000 426.320000 944.100000 ;
+ RECT 380.220000 747.530000 381.320000 944.100000 ;
+ RECT 438.030000 746.280000 439.030000 946.540000 ;
+ RECT 335.220000 747.530000 336.320000 944.100000 ;
+ RECT 290.220000 747.530000 291.320000 944.100000 ;
+ RECT 245.220000 747.530000 246.320000 944.100000 ;
+ RECT 241.390000 746.280000 242.390000 946.540000 ;
+ LAYER met3 ;
+ RECT 425.220000 938.820000 426.320000 939.300000 ;
+ RECT 438.030000 938.820000 439.030000 939.300000 ;
+ RECT 438.030000 927.940000 439.030000 928.420000 ;
+ RECT 438.030000 922.500000 439.030000 922.980000 ;
+ RECT 438.030000 933.380000 439.030000 933.860000 ;
+ RECT 425.220000 933.380000 426.320000 933.860000 ;
+ RECT 425.220000 927.940000 426.320000 928.420000 ;
+ RECT 425.220000 922.500000 426.320000 922.980000 ;
+ RECT 425.220000 911.620000 426.320000 912.100000 ;
+ RECT 425.220000 917.060000 426.320000 917.540000 ;
+ RECT 438.030000 911.620000 439.030000 912.100000 ;
+ RECT 438.030000 917.060000 439.030000 917.540000 ;
+ RECT 425.220000 900.740000 426.320000 901.220000 ;
+ RECT 425.220000 906.180000 426.320000 906.660000 ;
+ RECT 438.030000 900.740000 439.030000 901.220000 ;
+ RECT 438.030000 906.180000 439.030000 906.660000 ;
+ RECT 380.220000 922.500000 381.320000 922.980000 ;
+ RECT 380.220000 927.940000 381.320000 928.420000 ;
+ RECT 380.220000 933.380000 381.320000 933.860000 ;
+ RECT 380.220000 938.820000 381.320000 939.300000 ;
+ RECT 380.220000 906.180000 381.320000 906.660000 ;
+ RECT 380.220000 900.740000 381.320000 901.220000 ;
+ RECT 380.220000 911.620000 381.320000 912.100000 ;
+ RECT 380.220000 917.060000 381.320000 917.540000 ;
+ RECT 438.030000 889.860000 439.030000 890.340000 ;
+ RECT 438.030000 884.420000 439.030000 884.900000 ;
+ RECT 438.030000 895.300000 439.030000 895.780000 ;
+ RECT 425.220000 895.300000 426.320000 895.780000 ;
+ RECT 425.220000 889.860000 426.320000 890.340000 ;
+ RECT 425.220000 884.420000 426.320000 884.900000 ;
+ RECT 425.220000 873.540000 426.320000 874.020000 ;
+ RECT 425.220000 878.980000 426.320000 879.460000 ;
+ RECT 438.030000 873.540000 439.030000 874.020000 ;
+ RECT 438.030000 878.980000 439.030000 879.460000 ;
+ RECT 438.030000 862.660000 439.030000 863.140000 ;
+ RECT 438.030000 868.100000 439.030000 868.580000 ;
+ RECT 425.220000 868.100000 426.320000 868.580000 ;
+ RECT 425.220000 862.660000 426.320000 863.140000 ;
+ RECT 425.220000 851.780000 426.320000 852.260000 ;
+ RECT 425.220000 857.220000 426.320000 857.700000 ;
+ RECT 438.030000 851.780000 439.030000 852.260000 ;
+ RECT 438.030000 857.220000 439.030000 857.700000 ;
+ RECT 380.220000 873.540000 381.320000 874.020000 ;
+ RECT 380.220000 878.980000 381.320000 879.460000 ;
+ RECT 380.220000 884.420000 381.320000 884.900000 ;
+ RECT 380.220000 889.860000 381.320000 890.340000 ;
+ RECT 380.220000 895.300000 381.320000 895.780000 ;
+ RECT 380.220000 851.780000 381.320000 852.260000 ;
+ RECT 380.220000 857.220000 381.320000 857.700000 ;
+ RECT 380.220000 862.660000 381.320000 863.140000 ;
+ RECT 380.220000 868.100000 381.320000 868.580000 ;
+ RECT 335.220000 927.940000 336.320000 928.420000 ;
+ RECT 335.220000 922.500000 336.320000 922.980000 ;
+ RECT 335.220000 933.380000 336.320000 933.860000 ;
+ RECT 335.220000 938.820000 336.320000 939.300000 ;
+ RECT 290.220000 922.500000 291.320000 922.980000 ;
+ RECT 290.220000 927.940000 291.320000 928.420000 ;
+ RECT 290.220000 933.380000 291.320000 933.860000 ;
+ RECT 290.220000 938.820000 291.320000 939.300000 ;
+ RECT 335.220000 900.740000 336.320000 901.220000 ;
+ RECT 335.220000 906.180000 336.320000 906.660000 ;
+ RECT 335.220000 911.620000 336.320000 912.100000 ;
+ RECT 335.220000 917.060000 336.320000 917.540000 ;
+ RECT 290.220000 900.740000 291.320000 901.220000 ;
+ RECT 290.220000 906.180000 291.320000 906.660000 ;
+ RECT 290.220000 911.620000 291.320000 912.100000 ;
+ RECT 290.220000 917.060000 291.320000 917.540000 ;
+ RECT 241.390000 938.820000 242.390000 939.300000 ;
+ RECT 245.055000 938.820000 246.320000 939.300000 ;
+ RECT 241.390000 927.940000 242.390000 928.420000 ;
+ RECT 245.055000 927.940000 246.320000 928.420000 ;
+ RECT 241.390000 933.380000 242.390000 933.860000 ;
+ RECT 245.055000 933.380000 246.320000 933.860000 ;
+ RECT 241.390000 922.500000 242.390000 922.980000 ;
+ RECT 245.055000 922.500000 246.320000 922.980000 ;
+ RECT 241.390000 917.060000 242.390000 917.540000 ;
+ RECT 245.055000 917.060000 246.320000 917.540000 ;
+ RECT 241.390000 911.620000 242.390000 912.100000 ;
+ RECT 245.055000 911.620000 246.320000 912.100000 ;
+ RECT 241.390000 906.180000 242.390000 906.660000 ;
+ RECT 245.055000 906.180000 246.320000 906.660000 ;
+ RECT 241.390000 900.740000 242.390000 901.220000 ;
+ RECT 245.055000 900.740000 246.320000 901.220000 ;
+ RECT 335.220000 873.540000 336.320000 874.020000 ;
+ RECT 335.220000 878.980000 336.320000 879.460000 ;
+ RECT 335.220000 884.420000 336.320000 884.900000 ;
+ RECT 335.220000 889.860000 336.320000 890.340000 ;
+ RECT 335.220000 895.300000 336.320000 895.780000 ;
+ RECT 290.220000 873.540000 291.320000 874.020000 ;
+ RECT 290.220000 878.980000 291.320000 879.460000 ;
+ RECT 290.220000 884.420000 291.320000 884.900000 ;
+ RECT 290.220000 889.860000 291.320000 890.340000 ;
+ RECT 290.220000 895.300000 291.320000 895.780000 ;
+ RECT 335.220000 851.780000 336.320000 852.260000 ;
+ RECT 335.220000 857.220000 336.320000 857.700000 ;
+ RECT 335.220000 862.660000 336.320000 863.140000 ;
+ RECT 335.220000 868.100000 336.320000 868.580000 ;
+ RECT 290.220000 851.780000 291.320000 852.260000 ;
+ RECT 290.220000 857.220000 291.320000 857.700000 ;
+ RECT 290.220000 862.660000 291.320000 863.140000 ;
+ RECT 290.220000 868.100000 291.320000 868.580000 ;
+ RECT 241.390000 895.300000 242.390000 895.780000 ;
+ RECT 245.055000 895.300000 246.320000 895.780000 ;
+ RECT 241.390000 884.420000 242.390000 884.900000 ;
+ RECT 245.055000 884.420000 246.320000 884.900000 ;
+ RECT 241.390000 889.860000 242.390000 890.340000 ;
+ RECT 245.055000 889.860000 246.320000 890.340000 ;
+ RECT 241.390000 878.980000 242.390000 879.460000 ;
+ RECT 245.055000 878.980000 246.320000 879.460000 ;
+ RECT 241.390000 873.540000 242.390000 874.020000 ;
+ RECT 245.055000 873.540000 246.320000 874.020000 ;
+ RECT 241.390000 868.100000 242.390000 868.580000 ;
+ RECT 245.055000 868.100000 246.320000 868.580000 ;
+ RECT 241.390000 862.660000 242.390000 863.140000 ;
+ RECT 245.055000 862.660000 246.320000 863.140000 ;
+ RECT 241.390000 857.220000 242.390000 857.700000 ;
+ RECT 245.055000 857.220000 246.320000 857.700000 ;
+ RECT 241.390000 851.780000 242.390000 852.260000 ;
+ RECT 245.055000 851.780000 246.320000 852.260000 ;
+ RECT 425.220000 835.460000 426.320000 835.940000 ;
+ RECT 425.220000 840.900000 426.320000 841.380000 ;
+ RECT 438.030000 835.460000 439.030000 835.940000 ;
+ RECT 438.030000 840.900000 439.030000 841.380000 ;
+ RECT 438.030000 824.580000 439.030000 825.060000 ;
+ RECT 438.030000 830.020000 439.030000 830.500000 ;
+ RECT 425.220000 830.020000 426.320000 830.500000 ;
+ RECT 425.220000 824.580000 426.320000 825.060000 ;
+ RECT 425.220000 813.700000 426.320000 814.180000 ;
+ RECT 425.220000 819.140000 426.320000 819.620000 ;
+ RECT 438.030000 813.700000 439.030000 814.180000 ;
+ RECT 438.030000 819.140000 439.030000 819.620000 ;
+ RECT 438.030000 802.820000 439.030000 803.300000 ;
+ RECT 438.030000 797.380000 439.030000 797.860000 ;
+ RECT 438.030000 808.260000 439.030000 808.740000 ;
+ RECT 425.220000 808.260000 426.320000 808.740000 ;
+ RECT 425.220000 802.820000 426.320000 803.300000 ;
+ RECT 425.220000 797.380000 426.320000 797.860000 ;
+ RECT 380.220000 824.580000 381.320000 825.060000 ;
+ RECT 380.220000 830.020000 381.320000 830.500000 ;
+ RECT 380.220000 835.460000 381.320000 835.940000 ;
+ RECT 380.220000 840.900000 381.320000 841.380000 ;
+ RECT 380.220000 797.380000 381.320000 797.860000 ;
+ RECT 380.220000 802.820000 381.320000 803.300000 ;
+ RECT 380.220000 808.260000 381.320000 808.740000 ;
+ RECT 380.220000 813.700000 381.320000 814.180000 ;
+ RECT 380.220000 819.140000 381.320000 819.620000 ;
+ RECT 425.220000 786.500000 426.320000 786.980000 ;
+ RECT 425.220000 791.940000 426.320000 792.420000 ;
+ RECT 438.030000 786.500000 439.030000 786.980000 ;
+ RECT 438.030000 791.940000 439.030000 792.420000 ;
+ RECT 425.220000 775.620000 426.320000 776.100000 ;
+ RECT 425.220000 781.060000 426.320000 781.540000 ;
+ RECT 438.030000 775.620000 439.030000 776.100000 ;
+ RECT 438.030000 781.060000 439.030000 781.540000 ;
+ RECT 438.030000 764.740000 439.030000 765.220000 ;
+ RECT 438.030000 759.300000 439.030000 759.780000 ;
+ RECT 438.030000 770.180000 439.030000 770.660000 ;
+ RECT 425.220000 770.180000 426.320000 770.660000 ;
+ RECT 425.220000 764.740000 426.320000 765.220000 ;
+ RECT 425.220000 759.300000 426.320000 759.780000 ;
+ RECT 425.220000 753.860000 426.320000 754.340000 ;
+ RECT 438.030000 753.860000 439.030000 754.340000 ;
+ RECT 380.220000 775.620000 381.320000 776.100000 ;
+ RECT 380.220000 781.060000 381.320000 781.540000 ;
+ RECT 380.220000 786.500000 381.320000 786.980000 ;
+ RECT 380.220000 791.940000 381.320000 792.420000 ;
+ RECT 380.220000 753.860000 381.320000 754.340000 ;
+ RECT 380.220000 759.300000 381.320000 759.780000 ;
+ RECT 380.220000 764.740000 381.320000 765.220000 ;
+ RECT 380.220000 770.180000 381.320000 770.660000 ;
+ RECT 335.220000 824.580000 336.320000 825.060000 ;
+ RECT 335.220000 830.020000 336.320000 830.500000 ;
+ RECT 335.220000 835.460000 336.320000 835.940000 ;
+ RECT 335.220000 840.900000 336.320000 841.380000 ;
+ RECT 290.220000 824.580000 291.320000 825.060000 ;
+ RECT 290.220000 830.020000 291.320000 830.500000 ;
+ RECT 290.220000 835.460000 291.320000 835.940000 ;
+ RECT 290.220000 840.900000 291.320000 841.380000 ;
+ RECT 335.220000 797.380000 336.320000 797.860000 ;
+ RECT 335.220000 802.820000 336.320000 803.300000 ;
+ RECT 335.220000 808.260000 336.320000 808.740000 ;
+ RECT 335.220000 813.700000 336.320000 814.180000 ;
+ RECT 335.220000 819.140000 336.320000 819.620000 ;
+ RECT 290.220000 797.380000 291.320000 797.860000 ;
+ RECT 290.220000 802.820000 291.320000 803.300000 ;
+ RECT 290.220000 808.260000 291.320000 808.740000 ;
+ RECT 290.220000 813.700000 291.320000 814.180000 ;
+ RECT 290.220000 819.140000 291.320000 819.620000 ;
+ RECT 241.390000 840.900000 242.390000 841.380000 ;
+ RECT 245.055000 840.900000 246.320000 841.380000 ;
+ RECT 241.390000 835.460000 242.390000 835.940000 ;
+ RECT 245.055000 835.460000 246.320000 835.940000 ;
+ RECT 241.390000 830.020000 242.390000 830.500000 ;
+ RECT 245.055000 830.020000 246.320000 830.500000 ;
+ RECT 241.390000 824.580000 242.390000 825.060000 ;
+ RECT 245.055000 824.580000 246.320000 825.060000 ;
+ RECT 241.390000 819.140000 242.390000 819.620000 ;
+ RECT 245.055000 819.140000 246.320000 819.620000 ;
+ RECT 241.390000 813.700000 242.390000 814.180000 ;
+ RECT 245.055000 813.700000 246.320000 814.180000 ;
+ RECT 241.390000 802.820000 242.390000 803.300000 ;
+ RECT 245.055000 802.820000 246.320000 803.300000 ;
+ RECT 241.390000 808.260000 242.390000 808.740000 ;
+ RECT 245.055000 808.260000 246.320000 808.740000 ;
+ RECT 241.390000 797.380000 242.390000 797.860000 ;
+ RECT 245.055000 797.380000 246.320000 797.860000 ;
+ RECT 335.220000 775.620000 336.320000 776.100000 ;
+ RECT 335.220000 781.060000 336.320000 781.540000 ;
+ RECT 335.220000 786.500000 336.320000 786.980000 ;
+ RECT 335.220000 791.940000 336.320000 792.420000 ;
+ RECT 290.220000 775.620000 291.320000 776.100000 ;
+ RECT 290.220000 781.060000 291.320000 781.540000 ;
+ RECT 290.220000 786.500000 291.320000 786.980000 ;
+ RECT 290.220000 791.940000 291.320000 792.420000 ;
+ RECT 335.220000 753.860000 336.320000 754.340000 ;
+ RECT 335.220000 759.300000 336.320000 759.780000 ;
+ RECT 335.220000 764.740000 336.320000 765.220000 ;
+ RECT 335.220000 770.180000 336.320000 770.660000 ;
+ RECT 290.220000 753.860000 291.320000 754.340000 ;
+ RECT 290.220000 759.300000 291.320000 759.780000 ;
+ RECT 290.220000 764.740000 291.320000 765.220000 ;
+ RECT 290.220000 770.180000 291.320000 770.660000 ;
+ RECT 241.390000 791.940000 242.390000 792.420000 ;
+ RECT 245.055000 791.940000 246.320000 792.420000 ;
+ RECT 241.390000 786.500000 242.390000 786.980000 ;
+ RECT 245.055000 786.500000 246.320000 786.980000 ;
+ RECT 241.390000 781.060000 242.390000 781.540000 ;
+ RECT 245.055000 781.060000 246.320000 781.540000 ;
+ RECT 241.390000 775.620000 242.390000 776.100000 ;
+ RECT 245.055000 775.620000 246.320000 776.100000 ;
+ RECT 241.390000 770.180000 242.390000 770.660000 ;
+ RECT 245.055000 770.180000 246.320000 770.660000 ;
+ RECT 241.390000 759.300000 242.390000 759.780000 ;
+ RECT 245.055000 759.300000 246.320000 759.780000 ;
+ RECT 241.390000 764.740000 242.390000 765.220000 ;
+ RECT 245.055000 764.740000 246.320000 765.220000 ;
+ RECT 241.390000 753.860000 242.390000 754.340000 ;
+ RECT 245.055000 753.860000 246.320000 754.340000 ;
+ RECT 380.220000 846.340000 381.320000 846.820000 ;
+ RECT 425.220000 846.340000 426.320000 846.820000 ;
+ RECT 438.030000 846.340000 439.030000 846.820000 ;
+ RECT 290.220000 846.340000 291.320000 846.820000 ;
+ RECT 335.220000 846.340000 336.320000 846.820000 ;
+ RECT 241.390000 846.340000 242.390000 846.820000 ;
+ RECT 245.055000 846.340000 246.320000 846.820000 ;
+ RECT 240.160000 943.100000 440.260000 944.100000 ;
+ RECT 240.160000 747.530000 440.260000 748.530000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 746.280000 242.390000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 945.540000 242.390000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 746.280000 439.030000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 945.540000 439.030000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 747.530000 241.160000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 747.530000 440.260000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 943.100000 241.160000 944.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 943.100000 440.260000 944.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 738.560000 246.320000 739.040000 ;
+ RECT 245.055000 727.680000 246.320000 728.160000 ;
+ RECT 245.055000 733.120000 246.320000 733.600000 ;
+ RECT 245.055000 722.240000 246.320000 722.720000 ;
+ RECT 245.055000 716.800000 246.320000 717.280000 ;
+ RECT 245.055000 711.360000 246.320000 711.840000 ;
+ RECT 245.055000 705.920000 246.320000 706.400000 ;
+ RECT 245.055000 700.480000 246.320000 700.960000 ;
+ RECT 245.055000 695.040000 246.320000 695.520000 ;
+ RECT 245.055000 684.160000 246.320000 684.640000 ;
+ RECT 245.055000 689.600000 246.320000 690.080000 ;
+ RECT 245.055000 678.720000 246.320000 679.200000 ;
+ RECT 245.055000 673.280000 246.320000 673.760000 ;
+ RECT 245.055000 667.840000 246.320000 668.320000 ;
+ RECT 245.055000 662.400000 246.320000 662.880000 ;
+ RECT 245.055000 656.960000 246.320000 657.440000 ;
+ RECT 245.055000 651.520000 246.320000 652.000000 ;
+ RECT 245.055000 640.640000 246.320000 641.120000 ;
+ RECT 245.055000 635.200000 246.320000 635.680000 ;
+ RECT 245.055000 629.760000 246.320000 630.240000 ;
+ RECT 245.055000 624.320000 246.320000 624.800000 ;
+ RECT 245.055000 618.880000 246.320000 619.360000 ;
+ RECT 245.055000 613.440000 246.320000 613.920000 ;
+ RECT 245.055000 602.560000 246.320000 603.040000 ;
+ RECT 245.055000 608.000000 246.320000 608.480000 ;
+ RECT 245.055000 597.120000 246.320000 597.600000 ;
+ RECT 245.055000 591.680000 246.320000 592.160000 ;
+ RECT 245.055000 586.240000 246.320000 586.720000 ;
+ RECT 245.055000 580.800000 246.320000 581.280000 ;
+ RECT 245.055000 575.360000 246.320000 575.840000 ;
+ RECT 245.055000 569.920000 246.320000 570.400000 ;
+ RECT 245.055000 559.040000 246.320000 559.520000 ;
+ RECT 245.055000 564.480000 246.320000 564.960000 ;
+ RECT 245.055000 553.600000 246.320000 554.080000 ;
+ RECT 245.055000 646.080000 246.320000 646.560000 ;
+ RECT 425.220000 547.270000 426.320000 743.840000 ;
+ RECT 380.220000 547.270000 381.320000 743.840000 ;
+ RECT 438.030000 546.020000 439.030000 746.280000 ;
+ RECT 335.220000 547.270000 336.320000 743.840000 ;
+ RECT 290.220000 547.270000 291.320000 743.840000 ;
+ RECT 245.220000 547.270000 246.320000 743.840000 ;
+ RECT 241.390000 546.020000 242.390000 746.280000 ;
+ LAYER met3 ;
+ RECT 425.220000 738.560000 426.320000 739.040000 ;
+ RECT 438.030000 738.560000 439.030000 739.040000 ;
+ RECT 438.030000 727.680000 439.030000 728.160000 ;
+ RECT 438.030000 722.240000 439.030000 722.720000 ;
+ RECT 438.030000 733.120000 439.030000 733.600000 ;
+ RECT 425.220000 733.120000 426.320000 733.600000 ;
+ RECT 425.220000 727.680000 426.320000 728.160000 ;
+ RECT 425.220000 722.240000 426.320000 722.720000 ;
+ RECT 425.220000 711.360000 426.320000 711.840000 ;
+ RECT 425.220000 716.800000 426.320000 717.280000 ;
+ RECT 438.030000 711.360000 439.030000 711.840000 ;
+ RECT 438.030000 716.800000 439.030000 717.280000 ;
+ RECT 425.220000 700.480000 426.320000 700.960000 ;
+ RECT 425.220000 705.920000 426.320000 706.400000 ;
+ RECT 438.030000 700.480000 439.030000 700.960000 ;
+ RECT 438.030000 705.920000 439.030000 706.400000 ;
+ RECT 380.220000 722.240000 381.320000 722.720000 ;
+ RECT 380.220000 727.680000 381.320000 728.160000 ;
+ RECT 380.220000 733.120000 381.320000 733.600000 ;
+ RECT 380.220000 738.560000 381.320000 739.040000 ;
+ RECT 380.220000 705.920000 381.320000 706.400000 ;
+ RECT 380.220000 700.480000 381.320000 700.960000 ;
+ RECT 380.220000 711.360000 381.320000 711.840000 ;
+ RECT 380.220000 716.800000 381.320000 717.280000 ;
+ RECT 438.030000 689.600000 439.030000 690.080000 ;
+ RECT 438.030000 684.160000 439.030000 684.640000 ;
+ RECT 438.030000 695.040000 439.030000 695.520000 ;
+ RECT 425.220000 695.040000 426.320000 695.520000 ;
+ RECT 425.220000 689.600000 426.320000 690.080000 ;
+ RECT 425.220000 684.160000 426.320000 684.640000 ;
+ RECT 425.220000 673.280000 426.320000 673.760000 ;
+ RECT 425.220000 678.720000 426.320000 679.200000 ;
+ RECT 438.030000 673.280000 439.030000 673.760000 ;
+ RECT 438.030000 678.720000 439.030000 679.200000 ;
+ RECT 438.030000 662.400000 439.030000 662.880000 ;
+ RECT 438.030000 667.840000 439.030000 668.320000 ;
+ RECT 425.220000 667.840000 426.320000 668.320000 ;
+ RECT 425.220000 662.400000 426.320000 662.880000 ;
+ RECT 425.220000 651.520000 426.320000 652.000000 ;
+ RECT 425.220000 656.960000 426.320000 657.440000 ;
+ RECT 438.030000 651.520000 439.030000 652.000000 ;
+ RECT 438.030000 656.960000 439.030000 657.440000 ;
+ RECT 380.220000 673.280000 381.320000 673.760000 ;
+ RECT 380.220000 678.720000 381.320000 679.200000 ;
+ RECT 380.220000 684.160000 381.320000 684.640000 ;
+ RECT 380.220000 689.600000 381.320000 690.080000 ;
+ RECT 380.220000 695.040000 381.320000 695.520000 ;
+ RECT 380.220000 651.520000 381.320000 652.000000 ;
+ RECT 380.220000 656.960000 381.320000 657.440000 ;
+ RECT 380.220000 662.400000 381.320000 662.880000 ;
+ RECT 380.220000 667.840000 381.320000 668.320000 ;
+ RECT 335.220000 727.680000 336.320000 728.160000 ;
+ RECT 335.220000 722.240000 336.320000 722.720000 ;
+ RECT 335.220000 733.120000 336.320000 733.600000 ;
+ RECT 335.220000 738.560000 336.320000 739.040000 ;
+ RECT 290.220000 722.240000 291.320000 722.720000 ;
+ RECT 290.220000 727.680000 291.320000 728.160000 ;
+ RECT 290.220000 733.120000 291.320000 733.600000 ;
+ RECT 290.220000 738.560000 291.320000 739.040000 ;
+ RECT 335.220000 700.480000 336.320000 700.960000 ;
+ RECT 335.220000 705.920000 336.320000 706.400000 ;
+ RECT 335.220000 711.360000 336.320000 711.840000 ;
+ RECT 335.220000 716.800000 336.320000 717.280000 ;
+ RECT 290.220000 700.480000 291.320000 700.960000 ;
+ RECT 290.220000 705.920000 291.320000 706.400000 ;
+ RECT 290.220000 711.360000 291.320000 711.840000 ;
+ RECT 290.220000 716.800000 291.320000 717.280000 ;
+ RECT 241.390000 738.560000 242.390000 739.040000 ;
+ RECT 245.055000 738.560000 246.320000 739.040000 ;
+ RECT 241.390000 727.680000 242.390000 728.160000 ;
+ RECT 245.055000 727.680000 246.320000 728.160000 ;
+ RECT 241.390000 733.120000 242.390000 733.600000 ;
+ RECT 245.055000 733.120000 246.320000 733.600000 ;
+ RECT 241.390000 722.240000 242.390000 722.720000 ;
+ RECT 245.055000 722.240000 246.320000 722.720000 ;
+ RECT 241.390000 716.800000 242.390000 717.280000 ;
+ RECT 245.055000 716.800000 246.320000 717.280000 ;
+ RECT 241.390000 711.360000 242.390000 711.840000 ;
+ RECT 245.055000 711.360000 246.320000 711.840000 ;
+ RECT 241.390000 705.920000 242.390000 706.400000 ;
+ RECT 245.055000 705.920000 246.320000 706.400000 ;
+ RECT 241.390000 700.480000 242.390000 700.960000 ;
+ RECT 245.055000 700.480000 246.320000 700.960000 ;
+ RECT 335.220000 673.280000 336.320000 673.760000 ;
+ RECT 335.220000 678.720000 336.320000 679.200000 ;
+ RECT 335.220000 684.160000 336.320000 684.640000 ;
+ RECT 335.220000 689.600000 336.320000 690.080000 ;
+ RECT 335.220000 695.040000 336.320000 695.520000 ;
+ RECT 290.220000 673.280000 291.320000 673.760000 ;
+ RECT 290.220000 678.720000 291.320000 679.200000 ;
+ RECT 290.220000 684.160000 291.320000 684.640000 ;
+ RECT 290.220000 689.600000 291.320000 690.080000 ;
+ RECT 290.220000 695.040000 291.320000 695.520000 ;
+ RECT 335.220000 651.520000 336.320000 652.000000 ;
+ RECT 335.220000 656.960000 336.320000 657.440000 ;
+ RECT 335.220000 662.400000 336.320000 662.880000 ;
+ RECT 335.220000 667.840000 336.320000 668.320000 ;
+ RECT 290.220000 651.520000 291.320000 652.000000 ;
+ RECT 290.220000 656.960000 291.320000 657.440000 ;
+ RECT 290.220000 662.400000 291.320000 662.880000 ;
+ RECT 290.220000 667.840000 291.320000 668.320000 ;
+ RECT 241.390000 695.040000 242.390000 695.520000 ;
+ RECT 245.055000 695.040000 246.320000 695.520000 ;
+ RECT 241.390000 684.160000 242.390000 684.640000 ;
+ RECT 245.055000 684.160000 246.320000 684.640000 ;
+ RECT 241.390000 689.600000 242.390000 690.080000 ;
+ RECT 245.055000 689.600000 246.320000 690.080000 ;
+ RECT 241.390000 678.720000 242.390000 679.200000 ;
+ RECT 245.055000 678.720000 246.320000 679.200000 ;
+ RECT 241.390000 673.280000 242.390000 673.760000 ;
+ RECT 245.055000 673.280000 246.320000 673.760000 ;
+ RECT 241.390000 667.840000 242.390000 668.320000 ;
+ RECT 245.055000 667.840000 246.320000 668.320000 ;
+ RECT 241.390000 662.400000 242.390000 662.880000 ;
+ RECT 245.055000 662.400000 246.320000 662.880000 ;
+ RECT 241.390000 656.960000 242.390000 657.440000 ;
+ RECT 245.055000 656.960000 246.320000 657.440000 ;
+ RECT 241.390000 651.520000 242.390000 652.000000 ;
+ RECT 245.055000 651.520000 246.320000 652.000000 ;
+ RECT 425.220000 635.200000 426.320000 635.680000 ;
+ RECT 425.220000 640.640000 426.320000 641.120000 ;
+ RECT 438.030000 635.200000 439.030000 635.680000 ;
+ RECT 438.030000 640.640000 439.030000 641.120000 ;
+ RECT 438.030000 624.320000 439.030000 624.800000 ;
+ RECT 438.030000 629.760000 439.030000 630.240000 ;
+ RECT 425.220000 629.760000 426.320000 630.240000 ;
+ RECT 425.220000 624.320000 426.320000 624.800000 ;
+ RECT 425.220000 613.440000 426.320000 613.920000 ;
+ RECT 425.220000 618.880000 426.320000 619.360000 ;
+ RECT 438.030000 613.440000 439.030000 613.920000 ;
+ RECT 438.030000 618.880000 439.030000 619.360000 ;
+ RECT 438.030000 602.560000 439.030000 603.040000 ;
+ RECT 438.030000 597.120000 439.030000 597.600000 ;
+ RECT 438.030000 608.000000 439.030000 608.480000 ;
+ RECT 425.220000 608.000000 426.320000 608.480000 ;
+ RECT 425.220000 602.560000 426.320000 603.040000 ;
+ RECT 425.220000 597.120000 426.320000 597.600000 ;
+ RECT 380.220000 624.320000 381.320000 624.800000 ;
+ RECT 380.220000 629.760000 381.320000 630.240000 ;
+ RECT 380.220000 635.200000 381.320000 635.680000 ;
+ RECT 380.220000 640.640000 381.320000 641.120000 ;
+ RECT 380.220000 597.120000 381.320000 597.600000 ;
+ RECT 380.220000 602.560000 381.320000 603.040000 ;
+ RECT 380.220000 608.000000 381.320000 608.480000 ;
+ RECT 380.220000 613.440000 381.320000 613.920000 ;
+ RECT 380.220000 618.880000 381.320000 619.360000 ;
+ RECT 425.220000 586.240000 426.320000 586.720000 ;
+ RECT 425.220000 591.680000 426.320000 592.160000 ;
+ RECT 438.030000 586.240000 439.030000 586.720000 ;
+ RECT 438.030000 591.680000 439.030000 592.160000 ;
+ RECT 425.220000 575.360000 426.320000 575.840000 ;
+ RECT 425.220000 580.800000 426.320000 581.280000 ;
+ RECT 438.030000 575.360000 439.030000 575.840000 ;
+ RECT 438.030000 580.800000 439.030000 581.280000 ;
+ RECT 438.030000 564.480000 439.030000 564.960000 ;
+ RECT 438.030000 559.040000 439.030000 559.520000 ;
+ RECT 438.030000 569.920000 439.030000 570.400000 ;
+ RECT 425.220000 569.920000 426.320000 570.400000 ;
+ RECT 425.220000 564.480000 426.320000 564.960000 ;
+ RECT 425.220000 559.040000 426.320000 559.520000 ;
+ RECT 425.220000 553.600000 426.320000 554.080000 ;
+ RECT 438.030000 553.600000 439.030000 554.080000 ;
+ RECT 380.220000 575.360000 381.320000 575.840000 ;
+ RECT 380.220000 580.800000 381.320000 581.280000 ;
+ RECT 380.220000 586.240000 381.320000 586.720000 ;
+ RECT 380.220000 591.680000 381.320000 592.160000 ;
+ RECT 380.220000 553.600000 381.320000 554.080000 ;
+ RECT 380.220000 559.040000 381.320000 559.520000 ;
+ RECT 380.220000 564.480000 381.320000 564.960000 ;
+ RECT 380.220000 569.920000 381.320000 570.400000 ;
+ RECT 335.220000 624.320000 336.320000 624.800000 ;
+ RECT 335.220000 629.760000 336.320000 630.240000 ;
+ RECT 335.220000 635.200000 336.320000 635.680000 ;
+ RECT 335.220000 640.640000 336.320000 641.120000 ;
+ RECT 290.220000 624.320000 291.320000 624.800000 ;
+ RECT 290.220000 629.760000 291.320000 630.240000 ;
+ RECT 290.220000 635.200000 291.320000 635.680000 ;
+ RECT 290.220000 640.640000 291.320000 641.120000 ;
+ RECT 335.220000 597.120000 336.320000 597.600000 ;
+ RECT 335.220000 602.560000 336.320000 603.040000 ;
+ RECT 335.220000 608.000000 336.320000 608.480000 ;
+ RECT 335.220000 613.440000 336.320000 613.920000 ;
+ RECT 335.220000 618.880000 336.320000 619.360000 ;
+ RECT 290.220000 597.120000 291.320000 597.600000 ;
+ RECT 290.220000 602.560000 291.320000 603.040000 ;
+ RECT 290.220000 608.000000 291.320000 608.480000 ;
+ RECT 290.220000 613.440000 291.320000 613.920000 ;
+ RECT 290.220000 618.880000 291.320000 619.360000 ;
+ RECT 241.390000 640.640000 242.390000 641.120000 ;
+ RECT 245.055000 640.640000 246.320000 641.120000 ;
+ RECT 241.390000 635.200000 242.390000 635.680000 ;
+ RECT 245.055000 635.200000 246.320000 635.680000 ;
+ RECT 241.390000 629.760000 242.390000 630.240000 ;
+ RECT 245.055000 629.760000 246.320000 630.240000 ;
+ RECT 241.390000 624.320000 242.390000 624.800000 ;
+ RECT 245.055000 624.320000 246.320000 624.800000 ;
+ RECT 241.390000 618.880000 242.390000 619.360000 ;
+ RECT 245.055000 618.880000 246.320000 619.360000 ;
+ RECT 241.390000 613.440000 242.390000 613.920000 ;
+ RECT 245.055000 613.440000 246.320000 613.920000 ;
+ RECT 241.390000 602.560000 242.390000 603.040000 ;
+ RECT 245.055000 602.560000 246.320000 603.040000 ;
+ RECT 241.390000 608.000000 242.390000 608.480000 ;
+ RECT 245.055000 608.000000 246.320000 608.480000 ;
+ RECT 241.390000 597.120000 242.390000 597.600000 ;
+ RECT 245.055000 597.120000 246.320000 597.600000 ;
+ RECT 335.220000 575.360000 336.320000 575.840000 ;
+ RECT 335.220000 580.800000 336.320000 581.280000 ;
+ RECT 335.220000 586.240000 336.320000 586.720000 ;
+ RECT 335.220000 591.680000 336.320000 592.160000 ;
+ RECT 290.220000 575.360000 291.320000 575.840000 ;
+ RECT 290.220000 580.800000 291.320000 581.280000 ;
+ RECT 290.220000 586.240000 291.320000 586.720000 ;
+ RECT 290.220000 591.680000 291.320000 592.160000 ;
+ RECT 335.220000 553.600000 336.320000 554.080000 ;
+ RECT 335.220000 559.040000 336.320000 559.520000 ;
+ RECT 335.220000 564.480000 336.320000 564.960000 ;
+ RECT 335.220000 569.920000 336.320000 570.400000 ;
+ RECT 290.220000 553.600000 291.320000 554.080000 ;
+ RECT 290.220000 559.040000 291.320000 559.520000 ;
+ RECT 290.220000 564.480000 291.320000 564.960000 ;
+ RECT 290.220000 569.920000 291.320000 570.400000 ;
+ RECT 241.390000 591.680000 242.390000 592.160000 ;
+ RECT 245.055000 591.680000 246.320000 592.160000 ;
+ RECT 241.390000 586.240000 242.390000 586.720000 ;
+ RECT 245.055000 586.240000 246.320000 586.720000 ;
+ RECT 241.390000 580.800000 242.390000 581.280000 ;
+ RECT 245.055000 580.800000 246.320000 581.280000 ;
+ RECT 241.390000 575.360000 242.390000 575.840000 ;
+ RECT 245.055000 575.360000 246.320000 575.840000 ;
+ RECT 241.390000 569.920000 242.390000 570.400000 ;
+ RECT 245.055000 569.920000 246.320000 570.400000 ;
+ RECT 241.390000 559.040000 242.390000 559.520000 ;
+ RECT 245.055000 559.040000 246.320000 559.520000 ;
+ RECT 241.390000 564.480000 242.390000 564.960000 ;
+ RECT 245.055000 564.480000 246.320000 564.960000 ;
+ RECT 241.390000 553.600000 242.390000 554.080000 ;
+ RECT 245.055000 553.600000 246.320000 554.080000 ;
+ RECT 380.220000 646.080000 381.320000 646.560000 ;
+ RECT 425.220000 646.080000 426.320000 646.560000 ;
+ RECT 438.030000 646.080000 439.030000 646.560000 ;
+ RECT 290.220000 646.080000 291.320000 646.560000 ;
+ RECT 335.220000 646.080000 336.320000 646.560000 ;
+ RECT 241.390000 646.080000 242.390000 646.560000 ;
+ RECT 245.055000 646.080000 246.320000 646.560000 ;
+ RECT 240.160000 742.840000 440.260000 743.840000 ;
+ RECT 240.160000 547.270000 440.260000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 546.020000 242.390000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 745.280000 242.390000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 546.020000 439.030000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 745.280000 439.030000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 547.270000 241.160000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 547.270000 440.260000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 742.840000 241.160000 743.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 742.840000 440.260000 743.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 538.300000 246.320000 538.780000 ;
+ RECT 245.055000 527.420000 246.320000 527.900000 ;
+ RECT 245.055000 532.860000 246.320000 533.340000 ;
+ RECT 245.055000 521.980000 246.320000 522.460000 ;
+ RECT 245.055000 516.540000 246.320000 517.020000 ;
+ RECT 245.055000 511.100000 246.320000 511.580000 ;
+ RECT 245.055000 505.660000 246.320000 506.140000 ;
+ RECT 245.055000 500.220000 246.320000 500.700000 ;
+ RECT 245.055000 494.780000 246.320000 495.260000 ;
+ RECT 245.055000 483.900000 246.320000 484.380000 ;
+ RECT 245.055000 489.340000 246.320000 489.820000 ;
+ RECT 245.055000 478.460000 246.320000 478.940000 ;
+ RECT 245.055000 473.020000 246.320000 473.500000 ;
+ RECT 245.055000 467.580000 246.320000 468.060000 ;
+ RECT 245.055000 462.140000 246.320000 462.620000 ;
+ RECT 245.055000 456.700000 246.320000 457.180000 ;
+ RECT 245.055000 451.260000 246.320000 451.740000 ;
+ RECT 245.055000 440.380000 246.320000 440.860000 ;
+ RECT 245.055000 434.940000 246.320000 435.420000 ;
+ RECT 245.055000 429.500000 246.320000 429.980000 ;
+ RECT 245.055000 424.060000 246.320000 424.540000 ;
+ RECT 245.055000 418.620000 246.320000 419.100000 ;
+ RECT 245.055000 413.180000 246.320000 413.660000 ;
+ RECT 245.055000 402.300000 246.320000 402.780000 ;
+ RECT 245.055000 407.740000 246.320000 408.220000 ;
+ RECT 245.055000 396.860000 246.320000 397.340000 ;
+ RECT 245.055000 391.420000 246.320000 391.900000 ;
+ RECT 245.055000 385.980000 246.320000 386.460000 ;
+ RECT 245.055000 380.540000 246.320000 381.020000 ;
+ RECT 245.055000 375.100000 246.320000 375.580000 ;
+ RECT 245.055000 369.660000 246.320000 370.140000 ;
+ RECT 245.055000 358.780000 246.320000 359.260000 ;
+ RECT 245.055000 364.220000 246.320000 364.700000 ;
+ RECT 245.055000 353.340000 246.320000 353.820000 ;
+ RECT 245.055000 445.820000 246.320000 446.300000 ;
+ RECT 425.220000 347.010000 426.320000 543.580000 ;
+ RECT 380.220000 347.010000 381.320000 543.580000 ;
+ RECT 438.030000 345.760000 439.030000 546.020000 ;
+ RECT 335.220000 347.010000 336.320000 543.580000 ;
+ RECT 290.220000 347.010000 291.320000 543.580000 ;
+ RECT 245.220000 347.010000 246.320000 543.580000 ;
+ RECT 241.390000 345.760000 242.390000 546.020000 ;
+ LAYER met3 ;
+ RECT 425.220000 538.300000 426.320000 538.780000 ;
+ RECT 438.030000 538.300000 439.030000 538.780000 ;
+ RECT 438.030000 527.420000 439.030000 527.900000 ;
+ RECT 438.030000 521.980000 439.030000 522.460000 ;
+ RECT 438.030000 532.860000 439.030000 533.340000 ;
+ RECT 425.220000 532.860000 426.320000 533.340000 ;
+ RECT 425.220000 527.420000 426.320000 527.900000 ;
+ RECT 425.220000 521.980000 426.320000 522.460000 ;
+ RECT 425.220000 511.100000 426.320000 511.580000 ;
+ RECT 425.220000 516.540000 426.320000 517.020000 ;
+ RECT 438.030000 511.100000 439.030000 511.580000 ;
+ RECT 438.030000 516.540000 439.030000 517.020000 ;
+ RECT 425.220000 500.220000 426.320000 500.700000 ;
+ RECT 425.220000 505.660000 426.320000 506.140000 ;
+ RECT 438.030000 500.220000 439.030000 500.700000 ;
+ RECT 438.030000 505.660000 439.030000 506.140000 ;
+ RECT 380.220000 521.980000 381.320000 522.460000 ;
+ RECT 380.220000 527.420000 381.320000 527.900000 ;
+ RECT 380.220000 532.860000 381.320000 533.340000 ;
+ RECT 380.220000 538.300000 381.320000 538.780000 ;
+ RECT 380.220000 505.660000 381.320000 506.140000 ;
+ RECT 380.220000 500.220000 381.320000 500.700000 ;
+ RECT 380.220000 511.100000 381.320000 511.580000 ;
+ RECT 380.220000 516.540000 381.320000 517.020000 ;
+ RECT 438.030000 489.340000 439.030000 489.820000 ;
+ RECT 438.030000 483.900000 439.030000 484.380000 ;
+ RECT 438.030000 494.780000 439.030000 495.260000 ;
+ RECT 425.220000 494.780000 426.320000 495.260000 ;
+ RECT 425.220000 489.340000 426.320000 489.820000 ;
+ RECT 425.220000 483.900000 426.320000 484.380000 ;
+ RECT 425.220000 473.020000 426.320000 473.500000 ;
+ RECT 425.220000 478.460000 426.320000 478.940000 ;
+ RECT 438.030000 473.020000 439.030000 473.500000 ;
+ RECT 438.030000 478.460000 439.030000 478.940000 ;
+ RECT 438.030000 462.140000 439.030000 462.620000 ;
+ RECT 438.030000 467.580000 439.030000 468.060000 ;
+ RECT 425.220000 467.580000 426.320000 468.060000 ;
+ RECT 425.220000 462.140000 426.320000 462.620000 ;
+ RECT 425.220000 451.260000 426.320000 451.740000 ;
+ RECT 425.220000 456.700000 426.320000 457.180000 ;
+ RECT 438.030000 451.260000 439.030000 451.740000 ;
+ RECT 438.030000 456.700000 439.030000 457.180000 ;
+ RECT 380.220000 473.020000 381.320000 473.500000 ;
+ RECT 380.220000 478.460000 381.320000 478.940000 ;
+ RECT 380.220000 483.900000 381.320000 484.380000 ;
+ RECT 380.220000 489.340000 381.320000 489.820000 ;
+ RECT 380.220000 494.780000 381.320000 495.260000 ;
+ RECT 380.220000 451.260000 381.320000 451.740000 ;
+ RECT 380.220000 456.700000 381.320000 457.180000 ;
+ RECT 380.220000 462.140000 381.320000 462.620000 ;
+ RECT 380.220000 467.580000 381.320000 468.060000 ;
+ RECT 335.220000 527.420000 336.320000 527.900000 ;
+ RECT 335.220000 521.980000 336.320000 522.460000 ;
+ RECT 335.220000 532.860000 336.320000 533.340000 ;
+ RECT 335.220000 538.300000 336.320000 538.780000 ;
+ RECT 290.220000 521.980000 291.320000 522.460000 ;
+ RECT 290.220000 527.420000 291.320000 527.900000 ;
+ RECT 290.220000 532.860000 291.320000 533.340000 ;
+ RECT 290.220000 538.300000 291.320000 538.780000 ;
+ RECT 335.220000 500.220000 336.320000 500.700000 ;
+ RECT 335.220000 505.660000 336.320000 506.140000 ;
+ RECT 335.220000 511.100000 336.320000 511.580000 ;
+ RECT 335.220000 516.540000 336.320000 517.020000 ;
+ RECT 290.220000 500.220000 291.320000 500.700000 ;
+ RECT 290.220000 505.660000 291.320000 506.140000 ;
+ RECT 290.220000 511.100000 291.320000 511.580000 ;
+ RECT 290.220000 516.540000 291.320000 517.020000 ;
+ RECT 241.390000 538.300000 242.390000 538.780000 ;
+ RECT 245.055000 538.300000 246.320000 538.780000 ;
+ RECT 241.390000 527.420000 242.390000 527.900000 ;
+ RECT 245.055000 527.420000 246.320000 527.900000 ;
+ RECT 241.390000 532.860000 242.390000 533.340000 ;
+ RECT 245.055000 532.860000 246.320000 533.340000 ;
+ RECT 241.390000 521.980000 242.390000 522.460000 ;
+ RECT 245.055000 521.980000 246.320000 522.460000 ;
+ RECT 241.390000 516.540000 242.390000 517.020000 ;
+ RECT 245.055000 516.540000 246.320000 517.020000 ;
+ RECT 241.390000 511.100000 242.390000 511.580000 ;
+ RECT 245.055000 511.100000 246.320000 511.580000 ;
+ RECT 241.390000 505.660000 242.390000 506.140000 ;
+ RECT 245.055000 505.660000 246.320000 506.140000 ;
+ RECT 241.390000 500.220000 242.390000 500.700000 ;
+ RECT 245.055000 500.220000 246.320000 500.700000 ;
+ RECT 335.220000 473.020000 336.320000 473.500000 ;
+ RECT 335.220000 478.460000 336.320000 478.940000 ;
+ RECT 335.220000 483.900000 336.320000 484.380000 ;
+ RECT 335.220000 489.340000 336.320000 489.820000 ;
+ RECT 335.220000 494.780000 336.320000 495.260000 ;
+ RECT 290.220000 473.020000 291.320000 473.500000 ;
+ RECT 290.220000 478.460000 291.320000 478.940000 ;
+ RECT 290.220000 483.900000 291.320000 484.380000 ;
+ RECT 290.220000 489.340000 291.320000 489.820000 ;
+ RECT 290.220000 494.780000 291.320000 495.260000 ;
+ RECT 335.220000 451.260000 336.320000 451.740000 ;
+ RECT 335.220000 456.700000 336.320000 457.180000 ;
+ RECT 335.220000 462.140000 336.320000 462.620000 ;
+ RECT 335.220000 467.580000 336.320000 468.060000 ;
+ RECT 290.220000 451.260000 291.320000 451.740000 ;
+ RECT 290.220000 456.700000 291.320000 457.180000 ;
+ RECT 290.220000 462.140000 291.320000 462.620000 ;
+ RECT 290.220000 467.580000 291.320000 468.060000 ;
+ RECT 241.390000 494.780000 242.390000 495.260000 ;
+ RECT 245.055000 494.780000 246.320000 495.260000 ;
+ RECT 241.390000 483.900000 242.390000 484.380000 ;
+ RECT 245.055000 483.900000 246.320000 484.380000 ;
+ RECT 241.390000 489.340000 242.390000 489.820000 ;
+ RECT 245.055000 489.340000 246.320000 489.820000 ;
+ RECT 241.390000 478.460000 242.390000 478.940000 ;
+ RECT 245.055000 478.460000 246.320000 478.940000 ;
+ RECT 241.390000 473.020000 242.390000 473.500000 ;
+ RECT 245.055000 473.020000 246.320000 473.500000 ;
+ RECT 241.390000 467.580000 242.390000 468.060000 ;
+ RECT 245.055000 467.580000 246.320000 468.060000 ;
+ RECT 241.390000 462.140000 242.390000 462.620000 ;
+ RECT 245.055000 462.140000 246.320000 462.620000 ;
+ RECT 241.390000 456.700000 242.390000 457.180000 ;
+ RECT 245.055000 456.700000 246.320000 457.180000 ;
+ RECT 241.390000 451.260000 242.390000 451.740000 ;
+ RECT 245.055000 451.260000 246.320000 451.740000 ;
+ RECT 425.220000 434.940000 426.320000 435.420000 ;
+ RECT 425.220000 440.380000 426.320000 440.860000 ;
+ RECT 438.030000 434.940000 439.030000 435.420000 ;
+ RECT 438.030000 440.380000 439.030000 440.860000 ;
+ RECT 438.030000 424.060000 439.030000 424.540000 ;
+ RECT 438.030000 429.500000 439.030000 429.980000 ;
+ RECT 425.220000 429.500000 426.320000 429.980000 ;
+ RECT 425.220000 424.060000 426.320000 424.540000 ;
+ RECT 425.220000 413.180000 426.320000 413.660000 ;
+ RECT 425.220000 418.620000 426.320000 419.100000 ;
+ RECT 438.030000 413.180000 439.030000 413.660000 ;
+ RECT 438.030000 418.620000 439.030000 419.100000 ;
+ RECT 438.030000 402.300000 439.030000 402.780000 ;
+ RECT 438.030000 396.860000 439.030000 397.340000 ;
+ RECT 438.030000 407.740000 439.030000 408.220000 ;
+ RECT 425.220000 407.740000 426.320000 408.220000 ;
+ RECT 425.220000 402.300000 426.320000 402.780000 ;
+ RECT 425.220000 396.860000 426.320000 397.340000 ;
+ RECT 380.220000 424.060000 381.320000 424.540000 ;
+ RECT 380.220000 429.500000 381.320000 429.980000 ;
+ RECT 380.220000 434.940000 381.320000 435.420000 ;
+ RECT 380.220000 440.380000 381.320000 440.860000 ;
+ RECT 380.220000 396.860000 381.320000 397.340000 ;
+ RECT 380.220000 402.300000 381.320000 402.780000 ;
+ RECT 380.220000 407.740000 381.320000 408.220000 ;
+ RECT 380.220000 413.180000 381.320000 413.660000 ;
+ RECT 380.220000 418.620000 381.320000 419.100000 ;
+ RECT 425.220000 385.980000 426.320000 386.460000 ;
+ RECT 425.220000 391.420000 426.320000 391.900000 ;
+ RECT 438.030000 385.980000 439.030000 386.460000 ;
+ RECT 438.030000 391.420000 439.030000 391.900000 ;
+ RECT 425.220000 375.100000 426.320000 375.580000 ;
+ RECT 425.220000 380.540000 426.320000 381.020000 ;
+ RECT 438.030000 375.100000 439.030000 375.580000 ;
+ RECT 438.030000 380.540000 439.030000 381.020000 ;
+ RECT 438.030000 364.220000 439.030000 364.700000 ;
+ RECT 438.030000 358.780000 439.030000 359.260000 ;
+ RECT 438.030000 369.660000 439.030000 370.140000 ;
+ RECT 425.220000 369.660000 426.320000 370.140000 ;
+ RECT 425.220000 364.220000 426.320000 364.700000 ;
+ RECT 425.220000 358.780000 426.320000 359.260000 ;
+ RECT 425.220000 353.340000 426.320000 353.820000 ;
+ RECT 438.030000 353.340000 439.030000 353.820000 ;
+ RECT 380.220000 375.100000 381.320000 375.580000 ;
+ RECT 380.220000 380.540000 381.320000 381.020000 ;
+ RECT 380.220000 385.980000 381.320000 386.460000 ;
+ RECT 380.220000 391.420000 381.320000 391.900000 ;
+ RECT 380.220000 353.340000 381.320000 353.820000 ;
+ RECT 380.220000 358.780000 381.320000 359.260000 ;
+ RECT 380.220000 364.220000 381.320000 364.700000 ;
+ RECT 380.220000 369.660000 381.320000 370.140000 ;
+ RECT 335.220000 424.060000 336.320000 424.540000 ;
+ RECT 335.220000 429.500000 336.320000 429.980000 ;
+ RECT 335.220000 434.940000 336.320000 435.420000 ;
+ RECT 335.220000 440.380000 336.320000 440.860000 ;
+ RECT 290.220000 424.060000 291.320000 424.540000 ;
+ RECT 290.220000 429.500000 291.320000 429.980000 ;
+ RECT 290.220000 434.940000 291.320000 435.420000 ;
+ RECT 290.220000 440.380000 291.320000 440.860000 ;
+ RECT 335.220000 396.860000 336.320000 397.340000 ;
+ RECT 335.220000 402.300000 336.320000 402.780000 ;
+ RECT 335.220000 407.740000 336.320000 408.220000 ;
+ RECT 335.220000 413.180000 336.320000 413.660000 ;
+ RECT 335.220000 418.620000 336.320000 419.100000 ;
+ RECT 290.220000 396.860000 291.320000 397.340000 ;
+ RECT 290.220000 402.300000 291.320000 402.780000 ;
+ RECT 290.220000 407.740000 291.320000 408.220000 ;
+ RECT 290.220000 413.180000 291.320000 413.660000 ;
+ RECT 290.220000 418.620000 291.320000 419.100000 ;
+ RECT 241.390000 440.380000 242.390000 440.860000 ;
+ RECT 245.055000 440.380000 246.320000 440.860000 ;
+ RECT 241.390000 434.940000 242.390000 435.420000 ;
+ RECT 245.055000 434.940000 246.320000 435.420000 ;
+ RECT 241.390000 429.500000 242.390000 429.980000 ;
+ RECT 245.055000 429.500000 246.320000 429.980000 ;
+ RECT 241.390000 424.060000 242.390000 424.540000 ;
+ RECT 245.055000 424.060000 246.320000 424.540000 ;
+ RECT 241.390000 418.620000 242.390000 419.100000 ;
+ RECT 245.055000 418.620000 246.320000 419.100000 ;
+ RECT 241.390000 413.180000 242.390000 413.660000 ;
+ RECT 245.055000 413.180000 246.320000 413.660000 ;
+ RECT 241.390000 402.300000 242.390000 402.780000 ;
+ RECT 245.055000 402.300000 246.320000 402.780000 ;
+ RECT 241.390000 407.740000 242.390000 408.220000 ;
+ RECT 245.055000 407.740000 246.320000 408.220000 ;
+ RECT 241.390000 396.860000 242.390000 397.340000 ;
+ RECT 245.055000 396.860000 246.320000 397.340000 ;
+ RECT 335.220000 375.100000 336.320000 375.580000 ;
+ RECT 335.220000 380.540000 336.320000 381.020000 ;
+ RECT 335.220000 385.980000 336.320000 386.460000 ;
+ RECT 335.220000 391.420000 336.320000 391.900000 ;
+ RECT 290.220000 375.100000 291.320000 375.580000 ;
+ RECT 290.220000 380.540000 291.320000 381.020000 ;
+ RECT 290.220000 385.980000 291.320000 386.460000 ;
+ RECT 290.220000 391.420000 291.320000 391.900000 ;
+ RECT 335.220000 353.340000 336.320000 353.820000 ;
+ RECT 335.220000 358.780000 336.320000 359.260000 ;
+ RECT 335.220000 364.220000 336.320000 364.700000 ;
+ RECT 335.220000 369.660000 336.320000 370.140000 ;
+ RECT 290.220000 353.340000 291.320000 353.820000 ;
+ RECT 290.220000 358.780000 291.320000 359.260000 ;
+ RECT 290.220000 364.220000 291.320000 364.700000 ;
+ RECT 290.220000 369.660000 291.320000 370.140000 ;
+ RECT 241.390000 391.420000 242.390000 391.900000 ;
+ RECT 245.055000 391.420000 246.320000 391.900000 ;
+ RECT 241.390000 385.980000 242.390000 386.460000 ;
+ RECT 245.055000 385.980000 246.320000 386.460000 ;
+ RECT 241.390000 380.540000 242.390000 381.020000 ;
+ RECT 245.055000 380.540000 246.320000 381.020000 ;
+ RECT 241.390000 375.100000 242.390000 375.580000 ;
+ RECT 245.055000 375.100000 246.320000 375.580000 ;
+ RECT 241.390000 369.660000 242.390000 370.140000 ;
+ RECT 245.055000 369.660000 246.320000 370.140000 ;
+ RECT 241.390000 358.780000 242.390000 359.260000 ;
+ RECT 245.055000 358.780000 246.320000 359.260000 ;
+ RECT 241.390000 364.220000 242.390000 364.700000 ;
+ RECT 245.055000 364.220000 246.320000 364.700000 ;
+ RECT 241.390000 353.340000 242.390000 353.820000 ;
+ RECT 245.055000 353.340000 246.320000 353.820000 ;
+ RECT 380.220000 445.820000 381.320000 446.300000 ;
+ RECT 425.220000 445.820000 426.320000 446.300000 ;
+ RECT 438.030000 445.820000 439.030000 446.300000 ;
+ RECT 290.220000 445.820000 291.320000 446.300000 ;
+ RECT 335.220000 445.820000 336.320000 446.300000 ;
+ RECT 241.390000 445.820000 242.390000 446.300000 ;
+ RECT 245.055000 445.820000 246.320000 446.300000 ;
+ RECT 240.160000 542.580000 440.260000 543.580000 ;
+ RECT 240.160000 347.010000 440.260000 348.010000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 345.760000 242.390000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 545.020000 242.390000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 345.760000 439.030000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 545.020000 439.030000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 347.010000 241.160000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 347.010000 440.260000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 542.580000 241.160000 543.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 542.580000 440.260000 543.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 338.040000 246.320000 338.520000 ;
+ RECT 245.055000 327.160000 246.320000 327.640000 ;
+ RECT 245.055000 332.600000 246.320000 333.080000 ;
+ RECT 245.055000 321.720000 246.320000 322.200000 ;
+ RECT 245.055000 316.280000 246.320000 316.760000 ;
+ RECT 245.055000 310.840000 246.320000 311.320000 ;
+ RECT 245.055000 305.400000 246.320000 305.880000 ;
+ RECT 245.055000 299.960000 246.320000 300.440000 ;
+ RECT 245.055000 294.520000 246.320000 295.000000 ;
+ RECT 245.055000 283.640000 246.320000 284.120000 ;
+ RECT 245.055000 289.080000 246.320000 289.560000 ;
+ RECT 245.055000 278.200000 246.320000 278.680000 ;
+ RECT 245.055000 272.760000 246.320000 273.240000 ;
+ RECT 245.055000 267.320000 246.320000 267.800000 ;
+ RECT 245.055000 261.880000 246.320000 262.360000 ;
+ RECT 245.055000 256.440000 246.320000 256.920000 ;
+ RECT 245.055000 251.000000 246.320000 251.480000 ;
+ RECT 245.055000 240.120000 246.320000 240.600000 ;
+ RECT 245.055000 234.680000 246.320000 235.160000 ;
+ RECT 245.055000 229.240000 246.320000 229.720000 ;
+ RECT 245.055000 223.800000 246.320000 224.280000 ;
+ RECT 245.055000 218.360000 246.320000 218.840000 ;
+ RECT 245.055000 212.920000 246.320000 213.400000 ;
+ RECT 245.055000 202.040000 246.320000 202.520000 ;
+ RECT 245.055000 207.480000 246.320000 207.960000 ;
+ RECT 245.055000 196.600000 246.320000 197.080000 ;
+ RECT 245.055000 191.160000 246.320000 191.640000 ;
+ RECT 245.055000 185.720000 246.320000 186.200000 ;
+ RECT 245.055000 180.280000 246.320000 180.760000 ;
+ RECT 245.055000 174.840000 246.320000 175.320000 ;
+ RECT 245.055000 169.400000 246.320000 169.880000 ;
+ RECT 245.055000 158.520000 246.320000 159.000000 ;
+ RECT 245.055000 163.960000 246.320000 164.440000 ;
+ RECT 245.055000 153.080000 246.320000 153.560000 ;
+ RECT 245.055000 245.560000 246.320000 246.040000 ;
+ RECT 425.220000 146.750000 426.320000 343.320000 ;
+ RECT 380.220000 146.750000 381.320000 343.320000 ;
+ RECT 438.030000 145.500000 439.030000 345.760000 ;
+ RECT 335.220000 146.750000 336.320000 343.320000 ;
+ RECT 290.220000 146.750000 291.320000 343.320000 ;
+ RECT 245.220000 146.750000 246.320000 343.320000 ;
+ RECT 241.390000 145.500000 242.390000 345.760000 ;
+ LAYER met3 ;
+ RECT 425.220000 338.040000 426.320000 338.520000 ;
+ RECT 438.030000 338.040000 439.030000 338.520000 ;
+ RECT 438.030000 327.160000 439.030000 327.640000 ;
+ RECT 438.030000 321.720000 439.030000 322.200000 ;
+ RECT 438.030000 332.600000 439.030000 333.080000 ;
+ RECT 425.220000 332.600000 426.320000 333.080000 ;
+ RECT 425.220000 327.160000 426.320000 327.640000 ;
+ RECT 425.220000 321.720000 426.320000 322.200000 ;
+ RECT 425.220000 310.840000 426.320000 311.320000 ;
+ RECT 425.220000 316.280000 426.320000 316.760000 ;
+ RECT 438.030000 310.840000 439.030000 311.320000 ;
+ RECT 438.030000 316.280000 439.030000 316.760000 ;
+ RECT 425.220000 299.960000 426.320000 300.440000 ;
+ RECT 425.220000 305.400000 426.320000 305.880000 ;
+ RECT 438.030000 299.960000 439.030000 300.440000 ;
+ RECT 438.030000 305.400000 439.030000 305.880000 ;
+ RECT 380.220000 321.720000 381.320000 322.200000 ;
+ RECT 380.220000 327.160000 381.320000 327.640000 ;
+ RECT 380.220000 332.600000 381.320000 333.080000 ;
+ RECT 380.220000 338.040000 381.320000 338.520000 ;
+ RECT 380.220000 305.400000 381.320000 305.880000 ;
+ RECT 380.220000 299.960000 381.320000 300.440000 ;
+ RECT 380.220000 310.840000 381.320000 311.320000 ;
+ RECT 380.220000 316.280000 381.320000 316.760000 ;
+ RECT 438.030000 289.080000 439.030000 289.560000 ;
+ RECT 438.030000 283.640000 439.030000 284.120000 ;
+ RECT 438.030000 294.520000 439.030000 295.000000 ;
+ RECT 425.220000 294.520000 426.320000 295.000000 ;
+ RECT 425.220000 289.080000 426.320000 289.560000 ;
+ RECT 425.220000 283.640000 426.320000 284.120000 ;
+ RECT 425.220000 272.760000 426.320000 273.240000 ;
+ RECT 425.220000 278.200000 426.320000 278.680000 ;
+ RECT 438.030000 272.760000 439.030000 273.240000 ;
+ RECT 438.030000 278.200000 439.030000 278.680000 ;
+ RECT 438.030000 261.880000 439.030000 262.360000 ;
+ RECT 438.030000 267.320000 439.030000 267.800000 ;
+ RECT 425.220000 267.320000 426.320000 267.800000 ;
+ RECT 425.220000 261.880000 426.320000 262.360000 ;
+ RECT 425.220000 251.000000 426.320000 251.480000 ;
+ RECT 425.220000 256.440000 426.320000 256.920000 ;
+ RECT 438.030000 251.000000 439.030000 251.480000 ;
+ RECT 438.030000 256.440000 439.030000 256.920000 ;
+ RECT 380.220000 272.760000 381.320000 273.240000 ;
+ RECT 380.220000 278.200000 381.320000 278.680000 ;
+ RECT 380.220000 283.640000 381.320000 284.120000 ;
+ RECT 380.220000 289.080000 381.320000 289.560000 ;
+ RECT 380.220000 294.520000 381.320000 295.000000 ;
+ RECT 380.220000 251.000000 381.320000 251.480000 ;
+ RECT 380.220000 256.440000 381.320000 256.920000 ;
+ RECT 380.220000 261.880000 381.320000 262.360000 ;
+ RECT 380.220000 267.320000 381.320000 267.800000 ;
+ RECT 335.220000 327.160000 336.320000 327.640000 ;
+ RECT 335.220000 321.720000 336.320000 322.200000 ;
+ RECT 335.220000 332.600000 336.320000 333.080000 ;
+ RECT 335.220000 338.040000 336.320000 338.520000 ;
+ RECT 290.220000 321.720000 291.320000 322.200000 ;
+ RECT 290.220000 327.160000 291.320000 327.640000 ;
+ RECT 290.220000 332.600000 291.320000 333.080000 ;
+ RECT 290.220000 338.040000 291.320000 338.520000 ;
+ RECT 335.220000 299.960000 336.320000 300.440000 ;
+ RECT 335.220000 305.400000 336.320000 305.880000 ;
+ RECT 335.220000 310.840000 336.320000 311.320000 ;
+ RECT 335.220000 316.280000 336.320000 316.760000 ;
+ RECT 290.220000 299.960000 291.320000 300.440000 ;
+ RECT 290.220000 305.400000 291.320000 305.880000 ;
+ RECT 290.220000 310.840000 291.320000 311.320000 ;
+ RECT 290.220000 316.280000 291.320000 316.760000 ;
+ RECT 241.390000 338.040000 242.390000 338.520000 ;
+ RECT 245.055000 338.040000 246.320000 338.520000 ;
+ RECT 241.390000 327.160000 242.390000 327.640000 ;
+ RECT 245.055000 327.160000 246.320000 327.640000 ;
+ RECT 241.390000 332.600000 242.390000 333.080000 ;
+ RECT 245.055000 332.600000 246.320000 333.080000 ;
+ RECT 241.390000 321.720000 242.390000 322.200000 ;
+ RECT 245.055000 321.720000 246.320000 322.200000 ;
+ RECT 241.390000 316.280000 242.390000 316.760000 ;
+ RECT 245.055000 316.280000 246.320000 316.760000 ;
+ RECT 241.390000 310.840000 242.390000 311.320000 ;
+ RECT 245.055000 310.840000 246.320000 311.320000 ;
+ RECT 241.390000 305.400000 242.390000 305.880000 ;
+ RECT 245.055000 305.400000 246.320000 305.880000 ;
+ RECT 241.390000 299.960000 242.390000 300.440000 ;
+ RECT 245.055000 299.960000 246.320000 300.440000 ;
+ RECT 335.220000 272.760000 336.320000 273.240000 ;
+ RECT 335.220000 278.200000 336.320000 278.680000 ;
+ RECT 335.220000 283.640000 336.320000 284.120000 ;
+ RECT 335.220000 289.080000 336.320000 289.560000 ;
+ RECT 335.220000 294.520000 336.320000 295.000000 ;
+ RECT 290.220000 272.760000 291.320000 273.240000 ;
+ RECT 290.220000 278.200000 291.320000 278.680000 ;
+ RECT 290.220000 283.640000 291.320000 284.120000 ;
+ RECT 290.220000 289.080000 291.320000 289.560000 ;
+ RECT 290.220000 294.520000 291.320000 295.000000 ;
+ RECT 335.220000 251.000000 336.320000 251.480000 ;
+ RECT 335.220000 256.440000 336.320000 256.920000 ;
+ RECT 335.220000 261.880000 336.320000 262.360000 ;
+ RECT 335.220000 267.320000 336.320000 267.800000 ;
+ RECT 290.220000 251.000000 291.320000 251.480000 ;
+ RECT 290.220000 256.440000 291.320000 256.920000 ;
+ RECT 290.220000 261.880000 291.320000 262.360000 ;
+ RECT 290.220000 267.320000 291.320000 267.800000 ;
+ RECT 241.390000 294.520000 242.390000 295.000000 ;
+ RECT 245.055000 294.520000 246.320000 295.000000 ;
+ RECT 241.390000 283.640000 242.390000 284.120000 ;
+ RECT 245.055000 283.640000 246.320000 284.120000 ;
+ RECT 241.390000 289.080000 242.390000 289.560000 ;
+ RECT 245.055000 289.080000 246.320000 289.560000 ;
+ RECT 241.390000 278.200000 242.390000 278.680000 ;
+ RECT 245.055000 278.200000 246.320000 278.680000 ;
+ RECT 241.390000 272.760000 242.390000 273.240000 ;
+ RECT 245.055000 272.760000 246.320000 273.240000 ;
+ RECT 241.390000 267.320000 242.390000 267.800000 ;
+ RECT 245.055000 267.320000 246.320000 267.800000 ;
+ RECT 241.390000 261.880000 242.390000 262.360000 ;
+ RECT 245.055000 261.880000 246.320000 262.360000 ;
+ RECT 241.390000 256.440000 242.390000 256.920000 ;
+ RECT 245.055000 256.440000 246.320000 256.920000 ;
+ RECT 241.390000 251.000000 242.390000 251.480000 ;
+ RECT 245.055000 251.000000 246.320000 251.480000 ;
+ RECT 425.220000 234.680000 426.320000 235.160000 ;
+ RECT 425.220000 240.120000 426.320000 240.600000 ;
+ RECT 438.030000 234.680000 439.030000 235.160000 ;
+ RECT 438.030000 240.120000 439.030000 240.600000 ;
+ RECT 438.030000 223.800000 439.030000 224.280000 ;
+ RECT 438.030000 229.240000 439.030000 229.720000 ;
+ RECT 425.220000 229.240000 426.320000 229.720000 ;
+ RECT 425.220000 223.800000 426.320000 224.280000 ;
+ RECT 425.220000 212.920000 426.320000 213.400000 ;
+ RECT 425.220000 218.360000 426.320000 218.840000 ;
+ RECT 438.030000 212.920000 439.030000 213.400000 ;
+ RECT 438.030000 218.360000 439.030000 218.840000 ;
+ RECT 438.030000 202.040000 439.030000 202.520000 ;
+ RECT 438.030000 196.600000 439.030000 197.080000 ;
+ RECT 438.030000 207.480000 439.030000 207.960000 ;
+ RECT 425.220000 207.480000 426.320000 207.960000 ;
+ RECT 425.220000 202.040000 426.320000 202.520000 ;
+ RECT 425.220000 196.600000 426.320000 197.080000 ;
+ RECT 380.220000 223.800000 381.320000 224.280000 ;
+ RECT 380.220000 229.240000 381.320000 229.720000 ;
+ RECT 380.220000 234.680000 381.320000 235.160000 ;
+ RECT 380.220000 240.120000 381.320000 240.600000 ;
+ RECT 380.220000 196.600000 381.320000 197.080000 ;
+ RECT 380.220000 202.040000 381.320000 202.520000 ;
+ RECT 380.220000 207.480000 381.320000 207.960000 ;
+ RECT 380.220000 212.920000 381.320000 213.400000 ;
+ RECT 380.220000 218.360000 381.320000 218.840000 ;
+ RECT 425.220000 185.720000 426.320000 186.200000 ;
+ RECT 425.220000 191.160000 426.320000 191.640000 ;
+ RECT 438.030000 185.720000 439.030000 186.200000 ;
+ RECT 438.030000 191.160000 439.030000 191.640000 ;
+ RECT 425.220000 174.840000 426.320000 175.320000 ;
+ RECT 425.220000 180.280000 426.320000 180.760000 ;
+ RECT 438.030000 174.840000 439.030000 175.320000 ;
+ RECT 438.030000 180.280000 439.030000 180.760000 ;
+ RECT 438.030000 163.960000 439.030000 164.440000 ;
+ RECT 438.030000 158.520000 439.030000 159.000000 ;
+ RECT 438.030000 169.400000 439.030000 169.880000 ;
+ RECT 425.220000 169.400000 426.320000 169.880000 ;
+ RECT 425.220000 163.960000 426.320000 164.440000 ;
+ RECT 425.220000 158.520000 426.320000 159.000000 ;
+ RECT 425.220000 153.080000 426.320000 153.560000 ;
+ RECT 438.030000 153.080000 439.030000 153.560000 ;
+ RECT 380.220000 174.840000 381.320000 175.320000 ;
+ RECT 380.220000 180.280000 381.320000 180.760000 ;
+ RECT 380.220000 185.720000 381.320000 186.200000 ;
+ RECT 380.220000 191.160000 381.320000 191.640000 ;
+ RECT 380.220000 153.080000 381.320000 153.560000 ;
+ RECT 380.220000 158.520000 381.320000 159.000000 ;
+ RECT 380.220000 163.960000 381.320000 164.440000 ;
+ RECT 380.220000 169.400000 381.320000 169.880000 ;
+ RECT 335.220000 223.800000 336.320000 224.280000 ;
+ RECT 335.220000 229.240000 336.320000 229.720000 ;
+ RECT 335.220000 234.680000 336.320000 235.160000 ;
+ RECT 335.220000 240.120000 336.320000 240.600000 ;
+ RECT 290.220000 223.800000 291.320000 224.280000 ;
+ RECT 290.220000 229.240000 291.320000 229.720000 ;
+ RECT 290.220000 234.680000 291.320000 235.160000 ;
+ RECT 290.220000 240.120000 291.320000 240.600000 ;
+ RECT 335.220000 196.600000 336.320000 197.080000 ;
+ RECT 335.220000 202.040000 336.320000 202.520000 ;
+ RECT 335.220000 207.480000 336.320000 207.960000 ;
+ RECT 335.220000 212.920000 336.320000 213.400000 ;
+ RECT 335.220000 218.360000 336.320000 218.840000 ;
+ RECT 290.220000 196.600000 291.320000 197.080000 ;
+ RECT 290.220000 202.040000 291.320000 202.520000 ;
+ RECT 290.220000 207.480000 291.320000 207.960000 ;
+ RECT 290.220000 212.920000 291.320000 213.400000 ;
+ RECT 290.220000 218.360000 291.320000 218.840000 ;
+ RECT 241.390000 240.120000 242.390000 240.600000 ;
+ RECT 245.055000 240.120000 246.320000 240.600000 ;
+ RECT 241.390000 234.680000 242.390000 235.160000 ;
+ RECT 245.055000 234.680000 246.320000 235.160000 ;
+ RECT 241.390000 229.240000 242.390000 229.720000 ;
+ RECT 245.055000 229.240000 246.320000 229.720000 ;
+ RECT 241.390000 223.800000 242.390000 224.280000 ;
+ RECT 245.055000 223.800000 246.320000 224.280000 ;
+ RECT 241.390000 218.360000 242.390000 218.840000 ;
+ RECT 245.055000 218.360000 246.320000 218.840000 ;
+ RECT 241.390000 212.920000 242.390000 213.400000 ;
+ RECT 245.055000 212.920000 246.320000 213.400000 ;
+ RECT 241.390000 202.040000 242.390000 202.520000 ;
+ RECT 245.055000 202.040000 246.320000 202.520000 ;
+ RECT 241.390000 207.480000 242.390000 207.960000 ;
+ RECT 245.055000 207.480000 246.320000 207.960000 ;
+ RECT 241.390000 196.600000 242.390000 197.080000 ;
+ RECT 245.055000 196.600000 246.320000 197.080000 ;
+ RECT 335.220000 174.840000 336.320000 175.320000 ;
+ RECT 335.220000 180.280000 336.320000 180.760000 ;
+ RECT 335.220000 185.720000 336.320000 186.200000 ;
+ RECT 335.220000 191.160000 336.320000 191.640000 ;
+ RECT 290.220000 174.840000 291.320000 175.320000 ;
+ RECT 290.220000 180.280000 291.320000 180.760000 ;
+ RECT 290.220000 185.720000 291.320000 186.200000 ;
+ RECT 290.220000 191.160000 291.320000 191.640000 ;
+ RECT 335.220000 153.080000 336.320000 153.560000 ;
+ RECT 335.220000 158.520000 336.320000 159.000000 ;
+ RECT 335.220000 163.960000 336.320000 164.440000 ;
+ RECT 335.220000 169.400000 336.320000 169.880000 ;
+ RECT 290.220000 153.080000 291.320000 153.560000 ;
+ RECT 290.220000 158.520000 291.320000 159.000000 ;
+ RECT 290.220000 163.960000 291.320000 164.440000 ;
+ RECT 290.220000 169.400000 291.320000 169.880000 ;
+ RECT 241.390000 191.160000 242.390000 191.640000 ;
+ RECT 245.055000 191.160000 246.320000 191.640000 ;
+ RECT 241.390000 185.720000 242.390000 186.200000 ;
+ RECT 245.055000 185.720000 246.320000 186.200000 ;
+ RECT 241.390000 180.280000 242.390000 180.760000 ;
+ RECT 245.055000 180.280000 246.320000 180.760000 ;
+ RECT 241.390000 174.840000 242.390000 175.320000 ;
+ RECT 245.055000 174.840000 246.320000 175.320000 ;
+ RECT 241.390000 169.400000 242.390000 169.880000 ;
+ RECT 245.055000 169.400000 246.320000 169.880000 ;
+ RECT 241.390000 158.520000 242.390000 159.000000 ;
+ RECT 245.055000 158.520000 246.320000 159.000000 ;
+ RECT 241.390000 163.960000 242.390000 164.440000 ;
+ RECT 245.055000 163.960000 246.320000 164.440000 ;
+ RECT 241.390000 153.080000 242.390000 153.560000 ;
+ RECT 245.055000 153.080000 246.320000 153.560000 ;
+ RECT 380.220000 245.560000 381.320000 246.040000 ;
+ RECT 425.220000 245.560000 426.320000 246.040000 ;
+ RECT 438.030000 245.560000 439.030000 246.040000 ;
+ RECT 290.220000 245.560000 291.320000 246.040000 ;
+ RECT 335.220000 245.560000 336.320000 246.040000 ;
+ RECT 241.390000 245.560000 242.390000 246.040000 ;
+ RECT 245.055000 245.560000 246.320000 246.040000 ;
+ RECT 240.160000 342.320000 440.260000 343.320000 ;
+ RECT 240.160000 146.750000 440.260000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 145.500000 242.390000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 344.760000 242.390000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 145.500000 439.030000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 344.760000 439.030000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 146.750000 241.160000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 146.750000 440.260000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 342.320000 241.160000 343.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 342.320000 440.260000 343.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 139.140000 246.320000 139.620000 ;
+ RECT 245.055000 133.700000 246.320000 134.180000 ;
+ RECT 245.055000 128.260000 246.320000 128.740000 ;
+ RECT 245.055000 122.820000 246.320000 123.300000 ;
+ RECT 241.390000 115.240000 242.390000 145.500000 ;
+ RECT 438.030000 115.240000 439.030000 145.500000 ;
+ RECT 245.220000 116.490000 246.320000 143.740000 ;
+ RECT 290.220000 116.490000 291.320000 143.740000 ;
+ RECT 335.220000 116.490000 336.320000 143.740000 ;
+ RECT 380.220000 116.490000 381.320000 143.740000 ;
+ RECT 425.220000 116.490000 426.320000 143.740000 ;
+ LAYER met3 ;
+ RECT 438.030000 139.140000 439.030000 139.620000 ;
+ RECT 438.030000 133.700000 439.030000 134.180000 ;
+ RECT 425.220000 139.140000 426.320000 139.620000 ;
+ RECT 425.220000 133.700000 426.320000 134.180000 ;
+ RECT 380.220000 133.700000 381.320000 134.180000 ;
+ RECT 380.220000 139.140000 381.320000 139.620000 ;
+ RECT 335.220000 133.700000 336.320000 134.180000 ;
+ RECT 290.220000 133.700000 291.320000 134.180000 ;
+ RECT 335.220000 139.140000 336.320000 139.620000 ;
+ RECT 290.220000 139.140000 291.320000 139.620000 ;
+ RECT 245.055000 139.140000 246.320000 139.620000 ;
+ RECT 241.390000 139.140000 242.390000 139.620000 ;
+ RECT 245.055000 133.700000 246.320000 134.180000 ;
+ RECT 241.390000 133.700000 242.390000 134.180000 ;
+ RECT 438.030000 128.260000 439.030000 128.740000 ;
+ RECT 438.030000 122.820000 439.030000 123.300000 ;
+ RECT 425.220000 128.260000 426.320000 128.740000 ;
+ RECT 425.220000 122.820000 426.320000 123.300000 ;
+ RECT 380.220000 122.820000 381.320000 123.300000 ;
+ RECT 380.220000 128.260000 381.320000 128.740000 ;
+ RECT 335.220000 122.820000 336.320000 123.300000 ;
+ RECT 290.220000 122.820000 291.320000 123.300000 ;
+ RECT 335.220000 128.260000 336.320000 128.740000 ;
+ RECT 290.220000 128.260000 291.320000 128.740000 ;
+ RECT 245.055000 128.260000 246.320000 128.740000 ;
+ RECT 241.390000 128.260000 242.390000 128.740000 ;
+ RECT 245.055000 122.820000 246.320000 123.300000 ;
+ RECT 241.390000 122.820000 242.390000 123.300000 ;
+ RECT 240.160000 142.740000 440.260000 143.740000 ;
+ RECT 240.160000 116.490000 440.260000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 116.490000 241.160000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 116.490000 440.260000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 142.740000 241.160000 143.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 142.740000 440.260000 143.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 115.240000 242.390000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 144.500000 242.390000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 115.240000 439.030000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 144.500000 439.030000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 3341.940000 246.320000 3342.420000 ;
+ RECT 245.055000 3331.060000 246.320000 3331.540000 ;
+ RECT 245.055000 3336.500000 246.320000 3336.980000 ;
+ RECT 245.055000 3325.620000 246.320000 3326.100000 ;
+ RECT 245.055000 3320.180000 246.320000 3320.660000 ;
+ RECT 245.055000 3314.740000 246.320000 3315.220000 ;
+ RECT 245.055000 3309.300000 246.320000 3309.780000 ;
+ RECT 245.055000 3303.860000 246.320000 3304.340000 ;
+ RECT 245.055000 3298.420000 246.320000 3298.900000 ;
+ RECT 245.055000 3287.540000 246.320000 3288.020000 ;
+ RECT 245.055000 3292.980000 246.320000 3293.460000 ;
+ RECT 245.055000 3282.100000 246.320000 3282.580000 ;
+ RECT 245.055000 3276.660000 246.320000 3277.140000 ;
+ RECT 245.055000 3271.220000 246.320000 3271.700000 ;
+ RECT 245.055000 3265.780000 246.320000 3266.260000 ;
+ RECT 245.055000 3260.340000 246.320000 3260.820000 ;
+ RECT 245.055000 3254.900000 246.320000 3255.380000 ;
+ RECT 245.055000 3244.020000 246.320000 3244.500000 ;
+ RECT 245.055000 3238.580000 246.320000 3239.060000 ;
+ RECT 245.055000 3233.140000 246.320000 3233.620000 ;
+ RECT 245.055000 3227.700000 246.320000 3228.180000 ;
+ RECT 245.055000 3222.260000 246.320000 3222.740000 ;
+ RECT 245.055000 3216.820000 246.320000 3217.300000 ;
+ RECT 245.055000 3205.940000 246.320000 3206.420000 ;
+ RECT 245.055000 3211.380000 246.320000 3211.860000 ;
+ RECT 245.055000 3200.500000 246.320000 3200.980000 ;
+ RECT 245.055000 3195.060000 246.320000 3195.540000 ;
+ RECT 245.055000 3189.620000 246.320000 3190.100000 ;
+ RECT 245.055000 3184.180000 246.320000 3184.660000 ;
+ RECT 245.055000 3178.740000 246.320000 3179.220000 ;
+ RECT 245.055000 3173.300000 246.320000 3173.780000 ;
+ RECT 245.055000 3162.420000 246.320000 3162.900000 ;
+ RECT 245.055000 3167.860000 246.320000 3168.340000 ;
+ RECT 245.055000 3156.980000 246.320000 3157.460000 ;
+ RECT 245.055000 3249.460000 246.320000 3249.940000 ;
+ RECT 425.220000 3150.650000 426.320000 3347.220000 ;
+ RECT 380.220000 3150.650000 381.320000 3347.220000 ;
+ RECT 438.030000 3149.400000 439.030000 3349.660000 ;
+ RECT 335.220000 3150.650000 336.320000 3347.220000 ;
+ RECT 290.220000 3150.650000 291.320000 3347.220000 ;
+ RECT 245.220000 3150.650000 246.320000 3347.220000 ;
+ RECT 241.390000 3149.400000 242.390000 3349.660000 ;
+ LAYER met3 ;
+ RECT 425.220000 3341.940000 426.320000 3342.420000 ;
+ RECT 438.030000 3341.940000 439.030000 3342.420000 ;
+ RECT 438.030000 3331.060000 439.030000 3331.540000 ;
+ RECT 438.030000 3325.620000 439.030000 3326.100000 ;
+ RECT 438.030000 3336.500000 439.030000 3336.980000 ;
+ RECT 425.220000 3336.500000 426.320000 3336.980000 ;
+ RECT 425.220000 3331.060000 426.320000 3331.540000 ;
+ RECT 425.220000 3325.620000 426.320000 3326.100000 ;
+ RECT 425.220000 3314.740000 426.320000 3315.220000 ;
+ RECT 425.220000 3320.180000 426.320000 3320.660000 ;
+ RECT 438.030000 3314.740000 439.030000 3315.220000 ;
+ RECT 438.030000 3320.180000 439.030000 3320.660000 ;
+ RECT 425.220000 3303.860000 426.320000 3304.340000 ;
+ RECT 425.220000 3309.300000 426.320000 3309.780000 ;
+ RECT 438.030000 3303.860000 439.030000 3304.340000 ;
+ RECT 438.030000 3309.300000 439.030000 3309.780000 ;
+ RECT 380.220000 3325.620000 381.320000 3326.100000 ;
+ RECT 380.220000 3331.060000 381.320000 3331.540000 ;
+ RECT 380.220000 3336.500000 381.320000 3336.980000 ;
+ RECT 380.220000 3341.940000 381.320000 3342.420000 ;
+ RECT 380.220000 3309.300000 381.320000 3309.780000 ;
+ RECT 380.220000 3303.860000 381.320000 3304.340000 ;
+ RECT 380.220000 3314.740000 381.320000 3315.220000 ;
+ RECT 380.220000 3320.180000 381.320000 3320.660000 ;
+ RECT 438.030000 3292.980000 439.030000 3293.460000 ;
+ RECT 438.030000 3287.540000 439.030000 3288.020000 ;
+ RECT 438.030000 3298.420000 439.030000 3298.900000 ;
+ RECT 425.220000 3298.420000 426.320000 3298.900000 ;
+ RECT 425.220000 3292.980000 426.320000 3293.460000 ;
+ RECT 425.220000 3287.540000 426.320000 3288.020000 ;
+ RECT 425.220000 3276.660000 426.320000 3277.140000 ;
+ RECT 425.220000 3282.100000 426.320000 3282.580000 ;
+ RECT 438.030000 3276.660000 439.030000 3277.140000 ;
+ RECT 438.030000 3282.100000 439.030000 3282.580000 ;
+ RECT 438.030000 3265.780000 439.030000 3266.260000 ;
+ RECT 438.030000 3271.220000 439.030000 3271.700000 ;
+ RECT 425.220000 3271.220000 426.320000 3271.700000 ;
+ RECT 425.220000 3265.780000 426.320000 3266.260000 ;
+ RECT 425.220000 3254.900000 426.320000 3255.380000 ;
+ RECT 425.220000 3260.340000 426.320000 3260.820000 ;
+ RECT 438.030000 3254.900000 439.030000 3255.380000 ;
+ RECT 438.030000 3260.340000 439.030000 3260.820000 ;
+ RECT 380.220000 3276.660000 381.320000 3277.140000 ;
+ RECT 380.220000 3282.100000 381.320000 3282.580000 ;
+ RECT 380.220000 3287.540000 381.320000 3288.020000 ;
+ RECT 380.220000 3292.980000 381.320000 3293.460000 ;
+ RECT 380.220000 3298.420000 381.320000 3298.900000 ;
+ RECT 380.220000 3254.900000 381.320000 3255.380000 ;
+ RECT 380.220000 3260.340000 381.320000 3260.820000 ;
+ RECT 380.220000 3265.780000 381.320000 3266.260000 ;
+ RECT 380.220000 3271.220000 381.320000 3271.700000 ;
+ RECT 335.220000 3331.060000 336.320000 3331.540000 ;
+ RECT 335.220000 3325.620000 336.320000 3326.100000 ;
+ RECT 335.220000 3336.500000 336.320000 3336.980000 ;
+ RECT 335.220000 3341.940000 336.320000 3342.420000 ;
+ RECT 290.220000 3325.620000 291.320000 3326.100000 ;
+ RECT 290.220000 3331.060000 291.320000 3331.540000 ;
+ RECT 290.220000 3336.500000 291.320000 3336.980000 ;
+ RECT 290.220000 3341.940000 291.320000 3342.420000 ;
+ RECT 335.220000 3303.860000 336.320000 3304.340000 ;
+ RECT 335.220000 3309.300000 336.320000 3309.780000 ;
+ RECT 335.220000 3314.740000 336.320000 3315.220000 ;
+ RECT 335.220000 3320.180000 336.320000 3320.660000 ;
+ RECT 290.220000 3303.860000 291.320000 3304.340000 ;
+ RECT 290.220000 3309.300000 291.320000 3309.780000 ;
+ RECT 290.220000 3314.740000 291.320000 3315.220000 ;
+ RECT 290.220000 3320.180000 291.320000 3320.660000 ;
+ RECT 241.390000 3341.940000 242.390000 3342.420000 ;
+ RECT 245.055000 3341.940000 246.320000 3342.420000 ;
+ RECT 241.390000 3331.060000 242.390000 3331.540000 ;
+ RECT 245.055000 3331.060000 246.320000 3331.540000 ;
+ RECT 241.390000 3336.500000 242.390000 3336.980000 ;
+ RECT 245.055000 3336.500000 246.320000 3336.980000 ;
+ RECT 241.390000 3325.620000 242.390000 3326.100000 ;
+ RECT 245.055000 3325.620000 246.320000 3326.100000 ;
+ RECT 241.390000 3320.180000 242.390000 3320.660000 ;
+ RECT 245.055000 3320.180000 246.320000 3320.660000 ;
+ RECT 241.390000 3314.740000 242.390000 3315.220000 ;
+ RECT 245.055000 3314.740000 246.320000 3315.220000 ;
+ RECT 241.390000 3309.300000 242.390000 3309.780000 ;
+ RECT 245.055000 3309.300000 246.320000 3309.780000 ;
+ RECT 241.390000 3303.860000 242.390000 3304.340000 ;
+ RECT 245.055000 3303.860000 246.320000 3304.340000 ;
+ RECT 335.220000 3276.660000 336.320000 3277.140000 ;
+ RECT 335.220000 3282.100000 336.320000 3282.580000 ;
+ RECT 335.220000 3287.540000 336.320000 3288.020000 ;
+ RECT 335.220000 3292.980000 336.320000 3293.460000 ;
+ RECT 335.220000 3298.420000 336.320000 3298.900000 ;
+ RECT 290.220000 3276.660000 291.320000 3277.140000 ;
+ RECT 290.220000 3282.100000 291.320000 3282.580000 ;
+ RECT 290.220000 3287.540000 291.320000 3288.020000 ;
+ RECT 290.220000 3292.980000 291.320000 3293.460000 ;
+ RECT 290.220000 3298.420000 291.320000 3298.900000 ;
+ RECT 335.220000 3254.900000 336.320000 3255.380000 ;
+ RECT 335.220000 3260.340000 336.320000 3260.820000 ;
+ RECT 335.220000 3265.780000 336.320000 3266.260000 ;
+ RECT 335.220000 3271.220000 336.320000 3271.700000 ;
+ RECT 290.220000 3254.900000 291.320000 3255.380000 ;
+ RECT 290.220000 3260.340000 291.320000 3260.820000 ;
+ RECT 290.220000 3265.780000 291.320000 3266.260000 ;
+ RECT 290.220000 3271.220000 291.320000 3271.700000 ;
+ RECT 241.390000 3298.420000 242.390000 3298.900000 ;
+ RECT 245.055000 3298.420000 246.320000 3298.900000 ;
+ RECT 241.390000 3287.540000 242.390000 3288.020000 ;
+ RECT 245.055000 3287.540000 246.320000 3288.020000 ;
+ RECT 241.390000 3292.980000 242.390000 3293.460000 ;
+ RECT 245.055000 3292.980000 246.320000 3293.460000 ;
+ RECT 241.390000 3282.100000 242.390000 3282.580000 ;
+ RECT 245.055000 3282.100000 246.320000 3282.580000 ;
+ RECT 241.390000 3276.660000 242.390000 3277.140000 ;
+ RECT 245.055000 3276.660000 246.320000 3277.140000 ;
+ RECT 241.390000 3271.220000 242.390000 3271.700000 ;
+ RECT 245.055000 3271.220000 246.320000 3271.700000 ;
+ RECT 241.390000 3265.780000 242.390000 3266.260000 ;
+ RECT 245.055000 3265.780000 246.320000 3266.260000 ;
+ RECT 241.390000 3260.340000 242.390000 3260.820000 ;
+ RECT 245.055000 3260.340000 246.320000 3260.820000 ;
+ RECT 241.390000 3254.900000 242.390000 3255.380000 ;
+ RECT 245.055000 3254.900000 246.320000 3255.380000 ;
+ RECT 425.220000 3238.580000 426.320000 3239.060000 ;
+ RECT 425.220000 3244.020000 426.320000 3244.500000 ;
+ RECT 438.030000 3238.580000 439.030000 3239.060000 ;
+ RECT 438.030000 3244.020000 439.030000 3244.500000 ;
+ RECT 438.030000 3227.700000 439.030000 3228.180000 ;
+ RECT 438.030000 3233.140000 439.030000 3233.620000 ;
+ RECT 425.220000 3233.140000 426.320000 3233.620000 ;
+ RECT 425.220000 3227.700000 426.320000 3228.180000 ;
+ RECT 425.220000 3216.820000 426.320000 3217.300000 ;
+ RECT 425.220000 3222.260000 426.320000 3222.740000 ;
+ RECT 438.030000 3216.820000 439.030000 3217.300000 ;
+ RECT 438.030000 3222.260000 439.030000 3222.740000 ;
+ RECT 438.030000 3205.940000 439.030000 3206.420000 ;
+ RECT 438.030000 3200.500000 439.030000 3200.980000 ;
+ RECT 438.030000 3211.380000 439.030000 3211.860000 ;
+ RECT 425.220000 3211.380000 426.320000 3211.860000 ;
+ RECT 425.220000 3205.940000 426.320000 3206.420000 ;
+ RECT 425.220000 3200.500000 426.320000 3200.980000 ;
+ RECT 380.220000 3227.700000 381.320000 3228.180000 ;
+ RECT 380.220000 3233.140000 381.320000 3233.620000 ;
+ RECT 380.220000 3238.580000 381.320000 3239.060000 ;
+ RECT 380.220000 3244.020000 381.320000 3244.500000 ;
+ RECT 380.220000 3200.500000 381.320000 3200.980000 ;
+ RECT 380.220000 3205.940000 381.320000 3206.420000 ;
+ RECT 380.220000 3211.380000 381.320000 3211.860000 ;
+ RECT 380.220000 3216.820000 381.320000 3217.300000 ;
+ RECT 380.220000 3222.260000 381.320000 3222.740000 ;
+ RECT 425.220000 3189.620000 426.320000 3190.100000 ;
+ RECT 425.220000 3195.060000 426.320000 3195.540000 ;
+ RECT 438.030000 3189.620000 439.030000 3190.100000 ;
+ RECT 438.030000 3195.060000 439.030000 3195.540000 ;
+ RECT 425.220000 3178.740000 426.320000 3179.220000 ;
+ RECT 425.220000 3184.180000 426.320000 3184.660000 ;
+ RECT 438.030000 3178.740000 439.030000 3179.220000 ;
+ RECT 438.030000 3184.180000 439.030000 3184.660000 ;
+ RECT 438.030000 3167.860000 439.030000 3168.340000 ;
+ RECT 438.030000 3162.420000 439.030000 3162.900000 ;
+ RECT 438.030000 3173.300000 439.030000 3173.780000 ;
+ RECT 425.220000 3173.300000 426.320000 3173.780000 ;
+ RECT 425.220000 3167.860000 426.320000 3168.340000 ;
+ RECT 425.220000 3162.420000 426.320000 3162.900000 ;
+ RECT 425.220000 3156.980000 426.320000 3157.460000 ;
+ RECT 438.030000 3156.980000 439.030000 3157.460000 ;
+ RECT 380.220000 3178.740000 381.320000 3179.220000 ;
+ RECT 380.220000 3184.180000 381.320000 3184.660000 ;
+ RECT 380.220000 3189.620000 381.320000 3190.100000 ;
+ RECT 380.220000 3195.060000 381.320000 3195.540000 ;
+ RECT 380.220000 3156.980000 381.320000 3157.460000 ;
+ RECT 380.220000 3162.420000 381.320000 3162.900000 ;
+ RECT 380.220000 3167.860000 381.320000 3168.340000 ;
+ RECT 380.220000 3173.300000 381.320000 3173.780000 ;
+ RECT 335.220000 3227.700000 336.320000 3228.180000 ;
+ RECT 335.220000 3233.140000 336.320000 3233.620000 ;
+ RECT 335.220000 3238.580000 336.320000 3239.060000 ;
+ RECT 335.220000 3244.020000 336.320000 3244.500000 ;
+ RECT 290.220000 3227.700000 291.320000 3228.180000 ;
+ RECT 290.220000 3233.140000 291.320000 3233.620000 ;
+ RECT 290.220000 3238.580000 291.320000 3239.060000 ;
+ RECT 290.220000 3244.020000 291.320000 3244.500000 ;
+ RECT 335.220000 3200.500000 336.320000 3200.980000 ;
+ RECT 335.220000 3205.940000 336.320000 3206.420000 ;
+ RECT 335.220000 3211.380000 336.320000 3211.860000 ;
+ RECT 335.220000 3216.820000 336.320000 3217.300000 ;
+ RECT 335.220000 3222.260000 336.320000 3222.740000 ;
+ RECT 290.220000 3200.500000 291.320000 3200.980000 ;
+ RECT 290.220000 3205.940000 291.320000 3206.420000 ;
+ RECT 290.220000 3211.380000 291.320000 3211.860000 ;
+ RECT 290.220000 3216.820000 291.320000 3217.300000 ;
+ RECT 290.220000 3222.260000 291.320000 3222.740000 ;
+ RECT 241.390000 3244.020000 242.390000 3244.500000 ;
+ RECT 245.055000 3244.020000 246.320000 3244.500000 ;
+ RECT 241.390000 3238.580000 242.390000 3239.060000 ;
+ RECT 245.055000 3238.580000 246.320000 3239.060000 ;
+ RECT 241.390000 3233.140000 242.390000 3233.620000 ;
+ RECT 245.055000 3233.140000 246.320000 3233.620000 ;
+ RECT 241.390000 3227.700000 242.390000 3228.180000 ;
+ RECT 245.055000 3227.700000 246.320000 3228.180000 ;
+ RECT 241.390000 3222.260000 242.390000 3222.740000 ;
+ RECT 245.055000 3222.260000 246.320000 3222.740000 ;
+ RECT 241.390000 3216.820000 242.390000 3217.300000 ;
+ RECT 245.055000 3216.820000 246.320000 3217.300000 ;
+ RECT 241.390000 3205.940000 242.390000 3206.420000 ;
+ RECT 245.055000 3205.940000 246.320000 3206.420000 ;
+ RECT 241.390000 3211.380000 242.390000 3211.860000 ;
+ RECT 245.055000 3211.380000 246.320000 3211.860000 ;
+ RECT 241.390000 3200.500000 242.390000 3200.980000 ;
+ RECT 245.055000 3200.500000 246.320000 3200.980000 ;
+ RECT 335.220000 3178.740000 336.320000 3179.220000 ;
+ RECT 335.220000 3184.180000 336.320000 3184.660000 ;
+ RECT 335.220000 3189.620000 336.320000 3190.100000 ;
+ RECT 335.220000 3195.060000 336.320000 3195.540000 ;
+ RECT 290.220000 3178.740000 291.320000 3179.220000 ;
+ RECT 290.220000 3184.180000 291.320000 3184.660000 ;
+ RECT 290.220000 3189.620000 291.320000 3190.100000 ;
+ RECT 290.220000 3195.060000 291.320000 3195.540000 ;
+ RECT 335.220000 3156.980000 336.320000 3157.460000 ;
+ RECT 335.220000 3162.420000 336.320000 3162.900000 ;
+ RECT 335.220000 3167.860000 336.320000 3168.340000 ;
+ RECT 335.220000 3173.300000 336.320000 3173.780000 ;
+ RECT 290.220000 3156.980000 291.320000 3157.460000 ;
+ RECT 290.220000 3162.420000 291.320000 3162.900000 ;
+ RECT 290.220000 3167.860000 291.320000 3168.340000 ;
+ RECT 290.220000 3173.300000 291.320000 3173.780000 ;
+ RECT 241.390000 3195.060000 242.390000 3195.540000 ;
+ RECT 245.055000 3195.060000 246.320000 3195.540000 ;
+ RECT 241.390000 3189.620000 242.390000 3190.100000 ;
+ RECT 245.055000 3189.620000 246.320000 3190.100000 ;
+ RECT 241.390000 3184.180000 242.390000 3184.660000 ;
+ RECT 245.055000 3184.180000 246.320000 3184.660000 ;
+ RECT 241.390000 3178.740000 242.390000 3179.220000 ;
+ RECT 245.055000 3178.740000 246.320000 3179.220000 ;
+ RECT 241.390000 3173.300000 242.390000 3173.780000 ;
+ RECT 245.055000 3173.300000 246.320000 3173.780000 ;
+ RECT 241.390000 3162.420000 242.390000 3162.900000 ;
+ RECT 245.055000 3162.420000 246.320000 3162.900000 ;
+ RECT 241.390000 3167.860000 242.390000 3168.340000 ;
+ RECT 245.055000 3167.860000 246.320000 3168.340000 ;
+ RECT 241.390000 3156.980000 242.390000 3157.460000 ;
+ RECT 245.055000 3156.980000 246.320000 3157.460000 ;
+ RECT 380.220000 3249.460000 381.320000 3249.940000 ;
+ RECT 425.220000 3249.460000 426.320000 3249.940000 ;
+ RECT 438.030000 3249.460000 439.030000 3249.940000 ;
+ RECT 290.220000 3249.460000 291.320000 3249.940000 ;
+ RECT 335.220000 3249.460000 336.320000 3249.940000 ;
+ RECT 241.390000 3249.460000 242.390000 3249.940000 ;
+ RECT 245.055000 3249.460000 246.320000 3249.940000 ;
+ RECT 240.160000 3346.220000 440.260000 3347.220000 ;
+ RECT 240.160000 3150.650000 440.260000 3151.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 3149.400000 242.390000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 3348.660000 242.390000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 3149.400000 439.030000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 3348.660000 439.030000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 3150.650000 241.160000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 3150.650000 440.260000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 3346.220000 241.160000 3347.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 3346.220000 440.260000 3347.220000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 3141.680000 246.320000 3142.160000 ;
+ RECT 245.055000 3130.800000 246.320000 3131.280000 ;
+ RECT 245.055000 3136.240000 246.320000 3136.720000 ;
+ RECT 245.055000 3125.360000 246.320000 3125.840000 ;
+ RECT 245.055000 3119.920000 246.320000 3120.400000 ;
+ RECT 245.055000 3114.480000 246.320000 3114.960000 ;
+ RECT 245.055000 3109.040000 246.320000 3109.520000 ;
+ RECT 245.055000 3103.600000 246.320000 3104.080000 ;
+ RECT 245.055000 3098.160000 246.320000 3098.640000 ;
+ RECT 245.055000 3087.280000 246.320000 3087.760000 ;
+ RECT 245.055000 3092.720000 246.320000 3093.200000 ;
+ RECT 245.055000 3081.840000 246.320000 3082.320000 ;
+ RECT 245.055000 3076.400000 246.320000 3076.880000 ;
+ RECT 245.055000 3070.960000 246.320000 3071.440000 ;
+ RECT 245.055000 3065.520000 246.320000 3066.000000 ;
+ RECT 245.055000 3060.080000 246.320000 3060.560000 ;
+ RECT 245.055000 3054.640000 246.320000 3055.120000 ;
+ RECT 245.055000 3043.760000 246.320000 3044.240000 ;
+ RECT 245.055000 3038.320000 246.320000 3038.800000 ;
+ RECT 245.055000 3032.880000 246.320000 3033.360000 ;
+ RECT 245.055000 3027.440000 246.320000 3027.920000 ;
+ RECT 245.055000 3022.000000 246.320000 3022.480000 ;
+ RECT 245.055000 3016.560000 246.320000 3017.040000 ;
+ RECT 245.055000 3005.680000 246.320000 3006.160000 ;
+ RECT 245.055000 3011.120000 246.320000 3011.600000 ;
+ RECT 245.055000 3000.240000 246.320000 3000.720000 ;
+ RECT 245.055000 2994.800000 246.320000 2995.280000 ;
+ RECT 245.055000 2989.360000 246.320000 2989.840000 ;
+ RECT 245.055000 2983.920000 246.320000 2984.400000 ;
+ RECT 245.055000 2978.480000 246.320000 2978.960000 ;
+ RECT 245.055000 2973.040000 246.320000 2973.520000 ;
+ RECT 245.055000 2962.160000 246.320000 2962.640000 ;
+ RECT 245.055000 2967.600000 246.320000 2968.080000 ;
+ RECT 245.055000 2956.720000 246.320000 2957.200000 ;
+ RECT 245.055000 3049.200000 246.320000 3049.680000 ;
+ RECT 425.220000 2950.390000 426.320000 3146.960000 ;
+ RECT 380.220000 2950.390000 381.320000 3146.960000 ;
+ RECT 438.030000 2949.140000 439.030000 3149.400000 ;
+ RECT 335.220000 2950.390000 336.320000 3146.960000 ;
+ RECT 290.220000 2950.390000 291.320000 3146.960000 ;
+ RECT 245.220000 2950.390000 246.320000 3146.960000 ;
+ RECT 241.390000 2949.140000 242.390000 3149.400000 ;
+ LAYER met3 ;
+ RECT 425.220000 3141.680000 426.320000 3142.160000 ;
+ RECT 438.030000 3141.680000 439.030000 3142.160000 ;
+ RECT 438.030000 3130.800000 439.030000 3131.280000 ;
+ RECT 438.030000 3125.360000 439.030000 3125.840000 ;
+ RECT 438.030000 3136.240000 439.030000 3136.720000 ;
+ RECT 425.220000 3136.240000 426.320000 3136.720000 ;
+ RECT 425.220000 3130.800000 426.320000 3131.280000 ;
+ RECT 425.220000 3125.360000 426.320000 3125.840000 ;
+ RECT 425.220000 3114.480000 426.320000 3114.960000 ;
+ RECT 425.220000 3119.920000 426.320000 3120.400000 ;
+ RECT 438.030000 3114.480000 439.030000 3114.960000 ;
+ RECT 438.030000 3119.920000 439.030000 3120.400000 ;
+ RECT 425.220000 3103.600000 426.320000 3104.080000 ;
+ RECT 425.220000 3109.040000 426.320000 3109.520000 ;
+ RECT 438.030000 3103.600000 439.030000 3104.080000 ;
+ RECT 438.030000 3109.040000 439.030000 3109.520000 ;
+ RECT 380.220000 3125.360000 381.320000 3125.840000 ;
+ RECT 380.220000 3130.800000 381.320000 3131.280000 ;
+ RECT 380.220000 3136.240000 381.320000 3136.720000 ;
+ RECT 380.220000 3141.680000 381.320000 3142.160000 ;
+ RECT 380.220000 3109.040000 381.320000 3109.520000 ;
+ RECT 380.220000 3103.600000 381.320000 3104.080000 ;
+ RECT 380.220000 3114.480000 381.320000 3114.960000 ;
+ RECT 380.220000 3119.920000 381.320000 3120.400000 ;
+ RECT 438.030000 3092.720000 439.030000 3093.200000 ;
+ RECT 438.030000 3087.280000 439.030000 3087.760000 ;
+ RECT 438.030000 3098.160000 439.030000 3098.640000 ;
+ RECT 425.220000 3098.160000 426.320000 3098.640000 ;
+ RECT 425.220000 3092.720000 426.320000 3093.200000 ;
+ RECT 425.220000 3087.280000 426.320000 3087.760000 ;
+ RECT 425.220000 3076.400000 426.320000 3076.880000 ;
+ RECT 425.220000 3081.840000 426.320000 3082.320000 ;
+ RECT 438.030000 3076.400000 439.030000 3076.880000 ;
+ RECT 438.030000 3081.840000 439.030000 3082.320000 ;
+ RECT 438.030000 3065.520000 439.030000 3066.000000 ;
+ RECT 438.030000 3070.960000 439.030000 3071.440000 ;
+ RECT 425.220000 3070.960000 426.320000 3071.440000 ;
+ RECT 425.220000 3065.520000 426.320000 3066.000000 ;
+ RECT 425.220000 3054.640000 426.320000 3055.120000 ;
+ RECT 425.220000 3060.080000 426.320000 3060.560000 ;
+ RECT 438.030000 3054.640000 439.030000 3055.120000 ;
+ RECT 438.030000 3060.080000 439.030000 3060.560000 ;
+ RECT 380.220000 3076.400000 381.320000 3076.880000 ;
+ RECT 380.220000 3081.840000 381.320000 3082.320000 ;
+ RECT 380.220000 3087.280000 381.320000 3087.760000 ;
+ RECT 380.220000 3092.720000 381.320000 3093.200000 ;
+ RECT 380.220000 3098.160000 381.320000 3098.640000 ;
+ RECT 380.220000 3054.640000 381.320000 3055.120000 ;
+ RECT 380.220000 3060.080000 381.320000 3060.560000 ;
+ RECT 380.220000 3065.520000 381.320000 3066.000000 ;
+ RECT 380.220000 3070.960000 381.320000 3071.440000 ;
+ RECT 335.220000 3130.800000 336.320000 3131.280000 ;
+ RECT 335.220000 3125.360000 336.320000 3125.840000 ;
+ RECT 335.220000 3136.240000 336.320000 3136.720000 ;
+ RECT 335.220000 3141.680000 336.320000 3142.160000 ;
+ RECT 290.220000 3125.360000 291.320000 3125.840000 ;
+ RECT 290.220000 3130.800000 291.320000 3131.280000 ;
+ RECT 290.220000 3136.240000 291.320000 3136.720000 ;
+ RECT 290.220000 3141.680000 291.320000 3142.160000 ;
+ RECT 335.220000 3103.600000 336.320000 3104.080000 ;
+ RECT 335.220000 3109.040000 336.320000 3109.520000 ;
+ RECT 335.220000 3114.480000 336.320000 3114.960000 ;
+ RECT 335.220000 3119.920000 336.320000 3120.400000 ;
+ RECT 290.220000 3103.600000 291.320000 3104.080000 ;
+ RECT 290.220000 3109.040000 291.320000 3109.520000 ;
+ RECT 290.220000 3114.480000 291.320000 3114.960000 ;
+ RECT 290.220000 3119.920000 291.320000 3120.400000 ;
+ RECT 241.390000 3141.680000 242.390000 3142.160000 ;
+ RECT 245.055000 3141.680000 246.320000 3142.160000 ;
+ RECT 241.390000 3130.800000 242.390000 3131.280000 ;
+ RECT 245.055000 3130.800000 246.320000 3131.280000 ;
+ RECT 241.390000 3136.240000 242.390000 3136.720000 ;
+ RECT 245.055000 3136.240000 246.320000 3136.720000 ;
+ RECT 241.390000 3125.360000 242.390000 3125.840000 ;
+ RECT 245.055000 3125.360000 246.320000 3125.840000 ;
+ RECT 241.390000 3119.920000 242.390000 3120.400000 ;
+ RECT 245.055000 3119.920000 246.320000 3120.400000 ;
+ RECT 241.390000 3114.480000 242.390000 3114.960000 ;
+ RECT 245.055000 3114.480000 246.320000 3114.960000 ;
+ RECT 241.390000 3109.040000 242.390000 3109.520000 ;
+ RECT 245.055000 3109.040000 246.320000 3109.520000 ;
+ RECT 241.390000 3103.600000 242.390000 3104.080000 ;
+ RECT 245.055000 3103.600000 246.320000 3104.080000 ;
+ RECT 335.220000 3076.400000 336.320000 3076.880000 ;
+ RECT 335.220000 3081.840000 336.320000 3082.320000 ;
+ RECT 335.220000 3087.280000 336.320000 3087.760000 ;
+ RECT 335.220000 3092.720000 336.320000 3093.200000 ;
+ RECT 335.220000 3098.160000 336.320000 3098.640000 ;
+ RECT 290.220000 3076.400000 291.320000 3076.880000 ;
+ RECT 290.220000 3081.840000 291.320000 3082.320000 ;
+ RECT 290.220000 3087.280000 291.320000 3087.760000 ;
+ RECT 290.220000 3092.720000 291.320000 3093.200000 ;
+ RECT 290.220000 3098.160000 291.320000 3098.640000 ;
+ RECT 335.220000 3054.640000 336.320000 3055.120000 ;
+ RECT 335.220000 3060.080000 336.320000 3060.560000 ;
+ RECT 335.220000 3065.520000 336.320000 3066.000000 ;
+ RECT 335.220000 3070.960000 336.320000 3071.440000 ;
+ RECT 290.220000 3054.640000 291.320000 3055.120000 ;
+ RECT 290.220000 3060.080000 291.320000 3060.560000 ;
+ RECT 290.220000 3065.520000 291.320000 3066.000000 ;
+ RECT 290.220000 3070.960000 291.320000 3071.440000 ;
+ RECT 241.390000 3098.160000 242.390000 3098.640000 ;
+ RECT 245.055000 3098.160000 246.320000 3098.640000 ;
+ RECT 241.390000 3087.280000 242.390000 3087.760000 ;
+ RECT 245.055000 3087.280000 246.320000 3087.760000 ;
+ RECT 241.390000 3092.720000 242.390000 3093.200000 ;
+ RECT 245.055000 3092.720000 246.320000 3093.200000 ;
+ RECT 241.390000 3081.840000 242.390000 3082.320000 ;
+ RECT 245.055000 3081.840000 246.320000 3082.320000 ;
+ RECT 241.390000 3076.400000 242.390000 3076.880000 ;
+ RECT 245.055000 3076.400000 246.320000 3076.880000 ;
+ RECT 241.390000 3070.960000 242.390000 3071.440000 ;
+ RECT 245.055000 3070.960000 246.320000 3071.440000 ;
+ RECT 241.390000 3065.520000 242.390000 3066.000000 ;
+ RECT 245.055000 3065.520000 246.320000 3066.000000 ;
+ RECT 241.390000 3060.080000 242.390000 3060.560000 ;
+ RECT 245.055000 3060.080000 246.320000 3060.560000 ;
+ RECT 241.390000 3054.640000 242.390000 3055.120000 ;
+ RECT 245.055000 3054.640000 246.320000 3055.120000 ;
+ RECT 425.220000 3038.320000 426.320000 3038.800000 ;
+ RECT 425.220000 3043.760000 426.320000 3044.240000 ;
+ RECT 438.030000 3038.320000 439.030000 3038.800000 ;
+ RECT 438.030000 3043.760000 439.030000 3044.240000 ;
+ RECT 438.030000 3027.440000 439.030000 3027.920000 ;
+ RECT 438.030000 3032.880000 439.030000 3033.360000 ;
+ RECT 425.220000 3032.880000 426.320000 3033.360000 ;
+ RECT 425.220000 3027.440000 426.320000 3027.920000 ;
+ RECT 425.220000 3016.560000 426.320000 3017.040000 ;
+ RECT 425.220000 3022.000000 426.320000 3022.480000 ;
+ RECT 438.030000 3016.560000 439.030000 3017.040000 ;
+ RECT 438.030000 3022.000000 439.030000 3022.480000 ;
+ RECT 438.030000 3005.680000 439.030000 3006.160000 ;
+ RECT 438.030000 3000.240000 439.030000 3000.720000 ;
+ RECT 438.030000 3011.120000 439.030000 3011.600000 ;
+ RECT 425.220000 3011.120000 426.320000 3011.600000 ;
+ RECT 425.220000 3005.680000 426.320000 3006.160000 ;
+ RECT 425.220000 3000.240000 426.320000 3000.720000 ;
+ RECT 380.220000 3027.440000 381.320000 3027.920000 ;
+ RECT 380.220000 3032.880000 381.320000 3033.360000 ;
+ RECT 380.220000 3038.320000 381.320000 3038.800000 ;
+ RECT 380.220000 3043.760000 381.320000 3044.240000 ;
+ RECT 380.220000 3000.240000 381.320000 3000.720000 ;
+ RECT 380.220000 3005.680000 381.320000 3006.160000 ;
+ RECT 380.220000 3011.120000 381.320000 3011.600000 ;
+ RECT 380.220000 3016.560000 381.320000 3017.040000 ;
+ RECT 380.220000 3022.000000 381.320000 3022.480000 ;
+ RECT 425.220000 2989.360000 426.320000 2989.840000 ;
+ RECT 425.220000 2994.800000 426.320000 2995.280000 ;
+ RECT 438.030000 2989.360000 439.030000 2989.840000 ;
+ RECT 438.030000 2994.800000 439.030000 2995.280000 ;
+ RECT 425.220000 2978.480000 426.320000 2978.960000 ;
+ RECT 425.220000 2983.920000 426.320000 2984.400000 ;
+ RECT 438.030000 2978.480000 439.030000 2978.960000 ;
+ RECT 438.030000 2983.920000 439.030000 2984.400000 ;
+ RECT 438.030000 2967.600000 439.030000 2968.080000 ;
+ RECT 438.030000 2962.160000 439.030000 2962.640000 ;
+ RECT 438.030000 2973.040000 439.030000 2973.520000 ;
+ RECT 425.220000 2973.040000 426.320000 2973.520000 ;
+ RECT 425.220000 2967.600000 426.320000 2968.080000 ;
+ RECT 425.220000 2962.160000 426.320000 2962.640000 ;
+ RECT 425.220000 2956.720000 426.320000 2957.200000 ;
+ RECT 438.030000 2956.720000 439.030000 2957.200000 ;
+ RECT 380.220000 2978.480000 381.320000 2978.960000 ;
+ RECT 380.220000 2983.920000 381.320000 2984.400000 ;
+ RECT 380.220000 2989.360000 381.320000 2989.840000 ;
+ RECT 380.220000 2994.800000 381.320000 2995.280000 ;
+ RECT 380.220000 2956.720000 381.320000 2957.200000 ;
+ RECT 380.220000 2962.160000 381.320000 2962.640000 ;
+ RECT 380.220000 2967.600000 381.320000 2968.080000 ;
+ RECT 380.220000 2973.040000 381.320000 2973.520000 ;
+ RECT 335.220000 3027.440000 336.320000 3027.920000 ;
+ RECT 335.220000 3032.880000 336.320000 3033.360000 ;
+ RECT 335.220000 3038.320000 336.320000 3038.800000 ;
+ RECT 335.220000 3043.760000 336.320000 3044.240000 ;
+ RECT 290.220000 3027.440000 291.320000 3027.920000 ;
+ RECT 290.220000 3032.880000 291.320000 3033.360000 ;
+ RECT 290.220000 3038.320000 291.320000 3038.800000 ;
+ RECT 290.220000 3043.760000 291.320000 3044.240000 ;
+ RECT 335.220000 3000.240000 336.320000 3000.720000 ;
+ RECT 335.220000 3005.680000 336.320000 3006.160000 ;
+ RECT 335.220000 3011.120000 336.320000 3011.600000 ;
+ RECT 335.220000 3016.560000 336.320000 3017.040000 ;
+ RECT 335.220000 3022.000000 336.320000 3022.480000 ;
+ RECT 290.220000 3000.240000 291.320000 3000.720000 ;
+ RECT 290.220000 3005.680000 291.320000 3006.160000 ;
+ RECT 290.220000 3011.120000 291.320000 3011.600000 ;
+ RECT 290.220000 3016.560000 291.320000 3017.040000 ;
+ RECT 290.220000 3022.000000 291.320000 3022.480000 ;
+ RECT 241.390000 3043.760000 242.390000 3044.240000 ;
+ RECT 245.055000 3043.760000 246.320000 3044.240000 ;
+ RECT 241.390000 3038.320000 242.390000 3038.800000 ;
+ RECT 245.055000 3038.320000 246.320000 3038.800000 ;
+ RECT 241.390000 3032.880000 242.390000 3033.360000 ;
+ RECT 245.055000 3032.880000 246.320000 3033.360000 ;
+ RECT 241.390000 3027.440000 242.390000 3027.920000 ;
+ RECT 245.055000 3027.440000 246.320000 3027.920000 ;
+ RECT 241.390000 3022.000000 242.390000 3022.480000 ;
+ RECT 245.055000 3022.000000 246.320000 3022.480000 ;
+ RECT 241.390000 3016.560000 242.390000 3017.040000 ;
+ RECT 245.055000 3016.560000 246.320000 3017.040000 ;
+ RECT 241.390000 3005.680000 242.390000 3006.160000 ;
+ RECT 245.055000 3005.680000 246.320000 3006.160000 ;
+ RECT 241.390000 3011.120000 242.390000 3011.600000 ;
+ RECT 245.055000 3011.120000 246.320000 3011.600000 ;
+ RECT 241.390000 3000.240000 242.390000 3000.720000 ;
+ RECT 245.055000 3000.240000 246.320000 3000.720000 ;
+ RECT 335.220000 2978.480000 336.320000 2978.960000 ;
+ RECT 335.220000 2983.920000 336.320000 2984.400000 ;
+ RECT 335.220000 2989.360000 336.320000 2989.840000 ;
+ RECT 335.220000 2994.800000 336.320000 2995.280000 ;
+ RECT 290.220000 2978.480000 291.320000 2978.960000 ;
+ RECT 290.220000 2983.920000 291.320000 2984.400000 ;
+ RECT 290.220000 2989.360000 291.320000 2989.840000 ;
+ RECT 290.220000 2994.800000 291.320000 2995.280000 ;
+ RECT 335.220000 2956.720000 336.320000 2957.200000 ;
+ RECT 335.220000 2962.160000 336.320000 2962.640000 ;
+ RECT 335.220000 2967.600000 336.320000 2968.080000 ;
+ RECT 335.220000 2973.040000 336.320000 2973.520000 ;
+ RECT 290.220000 2956.720000 291.320000 2957.200000 ;
+ RECT 290.220000 2962.160000 291.320000 2962.640000 ;
+ RECT 290.220000 2967.600000 291.320000 2968.080000 ;
+ RECT 290.220000 2973.040000 291.320000 2973.520000 ;
+ RECT 241.390000 2994.800000 242.390000 2995.280000 ;
+ RECT 245.055000 2994.800000 246.320000 2995.280000 ;
+ RECT 241.390000 2989.360000 242.390000 2989.840000 ;
+ RECT 245.055000 2989.360000 246.320000 2989.840000 ;
+ RECT 241.390000 2983.920000 242.390000 2984.400000 ;
+ RECT 245.055000 2983.920000 246.320000 2984.400000 ;
+ RECT 241.390000 2978.480000 242.390000 2978.960000 ;
+ RECT 245.055000 2978.480000 246.320000 2978.960000 ;
+ RECT 241.390000 2973.040000 242.390000 2973.520000 ;
+ RECT 245.055000 2973.040000 246.320000 2973.520000 ;
+ RECT 241.390000 2962.160000 242.390000 2962.640000 ;
+ RECT 245.055000 2962.160000 246.320000 2962.640000 ;
+ RECT 241.390000 2967.600000 242.390000 2968.080000 ;
+ RECT 245.055000 2967.600000 246.320000 2968.080000 ;
+ RECT 241.390000 2956.720000 242.390000 2957.200000 ;
+ RECT 245.055000 2956.720000 246.320000 2957.200000 ;
+ RECT 380.220000 3049.200000 381.320000 3049.680000 ;
+ RECT 425.220000 3049.200000 426.320000 3049.680000 ;
+ RECT 438.030000 3049.200000 439.030000 3049.680000 ;
+ RECT 290.220000 3049.200000 291.320000 3049.680000 ;
+ RECT 335.220000 3049.200000 336.320000 3049.680000 ;
+ RECT 241.390000 3049.200000 242.390000 3049.680000 ;
+ RECT 245.055000 3049.200000 246.320000 3049.680000 ;
+ RECT 240.160000 3145.960000 440.260000 3146.960000 ;
+ RECT 240.160000 2950.390000 440.260000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 2949.140000 242.390000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 3148.400000 242.390000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 2949.140000 439.030000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 3148.400000 439.030000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2950.390000 241.160000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2950.390000 440.260000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 3145.960000 241.160000 3146.960000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 3145.960000 440.260000 3146.960000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 2941.420000 246.320000 2941.900000 ;
+ RECT 245.055000 2930.540000 246.320000 2931.020000 ;
+ RECT 245.055000 2935.980000 246.320000 2936.460000 ;
+ RECT 245.055000 2925.100000 246.320000 2925.580000 ;
+ RECT 245.055000 2919.660000 246.320000 2920.140000 ;
+ RECT 245.055000 2914.220000 246.320000 2914.700000 ;
+ RECT 245.055000 2908.780000 246.320000 2909.260000 ;
+ RECT 245.055000 2903.340000 246.320000 2903.820000 ;
+ RECT 245.055000 2897.900000 246.320000 2898.380000 ;
+ RECT 245.055000 2887.020000 246.320000 2887.500000 ;
+ RECT 245.055000 2892.460000 246.320000 2892.940000 ;
+ RECT 245.055000 2881.580000 246.320000 2882.060000 ;
+ RECT 245.055000 2876.140000 246.320000 2876.620000 ;
+ RECT 245.055000 2870.700000 246.320000 2871.180000 ;
+ RECT 245.055000 2865.260000 246.320000 2865.740000 ;
+ RECT 245.055000 2859.820000 246.320000 2860.300000 ;
+ RECT 245.055000 2854.380000 246.320000 2854.860000 ;
+ RECT 245.055000 2843.500000 246.320000 2843.980000 ;
+ RECT 245.055000 2838.060000 246.320000 2838.540000 ;
+ RECT 245.055000 2832.620000 246.320000 2833.100000 ;
+ RECT 245.055000 2827.180000 246.320000 2827.660000 ;
+ RECT 245.055000 2821.740000 246.320000 2822.220000 ;
+ RECT 245.055000 2816.300000 246.320000 2816.780000 ;
+ RECT 245.055000 2805.420000 246.320000 2805.900000 ;
+ RECT 245.055000 2810.860000 246.320000 2811.340000 ;
+ RECT 245.055000 2799.980000 246.320000 2800.460000 ;
+ RECT 245.055000 2794.540000 246.320000 2795.020000 ;
+ RECT 245.055000 2789.100000 246.320000 2789.580000 ;
+ RECT 245.055000 2783.660000 246.320000 2784.140000 ;
+ RECT 245.055000 2778.220000 246.320000 2778.700000 ;
+ RECT 245.055000 2772.780000 246.320000 2773.260000 ;
+ RECT 245.055000 2761.900000 246.320000 2762.380000 ;
+ RECT 245.055000 2767.340000 246.320000 2767.820000 ;
+ RECT 245.055000 2756.460000 246.320000 2756.940000 ;
+ RECT 245.055000 2848.940000 246.320000 2849.420000 ;
+ RECT 425.220000 2750.130000 426.320000 2946.700000 ;
+ RECT 380.220000 2750.130000 381.320000 2946.700000 ;
+ RECT 438.030000 2748.880000 439.030000 2949.140000 ;
+ RECT 335.220000 2750.130000 336.320000 2946.700000 ;
+ RECT 290.220000 2750.130000 291.320000 2946.700000 ;
+ RECT 245.220000 2750.130000 246.320000 2946.700000 ;
+ RECT 241.390000 2748.880000 242.390000 2949.140000 ;
+ LAYER met3 ;
+ RECT 425.220000 2941.420000 426.320000 2941.900000 ;
+ RECT 438.030000 2941.420000 439.030000 2941.900000 ;
+ RECT 438.030000 2930.540000 439.030000 2931.020000 ;
+ RECT 438.030000 2925.100000 439.030000 2925.580000 ;
+ RECT 438.030000 2935.980000 439.030000 2936.460000 ;
+ RECT 425.220000 2935.980000 426.320000 2936.460000 ;
+ RECT 425.220000 2930.540000 426.320000 2931.020000 ;
+ RECT 425.220000 2925.100000 426.320000 2925.580000 ;
+ RECT 425.220000 2914.220000 426.320000 2914.700000 ;
+ RECT 425.220000 2919.660000 426.320000 2920.140000 ;
+ RECT 438.030000 2914.220000 439.030000 2914.700000 ;
+ RECT 438.030000 2919.660000 439.030000 2920.140000 ;
+ RECT 425.220000 2903.340000 426.320000 2903.820000 ;
+ RECT 425.220000 2908.780000 426.320000 2909.260000 ;
+ RECT 438.030000 2903.340000 439.030000 2903.820000 ;
+ RECT 438.030000 2908.780000 439.030000 2909.260000 ;
+ RECT 380.220000 2925.100000 381.320000 2925.580000 ;
+ RECT 380.220000 2930.540000 381.320000 2931.020000 ;
+ RECT 380.220000 2935.980000 381.320000 2936.460000 ;
+ RECT 380.220000 2941.420000 381.320000 2941.900000 ;
+ RECT 380.220000 2908.780000 381.320000 2909.260000 ;
+ RECT 380.220000 2903.340000 381.320000 2903.820000 ;
+ RECT 380.220000 2914.220000 381.320000 2914.700000 ;
+ RECT 380.220000 2919.660000 381.320000 2920.140000 ;
+ RECT 438.030000 2892.460000 439.030000 2892.940000 ;
+ RECT 438.030000 2887.020000 439.030000 2887.500000 ;
+ RECT 438.030000 2897.900000 439.030000 2898.380000 ;
+ RECT 425.220000 2897.900000 426.320000 2898.380000 ;
+ RECT 425.220000 2892.460000 426.320000 2892.940000 ;
+ RECT 425.220000 2887.020000 426.320000 2887.500000 ;
+ RECT 425.220000 2876.140000 426.320000 2876.620000 ;
+ RECT 425.220000 2881.580000 426.320000 2882.060000 ;
+ RECT 438.030000 2876.140000 439.030000 2876.620000 ;
+ RECT 438.030000 2881.580000 439.030000 2882.060000 ;
+ RECT 438.030000 2865.260000 439.030000 2865.740000 ;
+ RECT 438.030000 2870.700000 439.030000 2871.180000 ;
+ RECT 425.220000 2870.700000 426.320000 2871.180000 ;
+ RECT 425.220000 2865.260000 426.320000 2865.740000 ;
+ RECT 425.220000 2854.380000 426.320000 2854.860000 ;
+ RECT 425.220000 2859.820000 426.320000 2860.300000 ;
+ RECT 438.030000 2854.380000 439.030000 2854.860000 ;
+ RECT 438.030000 2859.820000 439.030000 2860.300000 ;
+ RECT 380.220000 2876.140000 381.320000 2876.620000 ;
+ RECT 380.220000 2881.580000 381.320000 2882.060000 ;
+ RECT 380.220000 2887.020000 381.320000 2887.500000 ;
+ RECT 380.220000 2892.460000 381.320000 2892.940000 ;
+ RECT 380.220000 2897.900000 381.320000 2898.380000 ;
+ RECT 380.220000 2854.380000 381.320000 2854.860000 ;
+ RECT 380.220000 2859.820000 381.320000 2860.300000 ;
+ RECT 380.220000 2865.260000 381.320000 2865.740000 ;
+ RECT 380.220000 2870.700000 381.320000 2871.180000 ;
+ RECT 335.220000 2930.540000 336.320000 2931.020000 ;
+ RECT 335.220000 2925.100000 336.320000 2925.580000 ;
+ RECT 335.220000 2935.980000 336.320000 2936.460000 ;
+ RECT 335.220000 2941.420000 336.320000 2941.900000 ;
+ RECT 290.220000 2925.100000 291.320000 2925.580000 ;
+ RECT 290.220000 2930.540000 291.320000 2931.020000 ;
+ RECT 290.220000 2935.980000 291.320000 2936.460000 ;
+ RECT 290.220000 2941.420000 291.320000 2941.900000 ;
+ RECT 335.220000 2903.340000 336.320000 2903.820000 ;
+ RECT 335.220000 2908.780000 336.320000 2909.260000 ;
+ RECT 335.220000 2914.220000 336.320000 2914.700000 ;
+ RECT 335.220000 2919.660000 336.320000 2920.140000 ;
+ RECT 290.220000 2903.340000 291.320000 2903.820000 ;
+ RECT 290.220000 2908.780000 291.320000 2909.260000 ;
+ RECT 290.220000 2914.220000 291.320000 2914.700000 ;
+ RECT 290.220000 2919.660000 291.320000 2920.140000 ;
+ RECT 241.390000 2941.420000 242.390000 2941.900000 ;
+ RECT 245.055000 2941.420000 246.320000 2941.900000 ;
+ RECT 241.390000 2930.540000 242.390000 2931.020000 ;
+ RECT 245.055000 2930.540000 246.320000 2931.020000 ;
+ RECT 241.390000 2935.980000 242.390000 2936.460000 ;
+ RECT 245.055000 2935.980000 246.320000 2936.460000 ;
+ RECT 241.390000 2925.100000 242.390000 2925.580000 ;
+ RECT 245.055000 2925.100000 246.320000 2925.580000 ;
+ RECT 241.390000 2919.660000 242.390000 2920.140000 ;
+ RECT 245.055000 2919.660000 246.320000 2920.140000 ;
+ RECT 241.390000 2914.220000 242.390000 2914.700000 ;
+ RECT 245.055000 2914.220000 246.320000 2914.700000 ;
+ RECT 241.390000 2908.780000 242.390000 2909.260000 ;
+ RECT 245.055000 2908.780000 246.320000 2909.260000 ;
+ RECT 241.390000 2903.340000 242.390000 2903.820000 ;
+ RECT 245.055000 2903.340000 246.320000 2903.820000 ;
+ RECT 335.220000 2876.140000 336.320000 2876.620000 ;
+ RECT 335.220000 2881.580000 336.320000 2882.060000 ;
+ RECT 335.220000 2887.020000 336.320000 2887.500000 ;
+ RECT 335.220000 2892.460000 336.320000 2892.940000 ;
+ RECT 335.220000 2897.900000 336.320000 2898.380000 ;
+ RECT 290.220000 2876.140000 291.320000 2876.620000 ;
+ RECT 290.220000 2881.580000 291.320000 2882.060000 ;
+ RECT 290.220000 2887.020000 291.320000 2887.500000 ;
+ RECT 290.220000 2892.460000 291.320000 2892.940000 ;
+ RECT 290.220000 2897.900000 291.320000 2898.380000 ;
+ RECT 335.220000 2854.380000 336.320000 2854.860000 ;
+ RECT 335.220000 2859.820000 336.320000 2860.300000 ;
+ RECT 335.220000 2865.260000 336.320000 2865.740000 ;
+ RECT 335.220000 2870.700000 336.320000 2871.180000 ;
+ RECT 290.220000 2854.380000 291.320000 2854.860000 ;
+ RECT 290.220000 2859.820000 291.320000 2860.300000 ;
+ RECT 290.220000 2865.260000 291.320000 2865.740000 ;
+ RECT 290.220000 2870.700000 291.320000 2871.180000 ;
+ RECT 241.390000 2897.900000 242.390000 2898.380000 ;
+ RECT 245.055000 2897.900000 246.320000 2898.380000 ;
+ RECT 241.390000 2887.020000 242.390000 2887.500000 ;
+ RECT 245.055000 2887.020000 246.320000 2887.500000 ;
+ RECT 241.390000 2892.460000 242.390000 2892.940000 ;
+ RECT 245.055000 2892.460000 246.320000 2892.940000 ;
+ RECT 241.390000 2881.580000 242.390000 2882.060000 ;
+ RECT 245.055000 2881.580000 246.320000 2882.060000 ;
+ RECT 241.390000 2876.140000 242.390000 2876.620000 ;
+ RECT 245.055000 2876.140000 246.320000 2876.620000 ;
+ RECT 241.390000 2870.700000 242.390000 2871.180000 ;
+ RECT 245.055000 2870.700000 246.320000 2871.180000 ;
+ RECT 241.390000 2865.260000 242.390000 2865.740000 ;
+ RECT 245.055000 2865.260000 246.320000 2865.740000 ;
+ RECT 241.390000 2859.820000 242.390000 2860.300000 ;
+ RECT 245.055000 2859.820000 246.320000 2860.300000 ;
+ RECT 241.390000 2854.380000 242.390000 2854.860000 ;
+ RECT 245.055000 2854.380000 246.320000 2854.860000 ;
+ RECT 425.220000 2838.060000 426.320000 2838.540000 ;
+ RECT 425.220000 2843.500000 426.320000 2843.980000 ;
+ RECT 438.030000 2838.060000 439.030000 2838.540000 ;
+ RECT 438.030000 2843.500000 439.030000 2843.980000 ;
+ RECT 438.030000 2827.180000 439.030000 2827.660000 ;
+ RECT 438.030000 2832.620000 439.030000 2833.100000 ;
+ RECT 425.220000 2832.620000 426.320000 2833.100000 ;
+ RECT 425.220000 2827.180000 426.320000 2827.660000 ;
+ RECT 425.220000 2816.300000 426.320000 2816.780000 ;
+ RECT 425.220000 2821.740000 426.320000 2822.220000 ;
+ RECT 438.030000 2816.300000 439.030000 2816.780000 ;
+ RECT 438.030000 2821.740000 439.030000 2822.220000 ;
+ RECT 438.030000 2805.420000 439.030000 2805.900000 ;
+ RECT 438.030000 2799.980000 439.030000 2800.460000 ;
+ RECT 438.030000 2810.860000 439.030000 2811.340000 ;
+ RECT 425.220000 2810.860000 426.320000 2811.340000 ;
+ RECT 425.220000 2805.420000 426.320000 2805.900000 ;
+ RECT 425.220000 2799.980000 426.320000 2800.460000 ;
+ RECT 380.220000 2827.180000 381.320000 2827.660000 ;
+ RECT 380.220000 2832.620000 381.320000 2833.100000 ;
+ RECT 380.220000 2838.060000 381.320000 2838.540000 ;
+ RECT 380.220000 2843.500000 381.320000 2843.980000 ;
+ RECT 380.220000 2799.980000 381.320000 2800.460000 ;
+ RECT 380.220000 2805.420000 381.320000 2805.900000 ;
+ RECT 380.220000 2810.860000 381.320000 2811.340000 ;
+ RECT 380.220000 2816.300000 381.320000 2816.780000 ;
+ RECT 380.220000 2821.740000 381.320000 2822.220000 ;
+ RECT 425.220000 2789.100000 426.320000 2789.580000 ;
+ RECT 425.220000 2794.540000 426.320000 2795.020000 ;
+ RECT 438.030000 2789.100000 439.030000 2789.580000 ;
+ RECT 438.030000 2794.540000 439.030000 2795.020000 ;
+ RECT 425.220000 2778.220000 426.320000 2778.700000 ;
+ RECT 425.220000 2783.660000 426.320000 2784.140000 ;
+ RECT 438.030000 2778.220000 439.030000 2778.700000 ;
+ RECT 438.030000 2783.660000 439.030000 2784.140000 ;
+ RECT 438.030000 2767.340000 439.030000 2767.820000 ;
+ RECT 438.030000 2761.900000 439.030000 2762.380000 ;
+ RECT 438.030000 2772.780000 439.030000 2773.260000 ;
+ RECT 425.220000 2772.780000 426.320000 2773.260000 ;
+ RECT 425.220000 2767.340000 426.320000 2767.820000 ;
+ RECT 425.220000 2761.900000 426.320000 2762.380000 ;
+ RECT 425.220000 2756.460000 426.320000 2756.940000 ;
+ RECT 438.030000 2756.460000 439.030000 2756.940000 ;
+ RECT 380.220000 2778.220000 381.320000 2778.700000 ;
+ RECT 380.220000 2783.660000 381.320000 2784.140000 ;
+ RECT 380.220000 2789.100000 381.320000 2789.580000 ;
+ RECT 380.220000 2794.540000 381.320000 2795.020000 ;
+ RECT 380.220000 2756.460000 381.320000 2756.940000 ;
+ RECT 380.220000 2761.900000 381.320000 2762.380000 ;
+ RECT 380.220000 2767.340000 381.320000 2767.820000 ;
+ RECT 380.220000 2772.780000 381.320000 2773.260000 ;
+ RECT 335.220000 2827.180000 336.320000 2827.660000 ;
+ RECT 335.220000 2832.620000 336.320000 2833.100000 ;
+ RECT 335.220000 2838.060000 336.320000 2838.540000 ;
+ RECT 335.220000 2843.500000 336.320000 2843.980000 ;
+ RECT 290.220000 2827.180000 291.320000 2827.660000 ;
+ RECT 290.220000 2832.620000 291.320000 2833.100000 ;
+ RECT 290.220000 2838.060000 291.320000 2838.540000 ;
+ RECT 290.220000 2843.500000 291.320000 2843.980000 ;
+ RECT 335.220000 2799.980000 336.320000 2800.460000 ;
+ RECT 335.220000 2805.420000 336.320000 2805.900000 ;
+ RECT 335.220000 2810.860000 336.320000 2811.340000 ;
+ RECT 335.220000 2816.300000 336.320000 2816.780000 ;
+ RECT 335.220000 2821.740000 336.320000 2822.220000 ;
+ RECT 290.220000 2799.980000 291.320000 2800.460000 ;
+ RECT 290.220000 2805.420000 291.320000 2805.900000 ;
+ RECT 290.220000 2810.860000 291.320000 2811.340000 ;
+ RECT 290.220000 2816.300000 291.320000 2816.780000 ;
+ RECT 290.220000 2821.740000 291.320000 2822.220000 ;
+ RECT 241.390000 2843.500000 242.390000 2843.980000 ;
+ RECT 245.055000 2843.500000 246.320000 2843.980000 ;
+ RECT 241.390000 2838.060000 242.390000 2838.540000 ;
+ RECT 245.055000 2838.060000 246.320000 2838.540000 ;
+ RECT 241.390000 2832.620000 242.390000 2833.100000 ;
+ RECT 245.055000 2832.620000 246.320000 2833.100000 ;
+ RECT 241.390000 2827.180000 242.390000 2827.660000 ;
+ RECT 245.055000 2827.180000 246.320000 2827.660000 ;
+ RECT 241.390000 2821.740000 242.390000 2822.220000 ;
+ RECT 245.055000 2821.740000 246.320000 2822.220000 ;
+ RECT 241.390000 2816.300000 242.390000 2816.780000 ;
+ RECT 245.055000 2816.300000 246.320000 2816.780000 ;
+ RECT 241.390000 2805.420000 242.390000 2805.900000 ;
+ RECT 245.055000 2805.420000 246.320000 2805.900000 ;
+ RECT 241.390000 2810.860000 242.390000 2811.340000 ;
+ RECT 245.055000 2810.860000 246.320000 2811.340000 ;
+ RECT 241.390000 2799.980000 242.390000 2800.460000 ;
+ RECT 245.055000 2799.980000 246.320000 2800.460000 ;
+ RECT 335.220000 2778.220000 336.320000 2778.700000 ;
+ RECT 335.220000 2783.660000 336.320000 2784.140000 ;
+ RECT 335.220000 2789.100000 336.320000 2789.580000 ;
+ RECT 335.220000 2794.540000 336.320000 2795.020000 ;
+ RECT 290.220000 2778.220000 291.320000 2778.700000 ;
+ RECT 290.220000 2783.660000 291.320000 2784.140000 ;
+ RECT 290.220000 2789.100000 291.320000 2789.580000 ;
+ RECT 290.220000 2794.540000 291.320000 2795.020000 ;
+ RECT 335.220000 2756.460000 336.320000 2756.940000 ;
+ RECT 335.220000 2761.900000 336.320000 2762.380000 ;
+ RECT 335.220000 2767.340000 336.320000 2767.820000 ;
+ RECT 335.220000 2772.780000 336.320000 2773.260000 ;
+ RECT 290.220000 2756.460000 291.320000 2756.940000 ;
+ RECT 290.220000 2761.900000 291.320000 2762.380000 ;
+ RECT 290.220000 2767.340000 291.320000 2767.820000 ;
+ RECT 290.220000 2772.780000 291.320000 2773.260000 ;
+ RECT 241.390000 2794.540000 242.390000 2795.020000 ;
+ RECT 245.055000 2794.540000 246.320000 2795.020000 ;
+ RECT 241.390000 2789.100000 242.390000 2789.580000 ;
+ RECT 245.055000 2789.100000 246.320000 2789.580000 ;
+ RECT 241.390000 2783.660000 242.390000 2784.140000 ;
+ RECT 245.055000 2783.660000 246.320000 2784.140000 ;
+ RECT 241.390000 2778.220000 242.390000 2778.700000 ;
+ RECT 245.055000 2778.220000 246.320000 2778.700000 ;
+ RECT 241.390000 2772.780000 242.390000 2773.260000 ;
+ RECT 245.055000 2772.780000 246.320000 2773.260000 ;
+ RECT 241.390000 2761.900000 242.390000 2762.380000 ;
+ RECT 245.055000 2761.900000 246.320000 2762.380000 ;
+ RECT 241.390000 2767.340000 242.390000 2767.820000 ;
+ RECT 245.055000 2767.340000 246.320000 2767.820000 ;
+ RECT 241.390000 2756.460000 242.390000 2756.940000 ;
+ RECT 245.055000 2756.460000 246.320000 2756.940000 ;
+ RECT 380.220000 2848.940000 381.320000 2849.420000 ;
+ RECT 425.220000 2848.940000 426.320000 2849.420000 ;
+ RECT 438.030000 2848.940000 439.030000 2849.420000 ;
+ RECT 290.220000 2848.940000 291.320000 2849.420000 ;
+ RECT 335.220000 2848.940000 336.320000 2849.420000 ;
+ RECT 241.390000 2848.940000 242.390000 2849.420000 ;
+ RECT 245.055000 2848.940000 246.320000 2849.420000 ;
+ RECT 240.160000 2945.700000 440.260000 2946.700000 ;
+ RECT 240.160000 2750.130000 440.260000 2751.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 2748.880000 242.390000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 2948.140000 242.390000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 2748.880000 439.030000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 2948.140000 439.030000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2750.130000 241.160000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2750.130000 440.260000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2945.700000 241.160000 2946.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2945.700000 440.260000 2946.700000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 2741.160000 246.320000 2741.640000 ;
+ RECT 245.055000 2730.280000 246.320000 2730.760000 ;
+ RECT 245.055000 2735.720000 246.320000 2736.200000 ;
+ RECT 245.055000 2724.840000 246.320000 2725.320000 ;
+ RECT 245.055000 2719.400000 246.320000 2719.880000 ;
+ RECT 245.055000 2713.960000 246.320000 2714.440000 ;
+ RECT 245.055000 2708.520000 246.320000 2709.000000 ;
+ RECT 245.055000 2703.080000 246.320000 2703.560000 ;
+ RECT 245.055000 2697.640000 246.320000 2698.120000 ;
+ RECT 245.055000 2686.760000 246.320000 2687.240000 ;
+ RECT 245.055000 2692.200000 246.320000 2692.680000 ;
+ RECT 245.055000 2681.320000 246.320000 2681.800000 ;
+ RECT 245.055000 2675.880000 246.320000 2676.360000 ;
+ RECT 245.055000 2670.440000 246.320000 2670.920000 ;
+ RECT 245.055000 2665.000000 246.320000 2665.480000 ;
+ RECT 245.055000 2659.560000 246.320000 2660.040000 ;
+ RECT 245.055000 2654.120000 246.320000 2654.600000 ;
+ RECT 245.055000 2643.240000 246.320000 2643.720000 ;
+ RECT 245.055000 2637.800000 246.320000 2638.280000 ;
+ RECT 245.055000 2632.360000 246.320000 2632.840000 ;
+ RECT 245.055000 2626.920000 246.320000 2627.400000 ;
+ RECT 245.055000 2621.480000 246.320000 2621.960000 ;
+ RECT 245.055000 2616.040000 246.320000 2616.520000 ;
+ RECT 245.055000 2605.160000 246.320000 2605.640000 ;
+ RECT 245.055000 2610.600000 246.320000 2611.080000 ;
+ RECT 245.055000 2599.720000 246.320000 2600.200000 ;
+ RECT 245.055000 2594.280000 246.320000 2594.760000 ;
+ RECT 245.055000 2588.840000 246.320000 2589.320000 ;
+ RECT 245.055000 2583.400000 246.320000 2583.880000 ;
+ RECT 245.055000 2577.960000 246.320000 2578.440000 ;
+ RECT 245.055000 2572.520000 246.320000 2573.000000 ;
+ RECT 245.055000 2561.640000 246.320000 2562.120000 ;
+ RECT 245.055000 2567.080000 246.320000 2567.560000 ;
+ RECT 245.055000 2556.200000 246.320000 2556.680000 ;
+ RECT 245.055000 2648.680000 246.320000 2649.160000 ;
+ RECT 425.220000 2549.870000 426.320000 2746.440000 ;
+ RECT 380.220000 2549.870000 381.320000 2746.440000 ;
+ RECT 438.030000 2548.620000 439.030000 2748.880000 ;
+ RECT 335.220000 2549.870000 336.320000 2746.440000 ;
+ RECT 290.220000 2549.870000 291.320000 2746.440000 ;
+ RECT 245.220000 2549.870000 246.320000 2746.440000 ;
+ RECT 241.390000 2548.620000 242.390000 2748.880000 ;
+ LAYER met3 ;
+ RECT 425.220000 2741.160000 426.320000 2741.640000 ;
+ RECT 438.030000 2741.160000 439.030000 2741.640000 ;
+ RECT 438.030000 2730.280000 439.030000 2730.760000 ;
+ RECT 438.030000 2724.840000 439.030000 2725.320000 ;
+ RECT 438.030000 2735.720000 439.030000 2736.200000 ;
+ RECT 425.220000 2735.720000 426.320000 2736.200000 ;
+ RECT 425.220000 2730.280000 426.320000 2730.760000 ;
+ RECT 425.220000 2724.840000 426.320000 2725.320000 ;
+ RECT 425.220000 2713.960000 426.320000 2714.440000 ;
+ RECT 425.220000 2719.400000 426.320000 2719.880000 ;
+ RECT 438.030000 2713.960000 439.030000 2714.440000 ;
+ RECT 438.030000 2719.400000 439.030000 2719.880000 ;
+ RECT 425.220000 2703.080000 426.320000 2703.560000 ;
+ RECT 425.220000 2708.520000 426.320000 2709.000000 ;
+ RECT 438.030000 2703.080000 439.030000 2703.560000 ;
+ RECT 438.030000 2708.520000 439.030000 2709.000000 ;
+ RECT 380.220000 2724.840000 381.320000 2725.320000 ;
+ RECT 380.220000 2730.280000 381.320000 2730.760000 ;
+ RECT 380.220000 2735.720000 381.320000 2736.200000 ;
+ RECT 380.220000 2741.160000 381.320000 2741.640000 ;
+ RECT 380.220000 2708.520000 381.320000 2709.000000 ;
+ RECT 380.220000 2703.080000 381.320000 2703.560000 ;
+ RECT 380.220000 2713.960000 381.320000 2714.440000 ;
+ RECT 380.220000 2719.400000 381.320000 2719.880000 ;
+ RECT 438.030000 2692.200000 439.030000 2692.680000 ;
+ RECT 438.030000 2686.760000 439.030000 2687.240000 ;
+ RECT 438.030000 2697.640000 439.030000 2698.120000 ;
+ RECT 425.220000 2697.640000 426.320000 2698.120000 ;
+ RECT 425.220000 2692.200000 426.320000 2692.680000 ;
+ RECT 425.220000 2686.760000 426.320000 2687.240000 ;
+ RECT 425.220000 2675.880000 426.320000 2676.360000 ;
+ RECT 425.220000 2681.320000 426.320000 2681.800000 ;
+ RECT 438.030000 2675.880000 439.030000 2676.360000 ;
+ RECT 438.030000 2681.320000 439.030000 2681.800000 ;
+ RECT 438.030000 2665.000000 439.030000 2665.480000 ;
+ RECT 438.030000 2670.440000 439.030000 2670.920000 ;
+ RECT 425.220000 2670.440000 426.320000 2670.920000 ;
+ RECT 425.220000 2665.000000 426.320000 2665.480000 ;
+ RECT 425.220000 2654.120000 426.320000 2654.600000 ;
+ RECT 425.220000 2659.560000 426.320000 2660.040000 ;
+ RECT 438.030000 2654.120000 439.030000 2654.600000 ;
+ RECT 438.030000 2659.560000 439.030000 2660.040000 ;
+ RECT 380.220000 2675.880000 381.320000 2676.360000 ;
+ RECT 380.220000 2681.320000 381.320000 2681.800000 ;
+ RECT 380.220000 2686.760000 381.320000 2687.240000 ;
+ RECT 380.220000 2692.200000 381.320000 2692.680000 ;
+ RECT 380.220000 2697.640000 381.320000 2698.120000 ;
+ RECT 380.220000 2654.120000 381.320000 2654.600000 ;
+ RECT 380.220000 2659.560000 381.320000 2660.040000 ;
+ RECT 380.220000 2665.000000 381.320000 2665.480000 ;
+ RECT 380.220000 2670.440000 381.320000 2670.920000 ;
+ RECT 335.220000 2730.280000 336.320000 2730.760000 ;
+ RECT 335.220000 2724.840000 336.320000 2725.320000 ;
+ RECT 335.220000 2735.720000 336.320000 2736.200000 ;
+ RECT 335.220000 2741.160000 336.320000 2741.640000 ;
+ RECT 290.220000 2724.840000 291.320000 2725.320000 ;
+ RECT 290.220000 2730.280000 291.320000 2730.760000 ;
+ RECT 290.220000 2735.720000 291.320000 2736.200000 ;
+ RECT 290.220000 2741.160000 291.320000 2741.640000 ;
+ RECT 335.220000 2703.080000 336.320000 2703.560000 ;
+ RECT 335.220000 2708.520000 336.320000 2709.000000 ;
+ RECT 335.220000 2713.960000 336.320000 2714.440000 ;
+ RECT 335.220000 2719.400000 336.320000 2719.880000 ;
+ RECT 290.220000 2703.080000 291.320000 2703.560000 ;
+ RECT 290.220000 2708.520000 291.320000 2709.000000 ;
+ RECT 290.220000 2713.960000 291.320000 2714.440000 ;
+ RECT 290.220000 2719.400000 291.320000 2719.880000 ;
+ RECT 241.390000 2741.160000 242.390000 2741.640000 ;
+ RECT 245.055000 2741.160000 246.320000 2741.640000 ;
+ RECT 241.390000 2730.280000 242.390000 2730.760000 ;
+ RECT 245.055000 2730.280000 246.320000 2730.760000 ;
+ RECT 241.390000 2735.720000 242.390000 2736.200000 ;
+ RECT 245.055000 2735.720000 246.320000 2736.200000 ;
+ RECT 241.390000 2724.840000 242.390000 2725.320000 ;
+ RECT 245.055000 2724.840000 246.320000 2725.320000 ;
+ RECT 241.390000 2719.400000 242.390000 2719.880000 ;
+ RECT 245.055000 2719.400000 246.320000 2719.880000 ;
+ RECT 241.390000 2713.960000 242.390000 2714.440000 ;
+ RECT 245.055000 2713.960000 246.320000 2714.440000 ;
+ RECT 241.390000 2708.520000 242.390000 2709.000000 ;
+ RECT 245.055000 2708.520000 246.320000 2709.000000 ;
+ RECT 241.390000 2703.080000 242.390000 2703.560000 ;
+ RECT 245.055000 2703.080000 246.320000 2703.560000 ;
+ RECT 335.220000 2675.880000 336.320000 2676.360000 ;
+ RECT 335.220000 2681.320000 336.320000 2681.800000 ;
+ RECT 335.220000 2686.760000 336.320000 2687.240000 ;
+ RECT 335.220000 2692.200000 336.320000 2692.680000 ;
+ RECT 335.220000 2697.640000 336.320000 2698.120000 ;
+ RECT 290.220000 2675.880000 291.320000 2676.360000 ;
+ RECT 290.220000 2681.320000 291.320000 2681.800000 ;
+ RECT 290.220000 2686.760000 291.320000 2687.240000 ;
+ RECT 290.220000 2692.200000 291.320000 2692.680000 ;
+ RECT 290.220000 2697.640000 291.320000 2698.120000 ;
+ RECT 335.220000 2654.120000 336.320000 2654.600000 ;
+ RECT 335.220000 2659.560000 336.320000 2660.040000 ;
+ RECT 335.220000 2665.000000 336.320000 2665.480000 ;
+ RECT 335.220000 2670.440000 336.320000 2670.920000 ;
+ RECT 290.220000 2654.120000 291.320000 2654.600000 ;
+ RECT 290.220000 2659.560000 291.320000 2660.040000 ;
+ RECT 290.220000 2665.000000 291.320000 2665.480000 ;
+ RECT 290.220000 2670.440000 291.320000 2670.920000 ;
+ RECT 241.390000 2697.640000 242.390000 2698.120000 ;
+ RECT 245.055000 2697.640000 246.320000 2698.120000 ;
+ RECT 241.390000 2686.760000 242.390000 2687.240000 ;
+ RECT 245.055000 2686.760000 246.320000 2687.240000 ;
+ RECT 241.390000 2692.200000 242.390000 2692.680000 ;
+ RECT 245.055000 2692.200000 246.320000 2692.680000 ;
+ RECT 241.390000 2681.320000 242.390000 2681.800000 ;
+ RECT 245.055000 2681.320000 246.320000 2681.800000 ;
+ RECT 241.390000 2675.880000 242.390000 2676.360000 ;
+ RECT 245.055000 2675.880000 246.320000 2676.360000 ;
+ RECT 241.390000 2670.440000 242.390000 2670.920000 ;
+ RECT 245.055000 2670.440000 246.320000 2670.920000 ;
+ RECT 241.390000 2665.000000 242.390000 2665.480000 ;
+ RECT 245.055000 2665.000000 246.320000 2665.480000 ;
+ RECT 241.390000 2659.560000 242.390000 2660.040000 ;
+ RECT 245.055000 2659.560000 246.320000 2660.040000 ;
+ RECT 241.390000 2654.120000 242.390000 2654.600000 ;
+ RECT 245.055000 2654.120000 246.320000 2654.600000 ;
+ RECT 425.220000 2637.800000 426.320000 2638.280000 ;
+ RECT 425.220000 2643.240000 426.320000 2643.720000 ;
+ RECT 438.030000 2637.800000 439.030000 2638.280000 ;
+ RECT 438.030000 2643.240000 439.030000 2643.720000 ;
+ RECT 438.030000 2626.920000 439.030000 2627.400000 ;
+ RECT 438.030000 2632.360000 439.030000 2632.840000 ;
+ RECT 425.220000 2632.360000 426.320000 2632.840000 ;
+ RECT 425.220000 2626.920000 426.320000 2627.400000 ;
+ RECT 425.220000 2616.040000 426.320000 2616.520000 ;
+ RECT 425.220000 2621.480000 426.320000 2621.960000 ;
+ RECT 438.030000 2616.040000 439.030000 2616.520000 ;
+ RECT 438.030000 2621.480000 439.030000 2621.960000 ;
+ RECT 438.030000 2605.160000 439.030000 2605.640000 ;
+ RECT 438.030000 2599.720000 439.030000 2600.200000 ;
+ RECT 438.030000 2610.600000 439.030000 2611.080000 ;
+ RECT 425.220000 2610.600000 426.320000 2611.080000 ;
+ RECT 425.220000 2605.160000 426.320000 2605.640000 ;
+ RECT 425.220000 2599.720000 426.320000 2600.200000 ;
+ RECT 380.220000 2626.920000 381.320000 2627.400000 ;
+ RECT 380.220000 2632.360000 381.320000 2632.840000 ;
+ RECT 380.220000 2637.800000 381.320000 2638.280000 ;
+ RECT 380.220000 2643.240000 381.320000 2643.720000 ;
+ RECT 380.220000 2599.720000 381.320000 2600.200000 ;
+ RECT 380.220000 2605.160000 381.320000 2605.640000 ;
+ RECT 380.220000 2610.600000 381.320000 2611.080000 ;
+ RECT 380.220000 2616.040000 381.320000 2616.520000 ;
+ RECT 380.220000 2621.480000 381.320000 2621.960000 ;
+ RECT 425.220000 2588.840000 426.320000 2589.320000 ;
+ RECT 425.220000 2594.280000 426.320000 2594.760000 ;
+ RECT 438.030000 2588.840000 439.030000 2589.320000 ;
+ RECT 438.030000 2594.280000 439.030000 2594.760000 ;
+ RECT 425.220000 2577.960000 426.320000 2578.440000 ;
+ RECT 425.220000 2583.400000 426.320000 2583.880000 ;
+ RECT 438.030000 2577.960000 439.030000 2578.440000 ;
+ RECT 438.030000 2583.400000 439.030000 2583.880000 ;
+ RECT 438.030000 2567.080000 439.030000 2567.560000 ;
+ RECT 438.030000 2561.640000 439.030000 2562.120000 ;
+ RECT 438.030000 2572.520000 439.030000 2573.000000 ;
+ RECT 425.220000 2572.520000 426.320000 2573.000000 ;
+ RECT 425.220000 2567.080000 426.320000 2567.560000 ;
+ RECT 425.220000 2561.640000 426.320000 2562.120000 ;
+ RECT 425.220000 2556.200000 426.320000 2556.680000 ;
+ RECT 438.030000 2556.200000 439.030000 2556.680000 ;
+ RECT 380.220000 2577.960000 381.320000 2578.440000 ;
+ RECT 380.220000 2583.400000 381.320000 2583.880000 ;
+ RECT 380.220000 2588.840000 381.320000 2589.320000 ;
+ RECT 380.220000 2594.280000 381.320000 2594.760000 ;
+ RECT 380.220000 2556.200000 381.320000 2556.680000 ;
+ RECT 380.220000 2561.640000 381.320000 2562.120000 ;
+ RECT 380.220000 2567.080000 381.320000 2567.560000 ;
+ RECT 380.220000 2572.520000 381.320000 2573.000000 ;
+ RECT 335.220000 2626.920000 336.320000 2627.400000 ;
+ RECT 335.220000 2632.360000 336.320000 2632.840000 ;
+ RECT 335.220000 2637.800000 336.320000 2638.280000 ;
+ RECT 335.220000 2643.240000 336.320000 2643.720000 ;
+ RECT 290.220000 2626.920000 291.320000 2627.400000 ;
+ RECT 290.220000 2632.360000 291.320000 2632.840000 ;
+ RECT 290.220000 2637.800000 291.320000 2638.280000 ;
+ RECT 290.220000 2643.240000 291.320000 2643.720000 ;
+ RECT 335.220000 2599.720000 336.320000 2600.200000 ;
+ RECT 335.220000 2605.160000 336.320000 2605.640000 ;
+ RECT 335.220000 2610.600000 336.320000 2611.080000 ;
+ RECT 335.220000 2616.040000 336.320000 2616.520000 ;
+ RECT 335.220000 2621.480000 336.320000 2621.960000 ;
+ RECT 290.220000 2599.720000 291.320000 2600.200000 ;
+ RECT 290.220000 2605.160000 291.320000 2605.640000 ;
+ RECT 290.220000 2610.600000 291.320000 2611.080000 ;
+ RECT 290.220000 2616.040000 291.320000 2616.520000 ;
+ RECT 290.220000 2621.480000 291.320000 2621.960000 ;
+ RECT 241.390000 2643.240000 242.390000 2643.720000 ;
+ RECT 245.055000 2643.240000 246.320000 2643.720000 ;
+ RECT 241.390000 2637.800000 242.390000 2638.280000 ;
+ RECT 245.055000 2637.800000 246.320000 2638.280000 ;
+ RECT 241.390000 2632.360000 242.390000 2632.840000 ;
+ RECT 245.055000 2632.360000 246.320000 2632.840000 ;
+ RECT 241.390000 2626.920000 242.390000 2627.400000 ;
+ RECT 245.055000 2626.920000 246.320000 2627.400000 ;
+ RECT 241.390000 2621.480000 242.390000 2621.960000 ;
+ RECT 245.055000 2621.480000 246.320000 2621.960000 ;
+ RECT 241.390000 2616.040000 242.390000 2616.520000 ;
+ RECT 245.055000 2616.040000 246.320000 2616.520000 ;
+ RECT 241.390000 2605.160000 242.390000 2605.640000 ;
+ RECT 245.055000 2605.160000 246.320000 2605.640000 ;
+ RECT 241.390000 2610.600000 242.390000 2611.080000 ;
+ RECT 245.055000 2610.600000 246.320000 2611.080000 ;
+ RECT 241.390000 2599.720000 242.390000 2600.200000 ;
+ RECT 245.055000 2599.720000 246.320000 2600.200000 ;
+ RECT 335.220000 2577.960000 336.320000 2578.440000 ;
+ RECT 335.220000 2583.400000 336.320000 2583.880000 ;
+ RECT 335.220000 2588.840000 336.320000 2589.320000 ;
+ RECT 335.220000 2594.280000 336.320000 2594.760000 ;
+ RECT 290.220000 2577.960000 291.320000 2578.440000 ;
+ RECT 290.220000 2583.400000 291.320000 2583.880000 ;
+ RECT 290.220000 2588.840000 291.320000 2589.320000 ;
+ RECT 290.220000 2594.280000 291.320000 2594.760000 ;
+ RECT 335.220000 2556.200000 336.320000 2556.680000 ;
+ RECT 335.220000 2561.640000 336.320000 2562.120000 ;
+ RECT 335.220000 2567.080000 336.320000 2567.560000 ;
+ RECT 335.220000 2572.520000 336.320000 2573.000000 ;
+ RECT 290.220000 2556.200000 291.320000 2556.680000 ;
+ RECT 290.220000 2561.640000 291.320000 2562.120000 ;
+ RECT 290.220000 2567.080000 291.320000 2567.560000 ;
+ RECT 290.220000 2572.520000 291.320000 2573.000000 ;
+ RECT 241.390000 2594.280000 242.390000 2594.760000 ;
+ RECT 245.055000 2594.280000 246.320000 2594.760000 ;
+ RECT 241.390000 2588.840000 242.390000 2589.320000 ;
+ RECT 245.055000 2588.840000 246.320000 2589.320000 ;
+ RECT 241.390000 2583.400000 242.390000 2583.880000 ;
+ RECT 245.055000 2583.400000 246.320000 2583.880000 ;
+ RECT 241.390000 2577.960000 242.390000 2578.440000 ;
+ RECT 245.055000 2577.960000 246.320000 2578.440000 ;
+ RECT 241.390000 2572.520000 242.390000 2573.000000 ;
+ RECT 245.055000 2572.520000 246.320000 2573.000000 ;
+ RECT 241.390000 2561.640000 242.390000 2562.120000 ;
+ RECT 245.055000 2561.640000 246.320000 2562.120000 ;
+ RECT 241.390000 2567.080000 242.390000 2567.560000 ;
+ RECT 245.055000 2567.080000 246.320000 2567.560000 ;
+ RECT 241.390000 2556.200000 242.390000 2556.680000 ;
+ RECT 245.055000 2556.200000 246.320000 2556.680000 ;
+ RECT 380.220000 2648.680000 381.320000 2649.160000 ;
+ RECT 425.220000 2648.680000 426.320000 2649.160000 ;
+ RECT 438.030000 2648.680000 439.030000 2649.160000 ;
+ RECT 290.220000 2648.680000 291.320000 2649.160000 ;
+ RECT 335.220000 2648.680000 336.320000 2649.160000 ;
+ RECT 241.390000 2648.680000 242.390000 2649.160000 ;
+ RECT 245.055000 2648.680000 246.320000 2649.160000 ;
+ RECT 240.160000 2745.440000 440.260000 2746.440000 ;
+ RECT 240.160000 2549.870000 440.260000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 2548.620000 242.390000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 2747.880000 242.390000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 2548.620000 439.030000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 2747.880000 439.030000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2549.870000 241.160000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2549.870000 440.260000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2745.440000 241.160000 2746.440000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2745.440000 440.260000 2746.440000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 2540.900000 246.320000 2541.380000 ;
+ RECT 245.055000 2530.020000 246.320000 2530.500000 ;
+ RECT 245.055000 2535.460000 246.320000 2535.940000 ;
+ RECT 245.055000 2524.580000 246.320000 2525.060000 ;
+ RECT 245.055000 2519.140000 246.320000 2519.620000 ;
+ RECT 245.055000 2513.700000 246.320000 2514.180000 ;
+ RECT 245.055000 2508.260000 246.320000 2508.740000 ;
+ RECT 245.055000 2502.820000 246.320000 2503.300000 ;
+ RECT 245.055000 2497.380000 246.320000 2497.860000 ;
+ RECT 245.055000 2486.500000 246.320000 2486.980000 ;
+ RECT 245.055000 2491.940000 246.320000 2492.420000 ;
+ RECT 245.055000 2481.060000 246.320000 2481.540000 ;
+ RECT 245.055000 2475.620000 246.320000 2476.100000 ;
+ RECT 245.055000 2470.180000 246.320000 2470.660000 ;
+ RECT 245.055000 2464.740000 246.320000 2465.220000 ;
+ RECT 245.055000 2459.300000 246.320000 2459.780000 ;
+ RECT 245.055000 2453.860000 246.320000 2454.340000 ;
+ RECT 245.055000 2442.980000 246.320000 2443.460000 ;
+ RECT 245.055000 2437.540000 246.320000 2438.020000 ;
+ RECT 245.055000 2432.100000 246.320000 2432.580000 ;
+ RECT 245.055000 2426.660000 246.320000 2427.140000 ;
+ RECT 245.055000 2421.220000 246.320000 2421.700000 ;
+ RECT 245.055000 2415.780000 246.320000 2416.260000 ;
+ RECT 245.055000 2404.900000 246.320000 2405.380000 ;
+ RECT 245.055000 2410.340000 246.320000 2410.820000 ;
+ RECT 245.055000 2399.460000 246.320000 2399.940000 ;
+ RECT 245.055000 2394.020000 246.320000 2394.500000 ;
+ RECT 245.055000 2388.580000 246.320000 2389.060000 ;
+ RECT 245.055000 2383.140000 246.320000 2383.620000 ;
+ RECT 245.055000 2377.700000 246.320000 2378.180000 ;
+ RECT 245.055000 2372.260000 246.320000 2372.740000 ;
+ RECT 245.055000 2361.380000 246.320000 2361.860000 ;
+ RECT 245.055000 2366.820000 246.320000 2367.300000 ;
+ RECT 245.055000 2355.940000 246.320000 2356.420000 ;
+ RECT 245.055000 2448.420000 246.320000 2448.900000 ;
+ RECT 425.220000 2349.610000 426.320000 2546.180000 ;
+ RECT 380.220000 2349.610000 381.320000 2546.180000 ;
+ RECT 438.030000 2348.360000 439.030000 2548.620000 ;
+ RECT 335.220000 2349.610000 336.320000 2546.180000 ;
+ RECT 290.220000 2349.610000 291.320000 2546.180000 ;
+ RECT 245.220000 2349.610000 246.320000 2546.180000 ;
+ RECT 241.390000 2348.360000 242.390000 2548.620000 ;
+ LAYER met3 ;
+ RECT 425.220000 2540.900000 426.320000 2541.380000 ;
+ RECT 438.030000 2540.900000 439.030000 2541.380000 ;
+ RECT 438.030000 2530.020000 439.030000 2530.500000 ;
+ RECT 438.030000 2524.580000 439.030000 2525.060000 ;
+ RECT 438.030000 2535.460000 439.030000 2535.940000 ;
+ RECT 425.220000 2535.460000 426.320000 2535.940000 ;
+ RECT 425.220000 2530.020000 426.320000 2530.500000 ;
+ RECT 425.220000 2524.580000 426.320000 2525.060000 ;
+ RECT 425.220000 2513.700000 426.320000 2514.180000 ;
+ RECT 425.220000 2519.140000 426.320000 2519.620000 ;
+ RECT 438.030000 2513.700000 439.030000 2514.180000 ;
+ RECT 438.030000 2519.140000 439.030000 2519.620000 ;
+ RECT 425.220000 2502.820000 426.320000 2503.300000 ;
+ RECT 425.220000 2508.260000 426.320000 2508.740000 ;
+ RECT 438.030000 2502.820000 439.030000 2503.300000 ;
+ RECT 438.030000 2508.260000 439.030000 2508.740000 ;
+ RECT 380.220000 2524.580000 381.320000 2525.060000 ;
+ RECT 380.220000 2530.020000 381.320000 2530.500000 ;
+ RECT 380.220000 2535.460000 381.320000 2535.940000 ;
+ RECT 380.220000 2540.900000 381.320000 2541.380000 ;
+ RECT 380.220000 2508.260000 381.320000 2508.740000 ;
+ RECT 380.220000 2502.820000 381.320000 2503.300000 ;
+ RECT 380.220000 2513.700000 381.320000 2514.180000 ;
+ RECT 380.220000 2519.140000 381.320000 2519.620000 ;
+ RECT 438.030000 2491.940000 439.030000 2492.420000 ;
+ RECT 438.030000 2486.500000 439.030000 2486.980000 ;
+ RECT 438.030000 2497.380000 439.030000 2497.860000 ;
+ RECT 425.220000 2497.380000 426.320000 2497.860000 ;
+ RECT 425.220000 2491.940000 426.320000 2492.420000 ;
+ RECT 425.220000 2486.500000 426.320000 2486.980000 ;
+ RECT 425.220000 2475.620000 426.320000 2476.100000 ;
+ RECT 425.220000 2481.060000 426.320000 2481.540000 ;
+ RECT 438.030000 2475.620000 439.030000 2476.100000 ;
+ RECT 438.030000 2481.060000 439.030000 2481.540000 ;
+ RECT 438.030000 2464.740000 439.030000 2465.220000 ;
+ RECT 438.030000 2470.180000 439.030000 2470.660000 ;
+ RECT 425.220000 2470.180000 426.320000 2470.660000 ;
+ RECT 425.220000 2464.740000 426.320000 2465.220000 ;
+ RECT 425.220000 2453.860000 426.320000 2454.340000 ;
+ RECT 425.220000 2459.300000 426.320000 2459.780000 ;
+ RECT 438.030000 2453.860000 439.030000 2454.340000 ;
+ RECT 438.030000 2459.300000 439.030000 2459.780000 ;
+ RECT 380.220000 2475.620000 381.320000 2476.100000 ;
+ RECT 380.220000 2481.060000 381.320000 2481.540000 ;
+ RECT 380.220000 2486.500000 381.320000 2486.980000 ;
+ RECT 380.220000 2491.940000 381.320000 2492.420000 ;
+ RECT 380.220000 2497.380000 381.320000 2497.860000 ;
+ RECT 380.220000 2453.860000 381.320000 2454.340000 ;
+ RECT 380.220000 2459.300000 381.320000 2459.780000 ;
+ RECT 380.220000 2464.740000 381.320000 2465.220000 ;
+ RECT 380.220000 2470.180000 381.320000 2470.660000 ;
+ RECT 335.220000 2530.020000 336.320000 2530.500000 ;
+ RECT 335.220000 2524.580000 336.320000 2525.060000 ;
+ RECT 335.220000 2535.460000 336.320000 2535.940000 ;
+ RECT 335.220000 2540.900000 336.320000 2541.380000 ;
+ RECT 290.220000 2524.580000 291.320000 2525.060000 ;
+ RECT 290.220000 2530.020000 291.320000 2530.500000 ;
+ RECT 290.220000 2535.460000 291.320000 2535.940000 ;
+ RECT 290.220000 2540.900000 291.320000 2541.380000 ;
+ RECT 335.220000 2502.820000 336.320000 2503.300000 ;
+ RECT 335.220000 2508.260000 336.320000 2508.740000 ;
+ RECT 335.220000 2513.700000 336.320000 2514.180000 ;
+ RECT 335.220000 2519.140000 336.320000 2519.620000 ;
+ RECT 290.220000 2502.820000 291.320000 2503.300000 ;
+ RECT 290.220000 2508.260000 291.320000 2508.740000 ;
+ RECT 290.220000 2513.700000 291.320000 2514.180000 ;
+ RECT 290.220000 2519.140000 291.320000 2519.620000 ;
+ RECT 241.390000 2540.900000 242.390000 2541.380000 ;
+ RECT 245.055000 2540.900000 246.320000 2541.380000 ;
+ RECT 241.390000 2530.020000 242.390000 2530.500000 ;
+ RECT 245.055000 2530.020000 246.320000 2530.500000 ;
+ RECT 241.390000 2535.460000 242.390000 2535.940000 ;
+ RECT 245.055000 2535.460000 246.320000 2535.940000 ;
+ RECT 241.390000 2524.580000 242.390000 2525.060000 ;
+ RECT 245.055000 2524.580000 246.320000 2525.060000 ;
+ RECT 241.390000 2519.140000 242.390000 2519.620000 ;
+ RECT 245.055000 2519.140000 246.320000 2519.620000 ;
+ RECT 241.390000 2513.700000 242.390000 2514.180000 ;
+ RECT 245.055000 2513.700000 246.320000 2514.180000 ;
+ RECT 241.390000 2508.260000 242.390000 2508.740000 ;
+ RECT 245.055000 2508.260000 246.320000 2508.740000 ;
+ RECT 241.390000 2502.820000 242.390000 2503.300000 ;
+ RECT 245.055000 2502.820000 246.320000 2503.300000 ;
+ RECT 335.220000 2475.620000 336.320000 2476.100000 ;
+ RECT 335.220000 2481.060000 336.320000 2481.540000 ;
+ RECT 335.220000 2486.500000 336.320000 2486.980000 ;
+ RECT 335.220000 2491.940000 336.320000 2492.420000 ;
+ RECT 335.220000 2497.380000 336.320000 2497.860000 ;
+ RECT 290.220000 2475.620000 291.320000 2476.100000 ;
+ RECT 290.220000 2481.060000 291.320000 2481.540000 ;
+ RECT 290.220000 2486.500000 291.320000 2486.980000 ;
+ RECT 290.220000 2491.940000 291.320000 2492.420000 ;
+ RECT 290.220000 2497.380000 291.320000 2497.860000 ;
+ RECT 335.220000 2453.860000 336.320000 2454.340000 ;
+ RECT 335.220000 2459.300000 336.320000 2459.780000 ;
+ RECT 335.220000 2464.740000 336.320000 2465.220000 ;
+ RECT 335.220000 2470.180000 336.320000 2470.660000 ;
+ RECT 290.220000 2453.860000 291.320000 2454.340000 ;
+ RECT 290.220000 2459.300000 291.320000 2459.780000 ;
+ RECT 290.220000 2464.740000 291.320000 2465.220000 ;
+ RECT 290.220000 2470.180000 291.320000 2470.660000 ;
+ RECT 241.390000 2497.380000 242.390000 2497.860000 ;
+ RECT 245.055000 2497.380000 246.320000 2497.860000 ;
+ RECT 241.390000 2486.500000 242.390000 2486.980000 ;
+ RECT 245.055000 2486.500000 246.320000 2486.980000 ;
+ RECT 241.390000 2491.940000 242.390000 2492.420000 ;
+ RECT 245.055000 2491.940000 246.320000 2492.420000 ;
+ RECT 241.390000 2481.060000 242.390000 2481.540000 ;
+ RECT 245.055000 2481.060000 246.320000 2481.540000 ;
+ RECT 241.390000 2475.620000 242.390000 2476.100000 ;
+ RECT 245.055000 2475.620000 246.320000 2476.100000 ;
+ RECT 241.390000 2470.180000 242.390000 2470.660000 ;
+ RECT 245.055000 2470.180000 246.320000 2470.660000 ;
+ RECT 241.390000 2464.740000 242.390000 2465.220000 ;
+ RECT 245.055000 2464.740000 246.320000 2465.220000 ;
+ RECT 241.390000 2459.300000 242.390000 2459.780000 ;
+ RECT 245.055000 2459.300000 246.320000 2459.780000 ;
+ RECT 241.390000 2453.860000 242.390000 2454.340000 ;
+ RECT 245.055000 2453.860000 246.320000 2454.340000 ;
+ RECT 425.220000 2437.540000 426.320000 2438.020000 ;
+ RECT 425.220000 2442.980000 426.320000 2443.460000 ;
+ RECT 438.030000 2437.540000 439.030000 2438.020000 ;
+ RECT 438.030000 2442.980000 439.030000 2443.460000 ;
+ RECT 438.030000 2426.660000 439.030000 2427.140000 ;
+ RECT 438.030000 2432.100000 439.030000 2432.580000 ;
+ RECT 425.220000 2432.100000 426.320000 2432.580000 ;
+ RECT 425.220000 2426.660000 426.320000 2427.140000 ;
+ RECT 425.220000 2415.780000 426.320000 2416.260000 ;
+ RECT 425.220000 2421.220000 426.320000 2421.700000 ;
+ RECT 438.030000 2415.780000 439.030000 2416.260000 ;
+ RECT 438.030000 2421.220000 439.030000 2421.700000 ;
+ RECT 438.030000 2404.900000 439.030000 2405.380000 ;
+ RECT 438.030000 2399.460000 439.030000 2399.940000 ;
+ RECT 438.030000 2410.340000 439.030000 2410.820000 ;
+ RECT 425.220000 2410.340000 426.320000 2410.820000 ;
+ RECT 425.220000 2404.900000 426.320000 2405.380000 ;
+ RECT 425.220000 2399.460000 426.320000 2399.940000 ;
+ RECT 380.220000 2426.660000 381.320000 2427.140000 ;
+ RECT 380.220000 2432.100000 381.320000 2432.580000 ;
+ RECT 380.220000 2437.540000 381.320000 2438.020000 ;
+ RECT 380.220000 2442.980000 381.320000 2443.460000 ;
+ RECT 380.220000 2399.460000 381.320000 2399.940000 ;
+ RECT 380.220000 2404.900000 381.320000 2405.380000 ;
+ RECT 380.220000 2410.340000 381.320000 2410.820000 ;
+ RECT 380.220000 2415.780000 381.320000 2416.260000 ;
+ RECT 380.220000 2421.220000 381.320000 2421.700000 ;
+ RECT 425.220000 2388.580000 426.320000 2389.060000 ;
+ RECT 425.220000 2394.020000 426.320000 2394.500000 ;
+ RECT 438.030000 2388.580000 439.030000 2389.060000 ;
+ RECT 438.030000 2394.020000 439.030000 2394.500000 ;
+ RECT 425.220000 2377.700000 426.320000 2378.180000 ;
+ RECT 425.220000 2383.140000 426.320000 2383.620000 ;
+ RECT 438.030000 2377.700000 439.030000 2378.180000 ;
+ RECT 438.030000 2383.140000 439.030000 2383.620000 ;
+ RECT 438.030000 2366.820000 439.030000 2367.300000 ;
+ RECT 438.030000 2361.380000 439.030000 2361.860000 ;
+ RECT 438.030000 2372.260000 439.030000 2372.740000 ;
+ RECT 425.220000 2372.260000 426.320000 2372.740000 ;
+ RECT 425.220000 2366.820000 426.320000 2367.300000 ;
+ RECT 425.220000 2361.380000 426.320000 2361.860000 ;
+ RECT 425.220000 2355.940000 426.320000 2356.420000 ;
+ RECT 438.030000 2355.940000 439.030000 2356.420000 ;
+ RECT 380.220000 2377.700000 381.320000 2378.180000 ;
+ RECT 380.220000 2383.140000 381.320000 2383.620000 ;
+ RECT 380.220000 2388.580000 381.320000 2389.060000 ;
+ RECT 380.220000 2394.020000 381.320000 2394.500000 ;
+ RECT 380.220000 2355.940000 381.320000 2356.420000 ;
+ RECT 380.220000 2361.380000 381.320000 2361.860000 ;
+ RECT 380.220000 2366.820000 381.320000 2367.300000 ;
+ RECT 380.220000 2372.260000 381.320000 2372.740000 ;
+ RECT 335.220000 2426.660000 336.320000 2427.140000 ;
+ RECT 335.220000 2432.100000 336.320000 2432.580000 ;
+ RECT 335.220000 2437.540000 336.320000 2438.020000 ;
+ RECT 335.220000 2442.980000 336.320000 2443.460000 ;
+ RECT 290.220000 2426.660000 291.320000 2427.140000 ;
+ RECT 290.220000 2432.100000 291.320000 2432.580000 ;
+ RECT 290.220000 2437.540000 291.320000 2438.020000 ;
+ RECT 290.220000 2442.980000 291.320000 2443.460000 ;
+ RECT 335.220000 2399.460000 336.320000 2399.940000 ;
+ RECT 335.220000 2404.900000 336.320000 2405.380000 ;
+ RECT 335.220000 2410.340000 336.320000 2410.820000 ;
+ RECT 335.220000 2415.780000 336.320000 2416.260000 ;
+ RECT 335.220000 2421.220000 336.320000 2421.700000 ;
+ RECT 290.220000 2399.460000 291.320000 2399.940000 ;
+ RECT 290.220000 2404.900000 291.320000 2405.380000 ;
+ RECT 290.220000 2410.340000 291.320000 2410.820000 ;
+ RECT 290.220000 2415.780000 291.320000 2416.260000 ;
+ RECT 290.220000 2421.220000 291.320000 2421.700000 ;
+ RECT 241.390000 2442.980000 242.390000 2443.460000 ;
+ RECT 245.055000 2442.980000 246.320000 2443.460000 ;
+ RECT 241.390000 2437.540000 242.390000 2438.020000 ;
+ RECT 245.055000 2437.540000 246.320000 2438.020000 ;
+ RECT 241.390000 2432.100000 242.390000 2432.580000 ;
+ RECT 245.055000 2432.100000 246.320000 2432.580000 ;
+ RECT 241.390000 2426.660000 242.390000 2427.140000 ;
+ RECT 245.055000 2426.660000 246.320000 2427.140000 ;
+ RECT 241.390000 2421.220000 242.390000 2421.700000 ;
+ RECT 245.055000 2421.220000 246.320000 2421.700000 ;
+ RECT 241.390000 2415.780000 242.390000 2416.260000 ;
+ RECT 245.055000 2415.780000 246.320000 2416.260000 ;
+ RECT 241.390000 2404.900000 242.390000 2405.380000 ;
+ RECT 245.055000 2404.900000 246.320000 2405.380000 ;
+ RECT 241.390000 2410.340000 242.390000 2410.820000 ;
+ RECT 245.055000 2410.340000 246.320000 2410.820000 ;
+ RECT 241.390000 2399.460000 242.390000 2399.940000 ;
+ RECT 245.055000 2399.460000 246.320000 2399.940000 ;
+ RECT 335.220000 2377.700000 336.320000 2378.180000 ;
+ RECT 335.220000 2383.140000 336.320000 2383.620000 ;
+ RECT 335.220000 2388.580000 336.320000 2389.060000 ;
+ RECT 335.220000 2394.020000 336.320000 2394.500000 ;
+ RECT 290.220000 2377.700000 291.320000 2378.180000 ;
+ RECT 290.220000 2383.140000 291.320000 2383.620000 ;
+ RECT 290.220000 2388.580000 291.320000 2389.060000 ;
+ RECT 290.220000 2394.020000 291.320000 2394.500000 ;
+ RECT 335.220000 2355.940000 336.320000 2356.420000 ;
+ RECT 335.220000 2361.380000 336.320000 2361.860000 ;
+ RECT 335.220000 2366.820000 336.320000 2367.300000 ;
+ RECT 335.220000 2372.260000 336.320000 2372.740000 ;
+ RECT 290.220000 2355.940000 291.320000 2356.420000 ;
+ RECT 290.220000 2361.380000 291.320000 2361.860000 ;
+ RECT 290.220000 2366.820000 291.320000 2367.300000 ;
+ RECT 290.220000 2372.260000 291.320000 2372.740000 ;
+ RECT 241.390000 2394.020000 242.390000 2394.500000 ;
+ RECT 245.055000 2394.020000 246.320000 2394.500000 ;
+ RECT 241.390000 2388.580000 242.390000 2389.060000 ;
+ RECT 245.055000 2388.580000 246.320000 2389.060000 ;
+ RECT 241.390000 2383.140000 242.390000 2383.620000 ;
+ RECT 245.055000 2383.140000 246.320000 2383.620000 ;
+ RECT 241.390000 2377.700000 242.390000 2378.180000 ;
+ RECT 245.055000 2377.700000 246.320000 2378.180000 ;
+ RECT 241.390000 2372.260000 242.390000 2372.740000 ;
+ RECT 245.055000 2372.260000 246.320000 2372.740000 ;
+ RECT 241.390000 2361.380000 242.390000 2361.860000 ;
+ RECT 245.055000 2361.380000 246.320000 2361.860000 ;
+ RECT 241.390000 2366.820000 242.390000 2367.300000 ;
+ RECT 245.055000 2366.820000 246.320000 2367.300000 ;
+ RECT 241.390000 2355.940000 242.390000 2356.420000 ;
+ RECT 245.055000 2355.940000 246.320000 2356.420000 ;
+ RECT 380.220000 2448.420000 381.320000 2448.900000 ;
+ RECT 425.220000 2448.420000 426.320000 2448.900000 ;
+ RECT 438.030000 2448.420000 439.030000 2448.900000 ;
+ RECT 290.220000 2448.420000 291.320000 2448.900000 ;
+ RECT 335.220000 2448.420000 336.320000 2448.900000 ;
+ RECT 241.390000 2448.420000 242.390000 2448.900000 ;
+ RECT 245.055000 2448.420000 246.320000 2448.900000 ;
+ RECT 240.160000 2545.180000 440.260000 2546.180000 ;
+ RECT 240.160000 2349.610000 440.260000 2350.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 2348.360000 242.390000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 2547.620000 242.390000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 2348.360000 439.030000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 2547.620000 439.030000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2349.610000 241.160000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2349.610000 440.260000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2545.180000 241.160000 2546.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2545.180000 440.260000 2546.180000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 2340.640000 246.320000 2341.120000 ;
+ RECT 245.055000 2329.760000 246.320000 2330.240000 ;
+ RECT 245.055000 2335.200000 246.320000 2335.680000 ;
+ RECT 245.055000 2324.320000 246.320000 2324.800000 ;
+ RECT 245.055000 2318.880000 246.320000 2319.360000 ;
+ RECT 245.055000 2313.440000 246.320000 2313.920000 ;
+ RECT 245.055000 2308.000000 246.320000 2308.480000 ;
+ RECT 245.055000 2302.560000 246.320000 2303.040000 ;
+ RECT 245.055000 2297.120000 246.320000 2297.600000 ;
+ RECT 245.055000 2286.240000 246.320000 2286.720000 ;
+ RECT 245.055000 2291.680000 246.320000 2292.160000 ;
+ RECT 245.055000 2280.800000 246.320000 2281.280000 ;
+ RECT 245.055000 2275.360000 246.320000 2275.840000 ;
+ RECT 245.055000 2269.920000 246.320000 2270.400000 ;
+ RECT 245.055000 2264.480000 246.320000 2264.960000 ;
+ RECT 245.055000 2259.040000 246.320000 2259.520000 ;
+ RECT 245.055000 2253.600000 246.320000 2254.080000 ;
+ RECT 245.055000 2242.720000 246.320000 2243.200000 ;
+ RECT 245.055000 2237.280000 246.320000 2237.760000 ;
+ RECT 245.055000 2231.840000 246.320000 2232.320000 ;
+ RECT 245.055000 2226.400000 246.320000 2226.880000 ;
+ RECT 245.055000 2220.960000 246.320000 2221.440000 ;
+ RECT 245.055000 2215.520000 246.320000 2216.000000 ;
+ RECT 245.055000 2204.640000 246.320000 2205.120000 ;
+ RECT 245.055000 2210.080000 246.320000 2210.560000 ;
+ RECT 245.055000 2199.200000 246.320000 2199.680000 ;
+ RECT 245.055000 2193.760000 246.320000 2194.240000 ;
+ RECT 245.055000 2188.320000 246.320000 2188.800000 ;
+ RECT 245.055000 2182.880000 246.320000 2183.360000 ;
+ RECT 245.055000 2177.440000 246.320000 2177.920000 ;
+ RECT 245.055000 2172.000000 246.320000 2172.480000 ;
+ RECT 245.055000 2161.120000 246.320000 2161.600000 ;
+ RECT 245.055000 2166.560000 246.320000 2167.040000 ;
+ RECT 245.055000 2155.680000 246.320000 2156.160000 ;
+ RECT 245.055000 2248.160000 246.320000 2248.640000 ;
+ RECT 425.220000 2149.350000 426.320000 2345.920000 ;
+ RECT 380.220000 2149.350000 381.320000 2345.920000 ;
+ RECT 438.030000 2148.100000 439.030000 2348.360000 ;
+ RECT 335.220000 2149.350000 336.320000 2345.920000 ;
+ RECT 290.220000 2149.350000 291.320000 2345.920000 ;
+ RECT 245.220000 2149.350000 246.320000 2345.920000 ;
+ RECT 241.390000 2148.100000 242.390000 2348.360000 ;
+ LAYER met3 ;
+ RECT 425.220000 2340.640000 426.320000 2341.120000 ;
+ RECT 438.030000 2340.640000 439.030000 2341.120000 ;
+ RECT 438.030000 2329.760000 439.030000 2330.240000 ;
+ RECT 438.030000 2324.320000 439.030000 2324.800000 ;
+ RECT 438.030000 2335.200000 439.030000 2335.680000 ;
+ RECT 425.220000 2335.200000 426.320000 2335.680000 ;
+ RECT 425.220000 2329.760000 426.320000 2330.240000 ;
+ RECT 425.220000 2324.320000 426.320000 2324.800000 ;
+ RECT 425.220000 2313.440000 426.320000 2313.920000 ;
+ RECT 425.220000 2318.880000 426.320000 2319.360000 ;
+ RECT 438.030000 2313.440000 439.030000 2313.920000 ;
+ RECT 438.030000 2318.880000 439.030000 2319.360000 ;
+ RECT 425.220000 2302.560000 426.320000 2303.040000 ;
+ RECT 425.220000 2308.000000 426.320000 2308.480000 ;
+ RECT 438.030000 2302.560000 439.030000 2303.040000 ;
+ RECT 438.030000 2308.000000 439.030000 2308.480000 ;
+ RECT 380.220000 2324.320000 381.320000 2324.800000 ;
+ RECT 380.220000 2329.760000 381.320000 2330.240000 ;
+ RECT 380.220000 2335.200000 381.320000 2335.680000 ;
+ RECT 380.220000 2340.640000 381.320000 2341.120000 ;
+ RECT 380.220000 2308.000000 381.320000 2308.480000 ;
+ RECT 380.220000 2302.560000 381.320000 2303.040000 ;
+ RECT 380.220000 2313.440000 381.320000 2313.920000 ;
+ RECT 380.220000 2318.880000 381.320000 2319.360000 ;
+ RECT 438.030000 2291.680000 439.030000 2292.160000 ;
+ RECT 438.030000 2286.240000 439.030000 2286.720000 ;
+ RECT 438.030000 2297.120000 439.030000 2297.600000 ;
+ RECT 425.220000 2297.120000 426.320000 2297.600000 ;
+ RECT 425.220000 2291.680000 426.320000 2292.160000 ;
+ RECT 425.220000 2286.240000 426.320000 2286.720000 ;
+ RECT 425.220000 2275.360000 426.320000 2275.840000 ;
+ RECT 425.220000 2280.800000 426.320000 2281.280000 ;
+ RECT 438.030000 2275.360000 439.030000 2275.840000 ;
+ RECT 438.030000 2280.800000 439.030000 2281.280000 ;
+ RECT 438.030000 2264.480000 439.030000 2264.960000 ;
+ RECT 438.030000 2269.920000 439.030000 2270.400000 ;
+ RECT 425.220000 2269.920000 426.320000 2270.400000 ;
+ RECT 425.220000 2264.480000 426.320000 2264.960000 ;
+ RECT 425.220000 2253.600000 426.320000 2254.080000 ;
+ RECT 425.220000 2259.040000 426.320000 2259.520000 ;
+ RECT 438.030000 2253.600000 439.030000 2254.080000 ;
+ RECT 438.030000 2259.040000 439.030000 2259.520000 ;
+ RECT 380.220000 2275.360000 381.320000 2275.840000 ;
+ RECT 380.220000 2280.800000 381.320000 2281.280000 ;
+ RECT 380.220000 2286.240000 381.320000 2286.720000 ;
+ RECT 380.220000 2291.680000 381.320000 2292.160000 ;
+ RECT 380.220000 2297.120000 381.320000 2297.600000 ;
+ RECT 380.220000 2253.600000 381.320000 2254.080000 ;
+ RECT 380.220000 2259.040000 381.320000 2259.520000 ;
+ RECT 380.220000 2264.480000 381.320000 2264.960000 ;
+ RECT 380.220000 2269.920000 381.320000 2270.400000 ;
+ RECT 335.220000 2329.760000 336.320000 2330.240000 ;
+ RECT 335.220000 2324.320000 336.320000 2324.800000 ;
+ RECT 335.220000 2335.200000 336.320000 2335.680000 ;
+ RECT 335.220000 2340.640000 336.320000 2341.120000 ;
+ RECT 290.220000 2324.320000 291.320000 2324.800000 ;
+ RECT 290.220000 2329.760000 291.320000 2330.240000 ;
+ RECT 290.220000 2335.200000 291.320000 2335.680000 ;
+ RECT 290.220000 2340.640000 291.320000 2341.120000 ;
+ RECT 335.220000 2302.560000 336.320000 2303.040000 ;
+ RECT 335.220000 2308.000000 336.320000 2308.480000 ;
+ RECT 335.220000 2313.440000 336.320000 2313.920000 ;
+ RECT 335.220000 2318.880000 336.320000 2319.360000 ;
+ RECT 290.220000 2302.560000 291.320000 2303.040000 ;
+ RECT 290.220000 2308.000000 291.320000 2308.480000 ;
+ RECT 290.220000 2313.440000 291.320000 2313.920000 ;
+ RECT 290.220000 2318.880000 291.320000 2319.360000 ;
+ RECT 241.390000 2340.640000 242.390000 2341.120000 ;
+ RECT 245.055000 2340.640000 246.320000 2341.120000 ;
+ RECT 241.390000 2329.760000 242.390000 2330.240000 ;
+ RECT 245.055000 2329.760000 246.320000 2330.240000 ;
+ RECT 241.390000 2335.200000 242.390000 2335.680000 ;
+ RECT 245.055000 2335.200000 246.320000 2335.680000 ;
+ RECT 241.390000 2324.320000 242.390000 2324.800000 ;
+ RECT 245.055000 2324.320000 246.320000 2324.800000 ;
+ RECT 241.390000 2318.880000 242.390000 2319.360000 ;
+ RECT 245.055000 2318.880000 246.320000 2319.360000 ;
+ RECT 241.390000 2313.440000 242.390000 2313.920000 ;
+ RECT 245.055000 2313.440000 246.320000 2313.920000 ;
+ RECT 241.390000 2308.000000 242.390000 2308.480000 ;
+ RECT 245.055000 2308.000000 246.320000 2308.480000 ;
+ RECT 241.390000 2302.560000 242.390000 2303.040000 ;
+ RECT 245.055000 2302.560000 246.320000 2303.040000 ;
+ RECT 335.220000 2275.360000 336.320000 2275.840000 ;
+ RECT 335.220000 2280.800000 336.320000 2281.280000 ;
+ RECT 335.220000 2286.240000 336.320000 2286.720000 ;
+ RECT 335.220000 2291.680000 336.320000 2292.160000 ;
+ RECT 335.220000 2297.120000 336.320000 2297.600000 ;
+ RECT 290.220000 2275.360000 291.320000 2275.840000 ;
+ RECT 290.220000 2280.800000 291.320000 2281.280000 ;
+ RECT 290.220000 2286.240000 291.320000 2286.720000 ;
+ RECT 290.220000 2291.680000 291.320000 2292.160000 ;
+ RECT 290.220000 2297.120000 291.320000 2297.600000 ;
+ RECT 335.220000 2253.600000 336.320000 2254.080000 ;
+ RECT 335.220000 2259.040000 336.320000 2259.520000 ;
+ RECT 335.220000 2264.480000 336.320000 2264.960000 ;
+ RECT 335.220000 2269.920000 336.320000 2270.400000 ;
+ RECT 290.220000 2253.600000 291.320000 2254.080000 ;
+ RECT 290.220000 2259.040000 291.320000 2259.520000 ;
+ RECT 290.220000 2264.480000 291.320000 2264.960000 ;
+ RECT 290.220000 2269.920000 291.320000 2270.400000 ;
+ RECT 241.390000 2297.120000 242.390000 2297.600000 ;
+ RECT 245.055000 2297.120000 246.320000 2297.600000 ;
+ RECT 241.390000 2286.240000 242.390000 2286.720000 ;
+ RECT 245.055000 2286.240000 246.320000 2286.720000 ;
+ RECT 241.390000 2291.680000 242.390000 2292.160000 ;
+ RECT 245.055000 2291.680000 246.320000 2292.160000 ;
+ RECT 241.390000 2280.800000 242.390000 2281.280000 ;
+ RECT 245.055000 2280.800000 246.320000 2281.280000 ;
+ RECT 241.390000 2275.360000 242.390000 2275.840000 ;
+ RECT 245.055000 2275.360000 246.320000 2275.840000 ;
+ RECT 241.390000 2269.920000 242.390000 2270.400000 ;
+ RECT 245.055000 2269.920000 246.320000 2270.400000 ;
+ RECT 241.390000 2264.480000 242.390000 2264.960000 ;
+ RECT 245.055000 2264.480000 246.320000 2264.960000 ;
+ RECT 241.390000 2259.040000 242.390000 2259.520000 ;
+ RECT 245.055000 2259.040000 246.320000 2259.520000 ;
+ RECT 241.390000 2253.600000 242.390000 2254.080000 ;
+ RECT 245.055000 2253.600000 246.320000 2254.080000 ;
+ RECT 425.220000 2237.280000 426.320000 2237.760000 ;
+ RECT 425.220000 2242.720000 426.320000 2243.200000 ;
+ RECT 438.030000 2237.280000 439.030000 2237.760000 ;
+ RECT 438.030000 2242.720000 439.030000 2243.200000 ;
+ RECT 438.030000 2226.400000 439.030000 2226.880000 ;
+ RECT 438.030000 2231.840000 439.030000 2232.320000 ;
+ RECT 425.220000 2231.840000 426.320000 2232.320000 ;
+ RECT 425.220000 2226.400000 426.320000 2226.880000 ;
+ RECT 425.220000 2215.520000 426.320000 2216.000000 ;
+ RECT 425.220000 2220.960000 426.320000 2221.440000 ;
+ RECT 438.030000 2215.520000 439.030000 2216.000000 ;
+ RECT 438.030000 2220.960000 439.030000 2221.440000 ;
+ RECT 438.030000 2204.640000 439.030000 2205.120000 ;
+ RECT 438.030000 2199.200000 439.030000 2199.680000 ;
+ RECT 438.030000 2210.080000 439.030000 2210.560000 ;
+ RECT 425.220000 2210.080000 426.320000 2210.560000 ;
+ RECT 425.220000 2204.640000 426.320000 2205.120000 ;
+ RECT 425.220000 2199.200000 426.320000 2199.680000 ;
+ RECT 380.220000 2226.400000 381.320000 2226.880000 ;
+ RECT 380.220000 2231.840000 381.320000 2232.320000 ;
+ RECT 380.220000 2237.280000 381.320000 2237.760000 ;
+ RECT 380.220000 2242.720000 381.320000 2243.200000 ;
+ RECT 380.220000 2199.200000 381.320000 2199.680000 ;
+ RECT 380.220000 2204.640000 381.320000 2205.120000 ;
+ RECT 380.220000 2210.080000 381.320000 2210.560000 ;
+ RECT 380.220000 2215.520000 381.320000 2216.000000 ;
+ RECT 380.220000 2220.960000 381.320000 2221.440000 ;
+ RECT 425.220000 2188.320000 426.320000 2188.800000 ;
+ RECT 425.220000 2193.760000 426.320000 2194.240000 ;
+ RECT 438.030000 2188.320000 439.030000 2188.800000 ;
+ RECT 438.030000 2193.760000 439.030000 2194.240000 ;
+ RECT 425.220000 2177.440000 426.320000 2177.920000 ;
+ RECT 425.220000 2182.880000 426.320000 2183.360000 ;
+ RECT 438.030000 2177.440000 439.030000 2177.920000 ;
+ RECT 438.030000 2182.880000 439.030000 2183.360000 ;
+ RECT 438.030000 2166.560000 439.030000 2167.040000 ;
+ RECT 438.030000 2161.120000 439.030000 2161.600000 ;
+ RECT 438.030000 2172.000000 439.030000 2172.480000 ;
+ RECT 425.220000 2172.000000 426.320000 2172.480000 ;
+ RECT 425.220000 2166.560000 426.320000 2167.040000 ;
+ RECT 425.220000 2161.120000 426.320000 2161.600000 ;
+ RECT 425.220000 2155.680000 426.320000 2156.160000 ;
+ RECT 438.030000 2155.680000 439.030000 2156.160000 ;
+ RECT 380.220000 2177.440000 381.320000 2177.920000 ;
+ RECT 380.220000 2182.880000 381.320000 2183.360000 ;
+ RECT 380.220000 2188.320000 381.320000 2188.800000 ;
+ RECT 380.220000 2193.760000 381.320000 2194.240000 ;
+ RECT 380.220000 2155.680000 381.320000 2156.160000 ;
+ RECT 380.220000 2161.120000 381.320000 2161.600000 ;
+ RECT 380.220000 2166.560000 381.320000 2167.040000 ;
+ RECT 380.220000 2172.000000 381.320000 2172.480000 ;
+ RECT 335.220000 2226.400000 336.320000 2226.880000 ;
+ RECT 335.220000 2231.840000 336.320000 2232.320000 ;
+ RECT 335.220000 2237.280000 336.320000 2237.760000 ;
+ RECT 335.220000 2242.720000 336.320000 2243.200000 ;
+ RECT 290.220000 2226.400000 291.320000 2226.880000 ;
+ RECT 290.220000 2231.840000 291.320000 2232.320000 ;
+ RECT 290.220000 2237.280000 291.320000 2237.760000 ;
+ RECT 290.220000 2242.720000 291.320000 2243.200000 ;
+ RECT 335.220000 2199.200000 336.320000 2199.680000 ;
+ RECT 335.220000 2204.640000 336.320000 2205.120000 ;
+ RECT 335.220000 2210.080000 336.320000 2210.560000 ;
+ RECT 335.220000 2215.520000 336.320000 2216.000000 ;
+ RECT 335.220000 2220.960000 336.320000 2221.440000 ;
+ RECT 290.220000 2199.200000 291.320000 2199.680000 ;
+ RECT 290.220000 2204.640000 291.320000 2205.120000 ;
+ RECT 290.220000 2210.080000 291.320000 2210.560000 ;
+ RECT 290.220000 2215.520000 291.320000 2216.000000 ;
+ RECT 290.220000 2220.960000 291.320000 2221.440000 ;
+ RECT 241.390000 2242.720000 242.390000 2243.200000 ;
+ RECT 245.055000 2242.720000 246.320000 2243.200000 ;
+ RECT 241.390000 2237.280000 242.390000 2237.760000 ;
+ RECT 245.055000 2237.280000 246.320000 2237.760000 ;
+ RECT 241.390000 2231.840000 242.390000 2232.320000 ;
+ RECT 245.055000 2231.840000 246.320000 2232.320000 ;
+ RECT 241.390000 2226.400000 242.390000 2226.880000 ;
+ RECT 245.055000 2226.400000 246.320000 2226.880000 ;
+ RECT 241.390000 2220.960000 242.390000 2221.440000 ;
+ RECT 245.055000 2220.960000 246.320000 2221.440000 ;
+ RECT 241.390000 2215.520000 242.390000 2216.000000 ;
+ RECT 245.055000 2215.520000 246.320000 2216.000000 ;
+ RECT 241.390000 2204.640000 242.390000 2205.120000 ;
+ RECT 245.055000 2204.640000 246.320000 2205.120000 ;
+ RECT 241.390000 2210.080000 242.390000 2210.560000 ;
+ RECT 245.055000 2210.080000 246.320000 2210.560000 ;
+ RECT 241.390000 2199.200000 242.390000 2199.680000 ;
+ RECT 245.055000 2199.200000 246.320000 2199.680000 ;
+ RECT 335.220000 2177.440000 336.320000 2177.920000 ;
+ RECT 335.220000 2182.880000 336.320000 2183.360000 ;
+ RECT 335.220000 2188.320000 336.320000 2188.800000 ;
+ RECT 335.220000 2193.760000 336.320000 2194.240000 ;
+ RECT 290.220000 2177.440000 291.320000 2177.920000 ;
+ RECT 290.220000 2182.880000 291.320000 2183.360000 ;
+ RECT 290.220000 2188.320000 291.320000 2188.800000 ;
+ RECT 290.220000 2193.760000 291.320000 2194.240000 ;
+ RECT 335.220000 2155.680000 336.320000 2156.160000 ;
+ RECT 335.220000 2161.120000 336.320000 2161.600000 ;
+ RECT 335.220000 2166.560000 336.320000 2167.040000 ;
+ RECT 335.220000 2172.000000 336.320000 2172.480000 ;
+ RECT 290.220000 2155.680000 291.320000 2156.160000 ;
+ RECT 290.220000 2161.120000 291.320000 2161.600000 ;
+ RECT 290.220000 2166.560000 291.320000 2167.040000 ;
+ RECT 290.220000 2172.000000 291.320000 2172.480000 ;
+ RECT 241.390000 2193.760000 242.390000 2194.240000 ;
+ RECT 245.055000 2193.760000 246.320000 2194.240000 ;
+ RECT 241.390000 2188.320000 242.390000 2188.800000 ;
+ RECT 245.055000 2188.320000 246.320000 2188.800000 ;
+ RECT 241.390000 2182.880000 242.390000 2183.360000 ;
+ RECT 245.055000 2182.880000 246.320000 2183.360000 ;
+ RECT 241.390000 2177.440000 242.390000 2177.920000 ;
+ RECT 245.055000 2177.440000 246.320000 2177.920000 ;
+ RECT 241.390000 2172.000000 242.390000 2172.480000 ;
+ RECT 245.055000 2172.000000 246.320000 2172.480000 ;
+ RECT 241.390000 2161.120000 242.390000 2161.600000 ;
+ RECT 245.055000 2161.120000 246.320000 2161.600000 ;
+ RECT 241.390000 2166.560000 242.390000 2167.040000 ;
+ RECT 245.055000 2166.560000 246.320000 2167.040000 ;
+ RECT 241.390000 2155.680000 242.390000 2156.160000 ;
+ RECT 245.055000 2155.680000 246.320000 2156.160000 ;
+ RECT 380.220000 2248.160000 381.320000 2248.640000 ;
+ RECT 425.220000 2248.160000 426.320000 2248.640000 ;
+ RECT 438.030000 2248.160000 439.030000 2248.640000 ;
+ RECT 290.220000 2248.160000 291.320000 2248.640000 ;
+ RECT 335.220000 2248.160000 336.320000 2248.640000 ;
+ RECT 241.390000 2248.160000 242.390000 2248.640000 ;
+ RECT 245.055000 2248.160000 246.320000 2248.640000 ;
+ RECT 240.160000 2344.920000 440.260000 2345.920000 ;
+ RECT 240.160000 2149.350000 440.260000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 2148.100000 242.390000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 2347.360000 242.390000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 2148.100000 439.030000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 2347.360000 439.030000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2149.350000 241.160000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2149.350000 440.260000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2344.920000 241.160000 2345.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2344.920000 440.260000 2345.920000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 2140.380000 246.320000 2140.860000 ;
+ RECT 245.055000 2129.500000 246.320000 2129.980000 ;
+ RECT 245.055000 2134.940000 246.320000 2135.420000 ;
+ RECT 245.055000 2124.060000 246.320000 2124.540000 ;
+ RECT 245.055000 2118.620000 246.320000 2119.100000 ;
+ RECT 245.055000 2113.180000 246.320000 2113.660000 ;
+ RECT 245.055000 2107.740000 246.320000 2108.220000 ;
+ RECT 245.055000 2102.300000 246.320000 2102.780000 ;
+ RECT 245.055000 2096.860000 246.320000 2097.340000 ;
+ RECT 245.055000 2085.980000 246.320000 2086.460000 ;
+ RECT 245.055000 2091.420000 246.320000 2091.900000 ;
+ RECT 245.055000 2080.540000 246.320000 2081.020000 ;
+ RECT 245.055000 2075.100000 246.320000 2075.580000 ;
+ RECT 245.055000 2069.660000 246.320000 2070.140000 ;
+ RECT 245.055000 2064.220000 246.320000 2064.700000 ;
+ RECT 245.055000 2058.780000 246.320000 2059.260000 ;
+ RECT 245.055000 2053.340000 246.320000 2053.820000 ;
+ RECT 245.055000 2042.460000 246.320000 2042.940000 ;
+ RECT 245.055000 2037.020000 246.320000 2037.500000 ;
+ RECT 245.055000 2031.580000 246.320000 2032.060000 ;
+ RECT 245.055000 2026.140000 246.320000 2026.620000 ;
+ RECT 245.055000 2020.700000 246.320000 2021.180000 ;
+ RECT 245.055000 2015.260000 246.320000 2015.740000 ;
+ RECT 245.055000 2004.380000 246.320000 2004.860000 ;
+ RECT 245.055000 2009.820000 246.320000 2010.300000 ;
+ RECT 245.055000 1998.940000 246.320000 1999.420000 ;
+ RECT 245.055000 1993.500000 246.320000 1993.980000 ;
+ RECT 245.055000 1988.060000 246.320000 1988.540000 ;
+ RECT 245.055000 1982.620000 246.320000 1983.100000 ;
+ RECT 245.055000 1977.180000 246.320000 1977.660000 ;
+ RECT 245.055000 1971.740000 246.320000 1972.220000 ;
+ RECT 245.055000 1960.860000 246.320000 1961.340000 ;
+ RECT 245.055000 1966.300000 246.320000 1966.780000 ;
+ RECT 245.055000 1955.420000 246.320000 1955.900000 ;
+ RECT 245.055000 2047.900000 246.320000 2048.380000 ;
+ RECT 425.220000 1949.090000 426.320000 2145.660000 ;
+ RECT 380.220000 1949.090000 381.320000 2145.660000 ;
+ RECT 438.030000 1947.840000 439.030000 2148.100000 ;
+ RECT 335.220000 1949.090000 336.320000 2145.660000 ;
+ RECT 290.220000 1949.090000 291.320000 2145.660000 ;
+ RECT 245.220000 1949.090000 246.320000 2145.660000 ;
+ RECT 241.390000 1947.840000 242.390000 2148.100000 ;
+ LAYER met3 ;
+ RECT 425.220000 2140.380000 426.320000 2140.860000 ;
+ RECT 438.030000 2140.380000 439.030000 2140.860000 ;
+ RECT 438.030000 2129.500000 439.030000 2129.980000 ;
+ RECT 438.030000 2124.060000 439.030000 2124.540000 ;
+ RECT 438.030000 2134.940000 439.030000 2135.420000 ;
+ RECT 425.220000 2134.940000 426.320000 2135.420000 ;
+ RECT 425.220000 2129.500000 426.320000 2129.980000 ;
+ RECT 425.220000 2124.060000 426.320000 2124.540000 ;
+ RECT 425.220000 2113.180000 426.320000 2113.660000 ;
+ RECT 425.220000 2118.620000 426.320000 2119.100000 ;
+ RECT 438.030000 2113.180000 439.030000 2113.660000 ;
+ RECT 438.030000 2118.620000 439.030000 2119.100000 ;
+ RECT 425.220000 2102.300000 426.320000 2102.780000 ;
+ RECT 425.220000 2107.740000 426.320000 2108.220000 ;
+ RECT 438.030000 2102.300000 439.030000 2102.780000 ;
+ RECT 438.030000 2107.740000 439.030000 2108.220000 ;
+ RECT 380.220000 2124.060000 381.320000 2124.540000 ;
+ RECT 380.220000 2129.500000 381.320000 2129.980000 ;
+ RECT 380.220000 2134.940000 381.320000 2135.420000 ;
+ RECT 380.220000 2140.380000 381.320000 2140.860000 ;
+ RECT 380.220000 2107.740000 381.320000 2108.220000 ;
+ RECT 380.220000 2102.300000 381.320000 2102.780000 ;
+ RECT 380.220000 2113.180000 381.320000 2113.660000 ;
+ RECT 380.220000 2118.620000 381.320000 2119.100000 ;
+ RECT 438.030000 2091.420000 439.030000 2091.900000 ;
+ RECT 438.030000 2085.980000 439.030000 2086.460000 ;
+ RECT 438.030000 2096.860000 439.030000 2097.340000 ;
+ RECT 425.220000 2096.860000 426.320000 2097.340000 ;
+ RECT 425.220000 2091.420000 426.320000 2091.900000 ;
+ RECT 425.220000 2085.980000 426.320000 2086.460000 ;
+ RECT 425.220000 2075.100000 426.320000 2075.580000 ;
+ RECT 425.220000 2080.540000 426.320000 2081.020000 ;
+ RECT 438.030000 2075.100000 439.030000 2075.580000 ;
+ RECT 438.030000 2080.540000 439.030000 2081.020000 ;
+ RECT 438.030000 2064.220000 439.030000 2064.700000 ;
+ RECT 438.030000 2069.660000 439.030000 2070.140000 ;
+ RECT 425.220000 2069.660000 426.320000 2070.140000 ;
+ RECT 425.220000 2064.220000 426.320000 2064.700000 ;
+ RECT 425.220000 2053.340000 426.320000 2053.820000 ;
+ RECT 425.220000 2058.780000 426.320000 2059.260000 ;
+ RECT 438.030000 2053.340000 439.030000 2053.820000 ;
+ RECT 438.030000 2058.780000 439.030000 2059.260000 ;
+ RECT 380.220000 2075.100000 381.320000 2075.580000 ;
+ RECT 380.220000 2080.540000 381.320000 2081.020000 ;
+ RECT 380.220000 2085.980000 381.320000 2086.460000 ;
+ RECT 380.220000 2091.420000 381.320000 2091.900000 ;
+ RECT 380.220000 2096.860000 381.320000 2097.340000 ;
+ RECT 380.220000 2053.340000 381.320000 2053.820000 ;
+ RECT 380.220000 2058.780000 381.320000 2059.260000 ;
+ RECT 380.220000 2064.220000 381.320000 2064.700000 ;
+ RECT 380.220000 2069.660000 381.320000 2070.140000 ;
+ RECT 335.220000 2129.500000 336.320000 2129.980000 ;
+ RECT 335.220000 2124.060000 336.320000 2124.540000 ;
+ RECT 335.220000 2134.940000 336.320000 2135.420000 ;
+ RECT 335.220000 2140.380000 336.320000 2140.860000 ;
+ RECT 290.220000 2124.060000 291.320000 2124.540000 ;
+ RECT 290.220000 2129.500000 291.320000 2129.980000 ;
+ RECT 290.220000 2134.940000 291.320000 2135.420000 ;
+ RECT 290.220000 2140.380000 291.320000 2140.860000 ;
+ RECT 335.220000 2102.300000 336.320000 2102.780000 ;
+ RECT 335.220000 2107.740000 336.320000 2108.220000 ;
+ RECT 335.220000 2113.180000 336.320000 2113.660000 ;
+ RECT 335.220000 2118.620000 336.320000 2119.100000 ;
+ RECT 290.220000 2102.300000 291.320000 2102.780000 ;
+ RECT 290.220000 2107.740000 291.320000 2108.220000 ;
+ RECT 290.220000 2113.180000 291.320000 2113.660000 ;
+ RECT 290.220000 2118.620000 291.320000 2119.100000 ;
+ RECT 241.390000 2140.380000 242.390000 2140.860000 ;
+ RECT 245.055000 2140.380000 246.320000 2140.860000 ;
+ RECT 241.390000 2129.500000 242.390000 2129.980000 ;
+ RECT 245.055000 2129.500000 246.320000 2129.980000 ;
+ RECT 241.390000 2134.940000 242.390000 2135.420000 ;
+ RECT 245.055000 2134.940000 246.320000 2135.420000 ;
+ RECT 241.390000 2124.060000 242.390000 2124.540000 ;
+ RECT 245.055000 2124.060000 246.320000 2124.540000 ;
+ RECT 241.390000 2118.620000 242.390000 2119.100000 ;
+ RECT 245.055000 2118.620000 246.320000 2119.100000 ;
+ RECT 241.390000 2113.180000 242.390000 2113.660000 ;
+ RECT 245.055000 2113.180000 246.320000 2113.660000 ;
+ RECT 241.390000 2107.740000 242.390000 2108.220000 ;
+ RECT 245.055000 2107.740000 246.320000 2108.220000 ;
+ RECT 241.390000 2102.300000 242.390000 2102.780000 ;
+ RECT 245.055000 2102.300000 246.320000 2102.780000 ;
+ RECT 335.220000 2075.100000 336.320000 2075.580000 ;
+ RECT 335.220000 2080.540000 336.320000 2081.020000 ;
+ RECT 335.220000 2085.980000 336.320000 2086.460000 ;
+ RECT 335.220000 2091.420000 336.320000 2091.900000 ;
+ RECT 335.220000 2096.860000 336.320000 2097.340000 ;
+ RECT 290.220000 2075.100000 291.320000 2075.580000 ;
+ RECT 290.220000 2080.540000 291.320000 2081.020000 ;
+ RECT 290.220000 2085.980000 291.320000 2086.460000 ;
+ RECT 290.220000 2091.420000 291.320000 2091.900000 ;
+ RECT 290.220000 2096.860000 291.320000 2097.340000 ;
+ RECT 335.220000 2053.340000 336.320000 2053.820000 ;
+ RECT 335.220000 2058.780000 336.320000 2059.260000 ;
+ RECT 335.220000 2064.220000 336.320000 2064.700000 ;
+ RECT 335.220000 2069.660000 336.320000 2070.140000 ;
+ RECT 290.220000 2053.340000 291.320000 2053.820000 ;
+ RECT 290.220000 2058.780000 291.320000 2059.260000 ;
+ RECT 290.220000 2064.220000 291.320000 2064.700000 ;
+ RECT 290.220000 2069.660000 291.320000 2070.140000 ;
+ RECT 241.390000 2096.860000 242.390000 2097.340000 ;
+ RECT 245.055000 2096.860000 246.320000 2097.340000 ;
+ RECT 241.390000 2085.980000 242.390000 2086.460000 ;
+ RECT 245.055000 2085.980000 246.320000 2086.460000 ;
+ RECT 241.390000 2091.420000 242.390000 2091.900000 ;
+ RECT 245.055000 2091.420000 246.320000 2091.900000 ;
+ RECT 241.390000 2080.540000 242.390000 2081.020000 ;
+ RECT 245.055000 2080.540000 246.320000 2081.020000 ;
+ RECT 241.390000 2075.100000 242.390000 2075.580000 ;
+ RECT 245.055000 2075.100000 246.320000 2075.580000 ;
+ RECT 241.390000 2069.660000 242.390000 2070.140000 ;
+ RECT 245.055000 2069.660000 246.320000 2070.140000 ;
+ RECT 241.390000 2064.220000 242.390000 2064.700000 ;
+ RECT 245.055000 2064.220000 246.320000 2064.700000 ;
+ RECT 241.390000 2058.780000 242.390000 2059.260000 ;
+ RECT 245.055000 2058.780000 246.320000 2059.260000 ;
+ RECT 241.390000 2053.340000 242.390000 2053.820000 ;
+ RECT 245.055000 2053.340000 246.320000 2053.820000 ;
+ RECT 425.220000 2037.020000 426.320000 2037.500000 ;
+ RECT 425.220000 2042.460000 426.320000 2042.940000 ;
+ RECT 438.030000 2037.020000 439.030000 2037.500000 ;
+ RECT 438.030000 2042.460000 439.030000 2042.940000 ;
+ RECT 438.030000 2026.140000 439.030000 2026.620000 ;
+ RECT 438.030000 2031.580000 439.030000 2032.060000 ;
+ RECT 425.220000 2031.580000 426.320000 2032.060000 ;
+ RECT 425.220000 2026.140000 426.320000 2026.620000 ;
+ RECT 425.220000 2015.260000 426.320000 2015.740000 ;
+ RECT 425.220000 2020.700000 426.320000 2021.180000 ;
+ RECT 438.030000 2015.260000 439.030000 2015.740000 ;
+ RECT 438.030000 2020.700000 439.030000 2021.180000 ;
+ RECT 438.030000 2004.380000 439.030000 2004.860000 ;
+ RECT 438.030000 1998.940000 439.030000 1999.420000 ;
+ RECT 438.030000 2009.820000 439.030000 2010.300000 ;
+ RECT 425.220000 2009.820000 426.320000 2010.300000 ;
+ RECT 425.220000 2004.380000 426.320000 2004.860000 ;
+ RECT 425.220000 1998.940000 426.320000 1999.420000 ;
+ RECT 380.220000 2026.140000 381.320000 2026.620000 ;
+ RECT 380.220000 2031.580000 381.320000 2032.060000 ;
+ RECT 380.220000 2037.020000 381.320000 2037.500000 ;
+ RECT 380.220000 2042.460000 381.320000 2042.940000 ;
+ RECT 380.220000 1998.940000 381.320000 1999.420000 ;
+ RECT 380.220000 2004.380000 381.320000 2004.860000 ;
+ RECT 380.220000 2009.820000 381.320000 2010.300000 ;
+ RECT 380.220000 2015.260000 381.320000 2015.740000 ;
+ RECT 380.220000 2020.700000 381.320000 2021.180000 ;
+ RECT 425.220000 1988.060000 426.320000 1988.540000 ;
+ RECT 425.220000 1993.500000 426.320000 1993.980000 ;
+ RECT 438.030000 1988.060000 439.030000 1988.540000 ;
+ RECT 438.030000 1993.500000 439.030000 1993.980000 ;
+ RECT 425.220000 1977.180000 426.320000 1977.660000 ;
+ RECT 425.220000 1982.620000 426.320000 1983.100000 ;
+ RECT 438.030000 1977.180000 439.030000 1977.660000 ;
+ RECT 438.030000 1982.620000 439.030000 1983.100000 ;
+ RECT 438.030000 1966.300000 439.030000 1966.780000 ;
+ RECT 438.030000 1960.860000 439.030000 1961.340000 ;
+ RECT 438.030000 1971.740000 439.030000 1972.220000 ;
+ RECT 425.220000 1971.740000 426.320000 1972.220000 ;
+ RECT 425.220000 1966.300000 426.320000 1966.780000 ;
+ RECT 425.220000 1960.860000 426.320000 1961.340000 ;
+ RECT 425.220000 1955.420000 426.320000 1955.900000 ;
+ RECT 438.030000 1955.420000 439.030000 1955.900000 ;
+ RECT 380.220000 1977.180000 381.320000 1977.660000 ;
+ RECT 380.220000 1982.620000 381.320000 1983.100000 ;
+ RECT 380.220000 1988.060000 381.320000 1988.540000 ;
+ RECT 380.220000 1993.500000 381.320000 1993.980000 ;
+ RECT 380.220000 1955.420000 381.320000 1955.900000 ;
+ RECT 380.220000 1960.860000 381.320000 1961.340000 ;
+ RECT 380.220000 1966.300000 381.320000 1966.780000 ;
+ RECT 380.220000 1971.740000 381.320000 1972.220000 ;
+ RECT 335.220000 2026.140000 336.320000 2026.620000 ;
+ RECT 335.220000 2031.580000 336.320000 2032.060000 ;
+ RECT 335.220000 2037.020000 336.320000 2037.500000 ;
+ RECT 335.220000 2042.460000 336.320000 2042.940000 ;
+ RECT 290.220000 2026.140000 291.320000 2026.620000 ;
+ RECT 290.220000 2031.580000 291.320000 2032.060000 ;
+ RECT 290.220000 2037.020000 291.320000 2037.500000 ;
+ RECT 290.220000 2042.460000 291.320000 2042.940000 ;
+ RECT 335.220000 1998.940000 336.320000 1999.420000 ;
+ RECT 335.220000 2004.380000 336.320000 2004.860000 ;
+ RECT 335.220000 2009.820000 336.320000 2010.300000 ;
+ RECT 335.220000 2015.260000 336.320000 2015.740000 ;
+ RECT 335.220000 2020.700000 336.320000 2021.180000 ;
+ RECT 290.220000 1998.940000 291.320000 1999.420000 ;
+ RECT 290.220000 2004.380000 291.320000 2004.860000 ;
+ RECT 290.220000 2009.820000 291.320000 2010.300000 ;
+ RECT 290.220000 2015.260000 291.320000 2015.740000 ;
+ RECT 290.220000 2020.700000 291.320000 2021.180000 ;
+ RECT 241.390000 2042.460000 242.390000 2042.940000 ;
+ RECT 245.055000 2042.460000 246.320000 2042.940000 ;
+ RECT 241.390000 2037.020000 242.390000 2037.500000 ;
+ RECT 245.055000 2037.020000 246.320000 2037.500000 ;
+ RECT 241.390000 2031.580000 242.390000 2032.060000 ;
+ RECT 245.055000 2031.580000 246.320000 2032.060000 ;
+ RECT 241.390000 2026.140000 242.390000 2026.620000 ;
+ RECT 245.055000 2026.140000 246.320000 2026.620000 ;
+ RECT 241.390000 2020.700000 242.390000 2021.180000 ;
+ RECT 245.055000 2020.700000 246.320000 2021.180000 ;
+ RECT 241.390000 2015.260000 242.390000 2015.740000 ;
+ RECT 245.055000 2015.260000 246.320000 2015.740000 ;
+ RECT 241.390000 2004.380000 242.390000 2004.860000 ;
+ RECT 245.055000 2004.380000 246.320000 2004.860000 ;
+ RECT 241.390000 2009.820000 242.390000 2010.300000 ;
+ RECT 245.055000 2009.820000 246.320000 2010.300000 ;
+ RECT 241.390000 1998.940000 242.390000 1999.420000 ;
+ RECT 245.055000 1998.940000 246.320000 1999.420000 ;
+ RECT 335.220000 1977.180000 336.320000 1977.660000 ;
+ RECT 335.220000 1982.620000 336.320000 1983.100000 ;
+ RECT 335.220000 1988.060000 336.320000 1988.540000 ;
+ RECT 335.220000 1993.500000 336.320000 1993.980000 ;
+ RECT 290.220000 1977.180000 291.320000 1977.660000 ;
+ RECT 290.220000 1982.620000 291.320000 1983.100000 ;
+ RECT 290.220000 1988.060000 291.320000 1988.540000 ;
+ RECT 290.220000 1993.500000 291.320000 1993.980000 ;
+ RECT 335.220000 1955.420000 336.320000 1955.900000 ;
+ RECT 335.220000 1960.860000 336.320000 1961.340000 ;
+ RECT 335.220000 1966.300000 336.320000 1966.780000 ;
+ RECT 335.220000 1971.740000 336.320000 1972.220000 ;
+ RECT 290.220000 1955.420000 291.320000 1955.900000 ;
+ RECT 290.220000 1960.860000 291.320000 1961.340000 ;
+ RECT 290.220000 1966.300000 291.320000 1966.780000 ;
+ RECT 290.220000 1971.740000 291.320000 1972.220000 ;
+ RECT 241.390000 1993.500000 242.390000 1993.980000 ;
+ RECT 245.055000 1993.500000 246.320000 1993.980000 ;
+ RECT 241.390000 1988.060000 242.390000 1988.540000 ;
+ RECT 245.055000 1988.060000 246.320000 1988.540000 ;
+ RECT 241.390000 1982.620000 242.390000 1983.100000 ;
+ RECT 245.055000 1982.620000 246.320000 1983.100000 ;
+ RECT 241.390000 1977.180000 242.390000 1977.660000 ;
+ RECT 245.055000 1977.180000 246.320000 1977.660000 ;
+ RECT 241.390000 1971.740000 242.390000 1972.220000 ;
+ RECT 245.055000 1971.740000 246.320000 1972.220000 ;
+ RECT 241.390000 1960.860000 242.390000 1961.340000 ;
+ RECT 245.055000 1960.860000 246.320000 1961.340000 ;
+ RECT 241.390000 1966.300000 242.390000 1966.780000 ;
+ RECT 245.055000 1966.300000 246.320000 1966.780000 ;
+ RECT 241.390000 1955.420000 242.390000 1955.900000 ;
+ RECT 245.055000 1955.420000 246.320000 1955.900000 ;
+ RECT 380.220000 2047.900000 381.320000 2048.380000 ;
+ RECT 425.220000 2047.900000 426.320000 2048.380000 ;
+ RECT 438.030000 2047.900000 439.030000 2048.380000 ;
+ RECT 290.220000 2047.900000 291.320000 2048.380000 ;
+ RECT 335.220000 2047.900000 336.320000 2048.380000 ;
+ RECT 241.390000 2047.900000 242.390000 2048.380000 ;
+ RECT 245.055000 2047.900000 246.320000 2048.380000 ;
+ RECT 240.160000 2144.660000 440.260000 2145.660000 ;
+ RECT 240.160000 1949.090000 440.260000 1950.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 1947.840000 242.390000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 2147.100000 242.390000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 1947.840000 439.030000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 2147.100000 439.030000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1949.090000 241.160000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1949.090000 440.260000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2144.660000 241.160000 2145.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2144.660000 440.260000 2145.660000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 1940.120000 246.320000 1940.600000 ;
+ RECT 245.055000 1929.240000 246.320000 1929.720000 ;
+ RECT 245.055000 1934.680000 246.320000 1935.160000 ;
+ RECT 245.055000 1923.800000 246.320000 1924.280000 ;
+ RECT 245.055000 1918.360000 246.320000 1918.840000 ;
+ RECT 245.055000 1912.920000 246.320000 1913.400000 ;
+ RECT 245.055000 1907.480000 246.320000 1907.960000 ;
+ RECT 245.055000 1902.040000 246.320000 1902.520000 ;
+ RECT 245.055000 1896.600000 246.320000 1897.080000 ;
+ RECT 245.055000 1885.720000 246.320000 1886.200000 ;
+ RECT 245.055000 1891.160000 246.320000 1891.640000 ;
+ RECT 245.055000 1880.280000 246.320000 1880.760000 ;
+ RECT 245.055000 1874.840000 246.320000 1875.320000 ;
+ RECT 245.055000 1869.400000 246.320000 1869.880000 ;
+ RECT 245.055000 1863.960000 246.320000 1864.440000 ;
+ RECT 245.055000 1858.520000 246.320000 1859.000000 ;
+ RECT 245.055000 1853.080000 246.320000 1853.560000 ;
+ RECT 245.055000 1842.200000 246.320000 1842.680000 ;
+ RECT 245.055000 1836.760000 246.320000 1837.240000 ;
+ RECT 245.055000 1831.320000 246.320000 1831.800000 ;
+ RECT 245.055000 1825.880000 246.320000 1826.360000 ;
+ RECT 245.055000 1820.440000 246.320000 1820.920000 ;
+ RECT 245.055000 1815.000000 246.320000 1815.480000 ;
+ RECT 245.055000 1804.120000 246.320000 1804.600000 ;
+ RECT 245.055000 1809.560000 246.320000 1810.040000 ;
+ RECT 245.055000 1798.680000 246.320000 1799.160000 ;
+ RECT 245.055000 1793.240000 246.320000 1793.720000 ;
+ RECT 245.055000 1787.800000 246.320000 1788.280000 ;
+ RECT 245.055000 1782.360000 246.320000 1782.840000 ;
+ RECT 245.055000 1776.920000 246.320000 1777.400000 ;
+ RECT 245.055000 1771.480000 246.320000 1771.960000 ;
+ RECT 245.055000 1760.600000 246.320000 1761.080000 ;
+ RECT 245.055000 1766.040000 246.320000 1766.520000 ;
+ RECT 245.055000 1755.160000 246.320000 1755.640000 ;
+ RECT 245.055000 1847.640000 246.320000 1848.120000 ;
+ RECT 425.220000 1748.830000 426.320000 1945.400000 ;
+ RECT 380.220000 1748.830000 381.320000 1945.400000 ;
+ RECT 438.030000 1747.580000 439.030000 1947.840000 ;
+ RECT 335.220000 1748.830000 336.320000 1945.400000 ;
+ RECT 290.220000 1748.830000 291.320000 1945.400000 ;
+ RECT 245.220000 1748.830000 246.320000 1945.400000 ;
+ RECT 241.390000 1747.580000 242.390000 1947.840000 ;
+ LAYER met3 ;
+ RECT 425.220000 1940.120000 426.320000 1940.600000 ;
+ RECT 438.030000 1940.120000 439.030000 1940.600000 ;
+ RECT 438.030000 1929.240000 439.030000 1929.720000 ;
+ RECT 438.030000 1923.800000 439.030000 1924.280000 ;
+ RECT 438.030000 1934.680000 439.030000 1935.160000 ;
+ RECT 425.220000 1934.680000 426.320000 1935.160000 ;
+ RECT 425.220000 1929.240000 426.320000 1929.720000 ;
+ RECT 425.220000 1923.800000 426.320000 1924.280000 ;
+ RECT 425.220000 1912.920000 426.320000 1913.400000 ;
+ RECT 425.220000 1918.360000 426.320000 1918.840000 ;
+ RECT 438.030000 1912.920000 439.030000 1913.400000 ;
+ RECT 438.030000 1918.360000 439.030000 1918.840000 ;
+ RECT 425.220000 1902.040000 426.320000 1902.520000 ;
+ RECT 425.220000 1907.480000 426.320000 1907.960000 ;
+ RECT 438.030000 1902.040000 439.030000 1902.520000 ;
+ RECT 438.030000 1907.480000 439.030000 1907.960000 ;
+ RECT 380.220000 1923.800000 381.320000 1924.280000 ;
+ RECT 380.220000 1929.240000 381.320000 1929.720000 ;
+ RECT 380.220000 1934.680000 381.320000 1935.160000 ;
+ RECT 380.220000 1940.120000 381.320000 1940.600000 ;
+ RECT 380.220000 1907.480000 381.320000 1907.960000 ;
+ RECT 380.220000 1902.040000 381.320000 1902.520000 ;
+ RECT 380.220000 1912.920000 381.320000 1913.400000 ;
+ RECT 380.220000 1918.360000 381.320000 1918.840000 ;
+ RECT 438.030000 1891.160000 439.030000 1891.640000 ;
+ RECT 438.030000 1885.720000 439.030000 1886.200000 ;
+ RECT 438.030000 1896.600000 439.030000 1897.080000 ;
+ RECT 425.220000 1896.600000 426.320000 1897.080000 ;
+ RECT 425.220000 1891.160000 426.320000 1891.640000 ;
+ RECT 425.220000 1885.720000 426.320000 1886.200000 ;
+ RECT 425.220000 1874.840000 426.320000 1875.320000 ;
+ RECT 425.220000 1880.280000 426.320000 1880.760000 ;
+ RECT 438.030000 1874.840000 439.030000 1875.320000 ;
+ RECT 438.030000 1880.280000 439.030000 1880.760000 ;
+ RECT 438.030000 1863.960000 439.030000 1864.440000 ;
+ RECT 438.030000 1869.400000 439.030000 1869.880000 ;
+ RECT 425.220000 1869.400000 426.320000 1869.880000 ;
+ RECT 425.220000 1863.960000 426.320000 1864.440000 ;
+ RECT 425.220000 1853.080000 426.320000 1853.560000 ;
+ RECT 425.220000 1858.520000 426.320000 1859.000000 ;
+ RECT 438.030000 1853.080000 439.030000 1853.560000 ;
+ RECT 438.030000 1858.520000 439.030000 1859.000000 ;
+ RECT 380.220000 1874.840000 381.320000 1875.320000 ;
+ RECT 380.220000 1880.280000 381.320000 1880.760000 ;
+ RECT 380.220000 1885.720000 381.320000 1886.200000 ;
+ RECT 380.220000 1891.160000 381.320000 1891.640000 ;
+ RECT 380.220000 1896.600000 381.320000 1897.080000 ;
+ RECT 380.220000 1853.080000 381.320000 1853.560000 ;
+ RECT 380.220000 1858.520000 381.320000 1859.000000 ;
+ RECT 380.220000 1863.960000 381.320000 1864.440000 ;
+ RECT 380.220000 1869.400000 381.320000 1869.880000 ;
+ RECT 335.220000 1929.240000 336.320000 1929.720000 ;
+ RECT 335.220000 1923.800000 336.320000 1924.280000 ;
+ RECT 335.220000 1934.680000 336.320000 1935.160000 ;
+ RECT 335.220000 1940.120000 336.320000 1940.600000 ;
+ RECT 290.220000 1923.800000 291.320000 1924.280000 ;
+ RECT 290.220000 1929.240000 291.320000 1929.720000 ;
+ RECT 290.220000 1934.680000 291.320000 1935.160000 ;
+ RECT 290.220000 1940.120000 291.320000 1940.600000 ;
+ RECT 335.220000 1902.040000 336.320000 1902.520000 ;
+ RECT 335.220000 1907.480000 336.320000 1907.960000 ;
+ RECT 335.220000 1912.920000 336.320000 1913.400000 ;
+ RECT 335.220000 1918.360000 336.320000 1918.840000 ;
+ RECT 290.220000 1902.040000 291.320000 1902.520000 ;
+ RECT 290.220000 1907.480000 291.320000 1907.960000 ;
+ RECT 290.220000 1912.920000 291.320000 1913.400000 ;
+ RECT 290.220000 1918.360000 291.320000 1918.840000 ;
+ RECT 241.390000 1940.120000 242.390000 1940.600000 ;
+ RECT 245.055000 1940.120000 246.320000 1940.600000 ;
+ RECT 241.390000 1929.240000 242.390000 1929.720000 ;
+ RECT 245.055000 1929.240000 246.320000 1929.720000 ;
+ RECT 241.390000 1934.680000 242.390000 1935.160000 ;
+ RECT 245.055000 1934.680000 246.320000 1935.160000 ;
+ RECT 241.390000 1923.800000 242.390000 1924.280000 ;
+ RECT 245.055000 1923.800000 246.320000 1924.280000 ;
+ RECT 241.390000 1918.360000 242.390000 1918.840000 ;
+ RECT 245.055000 1918.360000 246.320000 1918.840000 ;
+ RECT 241.390000 1912.920000 242.390000 1913.400000 ;
+ RECT 245.055000 1912.920000 246.320000 1913.400000 ;
+ RECT 241.390000 1907.480000 242.390000 1907.960000 ;
+ RECT 245.055000 1907.480000 246.320000 1907.960000 ;
+ RECT 241.390000 1902.040000 242.390000 1902.520000 ;
+ RECT 245.055000 1902.040000 246.320000 1902.520000 ;
+ RECT 335.220000 1874.840000 336.320000 1875.320000 ;
+ RECT 335.220000 1880.280000 336.320000 1880.760000 ;
+ RECT 335.220000 1885.720000 336.320000 1886.200000 ;
+ RECT 335.220000 1891.160000 336.320000 1891.640000 ;
+ RECT 335.220000 1896.600000 336.320000 1897.080000 ;
+ RECT 290.220000 1874.840000 291.320000 1875.320000 ;
+ RECT 290.220000 1880.280000 291.320000 1880.760000 ;
+ RECT 290.220000 1885.720000 291.320000 1886.200000 ;
+ RECT 290.220000 1891.160000 291.320000 1891.640000 ;
+ RECT 290.220000 1896.600000 291.320000 1897.080000 ;
+ RECT 335.220000 1853.080000 336.320000 1853.560000 ;
+ RECT 335.220000 1858.520000 336.320000 1859.000000 ;
+ RECT 335.220000 1863.960000 336.320000 1864.440000 ;
+ RECT 335.220000 1869.400000 336.320000 1869.880000 ;
+ RECT 290.220000 1853.080000 291.320000 1853.560000 ;
+ RECT 290.220000 1858.520000 291.320000 1859.000000 ;
+ RECT 290.220000 1863.960000 291.320000 1864.440000 ;
+ RECT 290.220000 1869.400000 291.320000 1869.880000 ;
+ RECT 241.390000 1896.600000 242.390000 1897.080000 ;
+ RECT 245.055000 1896.600000 246.320000 1897.080000 ;
+ RECT 241.390000 1885.720000 242.390000 1886.200000 ;
+ RECT 245.055000 1885.720000 246.320000 1886.200000 ;
+ RECT 241.390000 1891.160000 242.390000 1891.640000 ;
+ RECT 245.055000 1891.160000 246.320000 1891.640000 ;
+ RECT 241.390000 1880.280000 242.390000 1880.760000 ;
+ RECT 245.055000 1880.280000 246.320000 1880.760000 ;
+ RECT 241.390000 1874.840000 242.390000 1875.320000 ;
+ RECT 245.055000 1874.840000 246.320000 1875.320000 ;
+ RECT 241.390000 1869.400000 242.390000 1869.880000 ;
+ RECT 245.055000 1869.400000 246.320000 1869.880000 ;
+ RECT 241.390000 1863.960000 242.390000 1864.440000 ;
+ RECT 245.055000 1863.960000 246.320000 1864.440000 ;
+ RECT 241.390000 1858.520000 242.390000 1859.000000 ;
+ RECT 245.055000 1858.520000 246.320000 1859.000000 ;
+ RECT 241.390000 1853.080000 242.390000 1853.560000 ;
+ RECT 245.055000 1853.080000 246.320000 1853.560000 ;
+ RECT 425.220000 1836.760000 426.320000 1837.240000 ;
+ RECT 425.220000 1842.200000 426.320000 1842.680000 ;
+ RECT 438.030000 1836.760000 439.030000 1837.240000 ;
+ RECT 438.030000 1842.200000 439.030000 1842.680000 ;
+ RECT 438.030000 1825.880000 439.030000 1826.360000 ;
+ RECT 438.030000 1831.320000 439.030000 1831.800000 ;
+ RECT 425.220000 1831.320000 426.320000 1831.800000 ;
+ RECT 425.220000 1825.880000 426.320000 1826.360000 ;
+ RECT 425.220000 1815.000000 426.320000 1815.480000 ;
+ RECT 425.220000 1820.440000 426.320000 1820.920000 ;
+ RECT 438.030000 1815.000000 439.030000 1815.480000 ;
+ RECT 438.030000 1820.440000 439.030000 1820.920000 ;
+ RECT 438.030000 1804.120000 439.030000 1804.600000 ;
+ RECT 438.030000 1798.680000 439.030000 1799.160000 ;
+ RECT 438.030000 1809.560000 439.030000 1810.040000 ;
+ RECT 425.220000 1809.560000 426.320000 1810.040000 ;
+ RECT 425.220000 1804.120000 426.320000 1804.600000 ;
+ RECT 425.220000 1798.680000 426.320000 1799.160000 ;
+ RECT 380.220000 1825.880000 381.320000 1826.360000 ;
+ RECT 380.220000 1831.320000 381.320000 1831.800000 ;
+ RECT 380.220000 1836.760000 381.320000 1837.240000 ;
+ RECT 380.220000 1842.200000 381.320000 1842.680000 ;
+ RECT 380.220000 1798.680000 381.320000 1799.160000 ;
+ RECT 380.220000 1804.120000 381.320000 1804.600000 ;
+ RECT 380.220000 1809.560000 381.320000 1810.040000 ;
+ RECT 380.220000 1815.000000 381.320000 1815.480000 ;
+ RECT 380.220000 1820.440000 381.320000 1820.920000 ;
+ RECT 425.220000 1787.800000 426.320000 1788.280000 ;
+ RECT 425.220000 1793.240000 426.320000 1793.720000 ;
+ RECT 438.030000 1787.800000 439.030000 1788.280000 ;
+ RECT 438.030000 1793.240000 439.030000 1793.720000 ;
+ RECT 425.220000 1776.920000 426.320000 1777.400000 ;
+ RECT 425.220000 1782.360000 426.320000 1782.840000 ;
+ RECT 438.030000 1776.920000 439.030000 1777.400000 ;
+ RECT 438.030000 1782.360000 439.030000 1782.840000 ;
+ RECT 438.030000 1766.040000 439.030000 1766.520000 ;
+ RECT 438.030000 1760.600000 439.030000 1761.080000 ;
+ RECT 438.030000 1771.480000 439.030000 1771.960000 ;
+ RECT 425.220000 1771.480000 426.320000 1771.960000 ;
+ RECT 425.220000 1766.040000 426.320000 1766.520000 ;
+ RECT 425.220000 1760.600000 426.320000 1761.080000 ;
+ RECT 425.220000 1755.160000 426.320000 1755.640000 ;
+ RECT 438.030000 1755.160000 439.030000 1755.640000 ;
+ RECT 380.220000 1776.920000 381.320000 1777.400000 ;
+ RECT 380.220000 1782.360000 381.320000 1782.840000 ;
+ RECT 380.220000 1787.800000 381.320000 1788.280000 ;
+ RECT 380.220000 1793.240000 381.320000 1793.720000 ;
+ RECT 380.220000 1755.160000 381.320000 1755.640000 ;
+ RECT 380.220000 1760.600000 381.320000 1761.080000 ;
+ RECT 380.220000 1766.040000 381.320000 1766.520000 ;
+ RECT 380.220000 1771.480000 381.320000 1771.960000 ;
+ RECT 335.220000 1825.880000 336.320000 1826.360000 ;
+ RECT 335.220000 1831.320000 336.320000 1831.800000 ;
+ RECT 335.220000 1836.760000 336.320000 1837.240000 ;
+ RECT 335.220000 1842.200000 336.320000 1842.680000 ;
+ RECT 290.220000 1825.880000 291.320000 1826.360000 ;
+ RECT 290.220000 1831.320000 291.320000 1831.800000 ;
+ RECT 290.220000 1836.760000 291.320000 1837.240000 ;
+ RECT 290.220000 1842.200000 291.320000 1842.680000 ;
+ RECT 335.220000 1798.680000 336.320000 1799.160000 ;
+ RECT 335.220000 1804.120000 336.320000 1804.600000 ;
+ RECT 335.220000 1809.560000 336.320000 1810.040000 ;
+ RECT 335.220000 1815.000000 336.320000 1815.480000 ;
+ RECT 335.220000 1820.440000 336.320000 1820.920000 ;
+ RECT 290.220000 1798.680000 291.320000 1799.160000 ;
+ RECT 290.220000 1804.120000 291.320000 1804.600000 ;
+ RECT 290.220000 1809.560000 291.320000 1810.040000 ;
+ RECT 290.220000 1815.000000 291.320000 1815.480000 ;
+ RECT 290.220000 1820.440000 291.320000 1820.920000 ;
+ RECT 241.390000 1842.200000 242.390000 1842.680000 ;
+ RECT 245.055000 1842.200000 246.320000 1842.680000 ;
+ RECT 241.390000 1836.760000 242.390000 1837.240000 ;
+ RECT 245.055000 1836.760000 246.320000 1837.240000 ;
+ RECT 241.390000 1831.320000 242.390000 1831.800000 ;
+ RECT 245.055000 1831.320000 246.320000 1831.800000 ;
+ RECT 241.390000 1825.880000 242.390000 1826.360000 ;
+ RECT 245.055000 1825.880000 246.320000 1826.360000 ;
+ RECT 241.390000 1820.440000 242.390000 1820.920000 ;
+ RECT 245.055000 1820.440000 246.320000 1820.920000 ;
+ RECT 241.390000 1815.000000 242.390000 1815.480000 ;
+ RECT 245.055000 1815.000000 246.320000 1815.480000 ;
+ RECT 241.390000 1804.120000 242.390000 1804.600000 ;
+ RECT 245.055000 1804.120000 246.320000 1804.600000 ;
+ RECT 241.390000 1809.560000 242.390000 1810.040000 ;
+ RECT 245.055000 1809.560000 246.320000 1810.040000 ;
+ RECT 241.390000 1798.680000 242.390000 1799.160000 ;
+ RECT 245.055000 1798.680000 246.320000 1799.160000 ;
+ RECT 335.220000 1776.920000 336.320000 1777.400000 ;
+ RECT 335.220000 1782.360000 336.320000 1782.840000 ;
+ RECT 335.220000 1787.800000 336.320000 1788.280000 ;
+ RECT 335.220000 1793.240000 336.320000 1793.720000 ;
+ RECT 290.220000 1776.920000 291.320000 1777.400000 ;
+ RECT 290.220000 1782.360000 291.320000 1782.840000 ;
+ RECT 290.220000 1787.800000 291.320000 1788.280000 ;
+ RECT 290.220000 1793.240000 291.320000 1793.720000 ;
+ RECT 335.220000 1755.160000 336.320000 1755.640000 ;
+ RECT 335.220000 1760.600000 336.320000 1761.080000 ;
+ RECT 335.220000 1766.040000 336.320000 1766.520000 ;
+ RECT 335.220000 1771.480000 336.320000 1771.960000 ;
+ RECT 290.220000 1755.160000 291.320000 1755.640000 ;
+ RECT 290.220000 1760.600000 291.320000 1761.080000 ;
+ RECT 290.220000 1766.040000 291.320000 1766.520000 ;
+ RECT 290.220000 1771.480000 291.320000 1771.960000 ;
+ RECT 241.390000 1793.240000 242.390000 1793.720000 ;
+ RECT 245.055000 1793.240000 246.320000 1793.720000 ;
+ RECT 241.390000 1787.800000 242.390000 1788.280000 ;
+ RECT 245.055000 1787.800000 246.320000 1788.280000 ;
+ RECT 241.390000 1782.360000 242.390000 1782.840000 ;
+ RECT 245.055000 1782.360000 246.320000 1782.840000 ;
+ RECT 241.390000 1776.920000 242.390000 1777.400000 ;
+ RECT 245.055000 1776.920000 246.320000 1777.400000 ;
+ RECT 241.390000 1771.480000 242.390000 1771.960000 ;
+ RECT 245.055000 1771.480000 246.320000 1771.960000 ;
+ RECT 241.390000 1760.600000 242.390000 1761.080000 ;
+ RECT 245.055000 1760.600000 246.320000 1761.080000 ;
+ RECT 241.390000 1766.040000 242.390000 1766.520000 ;
+ RECT 245.055000 1766.040000 246.320000 1766.520000 ;
+ RECT 241.390000 1755.160000 242.390000 1755.640000 ;
+ RECT 245.055000 1755.160000 246.320000 1755.640000 ;
+ RECT 380.220000 1847.640000 381.320000 1848.120000 ;
+ RECT 425.220000 1847.640000 426.320000 1848.120000 ;
+ RECT 438.030000 1847.640000 439.030000 1848.120000 ;
+ RECT 290.220000 1847.640000 291.320000 1848.120000 ;
+ RECT 335.220000 1847.640000 336.320000 1848.120000 ;
+ RECT 241.390000 1847.640000 242.390000 1848.120000 ;
+ RECT 245.055000 1847.640000 246.320000 1848.120000 ;
+ RECT 240.160000 1944.400000 440.260000 1945.400000 ;
+ RECT 240.160000 1748.830000 440.260000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 1747.580000 242.390000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 1946.840000 242.390000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 1747.580000 439.030000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 1946.840000 439.030000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1748.830000 241.160000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1748.830000 440.260000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1944.400000 241.160000 1945.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1944.400000 440.260000 1945.400000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 245.055000 1739.860000 246.320000 1740.340000 ;
+ RECT 245.055000 1728.980000 246.320000 1729.460000 ;
+ RECT 245.055000 1734.420000 246.320000 1734.900000 ;
+ RECT 245.055000 1723.540000 246.320000 1724.020000 ;
+ RECT 245.055000 1718.100000 246.320000 1718.580000 ;
+ RECT 245.055000 1712.660000 246.320000 1713.140000 ;
+ RECT 245.055000 1707.220000 246.320000 1707.700000 ;
+ RECT 245.055000 1701.780000 246.320000 1702.260000 ;
+ RECT 245.055000 1696.340000 246.320000 1696.820000 ;
+ RECT 245.055000 1685.460000 246.320000 1685.940000 ;
+ RECT 245.055000 1690.900000 246.320000 1691.380000 ;
+ RECT 245.055000 1680.020000 246.320000 1680.500000 ;
+ RECT 245.055000 1674.580000 246.320000 1675.060000 ;
+ RECT 245.055000 1669.140000 246.320000 1669.620000 ;
+ RECT 245.055000 1663.700000 246.320000 1664.180000 ;
+ RECT 245.055000 1658.260000 246.320000 1658.740000 ;
+ RECT 245.055000 1652.820000 246.320000 1653.300000 ;
+ RECT 245.055000 1641.940000 246.320000 1642.420000 ;
+ RECT 245.055000 1636.500000 246.320000 1636.980000 ;
+ RECT 245.055000 1631.060000 246.320000 1631.540000 ;
+ RECT 245.055000 1625.620000 246.320000 1626.100000 ;
+ RECT 245.055000 1620.180000 246.320000 1620.660000 ;
+ RECT 245.055000 1614.740000 246.320000 1615.220000 ;
+ RECT 245.055000 1603.860000 246.320000 1604.340000 ;
+ RECT 245.055000 1609.300000 246.320000 1609.780000 ;
+ RECT 245.055000 1598.420000 246.320000 1598.900000 ;
+ RECT 245.055000 1592.980000 246.320000 1593.460000 ;
+ RECT 245.055000 1587.540000 246.320000 1588.020000 ;
+ RECT 245.055000 1582.100000 246.320000 1582.580000 ;
+ RECT 245.055000 1576.660000 246.320000 1577.140000 ;
+ RECT 245.055000 1571.220000 246.320000 1571.700000 ;
+ RECT 245.055000 1560.340000 246.320000 1560.820000 ;
+ RECT 245.055000 1565.780000 246.320000 1566.260000 ;
+ RECT 245.055000 1554.900000 246.320000 1555.380000 ;
+ RECT 245.055000 1647.380000 246.320000 1647.860000 ;
+ RECT 425.220000 1548.570000 426.320000 1745.140000 ;
+ RECT 380.220000 1548.570000 381.320000 1745.140000 ;
+ RECT 438.030000 1547.320000 439.030000 1747.580000 ;
+ RECT 335.220000 1548.570000 336.320000 1745.140000 ;
+ RECT 290.220000 1548.570000 291.320000 1745.140000 ;
+ RECT 245.220000 1548.570000 246.320000 1745.140000 ;
+ RECT 241.390000 1547.320000 242.390000 1747.580000 ;
+ LAYER met3 ;
+ RECT 425.220000 1739.860000 426.320000 1740.340000 ;
+ RECT 438.030000 1739.860000 439.030000 1740.340000 ;
+ RECT 438.030000 1728.980000 439.030000 1729.460000 ;
+ RECT 438.030000 1723.540000 439.030000 1724.020000 ;
+ RECT 438.030000 1734.420000 439.030000 1734.900000 ;
+ RECT 425.220000 1734.420000 426.320000 1734.900000 ;
+ RECT 425.220000 1728.980000 426.320000 1729.460000 ;
+ RECT 425.220000 1723.540000 426.320000 1724.020000 ;
+ RECT 425.220000 1712.660000 426.320000 1713.140000 ;
+ RECT 425.220000 1718.100000 426.320000 1718.580000 ;
+ RECT 438.030000 1712.660000 439.030000 1713.140000 ;
+ RECT 438.030000 1718.100000 439.030000 1718.580000 ;
+ RECT 425.220000 1701.780000 426.320000 1702.260000 ;
+ RECT 425.220000 1707.220000 426.320000 1707.700000 ;
+ RECT 438.030000 1701.780000 439.030000 1702.260000 ;
+ RECT 438.030000 1707.220000 439.030000 1707.700000 ;
+ RECT 380.220000 1723.540000 381.320000 1724.020000 ;
+ RECT 380.220000 1728.980000 381.320000 1729.460000 ;
+ RECT 380.220000 1734.420000 381.320000 1734.900000 ;
+ RECT 380.220000 1739.860000 381.320000 1740.340000 ;
+ RECT 380.220000 1707.220000 381.320000 1707.700000 ;
+ RECT 380.220000 1701.780000 381.320000 1702.260000 ;
+ RECT 380.220000 1712.660000 381.320000 1713.140000 ;
+ RECT 380.220000 1718.100000 381.320000 1718.580000 ;
+ RECT 438.030000 1690.900000 439.030000 1691.380000 ;
+ RECT 438.030000 1685.460000 439.030000 1685.940000 ;
+ RECT 438.030000 1696.340000 439.030000 1696.820000 ;
+ RECT 425.220000 1696.340000 426.320000 1696.820000 ;
+ RECT 425.220000 1690.900000 426.320000 1691.380000 ;
+ RECT 425.220000 1685.460000 426.320000 1685.940000 ;
+ RECT 425.220000 1674.580000 426.320000 1675.060000 ;
+ RECT 425.220000 1680.020000 426.320000 1680.500000 ;
+ RECT 438.030000 1674.580000 439.030000 1675.060000 ;
+ RECT 438.030000 1680.020000 439.030000 1680.500000 ;
+ RECT 438.030000 1663.700000 439.030000 1664.180000 ;
+ RECT 438.030000 1669.140000 439.030000 1669.620000 ;
+ RECT 425.220000 1669.140000 426.320000 1669.620000 ;
+ RECT 425.220000 1663.700000 426.320000 1664.180000 ;
+ RECT 425.220000 1652.820000 426.320000 1653.300000 ;
+ RECT 425.220000 1658.260000 426.320000 1658.740000 ;
+ RECT 438.030000 1652.820000 439.030000 1653.300000 ;
+ RECT 438.030000 1658.260000 439.030000 1658.740000 ;
+ RECT 380.220000 1674.580000 381.320000 1675.060000 ;
+ RECT 380.220000 1680.020000 381.320000 1680.500000 ;
+ RECT 380.220000 1685.460000 381.320000 1685.940000 ;
+ RECT 380.220000 1690.900000 381.320000 1691.380000 ;
+ RECT 380.220000 1696.340000 381.320000 1696.820000 ;
+ RECT 380.220000 1652.820000 381.320000 1653.300000 ;
+ RECT 380.220000 1658.260000 381.320000 1658.740000 ;
+ RECT 380.220000 1663.700000 381.320000 1664.180000 ;
+ RECT 380.220000 1669.140000 381.320000 1669.620000 ;
+ RECT 335.220000 1728.980000 336.320000 1729.460000 ;
+ RECT 335.220000 1723.540000 336.320000 1724.020000 ;
+ RECT 335.220000 1734.420000 336.320000 1734.900000 ;
+ RECT 335.220000 1739.860000 336.320000 1740.340000 ;
+ RECT 290.220000 1723.540000 291.320000 1724.020000 ;
+ RECT 290.220000 1728.980000 291.320000 1729.460000 ;
+ RECT 290.220000 1734.420000 291.320000 1734.900000 ;
+ RECT 290.220000 1739.860000 291.320000 1740.340000 ;
+ RECT 335.220000 1701.780000 336.320000 1702.260000 ;
+ RECT 335.220000 1707.220000 336.320000 1707.700000 ;
+ RECT 335.220000 1712.660000 336.320000 1713.140000 ;
+ RECT 335.220000 1718.100000 336.320000 1718.580000 ;
+ RECT 290.220000 1701.780000 291.320000 1702.260000 ;
+ RECT 290.220000 1707.220000 291.320000 1707.700000 ;
+ RECT 290.220000 1712.660000 291.320000 1713.140000 ;
+ RECT 290.220000 1718.100000 291.320000 1718.580000 ;
+ RECT 241.390000 1739.860000 242.390000 1740.340000 ;
+ RECT 245.055000 1739.860000 246.320000 1740.340000 ;
+ RECT 241.390000 1728.980000 242.390000 1729.460000 ;
+ RECT 245.055000 1728.980000 246.320000 1729.460000 ;
+ RECT 241.390000 1734.420000 242.390000 1734.900000 ;
+ RECT 245.055000 1734.420000 246.320000 1734.900000 ;
+ RECT 241.390000 1723.540000 242.390000 1724.020000 ;
+ RECT 245.055000 1723.540000 246.320000 1724.020000 ;
+ RECT 241.390000 1718.100000 242.390000 1718.580000 ;
+ RECT 245.055000 1718.100000 246.320000 1718.580000 ;
+ RECT 241.390000 1712.660000 242.390000 1713.140000 ;
+ RECT 245.055000 1712.660000 246.320000 1713.140000 ;
+ RECT 241.390000 1707.220000 242.390000 1707.700000 ;
+ RECT 245.055000 1707.220000 246.320000 1707.700000 ;
+ RECT 241.390000 1701.780000 242.390000 1702.260000 ;
+ RECT 245.055000 1701.780000 246.320000 1702.260000 ;
+ RECT 335.220000 1674.580000 336.320000 1675.060000 ;
+ RECT 335.220000 1680.020000 336.320000 1680.500000 ;
+ RECT 335.220000 1685.460000 336.320000 1685.940000 ;
+ RECT 335.220000 1690.900000 336.320000 1691.380000 ;
+ RECT 335.220000 1696.340000 336.320000 1696.820000 ;
+ RECT 290.220000 1674.580000 291.320000 1675.060000 ;
+ RECT 290.220000 1680.020000 291.320000 1680.500000 ;
+ RECT 290.220000 1685.460000 291.320000 1685.940000 ;
+ RECT 290.220000 1690.900000 291.320000 1691.380000 ;
+ RECT 290.220000 1696.340000 291.320000 1696.820000 ;
+ RECT 335.220000 1652.820000 336.320000 1653.300000 ;
+ RECT 335.220000 1658.260000 336.320000 1658.740000 ;
+ RECT 335.220000 1663.700000 336.320000 1664.180000 ;
+ RECT 335.220000 1669.140000 336.320000 1669.620000 ;
+ RECT 290.220000 1652.820000 291.320000 1653.300000 ;
+ RECT 290.220000 1658.260000 291.320000 1658.740000 ;
+ RECT 290.220000 1663.700000 291.320000 1664.180000 ;
+ RECT 290.220000 1669.140000 291.320000 1669.620000 ;
+ RECT 241.390000 1696.340000 242.390000 1696.820000 ;
+ RECT 245.055000 1696.340000 246.320000 1696.820000 ;
+ RECT 241.390000 1685.460000 242.390000 1685.940000 ;
+ RECT 245.055000 1685.460000 246.320000 1685.940000 ;
+ RECT 241.390000 1690.900000 242.390000 1691.380000 ;
+ RECT 245.055000 1690.900000 246.320000 1691.380000 ;
+ RECT 241.390000 1680.020000 242.390000 1680.500000 ;
+ RECT 245.055000 1680.020000 246.320000 1680.500000 ;
+ RECT 241.390000 1674.580000 242.390000 1675.060000 ;
+ RECT 245.055000 1674.580000 246.320000 1675.060000 ;
+ RECT 241.390000 1669.140000 242.390000 1669.620000 ;
+ RECT 245.055000 1669.140000 246.320000 1669.620000 ;
+ RECT 241.390000 1663.700000 242.390000 1664.180000 ;
+ RECT 245.055000 1663.700000 246.320000 1664.180000 ;
+ RECT 241.390000 1658.260000 242.390000 1658.740000 ;
+ RECT 245.055000 1658.260000 246.320000 1658.740000 ;
+ RECT 241.390000 1652.820000 242.390000 1653.300000 ;
+ RECT 245.055000 1652.820000 246.320000 1653.300000 ;
+ RECT 425.220000 1636.500000 426.320000 1636.980000 ;
+ RECT 425.220000 1641.940000 426.320000 1642.420000 ;
+ RECT 438.030000 1636.500000 439.030000 1636.980000 ;
+ RECT 438.030000 1641.940000 439.030000 1642.420000 ;
+ RECT 438.030000 1625.620000 439.030000 1626.100000 ;
+ RECT 438.030000 1631.060000 439.030000 1631.540000 ;
+ RECT 425.220000 1631.060000 426.320000 1631.540000 ;
+ RECT 425.220000 1625.620000 426.320000 1626.100000 ;
+ RECT 425.220000 1614.740000 426.320000 1615.220000 ;
+ RECT 425.220000 1620.180000 426.320000 1620.660000 ;
+ RECT 438.030000 1614.740000 439.030000 1615.220000 ;
+ RECT 438.030000 1620.180000 439.030000 1620.660000 ;
+ RECT 438.030000 1603.860000 439.030000 1604.340000 ;
+ RECT 438.030000 1598.420000 439.030000 1598.900000 ;
+ RECT 438.030000 1609.300000 439.030000 1609.780000 ;
+ RECT 425.220000 1609.300000 426.320000 1609.780000 ;
+ RECT 425.220000 1603.860000 426.320000 1604.340000 ;
+ RECT 425.220000 1598.420000 426.320000 1598.900000 ;
+ RECT 380.220000 1625.620000 381.320000 1626.100000 ;
+ RECT 380.220000 1631.060000 381.320000 1631.540000 ;
+ RECT 380.220000 1636.500000 381.320000 1636.980000 ;
+ RECT 380.220000 1641.940000 381.320000 1642.420000 ;
+ RECT 380.220000 1598.420000 381.320000 1598.900000 ;
+ RECT 380.220000 1603.860000 381.320000 1604.340000 ;
+ RECT 380.220000 1609.300000 381.320000 1609.780000 ;
+ RECT 380.220000 1614.740000 381.320000 1615.220000 ;
+ RECT 380.220000 1620.180000 381.320000 1620.660000 ;
+ RECT 425.220000 1587.540000 426.320000 1588.020000 ;
+ RECT 425.220000 1592.980000 426.320000 1593.460000 ;
+ RECT 438.030000 1587.540000 439.030000 1588.020000 ;
+ RECT 438.030000 1592.980000 439.030000 1593.460000 ;
+ RECT 425.220000 1576.660000 426.320000 1577.140000 ;
+ RECT 425.220000 1582.100000 426.320000 1582.580000 ;
+ RECT 438.030000 1576.660000 439.030000 1577.140000 ;
+ RECT 438.030000 1582.100000 439.030000 1582.580000 ;
+ RECT 438.030000 1565.780000 439.030000 1566.260000 ;
+ RECT 438.030000 1560.340000 439.030000 1560.820000 ;
+ RECT 438.030000 1571.220000 439.030000 1571.700000 ;
+ RECT 425.220000 1571.220000 426.320000 1571.700000 ;
+ RECT 425.220000 1565.780000 426.320000 1566.260000 ;
+ RECT 425.220000 1560.340000 426.320000 1560.820000 ;
+ RECT 425.220000 1554.900000 426.320000 1555.380000 ;
+ RECT 438.030000 1554.900000 439.030000 1555.380000 ;
+ RECT 380.220000 1576.660000 381.320000 1577.140000 ;
+ RECT 380.220000 1582.100000 381.320000 1582.580000 ;
+ RECT 380.220000 1587.540000 381.320000 1588.020000 ;
+ RECT 380.220000 1592.980000 381.320000 1593.460000 ;
+ RECT 380.220000 1554.900000 381.320000 1555.380000 ;
+ RECT 380.220000 1560.340000 381.320000 1560.820000 ;
+ RECT 380.220000 1565.780000 381.320000 1566.260000 ;
+ RECT 380.220000 1571.220000 381.320000 1571.700000 ;
+ RECT 335.220000 1625.620000 336.320000 1626.100000 ;
+ RECT 335.220000 1631.060000 336.320000 1631.540000 ;
+ RECT 335.220000 1636.500000 336.320000 1636.980000 ;
+ RECT 335.220000 1641.940000 336.320000 1642.420000 ;
+ RECT 290.220000 1625.620000 291.320000 1626.100000 ;
+ RECT 290.220000 1631.060000 291.320000 1631.540000 ;
+ RECT 290.220000 1636.500000 291.320000 1636.980000 ;
+ RECT 290.220000 1641.940000 291.320000 1642.420000 ;
+ RECT 335.220000 1598.420000 336.320000 1598.900000 ;
+ RECT 335.220000 1603.860000 336.320000 1604.340000 ;
+ RECT 335.220000 1609.300000 336.320000 1609.780000 ;
+ RECT 335.220000 1614.740000 336.320000 1615.220000 ;
+ RECT 335.220000 1620.180000 336.320000 1620.660000 ;
+ RECT 290.220000 1598.420000 291.320000 1598.900000 ;
+ RECT 290.220000 1603.860000 291.320000 1604.340000 ;
+ RECT 290.220000 1609.300000 291.320000 1609.780000 ;
+ RECT 290.220000 1614.740000 291.320000 1615.220000 ;
+ RECT 290.220000 1620.180000 291.320000 1620.660000 ;
+ RECT 241.390000 1641.940000 242.390000 1642.420000 ;
+ RECT 245.055000 1641.940000 246.320000 1642.420000 ;
+ RECT 241.390000 1636.500000 242.390000 1636.980000 ;
+ RECT 245.055000 1636.500000 246.320000 1636.980000 ;
+ RECT 241.390000 1631.060000 242.390000 1631.540000 ;
+ RECT 245.055000 1631.060000 246.320000 1631.540000 ;
+ RECT 241.390000 1625.620000 242.390000 1626.100000 ;
+ RECT 245.055000 1625.620000 246.320000 1626.100000 ;
+ RECT 241.390000 1620.180000 242.390000 1620.660000 ;
+ RECT 245.055000 1620.180000 246.320000 1620.660000 ;
+ RECT 241.390000 1614.740000 242.390000 1615.220000 ;
+ RECT 245.055000 1614.740000 246.320000 1615.220000 ;
+ RECT 241.390000 1603.860000 242.390000 1604.340000 ;
+ RECT 245.055000 1603.860000 246.320000 1604.340000 ;
+ RECT 241.390000 1609.300000 242.390000 1609.780000 ;
+ RECT 245.055000 1609.300000 246.320000 1609.780000 ;
+ RECT 241.390000 1598.420000 242.390000 1598.900000 ;
+ RECT 245.055000 1598.420000 246.320000 1598.900000 ;
+ RECT 335.220000 1576.660000 336.320000 1577.140000 ;
+ RECT 335.220000 1582.100000 336.320000 1582.580000 ;
+ RECT 335.220000 1587.540000 336.320000 1588.020000 ;
+ RECT 335.220000 1592.980000 336.320000 1593.460000 ;
+ RECT 290.220000 1576.660000 291.320000 1577.140000 ;
+ RECT 290.220000 1582.100000 291.320000 1582.580000 ;
+ RECT 290.220000 1587.540000 291.320000 1588.020000 ;
+ RECT 290.220000 1592.980000 291.320000 1593.460000 ;
+ RECT 335.220000 1554.900000 336.320000 1555.380000 ;
+ RECT 335.220000 1560.340000 336.320000 1560.820000 ;
+ RECT 335.220000 1565.780000 336.320000 1566.260000 ;
+ RECT 335.220000 1571.220000 336.320000 1571.700000 ;
+ RECT 290.220000 1554.900000 291.320000 1555.380000 ;
+ RECT 290.220000 1560.340000 291.320000 1560.820000 ;
+ RECT 290.220000 1565.780000 291.320000 1566.260000 ;
+ RECT 290.220000 1571.220000 291.320000 1571.700000 ;
+ RECT 241.390000 1592.980000 242.390000 1593.460000 ;
+ RECT 245.055000 1592.980000 246.320000 1593.460000 ;
+ RECT 241.390000 1587.540000 242.390000 1588.020000 ;
+ RECT 245.055000 1587.540000 246.320000 1588.020000 ;
+ RECT 241.390000 1582.100000 242.390000 1582.580000 ;
+ RECT 245.055000 1582.100000 246.320000 1582.580000 ;
+ RECT 241.390000 1576.660000 242.390000 1577.140000 ;
+ RECT 245.055000 1576.660000 246.320000 1577.140000 ;
+ RECT 241.390000 1571.220000 242.390000 1571.700000 ;
+ RECT 245.055000 1571.220000 246.320000 1571.700000 ;
+ RECT 241.390000 1560.340000 242.390000 1560.820000 ;
+ RECT 245.055000 1560.340000 246.320000 1560.820000 ;
+ RECT 241.390000 1565.780000 242.390000 1566.260000 ;
+ RECT 245.055000 1565.780000 246.320000 1566.260000 ;
+ RECT 241.390000 1554.900000 242.390000 1555.380000 ;
+ RECT 245.055000 1554.900000 246.320000 1555.380000 ;
+ RECT 380.220000 1647.380000 381.320000 1647.860000 ;
+ RECT 425.220000 1647.380000 426.320000 1647.860000 ;
+ RECT 438.030000 1647.380000 439.030000 1647.860000 ;
+ RECT 290.220000 1647.380000 291.320000 1647.860000 ;
+ RECT 335.220000 1647.380000 336.320000 1647.860000 ;
+ RECT 241.390000 1647.380000 242.390000 1647.860000 ;
+ RECT 245.055000 1647.380000 246.320000 1647.860000 ;
+ RECT 240.160000 1744.140000 440.260000 1745.140000 ;
+ RECT 240.160000 1548.570000 440.260000 1549.570000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 1547.320000 242.390000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 241.390000 1746.580000 242.390000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 1547.320000 439.030000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 438.030000 1746.580000 439.030000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1548.570000 241.160000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1548.570000 440.260000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1744.140000 241.160000 1745.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1744.140000 440.260000 1745.140000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 3373.560000 446.420000 3374.040000 ;
+ RECT 445.155000 3368.120000 446.420000 3368.600000 ;
+ RECT 445.155000 3362.680000 446.420000 3363.160000 ;
+ RECT 445.155000 3357.240000 446.420000 3357.720000 ;
+ RECT 441.490000 3349.660000 442.490000 3379.920000 ;
+ RECT 638.130000 3349.660000 639.130000 3379.920000 ;
+ RECT 445.320000 3350.910000 446.420000 3378.160000 ;
+ RECT 490.320000 3350.910000 491.420000 3378.160000 ;
+ RECT 535.320000 3350.910000 536.420000 3378.160000 ;
+ RECT 580.320000 3350.910000 581.420000 3378.160000 ;
+ RECT 625.320000 3350.910000 626.420000 3378.160000 ;
+ LAYER met3 ;
+ RECT 638.130000 3373.560000 639.130000 3374.040000 ;
+ RECT 638.130000 3368.120000 639.130000 3368.600000 ;
+ RECT 625.320000 3373.560000 626.420000 3374.040000 ;
+ RECT 625.320000 3368.120000 626.420000 3368.600000 ;
+ RECT 580.320000 3368.120000 581.420000 3368.600000 ;
+ RECT 580.320000 3373.560000 581.420000 3374.040000 ;
+ RECT 535.320000 3368.120000 536.420000 3368.600000 ;
+ RECT 490.320000 3368.120000 491.420000 3368.600000 ;
+ RECT 535.320000 3373.560000 536.420000 3374.040000 ;
+ RECT 490.320000 3373.560000 491.420000 3374.040000 ;
+ RECT 445.155000 3373.560000 446.420000 3374.040000 ;
+ RECT 441.490000 3373.560000 442.490000 3374.040000 ;
+ RECT 445.155000 3368.120000 446.420000 3368.600000 ;
+ RECT 441.490000 3368.120000 442.490000 3368.600000 ;
+ RECT 638.130000 3362.680000 639.130000 3363.160000 ;
+ RECT 638.130000 3357.240000 639.130000 3357.720000 ;
+ RECT 625.320000 3362.680000 626.420000 3363.160000 ;
+ RECT 625.320000 3357.240000 626.420000 3357.720000 ;
+ RECT 580.320000 3357.240000 581.420000 3357.720000 ;
+ RECT 580.320000 3362.680000 581.420000 3363.160000 ;
+ RECT 535.320000 3357.240000 536.420000 3357.720000 ;
+ RECT 490.320000 3357.240000 491.420000 3357.720000 ;
+ RECT 535.320000 3362.680000 536.420000 3363.160000 ;
+ RECT 490.320000 3362.680000 491.420000 3363.160000 ;
+ RECT 445.155000 3362.680000 446.420000 3363.160000 ;
+ RECT 441.490000 3362.680000 442.490000 3363.160000 ;
+ RECT 445.155000 3357.240000 446.420000 3357.720000 ;
+ RECT 441.490000 3357.240000 442.490000 3357.720000 ;
+ RECT 440.260000 3377.160000 640.360000 3378.160000 ;
+ RECT 440.260000 3350.910000 640.360000 3351.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 3349.660000 442.490000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 3378.920000 442.490000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 3349.660000 639.130000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 3378.920000 639.130000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 3350.910000 441.260000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 3350.910000 640.360000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 3377.160000 441.260000 3378.160000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 3377.160000 640.360000 3378.160000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 1539.600000 446.420000 1540.080000 ;
+ RECT 445.155000 1528.720000 446.420000 1529.200000 ;
+ RECT 445.155000 1534.160000 446.420000 1534.640000 ;
+ RECT 445.155000 1523.280000 446.420000 1523.760000 ;
+ RECT 445.155000 1517.840000 446.420000 1518.320000 ;
+ RECT 445.155000 1512.400000 446.420000 1512.880000 ;
+ RECT 445.155000 1506.960000 446.420000 1507.440000 ;
+ RECT 445.155000 1501.520000 446.420000 1502.000000 ;
+ RECT 445.155000 1496.080000 446.420000 1496.560000 ;
+ RECT 445.155000 1485.200000 446.420000 1485.680000 ;
+ RECT 445.155000 1490.640000 446.420000 1491.120000 ;
+ RECT 445.155000 1479.760000 446.420000 1480.240000 ;
+ RECT 445.155000 1474.320000 446.420000 1474.800000 ;
+ RECT 445.155000 1468.880000 446.420000 1469.360000 ;
+ RECT 445.155000 1463.440000 446.420000 1463.920000 ;
+ RECT 445.155000 1458.000000 446.420000 1458.480000 ;
+ RECT 445.155000 1452.560000 446.420000 1453.040000 ;
+ RECT 445.155000 1441.680000 446.420000 1442.160000 ;
+ RECT 445.155000 1436.240000 446.420000 1436.720000 ;
+ RECT 445.155000 1430.800000 446.420000 1431.280000 ;
+ RECT 445.155000 1425.360000 446.420000 1425.840000 ;
+ RECT 445.155000 1419.920000 446.420000 1420.400000 ;
+ RECT 445.155000 1414.480000 446.420000 1414.960000 ;
+ RECT 445.155000 1403.600000 446.420000 1404.080000 ;
+ RECT 445.155000 1409.040000 446.420000 1409.520000 ;
+ RECT 445.155000 1398.160000 446.420000 1398.640000 ;
+ RECT 445.155000 1392.720000 446.420000 1393.200000 ;
+ RECT 445.155000 1387.280000 446.420000 1387.760000 ;
+ RECT 445.155000 1381.840000 446.420000 1382.320000 ;
+ RECT 445.155000 1376.400000 446.420000 1376.880000 ;
+ RECT 445.155000 1370.960000 446.420000 1371.440000 ;
+ RECT 445.155000 1360.080000 446.420000 1360.560000 ;
+ RECT 445.155000 1365.520000 446.420000 1366.000000 ;
+ RECT 445.155000 1354.640000 446.420000 1355.120000 ;
+ RECT 445.155000 1447.120000 446.420000 1447.600000 ;
+ RECT 625.320000 1348.310000 626.420000 1544.880000 ;
+ RECT 580.320000 1348.310000 581.420000 1544.880000 ;
+ RECT 638.130000 1347.060000 639.130000 1547.320000 ;
+ RECT 535.320000 1348.310000 536.420000 1544.880000 ;
+ RECT 490.320000 1348.310000 491.420000 1544.880000 ;
+ RECT 445.320000 1348.310000 446.420000 1544.880000 ;
+ RECT 441.490000 1347.060000 442.490000 1547.320000 ;
+ LAYER met3 ;
+ RECT 625.320000 1539.600000 626.420000 1540.080000 ;
+ RECT 638.130000 1539.600000 639.130000 1540.080000 ;
+ RECT 638.130000 1528.720000 639.130000 1529.200000 ;
+ RECT 638.130000 1523.280000 639.130000 1523.760000 ;
+ RECT 638.130000 1534.160000 639.130000 1534.640000 ;
+ RECT 625.320000 1534.160000 626.420000 1534.640000 ;
+ RECT 625.320000 1528.720000 626.420000 1529.200000 ;
+ RECT 625.320000 1523.280000 626.420000 1523.760000 ;
+ RECT 625.320000 1512.400000 626.420000 1512.880000 ;
+ RECT 625.320000 1517.840000 626.420000 1518.320000 ;
+ RECT 638.130000 1512.400000 639.130000 1512.880000 ;
+ RECT 638.130000 1517.840000 639.130000 1518.320000 ;
+ RECT 625.320000 1501.520000 626.420000 1502.000000 ;
+ RECT 625.320000 1506.960000 626.420000 1507.440000 ;
+ RECT 638.130000 1501.520000 639.130000 1502.000000 ;
+ RECT 638.130000 1506.960000 639.130000 1507.440000 ;
+ RECT 580.320000 1523.280000 581.420000 1523.760000 ;
+ RECT 580.320000 1528.720000 581.420000 1529.200000 ;
+ RECT 580.320000 1534.160000 581.420000 1534.640000 ;
+ RECT 580.320000 1539.600000 581.420000 1540.080000 ;
+ RECT 580.320000 1506.960000 581.420000 1507.440000 ;
+ RECT 580.320000 1501.520000 581.420000 1502.000000 ;
+ RECT 580.320000 1512.400000 581.420000 1512.880000 ;
+ RECT 580.320000 1517.840000 581.420000 1518.320000 ;
+ RECT 638.130000 1490.640000 639.130000 1491.120000 ;
+ RECT 638.130000 1485.200000 639.130000 1485.680000 ;
+ RECT 638.130000 1496.080000 639.130000 1496.560000 ;
+ RECT 625.320000 1496.080000 626.420000 1496.560000 ;
+ RECT 625.320000 1490.640000 626.420000 1491.120000 ;
+ RECT 625.320000 1485.200000 626.420000 1485.680000 ;
+ RECT 625.320000 1474.320000 626.420000 1474.800000 ;
+ RECT 625.320000 1479.760000 626.420000 1480.240000 ;
+ RECT 638.130000 1474.320000 639.130000 1474.800000 ;
+ RECT 638.130000 1479.760000 639.130000 1480.240000 ;
+ RECT 638.130000 1463.440000 639.130000 1463.920000 ;
+ RECT 638.130000 1468.880000 639.130000 1469.360000 ;
+ RECT 625.320000 1468.880000 626.420000 1469.360000 ;
+ RECT 625.320000 1463.440000 626.420000 1463.920000 ;
+ RECT 625.320000 1452.560000 626.420000 1453.040000 ;
+ RECT 625.320000 1458.000000 626.420000 1458.480000 ;
+ RECT 638.130000 1452.560000 639.130000 1453.040000 ;
+ RECT 638.130000 1458.000000 639.130000 1458.480000 ;
+ RECT 580.320000 1474.320000 581.420000 1474.800000 ;
+ RECT 580.320000 1479.760000 581.420000 1480.240000 ;
+ RECT 580.320000 1485.200000 581.420000 1485.680000 ;
+ RECT 580.320000 1490.640000 581.420000 1491.120000 ;
+ RECT 580.320000 1496.080000 581.420000 1496.560000 ;
+ RECT 580.320000 1452.560000 581.420000 1453.040000 ;
+ RECT 580.320000 1458.000000 581.420000 1458.480000 ;
+ RECT 580.320000 1463.440000 581.420000 1463.920000 ;
+ RECT 580.320000 1468.880000 581.420000 1469.360000 ;
+ RECT 535.320000 1528.720000 536.420000 1529.200000 ;
+ RECT 535.320000 1523.280000 536.420000 1523.760000 ;
+ RECT 535.320000 1534.160000 536.420000 1534.640000 ;
+ RECT 535.320000 1539.600000 536.420000 1540.080000 ;
+ RECT 490.320000 1523.280000 491.420000 1523.760000 ;
+ RECT 490.320000 1528.720000 491.420000 1529.200000 ;
+ RECT 490.320000 1534.160000 491.420000 1534.640000 ;
+ RECT 490.320000 1539.600000 491.420000 1540.080000 ;
+ RECT 535.320000 1501.520000 536.420000 1502.000000 ;
+ RECT 535.320000 1506.960000 536.420000 1507.440000 ;
+ RECT 535.320000 1512.400000 536.420000 1512.880000 ;
+ RECT 535.320000 1517.840000 536.420000 1518.320000 ;
+ RECT 490.320000 1501.520000 491.420000 1502.000000 ;
+ RECT 490.320000 1506.960000 491.420000 1507.440000 ;
+ RECT 490.320000 1512.400000 491.420000 1512.880000 ;
+ RECT 490.320000 1517.840000 491.420000 1518.320000 ;
+ RECT 441.490000 1539.600000 442.490000 1540.080000 ;
+ RECT 445.155000 1539.600000 446.420000 1540.080000 ;
+ RECT 441.490000 1528.720000 442.490000 1529.200000 ;
+ RECT 445.155000 1528.720000 446.420000 1529.200000 ;
+ RECT 441.490000 1534.160000 442.490000 1534.640000 ;
+ RECT 445.155000 1534.160000 446.420000 1534.640000 ;
+ RECT 441.490000 1523.280000 442.490000 1523.760000 ;
+ RECT 445.155000 1523.280000 446.420000 1523.760000 ;
+ RECT 441.490000 1517.840000 442.490000 1518.320000 ;
+ RECT 445.155000 1517.840000 446.420000 1518.320000 ;
+ RECT 441.490000 1512.400000 442.490000 1512.880000 ;
+ RECT 445.155000 1512.400000 446.420000 1512.880000 ;
+ RECT 441.490000 1506.960000 442.490000 1507.440000 ;
+ RECT 445.155000 1506.960000 446.420000 1507.440000 ;
+ RECT 441.490000 1501.520000 442.490000 1502.000000 ;
+ RECT 445.155000 1501.520000 446.420000 1502.000000 ;
+ RECT 535.320000 1474.320000 536.420000 1474.800000 ;
+ RECT 535.320000 1479.760000 536.420000 1480.240000 ;
+ RECT 535.320000 1485.200000 536.420000 1485.680000 ;
+ RECT 535.320000 1490.640000 536.420000 1491.120000 ;
+ RECT 535.320000 1496.080000 536.420000 1496.560000 ;
+ RECT 490.320000 1474.320000 491.420000 1474.800000 ;
+ RECT 490.320000 1479.760000 491.420000 1480.240000 ;
+ RECT 490.320000 1485.200000 491.420000 1485.680000 ;
+ RECT 490.320000 1490.640000 491.420000 1491.120000 ;
+ RECT 490.320000 1496.080000 491.420000 1496.560000 ;
+ RECT 535.320000 1452.560000 536.420000 1453.040000 ;
+ RECT 535.320000 1458.000000 536.420000 1458.480000 ;
+ RECT 535.320000 1463.440000 536.420000 1463.920000 ;
+ RECT 535.320000 1468.880000 536.420000 1469.360000 ;
+ RECT 490.320000 1452.560000 491.420000 1453.040000 ;
+ RECT 490.320000 1458.000000 491.420000 1458.480000 ;
+ RECT 490.320000 1463.440000 491.420000 1463.920000 ;
+ RECT 490.320000 1468.880000 491.420000 1469.360000 ;
+ RECT 441.490000 1496.080000 442.490000 1496.560000 ;
+ RECT 445.155000 1496.080000 446.420000 1496.560000 ;
+ RECT 441.490000 1485.200000 442.490000 1485.680000 ;
+ RECT 445.155000 1485.200000 446.420000 1485.680000 ;
+ RECT 441.490000 1490.640000 442.490000 1491.120000 ;
+ RECT 445.155000 1490.640000 446.420000 1491.120000 ;
+ RECT 441.490000 1479.760000 442.490000 1480.240000 ;
+ RECT 445.155000 1479.760000 446.420000 1480.240000 ;
+ RECT 441.490000 1474.320000 442.490000 1474.800000 ;
+ RECT 445.155000 1474.320000 446.420000 1474.800000 ;
+ RECT 441.490000 1468.880000 442.490000 1469.360000 ;
+ RECT 445.155000 1468.880000 446.420000 1469.360000 ;
+ RECT 441.490000 1463.440000 442.490000 1463.920000 ;
+ RECT 445.155000 1463.440000 446.420000 1463.920000 ;
+ RECT 441.490000 1458.000000 442.490000 1458.480000 ;
+ RECT 445.155000 1458.000000 446.420000 1458.480000 ;
+ RECT 441.490000 1452.560000 442.490000 1453.040000 ;
+ RECT 445.155000 1452.560000 446.420000 1453.040000 ;
+ RECT 625.320000 1436.240000 626.420000 1436.720000 ;
+ RECT 625.320000 1441.680000 626.420000 1442.160000 ;
+ RECT 638.130000 1436.240000 639.130000 1436.720000 ;
+ RECT 638.130000 1441.680000 639.130000 1442.160000 ;
+ RECT 638.130000 1425.360000 639.130000 1425.840000 ;
+ RECT 638.130000 1430.800000 639.130000 1431.280000 ;
+ RECT 625.320000 1430.800000 626.420000 1431.280000 ;
+ RECT 625.320000 1425.360000 626.420000 1425.840000 ;
+ RECT 625.320000 1414.480000 626.420000 1414.960000 ;
+ RECT 625.320000 1419.920000 626.420000 1420.400000 ;
+ RECT 638.130000 1414.480000 639.130000 1414.960000 ;
+ RECT 638.130000 1419.920000 639.130000 1420.400000 ;
+ RECT 638.130000 1403.600000 639.130000 1404.080000 ;
+ RECT 638.130000 1398.160000 639.130000 1398.640000 ;
+ RECT 638.130000 1409.040000 639.130000 1409.520000 ;
+ RECT 625.320000 1409.040000 626.420000 1409.520000 ;
+ RECT 625.320000 1403.600000 626.420000 1404.080000 ;
+ RECT 625.320000 1398.160000 626.420000 1398.640000 ;
+ RECT 580.320000 1425.360000 581.420000 1425.840000 ;
+ RECT 580.320000 1430.800000 581.420000 1431.280000 ;
+ RECT 580.320000 1436.240000 581.420000 1436.720000 ;
+ RECT 580.320000 1441.680000 581.420000 1442.160000 ;
+ RECT 580.320000 1398.160000 581.420000 1398.640000 ;
+ RECT 580.320000 1403.600000 581.420000 1404.080000 ;
+ RECT 580.320000 1409.040000 581.420000 1409.520000 ;
+ RECT 580.320000 1414.480000 581.420000 1414.960000 ;
+ RECT 580.320000 1419.920000 581.420000 1420.400000 ;
+ RECT 625.320000 1387.280000 626.420000 1387.760000 ;
+ RECT 625.320000 1392.720000 626.420000 1393.200000 ;
+ RECT 638.130000 1387.280000 639.130000 1387.760000 ;
+ RECT 638.130000 1392.720000 639.130000 1393.200000 ;
+ RECT 625.320000 1376.400000 626.420000 1376.880000 ;
+ RECT 625.320000 1381.840000 626.420000 1382.320000 ;
+ RECT 638.130000 1376.400000 639.130000 1376.880000 ;
+ RECT 638.130000 1381.840000 639.130000 1382.320000 ;
+ RECT 638.130000 1365.520000 639.130000 1366.000000 ;
+ RECT 638.130000 1360.080000 639.130000 1360.560000 ;
+ RECT 638.130000 1370.960000 639.130000 1371.440000 ;
+ RECT 625.320000 1370.960000 626.420000 1371.440000 ;
+ RECT 625.320000 1365.520000 626.420000 1366.000000 ;
+ RECT 625.320000 1360.080000 626.420000 1360.560000 ;
+ RECT 625.320000 1354.640000 626.420000 1355.120000 ;
+ RECT 638.130000 1354.640000 639.130000 1355.120000 ;
+ RECT 580.320000 1376.400000 581.420000 1376.880000 ;
+ RECT 580.320000 1381.840000 581.420000 1382.320000 ;
+ RECT 580.320000 1387.280000 581.420000 1387.760000 ;
+ RECT 580.320000 1392.720000 581.420000 1393.200000 ;
+ RECT 580.320000 1354.640000 581.420000 1355.120000 ;
+ RECT 580.320000 1360.080000 581.420000 1360.560000 ;
+ RECT 580.320000 1365.520000 581.420000 1366.000000 ;
+ RECT 580.320000 1370.960000 581.420000 1371.440000 ;
+ RECT 535.320000 1425.360000 536.420000 1425.840000 ;
+ RECT 535.320000 1430.800000 536.420000 1431.280000 ;
+ RECT 535.320000 1436.240000 536.420000 1436.720000 ;
+ RECT 535.320000 1441.680000 536.420000 1442.160000 ;
+ RECT 490.320000 1425.360000 491.420000 1425.840000 ;
+ RECT 490.320000 1430.800000 491.420000 1431.280000 ;
+ RECT 490.320000 1436.240000 491.420000 1436.720000 ;
+ RECT 490.320000 1441.680000 491.420000 1442.160000 ;
+ RECT 535.320000 1398.160000 536.420000 1398.640000 ;
+ RECT 535.320000 1403.600000 536.420000 1404.080000 ;
+ RECT 535.320000 1409.040000 536.420000 1409.520000 ;
+ RECT 535.320000 1414.480000 536.420000 1414.960000 ;
+ RECT 535.320000 1419.920000 536.420000 1420.400000 ;
+ RECT 490.320000 1398.160000 491.420000 1398.640000 ;
+ RECT 490.320000 1403.600000 491.420000 1404.080000 ;
+ RECT 490.320000 1409.040000 491.420000 1409.520000 ;
+ RECT 490.320000 1414.480000 491.420000 1414.960000 ;
+ RECT 490.320000 1419.920000 491.420000 1420.400000 ;
+ RECT 441.490000 1441.680000 442.490000 1442.160000 ;
+ RECT 445.155000 1441.680000 446.420000 1442.160000 ;
+ RECT 441.490000 1436.240000 442.490000 1436.720000 ;
+ RECT 445.155000 1436.240000 446.420000 1436.720000 ;
+ RECT 441.490000 1430.800000 442.490000 1431.280000 ;
+ RECT 445.155000 1430.800000 446.420000 1431.280000 ;
+ RECT 441.490000 1425.360000 442.490000 1425.840000 ;
+ RECT 445.155000 1425.360000 446.420000 1425.840000 ;
+ RECT 441.490000 1419.920000 442.490000 1420.400000 ;
+ RECT 445.155000 1419.920000 446.420000 1420.400000 ;
+ RECT 441.490000 1414.480000 442.490000 1414.960000 ;
+ RECT 445.155000 1414.480000 446.420000 1414.960000 ;
+ RECT 441.490000 1403.600000 442.490000 1404.080000 ;
+ RECT 445.155000 1403.600000 446.420000 1404.080000 ;
+ RECT 441.490000 1409.040000 442.490000 1409.520000 ;
+ RECT 445.155000 1409.040000 446.420000 1409.520000 ;
+ RECT 441.490000 1398.160000 442.490000 1398.640000 ;
+ RECT 445.155000 1398.160000 446.420000 1398.640000 ;
+ RECT 535.320000 1376.400000 536.420000 1376.880000 ;
+ RECT 535.320000 1381.840000 536.420000 1382.320000 ;
+ RECT 535.320000 1387.280000 536.420000 1387.760000 ;
+ RECT 535.320000 1392.720000 536.420000 1393.200000 ;
+ RECT 490.320000 1376.400000 491.420000 1376.880000 ;
+ RECT 490.320000 1381.840000 491.420000 1382.320000 ;
+ RECT 490.320000 1387.280000 491.420000 1387.760000 ;
+ RECT 490.320000 1392.720000 491.420000 1393.200000 ;
+ RECT 535.320000 1354.640000 536.420000 1355.120000 ;
+ RECT 535.320000 1360.080000 536.420000 1360.560000 ;
+ RECT 535.320000 1365.520000 536.420000 1366.000000 ;
+ RECT 535.320000 1370.960000 536.420000 1371.440000 ;
+ RECT 490.320000 1354.640000 491.420000 1355.120000 ;
+ RECT 490.320000 1360.080000 491.420000 1360.560000 ;
+ RECT 490.320000 1365.520000 491.420000 1366.000000 ;
+ RECT 490.320000 1370.960000 491.420000 1371.440000 ;
+ RECT 441.490000 1392.720000 442.490000 1393.200000 ;
+ RECT 445.155000 1392.720000 446.420000 1393.200000 ;
+ RECT 441.490000 1387.280000 442.490000 1387.760000 ;
+ RECT 445.155000 1387.280000 446.420000 1387.760000 ;
+ RECT 441.490000 1381.840000 442.490000 1382.320000 ;
+ RECT 445.155000 1381.840000 446.420000 1382.320000 ;
+ RECT 441.490000 1376.400000 442.490000 1376.880000 ;
+ RECT 445.155000 1376.400000 446.420000 1376.880000 ;
+ RECT 441.490000 1370.960000 442.490000 1371.440000 ;
+ RECT 445.155000 1370.960000 446.420000 1371.440000 ;
+ RECT 441.490000 1360.080000 442.490000 1360.560000 ;
+ RECT 445.155000 1360.080000 446.420000 1360.560000 ;
+ RECT 441.490000 1365.520000 442.490000 1366.000000 ;
+ RECT 445.155000 1365.520000 446.420000 1366.000000 ;
+ RECT 441.490000 1354.640000 442.490000 1355.120000 ;
+ RECT 445.155000 1354.640000 446.420000 1355.120000 ;
+ RECT 580.320000 1447.120000 581.420000 1447.600000 ;
+ RECT 625.320000 1447.120000 626.420000 1447.600000 ;
+ RECT 638.130000 1447.120000 639.130000 1447.600000 ;
+ RECT 490.320000 1447.120000 491.420000 1447.600000 ;
+ RECT 535.320000 1447.120000 536.420000 1447.600000 ;
+ RECT 441.490000 1447.120000 442.490000 1447.600000 ;
+ RECT 445.155000 1447.120000 446.420000 1447.600000 ;
+ RECT 440.260000 1543.880000 640.360000 1544.880000 ;
+ RECT 440.260000 1348.310000 640.360000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 1347.060000 442.490000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 1546.320000 442.490000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 1347.060000 639.130000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 1546.320000 639.130000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1348.310000 441.260000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1348.310000 640.360000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1543.880000 441.260000 1544.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1543.880000 640.360000 1544.880000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 1339.340000 446.420000 1339.820000 ;
+ RECT 445.155000 1328.460000 446.420000 1328.940000 ;
+ RECT 445.155000 1333.900000 446.420000 1334.380000 ;
+ RECT 445.155000 1323.020000 446.420000 1323.500000 ;
+ RECT 445.155000 1317.580000 446.420000 1318.060000 ;
+ RECT 445.155000 1312.140000 446.420000 1312.620000 ;
+ RECT 445.155000 1306.700000 446.420000 1307.180000 ;
+ RECT 445.155000 1301.260000 446.420000 1301.740000 ;
+ RECT 445.155000 1295.820000 446.420000 1296.300000 ;
+ RECT 445.155000 1284.940000 446.420000 1285.420000 ;
+ RECT 445.155000 1290.380000 446.420000 1290.860000 ;
+ RECT 445.155000 1279.500000 446.420000 1279.980000 ;
+ RECT 445.155000 1274.060000 446.420000 1274.540000 ;
+ RECT 445.155000 1268.620000 446.420000 1269.100000 ;
+ RECT 445.155000 1263.180000 446.420000 1263.660000 ;
+ RECT 445.155000 1257.740000 446.420000 1258.220000 ;
+ RECT 445.155000 1252.300000 446.420000 1252.780000 ;
+ RECT 445.155000 1241.420000 446.420000 1241.900000 ;
+ RECT 445.155000 1235.980000 446.420000 1236.460000 ;
+ RECT 445.155000 1230.540000 446.420000 1231.020000 ;
+ RECT 445.155000 1225.100000 446.420000 1225.580000 ;
+ RECT 445.155000 1219.660000 446.420000 1220.140000 ;
+ RECT 445.155000 1214.220000 446.420000 1214.700000 ;
+ RECT 445.155000 1203.340000 446.420000 1203.820000 ;
+ RECT 445.155000 1208.780000 446.420000 1209.260000 ;
+ RECT 445.155000 1197.900000 446.420000 1198.380000 ;
+ RECT 445.155000 1192.460000 446.420000 1192.940000 ;
+ RECT 445.155000 1187.020000 446.420000 1187.500000 ;
+ RECT 445.155000 1181.580000 446.420000 1182.060000 ;
+ RECT 445.155000 1176.140000 446.420000 1176.620000 ;
+ RECT 445.155000 1170.700000 446.420000 1171.180000 ;
+ RECT 445.155000 1159.820000 446.420000 1160.300000 ;
+ RECT 445.155000 1165.260000 446.420000 1165.740000 ;
+ RECT 445.155000 1154.380000 446.420000 1154.860000 ;
+ RECT 445.155000 1246.860000 446.420000 1247.340000 ;
+ RECT 625.320000 1148.050000 626.420000 1344.620000 ;
+ RECT 580.320000 1148.050000 581.420000 1344.620000 ;
+ RECT 638.130000 1146.800000 639.130000 1347.060000 ;
+ RECT 535.320000 1148.050000 536.420000 1344.620000 ;
+ RECT 490.320000 1148.050000 491.420000 1344.620000 ;
+ RECT 445.320000 1148.050000 446.420000 1344.620000 ;
+ RECT 441.490000 1146.800000 442.490000 1347.060000 ;
+ LAYER met3 ;
+ RECT 625.320000 1339.340000 626.420000 1339.820000 ;
+ RECT 638.130000 1339.340000 639.130000 1339.820000 ;
+ RECT 638.130000 1328.460000 639.130000 1328.940000 ;
+ RECT 638.130000 1323.020000 639.130000 1323.500000 ;
+ RECT 638.130000 1333.900000 639.130000 1334.380000 ;
+ RECT 625.320000 1333.900000 626.420000 1334.380000 ;
+ RECT 625.320000 1328.460000 626.420000 1328.940000 ;
+ RECT 625.320000 1323.020000 626.420000 1323.500000 ;
+ RECT 625.320000 1312.140000 626.420000 1312.620000 ;
+ RECT 625.320000 1317.580000 626.420000 1318.060000 ;
+ RECT 638.130000 1312.140000 639.130000 1312.620000 ;
+ RECT 638.130000 1317.580000 639.130000 1318.060000 ;
+ RECT 625.320000 1301.260000 626.420000 1301.740000 ;
+ RECT 625.320000 1306.700000 626.420000 1307.180000 ;
+ RECT 638.130000 1301.260000 639.130000 1301.740000 ;
+ RECT 638.130000 1306.700000 639.130000 1307.180000 ;
+ RECT 580.320000 1323.020000 581.420000 1323.500000 ;
+ RECT 580.320000 1328.460000 581.420000 1328.940000 ;
+ RECT 580.320000 1333.900000 581.420000 1334.380000 ;
+ RECT 580.320000 1339.340000 581.420000 1339.820000 ;
+ RECT 580.320000 1306.700000 581.420000 1307.180000 ;
+ RECT 580.320000 1301.260000 581.420000 1301.740000 ;
+ RECT 580.320000 1312.140000 581.420000 1312.620000 ;
+ RECT 580.320000 1317.580000 581.420000 1318.060000 ;
+ RECT 638.130000 1290.380000 639.130000 1290.860000 ;
+ RECT 638.130000 1284.940000 639.130000 1285.420000 ;
+ RECT 638.130000 1295.820000 639.130000 1296.300000 ;
+ RECT 625.320000 1295.820000 626.420000 1296.300000 ;
+ RECT 625.320000 1290.380000 626.420000 1290.860000 ;
+ RECT 625.320000 1284.940000 626.420000 1285.420000 ;
+ RECT 625.320000 1274.060000 626.420000 1274.540000 ;
+ RECT 625.320000 1279.500000 626.420000 1279.980000 ;
+ RECT 638.130000 1274.060000 639.130000 1274.540000 ;
+ RECT 638.130000 1279.500000 639.130000 1279.980000 ;
+ RECT 638.130000 1263.180000 639.130000 1263.660000 ;
+ RECT 638.130000 1268.620000 639.130000 1269.100000 ;
+ RECT 625.320000 1268.620000 626.420000 1269.100000 ;
+ RECT 625.320000 1263.180000 626.420000 1263.660000 ;
+ RECT 625.320000 1252.300000 626.420000 1252.780000 ;
+ RECT 625.320000 1257.740000 626.420000 1258.220000 ;
+ RECT 638.130000 1252.300000 639.130000 1252.780000 ;
+ RECT 638.130000 1257.740000 639.130000 1258.220000 ;
+ RECT 580.320000 1274.060000 581.420000 1274.540000 ;
+ RECT 580.320000 1279.500000 581.420000 1279.980000 ;
+ RECT 580.320000 1284.940000 581.420000 1285.420000 ;
+ RECT 580.320000 1290.380000 581.420000 1290.860000 ;
+ RECT 580.320000 1295.820000 581.420000 1296.300000 ;
+ RECT 580.320000 1252.300000 581.420000 1252.780000 ;
+ RECT 580.320000 1257.740000 581.420000 1258.220000 ;
+ RECT 580.320000 1263.180000 581.420000 1263.660000 ;
+ RECT 580.320000 1268.620000 581.420000 1269.100000 ;
+ RECT 535.320000 1328.460000 536.420000 1328.940000 ;
+ RECT 535.320000 1323.020000 536.420000 1323.500000 ;
+ RECT 535.320000 1333.900000 536.420000 1334.380000 ;
+ RECT 535.320000 1339.340000 536.420000 1339.820000 ;
+ RECT 490.320000 1323.020000 491.420000 1323.500000 ;
+ RECT 490.320000 1328.460000 491.420000 1328.940000 ;
+ RECT 490.320000 1333.900000 491.420000 1334.380000 ;
+ RECT 490.320000 1339.340000 491.420000 1339.820000 ;
+ RECT 535.320000 1301.260000 536.420000 1301.740000 ;
+ RECT 535.320000 1306.700000 536.420000 1307.180000 ;
+ RECT 535.320000 1312.140000 536.420000 1312.620000 ;
+ RECT 535.320000 1317.580000 536.420000 1318.060000 ;
+ RECT 490.320000 1301.260000 491.420000 1301.740000 ;
+ RECT 490.320000 1306.700000 491.420000 1307.180000 ;
+ RECT 490.320000 1312.140000 491.420000 1312.620000 ;
+ RECT 490.320000 1317.580000 491.420000 1318.060000 ;
+ RECT 441.490000 1339.340000 442.490000 1339.820000 ;
+ RECT 445.155000 1339.340000 446.420000 1339.820000 ;
+ RECT 441.490000 1328.460000 442.490000 1328.940000 ;
+ RECT 445.155000 1328.460000 446.420000 1328.940000 ;
+ RECT 441.490000 1333.900000 442.490000 1334.380000 ;
+ RECT 445.155000 1333.900000 446.420000 1334.380000 ;
+ RECT 441.490000 1323.020000 442.490000 1323.500000 ;
+ RECT 445.155000 1323.020000 446.420000 1323.500000 ;
+ RECT 441.490000 1317.580000 442.490000 1318.060000 ;
+ RECT 445.155000 1317.580000 446.420000 1318.060000 ;
+ RECT 441.490000 1312.140000 442.490000 1312.620000 ;
+ RECT 445.155000 1312.140000 446.420000 1312.620000 ;
+ RECT 441.490000 1306.700000 442.490000 1307.180000 ;
+ RECT 445.155000 1306.700000 446.420000 1307.180000 ;
+ RECT 441.490000 1301.260000 442.490000 1301.740000 ;
+ RECT 445.155000 1301.260000 446.420000 1301.740000 ;
+ RECT 535.320000 1274.060000 536.420000 1274.540000 ;
+ RECT 535.320000 1279.500000 536.420000 1279.980000 ;
+ RECT 535.320000 1284.940000 536.420000 1285.420000 ;
+ RECT 535.320000 1290.380000 536.420000 1290.860000 ;
+ RECT 535.320000 1295.820000 536.420000 1296.300000 ;
+ RECT 490.320000 1274.060000 491.420000 1274.540000 ;
+ RECT 490.320000 1279.500000 491.420000 1279.980000 ;
+ RECT 490.320000 1284.940000 491.420000 1285.420000 ;
+ RECT 490.320000 1290.380000 491.420000 1290.860000 ;
+ RECT 490.320000 1295.820000 491.420000 1296.300000 ;
+ RECT 535.320000 1252.300000 536.420000 1252.780000 ;
+ RECT 535.320000 1257.740000 536.420000 1258.220000 ;
+ RECT 535.320000 1263.180000 536.420000 1263.660000 ;
+ RECT 535.320000 1268.620000 536.420000 1269.100000 ;
+ RECT 490.320000 1252.300000 491.420000 1252.780000 ;
+ RECT 490.320000 1257.740000 491.420000 1258.220000 ;
+ RECT 490.320000 1263.180000 491.420000 1263.660000 ;
+ RECT 490.320000 1268.620000 491.420000 1269.100000 ;
+ RECT 441.490000 1295.820000 442.490000 1296.300000 ;
+ RECT 445.155000 1295.820000 446.420000 1296.300000 ;
+ RECT 441.490000 1284.940000 442.490000 1285.420000 ;
+ RECT 445.155000 1284.940000 446.420000 1285.420000 ;
+ RECT 441.490000 1290.380000 442.490000 1290.860000 ;
+ RECT 445.155000 1290.380000 446.420000 1290.860000 ;
+ RECT 441.490000 1279.500000 442.490000 1279.980000 ;
+ RECT 445.155000 1279.500000 446.420000 1279.980000 ;
+ RECT 441.490000 1274.060000 442.490000 1274.540000 ;
+ RECT 445.155000 1274.060000 446.420000 1274.540000 ;
+ RECT 441.490000 1268.620000 442.490000 1269.100000 ;
+ RECT 445.155000 1268.620000 446.420000 1269.100000 ;
+ RECT 441.490000 1263.180000 442.490000 1263.660000 ;
+ RECT 445.155000 1263.180000 446.420000 1263.660000 ;
+ RECT 441.490000 1257.740000 442.490000 1258.220000 ;
+ RECT 445.155000 1257.740000 446.420000 1258.220000 ;
+ RECT 441.490000 1252.300000 442.490000 1252.780000 ;
+ RECT 445.155000 1252.300000 446.420000 1252.780000 ;
+ RECT 625.320000 1235.980000 626.420000 1236.460000 ;
+ RECT 625.320000 1241.420000 626.420000 1241.900000 ;
+ RECT 638.130000 1235.980000 639.130000 1236.460000 ;
+ RECT 638.130000 1241.420000 639.130000 1241.900000 ;
+ RECT 638.130000 1225.100000 639.130000 1225.580000 ;
+ RECT 638.130000 1230.540000 639.130000 1231.020000 ;
+ RECT 625.320000 1230.540000 626.420000 1231.020000 ;
+ RECT 625.320000 1225.100000 626.420000 1225.580000 ;
+ RECT 625.320000 1214.220000 626.420000 1214.700000 ;
+ RECT 625.320000 1219.660000 626.420000 1220.140000 ;
+ RECT 638.130000 1214.220000 639.130000 1214.700000 ;
+ RECT 638.130000 1219.660000 639.130000 1220.140000 ;
+ RECT 638.130000 1203.340000 639.130000 1203.820000 ;
+ RECT 638.130000 1197.900000 639.130000 1198.380000 ;
+ RECT 638.130000 1208.780000 639.130000 1209.260000 ;
+ RECT 625.320000 1208.780000 626.420000 1209.260000 ;
+ RECT 625.320000 1203.340000 626.420000 1203.820000 ;
+ RECT 625.320000 1197.900000 626.420000 1198.380000 ;
+ RECT 580.320000 1225.100000 581.420000 1225.580000 ;
+ RECT 580.320000 1230.540000 581.420000 1231.020000 ;
+ RECT 580.320000 1235.980000 581.420000 1236.460000 ;
+ RECT 580.320000 1241.420000 581.420000 1241.900000 ;
+ RECT 580.320000 1197.900000 581.420000 1198.380000 ;
+ RECT 580.320000 1203.340000 581.420000 1203.820000 ;
+ RECT 580.320000 1208.780000 581.420000 1209.260000 ;
+ RECT 580.320000 1214.220000 581.420000 1214.700000 ;
+ RECT 580.320000 1219.660000 581.420000 1220.140000 ;
+ RECT 625.320000 1187.020000 626.420000 1187.500000 ;
+ RECT 625.320000 1192.460000 626.420000 1192.940000 ;
+ RECT 638.130000 1187.020000 639.130000 1187.500000 ;
+ RECT 638.130000 1192.460000 639.130000 1192.940000 ;
+ RECT 625.320000 1176.140000 626.420000 1176.620000 ;
+ RECT 625.320000 1181.580000 626.420000 1182.060000 ;
+ RECT 638.130000 1176.140000 639.130000 1176.620000 ;
+ RECT 638.130000 1181.580000 639.130000 1182.060000 ;
+ RECT 638.130000 1165.260000 639.130000 1165.740000 ;
+ RECT 638.130000 1159.820000 639.130000 1160.300000 ;
+ RECT 638.130000 1170.700000 639.130000 1171.180000 ;
+ RECT 625.320000 1170.700000 626.420000 1171.180000 ;
+ RECT 625.320000 1165.260000 626.420000 1165.740000 ;
+ RECT 625.320000 1159.820000 626.420000 1160.300000 ;
+ RECT 625.320000 1154.380000 626.420000 1154.860000 ;
+ RECT 638.130000 1154.380000 639.130000 1154.860000 ;
+ RECT 580.320000 1176.140000 581.420000 1176.620000 ;
+ RECT 580.320000 1181.580000 581.420000 1182.060000 ;
+ RECT 580.320000 1187.020000 581.420000 1187.500000 ;
+ RECT 580.320000 1192.460000 581.420000 1192.940000 ;
+ RECT 580.320000 1154.380000 581.420000 1154.860000 ;
+ RECT 580.320000 1159.820000 581.420000 1160.300000 ;
+ RECT 580.320000 1165.260000 581.420000 1165.740000 ;
+ RECT 580.320000 1170.700000 581.420000 1171.180000 ;
+ RECT 535.320000 1225.100000 536.420000 1225.580000 ;
+ RECT 535.320000 1230.540000 536.420000 1231.020000 ;
+ RECT 535.320000 1235.980000 536.420000 1236.460000 ;
+ RECT 535.320000 1241.420000 536.420000 1241.900000 ;
+ RECT 490.320000 1225.100000 491.420000 1225.580000 ;
+ RECT 490.320000 1230.540000 491.420000 1231.020000 ;
+ RECT 490.320000 1235.980000 491.420000 1236.460000 ;
+ RECT 490.320000 1241.420000 491.420000 1241.900000 ;
+ RECT 535.320000 1197.900000 536.420000 1198.380000 ;
+ RECT 535.320000 1203.340000 536.420000 1203.820000 ;
+ RECT 535.320000 1208.780000 536.420000 1209.260000 ;
+ RECT 535.320000 1214.220000 536.420000 1214.700000 ;
+ RECT 535.320000 1219.660000 536.420000 1220.140000 ;
+ RECT 490.320000 1197.900000 491.420000 1198.380000 ;
+ RECT 490.320000 1203.340000 491.420000 1203.820000 ;
+ RECT 490.320000 1208.780000 491.420000 1209.260000 ;
+ RECT 490.320000 1214.220000 491.420000 1214.700000 ;
+ RECT 490.320000 1219.660000 491.420000 1220.140000 ;
+ RECT 441.490000 1241.420000 442.490000 1241.900000 ;
+ RECT 445.155000 1241.420000 446.420000 1241.900000 ;
+ RECT 441.490000 1235.980000 442.490000 1236.460000 ;
+ RECT 445.155000 1235.980000 446.420000 1236.460000 ;
+ RECT 441.490000 1230.540000 442.490000 1231.020000 ;
+ RECT 445.155000 1230.540000 446.420000 1231.020000 ;
+ RECT 441.490000 1225.100000 442.490000 1225.580000 ;
+ RECT 445.155000 1225.100000 446.420000 1225.580000 ;
+ RECT 441.490000 1219.660000 442.490000 1220.140000 ;
+ RECT 445.155000 1219.660000 446.420000 1220.140000 ;
+ RECT 441.490000 1214.220000 442.490000 1214.700000 ;
+ RECT 445.155000 1214.220000 446.420000 1214.700000 ;
+ RECT 441.490000 1203.340000 442.490000 1203.820000 ;
+ RECT 445.155000 1203.340000 446.420000 1203.820000 ;
+ RECT 441.490000 1208.780000 442.490000 1209.260000 ;
+ RECT 445.155000 1208.780000 446.420000 1209.260000 ;
+ RECT 441.490000 1197.900000 442.490000 1198.380000 ;
+ RECT 445.155000 1197.900000 446.420000 1198.380000 ;
+ RECT 535.320000 1176.140000 536.420000 1176.620000 ;
+ RECT 535.320000 1181.580000 536.420000 1182.060000 ;
+ RECT 535.320000 1187.020000 536.420000 1187.500000 ;
+ RECT 535.320000 1192.460000 536.420000 1192.940000 ;
+ RECT 490.320000 1176.140000 491.420000 1176.620000 ;
+ RECT 490.320000 1181.580000 491.420000 1182.060000 ;
+ RECT 490.320000 1187.020000 491.420000 1187.500000 ;
+ RECT 490.320000 1192.460000 491.420000 1192.940000 ;
+ RECT 535.320000 1154.380000 536.420000 1154.860000 ;
+ RECT 535.320000 1159.820000 536.420000 1160.300000 ;
+ RECT 535.320000 1165.260000 536.420000 1165.740000 ;
+ RECT 535.320000 1170.700000 536.420000 1171.180000 ;
+ RECT 490.320000 1154.380000 491.420000 1154.860000 ;
+ RECT 490.320000 1159.820000 491.420000 1160.300000 ;
+ RECT 490.320000 1165.260000 491.420000 1165.740000 ;
+ RECT 490.320000 1170.700000 491.420000 1171.180000 ;
+ RECT 441.490000 1192.460000 442.490000 1192.940000 ;
+ RECT 445.155000 1192.460000 446.420000 1192.940000 ;
+ RECT 441.490000 1187.020000 442.490000 1187.500000 ;
+ RECT 445.155000 1187.020000 446.420000 1187.500000 ;
+ RECT 441.490000 1181.580000 442.490000 1182.060000 ;
+ RECT 445.155000 1181.580000 446.420000 1182.060000 ;
+ RECT 441.490000 1176.140000 442.490000 1176.620000 ;
+ RECT 445.155000 1176.140000 446.420000 1176.620000 ;
+ RECT 441.490000 1170.700000 442.490000 1171.180000 ;
+ RECT 445.155000 1170.700000 446.420000 1171.180000 ;
+ RECT 441.490000 1159.820000 442.490000 1160.300000 ;
+ RECT 445.155000 1159.820000 446.420000 1160.300000 ;
+ RECT 441.490000 1165.260000 442.490000 1165.740000 ;
+ RECT 445.155000 1165.260000 446.420000 1165.740000 ;
+ RECT 441.490000 1154.380000 442.490000 1154.860000 ;
+ RECT 445.155000 1154.380000 446.420000 1154.860000 ;
+ RECT 580.320000 1246.860000 581.420000 1247.340000 ;
+ RECT 625.320000 1246.860000 626.420000 1247.340000 ;
+ RECT 638.130000 1246.860000 639.130000 1247.340000 ;
+ RECT 490.320000 1246.860000 491.420000 1247.340000 ;
+ RECT 535.320000 1246.860000 536.420000 1247.340000 ;
+ RECT 441.490000 1246.860000 442.490000 1247.340000 ;
+ RECT 445.155000 1246.860000 446.420000 1247.340000 ;
+ RECT 440.260000 1343.620000 640.360000 1344.620000 ;
+ RECT 440.260000 1148.050000 640.360000 1149.050000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 1146.800000 442.490000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 1346.060000 442.490000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 1146.800000 639.130000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 1346.060000 639.130000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1148.050000 441.260000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1148.050000 640.360000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1343.620000 441.260000 1344.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1343.620000 640.360000 1344.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 1139.080000 446.420000 1139.560000 ;
+ RECT 445.155000 1128.200000 446.420000 1128.680000 ;
+ RECT 445.155000 1133.640000 446.420000 1134.120000 ;
+ RECT 445.155000 1122.760000 446.420000 1123.240000 ;
+ RECT 445.155000 1117.320000 446.420000 1117.800000 ;
+ RECT 445.155000 1111.880000 446.420000 1112.360000 ;
+ RECT 445.155000 1106.440000 446.420000 1106.920000 ;
+ RECT 445.155000 1101.000000 446.420000 1101.480000 ;
+ RECT 445.155000 1095.560000 446.420000 1096.040000 ;
+ RECT 445.155000 1084.680000 446.420000 1085.160000 ;
+ RECT 445.155000 1090.120000 446.420000 1090.600000 ;
+ RECT 445.155000 1079.240000 446.420000 1079.720000 ;
+ RECT 445.155000 1073.800000 446.420000 1074.280000 ;
+ RECT 445.155000 1068.360000 446.420000 1068.840000 ;
+ RECT 445.155000 1062.920000 446.420000 1063.400000 ;
+ RECT 445.155000 1057.480000 446.420000 1057.960000 ;
+ RECT 445.155000 1052.040000 446.420000 1052.520000 ;
+ RECT 445.155000 1041.160000 446.420000 1041.640000 ;
+ RECT 445.155000 1035.720000 446.420000 1036.200000 ;
+ RECT 445.155000 1030.280000 446.420000 1030.760000 ;
+ RECT 445.155000 1024.840000 446.420000 1025.320000 ;
+ RECT 445.155000 1019.400000 446.420000 1019.880000 ;
+ RECT 445.155000 1013.960000 446.420000 1014.440000 ;
+ RECT 445.155000 1003.080000 446.420000 1003.560000 ;
+ RECT 445.155000 1008.520000 446.420000 1009.000000 ;
+ RECT 445.155000 997.640000 446.420000 998.120000 ;
+ RECT 445.155000 992.200000 446.420000 992.680000 ;
+ RECT 445.155000 986.760000 446.420000 987.240000 ;
+ RECT 445.155000 981.320000 446.420000 981.800000 ;
+ RECT 445.155000 975.880000 446.420000 976.360000 ;
+ RECT 445.155000 970.440000 446.420000 970.920000 ;
+ RECT 445.155000 959.560000 446.420000 960.040000 ;
+ RECT 445.155000 965.000000 446.420000 965.480000 ;
+ RECT 445.155000 954.120000 446.420000 954.600000 ;
+ RECT 445.155000 1046.600000 446.420000 1047.080000 ;
+ RECT 625.320000 947.790000 626.420000 1144.360000 ;
+ RECT 580.320000 947.790000 581.420000 1144.360000 ;
+ RECT 638.130000 946.540000 639.130000 1146.800000 ;
+ RECT 535.320000 947.790000 536.420000 1144.360000 ;
+ RECT 490.320000 947.790000 491.420000 1144.360000 ;
+ RECT 445.320000 947.790000 446.420000 1144.360000 ;
+ RECT 441.490000 946.540000 442.490000 1146.800000 ;
+ LAYER met3 ;
+ RECT 625.320000 1139.080000 626.420000 1139.560000 ;
+ RECT 638.130000 1139.080000 639.130000 1139.560000 ;
+ RECT 638.130000 1128.200000 639.130000 1128.680000 ;
+ RECT 638.130000 1122.760000 639.130000 1123.240000 ;
+ RECT 638.130000 1133.640000 639.130000 1134.120000 ;
+ RECT 625.320000 1133.640000 626.420000 1134.120000 ;
+ RECT 625.320000 1128.200000 626.420000 1128.680000 ;
+ RECT 625.320000 1122.760000 626.420000 1123.240000 ;
+ RECT 625.320000 1111.880000 626.420000 1112.360000 ;
+ RECT 625.320000 1117.320000 626.420000 1117.800000 ;
+ RECT 638.130000 1111.880000 639.130000 1112.360000 ;
+ RECT 638.130000 1117.320000 639.130000 1117.800000 ;
+ RECT 625.320000 1101.000000 626.420000 1101.480000 ;
+ RECT 625.320000 1106.440000 626.420000 1106.920000 ;
+ RECT 638.130000 1101.000000 639.130000 1101.480000 ;
+ RECT 638.130000 1106.440000 639.130000 1106.920000 ;
+ RECT 580.320000 1122.760000 581.420000 1123.240000 ;
+ RECT 580.320000 1128.200000 581.420000 1128.680000 ;
+ RECT 580.320000 1133.640000 581.420000 1134.120000 ;
+ RECT 580.320000 1139.080000 581.420000 1139.560000 ;
+ RECT 580.320000 1106.440000 581.420000 1106.920000 ;
+ RECT 580.320000 1101.000000 581.420000 1101.480000 ;
+ RECT 580.320000 1111.880000 581.420000 1112.360000 ;
+ RECT 580.320000 1117.320000 581.420000 1117.800000 ;
+ RECT 638.130000 1090.120000 639.130000 1090.600000 ;
+ RECT 638.130000 1084.680000 639.130000 1085.160000 ;
+ RECT 638.130000 1095.560000 639.130000 1096.040000 ;
+ RECT 625.320000 1095.560000 626.420000 1096.040000 ;
+ RECT 625.320000 1090.120000 626.420000 1090.600000 ;
+ RECT 625.320000 1084.680000 626.420000 1085.160000 ;
+ RECT 625.320000 1073.800000 626.420000 1074.280000 ;
+ RECT 625.320000 1079.240000 626.420000 1079.720000 ;
+ RECT 638.130000 1073.800000 639.130000 1074.280000 ;
+ RECT 638.130000 1079.240000 639.130000 1079.720000 ;
+ RECT 638.130000 1062.920000 639.130000 1063.400000 ;
+ RECT 638.130000 1068.360000 639.130000 1068.840000 ;
+ RECT 625.320000 1068.360000 626.420000 1068.840000 ;
+ RECT 625.320000 1062.920000 626.420000 1063.400000 ;
+ RECT 625.320000 1052.040000 626.420000 1052.520000 ;
+ RECT 625.320000 1057.480000 626.420000 1057.960000 ;
+ RECT 638.130000 1052.040000 639.130000 1052.520000 ;
+ RECT 638.130000 1057.480000 639.130000 1057.960000 ;
+ RECT 580.320000 1073.800000 581.420000 1074.280000 ;
+ RECT 580.320000 1079.240000 581.420000 1079.720000 ;
+ RECT 580.320000 1084.680000 581.420000 1085.160000 ;
+ RECT 580.320000 1090.120000 581.420000 1090.600000 ;
+ RECT 580.320000 1095.560000 581.420000 1096.040000 ;
+ RECT 580.320000 1052.040000 581.420000 1052.520000 ;
+ RECT 580.320000 1057.480000 581.420000 1057.960000 ;
+ RECT 580.320000 1062.920000 581.420000 1063.400000 ;
+ RECT 580.320000 1068.360000 581.420000 1068.840000 ;
+ RECT 535.320000 1128.200000 536.420000 1128.680000 ;
+ RECT 535.320000 1122.760000 536.420000 1123.240000 ;
+ RECT 535.320000 1133.640000 536.420000 1134.120000 ;
+ RECT 535.320000 1139.080000 536.420000 1139.560000 ;
+ RECT 490.320000 1122.760000 491.420000 1123.240000 ;
+ RECT 490.320000 1128.200000 491.420000 1128.680000 ;
+ RECT 490.320000 1133.640000 491.420000 1134.120000 ;
+ RECT 490.320000 1139.080000 491.420000 1139.560000 ;
+ RECT 535.320000 1101.000000 536.420000 1101.480000 ;
+ RECT 535.320000 1106.440000 536.420000 1106.920000 ;
+ RECT 535.320000 1111.880000 536.420000 1112.360000 ;
+ RECT 535.320000 1117.320000 536.420000 1117.800000 ;
+ RECT 490.320000 1101.000000 491.420000 1101.480000 ;
+ RECT 490.320000 1106.440000 491.420000 1106.920000 ;
+ RECT 490.320000 1111.880000 491.420000 1112.360000 ;
+ RECT 490.320000 1117.320000 491.420000 1117.800000 ;
+ RECT 441.490000 1139.080000 442.490000 1139.560000 ;
+ RECT 445.155000 1139.080000 446.420000 1139.560000 ;
+ RECT 441.490000 1128.200000 442.490000 1128.680000 ;
+ RECT 445.155000 1128.200000 446.420000 1128.680000 ;
+ RECT 441.490000 1133.640000 442.490000 1134.120000 ;
+ RECT 445.155000 1133.640000 446.420000 1134.120000 ;
+ RECT 441.490000 1122.760000 442.490000 1123.240000 ;
+ RECT 445.155000 1122.760000 446.420000 1123.240000 ;
+ RECT 441.490000 1117.320000 442.490000 1117.800000 ;
+ RECT 445.155000 1117.320000 446.420000 1117.800000 ;
+ RECT 441.490000 1111.880000 442.490000 1112.360000 ;
+ RECT 445.155000 1111.880000 446.420000 1112.360000 ;
+ RECT 441.490000 1106.440000 442.490000 1106.920000 ;
+ RECT 445.155000 1106.440000 446.420000 1106.920000 ;
+ RECT 441.490000 1101.000000 442.490000 1101.480000 ;
+ RECT 445.155000 1101.000000 446.420000 1101.480000 ;
+ RECT 535.320000 1073.800000 536.420000 1074.280000 ;
+ RECT 535.320000 1079.240000 536.420000 1079.720000 ;
+ RECT 535.320000 1084.680000 536.420000 1085.160000 ;
+ RECT 535.320000 1090.120000 536.420000 1090.600000 ;
+ RECT 535.320000 1095.560000 536.420000 1096.040000 ;
+ RECT 490.320000 1073.800000 491.420000 1074.280000 ;
+ RECT 490.320000 1079.240000 491.420000 1079.720000 ;
+ RECT 490.320000 1084.680000 491.420000 1085.160000 ;
+ RECT 490.320000 1090.120000 491.420000 1090.600000 ;
+ RECT 490.320000 1095.560000 491.420000 1096.040000 ;
+ RECT 535.320000 1052.040000 536.420000 1052.520000 ;
+ RECT 535.320000 1057.480000 536.420000 1057.960000 ;
+ RECT 535.320000 1062.920000 536.420000 1063.400000 ;
+ RECT 535.320000 1068.360000 536.420000 1068.840000 ;
+ RECT 490.320000 1052.040000 491.420000 1052.520000 ;
+ RECT 490.320000 1057.480000 491.420000 1057.960000 ;
+ RECT 490.320000 1062.920000 491.420000 1063.400000 ;
+ RECT 490.320000 1068.360000 491.420000 1068.840000 ;
+ RECT 441.490000 1095.560000 442.490000 1096.040000 ;
+ RECT 445.155000 1095.560000 446.420000 1096.040000 ;
+ RECT 441.490000 1084.680000 442.490000 1085.160000 ;
+ RECT 445.155000 1084.680000 446.420000 1085.160000 ;
+ RECT 441.490000 1090.120000 442.490000 1090.600000 ;
+ RECT 445.155000 1090.120000 446.420000 1090.600000 ;
+ RECT 441.490000 1079.240000 442.490000 1079.720000 ;
+ RECT 445.155000 1079.240000 446.420000 1079.720000 ;
+ RECT 441.490000 1073.800000 442.490000 1074.280000 ;
+ RECT 445.155000 1073.800000 446.420000 1074.280000 ;
+ RECT 441.490000 1068.360000 442.490000 1068.840000 ;
+ RECT 445.155000 1068.360000 446.420000 1068.840000 ;
+ RECT 441.490000 1062.920000 442.490000 1063.400000 ;
+ RECT 445.155000 1062.920000 446.420000 1063.400000 ;
+ RECT 441.490000 1057.480000 442.490000 1057.960000 ;
+ RECT 445.155000 1057.480000 446.420000 1057.960000 ;
+ RECT 441.490000 1052.040000 442.490000 1052.520000 ;
+ RECT 445.155000 1052.040000 446.420000 1052.520000 ;
+ RECT 625.320000 1035.720000 626.420000 1036.200000 ;
+ RECT 625.320000 1041.160000 626.420000 1041.640000 ;
+ RECT 638.130000 1035.720000 639.130000 1036.200000 ;
+ RECT 638.130000 1041.160000 639.130000 1041.640000 ;
+ RECT 638.130000 1024.840000 639.130000 1025.320000 ;
+ RECT 638.130000 1030.280000 639.130000 1030.760000 ;
+ RECT 625.320000 1030.280000 626.420000 1030.760000 ;
+ RECT 625.320000 1024.840000 626.420000 1025.320000 ;
+ RECT 625.320000 1013.960000 626.420000 1014.440000 ;
+ RECT 625.320000 1019.400000 626.420000 1019.880000 ;
+ RECT 638.130000 1013.960000 639.130000 1014.440000 ;
+ RECT 638.130000 1019.400000 639.130000 1019.880000 ;
+ RECT 638.130000 1003.080000 639.130000 1003.560000 ;
+ RECT 638.130000 997.640000 639.130000 998.120000 ;
+ RECT 638.130000 1008.520000 639.130000 1009.000000 ;
+ RECT 625.320000 1008.520000 626.420000 1009.000000 ;
+ RECT 625.320000 1003.080000 626.420000 1003.560000 ;
+ RECT 625.320000 997.640000 626.420000 998.120000 ;
+ RECT 580.320000 1024.840000 581.420000 1025.320000 ;
+ RECT 580.320000 1030.280000 581.420000 1030.760000 ;
+ RECT 580.320000 1035.720000 581.420000 1036.200000 ;
+ RECT 580.320000 1041.160000 581.420000 1041.640000 ;
+ RECT 580.320000 997.640000 581.420000 998.120000 ;
+ RECT 580.320000 1003.080000 581.420000 1003.560000 ;
+ RECT 580.320000 1008.520000 581.420000 1009.000000 ;
+ RECT 580.320000 1013.960000 581.420000 1014.440000 ;
+ RECT 580.320000 1019.400000 581.420000 1019.880000 ;
+ RECT 625.320000 986.760000 626.420000 987.240000 ;
+ RECT 625.320000 992.200000 626.420000 992.680000 ;
+ RECT 638.130000 986.760000 639.130000 987.240000 ;
+ RECT 638.130000 992.200000 639.130000 992.680000 ;
+ RECT 625.320000 975.880000 626.420000 976.360000 ;
+ RECT 625.320000 981.320000 626.420000 981.800000 ;
+ RECT 638.130000 975.880000 639.130000 976.360000 ;
+ RECT 638.130000 981.320000 639.130000 981.800000 ;
+ RECT 638.130000 965.000000 639.130000 965.480000 ;
+ RECT 638.130000 959.560000 639.130000 960.040000 ;
+ RECT 638.130000 970.440000 639.130000 970.920000 ;
+ RECT 625.320000 970.440000 626.420000 970.920000 ;
+ RECT 625.320000 965.000000 626.420000 965.480000 ;
+ RECT 625.320000 959.560000 626.420000 960.040000 ;
+ RECT 625.320000 954.120000 626.420000 954.600000 ;
+ RECT 638.130000 954.120000 639.130000 954.600000 ;
+ RECT 580.320000 975.880000 581.420000 976.360000 ;
+ RECT 580.320000 981.320000 581.420000 981.800000 ;
+ RECT 580.320000 986.760000 581.420000 987.240000 ;
+ RECT 580.320000 992.200000 581.420000 992.680000 ;
+ RECT 580.320000 954.120000 581.420000 954.600000 ;
+ RECT 580.320000 959.560000 581.420000 960.040000 ;
+ RECT 580.320000 965.000000 581.420000 965.480000 ;
+ RECT 580.320000 970.440000 581.420000 970.920000 ;
+ RECT 535.320000 1024.840000 536.420000 1025.320000 ;
+ RECT 535.320000 1030.280000 536.420000 1030.760000 ;
+ RECT 535.320000 1035.720000 536.420000 1036.200000 ;
+ RECT 535.320000 1041.160000 536.420000 1041.640000 ;
+ RECT 490.320000 1024.840000 491.420000 1025.320000 ;
+ RECT 490.320000 1030.280000 491.420000 1030.760000 ;
+ RECT 490.320000 1035.720000 491.420000 1036.200000 ;
+ RECT 490.320000 1041.160000 491.420000 1041.640000 ;
+ RECT 535.320000 997.640000 536.420000 998.120000 ;
+ RECT 535.320000 1003.080000 536.420000 1003.560000 ;
+ RECT 535.320000 1008.520000 536.420000 1009.000000 ;
+ RECT 535.320000 1013.960000 536.420000 1014.440000 ;
+ RECT 535.320000 1019.400000 536.420000 1019.880000 ;
+ RECT 490.320000 997.640000 491.420000 998.120000 ;
+ RECT 490.320000 1003.080000 491.420000 1003.560000 ;
+ RECT 490.320000 1008.520000 491.420000 1009.000000 ;
+ RECT 490.320000 1013.960000 491.420000 1014.440000 ;
+ RECT 490.320000 1019.400000 491.420000 1019.880000 ;
+ RECT 441.490000 1041.160000 442.490000 1041.640000 ;
+ RECT 445.155000 1041.160000 446.420000 1041.640000 ;
+ RECT 441.490000 1035.720000 442.490000 1036.200000 ;
+ RECT 445.155000 1035.720000 446.420000 1036.200000 ;
+ RECT 441.490000 1030.280000 442.490000 1030.760000 ;
+ RECT 445.155000 1030.280000 446.420000 1030.760000 ;
+ RECT 441.490000 1024.840000 442.490000 1025.320000 ;
+ RECT 445.155000 1024.840000 446.420000 1025.320000 ;
+ RECT 441.490000 1019.400000 442.490000 1019.880000 ;
+ RECT 445.155000 1019.400000 446.420000 1019.880000 ;
+ RECT 441.490000 1013.960000 442.490000 1014.440000 ;
+ RECT 445.155000 1013.960000 446.420000 1014.440000 ;
+ RECT 441.490000 1003.080000 442.490000 1003.560000 ;
+ RECT 445.155000 1003.080000 446.420000 1003.560000 ;
+ RECT 441.490000 1008.520000 442.490000 1009.000000 ;
+ RECT 445.155000 1008.520000 446.420000 1009.000000 ;
+ RECT 441.490000 997.640000 442.490000 998.120000 ;
+ RECT 445.155000 997.640000 446.420000 998.120000 ;
+ RECT 535.320000 975.880000 536.420000 976.360000 ;
+ RECT 535.320000 981.320000 536.420000 981.800000 ;
+ RECT 535.320000 986.760000 536.420000 987.240000 ;
+ RECT 535.320000 992.200000 536.420000 992.680000 ;
+ RECT 490.320000 975.880000 491.420000 976.360000 ;
+ RECT 490.320000 981.320000 491.420000 981.800000 ;
+ RECT 490.320000 986.760000 491.420000 987.240000 ;
+ RECT 490.320000 992.200000 491.420000 992.680000 ;
+ RECT 535.320000 954.120000 536.420000 954.600000 ;
+ RECT 535.320000 959.560000 536.420000 960.040000 ;
+ RECT 535.320000 965.000000 536.420000 965.480000 ;
+ RECT 535.320000 970.440000 536.420000 970.920000 ;
+ RECT 490.320000 954.120000 491.420000 954.600000 ;
+ RECT 490.320000 959.560000 491.420000 960.040000 ;
+ RECT 490.320000 965.000000 491.420000 965.480000 ;
+ RECT 490.320000 970.440000 491.420000 970.920000 ;
+ RECT 441.490000 992.200000 442.490000 992.680000 ;
+ RECT 445.155000 992.200000 446.420000 992.680000 ;
+ RECT 441.490000 986.760000 442.490000 987.240000 ;
+ RECT 445.155000 986.760000 446.420000 987.240000 ;
+ RECT 441.490000 981.320000 442.490000 981.800000 ;
+ RECT 445.155000 981.320000 446.420000 981.800000 ;
+ RECT 441.490000 975.880000 442.490000 976.360000 ;
+ RECT 445.155000 975.880000 446.420000 976.360000 ;
+ RECT 441.490000 970.440000 442.490000 970.920000 ;
+ RECT 445.155000 970.440000 446.420000 970.920000 ;
+ RECT 441.490000 959.560000 442.490000 960.040000 ;
+ RECT 445.155000 959.560000 446.420000 960.040000 ;
+ RECT 441.490000 965.000000 442.490000 965.480000 ;
+ RECT 445.155000 965.000000 446.420000 965.480000 ;
+ RECT 441.490000 954.120000 442.490000 954.600000 ;
+ RECT 445.155000 954.120000 446.420000 954.600000 ;
+ RECT 580.320000 1046.600000 581.420000 1047.080000 ;
+ RECT 625.320000 1046.600000 626.420000 1047.080000 ;
+ RECT 638.130000 1046.600000 639.130000 1047.080000 ;
+ RECT 490.320000 1046.600000 491.420000 1047.080000 ;
+ RECT 535.320000 1046.600000 536.420000 1047.080000 ;
+ RECT 441.490000 1046.600000 442.490000 1047.080000 ;
+ RECT 445.155000 1046.600000 446.420000 1047.080000 ;
+ RECT 440.260000 1143.360000 640.360000 1144.360000 ;
+ RECT 440.260000 947.790000 640.360000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 946.540000 442.490000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 1145.800000 442.490000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 946.540000 639.130000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 1145.800000 639.130000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 947.790000 441.260000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 947.790000 640.360000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1143.360000 441.260000 1144.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1143.360000 640.360000 1144.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 938.820000 446.420000 939.300000 ;
+ RECT 445.155000 927.940000 446.420000 928.420000 ;
+ RECT 445.155000 933.380000 446.420000 933.860000 ;
+ RECT 445.155000 922.500000 446.420000 922.980000 ;
+ RECT 445.155000 917.060000 446.420000 917.540000 ;
+ RECT 445.155000 911.620000 446.420000 912.100000 ;
+ RECT 445.155000 906.180000 446.420000 906.660000 ;
+ RECT 445.155000 900.740000 446.420000 901.220000 ;
+ RECT 445.155000 895.300000 446.420000 895.780000 ;
+ RECT 445.155000 884.420000 446.420000 884.900000 ;
+ RECT 445.155000 889.860000 446.420000 890.340000 ;
+ RECT 445.155000 878.980000 446.420000 879.460000 ;
+ RECT 445.155000 873.540000 446.420000 874.020000 ;
+ RECT 445.155000 868.100000 446.420000 868.580000 ;
+ RECT 445.155000 862.660000 446.420000 863.140000 ;
+ RECT 445.155000 857.220000 446.420000 857.700000 ;
+ RECT 445.155000 851.780000 446.420000 852.260000 ;
+ RECT 445.155000 840.900000 446.420000 841.380000 ;
+ RECT 445.155000 835.460000 446.420000 835.940000 ;
+ RECT 445.155000 830.020000 446.420000 830.500000 ;
+ RECT 445.155000 824.580000 446.420000 825.060000 ;
+ RECT 445.155000 819.140000 446.420000 819.620000 ;
+ RECT 445.155000 813.700000 446.420000 814.180000 ;
+ RECT 445.155000 802.820000 446.420000 803.300000 ;
+ RECT 445.155000 808.260000 446.420000 808.740000 ;
+ RECT 445.155000 797.380000 446.420000 797.860000 ;
+ RECT 445.155000 791.940000 446.420000 792.420000 ;
+ RECT 445.155000 786.500000 446.420000 786.980000 ;
+ RECT 445.155000 781.060000 446.420000 781.540000 ;
+ RECT 445.155000 775.620000 446.420000 776.100000 ;
+ RECT 445.155000 770.180000 446.420000 770.660000 ;
+ RECT 445.155000 759.300000 446.420000 759.780000 ;
+ RECT 445.155000 764.740000 446.420000 765.220000 ;
+ RECT 445.155000 753.860000 446.420000 754.340000 ;
+ RECT 445.155000 846.340000 446.420000 846.820000 ;
+ RECT 625.320000 747.530000 626.420000 944.100000 ;
+ RECT 580.320000 747.530000 581.420000 944.100000 ;
+ RECT 638.130000 746.280000 639.130000 946.540000 ;
+ RECT 535.320000 747.530000 536.420000 944.100000 ;
+ RECT 490.320000 747.530000 491.420000 944.100000 ;
+ RECT 445.320000 747.530000 446.420000 944.100000 ;
+ RECT 441.490000 746.280000 442.490000 946.540000 ;
+ LAYER met3 ;
+ RECT 625.320000 938.820000 626.420000 939.300000 ;
+ RECT 638.130000 938.820000 639.130000 939.300000 ;
+ RECT 638.130000 927.940000 639.130000 928.420000 ;
+ RECT 638.130000 922.500000 639.130000 922.980000 ;
+ RECT 638.130000 933.380000 639.130000 933.860000 ;
+ RECT 625.320000 933.380000 626.420000 933.860000 ;
+ RECT 625.320000 927.940000 626.420000 928.420000 ;
+ RECT 625.320000 922.500000 626.420000 922.980000 ;
+ RECT 625.320000 911.620000 626.420000 912.100000 ;
+ RECT 625.320000 917.060000 626.420000 917.540000 ;
+ RECT 638.130000 911.620000 639.130000 912.100000 ;
+ RECT 638.130000 917.060000 639.130000 917.540000 ;
+ RECT 625.320000 900.740000 626.420000 901.220000 ;
+ RECT 625.320000 906.180000 626.420000 906.660000 ;
+ RECT 638.130000 900.740000 639.130000 901.220000 ;
+ RECT 638.130000 906.180000 639.130000 906.660000 ;
+ RECT 580.320000 922.500000 581.420000 922.980000 ;
+ RECT 580.320000 927.940000 581.420000 928.420000 ;
+ RECT 580.320000 933.380000 581.420000 933.860000 ;
+ RECT 580.320000 938.820000 581.420000 939.300000 ;
+ RECT 580.320000 906.180000 581.420000 906.660000 ;
+ RECT 580.320000 900.740000 581.420000 901.220000 ;
+ RECT 580.320000 911.620000 581.420000 912.100000 ;
+ RECT 580.320000 917.060000 581.420000 917.540000 ;
+ RECT 638.130000 889.860000 639.130000 890.340000 ;
+ RECT 638.130000 884.420000 639.130000 884.900000 ;
+ RECT 638.130000 895.300000 639.130000 895.780000 ;
+ RECT 625.320000 895.300000 626.420000 895.780000 ;
+ RECT 625.320000 889.860000 626.420000 890.340000 ;
+ RECT 625.320000 884.420000 626.420000 884.900000 ;
+ RECT 625.320000 873.540000 626.420000 874.020000 ;
+ RECT 625.320000 878.980000 626.420000 879.460000 ;
+ RECT 638.130000 873.540000 639.130000 874.020000 ;
+ RECT 638.130000 878.980000 639.130000 879.460000 ;
+ RECT 638.130000 862.660000 639.130000 863.140000 ;
+ RECT 638.130000 868.100000 639.130000 868.580000 ;
+ RECT 625.320000 868.100000 626.420000 868.580000 ;
+ RECT 625.320000 862.660000 626.420000 863.140000 ;
+ RECT 625.320000 851.780000 626.420000 852.260000 ;
+ RECT 625.320000 857.220000 626.420000 857.700000 ;
+ RECT 638.130000 851.780000 639.130000 852.260000 ;
+ RECT 638.130000 857.220000 639.130000 857.700000 ;
+ RECT 580.320000 873.540000 581.420000 874.020000 ;
+ RECT 580.320000 878.980000 581.420000 879.460000 ;
+ RECT 580.320000 884.420000 581.420000 884.900000 ;
+ RECT 580.320000 889.860000 581.420000 890.340000 ;
+ RECT 580.320000 895.300000 581.420000 895.780000 ;
+ RECT 580.320000 851.780000 581.420000 852.260000 ;
+ RECT 580.320000 857.220000 581.420000 857.700000 ;
+ RECT 580.320000 862.660000 581.420000 863.140000 ;
+ RECT 580.320000 868.100000 581.420000 868.580000 ;
+ RECT 535.320000 927.940000 536.420000 928.420000 ;
+ RECT 535.320000 922.500000 536.420000 922.980000 ;
+ RECT 535.320000 933.380000 536.420000 933.860000 ;
+ RECT 535.320000 938.820000 536.420000 939.300000 ;
+ RECT 490.320000 922.500000 491.420000 922.980000 ;
+ RECT 490.320000 927.940000 491.420000 928.420000 ;
+ RECT 490.320000 933.380000 491.420000 933.860000 ;
+ RECT 490.320000 938.820000 491.420000 939.300000 ;
+ RECT 535.320000 900.740000 536.420000 901.220000 ;
+ RECT 535.320000 906.180000 536.420000 906.660000 ;
+ RECT 535.320000 911.620000 536.420000 912.100000 ;
+ RECT 535.320000 917.060000 536.420000 917.540000 ;
+ RECT 490.320000 900.740000 491.420000 901.220000 ;
+ RECT 490.320000 906.180000 491.420000 906.660000 ;
+ RECT 490.320000 911.620000 491.420000 912.100000 ;
+ RECT 490.320000 917.060000 491.420000 917.540000 ;
+ RECT 441.490000 938.820000 442.490000 939.300000 ;
+ RECT 445.155000 938.820000 446.420000 939.300000 ;
+ RECT 441.490000 927.940000 442.490000 928.420000 ;
+ RECT 445.155000 927.940000 446.420000 928.420000 ;
+ RECT 441.490000 933.380000 442.490000 933.860000 ;
+ RECT 445.155000 933.380000 446.420000 933.860000 ;
+ RECT 441.490000 922.500000 442.490000 922.980000 ;
+ RECT 445.155000 922.500000 446.420000 922.980000 ;
+ RECT 441.490000 917.060000 442.490000 917.540000 ;
+ RECT 445.155000 917.060000 446.420000 917.540000 ;
+ RECT 441.490000 911.620000 442.490000 912.100000 ;
+ RECT 445.155000 911.620000 446.420000 912.100000 ;
+ RECT 441.490000 906.180000 442.490000 906.660000 ;
+ RECT 445.155000 906.180000 446.420000 906.660000 ;
+ RECT 441.490000 900.740000 442.490000 901.220000 ;
+ RECT 445.155000 900.740000 446.420000 901.220000 ;
+ RECT 535.320000 873.540000 536.420000 874.020000 ;
+ RECT 535.320000 878.980000 536.420000 879.460000 ;
+ RECT 535.320000 884.420000 536.420000 884.900000 ;
+ RECT 535.320000 889.860000 536.420000 890.340000 ;
+ RECT 535.320000 895.300000 536.420000 895.780000 ;
+ RECT 490.320000 873.540000 491.420000 874.020000 ;
+ RECT 490.320000 878.980000 491.420000 879.460000 ;
+ RECT 490.320000 884.420000 491.420000 884.900000 ;
+ RECT 490.320000 889.860000 491.420000 890.340000 ;
+ RECT 490.320000 895.300000 491.420000 895.780000 ;
+ RECT 535.320000 851.780000 536.420000 852.260000 ;
+ RECT 535.320000 857.220000 536.420000 857.700000 ;
+ RECT 535.320000 862.660000 536.420000 863.140000 ;
+ RECT 535.320000 868.100000 536.420000 868.580000 ;
+ RECT 490.320000 851.780000 491.420000 852.260000 ;
+ RECT 490.320000 857.220000 491.420000 857.700000 ;
+ RECT 490.320000 862.660000 491.420000 863.140000 ;
+ RECT 490.320000 868.100000 491.420000 868.580000 ;
+ RECT 441.490000 895.300000 442.490000 895.780000 ;
+ RECT 445.155000 895.300000 446.420000 895.780000 ;
+ RECT 441.490000 884.420000 442.490000 884.900000 ;
+ RECT 445.155000 884.420000 446.420000 884.900000 ;
+ RECT 441.490000 889.860000 442.490000 890.340000 ;
+ RECT 445.155000 889.860000 446.420000 890.340000 ;
+ RECT 441.490000 878.980000 442.490000 879.460000 ;
+ RECT 445.155000 878.980000 446.420000 879.460000 ;
+ RECT 441.490000 873.540000 442.490000 874.020000 ;
+ RECT 445.155000 873.540000 446.420000 874.020000 ;
+ RECT 441.490000 868.100000 442.490000 868.580000 ;
+ RECT 445.155000 868.100000 446.420000 868.580000 ;
+ RECT 441.490000 862.660000 442.490000 863.140000 ;
+ RECT 445.155000 862.660000 446.420000 863.140000 ;
+ RECT 441.490000 857.220000 442.490000 857.700000 ;
+ RECT 445.155000 857.220000 446.420000 857.700000 ;
+ RECT 441.490000 851.780000 442.490000 852.260000 ;
+ RECT 445.155000 851.780000 446.420000 852.260000 ;
+ RECT 625.320000 835.460000 626.420000 835.940000 ;
+ RECT 625.320000 840.900000 626.420000 841.380000 ;
+ RECT 638.130000 835.460000 639.130000 835.940000 ;
+ RECT 638.130000 840.900000 639.130000 841.380000 ;
+ RECT 638.130000 824.580000 639.130000 825.060000 ;
+ RECT 638.130000 830.020000 639.130000 830.500000 ;
+ RECT 625.320000 830.020000 626.420000 830.500000 ;
+ RECT 625.320000 824.580000 626.420000 825.060000 ;
+ RECT 625.320000 813.700000 626.420000 814.180000 ;
+ RECT 625.320000 819.140000 626.420000 819.620000 ;
+ RECT 638.130000 813.700000 639.130000 814.180000 ;
+ RECT 638.130000 819.140000 639.130000 819.620000 ;
+ RECT 638.130000 802.820000 639.130000 803.300000 ;
+ RECT 638.130000 797.380000 639.130000 797.860000 ;
+ RECT 638.130000 808.260000 639.130000 808.740000 ;
+ RECT 625.320000 808.260000 626.420000 808.740000 ;
+ RECT 625.320000 802.820000 626.420000 803.300000 ;
+ RECT 625.320000 797.380000 626.420000 797.860000 ;
+ RECT 580.320000 824.580000 581.420000 825.060000 ;
+ RECT 580.320000 830.020000 581.420000 830.500000 ;
+ RECT 580.320000 835.460000 581.420000 835.940000 ;
+ RECT 580.320000 840.900000 581.420000 841.380000 ;
+ RECT 580.320000 797.380000 581.420000 797.860000 ;
+ RECT 580.320000 802.820000 581.420000 803.300000 ;
+ RECT 580.320000 808.260000 581.420000 808.740000 ;
+ RECT 580.320000 813.700000 581.420000 814.180000 ;
+ RECT 580.320000 819.140000 581.420000 819.620000 ;
+ RECT 625.320000 786.500000 626.420000 786.980000 ;
+ RECT 625.320000 791.940000 626.420000 792.420000 ;
+ RECT 638.130000 786.500000 639.130000 786.980000 ;
+ RECT 638.130000 791.940000 639.130000 792.420000 ;
+ RECT 625.320000 775.620000 626.420000 776.100000 ;
+ RECT 625.320000 781.060000 626.420000 781.540000 ;
+ RECT 638.130000 775.620000 639.130000 776.100000 ;
+ RECT 638.130000 781.060000 639.130000 781.540000 ;
+ RECT 638.130000 764.740000 639.130000 765.220000 ;
+ RECT 638.130000 759.300000 639.130000 759.780000 ;
+ RECT 638.130000 770.180000 639.130000 770.660000 ;
+ RECT 625.320000 770.180000 626.420000 770.660000 ;
+ RECT 625.320000 764.740000 626.420000 765.220000 ;
+ RECT 625.320000 759.300000 626.420000 759.780000 ;
+ RECT 625.320000 753.860000 626.420000 754.340000 ;
+ RECT 638.130000 753.860000 639.130000 754.340000 ;
+ RECT 580.320000 775.620000 581.420000 776.100000 ;
+ RECT 580.320000 781.060000 581.420000 781.540000 ;
+ RECT 580.320000 786.500000 581.420000 786.980000 ;
+ RECT 580.320000 791.940000 581.420000 792.420000 ;
+ RECT 580.320000 753.860000 581.420000 754.340000 ;
+ RECT 580.320000 759.300000 581.420000 759.780000 ;
+ RECT 580.320000 764.740000 581.420000 765.220000 ;
+ RECT 580.320000 770.180000 581.420000 770.660000 ;
+ RECT 535.320000 824.580000 536.420000 825.060000 ;
+ RECT 535.320000 830.020000 536.420000 830.500000 ;
+ RECT 535.320000 835.460000 536.420000 835.940000 ;
+ RECT 535.320000 840.900000 536.420000 841.380000 ;
+ RECT 490.320000 824.580000 491.420000 825.060000 ;
+ RECT 490.320000 830.020000 491.420000 830.500000 ;
+ RECT 490.320000 835.460000 491.420000 835.940000 ;
+ RECT 490.320000 840.900000 491.420000 841.380000 ;
+ RECT 535.320000 797.380000 536.420000 797.860000 ;
+ RECT 535.320000 802.820000 536.420000 803.300000 ;
+ RECT 535.320000 808.260000 536.420000 808.740000 ;
+ RECT 535.320000 813.700000 536.420000 814.180000 ;
+ RECT 535.320000 819.140000 536.420000 819.620000 ;
+ RECT 490.320000 797.380000 491.420000 797.860000 ;
+ RECT 490.320000 802.820000 491.420000 803.300000 ;
+ RECT 490.320000 808.260000 491.420000 808.740000 ;
+ RECT 490.320000 813.700000 491.420000 814.180000 ;
+ RECT 490.320000 819.140000 491.420000 819.620000 ;
+ RECT 441.490000 840.900000 442.490000 841.380000 ;
+ RECT 445.155000 840.900000 446.420000 841.380000 ;
+ RECT 441.490000 835.460000 442.490000 835.940000 ;
+ RECT 445.155000 835.460000 446.420000 835.940000 ;
+ RECT 441.490000 830.020000 442.490000 830.500000 ;
+ RECT 445.155000 830.020000 446.420000 830.500000 ;
+ RECT 441.490000 824.580000 442.490000 825.060000 ;
+ RECT 445.155000 824.580000 446.420000 825.060000 ;
+ RECT 441.490000 819.140000 442.490000 819.620000 ;
+ RECT 445.155000 819.140000 446.420000 819.620000 ;
+ RECT 441.490000 813.700000 442.490000 814.180000 ;
+ RECT 445.155000 813.700000 446.420000 814.180000 ;
+ RECT 441.490000 802.820000 442.490000 803.300000 ;
+ RECT 445.155000 802.820000 446.420000 803.300000 ;
+ RECT 441.490000 808.260000 442.490000 808.740000 ;
+ RECT 445.155000 808.260000 446.420000 808.740000 ;
+ RECT 441.490000 797.380000 442.490000 797.860000 ;
+ RECT 445.155000 797.380000 446.420000 797.860000 ;
+ RECT 535.320000 775.620000 536.420000 776.100000 ;
+ RECT 535.320000 781.060000 536.420000 781.540000 ;
+ RECT 535.320000 786.500000 536.420000 786.980000 ;
+ RECT 535.320000 791.940000 536.420000 792.420000 ;
+ RECT 490.320000 775.620000 491.420000 776.100000 ;
+ RECT 490.320000 781.060000 491.420000 781.540000 ;
+ RECT 490.320000 786.500000 491.420000 786.980000 ;
+ RECT 490.320000 791.940000 491.420000 792.420000 ;
+ RECT 535.320000 753.860000 536.420000 754.340000 ;
+ RECT 535.320000 759.300000 536.420000 759.780000 ;
+ RECT 535.320000 764.740000 536.420000 765.220000 ;
+ RECT 535.320000 770.180000 536.420000 770.660000 ;
+ RECT 490.320000 753.860000 491.420000 754.340000 ;
+ RECT 490.320000 759.300000 491.420000 759.780000 ;
+ RECT 490.320000 764.740000 491.420000 765.220000 ;
+ RECT 490.320000 770.180000 491.420000 770.660000 ;
+ RECT 441.490000 791.940000 442.490000 792.420000 ;
+ RECT 445.155000 791.940000 446.420000 792.420000 ;
+ RECT 441.490000 786.500000 442.490000 786.980000 ;
+ RECT 445.155000 786.500000 446.420000 786.980000 ;
+ RECT 441.490000 781.060000 442.490000 781.540000 ;
+ RECT 445.155000 781.060000 446.420000 781.540000 ;
+ RECT 441.490000 775.620000 442.490000 776.100000 ;
+ RECT 445.155000 775.620000 446.420000 776.100000 ;
+ RECT 441.490000 770.180000 442.490000 770.660000 ;
+ RECT 445.155000 770.180000 446.420000 770.660000 ;
+ RECT 441.490000 759.300000 442.490000 759.780000 ;
+ RECT 445.155000 759.300000 446.420000 759.780000 ;
+ RECT 441.490000 764.740000 442.490000 765.220000 ;
+ RECT 445.155000 764.740000 446.420000 765.220000 ;
+ RECT 441.490000 753.860000 442.490000 754.340000 ;
+ RECT 445.155000 753.860000 446.420000 754.340000 ;
+ RECT 580.320000 846.340000 581.420000 846.820000 ;
+ RECT 625.320000 846.340000 626.420000 846.820000 ;
+ RECT 638.130000 846.340000 639.130000 846.820000 ;
+ RECT 490.320000 846.340000 491.420000 846.820000 ;
+ RECT 535.320000 846.340000 536.420000 846.820000 ;
+ RECT 441.490000 846.340000 442.490000 846.820000 ;
+ RECT 445.155000 846.340000 446.420000 846.820000 ;
+ RECT 440.260000 943.100000 640.360000 944.100000 ;
+ RECT 440.260000 747.530000 640.360000 748.530000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 746.280000 442.490000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 945.540000 442.490000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 746.280000 639.130000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 945.540000 639.130000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 747.530000 441.260000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 747.530000 640.360000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 943.100000 441.260000 944.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 943.100000 640.360000 944.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 738.560000 446.420000 739.040000 ;
+ RECT 445.155000 727.680000 446.420000 728.160000 ;
+ RECT 445.155000 733.120000 446.420000 733.600000 ;
+ RECT 445.155000 722.240000 446.420000 722.720000 ;
+ RECT 445.155000 716.800000 446.420000 717.280000 ;
+ RECT 445.155000 711.360000 446.420000 711.840000 ;
+ RECT 445.155000 705.920000 446.420000 706.400000 ;
+ RECT 445.155000 700.480000 446.420000 700.960000 ;
+ RECT 445.155000 695.040000 446.420000 695.520000 ;
+ RECT 445.155000 684.160000 446.420000 684.640000 ;
+ RECT 445.155000 689.600000 446.420000 690.080000 ;
+ RECT 445.155000 678.720000 446.420000 679.200000 ;
+ RECT 445.155000 673.280000 446.420000 673.760000 ;
+ RECT 445.155000 667.840000 446.420000 668.320000 ;
+ RECT 445.155000 662.400000 446.420000 662.880000 ;
+ RECT 445.155000 656.960000 446.420000 657.440000 ;
+ RECT 445.155000 651.520000 446.420000 652.000000 ;
+ RECT 445.155000 640.640000 446.420000 641.120000 ;
+ RECT 445.155000 635.200000 446.420000 635.680000 ;
+ RECT 445.155000 629.760000 446.420000 630.240000 ;
+ RECT 445.155000 624.320000 446.420000 624.800000 ;
+ RECT 445.155000 618.880000 446.420000 619.360000 ;
+ RECT 445.155000 613.440000 446.420000 613.920000 ;
+ RECT 445.155000 602.560000 446.420000 603.040000 ;
+ RECT 445.155000 608.000000 446.420000 608.480000 ;
+ RECT 445.155000 597.120000 446.420000 597.600000 ;
+ RECT 445.155000 591.680000 446.420000 592.160000 ;
+ RECT 445.155000 586.240000 446.420000 586.720000 ;
+ RECT 445.155000 580.800000 446.420000 581.280000 ;
+ RECT 445.155000 575.360000 446.420000 575.840000 ;
+ RECT 445.155000 569.920000 446.420000 570.400000 ;
+ RECT 445.155000 559.040000 446.420000 559.520000 ;
+ RECT 445.155000 564.480000 446.420000 564.960000 ;
+ RECT 445.155000 553.600000 446.420000 554.080000 ;
+ RECT 445.155000 646.080000 446.420000 646.560000 ;
+ RECT 625.320000 547.270000 626.420000 743.840000 ;
+ RECT 580.320000 547.270000 581.420000 743.840000 ;
+ RECT 638.130000 546.020000 639.130000 746.280000 ;
+ RECT 535.320000 547.270000 536.420000 743.840000 ;
+ RECT 490.320000 547.270000 491.420000 743.840000 ;
+ RECT 445.320000 547.270000 446.420000 743.840000 ;
+ RECT 441.490000 546.020000 442.490000 746.280000 ;
+ LAYER met3 ;
+ RECT 625.320000 738.560000 626.420000 739.040000 ;
+ RECT 638.130000 738.560000 639.130000 739.040000 ;
+ RECT 638.130000 727.680000 639.130000 728.160000 ;
+ RECT 638.130000 722.240000 639.130000 722.720000 ;
+ RECT 638.130000 733.120000 639.130000 733.600000 ;
+ RECT 625.320000 733.120000 626.420000 733.600000 ;
+ RECT 625.320000 727.680000 626.420000 728.160000 ;
+ RECT 625.320000 722.240000 626.420000 722.720000 ;
+ RECT 625.320000 711.360000 626.420000 711.840000 ;
+ RECT 625.320000 716.800000 626.420000 717.280000 ;
+ RECT 638.130000 711.360000 639.130000 711.840000 ;
+ RECT 638.130000 716.800000 639.130000 717.280000 ;
+ RECT 625.320000 700.480000 626.420000 700.960000 ;
+ RECT 625.320000 705.920000 626.420000 706.400000 ;
+ RECT 638.130000 700.480000 639.130000 700.960000 ;
+ RECT 638.130000 705.920000 639.130000 706.400000 ;
+ RECT 580.320000 722.240000 581.420000 722.720000 ;
+ RECT 580.320000 727.680000 581.420000 728.160000 ;
+ RECT 580.320000 733.120000 581.420000 733.600000 ;
+ RECT 580.320000 738.560000 581.420000 739.040000 ;
+ RECT 580.320000 705.920000 581.420000 706.400000 ;
+ RECT 580.320000 700.480000 581.420000 700.960000 ;
+ RECT 580.320000 711.360000 581.420000 711.840000 ;
+ RECT 580.320000 716.800000 581.420000 717.280000 ;
+ RECT 638.130000 689.600000 639.130000 690.080000 ;
+ RECT 638.130000 684.160000 639.130000 684.640000 ;
+ RECT 638.130000 695.040000 639.130000 695.520000 ;
+ RECT 625.320000 695.040000 626.420000 695.520000 ;
+ RECT 625.320000 689.600000 626.420000 690.080000 ;
+ RECT 625.320000 684.160000 626.420000 684.640000 ;
+ RECT 625.320000 673.280000 626.420000 673.760000 ;
+ RECT 625.320000 678.720000 626.420000 679.200000 ;
+ RECT 638.130000 673.280000 639.130000 673.760000 ;
+ RECT 638.130000 678.720000 639.130000 679.200000 ;
+ RECT 638.130000 662.400000 639.130000 662.880000 ;
+ RECT 638.130000 667.840000 639.130000 668.320000 ;
+ RECT 625.320000 667.840000 626.420000 668.320000 ;
+ RECT 625.320000 662.400000 626.420000 662.880000 ;
+ RECT 625.320000 651.520000 626.420000 652.000000 ;
+ RECT 625.320000 656.960000 626.420000 657.440000 ;
+ RECT 638.130000 651.520000 639.130000 652.000000 ;
+ RECT 638.130000 656.960000 639.130000 657.440000 ;
+ RECT 580.320000 673.280000 581.420000 673.760000 ;
+ RECT 580.320000 678.720000 581.420000 679.200000 ;
+ RECT 580.320000 684.160000 581.420000 684.640000 ;
+ RECT 580.320000 689.600000 581.420000 690.080000 ;
+ RECT 580.320000 695.040000 581.420000 695.520000 ;
+ RECT 580.320000 651.520000 581.420000 652.000000 ;
+ RECT 580.320000 656.960000 581.420000 657.440000 ;
+ RECT 580.320000 662.400000 581.420000 662.880000 ;
+ RECT 580.320000 667.840000 581.420000 668.320000 ;
+ RECT 535.320000 727.680000 536.420000 728.160000 ;
+ RECT 535.320000 722.240000 536.420000 722.720000 ;
+ RECT 535.320000 733.120000 536.420000 733.600000 ;
+ RECT 535.320000 738.560000 536.420000 739.040000 ;
+ RECT 490.320000 722.240000 491.420000 722.720000 ;
+ RECT 490.320000 727.680000 491.420000 728.160000 ;
+ RECT 490.320000 733.120000 491.420000 733.600000 ;
+ RECT 490.320000 738.560000 491.420000 739.040000 ;
+ RECT 535.320000 700.480000 536.420000 700.960000 ;
+ RECT 535.320000 705.920000 536.420000 706.400000 ;
+ RECT 535.320000 711.360000 536.420000 711.840000 ;
+ RECT 535.320000 716.800000 536.420000 717.280000 ;
+ RECT 490.320000 700.480000 491.420000 700.960000 ;
+ RECT 490.320000 705.920000 491.420000 706.400000 ;
+ RECT 490.320000 711.360000 491.420000 711.840000 ;
+ RECT 490.320000 716.800000 491.420000 717.280000 ;
+ RECT 441.490000 738.560000 442.490000 739.040000 ;
+ RECT 445.155000 738.560000 446.420000 739.040000 ;
+ RECT 441.490000 727.680000 442.490000 728.160000 ;
+ RECT 445.155000 727.680000 446.420000 728.160000 ;
+ RECT 441.490000 733.120000 442.490000 733.600000 ;
+ RECT 445.155000 733.120000 446.420000 733.600000 ;
+ RECT 441.490000 722.240000 442.490000 722.720000 ;
+ RECT 445.155000 722.240000 446.420000 722.720000 ;
+ RECT 441.490000 716.800000 442.490000 717.280000 ;
+ RECT 445.155000 716.800000 446.420000 717.280000 ;
+ RECT 441.490000 711.360000 442.490000 711.840000 ;
+ RECT 445.155000 711.360000 446.420000 711.840000 ;
+ RECT 441.490000 705.920000 442.490000 706.400000 ;
+ RECT 445.155000 705.920000 446.420000 706.400000 ;
+ RECT 441.490000 700.480000 442.490000 700.960000 ;
+ RECT 445.155000 700.480000 446.420000 700.960000 ;
+ RECT 535.320000 673.280000 536.420000 673.760000 ;
+ RECT 535.320000 678.720000 536.420000 679.200000 ;
+ RECT 535.320000 684.160000 536.420000 684.640000 ;
+ RECT 535.320000 689.600000 536.420000 690.080000 ;
+ RECT 535.320000 695.040000 536.420000 695.520000 ;
+ RECT 490.320000 673.280000 491.420000 673.760000 ;
+ RECT 490.320000 678.720000 491.420000 679.200000 ;
+ RECT 490.320000 684.160000 491.420000 684.640000 ;
+ RECT 490.320000 689.600000 491.420000 690.080000 ;
+ RECT 490.320000 695.040000 491.420000 695.520000 ;
+ RECT 535.320000 651.520000 536.420000 652.000000 ;
+ RECT 535.320000 656.960000 536.420000 657.440000 ;
+ RECT 535.320000 662.400000 536.420000 662.880000 ;
+ RECT 535.320000 667.840000 536.420000 668.320000 ;
+ RECT 490.320000 651.520000 491.420000 652.000000 ;
+ RECT 490.320000 656.960000 491.420000 657.440000 ;
+ RECT 490.320000 662.400000 491.420000 662.880000 ;
+ RECT 490.320000 667.840000 491.420000 668.320000 ;
+ RECT 441.490000 695.040000 442.490000 695.520000 ;
+ RECT 445.155000 695.040000 446.420000 695.520000 ;
+ RECT 441.490000 684.160000 442.490000 684.640000 ;
+ RECT 445.155000 684.160000 446.420000 684.640000 ;
+ RECT 441.490000 689.600000 442.490000 690.080000 ;
+ RECT 445.155000 689.600000 446.420000 690.080000 ;
+ RECT 441.490000 678.720000 442.490000 679.200000 ;
+ RECT 445.155000 678.720000 446.420000 679.200000 ;
+ RECT 441.490000 673.280000 442.490000 673.760000 ;
+ RECT 445.155000 673.280000 446.420000 673.760000 ;
+ RECT 441.490000 667.840000 442.490000 668.320000 ;
+ RECT 445.155000 667.840000 446.420000 668.320000 ;
+ RECT 441.490000 662.400000 442.490000 662.880000 ;
+ RECT 445.155000 662.400000 446.420000 662.880000 ;
+ RECT 441.490000 656.960000 442.490000 657.440000 ;
+ RECT 445.155000 656.960000 446.420000 657.440000 ;
+ RECT 441.490000 651.520000 442.490000 652.000000 ;
+ RECT 445.155000 651.520000 446.420000 652.000000 ;
+ RECT 625.320000 635.200000 626.420000 635.680000 ;
+ RECT 625.320000 640.640000 626.420000 641.120000 ;
+ RECT 638.130000 635.200000 639.130000 635.680000 ;
+ RECT 638.130000 640.640000 639.130000 641.120000 ;
+ RECT 638.130000 624.320000 639.130000 624.800000 ;
+ RECT 638.130000 629.760000 639.130000 630.240000 ;
+ RECT 625.320000 629.760000 626.420000 630.240000 ;
+ RECT 625.320000 624.320000 626.420000 624.800000 ;
+ RECT 625.320000 613.440000 626.420000 613.920000 ;
+ RECT 625.320000 618.880000 626.420000 619.360000 ;
+ RECT 638.130000 613.440000 639.130000 613.920000 ;
+ RECT 638.130000 618.880000 639.130000 619.360000 ;
+ RECT 638.130000 602.560000 639.130000 603.040000 ;
+ RECT 638.130000 597.120000 639.130000 597.600000 ;
+ RECT 638.130000 608.000000 639.130000 608.480000 ;
+ RECT 625.320000 608.000000 626.420000 608.480000 ;
+ RECT 625.320000 602.560000 626.420000 603.040000 ;
+ RECT 625.320000 597.120000 626.420000 597.600000 ;
+ RECT 580.320000 624.320000 581.420000 624.800000 ;
+ RECT 580.320000 629.760000 581.420000 630.240000 ;
+ RECT 580.320000 635.200000 581.420000 635.680000 ;
+ RECT 580.320000 640.640000 581.420000 641.120000 ;
+ RECT 580.320000 597.120000 581.420000 597.600000 ;
+ RECT 580.320000 602.560000 581.420000 603.040000 ;
+ RECT 580.320000 608.000000 581.420000 608.480000 ;
+ RECT 580.320000 613.440000 581.420000 613.920000 ;
+ RECT 580.320000 618.880000 581.420000 619.360000 ;
+ RECT 625.320000 586.240000 626.420000 586.720000 ;
+ RECT 625.320000 591.680000 626.420000 592.160000 ;
+ RECT 638.130000 586.240000 639.130000 586.720000 ;
+ RECT 638.130000 591.680000 639.130000 592.160000 ;
+ RECT 625.320000 575.360000 626.420000 575.840000 ;
+ RECT 625.320000 580.800000 626.420000 581.280000 ;
+ RECT 638.130000 575.360000 639.130000 575.840000 ;
+ RECT 638.130000 580.800000 639.130000 581.280000 ;
+ RECT 638.130000 564.480000 639.130000 564.960000 ;
+ RECT 638.130000 559.040000 639.130000 559.520000 ;
+ RECT 638.130000 569.920000 639.130000 570.400000 ;
+ RECT 625.320000 569.920000 626.420000 570.400000 ;
+ RECT 625.320000 564.480000 626.420000 564.960000 ;
+ RECT 625.320000 559.040000 626.420000 559.520000 ;
+ RECT 625.320000 553.600000 626.420000 554.080000 ;
+ RECT 638.130000 553.600000 639.130000 554.080000 ;
+ RECT 580.320000 575.360000 581.420000 575.840000 ;
+ RECT 580.320000 580.800000 581.420000 581.280000 ;
+ RECT 580.320000 586.240000 581.420000 586.720000 ;
+ RECT 580.320000 591.680000 581.420000 592.160000 ;
+ RECT 580.320000 553.600000 581.420000 554.080000 ;
+ RECT 580.320000 559.040000 581.420000 559.520000 ;
+ RECT 580.320000 564.480000 581.420000 564.960000 ;
+ RECT 580.320000 569.920000 581.420000 570.400000 ;
+ RECT 535.320000 624.320000 536.420000 624.800000 ;
+ RECT 535.320000 629.760000 536.420000 630.240000 ;
+ RECT 535.320000 635.200000 536.420000 635.680000 ;
+ RECT 535.320000 640.640000 536.420000 641.120000 ;
+ RECT 490.320000 624.320000 491.420000 624.800000 ;
+ RECT 490.320000 629.760000 491.420000 630.240000 ;
+ RECT 490.320000 635.200000 491.420000 635.680000 ;
+ RECT 490.320000 640.640000 491.420000 641.120000 ;
+ RECT 535.320000 597.120000 536.420000 597.600000 ;
+ RECT 535.320000 602.560000 536.420000 603.040000 ;
+ RECT 535.320000 608.000000 536.420000 608.480000 ;
+ RECT 535.320000 613.440000 536.420000 613.920000 ;
+ RECT 535.320000 618.880000 536.420000 619.360000 ;
+ RECT 490.320000 597.120000 491.420000 597.600000 ;
+ RECT 490.320000 602.560000 491.420000 603.040000 ;
+ RECT 490.320000 608.000000 491.420000 608.480000 ;
+ RECT 490.320000 613.440000 491.420000 613.920000 ;
+ RECT 490.320000 618.880000 491.420000 619.360000 ;
+ RECT 441.490000 640.640000 442.490000 641.120000 ;
+ RECT 445.155000 640.640000 446.420000 641.120000 ;
+ RECT 441.490000 635.200000 442.490000 635.680000 ;
+ RECT 445.155000 635.200000 446.420000 635.680000 ;
+ RECT 441.490000 629.760000 442.490000 630.240000 ;
+ RECT 445.155000 629.760000 446.420000 630.240000 ;
+ RECT 441.490000 624.320000 442.490000 624.800000 ;
+ RECT 445.155000 624.320000 446.420000 624.800000 ;
+ RECT 441.490000 618.880000 442.490000 619.360000 ;
+ RECT 445.155000 618.880000 446.420000 619.360000 ;
+ RECT 441.490000 613.440000 442.490000 613.920000 ;
+ RECT 445.155000 613.440000 446.420000 613.920000 ;
+ RECT 441.490000 602.560000 442.490000 603.040000 ;
+ RECT 445.155000 602.560000 446.420000 603.040000 ;
+ RECT 441.490000 608.000000 442.490000 608.480000 ;
+ RECT 445.155000 608.000000 446.420000 608.480000 ;
+ RECT 441.490000 597.120000 442.490000 597.600000 ;
+ RECT 445.155000 597.120000 446.420000 597.600000 ;
+ RECT 535.320000 575.360000 536.420000 575.840000 ;
+ RECT 535.320000 580.800000 536.420000 581.280000 ;
+ RECT 535.320000 586.240000 536.420000 586.720000 ;
+ RECT 535.320000 591.680000 536.420000 592.160000 ;
+ RECT 490.320000 575.360000 491.420000 575.840000 ;
+ RECT 490.320000 580.800000 491.420000 581.280000 ;
+ RECT 490.320000 586.240000 491.420000 586.720000 ;
+ RECT 490.320000 591.680000 491.420000 592.160000 ;
+ RECT 535.320000 553.600000 536.420000 554.080000 ;
+ RECT 535.320000 559.040000 536.420000 559.520000 ;
+ RECT 535.320000 564.480000 536.420000 564.960000 ;
+ RECT 535.320000 569.920000 536.420000 570.400000 ;
+ RECT 490.320000 553.600000 491.420000 554.080000 ;
+ RECT 490.320000 559.040000 491.420000 559.520000 ;
+ RECT 490.320000 564.480000 491.420000 564.960000 ;
+ RECT 490.320000 569.920000 491.420000 570.400000 ;
+ RECT 441.490000 591.680000 442.490000 592.160000 ;
+ RECT 445.155000 591.680000 446.420000 592.160000 ;
+ RECT 441.490000 586.240000 442.490000 586.720000 ;
+ RECT 445.155000 586.240000 446.420000 586.720000 ;
+ RECT 441.490000 580.800000 442.490000 581.280000 ;
+ RECT 445.155000 580.800000 446.420000 581.280000 ;
+ RECT 441.490000 575.360000 442.490000 575.840000 ;
+ RECT 445.155000 575.360000 446.420000 575.840000 ;
+ RECT 441.490000 569.920000 442.490000 570.400000 ;
+ RECT 445.155000 569.920000 446.420000 570.400000 ;
+ RECT 441.490000 559.040000 442.490000 559.520000 ;
+ RECT 445.155000 559.040000 446.420000 559.520000 ;
+ RECT 441.490000 564.480000 442.490000 564.960000 ;
+ RECT 445.155000 564.480000 446.420000 564.960000 ;
+ RECT 441.490000 553.600000 442.490000 554.080000 ;
+ RECT 445.155000 553.600000 446.420000 554.080000 ;
+ RECT 580.320000 646.080000 581.420000 646.560000 ;
+ RECT 625.320000 646.080000 626.420000 646.560000 ;
+ RECT 638.130000 646.080000 639.130000 646.560000 ;
+ RECT 490.320000 646.080000 491.420000 646.560000 ;
+ RECT 535.320000 646.080000 536.420000 646.560000 ;
+ RECT 441.490000 646.080000 442.490000 646.560000 ;
+ RECT 445.155000 646.080000 446.420000 646.560000 ;
+ RECT 440.260000 742.840000 640.360000 743.840000 ;
+ RECT 440.260000 547.270000 640.360000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 546.020000 442.490000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 745.280000 442.490000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 546.020000 639.130000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 745.280000 639.130000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 547.270000 441.260000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 547.270000 640.360000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 742.840000 441.260000 743.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 742.840000 640.360000 743.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 538.300000 446.420000 538.780000 ;
+ RECT 445.155000 527.420000 446.420000 527.900000 ;
+ RECT 445.155000 532.860000 446.420000 533.340000 ;
+ RECT 445.155000 521.980000 446.420000 522.460000 ;
+ RECT 445.155000 516.540000 446.420000 517.020000 ;
+ RECT 445.155000 511.100000 446.420000 511.580000 ;
+ RECT 445.155000 505.660000 446.420000 506.140000 ;
+ RECT 445.155000 500.220000 446.420000 500.700000 ;
+ RECT 445.155000 494.780000 446.420000 495.260000 ;
+ RECT 445.155000 483.900000 446.420000 484.380000 ;
+ RECT 445.155000 489.340000 446.420000 489.820000 ;
+ RECT 445.155000 478.460000 446.420000 478.940000 ;
+ RECT 445.155000 473.020000 446.420000 473.500000 ;
+ RECT 445.155000 467.580000 446.420000 468.060000 ;
+ RECT 445.155000 462.140000 446.420000 462.620000 ;
+ RECT 445.155000 456.700000 446.420000 457.180000 ;
+ RECT 445.155000 451.260000 446.420000 451.740000 ;
+ RECT 445.155000 440.380000 446.420000 440.860000 ;
+ RECT 445.155000 434.940000 446.420000 435.420000 ;
+ RECT 445.155000 429.500000 446.420000 429.980000 ;
+ RECT 445.155000 424.060000 446.420000 424.540000 ;
+ RECT 445.155000 418.620000 446.420000 419.100000 ;
+ RECT 445.155000 413.180000 446.420000 413.660000 ;
+ RECT 445.155000 402.300000 446.420000 402.780000 ;
+ RECT 445.155000 407.740000 446.420000 408.220000 ;
+ RECT 445.155000 396.860000 446.420000 397.340000 ;
+ RECT 445.155000 391.420000 446.420000 391.900000 ;
+ RECT 445.155000 385.980000 446.420000 386.460000 ;
+ RECT 445.155000 380.540000 446.420000 381.020000 ;
+ RECT 445.155000 375.100000 446.420000 375.580000 ;
+ RECT 445.155000 369.660000 446.420000 370.140000 ;
+ RECT 445.155000 358.780000 446.420000 359.260000 ;
+ RECT 445.155000 364.220000 446.420000 364.700000 ;
+ RECT 445.155000 353.340000 446.420000 353.820000 ;
+ RECT 445.155000 445.820000 446.420000 446.300000 ;
+ RECT 625.320000 347.010000 626.420000 543.580000 ;
+ RECT 580.320000 347.010000 581.420000 543.580000 ;
+ RECT 638.130000 345.760000 639.130000 546.020000 ;
+ RECT 535.320000 347.010000 536.420000 543.580000 ;
+ RECT 490.320000 347.010000 491.420000 543.580000 ;
+ RECT 445.320000 347.010000 446.420000 543.580000 ;
+ RECT 441.490000 345.760000 442.490000 546.020000 ;
+ LAYER met3 ;
+ RECT 625.320000 538.300000 626.420000 538.780000 ;
+ RECT 638.130000 538.300000 639.130000 538.780000 ;
+ RECT 638.130000 527.420000 639.130000 527.900000 ;
+ RECT 638.130000 521.980000 639.130000 522.460000 ;
+ RECT 638.130000 532.860000 639.130000 533.340000 ;
+ RECT 625.320000 532.860000 626.420000 533.340000 ;
+ RECT 625.320000 527.420000 626.420000 527.900000 ;
+ RECT 625.320000 521.980000 626.420000 522.460000 ;
+ RECT 625.320000 511.100000 626.420000 511.580000 ;
+ RECT 625.320000 516.540000 626.420000 517.020000 ;
+ RECT 638.130000 511.100000 639.130000 511.580000 ;
+ RECT 638.130000 516.540000 639.130000 517.020000 ;
+ RECT 625.320000 500.220000 626.420000 500.700000 ;
+ RECT 625.320000 505.660000 626.420000 506.140000 ;
+ RECT 638.130000 500.220000 639.130000 500.700000 ;
+ RECT 638.130000 505.660000 639.130000 506.140000 ;
+ RECT 580.320000 521.980000 581.420000 522.460000 ;
+ RECT 580.320000 527.420000 581.420000 527.900000 ;
+ RECT 580.320000 532.860000 581.420000 533.340000 ;
+ RECT 580.320000 538.300000 581.420000 538.780000 ;
+ RECT 580.320000 505.660000 581.420000 506.140000 ;
+ RECT 580.320000 500.220000 581.420000 500.700000 ;
+ RECT 580.320000 511.100000 581.420000 511.580000 ;
+ RECT 580.320000 516.540000 581.420000 517.020000 ;
+ RECT 638.130000 489.340000 639.130000 489.820000 ;
+ RECT 638.130000 483.900000 639.130000 484.380000 ;
+ RECT 638.130000 494.780000 639.130000 495.260000 ;
+ RECT 625.320000 494.780000 626.420000 495.260000 ;
+ RECT 625.320000 489.340000 626.420000 489.820000 ;
+ RECT 625.320000 483.900000 626.420000 484.380000 ;
+ RECT 625.320000 473.020000 626.420000 473.500000 ;
+ RECT 625.320000 478.460000 626.420000 478.940000 ;
+ RECT 638.130000 473.020000 639.130000 473.500000 ;
+ RECT 638.130000 478.460000 639.130000 478.940000 ;
+ RECT 638.130000 462.140000 639.130000 462.620000 ;
+ RECT 638.130000 467.580000 639.130000 468.060000 ;
+ RECT 625.320000 467.580000 626.420000 468.060000 ;
+ RECT 625.320000 462.140000 626.420000 462.620000 ;
+ RECT 625.320000 451.260000 626.420000 451.740000 ;
+ RECT 625.320000 456.700000 626.420000 457.180000 ;
+ RECT 638.130000 451.260000 639.130000 451.740000 ;
+ RECT 638.130000 456.700000 639.130000 457.180000 ;
+ RECT 580.320000 473.020000 581.420000 473.500000 ;
+ RECT 580.320000 478.460000 581.420000 478.940000 ;
+ RECT 580.320000 483.900000 581.420000 484.380000 ;
+ RECT 580.320000 489.340000 581.420000 489.820000 ;
+ RECT 580.320000 494.780000 581.420000 495.260000 ;
+ RECT 580.320000 451.260000 581.420000 451.740000 ;
+ RECT 580.320000 456.700000 581.420000 457.180000 ;
+ RECT 580.320000 462.140000 581.420000 462.620000 ;
+ RECT 580.320000 467.580000 581.420000 468.060000 ;
+ RECT 535.320000 527.420000 536.420000 527.900000 ;
+ RECT 535.320000 521.980000 536.420000 522.460000 ;
+ RECT 535.320000 532.860000 536.420000 533.340000 ;
+ RECT 535.320000 538.300000 536.420000 538.780000 ;
+ RECT 490.320000 521.980000 491.420000 522.460000 ;
+ RECT 490.320000 527.420000 491.420000 527.900000 ;
+ RECT 490.320000 532.860000 491.420000 533.340000 ;
+ RECT 490.320000 538.300000 491.420000 538.780000 ;
+ RECT 535.320000 500.220000 536.420000 500.700000 ;
+ RECT 535.320000 505.660000 536.420000 506.140000 ;
+ RECT 535.320000 511.100000 536.420000 511.580000 ;
+ RECT 535.320000 516.540000 536.420000 517.020000 ;
+ RECT 490.320000 500.220000 491.420000 500.700000 ;
+ RECT 490.320000 505.660000 491.420000 506.140000 ;
+ RECT 490.320000 511.100000 491.420000 511.580000 ;
+ RECT 490.320000 516.540000 491.420000 517.020000 ;
+ RECT 441.490000 538.300000 442.490000 538.780000 ;
+ RECT 445.155000 538.300000 446.420000 538.780000 ;
+ RECT 441.490000 527.420000 442.490000 527.900000 ;
+ RECT 445.155000 527.420000 446.420000 527.900000 ;
+ RECT 441.490000 532.860000 442.490000 533.340000 ;
+ RECT 445.155000 532.860000 446.420000 533.340000 ;
+ RECT 441.490000 521.980000 442.490000 522.460000 ;
+ RECT 445.155000 521.980000 446.420000 522.460000 ;
+ RECT 441.490000 516.540000 442.490000 517.020000 ;
+ RECT 445.155000 516.540000 446.420000 517.020000 ;
+ RECT 441.490000 511.100000 442.490000 511.580000 ;
+ RECT 445.155000 511.100000 446.420000 511.580000 ;
+ RECT 441.490000 505.660000 442.490000 506.140000 ;
+ RECT 445.155000 505.660000 446.420000 506.140000 ;
+ RECT 441.490000 500.220000 442.490000 500.700000 ;
+ RECT 445.155000 500.220000 446.420000 500.700000 ;
+ RECT 535.320000 473.020000 536.420000 473.500000 ;
+ RECT 535.320000 478.460000 536.420000 478.940000 ;
+ RECT 535.320000 483.900000 536.420000 484.380000 ;
+ RECT 535.320000 489.340000 536.420000 489.820000 ;
+ RECT 535.320000 494.780000 536.420000 495.260000 ;
+ RECT 490.320000 473.020000 491.420000 473.500000 ;
+ RECT 490.320000 478.460000 491.420000 478.940000 ;
+ RECT 490.320000 483.900000 491.420000 484.380000 ;
+ RECT 490.320000 489.340000 491.420000 489.820000 ;
+ RECT 490.320000 494.780000 491.420000 495.260000 ;
+ RECT 535.320000 451.260000 536.420000 451.740000 ;
+ RECT 535.320000 456.700000 536.420000 457.180000 ;
+ RECT 535.320000 462.140000 536.420000 462.620000 ;
+ RECT 535.320000 467.580000 536.420000 468.060000 ;
+ RECT 490.320000 451.260000 491.420000 451.740000 ;
+ RECT 490.320000 456.700000 491.420000 457.180000 ;
+ RECT 490.320000 462.140000 491.420000 462.620000 ;
+ RECT 490.320000 467.580000 491.420000 468.060000 ;
+ RECT 441.490000 494.780000 442.490000 495.260000 ;
+ RECT 445.155000 494.780000 446.420000 495.260000 ;
+ RECT 441.490000 483.900000 442.490000 484.380000 ;
+ RECT 445.155000 483.900000 446.420000 484.380000 ;
+ RECT 441.490000 489.340000 442.490000 489.820000 ;
+ RECT 445.155000 489.340000 446.420000 489.820000 ;
+ RECT 441.490000 478.460000 442.490000 478.940000 ;
+ RECT 445.155000 478.460000 446.420000 478.940000 ;
+ RECT 441.490000 473.020000 442.490000 473.500000 ;
+ RECT 445.155000 473.020000 446.420000 473.500000 ;
+ RECT 441.490000 467.580000 442.490000 468.060000 ;
+ RECT 445.155000 467.580000 446.420000 468.060000 ;
+ RECT 441.490000 462.140000 442.490000 462.620000 ;
+ RECT 445.155000 462.140000 446.420000 462.620000 ;
+ RECT 441.490000 456.700000 442.490000 457.180000 ;
+ RECT 445.155000 456.700000 446.420000 457.180000 ;
+ RECT 441.490000 451.260000 442.490000 451.740000 ;
+ RECT 445.155000 451.260000 446.420000 451.740000 ;
+ RECT 625.320000 434.940000 626.420000 435.420000 ;
+ RECT 625.320000 440.380000 626.420000 440.860000 ;
+ RECT 638.130000 434.940000 639.130000 435.420000 ;
+ RECT 638.130000 440.380000 639.130000 440.860000 ;
+ RECT 638.130000 424.060000 639.130000 424.540000 ;
+ RECT 638.130000 429.500000 639.130000 429.980000 ;
+ RECT 625.320000 429.500000 626.420000 429.980000 ;
+ RECT 625.320000 424.060000 626.420000 424.540000 ;
+ RECT 625.320000 413.180000 626.420000 413.660000 ;
+ RECT 625.320000 418.620000 626.420000 419.100000 ;
+ RECT 638.130000 413.180000 639.130000 413.660000 ;
+ RECT 638.130000 418.620000 639.130000 419.100000 ;
+ RECT 638.130000 402.300000 639.130000 402.780000 ;
+ RECT 638.130000 396.860000 639.130000 397.340000 ;
+ RECT 638.130000 407.740000 639.130000 408.220000 ;
+ RECT 625.320000 407.740000 626.420000 408.220000 ;
+ RECT 625.320000 402.300000 626.420000 402.780000 ;
+ RECT 625.320000 396.860000 626.420000 397.340000 ;
+ RECT 580.320000 424.060000 581.420000 424.540000 ;
+ RECT 580.320000 429.500000 581.420000 429.980000 ;
+ RECT 580.320000 434.940000 581.420000 435.420000 ;
+ RECT 580.320000 440.380000 581.420000 440.860000 ;
+ RECT 580.320000 396.860000 581.420000 397.340000 ;
+ RECT 580.320000 402.300000 581.420000 402.780000 ;
+ RECT 580.320000 407.740000 581.420000 408.220000 ;
+ RECT 580.320000 413.180000 581.420000 413.660000 ;
+ RECT 580.320000 418.620000 581.420000 419.100000 ;
+ RECT 625.320000 385.980000 626.420000 386.460000 ;
+ RECT 625.320000 391.420000 626.420000 391.900000 ;
+ RECT 638.130000 385.980000 639.130000 386.460000 ;
+ RECT 638.130000 391.420000 639.130000 391.900000 ;
+ RECT 625.320000 375.100000 626.420000 375.580000 ;
+ RECT 625.320000 380.540000 626.420000 381.020000 ;
+ RECT 638.130000 375.100000 639.130000 375.580000 ;
+ RECT 638.130000 380.540000 639.130000 381.020000 ;
+ RECT 638.130000 364.220000 639.130000 364.700000 ;
+ RECT 638.130000 358.780000 639.130000 359.260000 ;
+ RECT 638.130000 369.660000 639.130000 370.140000 ;
+ RECT 625.320000 369.660000 626.420000 370.140000 ;
+ RECT 625.320000 364.220000 626.420000 364.700000 ;
+ RECT 625.320000 358.780000 626.420000 359.260000 ;
+ RECT 625.320000 353.340000 626.420000 353.820000 ;
+ RECT 638.130000 353.340000 639.130000 353.820000 ;
+ RECT 580.320000 375.100000 581.420000 375.580000 ;
+ RECT 580.320000 380.540000 581.420000 381.020000 ;
+ RECT 580.320000 385.980000 581.420000 386.460000 ;
+ RECT 580.320000 391.420000 581.420000 391.900000 ;
+ RECT 580.320000 353.340000 581.420000 353.820000 ;
+ RECT 580.320000 358.780000 581.420000 359.260000 ;
+ RECT 580.320000 364.220000 581.420000 364.700000 ;
+ RECT 580.320000 369.660000 581.420000 370.140000 ;
+ RECT 535.320000 424.060000 536.420000 424.540000 ;
+ RECT 535.320000 429.500000 536.420000 429.980000 ;
+ RECT 535.320000 434.940000 536.420000 435.420000 ;
+ RECT 535.320000 440.380000 536.420000 440.860000 ;
+ RECT 490.320000 424.060000 491.420000 424.540000 ;
+ RECT 490.320000 429.500000 491.420000 429.980000 ;
+ RECT 490.320000 434.940000 491.420000 435.420000 ;
+ RECT 490.320000 440.380000 491.420000 440.860000 ;
+ RECT 535.320000 396.860000 536.420000 397.340000 ;
+ RECT 535.320000 402.300000 536.420000 402.780000 ;
+ RECT 535.320000 407.740000 536.420000 408.220000 ;
+ RECT 535.320000 413.180000 536.420000 413.660000 ;
+ RECT 535.320000 418.620000 536.420000 419.100000 ;
+ RECT 490.320000 396.860000 491.420000 397.340000 ;
+ RECT 490.320000 402.300000 491.420000 402.780000 ;
+ RECT 490.320000 407.740000 491.420000 408.220000 ;
+ RECT 490.320000 413.180000 491.420000 413.660000 ;
+ RECT 490.320000 418.620000 491.420000 419.100000 ;
+ RECT 441.490000 440.380000 442.490000 440.860000 ;
+ RECT 445.155000 440.380000 446.420000 440.860000 ;
+ RECT 441.490000 434.940000 442.490000 435.420000 ;
+ RECT 445.155000 434.940000 446.420000 435.420000 ;
+ RECT 441.490000 429.500000 442.490000 429.980000 ;
+ RECT 445.155000 429.500000 446.420000 429.980000 ;
+ RECT 441.490000 424.060000 442.490000 424.540000 ;
+ RECT 445.155000 424.060000 446.420000 424.540000 ;
+ RECT 441.490000 418.620000 442.490000 419.100000 ;
+ RECT 445.155000 418.620000 446.420000 419.100000 ;
+ RECT 441.490000 413.180000 442.490000 413.660000 ;
+ RECT 445.155000 413.180000 446.420000 413.660000 ;
+ RECT 441.490000 402.300000 442.490000 402.780000 ;
+ RECT 445.155000 402.300000 446.420000 402.780000 ;
+ RECT 441.490000 407.740000 442.490000 408.220000 ;
+ RECT 445.155000 407.740000 446.420000 408.220000 ;
+ RECT 441.490000 396.860000 442.490000 397.340000 ;
+ RECT 445.155000 396.860000 446.420000 397.340000 ;
+ RECT 535.320000 375.100000 536.420000 375.580000 ;
+ RECT 535.320000 380.540000 536.420000 381.020000 ;
+ RECT 535.320000 385.980000 536.420000 386.460000 ;
+ RECT 535.320000 391.420000 536.420000 391.900000 ;
+ RECT 490.320000 375.100000 491.420000 375.580000 ;
+ RECT 490.320000 380.540000 491.420000 381.020000 ;
+ RECT 490.320000 385.980000 491.420000 386.460000 ;
+ RECT 490.320000 391.420000 491.420000 391.900000 ;
+ RECT 535.320000 353.340000 536.420000 353.820000 ;
+ RECT 535.320000 358.780000 536.420000 359.260000 ;
+ RECT 535.320000 364.220000 536.420000 364.700000 ;
+ RECT 535.320000 369.660000 536.420000 370.140000 ;
+ RECT 490.320000 353.340000 491.420000 353.820000 ;
+ RECT 490.320000 358.780000 491.420000 359.260000 ;
+ RECT 490.320000 364.220000 491.420000 364.700000 ;
+ RECT 490.320000 369.660000 491.420000 370.140000 ;
+ RECT 441.490000 391.420000 442.490000 391.900000 ;
+ RECT 445.155000 391.420000 446.420000 391.900000 ;
+ RECT 441.490000 385.980000 442.490000 386.460000 ;
+ RECT 445.155000 385.980000 446.420000 386.460000 ;
+ RECT 441.490000 380.540000 442.490000 381.020000 ;
+ RECT 445.155000 380.540000 446.420000 381.020000 ;
+ RECT 441.490000 375.100000 442.490000 375.580000 ;
+ RECT 445.155000 375.100000 446.420000 375.580000 ;
+ RECT 441.490000 369.660000 442.490000 370.140000 ;
+ RECT 445.155000 369.660000 446.420000 370.140000 ;
+ RECT 441.490000 358.780000 442.490000 359.260000 ;
+ RECT 445.155000 358.780000 446.420000 359.260000 ;
+ RECT 441.490000 364.220000 442.490000 364.700000 ;
+ RECT 445.155000 364.220000 446.420000 364.700000 ;
+ RECT 441.490000 353.340000 442.490000 353.820000 ;
+ RECT 445.155000 353.340000 446.420000 353.820000 ;
+ RECT 580.320000 445.820000 581.420000 446.300000 ;
+ RECT 625.320000 445.820000 626.420000 446.300000 ;
+ RECT 638.130000 445.820000 639.130000 446.300000 ;
+ RECT 490.320000 445.820000 491.420000 446.300000 ;
+ RECT 535.320000 445.820000 536.420000 446.300000 ;
+ RECT 441.490000 445.820000 442.490000 446.300000 ;
+ RECT 445.155000 445.820000 446.420000 446.300000 ;
+ RECT 440.260000 542.580000 640.360000 543.580000 ;
+ RECT 440.260000 347.010000 640.360000 348.010000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 345.760000 442.490000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 545.020000 442.490000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 345.760000 639.130000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 545.020000 639.130000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 347.010000 441.260000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 347.010000 640.360000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 542.580000 441.260000 543.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 542.580000 640.360000 543.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 338.040000 446.420000 338.520000 ;
+ RECT 445.155000 327.160000 446.420000 327.640000 ;
+ RECT 445.155000 332.600000 446.420000 333.080000 ;
+ RECT 445.155000 321.720000 446.420000 322.200000 ;
+ RECT 445.155000 316.280000 446.420000 316.760000 ;
+ RECT 445.155000 310.840000 446.420000 311.320000 ;
+ RECT 445.155000 305.400000 446.420000 305.880000 ;
+ RECT 445.155000 299.960000 446.420000 300.440000 ;
+ RECT 445.155000 294.520000 446.420000 295.000000 ;
+ RECT 445.155000 283.640000 446.420000 284.120000 ;
+ RECT 445.155000 289.080000 446.420000 289.560000 ;
+ RECT 445.155000 278.200000 446.420000 278.680000 ;
+ RECT 445.155000 272.760000 446.420000 273.240000 ;
+ RECT 445.155000 267.320000 446.420000 267.800000 ;
+ RECT 445.155000 261.880000 446.420000 262.360000 ;
+ RECT 445.155000 256.440000 446.420000 256.920000 ;
+ RECT 445.155000 251.000000 446.420000 251.480000 ;
+ RECT 445.155000 240.120000 446.420000 240.600000 ;
+ RECT 445.155000 234.680000 446.420000 235.160000 ;
+ RECT 445.155000 229.240000 446.420000 229.720000 ;
+ RECT 445.155000 223.800000 446.420000 224.280000 ;
+ RECT 445.155000 218.360000 446.420000 218.840000 ;
+ RECT 445.155000 212.920000 446.420000 213.400000 ;
+ RECT 445.155000 202.040000 446.420000 202.520000 ;
+ RECT 445.155000 207.480000 446.420000 207.960000 ;
+ RECT 445.155000 196.600000 446.420000 197.080000 ;
+ RECT 445.155000 191.160000 446.420000 191.640000 ;
+ RECT 445.155000 185.720000 446.420000 186.200000 ;
+ RECT 445.155000 180.280000 446.420000 180.760000 ;
+ RECT 445.155000 174.840000 446.420000 175.320000 ;
+ RECT 445.155000 169.400000 446.420000 169.880000 ;
+ RECT 445.155000 158.520000 446.420000 159.000000 ;
+ RECT 445.155000 163.960000 446.420000 164.440000 ;
+ RECT 445.155000 153.080000 446.420000 153.560000 ;
+ RECT 445.155000 245.560000 446.420000 246.040000 ;
+ RECT 625.320000 146.750000 626.420000 343.320000 ;
+ RECT 580.320000 146.750000 581.420000 343.320000 ;
+ RECT 638.130000 145.500000 639.130000 345.760000 ;
+ RECT 535.320000 146.750000 536.420000 343.320000 ;
+ RECT 490.320000 146.750000 491.420000 343.320000 ;
+ RECT 445.320000 146.750000 446.420000 343.320000 ;
+ RECT 441.490000 145.500000 442.490000 345.760000 ;
+ LAYER met3 ;
+ RECT 625.320000 338.040000 626.420000 338.520000 ;
+ RECT 638.130000 338.040000 639.130000 338.520000 ;
+ RECT 638.130000 327.160000 639.130000 327.640000 ;
+ RECT 638.130000 321.720000 639.130000 322.200000 ;
+ RECT 638.130000 332.600000 639.130000 333.080000 ;
+ RECT 625.320000 332.600000 626.420000 333.080000 ;
+ RECT 625.320000 327.160000 626.420000 327.640000 ;
+ RECT 625.320000 321.720000 626.420000 322.200000 ;
+ RECT 625.320000 310.840000 626.420000 311.320000 ;
+ RECT 625.320000 316.280000 626.420000 316.760000 ;
+ RECT 638.130000 310.840000 639.130000 311.320000 ;
+ RECT 638.130000 316.280000 639.130000 316.760000 ;
+ RECT 625.320000 299.960000 626.420000 300.440000 ;
+ RECT 625.320000 305.400000 626.420000 305.880000 ;
+ RECT 638.130000 299.960000 639.130000 300.440000 ;
+ RECT 638.130000 305.400000 639.130000 305.880000 ;
+ RECT 580.320000 321.720000 581.420000 322.200000 ;
+ RECT 580.320000 327.160000 581.420000 327.640000 ;
+ RECT 580.320000 332.600000 581.420000 333.080000 ;
+ RECT 580.320000 338.040000 581.420000 338.520000 ;
+ RECT 580.320000 305.400000 581.420000 305.880000 ;
+ RECT 580.320000 299.960000 581.420000 300.440000 ;
+ RECT 580.320000 310.840000 581.420000 311.320000 ;
+ RECT 580.320000 316.280000 581.420000 316.760000 ;
+ RECT 638.130000 289.080000 639.130000 289.560000 ;
+ RECT 638.130000 283.640000 639.130000 284.120000 ;
+ RECT 638.130000 294.520000 639.130000 295.000000 ;
+ RECT 625.320000 294.520000 626.420000 295.000000 ;
+ RECT 625.320000 289.080000 626.420000 289.560000 ;
+ RECT 625.320000 283.640000 626.420000 284.120000 ;
+ RECT 625.320000 272.760000 626.420000 273.240000 ;
+ RECT 625.320000 278.200000 626.420000 278.680000 ;
+ RECT 638.130000 272.760000 639.130000 273.240000 ;
+ RECT 638.130000 278.200000 639.130000 278.680000 ;
+ RECT 638.130000 261.880000 639.130000 262.360000 ;
+ RECT 638.130000 267.320000 639.130000 267.800000 ;
+ RECT 625.320000 267.320000 626.420000 267.800000 ;
+ RECT 625.320000 261.880000 626.420000 262.360000 ;
+ RECT 625.320000 251.000000 626.420000 251.480000 ;
+ RECT 625.320000 256.440000 626.420000 256.920000 ;
+ RECT 638.130000 251.000000 639.130000 251.480000 ;
+ RECT 638.130000 256.440000 639.130000 256.920000 ;
+ RECT 580.320000 272.760000 581.420000 273.240000 ;
+ RECT 580.320000 278.200000 581.420000 278.680000 ;
+ RECT 580.320000 283.640000 581.420000 284.120000 ;
+ RECT 580.320000 289.080000 581.420000 289.560000 ;
+ RECT 580.320000 294.520000 581.420000 295.000000 ;
+ RECT 580.320000 251.000000 581.420000 251.480000 ;
+ RECT 580.320000 256.440000 581.420000 256.920000 ;
+ RECT 580.320000 261.880000 581.420000 262.360000 ;
+ RECT 580.320000 267.320000 581.420000 267.800000 ;
+ RECT 535.320000 327.160000 536.420000 327.640000 ;
+ RECT 535.320000 321.720000 536.420000 322.200000 ;
+ RECT 535.320000 332.600000 536.420000 333.080000 ;
+ RECT 535.320000 338.040000 536.420000 338.520000 ;
+ RECT 490.320000 321.720000 491.420000 322.200000 ;
+ RECT 490.320000 327.160000 491.420000 327.640000 ;
+ RECT 490.320000 332.600000 491.420000 333.080000 ;
+ RECT 490.320000 338.040000 491.420000 338.520000 ;
+ RECT 535.320000 299.960000 536.420000 300.440000 ;
+ RECT 535.320000 305.400000 536.420000 305.880000 ;
+ RECT 535.320000 310.840000 536.420000 311.320000 ;
+ RECT 535.320000 316.280000 536.420000 316.760000 ;
+ RECT 490.320000 299.960000 491.420000 300.440000 ;
+ RECT 490.320000 305.400000 491.420000 305.880000 ;
+ RECT 490.320000 310.840000 491.420000 311.320000 ;
+ RECT 490.320000 316.280000 491.420000 316.760000 ;
+ RECT 441.490000 338.040000 442.490000 338.520000 ;
+ RECT 445.155000 338.040000 446.420000 338.520000 ;
+ RECT 441.490000 327.160000 442.490000 327.640000 ;
+ RECT 445.155000 327.160000 446.420000 327.640000 ;
+ RECT 441.490000 332.600000 442.490000 333.080000 ;
+ RECT 445.155000 332.600000 446.420000 333.080000 ;
+ RECT 441.490000 321.720000 442.490000 322.200000 ;
+ RECT 445.155000 321.720000 446.420000 322.200000 ;
+ RECT 441.490000 316.280000 442.490000 316.760000 ;
+ RECT 445.155000 316.280000 446.420000 316.760000 ;
+ RECT 441.490000 310.840000 442.490000 311.320000 ;
+ RECT 445.155000 310.840000 446.420000 311.320000 ;
+ RECT 441.490000 305.400000 442.490000 305.880000 ;
+ RECT 445.155000 305.400000 446.420000 305.880000 ;
+ RECT 441.490000 299.960000 442.490000 300.440000 ;
+ RECT 445.155000 299.960000 446.420000 300.440000 ;
+ RECT 535.320000 272.760000 536.420000 273.240000 ;
+ RECT 535.320000 278.200000 536.420000 278.680000 ;
+ RECT 535.320000 283.640000 536.420000 284.120000 ;
+ RECT 535.320000 289.080000 536.420000 289.560000 ;
+ RECT 535.320000 294.520000 536.420000 295.000000 ;
+ RECT 490.320000 272.760000 491.420000 273.240000 ;
+ RECT 490.320000 278.200000 491.420000 278.680000 ;
+ RECT 490.320000 283.640000 491.420000 284.120000 ;
+ RECT 490.320000 289.080000 491.420000 289.560000 ;
+ RECT 490.320000 294.520000 491.420000 295.000000 ;
+ RECT 535.320000 251.000000 536.420000 251.480000 ;
+ RECT 535.320000 256.440000 536.420000 256.920000 ;
+ RECT 535.320000 261.880000 536.420000 262.360000 ;
+ RECT 535.320000 267.320000 536.420000 267.800000 ;
+ RECT 490.320000 251.000000 491.420000 251.480000 ;
+ RECT 490.320000 256.440000 491.420000 256.920000 ;
+ RECT 490.320000 261.880000 491.420000 262.360000 ;
+ RECT 490.320000 267.320000 491.420000 267.800000 ;
+ RECT 441.490000 294.520000 442.490000 295.000000 ;
+ RECT 445.155000 294.520000 446.420000 295.000000 ;
+ RECT 441.490000 283.640000 442.490000 284.120000 ;
+ RECT 445.155000 283.640000 446.420000 284.120000 ;
+ RECT 441.490000 289.080000 442.490000 289.560000 ;
+ RECT 445.155000 289.080000 446.420000 289.560000 ;
+ RECT 441.490000 278.200000 442.490000 278.680000 ;
+ RECT 445.155000 278.200000 446.420000 278.680000 ;
+ RECT 441.490000 272.760000 442.490000 273.240000 ;
+ RECT 445.155000 272.760000 446.420000 273.240000 ;
+ RECT 441.490000 267.320000 442.490000 267.800000 ;
+ RECT 445.155000 267.320000 446.420000 267.800000 ;
+ RECT 441.490000 261.880000 442.490000 262.360000 ;
+ RECT 445.155000 261.880000 446.420000 262.360000 ;
+ RECT 441.490000 256.440000 442.490000 256.920000 ;
+ RECT 445.155000 256.440000 446.420000 256.920000 ;
+ RECT 441.490000 251.000000 442.490000 251.480000 ;
+ RECT 445.155000 251.000000 446.420000 251.480000 ;
+ RECT 625.320000 234.680000 626.420000 235.160000 ;
+ RECT 625.320000 240.120000 626.420000 240.600000 ;
+ RECT 638.130000 234.680000 639.130000 235.160000 ;
+ RECT 638.130000 240.120000 639.130000 240.600000 ;
+ RECT 638.130000 223.800000 639.130000 224.280000 ;
+ RECT 638.130000 229.240000 639.130000 229.720000 ;
+ RECT 625.320000 229.240000 626.420000 229.720000 ;
+ RECT 625.320000 223.800000 626.420000 224.280000 ;
+ RECT 625.320000 212.920000 626.420000 213.400000 ;
+ RECT 625.320000 218.360000 626.420000 218.840000 ;
+ RECT 638.130000 212.920000 639.130000 213.400000 ;
+ RECT 638.130000 218.360000 639.130000 218.840000 ;
+ RECT 638.130000 202.040000 639.130000 202.520000 ;
+ RECT 638.130000 196.600000 639.130000 197.080000 ;
+ RECT 638.130000 207.480000 639.130000 207.960000 ;
+ RECT 625.320000 207.480000 626.420000 207.960000 ;
+ RECT 625.320000 202.040000 626.420000 202.520000 ;
+ RECT 625.320000 196.600000 626.420000 197.080000 ;
+ RECT 580.320000 223.800000 581.420000 224.280000 ;
+ RECT 580.320000 229.240000 581.420000 229.720000 ;
+ RECT 580.320000 234.680000 581.420000 235.160000 ;
+ RECT 580.320000 240.120000 581.420000 240.600000 ;
+ RECT 580.320000 196.600000 581.420000 197.080000 ;
+ RECT 580.320000 202.040000 581.420000 202.520000 ;
+ RECT 580.320000 207.480000 581.420000 207.960000 ;
+ RECT 580.320000 212.920000 581.420000 213.400000 ;
+ RECT 580.320000 218.360000 581.420000 218.840000 ;
+ RECT 625.320000 185.720000 626.420000 186.200000 ;
+ RECT 625.320000 191.160000 626.420000 191.640000 ;
+ RECT 638.130000 185.720000 639.130000 186.200000 ;
+ RECT 638.130000 191.160000 639.130000 191.640000 ;
+ RECT 625.320000 174.840000 626.420000 175.320000 ;
+ RECT 625.320000 180.280000 626.420000 180.760000 ;
+ RECT 638.130000 174.840000 639.130000 175.320000 ;
+ RECT 638.130000 180.280000 639.130000 180.760000 ;
+ RECT 638.130000 163.960000 639.130000 164.440000 ;
+ RECT 638.130000 158.520000 639.130000 159.000000 ;
+ RECT 638.130000 169.400000 639.130000 169.880000 ;
+ RECT 625.320000 169.400000 626.420000 169.880000 ;
+ RECT 625.320000 163.960000 626.420000 164.440000 ;
+ RECT 625.320000 158.520000 626.420000 159.000000 ;
+ RECT 625.320000 153.080000 626.420000 153.560000 ;
+ RECT 638.130000 153.080000 639.130000 153.560000 ;
+ RECT 580.320000 174.840000 581.420000 175.320000 ;
+ RECT 580.320000 180.280000 581.420000 180.760000 ;
+ RECT 580.320000 185.720000 581.420000 186.200000 ;
+ RECT 580.320000 191.160000 581.420000 191.640000 ;
+ RECT 580.320000 153.080000 581.420000 153.560000 ;
+ RECT 580.320000 158.520000 581.420000 159.000000 ;
+ RECT 580.320000 163.960000 581.420000 164.440000 ;
+ RECT 580.320000 169.400000 581.420000 169.880000 ;
+ RECT 535.320000 223.800000 536.420000 224.280000 ;
+ RECT 535.320000 229.240000 536.420000 229.720000 ;
+ RECT 535.320000 234.680000 536.420000 235.160000 ;
+ RECT 535.320000 240.120000 536.420000 240.600000 ;
+ RECT 490.320000 223.800000 491.420000 224.280000 ;
+ RECT 490.320000 229.240000 491.420000 229.720000 ;
+ RECT 490.320000 234.680000 491.420000 235.160000 ;
+ RECT 490.320000 240.120000 491.420000 240.600000 ;
+ RECT 535.320000 196.600000 536.420000 197.080000 ;
+ RECT 535.320000 202.040000 536.420000 202.520000 ;
+ RECT 535.320000 207.480000 536.420000 207.960000 ;
+ RECT 535.320000 212.920000 536.420000 213.400000 ;
+ RECT 535.320000 218.360000 536.420000 218.840000 ;
+ RECT 490.320000 196.600000 491.420000 197.080000 ;
+ RECT 490.320000 202.040000 491.420000 202.520000 ;
+ RECT 490.320000 207.480000 491.420000 207.960000 ;
+ RECT 490.320000 212.920000 491.420000 213.400000 ;
+ RECT 490.320000 218.360000 491.420000 218.840000 ;
+ RECT 441.490000 240.120000 442.490000 240.600000 ;
+ RECT 445.155000 240.120000 446.420000 240.600000 ;
+ RECT 441.490000 234.680000 442.490000 235.160000 ;
+ RECT 445.155000 234.680000 446.420000 235.160000 ;
+ RECT 441.490000 229.240000 442.490000 229.720000 ;
+ RECT 445.155000 229.240000 446.420000 229.720000 ;
+ RECT 441.490000 223.800000 442.490000 224.280000 ;
+ RECT 445.155000 223.800000 446.420000 224.280000 ;
+ RECT 441.490000 218.360000 442.490000 218.840000 ;
+ RECT 445.155000 218.360000 446.420000 218.840000 ;
+ RECT 441.490000 212.920000 442.490000 213.400000 ;
+ RECT 445.155000 212.920000 446.420000 213.400000 ;
+ RECT 441.490000 202.040000 442.490000 202.520000 ;
+ RECT 445.155000 202.040000 446.420000 202.520000 ;
+ RECT 441.490000 207.480000 442.490000 207.960000 ;
+ RECT 445.155000 207.480000 446.420000 207.960000 ;
+ RECT 441.490000 196.600000 442.490000 197.080000 ;
+ RECT 445.155000 196.600000 446.420000 197.080000 ;
+ RECT 535.320000 174.840000 536.420000 175.320000 ;
+ RECT 535.320000 180.280000 536.420000 180.760000 ;
+ RECT 535.320000 185.720000 536.420000 186.200000 ;
+ RECT 535.320000 191.160000 536.420000 191.640000 ;
+ RECT 490.320000 174.840000 491.420000 175.320000 ;
+ RECT 490.320000 180.280000 491.420000 180.760000 ;
+ RECT 490.320000 185.720000 491.420000 186.200000 ;
+ RECT 490.320000 191.160000 491.420000 191.640000 ;
+ RECT 535.320000 153.080000 536.420000 153.560000 ;
+ RECT 535.320000 158.520000 536.420000 159.000000 ;
+ RECT 535.320000 163.960000 536.420000 164.440000 ;
+ RECT 535.320000 169.400000 536.420000 169.880000 ;
+ RECT 490.320000 153.080000 491.420000 153.560000 ;
+ RECT 490.320000 158.520000 491.420000 159.000000 ;
+ RECT 490.320000 163.960000 491.420000 164.440000 ;
+ RECT 490.320000 169.400000 491.420000 169.880000 ;
+ RECT 441.490000 191.160000 442.490000 191.640000 ;
+ RECT 445.155000 191.160000 446.420000 191.640000 ;
+ RECT 441.490000 185.720000 442.490000 186.200000 ;
+ RECT 445.155000 185.720000 446.420000 186.200000 ;
+ RECT 441.490000 180.280000 442.490000 180.760000 ;
+ RECT 445.155000 180.280000 446.420000 180.760000 ;
+ RECT 441.490000 174.840000 442.490000 175.320000 ;
+ RECT 445.155000 174.840000 446.420000 175.320000 ;
+ RECT 441.490000 169.400000 442.490000 169.880000 ;
+ RECT 445.155000 169.400000 446.420000 169.880000 ;
+ RECT 441.490000 158.520000 442.490000 159.000000 ;
+ RECT 445.155000 158.520000 446.420000 159.000000 ;
+ RECT 441.490000 163.960000 442.490000 164.440000 ;
+ RECT 445.155000 163.960000 446.420000 164.440000 ;
+ RECT 441.490000 153.080000 442.490000 153.560000 ;
+ RECT 445.155000 153.080000 446.420000 153.560000 ;
+ RECT 580.320000 245.560000 581.420000 246.040000 ;
+ RECT 625.320000 245.560000 626.420000 246.040000 ;
+ RECT 638.130000 245.560000 639.130000 246.040000 ;
+ RECT 490.320000 245.560000 491.420000 246.040000 ;
+ RECT 535.320000 245.560000 536.420000 246.040000 ;
+ RECT 441.490000 245.560000 442.490000 246.040000 ;
+ RECT 445.155000 245.560000 446.420000 246.040000 ;
+ RECT 440.260000 342.320000 640.360000 343.320000 ;
+ RECT 440.260000 146.750000 640.360000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 145.500000 442.490000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 344.760000 442.490000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 145.500000 639.130000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 344.760000 639.130000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 146.750000 441.260000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 146.750000 640.360000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 342.320000 441.260000 343.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 342.320000 640.360000 343.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 139.140000 446.420000 139.620000 ;
+ RECT 445.155000 133.700000 446.420000 134.180000 ;
+ RECT 445.155000 128.260000 446.420000 128.740000 ;
+ RECT 445.155000 122.820000 446.420000 123.300000 ;
+ RECT 441.490000 115.240000 442.490000 145.500000 ;
+ RECT 638.130000 115.240000 639.130000 145.500000 ;
+ RECT 445.320000 116.490000 446.420000 143.740000 ;
+ RECT 490.320000 116.490000 491.420000 143.740000 ;
+ RECT 535.320000 116.490000 536.420000 143.740000 ;
+ RECT 580.320000 116.490000 581.420000 143.740000 ;
+ RECT 625.320000 116.490000 626.420000 143.740000 ;
+ LAYER met3 ;
+ RECT 638.130000 139.140000 639.130000 139.620000 ;
+ RECT 638.130000 133.700000 639.130000 134.180000 ;
+ RECT 625.320000 139.140000 626.420000 139.620000 ;
+ RECT 625.320000 133.700000 626.420000 134.180000 ;
+ RECT 580.320000 133.700000 581.420000 134.180000 ;
+ RECT 580.320000 139.140000 581.420000 139.620000 ;
+ RECT 535.320000 133.700000 536.420000 134.180000 ;
+ RECT 490.320000 133.700000 491.420000 134.180000 ;
+ RECT 535.320000 139.140000 536.420000 139.620000 ;
+ RECT 490.320000 139.140000 491.420000 139.620000 ;
+ RECT 445.155000 139.140000 446.420000 139.620000 ;
+ RECT 441.490000 139.140000 442.490000 139.620000 ;
+ RECT 445.155000 133.700000 446.420000 134.180000 ;
+ RECT 441.490000 133.700000 442.490000 134.180000 ;
+ RECT 638.130000 128.260000 639.130000 128.740000 ;
+ RECT 638.130000 122.820000 639.130000 123.300000 ;
+ RECT 625.320000 128.260000 626.420000 128.740000 ;
+ RECT 625.320000 122.820000 626.420000 123.300000 ;
+ RECT 580.320000 122.820000 581.420000 123.300000 ;
+ RECT 580.320000 128.260000 581.420000 128.740000 ;
+ RECT 535.320000 122.820000 536.420000 123.300000 ;
+ RECT 490.320000 122.820000 491.420000 123.300000 ;
+ RECT 535.320000 128.260000 536.420000 128.740000 ;
+ RECT 490.320000 128.260000 491.420000 128.740000 ;
+ RECT 445.155000 128.260000 446.420000 128.740000 ;
+ RECT 441.490000 128.260000 442.490000 128.740000 ;
+ RECT 445.155000 122.820000 446.420000 123.300000 ;
+ RECT 441.490000 122.820000 442.490000 123.300000 ;
+ RECT 440.260000 142.740000 640.360000 143.740000 ;
+ RECT 440.260000 116.490000 640.360000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 116.490000 441.260000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 116.490000 640.360000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 142.740000 441.260000 143.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 142.740000 640.360000 143.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 115.240000 442.490000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 144.500000 442.490000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 115.240000 639.130000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 144.500000 639.130000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 3341.940000 446.420000 3342.420000 ;
+ RECT 445.155000 3331.060000 446.420000 3331.540000 ;
+ RECT 445.155000 3336.500000 446.420000 3336.980000 ;
+ RECT 445.155000 3325.620000 446.420000 3326.100000 ;
+ RECT 445.155000 3320.180000 446.420000 3320.660000 ;
+ RECT 445.155000 3314.740000 446.420000 3315.220000 ;
+ RECT 445.155000 3309.300000 446.420000 3309.780000 ;
+ RECT 445.155000 3303.860000 446.420000 3304.340000 ;
+ RECT 445.155000 3298.420000 446.420000 3298.900000 ;
+ RECT 445.155000 3287.540000 446.420000 3288.020000 ;
+ RECT 445.155000 3292.980000 446.420000 3293.460000 ;
+ RECT 445.155000 3282.100000 446.420000 3282.580000 ;
+ RECT 445.155000 3276.660000 446.420000 3277.140000 ;
+ RECT 445.155000 3271.220000 446.420000 3271.700000 ;
+ RECT 445.155000 3265.780000 446.420000 3266.260000 ;
+ RECT 445.155000 3260.340000 446.420000 3260.820000 ;
+ RECT 445.155000 3254.900000 446.420000 3255.380000 ;
+ RECT 445.155000 3244.020000 446.420000 3244.500000 ;
+ RECT 445.155000 3238.580000 446.420000 3239.060000 ;
+ RECT 445.155000 3233.140000 446.420000 3233.620000 ;
+ RECT 445.155000 3227.700000 446.420000 3228.180000 ;
+ RECT 445.155000 3222.260000 446.420000 3222.740000 ;
+ RECT 445.155000 3216.820000 446.420000 3217.300000 ;
+ RECT 445.155000 3205.940000 446.420000 3206.420000 ;
+ RECT 445.155000 3211.380000 446.420000 3211.860000 ;
+ RECT 445.155000 3200.500000 446.420000 3200.980000 ;
+ RECT 445.155000 3195.060000 446.420000 3195.540000 ;
+ RECT 445.155000 3189.620000 446.420000 3190.100000 ;
+ RECT 445.155000 3184.180000 446.420000 3184.660000 ;
+ RECT 445.155000 3178.740000 446.420000 3179.220000 ;
+ RECT 445.155000 3173.300000 446.420000 3173.780000 ;
+ RECT 445.155000 3162.420000 446.420000 3162.900000 ;
+ RECT 445.155000 3167.860000 446.420000 3168.340000 ;
+ RECT 445.155000 3156.980000 446.420000 3157.460000 ;
+ RECT 445.155000 3249.460000 446.420000 3249.940000 ;
+ RECT 625.320000 3150.650000 626.420000 3347.220000 ;
+ RECT 580.320000 3150.650000 581.420000 3347.220000 ;
+ RECT 638.130000 3149.400000 639.130000 3349.660000 ;
+ RECT 535.320000 3150.650000 536.420000 3347.220000 ;
+ RECT 490.320000 3150.650000 491.420000 3347.220000 ;
+ RECT 445.320000 3150.650000 446.420000 3347.220000 ;
+ RECT 441.490000 3149.400000 442.490000 3349.660000 ;
+ LAYER met3 ;
+ RECT 625.320000 3341.940000 626.420000 3342.420000 ;
+ RECT 638.130000 3341.940000 639.130000 3342.420000 ;
+ RECT 638.130000 3331.060000 639.130000 3331.540000 ;
+ RECT 638.130000 3325.620000 639.130000 3326.100000 ;
+ RECT 638.130000 3336.500000 639.130000 3336.980000 ;
+ RECT 625.320000 3336.500000 626.420000 3336.980000 ;
+ RECT 625.320000 3331.060000 626.420000 3331.540000 ;
+ RECT 625.320000 3325.620000 626.420000 3326.100000 ;
+ RECT 625.320000 3314.740000 626.420000 3315.220000 ;
+ RECT 625.320000 3320.180000 626.420000 3320.660000 ;
+ RECT 638.130000 3314.740000 639.130000 3315.220000 ;
+ RECT 638.130000 3320.180000 639.130000 3320.660000 ;
+ RECT 625.320000 3303.860000 626.420000 3304.340000 ;
+ RECT 625.320000 3309.300000 626.420000 3309.780000 ;
+ RECT 638.130000 3303.860000 639.130000 3304.340000 ;
+ RECT 638.130000 3309.300000 639.130000 3309.780000 ;
+ RECT 580.320000 3325.620000 581.420000 3326.100000 ;
+ RECT 580.320000 3331.060000 581.420000 3331.540000 ;
+ RECT 580.320000 3336.500000 581.420000 3336.980000 ;
+ RECT 580.320000 3341.940000 581.420000 3342.420000 ;
+ RECT 580.320000 3309.300000 581.420000 3309.780000 ;
+ RECT 580.320000 3303.860000 581.420000 3304.340000 ;
+ RECT 580.320000 3314.740000 581.420000 3315.220000 ;
+ RECT 580.320000 3320.180000 581.420000 3320.660000 ;
+ RECT 638.130000 3292.980000 639.130000 3293.460000 ;
+ RECT 638.130000 3287.540000 639.130000 3288.020000 ;
+ RECT 638.130000 3298.420000 639.130000 3298.900000 ;
+ RECT 625.320000 3298.420000 626.420000 3298.900000 ;
+ RECT 625.320000 3292.980000 626.420000 3293.460000 ;
+ RECT 625.320000 3287.540000 626.420000 3288.020000 ;
+ RECT 625.320000 3276.660000 626.420000 3277.140000 ;
+ RECT 625.320000 3282.100000 626.420000 3282.580000 ;
+ RECT 638.130000 3276.660000 639.130000 3277.140000 ;
+ RECT 638.130000 3282.100000 639.130000 3282.580000 ;
+ RECT 638.130000 3265.780000 639.130000 3266.260000 ;
+ RECT 638.130000 3271.220000 639.130000 3271.700000 ;
+ RECT 625.320000 3271.220000 626.420000 3271.700000 ;
+ RECT 625.320000 3265.780000 626.420000 3266.260000 ;
+ RECT 625.320000 3254.900000 626.420000 3255.380000 ;
+ RECT 625.320000 3260.340000 626.420000 3260.820000 ;
+ RECT 638.130000 3254.900000 639.130000 3255.380000 ;
+ RECT 638.130000 3260.340000 639.130000 3260.820000 ;
+ RECT 580.320000 3276.660000 581.420000 3277.140000 ;
+ RECT 580.320000 3282.100000 581.420000 3282.580000 ;
+ RECT 580.320000 3287.540000 581.420000 3288.020000 ;
+ RECT 580.320000 3292.980000 581.420000 3293.460000 ;
+ RECT 580.320000 3298.420000 581.420000 3298.900000 ;
+ RECT 580.320000 3254.900000 581.420000 3255.380000 ;
+ RECT 580.320000 3260.340000 581.420000 3260.820000 ;
+ RECT 580.320000 3265.780000 581.420000 3266.260000 ;
+ RECT 580.320000 3271.220000 581.420000 3271.700000 ;
+ RECT 535.320000 3331.060000 536.420000 3331.540000 ;
+ RECT 535.320000 3325.620000 536.420000 3326.100000 ;
+ RECT 535.320000 3336.500000 536.420000 3336.980000 ;
+ RECT 535.320000 3341.940000 536.420000 3342.420000 ;
+ RECT 490.320000 3325.620000 491.420000 3326.100000 ;
+ RECT 490.320000 3331.060000 491.420000 3331.540000 ;
+ RECT 490.320000 3336.500000 491.420000 3336.980000 ;
+ RECT 490.320000 3341.940000 491.420000 3342.420000 ;
+ RECT 535.320000 3303.860000 536.420000 3304.340000 ;
+ RECT 535.320000 3309.300000 536.420000 3309.780000 ;
+ RECT 535.320000 3314.740000 536.420000 3315.220000 ;
+ RECT 535.320000 3320.180000 536.420000 3320.660000 ;
+ RECT 490.320000 3303.860000 491.420000 3304.340000 ;
+ RECT 490.320000 3309.300000 491.420000 3309.780000 ;
+ RECT 490.320000 3314.740000 491.420000 3315.220000 ;
+ RECT 490.320000 3320.180000 491.420000 3320.660000 ;
+ RECT 441.490000 3341.940000 442.490000 3342.420000 ;
+ RECT 445.155000 3341.940000 446.420000 3342.420000 ;
+ RECT 441.490000 3331.060000 442.490000 3331.540000 ;
+ RECT 445.155000 3331.060000 446.420000 3331.540000 ;
+ RECT 441.490000 3336.500000 442.490000 3336.980000 ;
+ RECT 445.155000 3336.500000 446.420000 3336.980000 ;
+ RECT 441.490000 3325.620000 442.490000 3326.100000 ;
+ RECT 445.155000 3325.620000 446.420000 3326.100000 ;
+ RECT 441.490000 3320.180000 442.490000 3320.660000 ;
+ RECT 445.155000 3320.180000 446.420000 3320.660000 ;
+ RECT 441.490000 3314.740000 442.490000 3315.220000 ;
+ RECT 445.155000 3314.740000 446.420000 3315.220000 ;
+ RECT 441.490000 3309.300000 442.490000 3309.780000 ;
+ RECT 445.155000 3309.300000 446.420000 3309.780000 ;
+ RECT 441.490000 3303.860000 442.490000 3304.340000 ;
+ RECT 445.155000 3303.860000 446.420000 3304.340000 ;
+ RECT 535.320000 3276.660000 536.420000 3277.140000 ;
+ RECT 535.320000 3282.100000 536.420000 3282.580000 ;
+ RECT 535.320000 3287.540000 536.420000 3288.020000 ;
+ RECT 535.320000 3292.980000 536.420000 3293.460000 ;
+ RECT 535.320000 3298.420000 536.420000 3298.900000 ;
+ RECT 490.320000 3276.660000 491.420000 3277.140000 ;
+ RECT 490.320000 3282.100000 491.420000 3282.580000 ;
+ RECT 490.320000 3287.540000 491.420000 3288.020000 ;
+ RECT 490.320000 3292.980000 491.420000 3293.460000 ;
+ RECT 490.320000 3298.420000 491.420000 3298.900000 ;
+ RECT 535.320000 3254.900000 536.420000 3255.380000 ;
+ RECT 535.320000 3260.340000 536.420000 3260.820000 ;
+ RECT 535.320000 3265.780000 536.420000 3266.260000 ;
+ RECT 535.320000 3271.220000 536.420000 3271.700000 ;
+ RECT 490.320000 3254.900000 491.420000 3255.380000 ;
+ RECT 490.320000 3260.340000 491.420000 3260.820000 ;
+ RECT 490.320000 3265.780000 491.420000 3266.260000 ;
+ RECT 490.320000 3271.220000 491.420000 3271.700000 ;
+ RECT 441.490000 3298.420000 442.490000 3298.900000 ;
+ RECT 445.155000 3298.420000 446.420000 3298.900000 ;
+ RECT 441.490000 3287.540000 442.490000 3288.020000 ;
+ RECT 445.155000 3287.540000 446.420000 3288.020000 ;
+ RECT 441.490000 3292.980000 442.490000 3293.460000 ;
+ RECT 445.155000 3292.980000 446.420000 3293.460000 ;
+ RECT 441.490000 3282.100000 442.490000 3282.580000 ;
+ RECT 445.155000 3282.100000 446.420000 3282.580000 ;
+ RECT 441.490000 3276.660000 442.490000 3277.140000 ;
+ RECT 445.155000 3276.660000 446.420000 3277.140000 ;
+ RECT 441.490000 3271.220000 442.490000 3271.700000 ;
+ RECT 445.155000 3271.220000 446.420000 3271.700000 ;
+ RECT 441.490000 3265.780000 442.490000 3266.260000 ;
+ RECT 445.155000 3265.780000 446.420000 3266.260000 ;
+ RECT 441.490000 3260.340000 442.490000 3260.820000 ;
+ RECT 445.155000 3260.340000 446.420000 3260.820000 ;
+ RECT 441.490000 3254.900000 442.490000 3255.380000 ;
+ RECT 445.155000 3254.900000 446.420000 3255.380000 ;
+ RECT 625.320000 3238.580000 626.420000 3239.060000 ;
+ RECT 625.320000 3244.020000 626.420000 3244.500000 ;
+ RECT 638.130000 3238.580000 639.130000 3239.060000 ;
+ RECT 638.130000 3244.020000 639.130000 3244.500000 ;
+ RECT 638.130000 3227.700000 639.130000 3228.180000 ;
+ RECT 638.130000 3233.140000 639.130000 3233.620000 ;
+ RECT 625.320000 3233.140000 626.420000 3233.620000 ;
+ RECT 625.320000 3227.700000 626.420000 3228.180000 ;
+ RECT 625.320000 3216.820000 626.420000 3217.300000 ;
+ RECT 625.320000 3222.260000 626.420000 3222.740000 ;
+ RECT 638.130000 3216.820000 639.130000 3217.300000 ;
+ RECT 638.130000 3222.260000 639.130000 3222.740000 ;
+ RECT 638.130000 3205.940000 639.130000 3206.420000 ;
+ RECT 638.130000 3200.500000 639.130000 3200.980000 ;
+ RECT 638.130000 3211.380000 639.130000 3211.860000 ;
+ RECT 625.320000 3211.380000 626.420000 3211.860000 ;
+ RECT 625.320000 3205.940000 626.420000 3206.420000 ;
+ RECT 625.320000 3200.500000 626.420000 3200.980000 ;
+ RECT 580.320000 3227.700000 581.420000 3228.180000 ;
+ RECT 580.320000 3233.140000 581.420000 3233.620000 ;
+ RECT 580.320000 3238.580000 581.420000 3239.060000 ;
+ RECT 580.320000 3244.020000 581.420000 3244.500000 ;
+ RECT 580.320000 3200.500000 581.420000 3200.980000 ;
+ RECT 580.320000 3205.940000 581.420000 3206.420000 ;
+ RECT 580.320000 3211.380000 581.420000 3211.860000 ;
+ RECT 580.320000 3216.820000 581.420000 3217.300000 ;
+ RECT 580.320000 3222.260000 581.420000 3222.740000 ;
+ RECT 625.320000 3189.620000 626.420000 3190.100000 ;
+ RECT 625.320000 3195.060000 626.420000 3195.540000 ;
+ RECT 638.130000 3189.620000 639.130000 3190.100000 ;
+ RECT 638.130000 3195.060000 639.130000 3195.540000 ;
+ RECT 625.320000 3178.740000 626.420000 3179.220000 ;
+ RECT 625.320000 3184.180000 626.420000 3184.660000 ;
+ RECT 638.130000 3178.740000 639.130000 3179.220000 ;
+ RECT 638.130000 3184.180000 639.130000 3184.660000 ;
+ RECT 638.130000 3167.860000 639.130000 3168.340000 ;
+ RECT 638.130000 3162.420000 639.130000 3162.900000 ;
+ RECT 638.130000 3173.300000 639.130000 3173.780000 ;
+ RECT 625.320000 3173.300000 626.420000 3173.780000 ;
+ RECT 625.320000 3167.860000 626.420000 3168.340000 ;
+ RECT 625.320000 3162.420000 626.420000 3162.900000 ;
+ RECT 625.320000 3156.980000 626.420000 3157.460000 ;
+ RECT 638.130000 3156.980000 639.130000 3157.460000 ;
+ RECT 580.320000 3178.740000 581.420000 3179.220000 ;
+ RECT 580.320000 3184.180000 581.420000 3184.660000 ;
+ RECT 580.320000 3189.620000 581.420000 3190.100000 ;
+ RECT 580.320000 3195.060000 581.420000 3195.540000 ;
+ RECT 580.320000 3156.980000 581.420000 3157.460000 ;
+ RECT 580.320000 3162.420000 581.420000 3162.900000 ;
+ RECT 580.320000 3167.860000 581.420000 3168.340000 ;
+ RECT 580.320000 3173.300000 581.420000 3173.780000 ;
+ RECT 535.320000 3227.700000 536.420000 3228.180000 ;
+ RECT 535.320000 3233.140000 536.420000 3233.620000 ;
+ RECT 535.320000 3238.580000 536.420000 3239.060000 ;
+ RECT 535.320000 3244.020000 536.420000 3244.500000 ;
+ RECT 490.320000 3227.700000 491.420000 3228.180000 ;
+ RECT 490.320000 3233.140000 491.420000 3233.620000 ;
+ RECT 490.320000 3238.580000 491.420000 3239.060000 ;
+ RECT 490.320000 3244.020000 491.420000 3244.500000 ;
+ RECT 535.320000 3200.500000 536.420000 3200.980000 ;
+ RECT 535.320000 3205.940000 536.420000 3206.420000 ;
+ RECT 535.320000 3211.380000 536.420000 3211.860000 ;
+ RECT 535.320000 3216.820000 536.420000 3217.300000 ;
+ RECT 535.320000 3222.260000 536.420000 3222.740000 ;
+ RECT 490.320000 3200.500000 491.420000 3200.980000 ;
+ RECT 490.320000 3205.940000 491.420000 3206.420000 ;
+ RECT 490.320000 3211.380000 491.420000 3211.860000 ;
+ RECT 490.320000 3216.820000 491.420000 3217.300000 ;
+ RECT 490.320000 3222.260000 491.420000 3222.740000 ;
+ RECT 441.490000 3244.020000 442.490000 3244.500000 ;
+ RECT 445.155000 3244.020000 446.420000 3244.500000 ;
+ RECT 441.490000 3238.580000 442.490000 3239.060000 ;
+ RECT 445.155000 3238.580000 446.420000 3239.060000 ;
+ RECT 441.490000 3233.140000 442.490000 3233.620000 ;
+ RECT 445.155000 3233.140000 446.420000 3233.620000 ;
+ RECT 441.490000 3227.700000 442.490000 3228.180000 ;
+ RECT 445.155000 3227.700000 446.420000 3228.180000 ;
+ RECT 441.490000 3222.260000 442.490000 3222.740000 ;
+ RECT 445.155000 3222.260000 446.420000 3222.740000 ;
+ RECT 441.490000 3216.820000 442.490000 3217.300000 ;
+ RECT 445.155000 3216.820000 446.420000 3217.300000 ;
+ RECT 441.490000 3205.940000 442.490000 3206.420000 ;
+ RECT 445.155000 3205.940000 446.420000 3206.420000 ;
+ RECT 441.490000 3211.380000 442.490000 3211.860000 ;
+ RECT 445.155000 3211.380000 446.420000 3211.860000 ;
+ RECT 441.490000 3200.500000 442.490000 3200.980000 ;
+ RECT 445.155000 3200.500000 446.420000 3200.980000 ;
+ RECT 535.320000 3178.740000 536.420000 3179.220000 ;
+ RECT 535.320000 3184.180000 536.420000 3184.660000 ;
+ RECT 535.320000 3189.620000 536.420000 3190.100000 ;
+ RECT 535.320000 3195.060000 536.420000 3195.540000 ;
+ RECT 490.320000 3178.740000 491.420000 3179.220000 ;
+ RECT 490.320000 3184.180000 491.420000 3184.660000 ;
+ RECT 490.320000 3189.620000 491.420000 3190.100000 ;
+ RECT 490.320000 3195.060000 491.420000 3195.540000 ;
+ RECT 535.320000 3156.980000 536.420000 3157.460000 ;
+ RECT 535.320000 3162.420000 536.420000 3162.900000 ;
+ RECT 535.320000 3167.860000 536.420000 3168.340000 ;
+ RECT 535.320000 3173.300000 536.420000 3173.780000 ;
+ RECT 490.320000 3156.980000 491.420000 3157.460000 ;
+ RECT 490.320000 3162.420000 491.420000 3162.900000 ;
+ RECT 490.320000 3167.860000 491.420000 3168.340000 ;
+ RECT 490.320000 3173.300000 491.420000 3173.780000 ;
+ RECT 441.490000 3195.060000 442.490000 3195.540000 ;
+ RECT 445.155000 3195.060000 446.420000 3195.540000 ;
+ RECT 441.490000 3189.620000 442.490000 3190.100000 ;
+ RECT 445.155000 3189.620000 446.420000 3190.100000 ;
+ RECT 441.490000 3184.180000 442.490000 3184.660000 ;
+ RECT 445.155000 3184.180000 446.420000 3184.660000 ;
+ RECT 441.490000 3178.740000 442.490000 3179.220000 ;
+ RECT 445.155000 3178.740000 446.420000 3179.220000 ;
+ RECT 441.490000 3173.300000 442.490000 3173.780000 ;
+ RECT 445.155000 3173.300000 446.420000 3173.780000 ;
+ RECT 441.490000 3162.420000 442.490000 3162.900000 ;
+ RECT 445.155000 3162.420000 446.420000 3162.900000 ;
+ RECT 441.490000 3167.860000 442.490000 3168.340000 ;
+ RECT 445.155000 3167.860000 446.420000 3168.340000 ;
+ RECT 441.490000 3156.980000 442.490000 3157.460000 ;
+ RECT 445.155000 3156.980000 446.420000 3157.460000 ;
+ RECT 580.320000 3249.460000 581.420000 3249.940000 ;
+ RECT 625.320000 3249.460000 626.420000 3249.940000 ;
+ RECT 638.130000 3249.460000 639.130000 3249.940000 ;
+ RECT 490.320000 3249.460000 491.420000 3249.940000 ;
+ RECT 535.320000 3249.460000 536.420000 3249.940000 ;
+ RECT 441.490000 3249.460000 442.490000 3249.940000 ;
+ RECT 445.155000 3249.460000 446.420000 3249.940000 ;
+ RECT 440.260000 3346.220000 640.360000 3347.220000 ;
+ RECT 440.260000 3150.650000 640.360000 3151.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 3149.400000 442.490000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 3348.660000 442.490000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 3149.400000 639.130000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 3348.660000 639.130000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 3150.650000 441.260000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 3150.650000 640.360000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 3346.220000 441.260000 3347.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 3346.220000 640.360000 3347.220000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 3141.680000 446.420000 3142.160000 ;
+ RECT 445.155000 3130.800000 446.420000 3131.280000 ;
+ RECT 445.155000 3136.240000 446.420000 3136.720000 ;
+ RECT 445.155000 3125.360000 446.420000 3125.840000 ;
+ RECT 445.155000 3119.920000 446.420000 3120.400000 ;
+ RECT 445.155000 3114.480000 446.420000 3114.960000 ;
+ RECT 445.155000 3109.040000 446.420000 3109.520000 ;
+ RECT 445.155000 3103.600000 446.420000 3104.080000 ;
+ RECT 445.155000 3098.160000 446.420000 3098.640000 ;
+ RECT 445.155000 3087.280000 446.420000 3087.760000 ;
+ RECT 445.155000 3092.720000 446.420000 3093.200000 ;
+ RECT 445.155000 3081.840000 446.420000 3082.320000 ;
+ RECT 445.155000 3076.400000 446.420000 3076.880000 ;
+ RECT 445.155000 3070.960000 446.420000 3071.440000 ;
+ RECT 445.155000 3065.520000 446.420000 3066.000000 ;
+ RECT 445.155000 3060.080000 446.420000 3060.560000 ;
+ RECT 445.155000 3054.640000 446.420000 3055.120000 ;
+ RECT 445.155000 3043.760000 446.420000 3044.240000 ;
+ RECT 445.155000 3038.320000 446.420000 3038.800000 ;
+ RECT 445.155000 3032.880000 446.420000 3033.360000 ;
+ RECT 445.155000 3027.440000 446.420000 3027.920000 ;
+ RECT 445.155000 3022.000000 446.420000 3022.480000 ;
+ RECT 445.155000 3016.560000 446.420000 3017.040000 ;
+ RECT 445.155000 3005.680000 446.420000 3006.160000 ;
+ RECT 445.155000 3011.120000 446.420000 3011.600000 ;
+ RECT 445.155000 3000.240000 446.420000 3000.720000 ;
+ RECT 445.155000 2994.800000 446.420000 2995.280000 ;
+ RECT 445.155000 2989.360000 446.420000 2989.840000 ;
+ RECT 445.155000 2983.920000 446.420000 2984.400000 ;
+ RECT 445.155000 2978.480000 446.420000 2978.960000 ;
+ RECT 445.155000 2973.040000 446.420000 2973.520000 ;
+ RECT 445.155000 2962.160000 446.420000 2962.640000 ;
+ RECT 445.155000 2967.600000 446.420000 2968.080000 ;
+ RECT 445.155000 2956.720000 446.420000 2957.200000 ;
+ RECT 445.155000 3049.200000 446.420000 3049.680000 ;
+ RECT 625.320000 2950.390000 626.420000 3146.960000 ;
+ RECT 580.320000 2950.390000 581.420000 3146.960000 ;
+ RECT 638.130000 2949.140000 639.130000 3149.400000 ;
+ RECT 535.320000 2950.390000 536.420000 3146.960000 ;
+ RECT 490.320000 2950.390000 491.420000 3146.960000 ;
+ RECT 445.320000 2950.390000 446.420000 3146.960000 ;
+ RECT 441.490000 2949.140000 442.490000 3149.400000 ;
+ LAYER met3 ;
+ RECT 625.320000 3141.680000 626.420000 3142.160000 ;
+ RECT 638.130000 3141.680000 639.130000 3142.160000 ;
+ RECT 638.130000 3130.800000 639.130000 3131.280000 ;
+ RECT 638.130000 3125.360000 639.130000 3125.840000 ;
+ RECT 638.130000 3136.240000 639.130000 3136.720000 ;
+ RECT 625.320000 3136.240000 626.420000 3136.720000 ;
+ RECT 625.320000 3130.800000 626.420000 3131.280000 ;
+ RECT 625.320000 3125.360000 626.420000 3125.840000 ;
+ RECT 625.320000 3114.480000 626.420000 3114.960000 ;
+ RECT 625.320000 3119.920000 626.420000 3120.400000 ;
+ RECT 638.130000 3114.480000 639.130000 3114.960000 ;
+ RECT 638.130000 3119.920000 639.130000 3120.400000 ;
+ RECT 625.320000 3103.600000 626.420000 3104.080000 ;
+ RECT 625.320000 3109.040000 626.420000 3109.520000 ;
+ RECT 638.130000 3103.600000 639.130000 3104.080000 ;
+ RECT 638.130000 3109.040000 639.130000 3109.520000 ;
+ RECT 580.320000 3125.360000 581.420000 3125.840000 ;
+ RECT 580.320000 3130.800000 581.420000 3131.280000 ;
+ RECT 580.320000 3136.240000 581.420000 3136.720000 ;
+ RECT 580.320000 3141.680000 581.420000 3142.160000 ;
+ RECT 580.320000 3109.040000 581.420000 3109.520000 ;
+ RECT 580.320000 3103.600000 581.420000 3104.080000 ;
+ RECT 580.320000 3114.480000 581.420000 3114.960000 ;
+ RECT 580.320000 3119.920000 581.420000 3120.400000 ;
+ RECT 638.130000 3092.720000 639.130000 3093.200000 ;
+ RECT 638.130000 3087.280000 639.130000 3087.760000 ;
+ RECT 638.130000 3098.160000 639.130000 3098.640000 ;
+ RECT 625.320000 3098.160000 626.420000 3098.640000 ;
+ RECT 625.320000 3092.720000 626.420000 3093.200000 ;
+ RECT 625.320000 3087.280000 626.420000 3087.760000 ;
+ RECT 625.320000 3076.400000 626.420000 3076.880000 ;
+ RECT 625.320000 3081.840000 626.420000 3082.320000 ;
+ RECT 638.130000 3076.400000 639.130000 3076.880000 ;
+ RECT 638.130000 3081.840000 639.130000 3082.320000 ;
+ RECT 638.130000 3065.520000 639.130000 3066.000000 ;
+ RECT 638.130000 3070.960000 639.130000 3071.440000 ;
+ RECT 625.320000 3070.960000 626.420000 3071.440000 ;
+ RECT 625.320000 3065.520000 626.420000 3066.000000 ;
+ RECT 625.320000 3054.640000 626.420000 3055.120000 ;
+ RECT 625.320000 3060.080000 626.420000 3060.560000 ;
+ RECT 638.130000 3054.640000 639.130000 3055.120000 ;
+ RECT 638.130000 3060.080000 639.130000 3060.560000 ;
+ RECT 580.320000 3076.400000 581.420000 3076.880000 ;
+ RECT 580.320000 3081.840000 581.420000 3082.320000 ;
+ RECT 580.320000 3087.280000 581.420000 3087.760000 ;
+ RECT 580.320000 3092.720000 581.420000 3093.200000 ;
+ RECT 580.320000 3098.160000 581.420000 3098.640000 ;
+ RECT 580.320000 3054.640000 581.420000 3055.120000 ;
+ RECT 580.320000 3060.080000 581.420000 3060.560000 ;
+ RECT 580.320000 3065.520000 581.420000 3066.000000 ;
+ RECT 580.320000 3070.960000 581.420000 3071.440000 ;
+ RECT 535.320000 3130.800000 536.420000 3131.280000 ;
+ RECT 535.320000 3125.360000 536.420000 3125.840000 ;
+ RECT 535.320000 3136.240000 536.420000 3136.720000 ;
+ RECT 535.320000 3141.680000 536.420000 3142.160000 ;
+ RECT 490.320000 3125.360000 491.420000 3125.840000 ;
+ RECT 490.320000 3130.800000 491.420000 3131.280000 ;
+ RECT 490.320000 3136.240000 491.420000 3136.720000 ;
+ RECT 490.320000 3141.680000 491.420000 3142.160000 ;
+ RECT 535.320000 3103.600000 536.420000 3104.080000 ;
+ RECT 535.320000 3109.040000 536.420000 3109.520000 ;
+ RECT 535.320000 3114.480000 536.420000 3114.960000 ;
+ RECT 535.320000 3119.920000 536.420000 3120.400000 ;
+ RECT 490.320000 3103.600000 491.420000 3104.080000 ;
+ RECT 490.320000 3109.040000 491.420000 3109.520000 ;
+ RECT 490.320000 3114.480000 491.420000 3114.960000 ;
+ RECT 490.320000 3119.920000 491.420000 3120.400000 ;
+ RECT 441.490000 3141.680000 442.490000 3142.160000 ;
+ RECT 445.155000 3141.680000 446.420000 3142.160000 ;
+ RECT 441.490000 3130.800000 442.490000 3131.280000 ;
+ RECT 445.155000 3130.800000 446.420000 3131.280000 ;
+ RECT 441.490000 3136.240000 442.490000 3136.720000 ;
+ RECT 445.155000 3136.240000 446.420000 3136.720000 ;
+ RECT 441.490000 3125.360000 442.490000 3125.840000 ;
+ RECT 445.155000 3125.360000 446.420000 3125.840000 ;
+ RECT 441.490000 3119.920000 442.490000 3120.400000 ;
+ RECT 445.155000 3119.920000 446.420000 3120.400000 ;
+ RECT 441.490000 3114.480000 442.490000 3114.960000 ;
+ RECT 445.155000 3114.480000 446.420000 3114.960000 ;
+ RECT 441.490000 3109.040000 442.490000 3109.520000 ;
+ RECT 445.155000 3109.040000 446.420000 3109.520000 ;
+ RECT 441.490000 3103.600000 442.490000 3104.080000 ;
+ RECT 445.155000 3103.600000 446.420000 3104.080000 ;
+ RECT 535.320000 3076.400000 536.420000 3076.880000 ;
+ RECT 535.320000 3081.840000 536.420000 3082.320000 ;
+ RECT 535.320000 3087.280000 536.420000 3087.760000 ;
+ RECT 535.320000 3092.720000 536.420000 3093.200000 ;
+ RECT 535.320000 3098.160000 536.420000 3098.640000 ;
+ RECT 490.320000 3076.400000 491.420000 3076.880000 ;
+ RECT 490.320000 3081.840000 491.420000 3082.320000 ;
+ RECT 490.320000 3087.280000 491.420000 3087.760000 ;
+ RECT 490.320000 3092.720000 491.420000 3093.200000 ;
+ RECT 490.320000 3098.160000 491.420000 3098.640000 ;
+ RECT 535.320000 3054.640000 536.420000 3055.120000 ;
+ RECT 535.320000 3060.080000 536.420000 3060.560000 ;
+ RECT 535.320000 3065.520000 536.420000 3066.000000 ;
+ RECT 535.320000 3070.960000 536.420000 3071.440000 ;
+ RECT 490.320000 3054.640000 491.420000 3055.120000 ;
+ RECT 490.320000 3060.080000 491.420000 3060.560000 ;
+ RECT 490.320000 3065.520000 491.420000 3066.000000 ;
+ RECT 490.320000 3070.960000 491.420000 3071.440000 ;
+ RECT 441.490000 3098.160000 442.490000 3098.640000 ;
+ RECT 445.155000 3098.160000 446.420000 3098.640000 ;
+ RECT 441.490000 3087.280000 442.490000 3087.760000 ;
+ RECT 445.155000 3087.280000 446.420000 3087.760000 ;
+ RECT 441.490000 3092.720000 442.490000 3093.200000 ;
+ RECT 445.155000 3092.720000 446.420000 3093.200000 ;
+ RECT 441.490000 3081.840000 442.490000 3082.320000 ;
+ RECT 445.155000 3081.840000 446.420000 3082.320000 ;
+ RECT 441.490000 3076.400000 442.490000 3076.880000 ;
+ RECT 445.155000 3076.400000 446.420000 3076.880000 ;
+ RECT 441.490000 3070.960000 442.490000 3071.440000 ;
+ RECT 445.155000 3070.960000 446.420000 3071.440000 ;
+ RECT 441.490000 3065.520000 442.490000 3066.000000 ;
+ RECT 445.155000 3065.520000 446.420000 3066.000000 ;
+ RECT 441.490000 3060.080000 442.490000 3060.560000 ;
+ RECT 445.155000 3060.080000 446.420000 3060.560000 ;
+ RECT 441.490000 3054.640000 442.490000 3055.120000 ;
+ RECT 445.155000 3054.640000 446.420000 3055.120000 ;
+ RECT 625.320000 3038.320000 626.420000 3038.800000 ;
+ RECT 625.320000 3043.760000 626.420000 3044.240000 ;
+ RECT 638.130000 3038.320000 639.130000 3038.800000 ;
+ RECT 638.130000 3043.760000 639.130000 3044.240000 ;
+ RECT 638.130000 3027.440000 639.130000 3027.920000 ;
+ RECT 638.130000 3032.880000 639.130000 3033.360000 ;
+ RECT 625.320000 3032.880000 626.420000 3033.360000 ;
+ RECT 625.320000 3027.440000 626.420000 3027.920000 ;
+ RECT 625.320000 3016.560000 626.420000 3017.040000 ;
+ RECT 625.320000 3022.000000 626.420000 3022.480000 ;
+ RECT 638.130000 3016.560000 639.130000 3017.040000 ;
+ RECT 638.130000 3022.000000 639.130000 3022.480000 ;
+ RECT 638.130000 3005.680000 639.130000 3006.160000 ;
+ RECT 638.130000 3000.240000 639.130000 3000.720000 ;
+ RECT 638.130000 3011.120000 639.130000 3011.600000 ;
+ RECT 625.320000 3011.120000 626.420000 3011.600000 ;
+ RECT 625.320000 3005.680000 626.420000 3006.160000 ;
+ RECT 625.320000 3000.240000 626.420000 3000.720000 ;
+ RECT 580.320000 3027.440000 581.420000 3027.920000 ;
+ RECT 580.320000 3032.880000 581.420000 3033.360000 ;
+ RECT 580.320000 3038.320000 581.420000 3038.800000 ;
+ RECT 580.320000 3043.760000 581.420000 3044.240000 ;
+ RECT 580.320000 3000.240000 581.420000 3000.720000 ;
+ RECT 580.320000 3005.680000 581.420000 3006.160000 ;
+ RECT 580.320000 3011.120000 581.420000 3011.600000 ;
+ RECT 580.320000 3016.560000 581.420000 3017.040000 ;
+ RECT 580.320000 3022.000000 581.420000 3022.480000 ;
+ RECT 625.320000 2989.360000 626.420000 2989.840000 ;
+ RECT 625.320000 2994.800000 626.420000 2995.280000 ;
+ RECT 638.130000 2989.360000 639.130000 2989.840000 ;
+ RECT 638.130000 2994.800000 639.130000 2995.280000 ;
+ RECT 625.320000 2978.480000 626.420000 2978.960000 ;
+ RECT 625.320000 2983.920000 626.420000 2984.400000 ;
+ RECT 638.130000 2978.480000 639.130000 2978.960000 ;
+ RECT 638.130000 2983.920000 639.130000 2984.400000 ;
+ RECT 638.130000 2967.600000 639.130000 2968.080000 ;
+ RECT 638.130000 2962.160000 639.130000 2962.640000 ;
+ RECT 638.130000 2973.040000 639.130000 2973.520000 ;
+ RECT 625.320000 2973.040000 626.420000 2973.520000 ;
+ RECT 625.320000 2967.600000 626.420000 2968.080000 ;
+ RECT 625.320000 2962.160000 626.420000 2962.640000 ;
+ RECT 625.320000 2956.720000 626.420000 2957.200000 ;
+ RECT 638.130000 2956.720000 639.130000 2957.200000 ;
+ RECT 580.320000 2978.480000 581.420000 2978.960000 ;
+ RECT 580.320000 2983.920000 581.420000 2984.400000 ;
+ RECT 580.320000 2989.360000 581.420000 2989.840000 ;
+ RECT 580.320000 2994.800000 581.420000 2995.280000 ;
+ RECT 580.320000 2956.720000 581.420000 2957.200000 ;
+ RECT 580.320000 2962.160000 581.420000 2962.640000 ;
+ RECT 580.320000 2967.600000 581.420000 2968.080000 ;
+ RECT 580.320000 2973.040000 581.420000 2973.520000 ;
+ RECT 535.320000 3027.440000 536.420000 3027.920000 ;
+ RECT 535.320000 3032.880000 536.420000 3033.360000 ;
+ RECT 535.320000 3038.320000 536.420000 3038.800000 ;
+ RECT 535.320000 3043.760000 536.420000 3044.240000 ;
+ RECT 490.320000 3027.440000 491.420000 3027.920000 ;
+ RECT 490.320000 3032.880000 491.420000 3033.360000 ;
+ RECT 490.320000 3038.320000 491.420000 3038.800000 ;
+ RECT 490.320000 3043.760000 491.420000 3044.240000 ;
+ RECT 535.320000 3000.240000 536.420000 3000.720000 ;
+ RECT 535.320000 3005.680000 536.420000 3006.160000 ;
+ RECT 535.320000 3011.120000 536.420000 3011.600000 ;
+ RECT 535.320000 3016.560000 536.420000 3017.040000 ;
+ RECT 535.320000 3022.000000 536.420000 3022.480000 ;
+ RECT 490.320000 3000.240000 491.420000 3000.720000 ;
+ RECT 490.320000 3005.680000 491.420000 3006.160000 ;
+ RECT 490.320000 3011.120000 491.420000 3011.600000 ;
+ RECT 490.320000 3016.560000 491.420000 3017.040000 ;
+ RECT 490.320000 3022.000000 491.420000 3022.480000 ;
+ RECT 441.490000 3043.760000 442.490000 3044.240000 ;
+ RECT 445.155000 3043.760000 446.420000 3044.240000 ;
+ RECT 441.490000 3038.320000 442.490000 3038.800000 ;
+ RECT 445.155000 3038.320000 446.420000 3038.800000 ;
+ RECT 441.490000 3032.880000 442.490000 3033.360000 ;
+ RECT 445.155000 3032.880000 446.420000 3033.360000 ;
+ RECT 441.490000 3027.440000 442.490000 3027.920000 ;
+ RECT 445.155000 3027.440000 446.420000 3027.920000 ;
+ RECT 441.490000 3022.000000 442.490000 3022.480000 ;
+ RECT 445.155000 3022.000000 446.420000 3022.480000 ;
+ RECT 441.490000 3016.560000 442.490000 3017.040000 ;
+ RECT 445.155000 3016.560000 446.420000 3017.040000 ;
+ RECT 441.490000 3005.680000 442.490000 3006.160000 ;
+ RECT 445.155000 3005.680000 446.420000 3006.160000 ;
+ RECT 441.490000 3011.120000 442.490000 3011.600000 ;
+ RECT 445.155000 3011.120000 446.420000 3011.600000 ;
+ RECT 441.490000 3000.240000 442.490000 3000.720000 ;
+ RECT 445.155000 3000.240000 446.420000 3000.720000 ;
+ RECT 535.320000 2978.480000 536.420000 2978.960000 ;
+ RECT 535.320000 2983.920000 536.420000 2984.400000 ;
+ RECT 535.320000 2989.360000 536.420000 2989.840000 ;
+ RECT 535.320000 2994.800000 536.420000 2995.280000 ;
+ RECT 490.320000 2978.480000 491.420000 2978.960000 ;
+ RECT 490.320000 2983.920000 491.420000 2984.400000 ;
+ RECT 490.320000 2989.360000 491.420000 2989.840000 ;
+ RECT 490.320000 2994.800000 491.420000 2995.280000 ;
+ RECT 535.320000 2956.720000 536.420000 2957.200000 ;
+ RECT 535.320000 2962.160000 536.420000 2962.640000 ;
+ RECT 535.320000 2967.600000 536.420000 2968.080000 ;
+ RECT 535.320000 2973.040000 536.420000 2973.520000 ;
+ RECT 490.320000 2956.720000 491.420000 2957.200000 ;
+ RECT 490.320000 2962.160000 491.420000 2962.640000 ;
+ RECT 490.320000 2967.600000 491.420000 2968.080000 ;
+ RECT 490.320000 2973.040000 491.420000 2973.520000 ;
+ RECT 441.490000 2994.800000 442.490000 2995.280000 ;
+ RECT 445.155000 2994.800000 446.420000 2995.280000 ;
+ RECT 441.490000 2989.360000 442.490000 2989.840000 ;
+ RECT 445.155000 2989.360000 446.420000 2989.840000 ;
+ RECT 441.490000 2983.920000 442.490000 2984.400000 ;
+ RECT 445.155000 2983.920000 446.420000 2984.400000 ;
+ RECT 441.490000 2978.480000 442.490000 2978.960000 ;
+ RECT 445.155000 2978.480000 446.420000 2978.960000 ;
+ RECT 441.490000 2973.040000 442.490000 2973.520000 ;
+ RECT 445.155000 2973.040000 446.420000 2973.520000 ;
+ RECT 441.490000 2962.160000 442.490000 2962.640000 ;
+ RECT 445.155000 2962.160000 446.420000 2962.640000 ;
+ RECT 441.490000 2967.600000 442.490000 2968.080000 ;
+ RECT 445.155000 2967.600000 446.420000 2968.080000 ;
+ RECT 441.490000 2956.720000 442.490000 2957.200000 ;
+ RECT 445.155000 2956.720000 446.420000 2957.200000 ;
+ RECT 580.320000 3049.200000 581.420000 3049.680000 ;
+ RECT 625.320000 3049.200000 626.420000 3049.680000 ;
+ RECT 638.130000 3049.200000 639.130000 3049.680000 ;
+ RECT 490.320000 3049.200000 491.420000 3049.680000 ;
+ RECT 535.320000 3049.200000 536.420000 3049.680000 ;
+ RECT 441.490000 3049.200000 442.490000 3049.680000 ;
+ RECT 445.155000 3049.200000 446.420000 3049.680000 ;
+ RECT 440.260000 3145.960000 640.360000 3146.960000 ;
+ RECT 440.260000 2950.390000 640.360000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 2949.140000 442.490000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 3148.400000 442.490000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 2949.140000 639.130000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 3148.400000 639.130000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2950.390000 441.260000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2950.390000 640.360000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 3145.960000 441.260000 3146.960000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 3145.960000 640.360000 3146.960000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 2941.420000 446.420000 2941.900000 ;
+ RECT 445.155000 2930.540000 446.420000 2931.020000 ;
+ RECT 445.155000 2935.980000 446.420000 2936.460000 ;
+ RECT 445.155000 2925.100000 446.420000 2925.580000 ;
+ RECT 445.155000 2919.660000 446.420000 2920.140000 ;
+ RECT 445.155000 2914.220000 446.420000 2914.700000 ;
+ RECT 445.155000 2908.780000 446.420000 2909.260000 ;
+ RECT 445.155000 2903.340000 446.420000 2903.820000 ;
+ RECT 445.155000 2897.900000 446.420000 2898.380000 ;
+ RECT 445.155000 2887.020000 446.420000 2887.500000 ;
+ RECT 445.155000 2892.460000 446.420000 2892.940000 ;
+ RECT 445.155000 2881.580000 446.420000 2882.060000 ;
+ RECT 445.155000 2876.140000 446.420000 2876.620000 ;
+ RECT 445.155000 2870.700000 446.420000 2871.180000 ;
+ RECT 445.155000 2865.260000 446.420000 2865.740000 ;
+ RECT 445.155000 2859.820000 446.420000 2860.300000 ;
+ RECT 445.155000 2854.380000 446.420000 2854.860000 ;
+ RECT 445.155000 2843.500000 446.420000 2843.980000 ;
+ RECT 445.155000 2838.060000 446.420000 2838.540000 ;
+ RECT 445.155000 2832.620000 446.420000 2833.100000 ;
+ RECT 445.155000 2827.180000 446.420000 2827.660000 ;
+ RECT 445.155000 2821.740000 446.420000 2822.220000 ;
+ RECT 445.155000 2816.300000 446.420000 2816.780000 ;
+ RECT 445.155000 2805.420000 446.420000 2805.900000 ;
+ RECT 445.155000 2810.860000 446.420000 2811.340000 ;
+ RECT 445.155000 2799.980000 446.420000 2800.460000 ;
+ RECT 445.155000 2794.540000 446.420000 2795.020000 ;
+ RECT 445.155000 2789.100000 446.420000 2789.580000 ;
+ RECT 445.155000 2783.660000 446.420000 2784.140000 ;
+ RECT 445.155000 2778.220000 446.420000 2778.700000 ;
+ RECT 445.155000 2772.780000 446.420000 2773.260000 ;
+ RECT 445.155000 2761.900000 446.420000 2762.380000 ;
+ RECT 445.155000 2767.340000 446.420000 2767.820000 ;
+ RECT 445.155000 2756.460000 446.420000 2756.940000 ;
+ RECT 445.155000 2848.940000 446.420000 2849.420000 ;
+ RECT 625.320000 2750.130000 626.420000 2946.700000 ;
+ RECT 580.320000 2750.130000 581.420000 2946.700000 ;
+ RECT 638.130000 2748.880000 639.130000 2949.140000 ;
+ RECT 535.320000 2750.130000 536.420000 2946.700000 ;
+ RECT 490.320000 2750.130000 491.420000 2946.700000 ;
+ RECT 445.320000 2750.130000 446.420000 2946.700000 ;
+ RECT 441.490000 2748.880000 442.490000 2949.140000 ;
+ LAYER met3 ;
+ RECT 625.320000 2941.420000 626.420000 2941.900000 ;
+ RECT 638.130000 2941.420000 639.130000 2941.900000 ;
+ RECT 638.130000 2930.540000 639.130000 2931.020000 ;
+ RECT 638.130000 2925.100000 639.130000 2925.580000 ;
+ RECT 638.130000 2935.980000 639.130000 2936.460000 ;
+ RECT 625.320000 2935.980000 626.420000 2936.460000 ;
+ RECT 625.320000 2930.540000 626.420000 2931.020000 ;
+ RECT 625.320000 2925.100000 626.420000 2925.580000 ;
+ RECT 625.320000 2914.220000 626.420000 2914.700000 ;
+ RECT 625.320000 2919.660000 626.420000 2920.140000 ;
+ RECT 638.130000 2914.220000 639.130000 2914.700000 ;
+ RECT 638.130000 2919.660000 639.130000 2920.140000 ;
+ RECT 625.320000 2903.340000 626.420000 2903.820000 ;
+ RECT 625.320000 2908.780000 626.420000 2909.260000 ;
+ RECT 638.130000 2903.340000 639.130000 2903.820000 ;
+ RECT 638.130000 2908.780000 639.130000 2909.260000 ;
+ RECT 580.320000 2925.100000 581.420000 2925.580000 ;
+ RECT 580.320000 2930.540000 581.420000 2931.020000 ;
+ RECT 580.320000 2935.980000 581.420000 2936.460000 ;
+ RECT 580.320000 2941.420000 581.420000 2941.900000 ;
+ RECT 580.320000 2908.780000 581.420000 2909.260000 ;
+ RECT 580.320000 2903.340000 581.420000 2903.820000 ;
+ RECT 580.320000 2914.220000 581.420000 2914.700000 ;
+ RECT 580.320000 2919.660000 581.420000 2920.140000 ;
+ RECT 638.130000 2892.460000 639.130000 2892.940000 ;
+ RECT 638.130000 2887.020000 639.130000 2887.500000 ;
+ RECT 638.130000 2897.900000 639.130000 2898.380000 ;
+ RECT 625.320000 2897.900000 626.420000 2898.380000 ;
+ RECT 625.320000 2892.460000 626.420000 2892.940000 ;
+ RECT 625.320000 2887.020000 626.420000 2887.500000 ;
+ RECT 625.320000 2876.140000 626.420000 2876.620000 ;
+ RECT 625.320000 2881.580000 626.420000 2882.060000 ;
+ RECT 638.130000 2876.140000 639.130000 2876.620000 ;
+ RECT 638.130000 2881.580000 639.130000 2882.060000 ;
+ RECT 638.130000 2865.260000 639.130000 2865.740000 ;
+ RECT 638.130000 2870.700000 639.130000 2871.180000 ;
+ RECT 625.320000 2870.700000 626.420000 2871.180000 ;
+ RECT 625.320000 2865.260000 626.420000 2865.740000 ;
+ RECT 625.320000 2854.380000 626.420000 2854.860000 ;
+ RECT 625.320000 2859.820000 626.420000 2860.300000 ;
+ RECT 638.130000 2854.380000 639.130000 2854.860000 ;
+ RECT 638.130000 2859.820000 639.130000 2860.300000 ;
+ RECT 580.320000 2876.140000 581.420000 2876.620000 ;
+ RECT 580.320000 2881.580000 581.420000 2882.060000 ;
+ RECT 580.320000 2887.020000 581.420000 2887.500000 ;
+ RECT 580.320000 2892.460000 581.420000 2892.940000 ;
+ RECT 580.320000 2897.900000 581.420000 2898.380000 ;
+ RECT 580.320000 2854.380000 581.420000 2854.860000 ;
+ RECT 580.320000 2859.820000 581.420000 2860.300000 ;
+ RECT 580.320000 2865.260000 581.420000 2865.740000 ;
+ RECT 580.320000 2870.700000 581.420000 2871.180000 ;
+ RECT 535.320000 2930.540000 536.420000 2931.020000 ;
+ RECT 535.320000 2925.100000 536.420000 2925.580000 ;
+ RECT 535.320000 2935.980000 536.420000 2936.460000 ;
+ RECT 535.320000 2941.420000 536.420000 2941.900000 ;
+ RECT 490.320000 2925.100000 491.420000 2925.580000 ;
+ RECT 490.320000 2930.540000 491.420000 2931.020000 ;
+ RECT 490.320000 2935.980000 491.420000 2936.460000 ;
+ RECT 490.320000 2941.420000 491.420000 2941.900000 ;
+ RECT 535.320000 2903.340000 536.420000 2903.820000 ;
+ RECT 535.320000 2908.780000 536.420000 2909.260000 ;
+ RECT 535.320000 2914.220000 536.420000 2914.700000 ;
+ RECT 535.320000 2919.660000 536.420000 2920.140000 ;
+ RECT 490.320000 2903.340000 491.420000 2903.820000 ;
+ RECT 490.320000 2908.780000 491.420000 2909.260000 ;
+ RECT 490.320000 2914.220000 491.420000 2914.700000 ;
+ RECT 490.320000 2919.660000 491.420000 2920.140000 ;
+ RECT 441.490000 2941.420000 442.490000 2941.900000 ;
+ RECT 445.155000 2941.420000 446.420000 2941.900000 ;
+ RECT 441.490000 2930.540000 442.490000 2931.020000 ;
+ RECT 445.155000 2930.540000 446.420000 2931.020000 ;
+ RECT 441.490000 2935.980000 442.490000 2936.460000 ;
+ RECT 445.155000 2935.980000 446.420000 2936.460000 ;
+ RECT 441.490000 2925.100000 442.490000 2925.580000 ;
+ RECT 445.155000 2925.100000 446.420000 2925.580000 ;
+ RECT 441.490000 2919.660000 442.490000 2920.140000 ;
+ RECT 445.155000 2919.660000 446.420000 2920.140000 ;
+ RECT 441.490000 2914.220000 442.490000 2914.700000 ;
+ RECT 445.155000 2914.220000 446.420000 2914.700000 ;
+ RECT 441.490000 2908.780000 442.490000 2909.260000 ;
+ RECT 445.155000 2908.780000 446.420000 2909.260000 ;
+ RECT 441.490000 2903.340000 442.490000 2903.820000 ;
+ RECT 445.155000 2903.340000 446.420000 2903.820000 ;
+ RECT 535.320000 2876.140000 536.420000 2876.620000 ;
+ RECT 535.320000 2881.580000 536.420000 2882.060000 ;
+ RECT 535.320000 2887.020000 536.420000 2887.500000 ;
+ RECT 535.320000 2892.460000 536.420000 2892.940000 ;
+ RECT 535.320000 2897.900000 536.420000 2898.380000 ;
+ RECT 490.320000 2876.140000 491.420000 2876.620000 ;
+ RECT 490.320000 2881.580000 491.420000 2882.060000 ;
+ RECT 490.320000 2887.020000 491.420000 2887.500000 ;
+ RECT 490.320000 2892.460000 491.420000 2892.940000 ;
+ RECT 490.320000 2897.900000 491.420000 2898.380000 ;
+ RECT 535.320000 2854.380000 536.420000 2854.860000 ;
+ RECT 535.320000 2859.820000 536.420000 2860.300000 ;
+ RECT 535.320000 2865.260000 536.420000 2865.740000 ;
+ RECT 535.320000 2870.700000 536.420000 2871.180000 ;
+ RECT 490.320000 2854.380000 491.420000 2854.860000 ;
+ RECT 490.320000 2859.820000 491.420000 2860.300000 ;
+ RECT 490.320000 2865.260000 491.420000 2865.740000 ;
+ RECT 490.320000 2870.700000 491.420000 2871.180000 ;
+ RECT 441.490000 2897.900000 442.490000 2898.380000 ;
+ RECT 445.155000 2897.900000 446.420000 2898.380000 ;
+ RECT 441.490000 2887.020000 442.490000 2887.500000 ;
+ RECT 445.155000 2887.020000 446.420000 2887.500000 ;
+ RECT 441.490000 2892.460000 442.490000 2892.940000 ;
+ RECT 445.155000 2892.460000 446.420000 2892.940000 ;
+ RECT 441.490000 2881.580000 442.490000 2882.060000 ;
+ RECT 445.155000 2881.580000 446.420000 2882.060000 ;
+ RECT 441.490000 2876.140000 442.490000 2876.620000 ;
+ RECT 445.155000 2876.140000 446.420000 2876.620000 ;
+ RECT 441.490000 2870.700000 442.490000 2871.180000 ;
+ RECT 445.155000 2870.700000 446.420000 2871.180000 ;
+ RECT 441.490000 2865.260000 442.490000 2865.740000 ;
+ RECT 445.155000 2865.260000 446.420000 2865.740000 ;
+ RECT 441.490000 2859.820000 442.490000 2860.300000 ;
+ RECT 445.155000 2859.820000 446.420000 2860.300000 ;
+ RECT 441.490000 2854.380000 442.490000 2854.860000 ;
+ RECT 445.155000 2854.380000 446.420000 2854.860000 ;
+ RECT 625.320000 2838.060000 626.420000 2838.540000 ;
+ RECT 625.320000 2843.500000 626.420000 2843.980000 ;
+ RECT 638.130000 2838.060000 639.130000 2838.540000 ;
+ RECT 638.130000 2843.500000 639.130000 2843.980000 ;
+ RECT 638.130000 2827.180000 639.130000 2827.660000 ;
+ RECT 638.130000 2832.620000 639.130000 2833.100000 ;
+ RECT 625.320000 2832.620000 626.420000 2833.100000 ;
+ RECT 625.320000 2827.180000 626.420000 2827.660000 ;
+ RECT 625.320000 2816.300000 626.420000 2816.780000 ;
+ RECT 625.320000 2821.740000 626.420000 2822.220000 ;
+ RECT 638.130000 2816.300000 639.130000 2816.780000 ;
+ RECT 638.130000 2821.740000 639.130000 2822.220000 ;
+ RECT 638.130000 2805.420000 639.130000 2805.900000 ;
+ RECT 638.130000 2799.980000 639.130000 2800.460000 ;
+ RECT 638.130000 2810.860000 639.130000 2811.340000 ;
+ RECT 625.320000 2810.860000 626.420000 2811.340000 ;
+ RECT 625.320000 2805.420000 626.420000 2805.900000 ;
+ RECT 625.320000 2799.980000 626.420000 2800.460000 ;
+ RECT 580.320000 2827.180000 581.420000 2827.660000 ;
+ RECT 580.320000 2832.620000 581.420000 2833.100000 ;
+ RECT 580.320000 2838.060000 581.420000 2838.540000 ;
+ RECT 580.320000 2843.500000 581.420000 2843.980000 ;
+ RECT 580.320000 2799.980000 581.420000 2800.460000 ;
+ RECT 580.320000 2805.420000 581.420000 2805.900000 ;
+ RECT 580.320000 2810.860000 581.420000 2811.340000 ;
+ RECT 580.320000 2816.300000 581.420000 2816.780000 ;
+ RECT 580.320000 2821.740000 581.420000 2822.220000 ;
+ RECT 625.320000 2789.100000 626.420000 2789.580000 ;
+ RECT 625.320000 2794.540000 626.420000 2795.020000 ;
+ RECT 638.130000 2789.100000 639.130000 2789.580000 ;
+ RECT 638.130000 2794.540000 639.130000 2795.020000 ;
+ RECT 625.320000 2778.220000 626.420000 2778.700000 ;
+ RECT 625.320000 2783.660000 626.420000 2784.140000 ;
+ RECT 638.130000 2778.220000 639.130000 2778.700000 ;
+ RECT 638.130000 2783.660000 639.130000 2784.140000 ;
+ RECT 638.130000 2767.340000 639.130000 2767.820000 ;
+ RECT 638.130000 2761.900000 639.130000 2762.380000 ;
+ RECT 638.130000 2772.780000 639.130000 2773.260000 ;
+ RECT 625.320000 2772.780000 626.420000 2773.260000 ;
+ RECT 625.320000 2767.340000 626.420000 2767.820000 ;
+ RECT 625.320000 2761.900000 626.420000 2762.380000 ;
+ RECT 625.320000 2756.460000 626.420000 2756.940000 ;
+ RECT 638.130000 2756.460000 639.130000 2756.940000 ;
+ RECT 580.320000 2778.220000 581.420000 2778.700000 ;
+ RECT 580.320000 2783.660000 581.420000 2784.140000 ;
+ RECT 580.320000 2789.100000 581.420000 2789.580000 ;
+ RECT 580.320000 2794.540000 581.420000 2795.020000 ;
+ RECT 580.320000 2756.460000 581.420000 2756.940000 ;
+ RECT 580.320000 2761.900000 581.420000 2762.380000 ;
+ RECT 580.320000 2767.340000 581.420000 2767.820000 ;
+ RECT 580.320000 2772.780000 581.420000 2773.260000 ;
+ RECT 535.320000 2827.180000 536.420000 2827.660000 ;
+ RECT 535.320000 2832.620000 536.420000 2833.100000 ;
+ RECT 535.320000 2838.060000 536.420000 2838.540000 ;
+ RECT 535.320000 2843.500000 536.420000 2843.980000 ;
+ RECT 490.320000 2827.180000 491.420000 2827.660000 ;
+ RECT 490.320000 2832.620000 491.420000 2833.100000 ;
+ RECT 490.320000 2838.060000 491.420000 2838.540000 ;
+ RECT 490.320000 2843.500000 491.420000 2843.980000 ;
+ RECT 535.320000 2799.980000 536.420000 2800.460000 ;
+ RECT 535.320000 2805.420000 536.420000 2805.900000 ;
+ RECT 535.320000 2810.860000 536.420000 2811.340000 ;
+ RECT 535.320000 2816.300000 536.420000 2816.780000 ;
+ RECT 535.320000 2821.740000 536.420000 2822.220000 ;
+ RECT 490.320000 2799.980000 491.420000 2800.460000 ;
+ RECT 490.320000 2805.420000 491.420000 2805.900000 ;
+ RECT 490.320000 2810.860000 491.420000 2811.340000 ;
+ RECT 490.320000 2816.300000 491.420000 2816.780000 ;
+ RECT 490.320000 2821.740000 491.420000 2822.220000 ;
+ RECT 441.490000 2843.500000 442.490000 2843.980000 ;
+ RECT 445.155000 2843.500000 446.420000 2843.980000 ;
+ RECT 441.490000 2838.060000 442.490000 2838.540000 ;
+ RECT 445.155000 2838.060000 446.420000 2838.540000 ;
+ RECT 441.490000 2832.620000 442.490000 2833.100000 ;
+ RECT 445.155000 2832.620000 446.420000 2833.100000 ;
+ RECT 441.490000 2827.180000 442.490000 2827.660000 ;
+ RECT 445.155000 2827.180000 446.420000 2827.660000 ;
+ RECT 441.490000 2821.740000 442.490000 2822.220000 ;
+ RECT 445.155000 2821.740000 446.420000 2822.220000 ;
+ RECT 441.490000 2816.300000 442.490000 2816.780000 ;
+ RECT 445.155000 2816.300000 446.420000 2816.780000 ;
+ RECT 441.490000 2805.420000 442.490000 2805.900000 ;
+ RECT 445.155000 2805.420000 446.420000 2805.900000 ;
+ RECT 441.490000 2810.860000 442.490000 2811.340000 ;
+ RECT 445.155000 2810.860000 446.420000 2811.340000 ;
+ RECT 441.490000 2799.980000 442.490000 2800.460000 ;
+ RECT 445.155000 2799.980000 446.420000 2800.460000 ;
+ RECT 535.320000 2778.220000 536.420000 2778.700000 ;
+ RECT 535.320000 2783.660000 536.420000 2784.140000 ;
+ RECT 535.320000 2789.100000 536.420000 2789.580000 ;
+ RECT 535.320000 2794.540000 536.420000 2795.020000 ;
+ RECT 490.320000 2778.220000 491.420000 2778.700000 ;
+ RECT 490.320000 2783.660000 491.420000 2784.140000 ;
+ RECT 490.320000 2789.100000 491.420000 2789.580000 ;
+ RECT 490.320000 2794.540000 491.420000 2795.020000 ;
+ RECT 535.320000 2756.460000 536.420000 2756.940000 ;
+ RECT 535.320000 2761.900000 536.420000 2762.380000 ;
+ RECT 535.320000 2767.340000 536.420000 2767.820000 ;
+ RECT 535.320000 2772.780000 536.420000 2773.260000 ;
+ RECT 490.320000 2756.460000 491.420000 2756.940000 ;
+ RECT 490.320000 2761.900000 491.420000 2762.380000 ;
+ RECT 490.320000 2767.340000 491.420000 2767.820000 ;
+ RECT 490.320000 2772.780000 491.420000 2773.260000 ;
+ RECT 441.490000 2794.540000 442.490000 2795.020000 ;
+ RECT 445.155000 2794.540000 446.420000 2795.020000 ;
+ RECT 441.490000 2789.100000 442.490000 2789.580000 ;
+ RECT 445.155000 2789.100000 446.420000 2789.580000 ;
+ RECT 441.490000 2783.660000 442.490000 2784.140000 ;
+ RECT 445.155000 2783.660000 446.420000 2784.140000 ;
+ RECT 441.490000 2778.220000 442.490000 2778.700000 ;
+ RECT 445.155000 2778.220000 446.420000 2778.700000 ;
+ RECT 441.490000 2772.780000 442.490000 2773.260000 ;
+ RECT 445.155000 2772.780000 446.420000 2773.260000 ;
+ RECT 441.490000 2761.900000 442.490000 2762.380000 ;
+ RECT 445.155000 2761.900000 446.420000 2762.380000 ;
+ RECT 441.490000 2767.340000 442.490000 2767.820000 ;
+ RECT 445.155000 2767.340000 446.420000 2767.820000 ;
+ RECT 441.490000 2756.460000 442.490000 2756.940000 ;
+ RECT 445.155000 2756.460000 446.420000 2756.940000 ;
+ RECT 580.320000 2848.940000 581.420000 2849.420000 ;
+ RECT 625.320000 2848.940000 626.420000 2849.420000 ;
+ RECT 638.130000 2848.940000 639.130000 2849.420000 ;
+ RECT 490.320000 2848.940000 491.420000 2849.420000 ;
+ RECT 535.320000 2848.940000 536.420000 2849.420000 ;
+ RECT 441.490000 2848.940000 442.490000 2849.420000 ;
+ RECT 445.155000 2848.940000 446.420000 2849.420000 ;
+ RECT 440.260000 2945.700000 640.360000 2946.700000 ;
+ RECT 440.260000 2750.130000 640.360000 2751.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 2748.880000 442.490000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 2948.140000 442.490000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 2748.880000 639.130000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 2948.140000 639.130000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2750.130000 441.260000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2750.130000 640.360000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2945.700000 441.260000 2946.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2945.700000 640.360000 2946.700000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 2741.160000 446.420000 2741.640000 ;
+ RECT 445.155000 2730.280000 446.420000 2730.760000 ;
+ RECT 445.155000 2735.720000 446.420000 2736.200000 ;
+ RECT 445.155000 2724.840000 446.420000 2725.320000 ;
+ RECT 445.155000 2719.400000 446.420000 2719.880000 ;
+ RECT 445.155000 2713.960000 446.420000 2714.440000 ;
+ RECT 445.155000 2708.520000 446.420000 2709.000000 ;
+ RECT 445.155000 2703.080000 446.420000 2703.560000 ;
+ RECT 445.155000 2697.640000 446.420000 2698.120000 ;
+ RECT 445.155000 2686.760000 446.420000 2687.240000 ;
+ RECT 445.155000 2692.200000 446.420000 2692.680000 ;
+ RECT 445.155000 2681.320000 446.420000 2681.800000 ;
+ RECT 445.155000 2675.880000 446.420000 2676.360000 ;
+ RECT 445.155000 2670.440000 446.420000 2670.920000 ;
+ RECT 445.155000 2665.000000 446.420000 2665.480000 ;
+ RECT 445.155000 2659.560000 446.420000 2660.040000 ;
+ RECT 445.155000 2654.120000 446.420000 2654.600000 ;
+ RECT 445.155000 2643.240000 446.420000 2643.720000 ;
+ RECT 445.155000 2637.800000 446.420000 2638.280000 ;
+ RECT 445.155000 2632.360000 446.420000 2632.840000 ;
+ RECT 445.155000 2626.920000 446.420000 2627.400000 ;
+ RECT 445.155000 2621.480000 446.420000 2621.960000 ;
+ RECT 445.155000 2616.040000 446.420000 2616.520000 ;
+ RECT 445.155000 2605.160000 446.420000 2605.640000 ;
+ RECT 445.155000 2610.600000 446.420000 2611.080000 ;
+ RECT 445.155000 2599.720000 446.420000 2600.200000 ;
+ RECT 445.155000 2594.280000 446.420000 2594.760000 ;
+ RECT 445.155000 2588.840000 446.420000 2589.320000 ;
+ RECT 445.155000 2583.400000 446.420000 2583.880000 ;
+ RECT 445.155000 2577.960000 446.420000 2578.440000 ;
+ RECT 445.155000 2572.520000 446.420000 2573.000000 ;
+ RECT 445.155000 2561.640000 446.420000 2562.120000 ;
+ RECT 445.155000 2567.080000 446.420000 2567.560000 ;
+ RECT 445.155000 2556.200000 446.420000 2556.680000 ;
+ RECT 445.155000 2648.680000 446.420000 2649.160000 ;
+ RECT 625.320000 2549.870000 626.420000 2746.440000 ;
+ RECT 580.320000 2549.870000 581.420000 2746.440000 ;
+ RECT 638.130000 2548.620000 639.130000 2748.880000 ;
+ RECT 535.320000 2549.870000 536.420000 2746.440000 ;
+ RECT 490.320000 2549.870000 491.420000 2746.440000 ;
+ RECT 445.320000 2549.870000 446.420000 2746.440000 ;
+ RECT 441.490000 2548.620000 442.490000 2748.880000 ;
+ LAYER met3 ;
+ RECT 625.320000 2741.160000 626.420000 2741.640000 ;
+ RECT 638.130000 2741.160000 639.130000 2741.640000 ;
+ RECT 638.130000 2730.280000 639.130000 2730.760000 ;
+ RECT 638.130000 2724.840000 639.130000 2725.320000 ;
+ RECT 638.130000 2735.720000 639.130000 2736.200000 ;
+ RECT 625.320000 2735.720000 626.420000 2736.200000 ;
+ RECT 625.320000 2730.280000 626.420000 2730.760000 ;
+ RECT 625.320000 2724.840000 626.420000 2725.320000 ;
+ RECT 625.320000 2713.960000 626.420000 2714.440000 ;
+ RECT 625.320000 2719.400000 626.420000 2719.880000 ;
+ RECT 638.130000 2713.960000 639.130000 2714.440000 ;
+ RECT 638.130000 2719.400000 639.130000 2719.880000 ;
+ RECT 625.320000 2703.080000 626.420000 2703.560000 ;
+ RECT 625.320000 2708.520000 626.420000 2709.000000 ;
+ RECT 638.130000 2703.080000 639.130000 2703.560000 ;
+ RECT 638.130000 2708.520000 639.130000 2709.000000 ;
+ RECT 580.320000 2724.840000 581.420000 2725.320000 ;
+ RECT 580.320000 2730.280000 581.420000 2730.760000 ;
+ RECT 580.320000 2735.720000 581.420000 2736.200000 ;
+ RECT 580.320000 2741.160000 581.420000 2741.640000 ;
+ RECT 580.320000 2708.520000 581.420000 2709.000000 ;
+ RECT 580.320000 2703.080000 581.420000 2703.560000 ;
+ RECT 580.320000 2713.960000 581.420000 2714.440000 ;
+ RECT 580.320000 2719.400000 581.420000 2719.880000 ;
+ RECT 638.130000 2692.200000 639.130000 2692.680000 ;
+ RECT 638.130000 2686.760000 639.130000 2687.240000 ;
+ RECT 638.130000 2697.640000 639.130000 2698.120000 ;
+ RECT 625.320000 2697.640000 626.420000 2698.120000 ;
+ RECT 625.320000 2692.200000 626.420000 2692.680000 ;
+ RECT 625.320000 2686.760000 626.420000 2687.240000 ;
+ RECT 625.320000 2675.880000 626.420000 2676.360000 ;
+ RECT 625.320000 2681.320000 626.420000 2681.800000 ;
+ RECT 638.130000 2675.880000 639.130000 2676.360000 ;
+ RECT 638.130000 2681.320000 639.130000 2681.800000 ;
+ RECT 638.130000 2665.000000 639.130000 2665.480000 ;
+ RECT 638.130000 2670.440000 639.130000 2670.920000 ;
+ RECT 625.320000 2670.440000 626.420000 2670.920000 ;
+ RECT 625.320000 2665.000000 626.420000 2665.480000 ;
+ RECT 625.320000 2654.120000 626.420000 2654.600000 ;
+ RECT 625.320000 2659.560000 626.420000 2660.040000 ;
+ RECT 638.130000 2654.120000 639.130000 2654.600000 ;
+ RECT 638.130000 2659.560000 639.130000 2660.040000 ;
+ RECT 580.320000 2675.880000 581.420000 2676.360000 ;
+ RECT 580.320000 2681.320000 581.420000 2681.800000 ;
+ RECT 580.320000 2686.760000 581.420000 2687.240000 ;
+ RECT 580.320000 2692.200000 581.420000 2692.680000 ;
+ RECT 580.320000 2697.640000 581.420000 2698.120000 ;
+ RECT 580.320000 2654.120000 581.420000 2654.600000 ;
+ RECT 580.320000 2659.560000 581.420000 2660.040000 ;
+ RECT 580.320000 2665.000000 581.420000 2665.480000 ;
+ RECT 580.320000 2670.440000 581.420000 2670.920000 ;
+ RECT 535.320000 2730.280000 536.420000 2730.760000 ;
+ RECT 535.320000 2724.840000 536.420000 2725.320000 ;
+ RECT 535.320000 2735.720000 536.420000 2736.200000 ;
+ RECT 535.320000 2741.160000 536.420000 2741.640000 ;
+ RECT 490.320000 2724.840000 491.420000 2725.320000 ;
+ RECT 490.320000 2730.280000 491.420000 2730.760000 ;
+ RECT 490.320000 2735.720000 491.420000 2736.200000 ;
+ RECT 490.320000 2741.160000 491.420000 2741.640000 ;
+ RECT 535.320000 2703.080000 536.420000 2703.560000 ;
+ RECT 535.320000 2708.520000 536.420000 2709.000000 ;
+ RECT 535.320000 2713.960000 536.420000 2714.440000 ;
+ RECT 535.320000 2719.400000 536.420000 2719.880000 ;
+ RECT 490.320000 2703.080000 491.420000 2703.560000 ;
+ RECT 490.320000 2708.520000 491.420000 2709.000000 ;
+ RECT 490.320000 2713.960000 491.420000 2714.440000 ;
+ RECT 490.320000 2719.400000 491.420000 2719.880000 ;
+ RECT 441.490000 2741.160000 442.490000 2741.640000 ;
+ RECT 445.155000 2741.160000 446.420000 2741.640000 ;
+ RECT 441.490000 2730.280000 442.490000 2730.760000 ;
+ RECT 445.155000 2730.280000 446.420000 2730.760000 ;
+ RECT 441.490000 2735.720000 442.490000 2736.200000 ;
+ RECT 445.155000 2735.720000 446.420000 2736.200000 ;
+ RECT 441.490000 2724.840000 442.490000 2725.320000 ;
+ RECT 445.155000 2724.840000 446.420000 2725.320000 ;
+ RECT 441.490000 2719.400000 442.490000 2719.880000 ;
+ RECT 445.155000 2719.400000 446.420000 2719.880000 ;
+ RECT 441.490000 2713.960000 442.490000 2714.440000 ;
+ RECT 445.155000 2713.960000 446.420000 2714.440000 ;
+ RECT 441.490000 2708.520000 442.490000 2709.000000 ;
+ RECT 445.155000 2708.520000 446.420000 2709.000000 ;
+ RECT 441.490000 2703.080000 442.490000 2703.560000 ;
+ RECT 445.155000 2703.080000 446.420000 2703.560000 ;
+ RECT 535.320000 2675.880000 536.420000 2676.360000 ;
+ RECT 535.320000 2681.320000 536.420000 2681.800000 ;
+ RECT 535.320000 2686.760000 536.420000 2687.240000 ;
+ RECT 535.320000 2692.200000 536.420000 2692.680000 ;
+ RECT 535.320000 2697.640000 536.420000 2698.120000 ;
+ RECT 490.320000 2675.880000 491.420000 2676.360000 ;
+ RECT 490.320000 2681.320000 491.420000 2681.800000 ;
+ RECT 490.320000 2686.760000 491.420000 2687.240000 ;
+ RECT 490.320000 2692.200000 491.420000 2692.680000 ;
+ RECT 490.320000 2697.640000 491.420000 2698.120000 ;
+ RECT 535.320000 2654.120000 536.420000 2654.600000 ;
+ RECT 535.320000 2659.560000 536.420000 2660.040000 ;
+ RECT 535.320000 2665.000000 536.420000 2665.480000 ;
+ RECT 535.320000 2670.440000 536.420000 2670.920000 ;
+ RECT 490.320000 2654.120000 491.420000 2654.600000 ;
+ RECT 490.320000 2659.560000 491.420000 2660.040000 ;
+ RECT 490.320000 2665.000000 491.420000 2665.480000 ;
+ RECT 490.320000 2670.440000 491.420000 2670.920000 ;
+ RECT 441.490000 2697.640000 442.490000 2698.120000 ;
+ RECT 445.155000 2697.640000 446.420000 2698.120000 ;
+ RECT 441.490000 2686.760000 442.490000 2687.240000 ;
+ RECT 445.155000 2686.760000 446.420000 2687.240000 ;
+ RECT 441.490000 2692.200000 442.490000 2692.680000 ;
+ RECT 445.155000 2692.200000 446.420000 2692.680000 ;
+ RECT 441.490000 2681.320000 442.490000 2681.800000 ;
+ RECT 445.155000 2681.320000 446.420000 2681.800000 ;
+ RECT 441.490000 2675.880000 442.490000 2676.360000 ;
+ RECT 445.155000 2675.880000 446.420000 2676.360000 ;
+ RECT 441.490000 2670.440000 442.490000 2670.920000 ;
+ RECT 445.155000 2670.440000 446.420000 2670.920000 ;
+ RECT 441.490000 2665.000000 442.490000 2665.480000 ;
+ RECT 445.155000 2665.000000 446.420000 2665.480000 ;
+ RECT 441.490000 2659.560000 442.490000 2660.040000 ;
+ RECT 445.155000 2659.560000 446.420000 2660.040000 ;
+ RECT 441.490000 2654.120000 442.490000 2654.600000 ;
+ RECT 445.155000 2654.120000 446.420000 2654.600000 ;
+ RECT 625.320000 2637.800000 626.420000 2638.280000 ;
+ RECT 625.320000 2643.240000 626.420000 2643.720000 ;
+ RECT 638.130000 2637.800000 639.130000 2638.280000 ;
+ RECT 638.130000 2643.240000 639.130000 2643.720000 ;
+ RECT 638.130000 2626.920000 639.130000 2627.400000 ;
+ RECT 638.130000 2632.360000 639.130000 2632.840000 ;
+ RECT 625.320000 2632.360000 626.420000 2632.840000 ;
+ RECT 625.320000 2626.920000 626.420000 2627.400000 ;
+ RECT 625.320000 2616.040000 626.420000 2616.520000 ;
+ RECT 625.320000 2621.480000 626.420000 2621.960000 ;
+ RECT 638.130000 2616.040000 639.130000 2616.520000 ;
+ RECT 638.130000 2621.480000 639.130000 2621.960000 ;
+ RECT 638.130000 2605.160000 639.130000 2605.640000 ;
+ RECT 638.130000 2599.720000 639.130000 2600.200000 ;
+ RECT 638.130000 2610.600000 639.130000 2611.080000 ;
+ RECT 625.320000 2610.600000 626.420000 2611.080000 ;
+ RECT 625.320000 2605.160000 626.420000 2605.640000 ;
+ RECT 625.320000 2599.720000 626.420000 2600.200000 ;
+ RECT 580.320000 2626.920000 581.420000 2627.400000 ;
+ RECT 580.320000 2632.360000 581.420000 2632.840000 ;
+ RECT 580.320000 2637.800000 581.420000 2638.280000 ;
+ RECT 580.320000 2643.240000 581.420000 2643.720000 ;
+ RECT 580.320000 2599.720000 581.420000 2600.200000 ;
+ RECT 580.320000 2605.160000 581.420000 2605.640000 ;
+ RECT 580.320000 2610.600000 581.420000 2611.080000 ;
+ RECT 580.320000 2616.040000 581.420000 2616.520000 ;
+ RECT 580.320000 2621.480000 581.420000 2621.960000 ;
+ RECT 625.320000 2588.840000 626.420000 2589.320000 ;
+ RECT 625.320000 2594.280000 626.420000 2594.760000 ;
+ RECT 638.130000 2588.840000 639.130000 2589.320000 ;
+ RECT 638.130000 2594.280000 639.130000 2594.760000 ;
+ RECT 625.320000 2577.960000 626.420000 2578.440000 ;
+ RECT 625.320000 2583.400000 626.420000 2583.880000 ;
+ RECT 638.130000 2577.960000 639.130000 2578.440000 ;
+ RECT 638.130000 2583.400000 639.130000 2583.880000 ;
+ RECT 638.130000 2567.080000 639.130000 2567.560000 ;
+ RECT 638.130000 2561.640000 639.130000 2562.120000 ;
+ RECT 638.130000 2572.520000 639.130000 2573.000000 ;
+ RECT 625.320000 2572.520000 626.420000 2573.000000 ;
+ RECT 625.320000 2567.080000 626.420000 2567.560000 ;
+ RECT 625.320000 2561.640000 626.420000 2562.120000 ;
+ RECT 625.320000 2556.200000 626.420000 2556.680000 ;
+ RECT 638.130000 2556.200000 639.130000 2556.680000 ;
+ RECT 580.320000 2577.960000 581.420000 2578.440000 ;
+ RECT 580.320000 2583.400000 581.420000 2583.880000 ;
+ RECT 580.320000 2588.840000 581.420000 2589.320000 ;
+ RECT 580.320000 2594.280000 581.420000 2594.760000 ;
+ RECT 580.320000 2556.200000 581.420000 2556.680000 ;
+ RECT 580.320000 2561.640000 581.420000 2562.120000 ;
+ RECT 580.320000 2567.080000 581.420000 2567.560000 ;
+ RECT 580.320000 2572.520000 581.420000 2573.000000 ;
+ RECT 535.320000 2626.920000 536.420000 2627.400000 ;
+ RECT 535.320000 2632.360000 536.420000 2632.840000 ;
+ RECT 535.320000 2637.800000 536.420000 2638.280000 ;
+ RECT 535.320000 2643.240000 536.420000 2643.720000 ;
+ RECT 490.320000 2626.920000 491.420000 2627.400000 ;
+ RECT 490.320000 2632.360000 491.420000 2632.840000 ;
+ RECT 490.320000 2637.800000 491.420000 2638.280000 ;
+ RECT 490.320000 2643.240000 491.420000 2643.720000 ;
+ RECT 535.320000 2599.720000 536.420000 2600.200000 ;
+ RECT 535.320000 2605.160000 536.420000 2605.640000 ;
+ RECT 535.320000 2610.600000 536.420000 2611.080000 ;
+ RECT 535.320000 2616.040000 536.420000 2616.520000 ;
+ RECT 535.320000 2621.480000 536.420000 2621.960000 ;
+ RECT 490.320000 2599.720000 491.420000 2600.200000 ;
+ RECT 490.320000 2605.160000 491.420000 2605.640000 ;
+ RECT 490.320000 2610.600000 491.420000 2611.080000 ;
+ RECT 490.320000 2616.040000 491.420000 2616.520000 ;
+ RECT 490.320000 2621.480000 491.420000 2621.960000 ;
+ RECT 441.490000 2643.240000 442.490000 2643.720000 ;
+ RECT 445.155000 2643.240000 446.420000 2643.720000 ;
+ RECT 441.490000 2637.800000 442.490000 2638.280000 ;
+ RECT 445.155000 2637.800000 446.420000 2638.280000 ;
+ RECT 441.490000 2632.360000 442.490000 2632.840000 ;
+ RECT 445.155000 2632.360000 446.420000 2632.840000 ;
+ RECT 441.490000 2626.920000 442.490000 2627.400000 ;
+ RECT 445.155000 2626.920000 446.420000 2627.400000 ;
+ RECT 441.490000 2621.480000 442.490000 2621.960000 ;
+ RECT 445.155000 2621.480000 446.420000 2621.960000 ;
+ RECT 441.490000 2616.040000 442.490000 2616.520000 ;
+ RECT 445.155000 2616.040000 446.420000 2616.520000 ;
+ RECT 441.490000 2605.160000 442.490000 2605.640000 ;
+ RECT 445.155000 2605.160000 446.420000 2605.640000 ;
+ RECT 441.490000 2610.600000 442.490000 2611.080000 ;
+ RECT 445.155000 2610.600000 446.420000 2611.080000 ;
+ RECT 441.490000 2599.720000 442.490000 2600.200000 ;
+ RECT 445.155000 2599.720000 446.420000 2600.200000 ;
+ RECT 535.320000 2577.960000 536.420000 2578.440000 ;
+ RECT 535.320000 2583.400000 536.420000 2583.880000 ;
+ RECT 535.320000 2588.840000 536.420000 2589.320000 ;
+ RECT 535.320000 2594.280000 536.420000 2594.760000 ;
+ RECT 490.320000 2577.960000 491.420000 2578.440000 ;
+ RECT 490.320000 2583.400000 491.420000 2583.880000 ;
+ RECT 490.320000 2588.840000 491.420000 2589.320000 ;
+ RECT 490.320000 2594.280000 491.420000 2594.760000 ;
+ RECT 535.320000 2556.200000 536.420000 2556.680000 ;
+ RECT 535.320000 2561.640000 536.420000 2562.120000 ;
+ RECT 535.320000 2567.080000 536.420000 2567.560000 ;
+ RECT 535.320000 2572.520000 536.420000 2573.000000 ;
+ RECT 490.320000 2556.200000 491.420000 2556.680000 ;
+ RECT 490.320000 2561.640000 491.420000 2562.120000 ;
+ RECT 490.320000 2567.080000 491.420000 2567.560000 ;
+ RECT 490.320000 2572.520000 491.420000 2573.000000 ;
+ RECT 441.490000 2594.280000 442.490000 2594.760000 ;
+ RECT 445.155000 2594.280000 446.420000 2594.760000 ;
+ RECT 441.490000 2588.840000 442.490000 2589.320000 ;
+ RECT 445.155000 2588.840000 446.420000 2589.320000 ;
+ RECT 441.490000 2583.400000 442.490000 2583.880000 ;
+ RECT 445.155000 2583.400000 446.420000 2583.880000 ;
+ RECT 441.490000 2577.960000 442.490000 2578.440000 ;
+ RECT 445.155000 2577.960000 446.420000 2578.440000 ;
+ RECT 441.490000 2572.520000 442.490000 2573.000000 ;
+ RECT 445.155000 2572.520000 446.420000 2573.000000 ;
+ RECT 441.490000 2561.640000 442.490000 2562.120000 ;
+ RECT 445.155000 2561.640000 446.420000 2562.120000 ;
+ RECT 441.490000 2567.080000 442.490000 2567.560000 ;
+ RECT 445.155000 2567.080000 446.420000 2567.560000 ;
+ RECT 441.490000 2556.200000 442.490000 2556.680000 ;
+ RECT 445.155000 2556.200000 446.420000 2556.680000 ;
+ RECT 580.320000 2648.680000 581.420000 2649.160000 ;
+ RECT 625.320000 2648.680000 626.420000 2649.160000 ;
+ RECT 638.130000 2648.680000 639.130000 2649.160000 ;
+ RECT 490.320000 2648.680000 491.420000 2649.160000 ;
+ RECT 535.320000 2648.680000 536.420000 2649.160000 ;
+ RECT 441.490000 2648.680000 442.490000 2649.160000 ;
+ RECT 445.155000 2648.680000 446.420000 2649.160000 ;
+ RECT 440.260000 2745.440000 640.360000 2746.440000 ;
+ RECT 440.260000 2549.870000 640.360000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 2548.620000 442.490000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 2747.880000 442.490000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 2548.620000 639.130000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 2747.880000 639.130000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2549.870000 441.260000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2549.870000 640.360000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2745.440000 441.260000 2746.440000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2745.440000 640.360000 2746.440000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 2540.900000 446.420000 2541.380000 ;
+ RECT 445.155000 2530.020000 446.420000 2530.500000 ;
+ RECT 445.155000 2535.460000 446.420000 2535.940000 ;
+ RECT 445.155000 2524.580000 446.420000 2525.060000 ;
+ RECT 445.155000 2519.140000 446.420000 2519.620000 ;
+ RECT 445.155000 2513.700000 446.420000 2514.180000 ;
+ RECT 445.155000 2508.260000 446.420000 2508.740000 ;
+ RECT 445.155000 2502.820000 446.420000 2503.300000 ;
+ RECT 445.155000 2497.380000 446.420000 2497.860000 ;
+ RECT 445.155000 2486.500000 446.420000 2486.980000 ;
+ RECT 445.155000 2491.940000 446.420000 2492.420000 ;
+ RECT 445.155000 2481.060000 446.420000 2481.540000 ;
+ RECT 445.155000 2475.620000 446.420000 2476.100000 ;
+ RECT 445.155000 2470.180000 446.420000 2470.660000 ;
+ RECT 445.155000 2464.740000 446.420000 2465.220000 ;
+ RECT 445.155000 2459.300000 446.420000 2459.780000 ;
+ RECT 445.155000 2453.860000 446.420000 2454.340000 ;
+ RECT 445.155000 2442.980000 446.420000 2443.460000 ;
+ RECT 445.155000 2437.540000 446.420000 2438.020000 ;
+ RECT 445.155000 2432.100000 446.420000 2432.580000 ;
+ RECT 445.155000 2426.660000 446.420000 2427.140000 ;
+ RECT 445.155000 2421.220000 446.420000 2421.700000 ;
+ RECT 445.155000 2415.780000 446.420000 2416.260000 ;
+ RECT 445.155000 2404.900000 446.420000 2405.380000 ;
+ RECT 445.155000 2410.340000 446.420000 2410.820000 ;
+ RECT 445.155000 2399.460000 446.420000 2399.940000 ;
+ RECT 445.155000 2394.020000 446.420000 2394.500000 ;
+ RECT 445.155000 2388.580000 446.420000 2389.060000 ;
+ RECT 445.155000 2383.140000 446.420000 2383.620000 ;
+ RECT 445.155000 2377.700000 446.420000 2378.180000 ;
+ RECT 445.155000 2372.260000 446.420000 2372.740000 ;
+ RECT 445.155000 2361.380000 446.420000 2361.860000 ;
+ RECT 445.155000 2366.820000 446.420000 2367.300000 ;
+ RECT 445.155000 2355.940000 446.420000 2356.420000 ;
+ RECT 445.155000 2448.420000 446.420000 2448.900000 ;
+ RECT 625.320000 2349.610000 626.420000 2546.180000 ;
+ RECT 580.320000 2349.610000 581.420000 2546.180000 ;
+ RECT 638.130000 2348.360000 639.130000 2548.620000 ;
+ RECT 535.320000 2349.610000 536.420000 2546.180000 ;
+ RECT 490.320000 2349.610000 491.420000 2546.180000 ;
+ RECT 445.320000 2349.610000 446.420000 2546.180000 ;
+ RECT 441.490000 2348.360000 442.490000 2548.620000 ;
+ LAYER met3 ;
+ RECT 625.320000 2540.900000 626.420000 2541.380000 ;
+ RECT 638.130000 2540.900000 639.130000 2541.380000 ;
+ RECT 638.130000 2530.020000 639.130000 2530.500000 ;
+ RECT 638.130000 2524.580000 639.130000 2525.060000 ;
+ RECT 638.130000 2535.460000 639.130000 2535.940000 ;
+ RECT 625.320000 2535.460000 626.420000 2535.940000 ;
+ RECT 625.320000 2530.020000 626.420000 2530.500000 ;
+ RECT 625.320000 2524.580000 626.420000 2525.060000 ;
+ RECT 625.320000 2513.700000 626.420000 2514.180000 ;
+ RECT 625.320000 2519.140000 626.420000 2519.620000 ;
+ RECT 638.130000 2513.700000 639.130000 2514.180000 ;
+ RECT 638.130000 2519.140000 639.130000 2519.620000 ;
+ RECT 625.320000 2502.820000 626.420000 2503.300000 ;
+ RECT 625.320000 2508.260000 626.420000 2508.740000 ;
+ RECT 638.130000 2502.820000 639.130000 2503.300000 ;
+ RECT 638.130000 2508.260000 639.130000 2508.740000 ;
+ RECT 580.320000 2524.580000 581.420000 2525.060000 ;
+ RECT 580.320000 2530.020000 581.420000 2530.500000 ;
+ RECT 580.320000 2535.460000 581.420000 2535.940000 ;
+ RECT 580.320000 2540.900000 581.420000 2541.380000 ;
+ RECT 580.320000 2508.260000 581.420000 2508.740000 ;
+ RECT 580.320000 2502.820000 581.420000 2503.300000 ;
+ RECT 580.320000 2513.700000 581.420000 2514.180000 ;
+ RECT 580.320000 2519.140000 581.420000 2519.620000 ;
+ RECT 638.130000 2491.940000 639.130000 2492.420000 ;
+ RECT 638.130000 2486.500000 639.130000 2486.980000 ;
+ RECT 638.130000 2497.380000 639.130000 2497.860000 ;
+ RECT 625.320000 2497.380000 626.420000 2497.860000 ;
+ RECT 625.320000 2491.940000 626.420000 2492.420000 ;
+ RECT 625.320000 2486.500000 626.420000 2486.980000 ;
+ RECT 625.320000 2475.620000 626.420000 2476.100000 ;
+ RECT 625.320000 2481.060000 626.420000 2481.540000 ;
+ RECT 638.130000 2475.620000 639.130000 2476.100000 ;
+ RECT 638.130000 2481.060000 639.130000 2481.540000 ;
+ RECT 638.130000 2464.740000 639.130000 2465.220000 ;
+ RECT 638.130000 2470.180000 639.130000 2470.660000 ;
+ RECT 625.320000 2470.180000 626.420000 2470.660000 ;
+ RECT 625.320000 2464.740000 626.420000 2465.220000 ;
+ RECT 625.320000 2453.860000 626.420000 2454.340000 ;
+ RECT 625.320000 2459.300000 626.420000 2459.780000 ;
+ RECT 638.130000 2453.860000 639.130000 2454.340000 ;
+ RECT 638.130000 2459.300000 639.130000 2459.780000 ;
+ RECT 580.320000 2475.620000 581.420000 2476.100000 ;
+ RECT 580.320000 2481.060000 581.420000 2481.540000 ;
+ RECT 580.320000 2486.500000 581.420000 2486.980000 ;
+ RECT 580.320000 2491.940000 581.420000 2492.420000 ;
+ RECT 580.320000 2497.380000 581.420000 2497.860000 ;
+ RECT 580.320000 2453.860000 581.420000 2454.340000 ;
+ RECT 580.320000 2459.300000 581.420000 2459.780000 ;
+ RECT 580.320000 2464.740000 581.420000 2465.220000 ;
+ RECT 580.320000 2470.180000 581.420000 2470.660000 ;
+ RECT 535.320000 2530.020000 536.420000 2530.500000 ;
+ RECT 535.320000 2524.580000 536.420000 2525.060000 ;
+ RECT 535.320000 2535.460000 536.420000 2535.940000 ;
+ RECT 535.320000 2540.900000 536.420000 2541.380000 ;
+ RECT 490.320000 2524.580000 491.420000 2525.060000 ;
+ RECT 490.320000 2530.020000 491.420000 2530.500000 ;
+ RECT 490.320000 2535.460000 491.420000 2535.940000 ;
+ RECT 490.320000 2540.900000 491.420000 2541.380000 ;
+ RECT 535.320000 2502.820000 536.420000 2503.300000 ;
+ RECT 535.320000 2508.260000 536.420000 2508.740000 ;
+ RECT 535.320000 2513.700000 536.420000 2514.180000 ;
+ RECT 535.320000 2519.140000 536.420000 2519.620000 ;
+ RECT 490.320000 2502.820000 491.420000 2503.300000 ;
+ RECT 490.320000 2508.260000 491.420000 2508.740000 ;
+ RECT 490.320000 2513.700000 491.420000 2514.180000 ;
+ RECT 490.320000 2519.140000 491.420000 2519.620000 ;
+ RECT 441.490000 2540.900000 442.490000 2541.380000 ;
+ RECT 445.155000 2540.900000 446.420000 2541.380000 ;
+ RECT 441.490000 2530.020000 442.490000 2530.500000 ;
+ RECT 445.155000 2530.020000 446.420000 2530.500000 ;
+ RECT 441.490000 2535.460000 442.490000 2535.940000 ;
+ RECT 445.155000 2535.460000 446.420000 2535.940000 ;
+ RECT 441.490000 2524.580000 442.490000 2525.060000 ;
+ RECT 445.155000 2524.580000 446.420000 2525.060000 ;
+ RECT 441.490000 2519.140000 442.490000 2519.620000 ;
+ RECT 445.155000 2519.140000 446.420000 2519.620000 ;
+ RECT 441.490000 2513.700000 442.490000 2514.180000 ;
+ RECT 445.155000 2513.700000 446.420000 2514.180000 ;
+ RECT 441.490000 2508.260000 442.490000 2508.740000 ;
+ RECT 445.155000 2508.260000 446.420000 2508.740000 ;
+ RECT 441.490000 2502.820000 442.490000 2503.300000 ;
+ RECT 445.155000 2502.820000 446.420000 2503.300000 ;
+ RECT 535.320000 2475.620000 536.420000 2476.100000 ;
+ RECT 535.320000 2481.060000 536.420000 2481.540000 ;
+ RECT 535.320000 2486.500000 536.420000 2486.980000 ;
+ RECT 535.320000 2491.940000 536.420000 2492.420000 ;
+ RECT 535.320000 2497.380000 536.420000 2497.860000 ;
+ RECT 490.320000 2475.620000 491.420000 2476.100000 ;
+ RECT 490.320000 2481.060000 491.420000 2481.540000 ;
+ RECT 490.320000 2486.500000 491.420000 2486.980000 ;
+ RECT 490.320000 2491.940000 491.420000 2492.420000 ;
+ RECT 490.320000 2497.380000 491.420000 2497.860000 ;
+ RECT 535.320000 2453.860000 536.420000 2454.340000 ;
+ RECT 535.320000 2459.300000 536.420000 2459.780000 ;
+ RECT 535.320000 2464.740000 536.420000 2465.220000 ;
+ RECT 535.320000 2470.180000 536.420000 2470.660000 ;
+ RECT 490.320000 2453.860000 491.420000 2454.340000 ;
+ RECT 490.320000 2459.300000 491.420000 2459.780000 ;
+ RECT 490.320000 2464.740000 491.420000 2465.220000 ;
+ RECT 490.320000 2470.180000 491.420000 2470.660000 ;
+ RECT 441.490000 2497.380000 442.490000 2497.860000 ;
+ RECT 445.155000 2497.380000 446.420000 2497.860000 ;
+ RECT 441.490000 2486.500000 442.490000 2486.980000 ;
+ RECT 445.155000 2486.500000 446.420000 2486.980000 ;
+ RECT 441.490000 2491.940000 442.490000 2492.420000 ;
+ RECT 445.155000 2491.940000 446.420000 2492.420000 ;
+ RECT 441.490000 2481.060000 442.490000 2481.540000 ;
+ RECT 445.155000 2481.060000 446.420000 2481.540000 ;
+ RECT 441.490000 2475.620000 442.490000 2476.100000 ;
+ RECT 445.155000 2475.620000 446.420000 2476.100000 ;
+ RECT 441.490000 2470.180000 442.490000 2470.660000 ;
+ RECT 445.155000 2470.180000 446.420000 2470.660000 ;
+ RECT 441.490000 2464.740000 442.490000 2465.220000 ;
+ RECT 445.155000 2464.740000 446.420000 2465.220000 ;
+ RECT 441.490000 2459.300000 442.490000 2459.780000 ;
+ RECT 445.155000 2459.300000 446.420000 2459.780000 ;
+ RECT 441.490000 2453.860000 442.490000 2454.340000 ;
+ RECT 445.155000 2453.860000 446.420000 2454.340000 ;
+ RECT 625.320000 2437.540000 626.420000 2438.020000 ;
+ RECT 625.320000 2442.980000 626.420000 2443.460000 ;
+ RECT 638.130000 2437.540000 639.130000 2438.020000 ;
+ RECT 638.130000 2442.980000 639.130000 2443.460000 ;
+ RECT 638.130000 2426.660000 639.130000 2427.140000 ;
+ RECT 638.130000 2432.100000 639.130000 2432.580000 ;
+ RECT 625.320000 2432.100000 626.420000 2432.580000 ;
+ RECT 625.320000 2426.660000 626.420000 2427.140000 ;
+ RECT 625.320000 2415.780000 626.420000 2416.260000 ;
+ RECT 625.320000 2421.220000 626.420000 2421.700000 ;
+ RECT 638.130000 2415.780000 639.130000 2416.260000 ;
+ RECT 638.130000 2421.220000 639.130000 2421.700000 ;
+ RECT 638.130000 2404.900000 639.130000 2405.380000 ;
+ RECT 638.130000 2399.460000 639.130000 2399.940000 ;
+ RECT 638.130000 2410.340000 639.130000 2410.820000 ;
+ RECT 625.320000 2410.340000 626.420000 2410.820000 ;
+ RECT 625.320000 2404.900000 626.420000 2405.380000 ;
+ RECT 625.320000 2399.460000 626.420000 2399.940000 ;
+ RECT 580.320000 2426.660000 581.420000 2427.140000 ;
+ RECT 580.320000 2432.100000 581.420000 2432.580000 ;
+ RECT 580.320000 2437.540000 581.420000 2438.020000 ;
+ RECT 580.320000 2442.980000 581.420000 2443.460000 ;
+ RECT 580.320000 2399.460000 581.420000 2399.940000 ;
+ RECT 580.320000 2404.900000 581.420000 2405.380000 ;
+ RECT 580.320000 2410.340000 581.420000 2410.820000 ;
+ RECT 580.320000 2415.780000 581.420000 2416.260000 ;
+ RECT 580.320000 2421.220000 581.420000 2421.700000 ;
+ RECT 625.320000 2388.580000 626.420000 2389.060000 ;
+ RECT 625.320000 2394.020000 626.420000 2394.500000 ;
+ RECT 638.130000 2388.580000 639.130000 2389.060000 ;
+ RECT 638.130000 2394.020000 639.130000 2394.500000 ;
+ RECT 625.320000 2377.700000 626.420000 2378.180000 ;
+ RECT 625.320000 2383.140000 626.420000 2383.620000 ;
+ RECT 638.130000 2377.700000 639.130000 2378.180000 ;
+ RECT 638.130000 2383.140000 639.130000 2383.620000 ;
+ RECT 638.130000 2366.820000 639.130000 2367.300000 ;
+ RECT 638.130000 2361.380000 639.130000 2361.860000 ;
+ RECT 638.130000 2372.260000 639.130000 2372.740000 ;
+ RECT 625.320000 2372.260000 626.420000 2372.740000 ;
+ RECT 625.320000 2366.820000 626.420000 2367.300000 ;
+ RECT 625.320000 2361.380000 626.420000 2361.860000 ;
+ RECT 625.320000 2355.940000 626.420000 2356.420000 ;
+ RECT 638.130000 2355.940000 639.130000 2356.420000 ;
+ RECT 580.320000 2377.700000 581.420000 2378.180000 ;
+ RECT 580.320000 2383.140000 581.420000 2383.620000 ;
+ RECT 580.320000 2388.580000 581.420000 2389.060000 ;
+ RECT 580.320000 2394.020000 581.420000 2394.500000 ;
+ RECT 580.320000 2355.940000 581.420000 2356.420000 ;
+ RECT 580.320000 2361.380000 581.420000 2361.860000 ;
+ RECT 580.320000 2366.820000 581.420000 2367.300000 ;
+ RECT 580.320000 2372.260000 581.420000 2372.740000 ;
+ RECT 535.320000 2426.660000 536.420000 2427.140000 ;
+ RECT 535.320000 2432.100000 536.420000 2432.580000 ;
+ RECT 535.320000 2437.540000 536.420000 2438.020000 ;
+ RECT 535.320000 2442.980000 536.420000 2443.460000 ;
+ RECT 490.320000 2426.660000 491.420000 2427.140000 ;
+ RECT 490.320000 2432.100000 491.420000 2432.580000 ;
+ RECT 490.320000 2437.540000 491.420000 2438.020000 ;
+ RECT 490.320000 2442.980000 491.420000 2443.460000 ;
+ RECT 535.320000 2399.460000 536.420000 2399.940000 ;
+ RECT 535.320000 2404.900000 536.420000 2405.380000 ;
+ RECT 535.320000 2410.340000 536.420000 2410.820000 ;
+ RECT 535.320000 2415.780000 536.420000 2416.260000 ;
+ RECT 535.320000 2421.220000 536.420000 2421.700000 ;
+ RECT 490.320000 2399.460000 491.420000 2399.940000 ;
+ RECT 490.320000 2404.900000 491.420000 2405.380000 ;
+ RECT 490.320000 2410.340000 491.420000 2410.820000 ;
+ RECT 490.320000 2415.780000 491.420000 2416.260000 ;
+ RECT 490.320000 2421.220000 491.420000 2421.700000 ;
+ RECT 441.490000 2442.980000 442.490000 2443.460000 ;
+ RECT 445.155000 2442.980000 446.420000 2443.460000 ;
+ RECT 441.490000 2437.540000 442.490000 2438.020000 ;
+ RECT 445.155000 2437.540000 446.420000 2438.020000 ;
+ RECT 441.490000 2432.100000 442.490000 2432.580000 ;
+ RECT 445.155000 2432.100000 446.420000 2432.580000 ;
+ RECT 441.490000 2426.660000 442.490000 2427.140000 ;
+ RECT 445.155000 2426.660000 446.420000 2427.140000 ;
+ RECT 441.490000 2421.220000 442.490000 2421.700000 ;
+ RECT 445.155000 2421.220000 446.420000 2421.700000 ;
+ RECT 441.490000 2415.780000 442.490000 2416.260000 ;
+ RECT 445.155000 2415.780000 446.420000 2416.260000 ;
+ RECT 441.490000 2404.900000 442.490000 2405.380000 ;
+ RECT 445.155000 2404.900000 446.420000 2405.380000 ;
+ RECT 441.490000 2410.340000 442.490000 2410.820000 ;
+ RECT 445.155000 2410.340000 446.420000 2410.820000 ;
+ RECT 441.490000 2399.460000 442.490000 2399.940000 ;
+ RECT 445.155000 2399.460000 446.420000 2399.940000 ;
+ RECT 535.320000 2377.700000 536.420000 2378.180000 ;
+ RECT 535.320000 2383.140000 536.420000 2383.620000 ;
+ RECT 535.320000 2388.580000 536.420000 2389.060000 ;
+ RECT 535.320000 2394.020000 536.420000 2394.500000 ;
+ RECT 490.320000 2377.700000 491.420000 2378.180000 ;
+ RECT 490.320000 2383.140000 491.420000 2383.620000 ;
+ RECT 490.320000 2388.580000 491.420000 2389.060000 ;
+ RECT 490.320000 2394.020000 491.420000 2394.500000 ;
+ RECT 535.320000 2355.940000 536.420000 2356.420000 ;
+ RECT 535.320000 2361.380000 536.420000 2361.860000 ;
+ RECT 535.320000 2366.820000 536.420000 2367.300000 ;
+ RECT 535.320000 2372.260000 536.420000 2372.740000 ;
+ RECT 490.320000 2355.940000 491.420000 2356.420000 ;
+ RECT 490.320000 2361.380000 491.420000 2361.860000 ;
+ RECT 490.320000 2366.820000 491.420000 2367.300000 ;
+ RECT 490.320000 2372.260000 491.420000 2372.740000 ;
+ RECT 441.490000 2394.020000 442.490000 2394.500000 ;
+ RECT 445.155000 2394.020000 446.420000 2394.500000 ;
+ RECT 441.490000 2388.580000 442.490000 2389.060000 ;
+ RECT 445.155000 2388.580000 446.420000 2389.060000 ;
+ RECT 441.490000 2383.140000 442.490000 2383.620000 ;
+ RECT 445.155000 2383.140000 446.420000 2383.620000 ;
+ RECT 441.490000 2377.700000 442.490000 2378.180000 ;
+ RECT 445.155000 2377.700000 446.420000 2378.180000 ;
+ RECT 441.490000 2372.260000 442.490000 2372.740000 ;
+ RECT 445.155000 2372.260000 446.420000 2372.740000 ;
+ RECT 441.490000 2361.380000 442.490000 2361.860000 ;
+ RECT 445.155000 2361.380000 446.420000 2361.860000 ;
+ RECT 441.490000 2366.820000 442.490000 2367.300000 ;
+ RECT 445.155000 2366.820000 446.420000 2367.300000 ;
+ RECT 441.490000 2355.940000 442.490000 2356.420000 ;
+ RECT 445.155000 2355.940000 446.420000 2356.420000 ;
+ RECT 580.320000 2448.420000 581.420000 2448.900000 ;
+ RECT 625.320000 2448.420000 626.420000 2448.900000 ;
+ RECT 638.130000 2448.420000 639.130000 2448.900000 ;
+ RECT 490.320000 2448.420000 491.420000 2448.900000 ;
+ RECT 535.320000 2448.420000 536.420000 2448.900000 ;
+ RECT 441.490000 2448.420000 442.490000 2448.900000 ;
+ RECT 445.155000 2448.420000 446.420000 2448.900000 ;
+ RECT 440.260000 2545.180000 640.360000 2546.180000 ;
+ RECT 440.260000 2349.610000 640.360000 2350.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 2348.360000 442.490000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 2547.620000 442.490000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 2348.360000 639.130000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 2547.620000 639.130000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2349.610000 441.260000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2349.610000 640.360000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2545.180000 441.260000 2546.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2545.180000 640.360000 2546.180000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 2340.640000 446.420000 2341.120000 ;
+ RECT 445.155000 2329.760000 446.420000 2330.240000 ;
+ RECT 445.155000 2335.200000 446.420000 2335.680000 ;
+ RECT 445.155000 2324.320000 446.420000 2324.800000 ;
+ RECT 445.155000 2318.880000 446.420000 2319.360000 ;
+ RECT 445.155000 2313.440000 446.420000 2313.920000 ;
+ RECT 445.155000 2308.000000 446.420000 2308.480000 ;
+ RECT 445.155000 2302.560000 446.420000 2303.040000 ;
+ RECT 445.155000 2297.120000 446.420000 2297.600000 ;
+ RECT 445.155000 2286.240000 446.420000 2286.720000 ;
+ RECT 445.155000 2291.680000 446.420000 2292.160000 ;
+ RECT 445.155000 2280.800000 446.420000 2281.280000 ;
+ RECT 445.155000 2275.360000 446.420000 2275.840000 ;
+ RECT 445.155000 2269.920000 446.420000 2270.400000 ;
+ RECT 445.155000 2264.480000 446.420000 2264.960000 ;
+ RECT 445.155000 2259.040000 446.420000 2259.520000 ;
+ RECT 445.155000 2253.600000 446.420000 2254.080000 ;
+ RECT 445.155000 2242.720000 446.420000 2243.200000 ;
+ RECT 445.155000 2237.280000 446.420000 2237.760000 ;
+ RECT 445.155000 2231.840000 446.420000 2232.320000 ;
+ RECT 445.155000 2226.400000 446.420000 2226.880000 ;
+ RECT 445.155000 2220.960000 446.420000 2221.440000 ;
+ RECT 445.155000 2215.520000 446.420000 2216.000000 ;
+ RECT 445.155000 2204.640000 446.420000 2205.120000 ;
+ RECT 445.155000 2210.080000 446.420000 2210.560000 ;
+ RECT 445.155000 2199.200000 446.420000 2199.680000 ;
+ RECT 445.155000 2193.760000 446.420000 2194.240000 ;
+ RECT 445.155000 2188.320000 446.420000 2188.800000 ;
+ RECT 445.155000 2182.880000 446.420000 2183.360000 ;
+ RECT 445.155000 2177.440000 446.420000 2177.920000 ;
+ RECT 445.155000 2172.000000 446.420000 2172.480000 ;
+ RECT 445.155000 2161.120000 446.420000 2161.600000 ;
+ RECT 445.155000 2166.560000 446.420000 2167.040000 ;
+ RECT 445.155000 2155.680000 446.420000 2156.160000 ;
+ RECT 445.155000 2248.160000 446.420000 2248.640000 ;
+ RECT 625.320000 2149.350000 626.420000 2345.920000 ;
+ RECT 580.320000 2149.350000 581.420000 2345.920000 ;
+ RECT 638.130000 2148.100000 639.130000 2348.360000 ;
+ RECT 535.320000 2149.350000 536.420000 2345.920000 ;
+ RECT 490.320000 2149.350000 491.420000 2345.920000 ;
+ RECT 445.320000 2149.350000 446.420000 2345.920000 ;
+ RECT 441.490000 2148.100000 442.490000 2348.360000 ;
+ LAYER met3 ;
+ RECT 625.320000 2340.640000 626.420000 2341.120000 ;
+ RECT 638.130000 2340.640000 639.130000 2341.120000 ;
+ RECT 638.130000 2329.760000 639.130000 2330.240000 ;
+ RECT 638.130000 2324.320000 639.130000 2324.800000 ;
+ RECT 638.130000 2335.200000 639.130000 2335.680000 ;
+ RECT 625.320000 2335.200000 626.420000 2335.680000 ;
+ RECT 625.320000 2329.760000 626.420000 2330.240000 ;
+ RECT 625.320000 2324.320000 626.420000 2324.800000 ;
+ RECT 625.320000 2313.440000 626.420000 2313.920000 ;
+ RECT 625.320000 2318.880000 626.420000 2319.360000 ;
+ RECT 638.130000 2313.440000 639.130000 2313.920000 ;
+ RECT 638.130000 2318.880000 639.130000 2319.360000 ;
+ RECT 625.320000 2302.560000 626.420000 2303.040000 ;
+ RECT 625.320000 2308.000000 626.420000 2308.480000 ;
+ RECT 638.130000 2302.560000 639.130000 2303.040000 ;
+ RECT 638.130000 2308.000000 639.130000 2308.480000 ;
+ RECT 580.320000 2324.320000 581.420000 2324.800000 ;
+ RECT 580.320000 2329.760000 581.420000 2330.240000 ;
+ RECT 580.320000 2335.200000 581.420000 2335.680000 ;
+ RECT 580.320000 2340.640000 581.420000 2341.120000 ;
+ RECT 580.320000 2308.000000 581.420000 2308.480000 ;
+ RECT 580.320000 2302.560000 581.420000 2303.040000 ;
+ RECT 580.320000 2313.440000 581.420000 2313.920000 ;
+ RECT 580.320000 2318.880000 581.420000 2319.360000 ;
+ RECT 638.130000 2291.680000 639.130000 2292.160000 ;
+ RECT 638.130000 2286.240000 639.130000 2286.720000 ;
+ RECT 638.130000 2297.120000 639.130000 2297.600000 ;
+ RECT 625.320000 2297.120000 626.420000 2297.600000 ;
+ RECT 625.320000 2291.680000 626.420000 2292.160000 ;
+ RECT 625.320000 2286.240000 626.420000 2286.720000 ;
+ RECT 625.320000 2275.360000 626.420000 2275.840000 ;
+ RECT 625.320000 2280.800000 626.420000 2281.280000 ;
+ RECT 638.130000 2275.360000 639.130000 2275.840000 ;
+ RECT 638.130000 2280.800000 639.130000 2281.280000 ;
+ RECT 638.130000 2264.480000 639.130000 2264.960000 ;
+ RECT 638.130000 2269.920000 639.130000 2270.400000 ;
+ RECT 625.320000 2269.920000 626.420000 2270.400000 ;
+ RECT 625.320000 2264.480000 626.420000 2264.960000 ;
+ RECT 625.320000 2253.600000 626.420000 2254.080000 ;
+ RECT 625.320000 2259.040000 626.420000 2259.520000 ;
+ RECT 638.130000 2253.600000 639.130000 2254.080000 ;
+ RECT 638.130000 2259.040000 639.130000 2259.520000 ;
+ RECT 580.320000 2275.360000 581.420000 2275.840000 ;
+ RECT 580.320000 2280.800000 581.420000 2281.280000 ;
+ RECT 580.320000 2286.240000 581.420000 2286.720000 ;
+ RECT 580.320000 2291.680000 581.420000 2292.160000 ;
+ RECT 580.320000 2297.120000 581.420000 2297.600000 ;
+ RECT 580.320000 2253.600000 581.420000 2254.080000 ;
+ RECT 580.320000 2259.040000 581.420000 2259.520000 ;
+ RECT 580.320000 2264.480000 581.420000 2264.960000 ;
+ RECT 580.320000 2269.920000 581.420000 2270.400000 ;
+ RECT 535.320000 2329.760000 536.420000 2330.240000 ;
+ RECT 535.320000 2324.320000 536.420000 2324.800000 ;
+ RECT 535.320000 2335.200000 536.420000 2335.680000 ;
+ RECT 535.320000 2340.640000 536.420000 2341.120000 ;
+ RECT 490.320000 2324.320000 491.420000 2324.800000 ;
+ RECT 490.320000 2329.760000 491.420000 2330.240000 ;
+ RECT 490.320000 2335.200000 491.420000 2335.680000 ;
+ RECT 490.320000 2340.640000 491.420000 2341.120000 ;
+ RECT 535.320000 2302.560000 536.420000 2303.040000 ;
+ RECT 535.320000 2308.000000 536.420000 2308.480000 ;
+ RECT 535.320000 2313.440000 536.420000 2313.920000 ;
+ RECT 535.320000 2318.880000 536.420000 2319.360000 ;
+ RECT 490.320000 2302.560000 491.420000 2303.040000 ;
+ RECT 490.320000 2308.000000 491.420000 2308.480000 ;
+ RECT 490.320000 2313.440000 491.420000 2313.920000 ;
+ RECT 490.320000 2318.880000 491.420000 2319.360000 ;
+ RECT 441.490000 2340.640000 442.490000 2341.120000 ;
+ RECT 445.155000 2340.640000 446.420000 2341.120000 ;
+ RECT 441.490000 2329.760000 442.490000 2330.240000 ;
+ RECT 445.155000 2329.760000 446.420000 2330.240000 ;
+ RECT 441.490000 2335.200000 442.490000 2335.680000 ;
+ RECT 445.155000 2335.200000 446.420000 2335.680000 ;
+ RECT 441.490000 2324.320000 442.490000 2324.800000 ;
+ RECT 445.155000 2324.320000 446.420000 2324.800000 ;
+ RECT 441.490000 2318.880000 442.490000 2319.360000 ;
+ RECT 445.155000 2318.880000 446.420000 2319.360000 ;
+ RECT 441.490000 2313.440000 442.490000 2313.920000 ;
+ RECT 445.155000 2313.440000 446.420000 2313.920000 ;
+ RECT 441.490000 2308.000000 442.490000 2308.480000 ;
+ RECT 445.155000 2308.000000 446.420000 2308.480000 ;
+ RECT 441.490000 2302.560000 442.490000 2303.040000 ;
+ RECT 445.155000 2302.560000 446.420000 2303.040000 ;
+ RECT 535.320000 2275.360000 536.420000 2275.840000 ;
+ RECT 535.320000 2280.800000 536.420000 2281.280000 ;
+ RECT 535.320000 2286.240000 536.420000 2286.720000 ;
+ RECT 535.320000 2291.680000 536.420000 2292.160000 ;
+ RECT 535.320000 2297.120000 536.420000 2297.600000 ;
+ RECT 490.320000 2275.360000 491.420000 2275.840000 ;
+ RECT 490.320000 2280.800000 491.420000 2281.280000 ;
+ RECT 490.320000 2286.240000 491.420000 2286.720000 ;
+ RECT 490.320000 2291.680000 491.420000 2292.160000 ;
+ RECT 490.320000 2297.120000 491.420000 2297.600000 ;
+ RECT 535.320000 2253.600000 536.420000 2254.080000 ;
+ RECT 535.320000 2259.040000 536.420000 2259.520000 ;
+ RECT 535.320000 2264.480000 536.420000 2264.960000 ;
+ RECT 535.320000 2269.920000 536.420000 2270.400000 ;
+ RECT 490.320000 2253.600000 491.420000 2254.080000 ;
+ RECT 490.320000 2259.040000 491.420000 2259.520000 ;
+ RECT 490.320000 2264.480000 491.420000 2264.960000 ;
+ RECT 490.320000 2269.920000 491.420000 2270.400000 ;
+ RECT 441.490000 2297.120000 442.490000 2297.600000 ;
+ RECT 445.155000 2297.120000 446.420000 2297.600000 ;
+ RECT 441.490000 2286.240000 442.490000 2286.720000 ;
+ RECT 445.155000 2286.240000 446.420000 2286.720000 ;
+ RECT 441.490000 2291.680000 442.490000 2292.160000 ;
+ RECT 445.155000 2291.680000 446.420000 2292.160000 ;
+ RECT 441.490000 2280.800000 442.490000 2281.280000 ;
+ RECT 445.155000 2280.800000 446.420000 2281.280000 ;
+ RECT 441.490000 2275.360000 442.490000 2275.840000 ;
+ RECT 445.155000 2275.360000 446.420000 2275.840000 ;
+ RECT 441.490000 2269.920000 442.490000 2270.400000 ;
+ RECT 445.155000 2269.920000 446.420000 2270.400000 ;
+ RECT 441.490000 2264.480000 442.490000 2264.960000 ;
+ RECT 445.155000 2264.480000 446.420000 2264.960000 ;
+ RECT 441.490000 2259.040000 442.490000 2259.520000 ;
+ RECT 445.155000 2259.040000 446.420000 2259.520000 ;
+ RECT 441.490000 2253.600000 442.490000 2254.080000 ;
+ RECT 445.155000 2253.600000 446.420000 2254.080000 ;
+ RECT 625.320000 2237.280000 626.420000 2237.760000 ;
+ RECT 625.320000 2242.720000 626.420000 2243.200000 ;
+ RECT 638.130000 2237.280000 639.130000 2237.760000 ;
+ RECT 638.130000 2242.720000 639.130000 2243.200000 ;
+ RECT 638.130000 2226.400000 639.130000 2226.880000 ;
+ RECT 638.130000 2231.840000 639.130000 2232.320000 ;
+ RECT 625.320000 2231.840000 626.420000 2232.320000 ;
+ RECT 625.320000 2226.400000 626.420000 2226.880000 ;
+ RECT 625.320000 2215.520000 626.420000 2216.000000 ;
+ RECT 625.320000 2220.960000 626.420000 2221.440000 ;
+ RECT 638.130000 2215.520000 639.130000 2216.000000 ;
+ RECT 638.130000 2220.960000 639.130000 2221.440000 ;
+ RECT 638.130000 2204.640000 639.130000 2205.120000 ;
+ RECT 638.130000 2199.200000 639.130000 2199.680000 ;
+ RECT 638.130000 2210.080000 639.130000 2210.560000 ;
+ RECT 625.320000 2210.080000 626.420000 2210.560000 ;
+ RECT 625.320000 2204.640000 626.420000 2205.120000 ;
+ RECT 625.320000 2199.200000 626.420000 2199.680000 ;
+ RECT 580.320000 2226.400000 581.420000 2226.880000 ;
+ RECT 580.320000 2231.840000 581.420000 2232.320000 ;
+ RECT 580.320000 2237.280000 581.420000 2237.760000 ;
+ RECT 580.320000 2242.720000 581.420000 2243.200000 ;
+ RECT 580.320000 2199.200000 581.420000 2199.680000 ;
+ RECT 580.320000 2204.640000 581.420000 2205.120000 ;
+ RECT 580.320000 2210.080000 581.420000 2210.560000 ;
+ RECT 580.320000 2215.520000 581.420000 2216.000000 ;
+ RECT 580.320000 2220.960000 581.420000 2221.440000 ;
+ RECT 625.320000 2188.320000 626.420000 2188.800000 ;
+ RECT 625.320000 2193.760000 626.420000 2194.240000 ;
+ RECT 638.130000 2188.320000 639.130000 2188.800000 ;
+ RECT 638.130000 2193.760000 639.130000 2194.240000 ;
+ RECT 625.320000 2177.440000 626.420000 2177.920000 ;
+ RECT 625.320000 2182.880000 626.420000 2183.360000 ;
+ RECT 638.130000 2177.440000 639.130000 2177.920000 ;
+ RECT 638.130000 2182.880000 639.130000 2183.360000 ;
+ RECT 638.130000 2166.560000 639.130000 2167.040000 ;
+ RECT 638.130000 2161.120000 639.130000 2161.600000 ;
+ RECT 638.130000 2172.000000 639.130000 2172.480000 ;
+ RECT 625.320000 2172.000000 626.420000 2172.480000 ;
+ RECT 625.320000 2166.560000 626.420000 2167.040000 ;
+ RECT 625.320000 2161.120000 626.420000 2161.600000 ;
+ RECT 625.320000 2155.680000 626.420000 2156.160000 ;
+ RECT 638.130000 2155.680000 639.130000 2156.160000 ;
+ RECT 580.320000 2177.440000 581.420000 2177.920000 ;
+ RECT 580.320000 2182.880000 581.420000 2183.360000 ;
+ RECT 580.320000 2188.320000 581.420000 2188.800000 ;
+ RECT 580.320000 2193.760000 581.420000 2194.240000 ;
+ RECT 580.320000 2155.680000 581.420000 2156.160000 ;
+ RECT 580.320000 2161.120000 581.420000 2161.600000 ;
+ RECT 580.320000 2166.560000 581.420000 2167.040000 ;
+ RECT 580.320000 2172.000000 581.420000 2172.480000 ;
+ RECT 535.320000 2226.400000 536.420000 2226.880000 ;
+ RECT 535.320000 2231.840000 536.420000 2232.320000 ;
+ RECT 535.320000 2237.280000 536.420000 2237.760000 ;
+ RECT 535.320000 2242.720000 536.420000 2243.200000 ;
+ RECT 490.320000 2226.400000 491.420000 2226.880000 ;
+ RECT 490.320000 2231.840000 491.420000 2232.320000 ;
+ RECT 490.320000 2237.280000 491.420000 2237.760000 ;
+ RECT 490.320000 2242.720000 491.420000 2243.200000 ;
+ RECT 535.320000 2199.200000 536.420000 2199.680000 ;
+ RECT 535.320000 2204.640000 536.420000 2205.120000 ;
+ RECT 535.320000 2210.080000 536.420000 2210.560000 ;
+ RECT 535.320000 2215.520000 536.420000 2216.000000 ;
+ RECT 535.320000 2220.960000 536.420000 2221.440000 ;
+ RECT 490.320000 2199.200000 491.420000 2199.680000 ;
+ RECT 490.320000 2204.640000 491.420000 2205.120000 ;
+ RECT 490.320000 2210.080000 491.420000 2210.560000 ;
+ RECT 490.320000 2215.520000 491.420000 2216.000000 ;
+ RECT 490.320000 2220.960000 491.420000 2221.440000 ;
+ RECT 441.490000 2242.720000 442.490000 2243.200000 ;
+ RECT 445.155000 2242.720000 446.420000 2243.200000 ;
+ RECT 441.490000 2237.280000 442.490000 2237.760000 ;
+ RECT 445.155000 2237.280000 446.420000 2237.760000 ;
+ RECT 441.490000 2231.840000 442.490000 2232.320000 ;
+ RECT 445.155000 2231.840000 446.420000 2232.320000 ;
+ RECT 441.490000 2226.400000 442.490000 2226.880000 ;
+ RECT 445.155000 2226.400000 446.420000 2226.880000 ;
+ RECT 441.490000 2220.960000 442.490000 2221.440000 ;
+ RECT 445.155000 2220.960000 446.420000 2221.440000 ;
+ RECT 441.490000 2215.520000 442.490000 2216.000000 ;
+ RECT 445.155000 2215.520000 446.420000 2216.000000 ;
+ RECT 441.490000 2204.640000 442.490000 2205.120000 ;
+ RECT 445.155000 2204.640000 446.420000 2205.120000 ;
+ RECT 441.490000 2210.080000 442.490000 2210.560000 ;
+ RECT 445.155000 2210.080000 446.420000 2210.560000 ;
+ RECT 441.490000 2199.200000 442.490000 2199.680000 ;
+ RECT 445.155000 2199.200000 446.420000 2199.680000 ;
+ RECT 535.320000 2177.440000 536.420000 2177.920000 ;
+ RECT 535.320000 2182.880000 536.420000 2183.360000 ;
+ RECT 535.320000 2188.320000 536.420000 2188.800000 ;
+ RECT 535.320000 2193.760000 536.420000 2194.240000 ;
+ RECT 490.320000 2177.440000 491.420000 2177.920000 ;
+ RECT 490.320000 2182.880000 491.420000 2183.360000 ;
+ RECT 490.320000 2188.320000 491.420000 2188.800000 ;
+ RECT 490.320000 2193.760000 491.420000 2194.240000 ;
+ RECT 535.320000 2155.680000 536.420000 2156.160000 ;
+ RECT 535.320000 2161.120000 536.420000 2161.600000 ;
+ RECT 535.320000 2166.560000 536.420000 2167.040000 ;
+ RECT 535.320000 2172.000000 536.420000 2172.480000 ;
+ RECT 490.320000 2155.680000 491.420000 2156.160000 ;
+ RECT 490.320000 2161.120000 491.420000 2161.600000 ;
+ RECT 490.320000 2166.560000 491.420000 2167.040000 ;
+ RECT 490.320000 2172.000000 491.420000 2172.480000 ;
+ RECT 441.490000 2193.760000 442.490000 2194.240000 ;
+ RECT 445.155000 2193.760000 446.420000 2194.240000 ;
+ RECT 441.490000 2188.320000 442.490000 2188.800000 ;
+ RECT 445.155000 2188.320000 446.420000 2188.800000 ;
+ RECT 441.490000 2182.880000 442.490000 2183.360000 ;
+ RECT 445.155000 2182.880000 446.420000 2183.360000 ;
+ RECT 441.490000 2177.440000 442.490000 2177.920000 ;
+ RECT 445.155000 2177.440000 446.420000 2177.920000 ;
+ RECT 441.490000 2172.000000 442.490000 2172.480000 ;
+ RECT 445.155000 2172.000000 446.420000 2172.480000 ;
+ RECT 441.490000 2161.120000 442.490000 2161.600000 ;
+ RECT 445.155000 2161.120000 446.420000 2161.600000 ;
+ RECT 441.490000 2166.560000 442.490000 2167.040000 ;
+ RECT 445.155000 2166.560000 446.420000 2167.040000 ;
+ RECT 441.490000 2155.680000 442.490000 2156.160000 ;
+ RECT 445.155000 2155.680000 446.420000 2156.160000 ;
+ RECT 580.320000 2248.160000 581.420000 2248.640000 ;
+ RECT 625.320000 2248.160000 626.420000 2248.640000 ;
+ RECT 638.130000 2248.160000 639.130000 2248.640000 ;
+ RECT 490.320000 2248.160000 491.420000 2248.640000 ;
+ RECT 535.320000 2248.160000 536.420000 2248.640000 ;
+ RECT 441.490000 2248.160000 442.490000 2248.640000 ;
+ RECT 445.155000 2248.160000 446.420000 2248.640000 ;
+ RECT 440.260000 2344.920000 640.360000 2345.920000 ;
+ RECT 440.260000 2149.350000 640.360000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 2148.100000 442.490000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 2347.360000 442.490000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 2148.100000 639.130000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 2347.360000 639.130000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2149.350000 441.260000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2149.350000 640.360000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2344.920000 441.260000 2345.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2344.920000 640.360000 2345.920000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 2140.380000 446.420000 2140.860000 ;
+ RECT 445.155000 2129.500000 446.420000 2129.980000 ;
+ RECT 445.155000 2134.940000 446.420000 2135.420000 ;
+ RECT 445.155000 2124.060000 446.420000 2124.540000 ;
+ RECT 445.155000 2118.620000 446.420000 2119.100000 ;
+ RECT 445.155000 2113.180000 446.420000 2113.660000 ;
+ RECT 445.155000 2107.740000 446.420000 2108.220000 ;
+ RECT 445.155000 2102.300000 446.420000 2102.780000 ;
+ RECT 445.155000 2096.860000 446.420000 2097.340000 ;
+ RECT 445.155000 2085.980000 446.420000 2086.460000 ;
+ RECT 445.155000 2091.420000 446.420000 2091.900000 ;
+ RECT 445.155000 2080.540000 446.420000 2081.020000 ;
+ RECT 445.155000 2075.100000 446.420000 2075.580000 ;
+ RECT 445.155000 2069.660000 446.420000 2070.140000 ;
+ RECT 445.155000 2064.220000 446.420000 2064.700000 ;
+ RECT 445.155000 2058.780000 446.420000 2059.260000 ;
+ RECT 445.155000 2053.340000 446.420000 2053.820000 ;
+ RECT 445.155000 2042.460000 446.420000 2042.940000 ;
+ RECT 445.155000 2037.020000 446.420000 2037.500000 ;
+ RECT 445.155000 2031.580000 446.420000 2032.060000 ;
+ RECT 445.155000 2026.140000 446.420000 2026.620000 ;
+ RECT 445.155000 2020.700000 446.420000 2021.180000 ;
+ RECT 445.155000 2015.260000 446.420000 2015.740000 ;
+ RECT 445.155000 2004.380000 446.420000 2004.860000 ;
+ RECT 445.155000 2009.820000 446.420000 2010.300000 ;
+ RECT 445.155000 1998.940000 446.420000 1999.420000 ;
+ RECT 445.155000 1993.500000 446.420000 1993.980000 ;
+ RECT 445.155000 1988.060000 446.420000 1988.540000 ;
+ RECT 445.155000 1982.620000 446.420000 1983.100000 ;
+ RECT 445.155000 1977.180000 446.420000 1977.660000 ;
+ RECT 445.155000 1971.740000 446.420000 1972.220000 ;
+ RECT 445.155000 1960.860000 446.420000 1961.340000 ;
+ RECT 445.155000 1966.300000 446.420000 1966.780000 ;
+ RECT 445.155000 1955.420000 446.420000 1955.900000 ;
+ RECT 445.155000 2047.900000 446.420000 2048.380000 ;
+ RECT 625.320000 1949.090000 626.420000 2145.660000 ;
+ RECT 580.320000 1949.090000 581.420000 2145.660000 ;
+ RECT 638.130000 1947.840000 639.130000 2148.100000 ;
+ RECT 535.320000 1949.090000 536.420000 2145.660000 ;
+ RECT 490.320000 1949.090000 491.420000 2145.660000 ;
+ RECT 445.320000 1949.090000 446.420000 2145.660000 ;
+ RECT 441.490000 1947.840000 442.490000 2148.100000 ;
+ LAYER met3 ;
+ RECT 625.320000 2140.380000 626.420000 2140.860000 ;
+ RECT 638.130000 2140.380000 639.130000 2140.860000 ;
+ RECT 638.130000 2129.500000 639.130000 2129.980000 ;
+ RECT 638.130000 2124.060000 639.130000 2124.540000 ;
+ RECT 638.130000 2134.940000 639.130000 2135.420000 ;
+ RECT 625.320000 2134.940000 626.420000 2135.420000 ;
+ RECT 625.320000 2129.500000 626.420000 2129.980000 ;
+ RECT 625.320000 2124.060000 626.420000 2124.540000 ;
+ RECT 625.320000 2113.180000 626.420000 2113.660000 ;
+ RECT 625.320000 2118.620000 626.420000 2119.100000 ;
+ RECT 638.130000 2113.180000 639.130000 2113.660000 ;
+ RECT 638.130000 2118.620000 639.130000 2119.100000 ;
+ RECT 625.320000 2102.300000 626.420000 2102.780000 ;
+ RECT 625.320000 2107.740000 626.420000 2108.220000 ;
+ RECT 638.130000 2102.300000 639.130000 2102.780000 ;
+ RECT 638.130000 2107.740000 639.130000 2108.220000 ;
+ RECT 580.320000 2124.060000 581.420000 2124.540000 ;
+ RECT 580.320000 2129.500000 581.420000 2129.980000 ;
+ RECT 580.320000 2134.940000 581.420000 2135.420000 ;
+ RECT 580.320000 2140.380000 581.420000 2140.860000 ;
+ RECT 580.320000 2107.740000 581.420000 2108.220000 ;
+ RECT 580.320000 2102.300000 581.420000 2102.780000 ;
+ RECT 580.320000 2113.180000 581.420000 2113.660000 ;
+ RECT 580.320000 2118.620000 581.420000 2119.100000 ;
+ RECT 638.130000 2091.420000 639.130000 2091.900000 ;
+ RECT 638.130000 2085.980000 639.130000 2086.460000 ;
+ RECT 638.130000 2096.860000 639.130000 2097.340000 ;
+ RECT 625.320000 2096.860000 626.420000 2097.340000 ;
+ RECT 625.320000 2091.420000 626.420000 2091.900000 ;
+ RECT 625.320000 2085.980000 626.420000 2086.460000 ;
+ RECT 625.320000 2075.100000 626.420000 2075.580000 ;
+ RECT 625.320000 2080.540000 626.420000 2081.020000 ;
+ RECT 638.130000 2075.100000 639.130000 2075.580000 ;
+ RECT 638.130000 2080.540000 639.130000 2081.020000 ;
+ RECT 638.130000 2064.220000 639.130000 2064.700000 ;
+ RECT 638.130000 2069.660000 639.130000 2070.140000 ;
+ RECT 625.320000 2069.660000 626.420000 2070.140000 ;
+ RECT 625.320000 2064.220000 626.420000 2064.700000 ;
+ RECT 625.320000 2053.340000 626.420000 2053.820000 ;
+ RECT 625.320000 2058.780000 626.420000 2059.260000 ;
+ RECT 638.130000 2053.340000 639.130000 2053.820000 ;
+ RECT 638.130000 2058.780000 639.130000 2059.260000 ;
+ RECT 580.320000 2075.100000 581.420000 2075.580000 ;
+ RECT 580.320000 2080.540000 581.420000 2081.020000 ;
+ RECT 580.320000 2085.980000 581.420000 2086.460000 ;
+ RECT 580.320000 2091.420000 581.420000 2091.900000 ;
+ RECT 580.320000 2096.860000 581.420000 2097.340000 ;
+ RECT 580.320000 2053.340000 581.420000 2053.820000 ;
+ RECT 580.320000 2058.780000 581.420000 2059.260000 ;
+ RECT 580.320000 2064.220000 581.420000 2064.700000 ;
+ RECT 580.320000 2069.660000 581.420000 2070.140000 ;
+ RECT 535.320000 2129.500000 536.420000 2129.980000 ;
+ RECT 535.320000 2124.060000 536.420000 2124.540000 ;
+ RECT 535.320000 2134.940000 536.420000 2135.420000 ;
+ RECT 535.320000 2140.380000 536.420000 2140.860000 ;
+ RECT 490.320000 2124.060000 491.420000 2124.540000 ;
+ RECT 490.320000 2129.500000 491.420000 2129.980000 ;
+ RECT 490.320000 2134.940000 491.420000 2135.420000 ;
+ RECT 490.320000 2140.380000 491.420000 2140.860000 ;
+ RECT 535.320000 2102.300000 536.420000 2102.780000 ;
+ RECT 535.320000 2107.740000 536.420000 2108.220000 ;
+ RECT 535.320000 2113.180000 536.420000 2113.660000 ;
+ RECT 535.320000 2118.620000 536.420000 2119.100000 ;
+ RECT 490.320000 2102.300000 491.420000 2102.780000 ;
+ RECT 490.320000 2107.740000 491.420000 2108.220000 ;
+ RECT 490.320000 2113.180000 491.420000 2113.660000 ;
+ RECT 490.320000 2118.620000 491.420000 2119.100000 ;
+ RECT 441.490000 2140.380000 442.490000 2140.860000 ;
+ RECT 445.155000 2140.380000 446.420000 2140.860000 ;
+ RECT 441.490000 2129.500000 442.490000 2129.980000 ;
+ RECT 445.155000 2129.500000 446.420000 2129.980000 ;
+ RECT 441.490000 2134.940000 442.490000 2135.420000 ;
+ RECT 445.155000 2134.940000 446.420000 2135.420000 ;
+ RECT 441.490000 2124.060000 442.490000 2124.540000 ;
+ RECT 445.155000 2124.060000 446.420000 2124.540000 ;
+ RECT 441.490000 2118.620000 442.490000 2119.100000 ;
+ RECT 445.155000 2118.620000 446.420000 2119.100000 ;
+ RECT 441.490000 2113.180000 442.490000 2113.660000 ;
+ RECT 445.155000 2113.180000 446.420000 2113.660000 ;
+ RECT 441.490000 2107.740000 442.490000 2108.220000 ;
+ RECT 445.155000 2107.740000 446.420000 2108.220000 ;
+ RECT 441.490000 2102.300000 442.490000 2102.780000 ;
+ RECT 445.155000 2102.300000 446.420000 2102.780000 ;
+ RECT 535.320000 2075.100000 536.420000 2075.580000 ;
+ RECT 535.320000 2080.540000 536.420000 2081.020000 ;
+ RECT 535.320000 2085.980000 536.420000 2086.460000 ;
+ RECT 535.320000 2091.420000 536.420000 2091.900000 ;
+ RECT 535.320000 2096.860000 536.420000 2097.340000 ;
+ RECT 490.320000 2075.100000 491.420000 2075.580000 ;
+ RECT 490.320000 2080.540000 491.420000 2081.020000 ;
+ RECT 490.320000 2085.980000 491.420000 2086.460000 ;
+ RECT 490.320000 2091.420000 491.420000 2091.900000 ;
+ RECT 490.320000 2096.860000 491.420000 2097.340000 ;
+ RECT 535.320000 2053.340000 536.420000 2053.820000 ;
+ RECT 535.320000 2058.780000 536.420000 2059.260000 ;
+ RECT 535.320000 2064.220000 536.420000 2064.700000 ;
+ RECT 535.320000 2069.660000 536.420000 2070.140000 ;
+ RECT 490.320000 2053.340000 491.420000 2053.820000 ;
+ RECT 490.320000 2058.780000 491.420000 2059.260000 ;
+ RECT 490.320000 2064.220000 491.420000 2064.700000 ;
+ RECT 490.320000 2069.660000 491.420000 2070.140000 ;
+ RECT 441.490000 2096.860000 442.490000 2097.340000 ;
+ RECT 445.155000 2096.860000 446.420000 2097.340000 ;
+ RECT 441.490000 2085.980000 442.490000 2086.460000 ;
+ RECT 445.155000 2085.980000 446.420000 2086.460000 ;
+ RECT 441.490000 2091.420000 442.490000 2091.900000 ;
+ RECT 445.155000 2091.420000 446.420000 2091.900000 ;
+ RECT 441.490000 2080.540000 442.490000 2081.020000 ;
+ RECT 445.155000 2080.540000 446.420000 2081.020000 ;
+ RECT 441.490000 2075.100000 442.490000 2075.580000 ;
+ RECT 445.155000 2075.100000 446.420000 2075.580000 ;
+ RECT 441.490000 2069.660000 442.490000 2070.140000 ;
+ RECT 445.155000 2069.660000 446.420000 2070.140000 ;
+ RECT 441.490000 2064.220000 442.490000 2064.700000 ;
+ RECT 445.155000 2064.220000 446.420000 2064.700000 ;
+ RECT 441.490000 2058.780000 442.490000 2059.260000 ;
+ RECT 445.155000 2058.780000 446.420000 2059.260000 ;
+ RECT 441.490000 2053.340000 442.490000 2053.820000 ;
+ RECT 445.155000 2053.340000 446.420000 2053.820000 ;
+ RECT 625.320000 2037.020000 626.420000 2037.500000 ;
+ RECT 625.320000 2042.460000 626.420000 2042.940000 ;
+ RECT 638.130000 2037.020000 639.130000 2037.500000 ;
+ RECT 638.130000 2042.460000 639.130000 2042.940000 ;
+ RECT 638.130000 2026.140000 639.130000 2026.620000 ;
+ RECT 638.130000 2031.580000 639.130000 2032.060000 ;
+ RECT 625.320000 2031.580000 626.420000 2032.060000 ;
+ RECT 625.320000 2026.140000 626.420000 2026.620000 ;
+ RECT 625.320000 2015.260000 626.420000 2015.740000 ;
+ RECT 625.320000 2020.700000 626.420000 2021.180000 ;
+ RECT 638.130000 2015.260000 639.130000 2015.740000 ;
+ RECT 638.130000 2020.700000 639.130000 2021.180000 ;
+ RECT 638.130000 2004.380000 639.130000 2004.860000 ;
+ RECT 638.130000 1998.940000 639.130000 1999.420000 ;
+ RECT 638.130000 2009.820000 639.130000 2010.300000 ;
+ RECT 625.320000 2009.820000 626.420000 2010.300000 ;
+ RECT 625.320000 2004.380000 626.420000 2004.860000 ;
+ RECT 625.320000 1998.940000 626.420000 1999.420000 ;
+ RECT 580.320000 2026.140000 581.420000 2026.620000 ;
+ RECT 580.320000 2031.580000 581.420000 2032.060000 ;
+ RECT 580.320000 2037.020000 581.420000 2037.500000 ;
+ RECT 580.320000 2042.460000 581.420000 2042.940000 ;
+ RECT 580.320000 1998.940000 581.420000 1999.420000 ;
+ RECT 580.320000 2004.380000 581.420000 2004.860000 ;
+ RECT 580.320000 2009.820000 581.420000 2010.300000 ;
+ RECT 580.320000 2015.260000 581.420000 2015.740000 ;
+ RECT 580.320000 2020.700000 581.420000 2021.180000 ;
+ RECT 625.320000 1988.060000 626.420000 1988.540000 ;
+ RECT 625.320000 1993.500000 626.420000 1993.980000 ;
+ RECT 638.130000 1988.060000 639.130000 1988.540000 ;
+ RECT 638.130000 1993.500000 639.130000 1993.980000 ;
+ RECT 625.320000 1977.180000 626.420000 1977.660000 ;
+ RECT 625.320000 1982.620000 626.420000 1983.100000 ;
+ RECT 638.130000 1977.180000 639.130000 1977.660000 ;
+ RECT 638.130000 1982.620000 639.130000 1983.100000 ;
+ RECT 638.130000 1966.300000 639.130000 1966.780000 ;
+ RECT 638.130000 1960.860000 639.130000 1961.340000 ;
+ RECT 638.130000 1971.740000 639.130000 1972.220000 ;
+ RECT 625.320000 1971.740000 626.420000 1972.220000 ;
+ RECT 625.320000 1966.300000 626.420000 1966.780000 ;
+ RECT 625.320000 1960.860000 626.420000 1961.340000 ;
+ RECT 625.320000 1955.420000 626.420000 1955.900000 ;
+ RECT 638.130000 1955.420000 639.130000 1955.900000 ;
+ RECT 580.320000 1977.180000 581.420000 1977.660000 ;
+ RECT 580.320000 1982.620000 581.420000 1983.100000 ;
+ RECT 580.320000 1988.060000 581.420000 1988.540000 ;
+ RECT 580.320000 1993.500000 581.420000 1993.980000 ;
+ RECT 580.320000 1955.420000 581.420000 1955.900000 ;
+ RECT 580.320000 1960.860000 581.420000 1961.340000 ;
+ RECT 580.320000 1966.300000 581.420000 1966.780000 ;
+ RECT 580.320000 1971.740000 581.420000 1972.220000 ;
+ RECT 535.320000 2026.140000 536.420000 2026.620000 ;
+ RECT 535.320000 2031.580000 536.420000 2032.060000 ;
+ RECT 535.320000 2037.020000 536.420000 2037.500000 ;
+ RECT 535.320000 2042.460000 536.420000 2042.940000 ;
+ RECT 490.320000 2026.140000 491.420000 2026.620000 ;
+ RECT 490.320000 2031.580000 491.420000 2032.060000 ;
+ RECT 490.320000 2037.020000 491.420000 2037.500000 ;
+ RECT 490.320000 2042.460000 491.420000 2042.940000 ;
+ RECT 535.320000 1998.940000 536.420000 1999.420000 ;
+ RECT 535.320000 2004.380000 536.420000 2004.860000 ;
+ RECT 535.320000 2009.820000 536.420000 2010.300000 ;
+ RECT 535.320000 2015.260000 536.420000 2015.740000 ;
+ RECT 535.320000 2020.700000 536.420000 2021.180000 ;
+ RECT 490.320000 1998.940000 491.420000 1999.420000 ;
+ RECT 490.320000 2004.380000 491.420000 2004.860000 ;
+ RECT 490.320000 2009.820000 491.420000 2010.300000 ;
+ RECT 490.320000 2015.260000 491.420000 2015.740000 ;
+ RECT 490.320000 2020.700000 491.420000 2021.180000 ;
+ RECT 441.490000 2042.460000 442.490000 2042.940000 ;
+ RECT 445.155000 2042.460000 446.420000 2042.940000 ;
+ RECT 441.490000 2037.020000 442.490000 2037.500000 ;
+ RECT 445.155000 2037.020000 446.420000 2037.500000 ;
+ RECT 441.490000 2031.580000 442.490000 2032.060000 ;
+ RECT 445.155000 2031.580000 446.420000 2032.060000 ;
+ RECT 441.490000 2026.140000 442.490000 2026.620000 ;
+ RECT 445.155000 2026.140000 446.420000 2026.620000 ;
+ RECT 441.490000 2020.700000 442.490000 2021.180000 ;
+ RECT 445.155000 2020.700000 446.420000 2021.180000 ;
+ RECT 441.490000 2015.260000 442.490000 2015.740000 ;
+ RECT 445.155000 2015.260000 446.420000 2015.740000 ;
+ RECT 441.490000 2004.380000 442.490000 2004.860000 ;
+ RECT 445.155000 2004.380000 446.420000 2004.860000 ;
+ RECT 441.490000 2009.820000 442.490000 2010.300000 ;
+ RECT 445.155000 2009.820000 446.420000 2010.300000 ;
+ RECT 441.490000 1998.940000 442.490000 1999.420000 ;
+ RECT 445.155000 1998.940000 446.420000 1999.420000 ;
+ RECT 535.320000 1977.180000 536.420000 1977.660000 ;
+ RECT 535.320000 1982.620000 536.420000 1983.100000 ;
+ RECT 535.320000 1988.060000 536.420000 1988.540000 ;
+ RECT 535.320000 1993.500000 536.420000 1993.980000 ;
+ RECT 490.320000 1977.180000 491.420000 1977.660000 ;
+ RECT 490.320000 1982.620000 491.420000 1983.100000 ;
+ RECT 490.320000 1988.060000 491.420000 1988.540000 ;
+ RECT 490.320000 1993.500000 491.420000 1993.980000 ;
+ RECT 535.320000 1955.420000 536.420000 1955.900000 ;
+ RECT 535.320000 1960.860000 536.420000 1961.340000 ;
+ RECT 535.320000 1966.300000 536.420000 1966.780000 ;
+ RECT 535.320000 1971.740000 536.420000 1972.220000 ;
+ RECT 490.320000 1955.420000 491.420000 1955.900000 ;
+ RECT 490.320000 1960.860000 491.420000 1961.340000 ;
+ RECT 490.320000 1966.300000 491.420000 1966.780000 ;
+ RECT 490.320000 1971.740000 491.420000 1972.220000 ;
+ RECT 441.490000 1993.500000 442.490000 1993.980000 ;
+ RECT 445.155000 1993.500000 446.420000 1993.980000 ;
+ RECT 441.490000 1988.060000 442.490000 1988.540000 ;
+ RECT 445.155000 1988.060000 446.420000 1988.540000 ;
+ RECT 441.490000 1982.620000 442.490000 1983.100000 ;
+ RECT 445.155000 1982.620000 446.420000 1983.100000 ;
+ RECT 441.490000 1977.180000 442.490000 1977.660000 ;
+ RECT 445.155000 1977.180000 446.420000 1977.660000 ;
+ RECT 441.490000 1971.740000 442.490000 1972.220000 ;
+ RECT 445.155000 1971.740000 446.420000 1972.220000 ;
+ RECT 441.490000 1960.860000 442.490000 1961.340000 ;
+ RECT 445.155000 1960.860000 446.420000 1961.340000 ;
+ RECT 441.490000 1966.300000 442.490000 1966.780000 ;
+ RECT 445.155000 1966.300000 446.420000 1966.780000 ;
+ RECT 441.490000 1955.420000 442.490000 1955.900000 ;
+ RECT 445.155000 1955.420000 446.420000 1955.900000 ;
+ RECT 580.320000 2047.900000 581.420000 2048.380000 ;
+ RECT 625.320000 2047.900000 626.420000 2048.380000 ;
+ RECT 638.130000 2047.900000 639.130000 2048.380000 ;
+ RECT 490.320000 2047.900000 491.420000 2048.380000 ;
+ RECT 535.320000 2047.900000 536.420000 2048.380000 ;
+ RECT 441.490000 2047.900000 442.490000 2048.380000 ;
+ RECT 445.155000 2047.900000 446.420000 2048.380000 ;
+ RECT 440.260000 2144.660000 640.360000 2145.660000 ;
+ RECT 440.260000 1949.090000 640.360000 1950.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 1947.840000 442.490000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 2147.100000 442.490000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 1947.840000 639.130000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 2147.100000 639.130000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1949.090000 441.260000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1949.090000 640.360000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2144.660000 441.260000 2145.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2144.660000 640.360000 2145.660000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 1940.120000 446.420000 1940.600000 ;
+ RECT 445.155000 1929.240000 446.420000 1929.720000 ;
+ RECT 445.155000 1934.680000 446.420000 1935.160000 ;
+ RECT 445.155000 1923.800000 446.420000 1924.280000 ;
+ RECT 445.155000 1918.360000 446.420000 1918.840000 ;
+ RECT 445.155000 1912.920000 446.420000 1913.400000 ;
+ RECT 445.155000 1907.480000 446.420000 1907.960000 ;
+ RECT 445.155000 1902.040000 446.420000 1902.520000 ;
+ RECT 445.155000 1896.600000 446.420000 1897.080000 ;
+ RECT 445.155000 1885.720000 446.420000 1886.200000 ;
+ RECT 445.155000 1891.160000 446.420000 1891.640000 ;
+ RECT 445.155000 1880.280000 446.420000 1880.760000 ;
+ RECT 445.155000 1874.840000 446.420000 1875.320000 ;
+ RECT 445.155000 1869.400000 446.420000 1869.880000 ;
+ RECT 445.155000 1863.960000 446.420000 1864.440000 ;
+ RECT 445.155000 1858.520000 446.420000 1859.000000 ;
+ RECT 445.155000 1853.080000 446.420000 1853.560000 ;
+ RECT 445.155000 1842.200000 446.420000 1842.680000 ;
+ RECT 445.155000 1836.760000 446.420000 1837.240000 ;
+ RECT 445.155000 1831.320000 446.420000 1831.800000 ;
+ RECT 445.155000 1825.880000 446.420000 1826.360000 ;
+ RECT 445.155000 1820.440000 446.420000 1820.920000 ;
+ RECT 445.155000 1815.000000 446.420000 1815.480000 ;
+ RECT 445.155000 1804.120000 446.420000 1804.600000 ;
+ RECT 445.155000 1809.560000 446.420000 1810.040000 ;
+ RECT 445.155000 1798.680000 446.420000 1799.160000 ;
+ RECT 445.155000 1793.240000 446.420000 1793.720000 ;
+ RECT 445.155000 1787.800000 446.420000 1788.280000 ;
+ RECT 445.155000 1782.360000 446.420000 1782.840000 ;
+ RECT 445.155000 1776.920000 446.420000 1777.400000 ;
+ RECT 445.155000 1771.480000 446.420000 1771.960000 ;
+ RECT 445.155000 1760.600000 446.420000 1761.080000 ;
+ RECT 445.155000 1766.040000 446.420000 1766.520000 ;
+ RECT 445.155000 1755.160000 446.420000 1755.640000 ;
+ RECT 445.155000 1847.640000 446.420000 1848.120000 ;
+ RECT 625.320000 1748.830000 626.420000 1945.400000 ;
+ RECT 580.320000 1748.830000 581.420000 1945.400000 ;
+ RECT 638.130000 1747.580000 639.130000 1947.840000 ;
+ RECT 535.320000 1748.830000 536.420000 1945.400000 ;
+ RECT 490.320000 1748.830000 491.420000 1945.400000 ;
+ RECT 445.320000 1748.830000 446.420000 1945.400000 ;
+ RECT 441.490000 1747.580000 442.490000 1947.840000 ;
+ LAYER met3 ;
+ RECT 625.320000 1940.120000 626.420000 1940.600000 ;
+ RECT 638.130000 1940.120000 639.130000 1940.600000 ;
+ RECT 638.130000 1929.240000 639.130000 1929.720000 ;
+ RECT 638.130000 1923.800000 639.130000 1924.280000 ;
+ RECT 638.130000 1934.680000 639.130000 1935.160000 ;
+ RECT 625.320000 1934.680000 626.420000 1935.160000 ;
+ RECT 625.320000 1929.240000 626.420000 1929.720000 ;
+ RECT 625.320000 1923.800000 626.420000 1924.280000 ;
+ RECT 625.320000 1912.920000 626.420000 1913.400000 ;
+ RECT 625.320000 1918.360000 626.420000 1918.840000 ;
+ RECT 638.130000 1912.920000 639.130000 1913.400000 ;
+ RECT 638.130000 1918.360000 639.130000 1918.840000 ;
+ RECT 625.320000 1902.040000 626.420000 1902.520000 ;
+ RECT 625.320000 1907.480000 626.420000 1907.960000 ;
+ RECT 638.130000 1902.040000 639.130000 1902.520000 ;
+ RECT 638.130000 1907.480000 639.130000 1907.960000 ;
+ RECT 580.320000 1923.800000 581.420000 1924.280000 ;
+ RECT 580.320000 1929.240000 581.420000 1929.720000 ;
+ RECT 580.320000 1934.680000 581.420000 1935.160000 ;
+ RECT 580.320000 1940.120000 581.420000 1940.600000 ;
+ RECT 580.320000 1907.480000 581.420000 1907.960000 ;
+ RECT 580.320000 1902.040000 581.420000 1902.520000 ;
+ RECT 580.320000 1912.920000 581.420000 1913.400000 ;
+ RECT 580.320000 1918.360000 581.420000 1918.840000 ;
+ RECT 638.130000 1891.160000 639.130000 1891.640000 ;
+ RECT 638.130000 1885.720000 639.130000 1886.200000 ;
+ RECT 638.130000 1896.600000 639.130000 1897.080000 ;
+ RECT 625.320000 1896.600000 626.420000 1897.080000 ;
+ RECT 625.320000 1891.160000 626.420000 1891.640000 ;
+ RECT 625.320000 1885.720000 626.420000 1886.200000 ;
+ RECT 625.320000 1874.840000 626.420000 1875.320000 ;
+ RECT 625.320000 1880.280000 626.420000 1880.760000 ;
+ RECT 638.130000 1874.840000 639.130000 1875.320000 ;
+ RECT 638.130000 1880.280000 639.130000 1880.760000 ;
+ RECT 638.130000 1863.960000 639.130000 1864.440000 ;
+ RECT 638.130000 1869.400000 639.130000 1869.880000 ;
+ RECT 625.320000 1869.400000 626.420000 1869.880000 ;
+ RECT 625.320000 1863.960000 626.420000 1864.440000 ;
+ RECT 625.320000 1853.080000 626.420000 1853.560000 ;
+ RECT 625.320000 1858.520000 626.420000 1859.000000 ;
+ RECT 638.130000 1853.080000 639.130000 1853.560000 ;
+ RECT 638.130000 1858.520000 639.130000 1859.000000 ;
+ RECT 580.320000 1874.840000 581.420000 1875.320000 ;
+ RECT 580.320000 1880.280000 581.420000 1880.760000 ;
+ RECT 580.320000 1885.720000 581.420000 1886.200000 ;
+ RECT 580.320000 1891.160000 581.420000 1891.640000 ;
+ RECT 580.320000 1896.600000 581.420000 1897.080000 ;
+ RECT 580.320000 1853.080000 581.420000 1853.560000 ;
+ RECT 580.320000 1858.520000 581.420000 1859.000000 ;
+ RECT 580.320000 1863.960000 581.420000 1864.440000 ;
+ RECT 580.320000 1869.400000 581.420000 1869.880000 ;
+ RECT 535.320000 1929.240000 536.420000 1929.720000 ;
+ RECT 535.320000 1923.800000 536.420000 1924.280000 ;
+ RECT 535.320000 1934.680000 536.420000 1935.160000 ;
+ RECT 535.320000 1940.120000 536.420000 1940.600000 ;
+ RECT 490.320000 1923.800000 491.420000 1924.280000 ;
+ RECT 490.320000 1929.240000 491.420000 1929.720000 ;
+ RECT 490.320000 1934.680000 491.420000 1935.160000 ;
+ RECT 490.320000 1940.120000 491.420000 1940.600000 ;
+ RECT 535.320000 1902.040000 536.420000 1902.520000 ;
+ RECT 535.320000 1907.480000 536.420000 1907.960000 ;
+ RECT 535.320000 1912.920000 536.420000 1913.400000 ;
+ RECT 535.320000 1918.360000 536.420000 1918.840000 ;
+ RECT 490.320000 1902.040000 491.420000 1902.520000 ;
+ RECT 490.320000 1907.480000 491.420000 1907.960000 ;
+ RECT 490.320000 1912.920000 491.420000 1913.400000 ;
+ RECT 490.320000 1918.360000 491.420000 1918.840000 ;
+ RECT 441.490000 1940.120000 442.490000 1940.600000 ;
+ RECT 445.155000 1940.120000 446.420000 1940.600000 ;
+ RECT 441.490000 1929.240000 442.490000 1929.720000 ;
+ RECT 445.155000 1929.240000 446.420000 1929.720000 ;
+ RECT 441.490000 1934.680000 442.490000 1935.160000 ;
+ RECT 445.155000 1934.680000 446.420000 1935.160000 ;
+ RECT 441.490000 1923.800000 442.490000 1924.280000 ;
+ RECT 445.155000 1923.800000 446.420000 1924.280000 ;
+ RECT 441.490000 1918.360000 442.490000 1918.840000 ;
+ RECT 445.155000 1918.360000 446.420000 1918.840000 ;
+ RECT 441.490000 1912.920000 442.490000 1913.400000 ;
+ RECT 445.155000 1912.920000 446.420000 1913.400000 ;
+ RECT 441.490000 1907.480000 442.490000 1907.960000 ;
+ RECT 445.155000 1907.480000 446.420000 1907.960000 ;
+ RECT 441.490000 1902.040000 442.490000 1902.520000 ;
+ RECT 445.155000 1902.040000 446.420000 1902.520000 ;
+ RECT 535.320000 1874.840000 536.420000 1875.320000 ;
+ RECT 535.320000 1880.280000 536.420000 1880.760000 ;
+ RECT 535.320000 1885.720000 536.420000 1886.200000 ;
+ RECT 535.320000 1891.160000 536.420000 1891.640000 ;
+ RECT 535.320000 1896.600000 536.420000 1897.080000 ;
+ RECT 490.320000 1874.840000 491.420000 1875.320000 ;
+ RECT 490.320000 1880.280000 491.420000 1880.760000 ;
+ RECT 490.320000 1885.720000 491.420000 1886.200000 ;
+ RECT 490.320000 1891.160000 491.420000 1891.640000 ;
+ RECT 490.320000 1896.600000 491.420000 1897.080000 ;
+ RECT 535.320000 1853.080000 536.420000 1853.560000 ;
+ RECT 535.320000 1858.520000 536.420000 1859.000000 ;
+ RECT 535.320000 1863.960000 536.420000 1864.440000 ;
+ RECT 535.320000 1869.400000 536.420000 1869.880000 ;
+ RECT 490.320000 1853.080000 491.420000 1853.560000 ;
+ RECT 490.320000 1858.520000 491.420000 1859.000000 ;
+ RECT 490.320000 1863.960000 491.420000 1864.440000 ;
+ RECT 490.320000 1869.400000 491.420000 1869.880000 ;
+ RECT 441.490000 1896.600000 442.490000 1897.080000 ;
+ RECT 445.155000 1896.600000 446.420000 1897.080000 ;
+ RECT 441.490000 1885.720000 442.490000 1886.200000 ;
+ RECT 445.155000 1885.720000 446.420000 1886.200000 ;
+ RECT 441.490000 1891.160000 442.490000 1891.640000 ;
+ RECT 445.155000 1891.160000 446.420000 1891.640000 ;
+ RECT 441.490000 1880.280000 442.490000 1880.760000 ;
+ RECT 445.155000 1880.280000 446.420000 1880.760000 ;
+ RECT 441.490000 1874.840000 442.490000 1875.320000 ;
+ RECT 445.155000 1874.840000 446.420000 1875.320000 ;
+ RECT 441.490000 1869.400000 442.490000 1869.880000 ;
+ RECT 445.155000 1869.400000 446.420000 1869.880000 ;
+ RECT 441.490000 1863.960000 442.490000 1864.440000 ;
+ RECT 445.155000 1863.960000 446.420000 1864.440000 ;
+ RECT 441.490000 1858.520000 442.490000 1859.000000 ;
+ RECT 445.155000 1858.520000 446.420000 1859.000000 ;
+ RECT 441.490000 1853.080000 442.490000 1853.560000 ;
+ RECT 445.155000 1853.080000 446.420000 1853.560000 ;
+ RECT 625.320000 1836.760000 626.420000 1837.240000 ;
+ RECT 625.320000 1842.200000 626.420000 1842.680000 ;
+ RECT 638.130000 1836.760000 639.130000 1837.240000 ;
+ RECT 638.130000 1842.200000 639.130000 1842.680000 ;
+ RECT 638.130000 1825.880000 639.130000 1826.360000 ;
+ RECT 638.130000 1831.320000 639.130000 1831.800000 ;
+ RECT 625.320000 1831.320000 626.420000 1831.800000 ;
+ RECT 625.320000 1825.880000 626.420000 1826.360000 ;
+ RECT 625.320000 1815.000000 626.420000 1815.480000 ;
+ RECT 625.320000 1820.440000 626.420000 1820.920000 ;
+ RECT 638.130000 1815.000000 639.130000 1815.480000 ;
+ RECT 638.130000 1820.440000 639.130000 1820.920000 ;
+ RECT 638.130000 1804.120000 639.130000 1804.600000 ;
+ RECT 638.130000 1798.680000 639.130000 1799.160000 ;
+ RECT 638.130000 1809.560000 639.130000 1810.040000 ;
+ RECT 625.320000 1809.560000 626.420000 1810.040000 ;
+ RECT 625.320000 1804.120000 626.420000 1804.600000 ;
+ RECT 625.320000 1798.680000 626.420000 1799.160000 ;
+ RECT 580.320000 1825.880000 581.420000 1826.360000 ;
+ RECT 580.320000 1831.320000 581.420000 1831.800000 ;
+ RECT 580.320000 1836.760000 581.420000 1837.240000 ;
+ RECT 580.320000 1842.200000 581.420000 1842.680000 ;
+ RECT 580.320000 1798.680000 581.420000 1799.160000 ;
+ RECT 580.320000 1804.120000 581.420000 1804.600000 ;
+ RECT 580.320000 1809.560000 581.420000 1810.040000 ;
+ RECT 580.320000 1815.000000 581.420000 1815.480000 ;
+ RECT 580.320000 1820.440000 581.420000 1820.920000 ;
+ RECT 625.320000 1787.800000 626.420000 1788.280000 ;
+ RECT 625.320000 1793.240000 626.420000 1793.720000 ;
+ RECT 638.130000 1787.800000 639.130000 1788.280000 ;
+ RECT 638.130000 1793.240000 639.130000 1793.720000 ;
+ RECT 625.320000 1776.920000 626.420000 1777.400000 ;
+ RECT 625.320000 1782.360000 626.420000 1782.840000 ;
+ RECT 638.130000 1776.920000 639.130000 1777.400000 ;
+ RECT 638.130000 1782.360000 639.130000 1782.840000 ;
+ RECT 638.130000 1766.040000 639.130000 1766.520000 ;
+ RECT 638.130000 1760.600000 639.130000 1761.080000 ;
+ RECT 638.130000 1771.480000 639.130000 1771.960000 ;
+ RECT 625.320000 1771.480000 626.420000 1771.960000 ;
+ RECT 625.320000 1766.040000 626.420000 1766.520000 ;
+ RECT 625.320000 1760.600000 626.420000 1761.080000 ;
+ RECT 625.320000 1755.160000 626.420000 1755.640000 ;
+ RECT 638.130000 1755.160000 639.130000 1755.640000 ;
+ RECT 580.320000 1776.920000 581.420000 1777.400000 ;
+ RECT 580.320000 1782.360000 581.420000 1782.840000 ;
+ RECT 580.320000 1787.800000 581.420000 1788.280000 ;
+ RECT 580.320000 1793.240000 581.420000 1793.720000 ;
+ RECT 580.320000 1755.160000 581.420000 1755.640000 ;
+ RECT 580.320000 1760.600000 581.420000 1761.080000 ;
+ RECT 580.320000 1766.040000 581.420000 1766.520000 ;
+ RECT 580.320000 1771.480000 581.420000 1771.960000 ;
+ RECT 535.320000 1825.880000 536.420000 1826.360000 ;
+ RECT 535.320000 1831.320000 536.420000 1831.800000 ;
+ RECT 535.320000 1836.760000 536.420000 1837.240000 ;
+ RECT 535.320000 1842.200000 536.420000 1842.680000 ;
+ RECT 490.320000 1825.880000 491.420000 1826.360000 ;
+ RECT 490.320000 1831.320000 491.420000 1831.800000 ;
+ RECT 490.320000 1836.760000 491.420000 1837.240000 ;
+ RECT 490.320000 1842.200000 491.420000 1842.680000 ;
+ RECT 535.320000 1798.680000 536.420000 1799.160000 ;
+ RECT 535.320000 1804.120000 536.420000 1804.600000 ;
+ RECT 535.320000 1809.560000 536.420000 1810.040000 ;
+ RECT 535.320000 1815.000000 536.420000 1815.480000 ;
+ RECT 535.320000 1820.440000 536.420000 1820.920000 ;
+ RECT 490.320000 1798.680000 491.420000 1799.160000 ;
+ RECT 490.320000 1804.120000 491.420000 1804.600000 ;
+ RECT 490.320000 1809.560000 491.420000 1810.040000 ;
+ RECT 490.320000 1815.000000 491.420000 1815.480000 ;
+ RECT 490.320000 1820.440000 491.420000 1820.920000 ;
+ RECT 441.490000 1842.200000 442.490000 1842.680000 ;
+ RECT 445.155000 1842.200000 446.420000 1842.680000 ;
+ RECT 441.490000 1836.760000 442.490000 1837.240000 ;
+ RECT 445.155000 1836.760000 446.420000 1837.240000 ;
+ RECT 441.490000 1831.320000 442.490000 1831.800000 ;
+ RECT 445.155000 1831.320000 446.420000 1831.800000 ;
+ RECT 441.490000 1825.880000 442.490000 1826.360000 ;
+ RECT 445.155000 1825.880000 446.420000 1826.360000 ;
+ RECT 441.490000 1820.440000 442.490000 1820.920000 ;
+ RECT 445.155000 1820.440000 446.420000 1820.920000 ;
+ RECT 441.490000 1815.000000 442.490000 1815.480000 ;
+ RECT 445.155000 1815.000000 446.420000 1815.480000 ;
+ RECT 441.490000 1804.120000 442.490000 1804.600000 ;
+ RECT 445.155000 1804.120000 446.420000 1804.600000 ;
+ RECT 441.490000 1809.560000 442.490000 1810.040000 ;
+ RECT 445.155000 1809.560000 446.420000 1810.040000 ;
+ RECT 441.490000 1798.680000 442.490000 1799.160000 ;
+ RECT 445.155000 1798.680000 446.420000 1799.160000 ;
+ RECT 535.320000 1776.920000 536.420000 1777.400000 ;
+ RECT 535.320000 1782.360000 536.420000 1782.840000 ;
+ RECT 535.320000 1787.800000 536.420000 1788.280000 ;
+ RECT 535.320000 1793.240000 536.420000 1793.720000 ;
+ RECT 490.320000 1776.920000 491.420000 1777.400000 ;
+ RECT 490.320000 1782.360000 491.420000 1782.840000 ;
+ RECT 490.320000 1787.800000 491.420000 1788.280000 ;
+ RECT 490.320000 1793.240000 491.420000 1793.720000 ;
+ RECT 535.320000 1755.160000 536.420000 1755.640000 ;
+ RECT 535.320000 1760.600000 536.420000 1761.080000 ;
+ RECT 535.320000 1766.040000 536.420000 1766.520000 ;
+ RECT 535.320000 1771.480000 536.420000 1771.960000 ;
+ RECT 490.320000 1755.160000 491.420000 1755.640000 ;
+ RECT 490.320000 1760.600000 491.420000 1761.080000 ;
+ RECT 490.320000 1766.040000 491.420000 1766.520000 ;
+ RECT 490.320000 1771.480000 491.420000 1771.960000 ;
+ RECT 441.490000 1793.240000 442.490000 1793.720000 ;
+ RECT 445.155000 1793.240000 446.420000 1793.720000 ;
+ RECT 441.490000 1787.800000 442.490000 1788.280000 ;
+ RECT 445.155000 1787.800000 446.420000 1788.280000 ;
+ RECT 441.490000 1782.360000 442.490000 1782.840000 ;
+ RECT 445.155000 1782.360000 446.420000 1782.840000 ;
+ RECT 441.490000 1776.920000 442.490000 1777.400000 ;
+ RECT 445.155000 1776.920000 446.420000 1777.400000 ;
+ RECT 441.490000 1771.480000 442.490000 1771.960000 ;
+ RECT 445.155000 1771.480000 446.420000 1771.960000 ;
+ RECT 441.490000 1760.600000 442.490000 1761.080000 ;
+ RECT 445.155000 1760.600000 446.420000 1761.080000 ;
+ RECT 441.490000 1766.040000 442.490000 1766.520000 ;
+ RECT 445.155000 1766.040000 446.420000 1766.520000 ;
+ RECT 441.490000 1755.160000 442.490000 1755.640000 ;
+ RECT 445.155000 1755.160000 446.420000 1755.640000 ;
+ RECT 580.320000 1847.640000 581.420000 1848.120000 ;
+ RECT 625.320000 1847.640000 626.420000 1848.120000 ;
+ RECT 638.130000 1847.640000 639.130000 1848.120000 ;
+ RECT 490.320000 1847.640000 491.420000 1848.120000 ;
+ RECT 535.320000 1847.640000 536.420000 1848.120000 ;
+ RECT 441.490000 1847.640000 442.490000 1848.120000 ;
+ RECT 445.155000 1847.640000 446.420000 1848.120000 ;
+ RECT 440.260000 1944.400000 640.360000 1945.400000 ;
+ RECT 440.260000 1748.830000 640.360000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 1747.580000 442.490000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 1946.840000 442.490000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 1747.580000 639.130000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 1946.840000 639.130000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1748.830000 441.260000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1748.830000 640.360000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1944.400000 441.260000 1945.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1944.400000 640.360000 1945.400000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 445.155000 1739.860000 446.420000 1740.340000 ;
+ RECT 445.155000 1728.980000 446.420000 1729.460000 ;
+ RECT 445.155000 1734.420000 446.420000 1734.900000 ;
+ RECT 445.155000 1723.540000 446.420000 1724.020000 ;
+ RECT 445.155000 1718.100000 446.420000 1718.580000 ;
+ RECT 445.155000 1712.660000 446.420000 1713.140000 ;
+ RECT 445.155000 1707.220000 446.420000 1707.700000 ;
+ RECT 445.155000 1701.780000 446.420000 1702.260000 ;
+ RECT 445.155000 1696.340000 446.420000 1696.820000 ;
+ RECT 445.155000 1685.460000 446.420000 1685.940000 ;
+ RECT 445.155000 1690.900000 446.420000 1691.380000 ;
+ RECT 445.155000 1680.020000 446.420000 1680.500000 ;
+ RECT 445.155000 1674.580000 446.420000 1675.060000 ;
+ RECT 445.155000 1669.140000 446.420000 1669.620000 ;
+ RECT 445.155000 1663.700000 446.420000 1664.180000 ;
+ RECT 445.155000 1658.260000 446.420000 1658.740000 ;
+ RECT 445.155000 1652.820000 446.420000 1653.300000 ;
+ RECT 445.155000 1641.940000 446.420000 1642.420000 ;
+ RECT 445.155000 1636.500000 446.420000 1636.980000 ;
+ RECT 445.155000 1631.060000 446.420000 1631.540000 ;
+ RECT 445.155000 1625.620000 446.420000 1626.100000 ;
+ RECT 445.155000 1620.180000 446.420000 1620.660000 ;
+ RECT 445.155000 1614.740000 446.420000 1615.220000 ;
+ RECT 445.155000 1603.860000 446.420000 1604.340000 ;
+ RECT 445.155000 1609.300000 446.420000 1609.780000 ;
+ RECT 445.155000 1598.420000 446.420000 1598.900000 ;
+ RECT 445.155000 1592.980000 446.420000 1593.460000 ;
+ RECT 445.155000 1587.540000 446.420000 1588.020000 ;
+ RECT 445.155000 1582.100000 446.420000 1582.580000 ;
+ RECT 445.155000 1576.660000 446.420000 1577.140000 ;
+ RECT 445.155000 1571.220000 446.420000 1571.700000 ;
+ RECT 445.155000 1560.340000 446.420000 1560.820000 ;
+ RECT 445.155000 1565.780000 446.420000 1566.260000 ;
+ RECT 445.155000 1554.900000 446.420000 1555.380000 ;
+ RECT 445.155000 1647.380000 446.420000 1647.860000 ;
+ RECT 625.320000 1548.570000 626.420000 1745.140000 ;
+ RECT 580.320000 1548.570000 581.420000 1745.140000 ;
+ RECT 638.130000 1547.320000 639.130000 1747.580000 ;
+ RECT 535.320000 1548.570000 536.420000 1745.140000 ;
+ RECT 490.320000 1548.570000 491.420000 1745.140000 ;
+ RECT 445.320000 1548.570000 446.420000 1745.140000 ;
+ RECT 441.490000 1547.320000 442.490000 1747.580000 ;
+ LAYER met3 ;
+ RECT 625.320000 1739.860000 626.420000 1740.340000 ;
+ RECT 638.130000 1739.860000 639.130000 1740.340000 ;
+ RECT 638.130000 1728.980000 639.130000 1729.460000 ;
+ RECT 638.130000 1723.540000 639.130000 1724.020000 ;
+ RECT 638.130000 1734.420000 639.130000 1734.900000 ;
+ RECT 625.320000 1734.420000 626.420000 1734.900000 ;
+ RECT 625.320000 1728.980000 626.420000 1729.460000 ;
+ RECT 625.320000 1723.540000 626.420000 1724.020000 ;
+ RECT 625.320000 1712.660000 626.420000 1713.140000 ;
+ RECT 625.320000 1718.100000 626.420000 1718.580000 ;
+ RECT 638.130000 1712.660000 639.130000 1713.140000 ;
+ RECT 638.130000 1718.100000 639.130000 1718.580000 ;
+ RECT 625.320000 1701.780000 626.420000 1702.260000 ;
+ RECT 625.320000 1707.220000 626.420000 1707.700000 ;
+ RECT 638.130000 1701.780000 639.130000 1702.260000 ;
+ RECT 638.130000 1707.220000 639.130000 1707.700000 ;
+ RECT 580.320000 1723.540000 581.420000 1724.020000 ;
+ RECT 580.320000 1728.980000 581.420000 1729.460000 ;
+ RECT 580.320000 1734.420000 581.420000 1734.900000 ;
+ RECT 580.320000 1739.860000 581.420000 1740.340000 ;
+ RECT 580.320000 1707.220000 581.420000 1707.700000 ;
+ RECT 580.320000 1701.780000 581.420000 1702.260000 ;
+ RECT 580.320000 1712.660000 581.420000 1713.140000 ;
+ RECT 580.320000 1718.100000 581.420000 1718.580000 ;
+ RECT 638.130000 1690.900000 639.130000 1691.380000 ;
+ RECT 638.130000 1685.460000 639.130000 1685.940000 ;
+ RECT 638.130000 1696.340000 639.130000 1696.820000 ;
+ RECT 625.320000 1696.340000 626.420000 1696.820000 ;
+ RECT 625.320000 1690.900000 626.420000 1691.380000 ;
+ RECT 625.320000 1685.460000 626.420000 1685.940000 ;
+ RECT 625.320000 1674.580000 626.420000 1675.060000 ;
+ RECT 625.320000 1680.020000 626.420000 1680.500000 ;
+ RECT 638.130000 1674.580000 639.130000 1675.060000 ;
+ RECT 638.130000 1680.020000 639.130000 1680.500000 ;
+ RECT 638.130000 1663.700000 639.130000 1664.180000 ;
+ RECT 638.130000 1669.140000 639.130000 1669.620000 ;
+ RECT 625.320000 1669.140000 626.420000 1669.620000 ;
+ RECT 625.320000 1663.700000 626.420000 1664.180000 ;
+ RECT 625.320000 1652.820000 626.420000 1653.300000 ;
+ RECT 625.320000 1658.260000 626.420000 1658.740000 ;
+ RECT 638.130000 1652.820000 639.130000 1653.300000 ;
+ RECT 638.130000 1658.260000 639.130000 1658.740000 ;
+ RECT 580.320000 1674.580000 581.420000 1675.060000 ;
+ RECT 580.320000 1680.020000 581.420000 1680.500000 ;
+ RECT 580.320000 1685.460000 581.420000 1685.940000 ;
+ RECT 580.320000 1690.900000 581.420000 1691.380000 ;
+ RECT 580.320000 1696.340000 581.420000 1696.820000 ;
+ RECT 580.320000 1652.820000 581.420000 1653.300000 ;
+ RECT 580.320000 1658.260000 581.420000 1658.740000 ;
+ RECT 580.320000 1663.700000 581.420000 1664.180000 ;
+ RECT 580.320000 1669.140000 581.420000 1669.620000 ;
+ RECT 535.320000 1728.980000 536.420000 1729.460000 ;
+ RECT 535.320000 1723.540000 536.420000 1724.020000 ;
+ RECT 535.320000 1734.420000 536.420000 1734.900000 ;
+ RECT 535.320000 1739.860000 536.420000 1740.340000 ;
+ RECT 490.320000 1723.540000 491.420000 1724.020000 ;
+ RECT 490.320000 1728.980000 491.420000 1729.460000 ;
+ RECT 490.320000 1734.420000 491.420000 1734.900000 ;
+ RECT 490.320000 1739.860000 491.420000 1740.340000 ;
+ RECT 535.320000 1701.780000 536.420000 1702.260000 ;
+ RECT 535.320000 1707.220000 536.420000 1707.700000 ;
+ RECT 535.320000 1712.660000 536.420000 1713.140000 ;
+ RECT 535.320000 1718.100000 536.420000 1718.580000 ;
+ RECT 490.320000 1701.780000 491.420000 1702.260000 ;
+ RECT 490.320000 1707.220000 491.420000 1707.700000 ;
+ RECT 490.320000 1712.660000 491.420000 1713.140000 ;
+ RECT 490.320000 1718.100000 491.420000 1718.580000 ;
+ RECT 441.490000 1739.860000 442.490000 1740.340000 ;
+ RECT 445.155000 1739.860000 446.420000 1740.340000 ;
+ RECT 441.490000 1728.980000 442.490000 1729.460000 ;
+ RECT 445.155000 1728.980000 446.420000 1729.460000 ;
+ RECT 441.490000 1734.420000 442.490000 1734.900000 ;
+ RECT 445.155000 1734.420000 446.420000 1734.900000 ;
+ RECT 441.490000 1723.540000 442.490000 1724.020000 ;
+ RECT 445.155000 1723.540000 446.420000 1724.020000 ;
+ RECT 441.490000 1718.100000 442.490000 1718.580000 ;
+ RECT 445.155000 1718.100000 446.420000 1718.580000 ;
+ RECT 441.490000 1712.660000 442.490000 1713.140000 ;
+ RECT 445.155000 1712.660000 446.420000 1713.140000 ;
+ RECT 441.490000 1707.220000 442.490000 1707.700000 ;
+ RECT 445.155000 1707.220000 446.420000 1707.700000 ;
+ RECT 441.490000 1701.780000 442.490000 1702.260000 ;
+ RECT 445.155000 1701.780000 446.420000 1702.260000 ;
+ RECT 535.320000 1674.580000 536.420000 1675.060000 ;
+ RECT 535.320000 1680.020000 536.420000 1680.500000 ;
+ RECT 535.320000 1685.460000 536.420000 1685.940000 ;
+ RECT 535.320000 1690.900000 536.420000 1691.380000 ;
+ RECT 535.320000 1696.340000 536.420000 1696.820000 ;
+ RECT 490.320000 1674.580000 491.420000 1675.060000 ;
+ RECT 490.320000 1680.020000 491.420000 1680.500000 ;
+ RECT 490.320000 1685.460000 491.420000 1685.940000 ;
+ RECT 490.320000 1690.900000 491.420000 1691.380000 ;
+ RECT 490.320000 1696.340000 491.420000 1696.820000 ;
+ RECT 535.320000 1652.820000 536.420000 1653.300000 ;
+ RECT 535.320000 1658.260000 536.420000 1658.740000 ;
+ RECT 535.320000 1663.700000 536.420000 1664.180000 ;
+ RECT 535.320000 1669.140000 536.420000 1669.620000 ;
+ RECT 490.320000 1652.820000 491.420000 1653.300000 ;
+ RECT 490.320000 1658.260000 491.420000 1658.740000 ;
+ RECT 490.320000 1663.700000 491.420000 1664.180000 ;
+ RECT 490.320000 1669.140000 491.420000 1669.620000 ;
+ RECT 441.490000 1696.340000 442.490000 1696.820000 ;
+ RECT 445.155000 1696.340000 446.420000 1696.820000 ;
+ RECT 441.490000 1685.460000 442.490000 1685.940000 ;
+ RECT 445.155000 1685.460000 446.420000 1685.940000 ;
+ RECT 441.490000 1690.900000 442.490000 1691.380000 ;
+ RECT 445.155000 1690.900000 446.420000 1691.380000 ;
+ RECT 441.490000 1680.020000 442.490000 1680.500000 ;
+ RECT 445.155000 1680.020000 446.420000 1680.500000 ;
+ RECT 441.490000 1674.580000 442.490000 1675.060000 ;
+ RECT 445.155000 1674.580000 446.420000 1675.060000 ;
+ RECT 441.490000 1669.140000 442.490000 1669.620000 ;
+ RECT 445.155000 1669.140000 446.420000 1669.620000 ;
+ RECT 441.490000 1663.700000 442.490000 1664.180000 ;
+ RECT 445.155000 1663.700000 446.420000 1664.180000 ;
+ RECT 441.490000 1658.260000 442.490000 1658.740000 ;
+ RECT 445.155000 1658.260000 446.420000 1658.740000 ;
+ RECT 441.490000 1652.820000 442.490000 1653.300000 ;
+ RECT 445.155000 1652.820000 446.420000 1653.300000 ;
+ RECT 625.320000 1636.500000 626.420000 1636.980000 ;
+ RECT 625.320000 1641.940000 626.420000 1642.420000 ;
+ RECT 638.130000 1636.500000 639.130000 1636.980000 ;
+ RECT 638.130000 1641.940000 639.130000 1642.420000 ;
+ RECT 638.130000 1625.620000 639.130000 1626.100000 ;
+ RECT 638.130000 1631.060000 639.130000 1631.540000 ;
+ RECT 625.320000 1631.060000 626.420000 1631.540000 ;
+ RECT 625.320000 1625.620000 626.420000 1626.100000 ;
+ RECT 625.320000 1614.740000 626.420000 1615.220000 ;
+ RECT 625.320000 1620.180000 626.420000 1620.660000 ;
+ RECT 638.130000 1614.740000 639.130000 1615.220000 ;
+ RECT 638.130000 1620.180000 639.130000 1620.660000 ;
+ RECT 638.130000 1603.860000 639.130000 1604.340000 ;
+ RECT 638.130000 1598.420000 639.130000 1598.900000 ;
+ RECT 638.130000 1609.300000 639.130000 1609.780000 ;
+ RECT 625.320000 1609.300000 626.420000 1609.780000 ;
+ RECT 625.320000 1603.860000 626.420000 1604.340000 ;
+ RECT 625.320000 1598.420000 626.420000 1598.900000 ;
+ RECT 580.320000 1625.620000 581.420000 1626.100000 ;
+ RECT 580.320000 1631.060000 581.420000 1631.540000 ;
+ RECT 580.320000 1636.500000 581.420000 1636.980000 ;
+ RECT 580.320000 1641.940000 581.420000 1642.420000 ;
+ RECT 580.320000 1598.420000 581.420000 1598.900000 ;
+ RECT 580.320000 1603.860000 581.420000 1604.340000 ;
+ RECT 580.320000 1609.300000 581.420000 1609.780000 ;
+ RECT 580.320000 1614.740000 581.420000 1615.220000 ;
+ RECT 580.320000 1620.180000 581.420000 1620.660000 ;
+ RECT 625.320000 1587.540000 626.420000 1588.020000 ;
+ RECT 625.320000 1592.980000 626.420000 1593.460000 ;
+ RECT 638.130000 1587.540000 639.130000 1588.020000 ;
+ RECT 638.130000 1592.980000 639.130000 1593.460000 ;
+ RECT 625.320000 1576.660000 626.420000 1577.140000 ;
+ RECT 625.320000 1582.100000 626.420000 1582.580000 ;
+ RECT 638.130000 1576.660000 639.130000 1577.140000 ;
+ RECT 638.130000 1582.100000 639.130000 1582.580000 ;
+ RECT 638.130000 1565.780000 639.130000 1566.260000 ;
+ RECT 638.130000 1560.340000 639.130000 1560.820000 ;
+ RECT 638.130000 1571.220000 639.130000 1571.700000 ;
+ RECT 625.320000 1571.220000 626.420000 1571.700000 ;
+ RECT 625.320000 1565.780000 626.420000 1566.260000 ;
+ RECT 625.320000 1560.340000 626.420000 1560.820000 ;
+ RECT 625.320000 1554.900000 626.420000 1555.380000 ;
+ RECT 638.130000 1554.900000 639.130000 1555.380000 ;
+ RECT 580.320000 1576.660000 581.420000 1577.140000 ;
+ RECT 580.320000 1582.100000 581.420000 1582.580000 ;
+ RECT 580.320000 1587.540000 581.420000 1588.020000 ;
+ RECT 580.320000 1592.980000 581.420000 1593.460000 ;
+ RECT 580.320000 1554.900000 581.420000 1555.380000 ;
+ RECT 580.320000 1560.340000 581.420000 1560.820000 ;
+ RECT 580.320000 1565.780000 581.420000 1566.260000 ;
+ RECT 580.320000 1571.220000 581.420000 1571.700000 ;
+ RECT 535.320000 1625.620000 536.420000 1626.100000 ;
+ RECT 535.320000 1631.060000 536.420000 1631.540000 ;
+ RECT 535.320000 1636.500000 536.420000 1636.980000 ;
+ RECT 535.320000 1641.940000 536.420000 1642.420000 ;
+ RECT 490.320000 1625.620000 491.420000 1626.100000 ;
+ RECT 490.320000 1631.060000 491.420000 1631.540000 ;
+ RECT 490.320000 1636.500000 491.420000 1636.980000 ;
+ RECT 490.320000 1641.940000 491.420000 1642.420000 ;
+ RECT 535.320000 1598.420000 536.420000 1598.900000 ;
+ RECT 535.320000 1603.860000 536.420000 1604.340000 ;
+ RECT 535.320000 1609.300000 536.420000 1609.780000 ;
+ RECT 535.320000 1614.740000 536.420000 1615.220000 ;
+ RECT 535.320000 1620.180000 536.420000 1620.660000 ;
+ RECT 490.320000 1598.420000 491.420000 1598.900000 ;
+ RECT 490.320000 1603.860000 491.420000 1604.340000 ;
+ RECT 490.320000 1609.300000 491.420000 1609.780000 ;
+ RECT 490.320000 1614.740000 491.420000 1615.220000 ;
+ RECT 490.320000 1620.180000 491.420000 1620.660000 ;
+ RECT 441.490000 1641.940000 442.490000 1642.420000 ;
+ RECT 445.155000 1641.940000 446.420000 1642.420000 ;
+ RECT 441.490000 1636.500000 442.490000 1636.980000 ;
+ RECT 445.155000 1636.500000 446.420000 1636.980000 ;
+ RECT 441.490000 1631.060000 442.490000 1631.540000 ;
+ RECT 445.155000 1631.060000 446.420000 1631.540000 ;
+ RECT 441.490000 1625.620000 442.490000 1626.100000 ;
+ RECT 445.155000 1625.620000 446.420000 1626.100000 ;
+ RECT 441.490000 1620.180000 442.490000 1620.660000 ;
+ RECT 445.155000 1620.180000 446.420000 1620.660000 ;
+ RECT 441.490000 1614.740000 442.490000 1615.220000 ;
+ RECT 445.155000 1614.740000 446.420000 1615.220000 ;
+ RECT 441.490000 1603.860000 442.490000 1604.340000 ;
+ RECT 445.155000 1603.860000 446.420000 1604.340000 ;
+ RECT 441.490000 1609.300000 442.490000 1609.780000 ;
+ RECT 445.155000 1609.300000 446.420000 1609.780000 ;
+ RECT 441.490000 1598.420000 442.490000 1598.900000 ;
+ RECT 445.155000 1598.420000 446.420000 1598.900000 ;
+ RECT 535.320000 1576.660000 536.420000 1577.140000 ;
+ RECT 535.320000 1582.100000 536.420000 1582.580000 ;
+ RECT 535.320000 1587.540000 536.420000 1588.020000 ;
+ RECT 535.320000 1592.980000 536.420000 1593.460000 ;
+ RECT 490.320000 1576.660000 491.420000 1577.140000 ;
+ RECT 490.320000 1582.100000 491.420000 1582.580000 ;
+ RECT 490.320000 1587.540000 491.420000 1588.020000 ;
+ RECT 490.320000 1592.980000 491.420000 1593.460000 ;
+ RECT 535.320000 1554.900000 536.420000 1555.380000 ;
+ RECT 535.320000 1560.340000 536.420000 1560.820000 ;
+ RECT 535.320000 1565.780000 536.420000 1566.260000 ;
+ RECT 535.320000 1571.220000 536.420000 1571.700000 ;
+ RECT 490.320000 1554.900000 491.420000 1555.380000 ;
+ RECT 490.320000 1560.340000 491.420000 1560.820000 ;
+ RECT 490.320000 1565.780000 491.420000 1566.260000 ;
+ RECT 490.320000 1571.220000 491.420000 1571.700000 ;
+ RECT 441.490000 1592.980000 442.490000 1593.460000 ;
+ RECT 445.155000 1592.980000 446.420000 1593.460000 ;
+ RECT 441.490000 1587.540000 442.490000 1588.020000 ;
+ RECT 445.155000 1587.540000 446.420000 1588.020000 ;
+ RECT 441.490000 1582.100000 442.490000 1582.580000 ;
+ RECT 445.155000 1582.100000 446.420000 1582.580000 ;
+ RECT 441.490000 1576.660000 442.490000 1577.140000 ;
+ RECT 445.155000 1576.660000 446.420000 1577.140000 ;
+ RECT 441.490000 1571.220000 442.490000 1571.700000 ;
+ RECT 445.155000 1571.220000 446.420000 1571.700000 ;
+ RECT 441.490000 1560.340000 442.490000 1560.820000 ;
+ RECT 445.155000 1560.340000 446.420000 1560.820000 ;
+ RECT 441.490000 1565.780000 442.490000 1566.260000 ;
+ RECT 445.155000 1565.780000 446.420000 1566.260000 ;
+ RECT 441.490000 1554.900000 442.490000 1555.380000 ;
+ RECT 445.155000 1554.900000 446.420000 1555.380000 ;
+ RECT 580.320000 1647.380000 581.420000 1647.860000 ;
+ RECT 625.320000 1647.380000 626.420000 1647.860000 ;
+ RECT 638.130000 1647.380000 639.130000 1647.860000 ;
+ RECT 490.320000 1647.380000 491.420000 1647.860000 ;
+ RECT 535.320000 1647.380000 536.420000 1647.860000 ;
+ RECT 441.490000 1647.380000 442.490000 1647.860000 ;
+ RECT 445.155000 1647.380000 446.420000 1647.860000 ;
+ RECT 440.260000 1744.140000 640.360000 1745.140000 ;
+ RECT 440.260000 1548.570000 640.360000 1549.570000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 1547.320000 442.490000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 441.490000 1746.580000 442.490000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 1547.320000 639.130000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 638.130000 1746.580000 639.130000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1548.570000 441.260000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1548.570000 640.360000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1744.140000 441.260000 1745.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1744.140000 640.360000 1745.140000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single2'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 3373.560000 646.520000 3374.040000 ;
+ RECT 645.255000 3368.120000 646.520000 3368.600000 ;
+ RECT 645.255000 3362.680000 646.520000 3363.160000 ;
+ RECT 645.255000 3357.240000 646.520000 3357.720000 ;
+ RECT 641.590000 3349.660000 642.590000 3379.920000 ;
+ RECT 838.230000 3349.660000 839.230000 3379.920000 ;
+ RECT 645.420000 3350.910000 646.520000 3378.160000 ;
+ RECT 690.420000 3350.910000 691.520000 3378.160000 ;
+ RECT 735.420000 3350.910000 736.520000 3378.160000 ;
+ RECT 780.420000 3350.910000 781.520000 3378.160000 ;
+ RECT 825.420000 3350.910000 826.520000 3378.160000 ;
+ LAYER met3 ;
+ RECT 838.230000 3373.560000 839.230000 3374.040000 ;
+ RECT 838.230000 3368.120000 839.230000 3368.600000 ;
+ RECT 825.420000 3373.560000 826.520000 3374.040000 ;
+ RECT 825.420000 3368.120000 826.520000 3368.600000 ;
+ RECT 780.420000 3368.120000 781.520000 3368.600000 ;
+ RECT 780.420000 3373.560000 781.520000 3374.040000 ;
+ RECT 735.420000 3368.120000 736.520000 3368.600000 ;
+ RECT 690.420000 3368.120000 691.520000 3368.600000 ;
+ RECT 735.420000 3373.560000 736.520000 3374.040000 ;
+ RECT 690.420000 3373.560000 691.520000 3374.040000 ;
+ RECT 645.255000 3373.560000 646.520000 3374.040000 ;
+ RECT 641.590000 3373.560000 642.590000 3374.040000 ;
+ RECT 645.255000 3368.120000 646.520000 3368.600000 ;
+ RECT 641.590000 3368.120000 642.590000 3368.600000 ;
+ RECT 838.230000 3362.680000 839.230000 3363.160000 ;
+ RECT 838.230000 3357.240000 839.230000 3357.720000 ;
+ RECT 825.420000 3362.680000 826.520000 3363.160000 ;
+ RECT 825.420000 3357.240000 826.520000 3357.720000 ;
+ RECT 780.420000 3357.240000 781.520000 3357.720000 ;
+ RECT 780.420000 3362.680000 781.520000 3363.160000 ;
+ RECT 735.420000 3357.240000 736.520000 3357.720000 ;
+ RECT 690.420000 3357.240000 691.520000 3357.720000 ;
+ RECT 735.420000 3362.680000 736.520000 3363.160000 ;
+ RECT 690.420000 3362.680000 691.520000 3363.160000 ;
+ RECT 645.255000 3362.680000 646.520000 3363.160000 ;
+ RECT 641.590000 3362.680000 642.590000 3363.160000 ;
+ RECT 645.255000 3357.240000 646.520000 3357.720000 ;
+ RECT 641.590000 3357.240000 642.590000 3357.720000 ;
+ RECT 640.360000 3377.160000 840.460000 3378.160000 ;
+ RECT 640.360000 3350.910000 840.460000 3351.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 3349.660000 642.590000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 3378.920000 642.590000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 3349.660000 839.230000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 3378.920000 839.230000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 3350.910000 641.360000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 3350.910000 840.460000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 3377.160000 641.360000 3378.160000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 3377.160000 840.460000 3378.160000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single2'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 1539.600000 646.520000 1540.080000 ;
+ RECT 645.255000 1528.720000 646.520000 1529.200000 ;
+ RECT 645.255000 1534.160000 646.520000 1534.640000 ;
+ RECT 645.255000 1523.280000 646.520000 1523.760000 ;
+ RECT 645.255000 1517.840000 646.520000 1518.320000 ;
+ RECT 645.255000 1512.400000 646.520000 1512.880000 ;
+ RECT 645.255000 1506.960000 646.520000 1507.440000 ;
+ RECT 645.255000 1501.520000 646.520000 1502.000000 ;
+ RECT 645.255000 1496.080000 646.520000 1496.560000 ;
+ RECT 645.255000 1485.200000 646.520000 1485.680000 ;
+ RECT 645.255000 1490.640000 646.520000 1491.120000 ;
+ RECT 645.255000 1479.760000 646.520000 1480.240000 ;
+ RECT 645.255000 1474.320000 646.520000 1474.800000 ;
+ RECT 645.255000 1468.880000 646.520000 1469.360000 ;
+ RECT 645.255000 1463.440000 646.520000 1463.920000 ;
+ RECT 645.255000 1458.000000 646.520000 1458.480000 ;
+ RECT 645.255000 1452.560000 646.520000 1453.040000 ;
+ RECT 645.255000 1441.680000 646.520000 1442.160000 ;
+ RECT 645.255000 1436.240000 646.520000 1436.720000 ;
+ RECT 645.255000 1430.800000 646.520000 1431.280000 ;
+ RECT 645.255000 1425.360000 646.520000 1425.840000 ;
+ RECT 645.255000 1419.920000 646.520000 1420.400000 ;
+ RECT 645.255000 1414.480000 646.520000 1414.960000 ;
+ RECT 645.255000 1403.600000 646.520000 1404.080000 ;
+ RECT 645.255000 1409.040000 646.520000 1409.520000 ;
+ RECT 645.255000 1398.160000 646.520000 1398.640000 ;
+ RECT 645.255000 1392.720000 646.520000 1393.200000 ;
+ RECT 645.255000 1387.280000 646.520000 1387.760000 ;
+ RECT 645.255000 1381.840000 646.520000 1382.320000 ;
+ RECT 645.255000 1376.400000 646.520000 1376.880000 ;
+ RECT 645.255000 1370.960000 646.520000 1371.440000 ;
+ RECT 645.255000 1360.080000 646.520000 1360.560000 ;
+ RECT 645.255000 1365.520000 646.520000 1366.000000 ;
+ RECT 645.255000 1354.640000 646.520000 1355.120000 ;
+ RECT 645.255000 1447.120000 646.520000 1447.600000 ;
+ RECT 825.420000 1348.310000 826.520000 1544.880000 ;
+ RECT 780.420000 1348.310000 781.520000 1544.880000 ;
+ RECT 838.230000 1347.060000 839.230000 1547.320000 ;
+ RECT 735.420000 1348.310000 736.520000 1544.880000 ;
+ RECT 690.420000 1348.310000 691.520000 1544.880000 ;
+ RECT 645.420000 1348.310000 646.520000 1544.880000 ;
+ RECT 641.590000 1347.060000 642.590000 1547.320000 ;
+ LAYER met3 ;
+ RECT 825.420000 1539.600000 826.520000 1540.080000 ;
+ RECT 838.230000 1539.600000 839.230000 1540.080000 ;
+ RECT 838.230000 1528.720000 839.230000 1529.200000 ;
+ RECT 838.230000 1523.280000 839.230000 1523.760000 ;
+ RECT 838.230000 1534.160000 839.230000 1534.640000 ;
+ RECT 825.420000 1534.160000 826.520000 1534.640000 ;
+ RECT 825.420000 1528.720000 826.520000 1529.200000 ;
+ RECT 825.420000 1523.280000 826.520000 1523.760000 ;
+ RECT 825.420000 1512.400000 826.520000 1512.880000 ;
+ RECT 825.420000 1517.840000 826.520000 1518.320000 ;
+ RECT 838.230000 1512.400000 839.230000 1512.880000 ;
+ RECT 838.230000 1517.840000 839.230000 1518.320000 ;
+ RECT 825.420000 1501.520000 826.520000 1502.000000 ;
+ RECT 825.420000 1506.960000 826.520000 1507.440000 ;
+ RECT 838.230000 1501.520000 839.230000 1502.000000 ;
+ RECT 838.230000 1506.960000 839.230000 1507.440000 ;
+ RECT 780.420000 1523.280000 781.520000 1523.760000 ;
+ RECT 780.420000 1528.720000 781.520000 1529.200000 ;
+ RECT 780.420000 1534.160000 781.520000 1534.640000 ;
+ RECT 780.420000 1539.600000 781.520000 1540.080000 ;
+ RECT 780.420000 1506.960000 781.520000 1507.440000 ;
+ RECT 780.420000 1501.520000 781.520000 1502.000000 ;
+ RECT 780.420000 1512.400000 781.520000 1512.880000 ;
+ RECT 780.420000 1517.840000 781.520000 1518.320000 ;
+ RECT 838.230000 1490.640000 839.230000 1491.120000 ;
+ RECT 838.230000 1485.200000 839.230000 1485.680000 ;
+ RECT 838.230000 1496.080000 839.230000 1496.560000 ;
+ RECT 825.420000 1496.080000 826.520000 1496.560000 ;
+ RECT 825.420000 1490.640000 826.520000 1491.120000 ;
+ RECT 825.420000 1485.200000 826.520000 1485.680000 ;
+ RECT 825.420000 1474.320000 826.520000 1474.800000 ;
+ RECT 825.420000 1479.760000 826.520000 1480.240000 ;
+ RECT 838.230000 1474.320000 839.230000 1474.800000 ;
+ RECT 838.230000 1479.760000 839.230000 1480.240000 ;
+ RECT 838.230000 1463.440000 839.230000 1463.920000 ;
+ RECT 838.230000 1468.880000 839.230000 1469.360000 ;
+ RECT 825.420000 1468.880000 826.520000 1469.360000 ;
+ RECT 825.420000 1463.440000 826.520000 1463.920000 ;
+ RECT 825.420000 1452.560000 826.520000 1453.040000 ;
+ RECT 825.420000 1458.000000 826.520000 1458.480000 ;
+ RECT 838.230000 1452.560000 839.230000 1453.040000 ;
+ RECT 838.230000 1458.000000 839.230000 1458.480000 ;
+ RECT 780.420000 1474.320000 781.520000 1474.800000 ;
+ RECT 780.420000 1479.760000 781.520000 1480.240000 ;
+ RECT 780.420000 1485.200000 781.520000 1485.680000 ;
+ RECT 780.420000 1490.640000 781.520000 1491.120000 ;
+ RECT 780.420000 1496.080000 781.520000 1496.560000 ;
+ RECT 780.420000 1452.560000 781.520000 1453.040000 ;
+ RECT 780.420000 1458.000000 781.520000 1458.480000 ;
+ RECT 780.420000 1463.440000 781.520000 1463.920000 ;
+ RECT 780.420000 1468.880000 781.520000 1469.360000 ;
+ RECT 735.420000 1528.720000 736.520000 1529.200000 ;
+ RECT 735.420000 1523.280000 736.520000 1523.760000 ;
+ RECT 735.420000 1534.160000 736.520000 1534.640000 ;
+ RECT 735.420000 1539.600000 736.520000 1540.080000 ;
+ RECT 690.420000 1523.280000 691.520000 1523.760000 ;
+ RECT 690.420000 1528.720000 691.520000 1529.200000 ;
+ RECT 690.420000 1534.160000 691.520000 1534.640000 ;
+ RECT 690.420000 1539.600000 691.520000 1540.080000 ;
+ RECT 735.420000 1501.520000 736.520000 1502.000000 ;
+ RECT 735.420000 1506.960000 736.520000 1507.440000 ;
+ RECT 735.420000 1512.400000 736.520000 1512.880000 ;
+ RECT 735.420000 1517.840000 736.520000 1518.320000 ;
+ RECT 690.420000 1501.520000 691.520000 1502.000000 ;
+ RECT 690.420000 1506.960000 691.520000 1507.440000 ;
+ RECT 690.420000 1512.400000 691.520000 1512.880000 ;
+ RECT 690.420000 1517.840000 691.520000 1518.320000 ;
+ RECT 641.590000 1539.600000 642.590000 1540.080000 ;
+ RECT 645.255000 1539.600000 646.520000 1540.080000 ;
+ RECT 641.590000 1528.720000 642.590000 1529.200000 ;
+ RECT 645.255000 1528.720000 646.520000 1529.200000 ;
+ RECT 641.590000 1534.160000 642.590000 1534.640000 ;
+ RECT 645.255000 1534.160000 646.520000 1534.640000 ;
+ RECT 641.590000 1523.280000 642.590000 1523.760000 ;
+ RECT 645.255000 1523.280000 646.520000 1523.760000 ;
+ RECT 641.590000 1517.840000 642.590000 1518.320000 ;
+ RECT 645.255000 1517.840000 646.520000 1518.320000 ;
+ RECT 641.590000 1512.400000 642.590000 1512.880000 ;
+ RECT 645.255000 1512.400000 646.520000 1512.880000 ;
+ RECT 641.590000 1506.960000 642.590000 1507.440000 ;
+ RECT 645.255000 1506.960000 646.520000 1507.440000 ;
+ RECT 641.590000 1501.520000 642.590000 1502.000000 ;
+ RECT 645.255000 1501.520000 646.520000 1502.000000 ;
+ RECT 735.420000 1474.320000 736.520000 1474.800000 ;
+ RECT 735.420000 1479.760000 736.520000 1480.240000 ;
+ RECT 735.420000 1485.200000 736.520000 1485.680000 ;
+ RECT 735.420000 1490.640000 736.520000 1491.120000 ;
+ RECT 735.420000 1496.080000 736.520000 1496.560000 ;
+ RECT 690.420000 1474.320000 691.520000 1474.800000 ;
+ RECT 690.420000 1479.760000 691.520000 1480.240000 ;
+ RECT 690.420000 1485.200000 691.520000 1485.680000 ;
+ RECT 690.420000 1490.640000 691.520000 1491.120000 ;
+ RECT 690.420000 1496.080000 691.520000 1496.560000 ;
+ RECT 735.420000 1452.560000 736.520000 1453.040000 ;
+ RECT 735.420000 1458.000000 736.520000 1458.480000 ;
+ RECT 735.420000 1463.440000 736.520000 1463.920000 ;
+ RECT 735.420000 1468.880000 736.520000 1469.360000 ;
+ RECT 690.420000 1452.560000 691.520000 1453.040000 ;
+ RECT 690.420000 1458.000000 691.520000 1458.480000 ;
+ RECT 690.420000 1463.440000 691.520000 1463.920000 ;
+ RECT 690.420000 1468.880000 691.520000 1469.360000 ;
+ RECT 641.590000 1496.080000 642.590000 1496.560000 ;
+ RECT 645.255000 1496.080000 646.520000 1496.560000 ;
+ RECT 641.590000 1485.200000 642.590000 1485.680000 ;
+ RECT 645.255000 1485.200000 646.520000 1485.680000 ;
+ RECT 641.590000 1490.640000 642.590000 1491.120000 ;
+ RECT 645.255000 1490.640000 646.520000 1491.120000 ;
+ RECT 641.590000 1479.760000 642.590000 1480.240000 ;
+ RECT 645.255000 1479.760000 646.520000 1480.240000 ;
+ RECT 641.590000 1474.320000 642.590000 1474.800000 ;
+ RECT 645.255000 1474.320000 646.520000 1474.800000 ;
+ RECT 641.590000 1468.880000 642.590000 1469.360000 ;
+ RECT 645.255000 1468.880000 646.520000 1469.360000 ;
+ RECT 641.590000 1463.440000 642.590000 1463.920000 ;
+ RECT 645.255000 1463.440000 646.520000 1463.920000 ;
+ RECT 641.590000 1458.000000 642.590000 1458.480000 ;
+ RECT 645.255000 1458.000000 646.520000 1458.480000 ;
+ RECT 641.590000 1452.560000 642.590000 1453.040000 ;
+ RECT 645.255000 1452.560000 646.520000 1453.040000 ;
+ RECT 825.420000 1436.240000 826.520000 1436.720000 ;
+ RECT 825.420000 1441.680000 826.520000 1442.160000 ;
+ RECT 838.230000 1436.240000 839.230000 1436.720000 ;
+ RECT 838.230000 1441.680000 839.230000 1442.160000 ;
+ RECT 838.230000 1425.360000 839.230000 1425.840000 ;
+ RECT 838.230000 1430.800000 839.230000 1431.280000 ;
+ RECT 825.420000 1430.800000 826.520000 1431.280000 ;
+ RECT 825.420000 1425.360000 826.520000 1425.840000 ;
+ RECT 825.420000 1414.480000 826.520000 1414.960000 ;
+ RECT 825.420000 1419.920000 826.520000 1420.400000 ;
+ RECT 838.230000 1414.480000 839.230000 1414.960000 ;
+ RECT 838.230000 1419.920000 839.230000 1420.400000 ;
+ RECT 838.230000 1403.600000 839.230000 1404.080000 ;
+ RECT 838.230000 1398.160000 839.230000 1398.640000 ;
+ RECT 838.230000 1409.040000 839.230000 1409.520000 ;
+ RECT 825.420000 1409.040000 826.520000 1409.520000 ;
+ RECT 825.420000 1403.600000 826.520000 1404.080000 ;
+ RECT 825.420000 1398.160000 826.520000 1398.640000 ;
+ RECT 780.420000 1425.360000 781.520000 1425.840000 ;
+ RECT 780.420000 1430.800000 781.520000 1431.280000 ;
+ RECT 780.420000 1436.240000 781.520000 1436.720000 ;
+ RECT 780.420000 1441.680000 781.520000 1442.160000 ;
+ RECT 780.420000 1398.160000 781.520000 1398.640000 ;
+ RECT 780.420000 1403.600000 781.520000 1404.080000 ;
+ RECT 780.420000 1409.040000 781.520000 1409.520000 ;
+ RECT 780.420000 1414.480000 781.520000 1414.960000 ;
+ RECT 780.420000 1419.920000 781.520000 1420.400000 ;
+ RECT 825.420000 1387.280000 826.520000 1387.760000 ;
+ RECT 825.420000 1392.720000 826.520000 1393.200000 ;
+ RECT 838.230000 1387.280000 839.230000 1387.760000 ;
+ RECT 838.230000 1392.720000 839.230000 1393.200000 ;
+ RECT 825.420000 1376.400000 826.520000 1376.880000 ;
+ RECT 825.420000 1381.840000 826.520000 1382.320000 ;
+ RECT 838.230000 1376.400000 839.230000 1376.880000 ;
+ RECT 838.230000 1381.840000 839.230000 1382.320000 ;
+ RECT 838.230000 1365.520000 839.230000 1366.000000 ;
+ RECT 838.230000 1360.080000 839.230000 1360.560000 ;
+ RECT 838.230000 1370.960000 839.230000 1371.440000 ;
+ RECT 825.420000 1370.960000 826.520000 1371.440000 ;
+ RECT 825.420000 1365.520000 826.520000 1366.000000 ;
+ RECT 825.420000 1360.080000 826.520000 1360.560000 ;
+ RECT 825.420000 1354.640000 826.520000 1355.120000 ;
+ RECT 838.230000 1354.640000 839.230000 1355.120000 ;
+ RECT 780.420000 1376.400000 781.520000 1376.880000 ;
+ RECT 780.420000 1381.840000 781.520000 1382.320000 ;
+ RECT 780.420000 1387.280000 781.520000 1387.760000 ;
+ RECT 780.420000 1392.720000 781.520000 1393.200000 ;
+ RECT 780.420000 1354.640000 781.520000 1355.120000 ;
+ RECT 780.420000 1360.080000 781.520000 1360.560000 ;
+ RECT 780.420000 1365.520000 781.520000 1366.000000 ;
+ RECT 780.420000 1370.960000 781.520000 1371.440000 ;
+ RECT 735.420000 1425.360000 736.520000 1425.840000 ;
+ RECT 735.420000 1430.800000 736.520000 1431.280000 ;
+ RECT 735.420000 1436.240000 736.520000 1436.720000 ;
+ RECT 735.420000 1441.680000 736.520000 1442.160000 ;
+ RECT 690.420000 1425.360000 691.520000 1425.840000 ;
+ RECT 690.420000 1430.800000 691.520000 1431.280000 ;
+ RECT 690.420000 1436.240000 691.520000 1436.720000 ;
+ RECT 690.420000 1441.680000 691.520000 1442.160000 ;
+ RECT 735.420000 1398.160000 736.520000 1398.640000 ;
+ RECT 735.420000 1403.600000 736.520000 1404.080000 ;
+ RECT 735.420000 1409.040000 736.520000 1409.520000 ;
+ RECT 735.420000 1414.480000 736.520000 1414.960000 ;
+ RECT 735.420000 1419.920000 736.520000 1420.400000 ;
+ RECT 690.420000 1398.160000 691.520000 1398.640000 ;
+ RECT 690.420000 1403.600000 691.520000 1404.080000 ;
+ RECT 690.420000 1409.040000 691.520000 1409.520000 ;
+ RECT 690.420000 1414.480000 691.520000 1414.960000 ;
+ RECT 690.420000 1419.920000 691.520000 1420.400000 ;
+ RECT 641.590000 1441.680000 642.590000 1442.160000 ;
+ RECT 645.255000 1441.680000 646.520000 1442.160000 ;
+ RECT 641.590000 1436.240000 642.590000 1436.720000 ;
+ RECT 645.255000 1436.240000 646.520000 1436.720000 ;
+ RECT 641.590000 1430.800000 642.590000 1431.280000 ;
+ RECT 645.255000 1430.800000 646.520000 1431.280000 ;
+ RECT 641.590000 1425.360000 642.590000 1425.840000 ;
+ RECT 645.255000 1425.360000 646.520000 1425.840000 ;
+ RECT 641.590000 1419.920000 642.590000 1420.400000 ;
+ RECT 645.255000 1419.920000 646.520000 1420.400000 ;
+ RECT 641.590000 1414.480000 642.590000 1414.960000 ;
+ RECT 645.255000 1414.480000 646.520000 1414.960000 ;
+ RECT 641.590000 1403.600000 642.590000 1404.080000 ;
+ RECT 645.255000 1403.600000 646.520000 1404.080000 ;
+ RECT 641.590000 1409.040000 642.590000 1409.520000 ;
+ RECT 645.255000 1409.040000 646.520000 1409.520000 ;
+ RECT 641.590000 1398.160000 642.590000 1398.640000 ;
+ RECT 645.255000 1398.160000 646.520000 1398.640000 ;
+ RECT 735.420000 1376.400000 736.520000 1376.880000 ;
+ RECT 735.420000 1381.840000 736.520000 1382.320000 ;
+ RECT 735.420000 1387.280000 736.520000 1387.760000 ;
+ RECT 735.420000 1392.720000 736.520000 1393.200000 ;
+ RECT 690.420000 1376.400000 691.520000 1376.880000 ;
+ RECT 690.420000 1381.840000 691.520000 1382.320000 ;
+ RECT 690.420000 1387.280000 691.520000 1387.760000 ;
+ RECT 690.420000 1392.720000 691.520000 1393.200000 ;
+ RECT 735.420000 1354.640000 736.520000 1355.120000 ;
+ RECT 735.420000 1360.080000 736.520000 1360.560000 ;
+ RECT 735.420000 1365.520000 736.520000 1366.000000 ;
+ RECT 735.420000 1370.960000 736.520000 1371.440000 ;
+ RECT 690.420000 1354.640000 691.520000 1355.120000 ;
+ RECT 690.420000 1360.080000 691.520000 1360.560000 ;
+ RECT 690.420000 1365.520000 691.520000 1366.000000 ;
+ RECT 690.420000 1370.960000 691.520000 1371.440000 ;
+ RECT 641.590000 1392.720000 642.590000 1393.200000 ;
+ RECT 645.255000 1392.720000 646.520000 1393.200000 ;
+ RECT 641.590000 1387.280000 642.590000 1387.760000 ;
+ RECT 645.255000 1387.280000 646.520000 1387.760000 ;
+ RECT 641.590000 1381.840000 642.590000 1382.320000 ;
+ RECT 645.255000 1381.840000 646.520000 1382.320000 ;
+ RECT 641.590000 1376.400000 642.590000 1376.880000 ;
+ RECT 645.255000 1376.400000 646.520000 1376.880000 ;
+ RECT 641.590000 1370.960000 642.590000 1371.440000 ;
+ RECT 645.255000 1370.960000 646.520000 1371.440000 ;
+ RECT 641.590000 1360.080000 642.590000 1360.560000 ;
+ RECT 645.255000 1360.080000 646.520000 1360.560000 ;
+ RECT 641.590000 1365.520000 642.590000 1366.000000 ;
+ RECT 645.255000 1365.520000 646.520000 1366.000000 ;
+ RECT 641.590000 1354.640000 642.590000 1355.120000 ;
+ RECT 645.255000 1354.640000 646.520000 1355.120000 ;
+ RECT 780.420000 1447.120000 781.520000 1447.600000 ;
+ RECT 825.420000 1447.120000 826.520000 1447.600000 ;
+ RECT 838.230000 1447.120000 839.230000 1447.600000 ;
+ RECT 690.420000 1447.120000 691.520000 1447.600000 ;
+ RECT 735.420000 1447.120000 736.520000 1447.600000 ;
+ RECT 641.590000 1447.120000 642.590000 1447.600000 ;
+ RECT 645.255000 1447.120000 646.520000 1447.600000 ;
+ RECT 640.360000 1543.880000 840.460000 1544.880000 ;
+ RECT 640.360000 1348.310000 840.460000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 1347.060000 642.590000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 1546.320000 642.590000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 1347.060000 839.230000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 1546.320000 839.230000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1348.310000 641.360000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1348.310000 840.460000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1543.880000 641.360000 1544.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1543.880000 840.460000 1544.880000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 1339.340000 646.520000 1339.820000 ;
+ RECT 645.255000 1328.460000 646.520000 1328.940000 ;
+ RECT 645.255000 1333.900000 646.520000 1334.380000 ;
+ RECT 645.255000 1323.020000 646.520000 1323.500000 ;
+ RECT 645.255000 1317.580000 646.520000 1318.060000 ;
+ RECT 645.255000 1312.140000 646.520000 1312.620000 ;
+ RECT 645.255000 1306.700000 646.520000 1307.180000 ;
+ RECT 645.255000 1301.260000 646.520000 1301.740000 ;
+ RECT 645.255000 1295.820000 646.520000 1296.300000 ;
+ RECT 645.255000 1284.940000 646.520000 1285.420000 ;
+ RECT 645.255000 1290.380000 646.520000 1290.860000 ;
+ RECT 645.255000 1279.500000 646.520000 1279.980000 ;
+ RECT 645.255000 1274.060000 646.520000 1274.540000 ;
+ RECT 645.255000 1268.620000 646.520000 1269.100000 ;
+ RECT 645.255000 1263.180000 646.520000 1263.660000 ;
+ RECT 645.255000 1257.740000 646.520000 1258.220000 ;
+ RECT 645.255000 1252.300000 646.520000 1252.780000 ;
+ RECT 645.255000 1241.420000 646.520000 1241.900000 ;
+ RECT 645.255000 1235.980000 646.520000 1236.460000 ;
+ RECT 645.255000 1230.540000 646.520000 1231.020000 ;
+ RECT 645.255000 1225.100000 646.520000 1225.580000 ;
+ RECT 645.255000 1219.660000 646.520000 1220.140000 ;
+ RECT 645.255000 1214.220000 646.520000 1214.700000 ;
+ RECT 645.255000 1203.340000 646.520000 1203.820000 ;
+ RECT 645.255000 1208.780000 646.520000 1209.260000 ;
+ RECT 645.255000 1197.900000 646.520000 1198.380000 ;
+ RECT 645.255000 1192.460000 646.520000 1192.940000 ;
+ RECT 645.255000 1187.020000 646.520000 1187.500000 ;
+ RECT 645.255000 1181.580000 646.520000 1182.060000 ;
+ RECT 645.255000 1176.140000 646.520000 1176.620000 ;
+ RECT 645.255000 1170.700000 646.520000 1171.180000 ;
+ RECT 645.255000 1159.820000 646.520000 1160.300000 ;
+ RECT 645.255000 1165.260000 646.520000 1165.740000 ;
+ RECT 645.255000 1154.380000 646.520000 1154.860000 ;
+ RECT 645.255000 1246.860000 646.520000 1247.340000 ;
+ RECT 825.420000 1148.050000 826.520000 1344.620000 ;
+ RECT 780.420000 1148.050000 781.520000 1344.620000 ;
+ RECT 838.230000 1146.800000 839.230000 1347.060000 ;
+ RECT 735.420000 1148.050000 736.520000 1344.620000 ;
+ RECT 690.420000 1148.050000 691.520000 1344.620000 ;
+ RECT 645.420000 1148.050000 646.520000 1344.620000 ;
+ RECT 641.590000 1146.800000 642.590000 1347.060000 ;
+ LAYER met3 ;
+ RECT 825.420000 1339.340000 826.520000 1339.820000 ;
+ RECT 838.230000 1339.340000 839.230000 1339.820000 ;
+ RECT 838.230000 1328.460000 839.230000 1328.940000 ;
+ RECT 838.230000 1323.020000 839.230000 1323.500000 ;
+ RECT 838.230000 1333.900000 839.230000 1334.380000 ;
+ RECT 825.420000 1333.900000 826.520000 1334.380000 ;
+ RECT 825.420000 1328.460000 826.520000 1328.940000 ;
+ RECT 825.420000 1323.020000 826.520000 1323.500000 ;
+ RECT 825.420000 1312.140000 826.520000 1312.620000 ;
+ RECT 825.420000 1317.580000 826.520000 1318.060000 ;
+ RECT 838.230000 1312.140000 839.230000 1312.620000 ;
+ RECT 838.230000 1317.580000 839.230000 1318.060000 ;
+ RECT 825.420000 1301.260000 826.520000 1301.740000 ;
+ RECT 825.420000 1306.700000 826.520000 1307.180000 ;
+ RECT 838.230000 1301.260000 839.230000 1301.740000 ;
+ RECT 838.230000 1306.700000 839.230000 1307.180000 ;
+ RECT 780.420000 1323.020000 781.520000 1323.500000 ;
+ RECT 780.420000 1328.460000 781.520000 1328.940000 ;
+ RECT 780.420000 1333.900000 781.520000 1334.380000 ;
+ RECT 780.420000 1339.340000 781.520000 1339.820000 ;
+ RECT 780.420000 1306.700000 781.520000 1307.180000 ;
+ RECT 780.420000 1301.260000 781.520000 1301.740000 ;
+ RECT 780.420000 1312.140000 781.520000 1312.620000 ;
+ RECT 780.420000 1317.580000 781.520000 1318.060000 ;
+ RECT 838.230000 1290.380000 839.230000 1290.860000 ;
+ RECT 838.230000 1284.940000 839.230000 1285.420000 ;
+ RECT 838.230000 1295.820000 839.230000 1296.300000 ;
+ RECT 825.420000 1295.820000 826.520000 1296.300000 ;
+ RECT 825.420000 1290.380000 826.520000 1290.860000 ;
+ RECT 825.420000 1284.940000 826.520000 1285.420000 ;
+ RECT 825.420000 1274.060000 826.520000 1274.540000 ;
+ RECT 825.420000 1279.500000 826.520000 1279.980000 ;
+ RECT 838.230000 1274.060000 839.230000 1274.540000 ;
+ RECT 838.230000 1279.500000 839.230000 1279.980000 ;
+ RECT 838.230000 1263.180000 839.230000 1263.660000 ;
+ RECT 838.230000 1268.620000 839.230000 1269.100000 ;
+ RECT 825.420000 1268.620000 826.520000 1269.100000 ;
+ RECT 825.420000 1263.180000 826.520000 1263.660000 ;
+ RECT 825.420000 1252.300000 826.520000 1252.780000 ;
+ RECT 825.420000 1257.740000 826.520000 1258.220000 ;
+ RECT 838.230000 1252.300000 839.230000 1252.780000 ;
+ RECT 838.230000 1257.740000 839.230000 1258.220000 ;
+ RECT 780.420000 1274.060000 781.520000 1274.540000 ;
+ RECT 780.420000 1279.500000 781.520000 1279.980000 ;
+ RECT 780.420000 1284.940000 781.520000 1285.420000 ;
+ RECT 780.420000 1290.380000 781.520000 1290.860000 ;
+ RECT 780.420000 1295.820000 781.520000 1296.300000 ;
+ RECT 780.420000 1252.300000 781.520000 1252.780000 ;
+ RECT 780.420000 1257.740000 781.520000 1258.220000 ;
+ RECT 780.420000 1263.180000 781.520000 1263.660000 ;
+ RECT 780.420000 1268.620000 781.520000 1269.100000 ;
+ RECT 735.420000 1328.460000 736.520000 1328.940000 ;
+ RECT 735.420000 1323.020000 736.520000 1323.500000 ;
+ RECT 735.420000 1333.900000 736.520000 1334.380000 ;
+ RECT 735.420000 1339.340000 736.520000 1339.820000 ;
+ RECT 690.420000 1323.020000 691.520000 1323.500000 ;
+ RECT 690.420000 1328.460000 691.520000 1328.940000 ;
+ RECT 690.420000 1333.900000 691.520000 1334.380000 ;
+ RECT 690.420000 1339.340000 691.520000 1339.820000 ;
+ RECT 735.420000 1301.260000 736.520000 1301.740000 ;
+ RECT 735.420000 1306.700000 736.520000 1307.180000 ;
+ RECT 735.420000 1312.140000 736.520000 1312.620000 ;
+ RECT 735.420000 1317.580000 736.520000 1318.060000 ;
+ RECT 690.420000 1301.260000 691.520000 1301.740000 ;
+ RECT 690.420000 1306.700000 691.520000 1307.180000 ;
+ RECT 690.420000 1312.140000 691.520000 1312.620000 ;
+ RECT 690.420000 1317.580000 691.520000 1318.060000 ;
+ RECT 641.590000 1339.340000 642.590000 1339.820000 ;
+ RECT 645.255000 1339.340000 646.520000 1339.820000 ;
+ RECT 641.590000 1328.460000 642.590000 1328.940000 ;
+ RECT 645.255000 1328.460000 646.520000 1328.940000 ;
+ RECT 641.590000 1333.900000 642.590000 1334.380000 ;
+ RECT 645.255000 1333.900000 646.520000 1334.380000 ;
+ RECT 641.590000 1323.020000 642.590000 1323.500000 ;
+ RECT 645.255000 1323.020000 646.520000 1323.500000 ;
+ RECT 641.590000 1317.580000 642.590000 1318.060000 ;
+ RECT 645.255000 1317.580000 646.520000 1318.060000 ;
+ RECT 641.590000 1312.140000 642.590000 1312.620000 ;
+ RECT 645.255000 1312.140000 646.520000 1312.620000 ;
+ RECT 641.590000 1306.700000 642.590000 1307.180000 ;
+ RECT 645.255000 1306.700000 646.520000 1307.180000 ;
+ RECT 641.590000 1301.260000 642.590000 1301.740000 ;
+ RECT 645.255000 1301.260000 646.520000 1301.740000 ;
+ RECT 735.420000 1274.060000 736.520000 1274.540000 ;
+ RECT 735.420000 1279.500000 736.520000 1279.980000 ;
+ RECT 735.420000 1284.940000 736.520000 1285.420000 ;
+ RECT 735.420000 1290.380000 736.520000 1290.860000 ;
+ RECT 735.420000 1295.820000 736.520000 1296.300000 ;
+ RECT 690.420000 1274.060000 691.520000 1274.540000 ;
+ RECT 690.420000 1279.500000 691.520000 1279.980000 ;
+ RECT 690.420000 1284.940000 691.520000 1285.420000 ;
+ RECT 690.420000 1290.380000 691.520000 1290.860000 ;
+ RECT 690.420000 1295.820000 691.520000 1296.300000 ;
+ RECT 735.420000 1252.300000 736.520000 1252.780000 ;
+ RECT 735.420000 1257.740000 736.520000 1258.220000 ;
+ RECT 735.420000 1263.180000 736.520000 1263.660000 ;
+ RECT 735.420000 1268.620000 736.520000 1269.100000 ;
+ RECT 690.420000 1252.300000 691.520000 1252.780000 ;
+ RECT 690.420000 1257.740000 691.520000 1258.220000 ;
+ RECT 690.420000 1263.180000 691.520000 1263.660000 ;
+ RECT 690.420000 1268.620000 691.520000 1269.100000 ;
+ RECT 641.590000 1295.820000 642.590000 1296.300000 ;
+ RECT 645.255000 1295.820000 646.520000 1296.300000 ;
+ RECT 641.590000 1284.940000 642.590000 1285.420000 ;
+ RECT 645.255000 1284.940000 646.520000 1285.420000 ;
+ RECT 641.590000 1290.380000 642.590000 1290.860000 ;
+ RECT 645.255000 1290.380000 646.520000 1290.860000 ;
+ RECT 641.590000 1279.500000 642.590000 1279.980000 ;
+ RECT 645.255000 1279.500000 646.520000 1279.980000 ;
+ RECT 641.590000 1274.060000 642.590000 1274.540000 ;
+ RECT 645.255000 1274.060000 646.520000 1274.540000 ;
+ RECT 641.590000 1268.620000 642.590000 1269.100000 ;
+ RECT 645.255000 1268.620000 646.520000 1269.100000 ;
+ RECT 641.590000 1263.180000 642.590000 1263.660000 ;
+ RECT 645.255000 1263.180000 646.520000 1263.660000 ;
+ RECT 641.590000 1257.740000 642.590000 1258.220000 ;
+ RECT 645.255000 1257.740000 646.520000 1258.220000 ;
+ RECT 641.590000 1252.300000 642.590000 1252.780000 ;
+ RECT 645.255000 1252.300000 646.520000 1252.780000 ;
+ RECT 825.420000 1235.980000 826.520000 1236.460000 ;
+ RECT 825.420000 1241.420000 826.520000 1241.900000 ;
+ RECT 838.230000 1235.980000 839.230000 1236.460000 ;
+ RECT 838.230000 1241.420000 839.230000 1241.900000 ;
+ RECT 838.230000 1225.100000 839.230000 1225.580000 ;
+ RECT 838.230000 1230.540000 839.230000 1231.020000 ;
+ RECT 825.420000 1230.540000 826.520000 1231.020000 ;
+ RECT 825.420000 1225.100000 826.520000 1225.580000 ;
+ RECT 825.420000 1214.220000 826.520000 1214.700000 ;
+ RECT 825.420000 1219.660000 826.520000 1220.140000 ;
+ RECT 838.230000 1214.220000 839.230000 1214.700000 ;
+ RECT 838.230000 1219.660000 839.230000 1220.140000 ;
+ RECT 838.230000 1203.340000 839.230000 1203.820000 ;
+ RECT 838.230000 1197.900000 839.230000 1198.380000 ;
+ RECT 838.230000 1208.780000 839.230000 1209.260000 ;
+ RECT 825.420000 1208.780000 826.520000 1209.260000 ;
+ RECT 825.420000 1203.340000 826.520000 1203.820000 ;
+ RECT 825.420000 1197.900000 826.520000 1198.380000 ;
+ RECT 780.420000 1225.100000 781.520000 1225.580000 ;
+ RECT 780.420000 1230.540000 781.520000 1231.020000 ;
+ RECT 780.420000 1235.980000 781.520000 1236.460000 ;
+ RECT 780.420000 1241.420000 781.520000 1241.900000 ;
+ RECT 780.420000 1197.900000 781.520000 1198.380000 ;
+ RECT 780.420000 1203.340000 781.520000 1203.820000 ;
+ RECT 780.420000 1208.780000 781.520000 1209.260000 ;
+ RECT 780.420000 1214.220000 781.520000 1214.700000 ;
+ RECT 780.420000 1219.660000 781.520000 1220.140000 ;
+ RECT 825.420000 1187.020000 826.520000 1187.500000 ;
+ RECT 825.420000 1192.460000 826.520000 1192.940000 ;
+ RECT 838.230000 1187.020000 839.230000 1187.500000 ;
+ RECT 838.230000 1192.460000 839.230000 1192.940000 ;
+ RECT 825.420000 1176.140000 826.520000 1176.620000 ;
+ RECT 825.420000 1181.580000 826.520000 1182.060000 ;
+ RECT 838.230000 1176.140000 839.230000 1176.620000 ;
+ RECT 838.230000 1181.580000 839.230000 1182.060000 ;
+ RECT 838.230000 1165.260000 839.230000 1165.740000 ;
+ RECT 838.230000 1159.820000 839.230000 1160.300000 ;
+ RECT 838.230000 1170.700000 839.230000 1171.180000 ;
+ RECT 825.420000 1170.700000 826.520000 1171.180000 ;
+ RECT 825.420000 1165.260000 826.520000 1165.740000 ;
+ RECT 825.420000 1159.820000 826.520000 1160.300000 ;
+ RECT 825.420000 1154.380000 826.520000 1154.860000 ;
+ RECT 838.230000 1154.380000 839.230000 1154.860000 ;
+ RECT 780.420000 1176.140000 781.520000 1176.620000 ;
+ RECT 780.420000 1181.580000 781.520000 1182.060000 ;
+ RECT 780.420000 1187.020000 781.520000 1187.500000 ;
+ RECT 780.420000 1192.460000 781.520000 1192.940000 ;
+ RECT 780.420000 1154.380000 781.520000 1154.860000 ;
+ RECT 780.420000 1159.820000 781.520000 1160.300000 ;
+ RECT 780.420000 1165.260000 781.520000 1165.740000 ;
+ RECT 780.420000 1170.700000 781.520000 1171.180000 ;
+ RECT 735.420000 1225.100000 736.520000 1225.580000 ;
+ RECT 735.420000 1230.540000 736.520000 1231.020000 ;
+ RECT 735.420000 1235.980000 736.520000 1236.460000 ;
+ RECT 735.420000 1241.420000 736.520000 1241.900000 ;
+ RECT 690.420000 1225.100000 691.520000 1225.580000 ;
+ RECT 690.420000 1230.540000 691.520000 1231.020000 ;
+ RECT 690.420000 1235.980000 691.520000 1236.460000 ;
+ RECT 690.420000 1241.420000 691.520000 1241.900000 ;
+ RECT 735.420000 1197.900000 736.520000 1198.380000 ;
+ RECT 735.420000 1203.340000 736.520000 1203.820000 ;
+ RECT 735.420000 1208.780000 736.520000 1209.260000 ;
+ RECT 735.420000 1214.220000 736.520000 1214.700000 ;
+ RECT 735.420000 1219.660000 736.520000 1220.140000 ;
+ RECT 690.420000 1197.900000 691.520000 1198.380000 ;
+ RECT 690.420000 1203.340000 691.520000 1203.820000 ;
+ RECT 690.420000 1208.780000 691.520000 1209.260000 ;
+ RECT 690.420000 1214.220000 691.520000 1214.700000 ;
+ RECT 690.420000 1219.660000 691.520000 1220.140000 ;
+ RECT 641.590000 1241.420000 642.590000 1241.900000 ;
+ RECT 645.255000 1241.420000 646.520000 1241.900000 ;
+ RECT 641.590000 1235.980000 642.590000 1236.460000 ;
+ RECT 645.255000 1235.980000 646.520000 1236.460000 ;
+ RECT 641.590000 1230.540000 642.590000 1231.020000 ;
+ RECT 645.255000 1230.540000 646.520000 1231.020000 ;
+ RECT 641.590000 1225.100000 642.590000 1225.580000 ;
+ RECT 645.255000 1225.100000 646.520000 1225.580000 ;
+ RECT 641.590000 1219.660000 642.590000 1220.140000 ;
+ RECT 645.255000 1219.660000 646.520000 1220.140000 ;
+ RECT 641.590000 1214.220000 642.590000 1214.700000 ;
+ RECT 645.255000 1214.220000 646.520000 1214.700000 ;
+ RECT 641.590000 1203.340000 642.590000 1203.820000 ;
+ RECT 645.255000 1203.340000 646.520000 1203.820000 ;
+ RECT 641.590000 1208.780000 642.590000 1209.260000 ;
+ RECT 645.255000 1208.780000 646.520000 1209.260000 ;
+ RECT 641.590000 1197.900000 642.590000 1198.380000 ;
+ RECT 645.255000 1197.900000 646.520000 1198.380000 ;
+ RECT 735.420000 1176.140000 736.520000 1176.620000 ;
+ RECT 735.420000 1181.580000 736.520000 1182.060000 ;
+ RECT 735.420000 1187.020000 736.520000 1187.500000 ;
+ RECT 735.420000 1192.460000 736.520000 1192.940000 ;
+ RECT 690.420000 1176.140000 691.520000 1176.620000 ;
+ RECT 690.420000 1181.580000 691.520000 1182.060000 ;
+ RECT 690.420000 1187.020000 691.520000 1187.500000 ;
+ RECT 690.420000 1192.460000 691.520000 1192.940000 ;
+ RECT 735.420000 1154.380000 736.520000 1154.860000 ;
+ RECT 735.420000 1159.820000 736.520000 1160.300000 ;
+ RECT 735.420000 1165.260000 736.520000 1165.740000 ;
+ RECT 735.420000 1170.700000 736.520000 1171.180000 ;
+ RECT 690.420000 1154.380000 691.520000 1154.860000 ;
+ RECT 690.420000 1159.820000 691.520000 1160.300000 ;
+ RECT 690.420000 1165.260000 691.520000 1165.740000 ;
+ RECT 690.420000 1170.700000 691.520000 1171.180000 ;
+ RECT 641.590000 1192.460000 642.590000 1192.940000 ;
+ RECT 645.255000 1192.460000 646.520000 1192.940000 ;
+ RECT 641.590000 1187.020000 642.590000 1187.500000 ;
+ RECT 645.255000 1187.020000 646.520000 1187.500000 ;
+ RECT 641.590000 1181.580000 642.590000 1182.060000 ;
+ RECT 645.255000 1181.580000 646.520000 1182.060000 ;
+ RECT 641.590000 1176.140000 642.590000 1176.620000 ;
+ RECT 645.255000 1176.140000 646.520000 1176.620000 ;
+ RECT 641.590000 1170.700000 642.590000 1171.180000 ;
+ RECT 645.255000 1170.700000 646.520000 1171.180000 ;
+ RECT 641.590000 1159.820000 642.590000 1160.300000 ;
+ RECT 645.255000 1159.820000 646.520000 1160.300000 ;
+ RECT 641.590000 1165.260000 642.590000 1165.740000 ;
+ RECT 645.255000 1165.260000 646.520000 1165.740000 ;
+ RECT 641.590000 1154.380000 642.590000 1154.860000 ;
+ RECT 645.255000 1154.380000 646.520000 1154.860000 ;
+ RECT 780.420000 1246.860000 781.520000 1247.340000 ;
+ RECT 825.420000 1246.860000 826.520000 1247.340000 ;
+ RECT 838.230000 1246.860000 839.230000 1247.340000 ;
+ RECT 690.420000 1246.860000 691.520000 1247.340000 ;
+ RECT 735.420000 1246.860000 736.520000 1247.340000 ;
+ RECT 641.590000 1246.860000 642.590000 1247.340000 ;
+ RECT 645.255000 1246.860000 646.520000 1247.340000 ;
+ RECT 640.360000 1343.620000 840.460000 1344.620000 ;
+ RECT 640.360000 1148.050000 840.460000 1149.050000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 1146.800000 642.590000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 1346.060000 642.590000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 1146.800000 839.230000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 1346.060000 839.230000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1148.050000 641.360000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1148.050000 840.460000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1343.620000 641.360000 1344.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1343.620000 840.460000 1344.620000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 1139.080000 646.520000 1139.560000 ;
+ RECT 645.255000 1128.200000 646.520000 1128.680000 ;
+ RECT 645.255000 1133.640000 646.520000 1134.120000 ;
+ RECT 645.255000 1122.760000 646.520000 1123.240000 ;
+ RECT 645.255000 1117.320000 646.520000 1117.800000 ;
+ RECT 645.255000 1111.880000 646.520000 1112.360000 ;
+ RECT 645.255000 1106.440000 646.520000 1106.920000 ;
+ RECT 645.255000 1101.000000 646.520000 1101.480000 ;
+ RECT 645.255000 1095.560000 646.520000 1096.040000 ;
+ RECT 645.255000 1084.680000 646.520000 1085.160000 ;
+ RECT 645.255000 1090.120000 646.520000 1090.600000 ;
+ RECT 645.255000 1079.240000 646.520000 1079.720000 ;
+ RECT 645.255000 1073.800000 646.520000 1074.280000 ;
+ RECT 645.255000 1068.360000 646.520000 1068.840000 ;
+ RECT 645.255000 1062.920000 646.520000 1063.400000 ;
+ RECT 645.255000 1057.480000 646.520000 1057.960000 ;
+ RECT 645.255000 1052.040000 646.520000 1052.520000 ;
+ RECT 645.255000 1041.160000 646.520000 1041.640000 ;
+ RECT 645.255000 1035.720000 646.520000 1036.200000 ;
+ RECT 645.255000 1030.280000 646.520000 1030.760000 ;
+ RECT 645.255000 1024.840000 646.520000 1025.320000 ;
+ RECT 645.255000 1019.400000 646.520000 1019.880000 ;
+ RECT 645.255000 1013.960000 646.520000 1014.440000 ;
+ RECT 645.255000 1003.080000 646.520000 1003.560000 ;
+ RECT 645.255000 1008.520000 646.520000 1009.000000 ;
+ RECT 645.255000 997.640000 646.520000 998.120000 ;
+ RECT 645.255000 992.200000 646.520000 992.680000 ;
+ RECT 645.255000 986.760000 646.520000 987.240000 ;
+ RECT 645.255000 981.320000 646.520000 981.800000 ;
+ RECT 645.255000 975.880000 646.520000 976.360000 ;
+ RECT 645.255000 970.440000 646.520000 970.920000 ;
+ RECT 645.255000 959.560000 646.520000 960.040000 ;
+ RECT 645.255000 965.000000 646.520000 965.480000 ;
+ RECT 645.255000 954.120000 646.520000 954.600000 ;
+ RECT 645.255000 1046.600000 646.520000 1047.080000 ;
+ RECT 825.420000 947.790000 826.520000 1144.360000 ;
+ RECT 780.420000 947.790000 781.520000 1144.360000 ;
+ RECT 838.230000 946.540000 839.230000 1146.800000 ;
+ RECT 735.420000 947.790000 736.520000 1144.360000 ;
+ RECT 690.420000 947.790000 691.520000 1144.360000 ;
+ RECT 645.420000 947.790000 646.520000 1144.360000 ;
+ RECT 641.590000 946.540000 642.590000 1146.800000 ;
+ LAYER met3 ;
+ RECT 825.420000 1139.080000 826.520000 1139.560000 ;
+ RECT 838.230000 1139.080000 839.230000 1139.560000 ;
+ RECT 838.230000 1128.200000 839.230000 1128.680000 ;
+ RECT 838.230000 1122.760000 839.230000 1123.240000 ;
+ RECT 838.230000 1133.640000 839.230000 1134.120000 ;
+ RECT 825.420000 1133.640000 826.520000 1134.120000 ;
+ RECT 825.420000 1128.200000 826.520000 1128.680000 ;
+ RECT 825.420000 1122.760000 826.520000 1123.240000 ;
+ RECT 825.420000 1111.880000 826.520000 1112.360000 ;
+ RECT 825.420000 1117.320000 826.520000 1117.800000 ;
+ RECT 838.230000 1111.880000 839.230000 1112.360000 ;
+ RECT 838.230000 1117.320000 839.230000 1117.800000 ;
+ RECT 825.420000 1101.000000 826.520000 1101.480000 ;
+ RECT 825.420000 1106.440000 826.520000 1106.920000 ;
+ RECT 838.230000 1101.000000 839.230000 1101.480000 ;
+ RECT 838.230000 1106.440000 839.230000 1106.920000 ;
+ RECT 780.420000 1122.760000 781.520000 1123.240000 ;
+ RECT 780.420000 1128.200000 781.520000 1128.680000 ;
+ RECT 780.420000 1133.640000 781.520000 1134.120000 ;
+ RECT 780.420000 1139.080000 781.520000 1139.560000 ;
+ RECT 780.420000 1106.440000 781.520000 1106.920000 ;
+ RECT 780.420000 1101.000000 781.520000 1101.480000 ;
+ RECT 780.420000 1111.880000 781.520000 1112.360000 ;
+ RECT 780.420000 1117.320000 781.520000 1117.800000 ;
+ RECT 838.230000 1090.120000 839.230000 1090.600000 ;
+ RECT 838.230000 1084.680000 839.230000 1085.160000 ;
+ RECT 838.230000 1095.560000 839.230000 1096.040000 ;
+ RECT 825.420000 1095.560000 826.520000 1096.040000 ;
+ RECT 825.420000 1090.120000 826.520000 1090.600000 ;
+ RECT 825.420000 1084.680000 826.520000 1085.160000 ;
+ RECT 825.420000 1073.800000 826.520000 1074.280000 ;
+ RECT 825.420000 1079.240000 826.520000 1079.720000 ;
+ RECT 838.230000 1073.800000 839.230000 1074.280000 ;
+ RECT 838.230000 1079.240000 839.230000 1079.720000 ;
+ RECT 838.230000 1062.920000 839.230000 1063.400000 ;
+ RECT 838.230000 1068.360000 839.230000 1068.840000 ;
+ RECT 825.420000 1068.360000 826.520000 1068.840000 ;
+ RECT 825.420000 1062.920000 826.520000 1063.400000 ;
+ RECT 825.420000 1052.040000 826.520000 1052.520000 ;
+ RECT 825.420000 1057.480000 826.520000 1057.960000 ;
+ RECT 838.230000 1052.040000 839.230000 1052.520000 ;
+ RECT 838.230000 1057.480000 839.230000 1057.960000 ;
+ RECT 780.420000 1073.800000 781.520000 1074.280000 ;
+ RECT 780.420000 1079.240000 781.520000 1079.720000 ;
+ RECT 780.420000 1084.680000 781.520000 1085.160000 ;
+ RECT 780.420000 1090.120000 781.520000 1090.600000 ;
+ RECT 780.420000 1095.560000 781.520000 1096.040000 ;
+ RECT 780.420000 1052.040000 781.520000 1052.520000 ;
+ RECT 780.420000 1057.480000 781.520000 1057.960000 ;
+ RECT 780.420000 1062.920000 781.520000 1063.400000 ;
+ RECT 780.420000 1068.360000 781.520000 1068.840000 ;
+ RECT 735.420000 1128.200000 736.520000 1128.680000 ;
+ RECT 735.420000 1122.760000 736.520000 1123.240000 ;
+ RECT 735.420000 1133.640000 736.520000 1134.120000 ;
+ RECT 735.420000 1139.080000 736.520000 1139.560000 ;
+ RECT 690.420000 1122.760000 691.520000 1123.240000 ;
+ RECT 690.420000 1128.200000 691.520000 1128.680000 ;
+ RECT 690.420000 1133.640000 691.520000 1134.120000 ;
+ RECT 690.420000 1139.080000 691.520000 1139.560000 ;
+ RECT 735.420000 1101.000000 736.520000 1101.480000 ;
+ RECT 735.420000 1106.440000 736.520000 1106.920000 ;
+ RECT 735.420000 1111.880000 736.520000 1112.360000 ;
+ RECT 735.420000 1117.320000 736.520000 1117.800000 ;
+ RECT 690.420000 1101.000000 691.520000 1101.480000 ;
+ RECT 690.420000 1106.440000 691.520000 1106.920000 ;
+ RECT 690.420000 1111.880000 691.520000 1112.360000 ;
+ RECT 690.420000 1117.320000 691.520000 1117.800000 ;
+ RECT 641.590000 1139.080000 642.590000 1139.560000 ;
+ RECT 645.255000 1139.080000 646.520000 1139.560000 ;
+ RECT 641.590000 1128.200000 642.590000 1128.680000 ;
+ RECT 645.255000 1128.200000 646.520000 1128.680000 ;
+ RECT 641.590000 1133.640000 642.590000 1134.120000 ;
+ RECT 645.255000 1133.640000 646.520000 1134.120000 ;
+ RECT 641.590000 1122.760000 642.590000 1123.240000 ;
+ RECT 645.255000 1122.760000 646.520000 1123.240000 ;
+ RECT 641.590000 1117.320000 642.590000 1117.800000 ;
+ RECT 645.255000 1117.320000 646.520000 1117.800000 ;
+ RECT 641.590000 1111.880000 642.590000 1112.360000 ;
+ RECT 645.255000 1111.880000 646.520000 1112.360000 ;
+ RECT 641.590000 1106.440000 642.590000 1106.920000 ;
+ RECT 645.255000 1106.440000 646.520000 1106.920000 ;
+ RECT 641.590000 1101.000000 642.590000 1101.480000 ;
+ RECT 645.255000 1101.000000 646.520000 1101.480000 ;
+ RECT 735.420000 1073.800000 736.520000 1074.280000 ;
+ RECT 735.420000 1079.240000 736.520000 1079.720000 ;
+ RECT 735.420000 1084.680000 736.520000 1085.160000 ;
+ RECT 735.420000 1090.120000 736.520000 1090.600000 ;
+ RECT 735.420000 1095.560000 736.520000 1096.040000 ;
+ RECT 690.420000 1073.800000 691.520000 1074.280000 ;
+ RECT 690.420000 1079.240000 691.520000 1079.720000 ;
+ RECT 690.420000 1084.680000 691.520000 1085.160000 ;
+ RECT 690.420000 1090.120000 691.520000 1090.600000 ;
+ RECT 690.420000 1095.560000 691.520000 1096.040000 ;
+ RECT 735.420000 1052.040000 736.520000 1052.520000 ;
+ RECT 735.420000 1057.480000 736.520000 1057.960000 ;
+ RECT 735.420000 1062.920000 736.520000 1063.400000 ;
+ RECT 735.420000 1068.360000 736.520000 1068.840000 ;
+ RECT 690.420000 1052.040000 691.520000 1052.520000 ;
+ RECT 690.420000 1057.480000 691.520000 1057.960000 ;
+ RECT 690.420000 1062.920000 691.520000 1063.400000 ;
+ RECT 690.420000 1068.360000 691.520000 1068.840000 ;
+ RECT 641.590000 1095.560000 642.590000 1096.040000 ;
+ RECT 645.255000 1095.560000 646.520000 1096.040000 ;
+ RECT 641.590000 1084.680000 642.590000 1085.160000 ;
+ RECT 645.255000 1084.680000 646.520000 1085.160000 ;
+ RECT 641.590000 1090.120000 642.590000 1090.600000 ;
+ RECT 645.255000 1090.120000 646.520000 1090.600000 ;
+ RECT 641.590000 1079.240000 642.590000 1079.720000 ;
+ RECT 645.255000 1079.240000 646.520000 1079.720000 ;
+ RECT 641.590000 1073.800000 642.590000 1074.280000 ;
+ RECT 645.255000 1073.800000 646.520000 1074.280000 ;
+ RECT 641.590000 1068.360000 642.590000 1068.840000 ;
+ RECT 645.255000 1068.360000 646.520000 1068.840000 ;
+ RECT 641.590000 1062.920000 642.590000 1063.400000 ;
+ RECT 645.255000 1062.920000 646.520000 1063.400000 ;
+ RECT 641.590000 1057.480000 642.590000 1057.960000 ;
+ RECT 645.255000 1057.480000 646.520000 1057.960000 ;
+ RECT 641.590000 1052.040000 642.590000 1052.520000 ;
+ RECT 645.255000 1052.040000 646.520000 1052.520000 ;
+ RECT 825.420000 1035.720000 826.520000 1036.200000 ;
+ RECT 825.420000 1041.160000 826.520000 1041.640000 ;
+ RECT 838.230000 1035.720000 839.230000 1036.200000 ;
+ RECT 838.230000 1041.160000 839.230000 1041.640000 ;
+ RECT 838.230000 1024.840000 839.230000 1025.320000 ;
+ RECT 838.230000 1030.280000 839.230000 1030.760000 ;
+ RECT 825.420000 1030.280000 826.520000 1030.760000 ;
+ RECT 825.420000 1024.840000 826.520000 1025.320000 ;
+ RECT 825.420000 1013.960000 826.520000 1014.440000 ;
+ RECT 825.420000 1019.400000 826.520000 1019.880000 ;
+ RECT 838.230000 1013.960000 839.230000 1014.440000 ;
+ RECT 838.230000 1019.400000 839.230000 1019.880000 ;
+ RECT 838.230000 1003.080000 839.230000 1003.560000 ;
+ RECT 838.230000 997.640000 839.230000 998.120000 ;
+ RECT 838.230000 1008.520000 839.230000 1009.000000 ;
+ RECT 825.420000 1008.520000 826.520000 1009.000000 ;
+ RECT 825.420000 1003.080000 826.520000 1003.560000 ;
+ RECT 825.420000 997.640000 826.520000 998.120000 ;
+ RECT 780.420000 1024.840000 781.520000 1025.320000 ;
+ RECT 780.420000 1030.280000 781.520000 1030.760000 ;
+ RECT 780.420000 1035.720000 781.520000 1036.200000 ;
+ RECT 780.420000 1041.160000 781.520000 1041.640000 ;
+ RECT 780.420000 997.640000 781.520000 998.120000 ;
+ RECT 780.420000 1003.080000 781.520000 1003.560000 ;
+ RECT 780.420000 1008.520000 781.520000 1009.000000 ;
+ RECT 780.420000 1013.960000 781.520000 1014.440000 ;
+ RECT 780.420000 1019.400000 781.520000 1019.880000 ;
+ RECT 825.420000 986.760000 826.520000 987.240000 ;
+ RECT 825.420000 992.200000 826.520000 992.680000 ;
+ RECT 838.230000 986.760000 839.230000 987.240000 ;
+ RECT 838.230000 992.200000 839.230000 992.680000 ;
+ RECT 825.420000 975.880000 826.520000 976.360000 ;
+ RECT 825.420000 981.320000 826.520000 981.800000 ;
+ RECT 838.230000 975.880000 839.230000 976.360000 ;
+ RECT 838.230000 981.320000 839.230000 981.800000 ;
+ RECT 838.230000 965.000000 839.230000 965.480000 ;
+ RECT 838.230000 959.560000 839.230000 960.040000 ;
+ RECT 838.230000 970.440000 839.230000 970.920000 ;
+ RECT 825.420000 970.440000 826.520000 970.920000 ;
+ RECT 825.420000 965.000000 826.520000 965.480000 ;
+ RECT 825.420000 959.560000 826.520000 960.040000 ;
+ RECT 825.420000 954.120000 826.520000 954.600000 ;
+ RECT 838.230000 954.120000 839.230000 954.600000 ;
+ RECT 780.420000 975.880000 781.520000 976.360000 ;
+ RECT 780.420000 981.320000 781.520000 981.800000 ;
+ RECT 780.420000 986.760000 781.520000 987.240000 ;
+ RECT 780.420000 992.200000 781.520000 992.680000 ;
+ RECT 780.420000 954.120000 781.520000 954.600000 ;
+ RECT 780.420000 959.560000 781.520000 960.040000 ;
+ RECT 780.420000 965.000000 781.520000 965.480000 ;
+ RECT 780.420000 970.440000 781.520000 970.920000 ;
+ RECT 735.420000 1024.840000 736.520000 1025.320000 ;
+ RECT 735.420000 1030.280000 736.520000 1030.760000 ;
+ RECT 735.420000 1035.720000 736.520000 1036.200000 ;
+ RECT 735.420000 1041.160000 736.520000 1041.640000 ;
+ RECT 690.420000 1024.840000 691.520000 1025.320000 ;
+ RECT 690.420000 1030.280000 691.520000 1030.760000 ;
+ RECT 690.420000 1035.720000 691.520000 1036.200000 ;
+ RECT 690.420000 1041.160000 691.520000 1041.640000 ;
+ RECT 735.420000 997.640000 736.520000 998.120000 ;
+ RECT 735.420000 1003.080000 736.520000 1003.560000 ;
+ RECT 735.420000 1008.520000 736.520000 1009.000000 ;
+ RECT 735.420000 1013.960000 736.520000 1014.440000 ;
+ RECT 735.420000 1019.400000 736.520000 1019.880000 ;
+ RECT 690.420000 997.640000 691.520000 998.120000 ;
+ RECT 690.420000 1003.080000 691.520000 1003.560000 ;
+ RECT 690.420000 1008.520000 691.520000 1009.000000 ;
+ RECT 690.420000 1013.960000 691.520000 1014.440000 ;
+ RECT 690.420000 1019.400000 691.520000 1019.880000 ;
+ RECT 641.590000 1041.160000 642.590000 1041.640000 ;
+ RECT 645.255000 1041.160000 646.520000 1041.640000 ;
+ RECT 641.590000 1035.720000 642.590000 1036.200000 ;
+ RECT 645.255000 1035.720000 646.520000 1036.200000 ;
+ RECT 641.590000 1030.280000 642.590000 1030.760000 ;
+ RECT 645.255000 1030.280000 646.520000 1030.760000 ;
+ RECT 641.590000 1024.840000 642.590000 1025.320000 ;
+ RECT 645.255000 1024.840000 646.520000 1025.320000 ;
+ RECT 641.590000 1019.400000 642.590000 1019.880000 ;
+ RECT 645.255000 1019.400000 646.520000 1019.880000 ;
+ RECT 641.590000 1013.960000 642.590000 1014.440000 ;
+ RECT 645.255000 1013.960000 646.520000 1014.440000 ;
+ RECT 641.590000 1003.080000 642.590000 1003.560000 ;
+ RECT 645.255000 1003.080000 646.520000 1003.560000 ;
+ RECT 641.590000 1008.520000 642.590000 1009.000000 ;
+ RECT 645.255000 1008.520000 646.520000 1009.000000 ;
+ RECT 641.590000 997.640000 642.590000 998.120000 ;
+ RECT 645.255000 997.640000 646.520000 998.120000 ;
+ RECT 735.420000 975.880000 736.520000 976.360000 ;
+ RECT 735.420000 981.320000 736.520000 981.800000 ;
+ RECT 735.420000 986.760000 736.520000 987.240000 ;
+ RECT 735.420000 992.200000 736.520000 992.680000 ;
+ RECT 690.420000 975.880000 691.520000 976.360000 ;
+ RECT 690.420000 981.320000 691.520000 981.800000 ;
+ RECT 690.420000 986.760000 691.520000 987.240000 ;
+ RECT 690.420000 992.200000 691.520000 992.680000 ;
+ RECT 735.420000 954.120000 736.520000 954.600000 ;
+ RECT 735.420000 959.560000 736.520000 960.040000 ;
+ RECT 735.420000 965.000000 736.520000 965.480000 ;
+ RECT 735.420000 970.440000 736.520000 970.920000 ;
+ RECT 690.420000 954.120000 691.520000 954.600000 ;
+ RECT 690.420000 959.560000 691.520000 960.040000 ;
+ RECT 690.420000 965.000000 691.520000 965.480000 ;
+ RECT 690.420000 970.440000 691.520000 970.920000 ;
+ RECT 641.590000 992.200000 642.590000 992.680000 ;
+ RECT 645.255000 992.200000 646.520000 992.680000 ;
+ RECT 641.590000 986.760000 642.590000 987.240000 ;
+ RECT 645.255000 986.760000 646.520000 987.240000 ;
+ RECT 641.590000 981.320000 642.590000 981.800000 ;
+ RECT 645.255000 981.320000 646.520000 981.800000 ;
+ RECT 641.590000 975.880000 642.590000 976.360000 ;
+ RECT 645.255000 975.880000 646.520000 976.360000 ;
+ RECT 641.590000 970.440000 642.590000 970.920000 ;
+ RECT 645.255000 970.440000 646.520000 970.920000 ;
+ RECT 641.590000 959.560000 642.590000 960.040000 ;
+ RECT 645.255000 959.560000 646.520000 960.040000 ;
+ RECT 641.590000 965.000000 642.590000 965.480000 ;
+ RECT 645.255000 965.000000 646.520000 965.480000 ;
+ RECT 641.590000 954.120000 642.590000 954.600000 ;
+ RECT 645.255000 954.120000 646.520000 954.600000 ;
+ RECT 780.420000 1046.600000 781.520000 1047.080000 ;
+ RECT 825.420000 1046.600000 826.520000 1047.080000 ;
+ RECT 838.230000 1046.600000 839.230000 1047.080000 ;
+ RECT 690.420000 1046.600000 691.520000 1047.080000 ;
+ RECT 735.420000 1046.600000 736.520000 1047.080000 ;
+ RECT 641.590000 1046.600000 642.590000 1047.080000 ;
+ RECT 645.255000 1046.600000 646.520000 1047.080000 ;
+ RECT 640.360000 1143.360000 840.460000 1144.360000 ;
+ RECT 640.360000 947.790000 840.460000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 946.540000 642.590000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 1145.800000 642.590000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 946.540000 839.230000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 1145.800000 839.230000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 947.790000 641.360000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 947.790000 840.460000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1143.360000 641.360000 1144.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1143.360000 840.460000 1144.360000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 938.820000 646.520000 939.300000 ;
+ RECT 645.255000 927.940000 646.520000 928.420000 ;
+ RECT 645.255000 933.380000 646.520000 933.860000 ;
+ RECT 645.255000 922.500000 646.520000 922.980000 ;
+ RECT 645.255000 917.060000 646.520000 917.540000 ;
+ RECT 645.255000 911.620000 646.520000 912.100000 ;
+ RECT 645.255000 906.180000 646.520000 906.660000 ;
+ RECT 645.255000 900.740000 646.520000 901.220000 ;
+ RECT 645.255000 895.300000 646.520000 895.780000 ;
+ RECT 645.255000 884.420000 646.520000 884.900000 ;
+ RECT 645.255000 889.860000 646.520000 890.340000 ;
+ RECT 645.255000 878.980000 646.520000 879.460000 ;
+ RECT 645.255000 873.540000 646.520000 874.020000 ;
+ RECT 645.255000 868.100000 646.520000 868.580000 ;
+ RECT 645.255000 862.660000 646.520000 863.140000 ;
+ RECT 645.255000 857.220000 646.520000 857.700000 ;
+ RECT 645.255000 851.780000 646.520000 852.260000 ;
+ RECT 645.255000 840.900000 646.520000 841.380000 ;
+ RECT 645.255000 835.460000 646.520000 835.940000 ;
+ RECT 645.255000 830.020000 646.520000 830.500000 ;
+ RECT 645.255000 824.580000 646.520000 825.060000 ;
+ RECT 645.255000 819.140000 646.520000 819.620000 ;
+ RECT 645.255000 813.700000 646.520000 814.180000 ;
+ RECT 645.255000 802.820000 646.520000 803.300000 ;
+ RECT 645.255000 808.260000 646.520000 808.740000 ;
+ RECT 645.255000 797.380000 646.520000 797.860000 ;
+ RECT 645.255000 791.940000 646.520000 792.420000 ;
+ RECT 645.255000 786.500000 646.520000 786.980000 ;
+ RECT 645.255000 781.060000 646.520000 781.540000 ;
+ RECT 645.255000 775.620000 646.520000 776.100000 ;
+ RECT 645.255000 770.180000 646.520000 770.660000 ;
+ RECT 645.255000 759.300000 646.520000 759.780000 ;
+ RECT 645.255000 764.740000 646.520000 765.220000 ;
+ RECT 645.255000 753.860000 646.520000 754.340000 ;
+ RECT 645.255000 846.340000 646.520000 846.820000 ;
+ RECT 825.420000 747.530000 826.520000 944.100000 ;
+ RECT 780.420000 747.530000 781.520000 944.100000 ;
+ RECT 838.230000 746.280000 839.230000 946.540000 ;
+ RECT 735.420000 747.530000 736.520000 944.100000 ;
+ RECT 690.420000 747.530000 691.520000 944.100000 ;
+ RECT 645.420000 747.530000 646.520000 944.100000 ;
+ RECT 641.590000 746.280000 642.590000 946.540000 ;
+ LAYER met3 ;
+ RECT 825.420000 938.820000 826.520000 939.300000 ;
+ RECT 838.230000 938.820000 839.230000 939.300000 ;
+ RECT 838.230000 927.940000 839.230000 928.420000 ;
+ RECT 838.230000 922.500000 839.230000 922.980000 ;
+ RECT 838.230000 933.380000 839.230000 933.860000 ;
+ RECT 825.420000 933.380000 826.520000 933.860000 ;
+ RECT 825.420000 927.940000 826.520000 928.420000 ;
+ RECT 825.420000 922.500000 826.520000 922.980000 ;
+ RECT 825.420000 911.620000 826.520000 912.100000 ;
+ RECT 825.420000 917.060000 826.520000 917.540000 ;
+ RECT 838.230000 911.620000 839.230000 912.100000 ;
+ RECT 838.230000 917.060000 839.230000 917.540000 ;
+ RECT 825.420000 900.740000 826.520000 901.220000 ;
+ RECT 825.420000 906.180000 826.520000 906.660000 ;
+ RECT 838.230000 900.740000 839.230000 901.220000 ;
+ RECT 838.230000 906.180000 839.230000 906.660000 ;
+ RECT 780.420000 922.500000 781.520000 922.980000 ;
+ RECT 780.420000 927.940000 781.520000 928.420000 ;
+ RECT 780.420000 933.380000 781.520000 933.860000 ;
+ RECT 780.420000 938.820000 781.520000 939.300000 ;
+ RECT 780.420000 906.180000 781.520000 906.660000 ;
+ RECT 780.420000 900.740000 781.520000 901.220000 ;
+ RECT 780.420000 911.620000 781.520000 912.100000 ;
+ RECT 780.420000 917.060000 781.520000 917.540000 ;
+ RECT 838.230000 889.860000 839.230000 890.340000 ;
+ RECT 838.230000 884.420000 839.230000 884.900000 ;
+ RECT 838.230000 895.300000 839.230000 895.780000 ;
+ RECT 825.420000 895.300000 826.520000 895.780000 ;
+ RECT 825.420000 889.860000 826.520000 890.340000 ;
+ RECT 825.420000 884.420000 826.520000 884.900000 ;
+ RECT 825.420000 873.540000 826.520000 874.020000 ;
+ RECT 825.420000 878.980000 826.520000 879.460000 ;
+ RECT 838.230000 873.540000 839.230000 874.020000 ;
+ RECT 838.230000 878.980000 839.230000 879.460000 ;
+ RECT 838.230000 862.660000 839.230000 863.140000 ;
+ RECT 838.230000 868.100000 839.230000 868.580000 ;
+ RECT 825.420000 868.100000 826.520000 868.580000 ;
+ RECT 825.420000 862.660000 826.520000 863.140000 ;
+ RECT 825.420000 851.780000 826.520000 852.260000 ;
+ RECT 825.420000 857.220000 826.520000 857.700000 ;
+ RECT 838.230000 851.780000 839.230000 852.260000 ;
+ RECT 838.230000 857.220000 839.230000 857.700000 ;
+ RECT 780.420000 873.540000 781.520000 874.020000 ;
+ RECT 780.420000 878.980000 781.520000 879.460000 ;
+ RECT 780.420000 884.420000 781.520000 884.900000 ;
+ RECT 780.420000 889.860000 781.520000 890.340000 ;
+ RECT 780.420000 895.300000 781.520000 895.780000 ;
+ RECT 780.420000 851.780000 781.520000 852.260000 ;
+ RECT 780.420000 857.220000 781.520000 857.700000 ;
+ RECT 780.420000 862.660000 781.520000 863.140000 ;
+ RECT 780.420000 868.100000 781.520000 868.580000 ;
+ RECT 735.420000 927.940000 736.520000 928.420000 ;
+ RECT 735.420000 922.500000 736.520000 922.980000 ;
+ RECT 735.420000 933.380000 736.520000 933.860000 ;
+ RECT 735.420000 938.820000 736.520000 939.300000 ;
+ RECT 690.420000 922.500000 691.520000 922.980000 ;
+ RECT 690.420000 927.940000 691.520000 928.420000 ;
+ RECT 690.420000 933.380000 691.520000 933.860000 ;
+ RECT 690.420000 938.820000 691.520000 939.300000 ;
+ RECT 735.420000 900.740000 736.520000 901.220000 ;
+ RECT 735.420000 906.180000 736.520000 906.660000 ;
+ RECT 735.420000 911.620000 736.520000 912.100000 ;
+ RECT 735.420000 917.060000 736.520000 917.540000 ;
+ RECT 690.420000 900.740000 691.520000 901.220000 ;
+ RECT 690.420000 906.180000 691.520000 906.660000 ;
+ RECT 690.420000 911.620000 691.520000 912.100000 ;
+ RECT 690.420000 917.060000 691.520000 917.540000 ;
+ RECT 641.590000 938.820000 642.590000 939.300000 ;
+ RECT 645.255000 938.820000 646.520000 939.300000 ;
+ RECT 641.590000 927.940000 642.590000 928.420000 ;
+ RECT 645.255000 927.940000 646.520000 928.420000 ;
+ RECT 641.590000 933.380000 642.590000 933.860000 ;
+ RECT 645.255000 933.380000 646.520000 933.860000 ;
+ RECT 641.590000 922.500000 642.590000 922.980000 ;
+ RECT 645.255000 922.500000 646.520000 922.980000 ;
+ RECT 641.590000 917.060000 642.590000 917.540000 ;
+ RECT 645.255000 917.060000 646.520000 917.540000 ;
+ RECT 641.590000 911.620000 642.590000 912.100000 ;
+ RECT 645.255000 911.620000 646.520000 912.100000 ;
+ RECT 641.590000 906.180000 642.590000 906.660000 ;
+ RECT 645.255000 906.180000 646.520000 906.660000 ;
+ RECT 641.590000 900.740000 642.590000 901.220000 ;
+ RECT 645.255000 900.740000 646.520000 901.220000 ;
+ RECT 735.420000 873.540000 736.520000 874.020000 ;
+ RECT 735.420000 878.980000 736.520000 879.460000 ;
+ RECT 735.420000 884.420000 736.520000 884.900000 ;
+ RECT 735.420000 889.860000 736.520000 890.340000 ;
+ RECT 735.420000 895.300000 736.520000 895.780000 ;
+ RECT 690.420000 873.540000 691.520000 874.020000 ;
+ RECT 690.420000 878.980000 691.520000 879.460000 ;
+ RECT 690.420000 884.420000 691.520000 884.900000 ;
+ RECT 690.420000 889.860000 691.520000 890.340000 ;
+ RECT 690.420000 895.300000 691.520000 895.780000 ;
+ RECT 735.420000 851.780000 736.520000 852.260000 ;
+ RECT 735.420000 857.220000 736.520000 857.700000 ;
+ RECT 735.420000 862.660000 736.520000 863.140000 ;
+ RECT 735.420000 868.100000 736.520000 868.580000 ;
+ RECT 690.420000 851.780000 691.520000 852.260000 ;
+ RECT 690.420000 857.220000 691.520000 857.700000 ;
+ RECT 690.420000 862.660000 691.520000 863.140000 ;
+ RECT 690.420000 868.100000 691.520000 868.580000 ;
+ RECT 641.590000 895.300000 642.590000 895.780000 ;
+ RECT 645.255000 895.300000 646.520000 895.780000 ;
+ RECT 641.590000 884.420000 642.590000 884.900000 ;
+ RECT 645.255000 884.420000 646.520000 884.900000 ;
+ RECT 641.590000 889.860000 642.590000 890.340000 ;
+ RECT 645.255000 889.860000 646.520000 890.340000 ;
+ RECT 641.590000 878.980000 642.590000 879.460000 ;
+ RECT 645.255000 878.980000 646.520000 879.460000 ;
+ RECT 641.590000 873.540000 642.590000 874.020000 ;
+ RECT 645.255000 873.540000 646.520000 874.020000 ;
+ RECT 641.590000 868.100000 642.590000 868.580000 ;
+ RECT 645.255000 868.100000 646.520000 868.580000 ;
+ RECT 641.590000 862.660000 642.590000 863.140000 ;
+ RECT 645.255000 862.660000 646.520000 863.140000 ;
+ RECT 641.590000 857.220000 642.590000 857.700000 ;
+ RECT 645.255000 857.220000 646.520000 857.700000 ;
+ RECT 641.590000 851.780000 642.590000 852.260000 ;
+ RECT 645.255000 851.780000 646.520000 852.260000 ;
+ RECT 825.420000 835.460000 826.520000 835.940000 ;
+ RECT 825.420000 840.900000 826.520000 841.380000 ;
+ RECT 838.230000 835.460000 839.230000 835.940000 ;
+ RECT 838.230000 840.900000 839.230000 841.380000 ;
+ RECT 838.230000 824.580000 839.230000 825.060000 ;
+ RECT 838.230000 830.020000 839.230000 830.500000 ;
+ RECT 825.420000 830.020000 826.520000 830.500000 ;
+ RECT 825.420000 824.580000 826.520000 825.060000 ;
+ RECT 825.420000 813.700000 826.520000 814.180000 ;
+ RECT 825.420000 819.140000 826.520000 819.620000 ;
+ RECT 838.230000 813.700000 839.230000 814.180000 ;
+ RECT 838.230000 819.140000 839.230000 819.620000 ;
+ RECT 838.230000 802.820000 839.230000 803.300000 ;
+ RECT 838.230000 797.380000 839.230000 797.860000 ;
+ RECT 838.230000 808.260000 839.230000 808.740000 ;
+ RECT 825.420000 808.260000 826.520000 808.740000 ;
+ RECT 825.420000 802.820000 826.520000 803.300000 ;
+ RECT 825.420000 797.380000 826.520000 797.860000 ;
+ RECT 780.420000 824.580000 781.520000 825.060000 ;
+ RECT 780.420000 830.020000 781.520000 830.500000 ;
+ RECT 780.420000 835.460000 781.520000 835.940000 ;
+ RECT 780.420000 840.900000 781.520000 841.380000 ;
+ RECT 780.420000 797.380000 781.520000 797.860000 ;
+ RECT 780.420000 802.820000 781.520000 803.300000 ;
+ RECT 780.420000 808.260000 781.520000 808.740000 ;
+ RECT 780.420000 813.700000 781.520000 814.180000 ;
+ RECT 780.420000 819.140000 781.520000 819.620000 ;
+ RECT 825.420000 786.500000 826.520000 786.980000 ;
+ RECT 825.420000 791.940000 826.520000 792.420000 ;
+ RECT 838.230000 786.500000 839.230000 786.980000 ;
+ RECT 838.230000 791.940000 839.230000 792.420000 ;
+ RECT 825.420000 775.620000 826.520000 776.100000 ;
+ RECT 825.420000 781.060000 826.520000 781.540000 ;
+ RECT 838.230000 775.620000 839.230000 776.100000 ;
+ RECT 838.230000 781.060000 839.230000 781.540000 ;
+ RECT 838.230000 764.740000 839.230000 765.220000 ;
+ RECT 838.230000 759.300000 839.230000 759.780000 ;
+ RECT 838.230000 770.180000 839.230000 770.660000 ;
+ RECT 825.420000 770.180000 826.520000 770.660000 ;
+ RECT 825.420000 764.740000 826.520000 765.220000 ;
+ RECT 825.420000 759.300000 826.520000 759.780000 ;
+ RECT 825.420000 753.860000 826.520000 754.340000 ;
+ RECT 838.230000 753.860000 839.230000 754.340000 ;
+ RECT 780.420000 775.620000 781.520000 776.100000 ;
+ RECT 780.420000 781.060000 781.520000 781.540000 ;
+ RECT 780.420000 786.500000 781.520000 786.980000 ;
+ RECT 780.420000 791.940000 781.520000 792.420000 ;
+ RECT 780.420000 753.860000 781.520000 754.340000 ;
+ RECT 780.420000 759.300000 781.520000 759.780000 ;
+ RECT 780.420000 764.740000 781.520000 765.220000 ;
+ RECT 780.420000 770.180000 781.520000 770.660000 ;
+ RECT 735.420000 824.580000 736.520000 825.060000 ;
+ RECT 735.420000 830.020000 736.520000 830.500000 ;
+ RECT 735.420000 835.460000 736.520000 835.940000 ;
+ RECT 735.420000 840.900000 736.520000 841.380000 ;
+ RECT 690.420000 824.580000 691.520000 825.060000 ;
+ RECT 690.420000 830.020000 691.520000 830.500000 ;
+ RECT 690.420000 835.460000 691.520000 835.940000 ;
+ RECT 690.420000 840.900000 691.520000 841.380000 ;
+ RECT 735.420000 797.380000 736.520000 797.860000 ;
+ RECT 735.420000 802.820000 736.520000 803.300000 ;
+ RECT 735.420000 808.260000 736.520000 808.740000 ;
+ RECT 735.420000 813.700000 736.520000 814.180000 ;
+ RECT 735.420000 819.140000 736.520000 819.620000 ;
+ RECT 690.420000 797.380000 691.520000 797.860000 ;
+ RECT 690.420000 802.820000 691.520000 803.300000 ;
+ RECT 690.420000 808.260000 691.520000 808.740000 ;
+ RECT 690.420000 813.700000 691.520000 814.180000 ;
+ RECT 690.420000 819.140000 691.520000 819.620000 ;
+ RECT 641.590000 840.900000 642.590000 841.380000 ;
+ RECT 645.255000 840.900000 646.520000 841.380000 ;
+ RECT 641.590000 835.460000 642.590000 835.940000 ;
+ RECT 645.255000 835.460000 646.520000 835.940000 ;
+ RECT 641.590000 830.020000 642.590000 830.500000 ;
+ RECT 645.255000 830.020000 646.520000 830.500000 ;
+ RECT 641.590000 824.580000 642.590000 825.060000 ;
+ RECT 645.255000 824.580000 646.520000 825.060000 ;
+ RECT 641.590000 819.140000 642.590000 819.620000 ;
+ RECT 645.255000 819.140000 646.520000 819.620000 ;
+ RECT 641.590000 813.700000 642.590000 814.180000 ;
+ RECT 645.255000 813.700000 646.520000 814.180000 ;
+ RECT 641.590000 802.820000 642.590000 803.300000 ;
+ RECT 645.255000 802.820000 646.520000 803.300000 ;
+ RECT 641.590000 808.260000 642.590000 808.740000 ;
+ RECT 645.255000 808.260000 646.520000 808.740000 ;
+ RECT 641.590000 797.380000 642.590000 797.860000 ;
+ RECT 645.255000 797.380000 646.520000 797.860000 ;
+ RECT 735.420000 775.620000 736.520000 776.100000 ;
+ RECT 735.420000 781.060000 736.520000 781.540000 ;
+ RECT 735.420000 786.500000 736.520000 786.980000 ;
+ RECT 735.420000 791.940000 736.520000 792.420000 ;
+ RECT 690.420000 775.620000 691.520000 776.100000 ;
+ RECT 690.420000 781.060000 691.520000 781.540000 ;
+ RECT 690.420000 786.500000 691.520000 786.980000 ;
+ RECT 690.420000 791.940000 691.520000 792.420000 ;
+ RECT 735.420000 753.860000 736.520000 754.340000 ;
+ RECT 735.420000 759.300000 736.520000 759.780000 ;
+ RECT 735.420000 764.740000 736.520000 765.220000 ;
+ RECT 735.420000 770.180000 736.520000 770.660000 ;
+ RECT 690.420000 753.860000 691.520000 754.340000 ;
+ RECT 690.420000 759.300000 691.520000 759.780000 ;
+ RECT 690.420000 764.740000 691.520000 765.220000 ;
+ RECT 690.420000 770.180000 691.520000 770.660000 ;
+ RECT 641.590000 791.940000 642.590000 792.420000 ;
+ RECT 645.255000 791.940000 646.520000 792.420000 ;
+ RECT 641.590000 786.500000 642.590000 786.980000 ;
+ RECT 645.255000 786.500000 646.520000 786.980000 ;
+ RECT 641.590000 781.060000 642.590000 781.540000 ;
+ RECT 645.255000 781.060000 646.520000 781.540000 ;
+ RECT 641.590000 775.620000 642.590000 776.100000 ;
+ RECT 645.255000 775.620000 646.520000 776.100000 ;
+ RECT 641.590000 770.180000 642.590000 770.660000 ;
+ RECT 645.255000 770.180000 646.520000 770.660000 ;
+ RECT 641.590000 759.300000 642.590000 759.780000 ;
+ RECT 645.255000 759.300000 646.520000 759.780000 ;
+ RECT 641.590000 764.740000 642.590000 765.220000 ;
+ RECT 645.255000 764.740000 646.520000 765.220000 ;
+ RECT 641.590000 753.860000 642.590000 754.340000 ;
+ RECT 645.255000 753.860000 646.520000 754.340000 ;
+ RECT 780.420000 846.340000 781.520000 846.820000 ;
+ RECT 825.420000 846.340000 826.520000 846.820000 ;
+ RECT 838.230000 846.340000 839.230000 846.820000 ;
+ RECT 690.420000 846.340000 691.520000 846.820000 ;
+ RECT 735.420000 846.340000 736.520000 846.820000 ;
+ RECT 641.590000 846.340000 642.590000 846.820000 ;
+ RECT 645.255000 846.340000 646.520000 846.820000 ;
+ RECT 640.360000 943.100000 840.460000 944.100000 ;
+ RECT 640.360000 747.530000 840.460000 748.530000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 746.280000 642.590000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 945.540000 642.590000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 746.280000 839.230000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 945.540000 839.230000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 747.530000 641.360000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 747.530000 840.460000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 943.100000 641.360000 944.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 943.100000 840.460000 944.100000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 738.560000 646.520000 739.040000 ;
+ RECT 645.255000 727.680000 646.520000 728.160000 ;
+ RECT 645.255000 733.120000 646.520000 733.600000 ;
+ RECT 645.255000 722.240000 646.520000 722.720000 ;
+ RECT 645.255000 716.800000 646.520000 717.280000 ;
+ RECT 645.255000 711.360000 646.520000 711.840000 ;
+ RECT 645.255000 705.920000 646.520000 706.400000 ;
+ RECT 645.255000 700.480000 646.520000 700.960000 ;
+ RECT 645.255000 695.040000 646.520000 695.520000 ;
+ RECT 645.255000 684.160000 646.520000 684.640000 ;
+ RECT 645.255000 689.600000 646.520000 690.080000 ;
+ RECT 645.255000 678.720000 646.520000 679.200000 ;
+ RECT 645.255000 673.280000 646.520000 673.760000 ;
+ RECT 645.255000 667.840000 646.520000 668.320000 ;
+ RECT 645.255000 662.400000 646.520000 662.880000 ;
+ RECT 645.255000 656.960000 646.520000 657.440000 ;
+ RECT 645.255000 651.520000 646.520000 652.000000 ;
+ RECT 645.255000 640.640000 646.520000 641.120000 ;
+ RECT 645.255000 635.200000 646.520000 635.680000 ;
+ RECT 645.255000 629.760000 646.520000 630.240000 ;
+ RECT 645.255000 624.320000 646.520000 624.800000 ;
+ RECT 645.255000 618.880000 646.520000 619.360000 ;
+ RECT 645.255000 613.440000 646.520000 613.920000 ;
+ RECT 645.255000 602.560000 646.520000 603.040000 ;
+ RECT 645.255000 608.000000 646.520000 608.480000 ;
+ RECT 645.255000 597.120000 646.520000 597.600000 ;
+ RECT 645.255000 591.680000 646.520000 592.160000 ;
+ RECT 645.255000 586.240000 646.520000 586.720000 ;
+ RECT 645.255000 580.800000 646.520000 581.280000 ;
+ RECT 645.255000 575.360000 646.520000 575.840000 ;
+ RECT 645.255000 569.920000 646.520000 570.400000 ;
+ RECT 645.255000 559.040000 646.520000 559.520000 ;
+ RECT 645.255000 564.480000 646.520000 564.960000 ;
+ RECT 645.255000 553.600000 646.520000 554.080000 ;
+ RECT 645.255000 646.080000 646.520000 646.560000 ;
+ RECT 825.420000 547.270000 826.520000 743.840000 ;
+ RECT 780.420000 547.270000 781.520000 743.840000 ;
+ RECT 838.230000 546.020000 839.230000 746.280000 ;
+ RECT 735.420000 547.270000 736.520000 743.840000 ;
+ RECT 690.420000 547.270000 691.520000 743.840000 ;
+ RECT 645.420000 547.270000 646.520000 743.840000 ;
+ RECT 641.590000 546.020000 642.590000 746.280000 ;
+ LAYER met3 ;
+ RECT 825.420000 738.560000 826.520000 739.040000 ;
+ RECT 838.230000 738.560000 839.230000 739.040000 ;
+ RECT 838.230000 727.680000 839.230000 728.160000 ;
+ RECT 838.230000 722.240000 839.230000 722.720000 ;
+ RECT 838.230000 733.120000 839.230000 733.600000 ;
+ RECT 825.420000 733.120000 826.520000 733.600000 ;
+ RECT 825.420000 727.680000 826.520000 728.160000 ;
+ RECT 825.420000 722.240000 826.520000 722.720000 ;
+ RECT 825.420000 711.360000 826.520000 711.840000 ;
+ RECT 825.420000 716.800000 826.520000 717.280000 ;
+ RECT 838.230000 711.360000 839.230000 711.840000 ;
+ RECT 838.230000 716.800000 839.230000 717.280000 ;
+ RECT 825.420000 700.480000 826.520000 700.960000 ;
+ RECT 825.420000 705.920000 826.520000 706.400000 ;
+ RECT 838.230000 700.480000 839.230000 700.960000 ;
+ RECT 838.230000 705.920000 839.230000 706.400000 ;
+ RECT 780.420000 722.240000 781.520000 722.720000 ;
+ RECT 780.420000 727.680000 781.520000 728.160000 ;
+ RECT 780.420000 733.120000 781.520000 733.600000 ;
+ RECT 780.420000 738.560000 781.520000 739.040000 ;
+ RECT 780.420000 705.920000 781.520000 706.400000 ;
+ RECT 780.420000 700.480000 781.520000 700.960000 ;
+ RECT 780.420000 711.360000 781.520000 711.840000 ;
+ RECT 780.420000 716.800000 781.520000 717.280000 ;
+ RECT 838.230000 689.600000 839.230000 690.080000 ;
+ RECT 838.230000 684.160000 839.230000 684.640000 ;
+ RECT 838.230000 695.040000 839.230000 695.520000 ;
+ RECT 825.420000 695.040000 826.520000 695.520000 ;
+ RECT 825.420000 689.600000 826.520000 690.080000 ;
+ RECT 825.420000 684.160000 826.520000 684.640000 ;
+ RECT 825.420000 673.280000 826.520000 673.760000 ;
+ RECT 825.420000 678.720000 826.520000 679.200000 ;
+ RECT 838.230000 673.280000 839.230000 673.760000 ;
+ RECT 838.230000 678.720000 839.230000 679.200000 ;
+ RECT 838.230000 662.400000 839.230000 662.880000 ;
+ RECT 838.230000 667.840000 839.230000 668.320000 ;
+ RECT 825.420000 667.840000 826.520000 668.320000 ;
+ RECT 825.420000 662.400000 826.520000 662.880000 ;
+ RECT 825.420000 651.520000 826.520000 652.000000 ;
+ RECT 825.420000 656.960000 826.520000 657.440000 ;
+ RECT 838.230000 651.520000 839.230000 652.000000 ;
+ RECT 838.230000 656.960000 839.230000 657.440000 ;
+ RECT 780.420000 673.280000 781.520000 673.760000 ;
+ RECT 780.420000 678.720000 781.520000 679.200000 ;
+ RECT 780.420000 684.160000 781.520000 684.640000 ;
+ RECT 780.420000 689.600000 781.520000 690.080000 ;
+ RECT 780.420000 695.040000 781.520000 695.520000 ;
+ RECT 780.420000 651.520000 781.520000 652.000000 ;
+ RECT 780.420000 656.960000 781.520000 657.440000 ;
+ RECT 780.420000 662.400000 781.520000 662.880000 ;
+ RECT 780.420000 667.840000 781.520000 668.320000 ;
+ RECT 735.420000 727.680000 736.520000 728.160000 ;
+ RECT 735.420000 722.240000 736.520000 722.720000 ;
+ RECT 735.420000 733.120000 736.520000 733.600000 ;
+ RECT 735.420000 738.560000 736.520000 739.040000 ;
+ RECT 690.420000 722.240000 691.520000 722.720000 ;
+ RECT 690.420000 727.680000 691.520000 728.160000 ;
+ RECT 690.420000 733.120000 691.520000 733.600000 ;
+ RECT 690.420000 738.560000 691.520000 739.040000 ;
+ RECT 735.420000 700.480000 736.520000 700.960000 ;
+ RECT 735.420000 705.920000 736.520000 706.400000 ;
+ RECT 735.420000 711.360000 736.520000 711.840000 ;
+ RECT 735.420000 716.800000 736.520000 717.280000 ;
+ RECT 690.420000 700.480000 691.520000 700.960000 ;
+ RECT 690.420000 705.920000 691.520000 706.400000 ;
+ RECT 690.420000 711.360000 691.520000 711.840000 ;
+ RECT 690.420000 716.800000 691.520000 717.280000 ;
+ RECT 641.590000 738.560000 642.590000 739.040000 ;
+ RECT 645.255000 738.560000 646.520000 739.040000 ;
+ RECT 641.590000 727.680000 642.590000 728.160000 ;
+ RECT 645.255000 727.680000 646.520000 728.160000 ;
+ RECT 641.590000 733.120000 642.590000 733.600000 ;
+ RECT 645.255000 733.120000 646.520000 733.600000 ;
+ RECT 641.590000 722.240000 642.590000 722.720000 ;
+ RECT 645.255000 722.240000 646.520000 722.720000 ;
+ RECT 641.590000 716.800000 642.590000 717.280000 ;
+ RECT 645.255000 716.800000 646.520000 717.280000 ;
+ RECT 641.590000 711.360000 642.590000 711.840000 ;
+ RECT 645.255000 711.360000 646.520000 711.840000 ;
+ RECT 641.590000 705.920000 642.590000 706.400000 ;
+ RECT 645.255000 705.920000 646.520000 706.400000 ;
+ RECT 641.590000 700.480000 642.590000 700.960000 ;
+ RECT 645.255000 700.480000 646.520000 700.960000 ;
+ RECT 735.420000 673.280000 736.520000 673.760000 ;
+ RECT 735.420000 678.720000 736.520000 679.200000 ;
+ RECT 735.420000 684.160000 736.520000 684.640000 ;
+ RECT 735.420000 689.600000 736.520000 690.080000 ;
+ RECT 735.420000 695.040000 736.520000 695.520000 ;
+ RECT 690.420000 673.280000 691.520000 673.760000 ;
+ RECT 690.420000 678.720000 691.520000 679.200000 ;
+ RECT 690.420000 684.160000 691.520000 684.640000 ;
+ RECT 690.420000 689.600000 691.520000 690.080000 ;
+ RECT 690.420000 695.040000 691.520000 695.520000 ;
+ RECT 735.420000 651.520000 736.520000 652.000000 ;
+ RECT 735.420000 656.960000 736.520000 657.440000 ;
+ RECT 735.420000 662.400000 736.520000 662.880000 ;
+ RECT 735.420000 667.840000 736.520000 668.320000 ;
+ RECT 690.420000 651.520000 691.520000 652.000000 ;
+ RECT 690.420000 656.960000 691.520000 657.440000 ;
+ RECT 690.420000 662.400000 691.520000 662.880000 ;
+ RECT 690.420000 667.840000 691.520000 668.320000 ;
+ RECT 641.590000 695.040000 642.590000 695.520000 ;
+ RECT 645.255000 695.040000 646.520000 695.520000 ;
+ RECT 641.590000 684.160000 642.590000 684.640000 ;
+ RECT 645.255000 684.160000 646.520000 684.640000 ;
+ RECT 641.590000 689.600000 642.590000 690.080000 ;
+ RECT 645.255000 689.600000 646.520000 690.080000 ;
+ RECT 641.590000 678.720000 642.590000 679.200000 ;
+ RECT 645.255000 678.720000 646.520000 679.200000 ;
+ RECT 641.590000 673.280000 642.590000 673.760000 ;
+ RECT 645.255000 673.280000 646.520000 673.760000 ;
+ RECT 641.590000 667.840000 642.590000 668.320000 ;
+ RECT 645.255000 667.840000 646.520000 668.320000 ;
+ RECT 641.590000 662.400000 642.590000 662.880000 ;
+ RECT 645.255000 662.400000 646.520000 662.880000 ;
+ RECT 641.590000 656.960000 642.590000 657.440000 ;
+ RECT 645.255000 656.960000 646.520000 657.440000 ;
+ RECT 641.590000 651.520000 642.590000 652.000000 ;
+ RECT 645.255000 651.520000 646.520000 652.000000 ;
+ RECT 825.420000 635.200000 826.520000 635.680000 ;
+ RECT 825.420000 640.640000 826.520000 641.120000 ;
+ RECT 838.230000 635.200000 839.230000 635.680000 ;
+ RECT 838.230000 640.640000 839.230000 641.120000 ;
+ RECT 838.230000 624.320000 839.230000 624.800000 ;
+ RECT 838.230000 629.760000 839.230000 630.240000 ;
+ RECT 825.420000 629.760000 826.520000 630.240000 ;
+ RECT 825.420000 624.320000 826.520000 624.800000 ;
+ RECT 825.420000 613.440000 826.520000 613.920000 ;
+ RECT 825.420000 618.880000 826.520000 619.360000 ;
+ RECT 838.230000 613.440000 839.230000 613.920000 ;
+ RECT 838.230000 618.880000 839.230000 619.360000 ;
+ RECT 838.230000 602.560000 839.230000 603.040000 ;
+ RECT 838.230000 597.120000 839.230000 597.600000 ;
+ RECT 838.230000 608.000000 839.230000 608.480000 ;
+ RECT 825.420000 608.000000 826.520000 608.480000 ;
+ RECT 825.420000 602.560000 826.520000 603.040000 ;
+ RECT 825.420000 597.120000 826.520000 597.600000 ;
+ RECT 780.420000 624.320000 781.520000 624.800000 ;
+ RECT 780.420000 629.760000 781.520000 630.240000 ;
+ RECT 780.420000 635.200000 781.520000 635.680000 ;
+ RECT 780.420000 640.640000 781.520000 641.120000 ;
+ RECT 780.420000 597.120000 781.520000 597.600000 ;
+ RECT 780.420000 602.560000 781.520000 603.040000 ;
+ RECT 780.420000 608.000000 781.520000 608.480000 ;
+ RECT 780.420000 613.440000 781.520000 613.920000 ;
+ RECT 780.420000 618.880000 781.520000 619.360000 ;
+ RECT 825.420000 586.240000 826.520000 586.720000 ;
+ RECT 825.420000 591.680000 826.520000 592.160000 ;
+ RECT 838.230000 586.240000 839.230000 586.720000 ;
+ RECT 838.230000 591.680000 839.230000 592.160000 ;
+ RECT 825.420000 575.360000 826.520000 575.840000 ;
+ RECT 825.420000 580.800000 826.520000 581.280000 ;
+ RECT 838.230000 575.360000 839.230000 575.840000 ;
+ RECT 838.230000 580.800000 839.230000 581.280000 ;
+ RECT 838.230000 564.480000 839.230000 564.960000 ;
+ RECT 838.230000 559.040000 839.230000 559.520000 ;
+ RECT 838.230000 569.920000 839.230000 570.400000 ;
+ RECT 825.420000 569.920000 826.520000 570.400000 ;
+ RECT 825.420000 564.480000 826.520000 564.960000 ;
+ RECT 825.420000 559.040000 826.520000 559.520000 ;
+ RECT 825.420000 553.600000 826.520000 554.080000 ;
+ RECT 838.230000 553.600000 839.230000 554.080000 ;
+ RECT 780.420000 575.360000 781.520000 575.840000 ;
+ RECT 780.420000 580.800000 781.520000 581.280000 ;
+ RECT 780.420000 586.240000 781.520000 586.720000 ;
+ RECT 780.420000 591.680000 781.520000 592.160000 ;
+ RECT 780.420000 553.600000 781.520000 554.080000 ;
+ RECT 780.420000 559.040000 781.520000 559.520000 ;
+ RECT 780.420000 564.480000 781.520000 564.960000 ;
+ RECT 780.420000 569.920000 781.520000 570.400000 ;
+ RECT 735.420000 624.320000 736.520000 624.800000 ;
+ RECT 735.420000 629.760000 736.520000 630.240000 ;
+ RECT 735.420000 635.200000 736.520000 635.680000 ;
+ RECT 735.420000 640.640000 736.520000 641.120000 ;
+ RECT 690.420000 624.320000 691.520000 624.800000 ;
+ RECT 690.420000 629.760000 691.520000 630.240000 ;
+ RECT 690.420000 635.200000 691.520000 635.680000 ;
+ RECT 690.420000 640.640000 691.520000 641.120000 ;
+ RECT 735.420000 597.120000 736.520000 597.600000 ;
+ RECT 735.420000 602.560000 736.520000 603.040000 ;
+ RECT 735.420000 608.000000 736.520000 608.480000 ;
+ RECT 735.420000 613.440000 736.520000 613.920000 ;
+ RECT 735.420000 618.880000 736.520000 619.360000 ;
+ RECT 690.420000 597.120000 691.520000 597.600000 ;
+ RECT 690.420000 602.560000 691.520000 603.040000 ;
+ RECT 690.420000 608.000000 691.520000 608.480000 ;
+ RECT 690.420000 613.440000 691.520000 613.920000 ;
+ RECT 690.420000 618.880000 691.520000 619.360000 ;
+ RECT 641.590000 640.640000 642.590000 641.120000 ;
+ RECT 645.255000 640.640000 646.520000 641.120000 ;
+ RECT 641.590000 635.200000 642.590000 635.680000 ;
+ RECT 645.255000 635.200000 646.520000 635.680000 ;
+ RECT 641.590000 629.760000 642.590000 630.240000 ;
+ RECT 645.255000 629.760000 646.520000 630.240000 ;
+ RECT 641.590000 624.320000 642.590000 624.800000 ;
+ RECT 645.255000 624.320000 646.520000 624.800000 ;
+ RECT 641.590000 618.880000 642.590000 619.360000 ;
+ RECT 645.255000 618.880000 646.520000 619.360000 ;
+ RECT 641.590000 613.440000 642.590000 613.920000 ;
+ RECT 645.255000 613.440000 646.520000 613.920000 ;
+ RECT 641.590000 602.560000 642.590000 603.040000 ;
+ RECT 645.255000 602.560000 646.520000 603.040000 ;
+ RECT 641.590000 608.000000 642.590000 608.480000 ;
+ RECT 645.255000 608.000000 646.520000 608.480000 ;
+ RECT 641.590000 597.120000 642.590000 597.600000 ;
+ RECT 645.255000 597.120000 646.520000 597.600000 ;
+ RECT 735.420000 575.360000 736.520000 575.840000 ;
+ RECT 735.420000 580.800000 736.520000 581.280000 ;
+ RECT 735.420000 586.240000 736.520000 586.720000 ;
+ RECT 735.420000 591.680000 736.520000 592.160000 ;
+ RECT 690.420000 575.360000 691.520000 575.840000 ;
+ RECT 690.420000 580.800000 691.520000 581.280000 ;
+ RECT 690.420000 586.240000 691.520000 586.720000 ;
+ RECT 690.420000 591.680000 691.520000 592.160000 ;
+ RECT 735.420000 553.600000 736.520000 554.080000 ;
+ RECT 735.420000 559.040000 736.520000 559.520000 ;
+ RECT 735.420000 564.480000 736.520000 564.960000 ;
+ RECT 735.420000 569.920000 736.520000 570.400000 ;
+ RECT 690.420000 553.600000 691.520000 554.080000 ;
+ RECT 690.420000 559.040000 691.520000 559.520000 ;
+ RECT 690.420000 564.480000 691.520000 564.960000 ;
+ RECT 690.420000 569.920000 691.520000 570.400000 ;
+ RECT 641.590000 591.680000 642.590000 592.160000 ;
+ RECT 645.255000 591.680000 646.520000 592.160000 ;
+ RECT 641.590000 586.240000 642.590000 586.720000 ;
+ RECT 645.255000 586.240000 646.520000 586.720000 ;
+ RECT 641.590000 580.800000 642.590000 581.280000 ;
+ RECT 645.255000 580.800000 646.520000 581.280000 ;
+ RECT 641.590000 575.360000 642.590000 575.840000 ;
+ RECT 645.255000 575.360000 646.520000 575.840000 ;
+ RECT 641.590000 569.920000 642.590000 570.400000 ;
+ RECT 645.255000 569.920000 646.520000 570.400000 ;
+ RECT 641.590000 559.040000 642.590000 559.520000 ;
+ RECT 645.255000 559.040000 646.520000 559.520000 ;
+ RECT 641.590000 564.480000 642.590000 564.960000 ;
+ RECT 645.255000 564.480000 646.520000 564.960000 ;
+ RECT 641.590000 553.600000 642.590000 554.080000 ;
+ RECT 645.255000 553.600000 646.520000 554.080000 ;
+ RECT 780.420000 646.080000 781.520000 646.560000 ;
+ RECT 825.420000 646.080000 826.520000 646.560000 ;
+ RECT 838.230000 646.080000 839.230000 646.560000 ;
+ RECT 690.420000 646.080000 691.520000 646.560000 ;
+ RECT 735.420000 646.080000 736.520000 646.560000 ;
+ RECT 641.590000 646.080000 642.590000 646.560000 ;
+ RECT 645.255000 646.080000 646.520000 646.560000 ;
+ RECT 640.360000 742.840000 840.460000 743.840000 ;
+ RECT 640.360000 547.270000 840.460000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 546.020000 642.590000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 745.280000 642.590000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 546.020000 839.230000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 745.280000 839.230000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 547.270000 641.360000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 547.270000 840.460000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 742.840000 641.360000 743.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 742.840000 840.460000 743.840000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 538.300000 646.520000 538.780000 ;
+ RECT 645.255000 527.420000 646.520000 527.900000 ;
+ RECT 645.255000 532.860000 646.520000 533.340000 ;
+ RECT 645.255000 521.980000 646.520000 522.460000 ;
+ RECT 645.255000 516.540000 646.520000 517.020000 ;
+ RECT 645.255000 511.100000 646.520000 511.580000 ;
+ RECT 645.255000 505.660000 646.520000 506.140000 ;
+ RECT 645.255000 500.220000 646.520000 500.700000 ;
+ RECT 645.255000 494.780000 646.520000 495.260000 ;
+ RECT 645.255000 483.900000 646.520000 484.380000 ;
+ RECT 645.255000 489.340000 646.520000 489.820000 ;
+ RECT 645.255000 478.460000 646.520000 478.940000 ;
+ RECT 645.255000 473.020000 646.520000 473.500000 ;
+ RECT 645.255000 467.580000 646.520000 468.060000 ;
+ RECT 645.255000 462.140000 646.520000 462.620000 ;
+ RECT 645.255000 456.700000 646.520000 457.180000 ;
+ RECT 645.255000 451.260000 646.520000 451.740000 ;
+ RECT 645.255000 440.380000 646.520000 440.860000 ;
+ RECT 645.255000 434.940000 646.520000 435.420000 ;
+ RECT 645.255000 429.500000 646.520000 429.980000 ;
+ RECT 645.255000 424.060000 646.520000 424.540000 ;
+ RECT 645.255000 418.620000 646.520000 419.100000 ;
+ RECT 645.255000 413.180000 646.520000 413.660000 ;
+ RECT 645.255000 402.300000 646.520000 402.780000 ;
+ RECT 645.255000 407.740000 646.520000 408.220000 ;
+ RECT 645.255000 396.860000 646.520000 397.340000 ;
+ RECT 645.255000 391.420000 646.520000 391.900000 ;
+ RECT 645.255000 385.980000 646.520000 386.460000 ;
+ RECT 645.255000 380.540000 646.520000 381.020000 ;
+ RECT 645.255000 375.100000 646.520000 375.580000 ;
+ RECT 645.255000 369.660000 646.520000 370.140000 ;
+ RECT 645.255000 358.780000 646.520000 359.260000 ;
+ RECT 645.255000 364.220000 646.520000 364.700000 ;
+ RECT 645.255000 353.340000 646.520000 353.820000 ;
+ RECT 645.255000 445.820000 646.520000 446.300000 ;
+ RECT 825.420000 347.010000 826.520000 543.580000 ;
+ RECT 780.420000 347.010000 781.520000 543.580000 ;
+ RECT 838.230000 345.760000 839.230000 546.020000 ;
+ RECT 735.420000 347.010000 736.520000 543.580000 ;
+ RECT 690.420000 347.010000 691.520000 543.580000 ;
+ RECT 645.420000 347.010000 646.520000 543.580000 ;
+ RECT 641.590000 345.760000 642.590000 546.020000 ;
+ LAYER met3 ;
+ RECT 825.420000 538.300000 826.520000 538.780000 ;
+ RECT 838.230000 538.300000 839.230000 538.780000 ;
+ RECT 838.230000 527.420000 839.230000 527.900000 ;
+ RECT 838.230000 521.980000 839.230000 522.460000 ;
+ RECT 838.230000 532.860000 839.230000 533.340000 ;
+ RECT 825.420000 532.860000 826.520000 533.340000 ;
+ RECT 825.420000 527.420000 826.520000 527.900000 ;
+ RECT 825.420000 521.980000 826.520000 522.460000 ;
+ RECT 825.420000 511.100000 826.520000 511.580000 ;
+ RECT 825.420000 516.540000 826.520000 517.020000 ;
+ RECT 838.230000 511.100000 839.230000 511.580000 ;
+ RECT 838.230000 516.540000 839.230000 517.020000 ;
+ RECT 825.420000 500.220000 826.520000 500.700000 ;
+ RECT 825.420000 505.660000 826.520000 506.140000 ;
+ RECT 838.230000 500.220000 839.230000 500.700000 ;
+ RECT 838.230000 505.660000 839.230000 506.140000 ;
+ RECT 780.420000 521.980000 781.520000 522.460000 ;
+ RECT 780.420000 527.420000 781.520000 527.900000 ;
+ RECT 780.420000 532.860000 781.520000 533.340000 ;
+ RECT 780.420000 538.300000 781.520000 538.780000 ;
+ RECT 780.420000 505.660000 781.520000 506.140000 ;
+ RECT 780.420000 500.220000 781.520000 500.700000 ;
+ RECT 780.420000 511.100000 781.520000 511.580000 ;
+ RECT 780.420000 516.540000 781.520000 517.020000 ;
+ RECT 838.230000 489.340000 839.230000 489.820000 ;
+ RECT 838.230000 483.900000 839.230000 484.380000 ;
+ RECT 838.230000 494.780000 839.230000 495.260000 ;
+ RECT 825.420000 494.780000 826.520000 495.260000 ;
+ RECT 825.420000 489.340000 826.520000 489.820000 ;
+ RECT 825.420000 483.900000 826.520000 484.380000 ;
+ RECT 825.420000 473.020000 826.520000 473.500000 ;
+ RECT 825.420000 478.460000 826.520000 478.940000 ;
+ RECT 838.230000 473.020000 839.230000 473.500000 ;
+ RECT 838.230000 478.460000 839.230000 478.940000 ;
+ RECT 838.230000 462.140000 839.230000 462.620000 ;
+ RECT 838.230000 467.580000 839.230000 468.060000 ;
+ RECT 825.420000 467.580000 826.520000 468.060000 ;
+ RECT 825.420000 462.140000 826.520000 462.620000 ;
+ RECT 825.420000 451.260000 826.520000 451.740000 ;
+ RECT 825.420000 456.700000 826.520000 457.180000 ;
+ RECT 838.230000 451.260000 839.230000 451.740000 ;
+ RECT 838.230000 456.700000 839.230000 457.180000 ;
+ RECT 780.420000 473.020000 781.520000 473.500000 ;
+ RECT 780.420000 478.460000 781.520000 478.940000 ;
+ RECT 780.420000 483.900000 781.520000 484.380000 ;
+ RECT 780.420000 489.340000 781.520000 489.820000 ;
+ RECT 780.420000 494.780000 781.520000 495.260000 ;
+ RECT 780.420000 451.260000 781.520000 451.740000 ;
+ RECT 780.420000 456.700000 781.520000 457.180000 ;
+ RECT 780.420000 462.140000 781.520000 462.620000 ;
+ RECT 780.420000 467.580000 781.520000 468.060000 ;
+ RECT 735.420000 527.420000 736.520000 527.900000 ;
+ RECT 735.420000 521.980000 736.520000 522.460000 ;
+ RECT 735.420000 532.860000 736.520000 533.340000 ;
+ RECT 735.420000 538.300000 736.520000 538.780000 ;
+ RECT 690.420000 521.980000 691.520000 522.460000 ;
+ RECT 690.420000 527.420000 691.520000 527.900000 ;
+ RECT 690.420000 532.860000 691.520000 533.340000 ;
+ RECT 690.420000 538.300000 691.520000 538.780000 ;
+ RECT 735.420000 500.220000 736.520000 500.700000 ;
+ RECT 735.420000 505.660000 736.520000 506.140000 ;
+ RECT 735.420000 511.100000 736.520000 511.580000 ;
+ RECT 735.420000 516.540000 736.520000 517.020000 ;
+ RECT 690.420000 500.220000 691.520000 500.700000 ;
+ RECT 690.420000 505.660000 691.520000 506.140000 ;
+ RECT 690.420000 511.100000 691.520000 511.580000 ;
+ RECT 690.420000 516.540000 691.520000 517.020000 ;
+ RECT 641.590000 538.300000 642.590000 538.780000 ;
+ RECT 645.255000 538.300000 646.520000 538.780000 ;
+ RECT 641.590000 527.420000 642.590000 527.900000 ;
+ RECT 645.255000 527.420000 646.520000 527.900000 ;
+ RECT 641.590000 532.860000 642.590000 533.340000 ;
+ RECT 645.255000 532.860000 646.520000 533.340000 ;
+ RECT 641.590000 521.980000 642.590000 522.460000 ;
+ RECT 645.255000 521.980000 646.520000 522.460000 ;
+ RECT 641.590000 516.540000 642.590000 517.020000 ;
+ RECT 645.255000 516.540000 646.520000 517.020000 ;
+ RECT 641.590000 511.100000 642.590000 511.580000 ;
+ RECT 645.255000 511.100000 646.520000 511.580000 ;
+ RECT 641.590000 505.660000 642.590000 506.140000 ;
+ RECT 645.255000 505.660000 646.520000 506.140000 ;
+ RECT 641.590000 500.220000 642.590000 500.700000 ;
+ RECT 645.255000 500.220000 646.520000 500.700000 ;
+ RECT 735.420000 473.020000 736.520000 473.500000 ;
+ RECT 735.420000 478.460000 736.520000 478.940000 ;
+ RECT 735.420000 483.900000 736.520000 484.380000 ;
+ RECT 735.420000 489.340000 736.520000 489.820000 ;
+ RECT 735.420000 494.780000 736.520000 495.260000 ;
+ RECT 690.420000 473.020000 691.520000 473.500000 ;
+ RECT 690.420000 478.460000 691.520000 478.940000 ;
+ RECT 690.420000 483.900000 691.520000 484.380000 ;
+ RECT 690.420000 489.340000 691.520000 489.820000 ;
+ RECT 690.420000 494.780000 691.520000 495.260000 ;
+ RECT 735.420000 451.260000 736.520000 451.740000 ;
+ RECT 735.420000 456.700000 736.520000 457.180000 ;
+ RECT 735.420000 462.140000 736.520000 462.620000 ;
+ RECT 735.420000 467.580000 736.520000 468.060000 ;
+ RECT 690.420000 451.260000 691.520000 451.740000 ;
+ RECT 690.420000 456.700000 691.520000 457.180000 ;
+ RECT 690.420000 462.140000 691.520000 462.620000 ;
+ RECT 690.420000 467.580000 691.520000 468.060000 ;
+ RECT 641.590000 494.780000 642.590000 495.260000 ;
+ RECT 645.255000 494.780000 646.520000 495.260000 ;
+ RECT 641.590000 483.900000 642.590000 484.380000 ;
+ RECT 645.255000 483.900000 646.520000 484.380000 ;
+ RECT 641.590000 489.340000 642.590000 489.820000 ;
+ RECT 645.255000 489.340000 646.520000 489.820000 ;
+ RECT 641.590000 478.460000 642.590000 478.940000 ;
+ RECT 645.255000 478.460000 646.520000 478.940000 ;
+ RECT 641.590000 473.020000 642.590000 473.500000 ;
+ RECT 645.255000 473.020000 646.520000 473.500000 ;
+ RECT 641.590000 467.580000 642.590000 468.060000 ;
+ RECT 645.255000 467.580000 646.520000 468.060000 ;
+ RECT 641.590000 462.140000 642.590000 462.620000 ;
+ RECT 645.255000 462.140000 646.520000 462.620000 ;
+ RECT 641.590000 456.700000 642.590000 457.180000 ;
+ RECT 645.255000 456.700000 646.520000 457.180000 ;
+ RECT 641.590000 451.260000 642.590000 451.740000 ;
+ RECT 645.255000 451.260000 646.520000 451.740000 ;
+ RECT 825.420000 434.940000 826.520000 435.420000 ;
+ RECT 825.420000 440.380000 826.520000 440.860000 ;
+ RECT 838.230000 434.940000 839.230000 435.420000 ;
+ RECT 838.230000 440.380000 839.230000 440.860000 ;
+ RECT 838.230000 424.060000 839.230000 424.540000 ;
+ RECT 838.230000 429.500000 839.230000 429.980000 ;
+ RECT 825.420000 429.500000 826.520000 429.980000 ;
+ RECT 825.420000 424.060000 826.520000 424.540000 ;
+ RECT 825.420000 413.180000 826.520000 413.660000 ;
+ RECT 825.420000 418.620000 826.520000 419.100000 ;
+ RECT 838.230000 413.180000 839.230000 413.660000 ;
+ RECT 838.230000 418.620000 839.230000 419.100000 ;
+ RECT 838.230000 402.300000 839.230000 402.780000 ;
+ RECT 838.230000 396.860000 839.230000 397.340000 ;
+ RECT 838.230000 407.740000 839.230000 408.220000 ;
+ RECT 825.420000 407.740000 826.520000 408.220000 ;
+ RECT 825.420000 402.300000 826.520000 402.780000 ;
+ RECT 825.420000 396.860000 826.520000 397.340000 ;
+ RECT 780.420000 424.060000 781.520000 424.540000 ;
+ RECT 780.420000 429.500000 781.520000 429.980000 ;
+ RECT 780.420000 434.940000 781.520000 435.420000 ;
+ RECT 780.420000 440.380000 781.520000 440.860000 ;
+ RECT 780.420000 396.860000 781.520000 397.340000 ;
+ RECT 780.420000 402.300000 781.520000 402.780000 ;
+ RECT 780.420000 407.740000 781.520000 408.220000 ;
+ RECT 780.420000 413.180000 781.520000 413.660000 ;
+ RECT 780.420000 418.620000 781.520000 419.100000 ;
+ RECT 825.420000 385.980000 826.520000 386.460000 ;
+ RECT 825.420000 391.420000 826.520000 391.900000 ;
+ RECT 838.230000 385.980000 839.230000 386.460000 ;
+ RECT 838.230000 391.420000 839.230000 391.900000 ;
+ RECT 825.420000 375.100000 826.520000 375.580000 ;
+ RECT 825.420000 380.540000 826.520000 381.020000 ;
+ RECT 838.230000 375.100000 839.230000 375.580000 ;
+ RECT 838.230000 380.540000 839.230000 381.020000 ;
+ RECT 838.230000 364.220000 839.230000 364.700000 ;
+ RECT 838.230000 358.780000 839.230000 359.260000 ;
+ RECT 838.230000 369.660000 839.230000 370.140000 ;
+ RECT 825.420000 369.660000 826.520000 370.140000 ;
+ RECT 825.420000 364.220000 826.520000 364.700000 ;
+ RECT 825.420000 358.780000 826.520000 359.260000 ;
+ RECT 825.420000 353.340000 826.520000 353.820000 ;
+ RECT 838.230000 353.340000 839.230000 353.820000 ;
+ RECT 780.420000 375.100000 781.520000 375.580000 ;
+ RECT 780.420000 380.540000 781.520000 381.020000 ;
+ RECT 780.420000 385.980000 781.520000 386.460000 ;
+ RECT 780.420000 391.420000 781.520000 391.900000 ;
+ RECT 780.420000 353.340000 781.520000 353.820000 ;
+ RECT 780.420000 358.780000 781.520000 359.260000 ;
+ RECT 780.420000 364.220000 781.520000 364.700000 ;
+ RECT 780.420000 369.660000 781.520000 370.140000 ;
+ RECT 735.420000 424.060000 736.520000 424.540000 ;
+ RECT 735.420000 429.500000 736.520000 429.980000 ;
+ RECT 735.420000 434.940000 736.520000 435.420000 ;
+ RECT 735.420000 440.380000 736.520000 440.860000 ;
+ RECT 690.420000 424.060000 691.520000 424.540000 ;
+ RECT 690.420000 429.500000 691.520000 429.980000 ;
+ RECT 690.420000 434.940000 691.520000 435.420000 ;
+ RECT 690.420000 440.380000 691.520000 440.860000 ;
+ RECT 735.420000 396.860000 736.520000 397.340000 ;
+ RECT 735.420000 402.300000 736.520000 402.780000 ;
+ RECT 735.420000 407.740000 736.520000 408.220000 ;
+ RECT 735.420000 413.180000 736.520000 413.660000 ;
+ RECT 735.420000 418.620000 736.520000 419.100000 ;
+ RECT 690.420000 396.860000 691.520000 397.340000 ;
+ RECT 690.420000 402.300000 691.520000 402.780000 ;
+ RECT 690.420000 407.740000 691.520000 408.220000 ;
+ RECT 690.420000 413.180000 691.520000 413.660000 ;
+ RECT 690.420000 418.620000 691.520000 419.100000 ;
+ RECT 641.590000 440.380000 642.590000 440.860000 ;
+ RECT 645.255000 440.380000 646.520000 440.860000 ;
+ RECT 641.590000 434.940000 642.590000 435.420000 ;
+ RECT 645.255000 434.940000 646.520000 435.420000 ;
+ RECT 641.590000 429.500000 642.590000 429.980000 ;
+ RECT 645.255000 429.500000 646.520000 429.980000 ;
+ RECT 641.590000 424.060000 642.590000 424.540000 ;
+ RECT 645.255000 424.060000 646.520000 424.540000 ;
+ RECT 641.590000 418.620000 642.590000 419.100000 ;
+ RECT 645.255000 418.620000 646.520000 419.100000 ;
+ RECT 641.590000 413.180000 642.590000 413.660000 ;
+ RECT 645.255000 413.180000 646.520000 413.660000 ;
+ RECT 641.590000 402.300000 642.590000 402.780000 ;
+ RECT 645.255000 402.300000 646.520000 402.780000 ;
+ RECT 641.590000 407.740000 642.590000 408.220000 ;
+ RECT 645.255000 407.740000 646.520000 408.220000 ;
+ RECT 641.590000 396.860000 642.590000 397.340000 ;
+ RECT 645.255000 396.860000 646.520000 397.340000 ;
+ RECT 735.420000 375.100000 736.520000 375.580000 ;
+ RECT 735.420000 380.540000 736.520000 381.020000 ;
+ RECT 735.420000 385.980000 736.520000 386.460000 ;
+ RECT 735.420000 391.420000 736.520000 391.900000 ;
+ RECT 690.420000 375.100000 691.520000 375.580000 ;
+ RECT 690.420000 380.540000 691.520000 381.020000 ;
+ RECT 690.420000 385.980000 691.520000 386.460000 ;
+ RECT 690.420000 391.420000 691.520000 391.900000 ;
+ RECT 735.420000 353.340000 736.520000 353.820000 ;
+ RECT 735.420000 358.780000 736.520000 359.260000 ;
+ RECT 735.420000 364.220000 736.520000 364.700000 ;
+ RECT 735.420000 369.660000 736.520000 370.140000 ;
+ RECT 690.420000 353.340000 691.520000 353.820000 ;
+ RECT 690.420000 358.780000 691.520000 359.260000 ;
+ RECT 690.420000 364.220000 691.520000 364.700000 ;
+ RECT 690.420000 369.660000 691.520000 370.140000 ;
+ RECT 641.590000 391.420000 642.590000 391.900000 ;
+ RECT 645.255000 391.420000 646.520000 391.900000 ;
+ RECT 641.590000 385.980000 642.590000 386.460000 ;
+ RECT 645.255000 385.980000 646.520000 386.460000 ;
+ RECT 641.590000 380.540000 642.590000 381.020000 ;
+ RECT 645.255000 380.540000 646.520000 381.020000 ;
+ RECT 641.590000 375.100000 642.590000 375.580000 ;
+ RECT 645.255000 375.100000 646.520000 375.580000 ;
+ RECT 641.590000 369.660000 642.590000 370.140000 ;
+ RECT 645.255000 369.660000 646.520000 370.140000 ;
+ RECT 641.590000 358.780000 642.590000 359.260000 ;
+ RECT 645.255000 358.780000 646.520000 359.260000 ;
+ RECT 641.590000 364.220000 642.590000 364.700000 ;
+ RECT 645.255000 364.220000 646.520000 364.700000 ;
+ RECT 641.590000 353.340000 642.590000 353.820000 ;
+ RECT 645.255000 353.340000 646.520000 353.820000 ;
+ RECT 780.420000 445.820000 781.520000 446.300000 ;
+ RECT 825.420000 445.820000 826.520000 446.300000 ;
+ RECT 838.230000 445.820000 839.230000 446.300000 ;
+ RECT 690.420000 445.820000 691.520000 446.300000 ;
+ RECT 735.420000 445.820000 736.520000 446.300000 ;
+ RECT 641.590000 445.820000 642.590000 446.300000 ;
+ RECT 645.255000 445.820000 646.520000 446.300000 ;
+ RECT 640.360000 542.580000 840.460000 543.580000 ;
+ RECT 640.360000 347.010000 840.460000 348.010000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 345.760000 642.590000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 545.020000 642.590000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 345.760000 839.230000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 545.020000 839.230000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 347.010000 641.360000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 347.010000 840.460000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 542.580000 641.360000 543.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 542.580000 840.460000 543.580000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 338.040000 646.520000 338.520000 ;
+ RECT 645.255000 327.160000 646.520000 327.640000 ;
+ RECT 645.255000 332.600000 646.520000 333.080000 ;
+ RECT 645.255000 321.720000 646.520000 322.200000 ;
+ RECT 645.255000 316.280000 646.520000 316.760000 ;
+ RECT 645.255000 310.840000 646.520000 311.320000 ;
+ RECT 645.255000 305.400000 646.520000 305.880000 ;
+ RECT 645.255000 299.960000 646.520000 300.440000 ;
+ RECT 645.255000 294.520000 646.520000 295.000000 ;
+ RECT 645.255000 283.640000 646.520000 284.120000 ;
+ RECT 645.255000 289.080000 646.520000 289.560000 ;
+ RECT 645.255000 278.200000 646.520000 278.680000 ;
+ RECT 645.255000 272.760000 646.520000 273.240000 ;
+ RECT 645.255000 267.320000 646.520000 267.800000 ;
+ RECT 645.255000 261.880000 646.520000 262.360000 ;
+ RECT 645.255000 256.440000 646.520000 256.920000 ;
+ RECT 645.255000 251.000000 646.520000 251.480000 ;
+ RECT 645.255000 240.120000 646.520000 240.600000 ;
+ RECT 645.255000 234.680000 646.520000 235.160000 ;
+ RECT 645.255000 229.240000 646.520000 229.720000 ;
+ RECT 645.255000 223.800000 646.520000 224.280000 ;
+ RECT 645.255000 218.360000 646.520000 218.840000 ;
+ RECT 645.255000 212.920000 646.520000 213.400000 ;
+ RECT 645.255000 202.040000 646.520000 202.520000 ;
+ RECT 645.255000 207.480000 646.520000 207.960000 ;
+ RECT 645.255000 196.600000 646.520000 197.080000 ;
+ RECT 645.255000 191.160000 646.520000 191.640000 ;
+ RECT 645.255000 185.720000 646.520000 186.200000 ;
+ RECT 645.255000 180.280000 646.520000 180.760000 ;
+ RECT 645.255000 174.840000 646.520000 175.320000 ;
+ RECT 645.255000 169.400000 646.520000 169.880000 ;
+ RECT 645.255000 158.520000 646.520000 159.000000 ;
+ RECT 645.255000 163.960000 646.520000 164.440000 ;
+ RECT 645.255000 153.080000 646.520000 153.560000 ;
+ RECT 645.255000 245.560000 646.520000 246.040000 ;
+ RECT 825.420000 146.750000 826.520000 343.320000 ;
+ RECT 780.420000 146.750000 781.520000 343.320000 ;
+ RECT 838.230000 145.500000 839.230000 345.760000 ;
+ RECT 735.420000 146.750000 736.520000 343.320000 ;
+ RECT 690.420000 146.750000 691.520000 343.320000 ;
+ RECT 645.420000 146.750000 646.520000 343.320000 ;
+ RECT 641.590000 145.500000 642.590000 345.760000 ;
+ LAYER met3 ;
+ RECT 825.420000 338.040000 826.520000 338.520000 ;
+ RECT 838.230000 338.040000 839.230000 338.520000 ;
+ RECT 838.230000 327.160000 839.230000 327.640000 ;
+ RECT 838.230000 321.720000 839.230000 322.200000 ;
+ RECT 838.230000 332.600000 839.230000 333.080000 ;
+ RECT 825.420000 332.600000 826.520000 333.080000 ;
+ RECT 825.420000 327.160000 826.520000 327.640000 ;
+ RECT 825.420000 321.720000 826.520000 322.200000 ;
+ RECT 825.420000 310.840000 826.520000 311.320000 ;
+ RECT 825.420000 316.280000 826.520000 316.760000 ;
+ RECT 838.230000 310.840000 839.230000 311.320000 ;
+ RECT 838.230000 316.280000 839.230000 316.760000 ;
+ RECT 825.420000 299.960000 826.520000 300.440000 ;
+ RECT 825.420000 305.400000 826.520000 305.880000 ;
+ RECT 838.230000 299.960000 839.230000 300.440000 ;
+ RECT 838.230000 305.400000 839.230000 305.880000 ;
+ RECT 780.420000 321.720000 781.520000 322.200000 ;
+ RECT 780.420000 327.160000 781.520000 327.640000 ;
+ RECT 780.420000 332.600000 781.520000 333.080000 ;
+ RECT 780.420000 338.040000 781.520000 338.520000 ;
+ RECT 780.420000 305.400000 781.520000 305.880000 ;
+ RECT 780.420000 299.960000 781.520000 300.440000 ;
+ RECT 780.420000 310.840000 781.520000 311.320000 ;
+ RECT 780.420000 316.280000 781.520000 316.760000 ;
+ RECT 838.230000 289.080000 839.230000 289.560000 ;
+ RECT 838.230000 283.640000 839.230000 284.120000 ;
+ RECT 838.230000 294.520000 839.230000 295.000000 ;
+ RECT 825.420000 294.520000 826.520000 295.000000 ;
+ RECT 825.420000 289.080000 826.520000 289.560000 ;
+ RECT 825.420000 283.640000 826.520000 284.120000 ;
+ RECT 825.420000 272.760000 826.520000 273.240000 ;
+ RECT 825.420000 278.200000 826.520000 278.680000 ;
+ RECT 838.230000 272.760000 839.230000 273.240000 ;
+ RECT 838.230000 278.200000 839.230000 278.680000 ;
+ RECT 838.230000 261.880000 839.230000 262.360000 ;
+ RECT 838.230000 267.320000 839.230000 267.800000 ;
+ RECT 825.420000 267.320000 826.520000 267.800000 ;
+ RECT 825.420000 261.880000 826.520000 262.360000 ;
+ RECT 825.420000 251.000000 826.520000 251.480000 ;
+ RECT 825.420000 256.440000 826.520000 256.920000 ;
+ RECT 838.230000 251.000000 839.230000 251.480000 ;
+ RECT 838.230000 256.440000 839.230000 256.920000 ;
+ RECT 780.420000 272.760000 781.520000 273.240000 ;
+ RECT 780.420000 278.200000 781.520000 278.680000 ;
+ RECT 780.420000 283.640000 781.520000 284.120000 ;
+ RECT 780.420000 289.080000 781.520000 289.560000 ;
+ RECT 780.420000 294.520000 781.520000 295.000000 ;
+ RECT 780.420000 251.000000 781.520000 251.480000 ;
+ RECT 780.420000 256.440000 781.520000 256.920000 ;
+ RECT 780.420000 261.880000 781.520000 262.360000 ;
+ RECT 780.420000 267.320000 781.520000 267.800000 ;
+ RECT 735.420000 327.160000 736.520000 327.640000 ;
+ RECT 735.420000 321.720000 736.520000 322.200000 ;
+ RECT 735.420000 332.600000 736.520000 333.080000 ;
+ RECT 735.420000 338.040000 736.520000 338.520000 ;
+ RECT 690.420000 321.720000 691.520000 322.200000 ;
+ RECT 690.420000 327.160000 691.520000 327.640000 ;
+ RECT 690.420000 332.600000 691.520000 333.080000 ;
+ RECT 690.420000 338.040000 691.520000 338.520000 ;
+ RECT 735.420000 299.960000 736.520000 300.440000 ;
+ RECT 735.420000 305.400000 736.520000 305.880000 ;
+ RECT 735.420000 310.840000 736.520000 311.320000 ;
+ RECT 735.420000 316.280000 736.520000 316.760000 ;
+ RECT 690.420000 299.960000 691.520000 300.440000 ;
+ RECT 690.420000 305.400000 691.520000 305.880000 ;
+ RECT 690.420000 310.840000 691.520000 311.320000 ;
+ RECT 690.420000 316.280000 691.520000 316.760000 ;
+ RECT 641.590000 338.040000 642.590000 338.520000 ;
+ RECT 645.255000 338.040000 646.520000 338.520000 ;
+ RECT 641.590000 327.160000 642.590000 327.640000 ;
+ RECT 645.255000 327.160000 646.520000 327.640000 ;
+ RECT 641.590000 332.600000 642.590000 333.080000 ;
+ RECT 645.255000 332.600000 646.520000 333.080000 ;
+ RECT 641.590000 321.720000 642.590000 322.200000 ;
+ RECT 645.255000 321.720000 646.520000 322.200000 ;
+ RECT 641.590000 316.280000 642.590000 316.760000 ;
+ RECT 645.255000 316.280000 646.520000 316.760000 ;
+ RECT 641.590000 310.840000 642.590000 311.320000 ;
+ RECT 645.255000 310.840000 646.520000 311.320000 ;
+ RECT 641.590000 305.400000 642.590000 305.880000 ;
+ RECT 645.255000 305.400000 646.520000 305.880000 ;
+ RECT 641.590000 299.960000 642.590000 300.440000 ;
+ RECT 645.255000 299.960000 646.520000 300.440000 ;
+ RECT 735.420000 272.760000 736.520000 273.240000 ;
+ RECT 735.420000 278.200000 736.520000 278.680000 ;
+ RECT 735.420000 283.640000 736.520000 284.120000 ;
+ RECT 735.420000 289.080000 736.520000 289.560000 ;
+ RECT 735.420000 294.520000 736.520000 295.000000 ;
+ RECT 690.420000 272.760000 691.520000 273.240000 ;
+ RECT 690.420000 278.200000 691.520000 278.680000 ;
+ RECT 690.420000 283.640000 691.520000 284.120000 ;
+ RECT 690.420000 289.080000 691.520000 289.560000 ;
+ RECT 690.420000 294.520000 691.520000 295.000000 ;
+ RECT 735.420000 251.000000 736.520000 251.480000 ;
+ RECT 735.420000 256.440000 736.520000 256.920000 ;
+ RECT 735.420000 261.880000 736.520000 262.360000 ;
+ RECT 735.420000 267.320000 736.520000 267.800000 ;
+ RECT 690.420000 251.000000 691.520000 251.480000 ;
+ RECT 690.420000 256.440000 691.520000 256.920000 ;
+ RECT 690.420000 261.880000 691.520000 262.360000 ;
+ RECT 690.420000 267.320000 691.520000 267.800000 ;
+ RECT 641.590000 294.520000 642.590000 295.000000 ;
+ RECT 645.255000 294.520000 646.520000 295.000000 ;
+ RECT 641.590000 283.640000 642.590000 284.120000 ;
+ RECT 645.255000 283.640000 646.520000 284.120000 ;
+ RECT 641.590000 289.080000 642.590000 289.560000 ;
+ RECT 645.255000 289.080000 646.520000 289.560000 ;
+ RECT 641.590000 278.200000 642.590000 278.680000 ;
+ RECT 645.255000 278.200000 646.520000 278.680000 ;
+ RECT 641.590000 272.760000 642.590000 273.240000 ;
+ RECT 645.255000 272.760000 646.520000 273.240000 ;
+ RECT 641.590000 267.320000 642.590000 267.800000 ;
+ RECT 645.255000 267.320000 646.520000 267.800000 ;
+ RECT 641.590000 261.880000 642.590000 262.360000 ;
+ RECT 645.255000 261.880000 646.520000 262.360000 ;
+ RECT 641.590000 256.440000 642.590000 256.920000 ;
+ RECT 645.255000 256.440000 646.520000 256.920000 ;
+ RECT 641.590000 251.000000 642.590000 251.480000 ;
+ RECT 645.255000 251.000000 646.520000 251.480000 ;
+ RECT 825.420000 234.680000 826.520000 235.160000 ;
+ RECT 825.420000 240.120000 826.520000 240.600000 ;
+ RECT 838.230000 234.680000 839.230000 235.160000 ;
+ RECT 838.230000 240.120000 839.230000 240.600000 ;
+ RECT 838.230000 223.800000 839.230000 224.280000 ;
+ RECT 838.230000 229.240000 839.230000 229.720000 ;
+ RECT 825.420000 229.240000 826.520000 229.720000 ;
+ RECT 825.420000 223.800000 826.520000 224.280000 ;
+ RECT 825.420000 212.920000 826.520000 213.400000 ;
+ RECT 825.420000 218.360000 826.520000 218.840000 ;
+ RECT 838.230000 212.920000 839.230000 213.400000 ;
+ RECT 838.230000 218.360000 839.230000 218.840000 ;
+ RECT 838.230000 202.040000 839.230000 202.520000 ;
+ RECT 838.230000 196.600000 839.230000 197.080000 ;
+ RECT 838.230000 207.480000 839.230000 207.960000 ;
+ RECT 825.420000 207.480000 826.520000 207.960000 ;
+ RECT 825.420000 202.040000 826.520000 202.520000 ;
+ RECT 825.420000 196.600000 826.520000 197.080000 ;
+ RECT 780.420000 223.800000 781.520000 224.280000 ;
+ RECT 780.420000 229.240000 781.520000 229.720000 ;
+ RECT 780.420000 234.680000 781.520000 235.160000 ;
+ RECT 780.420000 240.120000 781.520000 240.600000 ;
+ RECT 780.420000 196.600000 781.520000 197.080000 ;
+ RECT 780.420000 202.040000 781.520000 202.520000 ;
+ RECT 780.420000 207.480000 781.520000 207.960000 ;
+ RECT 780.420000 212.920000 781.520000 213.400000 ;
+ RECT 780.420000 218.360000 781.520000 218.840000 ;
+ RECT 825.420000 185.720000 826.520000 186.200000 ;
+ RECT 825.420000 191.160000 826.520000 191.640000 ;
+ RECT 838.230000 185.720000 839.230000 186.200000 ;
+ RECT 838.230000 191.160000 839.230000 191.640000 ;
+ RECT 825.420000 174.840000 826.520000 175.320000 ;
+ RECT 825.420000 180.280000 826.520000 180.760000 ;
+ RECT 838.230000 174.840000 839.230000 175.320000 ;
+ RECT 838.230000 180.280000 839.230000 180.760000 ;
+ RECT 838.230000 163.960000 839.230000 164.440000 ;
+ RECT 838.230000 158.520000 839.230000 159.000000 ;
+ RECT 838.230000 169.400000 839.230000 169.880000 ;
+ RECT 825.420000 169.400000 826.520000 169.880000 ;
+ RECT 825.420000 163.960000 826.520000 164.440000 ;
+ RECT 825.420000 158.520000 826.520000 159.000000 ;
+ RECT 825.420000 153.080000 826.520000 153.560000 ;
+ RECT 838.230000 153.080000 839.230000 153.560000 ;
+ RECT 780.420000 174.840000 781.520000 175.320000 ;
+ RECT 780.420000 180.280000 781.520000 180.760000 ;
+ RECT 780.420000 185.720000 781.520000 186.200000 ;
+ RECT 780.420000 191.160000 781.520000 191.640000 ;
+ RECT 780.420000 153.080000 781.520000 153.560000 ;
+ RECT 780.420000 158.520000 781.520000 159.000000 ;
+ RECT 780.420000 163.960000 781.520000 164.440000 ;
+ RECT 780.420000 169.400000 781.520000 169.880000 ;
+ RECT 735.420000 223.800000 736.520000 224.280000 ;
+ RECT 735.420000 229.240000 736.520000 229.720000 ;
+ RECT 735.420000 234.680000 736.520000 235.160000 ;
+ RECT 735.420000 240.120000 736.520000 240.600000 ;
+ RECT 690.420000 223.800000 691.520000 224.280000 ;
+ RECT 690.420000 229.240000 691.520000 229.720000 ;
+ RECT 690.420000 234.680000 691.520000 235.160000 ;
+ RECT 690.420000 240.120000 691.520000 240.600000 ;
+ RECT 735.420000 196.600000 736.520000 197.080000 ;
+ RECT 735.420000 202.040000 736.520000 202.520000 ;
+ RECT 735.420000 207.480000 736.520000 207.960000 ;
+ RECT 735.420000 212.920000 736.520000 213.400000 ;
+ RECT 735.420000 218.360000 736.520000 218.840000 ;
+ RECT 690.420000 196.600000 691.520000 197.080000 ;
+ RECT 690.420000 202.040000 691.520000 202.520000 ;
+ RECT 690.420000 207.480000 691.520000 207.960000 ;
+ RECT 690.420000 212.920000 691.520000 213.400000 ;
+ RECT 690.420000 218.360000 691.520000 218.840000 ;
+ RECT 641.590000 240.120000 642.590000 240.600000 ;
+ RECT 645.255000 240.120000 646.520000 240.600000 ;
+ RECT 641.590000 234.680000 642.590000 235.160000 ;
+ RECT 645.255000 234.680000 646.520000 235.160000 ;
+ RECT 641.590000 229.240000 642.590000 229.720000 ;
+ RECT 645.255000 229.240000 646.520000 229.720000 ;
+ RECT 641.590000 223.800000 642.590000 224.280000 ;
+ RECT 645.255000 223.800000 646.520000 224.280000 ;
+ RECT 641.590000 218.360000 642.590000 218.840000 ;
+ RECT 645.255000 218.360000 646.520000 218.840000 ;
+ RECT 641.590000 212.920000 642.590000 213.400000 ;
+ RECT 645.255000 212.920000 646.520000 213.400000 ;
+ RECT 641.590000 202.040000 642.590000 202.520000 ;
+ RECT 645.255000 202.040000 646.520000 202.520000 ;
+ RECT 641.590000 207.480000 642.590000 207.960000 ;
+ RECT 645.255000 207.480000 646.520000 207.960000 ;
+ RECT 641.590000 196.600000 642.590000 197.080000 ;
+ RECT 645.255000 196.600000 646.520000 197.080000 ;
+ RECT 735.420000 174.840000 736.520000 175.320000 ;
+ RECT 735.420000 180.280000 736.520000 180.760000 ;
+ RECT 735.420000 185.720000 736.520000 186.200000 ;
+ RECT 735.420000 191.160000 736.520000 191.640000 ;
+ RECT 690.420000 174.840000 691.520000 175.320000 ;
+ RECT 690.420000 180.280000 691.520000 180.760000 ;
+ RECT 690.420000 185.720000 691.520000 186.200000 ;
+ RECT 690.420000 191.160000 691.520000 191.640000 ;
+ RECT 735.420000 153.080000 736.520000 153.560000 ;
+ RECT 735.420000 158.520000 736.520000 159.000000 ;
+ RECT 735.420000 163.960000 736.520000 164.440000 ;
+ RECT 735.420000 169.400000 736.520000 169.880000 ;
+ RECT 690.420000 153.080000 691.520000 153.560000 ;
+ RECT 690.420000 158.520000 691.520000 159.000000 ;
+ RECT 690.420000 163.960000 691.520000 164.440000 ;
+ RECT 690.420000 169.400000 691.520000 169.880000 ;
+ RECT 641.590000 191.160000 642.590000 191.640000 ;
+ RECT 645.255000 191.160000 646.520000 191.640000 ;
+ RECT 641.590000 185.720000 642.590000 186.200000 ;
+ RECT 645.255000 185.720000 646.520000 186.200000 ;
+ RECT 641.590000 180.280000 642.590000 180.760000 ;
+ RECT 645.255000 180.280000 646.520000 180.760000 ;
+ RECT 641.590000 174.840000 642.590000 175.320000 ;
+ RECT 645.255000 174.840000 646.520000 175.320000 ;
+ RECT 641.590000 169.400000 642.590000 169.880000 ;
+ RECT 645.255000 169.400000 646.520000 169.880000 ;
+ RECT 641.590000 158.520000 642.590000 159.000000 ;
+ RECT 645.255000 158.520000 646.520000 159.000000 ;
+ RECT 641.590000 163.960000 642.590000 164.440000 ;
+ RECT 645.255000 163.960000 646.520000 164.440000 ;
+ RECT 641.590000 153.080000 642.590000 153.560000 ;
+ RECT 645.255000 153.080000 646.520000 153.560000 ;
+ RECT 780.420000 245.560000 781.520000 246.040000 ;
+ RECT 825.420000 245.560000 826.520000 246.040000 ;
+ RECT 838.230000 245.560000 839.230000 246.040000 ;
+ RECT 690.420000 245.560000 691.520000 246.040000 ;
+ RECT 735.420000 245.560000 736.520000 246.040000 ;
+ RECT 641.590000 245.560000 642.590000 246.040000 ;
+ RECT 645.255000 245.560000 646.520000 246.040000 ;
+ RECT 640.360000 342.320000 840.460000 343.320000 ;
+ RECT 640.360000 146.750000 840.460000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 145.500000 642.590000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 344.760000 642.590000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 145.500000 839.230000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 344.760000 839.230000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 146.750000 641.360000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 146.750000 840.460000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 342.320000 641.360000 343.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 342.320000 840.460000 343.320000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'S_term_single2'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 139.140000 646.520000 139.620000 ;
+ RECT 645.255000 133.700000 646.520000 134.180000 ;
+ RECT 645.255000 128.260000 646.520000 128.740000 ;
+ RECT 645.255000 122.820000 646.520000 123.300000 ;
+ RECT 641.590000 115.240000 642.590000 145.500000 ;
+ RECT 838.230000 115.240000 839.230000 145.500000 ;
+ RECT 645.420000 116.490000 646.520000 143.740000 ;
+ RECT 690.420000 116.490000 691.520000 143.740000 ;
+ RECT 735.420000 116.490000 736.520000 143.740000 ;
+ RECT 780.420000 116.490000 781.520000 143.740000 ;
+ RECT 825.420000 116.490000 826.520000 143.740000 ;
+ LAYER met3 ;
+ RECT 838.230000 139.140000 839.230000 139.620000 ;
+ RECT 838.230000 133.700000 839.230000 134.180000 ;
+ RECT 825.420000 139.140000 826.520000 139.620000 ;
+ RECT 825.420000 133.700000 826.520000 134.180000 ;
+ RECT 780.420000 133.700000 781.520000 134.180000 ;
+ RECT 780.420000 139.140000 781.520000 139.620000 ;
+ RECT 735.420000 133.700000 736.520000 134.180000 ;
+ RECT 690.420000 133.700000 691.520000 134.180000 ;
+ RECT 735.420000 139.140000 736.520000 139.620000 ;
+ RECT 690.420000 139.140000 691.520000 139.620000 ;
+ RECT 645.255000 139.140000 646.520000 139.620000 ;
+ RECT 641.590000 139.140000 642.590000 139.620000 ;
+ RECT 645.255000 133.700000 646.520000 134.180000 ;
+ RECT 641.590000 133.700000 642.590000 134.180000 ;
+ RECT 838.230000 128.260000 839.230000 128.740000 ;
+ RECT 838.230000 122.820000 839.230000 123.300000 ;
+ RECT 825.420000 128.260000 826.520000 128.740000 ;
+ RECT 825.420000 122.820000 826.520000 123.300000 ;
+ RECT 780.420000 122.820000 781.520000 123.300000 ;
+ RECT 780.420000 128.260000 781.520000 128.740000 ;
+ RECT 735.420000 122.820000 736.520000 123.300000 ;
+ RECT 690.420000 122.820000 691.520000 123.300000 ;
+ RECT 735.420000 128.260000 736.520000 128.740000 ;
+ RECT 690.420000 128.260000 691.520000 128.740000 ;
+ RECT 645.255000 128.260000 646.520000 128.740000 ;
+ RECT 641.590000 128.260000 642.590000 128.740000 ;
+ RECT 645.255000 122.820000 646.520000 123.300000 ;
+ RECT 641.590000 122.820000 642.590000 123.300000 ;
+ RECT 640.360000 142.740000 840.460000 143.740000 ;
+ RECT 640.360000 116.490000 840.460000 117.490000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 115.240000 642.590000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 144.500000 642.590000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 115.240000 839.230000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 144.500000 839.230000 145.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 116.490000 641.360000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 116.490000 840.460000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 142.740000 641.360000 143.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 142.740000 840.460000 143.740000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single2'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 3341.940000 646.520000 3342.420000 ;
+ RECT 645.255000 3331.060000 646.520000 3331.540000 ;
+ RECT 645.255000 3336.500000 646.520000 3336.980000 ;
+ RECT 645.255000 3325.620000 646.520000 3326.100000 ;
+ RECT 645.255000 3320.180000 646.520000 3320.660000 ;
+ RECT 645.255000 3314.740000 646.520000 3315.220000 ;
+ RECT 645.255000 3309.300000 646.520000 3309.780000 ;
+ RECT 645.255000 3303.860000 646.520000 3304.340000 ;
+ RECT 645.255000 3298.420000 646.520000 3298.900000 ;
+ RECT 645.255000 3287.540000 646.520000 3288.020000 ;
+ RECT 645.255000 3292.980000 646.520000 3293.460000 ;
+ RECT 645.255000 3282.100000 646.520000 3282.580000 ;
+ RECT 645.255000 3276.660000 646.520000 3277.140000 ;
+ RECT 645.255000 3271.220000 646.520000 3271.700000 ;
+ RECT 645.255000 3265.780000 646.520000 3266.260000 ;
+ RECT 645.255000 3260.340000 646.520000 3260.820000 ;
+ RECT 645.255000 3254.900000 646.520000 3255.380000 ;
+ RECT 645.255000 3244.020000 646.520000 3244.500000 ;
+ RECT 645.255000 3238.580000 646.520000 3239.060000 ;
+ RECT 645.255000 3233.140000 646.520000 3233.620000 ;
+ RECT 645.255000 3227.700000 646.520000 3228.180000 ;
+ RECT 645.255000 3222.260000 646.520000 3222.740000 ;
+ RECT 645.255000 3216.820000 646.520000 3217.300000 ;
+ RECT 645.255000 3205.940000 646.520000 3206.420000 ;
+ RECT 645.255000 3211.380000 646.520000 3211.860000 ;
+ RECT 645.255000 3200.500000 646.520000 3200.980000 ;
+ RECT 645.255000 3195.060000 646.520000 3195.540000 ;
+ RECT 645.255000 3189.620000 646.520000 3190.100000 ;
+ RECT 645.255000 3184.180000 646.520000 3184.660000 ;
+ RECT 645.255000 3178.740000 646.520000 3179.220000 ;
+ RECT 645.255000 3173.300000 646.520000 3173.780000 ;
+ RECT 645.255000 3162.420000 646.520000 3162.900000 ;
+ RECT 645.255000 3167.860000 646.520000 3168.340000 ;
+ RECT 645.255000 3156.980000 646.520000 3157.460000 ;
+ RECT 645.255000 3249.460000 646.520000 3249.940000 ;
+ RECT 825.420000 3150.650000 826.520000 3347.220000 ;
+ RECT 780.420000 3150.650000 781.520000 3347.220000 ;
+ RECT 838.230000 3149.400000 839.230000 3349.660000 ;
+ RECT 735.420000 3150.650000 736.520000 3347.220000 ;
+ RECT 690.420000 3150.650000 691.520000 3347.220000 ;
+ RECT 645.420000 3150.650000 646.520000 3347.220000 ;
+ RECT 641.590000 3149.400000 642.590000 3349.660000 ;
+ LAYER met3 ;
+ RECT 825.420000 3341.940000 826.520000 3342.420000 ;
+ RECT 838.230000 3341.940000 839.230000 3342.420000 ;
+ RECT 838.230000 3331.060000 839.230000 3331.540000 ;
+ RECT 838.230000 3325.620000 839.230000 3326.100000 ;
+ RECT 838.230000 3336.500000 839.230000 3336.980000 ;
+ RECT 825.420000 3336.500000 826.520000 3336.980000 ;
+ RECT 825.420000 3331.060000 826.520000 3331.540000 ;
+ RECT 825.420000 3325.620000 826.520000 3326.100000 ;
+ RECT 825.420000 3314.740000 826.520000 3315.220000 ;
+ RECT 825.420000 3320.180000 826.520000 3320.660000 ;
+ RECT 838.230000 3314.740000 839.230000 3315.220000 ;
+ RECT 838.230000 3320.180000 839.230000 3320.660000 ;
+ RECT 825.420000 3303.860000 826.520000 3304.340000 ;
+ RECT 825.420000 3309.300000 826.520000 3309.780000 ;
+ RECT 838.230000 3303.860000 839.230000 3304.340000 ;
+ RECT 838.230000 3309.300000 839.230000 3309.780000 ;
+ RECT 780.420000 3325.620000 781.520000 3326.100000 ;
+ RECT 780.420000 3331.060000 781.520000 3331.540000 ;
+ RECT 780.420000 3336.500000 781.520000 3336.980000 ;
+ RECT 780.420000 3341.940000 781.520000 3342.420000 ;
+ RECT 780.420000 3309.300000 781.520000 3309.780000 ;
+ RECT 780.420000 3303.860000 781.520000 3304.340000 ;
+ RECT 780.420000 3314.740000 781.520000 3315.220000 ;
+ RECT 780.420000 3320.180000 781.520000 3320.660000 ;
+ RECT 838.230000 3292.980000 839.230000 3293.460000 ;
+ RECT 838.230000 3287.540000 839.230000 3288.020000 ;
+ RECT 838.230000 3298.420000 839.230000 3298.900000 ;
+ RECT 825.420000 3298.420000 826.520000 3298.900000 ;
+ RECT 825.420000 3292.980000 826.520000 3293.460000 ;
+ RECT 825.420000 3287.540000 826.520000 3288.020000 ;
+ RECT 825.420000 3276.660000 826.520000 3277.140000 ;
+ RECT 825.420000 3282.100000 826.520000 3282.580000 ;
+ RECT 838.230000 3276.660000 839.230000 3277.140000 ;
+ RECT 838.230000 3282.100000 839.230000 3282.580000 ;
+ RECT 838.230000 3265.780000 839.230000 3266.260000 ;
+ RECT 838.230000 3271.220000 839.230000 3271.700000 ;
+ RECT 825.420000 3271.220000 826.520000 3271.700000 ;
+ RECT 825.420000 3265.780000 826.520000 3266.260000 ;
+ RECT 825.420000 3254.900000 826.520000 3255.380000 ;
+ RECT 825.420000 3260.340000 826.520000 3260.820000 ;
+ RECT 838.230000 3254.900000 839.230000 3255.380000 ;
+ RECT 838.230000 3260.340000 839.230000 3260.820000 ;
+ RECT 780.420000 3276.660000 781.520000 3277.140000 ;
+ RECT 780.420000 3282.100000 781.520000 3282.580000 ;
+ RECT 780.420000 3287.540000 781.520000 3288.020000 ;
+ RECT 780.420000 3292.980000 781.520000 3293.460000 ;
+ RECT 780.420000 3298.420000 781.520000 3298.900000 ;
+ RECT 780.420000 3254.900000 781.520000 3255.380000 ;
+ RECT 780.420000 3260.340000 781.520000 3260.820000 ;
+ RECT 780.420000 3265.780000 781.520000 3266.260000 ;
+ RECT 780.420000 3271.220000 781.520000 3271.700000 ;
+ RECT 735.420000 3331.060000 736.520000 3331.540000 ;
+ RECT 735.420000 3325.620000 736.520000 3326.100000 ;
+ RECT 735.420000 3336.500000 736.520000 3336.980000 ;
+ RECT 735.420000 3341.940000 736.520000 3342.420000 ;
+ RECT 690.420000 3325.620000 691.520000 3326.100000 ;
+ RECT 690.420000 3331.060000 691.520000 3331.540000 ;
+ RECT 690.420000 3336.500000 691.520000 3336.980000 ;
+ RECT 690.420000 3341.940000 691.520000 3342.420000 ;
+ RECT 735.420000 3303.860000 736.520000 3304.340000 ;
+ RECT 735.420000 3309.300000 736.520000 3309.780000 ;
+ RECT 735.420000 3314.740000 736.520000 3315.220000 ;
+ RECT 735.420000 3320.180000 736.520000 3320.660000 ;
+ RECT 690.420000 3303.860000 691.520000 3304.340000 ;
+ RECT 690.420000 3309.300000 691.520000 3309.780000 ;
+ RECT 690.420000 3314.740000 691.520000 3315.220000 ;
+ RECT 690.420000 3320.180000 691.520000 3320.660000 ;
+ RECT 641.590000 3341.940000 642.590000 3342.420000 ;
+ RECT 645.255000 3341.940000 646.520000 3342.420000 ;
+ RECT 641.590000 3331.060000 642.590000 3331.540000 ;
+ RECT 645.255000 3331.060000 646.520000 3331.540000 ;
+ RECT 641.590000 3336.500000 642.590000 3336.980000 ;
+ RECT 645.255000 3336.500000 646.520000 3336.980000 ;
+ RECT 641.590000 3325.620000 642.590000 3326.100000 ;
+ RECT 645.255000 3325.620000 646.520000 3326.100000 ;
+ RECT 641.590000 3320.180000 642.590000 3320.660000 ;
+ RECT 645.255000 3320.180000 646.520000 3320.660000 ;
+ RECT 641.590000 3314.740000 642.590000 3315.220000 ;
+ RECT 645.255000 3314.740000 646.520000 3315.220000 ;
+ RECT 641.590000 3309.300000 642.590000 3309.780000 ;
+ RECT 645.255000 3309.300000 646.520000 3309.780000 ;
+ RECT 641.590000 3303.860000 642.590000 3304.340000 ;
+ RECT 645.255000 3303.860000 646.520000 3304.340000 ;
+ RECT 735.420000 3276.660000 736.520000 3277.140000 ;
+ RECT 735.420000 3282.100000 736.520000 3282.580000 ;
+ RECT 735.420000 3287.540000 736.520000 3288.020000 ;
+ RECT 735.420000 3292.980000 736.520000 3293.460000 ;
+ RECT 735.420000 3298.420000 736.520000 3298.900000 ;
+ RECT 690.420000 3276.660000 691.520000 3277.140000 ;
+ RECT 690.420000 3282.100000 691.520000 3282.580000 ;
+ RECT 690.420000 3287.540000 691.520000 3288.020000 ;
+ RECT 690.420000 3292.980000 691.520000 3293.460000 ;
+ RECT 690.420000 3298.420000 691.520000 3298.900000 ;
+ RECT 735.420000 3254.900000 736.520000 3255.380000 ;
+ RECT 735.420000 3260.340000 736.520000 3260.820000 ;
+ RECT 735.420000 3265.780000 736.520000 3266.260000 ;
+ RECT 735.420000 3271.220000 736.520000 3271.700000 ;
+ RECT 690.420000 3254.900000 691.520000 3255.380000 ;
+ RECT 690.420000 3260.340000 691.520000 3260.820000 ;
+ RECT 690.420000 3265.780000 691.520000 3266.260000 ;
+ RECT 690.420000 3271.220000 691.520000 3271.700000 ;
+ RECT 641.590000 3298.420000 642.590000 3298.900000 ;
+ RECT 645.255000 3298.420000 646.520000 3298.900000 ;
+ RECT 641.590000 3287.540000 642.590000 3288.020000 ;
+ RECT 645.255000 3287.540000 646.520000 3288.020000 ;
+ RECT 641.590000 3292.980000 642.590000 3293.460000 ;
+ RECT 645.255000 3292.980000 646.520000 3293.460000 ;
+ RECT 641.590000 3282.100000 642.590000 3282.580000 ;
+ RECT 645.255000 3282.100000 646.520000 3282.580000 ;
+ RECT 641.590000 3276.660000 642.590000 3277.140000 ;
+ RECT 645.255000 3276.660000 646.520000 3277.140000 ;
+ RECT 641.590000 3271.220000 642.590000 3271.700000 ;
+ RECT 645.255000 3271.220000 646.520000 3271.700000 ;
+ RECT 641.590000 3265.780000 642.590000 3266.260000 ;
+ RECT 645.255000 3265.780000 646.520000 3266.260000 ;
+ RECT 641.590000 3260.340000 642.590000 3260.820000 ;
+ RECT 645.255000 3260.340000 646.520000 3260.820000 ;
+ RECT 641.590000 3254.900000 642.590000 3255.380000 ;
+ RECT 645.255000 3254.900000 646.520000 3255.380000 ;
+ RECT 825.420000 3238.580000 826.520000 3239.060000 ;
+ RECT 825.420000 3244.020000 826.520000 3244.500000 ;
+ RECT 838.230000 3238.580000 839.230000 3239.060000 ;
+ RECT 838.230000 3244.020000 839.230000 3244.500000 ;
+ RECT 838.230000 3227.700000 839.230000 3228.180000 ;
+ RECT 838.230000 3233.140000 839.230000 3233.620000 ;
+ RECT 825.420000 3233.140000 826.520000 3233.620000 ;
+ RECT 825.420000 3227.700000 826.520000 3228.180000 ;
+ RECT 825.420000 3216.820000 826.520000 3217.300000 ;
+ RECT 825.420000 3222.260000 826.520000 3222.740000 ;
+ RECT 838.230000 3216.820000 839.230000 3217.300000 ;
+ RECT 838.230000 3222.260000 839.230000 3222.740000 ;
+ RECT 838.230000 3205.940000 839.230000 3206.420000 ;
+ RECT 838.230000 3200.500000 839.230000 3200.980000 ;
+ RECT 838.230000 3211.380000 839.230000 3211.860000 ;
+ RECT 825.420000 3211.380000 826.520000 3211.860000 ;
+ RECT 825.420000 3205.940000 826.520000 3206.420000 ;
+ RECT 825.420000 3200.500000 826.520000 3200.980000 ;
+ RECT 780.420000 3227.700000 781.520000 3228.180000 ;
+ RECT 780.420000 3233.140000 781.520000 3233.620000 ;
+ RECT 780.420000 3238.580000 781.520000 3239.060000 ;
+ RECT 780.420000 3244.020000 781.520000 3244.500000 ;
+ RECT 780.420000 3200.500000 781.520000 3200.980000 ;
+ RECT 780.420000 3205.940000 781.520000 3206.420000 ;
+ RECT 780.420000 3211.380000 781.520000 3211.860000 ;
+ RECT 780.420000 3216.820000 781.520000 3217.300000 ;
+ RECT 780.420000 3222.260000 781.520000 3222.740000 ;
+ RECT 825.420000 3189.620000 826.520000 3190.100000 ;
+ RECT 825.420000 3195.060000 826.520000 3195.540000 ;
+ RECT 838.230000 3189.620000 839.230000 3190.100000 ;
+ RECT 838.230000 3195.060000 839.230000 3195.540000 ;
+ RECT 825.420000 3178.740000 826.520000 3179.220000 ;
+ RECT 825.420000 3184.180000 826.520000 3184.660000 ;
+ RECT 838.230000 3178.740000 839.230000 3179.220000 ;
+ RECT 838.230000 3184.180000 839.230000 3184.660000 ;
+ RECT 838.230000 3167.860000 839.230000 3168.340000 ;
+ RECT 838.230000 3162.420000 839.230000 3162.900000 ;
+ RECT 838.230000 3173.300000 839.230000 3173.780000 ;
+ RECT 825.420000 3173.300000 826.520000 3173.780000 ;
+ RECT 825.420000 3167.860000 826.520000 3168.340000 ;
+ RECT 825.420000 3162.420000 826.520000 3162.900000 ;
+ RECT 825.420000 3156.980000 826.520000 3157.460000 ;
+ RECT 838.230000 3156.980000 839.230000 3157.460000 ;
+ RECT 780.420000 3178.740000 781.520000 3179.220000 ;
+ RECT 780.420000 3184.180000 781.520000 3184.660000 ;
+ RECT 780.420000 3189.620000 781.520000 3190.100000 ;
+ RECT 780.420000 3195.060000 781.520000 3195.540000 ;
+ RECT 780.420000 3156.980000 781.520000 3157.460000 ;
+ RECT 780.420000 3162.420000 781.520000 3162.900000 ;
+ RECT 780.420000 3167.860000 781.520000 3168.340000 ;
+ RECT 780.420000 3173.300000 781.520000 3173.780000 ;
+ RECT 735.420000 3227.700000 736.520000 3228.180000 ;
+ RECT 735.420000 3233.140000 736.520000 3233.620000 ;
+ RECT 735.420000 3238.580000 736.520000 3239.060000 ;
+ RECT 735.420000 3244.020000 736.520000 3244.500000 ;
+ RECT 690.420000 3227.700000 691.520000 3228.180000 ;
+ RECT 690.420000 3233.140000 691.520000 3233.620000 ;
+ RECT 690.420000 3238.580000 691.520000 3239.060000 ;
+ RECT 690.420000 3244.020000 691.520000 3244.500000 ;
+ RECT 735.420000 3200.500000 736.520000 3200.980000 ;
+ RECT 735.420000 3205.940000 736.520000 3206.420000 ;
+ RECT 735.420000 3211.380000 736.520000 3211.860000 ;
+ RECT 735.420000 3216.820000 736.520000 3217.300000 ;
+ RECT 735.420000 3222.260000 736.520000 3222.740000 ;
+ RECT 690.420000 3200.500000 691.520000 3200.980000 ;
+ RECT 690.420000 3205.940000 691.520000 3206.420000 ;
+ RECT 690.420000 3211.380000 691.520000 3211.860000 ;
+ RECT 690.420000 3216.820000 691.520000 3217.300000 ;
+ RECT 690.420000 3222.260000 691.520000 3222.740000 ;
+ RECT 641.590000 3244.020000 642.590000 3244.500000 ;
+ RECT 645.255000 3244.020000 646.520000 3244.500000 ;
+ RECT 641.590000 3238.580000 642.590000 3239.060000 ;
+ RECT 645.255000 3238.580000 646.520000 3239.060000 ;
+ RECT 641.590000 3233.140000 642.590000 3233.620000 ;
+ RECT 645.255000 3233.140000 646.520000 3233.620000 ;
+ RECT 641.590000 3227.700000 642.590000 3228.180000 ;
+ RECT 645.255000 3227.700000 646.520000 3228.180000 ;
+ RECT 641.590000 3222.260000 642.590000 3222.740000 ;
+ RECT 645.255000 3222.260000 646.520000 3222.740000 ;
+ RECT 641.590000 3216.820000 642.590000 3217.300000 ;
+ RECT 645.255000 3216.820000 646.520000 3217.300000 ;
+ RECT 641.590000 3205.940000 642.590000 3206.420000 ;
+ RECT 645.255000 3205.940000 646.520000 3206.420000 ;
+ RECT 641.590000 3211.380000 642.590000 3211.860000 ;
+ RECT 645.255000 3211.380000 646.520000 3211.860000 ;
+ RECT 641.590000 3200.500000 642.590000 3200.980000 ;
+ RECT 645.255000 3200.500000 646.520000 3200.980000 ;
+ RECT 735.420000 3178.740000 736.520000 3179.220000 ;
+ RECT 735.420000 3184.180000 736.520000 3184.660000 ;
+ RECT 735.420000 3189.620000 736.520000 3190.100000 ;
+ RECT 735.420000 3195.060000 736.520000 3195.540000 ;
+ RECT 690.420000 3178.740000 691.520000 3179.220000 ;
+ RECT 690.420000 3184.180000 691.520000 3184.660000 ;
+ RECT 690.420000 3189.620000 691.520000 3190.100000 ;
+ RECT 690.420000 3195.060000 691.520000 3195.540000 ;
+ RECT 735.420000 3156.980000 736.520000 3157.460000 ;
+ RECT 735.420000 3162.420000 736.520000 3162.900000 ;
+ RECT 735.420000 3167.860000 736.520000 3168.340000 ;
+ RECT 735.420000 3173.300000 736.520000 3173.780000 ;
+ RECT 690.420000 3156.980000 691.520000 3157.460000 ;
+ RECT 690.420000 3162.420000 691.520000 3162.900000 ;
+ RECT 690.420000 3167.860000 691.520000 3168.340000 ;
+ RECT 690.420000 3173.300000 691.520000 3173.780000 ;
+ RECT 641.590000 3195.060000 642.590000 3195.540000 ;
+ RECT 645.255000 3195.060000 646.520000 3195.540000 ;
+ RECT 641.590000 3189.620000 642.590000 3190.100000 ;
+ RECT 645.255000 3189.620000 646.520000 3190.100000 ;
+ RECT 641.590000 3184.180000 642.590000 3184.660000 ;
+ RECT 645.255000 3184.180000 646.520000 3184.660000 ;
+ RECT 641.590000 3178.740000 642.590000 3179.220000 ;
+ RECT 645.255000 3178.740000 646.520000 3179.220000 ;
+ RECT 641.590000 3173.300000 642.590000 3173.780000 ;
+ RECT 645.255000 3173.300000 646.520000 3173.780000 ;
+ RECT 641.590000 3162.420000 642.590000 3162.900000 ;
+ RECT 645.255000 3162.420000 646.520000 3162.900000 ;
+ RECT 641.590000 3167.860000 642.590000 3168.340000 ;
+ RECT 645.255000 3167.860000 646.520000 3168.340000 ;
+ RECT 641.590000 3156.980000 642.590000 3157.460000 ;
+ RECT 645.255000 3156.980000 646.520000 3157.460000 ;
+ RECT 780.420000 3249.460000 781.520000 3249.940000 ;
+ RECT 825.420000 3249.460000 826.520000 3249.940000 ;
+ RECT 838.230000 3249.460000 839.230000 3249.940000 ;
+ RECT 690.420000 3249.460000 691.520000 3249.940000 ;
+ RECT 735.420000 3249.460000 736.520000 3249.940000 ;
+ RECT 641.590000 3249.460000 642.590000 3249.940000 ;
+ RECT 645.255000 3249.460000 646.520000 3249.940000 ;
+ RECT 640.360000 3346.220000 840.460000 3347.220000 ;
+ RECT 640.360000 3150.650000 840.460000 3151.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 3149.400000 642.590000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 3348.660000 642.590000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 3149.400000 839.230000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 3348.660000 839.230000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 3150.650000 641.360000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 3150.650000 840.460000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 3346.220000 641.360000 3347.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 3346.220000 840.460000 3347.220000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 3141.680000 646.520000 3142.160000 ;
+ RECT 645.255000 3130.800000 646.520000 3131.280000 ;
+ RECT 645.255000 3136.240000 646.520000 3136.720000 ;
+ RECT 645.255000 3125.360000 646.520000 3125.840000 ;
+ RECT 645.255000 3119.920000 646.520000 3120.400000 ;
+ RECT 645.255000 3114.480000 646.520000 3114.960000 ;
+ RECT 645.255000 3109.040000 646.520000 3109.520000 ;
+ RECT 645.255000 3103.600000 646.520000 3104.080000 ;
+ RECT 645.255000 3098.160000 646.520000 3098.640000 ;
+ RECT 645.255000 3087.280000 646.520000 3087.760000 ;
+ RECT 645.255000 3092.720000 646.520000 3093.200000 ;
+ RECT 645.255000 3081.840000 646.520000 3082.320000 ;
+ RECT 645.255000 3076.400000 646.520000 3076.880000 ;
+ RECT 645.255000 3070.960000 646.520000 3071.440000 ;
+ RECT 645.255000 3065.520000 646.520000 3066.000000 ;
+ RECT 645.255000 3060.080000 646.520000 3060.560000 ;
+ RECT 645.255000 3054.640000 646.520000 3055.120000 ;
+ RECT 645.255000 3043.760000 646.520000 3044.240000 ;
+ RECT 645.255000 3038.320000 646.520000 3038.800000 ;
+ RECT 645.255000 3032.880000 646.520000 3033.360000 ;
+ RECT 645.255000 3027.440000 646.520000 3027.920000 ;
+ RECT 645.255000 3022.000000 646.520000 3022.480000 ;
+ RECT 645.255000 3016.560000 646.520000 3017.040000 ;
+ RECT 645.255000 3005.680000 646.520000 3006.160000 ;
+ RECT 645.255000 3011.120000 646.520000 3011.600000 ;
+ RECT 645.255000 3000.240000 646.520000 3000.720000 ;
+ RECT 645.255000 2994.800000 646.520000 2995.280000 ;
+ RECT 645.255000 2989.360000 646.520000 2989.840000 ;
+ RECT 645.255000 2983.920000 646.520000 2984.400000 ;
+ RECT 645.255000 2978.480000 646.520000 2978.960000 ;
+ RECT 645.255000 2973.040000 646.520000 2973.520000 ;
+ RECT 645.255000 2962.160000 646.520000 2962.640000 ;
+ RECT 645.255000 2967.600000 646.520000 2968.080000 ;
+ RECT 645.255000 2956.720000 646.520000 2957.200000 ;
+ RECT 645.255000 3049.200000 646.520000 3049.680000 ;
+ RECT 825.420000 2950.390000 826.520000 3146.960000 ;
+ RECT 780.420000 2950.390000 781.520000 3146.960000 ;
+ RECT 838.230000 2949.140000 839.230000 3149.400000 ;
+ RECT 735.420000 2950.390000 736.520000 3146.960000 ;
+ RECT 690.420000 2950.390000 691.520000 3146.960000 ;
+ RECT 645.420000 2950.390000 646.520000 3146.960000 ;
+ RECT 641.590000 2949.140000 642.590000 3149.400000 ;
+ LAYER met3 ;
+ RECT 825.420000 3141.680000 826.520000 3142.160000 ;
+ RECT 838.230000 3141.680000 839.230000 3142.160000 ;
+ RECT 838.230000 3130.800000 839.230000 3131.280000 ;
+ RECT 838.230000 3125.360000 839.230000 3125.840000 ;
+ RECT 838.230000 3136.240000 839.230000 3136.720000 ;
+ RECT 825.420000 3136.240000 826.520000 3136.720000 ;
+ RECT 825.420000 3130.800000 826.520000 3131.280000 ;
+ RECT 825.420000 3125.360000 826.520000 3125.840000 ;
+ RECT 825.420000 3114.480000 826.520000 3114.960000 ;
+ RECT 825.420000 3119.920000 826.520000 3120.400000 ;
+ RECT 838.230000 3114.480000 839.230000 3114.960000 ;
+ RECT 838.230000 3119.920000 839.230000 3120.400000 ;
+ RECT 825.420000 3103.600000 826.520000 3104.080000 ;
+ RECT 825.420000 3109.040000 826.520000 3109.520000 ;
+ RECT 838.230000 3103.600000 839.230000 3104.080000 ;
+ RECT 838.230000 3109.040000 839.230000 3109.520000 ;
+ RECT 780.420000 3125.360000 781.520000 3125.840000 ;
+ RECT 780.420000 3130.800000 781.520000 3131.280000 ;
+ RECT 780.420000 3136.240000 781.520000 3136.720000 ;
+ RECT 780.420000 3141.680000 781.520000 3142.160000 ;
+ RECT 780.420000 3109.040000 781.520000 3109.520000 ;
+ RECT 780.420000 3103.600000 781.520000 3104.080000 ;
+ RECT 780.420000 3114.480000 781.520000 3114.960000 ;
+ RECT 780.420000 3119.920000 781.520000 3120.400000 ;
+ RECT 838.230000 3092.720000 839.230000 3093.200000 ;
+ RECT 838.230000 3087.280000 839.230000 3087.760000 ;
+ RECT 838.230000 3098.160000 839.230000 3098.640000 ;
+ RECT 825.420000 3098.160000 826.520000 3098.640000 ;
+ RECT 825.420000 3092.720000 826.520000 3093.200000 ;
+ RECT 825.420000 3087.280000 826.520000 3087.760000 ;
+ RECT 825.420000 3076.400000 826.520000 3076.880000 ;
+ RECT 825.420000 3081.840000 826.520000 3082.320000 ;
+ RECT 838.230000 3076.400000 839.230000 3076.880000 ;
+ RECT 838.230000 3081.840000 839.230000 3082.320000 ;
+ RECT 838.230000 3065.520000 839.230000 3066.000000 ;
+ RECT 838.230000 3070.960000 839.230000 3071.440000 ;
+ RECT 825.420000 3070.960000 826.520000 3071.440000 ;
+ RECT 825.420000 3065.520000 826.520000 3066.000000 ;
+ RECT 825.420000 3054.640000 826.520000 3055.120000 ;
+ RECT 825.420000 3060.080000 826.520000 3060.560000 ;
+ RECT 838.230000 3054.640000 839.230000 3055.120000 ;
+ RECT 838.230000 3060.080000 839.230000 3060.560000 ;
+ RECT 780.420000 3076.400000 781.520000 3076.880000 ;
+ RECT 780.420000 3081.840000 781.520000 3082.320000 ;
+ RECT 780.420000 3087.280000 781.520000 3087.760000 ;
+ RECT 780.420000 3092.720000 781.520000 3093.200000 ;
+ RECT 780.420000 3098.160000 781.520000 3098.640000 ;
+ RECT 780.420000 3054.640000 781.520000 3055.120000 ;
+ RECT 780.420000 3060.080000 781.520000 3060.560000 ;
+ RECT 780.420000 3065.520000 781.520000 3066.000000 ;
+ RECT 780.420000 3070.960000 781.520000 3071.440000 ;
+ RECT 735.420000 3130.800000 736.520000 3131.280000 ;
+ RECT 735.420000 3125.360000 736.520000 3125.840000 ;
+ RECT 735.420000 3136.240000 736.520000 3136.720000 ;
+ RECT 735.420000 3141.680000 736.520000 3142.160000 ;
+ RECT 690.420000 3125.360000 691.520000 3125.840000 ;
+ RECT 690.420000 3130.800000 691.520000 3131.280000 ;
+ RECT 690.420000 3136.240000 691.520000 3136.720000 ;
+ RECT 690.420000 3141.680000 691.520000 3142.160000 ;
+ RECT 735.420000 3103.600000 736.520000 3104.080000 ;
+ RECT 735.420000 3109.040000 736.520000 3109.520000 ;
+ RECT 735.420000 3114.480000 736.520000 3114.960000 ;
+ RECT 735.420000 3119.920000 736.520000 3120.400000 ;
+ RECT 690.420000 3103.600000 691.520000 3104.080000 ;
+ RECT 690.420000 3109.040000 691.520000 3109.520000 ;
+ RECT 690.420000 3114.480000 691.520000 3114.960000 ;
+ RECT 690.420000 3119.920000 691.520000 3120.400000 ;
+ RECT 641.590000 3141.680000 642.590000 3142.160000 ;
+ RECT 645.255000 3141.680000 646.520000 3142.160000 ;
+ RECT 641.590000 3130.800000 642.590000 3131.280000 ;
+ RECT 645.255000 3130.800000 646.520000 3131.280000 ;
+ RECT 641.590000 3136.240000 642.590000 3136.720000 ;
+ RECT 645.255000 3136.240000 646.520000 3136.720000 ;
+ RECT 641.590000 3125.360000 642.590000 3125.840000 ;
+ RECT 645.255000 3125.360000 646.520000 3125.840000 ;
+ RECT 641.590000 3119.920000 642.590000 3120.400000 ;
+ RECT 645.255000 3119.920000 646.520000 3120.400000 ;
+ RECT 641.590000 3114.480000 642.590000 3114.960000 ;
+ RECT 645.255000 3114.480000 646.520000 3114.960000 ;
+ RECT 641.590000 3109.040000 642.590000 3109.520000 ;
+ RECT 645.255000 3109.040000 646.520000 3109.520000 ;
+ RECT 641.590000 3103.600000 642.590000 3104.080000 ;
+ RECT 645.255000 3103.600000 646.520000 3104.080000 ;
+ RECT 735.420000 3076.400000 736.520000 3076.880000 ;
+ RECT 735.420000 3081.840000 736.520000 3082.320000 ;
+ RECT 735.420000 3087.280000 736.520000 3087.760000 ;
+ RECT 735.420000 3092.720000 736.520000 3093.200000 ;
+ RECT 735.420000 3098.160000 736.520000 3098.640000 ;
+ RECT 690.420000 3076.400000 691.520000 3076.880000 ;
+ RECT 690.420000 3081.840000 691.520000 3082.320000 ;
+ RECT 690.420000 3087.280000 691.520000 3087.760000 ;
+ RECT 690.420000 3092.720000 691.520000 3093.200000 ;
+ RECT 690.420000 3098.160000 691.520000 3098.640000 ;
+ RECT 735.420000 3054.640000 736.520000 3055.120000 ;
+ RECT 735.420000 3060.080000 736.520000 3060.560000 ;
+ RECT 735.420000 3065.520000 736.520000 3066.000000 ;
+ RECT 735.420000 3070.960000 736.520000 3071.440000 ;
+ RECT 690.420000 3054.640000 691.520000 3055.120000 ;
+ RECT 690.420000 3060.080000 691.520000 3060.560000 ;
+ RECT 690.420000 3065.520000 691.520000 3066.000000 ;
+ RECT 690.420000 3070.960000 691.520000 3071.440000 ;
+ RECT 641.590000 3098.160000 642.590000 3098.640000 ;
+ RECT 645.255000 3098.160000 646.520000 3098.640000 ;
+ RECT 641.590000 3087.280000 642.590000 3087.760000 ;
+ RECT 645.255000 3087.280000 646.520000 3087.760000 ;
+ RECT 641.590000 3092.720000 642.590000 3093.200000 ;
+ RECT 645.255000 3092.720000 646.520000 3093.200000 ;
+ RECT 641.590000 3081.840000 642.590000 3082.320000 ;
+ RECT 645.255000 3081.840000 646.520000 3082.320000 ;
+ RECT 641.590000 3076.400000 642.590000 3076.880000 ;
+ RECT 645.255000 3076.400000 646.520000 3076.880000 ;
+ RECT 641.590000 3070.960000 642.590000 3071.440000 ;
+ RECT 645.255000 3070.960000 646.520000 3071.440000 ;
+ RECT 641.590000 3065.520000 642.590000 3066.000000 ;
+ RECT 645.255000 3065.520000 646.520000 3066.000000 ;
+ RECT 641.590000 3060.080000 642.590000 3060.560000 ;
+ RECT 645.255000 3060.080000 646.520000 3060.560000 ;
+ RECT 641.590000 3054.640000 642.590000 3055.120000 ;
+ RECT 645.255000 3054.640000 646.520000 3055.120000 ;
+ RECT 825.420000 3038.320000 826.520000 3038.800000 ;
+ RECT 825.420000 3043.760000 826.520000 3044.240000 ;
+ RECT 838.230000 3038.320000 839.230000 3038.800000 ;
+ RECT 838.230000 3043.760000 839.230000 3044.240000 ;
+ RECT 838.230000 3027.440000 839.230000 3027.920000 ;
+ RECT 838.230000 3032.880000 839.230000 3033.360000 ;
+ RECT 825.420000 3032.880000 826.520000 3033.360000 ;
+ RECT 825.420000 3027.440000 826.520000 3027.920000 ;
+ RECT 825.420000 3016.560000 826.520000 3017.040000 ;
+ RECT 825.420000 3022.000000 826.520000 3022.480000 ;
+ RECT 838.230000 3016.560000 839.230000 3017.040000 ;
+ RECT 838.230000 3022.000000 839.230000 3022.480000 ;
+ RECT 838.230000 3005.680000 839.230000 3006.160000 ;
+ RECT 838.230000 3000.240000 839.230000 3000.720000 ;
+ RECT 838.230000 3011.120000 839.230000 3011.600000 ;
+ RECT 825.420000 3011.120000 826.520000 3011.600000 ;
+ RECT 825.420000 3005.680000 826.520000 3006.160000 ;
+ RECT 825.420000 3000.240000 826.520000 3000.720000 ;
+ RECT 780.420000 3027.440000 781.520000 3027.920000 ;
+ RECT 780.420000 3032.880000 781.520000 3033.360000 ;
+ RECT 780.420000 3038.320000 781.520000 3038.800000 ;
+ RECT 780.420000 3043.760000 781.520000 3044.240000 ;
+ RECT 780.420000 3000.240000 781.520000 3000.720000 ;
+ RECT 780.420000 3005.680000 781.520000 3006.160000 ;
+ RECT 780.420000 3011.120000 781.520000 3011.600000 ;
+ RECT 780.420000 3016.560000 781.520000 3017.040000 ;
+ RECT 780.420000 3022.000000 781.520000 3022.480000 ;
+ RECT 825.420000 2989.360000 826.520000 2989.840000 ;
+ RECT 825.420000 2994.800000 826.520000 2995.280000 ;
+ RECT 838.230000 2989.360000 839.230000 2989.840000 ;
+ RECT 838.230000 2994.800000 839.230000 2995.280000 ;
+ RECT 825.420000 2978.480000 826.520000 2978.960000 ;
+ RECT 825.420000 2983.920000 826.520000 2984.400000 ;
+ RECT 838.230000 2978.480000 839.230000 2978.960000 ;
+ RECT 838.230000 2983.920000 839.230000 2984.400000 ;
+ RECT 838.230000 2967.600000 839.230000 2968.080000 ;
+ RECT 838.230000 2962.160000 839.230000 2962.640000 ;
+ RECT 838.230000 2973.040000 839.230000 2973.520000 ;
+ RECT 825.420000 2973.040000 826.520000 2973.520000 ;
+ RECT 825.420000 2967.600000 826.520000 2968.080000 ;
+ RECT 825.420000 2962.160000 826.520000 2962.640000 ;
+ RECT 825.420000 2956.720000 826.520000 2957.200000 ;
+ RECT 838.230000 2956.720000 839.230000 2957.200000 ;
+ RECT 780.420000 2978.480000 781.520000 2978.960000 ;
+ RECT 780.420000 2983.920000 781.520000 2984.400000 ;
+ RECT 780.420000 2989.360000 781.520000 2989.840000 ;
+ RECT 780.420000 2994.800000 781.520000 2995.280000 ;
+ RECT 780.420000 2956.720000 781.520000 2957.200000 ;
+ RECT 780.420000 2962.160000 781.520000 2962.640000 ;
+ RECT 780.420000 2967.600000 781.520000 2968.080000 ;
+ RECT 780.420000 2973.040000 781.520000 2973.520000 ;
+ RECT 735.420000 3027.440000 736.520000 3027.920000 ;
+ RECT 735.420000 3032.880000 736.520000 3033.360000 ;
+ RECT 735.420000 3038.320000 736.520000 3038.800000 ;
+ RECT 735.420000 3043.760000 736.520000 3044.240000 ;
+ RECT 690.420000 3027.440000 691.520000 3027.920000 ;
+ RECT 690.420000 3032.880000 691.520000 3033.360000 ;
+ RECT 690.420000 3038.320000 691.520000 3038.800000 ;
+ RECT 690.420000 3043.760000 691.520000 3044.240000 ;
+ RECT 735.420000 3000.240000 736.520000 3000.720000 ;
+ RECT 735.420000 3005.680000 736.520000 3006.160000 ;
+ RECT 735.420000 3011.120000 736.520000 3011.600000 ;
+ RECT 735.420000 3016.560000 736.520000 3017.040000 ;
+ RECT 735.420000 3022.000000 736.520000 3022.480000 ;
+ RECT 690.420000 3000.240000 691.520000 3000.720000 ;
+ RECT 690.420000 3005.680000 691.520000 3006.160000 ;
+ RECT 690.420000 3011.120000 691.520000 3011.600000 ;
+ RECT 690.420000 3016.560000 691.520000 3017.040000 ;
+ RECT 690.420000 3022.000000 691.520000 3022.480000 ;
+ RECT 641.590000 3043.760000 642.590000 3044.240000 ;
+ RECT 645.255000 3043.760000 646.520000 3044.240000 ;
+ RECT 641.590000 3038.320000 642.590000 3038.800000 ;
+ RECT 645.255000 3038.320000 646.520000 3038.800000 ;
+ RECT 641.590000 3032.880000 642.590000 3033.360000 ;
+ RECT 645.255000 3032.880000 646.520000 3033.360000 ;
+ RECT 641.590000 3027.440000 642.590000 3027.920000 ;
+ RECT 645.255000 3027.440000 646.520000 3027.920000 ;
+ RECT 641.590000 3022.000000 642.590000 3022.480000 ;
+ RECT 645.255000 3022.000000 646.520000 3022.480000 ;
+ RECT 641.590000 3016.560000 642.590000 3017.040000 ;
+ RECT 645.255000 3016.560000 646.520000 3017.040000 ;
+ RECT 641.590000 3005.680000 642.590000 3006.160000 ;
+ RECT 645.255000 3005.680000 646.520000 3006.160000 ;
+ RECT 641.590000 3011.120000 642.590000 3011.600000 ;
+ RECT 645.255000 3011.120000 646.520000 3011.600000 ;
+ RECT 641.590000 3000.240000 642.590000 3000.720000 ;
+ RECT 645.255000 3000.240000 646.520000 3000.720000 ;
+ RECT 735.420000 2978.480000 736.520000 2978.960000 ;
+ RECT 735.420000 2983.920000 736.520000 2984.400000 ;
+ RECT 735.420000 2989.360000 736.520000 2989.840000 ;
+ RECT 735.420000 2994.800000 736.520000 2995.280000 ;
+ RECT 690.420000 2978.480000 691.520000 2978.960000 ;
+ RECT 690.420000 2983.920000 691.520000 2984.400000 ;
+ RECT 690.420000 2989.360000 691.520000 2989.840000 ;
+ RECT 690.420000 2994.800000 691.520000 2995.280000 ;
+ RECT 735.420000 2956.720000 736.520000 2957.200000 ;
+ RECT 735.420000 2962.160000 736.520000 2962.640000 ;
+ RECT 735.420000 2967.600000 736.520000 2968.080000 ;
+ RECT 735.420000 2973.040000 736.520000 2973.520000 ;
+ RECT 690.420000 2956.720000 691.520000 2957.200000 ;
+ RECT 690.420000 2962.160000 691.520000 2962.640000 ;
+ RECT 690.420000 2967.600000 691.520000 2968.080000 ;
+ RECT 690.420000 2973.040000 691.520000 2973.520000 ;
+ RECT 641.590000 2994.800000 642.590000 2995.280000 ;
+ RECT 645.255000 2994.800000 646.520000 2995.280000 ;
+ RECT 641.590000 2989.360000 642.590000 2989.840000 ;
+ RECT 645.255000 2989.360000 646.520000 2989.840000 ;
+ RECT 641.590000 2983.920000 642.590000 2984.400000 ;
+ RECT 645.255000 2983.920000 646.520000 2984.400000 ;
+ RECT 641.590000 2978.480000 642.590000 2978.960000 ;
+ RECT 645.255000 2978.480000 646.520000 2978.960000 ;
+ RECT 641.590000 2973.040000 642.590000 2973.520000 ;
+ RECT 645.255000 2973.040000 646.520000 2973.520000 ;
+ RECT 641.590000 2962.160000 642.590000 2962.640000 ;
+ RECT 645.255000 2962.160000 646.520000 2962.640000 ;
+ RECT 641.590000 2967.600000 642.590000 2968.080000 ;
+ RECT 645.255000 2967.600000 646.520000 2968.080000 ;
+ RECT 641.590000 2956.720000 642.590000 2957.200000 ;
+ RECT 645.255000 2956.720000 646.520000 2957.200000 ;
+ RECT 780.420000 3049.200000 781.520000 3049.680000 ;
+ RECT 825.420000 3049.200000 826.520000 3049.680000 ;
+ RECT 838.230000 3049.200000 839.230000 3049.680000 ;
+ RECT 690.420000 3049.200000 691.520000 3049.680000 ;
+ RECT 735.420000 3049.200000 736.520000 3049.680000 ;
+ RECT 641.590000 3049.200000 642.590000 3049.680000 ;
+ RECT 645.255000 3049.200000 646.520000 3049.680000 ;
+ RECT 640.360000 3145.960000 840.460000 3146.960000 ;
+ RECT 640.360000 2950.390000 840.460000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 2949.140000 642.590000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 3148.400000 642.590000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 2949.140000 839.230000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 3148.400000 839.230000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2950.390000 641.360000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2950.390000 840.460000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 3145.960000 641.360000 3146.960000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 3145.960000 840.460000 3146.960000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 2941.420000 646.520000 2941.900000 ;
+ RECT 645.255000 2930.540000 646.520000 2931.020000 ;
+ RECT 645.255000 2935.980000 646.520000 2936.460000 ;
+ RECT 645.255000 2925.100000 646.520000 2925.580000 ;
+ RECT 645.255000 2919.660000 646.520000 2920.140000 ;
+ RECT 645.255000 2914.220000 646.520000 2914.700000 ;
+ RECT 645.255000 2908.780000 646.520000 2909.260000 ;
+ RECT 645.255000 2903.340000 646.520000 2903.820000 ;
+ RECT 645.255000 2897.900000 646.520000 2898.380000 ;
+ RECT 645.255000 2887.020000 646.520000 2887.500000 ;
+ RECT 645.255000 2892.460000 646.520000 2892.940000 ;
+ RECT 645.255000 2881.580000 646.520000 2882.060000 ;
+ RECT 645.255000 2876.140000 646.520000 2876.620000 ;
+ RECT 645.255000 2870.700000 646.520000 2871.180000 ;
+ RECT 645.255000 2865.260000 646.520000 2865.740000 ;
+ RECT 645.255000 2859.820000 646.520000 2860.300000 ;
+ RECT 645.255000 2854.380000 646.520000 2854.860000 ;
+ RECT 645.255000 2843.500000 646.520000 2843.980000 ;
+ RECT 645.255000 2838.060000 646.520000 2838.540000 ;
+ RECT 645.255000 2832.620000 646.520000 2833.100000 ;
+ RECT 645.255000 2827.180000 646.520000 2827.660000 ;
+ RECT 645.255000 2821.740000 646.520000 2822.220000 ;
+ RECT 645.255000 2816.300000 646.520000 2816.780000 ;
+ RECT 645.255000 2805.420000 646.520000 2805.900000 ;
+ RECT 645.255000 2810.860000 646.520000 2811.340000 ;
+ RECT 645.255000 2799.980000 646.520000 2800.460000 ;
+ RECT 645.255000 2794.540000 646.520000 2795.020000 ;
+ RECT 645.255000 2789.100000 646.520000 2789.580000 ;
+ RECT 645.255000 2783.660000 646.520000 2784.140000 ;
+ RECT 645.255000 2778.220000 646.520000 2778.700000 ;
+ RECT 645.255000 2772.780000 646.520000 2773.260000 ;
+ RECT 645.255000 2761.900000 646.520000 2762.380000 ;
+ RECT 645.255000 2767.340000 646.520000 2767.820000 ;
+ RECT 645.255000 2756.460000 646.520000 2756.940000 ;
+ RECT 645.255000 2848.940000 646.520000 2849.420000 ;
+ RECT 825.420000 2750.130000 826.520000 2946.700000 ;
+ RECT 780.420000 2750.130000 781.520000 2946.700000 ;
+ RECT 838.230000 2748.880000 839.230000 2949.140000 ;
+ RECT 735.420000 2750.130000 736.520000 2946.700000 ;
+ RECT 690.420000 2750.130000 691.520000 2946.700000 ;
+ RECT 645.420000 2750.130000 646.520000 2946.700000 ;
+ RECT 641.590000 2748.880000 642.590000 2949.140000 ;
+ LAYER met3 ;
+ RECT 825.420000 2941.420000 826.520000 2941.900000 ;
+ RECT 838.230000 2941.420000 839.230000 2941.900000 ;
+ RECT 838.230000 2930.540000 839.230000 2931.020000 ;
+ RECT 838.230000 2925.100000 839.230000 2925.580000 ;
+ RECT 838.230000 2935.980000 839.230000 2936.460000 ;
+ RECT 825.420000 2935.980000 826.520000 2936.460000 ;
+ RECT 825.420000 2930.540000 826.520000 2931.020000 ;
+ RECT 825.420000 2925.100000 826.520000 2925.580000 ;
+ RECT 825.420000 2914.220000 826.520000 2914.700000 ;
+ RECT 825.420000 2919.660000 826.520000 2920.140000 ;
+ RECT 838.230000 2914.220000 839.230000 2914.700000 ;
+ RECT 838.230000 2919.660000 839.230000 2920.140000 ;
+ RECT 825.420000 2903.340000 826.520000 2903.820000 ;
+ RECT 825.420000 2908.780000 826.520000 2909.260000 ;
+ RECT 838.230000 2903.340000 839.230000 2903.820000 ;
+ RECT 838.230000 2908.780000 839.230000 2909.260000 ;
+ RECT 780.420000 2925.100000 781.520000 2925.580000 ;
+ RECT 780.420000 2930.540000 781.520000 2931.020000 ;
+ RECT 780.420000 2935.980000 781.520000 2936.460000 ;
+ RECT 780.420000 2941.420000 781.520000 2941.900000 ;
+ RECT 780.420000 2908.780000 781.520000 2909.260000 ;
+ RECT 780.420000 2903.340000 781.520000 2903.820000 ;
+ RECT 780.420000 2914.220000 781.520000 2914.700000 ;
+ RECT 780.420000 2919.660000 781.520000 2920.140000 ;
+ RECT 838.230000 2892.460000 839.230000 2892.940000 ;
+ RECT 838.230000 2887.020000 839.230000 2887.500000 ;
+ RECT 838.230000 2897.900000 839.230000 2898.380000 ;
+ RECT 825.420000 2897.900000 826.520000 2898.380000 ;
+ RECT 825.420000 2892.460000 826.520000 2892.940000 ;
+ RECT 825.420000 2887.020000 826.520000 2887.500000 ;
+ RECT 825.420000 2876.140000 826.520000 2876.620000 ;
+ RECT 825.420000 2881.580000 826.520000 2882.060000 ;
+ RECT 838.230000 2876.140000 839.230000 2876.620000 ;
+ RECT 838.230000 2881.580000 839.230000 2882.060000 ;
+ RECT 838.230000 2865.260000 839.230000 2865.740000 ;
+ RECT 838.230000 2870.700000 839.230000 2871.180000 ;
+ RECT 825.420000 2870.700000 826.520000 2871.180000 ;
+ RECT 825.420000 2865.260000 826.520000 2865.740000 ;
+ RECT 825.420000 2854.380000 826.520000 2854.860000 ;
+ RECT 825.420000 2859.820000 826.520000 2860.300000 ;
+ RECT 838.230000 2854.380000 839.230000 2854.860000 ;
+ RECT 838.230000 2859.820000 839.230000 2860.300000 ;
+ RECT 780.420000 2876.140000 781.520000 2876.620000 ;
+ RECT 780.420000 2881.580000 781.520000 2882.060000 ;
+ RECT 780.420000 2887.020000 781.520000 2887.500000 ;
+ RECT 780.420000 2892.460000 781.520000 2892.940000 ;
+ RECT 780.420000 2897.900000 781.520000 2898.380000 ;
+ RECT 780.420000 2854.380000 781.520000 2854.860000 ;
+ RECT 780.420000 2859.820000 781.520000 2860.300000 ;
+ RECT 780.420000 2865.260000 781.520000 2865.740000 ;
+ RECT 780.420000 2870.700000 781.520000 2871.180000 ;
+ RECT 735.420000 2930.540000 736.520000 2931.020000 ;
+ RECT 735.420000 2925.100000 736.520000 2925.580000 ;
+ RECT 735.420000 2935.980000 736.520000 2936.460000 ;
+ RECT 735.420000 2941.420000 736.520000 2941.900000 ;
+ RECT 690.420000 2925.100000 691.520000 2925.580000 ;
+ RECT 690.420000 2930.540000 691.520000 2931.020000 ;
+ RECT 690.420000 2935.980000 691.520000 2936.460000 ;
+ RECT 690.420000 2941.420000 691.520000 2941.900000 ;
+ RECT 735.420000 2903.340000 736.520000 2903.820000 ;
+ RECT 735.420000 2908.780000 736.520000 2909.260000 ;
+ RECT 735.420000 2914.220000 736.520000 2914.700000 ;
+ RECT 735.420000 2919.660000 736.520000 2920.140000 ;
+ RECT 690.420000 2903.340000 691.520000 2903.820000 ;
+ RECT 690.420000 2908.780000 691.520000 2909.260000 ;
+ RECT 690.420000 2914.220000 691.520000 2914.700000 ;
+ RECT 690.420000 2919.660000 691.520000 2920.140000 ;
+ RECT 641.590000 2941.420000 642.590000 2941.900000 ;
+ RECT 645.255000 2941.420000 646.520000 2941.900000 ;
+ RECT 641.590000 2930.540000 642.590000 2931.020000 ;
+ RECT 645.255000 2930.540000 646.520000 2931.020000 ;
+ RECT 641.590000 2935.980000 642.590000 2936.460000 ;
+ RECT 645.255000 2935.980000 646.520000 2936.460000 ;
+ RECT 641.590000 2925.100000 642.590000 2925.580000 ;
+ RECT 645.255000 2925.100000 646.520000 2925.580000 ;
+ RECT 641.590000 2919.660000 642.590000 2920.140000 ;
+ RECT 645.255000 2919.660000 646.520000 2920.140000 ;
+ RECT 641.590000 2914.220000 642.590000 2914.700000 ;
+ RECT 645.255000 2914.220000 646.520000 2914.700000 ;
+ RECT 641.590000 2908.780000 642.590000 2909.260000 ;
+ RECT 645.255000 2908.780000 646.520000 2909.260000 ;
+ RECT 641.590000 2903.340000 642.590000 2903.820000 ;
+ RECT 645.255000 2903.340000 646.520000 2903.820000 ;
+ RECT 735.420000 2876.140000 736.520000 2876.620000 ;
+ RECT 735.420000 2881.580000 736.520000 2882.060000 ;
+ RECT 735.420000 2887.020000 736.520000 2887.500000 ;
+ RECT 735.420000 2892.460000 736.520000 2892.940000 ;
+ RECT 735.420000 2897.900000 736.520000 2898.380000 ;
+ RECT 690.420000 2876.140000 691.520000 2876.620000 ;
+ RECT 690.420000 2881.580000 691.520000 2882.060000 ;
+ RECT 690.420000 2887.020000 691.520000 2887.500000 ;
+ RECT 690.420000 2892.460000 691.520000 2892.940000 ;
+ RECT 690.420000 2897.900000 691.520000 2898.380000 ;
+ RECT 735.420000 2854.380000 736.520000 2854.860000 ;
+ RECT 735.420000 2859.820000 736.520000 2860.300000 ;
+ RECT 735.420000 2865.260000 736.520000 2865.740000 ;
+ RECT 735.420000 2870.700000 736.520000 2871.180000 ;
+ RECT 690.420000 2854.380000 691.520000 2854.860000 ;
+ RECT 690.420000 2859.820000 691.520000 2860.300000 ;
+ RECT 690.420000 2865.260000 691.520000 2865.740000 ;
+ RECT 690.420000 2870.700000 691.520000 2871.180000 ;
+ RECT 641.590000 2897.900000 642.590000 2898.380000 ;
+ RECT 645.255000 2897.900000 646.520000 2898.380000 ;
+ RECT 641.590000 2887.020000 642.590000 2887.500000 ;
+ RECT 645.255000 2887.020000 646.520000 2887.500000 ;
+ RECT 641.590000 2892.460000 642.590000 2892.940000 ;
+ RECT 645.255000 2892.460000 646.520000 2892.940000 ;
+ RECT 641.590000 2881.580000 642.590000 2882.060000 ;
+ RECT 645.255000 2881.580000 646.520000 2882.060000 ;
+ RECT 641.590000 2876.140000 642.590000 2876.620000 ;
+ RECT 645.255000 2876.140000 646.520000 2876.620000 ;
+ RECT 641.590000 2870.700000 642.590000 2871.180000 ;
+ RECT 645.255000 2870.700000 646.520000 2871.180000 ;
+ RECT 641.590000 2865.260000 642.590000 2865.740000 ;
+ RECT 645.255000 2865.260000 646.520000 2865.740000 ;
+ RECT 641.590000 2859.820000 642.590000 2860.300000 ;
+ RECT 645.255000 2859.820000 646.520000 2860.300000 ;
+ RECT 641.590000 2854.380000 642.590000 2854.860000 ;
+ RECT 645.255000 2854.380000 646.520000 2854.860000 ;
+ RECT 825.420000 2838.060000 826.520000 2838.540000 ;
+ RECT 825.420000 2843.500000 826.520000 2843.980000 ;
+ RECT 838.230000 2838.060000 839.230000 2838.540000 ;
+ RECT 838.230000 2843.500000 839.230000 2843.980000 ;
+ RECT 838.230000 2827.180000 839.230000 2827.660000 ;
+ RECT 838.230000 2832.620000 839.230000 2833.100000 ;
+ RECT 825.420000 2832.620000 826.520000 2833.100000 ;
+ RECT 825.420000 2827.180000 826.520000 2827.660000 ;
+ RECT 825.420000 2816.300000 826.520000 2816.780000 ;
+ RECT 825.420000 2821.740000 826.520000 2822.220000 ;
+ RECT 838.230000 2816.300000 839.230000 2816.780000 ;
+ RECT 838.230000 2821.740000 839.230000 2822.220000 ;
+ RECT 838.230000 2805.420000 839.230000 2805.900000 ;
+ RECT 838.230000 2799.980000 839.230000 2800.460000 ;
+ RECT 838.230000 2810.860000 839.230000 2811.340000 ;
+ RECT 825.420000 2810.860000 826.520000 2811.340000 ;
+ RECT 825.420000 2805.420000 826.520000 2805.900000 ;
+ RECT 825.420000 2799.980000 826.520000 2800.460000 ;
+ RECT 780.420000 2827.180000 781.520000 2827.660000 ;
+ RECT 780.420000 2832.620000 781.520000 2833.100000 ;
+ RECT 780.420000 2838.060000 781.520000 2838.540000 ;
+ RECT 780.420000 2843.500000 781.520000 2843.980000 ;
+ RECT 780.420000 2799.980000 781.520000 2800.460000 ;
+ RECT 780.420000 2805.420000 781.520000 2805.900000 ;
+ RECT 780.420000 2810.860000 781.520000 2811.340000 ;
+ RECT 780.420000 2816.300000 781.520000 2816.780000 ;
+ RECT 780.420000 2821.740000 781.520000 2822.220000 ;
+ RECT 825.420000 2789.100000 826.520000 2789.580000 ;
+ RECT 825.420000 2794.540000 826.520000 2795.020000 ;
+ RECT 838.230000 2789.100000 839.230000 2789.580000 ;
+ RECT 838.230000 2794.540000 839.230000 2795.020000 ;
+ RECT 825.420000 2778.220000 826.520000 2778.700000 ;
+ RECT 825.420000 2783.660000 826.520000 2784.140000 ;
+ RECT 838.230000 2778.220000 839.230000 2778.700000 ;
+ RECT 838.230000 2783.660000 839.230000 2784.140000 ;
+ RECT 838.230000 2767.340000 839.230000 2767.820000 ;
+ RECT 838.230000 2761.900000 839.230000 2762.380000 ;
+ RECT 838.230000 2772.780000 839.230000 2773.260000 ;
+ RECT 825.420000 2772.780000 826.520000 2773.260000 ;
+ RECT 825.420000 2767.340000 826.520000 2767.820000 ;
+ RECT 825.420000 2761.900000 826.520000 2762.380000 ;
+ RECT 825.420000 2756.460000 826.520000 2756.940000 ;
+ RECT 838.230000 2756.460000 839.230000 2756.940000 ;
+ RECT 780.420000 2778.220000 781.520000 2778.700000 ;
+ RECT 780.420000 2783.660000 781.520000 2784.140000 ;
+ RECT 780.420000 2789.100000 781.520000 2789.580000 ;
+ RECT 780.420000 2794.540000 781.520000 2795.020000 ;
+ RECT 780.420000 2756.460000 781.520000 2756.940000 ;
+ RECT 780.420000 2761.900000 781.520000 2762.380000 ;
+ RECT 780.420000 2767.340000 781.520000 2767.820000 ;
+ RECT 780.420000 2772.780000 781.520000 2773.260000 ;
+ RECT 735.420000 2827.180000 736.520000 2827.660000 ;
+ RECT 735.420000 2832.620000 736.520000 2833.100000 ;
+ RECT 735.420000 2838.060000 736.520000 2838.540000 ;
+ RECT 735.420000 2843.500000 736.520000 2843.980000 ;
+ RECT 690.420000 2827.180000 691.520000 2827.660000 ;
+ RECT 690.420000 2832.620000 691.520000 2833.100000 ;
+ RECT 690.420000 2838.060000 691.520000 2838.540000 ;
+ RECT 690.420000 2843.500000 691.520000 2843.980000 ;
+ RECT 735.420000 2799.980000 736.520000 2800.460000 ;
+ RECT 735.420000 2805.420000 736.520000 2805.900000 ;
+ RECT 735.420000 2810.860000 736.520000 2811.340000 ;
+ RECT 735.420000 2816.300000 736.520000 2816.780000 ;
+ RECT 735.420000 2821.740000 736.520000 2822.220000 ;
+ RECT 690.420000 2799.980000 691.520000 2800.460000 ;
+ RECT 690.420000 2805.420000 691.520000 2805.900000 ;
+ RECT 690.420000 2810.860000 691.520000 2811.340000 ;
+ RECT 690.420000 2816.300000 691.520000 2816.780000 ;
+ RECT 690.420000 2821.740000 691.520000 2822.220000 ;
+ RECT 641.590000 2843.500000 642.590000 2843.980000 ;
+ RECT 645.255000 2843.500000 646.520000 2843.980000 ;
+ RECT 641.590000 2838.060000 642.590000 2838.540000 ;
+ RECT 645.255000 2838.060000 646.520000 2838.540000 ;
+ RECT 641.590000 2832.620000 642.590000 2833.100000 ;
+ RECT 645.255000 2832.620000 646.520000 2833.100000 ;
+ RECT 641.590000 2827.180000 642.590000 2827.660000 ;
+ RECT 645.255000 2827.180000 646.520000 2827.660000 ;
+ RECT 641.590000 2821.740000 642.590000 2822.220000 ;
+ RECT 645.255000 2821.740000 646.520000 2822.220000 ;
+ RECT 641.590000 2816.300000 642.590000 2816.780000 ;
+ RECT 645.255000 2816.300000 646.520000 2816.780000 ;
+ RECT 641.590000 2805.420000 642.590000 2805.900000 ;
+ RECT 645.255000 2805.420000 646.520000 2805.900000 ;
+ RECT 641.590000 2810.860000 642.590000 2811.340000 ;
+ RECT 645.255000 2810.860000 646.520000 2811.340000 ;
+ RECT 641.590000 2799.980000 642.590000 2800.460000 ;
+ RECT 645.255000 2799.980000 646.520000 2800.460000 ;
+ RECT 735.420000 2778.220000 736.520000 2778.700000 ;
+ RECT 735.420000 2783.660000 736.520000 2784.140000 ;
+ RECT 735.420000 2789.100000 736.520000 2789.580000 ;
+ RECT 735.420000 2794.540000 736.520000 2795.020000 ;
+ RECT 690.420000 2778.220000 691.520000 2778.700000 ;
+ RECT 690.420000 2783.660000 691.520000 2784.140000 ;
+ RECT 690.420000 2789.100000 691.520000 2789.580000 ;
+ RECT 690.420000 2794.540000 691.520000 2795.020000 ;
+ RECT 735.420000 2756.460000 736.520000 2756.940000 ;
+ RECT 735.420000 2761.900000 736.520000 2762.380000 ;
+ RECT 735.420000 2767.340000 736.520000 2767.820000 ;
+ RECT 735.420000 2772.780000 736.520000 2773.260000 ;
+ RECT 690.420000 2756.460000 691.520000 2756.940000 ;
+ RECT 690.420000 2761.900000 691.520000 2762.380000 ;
+ RECT 690.420000 2767.340000 691.520000 2767.820000 ;
+ RECT 690.420000 2772.780000 691.520000 2773.260000 ;
+ RECT 641.590000 2794.540000 642.590000 2795.020000 ;
+ RECT 645.255000 2794.540000 646.520000 2795.020000 ;
+ RECT 641.590000 2789.100000 642.590000 2789.580000 ;
+ RECT 645.255000 2789.100000 646.520000 2789.580000 ;
+ RECT 641.590000 2783.660000 642.590000 2784.140000 ;
+ RECT 645.255000 2783.660000 646.520000 2784.140000 ;
+ RECT 641.590000 2778.220000 642.590000 2778.700000 ;
+ RECT 645.255000 2778.220000 646.520000 2778.700000 ;
+ RECT 641.590000 2772.780000 642.590000 2773.260000 ;
+ RECT 645.255000 2772.780000 646.520000 2773.260000 ;
+ RECT 641.590000 2761.900000 642.590000 2762.380000 ;
+ RECT 645.255000 2761.900000 646.520000 2762.380000 ;
+ RECT 641.590000 2767.340000 642.590000 2767.820000 ;
+ RECT 645.255000 2767.340000 646.520000 2767.820000 ;
+ RECT 641.590000 2756.460000 642.590000 2756.940000 ;
+ RECT 645.255000 2756.460000 646.520000 2756.940000 ;
+ RECT 780.420000 2848.940000 781.520000 2849.420000 ;
+ RECT 825.420000 2848.940000 826.520000 2849.420000 ;
+ RECT 838.230000 2848.940000 839.230000 2849.420000 ;
+ RECT 690.420000 2848.940000 691.520000 2849.420000 ;
+ RECT 735.420000 2848.940000 736.520000 2849.420000 ;
+ RECT 641.590000 2848.940000 642.590000 2849.420000 ;
+ RECT 645.255000 2848.940000 646.520000 2849.420000 ;
+ RECT 640.360000 2945.700000 840.460000 2946.700000 ;
+ RECT 640.360000 2750.130000 840.460000 2751.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 2748.880000 642.590000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 2948.140000 642.590000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 2748.880000 839.230000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 2948.140000 839.230000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2750.130000 641.360000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2750.130000 840.460000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2945.700000 641.360000 2946.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2945.700000 840.460000 2946.700000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 2741.160000 646.520000 2741.640000 ;
+ RECT 645.255000 2730.280000 646.520000 2730.760000 ;
+ RECT 645.255000 2735.720000 646.520000 2736.200000 ;
+ RECT 645.255000 2724.840000 646.520000 2725.320000 ;
+ RECT 645.255000 2719.400000 646.520000 2719.880000 ;
+ RECT 645.255000 2713.960000 646.520000 2714.440000 ;
+ RECT 645.255000 2708.520000 646.520000 2709.000000 ;
+ RECT 645.255000 2703.080000 646.520000 2703.560000 ;
+ RECT 645.255000 2697.640000 646.520000 2698.120000 ;
+ RECT 645.255000 2686.760000 646.520000 2687.240000 ;
+ RECT 645.255000 2692.200000 646.520000 2692.680000 ;
+ RECT 645.255000 2681.320000 646.520000 2681.800000 ;
+ RECT 645.255000 2675.880000 646.520000 2676.360000 ;
+ RECT 645.255000 2670.440000 646.520000 2670.920000 ;
+ RECT 645.255000 2665.000000 646.520000 2665.480000 ;
+ RECT 645.255000 2659.560000 646.520000 2660.040000 ;
+ RECT 645.255000 2654.120000 646.520000 2654.600000 ;
+ RECT 645.255000 2643.240000 646.520000 2643.720000 ;
+ RECT 645.255000 2637.800000 646.520000 2638.280000 ;
+ RECT 645.255000 2632.360000 646.520000 2632.840000 ;
+ RECT 645.255000 2626.920000 646.520000 2627.400000 ;
+ RECT 645.255000 2621.480000 646.520000 2621.960000 ;
+ RECT 645.255000 2616.040000 646.520000 2616.520000 ;
+ RECT 645.255000 2605.160000 646.520000 2605.640000 ;
+ RECT 645.255000 2610.600000 646.520000 2611.080000 ;
+ RECT 645.255000 2599.720000 646.520000 2600.200000 ;
+ RECT 645.255000 2594.280000 646.520000 2594.760000 ;
+ RECT 645.255000 2588.840000 646.520000 2589.320000 ;
+ RECT 645.255000 2583.400000 646.520000 2583.880000 ;
+ RECT 645.255000 2577.960000 646.520000 2578.440000 ;
+ RECT 645.255000 2572.520000 646.520000 2573.000000 ;
+ RECT 645.255000 2561.640000 646.520000 2562.120000 ;
+ RECT 645.255000 2567.080000 646.520000 2567.560000 ;
+ RECT 645.255000 2556.200000 646.520000 2556.680000 ;
+ RECT 645.255000 2648.680000 646.520000 2649.160000 ;
+ RECT 825.420000 2549.870000 826.520000 2746.440000 ;
+ RECT 780.420000 2549.870000 781.520000 2746.440000 ;
+ RECT 838.230000 2548.620000 839.230000 2748.880000 ;
+ RECT 735.420000 2549.870000 736.520000 2746.440000 ;
+ RECT 690.420000 2549.870000 691.520000 2746.440000 ;
+ RECT 645.420000 2549.870000 646.520000 2746.440000 ;
+ RECT 641.590000 2548.620000 642.590000 2748.880000 ;
+ LAYER met3 ;
+ RECT 825.420000 2741.160000 826.520000 2741.640000 ;
+ RECT 838.230000 2741.160000 839.230000 2741.640000 ;
+ RECT 838.230000 2730.280000 839.230000 2730.760000 ;
+ RECT 838.230000 2724.840000 839.230000 2725.320000 ;
+ RECT 838.230000 2735.720000 839.230000 2736.200000 ;
+ RECT 825.420000 2735.720000 826.520000 2736.200000 ;
+ RECT 825.420000 2730.280000 826.520000 2730.760000 ;
+ RECT 825.420000 2724.840000 826.520000 2725.320000 ;
+ RECT 825.420000 2713.960000 826.520000 2714.440000 ;
+ RECT 825.420000 2719.400000 826.520000 2719.880000 ;
+ RECT 838.230000 2713.960000 839.230000 2714.440000 ;
+ RECT 838.230000 2719.400000 839.230000 2719.880000 ;
+ RECT 825.420000 2703.080000 826.520000 2703.560000 ;
+ RECT 825.420000 2708.520000 826.520000 2709.000000 ;
+ RECT 838.230000 2703.080000 839.230000 2703.560000 ;
+ RECT 838.230000 2708.520000 839.230000 2709.000000 ;
+ RECT 780.420000 2724.840000 781.520000 2725.320000 ;
+ RECT 780.420000 2730.280000 781.520000 2730.760000 ;
+ RECT 780.420000 2735.720000 781.520000 2736.200000 ;
+ RECT 780.420000 2741.160000 781.520000 2741.640000 ;
+ RECT 780.420000 2708.520000 781.520000 2709.000000 ;
+ RECT 780.420000 2703.080000 781.520000 2703.560000 ;
+ RECT 780.420000 2713.960000 781.520000 2714.440000 ;
+ RECT 780.420000 2719.400000 781.520000 2719.880000 ;
+ RECT 838.230000 2692.200000 839.230000 2692.680000 ;
+ RECT 838.230000 2686.760000 839.230000 2687.240000 ;
+ RECT 838.230000 2697.640000 839.230000 2698.120000 ;
+ RECT 825.420000 2697.640000 826.520000 2698.120000 ;
+ RECT 825.420000 2692.200000 826.520000 2692.680000 ;
+ RECT 825.420000 2686.760000 826.520000 2687.240000 ;
+ RECT 825.420000 2675.880000 826.520000 2676.360000 ;
+ RECT 825.420000 2681.320000 826.520000 2681.800000 ;
+ RECT 838.230000 2675.880000 839.230000 2676.360000 ;
+ RECT 838.230000 2681.320000 839.230000 2681.800000 ;
+ RECT 838.230000 2665.000000 839.230000 2665.480000 ;
+ RECT 838.230000 2670.440000 839.230000 2670.920000 ;
+ RECT 825.420000 2670.440000 826.520000 2670.920000 ;
+ RECT 825.420000 2665.000000 826.520000 2665.480000 ;
+ RECT 825.420000 2654.120000 826.520000 2654.600000 ;
+ RECT 825.420000 2659.560000 826.520000 2660.040000 ;
+ RECT 838.230000 2654.120000 839.230000 2654.600000 ;
+ RECT 838.230000 2659.560000 839.230000 2660.040000 ;
+ RECT 780.420000 2675.880000 781.520000 2676.360000 ;
+ RECT 780.420000 2681.320000 781.520000 2681.800000 ;
+ RECT 780.420000 2686.760000 781.520000 2687.240000 ;
+ RECT 780.420000 2692.200000 781.520000 2692.680000 ;
+ RECT 780.420000 2697.640000 781.520000 2698.120000 ;
+ RECT 780.420000 2654.120000 781.520000 2654.600000 ;
+ RECT 780.420000 2659.560000 781.520000 2660.040000 ;
+ RECT 780.420000 2665.000000 781.520000 2665.480000 ;
+ RECT 780.420000 2670.440000 781.520000 2670.920000 ;
+ RECT 735.420000 2730.280000 736.520000 2730.760000 ;
+ RECT 735.420000 2724.840000 736.520000 2725.320000 ;
+ RECT 735.420000 2735.720000 736.520000 2736.200000 ;
+ RECT 735.420000 2741.160000 736.520000 2741.640000 ;
+ RECT 690.420000 2724.840000 691.520000 2725.320000 ;
+ RECT 690.420000 2730.280000 691.520000 2730.760000 ;
+ RECT 690.420000 2735.720000 691.520000 2736.200000 ;
+ RECT 690.420000 2741.160000 691.520000 2741.640000 ;
+ RECT 735.420000 2703.080000 736.520000 2703.560000 ;
+ RECT 735.420000 2708.520000 736.520000 2709.000000 ;
+ RECT 735.420000 2713.960000 736.520000 2714.440000 ;
+ RECT 735.420000 2719.400000 736.520000 2719.880000 ;
+ RECT 690.420000 2703.080000 691.520000 2703.560000 ;
+ RECT 690.420000 2708.520000 691.520000 2709.000000 ;
+ RECT 690.420000 2713.960000 691.520000 2714.440000 ;
+ RECT 690.420000 2719.400000 691.520000 2719.880000 ;
+ RECT 641.590000 2741.160000 642.590000 2741.640000 ;
+ RECT 645.255000 2741.160000 646.520000 2741.640000 ;
+ RECT 641.590000 2730.280000 642.590000 2730.760000 ;
+ RECT 645.255000 2730.280000 646.520000 2730.760000 ;
+ RECT 641.590000 2735.720000 642.590000 2736.200000 ;
+ RECT 645.255000 2735.720000 646.520000 2736.200000 ;
+ RECT 641.590000 2724.840000 642.590000 2725.320000 ;
+ RECT 645.255000 2724.840000 646.520000 2725.320000 ;
+ RECT 641.590000 2719.400000 642.590000 2719.880000 ;
+ RECT 645.255000 2719.400000 646.520000 2719.880000 ;
+ RECT 641.590000 2713.960000 642.590000 2714.440000 ;
+ RECT 645.255000 2713.960000 646.520000 2714.440000 ;
+ RECT 641.590000 2708.520000 642.590000 2709.000000 ;
+ RECT 645.255000 2708.520000 646.520000 2709.000000 ;
+ RECT 641.590000 2703.080000 642.590000 2703.560000 ;
+ RECT 645.255000 2703.080000 646.520000 2703.560000 ;
+ RECT 735.420000 2675.880000 736.520000 2676.360000 ;
+ RECT 735.420000 2681.320000 736.520000 2681.800000 ;
+ RECT 735.420000 2686.760000 736.520000 2687.240000 ;
+ RECT 735.420000 2692.200000 736.520000 2692.680000 ;
+ RECT 735.420000 2697.640000 736.520000 2698.120000 ;
+ RECT 690.420000 2675.880000 691.520000 2676.360000 ;
+ RECT 690.420000 2681.320000 691.520000 2681.800000 ;
+ RECT 690.420000 2686.760000 691.520000 2687.240000 ;
+ RECT 690.420000 2692.200000 691.520000 2692.680000 ;
+ RECT 690.420000 2697.640000 691.520000 2698.120000 ;
+ RECT 735.420000 2654.120000 736.520000 2654.600000 ;
+ RECT 735.420000 2659.560000 736.520000 2660.040000 ;
+ RECT 735.420000 2665.000000 736.520000 2665.480000 ;
+ RECT 735.420000 2670.440000 736.520000 2670.920000 ;
+ RECT 690.420000 2654.120000 691.520000 2654.600000 ;
+ RECT 690.420000 2659.560000 691.520000 2660.040000 ;
+ RECT 690.420000 2665.000000 691.520000 2665.480000 ;
+ RECT 690.420000 2670.440000 691.520000 2670.920000 ;
+ RECT 641.590000 2697.640000 642.590000 2698.120000 ;
+ RECT 645.255000 2697.640000 646.520000 2698.120000 ;
+ RECT 641.590000 2686.760000 642.590000 2687.240000 ;
+ RECT 645.255000 2686.760000 646.520000 2687.240000 ;
+ RECT 641.590000 2692.200000 642.590000 2692.680000 ;
+ RECT 645.255000 2692.200000 646.520000 2692.680000 ;
+ RECT 641.590000 2681.320000 642.590000 2681.800000 ;
+ RECT 645.255000 2681.320000 646.520000 2681.800000 ;
+ RECT 641.590000 2675.880000 642.590000 2676.360000 ;
+ RECT 645.255000 2675.880000 646.520000 2676.360000 ;
+ RECT 641.590000 2670.440000 642.590000 2670.920000 ;
+ RECT 645.255000 2670.440000 646.520000 2670.920000 ;
+ RECT 641.590000 2665.000000 642.590000 2665.480000 ;
+ RECT 645.255000 2665.000000 646.520000 2665.480000 ;
+ RECT 641.590000 2659.560000 642.590000 2660.040000 ;
+ RECT 645.255000 2659.560000 646.520000 2660.040000 ;
+ RECT 641.590000 2654.120000 642.590000 2654.600000 ;
+ RECT 645.255000 2654.120000 646.520000 2654.600000 ;
+ RECT 825.420000 2637.800000 826.520000 2638.280000 ;
+ RECT 825.420000 2643.240000 826.520000 2643.720000 ;
+ RECT 838.230000 2637.800000 839.230000 2638.280000 ;
+ RECT 838.230000 2643.240000 839.230000 2643.720000 ;
+ RECT 838.230000 2626.920000 839.230000 2627.400000 ;
+ RECT 838.230000 2632.360000 839.230000 2632.840000 ;
+ RECT 825.420000 2632.360000 826.520000 2632.840000 ;
+ RECT 825.420000 2626.920000 826.520000 2627.400000 ;
+ RECT 825.420000 2616.040000 826.520000 2616.520000 ;
+ RECT 825.420000 2621.480000 826.520000 2621.960000 ;
+ RECT 838.230000 2616.040000 839.230000 2616.520000 ;
+ RECT 838.230000 2621.480000 839.230000 2621.960000 ;
+ RECT 838.230000 2605.160000 839.230000 2605.640000 ;
+ RECT 838.230000 2599.720000 839.230000 2600.200000 ;
+ RECT 838.230000 2610.600000 839.230000 2611.080000 ;
+ RECT 825.420000 2610.600000 826.520000 2611.080000 ;
+ RECT 825.420000 2605.160000 826.520000 2605.640000 ;
+ RECT 825.420000 2599.720000 826.520000 2600.200000 ;
+ RECT 780.420000 2626.920000 781.520000 2627.400000 ;
+ RECT 780.420000 2632.360000 781.520000 2632.840000 ;
+ RECT 780.420000 2637.800000 781.520000 2638.280000 ;
+ RECT 780.420000 2643.240000 781.520000 2643.720000 ;
+ RECT 780.420000 2599.720000 781.520000 2600.200000 ;
+ RECT 780.420000 2605.160000 781.520000 2605.640000 ;
+ RECT 780.420000 2610.600000 781.520000 2611.080000 ;
+ RECT 780.420000 2616.040000 781.520000 2616.520000 ;
+ RECT 780.420000 2621.480000 781.520000 2621.960000 ;
+ RECT 825.420000 2588.840000 826.520000 2589.320000 ;
+ RECT 825.420000 2594.280000 826.520000 2594.760000 ;
+ RECT 838.230000 2588.840000 839.230000 2589.320000 ;
+ RECT 838.230000 2594.280000 839.230000 2594.760000 ;
+ RECT 825.420000 2577.960000 826.520000 2578.440000 ;
+ RECT 825.420000 2583.400000 826.520000 2583.880000 ;
+ RECT 838.230000 2577.960000 839.230000 2578.440000 ;
+ RECT 838.230000 2583.400000 839.230000 2583.880000 ;
+ RECT 838.230000 2567.080000 839.230000 2567.560000 ;
+ RECT 838.230000 2561.640000 839.230000 2562.120000 ;
+ RECT 838.230000 2572.520000 839.230000 2573.000000 ;
+ RECT 825.420000 2572.520000 826.520000 2573.000000 ;
+ RECT 825.420000 2567.080000 826.520000 2567.560000 ;
+ RECT 825.420000 2561.640000 826.520000 2562.120000 ;
+ RECT 825.420000 2556.200000 826.520000 2556.680000 ;
+ RECT 838.230000 2556.200000 839.230000 2556.680000 ;
+ RECT 780.420000 2577.960000 781.520000 2578.440000 ;
+ RECT 780.420000 2583.400000 781.520000 2583.880000 ;
+ RECT 780.420000 2588.840000 781.520000 2589.320000 ;
+ RECT 780.420000 2594.280000 781.520000 2594.760000 ;
+ RECT 780.420000 2556.200000 781.520000 2556.680000 ;
+ RECT 780.420000 2561.640000 781.520000 2562.120000 ;
+ RECT 780.420000 2567.080000 781.520000 2567.560000 ;
+ RECT 780.420000 2572.520000 781.520000 2573.000000 ;
+ RECT 735.420000 2626.920000 736.520000 2627.400000 ;
+ RECT 735.420000 2632.360000 736.520000 2632.840000 ;
+ RECT 735.420000 2637.800000 736.520000 2638.280000 ;
+ RECT 735.420000 2643.240000 736.520000 2643.720000 ;
+ RECT 690.420000 2626.920000 691.520000 2627.400000 ;
+ RECT 690.420000 2632.360000 691.520000 2632.840000 ;
+ RECT 690.420000 2637.800000 691.520000 2638.280000 ;
+ RECT 690.420000 2643.240000 691.520000 2643.720000 ;
+ RECT 735.420000 2599.720000 736.520000 2600.200000 ;
+ RECT 735.420000 2605.160000 736.520000 2605.640000 ;
+ RECT 735.420000 2610.600000 736.520000 2611.080000 ;
+ RECT 735.420000 2616.040000 736.520000 2616.520000 ;
+ RECT 735.420000 2621.480000 736.520000 2621.960000 ;
+ RECT 690.420000 2599.720000 691.520000 2600.200000 ;
+ RECT 690.420000 2605.160000 691.520000 2605.640000 ;
+ RECT 690.420000 2610.600000 691.520000 2611.080000 ;
+ RECT 690.420000 2616.040000 691.520000 2616.520000 ;
+ RECT 690.420000 2621.480000 691.520000 2621.960000 ;
+ RECT 641.590000 2643.240000 642.590000 2643.720000 ;
+ RECT 645.255000 2643.240000 646.520000 2643.720000 ;
+ RECT 641.590000 2637.800000 642.590000 2638.280000 ;
+ RECT 645.255000 2637.800000 646.520000 2638.280000 ;
+ RECT 641.590000 2632.360000 642.590000 2632.840000 ;
+ RECT 645.255000 2632.360000 646.520000 2632.840000 ;
+ RECT 641.590000 2626.920000 642.590000 2627.400000 ;
+ RECT 645.255000 2626.920000 646.520000 2627.400000 ;
+ RECT 641.590000 2621.480000 642.590000 2621.960000 ;
+ RECT 645.255000 2621.480000 646.520000 2621.960000 ;
+ RECT 641.590000 2616.040000 642.590000 2616.520000 ;
+ RECT 645.255000 2616.040000 646.520000 2616.520000 ;
+ RECT 641.590000 2605.160000 642.590000 2605.640000 ;
+ RECT 645.255000 2605.160000 646.520000 2605.640000 ;
+ RECT 641.590000 2610.600000 642.590000 2611.080000 ;
+ RECT 645.255000 2610.600000 646.520000 2611.080000 ;
+ RECT 641.590000 2599.720000 642.590000 2600.200000 ;
+ RECT 645.255000 2599.720000 646.520000 2600.200000 ;
+ RECT 735.420000 2577.960000 736.520000 2578.440000 ;
+ RECT 735.420000 2583.400000 736.520000 2583.880000 ;
+ RECT 735.420000 2588.840000 736.520000 2589.320000 ;
+ RECT 735.420000 2594.280000 736.520000 2594.760000 ;
+ RECT 690.420000 2577.960000 691.520000 2578.440000 ;
+ RECT 690.420000 2583.400000 691.520000 2583.880000 ;
+ RECT 690.420000 2588.840000 691.520000 2589.320000 ;
+ RECT 690.420000 2594.280000 691.520000 2594.760000 ;
+ RECT 735.420000 2556.200000 736.520000 2556.680000 ;
+ RECT 735.420000 2561.640000 736.520000 2562.120000 ;
+ RECT 735.420000 2567.080000 736.520000 2567.560000 ;
+ RECT 735.420000 2572.520000 736.520000 2573.000000 ;
+ RECT 690.420000 2556.200000 691.520000 2556.680000 ;
+ RECT 690.420000 2561.640000 691.520000 2562.120000 ;
+ RECT 690.420000 2567.080000 691.520000 2567.560000 ;
+ RECT 690.420000 2572.520000 691.520000 2573.000000 ;
+ RECT 641.590000 2594.280000 642.590000 2594.760000 ;
+ RECT 645.255000 2594.280000 646.520000 2594.760000 ;
+ RECT 641.590000 2588.840000 642.590000 2589.320000 ;
+ RECT 645.255000 2588.840000 646.520000 2589.320000 ;
+ RECT 641.590000 2583.400000 642.590000 2583.880000 ;
+ RECT 645.255000 2583.400000 646.520000 2583.880000 ;
+ RECT 641.590000 2577.960000 642.590000 2578.440000 ;
+ RECT 645.255000 2577.960000 646.520000 2578.440000 ;
+ RECT 641.590000 2572.520000 642.590000 2573.000000 ;
+ RECT 645.255000 2572.520000 646.520000 2573.000000 ;
+ RECT 641.590000 2561.640000 642.590000 2562.120000 ;
+ RECT 645.255000 2561.640000 646.520000 2562.120000 ;
+ RECT 641.590000 2567.080000 642.590000 2567.560000 ;
+ RECT 645.255000 2567.080000 646.520000 2567.560000 ;
+ RECT 641.590000 2556.200000 642.590000 2556.680000 ;
+ RECT 645.255000 2556.200000 646.520000 2556.680000 ;
+ RECT 780.420000 2648.680000 781.520000 2649.160000 ;
+ RECT 825.420000 2648.680000 826.520000 2649.160000 ;
+ RECT 838.230000 2648.680000 839.230000 2649.160000 ;
+ RECT 690.420000 2648.680000 691.520000 2649.160000 ;
+ RECT 735.420000 2648.680000 736.520000 2649.160000 ;
+ RECT 641.590000 2648.680000 642.590000 2649.160000 ;
+ RECT 645.255000 2648.680000 646.520000 2649.160000 ;
+ RECT 640.360000 2745.440000 840.460000 2746.440000 ;
+ RECT 640.360000 2549.870000 840.460000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 2548.620000 642.590000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 2747.880000 642.590000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 2548.620000 839.230000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 2747.880000 839.230000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2549.870000 641.360000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2549.870000 840.460000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2745.440000 641.360000 2746.440000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2745.440000 840.460000 2746.440000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 2540.900000 646.520000 2541.380000 ;
+ RECT 645.255000 2530.020000 646.520000 2530.500000 ;
+ RECT 645.255000 2535.460000 646.520000 2535.940000 ;
+ RECT 645.255000 2524.580000 646.520000 2525.060000 ;
+ RECT 645.255000 2519.140000 646.520000 2519.620000 ;
+ RECT 645.255000 2513.700000 646.520000 2514.180000 ;
+ RECT 645.255000 2508.260000 646.520000 2508.740000 ;
+ RECT 645.255000 2502.820000 646.520000 2503.300000 ;
+ RECT 645.255000 2497.380000 646.520000 2497.860000 ;
+ RECT 645.255000 2486.500000 646.520000 2486.980000 ;
+ RECT 645.255000 2491.940000 646.520000 2492.420000 ;
+ RECT 645.255000 2481.060000 646.520000 2481.540000 ;
+ RECT 645.255000 2475.620000 646.520000 2476.100000 ;
+ RECT 645.255000 2470.180000 646.520000 2470.660000 ;
+ RECT 645.255000 2464.740000 646.520000 2465.220000 ;
+ RECT 645.255000 2459.300000 646.520000 2459.780000 ;
+ RECT 645.255000 2453.860000 646.520000 2454.340000 ;
+ RECT 645.255000 2442.980000 646.520000 2443.460000 ;
+ RECT 645.255000 2437.540000 646.520000 2438.020000 ;
+ RECT 645.255000 2432.100000 646.520000 2432.580000 ;
+ RECT 645.255000 2426.660000 646.520000 2427.140000 ;
+ RECT 645.255000 2421.220000 646.520000 2421.700000 ;
+ RECT 645.255000 2415.780000 646.520000 2416.260000 ;
+ RECT 645.255000 2404.900000 646.520000 2405.380000 ;
+ RECT 645.255000 2410.340000 646.520000 2410.820000 ;
+ RECT 645.255000 2399.460000 646.520000 2399.940000 ;
+ RECT 645.255000 2394.020000 646.520000 2394.500000 ;
+ RECT 645.255000 2388.580000 646.520000 2389.060000 ;
+ RECT 645.255000 2383.140000 646.520000 2383.620000 ;
+ RECT 645.255000 2377.700000 646.520000 2378.180000 ;
+ RECT 645.255000 2372.260000 646.520000 2372.740000 ;
+ RECT 645.255000 2361.380000 646.520000 2361.860000 ;
+ RECT 645.255000 2366.820000 646.520000 2367.300000 ;
+ RECT 645.255000 2355.940000 646.520000 2356.420000 ;
+ RECT 645.255000 2448.420000 646.520000 2448.900000 ;
+ RECT 825.420000 2349.610000 826.520000 2546.180000 ;
+ RECT 780.420000 2349.610000 781.520000 2546.180000 ;
+ RECT 838.230000 2348.360000 839.230000 2548.620000 ;
+ RECT 735.420000 2349.610000 736.520000 2546.180000 ;
+ RECT 690.420000 2349.610000 691.520000 2546.180000 ;
+ RECT 645.420000 2349.610000 646.520000 2546.180000 ;
+ RECT 641.590000 2348.360000 642.590000 2548.620000 ;
+ LAYER met3 ;
+ RECT 825.420000 2540.900000 826.520000 2541.380000 ;
+ RECT 838.230000 2540.900000 839.230000 2541.380000 ;
+ RECT 838.230000 2530.020000 839.230000 2530.500000 ;
+ RECT 838.230000 2524.580000 839.230000 2525.060000 ;
+ RECT 838.230000 2535.460000 839.230000 2535.940000 ;
+ RECT 825.420000 2535.460000 826.520000 2535.940000 ;
+ RECT 825.420000 2530.020000 826.520000 2530.500000 ;
+ RECT 825.420000 2524.580000 826.520000 2525.060000 ;
+ RECT 825.420000 2513.700000 826.520000 2514.180000 ;
+ RECT 825.420000 2519.140000 826.520000 2519.620000 ;
+ RECT 838.230000 2513.700000 839.230000 2514.180000 ;
+ RECT 838.230000 2519.140000 839.230000 2519.620000 ;
+ RECT 825.420000 2502.820000 826.520000 2503.300000 ;
+ RECT 825.420000 2508.260000 826.520000 2508.740000 ;
+ RECT 838.230000 2502.820000 839.230000 2503.300000 ;
+ RECT 838.230000 2508.260000 839.230000 2508.740000 ;
+ RECT 780.420000 2524.580000 781.520000 2525.060000 ;
+ RECT 780.420000 2530.020000 781.520000 2530.500000 ;
+ RECT 780.420000 2535.460000 781.520000 2535.940000 ;
+ RECT 780.420000 2540.900000 781.520000 2541.380000 ;
+ RECT 780.420000 2508.260000 781.520000 2508.740000 ;
+ RECT 780.420000 2502.820000 781.520000 2503.300000 ;
+ RECT 780.420000 2513.700000 781.520000 2514.180000 ;
+ RECT 780.420000 2519.140000 781.520000 2519.620000 ;
+ RECT 838.230000 2491.940000 839.230000 2492.420000 ;
+ RECT 838.230000 2486.500000 839.230000 2486.980000 ;
+ RECT 838.230000 2497.380000 839.230000 2497.860000 ;
+ RECT 825.420000 2497.380000 826.520000 2497.860000 ;
+ RECT 825.420000 2491.940000 826.520000 2492.420000 ;
+ RECT 825.420000 2486.500000 826.520000 2486.980000 ;
+ RECT 825.420000 2475.620000 826.520000 2476.100000 ;
+ RECT 825.420000 2481.060000 826.520000 2481.540000 ;
+ RECT 838.230000 2475.620000 839.230000 2476.100000 ;
+ RECT 838.230000 2481.060000 839.230000 2481.540000 ;
+ RECT 838.230000 2464.740000 839.230000 2465.220000 ;
+ RECT 838.230000 2470.180000 839.230000 2470.660000 ;
+ RECT 825.420000 2470.180000 826.520000 2470.660000 ;
+ RECT 825.420000 2464.740000 826.520000 2465.220000 ;
+ RECT 825.420000 2453.860000 826.520000 2454.340000 ;
+ RECT 825.420000 2459.300000 826.520000 2459.780000 ;
+ RECT 838.230000 2453.860000 839.230000 2454.340000 ;
+ RECT 838.230000 2459.300000 839.230000 2459.780000 ;
+ RECT 780.420000 2475.620000 781.520000 2476.100000 ;
+ RECT 780.420000 2481.060000 781.520000 2481.540000 ;
+ RECT 780.420000 2486.500000 781.520000 2486.980000 ;
+ RECT 780.420000 2491.940000 781.520000 2492.420000 ;
+ RECT 780.420000 2497.380000 781.520000 2497.860000 ;
+ RECT 780.420000 2453.860000 781.520000 2454.340000 ;
+ RECT 780.420000 2459.300000 781.520000 2459.780000 ;
+ RECT 780.420000 2464.740000 781.520000 2465.220000 ;
+ RECT 780.420000 2470.180000 781.520000 2470.660000 ;
+ RECT 735.420000 2530.020000 736.520000 2530.500000 ;
+ RECT 735.420000 2524.580000 736.520000 2525.060000 ;
+ RECT 735.420000 2535.460000 736.520000 2535.940000 ;
+ RECT 735.420000 2540.900000 736.520000 2541.380000 ;
+ RECT 690.420000 2524.580000 691.520000 2525.060000 ;
+ RECT 690.420000 2530.020000 691.520000 2530.500000 ;
+ RECT 690.420000 2535.460000 691.520000 2535.940000 ;
+ RECT 690.420000 2540.900000 691.520000 2541.380000 ;
+ RECT 735.420000 2502.820000 736.520000 2503.300000 ;
+ RECT 735.420000 2508.260000 736.520000 2508.740000 ;
+ RECT 735.420000 2513.700000 736.520000 2514.180000 ;
+ RECT 735.420000 2519.140000 736.520000 2519.620000 ;
+ RECT 690.420000 2502.820000 691.520000 2503.300000 ;
+ RECT 690.420000 2508.260000 691.520000 2508.740000 ;
+ RECT 690.420000 2513.700000 691.520000 2514.180000 ;
+ RECT 690.420000 2519.140000 691.520000 2519.620000 ;
+ RECT 641.590000 2540.900000 642.590000 2541.380000 ;
+ RECT 645.255000 2540.900000 646.520000 2541.380000 ;
+ RECT 641.590000 2530.020000 642.590000 2530.500000 ;
+ RECT 645.255000 2530.020000 646.520000 2530.500000 ;
+ RECT 641.590000 2535.460000 642.590000 2535.940000 ;
+ RECT 645.255000 2535.460000 646.520000 2535.940000 ;
+ RECT 641.590000 2524.580000 642.590000 2525.060000 ;
+ RECT 645.255000 2524.580000 646.520000 2525.060000 ;
+ RECT 641.590000 2519.140000 642.590000 2519.620000 ;
+ RECT 645.255000 2519.140000 646.520000 2519.620000 ;
+ RECT 641.590000 2513.700000 642.590000 2514.180000 ;
+ RECT 645.255000 2513.700000 646.520000 2514.180000 ;
+ RECT 641.590000 2508.260000 642.590000 2508.740000 ;
+ RECT 645.255000 2508.260000 646.520000 2508.740000 ;
+ RECT 641.590000 2502.820000 642.590000 2503.300000 ;
+ RECT 645.255000 2502.820000 646.520000 2503.300000 ;
+ RECT 735.420000 2475.620000 736.520000 2476.100000 ;
+ RECT 735.420000 2481.060000 736.520000 2481.540000 ;
+ RECT 735.420000 2486.500000 736.520000 2486.980000 ;
+ RECT 735.420000 2491.940000 736.520000 2492.420000 ;
+ RECT 735.420000 2497.380000 736.520000 2497.860000 ;
+ RECT 690.420000 2475.620000 691.520000 2476.100000 ;
+ RECT 690.420000 2481.060000 691.520000 2481.540000 ;
+ RECT 690.420000 2486.500000 691.520000 2486.980000 ;
+ RECT 690.420000 2491.940000 691.520000 2492.420000 ;
+ RECT 690.420000 2497.380000 691.520000 2497.860000 ;
+ RECT 735.420000 2453.860000 736.520000 2454.340000 ;
+ RECT 735.420000 2459.300000 736.520000 2459.780000 ;
+ RECT 735.420000 2464.740000 736.520000 2465.220000 ;
+ RECT 735.420000 2470.180000 736.520000 2470.660000 ;
+ RECT 690.420000 2453.860000 691.520000 2454.340000 ;
+ RECT 690.420000 2459.300000 691.520000 2459.780000 ;
+ RECT 690.420000 2464.740000 691.520000 2465.220000 ;
+ RECT 690.420000 2470.180000 691.520000 2470.660000 ;
+ RECT 641.590000 2497.380000 642.590000 2497.860000 ;
+ RECT 645.255000 2497.380000 646.520000 2497.860000 ;
+ RECT 641.590000 2486.500000 642.590000 2486.980000 ;
+ RECT 645.255000 2486.500000 646.520000 2486.980000 ;
+ RECT 641.590000 2491.940000 642.590000 2492.420000 ;
+ RECT 645.255000 2491.940000 646.520000 2492.420000 ;
+ RECT 641.590000 2481.060000 642.590000 2481.540000 ;
+ RECT 645.255000 2481.060000 646.520000 2481.540000 ;
+ RECT 641.590000 2475.620000 642.590000 2476.100000 ;
+ RECT 645.255000 2475.620000 646.520000 2476.100000 ;
+ RECT 641.590000 2470.180000 642.590000 2470.660000 ;
+ RECT 645.255000 2470.180000 646.520000 2470.660000 ;
+ RECT 641.590000 2464.740000 642.590000 2465.220000 ;
+ RECT 645.255000 2464.740000 646.520000 2465.220000 ;
+ RECT 641.590000 2459.300000 642.590000 2459.780000 ;
+ RECT 645.255000 2459.300000 646.520000 2459.780000 ;
+ RECT 641.590000 2453.860000 642.590000 2454.340000 ;
+ RECT 645.255000 2453.860000 646.520000 2454.340000 ;
+ RECT 825.420000 2437.540000 826.520000 2438.020000 ;
+ RECT 825.420000 2442.980000 826.520000 2443.460000 ;
+ RECT 838.230000 2437.540000 839.230000 2438.020000 ;
+ RECT 838.230000 2442.980000 839.230000 2443.460000 ;
+ RECT 838.230000 2426.660000 839.230000 2427.140000 ;
+ RECT 838.230000 2432.100000 839.230000 2432.580000 ;
+ RECT 825.420000 2432.100000 826.520000 2432.580000 ;
+ RECT 825.420000 2426.660000 826.520000 2427.140000 ;
+ RECT 825.420000 2415.780000 826.520000 2416.260000 ;
+ RECT 825.420000 2421.220000 826.520000 2421.700000 ;
+ RECT 838.230000 2415.780000 839.230000 2416.260000 ;
+ RECT 838.230000 2421.220000 839.230000 2421.700000 ;
+ RECT 838.230000 2404.900000 839.230000 2405.380000 ;
+ RECT 838.230000 2399.460000 839.230000 2399.940000 ;
+ RECT 838.230000 2410.340000 839.230000 2410.820000 ;
+ RECT 825.420000 2410.340000 826.520000 2410.820000 ;
+ RECT 825.420000 2404.900000 826.520000 2405.380000 ;
+ RECT 825.420000 2399.460000 826.520000 2399.940000 ;
+ RECT 780.420000 2426.660000 781.520000 2427.140000 ;
+ RECT 780.420000 2432.100000 781.520000 2432.580000 ;
+ RECT 780.420000 2437.540000 781.520000 2438.020000 ;
+ RECT 780.420000 2442.980000 781.520000 2443.460000 ;
+ RECT 780.420000 2399.460000 781.520000 2399.940000 ;
+ RECT 780.420000 2404.900000 781.520000 2405.380000 ;
+ RECT 780.420000 2410.340000 781.520000 2410.820000 ;
+ RECT 780.420000 2415.780000 781.520000 2416.260000 ;
+ RECT 780.420000 2421.220000 781.520000 2421.700000 ;
+ RECT 825.420000 2388.580000 826.520000 2389.060000 ;
+ RECT 825.420000 2394.020000 826.520000 2394.500000 ;
+ RECT 838.230000 2388.580000 839.230000 2389.060000 ;
+ RECT 838.230000 2394.020000 839.230000 2394.500000 ;
+ RECT 825.420000 2377.700000 826.520000 2378.180000 ;
+ RECT 825.420000 2383.140000 826.520000 2383.620000 ;
+ RECT 838.230000 2377.700000 839.230000 2378.180000 ;
+ RECT 838.230000 2383.140000 839.230000 2383.620000 ;
+ RECT 838.230000 2366.820000 839.230000 2367.300000 ;
+ RECT 838.230000 2361.380000 839.230000 2361.860000 ;
+ RECT 838.230000 2372.260000 839.230000 2372.740000 ;
+ RECT 825.420000 2372.260000 826.520000 2372.740000 ;
+ RECT 825.420000 2366.820000 826.520000 2367.300000 ;
+ RECT 825.420000 2361.380000 826.520000 2361.860000 ;
+ RECT 825.420000 2355.940000 826.520000 2356.420000 ;
+ RECT 838.230000 2355.940000 839.230000 2356.420000 ;
+ RECT 780.420000 2377.700000 781.520000 2378.180000 ;
+ RECT 780.420000 2383.140000 781.520000 2383.620000 ;
+ RECT 780.420000 2388.580000 781.520000 2389.060000 ;
+ RECT 780.420000 2394.020000 781.520000 2394.500000 ;
+ RECT 780.420000 2355.940000 781.520000 2356.420000 ;
+ RECT 780.420000 2361.380000 781.520000 2361.860000 ;
+ RECT 780.420000 2366.820000 781.520000 2367.300000 ;
+ RECT 780.420000 2372.260000 781.520000 2372.740000 ;
+ RECT 735.420000 2426.660000 736.520000 2427.140000 ;
+ RECT 735.420000 2432.100000 736.520000 2432.580000 ;
+ RECT 735.420000 2437.540000 736.520000 2438.020000 ;
+ RECT 735.420000 2442.980000 736.520000 2443.460000 ;
+ RECT 690.420000 2426.660000 691.520000 2427.140000 ;
+ RECT 690.420000 2432.100000 691.520000 2432.580000 ;
+ RECT 690.420000 2437.540000 691.520000 2438.020000 ;
+ RECT 690.420000 2442.980000 691.520000 2443.460000 ;
+ RECT 735.420000 2399.460000 736.520000 2399.940000 ;
+ RECT 735.420000 2404.900000 736.520000 2405.380000 ;
+ RECT 735.420000 2410.340000 736.520000 2410.820000 ;
+ RECT 735.420000 2415.780000 736.520000 2416.260000 ;
+ RECT 735.420000 2421.220000 736.520000 2421.700000 ;
+ RECT 690.420000 2399.460000 691.520000 2399.940000 ;
+ RECT 690.420000 2404.900000 691.520000 2405.380000 ;
+ RECT 690.420000 2410.340000 691.520000 2410.820000 ;
+ RECT 690.420000 2415.780000 691.520000 2416.260000 ;
+ RECT 690.420000 2421.220000 691.520000 2421.700000 ;
+ RECT 641.590000 2442.980000 642.590000 2443.460000 ;
+ RECT 645.255000 2442.980000 646.520000 2443.460000 ;
+ RECT 641.590000 2437.540000 642.590000 2438.020000 ;
+ RECT 645.255000 2437.540000 646.520000 2438.020000 ;
+ RECT 641.590000 2432.100000 642.590000 2432.580000 ;
+ RECT 645.255000 2432.100000 646.520000 2432.580000 ;
+ RECT 641.590000 2426.660000 642.590000 2427.140000 ;
+ RECT 645.255000 2426.660000 646.520000 2427.140000 ;
+ RECT 641.590000 2421.220000 642.590000 2421.700000 ;
+ RECT 645.255000 2421.220000 646.520000 2421.700000 ;
+ RECT 641.590000 2415.780000 642.590000 2416.260000 ;
+ RECT 645.255000 2415.780000 646.520000 2416.260000 ;
+ RECT 641.590000 2404.900000 642.590000 2405.380000 ;
+ RECT 645.255000 2404.900000 646.520000 2405.380000 ;
+ RECT 641.590000 2410.340000 642.590000 2410.820000 ;
+ RECT 645.255000 2410.340000 646.520000 2410.820000 ;
+ RECT 641.590000 2399.460000 642.590000 2399.940000 ;
+ RECT 645.255000 2399.460000 646.520000 2399.940000 ;
+ RECT 735.420000 2377.700000 736.520000 2378.180000 ;
+ RECT 735.420000 2383.140000 736.520000 2383.620000 ;
+ RECT 735.420000 2388.580000 736.520000 2389.060000 ;
+ RECT 735.420000 2394.020000 736.520000 2394.500000 ;
+ RECT 690.420000 2377.700000 691.520000 2378.180000 ;
+ RECT 690.420000 2383.140000 691.520000 2383.620000 ;
+ RECT 690.420000 2388.580000 691.520000 2389.060000 ;
+ RECT 690.420000 2394.020000 691.520000 2394.500000 ;
+ RECT 735.420000 2355.940000 736.520000 2356.420000 ;
+ RECT 735.420000 2361.380000 736.520000 2361.860000 ;
+ RECT 735.420000 2366.820000 736.520000 2367.300000 ;
+ RECT 735.420000 2372.260000 736.520000 2372.740000 ;
+ RECT 690.420000 2355.940000 691.520000 2356.420000 ;
+ RECT 690.420000 2361.380000 691.520000 2361.860000 ;
+ RECT 690.420000 2366.820000 691.520000 2367.300000 ;
+ RECT 690.420000 2372.260000 691.520000 2372.740000 ;
+ RECT 641.590000 2394.020000 642.590000 2394.500000 ;
+ RECT 645.255000 2394.020000 646.520000 2394.500000 ;
+ RECT 641.590000 2388.580000 642.590000 2389.060000 ;
+ RECT 645.255000 2388.580000 646.520000 2389.060000 ;
+ RECT 641.590000 2383.140000 642.590000 2383.620000 ;
+ RECT 645.255000 2383.140000 646.520000 2383.620000 ;
+ RECT 641.590000 2377.700000 642.590000 2378.180000 ;
+ RECT 645.255000 2377.700000 646.520000 2378.180000 ;
+ RECT 641.590000 2372.260000 642.590000 2372.740000 ;
+ RECT 645.255000 2372.260000 646.520000 2372.740000 ;
+ RECT 641.590000 2361.380000 642.590000 2361.860000 ;
+ RECT 645.255000 2361.380000 646.520000 2361.860000 ;
+ RECT 641.590000 2366.820000 642.590000 2367.300000 ;
+ RECT 645.255000 2366.820000 646.520000 2367.300000 ;
+ RECT 641.590000 2355.940000 642.590000 2356.420000 ;
+ RECT 645.255000 2355.940000 646.520000 2356.420000 ;
+ RECT 780.420000 2448.420000 781.520000 2448.900000 ;
+ RECT 825.420000 2448.420000 826.520000 2448.900000 ;
+ RECT 838.230000 2448.420000 839.230000 2448.900000 ;
+ RECT 690.420000 2448.420000 691.520000 2448.900000 ;
+ RECT 735.420000 2448.420000 736.520000 2448.900000 ;
+ RECT 641.590000 2448.420000 642.590000 2448.900000 ;
+ RECT 645.255000 2448.420000 646.520000 2448.900000 ;
+ RECT 640.360000 2545.180000 840.460000 2546.180000 ;
+ RECT 640.360000 2349.610000 840.460000 2350.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 2348.360000 642.590000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 2547.620000 642.590000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 2348.360000 839.230000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 2547.620000 839.230000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2349.610000 641.360000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2349.610000 840.460000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2545.180000 641.360000 2546.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2545.180000 840.460000 2546.180000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 2340.640000 646.520000 2341.120000 ;
+ RECT 645.255000 2329.760000 646.520000 2330.240000 ;
+ RECT 645.255000 2335.200000 646.520000 2335.680000 ;
+ RECT 645.255000 2324.320000 646.520000 2324.800000 ;
+ RECT 645.255000 2318.880000 646.520000 2319.360000 ;
+ RECT 645.255000 2313.440000 646.520000 2313.920000 ;
+ RECT 645.255000 2308.000000 646.520000 2308.480000 ;
+ RECT 645.255000 2302.560000 646.520000 2303.040000 ;
+ RECT 645.255000 2297.120000 646.520000 2297.600000 ;
+ RECT 645.255000 2286.240000 646.520000 2286.720000 ;
+ RECT 645.255000 2291.680000 646.520000 2292.160000 ;
+ RECT 645.255000 2280.800000 646.520000 2281.280000 ;
+ RECT 645.255000 2275.360000 646.520000 2275.840000 ;
+ RECT 645.255000 2269.920000 646.520000 2270.400000 ;
+ RECT 645.255000 2264.480000 646.520000 2264.960000 ;
+ RECT 645.255000 2259.040000 646.520000 2259.520000 ;
+ RECT 645.255000 2253.600000 646.520000 2254.080000 ;
+ RECT 645.255000 2242.720000 646.520000 2243.200000 ;
+ RECT 645.255000 2237.280000 646.520000 2237.760000 ;
+ RECT 645.255000 2231.840000 646.520000 2232.320000 ;
+ RECT 645.255000 2226.400000 646.520000 2226.880000 ;
+ RECT 645.255000 2220.960000 646.520000 2221.440000 ;
+ RECT 645.255000 2215.520000 646.520000 2216.000000 ;
+ RECT 645.255000 2204.640000 646.520000 2205.120000 ;
+ RECT 645.255000 2210.080000 646.520000 2210.560000 ;
+ RECT 645.255000 2199.200000 646.520000 2199.680000 ;
+ RECT 645.255000 2193.760000 646.520000 2194.240000 ;
+ RECT 645.255000 2188.320000 646.520000 2188.800000 ;
+ RECT 645.255000 2182.880000 646.520000 2183.360000 ;
+ RECT 645.255000 2177.440000 646.520000 2177.920000 ;
+ RECT 645.255000 2172.000000 646.520000 2172.480000 ;
+ RECT 645.255000 2161.120000 646.520000 2161.600000 ;
+ RECT 645.255000 2166.560000 646.520000 2167.040000 ;
+ RECT 645.255000 2155.680000 646.520000 2156.160000 ;
+ RECT 645.255000 2248.160000 646.520000 2248.640000 ;
+ RECT 825.420000 2149.350000 826.520000 2345.920000 ;
+ RECT 780.420000 2149.350000 781.520000 2345.920000 ;
+ RECT 838.230000 2148.100000 839.230000 2348.360000 ;
+ RECT 735.420000 2149.350000 736.520000 2345.920000 ;
+ RECT 690.420000 2149.350000 691.520000 2345.920000 ;
+ RECT 645.420000 2149.350000 646.520000 2345.920000 ;
+ RECT 641.590000 2148.100000 642.590000 2348.360000 ;
+ LAYER met3 ;
+ RECT 825.420000 2340.640000 826.520000 2341.120000 ;
+ RECT 838.230000 2340.640000 839.230000 2341.120000 ;
+ RECT 838.230000 2329.760000 839.230000 2330.240000 ;
+ RECT 838.230000 2324.320000 839.230000 2324.800000 ;
+ RECT 838.230000 2335.200000 839.230000 2335.680000 ;
+ RECT 825.420000 2335.200000 826.520000 2335.680000 ;
+ RECT 825.420000 2329.760000 826.520000 2330.240000 ;
+ RECT 825.420000 2324.320000 826.520000 2324.800000 ;
+ RECT 825.420000 2313.440000 826.520000 2313.920000 ;
+ RECT 825.420000 2318.880000 826.520000 2319.360000 ;
+ RECT 838.230000 2313.440000 839.230000 2313.920000 ;
+ RECT 838.230000 2318.880000 839.230000 2319.360000 ;
+ RECT 825.420000 2302.560000 826.520000 2303.040000 ;
+ RECT 825.420000 2308.000000 826.520000 2308.480000 ;
+ RECT 838.230000 2302.560000 839.230000 2303.040000 ;
+ RECT 838.230000 2308.000000 839.230000 2308.480000 ;
+ RECT 780.420000 2324.320000 781.520000 2324.800000 ;
+ RECT 780.420000 2329.760000 781.520000 2330.240000 ;
+ RECT 780.420000 2335.200000 781.520000 2335.680000 ;
+ RECT 780.420000 2340.640000 781.520000 2341.120000 ;
+ RECT 780.420000 2308.000000 781.520000 2308.480000 ;
+ RECT 780.420000 2302.560000 781.520000 2303.040000 ;
+ RECT 780.420000 2313.440000 781.520000 2313.920000 ;
+ RECT 780.420000 2318.880000 781.520000 2319.360000 ;
+ RECT 838.230000 2291.680000 839.230000 2292.160000 ;
+ RECT 838.230000 2286.240000 839.230000 2286.720000 ;
+ RECT 838.230000 2297.120000 839.230000 2297.600000 ;
+ RECT 825.420000 2297.120000 826.520000 2297.600000 ;
+ RECT 825.420000 2291.680000 826.520000 2292.160000 ;
+ RECT 825.420000 2286.240000 826.520000 2286.720000 ;
+ RECT 825.420000 2275.360000 826.520000 2275.840000 ;
+ RECT 825.420000 2280.800000 826.520000 2281.280000 ;
+ RECT 838.230000 2275.360000 839.230000 2275.840000 ;
+ RECT 838.230000 2280.800000 839.230000 2281.280000 ;
+ RECT 838.230000 2264.480000 839.230000 2264.960000 ;
+ RECT 838.230000 2269.920000 839.230000 2270.400000 ;
+ RECT 825.420000 2269.920000 826.520000 2270.400000 ;
+ RECT 825.420000 2264.480000 826.520000 2264.960000 ;
+ RECT 825.420000 2253.600000 826.520000 2254.080000 ;
+ RECT 825.420000 2259.040000 826.520000 2259.520000 ;
+ RECT 838.230000 2253.600000 839.230000 2254.080000 ;
+ RECT 838.230000 2259.040000 839.230000 2259.520000 ;
+ RECT 780.420000 2275.360000 781.520000 2275.840000 ;
+ RECT 780.420000 2280.800000 781.520000 2281.280000 ;
+ RECT 780.420000 2286.240000 781.520000 2286.720000 ;
+ RECT 780.420000 2291.680000 781.520000 2292.160000 ;
+ RECT 780.420000 2297.120000 781.520000 2297.600000 ;
+ RECT 780.420000 2253.600000 781.520000 2254.080000 ;
+ RECT 780.420000 2259.040000 781.520000 2259.520000 ;
+ RECT 780.420000 2264.480000 781.520000 2264.960000 ;
+ RECT 780.420000 2269.920000 781.520000 2270.400000 ;
+ RECT 735.420000 2329.760000 736.520000 2330.240000 ;
+ RECT 735.420000 2324.320000 736.520000 2324.800000 ;
+ RECT 735.420000 2335.200000 736.520000 2335.680000 ;
+ RECT 735.420000 2340.640000 736.520000 2341.120000 ;
+ RECT 690.420000 2324.320000 691.520000 2324.800000 ;
+ RECT 690.420000 2329.760000 691.520000 2330.240000 ;
+ RECT 690.420000 2335.200000 691.520000 2335.680000 ;
+ RECT 690.420000 2340.640000 691.520000 2341.120000 ;
+ RECT 735.420000 2302.560000 736.520000 2303.040000 ;
+ RECT 735.420000 2308.000000 736.520000 2308.480000 ;
+ RECT 735.420000 2313.440000 736.520000 2313.920000 ;
+ RECT 735.420000 2318.880000 736.520000 2319.360000 ;
+ RECT 690.420000 2302.560000 691.520000 2303.040000 ;
+ RECT 690.420000 2308.000000 691.520000 2308.480000 ;
+ RECT 690.420000 2313.440000 691.520000 2313.920000 ;
+ RECT 690.420000 2318.880000 691.520000 2319.360000 ;
+ RECT 641.590000 2340.640000 642.590000 2341.120000 ;
+ RECT 645.255000 2340.640000 646.520000 2341.120000 ;
+ RECT 641.590000 2329.760000 642.590000 2330.240000 ;
+ RECT 645.255000 2329.760000 646.520000 2330.240000 ;
+ RECT 641.590000 2335.200000 642.590000 2335.680000 ;
+ RECT 645.255000 2335.200000 646.520000 2335.680000 ;
+ RECT 641.590000 2324.320000 642.590000 2324.800000 ;
+ RECT 645.255000 2324.320000 646.520000 2324.800000 ;
+ RECT 641.590000 2318.880000 642.590000 2319.360000 ;
+ RECT 645.255000 2318.880000 646.520000 2319.360000 ;
+ RECT 641.590000 2313.440000 642.590000 2313.920000 ;
+ RECT 645.255000 2313.440000 646.520000 2313.920000 ;
+ RECT 641.590000 2308.000000 642.590000 2308.480000 ;
+ RECT 645.255000 2308.000000 646.520000 2308.480000 ;
+ RECT 641.590000 2302.560000 642.590000 2303.040000 ;
+ RECT 645.255000 2302.560000 646.520000 2303.040000 ;
+ RECT 735.420000 2275.360000 736.520000 2275.840000 ;
+ RECT 735.420000 2280.800000 736.520000 2281.280000 ;
+ RECT 735.420000 2286.240000 736.520000 2286.720000 ;
+ RECT 735.420000 2291.680000 736.520000 2292.160000 ;
+ RECT 735.420000 2297.120000 736.520000 2297.600000 ;
+ RECT 690.420000 2275.360000 691.520000 2275.840000 ;
+ RECT 690.420000 2280.800000 691.520000 2281.280000 ;
+ RECT 690.420000 2286.240000 691.520000 2286.720000 ;
+ RECT 690.420000 2291.680000 691.520000 2292.160000 ;
+ RECT 690.420000 2297.120000 691.520000 2297.600000 ;
+ RECT 735.420000 2253.600000 736.520000 2254.080000 ;
+ RECT 735.420000 2259.040000 736.520000 2259.520000 ;
+ RECT 735.420000 2264.480000 736.520000 2264.960000 ;
+ RECT 735.420000 2269.920000 736.520000 2270.400000 ;
+ RECT 690.420000 2253.600000 691.520000 2254.080000 ;
+ RECT 690.420000 2259.040000 691.520000 2259.520000 ;
+ RECT 690.420000 2264.480000 691.520000 2264.960000 ;
+ RECT 690.420000 2269.920000 691.520000 2270.400000 ;
+ RECT 641.590000 2297.120000 642.590000 2297.600000 ;
+ RECT 645.255000 2297.120000 646.520000 2297.600000 ;
+ RECT 641.590000 2286.240000 642.590000 2286.720000 ;
+ RECT 645.255000 2286.240000 646.520000 2286.720000 ;
+ RECT 641.590000 2291.680000 642.590000 2292.160000 ;
+ RECT 645.255000 2291.680000 646.520000 2292.160000 ;
+ RECT 641.590000 2280.800000 642.590000 2281.280000 ;
+ RECT 645.255000 2280.800000 646.520000 2281.280000 ;
+ RECT 641.590000 2275.360000 642.590000 2275.840000 ;
+ RECT 645.255000 2275.360000 646.520000 2275.840000 ;
+ RECT 641.590000 2269.920000 642.590000 2270.400000 ;
+ RECT 645.255000 2269.920000 646.520000 2270.400000 ;
+ RECT 641.590000 2264.480000 642.590000 2264.960000 ;
+ RECT 645.255000 2264.480000 646.520000 2264.960000 ;
+ RECT 641.590000 2259.040000 642.590000 2259.520000 ;
+ RECT 645.255000 2259.040000 646.520000 2259.520000 ;
+ RECT 641.590000 2253.600000 642.590000 2254.080000 ;
+ RECT 645.255000 2253.600000 646.520000 2254.080000 ;
+ RECT 825.420000 2237.280000 826.520000 2237.760000 ;
+ RECT 825.420000 2242.720000 826.520000 2243.200000 ;
+ RECT 838.230000 2237.280000 839.230000 2237.760000 ;
+ RECT 838.230000 2242.720000 839.230000 2243.200000 ;
+ RECT 838.230000 2226.400000 839.230000 2226.880000 ;
+ RECT 838.230000 2231.840000 839.230000 2232.320000 ;
+ RECT 825.420000 2231.840000 826.520000 2232.320000 ;
+ RECT 825.420000 2226.400000 826.520000 2226.880000 ;
+ RECT 825.420000 2215.520000 826.520000 2216.000000 ;
+ RECT 825.420000 2220.960000 826.520000 2221.440000 ;
+ RECT 838.230000 2215.520000 839.230000 2216.000000 ;
+ RECT 838.230000 2220.960000 839.230000 2221.440000 ;
+ RECT 838.230000 2204.640000 839.230000 2205.120000 ;
+ RECT 838.230000 2199.200000 839.230000 2199.680000 ;
+ RECT 838.230000 2210.080000 839.230000 2210.560000 ;
+ RECT 825.420000 2210.080000 826.520000 2210.560000 ;
+ RECT 825.420000 2204.640000 826.520000 2205.120000 ;
+ RECT 825.420000 2199.200000 826.520000 2199.680000 ;
+ RECT 780.420000 2226.400000 781.520000 2226.880000 ;
+ RECT 780.420000 2231.840000 781.520000 2232.320000 ;
+ RECT 780.420000 2237.280000 781.520000 2237.760000 ;
+ RECT 780.420000 2242.720000 781.520000 2243.200000 ;
+ RECT 780.420000 2199.200000 781.520000 2199.680000 ;
+ RECT 780.420000 2204.640000 781.520000 2205.120000 ;
+ RECT 780.420000 2210.080000 781.520000 2210.560000 ;
+ RECT 780.420000 2215.520000 781.520000 2216.000000 ;
+ RECT 780.420000 2220.960000 781.520000 2221.440000 ;
+ RECT 825.420000 2188.320000 826.520000 2188.800000 ;
+ RECT 825.420000 2193.760000 826.520000 2194.240000 ;
+ RECT 838.230000 2188.320000 839.230000 2188.800000 ;
+ RECT 838.230000 2193.760000 839.230000 2194.240000 ;
+ RECT 825.420000 2177.440000 826.520000 2177.920000 ;
+ RECT 825.420000 2182.880000 826.520000 2183.360000 ;
+ RECT 838.230000 2177.440000 839.230000 2177.920000 ;
+ RECT 838.230000 2182.880000 839.230000 2183.360000 ;
+ RECT 838.230000 2166.560000 839.230000 2167.040000 ;
+ RECT 838.230000 2161.120000 839.230000 2161.600000 ;
+ RECT 838.230000 2172.000000 839.230000 2172.480000 ;
+ RECT 825.420000 2172.000000 826.520000 2172.480000 ;
+ RECT 825.420000 2166.560000 826.520000 2167.040000 ;
+ RECT 825.420000 2161.120000 826.520000 2161.600000 ;
+ RECT 825.420000 2155.680000 826.520000 2156.160000 ;
+ RECT 838.230000 2155.680000 839.230000 2156.160000 ;
+ RECT 780.420000 2177.440000 781.520000 2177.920000 ;
+ RECT 780.420000 2182.880000 781.520000 2183.360000 ;
+ RECT 780.420000 2188.320000 781.520000 2188.800000 ;
+ RECT 780.420000 2193.760000 781.520000 2194.240000 ;
+ RECT 780.420000 2155.680000 781.520000 2156.160000 ;
+ RECT 780.420000 2161.120000 781.520000 2161.600000 ;
+ RECT 780.420000 2166.560000 781.520000 2167.040000 ;
+ RECT 780.420000 2172.000000 781.520000 2172.480000 ;
+ RECT 735.420000 2226.400000 736.520000 2226.880000 ;
+ RECT 735.420000 2231.840000 736.520000 2232.320000 ;
+ RECT 735.420000 2237.280000 736.520000 2237.760000 ;
+ RECT 735.420000 2242.720000 736.520000 2243.200000 ;
+ RECT 690.420000 2226.400000 691.520000 2226.880000 ;
+ RECT 690.420000 2231.840000 691.520000 2232.320000 ;
+ RECT 690.420000 2237.280000 691.520000 2237.760000 ;
+ RECT 690.420000 2242.720000 691.520000 2243.200000 ;
+ RECT 735.420000 2199.200000 736.520000 2199.680000 ;
+ RECT 735.420000 2204.640000 736.520000 2205.120000 ;
+ RECT 735.420000 2210.080000 736.520000 2210.560000 ;
+ RECT 735.420000 2215.520000 736.520000 2216.000000 ;
+ RECT 735.420000 2220.960000 736.520000 2221.440000 ;
+ RECT 690.420000 2199.200000 691.520000 2199.680000 ;
+ RECT 690.420000 2204.640000 691.520000 2205.120000 ;
+ RECT 690.420000 2210.080000 691.520000 2210.560000 ;
+ RECT 690.420000 2215.520000 691.520000 2216.000000 ;
+ RECT 690.420000 2220.960000 691.520000 2221.440000 ;
+ RECT 641.590000 2242.720000 642.590000 2243.200000 ;
+ RECT 645.255000 2242.720000 646.520000 2243.200000 ;
+ RECT 641.590000 2237.280000 642.590000 2237.760000 ;
+ RECT 645.255000 2237.280000 646.520000 2237.760000 ;
+ RECT 641.590000 2231.840000 642.590000 2232.320000 ;
+ RECT 645.255000 2231.840000 646.520000 2232.320000 ;
+ RECT 641.590000 2226.400000 642.590000 2226.880000 ;
+ RECT 645.255000 2226.400000 646.520000 2226.880000 ;
+ RECT 641.590000 2220.960000 642.590000 2221.440000 ;
+ RECT 645.255000 2220.960000 646.520000 2221.440000 ;
+ RECT 641.590000 2215.520000 642.590000 2216.000000 ;
+ RECT 645.255000 2215.520000 646.520000 2216.000000 ;
+ RECT 641.590000 2204.640000 642.590000 2205.120000 ;
+ RECT 645.255000 2204.640000 646.520000 2205.120000 ;
+ RECT 641.590000 2210.080000 642.590000 2210.560000 ;
+ RECT 645.255000 2210.080000 646.520000 2210.560000 ;
+ RECT 641.590000 2199.200000 642.590000 2199.680000 ;
+ RECT 645.255000 2199.200000 646.520000 2199.680000 ;
+ RECT 735.420000 2177.440000 736.520000 2177.920000 ;
+ RECT 735.420000 2182.880000 736.520000 2183.360000 ;
+ RECT 735.420000 2188.320000 736.520000 2188.800000 ;
+ RECT 735.420000 2193.760000 736.520000 2194.240000 ;
+ RECT 690.420000 2177.440000 691.520000 2177.920000 ;
+ RECT 690.420000 2182.880000 691.520000 2183.360000 ;
+ RECT 690.420000 2188.320000 691.520000 2188.800000 ;
+ RECT 690.420000 2193.760000 691.520000 2194.240000 ;
+ RECT 735.420000 2155.680000 736.520000 2156.160000 ;
+ RECT 735.420000 2161.120000 736.520000 2161.600000 ;
+ RECT 735.420000 2166.560000 736.520000 2167.040000 ;
+ RECT 735.420000 2172.000000 736.520000 2172.480000 ;
+ RECT 690.420000 2155.680000 691.520000 2156.160000 ;
+ RECT 690.420000 2161.120000 691.520000 2161.600000 ;
+ RECT 690.420000 2166.560000 691.520000 2167.040000 ;
+ RECT 690.420000 2172.000000 691.520000 2172.480000 ;
+ RECT 641.590000 2193.760000 642.590000 2194.240000 ;
+ RECT 645.255000 2193.760000 646.520000 2194.240000 ;
+ RECT 641.590000 2188.320000 642.590000 2188.800000 ;
+ RECT 645.255000 2188.320000 646.520000 2188.800000 ;
+ RECT 641.590000 2182.880000 642.590000 2183.360000 ;
+ RECT 645.255000 2182.880000 646.520000 2183.360000 ;
+ RECT 641.590000 2177.440000 642.590000 2177.920000 ;
+ RECT 645.255000 2177.440000 646.520000 2177.920000 ;
+ RECT 641.590000 2172.000000 642.590000 2172.480000 ;
+ RECT 645.255000 2172.000000 646.520000 2172.480000 ;
+ RECT 641.590000 2161.120000 642.590000 2161.600000 ;
+ RECT 645.255000 2161.120000 646.520000 2161.600000 ;
+ RECT 641.590000 2166.560000 642.590000 2167.040000 ;
+ RECT 645.255000 2166.560000 646.520000 2167.040000 ;
+ RECT 641.590000 2155.680000 642.590000 2156.160000 ;
+ RECT 645.255000 2155.680000 646.520000 2156.160000 ;
+ RECT 780.420000 2248.160000 781.520000 2248.640000 ;
+ RECT 825.420000 2248.160000 826.520000 2248.640000 ;
+ RECT 838.230000 2248.160000 839.230000 2248.640000 ;
+ RECT 690.420000 2248.160000 691.520000 2248.640000 ;
+ RECT 735.420000 2248.160000 736.520000 2248.640000 ;
+ RECT 641.590000 2248.160000 642.590000 2248.640000 ;
+ RECT 645.255000 2248.160000 646.520000 2248.640000 ;
+ RECT 640.360000 2344.920000 840.460000 2345.920000 ;
+ RECT 640.360000 2149.350000 840.460000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 2148.100000 642.590000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 2347.360000 642.590000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 2148.100000 839.230000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 2347.360000 839.230000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2149.350000 641.360000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2149.350000 840.460000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2344.920000 641.360000 2345.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2344.920000 840.460000 2345.920000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 2140.380000 646.520000 2140.860000 ;
+ RECT 645.255000 2129.500000 646.520000 2129.980000 ;
+ RECT 645.255000 2134.940000 646.520000 2135.420000 ;
+ RECT 645.255000 2124.060000 646.520000 2124.540000 ;
+ RECT 645.255000 2118.620000 646.520000 2119.100000 ;
+ RECT 645.255000 2113.180000 646.520000 2113.660000 ;
+ RECT 645.255000 2107.740000 646.520000 2108.220000 ;
+ RECT 645.255000 2102.300000 646.520000 2102.780000 ;
+ RECT 645.255000 2096.860000 646.520000 2097.340000 ;
+ RECT 645.255000 2085.980000 646.520000 2086.460000 ;
+ RECT 645.255000 2091.420000 646.520000 2091.900000 ;
+ RECT 645.255000 2080.540000 646.520000 2081.020000 ;
+ RECT 645.255000 2075.100000 646.520000 2075.580000 ;
+ RECT 645.255000 2069.660000 646.520000 2070.140000 ;
+ RECT 645.255000 2064.220000 646.520000 2064.700000 ;
+ RECT 645.255000 2058.780000 646.520000 2059.260000 ;
+ RECT 645.255000 2053.340000 646.520000 2053.820000 ;
+ RECT 645.255000 2042.460000 646.520000 2042.940000 ;
+ RECT 645.255000 2037.020000 646.520000 2037.500000 ;
+ RECT 645.255000 2031.580000 646.520000 2032.060000 ;
+ RECT 645.255000 2026.140000 646.520000 2026.620000 ;
+ RECT 645.255000 2020.700000 646.520000 2021.180000 ;
+ RECT 645.255000 2015.260000 646.520000 2015.740000 ;
+ RECT 645.255000 2004.380000 646.520000 2004.860000 ;
+ RECT 645.255000 2009.820000 646.520000 2010.300000 ;
+ RECT 645.255000 1998.940000 646.520000 1999.420000 ;
+ RECT 645.255000 1993.500000 646.520000 1993.980000 ;
+ RECT 645.255000 1988.060000 646.520000 1988.540000 ;
+ RECT 645.255000 1982.620000 646.520000 1983.100000 ;
+ RECT 645.255000 1977.180000 646.520000 1977.660000 ;
+ RECT 645.255000 1971.740000 646.520000 1972.220000 ;
+ RECT 645.255000 1960.860000 646.520000 1961.340000 ;
+ RECT 645.255000 1966.300000 646.520000 1966.780000 ;
+ RECT 645.255000 1955.420000 646.520000 1955.900000 ;
+ RECT 645.255000 2047.900000 646.520000 2048.380000 ;
+ RECT 825.420000 1949.090000 826.520000 2145.660000 ;
+ RECT 780.420000 1949.090000 781.520000 2145.660000 ;
+ RECT 838.230000 1947.840000 839.230000 2148.100000 ;
+ RECT 735.420000 1949.090000 736.520000 2145.660000 ;
+ RECT 690.420000 1949.090000 691.520000 2145.660000 ;
+ RECT 645.420000 1949.090000 646.520000 2145.660000 ;
+ RECT 641.590000 1947.840000 642.590000 2148.100000 ;
+ LAYER met3 ;
+ RECT 825.420000 2140.380000 826.520000 2140.860000 ;
+ RECT 838.230000 2140.380000 839.230000 2140.860000 ;
+ RECT 838.230000 2129.500000 839.230000 2129.980000 ;
+ RECT 838.230000 2124.060000 839.230000 2124.540000 ;
+ RECT 838.230000 2134.940000 839.230000 2135.420000 ;
+ RECT 825.420000 2134.940000 826.520000 2135.420000 ;
+ RECT 825.420000 2129.500000 826.520000 2129.980000 ;
+ RECT 825.420000 2124.060000 826.520000 2124.540000 ;
+ RECT 825.420000 2113.180000 826.520000 2113.660000 ;
+ RECT 825.420000 2118.620000 826.520000 2119.100000 ;
+ RECT 838.230000 2113.180000 839.230000 2113.660000 ;
+ RECT 838.230000 2118.620000 839.230000 2119.100000 ;
+ RECT 825.420000 2102.300000 826.520000 2102.780000 ;
+ RECT 825.420000 2107.740000 826.520000 2108.220000 ;
+ RECT 838.230000 2102.300000 839.230000 2102.780000 ;
+ RECT 838.230000 2107.740000 839.230000 2108.220000 ;
+ RECT 780.420000 2124.060000 781.520000 2124.540000 ;
+ RECT 780.420000 2129.500000 781.520000 2129.980000 ;
+ RECT 780.420000 2134.940000 781.520000 2135.420000 ;
+ RECT 780.420000 2140.380000 781.520000 2140.860000 ;
+ RECT 780.420000 2107.740000 781.520000 2108.220000 ;
+ RECT 780.420000 2102.300000 781.520000 2102.780000 ;
+ RECT 780.420000 2113.180000 781.520000 2113.660000 ;
+ RECT 780.420000 2118.620000 781.520000 2119.100000 ;
+ RECT 838.230000 2091.420000 839.230000 2091.900000 ;
+ RECT 838.230000 2085.980000 839.230000 2086.460000 ;
+ RECT 838.230000 2096.860000 839.230000 2097.340000 ;
+ RECT 825.420000 2096.860000 826.520000 2097.340000 ;
+ RECT 825.420000 2091.420000 826.520000 2091.900000 ;
+ RECT 825.420000 2085.980000 826.520000 2086.460000 ;
+ RECT 825.420000 2075.100000 826.520000 2075.580000 ;
+ RECT 825.420000 2080.540000 826.520000 2081.020000 ;
+ RECT 838.230000 2075.100000 839.230000 2075.580000 ;
+ RECT 838.230000 2080.540000 839.230000 2081.020000 ;
+ RECT 838.230000 2064.220000 839.230000 2064.700000 ;
+ RECT 838.230000 2069.660000 839.230000 2070.140000 ;
+ RECT 825.420000 2069.660000 826.520000 2070.140000 ;
+ RECT 825.420000 2064.220000 826.520000 2064.700000 ;
+ RECT 825.420000 2053.340000 826.520000 2053.820000 ;
+ RECT 825.420000 2058.780000 826.520000 2059.260000 ;
+ RECT 838.230000 2053.340000 839.230000 2053.820000 ;
+ RECT 838.230000 2058.780000 839.230000 2059.260000 ;
+ RECT 780.420000 2075.100000 781.520000 2075.580000 ;
+ RECT 780.420000 2080.540000 781.520000 2081.020000 ;
+ RECT 780.420000 2085.980000 781.520000 2086.460000 ;
+ RECT 780.420000 2091.420000 781.520000 2091.900000 ;
+ RECT 780.420000 2096.860000 781.520000 2097.340000 ;
+ RECT 780.420000 2053.340000 781.520000 2053.820000 ;
+ RECT 780.420000 2058.780000 781.520000 2059.260000 ;
+ RECT 780.420000 2064.220000 781.520000 2064.700000 ;
+ RECT 780.420000 2069.660000 781.520000 2070.140000 ;
+ RECT 735.420000 2129.500000 736.520000 2129.980000 ;
+ RECT 735.420000 2124.060000 736.520000 2124.540000 ;
+ RECT 735.420000 2134.940000 736.520000 2135.420000 ;
+ RECT 735.420000 2140.380000 736.520000 2140.860000 ;
+ RECT 690.420000 2124.060000 691.520000 2124.540000 ;
+ RECT 690.420000 2129.500000 691.520000 2129.980000 ;
+ RECT 690.420000 2134.940000 691.520000 2135.420000 ;
+ RECT 690.420000 2140.380000 691.520000 2140.860000 ;
+ RECT 735.420000 2102.300000 736.520000 2102.780000 ;
+ RECT 735.420000 2107.740000 736.520000 2108.220000 ;
+ RECT 735.420000 2113.180000 736.520000 2113.660000 ;
+ RECT 735.420000 2118.620000 736.520000 2119.100000 ;
+ RECT 690.420000 2102.300000 691.520000 2102.780000 ;
+ RECT 690.420000 2107.740000 691.520000 2108.220000 ;
+ RECT 690.420000 2113.180000 691.520000 2113.660000 ;
+ RECT 690.420000 2118.620000 691.520000 2119.100000 ;
+ RECT 641.590000 2140.380000 642.590000 2140.860000 ;
+ RECT 645.255000 2140.380000 646.520000 2140.860000 ;
+ RECT 641.590000 2129.500000 642.590000 2129.980000 ;
+ RECT 645.255000 2129.500000 646.520000 2129.980000 ;
+ RECT 641.590000 2134.940000 642.590000 2135.420000 ;
+ RECT 645.255000 2134.940000 646.520000 2135.420000 ;
+ RECT 641.590000 2124.060000 642.590000 2124.540000 ;
+ RECT 645.255000 2124.060000 646.520000 2124.540000 ;
+ RECT 641.590000 2118.620000 642.590000 2119.100000 ;
+ RECT 645.255000 2118.620000 646.520000 2119.100000 ;
+ RECT 641.590000 2113.180000 642.590000 2113.660000 ;
+ RECT 645.255000 2113.180000 646.520000 2113.660000 ;
+ RECT 641.590000 2107.740000 642.590000 2108.220000 ;
+ RECT 645.255000 2107.740000 646.520000 2108.220000 ;
+ RECT 641.590000 2102.300000 642.590000 2102.780000 ;
+ RECT 645.255000 2102.300000 646.520000 2102.780000 ;
+ RECT 735.420000 2075.100000 736.520000 2075.580000 ;
+ RECT 735.420000 2080.540000 736.520000 2081.020000 ;
+ RECT 735.420000 2085.980000 736.520000 2086.460000 ;
+ RECT 735.420000 2091.420000 736.520000 2091.900000 ;
+ RECT 735.420000 2096.860000 736.520000 2097.340000 ;
+ RECT 690.420000 2075.100000 691.520000 2075.580000 ;
+ RECT 690.420000 2080.540000 691.520000 2081.020000 ;
+ RECT 690.420000 2085.980000 691.520000 2086.460000 ;
+ RECT 690.420000 2091.420000 691.520000 2091.900000 ;
+ RECT 690.420000 2096.860000 691.520000 2097.340000 ;
+ RECT 735.420000 2053.340000 736.520000 2053.820000 ;
+ RECT 735.420000 2058.780000 736.520000 2059.260000 ;
+ RECT 735.420000 2064.220000 736.520000 2064.700000 ;
+ RECT 735.420000 2069.660000 736.520000 2070.140000 ;
+ RECT 690.420000 2053.340000 691.520000 2053.820000 ;
+ RECT 690.420000 2058.780000 691.520000 2059.260000 ;
+ RECT 690.420000 2064.220000 691.520000 2064.700000 ;
+ RECT 690.420000 2069.660000 691.520000 2070.140000 ;
+ RECT 641.590000 2096.860000 642.590000 2097.340000 ;
+ RECT 645.255000 2096.860000 646.520000 2097.340000 ;
+ RECT 641.590000 2085.980000 642.590000 2086.460000 ;
+ RECT 645.255000 2085.980000 646.520000 2086.460000 ;
+ RECT 641.590000 2091.420000 642.590000 2091.900000 ;
+ RECT 645.255000 2091.420000 646.520000 2091.900000 ;
+ RECT 641.590000 2080.540000 642.590000 2081.020000 ;
+ RECT 645.255000 2080.540000 646.520000 2081.020000 ;
+ RECT 641.590000 2075.100000 642.590000 2075.580000 ;
+ RECT 645.255000 2075.100000 646.520000 2075.580000 ;
+ RECT 641.590000 2069.660000 642.590000 2070.140000 ;
+ RECT 645.255000 2069.660000 646.520000 2070.140000 ;
+ RECT 641.590000 2064.220000 642.590000 2064.700000 ;
+ RECT 645.255000 2064.220000 646.520000 2064.700000 ;
+ RECT 641.590000 2058.780000 642.590000 2059.260000 ;
+ RECT 645.255000 2058.780000 646.520000 2059.260000 ;
+ RECT 641.590000 2053.340000 642.590000 2053.820000 ;
+ RECT 645.255000 2053.340000 646.520000 2053.820000 ;
+ RECT 825.420000 2037.020000 826.520000 2037.500000 ;
+ RECT 825.420000 2042.460000 826.520000 2042.940000 ;
+ RECT 838.230000 2037.020000 839.230000 2037.500000 ;
+ RECT 838.230000 2042.460000 839.230000 2042.940000 ;
+ RECT 838.230000 2026.140000 839.230000 2026.620000 ;
+ RECT 838.230000 2031.580000 839.230000 2032.060000 ;
+ RECT 825.420000 2031.580000 826.520000 2032.060000 ;
+ RECT 825.420000 2026.140000 826.520000 2026.620000 ;
+ RECT 825.420000 2015.260000 826.520000 2015.740000 ;
+ RECT 825.420000 2020.700000 826.520000 2021.180000 ;
+ RECT 838.230000 2015.260000 839.230000 2015.740000 ;
+ RECT 838.230000 2020.700000 839.230000 2021.180000 ;
+ RECT 838.230000 2004.380000 839.230000 2004.860000 ;
+ RECT 838.230000 1998.940000 839.230000 1999.420000 ;
+ RECT 838.230000 2009.820000 839.230000 2010.300000 ;
+ RECT 825.420000 2009.820000 826.520000 2010.300000 ;
+ RECT 825.420000 2004.380000 826.520000 2004.860000 ;
+ RECT 825.420000 1998.940000 826.520000 1999.420000 ;
+ RECT 780.420000 2026.140000 781.520000 2026.620000 ;
+ RECT 780.420000 2031.580000 781.520000 2032.060000 ;
+ RECT 780.420000 2037.020000 781.520000 2037.500000 ;
+ RECT 780.420000 2042.460000 781.520000 2042.940000 ;
+ RECT 780.420000 1998.940000 781.520000 1999.420000 ;
+ RECT 780.420000 2004.380000 781.520000 2004.860000 ;
+ RECT 780.420000 2009.820000 781.520000 2010.300000 ;
+ RECT 780.420000 2015.260000 781.520000 2015.740000 ;
+ RECT 780.420000 2020.700000 781.520000 2021.180000 ;
+ RECT 825.420000 1988.060000 826.520000 1988.540000 ;
+ RECT 825.420000 1993.500000 826.520000 1993.980000 ;
+ RECT 838.230000 1988.060000 839.230000 1988.540000 ;
+ RECT 838.230000 1993.500000 839.230000 1993.980000 ;
+ RECT 825.420000 1977.180000 826.520000 1977.660000 ;
+ RECT 825.420000 1982.620000 826.520000 1983.100000 ;
+ RECT 838.230000 1977.180000 839.230000 1977.660000 ;
+ RECT 838.230000 1982.620000 839.230000 1983.100000 ;
+ RECT 838.230000 1966.300000 839.230000 1966.780000 ;
+ RECT 838.230000 1960.860000 839.230000 1961.340000 ;
+ RECT 838.230000 1971.740000 839.230000 1972.220000 ;
+ RECT 825.420000 1971.740000 826.520000 1972.220000 ;
+ RECT 825.420000 1966.300000 826.520000 1966.780000 ;
+ RECT 825.420000 1960.860000 826.520000 1961.340000 ;
+ RECT 825.420000 1955.420000 826.520000 1955.900000 ;
+ RECT 838.230000 1955.420000 839.230000 1955.900000 ;
+ RECT 780.420000 1977.180000 781.520000 1977.660000 ;
+ RECT 780.420000 1982.620000 781.520000 1983.100000 ;
+ RECT 780.420000 1988.060000 781.520000 1988.540000 ;
+ RECT 780.420000 1993.500000 781.520000 1993.980000 ;
+ RECT 780.420000 1955.420000 781.520000 1955.900000 ;
+ RECT 780.420000 1960.860000 781.520000 1961.340000 ;
+ RECT 780.420000 1966.300000 781.520000 1966.780000 ;
+ RECT 780.420000 1971.740000 781.520000 1972.220000 ;
+ RECT 735.420000 2026.140000 736.520000 2026.620000 ;
+ RECT 735.420000 2031.580000 736.520000 2032.060000 ;
+ RECT 735.420000 2037.020000 736.520000 2037.500000 ;
+ RECT 735.420000 2042.460000 736.520000 2042.940000 ;
+ RECT 690.420000 2026.140000 691.520000 2026.620000 ;
+ RECT 690.420000 2031.580000 691.520000 2032.060000 ;
+ RECT 690.420000 2037.020000 691.520000 2037.500000 ;
+ RECT 690.420000 2042.460000 691.520000 2042.940000 ;
+ RECT 735.420000 1998.940000 736.520000 1999.420000 ;
+ RECT 735.420000 2004.380000 736.520000 2004.860000 ;
+ RECT 735.420000 2009.820000 736.520000 2010.300000 ;
+ RECT 735.420000 2015.260000 736.520000 2015.740000 ;
+ RECT 735.420000 2020.700000 736.520000 2021.180000 ;
+ RECT 690.420000 1998.940000 691.520000 1999.420000 ;
+ RECT 690.420000 2004.380000 691.520000 2004.860000 ;
+ RECT 690.420000 2009.820000 691.520000 2010.300000 ;
+ RECT 690.420000 2015.260000 691.520000 2015.740000 ;
+ RECT 690.420000 2020.700000 691.520000 2021.180000 ;
+ RECT 641.590000 2042.460000 642.590000 2042.940000 ;
+ RECT 645.255000 2042.460000 646.520000 2042.940000 ;
+ RECT 641.590000 2037.020000 642.590000 2037.500000 ;
+ RECT 645.255000 2037.020000 646.520000 2037.500000 ;
+ RECT 641.590000 2031.580000 642.590000 2032.060000 ;
+ RECT 645.255000 2031.580000 646.520000 2032.060000 ;
+ RECT 641.590000 2026.140000 642.590000 2026.620000 ;
+ RECT 645.255000 2026.140000 646.520000 2026.620000 ;
+ RECT 641.590000 2020.700000 642.590000 2021.180000 ;
+ RECT 645.255000 2020.700000 646.520000 2021.180000 ;
+ RECT 641.590000 2015.260000 642.590000 2015.740000 ;
+ RECT 645.255000 2015.260000 646.520000 2015.740000 ;
+ RECT 641.590000 2004.380000 642.590000 2004.860000 ;
+ RECT 645.255000 2004.380000 646.520000 2004.860000 ;
+ RECT 641.590000 2009.820000 642.590000 2010.300000 ;
+ RECT 645.255000 2009.820000 646.520000 2010.300000 ;
+ RECT 641.590000 1998.940000 642.590000 1999.420000 ;
+ RECT 645.255000 1998.940000 646.520000 1999.420000 ;
+ RECT 735.420000 1977.180000 736.520000 1977.660000 ;
+ RECT 735.420000 1982.620000 736.520000 1983.100000 ;
+ RECT 735.420000 1988.060000 736.520000 1988.540000 ;
+ RECT 735.420000 1993.500000 736.520000 1993.980000 ;
+ RECT 690.420000 1977.180000 691.520000 1977.660000 ;
+ RECT 690.420000 1982.620000 691.520000 1983.100000 ;
+ RECT 690.420000 1988.060000 691.520000 1988.540000 ;
+ RECT 690.420000 1993.500000 691.520000 1993.980000 ;
+ RECT 735.420000 1955.420000 736.520000 1955.900000 ;
+ RECT 735.420000 1960.860000 736.520000 1961.340000 ;
+ RECT 735.420000 1966.300000 736.520000 1966.780000 ;
+ RECT 735.420000 1971.740000 736.520000 1972.220000 ;
+ RECT 690.420000 1955.420000 691.520000 1955.900000 ;
+ RECT 690.420000 1960.860000 691.520000 1961.340000 ;
+ RECT 690.420000 1966.300000 691.520000 1966.780000 ;
+ RECT 690.420000 1971.740000 691.520000 1972.220000 ;
+ RECT 641.590000 1993.500000 642.590000 1993.980000 ;
+ RECT 645.255000 1993.500000 646.520000 1993.980000 ;
+ RECT 641.590000 1988.060000 642.590000 1988.540000 ;
+ RECT 645.255000 1988.060000 646.520000 1988.540000 ;
+ RECT 641.590000 1982.620000 642.590000 1983.100000 ;
+ RECT 645.255000 1982.620000 646.520000 1983.100000 ;
+ RECT 641.590000 1977.180000 642.590000 1977.660000 ;
+ RECT 645.255000 1977.180000 646.520000 1977.660000 ;
+ RECT 641.590000 1971.740000 642.590000 1972.220000 ;
+ RECT 645.255000 1971.740000 646.520000 1972.220000 ;
+ RECT 641.590000 1960.860000 642.590000 1961.340000 ;
+ RECT 645.255000 1960.860000 646.520000 1961.340000 ;
+ RECT 641.590000 1966.300000 642.590000 1966.780000 ;
+ RECT 645.255000 1966.300000 646.520000 1966.780000 ;
+ RECT 641.590000 1955.420000 642.590000 1955.900000 ;
+ RECT 645.255000 1955.420000 646.520000 1955.900000 ;
+ RECT 780.420000 2047.900000 781.520000 2048.380000 ;
+ RECT 825.420000 2047.900000 826.520000 2048.380000 ;
+ RECT 838.230000 2047.900000 839.230000 2048.380000 ;
+ RECT 690.420000 2047.900000 691.520000 2048.380000 ;
+ RECT 735.420000 2047.900000 736.520000 2048.380000 ;
+ RECT 641.590000 2047.900000 642.590000 2048.380000 ;
+ RECT 645.255000 2047.900000 646.520000 2048.380000 ;
+ RECT 640.360000 2144.660000 840.460000 2145.660000 ;
+ RECT 640.360000 1949.090000 840.460000 1950.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 1947.840000 642.590000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 2147.100000 642.590000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 1947.840000 839.230000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 2147.100000 839.230000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1949.090000 641.360000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1949.090000 840.460000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2144.660000 641.360000 2145.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2144.660000 840.460000 2145.660000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 1940.120000 646.520000 1940.600000 ;
+ RECT 645.255000 1929.240000 646.520000 1929.720000 ;
+ RECT 645.255000 1934.680000 646.520000 1935.160000 ;
+ RECT 645.255000 1923.800000 646.520000 1924.280000 ;
+ RECT 645.255000 1918.360000 646.520000 1918.840000 ;
+ RECT 645.255000 1912.920000 646.520000 1913.400000 ;
+ RECT 645.255000 1907.480000 646.520000 1907.960000 ;
+ RECT 645.255000 1902.040000 646.520000 1902.520000 ;
+ RECT 645.255000 1896.600000 646.520000 1897.080000 ;
+ RECT 645.255000 1885.720000 646.520000 1886.200000 ;
+ RECT 645.255000 1891.160000 646.520000 1891.640000 ;
+ RECT 645.255000 1880.280000 646.520000 1880.760000 ;
+ RECT 645.255000 1874.840000 646.520000 1875.320000 ;
+ RECT 645.255000 1869.400000 646.520000 1869.880000 ;
+ RECT 645.255000 1863.960000 646.520000 1864.440000 ;
+ RECT 645.255000 1858.520000 646.520000 1859.000000 ;
+ RECT 645.255000 1853.080000 646.520000 1853.560000 ;
+ RECT 645.255000 1842.200000 646.520000 1842.680000 ;
+ RECT 645.255000 1836.760000 646.520000 1837.240000 ;
+ RECT 645.255000 1831.320000 646.520000 1831.800000 ;
+ RECT 645.255000 1825.880000 646.520000 1826.360000 ;
+ RECT 645.255000 1820.440000 646.520000 1820.920000 ;
+ RECT 645.255000 1815.000000 646.520000 1815.480000 ;
+ RECT 645.255000 1804.120000 646.520000 1804.600000 ;
+ RECT 645.255000 1809.560000 646.520000 1810.040000 ;
+ RECT 645.255000 1798.680000 646.520000 1799.160000 ;
+ RECT 645.255000 1793.240000 646.520000 1793.720000 ;
+ RECT 645.255000 1787.800000 646.520000 1788.280000 ;
+ RECT 645.255000 1782.360000 646.520000 1782.840000 ;
+ RECT 645.255000 1776.920000 646.520000 1777.400000 ;
+ RECT 645.255000 1771.480000 646.520000 1771.960000 ;
+ RECT 645.255000 1760.600000 646.520000 1761.080000 ;
+ RECT 645.255000 1766.040000 646.520000 1766.520000 ;
+ RECT 645.255000 1755.160000 646.520000 1755.640000 ;
+ RECT 645.255000 1847.640000 646.520000 1848.120000 ;
+ RECT 825.420000 1748.830000 826.520000 1945.400000 ;
+ RECT 780.420000 1748.830000 781.520000 1945.400000 ;
+ RECT 838.230000 1747.580000 839.230000 1947.840000 ;
+ RECT 735.420000 1748.830000 736.520000 1945.400000 ;
+ RECT 690.420000 1748.830000 691.520000 1945.400000 ;
+ RECT 645.420000 1748.830000 646.520000 1945.400000 ;
+ RECT 641.590000 1747.580000 642.590000 1947.840000 ;
+ LAYER met3 ;
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+ RECT 838.230000 1940.120000 839.230000 1940.600000 ;
+ RECT 838.230000 1929.240000 839.230000 1929.720000 ;
+ RECT 838.230000 1923.800000 839.230000 1924.280000 ;
+ RECT 838.230000 1934.680000 839.230000 1935.160000 ;
+ RECT 825.420000 1934.680000 826.520000 1935.160000 ;
+ RECT 825.420000 1929.240000 826.520000 1929.720000 ;
+ RECT 825.420000 1923.800000 826.520000 1924.280000 ;
+ RECT 825.420000 1912.920000 826.520000 1913.400000 ;
+ RECT 825.420000 1918.360000 826.520000 1918.840000 ;
+ RECT 838.230000 1912.920000 839.230000 1913.400000 ;
+ RECT 838.230000 1918.360000 839.230000 1918.840000 ;
+ RECT 825.420000 1902.040000 826.520000 1902.520000 ;
+ RECT 825.420000 1907.480000 826.520000 1907.960000 ;
+ RECT 838.230000 1902.040000 839.230000 1902.520000 ;
+ RECT 838.230000 1907.480000 839.230000 1907.960000 ;
+ RECT 780.420000 1923.800000 781.520000 1924.280000 ;
+ RECT 780.420000 1929.240000 781.520000 1929.720000 ;
+ RECT 780.420000 1934.680000 781.520000 1935.160000 ;
+ RECT 780.420000 1940.120000 781.520000 1940.600000 ;
+ RECT 780.420000 1907.480000 781.520000 1907.960000 ;
+ RECT 780.420000 1902.040000 781.520000 1902.520000 ;
+ RECT 780.420000 1912.920000 781.520000 1913.400000 ;
+ RECT 780.420000 1918.360000 781.520000 1918.840000 ;
+ RECT 838.230000 1891.160000 839.230000 1891.640000 ;
+ RECT 838.230000 1885.720000 839.230000 1886.200000 ;
+ RECT 838.230000 1896.600000 839.230000 1897.080000 ;
+ RECT 825.420000 1896.600000 826.520000 1897.080000 ;
+ RECT 825.420000 1891.160000 826.520000 1891.640000 ;
+ RECT 825.420000 1885.720000 826.520000 1886.200000 ;
+ RECT 825.420000 1874.840000 826.520000 1875.320000 ;
+ RECT 825.420000 1880.280000 826.520000 1880.760000 ;
+ RECT 838.230000 1874.840000 839.230000 1875.320000 ;
+ RECT 838.230000 1880.280000 839.230000 1880.760000 ;
+ RECT 838.230000 1863.960000 839.230000 1864.440000 ;
+ RECT 838.230000 1869.400000 839.230000 1869.880000 ;
+ RECT 825.420000 1869.400000 826.520000 1869.880000 ;
+ RECT 825.420000 1863.960000 826.520000 1864.440000 ;
+ RECT 825.420000 1853.080000 826.520000 1853.560000 ;
+ RECT 825.420000 1858.520000 826.520000 1859.000000 ;
+ RECT 838.230000 1853.080000 839.230000 1853.560000 ;
+ RECT 838.230000 1858.520000 839.230000 1859.000000 ;
+ RECT 780.420000 1874.840000 781.520000 1875.320000 ;
+ RECT 780.420000 1880.280000 781.520000 1880.760000 ;
+ RECT 780.420000 1885.720000 781.520000 1886.200000 ;
+ RECT 780.420000 1891.160000 781.520000 1891.640000 ;
+ RECT 780.420000 1896.600000 781.520000 1897.080000 ;
+ RECT 780.420000 1853.080000 781.520000 1853.560000 ;
+ RECT 780.420000 1858.520000 781.520000 1859.000000 ;
+ RECT 780.420000 1863.960000 781.520000 1864.440000 ;
+ RECT 780.420000 1869.400000 781.520000 1869.880000 ;
+ RECT 735.420000 1929.240000 736.520000 1929.720000 ;
+ RECT 735.420000 1923.800000 736.520000 1924.280000 ;
+ RECT 735.420000 1934.680000 736.520000 1935.160000 ;
+ RECT 735.420000 1940.120000 736.520000 1940.600000 ;
+ RECT 690.420000 1923.800000 691.520000 1924.280000 ;
+ RECT 690.420000 1929.240000 691.520000 1929.720000 ;
+ RECT 690.420000 1934.680000 691.520000 1935.160000 ;
+ RECT 690.420000 1940.120000 691.520000 1940.600000 ;
+ RECT 735.420000 1902.040000 736.520000 1902.520000 ;
+ RECT 735.420000 1907.480000 736.520000 1907.960000 ;
+ RECT 735.420000 1912.920000 736.520000 1913.400000 ;
+ RECT 735.420000 1918.360000 736.520000 1918.840000 ;
+ RECT 690.420000 1902.040000 691.520000 1902.520000 ;
+ RECT 690.420000 1907.480000 691.520000 1907.960000 ;
+ RECT 690.420000 1912.920000 691.520000 1913.400000 ;
+ RECT 690.420000 1918.360000 691.520000 1918.840000 ;
+ RECT 641.590000 1940.120000 642.590000 1940.600000 ;
+ RECT 645.255000 1940.120000 646.520000 1940.600000 ;
+ RECT 641.590000 1929.240000 642.590000 1929.720000 ;
+ RECT 645.255000 1929.240000 646.520000 1929.720000 ;
+ RECT 641.590000 1934.680000 642.590000 1935.160000 ;
+ RECT 645.255000 1934.680000 646.520000 1935.160000 ;
+ RECT 641.590000 1923.800000 642.590000 1924.280000 ;
+ RECT 645.255000 1923.800000 646.520000 1924.280000 ;
+ RECT 641.590000 1918.360000 642.590000 1918.840000 ;
+ RECT 645.255000 1918.360000 646.520000 1918.840000 ;
+ RECT 641.590000 1912.920000 642.590000 1913.400000 ;
+ RECT 645.255000 1912.920000 646.520000 1913.400000 ;
+ RECT 641.590000 1907.480000 642.590000 1907.960000 ;
+ RECT 645.255000 1907.480000 646.520000 1907.960000 ;
+ RECT 641.590000 1902.040000 642.590000 1902.520000 ;
+ RECT 645.255000 1902.040000 646.520000 1902.520000 ;
+ RECT 735.420000 1874.840000 736.520000 1875.320000 ;
+ RECT 735.420000 1880.280000 736.520000 1880.760000 ;
+ RECT 735.420000 1885.720000 736.520000 1886.200000 ;
+ RECT 735.420000 1891.160000 736.520000 1891.640000 ;
+ RECT 735.420000 1896.600000 736.520000 1897.080000 ;
+ RECT 690.420000 1874.840000 691.520000 1875.320000 ;
+ RECT 690.420000 1880.280000 691.520000 1880.760000 ;
+ RECT 690.420000 1885.720000 691.520000 1886.200000 ;
+ RECT 690.420000 1891.160000 691.520000 1891.640000 ;
+ RECT 690.420000 1896.600000 691.520000 1897.080000 ;
+ RECT 735.420000 1853.080000 736.520000 1853.560000 ;
+ RECT 735.420000 1858.520000 736.520000 1859.000000 ;
+ RECT 735.420000 1863.960000 736.520000 1864.440000 ;
+ RECT 735.420000 1869.400000 736.520000 1869.880000 ;
+ RECT 690.420000 1853.080000 691.520000 1853.560000 ;
+ RECT 690.420000 1858.520000 691.520000 1859.000000 ;
+ RECT 690.420000 1863.960000 691.520000 1864.440000 ;
+ RECT 690.420000 1869.400000 691.520000 1869.880000 ;
+ RECT 641.590000 1896.600000 642.590000 1897.080000 ;
+ RECT 645.255000 1896.600000 646.520000 1897.080000 ;
+ RECT 641.590000 1885.720000 642.590000 1886.200000 ;
+ RECT 645.255000 1885.720000 646.520000 1886.200000 ;
+ RECT 641.590000 1891.160000 642.590000 1891.640000 ;
+ RECT 645.255000 1891.160000 646.520000 1891.640000 ;
+ RECT 641.590000 1880.280000 642.590000 1880.760000 ;
+ RECT 645.255000 1880.280000 646.520000 1880.760000 ;
+ RECT 641.590000 1874.840000 642.590000 1875.320000 ;
+ RECT 645.255000 1874.840000 646.520000 1875.320000 ;
+ RECT 641.590000 1869.400000 642.590000 1869.880000 ;
+ RECT 645.255000 1869.400000 646.520000 1869.880000 ;
+ RECT 641.590000 1863.960000 642.590000 1864.440000 ;
+ RECT 645.255000 1863.960000 646.520000 1864.440000 ;
+ RECT 641.590000 1858.520000 642.590000 1859.000000 ;
+ RECT 645.255000 1858.520000 646.520000 1859.000000 ;
+ RECT 641.590000 1853.080000 642.590000 1853.560000 ;
+ RECT 645.255000 1853.080000 646.520000 1853.560000 ;
+ RECT 825.420000 1836.760000 826.520000 1837.240000 ;
+ RECT 825.420000 1842.200000 826.520000 1842.680000 ;
+ RECT 838.230000 1836.760000 839.230000 1837.240000 ;
+ RECT 838.230000 1842.200000 839.230000 1842.680000 ;
+ RECT 838.230000 1825.880000 839.230000 1826.360000 ;
+ RECT 838.230000 1831.320000 839.230000 1831.800000 ;
+ RECT 825.420000 1831.320000 826.520000 1831.800000 ;
+ RECT 825.420000 1825.880000 826.520000 1826.360000 ;
+ RECT 825.420000 1815.000000 826.520000 1815.480000 ;
+ RECT 825.420000 1820.440000 826.520000 1820.920000 ;
+ RECT 838.230000 1815.000000 839.230000 1815.480000 ;
+ RECT 838.230000 1820.440000 839.230000 1820.920000 ;
+ RECT 838.230000 1804.120000 839.230000 1804.600000 ;
+ RECT 838.230000 1798.680000 839.230000 1799.160000 ;
+ RECT 838.230000 1809.560000 839.230000 1810.040000 ;
+ RECT 825.420000 1809.560000 826.520000 1810.040000 ;
+ RECT 825.420000 1804.120000 826.520000 1804.600000 ;
+ RECT 825.420000 1798.680000 826.520000 1799.160000 ;
+ RECT 780.420000 1825.880000 781.520000 1826.360000 ;
+ RECT 780.420000 1831.320000 781.520000 1831.800000 ;
+ RECT 780.420000 1836.760000 781.520000 1837.240000 ;
+ RECT 780.420000 1842.200000 781.520000 1842.680000 ;
+ RECT 780.420000 1798.680000 781.520000 1799.160000 ;
+ RECT 780.420000 1804.120000 781.520000 1804.600000 ;
+ RECT 780.420000 1809.560000 781.520000 1810.040000 ;
+ RECT 780.420000 1815.000000 781.520000 1815.480000 ;
+ RECT 780.420000 1820.440000 781.520000 1820.920000 ;
+ RECT 825.420000 1787.800000 826.520000 1788.280000 ;
+ RECT 825.420000 1793.240000 826.520000 1793.720000 ;
+ RECT 838.230000 1787.800000 839.230000 1788.280000 ;
+ RECT 838.230000 1793.240000 839.230000 1793.720000 ;
+ RECT 825.420000 1776.920000 826.520000 1777.400000 ;
+ RECT 825.420000 1782.360000 826.520000 1782.840000 ;
+ RECT 838.230000 1776.920000 839.230000 1777.400000 ;
+ RECT 838.230000 1782.360000 839.230000 1782.840000 ;
+ RECT 838.230000 1766.040000 839.230000 1766.520000 ;
+ RECT 838.230000 1760.600000 839.230000 1761.080000 ;
+ RECT 838.230000 1771.480000 839.230000 1771.960000 ;
+ RECT 825.420000 1771.480000 826.520000 1771.960000 ;
+ RECT 825.420000 1766.040000 826.520000 1766.520000 ;
+ RECT 825.420000 1760.600000 826.520000 1761.080000 ;
+ RECT 825.420000 1755.160000 826.520000 1755.640000 ;
+ RECT 838.230000 1755.160000 839.230000 1755.640000 ;
+ RECT 780.420000 1776.920000 781.520000 1777.400000 ;
+ RECT 780.420000 1782.360000 781.520000 1782.840000 ;
+ RECT 780.420000 1787.800000 781.520000 1788.280000 ;
+ RECT 780.420000 1793.240000 781.520000 1793.720000 ;
+ RECT 780.420000 1755.160000 781.520000 1755.640000 ;
+ RECT 780.420000 1760.600000 781.520000 1761.080000 ;
+ RECT 780.420000 1766.040000 781.520000 1766.520000 ;
+ RECT 780.420000 1771.480000 781.520000 1771.960000 ;
+ RECT 735.420000 1825.880000 736.520000 1826.360000 ;
+ RECT 735.420000 1831.320000 736.520000 1831.800000 ;
+ RECT 735.420000 1836.760000 736.520000 1837.240000 ;
+ RECT 735.420000 1842.200000 736.520000 1842.680000 ;
+ RECT 690.420000 1825.880000 691.520000 1826.360000 ;
+ RECT 690.420000 1831.320000 691.520000 1831.800000 ;
+ RECT 690.420000 1836.760000 691.520000 1837.240000 ;
+ RECT 690.420000 1842.200000 691.520000 1842.680000 ;
+ RECT 735.420000 1798.680000 736.520000 1799.160000 ;
+ RECT 735.420000 1804.120000 736.520000 1804.600000 ;
+ RECT 735.420000 1809.560000 736.520000 1810.040000 ;
+ RECT 735.420000 1815.000000 736.520000 1815.480000 ;
+ RECT 735.420000 1820.440000 736.520000 1820.920000 ;
+ RECT 690.420000 1798.680000 691.520000 1799.160000 ;
+ RECT 690.420000 1804.120000 691.520000 1804.600000 ;
+ RECT 690.420000 1809.560000 691.520000 1810.040000 ;
+ RECT 690.420000 1815.000000 691.520000 1815.480000 ;
+ RECT 690.420000 1820.440000 691.520000 1820.920000 ;
+ RECT 641.590000 1842.200000 642.590000 1842.680000 ;
+ RECT 645.255000 1842.200000 646.520000 1842.680000 ;
+ RECT 641.590000 1836.760000 642.590000 1837.240000 ;
+ RECT 645.255000 1836.760000 646.520000 1837.240000 ;
+ RECT 641.590000 1831.320000 642.590000 1831.800000 ;
+ RECT 645.255000 1831.320000 646.520000 1831.800000 ;
+ RECT 641.590000 1825.880000 642.590000 1826.360000 ;
+ RECT 645.255000 1825.880000 646.520000 1826.360000 ;
+ RECT 641.590000 1820.440000 642.590000 1820.920000 ;
+ RECT 645.255000 1820.440000 646.520000 1820.920000 ;
+ RECT 641.590000 1815.000000 642.590000 1815.480000 ;
+ RECT 645.255000 1815.000000 646.520000 1815.480000 ;
+ RECT 641.590000 1804.120000 642.590000 1804.600000 ;
+ RECT 645.255000 1804.120000 646.520000 1804.600000 ;
+ RECT 641.590000 1809.560000 642.590000 1810.040000 ;
+ RECT 645.255000 1809.560000 646.520000 1810.040000 ;
+ RECT 641.590000 1798.680000 642.590000 1799.160000 ;
+ RECT 645.255000 1798.680000 646.520000 1799.160000 ;
+ RECT 735.420000 1776.920000 736.520000 1777.400000 ;
+ RECT 735.420000 1782.360000 736.520000 1782.840000 ;
+ RECT 735.420000 1787.800000 736.520000 1788.280000 ;
+ RECT 735.420000 1793.240000 736.520000 1793.720000 ;
+ RECT 690.420000 1776.920000 691.520000 1777.400000 ;
+ RECT 690.420000 1782.360000 691.520000 1782.840000 ;
+ RECT 690.420000 1787.800000 691.520000 1788.280000 ;
+ RECT 690.420000 1793.240000 691.520000 1793.720000 ;
+ RECT 735.420000 1755.160000 736.520000 1755.640000 ;
+ RECT 735.420000 1760.600000 736.520000 1761.080000 ;
+ RECT 735.420000 1766.040000 736.520000 1766.520000 ;
+ RECT 735.420000 1771.480000 736.520000 1771.960000 ;
+ RECT 690.420000 1755.160000 691.520000 1755.640000 ;
+ RECT 690.420000 1760.600000 691.520000 1761.080000 ;
+ RECT 690.420000 1766.040000 691.520000 1766.520000 ;
+ RECT 690.420000 1771.480000 691.520000 1771.960000 ;
+ RECT 641.590000 1793.240000 642.590000 1793.720000 ;
+ RECT 645.255000 1793.240000 646.520000 1793.720000 ;
+ RECT 641.590000 1787.800000 642.590000 1788.280000 ;
+ RECT 645.255000 1787.800000 646.520000 1788.280000 ;
+ RECT 641.590000 1782.360000 642.590000 1782.840000 ;
+ RECT 645.255000 1782.360000 646.520000 1782.840000 ;
+ RECT 641.590000 1776.920000 642.590000 1777.400000 ;
+ RECT 645.255000 1776.920000 646.520000 1777.400000 ;
+ RECT 641.590000 1771.480000 642.590000 1771.960000 ;
+ RECT 645.255000 1771.480000 646.520000 1771.960000 ;
+ RECT 641.590000 1760.600000 642.590000 1761.080000 ;
+ RECT 645.255000 1760.600000 646.520000 1761.080000 ;
+ RECT 641.590000 1766.040000 642.590000 1766.520000 ;
+ RECT 645.255000 1766.040000 646.520000 1766.520000 ;
+ RECT 641.590000 1755.160000 642.590000 1755.640000 ;
+ RECT 645.255000 1755.160000 646.520000 1755.640000 ;
+ RECT 780.420000 1847.640000 781.520000 1848.120000 ;
+ RECT 825.420000 1847.640000 826.520000 1848.120000 ;
+ RECT 838.230000 1847.640000 839.230000 1848.120000 ;
+ RECT 690.420000 1847.640000 691.520000 1848.120000 ;
+ RECT 735.420000 1847.640000 736.520000 1848.120000 ;
+ RECT 641.590000 1847.640000 642.590000 1848.120000 ;
+ RECT 645.255000 1847.640000 646.520000 1848.120000 ;
+ RECT 640.360000 1944.400000 840.460000 1945.400000 ;
+ RECT 640.360000 1748.830000 840.460000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 1747.580000 642.590000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 1946.840000 642.590000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 1747.580000 839.230000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 1946.840000 839.230000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1748.830000 641.360000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1748.830000 840.460000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1944.400000 641.360000 1945.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1944.400000 840.460000 1945.400000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 645.255000 1739.860000 646.520000 1740.340000 ;
+ RECT 645.255000 1728.980000 646.520000 1729.460000 ;
+ RECT 645.255000 1734.420000 646.520000 1734.900000 ;
+ RECT 645.255000 1723.540000 646.520000 1724.020000 ;
+ RECT 645.255000 1718.100000 646.520000 1718.580000 ;
+ RECT 645.255000 1712.660000 646.520000 1713.140000 ;
+ RECT 645.255000 1707.220000 646.520000 1707.700000 ;
+ RECT 645.255000 1701.780000 646.520000 1702.260000 ;
+ RECT 645.255000 1696.340000 646.520000 1696.820000 ;
+ RECT 645.255000 1685.460000 646.520000 1685.940000 ;
+ RECT 645.255000 1690.900000 646.520000 1691.380000 ;
+ RECT 645.255000 1680.020000 646.520000 1680.500000 ;
+ RECT 645.255000 1674.580000 646.520000 1675.060000 ;
+ RECT 645.255000 1669.140000 646.520000 1669.620000 ;
+ RECT 645.255000 1663.700000 646.520000 1664.180000 ;
+ RECT 645.255000 1658.260000 646.520000 1658.740000 ;
+ RECT 645.255000 1652.820000 646.520000 1653.300000 ;
+ RECT 645.255000 1641.940000 646.520000 1642.420000 ;
+ RECT 645.255000 1636.500000 646.520000 1636.980000 ;
+ RECT 645.255000 1631.060000 646.520000 1631.540000 ;
+ RECT 645.255000 1625.620000 646.520000 1626.100000 ;
+ RECT 645.255000 1620.180000 646.520000 1620.660000 ;
+ RECT 645.255000 1614.740000 646.520000 1615.220000 ;
+ RECT 645.255000 1603.860000 646.520000 1604.340000 ;
+ RECT 645.255000 1609.300000 646.520000 1609.780000 ;
+ RECT 645.255000 1598.420000 646.520000 1598.900000 ;
+ RECT 645.255000 1592.980000 646.520000 1593.460000 ;
+ RECT 645.255000 1587.540000 646.520000 1588.020000 ;
+ RECT 645.255000 1582.100000 646.520000 1582.580000 ;
+ RECT 645.255000 1576.660000 646.520000 1577.140000 ;
+ RECT 645.255000 1571.220000 646.520000 1571.700000 ;
+ RECT 645.255000 1560.340000 646.520000 1560.820000 ;
+ RECT 645.255000 1565.780000 646.520000 1566.260000 ;
+ RECT 645.255000 1554.900000 646.520000 1555.380000 ;
+ RECT 645.255000 1647.380000 646.520000 1647.860000 ;
+ RECT 825.420000 1548.570000 826.520000 1745.140000 ;
+ RECT 780.420000 1548.570000 781.520000 1745.140000 ;
+ RECT 838.230000 1547.320000 839.230000 1747.580000 ;
+ RECT 735.420000 1548.570000 736.520000 1745.140000 ;
+ RECT 690.420000 1548.570000 691.520000 1745.140000 ;
+ RECT 645.420000 1548.570000 646.520000 1745.140000 ;
+ RECT 641.590000 1547.320000 642.590000 1747.580000 ;
+ LAYER met3 ;
+ RECT 825.420000 1739.860000 826.520000 1740.340000 ;
+ RECT 838.230000 1739.860000 839.230000 1740.340000 ;
+ RECT 838.230000 1728.980000 839.230000 1729.460000 ;
+ RECT 838.230000 1723.540000 839.230000 1724.020000 ;
+ RECT 838.230000 1734.420000 839.230000 1734.900000 ;
+ RECT 825.420000 1734.420000 826.520000 1734.900000 ;
+ RECT 825.420000 1728.980000 826.520000 1729.460000 ;
+ RECT 825.420000 1723.540000 826.520000 1724.020000 ;
+ RECT 825.420000 1712.660000 826.520000 1713.140000 ;
+ RECT 825.420000 1718.100000 826.520000 1718.580000 ;
+ RECT 838.230000 1712.660000 839.230000 1713.140000 ;
+ RECT 838.230000 1718.100000 839.230000 1718.580000 ;
+ RECT 825.420000 1701.780000 826.520000 1702.260000 ;
+ RECT 825.420000 1707.220000 826.520000 1707.700000 ;
+ RECT 838.230000 1701.780000 839.230000 1702.260000 ;
+ RECT 838.230000 1707.220000 839.230000 1707.700000 ;
+ RECT 780.420000 1723.540000 781.520000 1724.020000 ;
+ RECT 780.420000 1728.980000 781.520000 1729.460000 ;
+ RECT 780.420000 1734.420000 781.520000 1734.900000 ;
+ RECT 780.420000 1739.860000 781.520000 1740.340000 ;
+ RECT 780.420000 1707.220000 781.520000 1707.700000 ;
+ RECT 780.420000 1701.780000 781.520000 1702.260000 ;
+ RECT 780.420000 1712.660000 781.520000 1713.140000 ;
+ RECT 780.420000 1718.100000 781.520000 1718.580000 ;
+ RECT 838.230000 1690.900000 839.230000 1691.380000 ;
+ RECT 838.230000 1685.460000 839.230000 1685.940000 ;
+ RECT 838.230000 1696.340000 839.230000 1696.820000 ;
+ RECT 825.420000 1696.340000 826.520000 1696.820000 ;
+ RECT 825.420000 1690.900000 826.520000 1691.380000 ;
+ RECT 825.420000 1685.460000 826.520000 1685.940000 ;
+ RECT 825.420000 1674.580000 826.520000 1675.060000 ;
+ RECT 825.420000 1680.020000 826.520000 1680.500000 ;
+ RECT 838.230000 1674.580000 839.230000 1675.060000 ;
+ RECT 838.230000 1680.020000 839.230000 1680.500000 ;
+ RECT 838.230000 1663.700000 839.230000 1664.180000 ;
+ RECT 838.230000 1669.140000 839.230000 1669.620000 ;
+ RECT 825.420000 1669.140000 826.520000 1669.620000 ;
+ RECT 825.420000 1663.700000 826.520000 1664.180000 ;
+ RECT 825.420000 1652.820000 826.520000 1653.300000 ;
+ RECT 825.420000 1658.260000 826.520000 1658.740000 ;
+ RECT 838.230000 1652.820000 839.230000 1653.300000 ;
+ RECT 838.230000 1658.260000 839.230000 1658.740000 ;
+ RECT 780.420000 1674.580000 781.520000 1675.060000 ;
+ RECT 780.420000 1680.020000 781.520000 1680.500000 ;
+ RECT 780.420000 1685.460000 781.520000 1685.940000 ;
+ RECT 780.420000 1690.900000 781.520000 1691.380000 ;
+ RECT 780.420000 1696.340000 781.520000 1696.820000 ;
+ RECT 780.420000 1652.820000 781.520000 1653.300000 ;
+ RECT 780.420000 1658.260000 781.520000 1658.740000 ;
+ RECT 780.420000 1663.700000 781.520000 1664.180000 ;
+ RECT 780.420000 1669.140000 781.520000 1669.620000 ;
+ RECT 735.420000 1728.980000 736.520000 1729.460000 ;
+ RECT 735.420000 1723.540000 736.520000 1724.020000 ;
+ RECT 735.420000 1734.420000 736.520000 1734.900000 ;
+ RECT 735.420000 1739.860000 736.520000 1740.340000 ;
+ RECT 690.420000 1723.540000 691.520000 1724.020000 ;
+ RECT 690.420000 1728.980000 691.520000 1729.460000 ;
+ RECT 690.420000 1734.420000 691.520000 1734.900000 ;
+ RECT 690.420000 1739.860000 691.520000 1740.340000 ;
+ RECT 735.420000 1701.780000 736.520000 1702.260000 ;
+ RECT 735.420000 1707.220000 736.520000 1707.700000 ;
+ RECT 735.420000 1712.660000 736.520000 1713.140000 ;
+ RECT 735.420000 1718.100000 736.520000 1718.580000 ;
+ RECT 690.420000 1701.780000 691.520000 1702.260000 ;
+ RECT 690.420000 1707.220000 691.520000 1707.700000 ;
+ RECT 690.420000 1712.660000 691.520000 1713.140000 ;
+ RECT 690.420000 1718.100000 691.520000 1718.580000 ;
+ RECT 641.590000 1739.860000 642.590000 1740.340000 ;
+ RECT 645.255000 1739.860000 646.520000 1740.340000 ;
+ RECT 641.590000 1728.980000 642.590000 1729.460000 ;
+ RECT 645.255000 1728.980000 646.520000 1729.460000 ;
+ RECT 641.590000 1734.420000 642.590000 1734.900000 ;
+ RECT 645.255000 1734.420000 646.520000 1734.900000 ;
+ RECT 641.590000 1723.540000 642.590000 1724.020000 ;
+ RECT 645.255000 1723.540000 646.520000 1724.020000 ;
+ RECT 641.590000 1718.100000 642.590000 1718.580000 ;
+ RECT 645.255000 1718.100000 646.520000 1718.580000 ;
+ RECT 641.590000 1712.660000 642.590000 1713.140000 ;
+ RECT 645.255000 1712.660000 646.520000 1713.140000 ;
+ RECT 641.590000 1707.220000 642.590000 1707.700000 ;
+ RECT 645.255000 1707.220000 646.520000 1707.700000 ;
+ RECT 641.590000 1701.780000 642.590000 1702.260000 ;
+ RECT 645.255000 1701.780000 646.520000 1702.260000 ;
+ RECT 735.420000 1674.580000 736.520000 1675.060000 ;
+ RECT 735.420000 1680.020000 736.520000 1680.500000 ;
+ RECT 735.420000 1685.460000 736.520000 1685.940000 ;
+ RECT 735.420000 1690.900000 736.520000 1691.380000 ;
+ RECT 735.420000 1696.340000 736.520000 1696.820000 ;
+ RECT 690.420000 1674.580000 691.520000 1675.060000 ;
+ RECT 690.420000 1680.020000 691.520000 1680.500000 ;
+ RECT 690.420000 1685.460000 691.520000 1685.940000 ;
+ RECT 690.420000 1690.900000 691.520000 1691.380000 ;
+ RECT 690.420000 1696.340000 691.520000 1696.820000 ;
+ RECT 735.420000 1652.820000 736.520000 1653.300000 ;
+ RECT 735.420000 1658.260000 736.520000 1658.740000 ;
+ RECT 735.420000 1663.700000 736.520000 1664.180000 ;
+ RECT 735.420000 1669.140000 736.520000 1669.620000 ;
+ RECT 690.420000 1652.820000 691.520000 1653.300000 ;
+ RECT 690.420000 1658.260000 691.520000 1658.740000 ;
+ RECT 690.420000 1663.700000 691.520000 1664.180000 ;
+ RECT 690.420000 1669.140000 691.520000 1669.620000 ;
+ RECT 641.590000 1696.340000 642.590000 1696.820000 ;
+ RECT 645.255000 1696.340000 646.520000 1696.820000 ;
+ RECT 641.590000 1685.460000 642.590000 1685.940000 ;
+ RECT 645.255000 1685.460000 646.520000 1685.940000 ;
+ RECT 641.590000 1690.900000 642.590000 1691.380000 ;
+ RECT 645.255000 1690.900000 646.520000 1691.380000 ;
+ RECT 641.590000 1680.020000 642.590000 1680.500000 ;
+ RECT 645.255000 1680.020000 646.520000 1680.500000 ;
+ RECT 641.590000 1674.580000 642.590000 1675.060000 ;
+ RECT 645.255000 1674.580000 646.520000 1675.060000 ;
+ RECT 641.590000 1669.140000 642.590000 1669.620000 ;
+ RECT 645.255000 1669.140000 646.520000 1669.620000 ;
+ RECT 641.590000 1663.700000 642.590000 1664.180000 ;
+ RECT 645.255000 1663.700000 646.520000 1664.180000 ;
+ RECT 641.590000 1658.260000 642.590000 1658.740000 ;
+ RECT 645.255000 1658.260000 646.520000 1658.740000 ;
+ RECT 641.590000 1652.820000 642.590000 1653.300000 ;
+ RECT 645.255000 1652.820000 646.520000 1653.300000 ;
+ RECT 825.420000 1636.500000 826.520000 1636.980000 ;
+ RECT 825.420000 1641.940000 826.520000 1642.420000 ;
+ RECT 838.230000 1636.500000 839.230000 1636.980000 ;
+ RECT 838.230000 1641.940000 839.230000 1642.420000 ;
+ RECT 838.230000 1625.620000 839.230000 1626.100000 ;
+ RECT 838.230000 1631.060000 839.230000 1631.540000 ;
+ RECT 825.420000 1631.060000 826.520000 1631.540000 ;
+ RECT 825.420000 1625.620000 826.520000 1626.100000 ;
+ RECT 825.420000 1614.740000 826.520000 1615.220000 ;
+ RECT 825.420000 1620.180000 826.520000 1620.660000 ;
+ RECT 838.230000 1614.740000 839.230000 1615.220000 ;
+ RECT 838.230000 1620.180000 839.230000 1620.660000 ;
+ RECT 838.230000 1603.860000 839.230000 1604.340000 ;
+ RECT 838.230000 1598.420000 839.230000 1598.900000 ;
+ RECT 838.230000 1609.300000 839.230000 1609.780000 ;
+ RECT 825.420000 1609.300000 826.520000 1609.780000 ;
+ RECT 825.420000 1603.860000 826.520000 1604.340000 ;
+ RECT 825.420000 1598.420000 826.520000 1598.900000 ;
+ RECT 780.420000 1625.620000 781.520000 1626.100000 ;
+ RECT 780.420000 1631.060000 781.520000 1631.540000 ;
+ RECT 780.420000 1636.500000 781.520000 1636.980000 ;
+ RECT 780.420000 1641.940000 781.520000 1642.420000 ;
+ RECT 780.420000 1598.420000 781.520000 1598.900000 ;
+ RECT 780.420000 1603.860000 781.520000 1604.340000 ;
+ RECT 780.420000 1609.300000 781.520000 1609.780000 ;
+ RECT 780.420000 1614.740000 781.520000 1615.220000 ;
+ RECT 780.420000 1620.180000 781.520000 1620.660000 ;
+ RECT 825.420000 1587.540000 826.520000 1588.020000 ;
+ RECT 825.420000 1592.980000 826.520000 1593.460000 ;
+ RECT 838.230000 1587.540000 839.230000 1588.020000 ;
+ RECT 838.230000 1592.980000 839.230000 1593.460000 ;
+ RECT 825.420000 1576.660000 826.520000 1577.140000 ;
+ RECT 825.420000 1582.100000 826.520000 1582.580000 ;
+ RECT 838.230000 1576.660000 839.230000 1577.140000 ;
+ RECT 838.230000 1582.100000 839.230000 1582.580000 ;
+ RECT 838.230000 1565.780000 839.230000 1566.260000 ;
+ RECT 838.230000 1560.340000 839.230000 1560.820000 ;
+ RECT 838.230000 1571.220000 839.230000 1571.700000 ;
+ RECT 825.420000 1571.220000 826.520000 1571.700000 ;
+ RECT 825.420000 1565.780000 826.520000 1566.260000 ;
+ RECT 825.420000 1560.340000 826.520000 1560.820000 ;
+ RECT 825.420000 1554.900000 826.520000 1555.380000 ;
+ RECT 838.230000 1554.900000 839.230000 1555.380000 ;
+ RECT 780.420000 1576.660000 781.520000 1577.140000 ;
+ RECT 780.420000 1582.100000 781.520000 1582.580000 ;
+ RECT 780.420000 1587.540000 781.520000 1588.020000 ;
+ RECT 780.420000 1592.980000 781.520000 1593.460000 ;
+ RECT 780.420000 1554.900000 781.520000 1555.380000 ;
+ RECT 780.420000 1560.340000 781.520000 1560.820000 ;
+ RECT 780.420000 1565.780000 781.520000 1566.260000 ;
+ RECT 780.420000 1571.220000 781.520000 1571.700000 ;
+ RECT 735.420000 1625.620000 736.520000 1626.100000 ;
+ RECT 735.420000 1631.060000 736.520000 1631.540000 ;
+ RECT 735.420000 1636.500000 736.520000 1636.980000 ;
+ RECT 735.420000 1641.940000 736.520000 1642.420000 ;
+ RECT 690.420000 1625.620000 691.520000 1626.100000 ;
+ RECT 690.420000 1631.060000 691.520000 1631.540000 ;
+ RECT 690.420000 1636.500000 691.520000 1636.980000 ;
+ RECT 690.420000 1641.940000 691.520000 1642.420000 ;
+ RECT 735.420000 1598.420000 736.520000 1598.900000 ;
+ RECT 735.420000 1603.860000 736.520000 1604.340000 ;
+ RECT 735.420000 1609.300000 736.520000 1609.780000 ;
+ RECT 735.420000 1614.740000 736.520000 1615.220000 ;
+ RECT 735.420000 1620.180000 736.520000 1620.660000 ;
+ RECT 690.420000 1598.420000 691.520000 1598.900000 ;
+ RECT 690.420000 1603.860000 691.520000 1604.340000 ;
+ RECT 690.420000 1609.300000 691.520000 1609.780000 ;
+ RECT 690.420000 1614.740000 691.520000 1615.220000 ;
+ RECT 690.420000 1620.180000 691.520000 1620.660000 ;
+ RECT 641.590000 1641.940000 642.590000 1642.420000 ;
+ RECT 645.255000 1641.940000 646.520000 1642.420000 ;
+ RECT 641.590000 1636.500000 642.590000 1636.980000 ;
+ RECT 645.255000 1636.500000 646.520000 1636.980000 ;
+ RECT 641.590000 1631.060000 642.590000 1631.540000 ;
+ RECT 645.255000 1631.060000 646.520000 1631.540000 ;
+ RECT 641.590000 1625.620000 642.590000 1626.100000 ;
+ RECT 645.255000 1625.620000 646.520000 1626.100000 ;
+ RECT 641.590000 1620.180000 642.590000 1620.660000 ;
+ RECT 645.255000 1620.180000 646.520000 1620.660000 ;
+ RECT 641.590000 1614.740000 642.590000 1615.220000 ;
+ RECT 645.255000 1614.740000 646.520000 1615.220000 ;
+ RECT 641.590000 1603.860000 642.590000 1604.340000 ;
+ RECT 645.255000 1603.860000 646.520000 1604.340000 ;
+ RECT 641.590000 1609.300000 642.590000 1609.780000 ;
+ RECT 645.255000 1609.300000 646.520000 1609.780000 ;
+ RECT 641.590000 1598.420000 642.590000 1598.900000 ;
+ RECT 645.255000 1598.420000 646.520000 1598.900000 ;
+ RECT 735.420000 1576.660000 736.520000 1577.140000 ;
+ RECT 735.420000 1582.100000 736.520000 1582.580000 ;
+ RECT 735.420000 1587.540000 736.520000 1588.020000 ;
+ RECT 735.420000 1592.980000 736.520000 1593.460000 ;
+ RECT 690.420000 1576.660000 691.520000 1577.140000 ;
+ RECT 690.420000 1582.100000 691.520000 1582.580000 ;
+ RECT 690.420000 1587.540000 691.520000 1588.020000 ;
+ RECT 690.420000 1592.980000 691.520000 1593.460000 ;
+ RECT 735.420000 1554.900000 736.520000 1555.380000 ;
+ RECT 735.420000 1560.340000 736.520000 1560.820000 ;
+ RECT 735.420000 1565.780000 736.520000 1566.260000 ;
+ RECT 735.420000 1571.220000 736.520000 1571.700000 ;
+ RECT 690.420000 1554.900000 691.520000 1555.380000 ;
+ RECT 690.420000 1560.340000 691.520000 1560.820000 ;
+ RECT 690.420000 1565.780000 691.520000 1566.260000 ;
+ RECT 690.420000 1571.220000 691.520000 1571.700000 ;
+ RECT 641.590000 1592.980000 642.590000 1593.460000 ;
+ RECT 645.255000 1592.980000 646.520000 1593.460000 ;
+ RECT 641.590000 1587.540000 642.590000 1588.020000 ;
+ RECT 645.255000 1587.540000 646.520000 1588.020000 ;
+ RECT 641.590000 1582.100000 642.590000 1582.580000 ;
+ RECT 645.255000 1582.100000 646.520000 1582.580000 ;
+ RECT 641.590000 1576.660000 642.590000 1577.140000 ;
+ RECT 645.255000 1576.660000 646.520000 1577.140000 ;
+ RECT 641.590000 1571.220000 642.590000 1571.700000 ;
+ RECT 645.255000 1571.220000 646.520000 1571.700000 ;
+ RECT 641.590000 1560.340000 642.590000 1560.820000 ;
+ RECT 645.255000 1560.340000 646.520000 1560.820000 ;
+ RECT 641.590000 1565.780000 642.590000 1566.260000 ;
+ RECT 645.255000 1565.780000 646.520000 1566.260000 ;
+ RECT 641.590000 1554.900000 642.590000 1555.380000 ;
+ RECT 645.255000 1554.900000 646.520000 1555.380000 ;
+ RECT 780.420000 1647.380000 781.520000 1647.860000 ;
+ RECT 825.420000 1647.380000 826.520000 1647.860000 ;
+ RECT 838.230000 1647.380000 839.230000 1647.860000 ;
+ RECT 690.420000 1647.380000 691.520000 1647.860000 ;
+ RECT 735.420000 1647.380000 736.520000 1647.860000 ;
+ RECT 641.590000 1647.380000 642.590000 1647.860000 ;
+ RECT 645.255000 1647.380000 646.520000 1647.860000 ;
+ RECT 640.360000 1744.140000 840.460000 1745.140000 ;
+ RECT 640.360000 1548.570000 840.460000 1549.570000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 1547.320000 642.590000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 641.590000 1746.580000 642.590000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 1547.320000 839.230000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 838.230000 1746.580000 839.230000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1548.570000 641.360000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1548.570000 840.460000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1744.140000 641.360000 1745.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1744.140000 840.460000 1745.140000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 3373.560000 846.620000 3374.040000 ;
+ RECT 845.355000 3368.120000 846.620000 3368.600000 ;
+ RECT 845.355000 3362.680000 846.620000 3363.160000 ;
+ RECT 845.355000 3357.240000 846.620000 3357.720000 ;
+ RECT 841.690000 3349.660000 842.690000 3379.920000 ;
+ RECT 1038.330000 3349.660000 1039.330000 3379.920000 ;
+ RECT 845.520000 3350.910000 846.620000 3378.160000 ;
+ RECT 890.520000 3350.910000 891.620000 3378.160000 ;
+ RECT 935.520000 3350.910000 936.620000 3378.160000 ;
+ RECT 980.520000 3350.910000 981.620000 3378.160000 ;
+ RECT 1025.520000 3350.910000 1026.620000 3378.160000 ;
+ LAYER met3 ;
+ RECT 1038.330000 3373.560000 1039.330000 3374.040000 ;
+ RECT 1038.330000 3368.120000 1039.330000 3368.600000 ;
+ RECT 1025.520000 3373.560000 1026.620000 3374.040000 ;
+ RECT 1025.520000 3368.120000 1026.620000 3368.600000 ;
+ RECT 980.520000 3368.120000 981.620000 3368.600000 ;
+ RECT 980.520000 3373.560000 981.620000 3374.040000 ;
+ RECT 935.520000 3368.120000 936.620000 3368.600000 ;
+ RECT 890.520000 3368.120000 891.620000 3368.600000 ;
+ RECT 935.520000 3373.560000 936.620000 3374.040000 ;
+ RECT 890.520000 3373.560000 891.620000 3374.040000 ;
+ RECT 845.355000 3373.560000 846.620000 3374.040000 ;
+ RECT 841.690000 3373.560000 842.690000 3374.040000 ;
+ RECT 845.355000 3368.120000 846.620000 3368.600000 ;
+ RECT 841.690000 3368.120000 842.690000 3368.600000 ;
+ RECT 1038.330000 3362.680000 1039.330000 3363.160000 ;
+ RECT 1038.330000 3357.240000 1039.330000 3357.720000 ;
+ RECT 1025.520000 3362.680000 1026.620000 3363.160000 ;
+ RECT 1025.520000 3357.240000 1026.620000 3357.720000 ;
+ RECT 980.520000 3357.240000 981.620000 3357.720000 ;
+ RECT 980.520000 3362.680000 981.620000 3363.160000 ;
+ RECT 935.520000 3357.240000 936.620000 3357.720000 ;
+ RECT 890.520000 3357.240000 891.620000 3357.720000 ;
+ RECT 935.520000 3362.680000 936.620000 3363.160000 ;
+ RECT 890.520000 3362.680000 891.620000 3363.160000 ;
+ RECT 845.355000 3362.680000 846.620000 3363.160000 ;
+ RECT 841.690000 3362.680000 842.690000 3363.160000 ;
+ RECT 845.355000 3357.240000 846.620000 3357.720000 ;
+ RECT 841.690000 3357.240000 842.690000 3357.720000 ;
+ RECT 840.460000 3377.160000 1040.560000 3378.160000 ;
+ RECT 840.460000 3350.910000 1040.560000 3351.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 3349.660000 842.690000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 3378.920000 842.690000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 3349.660000 1039.330000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 3378.920000 1039.330000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 3350.910000 841.460000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 3350.910000 1040.560000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 3377.160000 841.460000 3378.160000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 3377.160000 1040.560000 3378.160000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 1539.600000 846.620000 1540.080000 ;
+ RECT 845.355000 1528.720000 846.620000 1529.200000 ;
+ RECT 845.355000 1534.160000 846.620000 1534.640000 ;
+ RECT 845.355000 1523.280000 846.620000 1523.760000 ;
+ RECT 845.355000 1517.840000 846.620000 1518.320000 ;
+ RECT 845.355000 1512.400000 846.620000 1512.880000 ;
+ RECT 845.355000 1506.960000 846.620000 1507.440000 ;
+ RECT 845.355000 1501.520000 846.620000 1502.000000 ;
+ RECT 845.355000 1496.080000 846.620000 1496.560000 ;
+ RECT 845.355000 1485.200000 846.620000 1485.680000 ;
+ RECT 845.355000 1490.640000 846.620000 1491.120000 ;
+ RECT 845.355000 1479.760000 846.620000 1480.240000 ;
+ RECT 845.355000 1474.320000 846.620000 1474.800000 ;
+ RECT 845.355000 1468.880000 846.620000 1469.360000 ;
+ RECT 845.355000 1463.440000 846.620000 1463.920000 ;
+ RECT 845.355000 1458.000000 846.620000 1458.480000 ;
+ RECT 845.355000 1452.560000 846.620000 1453.040000 ;
+ RECT 845.355000 1441.680000 846.620000 1442.160000 ;
+ RECT 845.355000 1436.240000 846.620000 1436.720000 ;
+ RECT 845.355000 1430.800000 846.620000 1431.280000 ;
+ RECT 845.355000 1425.360000 846.620000 1425.840000 ;
+ RECT 845.355000 1419.920000 846.620000 1420.400000 ;
+ RECT 845.355000 1414.480000 846.620000 1414.960000 ;
+ RECT 845.355000 1403.600000 846.620000 1404.080000 ;
+ RECT 845.355000 1409.040000 846.620000 1409.520000 ;
+ RECT 845.355000 1398.160000 846.620000 1398.640000 ;
+ RECT 845.355000 1392.720000 846.620000 1393.200000 ;
+ RECT 845.355000 1387.280000 846.620000 1387.760000 ;
+ RECT 845.355000 1381.840000 846.620000 1382.320000 ;
+ RECT 845.355000 1376.400000 846.620000 1376.880000 ;
+ RECT 845.355000 1370.960000 846.620000 1371.440000 ;
+ RECT 845.355000 1360.080000 846.620000 1360.560000 ;
+ RECT 845.355000 1365.520000 846.620000 1366.000000 ;
+ RECT 845.355000 1354.640000 846.620000 1355.120000 ;
+ RECT 845.355000 1447.120000 846.620000 1447.600000 ;
+ RECT 1025.520000 1348.310000 1026.620000 1544.880000 ;
+ RECT 980.520000 1348.310000 981.620000 1544.880000 ;
+ RECT 1038.330000 1347.060000 1039.330000 1547.320000 ;
+ RECT 935.520000 1348.310000 936.620000 1544.880000 ;
+ RECT 890.520000 1348.310000 891.620000 1544.880000 ;
+ RECT 845.520000 1348.310000 846.620000 1544.880000 ;
+ RECT 841.690000 1347.060000 842.690000 1547.320000 ;
+ LAYER met3 ;
+ RECT 1025.520000 1539.600000 1026.620000 1540.080000 ;
+ RECT 1038.330000 1539.600000 1039.330000 1540.080000 ;
+ RECT 1038.330000 1528.720000 1039.330000 1529.200000 ;
+ RECT 1038.330000 1523.280000 1039.330000 1523.760000 ;
+ RECT 1038.330000 1534.160000 1039.330000 1534.640000 ;
+ RECT 1025.520000 1534.160000 1026.620000 1534.640000 ;
+ RECT 1025.520000 1528.720000 1026.620000 1529.200000 ;
+ RECT 1025.520000 1523.280000 1026.620000 1523.760000 ;
+ RECT 1025.520000 1512.400000 1026.620000 1512.880000 ;
+ RECT 1025.520000 1517.840000 1026.620000 1518.320000 ;
+ RECT 1038.330000 1512.400000 1039.330000 1512.880000 ;
+ RECT 1038.330000 1517.840000 1039.330000 1518.320000 ;
+ RECT 1025.520000 1501.520000 1026.620000 1502.000000 ;
+ RECT 1025.520000 1506.960000 1026.620000 1507.440000 ;
+ RECT 1038.330000 1501.520000 1039.330000 1502.000000 ;
+ RECT 1038.330000 1506.960000 1039.330000 1507.440000 ;
+ RECT 980.520000 1523.280000 981.620000 1523.760000 ;
+ RECT 980.520000 1528.720000 981.620000 1529.200000 ;
+ RECT 980.520000 1534.160000 981.620000 1534.640000 ;
+ RECT 980.520000 1539.600000 981.620000 1540.080000 ;
+ RECT 980.520000 1506.960000 981.620000 1507.440000 ;
+ RECT 980.520000 1501.520000 981.620000 1502.000000 ;
+ RECT 980.520000 1512.400000 981.620000 1512.880000 ;
+ RECT 980.520000 1517.840000 981.620000 1518.320000 ;
+ RECT 1038.330000 1490.640000 1039.330000 1491.120000 ;
+ RECT 1038.330000 1485.200000 1039.330000 1485.680000 ;
+ RECT 1038.330000 1496.080000 1039.330000 1496.560000 ;
+ RECT 1025.520000 1496.080000 1026.620000 1496.560000 ;
+ RECT 1025.520000 1490.640000 1026.620000 1491.120000 ;
+ RECT 1025.520000 1485.200000 1026.620000 1485.680000 ;
+ RECT 1025.520000 1474.320000 1026.620000 1474.800000 ;
+ RECT 1025.520000 1479.760000 1026.620000 1480.240000 ;
+ RECT 1038.330000 1474.320000 1039.330000 1474.800000 ;
+ RECT 1038.330000 1479.760000 1039.330000 1480.240000 ;
+ RECT 1038.330000 1463.440000 1039.330000 1463.920000 ;
+ RECT 1038.330000 1468.880000 1039.330000 1469.360000 ;
+ RECT 1025.520000 1468.880000 1026.620000 1469.360000 ;
+ RECT 1025.520000 1463.440000 1026.620000 1463.920000 ;
+ RECT 1025.520000 1452.560000 1026.620000 1453.040000 ;
+ RECT 1025.520000 1458.000000 1026.620000 1458.480000 ;
+ RECT 1038.330000 1452.560000 1039.330000 1453.040000 ;
+ RECT 1038.330000 1458.000000 1039.330000 1458.480000 ;
+ RECT 980.520000 1474.320000 981.620000 1474.800000 ;
+ RECT 980.520000 1479.760000 981.620000 1480.240000 ;
+ RECT 980.520000 1485.200000 981.620000 1485.680000 ;
+ RECT 980.520000 1490.640000 981.620000 1491.120000 ;
+ RECT 980.520000 1496.080000 981.620000 1496.560000 ;
+ RECT 980.520000 1452.560000 981.620000 1453.040000 ;
+ RECT 980.520000 1458.000000 981.620000 1458.480000 ;
+ RECT 980.520000 1463.440000 981.620000 1463.920000 ;
+ RECT 980.520000 1468.880000 981.620000 1469.360000 ;
+ RECT 935.520000 1528.720000 936.620000 1529.200000 ;
+ RECT 935.520000 1523.280000 936.620000 1523.760000 ;
+ RECT 935.520000 1534.160000 936.620000 1534.640000 ;
+ RECT 935.520000 1539.600000 936.620000 1540.080000 ;
+ RECT 890.520000 1523.280000 891.620000 1523.760000 ;
+ RECT 890.520000 1528.720000 891.620000 1529.200000 ;
+ RECT 890.520000 1534.160000 891.620000 1534.640000 ;
+ RECT 890.520000 1539.600000 891.620000 1540.080000 ;
+ RECT 935.520000 1501.520000 936.620000 1502.000000 ;
+ RECT 935.520000 1506.960000 936.620000 1507.440000 ;
+ RECT 935.520000 1512.400000 936.620000 1512.880000 ;
+ RECT 935.520000 1517.840000 936.620000 1518.320000 ;
+ RECT 890.520000 1501.520000 891.620000 1502.000000 ;
+ RECT 890.520000 1506.960000 891.620000 1507.440000 ;
+ RECT 890.520000 1512.400000 891.620000 1512.880000 ;
+ RECT 890.520000 1517.840000 891.620000 1518.320000 ;
+ RECT 841.690000 1539.600000 842.690000 1540.080000 ;
+ RECT 845.355000 1539.600000 846.620000 1540.080000 ;
+ RECT 841.690000 1528.720000 842.690000 1529.200000 ;
+ RECT 845.355000 1528.720000 846.620000 1529.200000 ;
+ RECT 841.690000 1534.160000 842.690000 1534.640000 ;
+ RECT 845.355000 1534.160000 846.620000 1534.640000 ;
+ RECT 841.690000 1523.280000 842.690000 1523.760000 ;
+ RECT 845.355000 1523.280000 846.620000 1523.760000 ;
+ RECT 841.690000 1517.840000 842.690000 1518.320000 ;
+ RECT 845.355000 1517.840000 846.620000 1518.320000 ;
+ RECT 841.690000 1512.400000 842.690000 1512.880000 ;
+ RECT 845.355000 1512.400000 846.620000 1512.880000 ;
+ RECT 841.690000 1506.960000 842.690000 1507.440000 ;
+ RECT 845.355000 1506.960000 846.620000 1507.440000 ;
+ RECT 841.690000 1501.520000 842.690000 1502.000000 ;
+ RECT 845.355000 1501.520000 846.620000 1502.000000 ;
+ RECT 935.520000 1474.320000 936.620000 1474.800000 ;
+ RECT 935.520000 1479.760000 936.620000 1480.240000 ;
+ RECT 935.520000 1485.200000 936.620000 1485.680000 ;
+ RECT 935.520000 1490.640000 936.620000 1491.120000 ;
+ RECT 935.520000 1496.080000 936.620000 1496.560000 ;
+ RECT 890.520000 1474.320000 891.620000 1474.800000 ;
+ RECT 890.520000 1479.760000 891.620000 1480.240000 ;
+ RECT 890.520000 1485.200000 891.620000 1485.680000 ;
+ RECT 890.520000 1490.640000 891.620000 1491.120000 ;
+ RECT 890.520000 1496.080000 891.620000 1496.560000 ;
+ RECT 935.520000 1452.560000 936.620000 1453.040000 ;
+ RECT 935.520000 1458.000000 936.620000 1458.480000 ;
+ RECT 935.520000 1463.440000 936.620000 1463.920000 ;
+ RECT 935.520000 1468.880000 936.620000 1469.360000 ;
+ RECT 890.520000 1452.560000 891.620000 1453.040000 ;
+ RECT 890.520000 1458.000000 891.620000 1458.480000 ;
+ RECT 890.520000 1463.440000 891.620000 1463.920000 ;
+ RECT 890.520000 1468.880000 891.620000 1469.360000 ;
+ RECT 841.690000 1496.080000 842.690000 1496.560000 ;
+ RECT 845.355000 1496.080000 846.620000 1496.560000 ;
+ RECT 841.690000 1485.200000 842.690000 1485.680000 ;
+ RECT 845.355000 1485.200000 846.620000 1485.680000 ;
+ RECT 841.690000 1490.640000 842.690000 1491.120000 ;
+ RECT 845.355000 1490.640000 846.620000 1491.120000 ;
+ RECT 841.690000 1479.760000 842.690000 1480.240000 ;
+ RECT 845.355000 1479.760000 846.620000 1480.240000 ;
+ RECT 841.690000 1474.320000 842.690000 1474.800000 ;
+ RECT 845.355000 1474.320000 846.620000 1474.800000 ;
+ RECT 841.690000 1468.880000 842.690000 1469.360000 ;
+ RECT 845.355000 1468.880000 846.620000 1469.360000 ;
+ RECT 841.690000 1463.440000 842.690000 1463.920000 ;
+ RECT 845.355000 1463.440000 846.620000 1463.920000 ;
+ RECT 841.690000 1458.000000 842.690000 1458.480000 ;
+ RECT 845.355000 1458.000000 846.620000 1458.480000 ;
+ RECT 841.690000 1452.560000 842.690000 1453.040000 ;
+ RECT 845.355000 1452.560000 846.620000 1453.040000 ;
+ RECT 1025.520000 1436.240000 1026.620000 1436.720000 ;
+ RECT 1025.520000 1441.680000 1026.620000 1442.160000 ;
+ RECT 1038.330000 1436.240000 1039.330000 1436.720000 ;
+ RECT 1038.330000 1441.680000 1039.330000 1442.160000 ;
+ RECT 1038.330000 1425.360000 1039.330000 1425.840000 ;
+ RECT 1038.330000 1430.800000 1039.330000 1431.280000 ;
+ RECT 1025.520000 1430.800000 1026.620000 1431.280000 ;
+ RECT 1025.520000 1425.360000 1026.620000 1425.840000 ;
+ RECT 1025.520000 1414.480000 1026.620000 1414.960000 ;
+ RECT 1025.520000 1419.920000 1026.620000 1420.400000 ;
+ RECT 1038.330000 1414.480000 1039.330000 1414.960000 ;
+ RECT 1038.330000 1419.920000 1039.330000 1420.400000 ;
+ RECT 1038.330000 1403.600000 1039.330000 1404.080000 ;
+ RECT 1038.330000 1398.160000 1039.330000 1398.640000 ;
+ RECT 1038.330000 1409.040000 1039.330000 1409.520000 ;
+ RECT 1025.520000 1409.040000 1026.620000 1409.520000 ;
+ RECT 1025.520000 1403.600000 1026.620000 1404.080000 ;
+ RECT 1025.520000 1398.160000 1026.620000 1398.640000 ;
+ RECT 980.520000 1425.360000 981.620000 1425.840000 ;
+ RECT 980.520000 1430.800000 981.620000 1431.280000 ;
+ RECT 980.520000 1436.240000 981.620000 1436.720000 ;
+ RECT 980.520000 1441.680000 981.620000 1442.160000 ;
+ RECT 980.520000 1398.160000 981.620000 1398.640000 ;
+ RECT 980.520000 1403.600000 981.620000 1404.080000 ;
+ RECT 980.520000 1409.040000 981.620000 1409.520000 ;
+ RECT 980.520000 1414.480000 981.620000 1414.960000 ;
+ RECT 980.520000 1419.920000 981.620000 1420.400000 ;
+ RECT 1025.520000 1387.280000 1026.620000 1387.760000 ;
+ RECT 1025.520000 1392.720000 1026.620000 1393.200000 ;
+ RECT 1038.330000 1387.280000 1039.330000 1387.760000 ;
+ RECT 1038.330000 1392.720000 1039.330000 1393.200000 ;
+ RECT 1025.520000 1376.400000 1026.620000 1376.880000 ;
+ RECT 1025.520000 1381.840000 1026.620000 1382.320000 ;
+ RECT 1038.330000 1376.400000 1039.330000 1376.880000 ;
+ RECT 1038.330000 1381.840000 1039.330000 1382.320000 ;
+ RECT 1038.330000 1365.520000 1039.330000 1366.000000 ;
+ RECT 1038.330000 1360.080000 1039.330000 1360.560000 ;
+ RECT 1038.330000 1370.960000 1039.330000 1371.440000 ;
+ RECT 1025.520000 1370.960000 1026.620000 1371.440000 ;
+ RECT 1025.520000 1365.520000 1026.620000 1366.000000 ;
+ RECT 1025.520000 1360.080000 1026.620000 1360.560000 ;
+ RECT 1025.520000 1354.640000 1026.620000 1355.120000 ;
+ RECT 1038.330000 1354.640000 1039.330000 1355.120000 ;
+ RECT 980.520000 1376.400000 981.620000 1376.880000 ;
+ RECT 980.520000 1381.840000 981.620000 1382.320000 ;
+ RECT 980.520000 1387.280000 981.620000 1387.760000 ;
+ RECT 980.520000 1392.720000 981.620000 1393.200000 ;
+ RECT 980.520000 1354.640000 981.620000 1355.120000 ;
+ RECT 980.520000 1360.080000 981.620000 1360.560000 ;
+ RECT 980.520000 1365.520000 981.620000 1366.000000 ;
+ RECT 980.520000 1370.960000 981.620000 1371.440000 ;
+ RECT 935.520000 1425.360000 936.620000 1425.840000 ;
+ RECT 935.520000 1430.800000 936.620000 1431.280000 ;
+ RECT 935.520000 1436.240000 936.620000 1436.720000 ;
+ RECT 935.520000 1441.680000 936.620000 1442.160000 ;
+ RECT 890.520000 1425.360000 891.620000 1425.840000 ;
+ RECT 890.520000 1430.800000 891.620000 1431.280000 ;
+ RECT 890.520000 1436.240000 891.620000 1436.720000 ;
+ RECT 890.520000 1441.680000 891.620000 1442.160000 ;
+ RECT 935.520000 1398.160000 936.620000 1398.640000 ;
+ RECT 935.520000 1403.600000 936.620000 1404.080000 ;
+ RECT 935.520000 1409.040000 936.620000 1409.520000 ;
+ RECT 935.520000 1414.480000 936.620000 1414.960000 ;
+ RECT 935.520000 1419.920000 936.620000 1420.400000 ;
+ RECT 890.520000 1398.160000 891.620000 1398.640000 ;
+ RECT 890.520000 1403.600000 891.620000 1404.080000 ;
+ RECT 890.520000 1409.040000 891.620000 1409.520000 ;
+ RECT 890.520000 1414.480000 891.620000 1414.960000 ;
+ RECT 890.520000 1419.920000 891.620000 1420.400000 ;
+ RECT 841.690000 1441.680000 842.690000 1442.160000 ;
+ RECT 845.355000 1441.680000 846.620000 1442.160000 ;
+ RECT 841.690000 1436.240000 842.690000 1436.720000 ;
+ RECT 845.355000 1436.240000 846.620000 1436.720000 ;
+ RECT 841.690000 1430.800000 842.690000 1431.280000 ;
+ RECT 845.355000 1430.800000 846.620000 1431.280000 ;
+ RECT 841.690000 1425.360000 842.690000 1425.840000 ;
+ RECT 845.355000 1425.360000 846.620000 1425.840000 ;
+ RECT 841.690000 1419.920000 842.690000 1420.400000 ;
+ RECT 845.355000 1419.920000 846.620000 1420.400000 ;
+ RECT 841.690000 1414.480000 842.690000 1414.960000 ;
+ RECT 845.355000 1414.480000 846.620000 1414.960000 ;
+ RECT 841.690000 1403.600000 842.690000 1404.080000 ;
+ RECT 845.355000 1403.600000 846.620000 1404.080000 ;
+ RECT 841.690000 1409.040000 842.690000 1409.520000 ;
+ RECT 845.355000 1409.040000 846.620000 1409.520000 ;
+ RECT 841.690000 1398.160000 842.690000 1398.640000 ;
+ RECT 845.355000 1398.160000 846.620000 1398.640000 ;
+ RECT 935.520000 1376.400000 936.620000 1376.880000 ;
+ RECT 935.520000 1381.840000 936.620000 1382.320000 ;
+ RECT 935.520000 1387.280000 936.620000 1387.760000 ;
+ RECT 935.520000 1392.720000 936.620000 1393.200000 ;
+ RECT 890.520000 1376.400000 891.620000 1376.880000 ;
+ RECT 890.520000 1381.840000 891.620000 1382.320000 ;
+ RECT 890.520000 1387.280000 891.620000 1387.760000 ;
+ RECT 890.520000 1392.720000 891.620000 1393.200000 ;
+ RECT 935.520000 1354.640000 936.620000 1355.120000 ;
+ RECT 935.520000 1360.080000 936.620000 1360.560000 ;
+ RECT 935.520000 1365.520000 936.620000 1366.000000 ;
+ RECT 935.520000 1370.960000 936.620000 1371.440000 ;
+ RECT 890.520000 1354.640000 891.620000 1355.120000 ;
+ RECT 890.520000 1360.080000 891.620000 1360.560000 ;
+ RECT 890.520000 1365.520000 891.620000 1366.000000 ;
+ RECT 890.520000 1370.960000 891.620000 1371.440000 ;
+ RECT 841.690000 1392.720000 842.690000 1393.200000 ;
+ RECT 845.355000 1392.720000 846.620000 1393.200000 ;
+ RECT 841.690000 1387.280000 842.690000 1387.760000 ;
+ RECT 845.355000 1387.280000 846.620000 1387.760000 ;
+ RECT 841.690000 1381.840000 842.690000 1382.320000 ;
+ RECT 845.355000 1381.840000 846.620000 1382.320000 ;
+ RECT 841.690000 1376.400000 842.690000 1376.880000 ;
+ RECT 845.355000 1376.400000 846.620000 1376.880000 ;
+ RECT 841.690000 1370.960000 842.690000 1371.440000 ;
+ RECT 845.355000 1370.960000 846.620000 1371.440000 ;
+ RECT 841.690000 1360.080000 842.690000 1360.560000 ;
+ RECT 845.355000 1360.080000 846.620000 1360.560000 ;
+ RECT 841.690000 1365.520000 842.690000 1366.000000 ;
+ RECT 845.355000 1365.520000 846.620000 1366.000000 ;
+ RECT 841.690000 1354.640000 842.690000 1355.120000 ;
+ RECT 845.355000 1354.640000 846.620000 1355.120000 ;
+ RECT 980.520000 1447.120000 981.620000 1447.600000 ;
+ RECT 1025.520000 1447.120000 1026.620000 1447.600000 ;
+ RECT 1038.330000 1447.120000 1039.330000 1447.600000 ;
+ RECT 890.520000 1447.120000 891.620000 1447.600000 ;
+ RECT 935.520000 1447.120000 936.620000 1447.600000 ;
+ RECT 841.690000 1447.120000 842.690000 1447.600000 ;
+ RECT 845.355000 1447.120000 846.620000 1447.600000 ;
+ RECT 840.460000 1543.880000 1040.560000 1544.880000 ;
+ RECT 840.460000 1348.310000 1040.560000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 1347.060000 842.690000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 1546.320000 842.690000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 1347.060000 1039.330000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 1546.320000 1039.330000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1348.310000 841.460000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1348.310000 1040.560000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1543.880000 841.460000 1544.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1543.880000 1040.560000 1544.880000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 1339.340000 846.620000 1339.820000 ;
+ RECT 845.355000 1328.460000 846.620000 1328.940000 ;
+ RECT 845.355000 1333.900000 846.620000 1334.380000 ;
+ RECT 845.355000 1323.020000 846.620000 1323.500000 ;
+ RECT 845.355000 1317.580000 846.620000 1318.060000 ;
+ RECT 845.355000 1312.140000 846.620000 1312.620000 ;
+ RECT 845.355000 1306.700000 846.620000 1307.180000 ;
+ RECT 845.355000 1301.260000 846.620000 1301.740000 ;
+ RECT 845.355000 1295.820000 846.620000 1296.300000 ;
+ RECT 845.355000 1284.940000 846.620000 1285.420000 ;
+ RECT 845.355000 1290.380000 846.620000 1290.860000 ;
+ RECT 845.355000 1279.500000 846.620000 1279.980000 ;
+ RECT 845.355000 1274.060000 846.620000 1274.540000 ;
+ RECT 845.355000 1268.620000 846.620000 1269.100000 ;
+ RECT 845.355000 1263.180000 846.620000 1263.660000 ;
+ RECT 845.355000 1257.740000 846.620000 1258.220000 ;
+ RECT 845.355000 1252.300000 846.620000 1252.780000 ;
+ RECT 845.355000 1241.420000 846.620000 1241.900000 ;
+ RECT 845.355000 1235.980000 846.620000 1236.460000 ;
+ RECT 845.355000 1230.540000 846.620000 1231.020000 ;
+ RECT 845.355000 1225.100000 846.620000 1225.580000 ;
+ RECT 845.355000 1219.660000 846.620000 1220.140000 ;
+ RECT 845.355000 1214.220000 846.620000 1214.700000 ;
+ RECT 845.355000 1203.340000 846.620000 1203.820000 ;
+ RECT 845.355000 1208.780000 846.620000 1209.260000 ;
+ RECT 845.355000 1197.900000 846.620000 1198.380000 ;
+ RECT 845.355000 1192.460000 846.620000 1192.940000 ;
+ RECT 845.355000 1187.020000 846.620000 1187.500000 ;
+ RECT 845.355000 1181.580000 846.620000 1182.060000 ;
+ RECT 845.355000 1176.140000 846.620000 1176.620000 ;
+ RECT 845.355000 1170.700000 846.620000 1171.180000 ;
+ RECT 845.355000 1159.820000 846.620000 1160.300000 ;
+ RECT 845.355000 1165.260000 846.620000 1165.740000 ;
+ RECT 845.355000 1154.380000 846.620000 1154.860000 ;
+ RECT 845.355000 1246.860000 846.620000 1247.340000 ;
+ RECT 1025.520000 1148.050000 1026.620000 1344.620000 ;
+ RECT 980.520000 1148.050000 981.620000 1344.620000 ;
+ RECT 1038.330000 1146.800000 1039.330000 1347.060000 ;
+ RECT 935.520000 1148.050000 936.620000 1344.620000 ;
+ RECT 890.520000 1148.050000 891.620000 1344.620000 ;
+ RECT 845.520000 1148.050000 846.620000 1344.620000 ;
+ RECT 841.690000 1146.800000 842.690000 1347.060000 ;
+ LAYER met3 ;
+ RECT 1025.520000 1339.340000 1026.620000 1339.820000 ;
+ RECT 1038.330000 1339.340000 1039.330000 1339.820000 ;
+ RECT 1038.330000 1328.460000 1039.330000 1328.940000 ;
+ RECT 1038.330000 1323.020000 1039.330000 1323.500000 ;
+ RECT 1038.330000 1333.900000 1039.330000 1334.380000 ;
+ RECT 1025.520000 1333.900000 1026.620000 1334.380000 ;
+ RECT 1025.520000 1328.460000 1026.620000 1328.940000 ;
+ RECT 1025.520000 1323.020000 1026.620000 1323.500000 ;
+ RECT 1025.520000 1312.140000 1026.620000 1312.620000 ;
+ RECT 1025.520000 1317.580000 1026.620000 1318.060000 ;
+ RECT 1038.330000 1312.140000 1039.330000 1312.620000 ;
+ RECT 1038.330000 1317.580000 1039.330000 1318.060000 ;
+ RECT 1025.520000 1301.260000 1026.620000 1301.740000 ;
+ RECT 1025.520000 1306.700000 1026.620000 1307.180000 ;
+ RECT 1038.330000 1301.260000 1039.330000 1301.740000 ;
+ RECT 1038.330000 1306.700000 1039.330000 1307.180000 ;
+ RECT 980.520000 1323.020000 981.620000 1323.500000 ;
+ RECT 980.520000 1328.460000 981.620000 1328.940000 ;
+ RECT 980.520000 1333.900000 981.620000 1334.380000 ;
+ RECT 980.520000 1339.340000 981.620000 1339.820000 ;
+ RECT 980.520000 1306.700000 981.620000 1307.180000 ;
+ RECT 980.520000 1301.260000 981.620000 1301.740000 ;
+ RECT 980.520000 1312.140000 981.620000 1312.620000 ;
+ RECT 980.520000 1317.580000 981.620000 1318.060000 ;
+ RECT 1038.330000 1290.380000 1039.330000 1290.860000 ;
+ RECT 1038.330000 1284.940000 1039.330000 1285.420000 ;
+ RECT 1038.330000 1295.820000 1039.330000 1296.300000 ;
+ RECT 1025.520000 1295.820000 1026.620000 1296.300000 ;
+ RECT 1025.520000 1290.380000 1026.620000 1290.860000 ;
+ RECT 1025.520000 1284.940000 1026.620000 1285.420000 ;
+ RECT 1025.520000 1274.060000 1026.620000 1274.540000 ;
+ RECT 1025.520000 1279.500000 1026.620000 1279.980000 ;
+ RECT 1038.330000 1274.060000 1039.330000 1274.540000 ;
+ RECT 1038.330000 1279.500000 1039.330000 1279.980000 ;
+ RECT 1038.330000 1263.180000 1039.330000 1263.660000 ;
+ RECT 1038.330000 1268.620000 1039.330000 1269.100000 ;
+ RECT 1025.520000 1268.620000 1026.620000 1269.100000 ;
+ RECT 1025.520000 1263.180000 1026.620000 1263.660000 ;
+ RECT 1025.520000 1252.300000 1026.620000 1252.780000 ;
+ RECT 1025.520000 1257.740000 1026.620000 1258.220000 ;
+ RECT 1038.330000 1252.300000 1039.330000 1252.780000 ;
+ RECT 1038.330000 1257.740000 1039.330000 1258.220000 ;
+ RECT 980.520000 1274.060000 981.620000 1274.540000 ;
+ RECT 980.520000 1279.500000 981.620000 1279.980000 ;
+ RECT 980.520000 1284.940000 981.620000 1285.420000 ;
+ RECT 980.520000 1290.380000 981.620000 1290.860000 ;
+ RECT 980.520000 1295.820000 981.620000 1296.300000 ;
+ RECT 980.520000 1252.300000 981.620000 1252.780000 ;
+ RECT 980.520000 1257.740000 981.620000 1258.220000 ;
+ RECT 980.520000 1263.180000 981.620000 1263.660000 ;
+ RECT 980.520000 1268.620000 981.620000 1269.100000 ;
+ RECT 935.520000 1328.460000 936.620000 1328.940000 ;
+ RECT 935.520000 1323.020000 936.620000 1323.500000 ;
+ RECT 935.520000 1333.900000 936.620000 1334.380000 ;
+ RECT 935.520000 1339.340000 936.620000 1339.820000 ;
+ RECT 890.520000 1323.020000 891.620000 1323.500000 ;
+ RECT 890.520000 1328.460000 891.620000 1328.940000 ;
+ RECT 890.520000 1333.900000 891.620000 1334.380000 ;
+ RECT 890.520000 1339.340000 891.620000 1339.820000 ;
+ RECT 935.520000 1301.260000 936.620000 1301.740000 ;
+ RECT 935.520000 1306.700000 936.620000 1307.180000 ;
+ RECT 935.520000 1312.140000 936.620000 1312.620000 ;
+ RECT 935.520000 1317.580000 936.620000 1318.060000 ;
+ RECT 890.520000 1301.260000 891.620000 1301.740000 ;
+ RECT 890.520000 1306.700000 891.620000 1307.180000 ;
+ RECT 890.520000 1312.140000 891.620000 1312.620000 ;
+ RECT 890.520000 1317.580000 891.620000 1318.060000 ;
+ RECT 841.690000 1339.340000 842.690000 1339.820000 ;
+ RECT 845.355000 1339.340000 846.620000 1339.820000 ;
+ RECT 841.690000 1328.460000 842.690000 1328.940000 ;
+ RECT 845.355000 1328.460000 846.620000 1328.940000 ;
+ RECT 841.690000 1333.900000 842.690000 1334.380000 ;
+ RECT 845.355000 1333.900000 846.620000 1334.380000 ;
+ RECT 841.690000 1323.020000 842.690000 1323.500000 ;
+ RECT 845.355000 1323.020000 846.620000 1323.500000 ;
+ RECT 841.690000 1317.580000 842.690000 1318.060000 ;
+ RECT 845.355000 1317.580000 846.620000 1318.060000 ;
+ RECT 841.690000 1312.140000 842.690000 1312.620000 ;
+ RECT 845.355000 1312.140000 846.620000 1312.620000 ;
+ RECT 841.690000 1306.700000 842.690000 1307.180000 ;
+ RECT 845.355000 1306.700000 846.620000 1307.180000 ;
+ RECT 841.690000 1301.260000 842.690000 1301.740000 ;
+ RECT 845.355000 1301.260000 846.620000 1301.740000 ;
+ RECT 935.520000 1274.060000 936.620000 1274.540000 ;
+ RECT 935.520000 1279.500000 936.620000 1279.980000 ;
+ RECT 935.520000 1284.940000 936.620000 1285.420000 ;
+ RECT 935.520000 1290.380000 936.620000 1290.860000 ;
+ RECT 935.520000 1295.820000 936.620000 1296.300000 ;
+ RECT 890.520000 1274.060000 891.620000 1274.540000 ;
+ RECT 890.520000 1279.500000 891.620000 1279.980000 ;
+ RECT 890.520000 1284.940000 891.620000 1285.420000 ;
+ RECT 890.520000 1290.380000 891.620000 1290.860000 ;
+ RECT 890.520000 1295.820000 891.620000 1296.300000 ;
+ RECT 935.520000 1252.300000 936.620000 1252.780000 ;
+ RECT 935.520000 1257.740000 936.620000 1258.220000 ;
+ RECT 935.520000 1263.180000 936.620000 1263.660000 ;
+ RECT 935.520000 1268.620000 936.620000 1269.100000 ;
+ RECT 890.520000 1252.300000 891.620000 1252.780000 ;
+ RECT 890.520000 1257.740000 891.620000 1258.220000 ;
+ RECT 890.520000 1263.180000 891.620000 1263.660000 ;
+ RECT 890.520000 1268.620000 891.620000 1269.100000 ;
+ RECT 841.690000 1295.820000 842.690000 1296.300000 ;
+ RECT 845.355000 1295.820000 846.620000 1296.300000 ;
+ RECT 841.690000 1284.940000 842.690000 1285.420000 ;
+ RECT 845.355000 1284.940000 846.620000 1285.420000 ;
+ RECT 841.690000 1290.380000 842.690000 1290.860000 ;
+ RECT 845.355000 1290.380000 846.620000 1290.860000 ;
+ RECT 841.690000 1279.500000 842.690000 1279.980000 ;
+ RECT 845.355000 1279.500000 846.620000 1279.980000 ;
+ RECT 841.690000 1274.060000 842.690000 1274.540000 ;
+ RECT 845.355000 1274.060000 846.620000 1274.540000 ;
+ RECT 841.690000 1268.620000 842.690000 1269.100000 ;
+ RECT 845.355000 1268.620000 846.620000 1269.100000 ;
+ RECT 841.690000 1263.180000 842.690000 1263.660000 ;
+ RECT 845.355000 1263.180000 846.620000 1263.660000 ;
+ RECT 841.690000 1257.740000 842.690000 1258.220000 ;
+ RECT 845.355000 1257.740000 846.620000 1258.220000 ;
+ RECT 841.690000 1252.300000 842.690000 1252.780000 ;
+ RECT 845.355000 1252.300000 846.620000 1252.780000 ;
+ RECT 1025.520000 1235.980000 1026.620000 1236.460000 ;
+ RECT 1025.520000 1241.420000 1026.620000 1241.900000 ;
+ RECT 1038.330000 1235.980000 1039.330000 1236.460000 ;
+ RECT 1038.330000 1241.420000 1039.330000 1241.900000 ;
+ RECT 1038.330000 1225.100000 1039.330000 1225.580000 ;
+ RECT 1038.330000 1230.540000 1039.330000 1231.020000 ;
+ RECT 1025.520000 1230.540000 1026.620000 1231.020000 ;
+ RECT 1025.520000 1225.100000 1026.620000 1225.580000 ;
+ RECT 1025.520000 1214.220000 1026.620000 1214.700000 ;
+ RECT 1025.520000 1219.660000 1026.620000 1220.140000 ;
+ RECT 1038.330000 1214.220000 1039.330000 1214.700000 ;
+ RECT 1038.330000 1219.660000 1039.330000 1220.140000 ;
+ RECT 1038.330000 1203.340000 1039.330000 1203.820000 ;
+ RECT 1038.330000 1197.900000 1039.330000 1198.380000 ;
+ RECT 1038.330000 1208.780000 1039.330000 1209.260000 ;
+ RECT 1025.520000 1208.780000 1026.620000 1209.260000 ;
+ RECT 1025.520000 1203.340000 1026.620000 1203.820000 ;
+ RECT 1025.520000 1197.900000 1026.620000 1198.380000 ;
+ RECT 980.520000 1225.100000 981.620000 1225.580000 ;
+ RECT 980.520000 1230.540000 981.620000 1231.020000 ;
+ RECT 980.520000 1235.980000 981.620000 1236.460000 ;
+ RECT 980.520000 1241.420000 981.620000 1241.900000 ;
+ RECT 980.520000 1197.900000 981.620000 1198.380000 ;
+ RECT 980.520000 1203.340000 981.620000 1203.820000 ;
+ RECT 980.520000 1208.780000 981.620000 1209.260000 ;
+ RECT 980.520000 1214.220000 981.620000 1214.700000 ;
+ RECT 980.520000 1219.660000 981.620000 1220.140000 ;
+ RECT 1025.520000 1187.020000 1026.620000 1187.500000 ;
+ RECT 1025.520000 1192.460000 1026.620000 1192.940000 ;
+ RECT 1038.330000 1187.020000 1039.330000 1187.500000 ;
+ RECT 1038.330000 1192.460000 1039.330000 1192.940000 ;
+ RECT 1025.520000 1176.140000 1026.620000 1176.620000 ;
+ RECT 1025.520000 1181.580000 1026.620000 1182.060000 ;
+ RECT 1038.330000 1176.140000 1039.330000 1176.620000 ;
+ RECT 1038.330000 1181.580000 1039.330000 1182.060000 ;
+ RECT 1038.330000 1165.260000 1039.330000 1165.740000 ;
+ RECT 1038.330000 1159.820000 1039.330000 1160.300000 ;
+ RECT 1038.330000 1170.700000 1039.330000 1171.180000 ;
+ RECT 1025.520000 1170.700000 1026.620000 1171.180000 ;
+ RECT 1025.520000 1165.260000 1026.620000 1165.740000 ;
+ RECT 1025.520000 1159.820000 1026.620000 1160.300000 ;
+ RECT 1025.520000 1154.380000 1026.620000 1154.860000 ;
+ RECT 1038.330000 1154.380000 1039.330000 1154.860000 ;
+ RECT 980.520000 1176.140000 981.620000 1176.620000 ;
+ RECT 980.520000 1181.580000 981.620000 1182.060000 ;
+ RECT 980.520000 1187.020000 981.620000 1187.500000 ;
+ RECT 980.520000 1192.460000 981.620000 1192.940000 ;
+ RECT 980.520000 1154.380000 981.620000 1154.860000 ;
+ RECT 980.520000 1159.820000 981.620000 1160.300000 ;
+ RECT 980.520000 1165.260000 981.620000 1165.740000 ;
+ RECT 980.520000 1170.700000 981.620000 1171.180000 ;
+ RECT 935.520000 1225.100000 936.620000 1225.580000 ;
+ RECT 935.520000 1230.540000 936.620000 1231.020000 ;
+ RECT 935.520000 1235.980000 936.620000 1236.460000 ;
+ RECT 935.520000 1241.420000 936.620000 1241.900000 ;
+ RECT 890.520000 1225.100000 891.620000 1225.580000 ;
+ RECT 890.520000 1230.540000 891.620000 1231.020000 ;
+ RECT 890.520000 1235.980000 891.620000 1236.460000 ;
+ RECT 890.520000 1241.420000 891.620000 1241.900000 ;
+ RECT 935.520000 1197.900000 936.620000 1198.380000 ;
+ RECT 935.520000 1203.340000 936.620000 1203.820000 ;
+ RECT 935.520000 1208.780000 936.620000 1209.260000 ;
+ RECT 935.520000 1214.220000 936.620000 1214.700000 ;
+ RECT 935.520000 1219.660000 936.620000 1220.140000 ;
+ RECT 890.520000 1197.900000 891.620000 1198.380000 ;
+ RECT 890.520000 1203.340000 891.620000 1203.820000 ;
+ RECT 890.520000 1208.780000 891.620000 1209.260000 ;
+ RECT 890.520000 1214.220000 891.620000 1214.700000 ;
+ RECT 890.520000 1219.660000 891.620000 1220.140000 ;
+ RECT 841.690000 1241.420000 842.690000 1241.900000 ;
+ RECT 845.355000 1241.420000 846.620000 1241.900000 ;
+ RECT 841.690000 1235.980000 842.690000 1236.460000 ;
+ RECT 845.355000 1235.980000 846.620000 1236.460000 ;
+ RECT 841.690000 1230.540000 842.690000 1231.020000 ;
+ RECT 845.355000 1230.540000 846.620000 1231.020000 ;
+ RECT 841.690000 1225.100000 842.690000 1225.580000 ;
+ RECT 845.355000 1225.100000 846.620000 1225.580000 ;
+ RECT 841.690000 1219.660000 842.690000 1220.140000 ;
+ RECT 845.355000 1219.660000 846.620000 1220.140000 ;
+ RECT 841.690000 1214.220000 842.690000 1214.700000 ;
+ RECT 845.355000 1214.220000 846.620000 1214.700000 ;
+ RECT 841.690000 1203.340000 842.690000 1203.820000 ;
+ RECT 845.355000 1203.340000 846.620000 1203.820000 ;
+ RECT 841.690000 1208.780000 842.690000 1209.260000 ;
+ RECT 845.355000 1208.780000 846.620000 1209.260000 ;
+ RECT 841.690000 1197.900000 842.690000 1198.380000 ;
+ RECT 845.355000 1197.900000 846.620000 1198.380000 ;
+ RECT 935.520000 1176.140000 936.620000 1176.620000 ;
+ RECT 935.520000 1181.580000 936.620000 1182.060000 ;
+ RECT 935.520000 1187.020000 936.620000 1187.500000 ;
+ RECT 935.520000 1192.460000 936.620000 1192.940000 ;
+ RECT 890.520000 1176.140000 891.620000 1176.620000 ;
+ RECT 890.520000 1181.580000 891.620000 1182.060000 ;
+ RECT 890.520000 1187.020000 891.620000 1187.500000 ;
+ RECT 890.520000 1192.460000 891.620000 1192.940000 ;
+ RECT 935.520000 1154.380000 936.620000 1154.860000 ;
+ RECT 935.520000 1159.820000 936.620000 1160.300000 ;
+ RECT 935.520000 1165.260000 936.620000 1165.740000 ;
+ RECT 935.520000 1170.700000 936.620000 1171.180000 ;
+ RECT 890.520000 1154.380000 891.620000 1154.860000 ;
+ RECT 890.520000 1159.820000 891.620000 1160.300000 ;
+ RECT 890.520000 1165.260000 891.620000 1165.740000 ;
+ RECT 890.520000 1170.700000 891.620000 1171.180000 ;
+ RECT 841.690000 1192.460000 842.690000 1192.940000 ;
+ RECT 845.355000 1192.460000 846.620000 1192.940000 ;
+ RECT 841.690000 1187.020000 842.690000 1187.500000 ;
+ RECT 845.355000 1187.020000 846.620000 1187.500000 ;
+ RECT 841.690000 1181.580000 842.690000 1182.060000 ;
+ RECT 845.355000 1181.580000 846.620000 1182.060000 ;
+ RECT 841.690000 1176.140000 842.690000 1176.620000 ;
+ RECT 845.355000 1176.140000 846.620000 1176.620000 ;
+ RECT 841.690000 1170.700000 842.690000 1171.180000 ;
+ RECT 845.355000 1170.700000 846.620000 1171.180000 ;
+ RECT 841.690000 1159.820000 842.690000 1160.300000 ;
+ RECT 845.355000 1159.820000 846.620000 1160.300000 ;
+ RECT 841.690000 1165.260000 842.690000 1165.740000 ;
+ RECT 845.355000 1165.260000 846.620000 1165.740000 ;
+ RECT 841.690000 1154.380000 842.690000 1154.860000 ;
+ RECT 845.355000 1154.380000 846.620000 1154.860000 ;
+ RECT 980.520000 1246.860000 981.620000 1247.340000 ;
+ RECT 1025.520000 1246.860000 1026.620000 1247.340000 ;
+ RECT 1038.330000 1246.860000 1039.330000 1247.340000 ;
+ RECT 890.520000 1246.860000 891.620000 1247.340000 ;
+ RECT 935.520000 1246.860000 936.620000 1247.340000 ;
+ RECT 841.690000 1246.860000 842.690000 1247.340000 ;
+ RECT 845.355000 1246.860000 846.620000 1247.340000 ;
+ RECT 840.460000 1343.620000 1040.560000 1344.620000 ;
+ RECT 840.460000 1148.050000 1040.560000 1149.050000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 1146.800000 842.690000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 1346.060000 842.690000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 1146.800000 1039.330000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 1346.060000 1039.330000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1148.050000 841.460000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1148.050000 1040.560000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1343.620000 841.460000 1344.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1343.620000 1040.560000 1344.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 1139.080000 846.620000 1139.560000 ;
+ RECT 845.355000 1128.200000 846.620000 1128.680000 ;
+ RECT 845.355000 1133.640000 846.620000 1134.120000 ;
+ RECT 845.355000 1122.760000 846.620000 1123.240000 ;
+ RECT 845.355000 1117.320000 846.620000 1117.800000 ;
+ RECT 845.355000 1111.880000 846.620000 1112.360000 ;
+ RECT 845.355000 1106.440000 846.620000 1106.920000 ;
+ RECT 845.355000 1101.000000 846.620000 1101.480000 ;
+ RECT 845.355000 1095.560000 846.620000 1096.040000 ;
+ RECT 845.355000 1084.680000 846.620000 1085.160000 ;
+ RECT 845.355000 1090.120000 846.620000 1090.600000 ;
+ RECT 845.355000 1079.240000 846.620000 1079.720000 ;
+ RECT 845.355000 1073.800000 846.620000 1074.280000 ;
+ RECT 845.355000 1068.360000 846.620000 1068.840000 ;
+ RECT 845.355000 1062.920000 846.620000 1063.400000 ;
+ RECT 845.355000 1057.480000 846.620000 1057.960000 ;
+ RECT 845.355000 1052.040000 846.620000 1052.520000 ;
+ RECT 845.355000 1041.160000 846.620000 1041.640000 ;
+ RECT 845.355000 1035.720000 846.620000 1036.200000 ;
+ RECT 845.355000 1030.280000 846.620000 1030.760000 ;
+ RECT 845.355000 1024.840000 846.620000 1025.320000 ;
+ RECT 845.355000 1019.400000 846.620000 1019.880000 ;
+ RECT 845.355000 1013.960000 846.620000 1014.440000 ;
+ RECT 845.355000 1003.080000 846.620000 1003.560000 ;
+ RECT 845.355000 1008.520000 846.620000 1009.000000 ;
+ RECT 845.355000 997.640000 846.620000 998.120000 ;
+ RECT 845.355000 992.200000 846.620000 992.680000 ;
+ RECT 845.355000 986.760000 846.620000 987.240000 ;
+ RECT 845.355000 981.320000 846.620000 981.800000 ;
+ RECT 845.355000 975.880000 846.620000 976.360000 ;
+ RECT 845.355000 970.440000 846.620000 970.920000 ;
+ RECT 845.355000 959.560000 846.620000 960.040000 ;
+ RECT 845.355000 965.000000 846.620000 965.480000 ;
+ RECT 845.355000 954.120000 846.620000 954.600000 ;
+ RECT 845.355000 1046.600000 846.620000 1047.080000 ;
+ RECT 1025.520000 947.790000 1026.620000 1144.360000 ;
+ RECT 980.520000 947.790000 981.620000 1144.360000 ;
+ RECT 1038.330000 946.540000 1039.330000 1146.800000 ;
+ RECT 935.520000 947.790000 936.620000 1144.360000 ;
+ RECT 890.520000 947.790000 891.620000 1144.360000 ;
+ RECT 845.520000 947.790000 846.620000 1144.360000 ;
+ RECT 841.690000 946.540000 842.690000 1146.800000 ;
+ LAYER met3 ;
+ RECT 1025.520000 1139.080000 1026.620000 1139.560000 ;
+ RECT 1038.330000 1139.080000 1039.330000 1139.560000 ;
+ RECT 1038.330000 1128.200000 1039.330000 1128.680000 ;
+ RECT 1038.330000 1122.760000 1039.330000 1123.240000 ;
+ RECT 1038.330000 1133.640000 1039.330000 1134.120000 ;
+ RECT 1025.520000 1133.640000 1026.620000 1134.120000 ;
+ RECT 1025.520000 1128.200000 1026.620000 1128.680000 ;
+ RECT 1025.520000 1122.760000 1026.620000 1123.240000 ;
+ RECT 1025.520000 1111.880000 1026.620000 1112.360000 ;
+ RECT 1025.520000 1117.320000 1026.620000 1117.800000 ;
+ RECT 1038.330000 1111.880000 1039.330000 1112.360000 ;
+ RECT 1038.330000 1117.320000 1039.330000 1117.800000 ;
+ RECT 1025.520000 1101.000000 1026.620000 1101.480000 ;
+ RECT 1025.520000 1106.440000 1026.620000 1106.920000 ;
+ RECT 1038.330000 1101.000000 1039.330000 1101.480000 ;
+ RECT 1038.330000 1106.440000 1039.330000 1106.920000 ;
+ RECT 980.520000 1122.760000 981.620000 1123.240000 ;
+ RECT 980.520000 1128.200000 981.620000 1128.680000 ;
+ RECT 980.520000 1133.640000 981.620000 1134.120000 ;
+ RECT 980.520000 1139.080000 981.620000 1139.560000 ;
+ RECT 980.520000 1106.440000 981.620000 1106.920000 ;
+ RECT 980.520000 1101.000000 981.620000 1101.480000 ;
+ RECT 980.520000 1111.880000 981.620000 1112.360000 ;
+ RECT 980.520000 1117.320000 981.620000 1117.800000 ;
+ RECT 1038.330000 1090.120000 1039.330000 1090.600000 ;
+ RECT 1038.330000 1084.680000 1039.330000 1085.160000 ;
+ RECT 1038.330000 1095.560000 1039.330000 1096.040000 ;
+ RECT 1025.520000 1095.560000 1026.620000 1096.040000 ;
+ RECT 1025.520000 1090.120000 1026.620000 1090.600000 ;
+ RECT 1025.520000 1084.680000 1026.620000 1085.160000 ;
+ RECT 1025.520000 1073.800000 1026.620000 1074.280000 ;
+ RECT 1025.520000 1079.240000 1026.620000 1079.720000 ;
+ RECT 1038.330000 1073.800000 1039.330000 1074.280000 ;
+ RECT 1038.330000 1079.240000 1039.330000 1079.720000 ;
+ RECT 1038.330000 1062.920000 1039.330000 1063.400000 ;
+ RECT 1038.330000 1068.360000 1039.330000 1068.840000 ;
+ RECT 1025.520000 1068.360000 1026.620000 1068.840000 ;
+ RECT 1025.520000 1062.920000 1026.620000 1063.400000 ;
+ RECT 1025.520000 1052.040000 1026.620000 1052.520000 ;
+ RECT 1025.520000 1057.480000 1026.620000 1057.960000 ;
+ RECT 1038.330000 1052.040000 1039.330000 1052.520000 ;
+ RECT 1038.330000 1057.480000 1039.330000 1057.960000 ;
+ RECT 980.520000 1073.800000 981.620000 1074.280000 ;
+ RECT 980.520000 1079.240000 981.620000 1079.720000 ;
+ RECT 980.520000 1084.680000 981.620000 1085.160000 ;
+ RECT 980.520000 1090.120000 981.620000 1090.600000 ;
+ RECT 980.520000 1095.560000 981.620000 1096.040000 ;
+ RECT 980.520000 1052.040000 981.620000 1052.520000 ;
+ RECT 980.520000 1057.480000 981.620000 1057.960000 ;
+ RECT 980.520000 1062.920000 981.620000 1063.400000 ;
+ RECT 980.520000 1068.360000 981.620000 1068.840000 ;
+ RECT 935.520000 1128.200000 936.620000 1128.680000 ;
+ RECT 935.520000 1122.760000 936.620000 1123.240000 ;
+ RECT 935.520000 1133.640000 936.620000 1134.120000 ;
+ RECT 935.520000 1139.080000 936.620000 1139.560000 ;
+ RECT 890.520000 1122.760000 891.620000 1123.240000 ;
+ RECT 890.520000 1128.200000 891.620000 1128.680000 ;
+ RECT 890.520000 1133.640000 891.620000 1134.120000 ;
+ RECT 890.520000 1139.080000 891.620000 1139.560000 ;
+ RECT 935.520000 1101.000000 936.620000 1101.480000 ;
+ RECT 935.520000 1106.440000 936.620000 1106.920000 ;
+ RECT 935.520000 1111.880000 936.620000 1112.360000 ;
+ RECT 935.520000 1117.320000 936.620000 1117.800000 ;
+ RECT 890.520000 1101.000000 891.620000 1101.480000 ;
+ RECT 890.520000 1106.440000 891.620000 1106.920000 ;
+ RECT 890.520000 1111.880000 891.620000 1112.360000 ;
+ RECT 890.520000 1117.320000 891.620000 1117.800000 ;
+ RECT 841.690000 1139.080000 842.690000 1139.560000 ;
+ RECT 845.355000 1139.080000 846.620000 1139.560000 ;
+ RECT 841.690000 1128.200000 842.690000 1128.680000 ;
+ RECT 845.355000 1128.200000 846.620000 1128.680000 ;
+ RECT 841.690000 1133.640000 842.690000 1134.120000 ;
+ RECT 845.355000 1133.640000 846.620000 1134.120000 ;
+ RECT 841.690000 1122.760000 842.690000 1123.240000 ;
+ RECT 845.355000 1122.760000 846.620000 1123.240000 ;
+ RECT 841.690000 1117.320000 842.690000 1117.800000 ;
+ RECT 845.355000 1117.320000 846.620000 1117.800000 ;
+ RECT 841.690000 1111.880000 842.690000 1112.360000 ;
+ RECT 845.355000 1111.880000 846.620000 1112.360000 ;
+ RECT 841.690000 1106.440000 842.690000 1106.920000 ;
+ RECT 845.355000 1106.440000 846.620000 1106.920000 ;
+ RECT 841.690000 1101.000000 842.690000 1101.480000 ;
+ RECT 845.355000 1101.000000 846.620000 1101.480000 ;
+ RECT 935.520000 1073.800000 936.620000 1074.280000 ;
+ RECT 935.520000 1079.240000 936.620000 1079.720000 ;
+ RECT 935.520000 1084.680000 936.620000 1085.160000 ;
+ RECT 935.520000 1090.120000 936.620000 1090.600000 ;
+ RECT 935.520000 1095.560000 936.620000 1096.040000 ;
+ RECT 890.520000 1073.800000 891.620000 1074.280000 ;
+ RECT 890.520000 1079.240000 891.620000 1079.720000 ;
+ RECT 890.520000 1084.680000 891.620000 1085.160000 ;
+ RECT 890.520000 1090.120000 891.620000 1090.600000 ;
+ RECT 890.520000 1095.560000 891.620000 1096.040000 ;
+ RECT 935.520000 1052.040000 936.620000 1052.520000 ;
+ RECT 935.520000 1057.480000 936.620000 1057.960000 ;
+ RECT 935.520000 1062.920000 936.620000 1063.400000 ;
+ RECT 935.520000 1068.360000 936.620000 1068.840000 ;
+ RECT 890.520000 1052.040000 891.620000 1052.520000 ;
+ RECT 890.520000 1057.480000 891.620000 1057.960000 ;
+ RECT 890.520000 1062.920000 891.620000 1063.400000 ;
+ RECT 890.520000 1068.360000 891.620000 1068.840000 ;
+ RECT 841.690000 1095.560000 842.690000 1096.040000 ;
+ RECT 845.355000 1095.560000 846.620000 1096.040000 ;
+ RECT 841.690000 1084.680000 842.690000 1085.160000 ;
+ RECT 845.355000 1084.680000 846.620000 1085.160000 ;
+ RECT 841.690000 1090.120000 842.690000 1090.600000 ;
+ RECT 845.355000 1090.120000 846.620000 1090.600000 ;
+ RECT 841.690000 1079.240000 842.690000 1079.720000 ;
+ RECT 845.355000 1079.240000 846.620000 1079.720000 ;
+ RECT 841.690000 1073.800000 842.690000 1074.280000 ;
+ RECT 845.355000 1073.800000 846.620000 1074.280000 ;
+ RECT 841.690000 1068.360000 842.690000 1068.840000 ;
+ RECT 845.355000 1068.360000 846.620000 1068.840000 ;
+ RECT 841.690000 1062.920000 842.690000 1063.400000 ;
+ RECT 845.355000 1062.920000 846.620000 1063.400000 ;
+ RECT 841.690000 1057.480000 842.690000 1057.960000 ;
+ RECT 845.355000 1057.480000 846.620000 1057.960000 ;
+ RECT 841.690000 1052.040000 842.690000 1052.520000 ;
+ RECT 845.355000 1052.040000 846.620000 1052.520000 ;
+ RECT 1025.520000 1035.720000 1026.620000 1036.200000 ;
+ RECT 1025.520000 1041.160000 1026.620000 1041.640000 ;
+ RECT 1038.330000 1035.720000 1039.330000 1036.200000 ;
+ RECT 1038.330000 1041.160000 1039.330000 1041.640000 ;
+ RECT 1038.330000 1024.840000 1039.330000 1025.320000 ;
+ RECT 1038.330000 1030.280000 1039.330000 1030.760000 ;
+ RECT 1025.520000 1030.280000 1026.620000 1030.760000 ;
+ RECT 1025.520000 1024.840000 1026.620000 1025.320000 ;
+ RECT 1025.520000 1013.960000 1026.620000 1014.440000 ;
+ RECT 1025.520000 1019.400000 1026.620000 1019.880000 ;
+ RECT 1038.330000 1013.960000 1039.330000 1014.440000 ;
+ RECT 1038.330000 1019.400000 1039.330000 1019.880000 ;
+ RECT 1038.330000 1003.080000 1039.330000 1003.560000 ;
+ RECT 1038.330000 997.640000 1039.330000 998.120000 ;
+ RECT 1038.330000 1008.520000 1039.330000 1009.000000 ;
+ RECT 1025.520000 1008.520000 1026.620000 1009.000000 ;
+ RECT 1025.520000 1003.080000 1026.620000 1003.560000 ;
+ RECT 1025.520000 997.640000 1026.620000 998.120000 ;
+ RECT 980.520000 1024.840000 981.620000 1025.320000 ;
+ RECT 980.520000 1030.280000 981.620000 1030.760000 ;
+ RECT 980.520000 1035.720000 981.620000 1036.200000 ;
+ RECT 980.520000 1041.160000 981.620000 1041.640000 ;
+ RECT 980.520000 997.640000 981.620000 998.120000 ;
+ RECT 980.520000 1003.080000 981.620000 1003.560000 ;
+ RECT 980.520000 1008.520000 981.620000 1009.000000 ;
+ RECT 980.520000 1013.960000 981.620000 1014.440000 ;
+ RECT 980.520000 1019.400000 981.620000 1019.880000 ;
+ RECT 1025.520000 986.760000 1026.620000 987.240000 ;
+ RECT 1025.520000 992.200000 1026.620000 992.680000 ;
+ RECT 1038.330000 986.760000 1039.330000 987.240000 ;
+ RECT 1038.330000 992.200000 1039.330000 992.680000 ;
+ RECT 1025.520000 975.880000 1026.620000 976.360000 ;
+ RECT 1025.520000 981.320000 1026.620000 981.800000 ;
+ RECT 1038.330000 975.880000 1039.330000 976.360000 ;
+ RECT 1038.330000 981.320000 1039.330000 981.800000 ;
+ RECT 1038.330000 965.000000 1039.330000 965.480000 ;
+ RECT 1038.330000 959.560000 1039.330000 960.040000 ;
+ RECT 1038.330000 970.440000 1039.330000 970.920000 ;
+ RECT 1025.520000 970.440000 1026.620000 970.920000 ;
+ RECT 1025.520000 965.000000 1026.620000 965.480000 ;
+ RECT 1025.520000 959.560000 1026.620000 960.040000 ;
+ RECT 1025.520000 954.120000 1026.620000 954.600000 ;
+ RECT 1038.330000 954.120000 1039.330000 954.600000 ;
+ RECT 980.520000 975.880000 981.620000 976.360000 ;
+ RECT 980.520000 981.320000 981.620000 981.800000 ;
+ RECT 980.520000 986.760000 981.620000 987.240000 ;
+ RECT 980.520000 992.200000 981.620000 992.680000 ;
+ RECT 980.520000 954.120000 981.620000 954.600000 ;
+ RECT 980.520000 959.560000 981.620000 960.040000 ;
+ RECT 980.520000 965.000000 981.620000 965.480000 ;
+ RECT 980.520000 970.440000 981.620000 970.920000 ;
+ RECT 935.520000 1024.840000 936.620000 1025.320000 ;
+ RECT 935.520000 1030.280000 936.620000 1030.760000 ;
+ RECT 935.520000 1035.720000 936.620000 1036.200000 ;
+ RECT 935.520000 1041.160000 936.620000 1041.640000 ;
+ RECT 890.520000 1024.840000 891.620000 1025.320000 ;
+ RECT 890.520000 1030.280000 891.620000 1030.760000 ;
+ RECT 890.520000 1035.720000 891.620000 1036.200000 ;
+ RECT 890.520000 1041.160000 891.620000 1041.640000 ;
+ RECT 935.520000 997.640000 936.620000 998.120000 ;
+ RECT 935.520000 1003.080000 936.620000 1003.560000 ;
+ RECT 935.520000 1008.520000 936.620000 1009.000000 ;
+ RECT 935.520000 1013.960000 936.620000 1014.440000 ;
+ RECT 935.520000 1019.400000 936.620000 1019.880000 ;
+ RECT 890.520000 997.640000 891.620000 998.120000 ;
+ RECT 890.520000 1003.080000 891.620000 1003.560000 ;
+ RECT 890.520000 1008.520000 891.620000 1009.000000 ;
+ RECT 890.520000 1013.960000 891.620000 1014.440000 ;
+ RECT 890.520000 1019.400000 891.620000 1019.880000 ;
+ RECT 841.690000 1041.160000 842.690000 1041.640000 ;
+ RECT 845.355000 1041.160000 846.620000 1041.640000 ;
+ RECT 841.690000 1035.720000 842.690000 1036.200000 ;
+ RECT 845.355000 1035.720000 846.620000 1036.200000 ;
+ RECT 841.690000 1030.280000 842.690000 1030.760000 ;
+ RECT 845.355000 1030.280000 846.620000 1030.760000 ;
+ RECT 841.690000 1024.840000 842.690000 1025.320000 ;
+ RECT 845.355000 1024.840000 846.620000 1025.320000 ;
+ RECT 841.690000 1019.400000 842.690000 1019.880000 ;
+ RECT 845.355000 1019.400000 846.620000 1019.880000 ;
+ RECT 841.690000 1013.960000 842.690000 1014.440000 ;
+ RECT 845.355000 1013.960000 846.620000 1014.440000 ;
+ RECT 841.690000 1003.080000 842.690000 1003.560000 ;
+ RECT 845.355000 1003.080000 846.620000 1003.560000 ;
+ RECT 841.690000 1008.520000 842.690000 1009.000000 ;
+ RECT 845.355000 1008.520000 846.620000 1009.000000 ;
+ RECT 841.690000 997.640000 842.690000 998.120000 ;
+ RECT 845.355000 997.640000 846.620000 998.120000 ;
+ RECT 935.520000 975.880000 936.620000 976.360000 ;
+ RECT 935.520000 981.320000 936.620000 981.800000 ;
+ RECT 935.520000 986.760000 936.620000 987.240000 ;
+ RECT 935.520000 992.200000 936.620000 992.680000 ;
+ RECT 890.520000 975.880000 891.620000 976.360000 ;
+ RECT 890.520000 981.320000 891.620000 981.800000 ;
+ RECT 890.520000 986.760000 891.620000 987.240000 ;
+ RECT 890.520000 992.200000 891.620000 992.680000 ;
+ RECT 935.520000 954.120000 936.620000 954.600000 ;
+ RECT 935.520000 959.560000 936.620000 960.040000 ;
+ RECT 935.520000 965.000000 936.620000 965.480000 ;
+ RECT 935.520000 970.440000 936.620000 970.920000 ;
+ RECT 890.520000 954.120000 891.620000 954.600000 ;
+ RECT 890.520000 959.560000 891.620000 960.040000 ;
+ RECT 890.520000 965.000000 891.620000 965.480000 ;
+ RECT 890.520000 970.440000 891.620000 970.920000 ;
+ RECT 841.690000 992.200000 842.690000 992.680000 ;
+ RECT 845.355000 992.200000 846.620000 992.680000 ;
+ RECT 841.690000 986.760000 842.690000 987.240000 ;
+ RECT 845.355000 986.760000 846.620000 987.240000 ;
+ RECT 841.690000 981.320000 842.690000 981.800000 ;
+ RECT 845.355000 981.320000 846.620000 981.800000 ;
+ RECT 841.690000 975.880000 842.690000 976.360000 ;
+ RECT 845.355000 975.880000 846.620000 976.360000 ;
+ RECT 841.690000 970.440000 842.690000 970.920000 ;
+ RECT 845.355000 970.440000 846.620000 970.920000 ;
+ RECT 841.690000 959.560000 842.690000 960.040000 ;
+ RECT 845.355000 959.560000 846.620000 960.040000 ;
+ RECT 841.690000 965.000000 842.690000 965.480000 ;
+ RECT 845.355000 965.000000 846.620000 965.480000 ;
+ RECT 841.690000 954.120000 842.690000 954.600000 ;
+ RECT 845.355000 954.120000 846.620000 954.600000 ;
+ RECT 980.520000 1046.600000 981.620000 1047.080000 ;
+ RECT 1025.520000 1046.600000 1026.620000 1047.080000 ;
+ RECT 1038.330000 1046.600000 1039.330000 1047.080000 ;
+ RECT 890.520000 1046.600000 891.620000 1047.080000 ;
+ RECT 935.520000 1046.600000 936.620000 1047.080000 ;
+ RECT 841.690000 1046.600000 842.690000 1047.080000 ;
+ RECT 845.355000 1046.600000 846.620000 1047.080000 ;
+ RECT 840.460000 1143.360000 1040.560000 1144.360000 ;
+ RECT 840.460000 947.790000 1040.560000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 946.540000 842.690000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 1145.800000 842.690000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 946.540000 1039.330000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 1145.800000 1039.330000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 947.790000 841.460000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 947.790000 1040.560000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1143.360000 841.460000 1144.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1143.360000 1040.560000 1144.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 938.820000 846.620000 939.300000 ;
+ RECT 845.355000 927.940000 846.620000 928.420000 ;
+ RECT 845.355000 933.380000 846.620000 933.860000 ;
+ RECT 845.355000 922.500000 846.620000 922.980000 ;
+ RECT 845.355000 917.060000 846.620000 917.540000 ;
+ RECT 845.355000 911.620000 846.620000 912.100000 ;
+ RECT 845.355000 906.180000 846.620000 906.660000 ;
+ RECT 845.355000 900.740000 846.620000 901.220000 ;
+ RECT 845.355000 895.300000 846.620000 895.780000 ;
+ RECT 845.355000 884.420000 846.620000 884.900000 ;
+ RECT 845.355000 889.860000 846.620000 890.340000 ;
+ RECT 845.355000 878.980000 846.620000 879.460000 ;
+ RECT 845.355000 873.540000 846.620000 874.020000 ;
+ RECT 845.355000 868.100000 846.620000 868.580000 ;
+ RECT 845.355000 862.660000 846.620000 863.140000 ;
+ RECT 845.355000 857.220000 846.620000 857.700000 ;
+ RECT 845.355000 851.780000 846.620000 852.260000 ;
+ RECT 845.355000 840.900000 846.620000 841.380000 ;
+ RECT 845.355000 835.460000 846.620000 835.940000 ;
+ RECT 845.355000 830.020000 846.620000 830.500000 ;
+ RECT 845.355000 824.580000 846.620000 825.060000 ;
+ RECT 845.355000 819.140000 846.620000 819.620000 ;
+ RECT 845.355000 813.700000 846.620000 814.180000 ;
+ RECT 845.355000 802.820000 846.620000 803.300000 ;
+ RECT 845.355000 808.260000 846.620000 808.740000 ;
+ RECT 845.355000 797.380000 846.620000 797.860000 ;
+ RECT 845.355000 791.940000 846.620000 792.420000 ;
+ RECT 845.355000 786.500000 846.620000 786.980000 ;
+ RECT 845.355000 781.060000 846.620000 781.540000 ;
+ RECT 845.355000 775.620000 846.620000 776.100000 ;
+ RECT 845.355000 770.180000 846.620000 770.660000 ;
+ RECT 845.355000 759.300000 846.620000 759.780000 ;
+ RECT 845.355000 764.740000 846.620000 765.220000 ;
+ RECT 845.355000 753.860000 846.620000 754.340000 ;
+ RECT 845.355000 846.340000 846.620000 846.820000 ;
+ RECT 1025.520000 747.530000 1026.620000 944.100000 ;
+ RECT 980.520000 747.530000 981.620000 944.100000 ;
+ RECT 1038.330000 746.280000 1039.330000 946.540000 ;
+ RECT 935.520000 747.530000 936.620000 944.100000 ;
+ RECT 890.520000 747.530000 891.620000 944.100000 ;
+ RECT 845.520000 747.530000 846.620000 944.100000 ;
+ RECT 841.690000 746.280000 842.690000 946.540000 ;
+ LAYER met3 ;
+ RECT 1025.520000 938.820000 1026.620000 939.300000 ;
+ RECT 1038.330000 938.820000 1039.330000 939.300000 ;
+ RECT 1038.330000 927.940000 1039.330000 928.420000 ;
+ RECT 1038.330000 922.500000 1039.330000 922.980000 ;
+ RECT 1038.330000 933.380000 1039.330000 933.860000 ;
+ RECT 1025.520000 933.380000 1026.620000 933.860000 ;
+ RECT 1025.520000 927.940000 1026.620000 928.420000 ;
+ RECT 1025.520000 922.500000 1026.620000 922.980000 ;
+ RECT 1025.520000 911.620000 1026.620000 912.100000 ;
+ RECT 1025.520000 917.060000 1026.620000 917.540000 ;
+ RECT 1038.330000 911.620000 1039.330000 912.100000 ;
+ RECT 1038.330000 917.060000 1039.330000 917.540000 ;
+ RECT 1025.520000 900.740000 1026.620000 901.220000 ;
+ RECT 1025.520000 906.180000 1026.620000 906.660000 ;
+ RECT 1038.330000 900.740000 1039.330000 901.220000 ;
+ RECT 1038.330000 906.180000 1039.330000 906.660000 ;
+ RECT 980.520000 922.500000 981.620000 922.980000 ;
+ RECT 980.520000 927.940000 981.620000 928.420000 ;
+ RECT 980.520000 933.380000 981.620000 933.860000 ;
+ RECT 980.520000 938.820000 981.620000 939.300000 ;
+ RECT 980.520000 906.180000 981.620000 906.660000 ;
+ RECT 980.520000 900.740000 981.620000 901.220000 ;
+ RECT 980.520000 911.620000 981.620000 912.100000 ;
+ RECT 980.520000 917.060000 981.620000 917.540000 ;
+ RECT 1038.330000 889.860000 1039.330000 890.340000 ;
+ RECT 1038.330000 884.420000 1039.330000 884.900000 ;
+ RECT 1038.330000 895.300000 1039.330000 895.780000 ;
+ RECT 1025.520000 895.300000 1026.620000 895.780000 ;
+ RECT 1025.520000 889.860000 1026.620000 890.340000 ;
+ RECT 1025.520000 884.420000 1026.620000 884.900000 ;
+ RECT 1025.520000 873.540000 1026.620000 874.020000 ;
+ RECT 1025.520000 878.980000 1026.620000 879.460000 ;
+ RECT 1038.330000 873.540000 1039.330000 874.020000 ;
+ RECT 1038.330000 878.980000 1039.330000 879.460000 ;
+ RECT 1038.330000 862.660000 1039.330000 863.140000 ;
+ RECT 1038.330000 868.100000 1039.330000 868.580000 ;
+ RECT 1025.520000 868.100000 1026.620000 868.580000 ;
+ RECT 1025.520000 862.660000 1026.620000 863.140000 ;
+ RECT 1025.520000 851.780000 1026.620000 852.260000 ;
+ RECT 1025.520000 857.220000 1026.620000 857.700000 ;
+ RECT 1038.330000 851.780000 1039.330000 852.260000 ;
+ RECT 1038.330000 857.220000 1039.330000 857.700000 ;
+ RECT 980.520000 873.540000 981.620000 874.020000 ;
+ RECT 980.520000 878.980000 981.620000 879.460000 ;
+ RECT 980.520000 884.420000 981.620000 884.900000 ;
+ RECT 980.520000 889.860000 981.620000 890.340000 ;
+ RECT 980.520000 895.300000 981.620000 895.780000 ;
+ RECT 980.520000 851.780000 981.620000 852.260000 ;
+ RECT 980.520000 857.220000 981.620000 857.700000 ;
+ RECT 980.520000 862.660000 981.620000 863.140000 ;
+ RECT 980.520000 868.100000 981.620000 868.580000 ;
+ RECT 935.520000 927.940000 936.620000 928.420000 ;
+ RECT 935.520000 922.500000 936.620000 922.980000 ;
+ RECT 935.520000 933.380000 936.620000 933.860000 ;
+ RECT 935.520000 938.820000 936.620000 939.300000 ;
+ RECT 890.520000 922.500000 891.620000 922.980000 ;
+ RECT 890.520000 927.940000 891.620000 928.420000 ;
+ RECT 890.520000 933.380000 891.620000 933.860000 ;
+ RECT 890.520000 938.820000 891.620000 939.300000 ;
+ RECT 935.520000 900.740000 936.620000 901.220000 ;
+ RECT 935.520000 906.180000 936.620000 906.660000 ;
+ RECT 935.520000 911.620000 936.620000 912.100000 ;
+ RECT 935.520000 917.060000 936.620000 917.540000 ;
+ RECT 890.520000 900.740000 891.620000 901.220000 ;
+ RECT 890.520000 906.180000 891.620000 906.660000 ;
+ RECT 890.520000 911.620000 891.620000 912.100000 ;
+ RECT 890.520000 917.060000 891.620000 917.540000 ;
+ RECT 841.690000 938.820000 842.690000 939.300000 ;
+ RECT 845.355000 938.820000 846.620000 939.300000 ;
+ RECT 841.690000 927.940000 842.690000 928.420000 ;
+ RECT 845.355000 927.940000 846.620000 928.420000 ;
+ RECT 841.690000 933.380000 842.690000 933.860000 ;
+ RECT 845.355000 933.380000 846.620000 933.860000 ;
+ RECT 841.690000 922.500000 842.690000 922.980000 ;
+ RECT 845.355000 922.500000 846.620000 922.980000 ;
+ RECT 841.690000 917.060000 842.690000 917.540000 ;
+ RECT 845.355000 917.060000 846.620000 917.540000 ;
+ RECT 841.690000 911.620000 842.690000 912.100000 ;
+ RECT 845.355000 911.620000 846.620000 912.100000 ;
+ RECT 841.690000 906.180000 842.690000 906.660000 ;
+ RECT 845.355000 906.180000 846.620000 906.660000 ;
+ RECT 841.690000 900.740000 842.690000 901.220000 ;
+ RECT 845.355000 900.740000 846.620000 901.220000 ;
+ RECT 935.520000 873.540000 936.620000 874.020000 ;
+ RECT 935.520000 878.980000 936.620000 879.460000 ;
+ RECT 935.520000 884.420000 936.620000 884.900000 ;
+ RECT 935.520000 889.860000 936.620000 890.340000 ;
+ RECT 935.520000 895.300000 936.620000 895.780000 ;
+ RECT 890.520000 873.540000 891.620000 874.020000 ;
+ RECT 890.520000 878.980000 891.620000 879.460000 ;
+ RECT 890.520000 884.420000 891.620000 884.900000 ;
+ RECT 890.520000 889.860000 891.620000 890.340000 ;
+ RECT 890.520000 895.300000 891.620000 895.780000 ;
+ RECT 935.520000 851.780000 936.620000 852.260000 ;
+ RECT 935.520000 857.220000 936.620000 857.700000 ;
+ RECT 935.520000 862.660000 936.620000 863.140000 ;
+ RECT 935.520000 868.100000 936.620000 868.580000 ;
+ RECT 890.520000 851.780000 891.620000 852.260000 ;
+ RECT 890.520000 857.220000 891.620000 857.700000 ;
+ RECT 890.520000 862.660000 891.620000 863.140000 ;
+ RECT 890.520000 868.100000 891.620000 868.580000 ;
+ RECT 841.690000 895.300000 842.690000 895.780000 ;
+ RECT 845.355000 895.300000 846.620000 895.780000 ;
+ RECT 841.690000 884.420000 842.690000 884.900000 ;
+ RECT 845.355000 884.420000 846.620000 884.900000 ;
+ RECT 841.690000 889.860000 842.690000 890.340000 ;
+ RECT 845.355000 889.860000 846.620000 890.340000 ;
+ RECT 841.690000 878.980000 842.690000 879.460000 ;
+ RECT 845.355000 878.980000 846.620000 879.460000 ;
+ RECT 841.690000 873.540000 842.690000 874.020000 ;
+ RECT 845.355000 873.540000 846.620000 874.020000 ;
+ RECT 841.690000 868.100000 842.690000 868.580000 ;
+ RECT 845.355000 868.100000 846.620000 868.580000 ;
+ RECT 841.690000 862.660000 842.690000 863.140000 ;
+ RECT 845.355000 862.660000 846.620000 863.140000 ;
+ RECT 841.690000 857.220000 842.690000 857.700000 ;
+ RECT 845.355000 857.220000 846.620000 857.700000 ;
+ RECT 841.690000 851.780000 842.690000 852.260000 ;
+ RECT 845.355000 851.780000 846.620000 852.260000 ;
+ RECT 1025.520000 835.460000 1026.620000 835.940000 ;
+ RECT 1025.520000 840.900000 1026.620000 841.380000 ;
+ RECT 1038.330000 835.460000 1039.330000 835.940000 ;
+ RECT 1038.330000 840.900000 1039.330000 841.380000 ;
+ RECT 1038.330000 824.580000 1039.330000 825.060000 ;
+ RECT 1038.330000 830.020000 1039.330000 830.500000 ;
+ RECT 1025.520000 830.020000 1026.620000 830.500000 ;
+ RECT 1025.520000 824.580000 1026.620000 825.060000 ;
+ RECT 1025.520000 813.700000 1026.620000 814.180000 ;
+ RECT 1025.520000 819.140000 1026.620000 819.620000 ;
+ RECT 1038.330000 813.700000 1039.330000 814.180000 ;
+ RECT 1038.330000 819.140000 1039.330000 819.620000 ;
+ RECT 1038.330000 802.820000 1039.330000 803.300000 ;
+ RECT 1038.330000 797.380000 1039.330000 797.860000 ;
+ RECT 1038.330000 808.260000 1039.330000 808.740000 ;
+ RECT 1025.520000 808.260000 1026.620000 808.740000 ;
+ RECT 1025.520000 802.820000 1026.620000 803.300000 ;
+ RECT 1025.520000 797.380000 1026.620000 797.860000 ;
+ RECT 980.520000 824.580000 981.620000 825.060000 ;
+ RECT 980.520000 830.020000 981.620000 830.500000 ;
+ RECT 980.520000 835.460000 981.620000 835.940000 ;
+ RECT 980.520000 840.900000 981.620000 841.380000 ;
+ RECT 980.520000 797.380000 981.620000 797.860000 ;
+ RECT 980.520000 802.820000 981.620000 803.300000 ;
+ RECT 980.520000 808.260000 981.620000 808.740000 ;
+ RECT 980.520000 813.700000 981.620000 814.180000 ;
+ RECT 980.520000 819.140000 981.620000 819.620000 ;
+ RECT 1025.520000 786.500000 1026.620000 786.980000 ;
+ RECT 1025.520000 791.940000 1026.620000 792.420000 ;
+ RECT 1038.330000 786.500000 1039.330000 786.980000 ;
+ RECT 1038.330000 791.940000 1039.330000 792.420000 ;
+ RECT 1025.520000 775.620000 1026.620000 776.100000 ;
+ RECT 1025.520000 781.060000 1026.620000 781.540000 ;
+ RECT 1038.330000 775.620000 1039.330000 776.100000 ;
+ RECT 1038.330000 781.060000 1039.330000 781.540000 ;
+ RECT 1038.330000 764.740000 1039.330000 765.220000 ;
+ RECT 1038.330000 759.300000 1039.330000 759.780000 ;
+ RECT 1038.330000 770.180000 1039.330000 770.660000 ;
+ RECT 1025.520000 770.180000 1026.620000 770.660000 ;
+ RECT 1025.520000 764.740000 1026.620000 765.220000 ;
+ RECT 1025.520000 759.300000 1026.620000 759.780000 ;
+ RECT 1025.520000 753.860000 1026.620000 754.340000 ;
+ RECT 1038.330000 753.860000 1039.330000 754.340000 ;
+ RECT 980.520000 775.620000 981.620000 776.100000 ;
+ RECT 980.520000 781.060000 981.620000 781.540000 ;
+ RECT 980.520000 786.500000 981.620000 786.980000 ;
+ RECT 980.520000 791.940000 981.620000 792.420000 ;
+ RECT 980.520000 753.860000 981.620000 754.340000 ;
+ RECT 980.520000 759.300000 981.620000 759.780000 ;
+ RECT 980.520000 764.740000 981.620000 765.220000 ;
+ RECT 980.520000 770.180000 981.620000 770.660000 ;
+ RECT 935.520000 824.580000 936.620000 825.060000 ;
+ RECT 935.520000 830.020000 936.620000 830.500000 ;
+ RECT 935.520000 835.460000 936.620000 835.940000 ;
+ RECT 935.520000 840.900000 936.620000 841.380000 ;
+ RECT 890.520000 824.580000 891.620000 825.060000 ;
+ RECT 890.520000 830.020000 891.620000 830.500000 ;
+ RECT 890.520000 835.460000 891.620000 835.940000 ;
+ RECT 890.520000 840.900000 891.620000 841.380000 ;
+ RECT 935.520000 797.380000 936.620000 797.860000 ;
+ RECT 935.520000 802.820000 936.620000 803.300000 ;
+ RECT 935.520000 808.260000 936.620000 808.740000 ;
+ RECT 935.520000 813.700000 936.620000 814.180000 ;
+ RECT 935.520000 819.140000 936.620000 819.620000 ;
+ RECT 890.520000 797.380000 891.620000 797.860000 ;
+ RECT 890.520000 802.820000 891.620000 803.300000 ;
+ RECT 890.520000 808.260000 891.620000 808.740000 ;
+ RECT 890.520000 813.700000 891.620000 814.180000 ;
+ RECT 890.520000 819.140000 891.620000 819.620000 ;
+ RECT 841.690000 840.900000 842.690000 841.380000 ;
+ RECT 845.355000 840.900000 846.620000 841.380000 ;
+ RECT 841.690000 835.460000 842.690000 835.940000 ;
+ RECT 845.355000 835.460000 846.620000 835.940000 ;
+ RECT 841.690000 830.020000 842.690000 830.500000 ;
+ RECT 845.355000 830.020000 846.620000 830.500000 ;
+ RECT 841.690000 824.580000 842.690000 825.060000 ;
+ RECT 845.355000 824.580000 846.620000 825.060000 ;
+ RECT 841.690000 819.140000 842.690000 819.620000 ;
+ RECT 845.355000 819.140000 846.620000 819.620000 ;
+ RECT 841.690000 813.700000 842.690000 814.180000 ;
+ RECT 845.355000 813.700000 846.620000 814.180000 ;
+ RECT 841.690000 802.820000 842.690000 803.300000 ;
+ RECT 845.355000 802.820000 846.620000 803.300000 ;
+ RECT 841.690000 808.260000 842.690000 808.740000 ;
+ RECT 845.355000 808.260000 846.620000 808.740000 ;
+ RECT 841.690000 797.380000 842.690000 797.860000 ;
+ RECT 845.355000 797.380000 846.620000 797.860000 ;
+ RECT 935.520000 775.620000 936.620000 776.100000 ;
+ RECT 935.520000 781.060000 936.620000 781.540000 ;
+ RECT 935.520000 786.500000 936.620000 786.980000 ;
+ RECT 935.520000 791.940000 936.620000 792.420000 ;
+ RECT 890.520000 775.620000 891.620000 776.100000 ;
+ RECT 890.520000 781.060000 891.620000 781.540000 ;
+ RECT 890.520000 786.500000 891.620000 786.980000 ;
+ RECT 890.520000 791.940000 891.620000 792.420000 ;
+ RECT 935.520000 753.860000 936.620000 754.340000 ;
+ RECT 935.520000 759.300000 936.620000 759.780000 ;
+ RECT 935.520000 764.740000 936.620000 765.220000 ;
+ RECT 935.520000 770.180000 936.620000 770.660000 ;
+ RECT 890.520000 753.860000 891.620000 754.340000 ;
+ RECT 890.520000 759.300000 891.620000 759.780000 ;
+ RECT 890.520000 764.740000 891.620000 765.220000 ;
+ RECT 890.520000 770.180000 891.620000 770.660000 ;
+ RECT 841.690000 791.940000 842.690000 792.420000 ;
+ RECT 845.355000 791.940000 846.620000 792.420000 ;
+ RECT 841.690000 786.500000 842.690000 786.980000 ;
+ RECT 845.355000 786.500000 846.620000 786.980000 ;
+ RECT 841.690000 781.060000 842.690000 781.540000 ;
+ RECT 845.355000 781.060000 846.620000 781.540000 ;
+ RECT 841.690000 775.620000 842.690000 776.100000 ;
+ RECT 845.355000 775.620000 846.620000 776.100000 ;
+ RECT 841.690000 770.180000 842.690000 770.660000 ;
+ RECT 845.355000 770.180000 846.620000 770.660000 ;
+ RECT 841.690000 759.300000 842.690000 759.780000 ;
+ RECT 845.355000 759.300000 846.620000 759.780000 ;
+ RECT 841.690000 764.740000 842.690000 765.220000 ;
+ RECT 845.355000 764.740000 846.620000 765.220000 ;
+ RECT 841.690000 753.860000 842.690000 754.340000 ;
+ RECT 845.355000 753.860000 846.620000 754.340000 ;
+ RECT 980.520000 846.340000 981.620000 846.820000 ;
+ RECT 1025.520000 846.340000 1026.620000 846.820000 ;
+ RECT 1038.330000 846.340000 1039.330000 846.820000 ;
+ RECT 890.520000 846.340000 891.620000 846.820000 ;
+ RECT 935.520000 846.340000 936.620000 846.820000 ;
+ RECT 841.690000 846.340000 842.690000 846.820000 ;
+ RECT 845.355000 846.340000 846.620000 846.820000 ;
+ RECT 840.460000 943.100000 1040.560000 944.100000 ;
+ RECT 840.460000 747.530000 1040.560000 748.530000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 746.280000 842.690000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 945.540000 842.690000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 746.280000 1039.330000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 945.540000 1039.330000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 747.530000 841.460000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 747.530000 1040.560000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 943.100000 841.460000 944.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 943.100000 1040.560000 944.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 738.560000 846.620000 739.040000 ;
+ RECT 845.355000 727.680000 846.620000 728.160000 ;
+ RECT 845.355000 733.120000 846.620000 733.600000 ;
+ RECT 845.355000 722.240000 846.620000 722.720000 ;
+ RECT 845.355000 716.800000 846.620000 717.280000 ;
+ RECT 845.355000 711.360000 846.620000 711.840000 ;
+ RECT 845.355000 705.920000 846.620000 706.400000 ;
+ RECT 845.355000 700.480000 846.620000 700.960000 ;
+ RECT 845.355000 695.040000 846.620000 695.520000 ;
+ RECT 845.355000 684.160000 846.620000 684.640000 ;
+ RECT 845.355000 689.600000 846.620000 690.080000 ;
+ RECT 845.355000 678.720000 846.620000 679.200000 ;
+ RECT 845.355000 673.280000 846.620000 673.760000 ;
+ RECT 845.355000 667.840000 846.620000 668.320000 ;
+ RECT 845.355000 662.400000 846.620000 662.880000 ;
+ RECT 845.355000 656.960000 846.620000 657.440000 ;
+ RECT 845.355000 651.520000 846.620000 652.000000 ;
+ RECT 845.355000 640.640000 846.620000 641.120000 ;
+ RECT 845.355000 635.200000 846.620000 635.680000 ;
+ RECT 845.355000 629.760000 846.620000 630.240000 ;
+ RECT 845.355000 624.320000 846.620000 624.800000 ;
+ RECT 845.355000 618.880000 846.620000 619.360000 ;
+ RECT 845.355000 613.440000 846.620000 613.920000 ;
+ RECT 845.355000 602.560000 846.620000 603.040000 ;
+ RECT 845.355000 608.000000 846.620000 608.480000 ;
+ RECT 845.355000 597.120000 846.620000 597.600000 ;
+ RECT 845.355000 591.680000 846.620000 592.160000 ;
+ RECT 845.355000 586.240000 846.620000 586.720000 ;
+ RECT 845.355000 580.800000 846.620000 581.280000 ;
+ RECT 845.355000 575.360000 846.620000 575.840000 ;
+ RECT 845.355000 569.920000 846.620000 570.400000 ;
+ RECT 845.355000 559.040000 846.620000 559.520000 ;
+ RECT 845.355000 564.480000 846.620000 564.960000 ;
+ RECT 845.355000 553.600000 846.620000 554.080000 ;
+ RECT 845.355000 646.080000 846.620000 646.560000 ;
+ RECT 1025.520000 547.270000 1026.620000 743.840000 ;
+ RECT 980.520000 547.270000 981.620000 743.840000 ;
+ RECT 1038.330000 546.020000 1039.330000 746.280000 ;
+ RECT 935.520000 547.270000 936.620000 743.840000 ;
+ RECT 890.520000 547.270000 891.620000 743.840000 ;
+ RECT 845.520000 547.270000 846.620000 743.840000 ;
+ RECT 841.690000 546.020000 842.690000 746.280000 ;
+ LAYER met3 ;
+ RECT 1025.520000 738.560000 1026.620000 739.040000 ;
+ RECT 1038.330000 738.560000 1039.330000 739.040000 ;
+ RECT 1038.330000 727.680000 1039.330000 728.160000 ;
+ RECT 1038.330000 722.240000 1039.330000 722.720000 ;
+ RECT 1038.330000 733.120000 1039.330000 733.600000 ;
+ RECT 1025.520000 733.120000 1026.620000 733.600000 ;
+ RECT 1025.520000 727.680000 1026.620000 728.160000 ;
+ RECT 1025.520000 722.240000 1026.620000 722.720000 ;
+ RECT 1025.520000 711.360000 1026.620000 711.840000 ;
+ RECT 1025.520000 716.800000 1026.620000 717.280000 ;
+ RECT 1038.330000 711.360000 1039.330000 711.840000 ;
+ RECT 1038.330000 716.800000 1039.330000 717.280000 ;
+ RECT 1025.520000 700.480000 1026.620000 700.960000 ;
+ RECT 1025.520000 705.920000 1026.620000 706.400000 ;
+ RECT 1038.330000 700.480000 1039.330000 700.960000 ;
+ RECT 1038.330000 705.920000 1039.330000 706.400000 ;
+ RECT 980.520000 722.240000 981.620000 722.720000 ;
+ RECT 980.520000 727.680000 981.620000 728.160000 ;
+ RECT 980.520000 733.120000 981.620000 733.600000 ;
+ RECT 980.520000 738.560000 981.620000 739.040000 ;
+ RECT 980.520000 705.920000 981.620000 706.400000 ;
+ RECT 980.520000 700.480000 981.620000 700.960000 ;
+ RECT 980.520000 711.360000 981.620000 711.840000 ;
+ RECT 980.520000 716.800000 981.620000 717.280000 ;
+ RECT 1038.330000 689.600000 1039.330000 690.080000 ;
+ RECT 1038.330000 684.160000 1039.330000 684.640000 ;
+ RECT 1038.330000 695.040000 1039.330000 695.520000 ;
+ RECT 1025.520000 695.040000 1026.620000 695.520000 ;
+ RECT 1025.520000 689.600000 1026.620000 690.080000 ;
+ RECT 1025.520000 684.160000 1026.620000 684.640000 ;
+ RECT 1025.520000 673.280000 1026.620000 673.760000 ;
+ RECT 1025.520000 678.720000 1026.620000 679.200000 ;
+ RECT 1038.330000 673.280000 1039.330000 673.760000 ;
+ RECT 1038.330000 678.720000 1039.330000 679.200000 ;
+ RECT 1038.330000 662.400000 1039.330000 662.880000 ;
+ RECT 1038.330000 667.840000 1039.330000 668.320000 ;
+ RECT 1025.520000 667.840000 1026.620000 668.320000 ;
+ RECT 1025.520000 662.400000 1026.620000 662.880000 ;
+ RECT 1025.520000 651.520000 1026.620000 652.000000 ;
+ RECT 1025.520000 656.960000 1026.620000 657.440000 ;
+ RECT 1038.330000 651.520000 1039.330000 652.000000 ;
+ RECT 1038.330000 656.960000 1039.330000 657.440000 ;
+ RECT 980.520000 673.280000 981.620000 673.760000 ;
+ RECT 980.520000 678.720000 981.620000 679.200000 ;
+ RECT 980.520000 684.160000 981.620000 684.640000 ;
+ RECT 980.520000 689.600000 981.620000 690.080000 ;
+ RECT 980.520000 695.040000 981.620000 695.520000 ;
+ RECT 980.520000 651.520000 981.620000 652.000000 ;
+ RECT 980.520000 656.960000 981.620000 657.440000 ;
+ RECT 980.520000 662.400000 981.620000 662.880000 ;
+ RECT 980.520000 667.840000 981.620000 668.320000 ;
+ RECT 935.520000 727.680000 936.620000 728.160000 ;
+ RECT 935.520000 722.240000 936.620000 722.720000 ;
+ RECT 935.520000 733.120000 936.620000 733.600000 ;
+ RECT 935.520000 738.560000 936.620000 739.040000 ;
+ RECT 890.520000 722.240000 891.620000 722.720000 ;
+ RECT 890.520000 727.680000 891.620000 728.160000 ;
+ RECT 890.520000 733.120000 891.620000 733.600000 ;
+ RECT 890.520000 738.560000 891.620000 739.040000 ;
+ RECT 935.520000 700.480000 936.620000 700.960000 ;
+ RECT 935.520000 705.920000 936.620000 706.400000 ;
+ RECT 935.520000 711.360000 936.620000 711.840000 ;
+ RECT 935.520000 716.800000 936.620000 717.280000 ;
+ RECT 890.520000 700.480000 891.620000 700.960000 ;
+ RECT 890.520000 705.920000 891.620000 706.400000 ;
+ RECT 890.520000 711.360000 891.620000 711.840000 ;
+ RECT 890.520000 716.800000 891.620000 717.280000 ;
+ RECT 841.690000 738.560000 842.690000 739.040000 ;
+ RECT 845.355000 738.560000 846.620000 739.040000 ;
+ RECT 841.690000 727.680000 842.690000 728.160000 ;
+ RECT 845.355000 727.680000 846.620000 728.160000 ;
+ RECT 841.690000 733.120000 842.690000 733.600000 ;
+ RECT 845.355000 733.120000 846.620000 733.600000 ;
+ RECT 841.690000 722.240000 842.690000 722.720000 ;
+ RECT 845.355000 722.240000 846.620000 722.720000 ;
+ RECT 841.690000 716.800000 842.690000 717.280000 ;
+ RECT 845.355000 716.800000 846.620000 717.280000 ;
+ RECT 841.690000 711.360000 842.690000 711.840000 ;
+ RECT 845.355000 711.360000 846.620000 711.840000 ;
+ RECT 841.690000 705.920000 842.690000 706.400000 ;
+ RECT 845.355000 705.920000 846.620000 706.400000 ;
+ RECT 841.690000 700.480000 842.690000 700.960000 ;
+ RECT 845.355000 700.480000 846.620000 700.960000 ;
+ RECT 935.520000 673.280000 936.620000 673.760000 ;
+ RECT 935.520000 678.720000 936.620000 679.200000 ;
+ RECT 935.520000 684.160000 936.620000 684.640000 ;
+ RECT 935.520000 689.600000 936.620000 690.080000 ;
+ RECT 935.520000 695.040000 936.620000 695.520000 ;
+ RECT 890.520000 673.280000 891.620000 673.760000 ;
+ RECT 890.520000 678.720000 891.620000 679.200000 ;
+ RECT 890.520000 684.160000 891.620000 684.640000 ;
+ RECT 890.520000 689.600000 891.620000 690.080000 ;
+ RECT 890.520000 695.040000 891.620000 695.520000 ;
+ RECT 935.520000 651.520000 936.620000 652.000000 ;
+ RECT 935.520000 656.960000 936.620000 657.440000 ;
+ RECT 935.520000 662.400000 936.620000 662.880000 ;
+ RECT 935.520000 667.840000 936.620000 668.320000 ;
+ RECT 890.520000 651.520000 891.620000 652.000000 ;
+ RECT 890.520000 656.960000 891.620000 657.440000 ;
+ RECT 890.520000 662.400000 891.620000 662.880000 ;
+ RECT 890.520000 667.840000 891.620000 668.320000 ;
+ RECT 841.690000 695.040000 842.690000 695.520000 ;
+ RECT 845.355000 695.040000 846.620000 695.520000 ;
+ RECT 841.690000 684.160000 842.690000 684.640000 ;
+ RECT 845.355000 684.160000 846.620000 684.640000 ;
+ RECT 841.690000 689.600000 842.690000 690.080000 ;
+ RECT 845.355000 689.600000 846.620000 690.080000 ;
+ RECT 841.690000 678.720000 842.690000 679.200000 ;
+ RECT 845.355000 678.720000 846.620000 679.200000 ;
+ RECT 841.690000 673.280000 842.690000 673.760000 ;
+ RECT 845.355000 673.280000 846.620000 673.760000 ;
+ RECT 841.690000 667.840000 842.690000 668.320000 ;
+ RECT 845.355000 667.840000 846.620000 668.320000 ;
+ RECT 841.690000 662.400000 842.690000 662.880000 ;
+ RECT 845.355000 662.400000 846.620000 662.880000 ;
+ RECT 841.690000 656.960000 842.690000 657.440000 ;
+ RECT 845.355000 656.960000 846.620000 657.440000 ;
+ RECT 841.690000 651.520000 842.690000 652.000000 ;
+ RECT 845.355000 651.520000 846.620000 652.000000 ;
+ RECT 1025.520000 635.200000 1026.620000 635.680000 ;
+ RECT 1025.520000 640.640000 1026.620000 641.120000 ;
+ RECT 1038.330000 635.200000 1039.330000 635.680000 ;
+ RECT 1038.330000 640.640000 1039.330000 641.120000 ;
+ RECT 1038.330000 624.320000 1039.330000 624.800000 ;
+ RECT 1038.330000 629.760000 1039.330000 630.240000 ;
+ RECT 1025.520000 629.760000 1026.620000 630.240000 ;
+ RECT 1025.520000 624.320000 1026.620000 624.800000 ;
+ RECT 1025.520000 613.440000 1026.620000 613.920000 ;
+ RECT 1025.520000 618.880000 1026.620000 619.360000 ;
+ RECT 1038.330000 613.440000 1039.330000 613.920000 ;
+ RECT 1038.330000 618.880000 1039.330000 619.360000 ;
+ RECT 1038.330000 602.560000 1039.330000 603.040000 ;
+ RECT 1038.330000 597.120000 1039.330000 597.600000 ;
+ RECT 1038.330000 608.000000 1039.330000 608.480000 ;
+ RECT 1025.520000 608.000000 1026.620000 608.480000 ;
+ RECT 1025.520000 602.560000 1026.620000 603.040000 ;
+ RECT 1025.520000 597.120000 1026.620000 597.600000 ;
+ RECT 980.520000 624.320000 981.620000 624.800000 ;
+ RECT 980.520000 629.760000 981.620000 630.240000 ;
+ RECT 980.520000 635.200000 981.620000 635.680000 ;
+ RECT 980.520000 640.640000 981.620000 641.120000 ;
+ RECT 980.520000 597.120000 981.620000 597.600000 ;
+ RECT 980.520000 602.560000 981.620000 603.040000 ;
+ RECT 980.520000 608.000000 981.620000 608.480000 ;
+ RECT 980.520000 613.440000 981.620000 613.920000 ;
+ RECT 980.520000 618.880000 981.620000 619.360000 ;
+ RECT 1025.520000 586.240000 1026.620000 586.720000 ;
+ RECT 1025.520000 591.680000 1026.620000 592.160000 ;
+ RECT 1038.330000 586.240000 1039.330000 586.720000 ;
+ RECT 1038.330000 591.680000 1039.330000 592.160000 ;
+ RECT 1025.520000 575.360000 1026.620000 575.840000 ;
+ RECT 1025.520000 580.800000 1026.620000 581.280000 ;
+ RECT 1038.330000 575.360000 1039.330000 575.840000 ;
+ RECT 1038.330000 580.800000 1039.330000 581.280000 ;
+ RECT 1038.330000 564.480000 1039.330000 564.960000 ;
+ RECT 1038.330000 559.040000 1039.330000 559.520000 ;
+ RECT 1038.330000 569.920000 1039.330000 570.400000 ;
+ RECT 1025.520000 569.920000 1026.620000 570.400000 ;
+ RECT 1025.520000 564.480000 1026.620000 564.960000 ;
+ RECT 1025.520000 559.040000 1026.620000 559.520000 ;
+ RECT 1025.520000 553.600000 1026.620000 554.080000 ;
+ RECT 1038.330000 553.600000 1039.330000 554.080000 ;
+ RECT 980.520000 575.360000 981.620000 575.840000 ;
+ RECT 980.520000 580.800000 981.620000 581.280000 ;
+ RECT 980.520000 586.240000 981.620000 586.720000 ;
+ RECT 980.520000 591.680000 981.620000 592.160000 ;
+ RECT 980.520000 553.600000 981.620000 554.080000 ;
+ RECT 980.520000 559.040000 981.620000 559.520000 ;
+ RECT 980.520000 564.480000 981.620000 564.960000 ;
+ RECT 980.520000 569.920000 981.620000 570.400000 ;
+ RECT 935.520000 624.320000 936.620000 624.800000 ;
+ RECT 935.520000 629.760000 936.620000 630.240000 ;
+ RECT 935.520000 635.200000 936.620000 635.680000 ;
+ RECT 935.520000 640.640000 936.620000 641.120000 ;
+ RECT 890.520000 624.320000 891.620000 624.800000 ;
+ RECT 890.520000 629.760000 891.620000 630.240000 ;
+ RECT 890.520000 635.200000 891.620000 635.680000 ;
+ RECT 890.520000 640.640000 891.620000 641.120000 ;
+ RECT 935.520000 597.120000 936.620000 597.600000 ;
+ RECT 935.520000 602.560000 936.620000 603.040000 ;
+ RECT 935.520000 608.000000 936.620000 608.480000 ;
+ RECT 935.520000 613.440000 936.620000 613.920000 ;
+ RECT 935.520000 618.880000 936.620000 619.360000 ;
+ RECT 890.520000 597.120000 891.620000 597.600000 ;
+ RECT 890.520000 602.560000 891.620000 603.040000 ;
+ RECT 890.520000 608.000000 891.620000 608.480000 ;
+ RECT 890.520000 613.440000 891.620000 613.920000 ;
+ RECT 890.520000 618.880000 891.620000 619.360000 ;
+ RECT 841.690000 640.640000 842.690000 641.120000 ;
+ RECT 845.355000 640.640000 846.620000 641.120000 ;
+ RECT 841.690000 635.200000 842.690000 635.680000 ;
+ RECT 845.355000 635.200000 846.620000 635.680000 ;
+ RECT 841.690000 629.760000 842.690000 630.240000 ;
+ RECT 845.355000 629.760000 846.620000 630.240000 ;
+ RECT 841.690000 624.320000 842.690000 624.800000 ;
+ RECT 845.355000 624.320000 846.620000 624.800000 ;
+ RECT 841.690000 618.880000 842.690000 619.360000 ;
+ RECT 845.355000 618.880000 846.620000 619.360000 ;
+ RECT 841.690000 613.440000 842.690000 613.920000 ;
+ RECT 845.355000 613.440000 846.620000 613.920000 ;
+ RECT 841.690000 602.560000 842.690000 603.040000 ;
+ RECT 845.355000 602.560000 846.620000 603.040000 ;
+ RECT 841.690000 608.000000 842.690000 608.480000 ;
+ RECT 845.355000 608.000000 846.620000 608.480000 ;
+ RECT 841.690000 597.120000 842.690000 597.600000 ;
+ RECT 845.355000 597.120000 846.620000 597.600000 ;
+ RECT 935.520000 575.360000 936.620000 575.840000 ;
+ RECT 935.520000 580.800000 936.620000 581.280000 ;
+ RECT 935.520000 586.240000 936.620000 586.720000 ;
+ RECT 935.520000 591.680000 936.620000 592.160000 ;
+ RECT 890.520000 575.360000 891.620000 575.840000 ;
+ RECT 890.520000 580.800000 891.620000 581.280000 ;
+ RECT 890.520000 586.240000 891.620000 586.720000 ;
+ RECT 890.520000 591.680000 891.620000 592.160000 ;
+ RECT 935.520000 553.600000 936.620000 554.080000 ;
+ RECT 935.520000 559.040000 936.620000 559.520000 ;
+ RECT 935.520000 564.480000 936.620000 564.960000 ;
+ RECT 935.520000 569.920000 936.620000 570.400000 ;
+ RECT 890.520000 553.600000 891.620000 554.080000 ;
+ RECT 890.520000 559.040000 891.620000 559.520000 ;
+ RECT 890.520000 564.480000 891.620000 564.960000 ;
+ RECT 890.520000 569.920000 891.620000 570.400000 ;
+ RECT 841.690000 591.680000 842.690000 592.160000 ;
+ RECT 845.355000 591.680000 846.620000 592.160000 ;
+ RECT 841.690000 586.240000 842.690000 586.720000 ;
+ RECT 845.355000 586.240000 846.620000 586.720000 ;
+ RECT 841.690000 580.800000 842.690000 581.280000 ;
+ RECT 845.355000 580.800000 846.620000 581.280000 ;
+ RECT 841.690000 575.360000 842.690000 575.840000 ;
+ RECT 845.355000 575.360000 846.620000 575.840000 ;
+ RECT 841.690000 569.920000 842.690000 570.400000 ;
+ RECT 845.355000 569.920000 846.620000 570.400000 ;
+ RECT 841.690000 559.040000 842.690000 559.520000 ;
+ RECT 845.355000 559.040000 846.620000 559.520000 ;
+ RECT 841.690000 564.480000 842.690000 564.960000 ;
+ RECT 845.355000 564.480000 846.620000 564.960000 ;
+ RECT 841.690000 553.600000 842.690000 554.080000 ;
+ RECT 845.355000 553.600000 846.620000 554.080000 ;
+ RECT 980.520000 646.080000 981.620000 646.560000 ;
+ RECT 1025.520000 646.080000 1026.620000 646.560000 ;
+ RECT 1038.330000 646.080000 1039.330000 646.560000 ;
+ RECT 890.520000 646.080000 891.620000 646.560000 ;
+ RECT 935.520000 646.080000 936.620000 646.560000 ;
+ RECT 841.690000 646.080000 842.690000 646.560000 ;
+ RECT 845.355000 646.080000 846.620000 646.560000 ;
+ RECT 840.460000 742.840000 1040.560000 743.840000 ;
+ RECT 840.460000 547.270000 1040.560000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 546.020000 842.690000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 745.280000 842.690000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 546.020000 1039.330000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 745.280000 1039.330000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 547.270000 841.460000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 547.270000 1040.560000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 742.840000 841.460000 743.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 742.840000 1040.560000 743.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 538.300000 846.620000 538.780000 ;
+ RECT 845.355000 527.420000 846.620000 527.900000 ;
+ RECT 845.355000 532.860000 846.620000 533.340000 ;
+ RECT 845.355000 521.980000 846.620000 522.460000 ;
+ RECT 845.355000 516.540000 846.620000 517.020000 ;
+ RECT 845.355000 511.100000 846.620000 511.580000 ;
+ RECT 845.355000 505.660000 846.620000 506.140000 ;
+ RECT 845.355000 500.220000 846.620000 500.700000 ;
+ RECT 845.355000 494.780000 846.620000 495.260000 ;
+ RECT 845.355000 483.900000 846.620000 484.380000 ;
+ RECT 845.355000 489.340000 846.620000 489.820000 ;
+ RECT 845.355000 478.460000 846.620000 478.940000 ;
+ RECT 845.355000 473.020000 846.620000 473.500000 ;
+ RECT 845.355000 467.580000 846.620000 468.060000 ;
+ RECT 845.355000 462.140000 846.620000 462.620000 ;
+ RECT 845.355000 456.700000 846.620000 457.180000 ;
+ RECT 845.355000 451.260000 846.620000 451.740000 ;
+ RECT 845.355000 440.380000 846.620000 440.860000 ;
+ RECT 845.355000 434.940000 846.620000 435.420000 ;
+ RECT 845.355000 429.500000 846.620000 429.980000 ;
+ RECT 845.355000 424.060000 846.620000 424.540000 ;
+ RECT 845.355000 418.620000 846.620000 419.100000 ;
+ RECT 845.355000 413.180000 846.620000 413.660000 ;
+ RECT 845.355000 402.300000 846.620000 402.780000 ;
+ RECT 845.355000 407.740000 846.620000 408.220000 ;
+ RECT 845.355000 396.860000 846.620000 397.340000 ;
+ RECT 845.355000 391.420000 846.620000 391.900000 ;
+ RECT 845.355000 385.980000 846.620000 386.460000 ;
+ RECT 845.355000 380.540000 846.620000 381.020000 ;
+ RECT 845.355000 375.100000 846.620000 375.580000 ;
+ RECT 845.355000 369.660000 846.620000 370.140000 ;
+ RECT 845.355000 358.780000 846.620000 359.260000 ;
+ RECT 845.355000 364.220000 846.620000 364.700000 ;
+ RECT 845.355000 353.340000 846.620000 353.820000 ;
+ RECT 845.355000 445.820000 846.620000 446.300000 ;
+ RECT 1025.520000 347.010000 1026.620000 543.580000 ;
+ RECT 980.520000 347.010000 981.620000 543.580000 ;
+ RECT 1038.330000 345.760000 1039.330000 546.020000 ;
+ RECT 935.520000 347.010000 936.620000 543.580000 ;
+ RECT 890.520000 347.010000 891.620000 543.580000 ;
+ RECT 845.520000 347.010000 846.620000 543.580000 ;
+ RECT 841.690000 345.760000 842.690000 546.020000 ;
+ LAYER met3 ;
+ RECT 1025.520000 538.300000 1026.620000 538.780000 ;
+ RECT 1038.330000 538.300000 1039.330000 538.780000 ;
+ RECT 1038.330000 527.420000 1039.330000 527.900000 ;
+ RECT 1038.330000 521.980000 1039.330000 522.460000 ;
+ RECT 1038.330000 532.860000 1039.330000 533.340000 ;
+ RECT 1025.520000 532.860000 1026.620000 533.340000 ;
+ RECT 1025.520000 527.420000 1026.620000 527.900000 ;
+ RECT 1025.520000 521.980000 1026.620000 522.460000 ;
+ RECT 1025.520000 511.100000 1026.620000 511.580000 ;
+ RECT 1025.520000 516.540000 1026.620000 517.020000 ;
+ RECT 1038.330000 511.100000 1039.330000 511.580000 ;
+ RECT 1038.330000 516.540000 1039.330000 517.020000 ;
+ RECT 1025.520000 500.220000 1026.620000 500.700000 ;
+ RECT 1025.520000 505.660000 1026.620000 506.140000 ;
+ RECT 1038.330000 500.220000 1039.330000 500.700000 ;
+ RECT 1038.330000 505.660000 1039.330000 506.140000 ;
+ RECT 980.520000 521.980000 981.620000 522.460000 ;
+ RECT 980.520000 527.420000 981.620000 527.900000 ;
+ RECT 980.520000 532.860000 981.620000 533.340000 ;
+ RECT 980.520000 538.300000 981.620000 538.780000 ;
+ RECT 980.520000 505.660000 981.620000 506.140000 ;
+ RECT 980.520000 500.220000 981.620000 500.700000 ;
+ RECT 980.520000 511.100000 981.620000 511.580000 ;
+ RECT 980.520000 516.540000 981.620000 517.020000 ;
+ RECT 1038.330000 489.340000 1039.330000 489.820000 ;
+ RECT 1038.330000 483.900000 1039.330000 484.380000 ;
+ RECT 1038.330000 494.780000 1039.330000 495.260000 ;
+ RECT 1025.520000 494.780000 1026.620000 495.260000 ;
+ RECT 1025.520000 489.340000 1026.620000 489.820000 ;
+ RECT 1025.520000 483.900000 1026.620000 484.380000 ;
+ RECT 1025.520000 473.020000 1026.620000 473.500000 ;
+ RECT 1025.520000 478.460000 1026.620000 478.940000 ;
+ RECT 1038.330000 473.020000 1039.330000 473.500000 ;
+ RECT 1038.330000 478.460000 1039.330000 478.940000 ;
+ RECT 1038.330000 462.140000 1039.330000 462.620000 ;
+ RECT 1038.330000 467.580000 1039.330000 468.060000 ;
+ RECT 1025.520000 467.580000 1026.620000 468.060000 ;
+ RECT 1025.520000 462.140000 1026.620000 462.620000 ;
+ RECT 1025.520000 451.260000 1026.620000 451.740000 ;
+ RECT 1025.520000 456.700000 1026.620000 457.180000 ;
+ RECT 1038.330000 451.260000 1039.330000 451.740000 ;
+ RECT 1038.330000 456.700000 1039.330000 457.180000 ;
+ RECT 980.520000 473.020000 981.620000 473.500000 ;
+ RECT 980.520000 478.460000 981.620000 478.940000 ;
+ RECT 980.520000 483.900000 981.620000 484.380000 ;
+ RECT 980.520000 489.340000 981.620000 489.820000 ;
+ RECT 980.520000 494.780000 981.620000 495.260000 ;
+ RECT 980.520000 451.260000 981.620000 451.740000 ;
+ RECT 980.520000 456.700000 981.620000 457.180000 ;
+ RECT 980.520000 462.140000 981.620000 462.620000 ;
+ RECT 980.520000 467.580000 981.620000 468.060000 ;
+ RECT 935.520000 527.420000 936.620000 527.900000 ;
+ RECT 935.520000 521.980000 936.620000 522.460000 ;
+ RECT 935.520000 532.860000 936.620000 533.340000 ;
+ RECT 935.520000 538.300000 936.620000 538.780000 ;
+ RECT 890.520000 521.980000 891.620000 522.460000 ;
+ RECT 890.520000 527.420000 891.620000 527.900000 ;
+ RECT 890.520000 532.860000 891.620000 533.340000 ;
+ RECT 890.520000 538.300000 891.620000 538.780000 ;
+ RECT 935.520000 500.220000 936.620000 500.700000 ;
+ RECT 935.520000 505.660000 936.620000 506.140000 ;
+ RECT 935.520000 511.100000 936.620000 511.580000 ;
+ RECT 935.520000 516.540000 936.620000 517.020000 ;
+ RECT 890.520000 500.220000 891.620000 500.700000 ;
+ RECT 890.520000 505.660000 891.620000 506.140000 ;
+ RECT 890.520000 511.100000 891.620000 511.580000 ;
+ RECT 890.520000 516.540000 891.620000 517.020000 ;
+ RECT 841.690000 538.300000 842.690000 538.780000 ;
+ RECT 845.355000 538.300000 846.620000 538.780000 ;
+ RECT 841.690000 527.420000 842.690000 527.900000 ;
+ RECT 845.355000 527.420000 846.620000 527.900000 ;
+ RECT 841.690000 532.860000 842.690000 533.340000 ;
+ RECT 845.355000 532.860000 846.620000 533.340000 ;
+ RECT 841.690000 521.980000 842.690000 522.460000 ;
+ RECT 845.355000 521.980000 846.620000 522.460000 ;
+ RECT 841.690000 516.540000 842.690000 517.020000 ;
+ RECT 845.355000 516.540000 846.620000 517.020000 ;
+ RECT 841.690000 511.100000 842.690000 511.580000 ;
+ RECT 845.355000 511.100000 846.620000 511.580000 ;
+ RECT 841.690000 505.660000 842.690000 506.140000 ;
+ RECT 845.355000 505.660000 846.620000 506.140000 ;
+ RECT 841.690000 500.220000 842.690000 500.700000 ;
+ RECT 845.355000 500.220000 846.620000 500.700000 ;
+ RECT 935.520000 473.020000 936.620000 473.500000 ;
+ RECT 935.520000 478.460000 936.620000 478.940000 ;
+ RECT 935.520000 483.900000 936.620000 484.380000 ;
+ RECT 935.520000 489.340000 936.620000 489.820000 ;
+ RECT 935.520000 494.780000 936.620000 495.260000 ;
+ RECT 890.520000 473.020000 891.620000 473.500000 ;
+ RECT 890.520000 478.460000 891.620000 478.940000 ;
+ RECT 890.520000 483.900000 891.620000 484.380000 ;
+ RECT 890.520000 489.340000 891.620000 489.820000 ;
+ RECT 890.520000 494.780000 891.620000 495.260000 ;
+ RECT 935.520000 451.260000 936.620000 451.740000 ;
+ RECT 935.520000 456.700000 936.620000 457.180000 ;
+ RECT 935.520000 462.140000 936.620000 462.620000 ;
+ RECT 935.520000 467.580000 936.620000 468.060000 ;
+ RECT 890.520000 451.260000 891.620000 451.740000 ;
+ RECT 890.520000 456.700000 891.620000 457.180000 ;
+ RECT 890.520000 462.140000 891.620000 462.620000 ;
+ RECT 890.520000 467.580000 891.620000 468.060000 ;
+ RECT 841.690000 494.780000 842.690000 495.260000 ;
+ RECT 845.355000 494.780000 846.620000 495.260000 ;
+ RECT 841.690000 483.900000 842.690000 484.380000 ;
+ RECT 845.355000 483.900000 846.620000 484.380000 ;
+ RECT 841.690000 489.340000 842.690000 489.820000 ;
+ RECT 845.355000 489.340000 846.620000 489.820000 ;
+ RECT 841.690000 478.460000 842.690000 478.940000 ;
+ RECT 845.355000 478.460000 846.620000 478.940000 ;
+ RECT 841.690000 473.020000 842.690000 473.500000 ;
+ RECT 845.355000 473.020000 846.620000 473.500000 ;
+ RECT 841.690000 467.580000 842.690000 468.060000 ;
+ RECT 845.355000 467.580000 846.620000 468.060000 ;
+ RECT 841.690000 462.140000 842.690000 462.620000 ;
+ RECT 845.355000 462.140000 846.620000 462.620000 ;
+ RECT 841.690000 456.700000 842.690000 457.180000 ;
+ RECT 845.355000 456.700000 846.620000 457.180000 ;
+ RECT 841.690000 451.260000 842.690000 451.740000 ;
+ RECT 845.355000 451.260000 846.620000 451.740000 ;
+ RECT 1025.520000 434.940000 1026.620000 435.420000 ;
+ RECT 1025.520000 440.380000 1026.620000 440.860000 ;
+ RECT 1038.330000 434.940000 1039.330000 435.420000 ;
+ RECT 1038.330000 440.380000 1039.330000 440.860000 ;
+ RECT 1038.330000 424.060000 1039.330000 424.540000 ;
+ RECT 1038.330000 429.500000 1039.330000 429.980000 ;
+ RECT 1025.520000 429.500000 1026.620000 429.980000 ;
+ RECT 1025.520000 424.060000 1026.620000 424.540000 ;
+ RECT 1025.520000 413.180000 1026.620000 413.660000 ;
+ RECT 1025.520000 418.620000 1026.620000 419.100000 ;
+ RECT 1038.330000 413.180000 1039.330000 413.660000 ;
+ RECT 1038.330000 418.620000 1039.330000 419.100000 ;
+ RECT 1038.330000 402.300000 1039.330000 402.780000 ;
+ RECT 1038.330000 396.860000 1039.330000 397.340000 ;
+ RECT 1038.330000 407.740000 1039.330000 408.220000 ;
+ RECT 1025.520000 407.740000 1026.620000 408.220000 ;
+ RECT 1025.520000 402.300000 1026.620000 402.780000 ;
+ RECT 1025.520000 396.860000 1026.620000 397.340000 ;
+ RECT 980.520000 424.060000 981.620000 424.540000 ;
+ RECT 980.520000 429.500000 981.620000 429.980000 ;
+ RECT 980.520000 434.940000 981.620000 435.420000 ;
+ RECT 980.520000 440.380000 981.620000 440.860000 ;
+ RECT 980.520000 396.860000 981.620000 397.340000 ;
+ RECT 980.520000 402.300000 981.620000 402.780000 ;
+ RECT 980.520000 407.740000 981.620000 408.220000 ;
+ RECT 980.520000 413.180000 981.620000 413.660000 ;
+ RECT 980.520000 418.620000 981.620000 419.100000 ;
+ RECT 1025.520000 385.980000 1026.620000 386.460000 ;
+ RECT 1025.520000 391.420000 1026.620000 391.900000 ;
+ RECT 1038.330000 385.980000 1039.330000 386.460000 ;
+ RECT 1038.330000 391.420000 1039.330000 391.900000 ;
+ RECT 1025.520000 375.100000 1026.620000 375.580000 ;
+ RECT 1025.520000 380.540000 1026.620000 381.020000 ;
+ RECT 1038.330000 375.100000 1039.330000 375.580000 ;
+ RECT 1038.330000 380.540000 1039.330000 381.020000 ;
+ RECT 1038.330000 364.220000 1039.330000 364.700000 ;
+ RECT 1038.330000 358.780000 1039.330000 359.260000 ;
+ RECT 1038.330000 369.660000 1039.330000 370.140000 ;
+ RECT 1025.520000 369.660000 1026.620000 370.140000 ;
+ RECT 1025.520000 364.220000 1026.620000 364.700000 ;
+ RECT 1025.520000 358.780000 1026.620000 359.260000 ;
+ RECT 1025.520000 353.340000 1026.620000 353.820000 ;
+ RECT 1038.330000 353.340000 1039.330000 353.820000 ;
+ RECT 980.520000 375.100000 981.620000 375.580000 ;
+ RECT 980.520000 380.540000 981.620000 381.020000 ;
+ RECT 980.520000 385.980000 981.620000 386.460000 ;
+ RECT 980.520000 391.420000 981.620000 391.900000 ;
+ RECT 980.520000 353.340000 981.620000 353.820000 ;
+ RECT 980.520000 358.780000 981.620000 359.260000 ;
+ RECT 980.520000 364.220000 981.620000 364.700000 ;
+ RECT 980.520000 369.660000 981.620000 370.140000 ;
+ RECT 935.520000 424.060000 936.620000 424.540000 ;
+ RECT 935.520000 429.500000 936.620000 429.980000 ;
+ RECT 935.520000 434.940000 936.620000 435.420000 ;
+ RECT 935.520000 440.380000 936.620000 440.860000 ;
+ RECT 890.520000 424.060000 891.620000 424.540000 ;
+ RECT 890.520000 429.500000 891.620000 429.980000 ;
+ RECT 890.520000 434.940000 891.620000 435.420000 ;
+ RECT 890.520000 440.380000 891.620000 440.860000 ;
+ RECT 935.520000 396.860000 936.620000 397.340000 ;
+ RECT 935.520000 402.300000 936.620000 402.780000 ;
+ RECT 935.520000 407.740000 936.620000 408.220000 ;
+ RECT 935.520000 413.180000 936.620000 413.660000 ;
+ RECT 935.520000 418.620000 936.620000 419.100000 ;
+ RECT 890.520000 396.860000 891.620000 397.340000 ;
+ RECT 890.520000 402.300000 891.620000 402.780000 ;
+ RECT 890.520000 407.740000 891.620000 408.220000 ;
+ RECT 890.520000 413.180000 891.620000 413.660000 ;
+ RECT 890.520000 418.620000 891.620000 419.100000 ;
+ RECT 841.690000 440.380000 842.690000 440.860000 ;
+ RECT 845.355000 440.380000 846.620000 440.860000 ;
+ RECT 841.690000 434.940000 842.690000 435.420000 ;
+ RECT 845.355000 434.940000 846.620000 435.420000 ;
+ RECT 841.690000 429.500000 842.690000 429.980000 ;
+ RECT 845.355000 429.500000 846.620000 429.980000 ;
+ RECT 841.690000 424.060000 842.690000 424.540000 ;
+ RECT 845.355000 424.060000 846.620000 424.540000 ;
+ RECT 841.690000 418.620000 842.690000 419.100000 ;
+ RECT 845.355000 418.620000 846.620000 419.100000 ;
+ RECT 841.690000 413.180000 842.690000 413.660000 ;
+ RECT 845.355000 413.180000 846.620000 413.660000 ;
+ RECT 841.690000 402.300000 842.690000 402.780000 ;
+ RECT 845.355000 402.300000 846.620000 402.780000 ;
+ RECT 841.690000 407.740000 842.690000 408.220000 ;
+ RECT 845.355000 407.740000 846.620000 408.220000 ;
+ RECT 841.690000 396.860000 842.690000 397.340000 ;
+ RECT 845.355000 396.860000 846.620000 397.340000 ;
+ RECT 935.520000 375.100000 936.620000 375.580000 ;
+ RECT 935.520000 380.540000 936.620000 381.020000 ;
+ RECT 935.520000 385.980000 936.620000 386.460000 ;
+ RECT 935.520000 391.420000 936.620000 391.900000 ;
+ RECT 890.520000 375.100000 891.620000 375.580000 ;
+ RECT 890.520000 380.540000 891.620000 381.020000 ;
+ RECT 890.520000 385.980000 891.620000 386.460000 ;
+ RECT 890.520000 391.420000 891.620000 391.900000 ;
+ RECT 935.520000 353.340000 936.620000 353.820000 ;
+ RECT 935.520000 358.780000 936.620000 359.260000 ;
+ RECT 935.520000 364.220000 936.620000 364.700000 ;
+ RECT 935.520000 369.660000 936.620000 370.140000 ;
+ RECT 890.520000 353.340000 891.620000 353.820000 ;
+ RECT 890.520000 358.780000 891.620000 359.260000 ;
+ RECT 890.520000 364.220000 891.620000 364.700000 ;
+ RECT 890.520000 369.660000 891.620000 370.140000 ;
+ RECT 841.690000 391.420000 842.690000 391.900000 ;
+ RECT 845.355000 391.420000 846.620000 391.900000 ;
+ RECT 841.690000 385.980000 842.690000 386.460000 ;
+ RECT 845.355000 385.980000 846.620000 386.460000 ;
+ RECT 841.690000 380.540000 842.690000 381.020000 ;
+ RECT 845.355000 380.540000 846.620000 381.020000 ;
+ RECT 841.690000 375.100000 842.690000 375.580000 ;
+ RECT 845.355000 375.100000 846.620000 375.580000 ;
+ RECT 841.690000 369.660000 842.690000 370.140000 ;
+ RECT 845.355000 369.660000 846.620000 370.140000 ;
+ RECT 841.690000 358.780000 842.690000 359.260000 ;
+ RECT 845.355000 358.780000 846.620000 359.260000 ;
+ RECT 841.690000 364.220000 842.690000 364.700000 ;
+ RECT 845.355000 364.220000 846.620000 364.700000 ;
+ RECT 841.690000 353.340000 842.690000 353.820000 ;
+ RECT 845.355000 353.340000 846.620000 353.820000 ;
+ RECT 980.520000 445.820000 981.620000 446.300000 ;
+ RECT 1025.520000 445.820000 1026.620000 446.300000 ;
+ RECT 1038.330000 445.820000 1039.330000 446.300000 ;
+ RECT 890.520000 445.820000 891.620000 446.300000 ;
+ RECT 935.520000 445.820000 936.620000 446.300000 ;
+ RECT 841.690000 445.820000 842.690000 446.300000 ;
+ RECT 845.355000 445.820000 846.620000 446.300000 ;
+ RECT 840.460000 542.580000 1040.560000 543.580000 ;
+ RECT 840.460000 347.010000 1040.560000 348.010000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 345.760000 842.690000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 545.020000 842.690000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 345.760000 1039.330000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 545.020000 1039.330000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 347.010000 841.460000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 347.010000 1040.560000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 542.580000 841.460000 543.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 542.580000 1040.560000 543.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 338.040000 846.620000 338.520000 ;
+ RECT 845.355000 327.160000 846.620000 327.640000 ;
+ RECT 845.355000 332.600000 846.620000 333.080000 ;
+ RECT 845.355000 321.720000 846.620000 322.200000 ;
+ RECT 845.355000 316.280000 846.620000 316.760000 ;
+ RECT 845.355000 310.840000 846.620000 311.320000 ;
+ RECT 845.355000 305.400000 846.620000 305.880000 ;
+ RECT 845.355000 299.960000 846.620000 300.440000 ;
+ RECT 845.355000 294.520000 846.620000 295.000000 ;
+ RECT 845.355000 283.640000 846.620000 284.120000 ;
+ RECT 845.355000 289.080000 846.620000 289.560000 ;
+ RECT 845.355000 278.200000 846.620000 278.680000 ;
+ RECT 845.355000 272.760000 846.620000 273.240000 ;
+ RECT 845.355000 267.320000 846.620000 267.800000 ;
+ RECT 845.355000 261.880000 846.620000 262.360000 ;
+ RECT 845.355000 256.440000 846.620000 256.920000 ;
+ RECT 845.355000 251.000000 846.620000 251.480000 ;
+ RECT 845.355000 240.120000 846.620000 240.600000 ;
+ RECT 845.355000 234.680000 846.620000 235.160000 ;
+ RECT 845.355000 229.240000 846.620000 229.720000 ;
+ RECT 845.355000 223.800000 846.620000 224.280000 ;
+ RECT 845.355000 218.360000 846.620000 218.840000 ;
+ RECT 845.355000 212.920000 846.620000 213.400000 ;
+ RECT 845.355000 202.040000 846.620000 202.520000 ;
+ RECT 845.355000 207.480000 846.620000 207.960000 ;
+ RECT 845.355000 196.600000 846.620000 197.080000 ;
+ RECT 845.355000 191.160000 846.620000 191.640000 ;
+ RECT 845.355000 185.720000 846.620000 186.200000 ;
+ RECT 845.355000 180.280000 846.620000 180.760000 ;
+ RECT 845.355000 174.840000 846.620000 175.320000 ;
+ RECT 845.355000 169.400000 846.620000 169.880000 ;
+ RECT 845.355000 158.520000 846.620000 159.000000 ;
+ RECT 845.355000 163.960000 846.620000 164.440000 ;
+ RECT 845.355000 153.080000 846.620000 153.560000 ;
+ RECT 845.355000 245.560000 846.620000 246.040000 ;
+ RECT 1025.520000 146.750000 1026.620000 343.320000 ;
+ RECT 980.520000 146.750000 981.620000 343.320000 ;
+ RECT 1038.330000 145.500000 1039.330000 345.760000 ;
+ RECT 935.520000 146.750000 936.620000 343.320000 ;
+ RECT 890.520000 146.750000 891.620000 343.320000 ;
+ RECT 845.520000 146.750000 846.620000 343.320000 ;
+ RECT 841.690000 145.500000 842.690000 345.760000 ;
+ LAYER met3 ;
+ RECT 1025.520000 338.040000 1026.620000 338.520000 ;
+ RECT 1038.330000 338.040000 1039.330000 338.520000 ;
+ RECT 1038.330000 327.160000 1039.330000 327.640000 ;
+ RECT 1038.330000 321.720000 1039.330000 322.200000 ;
+ RECT 1038.330000 332.600000 1039.330000 333.080000 ;
+ RECT 1025.520000 332.600000 1026.620000 333.080000 ;
+ RECT 1025.520000 327.160000 1026.620000 327.640000 ;
+ RECT 1025.520000 321.720000 1026.620000 322.200000 ;
+ RECT 1025.520000 310.840000 1026.620000 311.320000 ;
+ RECT 1025.520000 316.280000 1026.620000 316.760000 ;
+ RECT 1038.330000 310.840000 1039.330000 311.320000 ;
+ RECT 1038.330000 316.280000 1039.330000 316.760000 ;
+ RECT 1025.520000 299.960000 1026.620000 300.440000 ;
+ RECT 1025.520000 305.400000 1026.620000 305.880000 ;
+ RECT 1038.330000 299.960000 1039.330000 300.440000 ;
+ RECT 1038.330000 305.400000 1039.330000 305.880000 ;
+ RECT 980.520000 321.720000 981.620000 322.200000 ;
+ RECT 980.520000 327.160000 981.620000 327.640000 ;
+ RECT 980.520000 332.600000 981.620000 333.080000 ;
+ RECT 980.520000 338.040000 981.620000 338.520000 ;
+ RECT 980.520000 305.400000 981.620000 305.880000 ;
+ RECT 980.520000 299.960000 981.620000 300.440000 ;
+ RECT 980.520000 310.840000 981.620000 311.320000 ;
+ RECT 980.520000 316.280000 981.620000 316.760000 ;
+ RECT 1038.330000 289.080000 1039.330000 289.560000 ;
+ RECT 1038.330000 283.640000 1039.330000 284.120000 ;
+ RECT 1038.330000 294.520000 1039.330000 295.000000 ;
+ RECT 1025.520000 294.520000 1026.620000 295.000000 ;
+ RECT 1025.520000 289.080000 1026.620000 289.560000 ;
+ RECT 1025.520000 283.640000 1026.620000 284.120000 ;
+ RECT 1025.520000 272.760000 1026.620000 273.240000 ;
+ RECT 1025.520000 278.200000 1026.620000 278.680000 ;
+ RECT 1038.330000 272.760000 1039.330000 273.240000 ;
+ RECT 1038.330000 278.200000 1039.330000 278.680000 ;
+ RECT 1038.330000 261.880000 1039.330000 262.360000 ;
+ RECT 1038.330000 267.320000 1039.330000 267.800000 ;
+ RECT 1025.520000 267.320000 1026.620000 267.800000 ;
+ RECT 1025.520000 261.880000 1026.620000 262.360000 ;
+ RECT 1025.520000 251.000000 1026.620000 251.480000 ;
+ RECT 1025.520000 256.440000 1026.620000 256.920000 ;
+ RECT 1038.330000 251.000000 1039.330000 251.480000 ;
+ RECT 1038.330000 256.440000 1039.330000 256.920000 ;
+ RECT 980.520000 272.760000 981.620000 273.240000 ;
+ RECT 980.520000 278.200000 981.620000 278.680000 ;
+ RECT 980.520000 283.640000 981.620000 284.120000 ;
+ RECT 980.520000 289.080000 981.620000 289.560000 ;
+ RECT 980.520000 294.520000 981.620000 295.000000 ;
+ RECT 980.520000 251.000000 981.620000 251.480000 ;
+ RECT 980.520000 256.440000 981.620000 256.920000 ;
+ RECT 980.520000 261.880000 981.620000 262.360000 ;
+ RECT 980.520000 267.320000 981.620000 267.800000 ;
+ RECT 935.520000 327.160000 936.620000 327.640000 ;
+ RECT 935.520000 321.720000 936.620000 322.200000 ;
+ RECT 935.520000 332.600000 936.620000 333.080000 ;
+ RECT 935.520000 338.040000 936.620000 338.520000 ;
+ RECT 890.520000 321.720000 891.620000 322.200000 ;
+ RECT 890.520000 327.160000 891.620000 327.640000 ;
+ RECT 890.520000 332.600000 891.620000 333.080000 ;
+ RECT 890.520000 338.040000 891.620000 338.520000 ;
+ RECT 935.520000 299.960000 936.620000 300.440000 ;
+ RECT 935.520000 305.400000 936.620000 305.880000 ;
+ RECT 935.520000 310.840000 936.620000 311.320000 ;
+ RECT 935.520000 316.280000 936.620000 316.760000 ;
+ RECT 890.520000 299.960000 891.620000 300.440000 ;
+ RECT 890.520000 305.400000 891.620000 305.880000 ;
+ RECT 890.520000 310.840000 891.620000 311.320000 ;
+ RECT 890.520000 316.280000 891.620000 316.760000 ;
+ RECT 841.690000 338.040000 842.690000 338.520000 ;
+ RECT 845.355000 338.040000 846.620000 338.520000 ;
+ RECT 841.690000 327.160000 842.690000 327.640000 ;
+ RECT 845.355000 327.160000 846.620000 327.640000 ;
+ RECT 841.690000 332.600000 842.690000 333.080000 ;
+ RECT 845.355000 332.600000 846.620000 333.080000 ;
+ RECT 841.690000 321.720000 842.690000 322.200000 ;
+ RECT 845.355000 321.720000 846.620000 322.200000 ;
+ RECT 841.690000 316.280000 842.690000 316.760000 ;
+ RECT 845.355000 316.280000 846.620000 316.760000 ;
+ RECT 841.690000 310.840000 842.690000 311.320000 ;
+ RECT 845.355000 310.840000 846.620000 311.320000 ;
+ RECT 841.690000 305.400000 842.690000 305.880000 ;
+ RECT 845.355000 305.400000 846.620000 305.880000 ;
+ RECT 841.690000 299.960000 842.690000 300.440000 ;
+ RECT 845.355000 299.960000 846.620000 300.440000 ;
+ RECT 935.520000 272.760000 936.620000 273.240000 ;
+ RECT 935.520000 278.200000 936.620000 278.680000 ;
+ RECT 935.520000 283.640000 936.620000 284.120000 ;
+ RECT 935.520000 289.080000 936.620000 289.560000 ;
+ RECT 935.520000 294.520000 936.620000 295.000000 ;
+ RECT 890.520000 272.760000 891.620000 273.240000 ;
+ RECT 890.520000 278.200000 891.620000 278.680000 ;
+ RECT 890.520000 283.640000 891.620000 284.120000 ;
+ RECT 890.520000 289.080000 891.620000 289.560000 ;
+ RECT 890.520000 294.520000 891.620000 295.000000 ;
+ RECT 935.520000 251.000000 936.620000 251.480000 ;
+ RECT 935.520000 256.440000 936.620000 256.920000 ;
+ RECT 935.520000 261.880000 936.620000 262.360000 ;
+ RECT 935.520000 267.320000 936.620000 267.800000 ;
+ RECT 890.520000 251.000000 891.620000 251.480000 ;
+ RECT 890.520000 256.440000 891.620000 256.920000 ;
+ RECT 890.520000 261.880000 891.620000 262.360000 ;
+ RECT 890.520000 267.320000 891.620000 267.800000 ;
+ RECT 841.690000 294.520000 842.690000 295.000000 ;
+ RECT 845.355000 294.520000 846.620000 295.000000 ;
+ RECT 841.690000 283.640000 842.690000 284.120000 ;
+ RECT 845.355000 283.640000 846.620000 284.120000 ;
+ RECT 841.690000 289.080000 842.690000 289.560000 ;
+ RECT 845.355000 289.080000 846.620000 289.560000 ;
+ RECT 841.690000 278.200000 842.690000 278.680000 ;
+ RECT 845.355000 278.200000 846.620000 278.680000 ;
+ RECT 841.690000 272.760000 842.690000 273.240000 ;
+ RECT 845.355000 272.760000 846.620000 273.240000 ;
+ RECT 841.690000 267.320000 842.690000 267.800000 ;
+ RECT 845.355000 267.320000 846.620000 267.800000 ;
+ RECT 841.690000 261.880000 842.690000 262.360000 ;
+ RECT 845.355000 261.880000 846.620000 262.360000 ;
+ RECT 841.690000 256.440000 842.690000 256.920000 ;
+ RECT 845.355000 256.440000 846.620000 256.920000 ;
+ RECT 841.690000 251.000000 842.690000 251.480000 ;
+ RECT 845.355000 251.000000 846.620000 251.480000 ;
+ RECT 1025.520000 234.680000 1026.620000 235.160000 ;
+ RECT 1025.520000 240.120000 1026.620000 240.600000 ;
+ RECT 1038.330000 234.680000 1039.330000 235.160000 ;
+ RECT 1038.330000 240.120000 1039.330000 240.600000 ;
+ RECT 1038.330000 223.800000 1039.330000 224.280000 ;
+ RECT 1038.330000 229.240000 1039.330000 229.720000 ;
+ RECT 1025.520000 229.240000 1026.620000 229.720000 ;
+ RECT 1025.520000 223.800000 1026.620000 224.280000 ;
+ RECT 1025.520000 212.920000 1026.620000 213.400000 ;
+ RECT 1025.520000 218.360000 1026.620000 218.840000 ;
+ RECT 1038.330000 212.920000 1039.330000 213.400000 ;
+ RECT 1038.330000 218.360000 1039.330000 218.840000 ;
+ RECT 1038.330000 202.040000 1039.330000 202.520000 ;
+ RECT 1038.330000 196.600000 1039.330000 197.080000 ;
+ RECT 1038.330000 207.480000 1039.330000 207.960000 ;
+ RECT 1025.520000 207.480000 1026.620000 207.960000 ;
+ RECT 1025.520000 202.040000 1026.620000 202.520000 ;
+ RECT 1025.520000 196.600000 1026.620000 197.080000 ;
+ RECT 980.520000 223.800000 981.620000 224.280000 ;
+ RECT 980.520000 229.240000 981.620000 229.720000 ;
+ RECT 980.520000 234.680000 981.620000 235.160000 ;
+ RECT 980.520000 240.120000 981.620000 240.600000 ;
+ RECT 980.520000 196.600000 981.620000 197.080000 ;
+ RECT 980.520000 202.040000 981.620000 202.520000 ;
+ RECT 980.520000 207.480000 981.620000 207.960000 ;
+ RECT 980.520000 212.920000 981.620000 213.400000 ;
+ RECT 980.520000 218.360000 981.620000 218.840000 ;
+ RECT 1025.520000 185.720000 1026.620000 186.200000 ;
+ RECT 1025.520000 191.160000 1026.620000 191.640000 ;
+ RECT 1038.330000 185.720000 1039.330000 186.200000 ;
+ RECT 1038.330000 191.160000 1039.330000 191.640000 ;
+ RECT 1025.520000 174.840000 1026.620000 175.320000 ;
+ RECT 1025.520000 180.280000 1026.620000 180.760000 ;
+ RECT 1038.330000 174.840000 1039.330000 175.320000 ;
+ RECT 1038.330000 180.280000 1039.330000 180.760000 ;
+ RECT 1038.330000 163.960000 1039.330000 164.440000 ;
+ RECT 1038.330000 158.520000 1039.330000 159.000000 ;
+ RECT 1038.330000 169.400000 1039.330000 169.880000 ;
+ RECT 1025.520000 169.400000 1026.620000 169.880000 ;
+ RECT 1025.520000 163.960000 1026.620000 164.440000 ;
+ RECT 1025.520000 158.520000 1026.620000 159.000000 ;
+ RECT 1025.520000 153.080000 1026.620000 153.560000 ;
+ RECT 1038.330000 153.080000 1039.330000 153.560000 ;
+ RECT 980.520000 174.840000 981.620000 175.320000 ;
+ RECT 980.520000 180.280000 981.620000 180.760000 ;
+ RECT 980.520000 185.720000 981.620000 186.200000 ;
+ RECT 980.520000 191.160000 981.620000 191.640000 ;
+ RECT 980.520000 153.080000 981.620000 153.560000 ;
+ RECT 980.520000 158.520000 981.620000 159.000000 ;
+ RECT 980.520000 163.960000 981.620000 164.440000 ;
+ RECT 980.520000 169.400000 981.620000 169.880000 ;
+ RECT 935.520000 223.800000 936.620000 224.280000 ;
+ RECT 935.520000 229.240000 936.620000 229.720000 ;
+ RECT 935.520000 234.680000 936.620000 235.160000 ;
+ RECT 935.520000 240.120000 936.620000 240.600000 ;
+ RECT 890.520000 223.800000 891.620000 224.280000 ;
+ RECT 890.520000 229.240000 891.620000 229.720000 ;
+ RECT 890.520000 234.680000 891.620000 235.160000 ;
+ RECT 890.520000 240.120000 891.620000 240.600000 ;
+ RECT 935.520000 196.600000 936.620000 197.080000 ;
+ RECT 935.520000 202.040000 936.620000 202.520000 ;
+ RECT 935.520000 207.480000 936.620000 207.960000 ;
+ RECT 935.520000 212.920000 936.620000 213.400000 ;
+ RECT 935.520000 218.360000 936.620000 218.840000 ;
+ RECT 890.520000 196.600000 891.620000 197.080000 ;
+ RECT 890.520000 202.040000 891.620000 202.520000 ;
+ RECT 890.520000 207.480000 891.620000 207.960000 ;
+ RECT 890.520000 212.920000 891.620000 213.400000 ;
+ RECT 890.520000 218.360000 891.620000 218.840000 ;
+ RECT 841.690000 240.120000 842.690000 240.600000 ;
+ RECT 845.355000 240.120000 846.620000 240.600000 ;
+ RECT 841.690000 234.680000 842.690000 235.160000 ;
+ RECT 845.355000 234.680000 846.620000 235.160000 ;
+ RECT 841.690000 229.240000 842.690000 229.720000 ;
+ RECT 845.355000 229.240000 846.620000 229.720000 ;
+ RECT 841.690000 223.800000 842.690000 224.280000 ;
+ RECT 845.355000 223.800000 846.620000 224.280000 ;
+ RECT 841.690000 218.360000 842.690000 218.840000 ;
+ RECT 845.355000 218.360000 846.620000 218.840000 ;
+ RECT 841.690000 212.920000 842.690000 213.400000 ;
+ RECT 845.355000 212.920000 846.620000 213.400000 ;
+ RECT 841.690000 202.040000 842.690000 202.520000 ;
+ RECT 845.355000 202.040000 846.620000 202.520000 ;
+ RECT 841.690000 207.480000 842.690000 207.960000 ;
+ RECT 845.355000 207.480000 846.620000 207.960000 ;
+ RECT 841.690000 196.600000 842.690000 197.080000 ;
+ RECT 845.355000 196.600000 846.620000 197.080000 ;
+ RECT 935.520000 174.840000 936.620000 175.320000 ;
+ RECT 935.520000 180.280000 936.620000 180.760000 ;
+ RECT 935.520000 185.720000 936.620000 186.200000 ;
+ RECT 935.520000 191.160000 936.620000 191.640000 ;
+ RECT 890.520000 174.840000 891.620000 175.320000 ;
+ RECT 890.520000 180.280000 891.620000 180.760000 ;
+ RECT 890.520000 185.720000 891.620000 186.200000 ;
+ RECT 890.520000 191.160000 891.620000 191.640000 ;
+ RECT 935.520000 153.080000 936.620000 153.560000 ;
+ RECT 935.520000 158.520000 936.620000 159.000000 ;
+ RECT 935.520000 163.960000 936.620000 164.440000 ;
+ RECT 935.520000 169.400000 936.620000 169.880000 ;
+ RECT 890.520000 153.080000 891.620000 153.560000 ;
+ RECT 890.520000 158.520000 891.620000 159.000000 ;
+ RECT 890.520000 163.960000 891.620000 164.440000 ;
+ RECT 890.520000 169.400000 891.620000 169.880000 ;
+ RECT 841.690000 191.160000 842.690000 191.640000 ;
+ RECT 845.355000 191.160000 846.620000 191.640000 ;
+ RECT 841.690000 185.720000 842.690000 186.200000 ;
+ RECT 845.355000 185.720000 846.620000 186.200000 ;
+ RECT 841.690000 180.280000 842.690000 180.760000 ;
+ RECT 845.355000 180.280000 846.620000 180.760000 ;
+ RECT 841.690000 174.840000 842.690000 175.320000 ;
+ RECT 845.355000 174.840000 846.620000 175.320000 ;
+ RECT 841.690000 169.400000 842.690000 169.880000 ;
+ RECT 845.355000 169.400000 846.620000 169.880000 ;
+ RECT 841.690000 158.520000 842.690000 159.000000 ;
+ RECT 845.355000 158.520000 846.620000 159.000000 ;
+ RECT 841.690000 163.960000 842.690000 164.440000 ;
+ RECT 845.355000 163.960000 846.620000 164.440000 ;
+ RECT 841.690000 153.080000 842.690000 153.560000 ;
+ RECT 845.355000 153.080000 846.620000 153.560000 ;
+ RECT 980.520000 245.560000 981.620000 246.040000 ;
+ RECT 1025.520000 245.560000 1026.620000 246.040000 ;
+ RECT 1038.330000 245.560000 1039.330000 246.040000 ;
+ RECT 890.520000 245.560000 891.620000 246.040000 ;
+ RECT 935.520000 245.560000 936.620000 246.040000 ;
+ RECT 841.690000 245.560000 842.690000 246.040000 ;
+ RECT 845.355000 245.560000 846.620000 246.040000 ;
+ RECT 840.460000 342.320000 1040.560000 343.320000 ;
+ RECT 840.460000 146.750000 1040.560000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 145.500000 842.690000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 344.760000 842.690000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 145.500000 1039.330000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 344.760000 1039.330000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 146.750000 841.460000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 146.750000 1040.560000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 342.320000 841.460000 343.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 342.320000 1040.560000 343.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 139.140000 846.620000 139.620000 ;
+ RECT 845.355000 133.700000 846.620000 134.180000 ;
+ RECT 845.355000 128.260000 846.620000 128.740000 ;
+ RECT 845.355000 122.820000 846.620000 123.300000 ;
+ RECT 841.690000 115.240000 842.690000 145.500000 ;
+ RECT 1038.330000 115.240000 1039.330000 145.500000 ;
+ RECT 845.520000 116.490000 846.620000 143.740000 ;
+ RECT 890.520000 116.490000 891.620000 143.740000 ;
+ RECT 935.520000 116.490000 936.620000 143.740000 ;
+ RECT 980.520000 116.490000 981.620000 143.740000 ;
+ RECT 1025.520000 116.490000 1026.620000 143.740000 ;
+ LAYER met3 ;
+ RECT 1038.330000 139.140000 1039.330000 139.620000 ;
+ RECT 1038.330000 133.700000 1039.330000 134.180000 ;
+ RECT 1025.520000 139.140000 1026.620000 139.620000 ;
+ RECT 1025.520000 133.700000 1026.620000 134.180000 ;
+ RECT 980.520000 133.700000 981.620000 134.180000 ;
+ RECT 980.520000 139.140000 981.620000 139.620000 ;
+ RECT 935.520000 133.700000 936.620000 134.180000 ;
+ RECT 890.520000 133.700000 891.620000 134.180000 ;
+ RECT 935.520000 139.140000 936.620000 139.620000 ;
+ RECT 890.520000 139.140000 891.620000 139.620000 ;
+ RECT 845.355000 139.140000 846.620000 139.620000 ;
+ RECT 841.690000 139.140000 842.690000 139.620000 ;
+ RECT 845.355000 133.700000 846.620000 134.180000 ;
+ RECT 841.690000 133.700000 842.690000 134.180000 ;
+ RECT 1038.330000 128.260000 1039.330000 128.740000 ;
+ RECT 1038.330000 122.820000 1039.330000 123.300000 ;
+ RECT 1025.520000 128.260000 1026.620000 128.740000 ;
+ RECT 1025.520000 122.820000 1026.620000 123.300000 ;
+ RECT 980.520000 122.820000 981.620000 123.300000 ;
+ RECT 980.520000 128.260000 981.620000 128.740000 ;
+ RECT 935.520000 122.820000 936.620000 123.300000 ;
+ RECT 890.520000 122.820000 891.620000 123.300000 ;
+ RECT 935.520000 128.260000 936.620000 128.740000 ;
+ RECT 890.520000 128.260000 891.620000 128.740000 ;
+ RECT 845.355000 128.260000 846.620000 128.740000 ;
+ RECT 841.690000 128.260000 842.690000 128.740000 ;
+ RECT 845.355000 122.820000 846.620000 123.300000 ;
+ RECT 841.690000 122.820000 842.690000 123.300000 ;
+ RECT 840.460000 142.740000 1040.560000 143.740000 ;
+ RECT 840.460000 116.490000 1040.560000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 116.490000 841.460000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 116.490000 1040.560000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 142.740000 841.460000 143.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 142.740000 1040.560000 143.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 115.240000 842.690000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 144.500000 842.690000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 115.240000 1039.330000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 144.500000 1039.330000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 3341.940000 846.620000 3342.420000 ;
+ RECT 845.355000 3331.060000 846.620000 3331.540000 ;
+ RECT 845.355000 3336.500000 846.620000 3336.980000 ;
+ RECT 845.355000 3325.620000 846.620000 3326.100000 ;
+ RECT 845.355000 3320.180000 846.620000 3320.660000 ;
+ RECT 845.355000 3314.740000 846.620000 3315.220000 ;
+ RECT 845.355000 3309.300000 846.620000 3309.780000 ;
+ RECT 845.355000 3303.860000 846.620000 3304.340000 ;
+ RECT 845.355000 3298.420000 846.620000 3298.900000 ;
+ RECT 845.355000 3287.540000 846.620000 3288.020000 ;
+ RECT 845.355000 3292.980000 846.620000 3293.460000 ;
+ RECT 845.355000 3282.100000 846.620000 3282.580000 ;
+ RECT 845.355000 3276.660000 846.620000 3277.140000 ;
+ RECT 845.355000 3271.220000 846.620000 3271.700000 ;
+ RECT 845.355000 3265.780000 846.620000 3266.260000 ;
+ RECT 845.355000 3260.340000 846.620000 3260.820000 ;
+ RECT 845.355000 3254.900000 846.620000 3255.380000 ;
+ RECT 845.355000 3244.020000 846.620000 3244.500000 ;
+ RECT 845.355000 3238.580000 846.620000 3239.060000 ;
+ RECT 845.355000 3233.140000 846.620000 3233.620000 ;
+ RECT 845.355000 3227.700000 846.620000 3228.180000 ;
+ RECT 845.355000 3222.260000 846.620000 3222.740000 ;
+ RECT 845.355000 3216.820000 846.620000 3217.300000 ;
+ RECT 845.355000 3205.940000 846.620000 3206.420000 ;
+ RECT 845.355000 3211.380000 846.620000 3211.860000 ;
+ RECT 845.355000 3200.500000 846.620000 3200.980000 ;
+ RECT 845.355000 3195.060000 846.620000 3195.540000 ;
+ RECT 845.355000 3189.620000 846.620000 3190.100000 ;
+ RECT 845.355000 3184.180000 846.620000 3184.660000 ;
+ RECT 845.355000 3178.740000 846.620000 3179.220000 ;
+ RECT 845.355000 3173.300000 846.620000 3173.780000 ;
+ RECT 845.355000 3162.420000 846.620000 3162.900000 ;
+ RECT 845.355000 3167.860000 846.620000 3168.340000 ;
+ RECT 845.355000 3156.980000 846.620000 3157.460000 ;
+ RECT 845.355000 3249.460000 846.620000 3249.940000 ;
+ RECT 1025.520000 3150.650000 1026.620000 3347.220000 ;
+ RECT 980.520000 3150.650000 981.620000 3347.220000 ;
+ RECT 1038.330000 3149.400000 1039.330000 3349.660000 ;
+ RECT 935.520000 3150.650000 936.620000 3347.220000 ;
+ RECT 890.520000 3150.650000 891.620000 3347.220000 ;
+ RECT 845.520000 3150.650000 846.620000 3347.220000 ;
+ RECT 841.690000 3149.400000 842.690000 3349.660000 ;
+ LAYER met3 ;
+ RECT 1025.520000 3341.940000 1026.620000 3342.420000 ;
+ RECT 1038.330000 3341.940000 1039.330000 3342.420000 ;
+ RECT 1038.330000 3331.060000 1039.330000 3331.540000 ;
+ RECT 1038.330000 3325.620000 1039.330000 3326.100000 ;
+ RECT 1038.330000 3336.500000 1039.330000 3336.980000 ;
+ RECT 1025.520000 3336.500000 1026.620000 3336.980000 ;
+ RECT 1025.520000 3331.060000 1026.620000 3331.540000 ;
+ RECT 1025.520000 3325.620000 1026.620000 3326.100000 ;
+ RECT 1025.520000 3314.740000 1026.620000 3315.220000 ;
+ RECT 1025.520000 3320.180000 1026.620000 3320.660000 ;
+ RECT 1038.330000 3314.740000 1039.330000 3315.220000 ;
+ RECT 1038.330000 3320.180000 1039.330000 3320.660000 ;
+ RECT 1025.520000 3303.860000 1026.620000 3304.340000 ;
+ RECT 1025.520000 3309.300000 1026.620000 3309.780000 ;
+ RECT 1038.330000 3303.860000 1039.330000 3304.340000 ;
+ RECT 1038.330000 3309.300000 1039.330000 3309.780000 ;
+ RECT 980.520000 3325.620000 981.620000 3326.100000 ;
+ RECT 980.520000 3331.060000 981.620000 3331.540000 ;
+ RECT 980.520000 3336.500000 981.620000 3336.980000 ;
+ RECT 980.520000 3341.940000 981.620000 3342.420000 ;
+ RECT 980.520000 3309.300000 981.620000 3309.780000 ;
+ RECT 980.520000 3303.860000 981.620000 3304.340000 ;
+ RECT 980.520000 3314.740000 981.620000 3315.220000 ;
+ RECT 980.520000 3320.180000 981.620000 3320.660000 ;
+ RECT 1038.330000 3292.980000 1039.330000 3293.460000 ;
+ RECT 1038.330000 3287.540000 1039.330000 3288.020000 ;
+ RECT 1038.330000 3298.420000 1039.330000 3298.900000 ;
+ RECT 1025.520000 3298.420000 1026.620000 3298.900000 ;
+ RECT 1025.520000 3292.980000 1026.620000 3293.460000 ;
+ RECT 1025.520000 3287.540000 1026.620000 3288.020000 ;
+ RECT 1025.520000 3276.660000 1026.620000 3277.140000 ;
+ RECT 1025.520000 3282.100000 1026.620000 3282.580000 ;
+ RECT 1038.330000 3276.660000 1039.330000 3277.140000 ;
+ RECT 1038.330000 3282.100000 1039.330000 3282.580000 ;
+ RECT 1038.330000 3265.780000 1039.330000 3266.260000 ;
+ RECT 1038.330000 3271.220000 1039.330000 3271.700000 ;
+ RECT 1025.520000 3271.220000 1026.620000 3271.700000 ;
+ RECT 1025.520000 3265.780000 1026.620000 3266.260000 ;
+ RECT 1025.520000 3254.900000 1026.620000 3255.380000 ;
+ RECT 1025.520000 3260.340000 1026.620000 3260.820000 ;
+ RECT 1038.330000 3254.900000 1039.330000 3255.380000 ;
+ RECT 1038.330000 3260.340000 1039.330000 3260.820000 ;
+ RECT 980.520000 3276.660000 981.620000 3277.140000 ;
+ RECT 980.520000 3282.100000 981.620000 3282.580000 ;
+ RECT 980.520000 3287.540000 981.620000 3288.020000 ;
+ RECT 980.520000 3292.980000 981.620000 3293.460000 ;
+ RECT 980.520000 3298.420000 981.620000 3298.900000 ;
+ RECT 980.520000 3254.900000 981.620000 3255.380000 ;
+ RECT 980.520000 3260.340000 981.620000 3260.820000 ;
+ RECT 980.520000 3265.780000 981.620000 3266.260000 ;
+ RECT 980.520000 3271.220000 981.620000 3271.700000 ;
+ RECT 935.520000 3331.060000 936.620000 3331.540000 ;
+ RECT 935.520000 3325.620000 936.620000 3326.100000 ;
+ RECT 935.520000 3336.500000 936.620000 3336.980000 ;
+ RECT 935.520000 3341.940000 936.620000 3342.420000 ;
+ RECT 890.520000 3325.620000 891.620000 3326.100000 ;
+ RECT 890.520000 3331.060000 891.620000 3331.540000 ;
+ RECT 890.520000 3336.500000 891.620000 3336.980000 ;
+ RECT 890.520000 3341.940000 891.620000 3342.420000 ;
+ RECT 935.520000 3303.860000 936.620000 3304.340000 ;
+ RECT 935.520000 3309.300000 936.620000 3309.780000 ;
+ RECT 935.520000 3314.740000 936.620000 3315.220000 ;
+ RECT 935.520000 3320.180000 936.620000 3320.660000 ;
+ RECT 890.520000 3303.860000 891.620000 3304.340000 ;
+ RECT 890.520000 3309.300000 891.620000 3309.780000 ;
+ RECT 890.520000 3314.740000 891.620000 3315.220000 ;
+ RECT 890.520000 3320.180000 891.620000 3320.660000 ;
+ RECT 841.690000 3341.940000 842.690000 3342.420000 ;
+ RECT 845.355000 3341.940000 846.620000 3342.420000 ;
+ RECT 841.690000 3331.060000 842.690000 3331.540000 ;
+ RECT 845.355000 3331.060000 846.620000 3331.540000 ;
+ RECT 841.690000 3336.500000 842.690000 3336.980000 ;
+ RECT 845.355000 3336.500000 846.620000 3336.980000 ;
+ RECT 841.690000 3325.620000 842.690000 3326.100000 ;
+ RECT 845.355000 3325.620000 846.620000 3326.100000 ;
+ RECT 841.690000 3320.180000 842.690000 3320.660000 ;
+ RECT 845.355000 3320.180000 846.620000 3320.660000 ;
+ RECT 841.690000 3314.740000 842.690000 3315.220000 ;
+ RECT 845.355000 3314.740000 846.620000 3315.220000 ;
+ RECT 841.690000 3309.300000 842.690000 3309.780000 ;
+ RECT 845.355000 3309.300000 846.620000 3309.780000 ;
+ RECT 841.690000 3303.860000 842.690000 3304.340000 ;
+ RECT 845.355000 3303.860000 846.620000 3304.340000 ;
+ RECT 935.520000 3276.660000 936.620000 3277.140000 ;
+ RECT 935.520000 3282.100000 936.620000 3282.580000 ;
+ RECT 935.520000 3287.540000 936.620000 3288.020000 ;
+ RECT 935.520000 3292.980000 936.620000 3293.460000 ;
+ RECT 935.520000 3298.420000 936.620000 3298.900000 ;
+ RECT 890.520000 3276.660000 891.620000 3277.140000 ;
+ RECT 890.520000 3282.100000 891.620000 3282.580000 ;
+ RECT 890.520000 3287.540000 891.620000 3288.020000 ;
+ RECT 890.520000 3292.980000 891.620000 3293.460000 ;
+ RECT 890.520000 3298.420000 891.620000 3298.900000 ;
+ RECT 935.520000 3254.900000 936.620000 3255.380000 ;
+ RECT 935.520000 3260.340000 936.620000 3260.820000 ;
+ RECT 935.520000 3265.780000 936.620000 3266.260000 ;
+ RECT 935.520000 3271.220000 936.620000 3271.700000 ;
+ RECT 890.520000 3254.900000 891.620000 3255.380000 ;
+ RECT 890.520000 3260.340000 891.620000 3260.820000 ;
+ RECT 890.520000 3265.780000 891.620000 3266.260000 ;
+ RECT 890.520000 3271.220000 891.620000 3271.700000 ;
+ RECT 841.690000 3298.420000 842.690000 3298.900000 ;
+ RECT 845.355000 3298.420000 846.620000 3298.900000 ;
+ RECT 841.690000 3287.540000 842.690000 3288.020000 ;
+ RECT 845.355000 3287.540000 846.620000 3288.020000 ;
+ RECT 841.690000 3292.980000 842.690000 3293.460000 ;
+ RECT 845.355000 3292.980000 846.620000 3293.460000 ;
+ RECT 841.690000 3282.100000 842.690000 3282.580000 ;
+ RECT 845.355000 3282.100000 846.620000 3282.580000 ;
+ RECT 841.690000 3276.660000 842.690000 3277.140000 ;
+ RECT 845.355000 3276.660000 846.620000 3277.140000 ;
+ RECT 841.690000 3271.220000 842.690000 3271.700000 ;
+ RECT 845.355000 3271.220000 846.620000 3271.700000 ;
+ RECT 841.690000 3265.780000 842.690000 3266.260000 ;
+ RECT 845.355000 3265.780000 846.620000 3266.260000 ;
+ RECT 841.690000 3260.340000 842.690000 3260.820000 ;
+ RECT 845.355000 3260.340000 846.620000 3260.820000 ;
+ RECT 841.690000 3254.900000 842.690000 3255.380000 ;
+ RECT 845.355000 3254.900000 846.620000 3255.380000 ;
+ RECT 1025.520000 3238.580000 1026.620000 3239.060000 ;
+ RECT 1025.520000 3244.020000 1026.620000 3244.500000 ;
+ RECT 1038.330000 3238.580000 1039.330000 3239.060000 ;
+ RECT 1038.330000 3244.020000 1039.330000 3244.500000 ;
+ RECT 1038.330000 3227.700000 1039.330000 3228.180000 ;
+ RECT 1038.330000 3233.140000 1039.330000 3233.620000 ;
+ RECT 1025.520000 3233.140000 1026.620000 3233.620000 ;
+ RECT 1025.520000 3227.700000 1026.620000 3228.180000 ;
+ RECT 1025.520000 3216.820000 1026.620000 3217.300000 ;
+ RECT 1025.520000 3222.260000 1026.620000 3222.740000 ;
+ RECT 1038.330000 3216.820000 1039.330000 3217.300000 ;
+ RECT 1038.330000 3222.260000 1039.330000 3222.740000 ;
+ RECT 1038.330000 3205.940000 1039.330000 3206.420000 ;
+ RECT 1038.330000 3200.500000 1039.330000 3200.980000 ;
+ RECT 1038.330000 3211.380000 1039.330000 3211.860000 ;
+ RECT 1025.520000 3211.380000 1026.620000 3211.860000 ;
+ RECT 1025.520000 3205.940000 1026.620000 3206.420000 ;
+ RECT 1025.520000 3200.500000 1026.620000 3200.980000 ;
+ RECT 980.520000 3227.700000 981.620000 3228.180000 ;
+ RECT 980.520000 3233.140000 981.620000 3233.620000 ;
+ RECT 980.520000 3238.580000 981.620000 3239.060000 ;
+ RECT 980.520000 3244.020000 981.620000 3244.500000 ;
+ RECT 980.520000 3200.500000 981.620000 3200.980000 ;
+ RECT 980.520000 3205.940000 981.620000 3206.420000 ;
+ RECT 980.520000 3211.380000 981.620000 3211.860000 ;
+ RECT 980.520000 3216.820000 981.620000 3217.300000 ;
+ RECT 980.520000 3222.260000 981.620000 3222.740000 ;
+ RECT 1025.520000 3189.620000 1026.620000 3190.100000 ;
+ RECT 1025.520000 3195.060000 1026.620000 3195.540000 ;
+ RECT 1038.330000 3189.620000 1039.330000 3190.100000 ;
+ RECT 1038.330000 3195.060000 1039.330000 3195.540000 ;
+ RECT 1025.520000 3178.740000 1026.620000 3179.220000 ;
+ RECT 1025.520000 3184.180000 1026.620000 3184.660000 ;
+ RECT 1038.330000 3178.740000 1039.330000 3179.220000 ;
+ RECT 1038.330000 3184.180000 1039.330000 3184.660000 ;
+ RECT 1038.330000 3167.860000 1039.330000 3168.340000 ;
+ RECT 1038.330000 3162.420000 1039.330000 3162.900000 ;
+ RECT 1038.330000 3173.300000 1039.330000 3173.780000 ;
+ RECT 1025.520000 3173.300000 1026.620000 3173.780000 ;
+ RECT 1025.520000 3167.860000 1026.620000 3168.340000 ;
+ RECT 1025.520000 3162.420000 1026.620000 3162.900000 ;
+ RECT 1025.520000 3156.980000 1026.620000 3157.460000 ;
+ RECT 1038.330000 3156.980000 1039.330000 3157.460000 ;
+ RECT 980.520000 3178.740000 981.620000 3179.220000 ;
+ RECT 980.520000 3184.180000 981.620000 3184.660000 ;
+ RECT 980.520000 3189.620000 981.620000 3190.100000 ;
+ RECT 980.520000 3195.060000 981.620000 3195.540000 ;
+ RECT 980.520000 3156.980000 981.620000 3157.460000 ;
+ RECT 980.520000 3162.420000 981.620000 3162.900000 ;
+ RECT 980.520000 3167.860000 981.620000 3168.340000 ;
+ RECT 980.520000 3173.300000 981.620000 3173.780000 ;
+ RECT 935.520000 3227.700000 936.620000 3228.180000 ;
+ RECT 935.520000 3233.140000 936.620000 3233.620000 ;
+ RECT 935.520000 3238.580000 936.620000 3239.060000 ;
+ RECT 935.520000 3244.020000 936.620000 3244.500000 ;
+ RECT 890.520000 3227.700000 891.620000 3228.180000 ;
+ RECT 890.520000 3233.140000 891.620000 3233.620000 ;
+ RECT 890.520000 3238.580000 891.620000 3239.060000 ;
+ RECT 890.520000 3244.020000 891.620000 3244.500000 ;
+ RECT 935.520000 3200.500000 936.620000 3200.980000 ;
+ RECT 935.520000 3205.940000 936.620000 3206.420000 ;
+ RECT 935.520000 3211.380000 936.620000 3211.860000 ;
+ RECT 935.520000 3216.820000 936.620000 3217.300000 ;
+ RECT 935.520000 3222.260000 936.620000 3222.740000 ;
+ RECT 890.520000 3200.500000 891.620000 3200.980000 ;
+ RECT 890.520000 3205.940000 891.620000 3206.420000 ;
+ RECT 890.520000 3211.380000 891.620000 3211.860000 ;
+ RECT 890.520000 3216.820000 891.620000 3217.300000 ;
+ RECT 890.520000 3222.260000 891.620000 3222.740000 ;
+ RECT 841.690000 3244.020000 842.690000 3244.500000 ;
+ RECT 845.355000 3244.020000 846.620000 3244.500000 ;
+ RECT 841.690000 3238.580000 842.690000 3239.060000 ;
+ RECT 845.355000 3238.580000 846.620000 3239.060000 ;
+ RECT 841.690000 3233.140000 842.690000 3233.620000 ;
+ RECT 845.355000 3233.140000 846.620000 3233.620000 ;
+ RECT 841.690000 3227.700000 842.690000 3228.180000 ;
+ RECT 845.355000 3227.700000 846.620000 3228.180000 ;
+ RECT 841.690000 3222.260000 842.690000 3222.740000 ;
+ RECT 845.355000 3222.260000 846.620000 3222.740000 ;
+ RECT 841.690000 3216.820000 842.690000 3217.300000 ;
+ RECT 845.355000 3216.820000 846.620000 3217.300000 ;
+ RECT 841.690000 3205.940000 842.690000 3206.420000 ;
+ RECT 845.355000 3205.940000 846.620000 3206.420000 ;
+ RECT 841.690000 3211.380000 842.690000 3211.860000 ;
+ RECT 845.355000 3211.380000 846.620000 3211.860000 ;
+ RECT 841.690000 3200.500000 842.690000 3200.980000 ;
+ RECT 845.355000 3200.500000 846.620000 3200.980000 ;
+ RECT 935.520000 3178.740000 936.620000 3179.220000 ;
+ RECT 935.520000 3184.180000 936.620000 3184.660000 ;
+ RECT 935.520000 3189.620000 936.620000 3190.100000 ;
+ RECT 935.520000 3195.060000 936.620000 3195.540000 ;
+ RECT 890.520000 3178.740000 891.620000 3179.220000 ;
+ RECT 890.520000 3184.180000 891.620000 3184.660000 ;
+ RECT 890.520000 3189.620000 891.620000 3190.100000 ;
+ RECT 890.520000 3195.060000 891.620000 3195.540000 ;
+ RECT 935.520000 3156.980000 936.620000 3157.460000 ;
+ RECT 935.520000 3162.420000 936.620000 3162.900000 ;
+ RECT 935.520000 3167.860000 936.620000 3168.340000 ;
+ RECT 935.520000 3173.300000 936.620000 3173.780000 ;
+ RECT 890.520000 3156.980000 891.620000 3157.460000 ;
+ RECT 890.520000 3162.420000 891.620000 3162.900000 ;
+ RECT 890.520000 3167.860000 891.620000 3168.340000 ;
+ RECT 890.520000 3173.300000 891.620000 3173.780000 ;
+ RECT 841.690000 3195.060000 842.690000 3195.540000 ;
+ RECT 845.355000 3195.060000 846.620000 3195.540000 ;
+ RECT 841.690000 3189.620000 842.690000 3190.100000 ;
+ RECT 845.355000 3189.620000 846.620000 3190.100000 ;
+ RECT 841.690000 3184.180000 842.690000 3184.660000 ;
+ RECT 845.355000 3184.180000 846.620000 3184.660000 ;
+ RECT 841.690000 3178.740000 842.690000 3179.220000 ;
+ RECT 845.355000 3178.740000 846.620000 3179.220000 ;
+ RECT 841.690000 3173.300000 842.690000 3173.780000 ;
+ RECT 845.355000 3173.300000 846.620000 3173.780000 ;
+ RECT 841.690000 3162.420000 842.690000 3162.900000 ;
+ RECT 845.355000 3162.420000 846.620000 3162.900000 ;
+ RECT 841.690000 3167.860000 842.690000 3168.340000 ;
+ RECT 845.355000 3167.860000 846.620000 3168.340000 ;
+ RECT 841.690000 3156.980000 842.690000 3157.460000 ;
+ RECT 845.355000 3156.980000 846.620000 3157.460000 ;
+ RECT 980.520000 3249.460000 981.620000 3249.940000 ;
+ RECT 1025.520000 3249.460000 1026.620000 3249.940000 ;
+ RECT 1038.330000 3249.460000 1039.330000 3249.940000 ;
+ RECT 890.520000 3249.460000 891.620000 3249.940000 ;
+ RECT 935.520000 3249.460000 936.620000 3249.940000 ;
+ RECT 841.690000 3249.460000 842.690000 3249.940000 ;
+ RECT 845.355000 3249.460000 846.620000 3249.940000 ;
+ RECT 840.460000 3346.220000 1040.560000 3347.220000 ;
+ RECT 840.460000 3150.650000 1040.560000 3151.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 3149.400000 842.690000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 3348.660000 842.690000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 3149.400000 1039.330000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 3348.660000 1039.330000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 3150.650000 841.460000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 3150.650000 1040.560000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 3346.220000 841.460000 3347.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 3346.220000 1040.560000 3347.220000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 3141.680000 846.620000 3142.160000 ;
+ RECT 845.355000 3130.800000 846.620000 3131.280000 ;
+ RECT 845.355000 3136.240000 846.620000 3136.720000 ;
+ RECT 845.355000 3125.360000 846.620000 3125.840000 ;
+ RECT 845.355000 3119.920000 846.620000 3120.400000 ;
+ RECT 845.355000 3114.480000 846.620000 3114.960000 ;
+ RECT 845.355000 3109.040000 846.620000 3109.520000 ;
+ RECT 845.355000 3103.600000 846.620000 3104.080000 ;
+ RECT 845.355000 3098.160000 846.620000 3098.640000 ;
+ RECT 845.355000 3087.280000 846.620000 3087.760000 ;
+ RECT 845.355000 3092.720000 846.620000 3093.200000 ;
+ RECT 845.355000 3081.840000 846.620000 3082.320000 ;
+ RECT 845.355000 3076.400000 846.620000 3076.880000 ;
+ RECT 845.355000 3070.960000 846.620000 3071.440000 ;
+ RECT 845.355000 3065.520000 846.620000 3066.000000 ;
+ RECT 845.355000 3060.080000 846.620000 3060.560000 ;
+ RECT 845.355000 3054.640000 846.620000 3055.120000 ;
+ RECT 845.355000 3043.760000 846.620000 3044.240000 ;
+ RECT 845.355000 3038.320000 846.620000 3038.800000 ;
+ RECT 845.355000 3032.880000 846.620000 3033.360000 ;
+ RECT 845.355000 3027.440000 846.620000 3027.920000 ;
+ RECT 845.355000 3022.000000 846.620000 3022.480000 ;
+ RECT 845.355000 3016.560000 846.620000 3017.040000 ;
+ RECT 845.355000 3005.680000 846.620000 3006.160000 ;
+ RECT 845.355000 3011.120000 846.620000 3011.600000 ;
+ RECT 845.355000 3000.240000 846.620000 3000.720000 ;
+ RECT 845.355000 2994.800000 846.620000 2995.280000 ;
+ RECT 845.355000 2989.360000 846.620000 2989.840000 ;
+ RECT 845.355000 2983.920000 846.620000 2984.400000 ;
+ RECT 845.355000 2978.480000 846.620000 2978.960000 ;
+ RECT 845.355000 2973.040000 846.620000 2973.520000 ;
+ RECT 845.355000 2962.160000 846.620000 2962.640000 ;
+ RECT 845.355000 2967.600000 846.620000 2968.080000 ;
+ RECT 845.355000 2956.720000 846.620000 2957.200000 ;
+ RECT 845.355000 3049.200000 846.620000 3049.680000 ;
+ RECT 1025.520000 2950.390000 1026.620000 3146.960000 ;
+ RECT 980.520000 2950.390000 981.620000 3146.960000 ;
+ RECT 1038.330000 2949.140000 1039.330000 3149.400000 ;
+ RECT 935.520000 2950.390000 936.620000 3146.960000 ;
+ RECT 890.520000 2950.390000 891.620000 3146.960000 ;
+ RECT 845.520000 2950.390000 846.620000 3146.960000 ;
+ RECT 841.690000 2949.140000 842.690000 3149.400000 ;
+ LAYER met3 ;
+ RECT 1025.520000 3141.680000 1026.620000 3142.160000 ;
+ RECT 1038.330000 3141.680000 1039.330000 3142.160000 ;
+ RECT 1038.330000 3130.800000 1039.330000 3131.280000 ;
+ RECT 1038.330000 3125.360000 1039.330000 3125.840000 ;
+ RECT 1038.330000 3136.240000 1039.330000 3136.720000 ;
+ RECT 1025.520000 3136.240000 1026.620000 3136.720000 ;
+ RECT 1025.520000 3130.800000 1026.620000 3131.280000 ;
+ RECT 1025.520000 3125.360000 1026.620000 3125.840000 ;
+ RECT 1025.520000 3114.480000 1026.620000 3114.960000 ;
+ RECT 1025.520000 3119.920000 1026.620000 3120.400000 ;
+ RECT 1038.330000 3114.480000 1039.330000 3114.960000 ;
+ RECT 1038.330000 3119.920000 1039.330000 3120.400000 ;
+ RECT 1025.520000 3103.600000 1026.620000 3104.080000 ;
+ RECT 1025.520000 3109.040000 1026.620000 3109.520000 ;
+ RECT 1038.330000 3103.600000 1039.330000 3104.080000 ;
+ RECT 1038.330000 3109.040000 1039.330000 3109.520000 ;
+ RECT 980.520000 3125.360000 981.620000 3125.840000 ;
+ RECT 980.520000 3130.800000 981.620000 3131.280000 ;
+ RECT 980.520000 3136.240000 981.620000 3136.720000 ;
+ RECT 980.520000 3141.680000 981.620000 3142.160000 ;
+ RECT 980.520000 3109.040000 981.620000 3109.520000 ;
+ RECT 980.520000 3103.600000 981.620000 3104.080000 ;
+ RECT 980.520000 3114.480000 981.620000 3114.960000 ;
+ RECT 980.520000 3119.920000 981.620000 3120.400000 ;
+ RECT 1038.330000 3092.720000 1039.330000 3093.200000 ;
+ RECT 1038.330000 3087.280000 1039.330000 3087.760000 ;
+ RECT 1038.330000 3098.160000 1039.330000 3098.640000 ;
+ RECT 1025.520000 3098.160000 1026.620000 3098.640000 ;
+ RECT 1025.520000 3092.720000 1026.620000 3093.200000 ;
+ RECT 1025.520000 3087.280000 1026.620000 3087.760000 ;
+ RECT 1025.520000 3076.400000 1026.620000 3076.880000 ;
+ RECT 1025.520000 3081.840000 1026.620000 3082.320000 ;
+ RECT 1038.330000 3076.400000 1039.330000 3076.880000 ;
+ RECT 1038.330000 3081.840000 1039.330000 3082.320000 ;
+ RECT 1038.330000 3065.520000 1039.330000 3066.000000 ;
+ RECT 1038.330000 3070.960000 1039.330000 3071.440000 ;
+ RECT 1025.520000 3070.960000 1026.620000 3071.440000 ;
+ RECT 1025.520000 3065.520000 1026.620000 3066.000000 ;
+ RECT 1025.520000 3054.640000 1026.620000 3055.120000 ;
+ RECT 1025.520000 3060.080000 1026.620000 3060.560000 ;
+ RECT 1038.330000 3054.640000 1039.330000 3055.120000 ;
+ RECT 1038.330000 3060.080000 1039.330000 3060.560000 ;
+ RECT 980.520000 3076.400000 981.620000 3076.880000 ;
+ RECT 980.520000 3081.840000 981.620000 3082.320000 ;
+ RECT 980.520000 3087.280000 981.620000 3087.760000 ;
+ RECT 980.520000 3092.720000 981.620000 3093.200000 ;
+ RECT 980.520000 3098.160000 981.620000 3098.640000 ;
+ RECT 980.520000 3054.640000 981.620000 3055.120000 ;
+ RECT 980.520000 3060.080000 981.620000 3060.560000 ;
+ RECT 980.520000 3065.520000 981.620000 3066.000000 ;
+ RECT 980.520000 3070.960000 981.620000 3071.440000 ;
+ RECT 935.520000 3130.800000 936.620000 3131.280000 ;
+ RECT 935.520000 3125.360000 936.620000 3125.840000 ;
+ RECT 935.520000 3136.240000 936.620000 3136.720000 ;
+ RECT 935.520000 3141.680000 936.620000 3142.160000 ;
+ RECT 890.520000 3125.360000 891.620000 3125.840000 ;
+ RECT 890.520000 3130.800000 891.620000 3131.280000 ;
+ RECT 890.520000 3136.240000 891.620000 3136.720000 ;
+ RECT 890.520000 3141.680000 891.620000 3142.160000 ;
+ RECT 935.520000 3103.600000 936.620000 3104.080000 ;
+ RECT 935.520000 3109.040000 936.620000 3109.520000 ;
+ RECT 935.520000 3114.480000 936.620000 3114.960000 ;
+ RECT 935.520000 3119.920000 936.620000 3120.400000 ;
+ RECT 890.520000 3103.600000 891.620000 3104.080000 ;
+ RECT 890.520000 3109.040000 891.620000 3109.520000 ;
+ RECT 890.520000 3114.480000 891.620000 3114.960000 ;
+ RECT 890.520000 3119.920000 891.620000 3120.400000 ;
+ RECT 841.690000 3141.680000 842.690000 3142.160000 ;
+ RECT 845.355000 3141.680000 846.620000 3142.160000 ;
+ RECT 841.690000 3130.800000 842.690000 3131.280000 ;
+ RECT 845.355000 3130.800000 846.620000 3131.280000 ;
+ RECT 841.690000 3136.240000 842.690000 3136.720000 ;
+ RECT 845.355000 3136.240000 846.620000 3136.720000 ;
+ RECT 841.690000 3125.360000 842.690000 3125.840000 ;
+ RECT 845.355000 3125.360000 846.620000 3125.840000 ;
+ RECT 841.690000 3119.920000 842.690000 3120.400000 ;
+ RECT 845.355000 3119.920000 846.620000 3120.400000 ;
+ RECT 841.690000 3114.480000 842.690000 3114.960000 ;
+ RECT 845.355000 3114.480000 846.620000 3114.960000 ;
+ RECT 841.690000 3109.040000 842.690000 3109.520000 ;
+ RECT 845.355000 3109.040000 846.620000 3109.520000 ;
+ RECT 841.690000 3103.600000 842.690000 3104.080000 ;
+ RECT 845.355000 3103.600000 846.620000 3104.080000 ;
+ RECT 935.520000 3076.400000 936.620000 3076.880000 ;
+ RECT 935.520000 3081.840000 936.620000 3082.320000 ;
+ RECT 935.520000 3087.280000 936.620000 3087.760000 ;
+ RECT 935.520000 3092.720000 936.620000 3093.200000 ;
+ RECT 935.520000 3098.160000 936.620000 3098.640000 ;
+ RECT 890.520000 3076.400000 891.620000 3076.880000 ;
+ RECT 890.520000 3081.840000 891.620000 3082.320000 ;
+ RECT 890.520000 3087.280000 891.620000 3087.760000 ;
+ RECT 890.520000 3092.720000 891.620000 3093.200000 ;
+ RECT 890.520000 3098.160000 891.620000 3098.640000 ;
+ RECT 935.520000 3054.640000 936.620000 3055.120000 ;
+ RECT 935.520000 3060.080000 936.620000 3060.560000 ;
+ RECT 935.520000 3065.520000 936.620000 3066.000000 ;
+ RECT 935.520000 3070.960000 936.620000 3071.440000 ;
+ RECT 890.520000 3054.640000 891.620000 3055.120000 ;
+ RECT 890.520000 3060.080000 891.620000 3060.560000 ;
+ RECT 890.520000 3065.520000 891.620000 3066.000000 ;
+ RECT 890.520000 3070.960000 891.620000 3071.440000 ;
+ RECT 841.690000 3098.160000 842.690000 3098.640000 ;
+ RECT 845.355000 3098.160000 846.620000 3098.640000 ;
+ RECT 841.690000 3087.280000 842.690000 3087.760000 ;
+ RECT 845.355000 3087.280000 846.620000 3087.760000 ;
+ RECT 841.690000 3092.720000 842.690000 3093.200000 ;
+ RECT 845.355000 3092.720000 846.620000 3093.200000 ;
+ RECT 841.690000 3081.840000 842.690000 3082.320000 ;
+ RECT 845.355000 3081.840000 846.620000 3082.320000 ;
+ RECT 841.690000 3076.400000 842.690000 3076.880000 ;
+ RECT 845.355000 3076.400000 846.620000 3076.880000 ;
+ RECT 841.690000 3070.960000 842.690000 3071.440000 ;
+ RECT 845.355000 3070.960000 846.620000 3071.440000 ;
+ RECT 841.690000 3065.520000 842.690000 3066.000000 ;
+ RECT 845.355000 3065.520000 846.620000 3066.000000 ;
+ RECT 841.690000 3060.080000 842.690000 3060.560000 ;
+ RECT 845.355000 3060.080000 846.620000 3060.560000 ;
+ RECT 841.690000 3054.640000 842.690000 3055.120000 ;
+ RECT 845.355000 3054.640000 846.620000 3055.120000 ;
+ RECT 1025.520000 3038.320000 1026.620000 3038.800000 ;
+ RECT 1025.520000 3043.760000 1026.620000 3044.240000 ;
+ RECT 1038.330000 3038.320000 1039.330000 3038.800000 ;
+ RECT 1038.330000 3043.760000 1039.330000 3044.240000 ;
+ RECT 1038.330000 3027.440000 1039.330000 3027.920000 ;
+ RECT 1038.330000 3032.880000 1039.330000 3033.360000 ;
+ RECT 1025.520000 3032.880000 1026.620000 3033.360000 ;
+ RECT 1025.520000 3027.440000 1026.620000 3027.920000 ;
+ RECT 1025.520000 3016.560000 1026.620000 3017.040000 ;
+ RECT 1025.520000 3022.000000 1026.620000 3022.480000 ;
+ RECT 1038.330000 3016.560000 1039.330000 3017.040000 ;
+ RECT 1038.330000 3022.000000 1039.330000 3022.480000 ;
+ RECT 1038.330000 3005.680000 1039.330000 3006.160000 ;
+ RECT 1038.330000 3000.240000 1039.330000 3000.720000 ;
+ RECT 1038.330000 3011.120000 1039.330000 3011.600000 ;
+ RECT 1025.520000 3011.120000 1026.620000 3011.600000 ;
+ RECT 1025.520000 3005.680000 1026.620000 3006.160000 ;
+ RECT 1025.520000 3000.240000 1026.620000 3000.720000 ;
+ RECT 980.520000 3027.440000 981.620000 3027.920000 ;
+ RECT 980.520000 3032.880000 981.620000 3033.360000 ;
+ RECT 980.520000 3038.320000 981.620000 3038.800000 ;
+ RECT 980.520000 3043.760000 981.620000 3044.240000 ;
+ RECT 980.520000 3000.240000 981.620000 3000.720000 ;
+ RECT 980.520000 3005.680000 981.620000 3006.160000 ;
+ RECT 980.520000 3011.120000 981.620000 3011.600000 ;
+ RECT 980.520000 3016.560000 981.620000 3017.040000 ;
+ RECT 980.520000 3022.000000 981.620000 3022.480000 ;
+ RECT 1025.520000 2989.360000 1026.620000 2989.840000 ;
+ RECT 1025.520000 2994.800000 1026.620000 2995.280000 ;
+ RECT 1038.330000 2989.360000 1039.330000 2989.840000 ;
+ RECT 1038.330000 2994.800000 1039.330000 2995.280000 ;
+ RECT 1025.520000 2978.480000 1026.620000 2978.960000 ;
+ RECT 1025.520000 2983.920000 1026.620000 2984.400000 ;
+ RECT 1038.330000 2978.480000 1039.330000 2978.960000 ;
+ RECT 1038.330000 2983.920000 1039.330000 2984.400000 ;
+ RECT 1038.330000 2967.600000 1039.330000 2968.080000 ;
+ RECT 1038.330000 2962.160000 1039.330000 2962.640000 ;
+ RECT 1038.330000 2973.040000 1039.330000 2973.520000 ;
+ RECT 1025.520000 2973.040000 1026.620000 2973.520000 ;
+ RECT 1025.520000 2967.600000 1026.620000 2968.080000 ;
+ RECT 1025.520000 2962.160000 1026.620000 2962.640000 ;
+ RECT 1025.520000 2956.720000 1026.620000 2957.200000 ;
+ RECT 1038.330000 2956.720000 1039.330000 2957.200000 ;
+ RECT 980.520000 2978.480000 981.620000 2978.960000 ;
+ RECT 980.520000 2983.920000 981.620000 2984.400000 ;
+ RECT 980.520000 2989.360000 981.620000 2989.840000 ;
+ RECT 980.520000 2994.800000 981.620000 2995.280000 ;
+ RECT 980.520000 2956.720000 981.620000 2957.200000 ;
+ RECT 980.520000 2962.160000 981.620000 2962.640000 ;
+ RECT 980.520000 2967.600000 981.620000 2968.080000 ;
+ RECT 980.520000 2973.040000 981.620000 2973.520000 ;
+ RECT 935.520000 3027.440000 936.620000 3027.920000 ;
+ RECT 935.520000 3032.880000 936.620000 3033.360000 ;
+ RECT 935.520000 3038.320000 936.620000 3038.800000 ;
+ RECT 935.520000 3043.760000 936.620000 3044.240000 ;
+ RECT 890.520000 3027.440000 891.620000 3027.920000 ;
+ RECT 890.520000 3032.880000 891.620000 3033.360000 ;
+ RECT 890.520000 3038.320000 891.620000 3038.800000 ;
+ RECT 890.520000 3043.760000 891.620000 3044.240000 ;
+ RECT 935.520000 3000.240000 936.620000 3000.720000 ;
+ RECT 935.520000 3005.680000 936.620000 3006.160000 ;
+ RECT 935.520000 3011.120000 936.620000 3011.600000 ;
+ RECT 935.520000 3016.560000 936.620000 3017.040000 ;
+ RECT 935.520000 3022.000000 936.620000 3022.480000 ;
+ RECT 890.520000 3000.240000 891.620000 3000.720000 ;
+ RECT 890.520000 3005.680000 891.620000 3006.160000 ;
+ RECT 890.520000 3011.120000 891.620000 3011.600000 ;
+ RECT 890.520000 3016.560000 891.620000 3017.040000 ;
+ RECT 890.520000 3022.000000 891.620000 3022.480000 ;
+ RECT 841.690000 3043.760000 842.690000 3044.240000 ;
+ RECT 845.355000 3043.760000 846.620000 3044.240000 ;
+ RECT 841.690000 3038.320000 842.690000 3038.800000 ;
+ RECT 845.355000 3038.320000 846.620000 3038.800000 ;
+ RECT 841.690000 3032.880000 842.690000 3033.360000 ;
+ RECT 845.355000 3032.880000 846.620000 3033.360000 ;
+ RECT 841.690000 3027.440000 842.690000 3027.920000 ;
+ RECT 845.355000 3027.440000 846.620000 3027.920000 ;
+ RECT 841.690000 3022.000000 842.690000 3022.480000 ;
+ RECT 845.355000 3022.000000 846.620000 3022.480000 ;
+ RECT 841.690000 3016.560000 842.690000 3017.040000 ;
+ RECT 845.355000 3016.560000 846.620000 3017.040000 ;
+ RECT 841.690000 3005.680000 842.690000 3006.160000 ;
+ RECT 845.355000 3005.680000 846.620000 3006.160000 ;
+ RECT 841.690000 3011.120000 842.690000 3011.600000 ;
+ RECT 845.355000 3011.120000 846.620000 3011.600000 ;
+ RECT 841.690000 3000.240000 842.690000 3000.720000 ;
+ RECT 845.355000 3000.240000 846.620000 3000.720000 ;
+ RECT 935.520000 2978.480000 936.620000 2978.960000 ;
+ RECT 935.520000 2983.920000 936.620000 2984.400000 ;
+ RECT 935.520000 2989.360000 936.620000 2989.840000 ;
+ RECT 935.520000 2994.800000 936.620000 2995.280000 ;
+ RECT 890.520000 2978.480000 891.620000 2978.960000 ;
+ RECT 890.520000 2983.920000 891.620000 2984.400000 ;
+ RECT 890.520000 2989.360000 891.620000 2989.840000 ;
+ RECT 890.520000 2994.800000 891.620000 2995.280000 ;
+ RECT 935.520000 2956.720000 936.620000 2957.200000 ;
+ RECT 935.520000 2962.160000 936.620000 2962.640000 ;
+ RECT 935.520000 2967.600000 936.620000 2968.080000 ;
+ RECT 935.520000 2973.040000 936.620000 2973.520000 ;
+ RECT 890.520000 2956.720000 891.620000 2957.200000 ;
+ RECT 890.520000 2962.160000 891.620000 2962.640000 ;
+ RECT 890.520000 2967.600000 891.620000 2968.080000 ;
+ RECT 890.520000 2973.040000 891.620000 2973.520000 ;
+ RECT 841.690000 2994.800000 842.690000 2995.280000 ;
+ RECT 845.355000 2994.800000 846.620000 2995.280000 ;
+ RECT 841.690000 2989.360000 842.690000 2989.840000 ;
+ RECT 845.355000 2989.360000 846.620000 2989.840000 ;
+ RECT 841.690000 2983.920000 842.690000 2984.400000 ;
+ RECT 845.355000 2983.920000 846.620000 2984.400000 ;
+ RECT 841.690000 2978.480000 842.690000 2978.960000 ;
+ RECT 845.355000 2978.480000 846.620000 2978.960000 ;
+ RECT 841.690000 2973.040000 842.690000 2973.520000 ;
+ RECT 845.355000 2973.040000 846.620000 2973.520000 ;
+ RECT 841.690000 2962.160000 842.690000 2962.640000 ;
+ RECT 845.355000 2962.160000 846.620000 2962.640000 ;
+ RECT 841.690000 2967.600000 842.690000 2968.080000 ;
+ RECT 845.355000 2967.600000 846.620000 2968.080000 ;
+ RECT 841.690000 2956.720000 842.690000 2957.200000 ;
+ RECT 845.355000 2956.720000 846.620000 2957.200000 ;
+ RECT 980.520000 3049.200000 981.620000 3049.680000 ;
+ RECT 1025.520000 3049.200000 1026.620000 3049.680000 ;
+ RECT 1038.330000 3049.200000 1039.330000 3049.680000 ;
+ RECT 890.520000 3049.200000 891.620000 3049.680000 ;
+ RECT 935.520000 3049.200000 936.620000 3049.680000 ;
+ RECT 841.690000 3049.200000 842.690000 3049.680000 ;
+ RECT 845.355000 3049.200000 846.620000 3049.680000 ;
+ RECT 840.460000 3145.960000 1040.560000 3146.960000 ;
+ RECT 840.460000 2950.390000 1040.560000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 2949.140000 842.690000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 3148.400000 842.690000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 2949.140000 1039.330000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 3148.400000 1039.330000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2950.390000 841.460000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2950.390000 1040.560000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 3145.960000 841.460000 3146.960000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 3145.960000 1040.560000 3146.960000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 2941.420000 846.620000 2941.900000 ;
+ RECT 845.355000 2930.540000 846.620000 2931.020000 ;
+ RECT 845.355000 2935.980000 846.620000 2936.460000 ;
+ RECT 845.355000 2925.100000 846.620000 2925.580000 ;
+ RECT 845.355000 2919.660000 846.620000 2920.140000 ;
+ RECT 845.355000 2914.220000 846.620000 2914.700000 ;
+ RECT 845.355000 2908.780000 846.620000 2909.260000 ;
+ RECT 845.355000 2903.340000 846.620000 2903.820000 ;
+ RECT 845.355000 2897.900000 846.620000 2898.380000 ;
+ RECT 845.355000 2887.020000 846.620000 2887.500000 ;
+ RECT 845.355000 2892.460000 846.620000 2892.940000 ;
+ RECT 845.355000 2881.580000 846.620000 2882.060000 ;
+ RECT 845.355000 2876.140000 846.620000 2876.620000 ;
+ RECT 845.355000 2870.700000 846.620000 2871.180000 ;
+ RECT 845.355000 2865.260000 846.620000 2865.740000 ;
+ RECT 845.355000 2859.820000 846.620000 2860.300000 ;
+ RECT 845.355000 2854.380000 846.620000 2854.860000 ;
+ RECT 845.355000 2843.500000 846.620000 2843.980000 ;
+ RECT 845.355000 2838.060000 846.620000 2838.540000 ;
+ RECT 845.355000 2832.620000 846.620000 2833.100000 ;
+ RECT 845.355000 2827.180000 846.620000 2827.660000 ;
+ RECT 845.355000 2821.740000 846.620000 2822.220000 ;
+ RECT 845.355000 2816.300000 846.620000 2816.780000 ;
+ RECT 845.355000 2805.420000 846.620000 2805.900000 ;
+ RECT 845.355000 2810.860000 846.620000 2811.340000 ;
+ RECT 845.355000 2799.980000 846.620000 2800.460000 ;
+ RECT 845.355000 2794.540000 846.620000 2795.020000 ;
+ RECT 845.355000 2789.100000 846.620000 2789.580000 ;
+ RECT 845.355000 2783.660000 846.620000 2784.140000 ;
+ RECT 845.355000 2778.220000 846.620000 2778.700000 ;
+ RECT 845.355000 2772.780000 846.620000 2773.260000 ;
+ RECT 845.355000 2761.900000 846.620000 2762.380000 ;
+ RECT 845.355000 2767.340000 846.620000 2767.820000 ;
+ RECT 845.355000 2756.460000 846.620000 2756.940000 ;
+ RECT 845.355000 2848.940000 846.620000 2849.420000 ;
+ RECT 1025.520000 2750.130000 1026.620000 2946.700000 ;
+ RECT 980.520000 2750.130000 981.620000 2946.700000 ;
+ RECT 1038.330000 2748.880000 1039.330000 2949.140000 ;
+ RECT 935.520000 2750.130000 936.620000 2946.700000 ;
+ RECT 890.520000 2750.130000 891.620000 2946.700000 ;
+ RECT 845.520000 2750.130000 846.620000 2946.700000 ;
+ RECT 841.690000 2748.880000 842.690000 2949.140000 ;
+ LAYER met3 ;
+ RECT 1025.520000 2941.420000 1026.620000 2941.900000 ;
+ RECT 1038.330000 2941.420000 1039.330000 2941.900000 ;
+ RECT 1038.330000 2930.540000 1039.330000 2931.020000 ;
+ RECT 1038.330000 2925.100000 1039.330000 2925.580000 ;
+ RECT 1038.330000 2935.980000 1039.330000 2936.460000 ;
+ RECT 1025.520000 2935.980000 1026.620000 2936.460000 ;
+ RECT 1025.520000 2930.540000 1026.620000 2931.020000 ;
+ RECT 1025.520000 2925.100000 1026.620000 2925.580000 ;
+ RECT 1025.520000 2914.220000 1026.620000 2914.700000 ;
+ RECT 1025.520000 2919.660000 1026.620000 2920.140000 ;
+ RECT 1038.330000 2914.220000 1039.330000 2914.700000 ;
+ RECT 1038.330000 2919.660000 1039.330000 2920.140000 ;
+ RECT 1025.520000 2903.340000 1026.620000 2903.820000 ;
+ RECT 1025.520000 2908.780000 1026.620000 2909.260000 ;
+ RECT 1038.330000 2903.340000 1039.330000 2903.820000 ;
+ RECT 1038.330000 2908.780000 1039.330000 2909.260000 ;
+ RECT 980.520000 2925.100000 981.620000 2925.580000 ;
+ RECT 980.520000 2930.540000 981.620000 2931.020000 ;
+ RECT 980.520000 2935.980000 981.620000 2936.460000 ;
+ RECT 980.520000 2941.420000 981.620000 2941.900000 ;
+ RECT 980.520000 2908.780000 981.620000 2909.260000 ;
+ RECT 980.520000 2903.340000 981.620000 2903.820000 ;
+ RECT 980.520000 2914.220000 981.620000 2914.700000 ;
+ RECT 980.520000 2919.660000 981.620000 2920.140000 ;
+ RECT 1038.330000 2892.460000 1039.330000 2892.940000 ;
+ RECT 1038.330000 2887.020000 1039.330000 2887.500000 ;
+ RECT 1038.330000 2897.900000 1039.330000 2898.380000 ;
+ RECT 1025.520000 2897.900000 1026.620000 2898.380000 ;
+ RECT 1025.520000 2892.460000 1026.620000 2892.940000 ;
+ RECT 1025.520000 2887.020000 1026.620000 2887.500000 ;
+ RECT 1025.520000 2876.140000 1026.620000 2876.620000 ;
+ RECT 1025.520000 2881.580000 1026.620000 2882.060000 ;
+ RECT 1038.330000 2876.140000 1039.330000 2876.620000 ;
+ RECT 1038.330000 2881.580000 1039.330000 2882.060000 ;
+ RECT 1038.330000 2865.260000 1039.330000 2865.740000 ;
+ RECT 1038.330000 2870.700000 1039.330000 2871.180000 ;
+ RECT 1025.520000 2870.700000 1026.620000 2871.180000 ;
+ RECT 1025.520000 2865.260000 1026.620000 2865.740000 ;
+ RECT 1025.520000 2854.380000 1026.620000 2854.860000 ;
+ RECT 1025.520000 2859.820000 1026.620000 2860.300000 ;
+ RECT 1038.330000 2854.380000 1039.330000 2854.860000 ;
+ RECT 1038.330000 2859.820000 1039.330000 2860.300000 ;
+ RECT 980.520000 2876.140000 981.620000 2876.620000 ;
+ RECT 980.520000 2881.580000 981.620000 2882.060000 ;
+ RECT 980.520000 2887.020000 981.620000 2887.500000 ;
+ RECT 980.520000 2892.460000 981.620000 2892.940000 ;
+ RECT 980.520000 2897.900000 981.620000 2898.380000 ;
+ RECT 980.520000 2854.380000 981.620000 2854.860000 ;
+ RECT 980.520000 2859.820000 981.620000 2860.300000 ;
+ RECT 980.520000 2865.260000 981.620000 2865.740000 ;
+ RECT 980.520000 2870.700000 981.620000 2871.180000 ;
+ RECT 935.520000 2930.540000 936.620000 2931.020000 ;
+ RECT 935.520000 2925.100000 936.620000 2925.580000 ;
+ RECT 935.520000 2935.980000 936.620000 2936.460000 ;
+ RECT 935.520000 2941.420000 936.620000 2941.900000 ;
+ RECT 890.520000 2925.100000 891.620000 2925.580000 ;
+ RECT 890.520000 2930.540000 891.620000 2931.020000 ;
+ RECT 890.520000 2935.980000 891.620000 2936.460000 ;
+ RECT 890.520000 2941.420000 891.620000 2941.900000 ;
+ RECT 935.520000 2903.340000 936.620000 2903.820000 ;
+ RECT 935.520000 2908.780000 936.620000 2909.260000 ;
+ RECT 935.520000 2914.220000 936.620000 2914.700000 ;
+ RECT 935.520000 2919.660000 936.620000 2920.140000 ;
+ RECT 890.520000 2903.340000 891.620000 2903.820000 ;
+ RECT 890.520000 2908.780000 891.620000 2909.260000 ;
+ RECT 890.520000 2914.220000 891.620000 2914.700000 ;
+ RECT 890.520000 2919.660000 891.620000 2920.140000 ;
+ RECT 841.690000 2941.420000 842.690000 2941.900000 ;
+ RECT 845.355000 2941.420000 846.620000 2941.900000 ;
+ RECT 841.690000 2930.540000 842.690000 2931.020000 ;
+ RECT 845.355000 2930.540000 846.620000 2931.020000 ;
+ RECT 841.690000 2935.980000 842.690000 2936.460000 ;
+ RECT 845.355000 2935.980000 846.620000 2936.460000 ;
+ RECT 841.690000 2925.100000 842.690000 2925.580000 ;
+ RECT 845.355000 2925.100000 846.620000 2925.580000 ;
+ RECT 841.690000 2919.660000 842.690000 2920.140000 ;
+ RECT 845.355000 2919.660000 846.620000 2920.140000 ;
+ RECT 841.690000 2914.220000 842.690000 2914.700000 ;
+ RECT 845.355000 2914.220000 846.620000 2914.700000 ;
+ RECT 841.690000 2908.780000 842.690000 2909.260000 ;
+ RECT 845.355000 2908.780000 846.620000 2909.260000 ;
+ RECT 841.690000 2903.340000 842.690000 2903.820000 ;
+ RECT 845.355000 2903.340000 846.620000 2903.820000 ;
+ RECT 935.520000 2876.140000 936.620000 2876.620000 ;
+ RECT 935.520000 2881.580000 936.620000 2882.060000 ;
+ RECT 935.520000 2887.020000 936.620000 2887.500000 ;
+ RECT 935.520000 2892.460000 936.620000 2892.940000 ;
+ RECT 935.520000 2897.900000 936.620000 2898.380000 ;
+ RECT 890.520000 2876.140000 891.620000 2876.620000 ;
+ RECT 890.520000 2881.580000 891.620000 2882.060000 ;
+ RECT 890.520000 2887.020000 891.620000 2887.500000 ;
+ RECT 890.520000 2892.460000 891.620000 2892.940000 ;
+ RECT 890.520000 2897.900000 891.620000 2898.380000 ;
+ RECT 935.520000 2854.380000 936.620000 2854.860000 ;
+ RECT 935.520000 2859.820000 936.620000 2860.300000 ;
+ RECT 935.520000 2865.260000 936.620000 2865.740000 ;
+ RECT 935.520000 2870.700000 936.620000 2871.180000 ;
+ RECT 890.520000 2854.380000 891.620000 2854.860000 ;
+ RECT 890.520000 2859.820000 891.620000 2860.300000 ;
+ RECT 890.520000 2865.260000 891.620000 2865.740000 ;
+ RECT 890.520000 2870.700000 891.620000 2871.180000 ;
+ RECT 841.690000 2897.900000 842.690000 2898.380000 ;
+ RECT 845.355000 2897.900000 846.620000 2898.380000 ;
+ RECT 841.690000 2887.020000 842.690000 2887.500000 ;
+ RECT 845.355000 2887.020000 846.620000 2887.500000 ;
+ RECT 841.690000 2892.460000 842.690000 2892.940000 ;
+ RECT 845.355000 2892.460000 846.620000 2892.940000 ;
+ RECT 841.690000 2881.580000 842.690000 2882.060000 ;
+ RECT 845.355000 2881.580000 846.620000 2882.060000 ;
+ RECT 841.690000 2876.140000 842.690000 2876.620000 ;
+ RECT 845.355000 2876.140000 846.620000 2876.620000 ;
+ RECT 841.690000 2870.700000 842.690000 2871.180000 ;
+ RECT 845.355000 2870.700000 846.620000 2871.180000 ;
+ RECT 841.690000 2865.260000 842.690000 2865.740000 ;
+ RECT 845.355000 2865.260000 846.620000 2865.740000 ;
+ RECT 841.690000 2859.820000 842.690000 2860.300000 ;
+ RECT 845.355000 2859.820000 846.620000 2860.300000 ;
+ RECT 841.690000 2854.380000 842.690000 2854.860000 ;
+ RECT 845.355000 2854.380000 846.620000 2854.860000 ;
+ RECT 1025.520000 2838.060000 1026.620000 2838.540000 ;
+ RECT 1025.520000 2843.500000 1026.620000 2843.980000 ;
+ RECT 1038.330000 2838.060000 1039.330000 2838.540000 ;
+ RECT 1038.330000 2843.500000 1039.330000 2843.980000 ;
+ RECT 1038.330000 2827.180000 1039.330000 2827.660000 ;
+ RECT 1038.330000 2832.620000 1039.330000 2833.100000 ;
+ RECT 1025.520000 2832.620000 1026.620000 2833.100000 ;
+ RECT 1025.520000 2827.180000 1026.620000 2827.660000 ;
+ RECT 1025.520000 2816.300000 1026.620000 2816.780000 ;
+ RECT 1025.520000 2821.740000 1026.620000 2822.220000 ;
+ RECT 1038.330000 2816.300000 1039.330000 2816.780000 ;
+ RECT 1038.330000 2821.740000 1039.330000 2822.220000 ;
+ RECT 1038.330000 2805.420000 1039.330000 2805.900000 ;
+ RECT 1038.330000 2799.980000 1039.330000 2800.460000 ;
+ RECT 1038.330000 2810.860000 1039.330000 2811.340000 ;
+ RECT 1025.520000 2810.860000 1026.620000 2811.340000 ;
+ RECT 1025.520000 2805.420000 1026.620000 2805.900000 ;
+ RECT 1025.520000 2799.980000 1026.620000 2800.460000 ;
+ RECT 980.520000 2827.180000 981.620000 2827.660000 ;
+ RECT 980.520000 2832.620000 981.620000 2833.100000 ;
+ RECT 980.520000 2838.060000 981.620000 2838.540000 ;
+ RECT 980.520000 2843.500000 981.620000 2843.980000 ;
+ RECT 980.520000 2799.980000 981.620000 2800.460000 ;
+ RECT 980.520000 2805.420000 981.620000 2805.900000 ;
+ RECT 980.520000 2810.860000 981.620000 2811.340000 ;
+ RECT 980.520000 2816.300000 981.620000 2816.780000 ;
+ RECT 980.520000 2821.740000 981.620000 2822.220000 ;
+ RECT 1025.520000 2789.100000 1026.620000 2789.580000 ;
+ RECT 1025.520000 2794.540000 1026.620000 2795.020000 ;
+ RECT 1038.330000 2789.100000 1039.330000 2789.580000 ;
+ RECT 1038.330000 2794.540000 1039.330000 2795.020000 ;
+ RECT 1025.520000 2778.220000 1026.620000 2778.700000 ;
+ RECT 1025.520000 2783.660000 1026.620000 2784.140000 ;
+ RECT 1038.330000 2778.220000 1039.330000 2778.700000 ;
+ RECT 1038.330000 2783.660000 1039.330000 2784.140000 ;
+ RECT 1038.330000 2767.340000 1039.330000 2767.820000 ;
+ RECT 1038.330000 2761.900000 1039.330000 2762.380000 ;
+ RECT 1038.330000 2772.780000 1039.330000 2773.260000 ;
+ RECT 1025.520000 2772.780000 1026.620000 2773.260000 ;
+ RECT 1025.520000 2767.340000 1026.620000 2767.820000 ;
+ RECT 1025.520000 2761.900000 1026.620000 2762.380000 ;
+ RECT 1025.520000 2756.460000 1026.620000 2756.940000 ;
+ RECT 1038.330000 2756.460000 1039.330000 2756.940000 ;
+ RECT 980.520000 2778.220000 981.620000 2778.700000 ;
+ RECT 980.520000 2783.660000 981.620000 2784.140000 ;
+ RECT 980.520000 2789.100000 981.620000 2789.580000 ;
+ RECT 980.520000 2794.540000 981.620000 2795.020000 ;
+ RECT 980.520000 2756.460000 981.620000 2756.940000 ;
+ RECT 980.520000 2761.900000 981.620000 2762.380000 ;
+ RECT 980.520000 2767.340000 981.620000 2767.820000 ;
+ RECT 980.520000 2772.780000 981.620000 2773.260000 ;
+ RECT 935.520000 2827.180000 936.620000 2827.660000 ;
+ RECT 935.520000 2832.620000 936.620000 2833.100000 ;
+ RECT 935.520000 2838.060000 936.620000 2838.540000 ;
+ RECT 935.520000 2843.500000 936.620000 2843.980000 ;
+ RECT 890.520000 2827.180000 891.620000 2827.660000 ;
+ RECT 890.520000 2832.620000 891.620000 2833.100000 ;
+ RECT 890.520000 2838.060000 891.620000 2838.540000 ;
+ RECT 890.520000 2843.500000 891.620000 2843.980000 ;
+ RECT 935.520000 2799.980000 936.620000 2800.460000 ;
+ RECT 935.520000 2805.420000 936.620000 2805.900000 ;
+ RECT 935.520000 2810.860000 936.620000 2811.340000 ;
+ RECT 935.520000 2816.300000 936.620000 2816.780000 ;
+ RECT 935.520000 2821.740000 936.620000 2822.220000 ;
+ RECT 890.520000 2799.980000 891.620000 2800.460000 ;
+ RECT 890.520000 2805.420000 891.620000 2805.900000 ;
+ RECT 890.520000 2810.860000 891.620000 2811.340000 ;
+ RECT 890.520000 2816.300000 891.620000 2816.780000 ;
+ RECT 890.520000 2821.740000 891.620000 2822.220000 ;
+ RECT 841.690000 2843.500000 842.690000 2843.980000 ;
+ RECT 845.355000 2843.500000 846.620000 2843.980000 ;
+ RECT 841.690000 2838.060000 842.690000 2838.540000 ;
+ RECT 845.355000 2838.060000 846.620000 2838.540000 ;
+ RECT 841.690000 2832.620000 842.690000 2833.100000 ;
+ RECT 845.355000 2832.620000 846.620000 2833.100000 ;
+ RECT 841.690000 2827.180000 842.690000 2827.660000 ;
+ RECT 845.355000 2827.180000 846.620000 2827.660000 ;
+ RECT 841.690000 2821.740000 842.690000 2822.220000 ;
+ RECT 845.355000 2821.740000 846.620000 2822.220000 ;
+ RECT 841.690000 2816.300000 842.690000 2816.780000 ;
+ RECT 845.355000 2816.300000 846.620000 2816.780000 ;
+ RECT 841.690000 2805.420000 842.690000 2805.900000 ;
+ RECT 845.355000 2805.420000 846.620000 2805.900000 ;
+ RECT 841.690000 2810.860000 842.690000 2811.340000 ;
+ RECT 845.355000 2810.860000 846.620000 2811.340000 ;
+ RECT 841.690000 2799.980000 842.690000 2800.460000 ;
+ RECT 845.355000 2799.980000 846.620000 2800.460000 ;
+ RECT 935.520000 2778.220000 936.620000 2778.700000 ;
+ RECT 935.520000 2783.660000 936.620000 2784.140000 ;
+ RECT 935.520000 2789.100000 936.620000 2789.580000 ;
+ RECT 935.520000 2794.540000 936.620000 2795.020000 ;
+ RECT 890.520000 2778.220000 891.620000 2778.700000 ;
+ RECT 890.520000 2783.660000 891.620000 2784.140000 ;
+ RECT 890.520000 2789.100000 891.620000 2789.580000 ;
+ RECT 890.520000 2794.540000 891.620000 2795.020000 ;
+ RECT 935.520000 2756.460000 936.620000 2756.940000 ;
+ RECT 935.520000 2761.900000 936.620000 2762.380000 ;
+ RECT 935.520000 2767.340000 936.620000 2767.820000 ;
+ RECT 935.520000 2772.780000 936.620000 2773.260000 ;
+ RECT 890.520000 2756.460000 891.620000 2756.940000 ;
+ RECT 890.520000 2761.900000 891.620000 2762.380000 ;
+ RECT 890.520000 2767.340000 891.620000 2767.820000 ;
+ RECT 890.520000 2772.780000 891.620000 2773.260000 ;
+ RECT 841.690000 2794.540000 842.690000 2795.020000 ;
+ RECT 845.355000 2794.540000 846.620000 2795.020000 ;
+ RECT 841.690000 2789.100000 842.690000 2789.580000 ;
+ RECT 845.355000 2789.100000 846.620000 2789.580000 ;
+ RECT 841.690000 2783.660000 842.690000 2784.140000 ;
+ RECT 845.355000 2783.660000 846.620000 2784.140000 ;
+ RECT 841.690000 2778.220000 842.690000 2778.700000 ;
+ RECT 845.355000 2778.220000 846.620000 2778.700000 ;
+ RECT 841.690000 2772.780000 842.690000 2773.260000 ;
+ RECT 845.355000 2772.780000 846.620000 2773.260000 ;
+ RECT 841.690000 2761.900000 842.690000 2762.380000 ;
+ RECT 845.355000 2761.900000 846.620000 2762.380000 ;
+ RECT 841.690000 2767.340000 842.690000 2767.820000 ;
+ RECT 845.355000 2767.340000 846.620000 2767.820000 ;
+ RECT 841.690000 2756.460000 842.690000 2756.940000 ;
+ RECT 845.355000 2756.460000 846.620000 2756.940000 ;
+ RECT 980.520000 2848.940000 981.620000 2849.420000 ;
+ RECT 1025.520000 2848.940000 1026.620000 2849.420000 ;
+ RECT 1038.330000 2848.940000 1039.330000 2849.420000 ;
+ RECT 890.520000 2848.940000 891.620000 2849.420000 ;
+ RECT 935.520000 2848.940000 936.620000 2849.420000 ;
+ RECT 841.690000 2848.940000 842.690000 2849.420000 ;
+ RECT 845.355000 2848.940000 846.620000 2849.420000 ;
+ RECT 840.460000 2945.700000 1040.560000 2946.700000 ;
+ RECT 840.460000 2750.130000 1040.560000 2751.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 2748.880000 842.690000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 2948.140000 842.690000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 2748.880000 1039.330000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 2948.140000 1039.330000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2750.130000 841.460000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2750.130000 1040.560000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2945.700000 841.460000 2946.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2945.700000 1040.560000 2946.700000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 2741.160000 846.620000 2741.640000 ;
+ RECT 845.355000 2730.280000 846.620000 2730.760000 ;
+ RECT 845.355000 2735.720000 846.620000 2736.200000 ;
+ RECT 845.355000 2724.840000 846.620000 2725.320000 ;
+ RECT 845.355000 2719.400000 846.620000 2719.880000 ;
+ RECT 845.355000 2713.960000 846.620000 2714.440000 ;
+ RECT 845.355000 2708.520000 846.620000 2709.000000 ;
+ RECT 845.355000 2703.080000 846.620000 2703.560000 ;
+ RECT 845.355000 2697.640000 846.620000 2698.120000 ;
+ RECT 845.355000 2686.760000 846.620000 2687.240000 ;
+ RECT 845.355000 2692.200000 846.620000 2692.680000 ;
+ RECT 845.355000 2681.320000 846.620000 2681.800000 ;
+ RECT 845.355000 2675.880000 846.620000 2676.360000 ;
+ RECT 845.355000 2670.440000 846.620000 2670.920000 ;
+ RECT 845.355000 2665.000000 846.620000 2665.480000 ;
+ RECT 845.355000 2659.560000 846.620000 2660.040000 ;
+ RECT 845.355000 2654.120000 846.620000 2654.600000 ;
+ RECT 845.355000 2643.240000 846.620000 2643.720000 ;
+ RECT 845.355000 2637.800000 846.620000 2638.280000 ;
+ RECT 845.355000 2632.360000 846.620000 2632.840000 ;
+ RECT 845.355000 2626.920000 846.620000 2627.400000 ;
+ RECT 845.355000 2621.480000 846.620000 2621.960000 ;
+ RECT 845.355000 2616.040000 846.620000 2616.520000 ;
+ RECT 845.355000 2605.160000 846.620000 2605.640000 ;
+ RECT 845.355000 2610.600000 846.620000 2611.080000 ;
+ RECT 845.355000 2599.720000 846.620000 2600.200000 ;
+ RECT 845.355000 2594.280000 846.620000 2594.760000 ;
+ RECT 845.355000 2588.840000 846.620000 2589.320000 ;
+ RECT 845.355000 2583.400000 846.620000 2583.880000 ;
+ RECT 845.355000 2577.960000 846.620000 2578.440000 ;
+ RECT 845.355000 2572.520000 846.620000 2573.000000 ;
+ RECT 845.355000 2561.640000 846.620000 2562.120000 ;
+ RECT 845.355000 2567.080000 846.620000 2567.560000 ;
+ RECT 845.355000 2556.200000 846.620000 2556.680000 ;
+ RECT 845.355000 2648.680000 846.620000 2649.160000 ;
+ RECT 1025.520000 2549.870000 1026.620000 2746.440000 ;
+ RECT 980.520000 2549.870000 981.620000 2746.440000 ;
+ RECT 1038.330000 2548.620000 1039.330000 2748.880000 ;
+ RECT 935.520000 2549.870000 936.620000 2746.440000 ;
+ RECT 890.520000 2549.870000 891.620000 2746.440000 ;
+ RECT 845.520000 2549.870000 846.620000 2746.440000 ;
+ RECT 841.690000 2548.620000 842.690000 2748.880000 ;
+ LAYER met3 ;
+ RECT 1025.520000 2741.160000 1026.620000 2741.640000 ;
+ RECT 1038.330000 2741.160000 1039.330000 2741.640000 ;
+ RECT 1038.330000 2730.280000 1039.330000 2730.760000 ;
+ RECT 1038.330000 2724.840000 1039.330000 2725.320000 ;
+ RECT 1038.330000 2735.720000 1039.330000 2736.200000 ;
+ RECT 1025.520000 2735.720000 1026.620000 2736.200000 ;
+ RECT 1025.520000 2730.280000 1026.620000 2730.760000 ;
+ RECT 1025.520000 2724.840000 1026.620000 2725.320000 ;
+ RECT 1025.520000 2713.960000 1026.620000 2714.440000 ;
+ RECT 1025.520000 2719.400000 1026.620000 2719.880000 ;
+ RECT 1038.330000 2713.960000 1039.330000 2714.440000 ;
+ RECT 1038.330000 2719.400000 1039.330000 2719.880000 ;
+ RECT 1025.520000 2703.080000 1026.620000 2703.560000 ;
+ RECT 1025.520000 2708.520000 1026.620000 2709.000000 ;
+ RECT 1038.330000 2703.080000 1039.330000 2703.560000 ;
+ RECT 1038.330000 2708.520000 1039.330000 2709.000000 ;
+ RECT 980.520000 2724.840000 981.620000 2725.320000 ;
+ RECT 980.520000 2730.280000 981.620000 2730.760000 ;
+ RECT 980.520000 2735.720000 981.620000 2736.200000 ;
+ RECT 980.520000 2741.160000 981.620000 2741.640000 ;
+ RECT 980.520000 2708.520000 981.620000 2709.000000 ;
+ RECT 980.520000 2703.080000 981.620000 2703.560000 ;
+ RECT 980.520000 2713.960000 981.620000 2714.440000 ;
+ RECT 980.520000 2719.400000 981.620000 2719.880000 ;
+ RECT 1038.330000 2692.200000 1039.330000 2692.680000 ;
+ RECT 1038.330000 2686.760000 1039.330000 2687.240000 ;
+ RECT 1038.330000 2697.640000 1039.330000 2698.120000 ;
+ RECT 1025.520000 2697.640000 1026.620000 2698.120000 ;
+ RECT 1025.520000 2692.200000 1026.620000 2692.680000 ;
+ RECT 1025.520000 2686.760000 1026.620000 2687.240000 ;
+ RECT 1025.520000 2675.880000 1026.620000 2676.360000 ;
+ RECT 1025.520000 2681.320000 1026.620000 2681.800000 ;
+ RECT 1038.330000 2675.880000 1039.330000 2676.360000 ;
+ RECT 1038.330000 2681.320000 1039.330000 2681.800000 ;
+ RECT 1038.330000 2665.000000 1039.330000 2665.480000 ;
+ RECT 1038.330000 2670.440000 1039.330000 2670.920000 ;
+ RECT 1025.520000 2670.440000 1026.620000 2670.920000 ;
+ RECT 1025.520000 2665.000000 1026.620000 2665.480000 ;
+ RECT 1025.520000 2654.120000 1026.620000 2654.600000 ;
+ RECT 1025.520000 2659.560000 1026.620000 2660.040000 ;
+ RECT 1038.330000 2654.120000 1039.330000 2654.600000 ;
+ RECT 1038.330000 2659.560000 1039.330000 2660.040000 ;
+ RECT 980.520000 2675.880000 981.620000 2676.360000 ;
+ RECT 980.520000 2681.320000 981.620000 2681.800000 ;
+ RECT 980.520000 2686.760000 981.620000 2687.240000 ;
+ RECT 980.520000 2692.200000 981.620000 2692.680000 ;
+ RECT 980.520000 2697.640000 981.620000 2698.120000 ;
+ RECT 980.520000 2654.120000 981.620000 2654.600000 ;
+ RECT 980.520000 2659.560000 981.620000 2660.040000 ;
+ RECT 980.520000 2665.000000 981.620000 2665.480000 ;
+ RECT 980.520000 2670.440000 981.620000 2670.920000 ;
+ RECT 935.520000 2730.280000 936.620000 2730.760000 ;
+ RECT 935.520000 2724.840000 936.620000 2725.320000 ;
+ RECT 935.520000 2735.720000 936.620000 2736.200000 ;
+ RECT 935.520000 2741.160000 936.620000 2741.640000 ;
+ RECT 890.520000 2724.840000 891.620000 2725.320000 ;
+ RECT 890.520000 2730.280000 891.620000 2730.760000 ;
+ RECT 890.520000 2735.720000 891.620000 2736.200000 ;
+ RECT 890.520000 2741.160000 891.620000 2741.640000 ;
+ RECT 935.520000 2703.080000 936.620000 2703.560000 ;
+ RECT 935.520000 2708.520000 936.620000 2709.000000 ;
+ RECT 935.520000 2713.960000 936.620000 2714.440000 ;
+ RECT 935.520000 2719.400000 936.620000 2719.880000 ;
+ RECT 890.520000 2703.080000 891.620000 2703.560000 ;
+ RECT 890.520000 2708.520000 891.620000 2709.000000 ;
+ RECT 890.520000 2713.960000 891.620000 2714.440000 ;
+ RECT 890.520000 2719.400000 891.620000 2719.880000 ;
+ RECT 841.690000 2741.160000 842.690000 2741.640000 ;
+ RECT 845.355000 2741.160000 846.620000 2741.640000 ;
+ RECT 841.690000 2730.280000 842.690000 2730.760000 ;
+ RECT 845.355000 2730.280000 846.620000 2730.760000 ;
+ RECT 841.690000 2735.720000 842.690000 2736.200000 ;
+ RECT 845.355000 2735.720000 846.620000 2736.200000 ;
+ RECT 841.690000 2724.840000 842.690000 2725.320000 ;
+ RECT 845.355000 2724.840000 846.620000 2725.320000 ;
+ RECT 841.690000 2719.400000 842.690000 2719.880000 ;
+ RECT 845.355000 2719.400000 846.620000 2719.880000 ;
+ RECT 841.690000 2713.960000 842.690000 2714.440000 ;
+ RECT 845.355000 2713.960000 846.620000 2714.440000 ;
+ RECT 841.690000 2708.520000 842.690000 2709.000000 ;
+ RECT 845.355000 2708.520000 846.620000 2709.000000 ;
+ RECT 841.690000 2703.080000 842.690000 2703.560000 ;
+ RECT 845.355000 2703.080000 846.620000 2703.560000 ;
+ RECT 935.520000 2675.880000 936.620000 2676.360000 ;
+ RECT 935.520000 2681.320000 936.620000 2681.800000 ;
+ RECT 935.520000 2686.760000 936.620000 2687.240000 ;
+ RECT 935.520000 2692.200000 936.620000 2692.680000 ;
+ RECT 935.520000 2697.640000 936.620000 2698.120000 ;
+ RECT 890.520000 2675.880000 891.620000 2676.360000 ;
+ RECT 890.520000 2681.320000 891.620000 2681.800000 ;
+ RECT 890.520000 2686.760000 891.620000 2687.240000 ;
+ RECT 890.520000 2692.200000 891.620000 2692.680000 ;
+ RECT 890.520000 2697.640000 891.620000 2698.120000 ;
+ RECT 935.520000 2654.120000 936.620000 2654.600000 ;
+ RECT 935.520000 2659.560000 936.620000 2660.040000 ;
+ RECT 935.520000 2665.000000 936.620000 2665.480000 ;
+ RECT 935.520000 2670.440000 936.620000 2670.920000 ;
+ RECT 890.520000 2654.120000 891.620000 2654.600000 ;
+ RECT 890.520000 2659.560000 891.620000 2660.040000 ;
+ RECT 890.520000 2665.000000 891.620000 2665.480000 ;
+ RECT 890.520000 2670.440000 891.620000 2670.920000 ;
+ RECT 841.690000 2697.640000 842.690000 2698.120000 ;
+ RECT 845.355000 2697.640000 846.620000 2698.120000 ;
+ RECT 841.690000 2686.760000 842.690000 2687.240000 ;
+ RECT 845.355000 2686.760000 846.620000 2687.240000 ;
+ RECT 841.690000 2692.200000 842.690000 2692.680000 ;
+ RECT 845.355000 2692.200000 846.620000 2692.680000 ;
+ RECT 841.690000 2681.320000 842.690000 2681.800000 ;
+ RECT 845.355000 2681.320000 846.620000 2681.800000 ;
+ RECT 841.690000 2675.880000 842.690000 2676.360000 ;
+ RECT 845.355000 2675.880000 846.620000 2676.360000 ;
+ RECT 841.690000 2670.440000 842.690000 2670.920000 ;
+ RECT 845.355000 2670.440000 846.620000 2670.920000 ;
+ RECT 841.690000 2665.000000 842.690000 2665.480000 ;
+ RECT 845.355000 2665.000000 846.620000 2665.480000 ;
+ RECT 841.690000 2659.560000 842.690000 2660.040000 ;
+ RECT 845.355000 2659.560000 846.620000 2660.040000 ;
+ RECT 841.690000 2654.120000 842.690000 2654.600000 ;
+ RECT 845.355000 2654.120000 846.620000 2654.600000 ;
+ RECT 1025.520000 2637.800000 1026.620000 2638.280000 ;
+ RECT 1025.520000 2643.240000 1026.620000 2643.720000 ;
+ RECT 1038.330000 2637.800000 1039.330000 2638.280000 ;
+ RECT 1038.330000 2643.240000 1039.330000 2643.720000 ;
+ RECT 1038.330000 2626.920000 1039.330000 2627.400000 ;
+ RECT 1038.330000 2632.360000 1039.330000 2632.840000 ;
+ RECT 1025.520000 2632.360000 1026.620000 2632.840000 ;
+ RECT 1025.520000 2626.920000 1026.620000 2627.400000 ;
+ RECT 1025.520000 2616.040000 1026.620000 2616.520000 ;
+ RECT 1025.520000 2621.480000 1026.620000 2621.960000 ;
+ RECT 1038.330000 2616.040000 1039.330000 2616.520000 ;
+ RECT 1038.330000 2621.480000 1039.330000 2621.960000 ;
+ RECT 1038.330000 2605.160000 1039.330000 2605.640000 ;
+ RECT 1038.330000 2599.720000 1039.330000 2600.200000 ;
+ RECT 1038.330000 2610.600000 1039.330000 2611.080000 ;
+ RECT 1025.520000 2610.600000 1026.620000 2611.080000 ;
+ RECT 1025.520000 2605.160000 1026.620000 2605.640000 ;
+ RECT 1025.520000 2599.720000 1026.620000 2600.200000 ;
+ RECT 980.520000 2626.920000 981.620000 2627.400000 ;
+ RECT 980.520000 2632.360000 981.620000 2632.840000 ;
+ RECT 980.520000 2637.800000 981.620000 2638.280000 ;
+ RECT 980.520000 2643.240000 981.620000 2643.720000 ;
+ RECT 980.520000 2599.720000 981.620000 2600.200000 ;
+ RECT 980.520000 2605.160000 981.620000 2605.640000 ;
+ RECT 980.520000 2610.600000 981.620000 2611.080000 ;
+ RECT 980.520000 2616.040000 981.620000 2616.520000 ;
+ RECT 980.520000 2621.480000 981.620000 2621.960000 ;
+ RECT 1025.520000 2588.840000 1026.620000 2589.320000 ;
+ RECT 1025.520000 2594.280000 1026.620000 2594.760000 ;
+ RECT 1038.330000 2588.840000 1039.330000 2589.320000 ;
+ RECT 1038.330000 2594.280000 1039.330000 2594.760000 ;
+ RECT 1025.520000 2577.960000 1026.620000 2578.440000 ;
+ RECT 1025.520000 2583.400000 1026.620000 2583.880000 ;
+ RECT 1038.330000 2577.960000 1039.330000 2578.440000 ;
+ RECT 1038.330000 2583.400000 1039.330000 2583.880000 ;
+ RECT 1038.330000 2567.080000 1039.330000 2567.560000 ;
+ RECT 1038.330000 2561.640000 1039.330000 2562.120000 ;
+ RECT 1038.330000 2572.520000 1039.330000 2573.000000 ;
+ RECT 1025.520000 2572.520000 1026.620000 2573.000000 ;
+ RECT 1025.520000 2567.080000 1026.620000 2567.560000 ;
+ RECT 1025.520000 2561.640000 1026.620000 2562.120000 ;
+ RECT 1025.520000 2556.200000 1026.620000 2556.680000 ;
+ RECT 1038.330000 2556.200000 1039.330000 2556.680000 ;
+ RECT 980.520000 2577.960000 981.620000 2578.440000 ;
+ RECT 980.520000 2583.400000 981.620000 2583.880000 ;
+ RECT 980.520000 2588.840000 981.620000 2589.320000 ;
+ RECT 980.520000 2594.280000 981.620000 2594.760000 ;
+ RECT 980.520000 2556.200000 981.620000 2556.680000 ;
+ RECT 980.520000 2561.640000 981.620000 2562.120000 ;
+ RECT 980.520000 2567.080000 981.620000 2567.560000 ;
+ RECT 980.520000 2572.520000 981.620000 2573.000000 ;
+ RECT 935.520000 2626.920000 936.620000 2627.400000 ;
+ RECT 935.520000 2632.360000 936.620000 2632.840000 ;
+ RECT 935.520000 2637.800000 936.620000 2638.280000 ;
+ RECT 935.520000 2643.240000 936.620000 2643.720000 ;
+ RECT 890.520000 2626.920000 891.620000 2627.400000 ;
+ RECT 890.520000 2632.360000 891.620000 2632.840000 ;
+ RECT 890.520000 2637.800000 891.620000 2638.280000 ;
+ RECT 890.520000 2643.240000 891.620000 2643.720000 ;
+ RECT 935.520000 2599.720000 936.620000 2600.200000 ;
+ RECT 935.520000 2605.160000 936.620000 2605.640000 ;
+ RECT 935.520000 2610.600000 936.620000 2611.080000 ;
+ RECT 935.520000 2616.040000 936.620000 2616.520000 ;
+ RECT 935.520000 2621.480000 936.620000 2621.960000 ;
+ RECT 890.520000 2599.720000 891.620000 2600.200000 ;
+ RECT 890.520000 2605.160000 891.620000 2605.640000 ;
+ RECT 890.520000 2610.600000 891.620000 2611.080000 ;
+ RECT 890.520000 2616.040000 891.620000 2616.520000 ;
+ RECT 890.520000 2621.480000 891.620000 2621.960000 ;
+ RECT 841.690000 2643.240000 842.690000 2643.720000 ;
+ RECT 845.355000 2643.240000 846.620000 2643.720000 ;
+ RECT 841.690000 2637.800000 842.690000 2638.280000 ;
+ RECT 845.355000 2637.800000 846.620000 2638.280000 ;
+ RECT 841.690000 2632.360000 842.690000 2632.840000 ;
+ RECT 845.355000 2632.360000 846.620000 2632.840000 ;
+ RECT 841.690000 2626.920000 842.690000 2627.400000 ;
+ RECT 845.355000 2626.920000 846.620000 2627.400000 ;
+ RECT 841.690000 2621.480000 842.690000 2621.960000 ;
+ RECT 845.355000 2621.480000 846.620000 2621.960000 ;
+ RECT 841.690000 2616.040000 842.690000 2616.520000 ;
+ RECT 845.355000 2616.040000 846.620000 2616.520000 ;
+ RECT 841.690000 2605.160000 842.690000 2605.640000 ;
+ RECT 845.355000 2605.160000 846.620000 2605.640000 ;
+ RECT 841.690000 2610.600000 842.690000 2611.080000 ;
+ RECT 845.355000 2610.600000 846.620000 2611.080000 ;
+ RECT 841.690000 2599.720000 842.690000 2600.200000 ;
+ RECT 845.355000 2599.720000 846.620000 2600.200000 ;
+ RECT 935.520000 2577.960000 936.620000 2578.440000 ;
+ RECT 935.520000 2583.400000 936.620000 2583.880000 ;
+ RECT 935.520000 2588.840000 936.620000 2589.320000 ;
+ RECT 935.520000 2594.280000 936.620000 2594.760000 ;
+ RECT 890.520000 2577.960000 891.620000 2578.440000 ;
+ RECT 890.520000 2583.400000 891.620000 2583.880000 ;
+ RECT 890.520000 2588.840000 891.620000 2589.320000 ;
+ RECT 890.520000 2594.280000 891.620000 2594.760000 ;
+ RECT 935.520000 2556.200000 936.620000 2556.680000 ;
+ RECT 935.520000 2561.640000 936.620000 2562.120000 ;
+ RECT 935.520000 2567.080000 936.620000 2567.560000 ;
+ RECT 935.520000 2572.520000 936.620000 2573.000000 ;
+ RECT 890.520000 2556.200000 891.620000 2556.680000 ;
+ RECT 890.520000 2561.640000 891.620000 2562.120000 ;
+ RECT 890.520000 2567.080000 891.620000 2567.560000 ;
+ RECT 890.520000 2572.520000 891.620000 2573.000000 ;
+ RECT 841.690000 2594.280000 842.690000 2594.760000 ;
+ RECT 845.355000 2594.280000 846.620000 2594.760000 ;
+ RECT 841.690000 2588.840000 842.690000 2589.320000 ;
+ RECT 845.355000 2588.840000 846.620000 2589.320000 ;
+ RECT 841.690000 2583.400000 842.690000 2583.880000 ;
+ RECT 845.355000 2583.400000 846.620000 2583.880000 ;
+ RECT 841.690000 2577.960000 842.690000 2578.440000 ;
+ RECT 845.355000 2577.960000 846.620000 2578.440000 ;
+ RECT 841.690000 2572.520000 842.690000 2573.000000 ;
+ RECT 845.355000 2572.520000 846.620000 2573.000000 ;
+ RECT 841.690000 2561.640000 842.690000 2562.120000 ;
+ RECT 845.355000 2561.640000 846.620000 2562.120000 ;
+ RECT 841.690000 2567.080000 842.690000 2567.560000 ;
+ RECT 845.355000 2567.080000 846.620000 2567.560000 ;
+ RECT 841.690000 2556.200000 842.690000 2556.680000 ;
+ RECT 845.355000 2556.200000 846.620000 2556.680000 ;
+ RECT 980.520000 2648.680000 981.620000 2649.160000 ;
+ RECT 1025.520000 2648.680000 1026.620000 2649.160000 ;
+ RECT 1038.330000 2648.680000 1039.330000 2649.160000 ;
+ RECT 890.520000 2648.680000 891.620000 2649.160000 ;
+ RECT 935.520000 2648.680000 936.620000 2649.160000 ;
+ RECT 841.690000 2648.680000 842.690000 2649.160000 ;
+ RECT 845.355000 2648.680000 846.620000 2649.160000 ;
+ RECT 840.460000 2745.440000 1040.560000 2746.440000 ;
+ RECT 840.460000 2549.870000 1040.560000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 2548.620000 842.690000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 2747.880000 842.690000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 2548.620000 1039.330000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 2747.880000 1039.330000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2549.870000 841.460000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2549.870000 1040.560000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2745.440000 841.460000 2746.440000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2745.440000 1040.560000 2746.440000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 2540.900000 846.620000 2541.380000 ;
+ RECT 845.355000 2530.020000 846.620000 2530.500000 ;
+ RECT 845.355000 2535.460000 846.620000 2535.940000 ;
+ RECT 845.355000 2524.580000 846.620000 2525.060000 ;
+ RECT 845.355000 2519.140000 846.620000 2519.620000 ;
+ RECT 845.355000 2513.700000 846.620000 2514.180000 ;
+ RECT 845.355000 2508.260000 846.620000 2508.740000 ;
+ RECT 845.355000 2502.820000 846.620000 2503.300000 ;
+ RECT 845.355000 2497.380000 846.620000 2497.860000 ;
+ RECT 845.355000 2486.500000 846.620000 2486.980000 ;
+ RECT 845.355000 2491.940000 846.620000 2492.420000 ;
+ RECT 845.355000 2481.060000 846.620000 2481.540000 ;
+ RECT 845.355000 2475.620000 846.620000 2476.100000 ;
+ RECT 845.355000 2470.180000 846.620000 2470.660000 ;
+ RECT 845.355000 2464.740000 846.620000 2465.220000 ;
+ RECT 845.355000 2459.300000 846.620000 2459.780000 ;
+ RECT 845.355000 2453.860000 846.620000 2454.340000 ;
+ RECT 845.355000 2442.980000 846.620000 2443.460000 ;
+ RECT 845.355000 2437.540000 846.620000 2438.020000 ;
+ RECT 845.355000 2432.100000 846.620000 2432.580000 ;
+ RECT 845.355000 2426.660000 846.620000 2427.140000 ;
+ RECT 845.355000 2421.220000 846.620000 2421.700000 ;
+ RECT 845.355000 2415.780000 846.620000 2416.260000 ;
+ RECT 845.355000 2404.900000 846.620000 2405.380000 ;
+ RECT 845.355000 2410.340000 846.620000 2410.820000 ;
+ RECT 845.355000 2399.460000 846.620000 2399.940000 ;
+ RECT 845.355000 2394.020000 846.620000 2394.500000 ;
+ RECT 845.355000 2388.580000 846.620000 2389.060000 ;
+ RECT 845.355000 2383.140000 846.620000 2383.620000 ;
+ RECT 845.355000 2377.700000 846.620000 2378.180000 ;
+ RECT 845.355000 2372.260000 846.620000 2372.740000 ;
+ RECT 845.355000 2361.380000 846.620000 2361.860000 ;
+ RECT 845.355000 2366.820000 846.620000 2367.300000 ;
+ RECT 845.355000 2355.940000 846.620000 2356.420000 ;
+ RECT 845.355000 2448.420000 846.620000 2448.900000 ;
+ RECT 1025.520000 2349.610000 1026.620000 2546.180000 ;
+ RECT 980.520000 2349.610000 981.620000 2546.180000 ;
+ RECT 1038.330000 2348.360000 1039.330000 2548.620000 ;
+ RECT 935.520000 2349.610000 936.620000 2546.180000 ;
+ RECT 890.520000 2349.610000 891.620000 2546.180000 ;
+ RECT 845.520000 2349.610000 846.620000 2546.180000 ;
+ RECT 841.690000 2348.360000 842.690000 2548.620000 ;
+ LAYER met3 ;
+ RECT 1025.520000 2540.900000 1026.620000 2541.380000 ;
+ RECT 1038.330000 2540.900000 1039.330000 2541.380000 ;
+ RECT 1038.330000 2530.020000 1039.330000 2530.500000 ;
+ RECT 1038.330000 2524.580000 1039.330000 2525.060000 ;
+ RECT 1038.330000 2535.460000 1039.330000 2535.940000 ;
+ RECT 1025.520000 2535.460000 1026.620000 2535.940000 ;
+ RECT 1025.520000 2530.020000 1026.620000 2530.500000 ;
+ RECT 1025.520000 2524.580000 1026.620000 2525.060000 ;
+ RECT 1025.520000 2513.700000 1026.620000 2514.180000 ;
+ RECT 1025.520000 2519.140000 1026.620000 2519.620000 ;
+ RECT 1038.330000 2513.700000 1039.330000 2514.180000 ;
+ RECT 1038.330000 2519.140000 1039.330000 2519.620000 ;
+ RECT 1025.520000 2502.820000 1026.620000 2503.300000 ;
+ RECT 1025.520000 2508.260000 1026.620000 2508.740000 ;
+ RECT 1038.330000 2502.820000 1039.330000 2503.300000 ;
+ RECT 1038.330000 2508.260000 1039.330000 2508.740000 ;
+ RECT 980.520000 2524.580000 981.620000 2525.060000 ;
+ RECT 980.520000 2530.020000 981.620000 2530.500000 ;
+ RECT 980.520000 2535.460000 981.620000 2535.940000 ;
+ RECT 980.520000 2540.900000 981.620000 2541.380000 ;
+ RECT 980.520000 2508.260000 981.620000 2508.740000 ;
+ RECT 980.520000 2502.820000 981.620000 2503.300000 ;
+ RECT 980.520000 2513.700000 981.620000 2514.180000 ;
+ RECT 980.520000 2519.140000 981.620000 2519.620000 ;
+ RECT 1038.330000 2491.940000 1039.330000 2492.420000 ;
+ RECT 1038.330000 2486.500000 1039.330000 2486.980000 ;
+ RECT 1038.330000 2497.380000 1039.330000 2497.860000 ;
+ RECT 1025.520000 2497.380000 1026.620000 2497.860000 ;
+ RECT 1025.520000 2491.940000 1026.620000 2492.420000 ;
+ RECT 1025.520000 2486.500000 1026.620000 2486.980000 ;
+ RECT 1025.520000 2475.620000 1026.620000 2476.100000 ;
+ RECT 1025.520000 2481.060000 1026.620000 2481.540000 ;
+ RECT 1038.330000 2475.620000 1039.330000 2476.100000 ;
+ RECT 1038.330000 2481.060000 1039.330000 2481.540000 ;
+ RECT 1038.330000 2464.740000 1039.330000 2465.220000 ;
+ RECT 1038.330000 2470.180000 1039.330000 2470.660000 ;
+ RECT 1025.520000 2470.180000 1026.620000 2470.660000 ;
+ RECT 1025.520000 2464.740000 1026.620000 2465.220000 ;
+ RECT 1025.520000 2453.860000 1026.620000 2454.340000 ;
+ RECT 1025.520000 2459.300000 1026.620000 2459.780000 ;
+ RECT 1038.330000 2453.860000 1039.330000 2454.340000 ;
+ RECT 1038.330000 2459.300000 1039.330000 2459.780000 ;
+ RECT 980.520000 2475.620000 981.620000 2476.100000 ;
+ RECT 980.520000 2481.060000 981.620000 2481.540000 ;
+ RECT 980.520000 2486.500000 981.620000 2486.980000 ;
+ RECT 980.520000 2491.940000 981.620000 2492.420000 ;
+ RECT 980.520000 2497.380000 981.620000 2497.860000 ;
+ RECT 980.520000 2453.860000 981.620000 2454.340000 ;
+ RECT 980.520000 2459.300000 981.620000 2459.780000 ;
+ RECT 980.520000 2464.740000 981.620000 2465.220000 ;
+ RECT 980.520000 2470.180000 981.620000 2470.660000 ;
+ RECT 935.520000 2530.020000 936.620000 2530.500000 ;
+ RECT 935.520000 2524.580000 936.620000 2525.060000 ;
+ RECT 935.520000 2535.460000 936.620000 2535.940000 ;
+ RECT 935.520000 2540.900000 936.620000 2541.380000 ;
+ RECT 890.520000 2524.580000 891.620000 2525.060000 ;
+ RECT 890.520000 2530.020000 891.620000 2530.500000 ;
+ RECT 890.520000 2535.460000 891.620000 2535.940000 ;
+ RECT 890.520000 2540.900000 891.620000 2541.380000 ;
+ RECT 935.520000 2502.820000 936.620000 2503.300000 ;
+ RECT 935.520000 2508.260000 936.620000 2508.740000 ;
+ RECT 935.520000 2513.700000 936.620000 2514.180000 ;
+ RECT 935.520000 2519.140000 936.620000 2519.620000 ;
+ RECT 890.520000 2502.820000 891.620000 2503.300000 ;
+ RECT 890.520000 2508.260000 891.620000 2508.740000 ;
+ RECT 890.520000 2513.700000 891.620000 2514.180000 ;
+ RECT 890.520000 2519.140000 891.620000 2519.620000 ;
+ RECT 841.690000 2540.900000 842.690000 2541.380000 ;
+ RECT 845.355000 2540.900000 846.620000 2541.380000 ;
+ RECT 841.690000 2530.020000 842.690000 2530.500000 ;
+ RECT 845.355000 2530.020000 846.620000 2530.500000 ;
+ RECT 841.690000 2535.460000 842.690000 2535.940000 ;
+ RECT 845.355000 2535.460000 846.620000 2535.940000 ;
+ RECT 841.690000 2524.580000 842.690000 2525.060000 ;
+ RECT 845.355000 2524.580000 846.620000 2525.060000 ;
+ RECT 841.690000 2519.140000 842.690000 2519.620000 ;
+ RECT 845.355000 2519.140000 846.620000 2519.620000 ;
+ RECT 841.690000 2513.700000 842.690000 2514.180000 ;
+ RECT 845.355000 2513.700000 846.620000 2514.180000 ;
+ RECT 841.690000 2508.260000 842.690000 2508.740000 ;
+ RECT 845.355000 2508.260000 846.620000 2508.740000 ;
+ RECT 841.690000 2502.820000 842.690000 2503.300000 ;
+ RECT 845.355000 2502.820000 846.620000 2503.300000 ;
+ RECT 935.520000 2475.620000 936.620000 2476.100000 ;
+ RECT 935.520000 2481.060000 936.620000 2481.540000 ;
+ RECT 935.520000 2486.500000 936.620000 2486.980000 ;
+ RECT 935.520000 2491.940000 936.620000 2492.420000 ;
+ RECT 935.520000 2497.380000 936.620000 2497.860000 ;
+ RECT 890.520000 2475.620000 891.620000 2476.100000 ;
+ RECT 890.520000 2481.060000 891.620000 2481.540000 ;
+ RECT 890.520000 2486.500000 891.620000 2486.980000 ;
+ RECT 890.520000 2491.940000 891.620000 2492.420000 ;
+ RECT 890.520000 2497.380000 891.620000 2497.860000 ;
+ RECT 935.520000 2453.860000 936.620000 2454.340000 ;
+ RECT 935.520000 2459.300000 936.620000 2459.780000 ;
+ RECT 935.520000 2464.740000 936.620000 2465.220000 ;
+ RECT 935.520000 2470.180000 936.620000 2470.660000 ;
+ RECT 890.520000 2453.860000 891.620000 2454.340000 ;
+ RECT 890.520000 2459.300000 891.620000 2459.780000 ;
+ RECT 890.520000 2464.740000 891.620000 2465.220000 ;
+ RECT 890.520000 2470.180000 891.620000 2470.660000 ;
+ RECT 841.690000 2497.380000 842.690000 2497.860000 ;
+ RECT 845.355000 2497.380000 846.620000 2497.860000 ;
+ RECT 841.690000 2486.500000 842.690000 2486.980000 ;
+ RECT 845.355000 2486.500000 846.620000 2486.980000 ;
+ RECT 841.690000 2491.940000 842.690000 2492.420000 ;
+ RECT 845.355000 2491.940000 846.620000 2492.420000 ;
+ RECT 841.690000 2481.060000 842.690000 2481.540000 ;
+ RECT 845.355000 2481.060000 846.620000 2481.540000 ;
+ RECT 841.690000 2475.620000 842.690000 2476.100000 ;
+ RECT 845.355000 2475.620000 846.620000 2476.100000 ;
+ RECT 841.690000 2470.180000 842.690000 2470.660000 ;
+ RECT 845.355000 2470.180000 846.620000 2470.660000 ;
+ RECT 841.690000 2464.740000 842.690000 2465.220000 ;
+ RECT 845.355000 2464.740000 846.620000 2465.220000 ;
+ RECT 841.690000 2459.300000 842.690000 2459.780000 ;
+ RECT 845.355000 2459.300000 846.620000 2459.780000 ;
+ RECT 841.690000 2453.860000 842.690000 2454.340000 ;
+ RECT 845.355000 2453.860000 846.620000 2454.340000 ;
+ RECT 1025.520000 2437.540000 1026.620000 2438.020000 ;
+ RECT 1025.520000 2442.980000 1026.620000 2443.460000 ;
+ RECT 1038.330000 2437.540000 1039.330000 2438.020000 ;
+ RECT 1038.330000 2442.980000 1039.330000 2443.460000 ;
+ RECT 1038.330000 2426.660000 1039.330000 2427.140000 ;
+ RECT 1038.330000 2432.100000 1039.330000 2432.580000 ;
+ RECT 1025.520000 2432.100000 1026.620000 2432.580000 ;
+ RECT 1025.520000 2426.660000 1026.620000 2427.140000 ;
+ RECT 1025.520000 2415.780000 1026.620000 2416.260000 ;
+ RECT 1025.520000 2421.220000 1026.620000 2421.700000 ;
+ RECT 1038.330000 2415.780000 1039.330000 2416.260000 ;
+ RECT 1038.330000 2421.220000 1039.330000 2421.700000 ;
+ RECT 1038.330000 2404.900000 1039.330000 2405.380000 ;
+ RECT 1038.330000 2399.460000 1039.330000 2399.940000 ;
+ RECT 1038.330000 2410.340000 1039.330000 2410.820000 ;
+ RECT 1025.520000 2410.340000 1026.620000 2410.820000 ;
+ RECT 1025.520000 2404.900000 1026.620000 2405.380000 ;
+ RECT 1025.520000 2399.460000 1026.620000 2399.940000 ;
+ RECT 980.520000 2426.660000 981.620000 2427.140000 ;
+ RECT 980.520000 2432.100000 981.620000 2432.580000 ;
+ RECT 980.520000 2437.540000 981.620000 2438.020000 ;
+ RECT 980.520000 2442.980000 981.620000 2443.460000 ;
+ RECT 980.520000 2399.460000 981.620000 2399.940000 ;
+ RECT 980.520000 2404.900000 981.620000 2405.380000 ;
+ RECT 980.520000 2410.340000 981.620000 2410.820000 ;
+ RECT 980.520000 2415.780000 981.620000 2416.260000 ;
+ RECT 980.520000 2421.220000 981.620000 2421.700000 ;
+ RECT 1025.520000 2388.580000 1026.620000 2389.060000 ;
+ RECT 1025.520000 2394.020000 1026.620000 2394.500000 ;
+ RECT 1038.330000 2388.580000 1039.330000 2389.060000 ;
+ RECT 1038.330000 2394.020000 1039.330000 2394.500000 ;
+ RECT 1025.520000 2377.700000 1026.620000 2378.180000 ;
+ RECT 1025.520000 2383.140000 1026.620000 2383.620000 ;
+ RECT 1038.330000 2377.700000 1039.330000 2378.180000 ;
+ RECT 1038.330000 2383.140000 1039.330000 2383.620000 ;
+ RECT 1038.330000 2366.820000 1039.330000 2367.300000 ;
+ RECT 1038.330000 2361.380000 1039.330000 2361.860000 ;
+ RECT 1038.330000 2372.260000 1039.330000 2372.740000 ;
+ RECT 1025.520000 2372.260000 1026.620000 2372.740000 ;
+ RECT 1025.520000 2366.820000 1026.620000 2367.300000 ;
+ RECT 1025.520000 2361.380000 1026.620000 2361.860000 ;
+ RECT 1025.520000 2355.940000 1026.620000 2356.420000 ;
+ RECT 1038.330000 2355.940000 1039.330000 2356.420000 ;
+ RECT 980.520000 2377.700000 981.620000 2378.180000 ;
+ RECT 980.520000 2383.140000 981.620000 2383.620000 ;
+ RECT 980.520000 2388.580000 981.620000 2389.060000 ;
+ RECT 980.520000 2394.020000 981.620000 2394.500000 ;
+ RECT 980.520000 2355.940000 981.620000 2356.420000 ;
+ RECT 980.520000 2361.380000 981.620000 2361.860000 ;
+ RECT 980.520000 2366.820000 981.620000 2367.300000 ;
+ RECT 980.520000 2372.260000 981.620000 2372.740000 ;
+ RECT 935.520000 2426.660000 936.620000 2427.140000 ;
+ RECT 935.520000 2432.100000 936.620000 2432.580000 ;
+ RECT 935.520000 2437.540000 936.620000 2438.020000 ;
+ RECT 935.520000 2442.980000 936.620000 2443.460000 ;
+ RECT 890.520000 2426.660000 891.620000 2427.140000 ;
+ RECT 890.520000 2432.100000 891.620000 2432.580000 ;
+ RECT 890.520000 2437.540000 891.620000 2438.020000 ;
+ RECT 890.520000 2442.980000 891.620000 2443.460000 ;
+ RECT 935.520000 2399.460000 936.620000 2399.940000 ;
+ RECT 935.520000 2404.900000 936.620000 2405.380000 ;
+ RECT 935.520000 2410.340000 936.620000 2410.820000 ;
+ RECT 935.520000 2415.780000 936.620000 2416.260000 ;
+ RECT 935.520000 2421.220000 936.620000 2421.700000 ;
+ RECT 890.520000 2399.460000 891.620000 2399.940000 ;
+ RECT 890.520000 2404.900000 891.620000 2405.380000 ;
+ RECT 890.520000 2410.340000 891.620000 2410.820000 ;
+ RECT 890.520000 2415.780000 891.620000 2416.260000 ;
+ RECT 890.520000 2421.220000 891.620000 2421.700000 ;
+ RECT 841.690000 2442.980000 842.690000 2443.460000 ;
+ RECT 845.355000 2442.980000 846.620000 2443.460000 ;
+ RECT 841.690000 2437.540000 842.690000 2438.020000 ;
+ RECT 845.355000 2437.540000 846.620000 2438.020000 ;
+ RECT 841.690000 2432.100000 842.690000 2432.580000 ;
+ RECT 845.355000 2432.100000 846.620000 2432.580000 ;
+ RECT 841.690000 2426.660000 842.690000 2427.140000 ;
+ RECT 845.355000 2426.660000 846.620000 2427.140000 ;
+ RECT 841.690000 2421.220000 842.690000 2421.700000 ;
+ RECT 845.355000 2421.220000 846.620000 2421.700000 ;
+ RECT 841.690000 2415.780000 842.690000 2416.260000 ;
+ RECT 845.355000 2415.780000 846.620000 2416.260000 ;
+ RECT 841.690000 2404.900000 842.690000 2405.380000 ;
+ RECT 845.355000 2404.900000 846.620000 2405.380000 ;
+ RECT 841.690000 2410.340000 842.690000 2410.820000 ;
+ RECT 845.355000 2410.340000 846.620000 2410.820000 ;
+ RECT 841.690000 2399.460000 842.690000 2399.940000 ;
+ RECT 845.355000 2399.460000 846.620000 2399.940000 ;
+ RECT 935.520000 2377.700000 936.620000 2378.180000 ;
+ RECT 935.520000 2383.140000 936.620000 2383.620000 ;
+ RECT 935.520000 2388.580000 936.620000 2389.060000 ;
+ RECT 935.520000 2394.020000 936.620000 2394.500000 ;
+ RECT 890.520000 2377.700000 891.620000 2378.180000 ;
+ RECT 890.520000 2383.140000 891.620000 2383.620000 ;
+ RECT 890.520000 2388.580000 891.620000 2389.060000 ;
+ RECT 890.520000 2394.020000 891.620000 2394.500000 ;
+ RECT 935.520000 2355.940000 936.620000 2356.420000 ;
+ RECT 935.520000 2361.380000 936.620000 2361.860000 ;
+ RECT 935.520000 2366.820000 936.620000 2367.300000 ;
+ RECT 935.520000 2372.260000 936.620000 2372.740000 ;
+ RECT 890.520000 2355.940000 891.620000 2356.420000 ;
+ RECT 890.520000 2361.380000 891.620000 2361.860000 ;
+ RECT 890.520000 2366.820000 891.620000 2367.300000 ;
+ RECT 890.520000 2372.260000 891.620000 2372.740000 ;
+ RECT 841.690000 2394.020000 842.690000 2394.500000 ;
+ RECT 845.355000 2394.020000 846.620000 2394.500000 ;
+ RECT 841.690000 2388.580000 842.690000 2389.060000 ;
+ RECT 845.355000 2388.580000 846.620000 2389.060000 ;
+ RECT 841.690000 2383.140000 842.690000 2383.620000 ;
+ RECT 845.355000 2383.140000 846.620000 2383.620000 ;
+ RECT 841.690000 2377.700000 842.690000 2378.180000 ;
+ RECT 845.355000 2377.700000 846.620000 2378.180000 ;
+ RECT 841.690000 2372.260000 842.690000 2372.740000 ;
+ RECT 845.355000 2372.260000 846.620000 2372.740000 ;
+ RECT 841.690000 2361.380000 842.690000 2361.860000 ;
+ RECT 845.355000 2361.380000 846.620000 2361.860000 ;
+ RECT 841.690000 2366.820000 842.690000 2367.300000 ;
+ RECT 845.355000 2366.820000 846.620000 2367.300000 ;
+ RECT 841.690000 2355.940000 842.690000 2356.420000 ;
+ RECT 845.355000 2355.940000 846.620000 2356.420000 ;
+ RECT 980.520000 2448.420000 981.620000 2448.900000 ;
+ RECT 1025.520000 2448.420000 1026.620000 2448.900000 ;
+ RECT 1038.330000 2448.420000 1039.330000 2448.900000 ;
+ RECT 890.520000 2448.420000 891.620000 2448.900000 ;
+ RECT 935.520000 2448.420000 936.620000 2448.900000 ;
+ RECT 841.690000 2448.420000 842.690000 2448.900000 ;
+ RECT 845.355000 2448.420000 846.620000 2448.900000 ;
+ RECT 840.460000 2545.180000 1040.560000 2546.180000 ;
+ RECT 840.460000 2349.610000 1040.560000 2350.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 2348.360000 842.690000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 2547.620000 842.690000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 2348.360000 1039.330000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 2547.620000 1039.330000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2349.610000 841.460000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2349.610000 1040.560000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2545.180000 841.460000 2546.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2545.180000 1040.560000 2546.180000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 2340.640000 846.620000 2341.120000 ;
+ RECT 845.355000 2329.760000 846.620000 2330.240000 ;
+ RECT 845.355000 2335.200000 846.620000 2335.680000 ;
+ RECT 845.355000 2324.320000 846.620000 2324.800000 ;
+ RECT 845.355000 2318.880000 846.620000 2319.360000 ;
+ RECT 845.355000 2313.440000 846.620000 2313.920000 ;
+ RECT 845.355000 2308.000000 846.620000 2308.480000 ;
+ RECT 845.355000 2302.560000 846.620000 2303.040000 ;
+ RECT 845.355000 2297.120000 846.620000 2297.600000 ;
+ RECT 845.355000 2286.240000 846.620000 2286.720000 ;
+ RECT 845.355000 2291.680000 846.620000 2292.160000 ;
+ RECT 845.355000 2280.800000 846.620000 2281.280000 ;
+ RECT 845.355000 2275.360000 846.620000 2275.840000 ;
+ RECT 845.355000 2269.920000 846.620000 2270.400000 ;
+ RECT 845.355000 2264.480000 846.620000 2264.960000 ;
+ RECT 845.355000 2259.040000 846.620000 2259.520000 ;
+ RECT 845.355000 2253.600000 846.620000 2254.080000 ;
+ RECT 845.355000 2242.720000 846.620000 2243.200000 ;
+ RECT 845.355000 2237.280000 846.620000 2237.760000 ;
+ RECT 845.355000 2231.840000 846.620000 2232.320000 ;
+ RECT 845.355000 2226.400000 846.620000 2226.880000 ;
+ RECT 845.355000 2220.960000 846.620000 2221.440000 ;
+ RECT 845.355000 2215.520000 846.620000 2216.000000 ;
+ RECT 845.355000 2204.640000 846.620000 2205.120000 ;
+ RECT 845.355000 2210.080000 846.620000 2210.560000 ;
+ RECT 845.355000 2199.200000 846.620000 2199.680000 ;
+ RECT 845.355000 2193.760000 846.620000 2194.240000 ;
+ RECT 845.355000 2188.320000 846.620000 2188.800000 ;
+ RECT 845.355000 2182.880000 846.620000 2183.360000 ;
+ RECT 845.355000 2177.440000 846.620000 2177.920000 ;
+ RECT 845.355000 2172.000000 846.620000 2172.480000 ;
+ RECT 845.355000 2161.120000 846.620000 2161.600000 ;
+ RECT 845.355000 2166.560000 846.620000 2167.040000 ;
+ RECT 845.355000 2155.680000 846.620000 2156.160000 ;
+ RECT 845.355000 2248.160000 846.620000 2248.640000 ;
+ RECT 1025.520000 2149.350000 1026.620000 2345.920000 ;
+ RECT 980.520000 2149.350000 981.620000 2345.920000 ;
+ RECT 1038.330000 2148.100000 1039.330000 2348.360000 ;
+ RECT 935.520000 2149.350000 936.620000 2345.920000 ;
+ RECT 890.520000 2149.350000 891.620000 2345.920000 ;
+ RECT 845.520000 2149.350000 846.620000 2345.920000 ;
+ RECT 841.690000 2148.100000 842.690000 2348.360000 ;
+ LAYER met3 ;
+ RECT 1025.520000 2340.640000 1026.620000 2341.120000 ;
+ RECT 1038.330000 2340.640000 1039.330000 2341.120000 ;
+ RECT 1038.330000 2329.760000 1039.330000 2330.240000 ;
+ RECT 1038.330000 2324.320000 1039.330000 2324.800000 ;
+ RECT 1038.330000 2335.200000 1039.330000 2335.680000 ;
+ RECT 1025.520000 2335.200000 1026.620000 2335.680000 ;
+ RECT 1025.520000 2329.760000 1026.620000 2330.240000 ;
+ RECT 1025.520000 2324.320000 1026.620000 2324.800000 ;
+ RECT 1025.520000 2313.440000 1026.620000 2313.920000 ;
+ RECT 1025.520000 2318.880000 1026.620000 2319.360000 ;
+ RECT 1038.330000 2313.440000 1039.330000 2313.920000 ;
+ RECT 1038.330000 2318.880000 1039.330000 2319.360000 ;
+ RECT 1025.520000 2302.560000 1026.620000 2303.040000 ;
+ RECT 1025.520000 2308.000000 1026.620000 2308.480000 ;
+ RECT 1038.330000 2302.560000 1039.330000 2303.040000 ;
+ RECT 1038.330000 2308.000000 1039.330000 2308.480000 ;
+ RECT 980.520000 2324.320000 981.620000 2324.800000 ;
+ RECT 980.520000 2329.760000 981.620000 2330.240000 ;
+ RECT 980.520000 2335.200000 981.620000 2335.680000 ;
+ RECT 980.520000 2340.640000 981.620000 2341.120000 ;
+ RECT 980.520000 2308.000000 981.620000 2308.480000 ;
+ RECT 980.520000 2302.560000 981.620000 2303.040000 ;
+ RECT 980.520000 2313.440000 981.620000 2313.920000 ;
+ RECT 980.520000 2318.880000 981.620000 2319.360000 ;
+ RECT 1038.330000 2291.680000 1039.330000 2292.160000 ;
+ RECT 1038.330000 2286.240000 1039.330000 2286.720000 ;
+ RECT 1038.330000 2297.120000 1039.330000 2297.600000 ;
+ RECT 1025.520000 2297.120000 1026.620000 2297.600000 ;
+ RECT 1025.520000 2291.680000 1026.620000 2292.160000 ;
+ RECT 1025.520000 2286.240000 1026.620000 2286.720000 ;
+ RECT 1025.520000 2275.360000 1026.620000 2275.840000 ;
+ RECT 1025.520000 2280.800000 1026.620000 2281.280000 ;
+ RECT 1038.330000 2275.360000 1039.330000 2275.840000 ;
+ RECT 1038.330000 2280.800000 1039.330000 2281.280000 ;
+ RECT 1038.330000 2264.480000 1039.330000 2264.960000 ;
+ RECT 1038.330000 2269.920000 1039.330000 2270.400000 ;
+ RECT 1025.520000 2269.920000 1026.620000 2270.400000 ;
+ RECT 1025.520000 2264.480000 1026.620000 2264.960000 ;
+ RECT 1025.520000 2253.600000 1026.620000 2254.080000 ;
+ RECT 1025.520000 2259.040000 1026.620000 2259.520000 ;
+ RECT 1038.330000 2253.600000 1039.330000 2254.080000 ;
+ RECT 1038.330000 2259.040000 1039.330000 2259.520000 ;
+ RECT 980.520000 2275.360000 981.620000 2275.840000 ;
+ RECT 980.520000 2280.800000 981.620000 2281.280000 ;
+ RECT 980.520000 2286.240000 981.620000 2286.720000 ;
+ RECT 980.520000 2291.680000 981.620000 2292.160000 ;
+ RECT 980.520000 2297.120000 981.620000 2297.600000 ;
+ RECT 980.520000 2253.600000 981.620000 2254.080000 ;
+ RECT 980.520000 2259.040000 981.620000 2259.520000 ;
+ RECT 980.520000 2264.480000 981.620000 2264.960000 ;
+ RECT 980.520000 2269.920000 981.620000 2270.400000 ;
+ RECT 935.520000 2329.760000 936.620000 2330.240000 ;
+ RECT 935.520000 2324.320000 936.620000 2324.800000 ;
+ RECT 935.520000 2335.200000 936.620000 2335.680000 ;
+ RECT 935.520000 2340.640000 936.620000 2341.120000 ;
+ RECT 890.520000 2324.320000 891.620000 2324.800000 ;
+ RECT 890.520000 2329.760000 891.620000 2330.240000 ;
+ RECT 890.520000 2335.200000 891.620000 2335.680000 ;
+ RECT 890.520000 2340.640000 891.620000 2341.120000 ;
+ RECT 935.520000 2302.560000 936.620000 2303.040000 ;
+ RECT 935.520000 2308.000000 936.620000 2308.480000 ;
+ RECT 935.520000 2313.440000 936.620000 2313.920000 ;
+ RECT 935.520000 2318.880000 936.620000 2319.360000 ;
+ RECT 890.520000 2302.560000 891.620000 2303.040000 ;
+ RECT 890.520000 2308.000000 891.620000 2308.480000 ;
+ RECT 890.520000 2313.440000 891.620000 2313.920000 ;
+ RECT 890.520000 2318.880000 891.620000 2319.360000 ;
+ RECT 841.690000 2340.640000 842.690000 2341.120000 ;
+ RECT 845.355000 2340.640000 846.620000 2341.120000 ;
+ RECT 841.690000 2329.760000 842.690000 2330.240000 ;
+ RECT 845.355000 2329.760000 846.620000 2330.240000 ;
+ RECT 841.690000 2335.200000 842.690000 2335.680000 ;
+ RECT 845.355000 2335.200000 846.620000 2335.680000 ;
+ RECT 841.690000 2324.320000 842.690000 2324.800000 ;
+ RECT 845.355000 2324.320000 846.620000 2324.800000 ;
+ RECT 841.690000 2318.880000 842.690000 2319.360000 ;
+ RECT 845.355000 2318.880000 846.620000 2319.360000 ;
+ RECT 841.690000 2313.440000 842.690000 2313.920000 ;
+ RECT 845.355000 2313.440000 846.620000 2313.920000 ;
+ RECT 841.690000 2308.000000 842.690000 2308.480000 ;
+ RECT 845.355000 2308.000000 846.620000 2308.480000 ;
+ RECT 841.690000 2302.560000 842.690000 2303.040000 ;
+ RECT 845.355000 2302.560000 846.620000 2303.040000 ;
+ RECT 935.520000 2275.360000 936.620000 2275.840000 ;
+ RECT 935.520000 2280.800000 936.620000 2281.280000 ;
+ RECT 935.520000 2286.240000 936.620000 2286.720000 ;
+ RECT 935.520000 2291.680000 936.620000 2292.160000 ;
+ RECT 935.520000 2297.120000 936.620000 2297.600000 ;
+ RECT 890.520000 2275.360000 891.620000 2275.840000 ;
+ RECT 890.520000 2280.800000 891.620000 2281.280000 ;
+ RECT 890.520000 2286.240000 891.620000 2286.720000 ;
+ RECT 890.520000 2291.680000 891.620000 2292.160000 ;
+ RECT 890.520000 2297.120000 891.620000 2297.600000 ;
+ RECT 935.520000 2253.600000 936.620000 2254.080000 ;
+ RECT 935.520000 2259.040000 936.620000 2259.520000 ;
+ RECT 935.520000 2264.480000 936.620000 2264.960000 ;
+ RECT 935.520000 2269.920000 936.620000 2270.400000 ;
+ RECT 890.520000 2253.600000 891.620000 2254.080000 ;
+ RECT 890.520000 2259.040000 891.620000 2259.520000 ;
+ RECT 890.520000 2264.480000 891.620000 2264.960000 ;
+ RECT 890.520000 2269.920000 891.620000 2270.400000 ;
+ RECT 841.690000 2297.120000 842.690000 2297.600000 ;
+ RECT 845.355000 2297.120000 846.620000 2297.600000 ;
+ RECT 841.690000 2286.240000 842.690000 2286.720000 ;
+ RECT 845.355000 2286.240000 846.620000 2286.720000 ;
+ RECT 841.690000 2291.680000 842.690000 2292.160000 ;
+ RECT 845.355000 2291.680000 846.620000 2292.160000 ;
+ RECT 841.690000 2280.800000 842.690000 2281.280000 ;
+ RECT 845.355000 2280.800000 846.620000 2281.280000 ;
+ RECT 841.690000 2275.360000 842.690000 2275.840000 ;
+ RECT 845.355000 2275.360000 846.620000 2275.840000 ;
+ RECT 841.690000 2269.920000 842.690000 2270.400000 ;
+ RECT 845.355000 2269.920000 846.620000 2270.400000 ;
+ RECT 841.690000 2264.480000 842.690000 2264.960000 ;
+ RECT 845.355000 2264.480000 846.620000 2264.960000 ;
+ RECT 841.690000 2259.040000 842.690000 2259.520000 ;
+ RECT 845.355000 2259.040000 846.620000 2259.520000 ;
+ RECT 841.690000 2253.600000 842.690000 2254.080000 ;
+ RECT 845.355000 2253.600000 846.620000 2254.080000 ;
+ RECT 1025.520000 2237.280000 1026.620000 2237.760000 ;
+ RECT 1025.520000 2242.720000 1026.620000 2243.200000 ;
+ RECT 1038.330000 2237.280000 1039.330000 2237.760000 ;
+ RECT 1038.330000 2242.720000 1039.330000 2243.200000 ;
+ RECT 1038.330000 2226.400000 1039.330000 2226.880000 ;
+ RECT 1038.330000 2231.840000 1039.330000 2232.320000 ;
+ RECT 1025.520000 2231.840000 1026.620000 2232.320000 ;
+ RECT 1025.520000 2226.400000 1026.620000 2226.880000 ;
+ RECT 1025.520000 2215.520000 1026.620000 2216.000000 ;
+ RECT 1025.520000 2220.960000 1026.620000 2221.440000 ;
+ RECT 1038.330000 2215.520000 1039.330000 2216.000000 ;
+ RECT 1038.330000 2220.960000 1039.330000 2221.440000 ;
+ RECT 1038.330000 2204.640000 1039.330000 2205.120000 ;
+ RECT 1038.330000 2199.200000 1039.330000 2199.680000 ;
+ RECT 1038.330000 2210.080000 1039.330000 2210.560000 ;
+ RECT 1025.520000 2210.080000 1026.620000 2210.560000 ;
+ RECT 1025.520000 2204.640000 1026.620000 2205.120000 ;
+ RECT 1025.520000 2199.200000 1026.620000 2199.680000 ;
+ RECT 980.520000 2226.400000 981.620000 2226.880000 ;
+ RECT 980.520000 2231.840000 981.620000 2232.320000 ;
+ RECT 980.520000 2237.280000 981.620000 2237.760000 ;
+ RECT 980.520000 2242.720000 981.620000 2243.200000 ;
+ RECT 980.520000 2199.200000 981.620000 2199.680000 ;
+ RECT 980.520000 2204.640000 981.620000 2205.120000 ;
+ RECT 980.520000 2210.080000 981.620000 2210.560000 ;
+ RECT 980.520000 2215.520000 981.620000 2216.000000 ;
+ RECT 980.520000 2220.960000 981.620000 2221.440000 ;
+ RECT 1025.520000 2188.320000 1026.620000 2188.800000 ;
+ RECT 1025.520000 2193.760000 1026.620000 2194.240000 ;
+ RECT 1038.330000 2188.320000 1039.330000 2188.800000 ;
+ RECT 1038.330000 2193.760000 1039.330000 2194.240000 ;
+ RECT 1025.520000 2177.440000 1026.620000 2177.920000 ;
+ RECT 1025.520000 2182.880000 1026.620000 2183.360000 ;
+ RECT 1038.330000 2177.440000 1039.330000 2177.920000 ;
+ RECT 1038.330000 2182.880000 1039.330000 2183.360000 ;
+ RECT 1038.330000 2166.560000 1039.330000 2167.040000 ;
+ RECT 1038.330000 2161.120000 1039.330000 2161.600000 ;
+ RECT 1038.330000 2172.000000 1039.330000 2172.480000 ;
+ RECT 1025.520000 2172.000000 1026.620000 2172.480000 ;
+ RECT 1025.520000 2166.560000 1026.620000 2167.040000 ;
+ RECT 1025.520000 2161.120000 1026.620000 2161.600000 ;
+ RECT 1025.520000 2155.680000 1026.620000 2156.160000 ;
+ RECT 1038.330000 2155.680000 1039.330000 2156.160000 ;
+ RECT 980.520000 2177.440000 981.620000 2177.920000 ;
+ RECT 980.520000 2182.880000 981.620000 2183.360000 ;
+ RECT 980.520000 2188.320000 981.620000 2188.800000 ;
+ RECT 980.520000 2193.760000 981.620000 2194.240000 ;
+ RECT 980.520000 2155.680000 981.620000 2156.160000 ;
+ RECT 980.520000 2161.120000 981.620000 2161.600000 ;
+ RECT 980.520000 2166.560000 981.620000 2167.040000 ;
+ RECT 980.520000 2172.000000 981.620000 2172.480000 ;
+ RECT 935.520000 2226.400000 936.620000 2226.880000 ;
+ RECT 935.520000 2231.840000 936.620000 2232.320000 ;
+ RECT 935.520000 2237.280000 936.620000 2237.760000 ;
+ RECT 935.520000 2242.720000 936.620000 2243.200000 ;
+ RECT 890.520000 2226.400000 891.620000 2226.880000 ;
+ RECT 890.520000 2231.840000 891.620000 2232.320000 ;
+ RECT 890.520000 2237.280000 891.620000 2237.760000 ;
+ RECT 890.520000 2242.720000 891.620000 2243.200000 ;
+ RECT 935.520000 2199.200000 936.620000 2199.680000 ;
+ RECT 935.520000 2204.640000 936.620000 2205.120000 ;
+ RECT 935.520000 2210.080000 936.620000 2210.560000 ;
+ RECT 935.520000 2215.520000 936.620000 2216.000000 ;
+ RECT 935.520000 2220.960000 936.620000 2221.440000 ;
+ RECT 890.520000 2199.200000 891.620000 2199.680000 ;
+ RECT 890.520000 2204.640000 891.620000 2205.120000 ;
+ RECT 890.520000 2210.080000 891.620000 2210.560000 ;
+ RECT 890.520000 2215.520000 891.620000 2216.000000 ;
+ RECT 890.520000 2220.960000 891.620000 2221.440000 ;
+ RECT 841.690000 2242.720000 842.690000 2243.200000 ;
+ RECT 845.355000 2242.720000 846.620000 2243.200000 ;
+ RECT 841.690000 2237.280000 842.690000 2237.760000 ;
+ RECT 845.355000 2237.280000 846.620000 2237.760000 ;
+ RECT 841.690000 2231.840000 842.690000 2232.320000 ;
+ RECT 845.355000 2231.840000 846.620000 2232.320000 ;
+ RECT 841.690000 2226.400000 842.690000 2226.880000 ;
+ RECT 845.355000 2226.400000 846.620000 2226.880000 ;
+ RECT 841.690000 2220.960000 842.690000 2221.440000 ;
+ RECT 845.355000 2220.960000 846.620000 2221.440000 ;
+ RECT 841.690000 2215.520000 842.690000 2216.000000 ;
+ RECT 845.355000 2215.520000 846.620000 2216.000000 ;
+ RECT 841.690000 2204.640000 842.690000 2205.120000 ;
+ RECT 845.355000 2204.640000 846.620000 2205.120000 ;
+ RECT 841.690000 2210.080000 842.690000 2210.560000 ;
+ RECT 845.355000 2210.080000 846.620000 2210.560000 ;
+ RECT 841.690000 2199.200000 842.690000 2199.680000 ;
+ RECT 845.355000 2199.200000 846.620000 2199.680000 ;
+ RECT 935.520000 2177.440000 936.620000 2177.920000 ;
+ RECT 935.520000 2182.880000 936.620000 2183.360000 ;
+ RECT 935.520000 2188.320000 936.620000 2188.800000 ;
+ RECT 935.520000 2193.760000 936.620000 2194.240000 ;
+ RECT 890.520000 2177.440000 891.620000 2177.920000 ;
+ RECT 890.520000 2182.880000 891.620000 2183.360000 ;
+ RECT 890.520000 2188.320000 891.620000 2188.800000 ;
+ RECT 890.520000 2193.760000 891.620000 2194.240000 ;
+ RECT 935.520000 2155.680000 936.620000 2156.160000 ;
+ RECT 935.520000 2161.120000 936.620000 2161.600000 ;
+ RECT 935.520000 2166.560000 936.620000 2167.040000 ;
+ RECT 935.520000 2172.000000 936.620000 2172.480000 ;
+ RECT 890.520000 2155.680000 891.620000 2156.160000 ;
+ RECT 890.520000 2161.120000 891.620000 2161.600000 ;
+ RECT 890.520000 2166.560000 891.620000 2167.040000 ;
+ RECT 890.520000 2172.000000 891.620000 2172.480000 ;
+ RECT 841.690000 2193.760000 842.690000 2194.240000 ;
+ RECT 845.355000 2193.760000 846.620000 2194.240000 ;
+ RECT 841.690000 2188.320000 842.690000 2188.800000 ;
+ RECT 845.355000 2188.320000 846.620000 2188.800000 ;
+ RECT 841.690000 2182.880000 842.690000 2183.360000 ;
+ RECT 845.355000 2182.880000 846.620000 2183.360000 ;
+ RECT 841.690000 2177.440000 842.690000 2177.920000 ;
+ RECT 845.355000 2177.440000 846.620000 2177.920000 ;
+ RECT 841.690000 2172.000000 842.690000 2172.480000 ;
+ RECT 845.355000 2172.000000 846.620000 2172.480000 ;
+ RECT 841.690000 2161.120000 842.690000 2161.600000 ;
+ RECT 845.355000 2161.120000 846.620000 2161.600000 ;
+ RECT 841.690000 2166.560000 842.690000 2167.040000 ;
+ RECT 845.355000 2166.560000 846.620000 2167.040000 ;
+ RECT 841.690000 2155.680000 842.690000 2156.160000 ;
+ RECT 845.355000 2155.680000 846.620000 2156.160000 ;
+ RECT 980.520000 2248.160000 981.620000 2248.640000 ;
+ RECT 1025.520000 2248.160000 1026.620000 2248.640000 ;
+ RECT 1038.330000 2248.160000 1039.330000 2248.640000 ;
+ RECT 890.520000 2248.160000 891.620000 2248.640000 ;
+ RECT 935.520000 2248.160000 936.620000 2248.640000 ;
+ RECT 841.690000 2248.160000 842.690000 2248.640000 ;
+ RECT 845.355000 2248.160000 846.620000 2248.640000 ;
+ RECT 840.460000 2344.920000 1040.560000 2345.920000 ;
+ RECT 840.460000 2149.350000 1040.560000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 2148.100000 842.690000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 2347.360000 842.690000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 2148.100000 1039.330000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 2347.360000 1039.330000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2149.350000 841.460000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2149.350000 1040.560000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2344.920000 841.460000 2345.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2344.920000 1040.560000 2345.920000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 2140.380000 846.620000 2140.860000 ;
+ RECT 845.355000 2129.500000 846.620000 2129.980000 ;
+ RECT 845.355000 2134.940000 846.620000 2135.420000 ;
+ RECT 845.355000 2124.060000 846.620000 2124.540000 ;
+ RECT 845.355000 2118.620000 846.620000 2119.100000 ;
+ RECT 845.355000 2113.180000 846.620000 2113.660000 ;
+ RECT 845.355000 2107.740000 846.620000 2108.220000 ;
+ RECT 845.355000 2102.300000 846.620000 2102.780000 ;
+ RECT 845.355000 2096.860000 846.620000 2097.340000 ;
+ RECT 845.355000 2085.980000 846.620000 2086.460000 ;
+ RECT 845.355000 2091.420000 846.620000 2091.900000 ;
+ RECT 845.355000 2080.540000 846.620000 2081.020000 ;
+ RECT 845.355000 2075.100000 846.620000 2075.580000 ;
+ RECT 845.355000 2069.660000 846.620000 2070.140000 ;
+ RECT 845.355000 2064.220000 846.620000 2064.700000 ;
+ RECT 845.355000 2058.780000 846.620000 2059.260000 ;
+ RECT 845.355000 2053.340000 846.620000 2053.820000 ;
+ RECT 845.355000 2042.460000 846.620000 2042.940000 ;
+ RECT 845.355000 2037.020000 846.620000 2037.500000 ;
+ RECT 845.355000 2031.580000 846.620000 2032.060000 ;
+ RECT 845.355000 2026.140000 846.620000 2026.620000 ;
+ RECT 845.355000 2020.700000 846.620000 2021.180000 ;
+ RECT 845.355000 2015.260000 846.620000 2015.740000 ;
+ RECT 845.355000 2004.380000 846.620000 2004.860000 ;
+ RECT 845.355000 2009.820000 846.620000 2010.300000 ;
+ RECT 845.355000 1998.940000 846.620000 1999.420000 ;
+ RECT 845.355000 1993.500000 846.620000 1993.980000 ;
+ RECT 845.355000 1988.060000 846.620000 1988.540000 ;
+ RECT 845.355000 1982.620000 846.620000 1983.100000 ;
+ RECT 845.355000 1977.180000 846.620000 1977.660000 ;
+ RECT 845.355000 1971.740000 846.620000 1972.220000 ;
+ RECT 845.355000 1960.860000 846.620000 1961.340000 ;
+ RECT 845.355000 1966.300000 846.620000 1966.780000 ;
+ RECT 845.355000 1955.420000 846.620000 1955.900000 ;
+ RECT 845.355000 2047.900000 846.620000 2048.380000 ;
+ RECT 1025.520000 1949.090000 1026.620000 2145.660000 ;
+ RECT 980.520000 1949.090000 981.620000 2145.660000 ;
+ RECT 1038.330000 1947.840000 1039.330000 2148.100000 ;
+ RECT 935.520000 1949.090000 936.620000 2145.660000 ;
+ RECT 890.520000 1949.090000 891.620000 2145.660000 ;
+ RECT 845.520000 1949.090000 846.620000 2145.660000 ;
+ RECT 841.690000 1947.840000 842.690000 2148.100000 ;
+ LAYER met3 ;
+ RECT 1025.520000 2140.380000 1026.620000 2140.860000 ;
+ RECT 1038.330000 2140.380000 1039.330000 2140.860000 ;
+ RECT 1038.330000 2129.500000 1039.330000 2129.980000 ;
+ RECT 1038.330000 2124.060000 1039.330000 2124.540000 ;
+ RECT 1038.330000 2134.940000 1039.330000 2135.420000 ;
+ RECT 1025.520000 2134.940000 1026.620000 2135.420000 ;
+ RECT 1025.520000 2129.500000 1026.620000 2129.980000 ;
+ RECT 1025.520000 2124.060000 1026.620000 2124.540000 ;
+ RECT 1025.520000 2113.180000 1026.620000 2113.660000 ;
+ RECT 1025.520000 2118.620000 1026.620000 2119.100000 ;
+ RECT 1038.330000 2113.180000 1039.330000 2113.660000 ;
+ RECT 1038.330000 2118.620000 1039.330000 2119.100000 ;
+ RECT 1025.520000 2102.300000 1026.620000 2102.780000 ;
+ RECT 1025.520000 2107.740000 1026.620000 2108.220000 ;
+ RECT 1038.330000 2102.300000 1039.330000 2102.780000 ;
+ RECT 1038.330000 2107.740000 1039.330000 2108.220000 ;
+ RECT 980.520000 2124.060000 981.620000 2124.540000 ;
+ RECT 980.520000 2129.500000 981.620000 2129.980000 ;
+ RECT 980.520000 2134.940000 981.620000 2135.420000 ;
+ RECT 980.520000 2140.380000 981.620000 2140.860000 ;
+ RECT 980.520000 2107.740000 981.620000 2108.220000 ;
+ RECT 980.520000 2102.300000 981.620000 2102.780000 ;
+ RECT 980.520000 2113.180000 981.620000 2113.660000 ;
+ RECT 980.520000 2118.620000 981.620000 2119.100000 ;
+ RECT 1038.330000 2091.420000 1039.330000 2091.900000 ;
+ RECT 1038.330000 2085.980000 1039.330000 2086.460000 ;
+ RECT 1038.330000 2096.860000 1039.330000 2097.340000 ;
+ RECT 1025.520000 2096.860000 1026.620000 2097.340000 ;
+ RECT 1025.520000 2091.420000 1026.620000 2091.900000 ;
+ RECT 1025.520000 2085.980000 1026.620000 2086.460000 ;
+ RECT 1025.520000 2075.100000 1026.620000 2075.580000 ;
+ RECT 1025.520000 2080.540000 1026.620000 2081.020000 ;
+ RECT 1038.330000 2075.100000 1039.330000 2075.580000 ;
+ RECT 1038.330000 2080.540000 1039.330000 2081.020000 ;
+ RECT 1038.330000 2064.220000 1039.330000 2064.700000 ;
+ RECT 1038.330000 2069.660000 1039.330000 2070.140000 ;
+ RECT 1025.520000 2069.660000 1026.620000 2070.140000 ;
+ RECT 1025.520000 2064.220000 1026.620000 2064.700000 ;
+ RECT 1025.520000 2053.340000 1026.620000 2053.820000 ;
+ RECT 1025.520000 2058.780000 1026.620000 2059.260000 ;
+ RECT 1038.330000 2053.340000 1039.330000 2053.820000 ;
+ RECT 1038.330000 2058.780000 1039.330000 2059.260000 ;
+ RECT 980.520000 2075.100000 981.620000 2075.580000 ;
+ RECT 980.520000 2080.540000 981.620000 2081.020000 ;
+ RECT 980.520000 2085.980000 981.620000 2086.460000 ;
+ RECT 980.520000 2091.420000 981.620000 2091.900000 ;
+ RECT 980.520000 2096.860000 981.620000 2097.340000 ;
+ RECT 980.520000 2053.340000 981.620000 2053.820000 ;
+ RECT 980.520000 2058.780000 981.620000 2059.260000 ;
+ RECT 980.520000 2064.220000 981.620000 2064.700000 ;
+ RECT 980.520000 2069.660000 981.620000 2070.140000 ;
+ RECT 935.520000 2129.500000 936.620000 2129.980000 ;
+ RECT 935.520000 2124.060000 936.620000 2124.540000 ;
+ RECT 935.520000 2134.940000 936.620000 2135.420000 ;
+ RECT 935.520000 2140.380000 936.620000 2140.860000 ;
+ RECT 890.520000 2124.060000 891.620000 2124.540000 ;
+ RECT 890.520000 2129.500000 891.620000 2129.980000 ;
+ RECT 890.520000 2134.940000 891.620000 2135.420000 ;
+ RECT 890.520000 2140.380000 891.620000 2140.860000 ;
+ RECT 935.520000 2102.300000 936.620000 2102.780000 ;
+ RECT 935.520000 2107.740000 936.620000 2108.220000 ;
+ RECT 935.520000 2113.180000 936.620000 2113.660000 ;
+ RECT 935.520000 2118.620000 936.620000 2119.100000 ;
+ RECT 890.520000 2102.300000 891.620000 2102.780000 ;
+ RECT 890.520000 2107.740000 891.620000 2108.220000 ;
+ RECT 890.520000 2113.180000 891.620000 2113.660000 ;
+ RECT 890.520000 2118.620000 891.620000 2119.100000 ;
+ RECT 841.690000 2140.380000 842.690000 2140.860000 ;
+ RECT 845.355000 2140.380000 846.620000 2140.860000 ;
+ RECT 841.690000 2129.500000 842.690000 2129.980000 ;
+ RECT 845.355000 2129.500000 846.620000 2129.980000 ;
+ RECT 841.690000 2134.940000 842.690000 2135.420000 ;
+ RECT 845.355000 2134.940000 846.620000 2135.420000 ;
+ RECT 841.690000 2124.060000 842.690000 2124.540000 ;
+ RECT 845.355000 2124.060000 846.620000 2124.540000 ;
+ RECT 841.690000 2118.620000 842.690000 2119.100000 ;
+ RECT 845.355000 2118.620000 846.620000 2119.100000 ;
+ RECT 841.690000 2113.180000 842.690000 2113.660000 ;
+ RECT 845.355000 2113.180000 846.620000 2113.660000 ;
+ RECT 841.690000 2107.740000 842.690000 2108.220000 ;
+ RECT 845.355000 2107.740000 846.620000 2108.220000 ;
+ RECT 841.690000 2102.300000 842.690000 2102.780000 ;
+ RECT 845.355000 2102.300000 846.620000 2102.780000 ;
+ RECT 935.520000 2075.100000 936.620000 2075.580000 ;
+ RECT 935.520000 2080.540000 936.620000 2081.020000 ;
+ RECT 935.520000 2085.980000 936.620000 2086.460000 ;
+ RECT 935.520000 2091.420000 936.620000 2091.900000 ;
+ RECT 935.520000 2096.860000 936.620000 2097.340000 ;
+ RECT 890.520000 2075.100000 891.620000 2075.580000 ;
+ RECT 890.520000 2080.540000 891.620000 2081.020000 ;
+ RECT 890.520000 2085.980000 891.620000 2086.460000 ;
+ RECT 890.520000 2091.420000 891.620000 2091.900000 ;
+ RECT 890.520000 2096.860000 891.620000 2097.340000 ;
+ RECT 935.520000 2053.340000 936.620000 2053.820000 ;
+ RECT 935.520000 2058.780000 936.620000 2059.260000 ;
+ RECT 935.520000 2064.220000 936.620000 2064.700000 ;
+ RECT 935.520000 2069.660000 936.620000 2070.140000 ;
+ RECT 890.520000 2053.340000 891.620000 2053.820000 ;
+ RECT 890.520000 2058.780000 891.620000 2059.260000 ;
+ RECT 890.520000 2064.220000 891.620000 2064.700000 ;
+ RECT 890.520000 2069.660000 891.620000 2070.140000 ;
+ RECT 841.690000 2096.860000 842.690000 2097.340000 ;
+ RECT 845.355000 2096.860000 846.620000 2097.340000 ;
+ RECT 841.690000 2085.980000 842.690000 2086.460000 ;
+ RECT 845.355000 2085.980000 846.620000 2086.460000 ;
+ RECT 841.690000 2091.420000 842.690000 2091.900000 ;
+ RECT 845.355000 2091.420000 846.620000 2091.900000 ;
+ RECT 841.690000 2080.540000 842.690000 2081.020000 ;
+ RECT 845.355000 2080.540000 846.620000 2081.020000 ;
+ RECT 841.690000 2075.100000 842.690000 2075.580000 ;
+ RECT 845.355000 2075.100000 846.620000 2075.580000 ;
+ RECT 841.690000 2069.660000 842.690000 2070.140000 ;
+ RECT 845.355000 2069.660000 846.620000 2070.140000 ;
+ RECT 841.690000 2064.220000 842.690000 2064.700000 ;
+ RECT 845.355000 2064.220000 846.620000 2064.700000 ;
+ RECT 841.690000 2058.780000 842.690000 2059.260000 ;
+ RECT 845.355000 2058.780000 846.620000 2059.260000 ;
+ RECT 841.690000 2053.340000 842.690000 2053.820000 ;
+ RECT 845.355000 2053.340000 846.620000 2053.820000 ;
+ RECT 1025.520000 2037.020000 1026.620000 2037.500000 ;
+ RECT 1025.520000 2042.460000 1026.620000 2042.940000 ;
+ RECT 1038.330000 2037.020000 1039.330000 2037.500000 ;
+ RECT 1038.330000 2042.460000 1039.330000 2042.940000 ;
+ RECT 1038.330000 2026.140000 1039.330000 2026.620000 ;
+ RECT 1038.330000 2031.580000 1039.330000 2032.060000 ;
+ RECT 1025.520000 2031.580000 1026.620000 2032.060000 ;
+ RECT 1025.520000 2026.140000 1026.620000 2026.620000 ;
+ RECT 1025.520000 2015.260000 1026.620000 2015.740000 ;
+ RECT 1025.520000 2020.700000 1026.620000 2021.180000 ;
+ RECT 1038.330000 2015.260000 1039.330000 2015.740000 ;
+ RECT 1038.330000 2020.700000 1039.330000 2021.180000 ;
+ RECT 1038.330000 2004.380000 1039.330000 2004.860000 ;
+ RECT 1038.330000 1998.940000 1039.330000 1999.420000 ;
+ RECT 1038.330000 2009.820000 1039.330000 2010.300000 ;
+ RECT 1025.520000 2009.820000 1026.620000 2010.300000 ;
+ RECT 1025.520000 2004.380000 1026.620000 2004.860000 ;
+ RECT 1025.520000 1998.940000 1026.620000 1999.420000 ;
+ RECT 980.520000 2026.140000 981.620000 2026.620000 ;
+ RECT 980.520000 2031.580000 981.620000 2032.060000 ;
+ RECT 980.520000 2037.020000 981.620000 2037.500000 ;
+ RECT 980.520000 2042.460000 981.620000 2042.940000 ;
+ RECT 980.520000 1998.940000 981.620000 1999.420000 ;
+ RECT 980.520000 2004.380000 981.620000 2004.860000 ;
+ RECT 980.520000 2009.820000 981.620000 2010.300000 ;
+ RECT 980.520000 2015.260000 981.620000 2015.740000 ;
+ RECT 980.520000 2020.700000 981.620000 2021.180000 ;
+ RECT 1025.520000 1988.060000 1026.620000 1988.540000 ;
+ RECT 1025.520000 1993.500000 1026.620000 1993.980000 ;
+ RECT 1038.330000 1988.060000 1039.330000 1988.540000 ;
+ RECT 1038.330000 1993.500000 1039.330000 1993.980000 ;
+ RECT 1025.520000 1977.180000 1026.620000 1977.660000 ;
+ RECT 1025.520000 1982.620000 1026.620000 1983.100000 ;
+ RECT 1038.330000 1977.180000 1039.330000 1977.660000 ;
+ RECT 1038.330000 1982.620000 1039.330000 1983.100000 ;
+ RECT 1038.330000 1966.300000 1039.330000 1966.780000 ;
+ RECT 1038.330000 1960.860000 1039.330000 1961.340000 ;
+ RECT 1038.330000 1971.740000 1039.330000 1972.220000 ;
+ RECT 1025.520000 1971.740000 1026.620000 1972.220000 ;
+ RECT 1025.520000 1966.300000 1026.620000 1966.780000 ;
+ RECT 1025.520000 1960.860000 1026.620000 1961.340000 ;
+ RECT 1025.520000 1955.420000 1026.620000 1955.900000 ;
+ RECT 1038.330000 1955.420000 1039.330000 1955.900000 ;
+ RECT 980.520000 1977.180000 981.620000 1977.660000 ;
+ RECT 980.520000 1982.620000 981.620000 1983.100000 ;
+ RECT 980.520000 1988.060000 981.620000 1988.540000 ;
+ RECT 980.520000 1993.500000 981.620000 1993.980000 ;
+ RECT 980.520000 1955.420000 981.620000 1955.900000 ;
+ RECT 980.520000 1960.860000 981.620000 1961.340000 ;
+ RECT 980.520000 1966.300000 981.620000 1966.780000 ;
+ RECT 980.520000 1971.740000 981.620000 1972.220000 ;
+ RECT 935.520000 2026.140000 936.620000 2026.620000 ;
+ RECT 935.520000 2031.580000 936.620000 2032.060000 ;
+ RECT 935.520000 2037.020000 936.620000 2037.500000 ;
+ RECT 935.520000 2042.460000 936.620000 2042.940000 ;
+ RECT 890.520000 2026.140000 891.620000 2026.620000 ;
+ RECT 890.520000 2031.580000 891.620000 2032.060000 ;
+ RECT 890.520000 2037.020000 891.620000 2037.500000 ;
+ RECT 890.520000 2042.460000 891.620000 2042.940000 ;
+ RECT 935.520000 1998.940000 936.620000 1999.420000 ;
+ RECT 935.520000 2004.380000 936.620000 2004.860000 ;
+ RECT 935.520000 2009.820000 936.620000 2010.300000 ;
+ RECT 935.520000 2015.260000 936.620000 2015.740000 ;
+ RECT 935.520000 2020.700000 936.620000 2021.180000 ;
+ RECT 890.520000 1998.940000 891.620000 1999.420000 ;
+ RECT 890.520000 2004.380000 891.620000 2004.860000 ;
+ RECT 890.520000 2009.820000 891.620000 2010.300000 ;
+ RECT 890.520000 2015.260000 891.620000 2015.740000 ;
+ RECT 890.520000 2020.700000 891.620000 2021.180000 ;
+ RECT 841.690000 2042.460000 842.690000 2042.940000 ;
+ RECT 845.355000 2042.460000 846.620000 2042.940000 ;
+ RECT 841.690000 2037.020000 842.690000 2037.500000 ;
+ RECT 845.355000 2037.020000 846.620000 2037.500000 ;
+ RECT 841.690000 2031.580000 842.690000 2032.060000 ;
+ RECT 845.355000 2031.580000 846.620000 2032.060000 ;
+ RECT 841.690000 2026.140000 842.690000 2026.620000 ;
+ RECT 845.355000 2026.140000 846.620000 2026.620000 ;
+ RECT 841.690000 2020.700000 842.690000 2021.180000 ;
+ RECT 845.355000 2020.700000 846.620000 2021.180000 ;
+ RECT 841.690000 2015.260000 842.690000 2015.740000 ;
+ RECT 845.355000 2015.260000 846.620000 2015.740000 ;
+ RECT 841.690000 2004.380000 842.690000 2004.860000 ;
+ RECT 845.355000 2004.380000 846.620000 2004.860000 ;
+ RECT 841.690000 2009.820000 842.690000 2010.300000 ;
+ RECT 845.355000 2009.820000 846.620000 2010.300000 ;
+ RECT 841.690000 1998.940000 842.690000 1999.420000 ;
+ RECT 845.355000 1998.940000 846.620000 1999.420000 ;
+ RECT 935.520000 1977.180000 936.620000 1977.660000 ;
+ RECT 935.520000 1982.620000 936.620000 1983.100000 ;
+ RECT 935.520000 1988.060000 936.620000 1988.540000 ;
+ RECT 935.520000 1993.500000 936.620000 1993.980000 ;
+ RECT 890.520000 1977.180000 891.620000 1977.660000 ;
+ RECT 890.520000 1982.620000 891.620000 1983.100000 ;
+ RECT 890.520000 1988.060000 891.620000 1988.540000 ;
+ RECT 890.520000 1993.500000 891.620000 1993.980000 ;
+ RECT 935.520000 1955.420000 936.620000 1955.900000 ;
+ RECT 935.520000 1960.860000 936.620000 1961.340000 ;
+ RECT 935.520000 1966.300000 936.620000 1966.780000 ;
+ RECT 935.520000 1971.740000 936.620000 1972.220000 ;
+ RECT 890.520000 1955.420000 891.620000 1955.900000 ;
+ RECT 890.520000 1960.860000 891.620000 1961.340000 ;
+ RECT 890.520000 1966.300000 891.620000 1966.780000 ;
+ RECT 890.520000 1971.740000 891.620000 1972.220000 ;
+ RECT 841.690000 1993.500000 842.690000 1993.980000 ;
+ RECT 845.355000 1993.500000 846.620000 1993.980000 ;
+ RECT 841.690000 1988.060000 842.690000 1988.540000 ;
+ RECT 845.355000 1988.060000 846.620000 1988.540000 ;
+ RECT 841.690000 1982.620000 842.690000 1983.100000 ;
+ RECT 845.355000 1982.620000 846.620000 1983.100000 ;
+ RECT 841.690000 1977.180000 842.690000 1977.660000 ;
+ RECT 845.355000 1977.180000 846.620000 1977.660000 ;
+ RECT 841.690000 1971.740000 842.690000 1972.220000 ;
+ RECT 845.355000 1971.740000 846.620000 1972.220000 ;
+ RECT 841.690000 1960.860000 842.690000 1961.340000 ;
+ RECT 845.355000 1960.860000 846.620000 1961.340000 ;
+ RECT 841.690000 1966.300000 842.690000 1966.780000 ;
+ RECT 845.355000 1966.300000 846.620000 1966.780000 ;
+ RECT 841.690000 1955.420000 842.690000 1955.900000 ;
+ RECT 845.355000 1955.420000 846.620000 1955.900000 ;
+ RECT 980.520000 2047.900000 981.620000 2048.380000 ;
+ RECT 1025.520000 2047.900000 1026.620000 2048.380000 ;
+ RECT 1038.330000 2047.900000 1039.330000 2048.380000 ;
+ RECT 890.520000 2047.900000 891.620000 2048.380000 ;
+ RECT 935.520000 2047.900000 936.620000 2048.380000 ;
+ RECT 841.690000 2047.900000 842.690000 2048.380000 ;
+ RECT 845.355000 2047.900000 846.620000 2048.380000 ;
+ RECT 840.460000 2144.660000 1040.560000 2145.660000 ;
+ RECT 840.460000 1949.090000 1040.560000 1950.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 1947.840000 842.690000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 2147.100000 842.690000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 1947.840000 1039.330000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 2147.100000 1039.330000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1949.090000 841.460000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1949.090000 1040.560000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2144.660000 841.460000 2145.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2144.660000 1040.560000 2145.660000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 1940.120000 846.620000 1940.600000 ;
+ RECT 845.355000 1929.240000 846.620000 1929.720000 ;
+ RECT 845.355000 1934.680000 846.620000 1935.160000 ;
+ RECT 845.355000 1923.800000 846.620000 1924.280000 ;
+ RECT 845.355000 1918.360000 846.620000 1918.840000 ;
+ RECT 845.355000 1912.920000 846.620000 1913.400000 ;
+ RECT 845.355000 1907.480000 846.620000 1907.960000 ;
+ RECT 845.355000 1902.040000 846.620000 1902.520000 ;
+ RECT 845.355000 1896.600000 846.620000 1897.080000 ;
+ RECT 845.355000 1885.720000 846.620000 1886.200000 ;
+ RECT 845.355000 1891.160000 846.620000 1891.640000 ;
+ RECT 845.355000 1880.280000 846.620000 1880.760000 ;
+ RECT 845.355000 1874.840000 846.620000 1875.320000 ;
+ RECT 845.355000 1869.400000 846.620000 1869.880000 ;
+ RECT 845.355000 1863.960000 846.620000 1864.440000 ;
+ RECT 845.355000 1858.520000 846.620000 1859.000000 ;
+ RECT 845.355000 1853.080000 846.620000 1853.560000 ;
+ RECT 845.355000 1842.200000 846.620000 1842.680000 ;
+ RECT 845.355000 1836.760000 846.620000 1837.240000 ;
+ RECT 845.355000 1831.320000 846.620000 1831.800000 ;
+ RECT 845.355000 1825.880000 846.620000 1826.360000 ;
+ RECT 845.355000 1820.440000 846.620000 1820.920000 ;
+ RECT 845.355000 1815.000000 846.620000 1815.480000 ;
+ RECT 845.355000 1804.120000 846.620000 1804.600000 ;
+ RECT 845.355000 1809.560000 846.620000 1810.040000 ;
+ RECT 845.355000 1798.680000 846.620000 1799.160000 ;
+ RECT 845.355000 1793.240000 846.620000 1793.720000 ;
+ RECT 845.355000 1787.800000 846.620000 1788.280000 ;
+ RECT 845.355000 1782.360000 846.620000 1782.840000 ;
+ RECT 845.355000 1776.920000 846.620000 1777.400000 ;
+ RECT 845.355000 1771.480000 846.620000 1771.960000 ;
+ RECT 845.355000 1760.600000 846.620000 1761.080000 ;
+ RECT 845.355000 1766.040000 846.620000 1766.520000 ;
+ RECT 845.355000 1755.160000 846.620000 1755.640000 ;
+ RECT 845.355000 1847.640000 846.620000 1848.120000 ;
+ RECT 1025.520000 1748.830000 1026.620000 1945.400000 ;
+ RECT 980.520000 1748.830000 981.620000 1945.400000 ;
+ RECT 1038.330000 1747.580000 1039.330000 1947.840000 ;
+ RECT 935.520000 1748.830000 936.620000 1945.400000 ;
+ RECT 890.520000 1748.830000 891.620000 1945.400000 ;
+ RECT 845.520000 1748.830000 846.620000 1945.400000 ;
+ RECT 841.690000 1747.580000 842.690000 1947.840000 ;
+ LAYER met3 ;
+ RECT 1025.520000 1940.120000 1026.620000 1940.600000 ;
+ RECT 1038.330000 1940.120000 1039.330000 1940.600000 ;
+ RECT 1038.330000 1929.240000 1039.330000 1929.720000 ;
+ RECT 1038.330000 1923.800000 1039.330000 1924.280000 ;
+ RECT 1038.330000 1934.680000 1039.330000 1935.160000 ;
+ RECT 1025.520000 1934.680000 1026.620000 1935.160000 ;
+ RECT 1025.520000 1929.240000 1026.620000 1929.720000 ;
+ RECT 1025.520000 1923.800000 1026.620000 1924.280000 ;
+ RECT 1025.520000 1912.920000 1026.620000 1913.400000 ;
+ RECT 1025.520000 1918.360000 1026.620000 1918.840000 ;
+ RECT 1038.330000 1912.920000 1039.330000 1913.400000 ;
+ RECT 1038.330000 1918.360000 1039.330000 1918.840000 ;
+ RECT 1025.520000 1902.040000 1026.620000 1902.520000 ;
+ RECT 1025.520000 1907.480000 1026.620000 1907.960000 ;
+ RECT 1038.330000 1902.040000 1039.330000 1902.520000 ;
+ RECT 1038.330000 1907.480000 1039.330000 1907.960000 ;
+ RECT 980.520000 1923.800000 981.620000 1924.280000 ;
+ RECT 980.520000 1929.240000 981.620000 1929.720000 ;
+ RECT 980.520000 1934.680000 981.620000 1935.160000 ;
+ RECT 980.520000 1940.120000 981.620000 1940.600000 ;
+ RECT 980.520000 1907.480000 981.620000 1907.960000 ;
+ RECT 980.520000 1902.040000 981.620000 1902.520000 ;
+ RECT 980.520000 1912.920000 981.620000 1913.400000 ;
+ RECT 980.520000 1918.360000 981.620000 1918.840000 ;
+ RECT 1038.330000 1891.160000 1039.330000 1891.640000 ;
+ RECT 1038.330000 1885.720000 1039.330000 1886.200000 ;
+ RECT 1038.330000 1896.600000 1039.330000 1897.080000 ;
+ RECT 1025.520000 1896.600000 1026.620000 1897.080000 ;
+ RECT 1025.520000 1891.160000 1026.620000 1891.640000 ;
+ RECT 1025.520000 1885.720000 1026.620000 1886.200000 ;
+ RECT 1025.520000 1874.840000 1026.620000 1875.320000 ;
+ RECT 1025.520000 1880.280000 1026.620000 1880.760000 ;
+ RECT 1038.330000 1874.840000 1039.330000 1875.320000 ;
+ RECT 1038.330000 1880.280000 1039.330000 1880.760000 ;
+ RECT 1038.330000 1863.960000 1039.330000 1864.440000 ;
+ RECT 1038.330000 1869.400000 1039.330000 1869.880000 ;
+ RECT 1025.520000 1869.400000 1026.620000 1869.880000 ;
+ RECT 1025.520000 1863.960000 1026.620000 1864.440000 ;
+ RECT 1025.520000 1853.080000 1026.620000 1853.560000 ;
+ RECT 1025.520000 1858.520000 1026.620000 1859.000000 ;
+ RECT 1038.330000 1853.080000 1039.330000 1853.560000 ;
+ RECT 1038.330000 1858.520000 1039.330000 1859.000000 ;
+ RECT 980.520000 1874.840000 981.620000 1875.320000 ;
+ RECT 980.520000 1880.280000 981.620000 1880.760000 ;
+ RECT 980.520000 1885.720000 981.620000 1886.200000 ;
+ RECT 980.520000 1891.160000 981.620000 1891.640000 ;
+ RECT 980.520000 1896.600000 981.620000 1897.080000 ;
+ RECT 980.520000 1853.080000 981.620000 1853.560000 ;
+ RECT 980.520000 1858.520000 981.620000 1859.000000 ;
+ RECT 980.520000 1863.960000 981.620000 1864.440000 ;
+ RECT 980.520000 1869.400000 981.620000 1869.880000 ;
+ RECT 935.520000 1929.240000 936.620000 1929.720000 ;
+ RECT 935.520000 1923.800000 936.620000 1924.280000 ;
+ RECT 935.520000 1934.680000 936.620000 1935.160000 ;
+ RECT 935.520000 1940.120000 936.620000 1940.600000 ;
+ RECT 890.520000 1923.800000 891.620000 1924.280000 ;
+ RECT 890.520000 1929.240000 891.620000 1929.720000 ;
+ RECT 890.520000 1934.680000 891.620000 1935.160000 ;
+ RECT 890.520000 1940.120000 891.620000 1940.600000 ;
+ RECT 935.520000 1902.040000 936.620000 1902.520000 ;
+ RECT 935.520000 1907.480000 936.620000 1907.960000 ;
+ RECT 935.520000 1912.920000 936.620000 1913.400000 ;
+ RECT 935.520000 1918.360000 936.620000 1918.840000 ;
+ RECT 890.520000 1902.040000 891.620000 1902.520000 ;
+ RECT 890.520000 1907.480000 891.620000 1907.960000 ;
+ RECT 890.520000 1912.920000 891.620000 1913.400000 ;
+ RECT 890.520000 1918.360000 891.620000 1918.840000 ;
+ RECT 841.690000 1940.120000 842.690000 1940.600000 ;
+ RECT 845.355000 1940.120000 846.620000 1940.600000 ;
+ RECT 841.690000 1929.240000 842.690000 1929.720000 ;
+ RECT 845.355000 1929.240000 846.620000 1929.720000 ;
+ RECT 841.690000 1934.680000 842.690000 1935.160000 ;
+ RECT 845.355000 1934.680000 846.620000 1935.160000 ;
+ RECT 841.690000 1923.800000 842.690000 1924.280000 ;
+ RECT 845.355000 1923.800000 846.620000 1924.280000 ;
+ RECT 841.690000 1918.360000 842.690000 1918.840000 ;
+ RECT 845.355000 1918.360000 846.620000 1918.840000 ;
+ RECT 841.690000 1912.920000 842.690000 1913.400000 ;
+ RECT 845.355000 1912.920000 846.620000 1913.400000 ;
+ RECT 841.690000 1907.480000 842.690000 1907.960000 ;
+ RECT 845.355000 1907.480000 846.620000 1907.960000 ;
+ RECT 841.690000 1902.040000 842.690000 1902.520000 ;
+ RECT 845.355000 1902.040000 846.620000 1902.520000 ;
+ RECT 935.520000 1874.840000 936.620000 1875.320000 ;
+ RECT 935.520000 1880.280000 936.620000 1880.760000 ;
+ RECT 935.520000 1885.720000 936.620000 1886.200000 ;
+ RECT 935.520000 1891.160000 936.620000 1891.640000 ;
+ RECT 935.520000 1896.600000 936.620000 1897.080000 ;
+ RECT 890.520000 1874.840000 891.620000 1875.320000 ;
+ RECT 890.520000 1880.280000 891.620000 1880.760000 ;
+ RECT 890.520000 1885.720000 891.620000 1886.200000 ;
+ RECT 890.520000 1891.160000 891.620000 1891.640000 ;
+ RECT 890.520000 1896.600000 891.620000 1897.080000 ;
+ RECT 935.520000 1853.080000 936.620000 1853.560000 ;
+ RECT 935.520000 1858.520000 936.620000 1859.000000 ;
+ RECT 935.520000 1863.960000 936.620000 1864.440000 ;
+ RECT 935.520000 1869.400000 936.620000 1869.880000 ;
+ RECT 890.520000 1853.080000 891.620000 1853.560000 ;
+ RECT 890.520000 1858.520000 891.620000 1859.000000 ;
+ RECT 890.520000 1863.960000 891.620000 1864.440000 ;
+ RECT 890.520000 1869.400000 891.620000 1869.880000 ;
+ RECT 841.690000 1896.600000 842.690000 1897.080000 ;
+ RECT 845.355000 1896.600000 846.620000 1897.080000 ;
+ RECT 841.690000 1885.720000 842.690000 1886.200000 ;
+ RECT 845.355000 1885.720000 846.620000 1886.200000 ;
+ RECT 841.690000 1891.160000 842.690000 1891.640000 ;
+ RECT 845.355000 1891.160000 846.620000 1891.640000 ;
+ RECT 841.690000 1880.280000 842.690000 1880.760000 ;
+ RECT 845.355000 1880.280000 846.620000 1880.760000 ;
+ RECT 841.690000 1874.840000 842.690000 1875.320000 ;
+ RECT 845.355000 1874.840000 846.620000 1875.320000 ;
+ RECT 841.690000 1869.400000 842.690000 1869.880000 ;
+ RECT 845.355000 1869.400000 846.620000 1869.880000 ;
+ RECT 841.690000 1863.960000 842.690000 1864.440000 ;
+ RECT 845.355000 1863.960000 846.620000 1864.440000 ;
+ RECT 841.690000 1858.520000 842.690000 1859.000000 ;
+ RECT 845.355000 1858.520000 846.620000 1859.000000 ;
+ RECT 841.690000 1853.080000 842.690000 1853.560000 ;
+ RECT 845.355000 1853.080000 846.620000 1853.560000 ;
+ RECT 1025.520000 1836.760000 1026.620000 1837.240000 ;
+ RECT 1025.520000 1842.200000 1026.620000 1842.680000 ;
+ RECT 1038.330000 1836.760000 1039.330000 1837.240000 ;
+ RECT 1038.330000 1842.200000 1039.330000 1842.680000 ;
+ RECT 1038.330000 1825.880000 1039.330000 1826.360000 ;
+ RECT 1038.330000 1831.320000 1039.330000 1831.800000 ;
+ RECT 1025.520000 1831.320000 1026.620000 1831.800000 ;
+ RECT 1025.520000 1825.880000 1026.620000 1826.360000 ;
+ RECT 1025.520000 1815.000000 1026.620000 1815.480000 ;
+ RECT 1025.520000 1820.440000 1026.620000 1820.920000 ;
+ RECT 1038.330000 1815.000000 1039.330000 1815.480000 ;
+ RECT 1038.330000 1820.440000 1039.330000 1820.920000 ;
+ RECT 1038.330000 1804.120000 1039.330000 1804.600000 ;
+ RECT 1038.330000 1798.680000 1039.330000 1799.160000 ;
+ RECT 1038.330000 1809.560000 1039.330000 1810.040000 ;
+ RECT 1025.520000 1809.560000 1026.620000 1810.040000 ;
+ RECT 1025.520000 1804.120000 1026.620000 1804.600000 ;
+ RECT 1025.520000 1798.680000 1026.620000 1799.160000 ;
+ RECT 980.520000 1825.880000 981.620000 1826.360000 ;
+ RECT 980.520000 1831.320000 981.620000 1831.800000 ;
+ RECT 980.520000 1836.760000 981.620000 1837.240000 ;
+ RECT 980.520000 1842.200000 981.620000 1842.680000 ;
+ RECT 980.520000 1798.680000 981.620000 1799.160000 ;
+ RECT 980.520000 1804.120000 981.620000 1804.600000 ;
+ RECT 980.520000 1809.560000 981.620000 1810.040000 ;
+ RECT 980.520000 1815.000000 981.620000 1815.480000 ;
+ RECT 980.520000 1820.440000 981.620000 1820.920000 ;
+ RECT 1025.520000 1787.800000 1026.620000 1788.280000 ;
+ RECT 1025.520000 1793.240000 1026.620000 1793.720000 ;
+ RECT 1038.330000 1787.800000 1039.330000 1788.280000 ;
+ RECT 1038.330000 1793.240000 1039.330000 1793.720000 ;
+ RECT 1025.520000 1776.920000 1026.620000 1777.400000 ;
+ RECT 1025.520000 1782.360000 1026.620000 1782.840000 ;
+ RECT 1038.330000 1776.920000 1039.330000 1777.400000 ;
+ RECT 1038.330000 1782.360000 1039.330000 1782.840000 ;
+ RECT 1038.330000 1766.040000 1039.330000 1766.520000 ;
+ RECT 1038.330000 1760.600000 1039.330000 1761.080000 ;
+ RECT 1038.330000 1771.480000 1039.330000 1771.960000 ;
+ RECT 1025.520000 1771.480000 1026.620000 1771.960000 ;
+ RECT 1025.520000 1766.040000 1026.620000 1766.520000 ;
+ RECT 1025.520000 1760.600000 1026.620000 1761.080000 ;
+ RECT 1025.520000 1755.160000 1026.620000 1755.640000 ;
+ RECT 1038.330000 1755.160000 1039.330000 1755.640000 ;
+ RECT 980.520000 1776.920000 981.620000 1777.400000 ;
+ RECT 980.520000 1782.360000 981.620000 1782.840000 ;
+ RECT 980.520000 1787.800000 981.620000 1788.280000 ;
+ RECT 980.520000 1793.240000 981.620000 1793.720000 ;
+ RECT 980.520000 1755.160000 981.620000 1755.640000 ;
+ RECT 980.520000 1760.600000 981.620000 1761.080000 ;
+ RECT 980.520000 1766.040000 981.620000 1766.520000 ;
+ RECT 980.520000 1771.480000 981.620000 1771.960000 ;
+ RECT 935.520000 1825.880000 936.620000 1826.360000 ;
+ RECT 935.520000 1831.320000 936.620000 1831.800000 ;
+ RECT 935.520000 1836.760000 936.620000 1837.240000 ;
+ RECT 935.520000 1842.200000 936.620000 1842.680000 ;
+ RECT 890.520000 1825.880000 891.620000 1826.360000 ;
+ RECT 890.520000 1831.320000 891.620000 1831.800000 ;
+ RECT 890.520000 1836.760000 891.620000 1837.240000 ;
+ RECT 890.520000 1842.200000 891.620000 1842.680000 ;
+ RECT 935.520000 1798.680000 936.620000 1799.160000 ;
+ RECT 935.520000 1804.120000 936.620000 1804.600000 ;
+ RECT 935.520000 1809.560000 936.620000 1810.040000 ;
+ RECT 935.520000 1815.000000 936.620000 1815.480000 ;
+ RECT 935.520000 1820.440000 936.620000 1820.920000 ;
+ RECT 890.520000 1798.680000 891.620000 1799.160000 ;
+ RECT 890.520000 1804.120000 891.620000 1804.600000 ;
+ RECT 890.520000 1809.560000 891.620000 1810.040000 ;
+ RECT 890.520000 1815.000000 891.620000 1815.480000 ;
+ RECT 890.520000 1820.440000 891.620000 1820.920000 ;
+ RECT 841.690000 1842.200000 842.690000 1842.680000 ;
+ RECT 845.355000 1842.200000 846.620000 1842.680000 ;
+ RECT 841.690000 1836.760000 842.690000 1837.240000 ;
+ RECT 845.355000 1836.760000 846.620000 1837.240000 ;
+ RECT 841.690000 1831.320000 842.690000 1831.800000 ;
+ RECT 845.355000 1831.320000 846.620000 1831.800000 ;
+ RECT 841.690000 1825.880000 842.690000 1826.360000 ;
+ RECT 845.355000 1825.880000 846.620000 1826.360000 ;
+ RECT 841.690000 1820.440000 842.690000 1820.920000 ;
+ RECT 845.355000 1820.440000 846.620000 1820.920000 ;
+ RECT 841.690000 1815.000000 842.690000 1815.480000 ;
+ RECT 845.355000 1815.000000 846.620000 1815.480000 ;
+ RECT 841.690000 1804.120000 842.690000 1804.600000 ;
+ RECT 845.355000 1804.120000 846.620000 1804.600000 ;
+ RECT 841.690000 1809.560000 842.690000 1810.040000 ;
+ RECT 845.355000 1809.560000 846.620000 1810.040000 ;
+ RECT 841.690000 1798.680000 842.690000 1799.160000 ;
+ RECT 845.355000 1798.680000 846.620000 1799.160000 ;
+ RECT 935.520000 1776.920000 936.620000 1777.400000 ;
+ RECT 935.520000 1782.360000 936.620000 1782.840000 ;
+ RECT 935.520000 1787.800000 936.620000 1788.280000 ;
+ RECT 935.520000 1793.240000 936.620000 1793.720000 ;
+ RECT 890.520000 1776.920000 891.620000 1777.400000 ;
+ RECT 890.520000 1782.360000 891.620000 1782.840000 ;
+ RECT 890.520000 1787.800000 891.620000 1788.280000 ;
+ RECT 890.520000 1793.240000 891.620000 1793.720000 ;
+ RECT 935.520000 1755.160000 936.620000 1755.640000 ;
+ RECT 935.520000 1760.600000 936.620000 1761.080000 ;
+ RECT 935.520000 1766.040000 936.620000 1766.520000 ;
+ RECT 935.520000 1771.480000 936.620000 1771.960000 ;
+ RECT 890.520000 1755.160000 891.620000 1755.640000 ;
+ RECT 890.520000 1760.600000 891.620000 1761.080000 ;
+ RECT 890.520000 1766.040000 891.620000 1766.520000 ;
+ RECT 890.520000 1771.480000 891.620000 1771.960000 ;
+ RECT 841.690000 1793.240000 842.690000 1793.720000 ;
+ RECT 845.355000 1793.240000 846.620000 1793.720000 ;
+ RECT 841.690000 1787.800000 842.690000 1788.280000 ;
+ RECT 845.355000 1787.800000 846.620000 1788.280000 ;
+ RECT 841.690000 1782.360000 842.690000 1782.840000 ;
+ RECT 845.355000 1782.360000 846.620000 1782.840000 ;
+ RECT 841.690000 1776.920000 842.690000 1777.400000 ;
+ RECT 845.355000 1776.920000 846.620000 1777.400000 ;
+ RECT 841.690000 1771.480000 842.690000 1771.960000 ;
+ RECT 845.355000 1771.480000 846.620000 1771.960000 ;
+ RECT 841.690000 1760.600000 842.690000 1761.080000 ;
+ RECT 845.355000 1760.600000 846.620000 1761.080000 ;
+ RECT 841.690000 1766.040000 842.690000 1766.520000 ;
+ RECT 845.355000 1766.040000 846.620000 1766.520000 ;
+ RECT 841.690000 1755.160000 842.690000 1755.640000 ;
+ RECT 845.355000 1755.160000 846.620000 1755.640000 ;
+ RECT 980.520000 1847.640000 981.620000 1848.120000 ;
+ RECT 1025.520000 1847.640000 1026.620000 1848.120000 ;
+ RECT 1038.330000 1847.640000 1039.330000 1848.120000 ;
+ RECT 890.520000 1847.640000 891.620000 1848.120000 ;
+ RECT 935.520000 1847.640000 936.620000 1848.120000 ;
+ RECT 841.690000 1847.640000 842.690000 1848.120000 ;
+ RECT 845.355000 1847.640000 846.620000 1848.120000 ;
+ RECT 840.460000 1944.400000 1040.560000 1945.400000 ;
+ RECT 840.460000 1748.830000 1040.560000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 1747.580000 842.690000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 1946.840000 842.690000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 1747.580000 1039.330000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 1946.840000 1039.330000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1748.830000 841.460000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1748.830000 1040.560000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1944.400000 841.460000 1945.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1944.400000 1040.560000 1945.400000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 845.355000 1739.860000 846.620000 1740.340000 ;
+ RECT 845.355000 1728.980000 846.620000 1729.460000 ;
+ RECT 845.355000 1734.420000 846.620000 1734.900000 ;
+ RECT 845.355000 1723.540000 846.620000 1724.020000 ;
+ RECT 845.355000 1718.100000 846.620000 1718.580000 ;
+ RECT 845.355000 1712.660000 846.620000 1713.140000 ;
+ RECT 845.355000 1707.220000 846.620000 1707.700000 ;
+ RECT 845.355000 1701.780000 846.620000 1702.260000 ;
+ RECT 845.355000 1696.340000 846.620000 1696.820000 ;
+ RECT 845.355000 1685.460000 846.620000 1685.940000 ;
+ RECT 845.355000 1690.900000 846.620000 1691.380000 ;
+ RECT 845.355000 1680.020000 846.620000 1680.500000 ;
+ RECT 845.355000 1674.580000 846.620000 1675.060000 ;
+ RECT 845.355000 1669.140000 846.620000 1669.620000 ;
+ RECT 845.355000 1663.700000 846.620000 1664.180000 ;
+ RECT 845.355000 1658.260000 846.620000 1658.740000 ;
+ RECT 845.355000 1652.820000 846.620000 1653.300000 ;
+ RECT 845.355000 1641.940000 846.620000 1642.420000 ;
+ RECT 845.355000 1636.500000 846.620000 1636.980000 ;
+ RECT 845.355000 1631.060000 846.620000 1631.540000 ;
+ RECT 845.355000 1625.620000 846.620000 1626.100000 ;
+ RECT 845.355000 1620.180000 846.620000 1620.660000 ;
+ RECT 845.355000 1614.740000 846.620000 1615.220000 ;
+ RECT 845.355000 1603.860000 846.620000 1604.340000 ;
+ RECT 845.355000 1609.300000 846.620000 1609.780000 ;
+ RECT 845.355000 1598.420000 846.620000 1598.900000 ;
+ RECT 845.355000 1592.980000 846.620000 1593.460000 ;
+ RECT 845.355000 1587.540000 846.620000 1588.020000 ;
+ RECT 845.355000 1582.100000 846.620000 1582.580000 ;
+ RECT 845.355000 1576.660000 846.620000 1577.140000 ;
+ RECT 845.355000 1571.220000 846.620000 1571.700000 ;
+ RECT 845.355000 1560.340000 846.620000 1560.820000 ;
+ RECT 845.355000 1565.780000 846.620000 1566.260000 ;
+ RECT 845.355000 1554.900000 846.620000 1555.380000 ;
+ RECT 845.355000 1647.380000 846.620000 1647.860000 ;
+ RECT 1025.520000 1548.570000 1026.620000 1745.140000 ;
+ RECT 980.520000 1548.570000 981.620000 1745.140000 ;
+ RECT 1038.330000 1547.320000 1039.330000 1747.580000 ;
+ RECT 935.520000 1548.570000 936.620000 1745.140000 ;
+ RECT 890.520000 1548.570000 891.620000 1745.140000 ;
+ RECT 845.520000 1548.570000 846.620000 1745.140000 ;
+ RECT 841.690000 1547.320000 842.690000 1747.580000 ;
+ LAYER met3 ;
+ RECT 1025.520000 1739.860000 1026.620000 1740.340000 ;
+ RECT 1038.330000 1739.860000 1039.330000 1740.340000 ;
+ RECT 1038.330000 1728.980000 1039.330000 1729.460000 ;
+ RECT 1038.330000 1723.540000 1039.330000 1724.020000 ;
+ RECT 1038.330000 1734.420000 1039.330000 1734.900000 ;
+ RECT 1025.520000 1734.420000 1026.620000 1734.900000 ;
+ RECT 1025.520000 1728.980000 1026.620000 1729.460000 ;
+ RECT 1025.520000 1723.540000 1026.620000 1724.020000 ;
+ RECT 1025.520000 1712.660000 1026.620000 1713.140000 ;
+ RECT 1025.520000 1718.100000 1026.620000 1718.580000 ;
+ RECT 1038.330000 1712.660000 1039.330000 1713.140000 ;
+ RECT 1038.330000 1718.100000 1039.330000 1718.580000 ;
+ RECT 1025.520000 1701.780000 1026.620000 1702.260000 ;
+ RECT 1025.520000 1707.220000 1026.620000 1707.700000 ;
+ RECT 1038.330000 1701.780000 1039.330000 1702.260000 ;
+ RECT 1038.330000 1707.220000 1039.330000 1707.700000 ;
+ RECT 980.520000 1723.540000 981.620000 1724.020000 ;
+ RECT 980.520000 1728.980000 981.620000 1729.460000 ;
+ RECT 980.520000 1734.420000 981.620000 1734.900000 ;
+ RECT 980.520000 1739.860000 981.620000 1740.340000 ;
+ RECT 980.520000 1707.220000 981.620000 1707.700000 ;
+ RECT 980.520000 1701.780000 981.620000 1702.260000 ;
+ RECT 980.520000 1712.660000 981.620000 1713.140000 ;
+ RECT 980.520000 1718.100000 981.620000 1718.580000 ;
+ RECT 1038.330000 1690.900000 1039.330000 1691.380000 ;
+ RECT 1038.330000 1685.460000 1039.330000 1685.940000 ;
+ RECT 1038.330000 1696.340000 1039.330000 1696.820000 ;
+ RECT 1025.520000 1696.340000 1026.620000 1696.820000 ;
+ RECT 1025.520000 1690.900000 1026.620000 1691.380000 ;
+ RECT 1025.520000 1685.460000 1026.620000 1685.940000 ;
+ RECT 1025.520000 1674.580000 1026.620000 1675.060000 ;
+ RECT 1025.520000 1680.020000 1026.620000 1680.500000 ;
+ RECT 1038.330000 1674.580000 1039.330000 1675.060000 ;
+ RECT 1038.330000 1680.020000 1039.330000 1680.500000 ;
+ RECT 1038.330000 1663.700000 1039.330000 1664.180000 ;
+ RECT 1038.330000 1669.140000 1039.330000 1669.620000 ;
+ RECT 1025.520000 1669.140000 1026.620000 1669.620000 ;
+ RECT 1025.520000 1663.700000 1026.620000 1664.180000 ;
+ RECT 1025.520000 1652.820000 1026.620000 1653.300000 ;
+ RECT 1025.520000 1658.260000 1026.620000 1658.740000 ;
+ RECT 1038.330000 1652.820000 1039.330000 1653.300000 ;
+ RECT 1038.330000 1658.260000 1039.330000 1658.740000 ;
+ RECT 980.520000 1674.580000 981.620000 1675.060000 ;
+ RECT 980.520000 1680.020000 981.620000 1680.500000 ;
+ RECT 980.520000 1685.460000 981.620000 1685.940000 ;
+ RECT 980.520000 1690.900000 981.620000 1691.380000 ;
+ RECT 980.520000 1696.340000 981.620000 1696.820000 ;
+ RECT 980.520000 1652.820000 981.620000 1653.300000 ;
+ RECT 980.520000 1658.260000 981.620000 1658.740000 ;
+ RECT 980.520000 1663.700000 981.620000 1664.180000 ;
+ RECT 980.520000 1669.140000 981.620000 1669.620000 ;
+ RECT 935.520000 1728.980000 936.620000 1729.460000 ;
+ RECT 935.520000 1723.540000 936.620000 1724.020000 ;
+ RECT 935.520000 1734.420000 936.620000 1734.900000 ;
+ RECT 935.520000 1739.860000 936.620000 1740.340000 ;
+ RECT 890.520000 1723.540000 891.620000 1724.020000 ;
+ RECT 890.520000 1728.980000 891.620000 1729.460000 ;
+ RECT 890.520000 1734.420000 891.620000 1734.900000 ;
+ RECT 890.520000 1739.860000 891.620000 1740.340000 ;
+ RECT 935.520000 1701.780000 936.620000 1702.260000 ;
+ RECT 935.520000 1707.220000 936.620000 1707.700000 ;
+ RECT 935.520000 1712.660000 936.620000 1713.140000 ;
+ RECT 935.520000 1718.100000 936.620000 1718.580000 ;
+ RECT 890.520000 1701.780000 891.620000 1702.260000 ;
+ RECT 890.520000 1707.220000 891.620000 1707.700000 ;
+ RECT 890.520000 1712.660000 891.620000 1713.140000 ;
+ RECT 890.520000 1718.100000 891.620000 1718.580000 ;
+ RECT 841.690000 1739.860000 842.690000 1740.340000 ;
+ RECT 845.355000 1739.860000 846.620000 1740.340000 ;
+ RECT 841.690000 1728.980000 842.690000 1729.460000 ;
+ RECT 845.355000 1728.980000 846.620000 1729.460000 ;
+ RECT 841.690000 1734.420000 842.690000 1734.900000 ;
+ RECT 845.355000 1734.420000 846.620000 1734.900000 ;
+ RECT 841.690000 1723.540000 842.690000 1724.020000 ;
+ RECT 845.355000 1723.540000 846.620000 1724.020000 ;
+ RECT 841.690000 1718.100000 842.690000 1718.580000 ;
+ RECT 845.355000 1718.100000 846.620000 1718.580000 ;
+ RECT 841.690000 1712.660000 842.690000 1713.140000 ;
+ RECT 845.355000 1712.660000 846.620000 1713.140000 ;
+ RECT 841.690000 1707.220000 842.690000 1707.700000 ;
+ RECT 845.355000 1707.220000 846.620000 1707.700000 ;
+ RECT 841.690000 1701.780000 842.690000 1702.260000 ;
+ RECT 845.355000 1701.780000 846.620000 1702.260000 ;
+ RECT 935.520000 1674.580000 936.620000 1675.060000 ;
+ RECT 935.520000 1680.020000 936.620000 1680.500000 ;
+ RECT 935.520000 1685.460000 936.620000 1685.940000 ;
+ RECT 935.520000 1690.900000 936.620000 1691.380000 ;
+ RECT 935.520000 1696.340000 936.620000 1696.820000 ;
+ RECT 890.520000 1674.580000 891.620000 1675.060000 ;
+ RECT 890.520000 1680.020000 891.620000 1680.500000 ;
+ RECT 890.520000 1685.460000 891.620000 1685.940000 ;
+ RECT 890.520000 1690.900000 891.620000 1691.380000 ;
+ RECT 890.520000 1696.340000 891.620000 1696.820000 ;
+ RECT 935.520000 1652.820000 936.620000 1653.300000 ;
+ RECT 935.520000 1658.260000 936.620000 1658.740000 ;
+ RECT 935.520000 1663.700000 936.620000 1664.180000 ;
+ RECT 935.520000 1669.140000 936.620000 1669.620000 ;
+ RECT 890.520000 1652.820000 891.620000 1653.300000 ;
+ RECT 890.520000 1658.260000 891.620000 1658.740000 ;
+ RECT 890.520000 1663.700000 891.620000 1664.180000 ;
+ RECT 890.520000 1669.140000 891.620000 1669.620000 ;
+ RECT 841.690000 1696.340000 842.690000 1696.820000 ;
+ RECT 845.355000 1696.340000 846.620000 1696.820000 ;
+ RECT 841.690000 1685.460000 842.690000 1685.940000 ;
+ RECT 845.355000 1685.460000 846.620000 1685.940000 ;
+ RECT 841.690000 1690.900000 842.690000 1691.380000 ;
+ RECT 845.355000 1690.900000 846.620000 1691.380000 ;
+ RECT 841.690000 1680.020000 842.690000 1680.500000 ;
+ RECT 845.355000 1680.020000 846.620000 1680.500000 ;
+ RECT 841.690000 1674.580000 842.690000 1675.060000 ;
+ RECT 845.355000 1674.580000 846.620000 1675.060000 ;
+ RECT 841.690000 1669.140000 842.690000 1669.620000 ;
+ RECT 845.355000 1669.140000 846.620000 1669.620000 ;
+ RECT 841.690000 1663.700000 842.690000 1664.180000 ;
+ RECT 845.355000 1663.700000 846.620000 1664.180000 ;
+ RECT 841.690000 1658.260000 842.690000 1658.740000 ;
+ RECT 845.355000 1658.260000 846.620000 1658.740000 ;
+ RECT 841.690000 1652.820000 842.690000 1653.300000 ;
+ RECT 845.355000 1652.820000 846.620000 1653.300000 ;
+ RECT 1025.520000 1636.500000 1026.620000 1636.980000 ;
+ RECT 1025.520000 1641.940000 1026.620000 1642.420000 ;
+ RECT 1038.330000 1636.500000 1039.330000 1636.980000 ;
+ RECT 1038.330000 1641.940000 1039.330000 1642.420000 ;
+ RECT 1038.330000 1625.620000 1039.330000 1626.100000 ;
+ RECT 1038.330000 1631.060000 1039.330000 1631.540000 ;
+ RECT 1025.520000 1631.060000 1026.620000 1631.540000 ;
+ RECT 1025.520000 1625.620000 1026.620000 1626.100000 ;
+ RECT 1025.520000 1614.740000 1026.620000 1615.220000 ;
+ RECT 1025.520000 1620.180000 1026.620000 1620.660000 ;
+ RECT 1038.330000 1614.740000 1039.330000 1615.220000 ;
+ RECT 1038.330000 1620.180000 1039.330000 1620.660000 ;
+ RECT 1038.330000 1603.860000 1039.330000 1604.340000 ;
+ RECT 1038.330000 1598.420000 1039.330000 1598.900000 ;
+ RECT 1038.330000 1609.300000 1039.330000 1609.780000 ;
+ RECT 1025.520000 1609.300000 1026.620000 1609.780000 ;
+ RECT 1025.520000 1603.860000 1026.620000 1604.340000 ;
+ RECT 1025.520000 1598.420000 1026.620000 1598.900000 ;
+ RECT 980.520000 1625.620000 981.620000 1626.100000 ;
+ RECT 980.520000 1631.060000 981.620000 1631.540000 ;
+ RECT 980.520000 1636.500000 981.620000 1636.980000 ;
+ RECT 980.520000 1641.940000 981.620000 1642.420000 ;
+ RECT 980.520000 1598.420000 981.620000 1598.900000 ;
+ RECT 980.520000 1603.860000 981.620000 1604.340000 ;
+ RECT 980.520000 1609.300000 981.620000 1609.780000 ;
+ RECT 980.520000 1614.740000 981.620000 1615.220000 ;
+ RECT 980.520000 1620.180000 981.620000 1620.660000 ;
+ RECT 1025.520000 1587.540000 1026.620000 1588.020000 ;
+ RECT 1025.520000 1592.980000 1026.620000 1593.460000 ;
+ RECT 1038.330000 1587.540000 1039.330000 1588.020000 ;
+ RECT 1038.330000 1592.980000 1039.330000 1593.460000 ;
+ RECT 1025.520000 1576.660000 1026.620000 1577.140000 ;
+ RECT 1025.520000 1582.100000 1026.620000 1582.580000 ;
+ RECT 1038.330000 1576.660000 1039.330000 1577.140000 ;
+ RECT 1038.330000 1582.100000 1039.330000 1582.580000 ;
+ RECT 1038.330000 1565.780000 1039.330000 1566.260000 ;
+ RECT 1038.330000 1560.340000 1039.330000 1560.820000 ;
+ RECT 1038.330000 1571.220000 1039.330000 1571.700000 ;
+ RECT 1025.520000 1571.220000 1026.620000 1571.700000 ;
+ RECT 1025.520000 1565.780000 1026.620000 1566.260000 ;
+ RECT 1025.520000 1560.340000 1026.620000 1560.820000 ;
+ RECT 1025.520000 1554.900000 1026.620000 1555.380000 ;
+ RECT 1038.330000 1554.900000 1039.330000 1555.380000 ;
+ RECT 980.520000 1576.660000 981.620000 1577.140000 ;
+ RECT 980.520000 1582.100000 981.620000 1582.580000 ;
+ RECT 980.520000 1587.540000 981.620000 1588.020000 ;
+ RECT 980.520000 1592.980000 981.620000 1593.460000 ;
+ RECT 980.520000 1554.900000 981.620000 1555.380000 ;
+ RECT 980.520000 1560.340000 981.620000 1560.820000 ;
+ RECT 980.520000 1565.780000 981.620000 1566.260000 ;
+ RECT 980.520000 1571.220000 981.620000 1571.700000 ;
+ RECT 935.520000 1625.620000 936.620000 1626.100000 ;
+ RECT 935.520000 1631.060000 936.620000 1631.540000 ;
+ RECT 935.520000 1636.500000 936.620000 1636.980000 ;
+ RECT 935.520000 1641.940000 936.620000 1642.420000 ;
+ RECT 890.520000 1625.620000 891.620000 1626.100000 ;
+ RECT 890.520000 1631.060000 891.620000 1631.540000 ;
+ RECT 890.520000 1636.500000 891.620000 1636.980000 ;
+ RECT 890.520000 1641.940000 891.620000 1642.420000 ;
+ RECT 935.520000 1598.420000 936.620000 1598.900000 ;
+ RECT 935.520000 1603.860000 936.620000 1604.340000 ;
+ RECT 935.520000 1609.300000 936.620000 1609.780000 ;
+ RECT 935.520000 1614.740000 936.620000 1615.220000 ;
+ RECT 935.520000 1620.180000 936.620000 1620.660000 ;
+ RECT 890.520000 1598.420000 891.620000 1598.900000 ;
+ RECT 890.520000 1603.860000 891.620000 1604.340000 ;
+ RECT 890.520000 1609.300000 891.620000 1609.780000 ;
+ RECT 890.520000 1614.740000 891.620000 1615.220000 ;
+ RECT 890.520000 1620.180000 891.620000 1620.660000 ;
+ RECT 841.690000 1641.940000 842.690000 1642.420000 ;
+ RECT 845.355000 1641.940000 846.620000 1642.420000 ;
+ RECT 841.690000 1636.500000 842.690000 1636.980000 ;
+ RECT 845.355000 1636.500000 846.620000 1636.980000 ;
+ RECT 841.690000 1631.060000 842.690000 1631.540000 ;
+ RECT 845.355000 1631.060000 846.620000 1631.540000 ;
+ RECT 841.690000 1625.620000 842.690000 1626.100000 ;
+ RECT 845.355000 1625.620000 846.620000 1626.100000 ;
+ RECT 841.690000 1620.180000 842.690000 1620.660000 ;
+ RECT 845.355000 1620.180000 846.620000 1620.660000 ;
+ RECT 841.690000 1614.740000 842.690000 1615.220000 ;
+ RECT 845.355000 1614.740000 846.620000 1615.220000 ;
+ RECT 841.690000 1603.860000 842.690000 1604.340000 ;
+ RECT 845.355000 1603.860000 846.620000 1604.340000 ;
+ RECT 841.690000 1609.300000 842.690000 1609.780000 ;
+ RECT 845.355000 1609.300000 846.620000 1609.780000 ;
+ RECT 841.690000 1598.420000 842.690000 1598.900000 ;
+ RECT 845.355000 1598.420000 846.620000 1598.900000 ;
+ RECT 935.520000 1576.660000 936.620000 1577.140000 ;
+ RECT 935.520000 1582.100000 936.620000 1582.580000 ;
+ RECT 935.520000 1587.540000 936.620000 1588.020000 ;
+ RECT 935.520000 1592.980000 936.620000 1593.460000 ;
+ RECT 890.520000 1576.660000 891.620000 1577.140000 ;
+ RECT 890.520000 1582.100000 891.620000 1582.580000 ;
+ RECT 890.520000 1587.540000 891.620000 1588.020000 ;
+ RECT 890.520000 1592.980000 891.620000 1593.460000 ;
+ RECT 935.520000 1554.900000 936.620000 1555.380000 ;
+ RECT 935.520000 1560.340000 936.620000 1560.820000 ;
+ RECT 935.520000 1565.780000 936.620000 1566.260000 ;
+ RECT 935.520000 1571.220000 936.620000 1571.700000 ;
+ RECT 890.520000 1554.900000 891.620000 1555.380000 ;
+ RECT 890.520000 1560.340000 891.620000 1560.820000 ;
+ RECT 890.520000 1565.780000 891.620000 1566.260000 ;
+ RECT 890.520000 1571.220000 891.620000 1571.700000 ;
+ RECT 841.690000 1592.980000 842.690000 1593.460000 ;
+ RECT 845.355000 1592.980000 846.620000 1593.460000 ;
+ RECT 841.690000 1587.540000 842.690000 1588.020000 ;
+ RECT 845.355000 1587.540000 846.620000 1588.020000 ;
+ RECT 841.690000 1582.100000 842.690000 1582.580000 ;
+ RECT 845.355000 1582.100000 846.620000 1582.580000 ;
+ RECT 841.690000 1576.660000 842.690000 1577.140000 ;
+ RECT 845.355000 1576.660000 846.620000 1577.140000 ;
+ RECT 841.690000 1571.220000 842.690000 1571.700000 ;
+ RECT 845.355000 1571.220000 846.620000 1571.700000 ;
+ RECT 841.690000 1560.340000 842.690000 1560.820000 ;
+ RECT 845.355000 1560.340000 846.620000 1560.820000 ;
+ RECT 841.690000 1565.780000 842.690000 1566.260000 ;
+ RECT 845.355000 1565.780000 846.620000 1566.260000 ;
+ RECT 841.690000 1554.900000 842.690000 1555.380000 ;
+ RECT 845.355000 1554.900000 846.620000 1555.380000 ;
+ RECT 980.520000 1647.380000 981.620000 1647.860000 ;
+ RECT 1025.520000 1647.380000 1026.620000 1647.860000 ;
+ RECT 1038.330000 1647.380000 1039.330000 1647.860000 ;
+ RECT 890.520000 1647.380000 891.620000 1647.860000 ;
+ RECT 935.520000 1647.380000 936.620000 1647.860000 ;
+ RECT 841.690000 1647.380000 842.690000 1647.860000 ;
+ RECT 845.355000 1647.380000 846.620000 1647.860000 ;
+ RECT 840.460000 1744.140000 1040.560000 1745.140000 ;
+ RECT 840.460000 1548.570000 1040.560000 1549.570000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 1547.320000 842.690000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 841.690000 1746.580000 842.690000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 1547.320000 1039.330000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1038.330000 1746.580000 1039.330000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1548.570000 841.460000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1548.570000 1040.560000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1744.140000 841.460000 1745.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1744.140000 1040.560000 1745.140000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 3373.560000 1046.720000 3374.040000 ;
+ RECT 1045.455000 3368.120000 1046.720000 3368.600000 ;
+ RECT 1045.455000 3362.680000 1046.720000 3363.160000 ;
+ RECT 1045.455000 3357.240000 1046.720000 3357.720000 ;
+ RECT 1041.790000 3349.660000 1042.790000 3379.920000 ;
+ RECT 1238.430000 3349.660000 1239.430000 3379.920000 ;
+ RECT 1045.620000 3350.910000 1046.720000 3378.160000 ;
+ RECT 1090.620000 3350.910000 1091.720000 3378.160000 ;
+ RECT 1135.620000 3350.910000 1136.720000 3378.160000 ;
+ RECT 1180.620000 3350.910000 1181.720000 3378.160000 ;
+ RECT 1225.620000 3350.910000 1226.720000 3378.160000 ;
+ LAYER met3 ;
+ RECT 1238.430000 3373.560000 1239.430000 3374.040000 ;
+ RECT 1238.430000 3368.120000 1239.430000 3368.600000 ;
+ RECT 1225.620000 3373.560000 1226.720000 3374.040000 ;
+ RECT 1225.620000 3368.120000 1226.720000 3368.600000 ;
+ RECT 1180.620000 3368.120000 1181.720000 3368.600000 ;
+ RECT 1180.620000 3373.560000 1181.720000 3374.040000 ;
+ RECT 1135.620000 3368.120000 1136.720000 3368.600000 ;
+ RECT 1090.620000 3368.120000 1091.720000 3368.600000 ;
+ RECT 1135.620000 3373.560000 1136.720000 3374.040000 ;
+ RECT 1090.620000 3373.560000 1091.720000 3374.040000 ;
+ RECT 1045.455000 3373.560000 1046.720000 3374.040000 ;
+ RECT 1041.790000 3373.560000 1042.790000 3374.040000 ;
+ RECT 1045.455000 3368.120000 1046.720000 3368.600000 ;
+ RECT 1041.790000 3368.120000 1042.790000 3368.600000 ;
+ RECT 1238.430000 3362.680000 1239.430000 3363.160000 ;
+ RECT 1238.430000 3357.240000 1239.430000 3357.720000 ;
+ RECT 1225.620000 3362.680000 1226.720000 3363.160000 ;
+ RECT 1225.620000 3357.240000 1226.720000 3357.720000 ;
+ RECT 1180.620000 3357.240000 1181.720000 3357.720000 ;
+ RECT 1180.620000 3362.680000 1181.720000 3363.160000 ;
+ RECT 1135.620000 3357.240000 1136.720000 3357.720000 ;
+ RECT 1090.620000 3357.240000 1091.720000 3357.720000 ;
+ RECT 1135.620000 3362.680000 1136.720000 3363.160000 ;
+ RECT 1090.620000 3362.680000 1091.720000 3363.160000 ;
+ RECT 1045.455000 3362.680000 1046.720000 3363.160000 ;
+ RECT 1041.790000 3362.680000 1042.790000 3363.160000 ;
+ RECT 1045.455000 3357.240000 1046.720000 3357.720000 ;
+ RECT 1041.790000 3357.240000 1042.790000 3357.720000 ;
+ RECT 1040.560000 3377.160000 1240.660000 3378.160000 ;
+ RECT 1040.560000 3350.910000 1240.660000 3351.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 3349.660000 1042.790000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 3378.920000 1042.790000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 3349.660000 1239.430000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 3378.920000 1239.430000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 3350.910000 1041.560000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 3350.910000 1240.660000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 3377.160000 1041.560000 3378.160000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 3377.160000 1240.660000 3378.160000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 1539.600000 1046.720000 1540.080000 ;
+ RECT 1045.455000 1528.720000 1046.720000 1529.200000 ;
+ RECT 1045.455000 1534.160000 1046.720000 1534.640000 ;
+ RECT 1045.455000 1523.280000 1046.720000 1523.760000 ;
+ RECT 1045.455000 1517.840000 1046.720000 1518.320000 ;
+ RECT 1045.455000 1512.400000 1046.720000 1512.880000 ;
+ RECT 1045.455000 1506.960000 1046.720000 1507.440000 ;
+ RECT 1045.455000 1501.520000 1046.720000 1502.000000 ;
+ RECT 1045.455000 1496.080000 1046.720000 1496.560000 ;
+ RECT 1045.455000 1485.200000 1046.720000 1485.680000 ;
+ RECT 1045.455000 1490.640000 1046.720000 1491.120000 ;
+ RECT 1045.455000 1479.760000 1046.720000 1480.240000 ;
+ RECT 1045.455000 1474.320000 1046.720000 1474.800000 ;
+ RECT 1045.455000 1468.880000 1046.720000 1469.360000 ;
+ RECT 1045.455000 1463.440000 1046.720000 1463.920000 ;
+ RECT 1045.455000 1458.000000 1046.720000 1458.480000 ;
+ RECT 1045.455000 1452.560000 1046.720000 1453.040000 ;
+ RECT 1045.455000 1441.680000 1046.720000 1442.160000 ;
+ RECT 1045.455000 1436.240000 1046.720000 1436.720000 ;
+ RECT 1045.455000 1430.800000 1046.720000 1431.280000 ;
+ RECT 1045.455000 1425.360000 1046.720000 1425.840000 ;
+ RECT 1045.455000 1419.920000 1046.720000 1420.400000 ;
+ RECT 1045.455000 1414.480000 1046.720000 1414.960000 ;
+ RECT 1045.455000 1403.600000 1046.720000 1404.080000 ;
+ RECT 1045.455000 1409.040000 1046.720000 1409.520000 ;
+ RECT 1045.455000 1398.160000 1046.720000 1398.640000 ;
+ RECT 1045.455000 1392.720000 1046.720000 1393.200000 ;
+ RECT 1045.455000 1387.280000 1046.720000 1387.760000 ;
+ RECT 1045.455000 1381.840000 1046.720000 1382.320000 ;
+ RECT 1045.455000 1376.400000 1046.720000 1376.880000 ;
+ RECT 1045.455000 1370.960000 1046.720000 1371.440000 ;
+ RECT 1045.455000 1360.080000 1046.720000 1360.560000 ;
+ RECT 1045.455000 1365.520000 1046.720000 1366.000000 ;
+ RECT 1045.455000 1354.640000 1046.720000 1355.120000 ;
+ RECT 1045.455000 1447.120000 1046.720000 1447.600000 ;
+ RECT 1225.620000 1348.310000 1226.720000 1544.880000 ;
+ RECT 1180.620000 1348.310000 1181.720000 1544.880000 ;
+ RECT 1238.430000 1347.060000 1239.430000 1547.320000 ;
+ RECT 1135.620000 1348.310000 1136.720000 1544.880000 ;
+ RECT 1090.620000 1348.310000 1091.720000 1544.880000 ;
+ RECT 1045.620000 1348.310000 1046.720000 1544.880000 ;
+ RECT 1041.790000 1347.060000 1042.790000 1547.320000 ;
+ LAYER met3 ;
+ RECT 1225.620000 1539.600000 1226.720000 1540.080000 ;
+ RECT 1238.430000 1539.600000 1239.430000 1540.080000 ;
+ RECT 1238.430000 1528.720000 1239.430000 1529.200000 ;
+ RECT 1238.430000 1523.280000 1239.430000 1523.760000 ;
+ RECT 1238.430000 1534.160000 1239.430000 1534.640000 ;
+ RECT 1225.620000 1534.160000 1226.720000 1534.640000 ;
+ RECT 1225.620000 1528.720000 1226.720000 1529.200000 ;
+ RECT 1225.620000 1523.280000 1226.720000 1523.760000 ;
+ RECT 1225.620000 1512.400000 1226.720000 1512.880000 ;
+ RECT 1225.620000 1517.840000 1226.720000 1518.320000 ;
+ RECT 1238.430000 1512.400000 1239.430000 1512.880000 ;
+ RECT 1238.430000 1517.840000 1239.430000 1518.320000 ;
+ RECT 1225.620000 1501.520000 1226.720000 1502.000000 ;
+ RECT 1225.620000 1506.960000 1226.720000 1507.440000 ;
+ RECT 1238.430000 1501.520000 1239.430000 1502.000000 ;
+ RECT 1238.430000 1506.960000 1239.430000 1507.440000 ;
+ RECT 1180.620000 1523.280000 1181.720000 1523.760000 ;
+ RECT 1180.620000 1528.720000 1181.720000 1529.200000 ;
+ RECT 1180.620000 1534.160000 1181.720000 1534.640000 ;
+ RECT 1180.620000 1539.600000 1181.720000 1540.080000 ;
+ RECT 1180.620000 1506.960000 1181.720000 1507.440000 ;
+ RECT 1180.620000 1501.520000 1181.720000 1502.000000 ;
+ RECT 1180.620000 1512.400000 1181.720000 1512.880000 ;
+ RECT 1180.620000 1517.840000 1181.720000 1518.320000 ;
+ RECT 1238.430000 1490.640000 1239.430000 1491.120000 ;
+ RECT 1238.430000 1485.200000 1239.430000 1485.680000 ;
+ RECT 1238.430000 1496.080000 1239.430000 1496.560000 ;
+ RECT 1225.620000 1496.080000 1226.720000 1496.560000 ;
+ RECT 1225.620000 1490.640000 1226.720000 1491.120000 ;
+ RECT 1225.620000 1485.200000 1226.720000 1485.680000 ;
+ RECT 1225.620000 1474.320000 1226.720000 1474.800000 ;
+ RECT 1225.620000 1479.760000 1226.720000 1480.240000 ;
+ RECT 1238.430000 1474.320000 1239.430000 1474.800000 ;
+ RECT 1238.430000 1479.760000 1239.430000 1480.240000 ;
+ RECT 1238.430000 1463.440000 1239.430000 1463.920000 ;
+ RECT 1238.430000 1468.880000 1239.430000 1469.360000 ;
+ RECT 1225.620000 1468.880000 1226.720000 1469.360000 ;
+ RECT 1225.620000 1463.440000 1226.720000 1463.920000 ;
+ RECT 1225.620000 1452.560000 1226.720000 1453.040000 ;
+ RECT 1225.620000 1458.000000 1226.720000 1458.480000 ;
+ RECT 1238.430000 1452.560000 1239.430000 1453.040000 ;
+ RECT 1238.430000 1458.000000 1239.430000 1458.480000 ;
+ RECT 1180.620000 1474.320000 1181.720000 1474.800000 ;
+ RECT 1180.620000 1479.760000 1181.720000 1480.240000 ;
+ RECT 1180.620000 1485.200000 1181.720000 1485.680000 ;
+ RECT 1180.620000 1490.640000 1181.720000 1491.120000 ;
+ RECT 1180.620000 1496.080000 1181.720000 1496.560000 ;
+ RECT 1180.620000 1452.560000 1181.720000 1453.040000 ;
+ RECT 1180.620000 1458.000000 1181.720000 1458.480000 ;
+ RECT 1180.620000 1463.440000 1181.720000 1463.920000 ;
+ RECT 1180.620000 1468.880000 1181.720000 1469.360000 ;
+ RECT 1135.620000 1528.720000 1136.720000 1529.200000 ;
+ RECT 1135.620000 1523.280000 1136.720000 1523.760000 ;
+ RECT 1135.620000 1534.160000 1136.720000 1534.640000 ;
+ RECT 1135.620000 1539.600000 1136.720000 1540.080000 ;
+ RECT 1090.620000 1523.280000 1091.720000 1523.760000 ;
+ RECT 1090.620000 1528.720000 1091.720000 1529.200000 ;
+ RECT 1090.620000 1534.160000 1091.720000 1534.640000 ;
+ RECT 1090.620000 1539.600000 1091.720000 1540.080000 ;
+ RECT 1135.620000 1501.520000 1136.720000 1502.000000 ;
+ RECT 1135.620000 1506.960000 1136.720000 1507.440000 ;
+ RECT 1135.620000 1512.400000 1136.720000 1512.880000 ;
+ RECT 1135.620000 1517.840000 1136.720000 1518.320000 ;
+ RECT 1090.620000 1501.520000 1091.720000 1502.000000 ;
+ RECT 1090.620000 1506.960000 1091.720000 1507.440000 ;
+ RECT 1090.620000 1512.400000 1091.720000 1512.880000 ;
+ RECT 1090.620000 1517.840000 1091.720000 1518.320000 ;
+ RECT 1041.790000 1539.600000 1042.790000 1540.080000 ;
+ RECT 1045.455000 1539.600000 1046.720000 1540.080000 ;
+ RECT 1041.790000 1528.720000 1042.790000 1529.200000 ;
+ RECT 1045.455000 1528.720000 1046.720000 1529.200000 ;
+ RECT 1041.790000 1534.160000 1042.790000 1534.640000 ;
+ RECT 1045.455000 1534.160000 1046.720000 1534.640000 ;
+ RECT 1041.790000 1523.280000 1042.790000 1523.760000 ;
+ RECT 1045.455000 1523.280000 1046.720000 1523.760000 ;
+ RECT 1041.790000 1517.840000 1042.790000 1518.320000 ;
+ RECT 1045.455000 1517.840000 1046.720000 1518.320000 ;
+ RECT 1041.790000 1512.400000 1042.790000 1512.880000 ;
+ RECT 1045.455000 1512.400000 1046.720000 1512.880000 ;
+ RECT 1041.790000 1506.960000 1042.790000 1507.440000 ;
+ RECT 1045.455000 1506.960000 1046.720000 1507.440000 ;
+ RECT 1041.790000 1501.520000 1042.790000 1502.000000 ;
+ RECT 1045.455000 1501.520000 1046.720000 1502.000000 ;
+ RECT 1135.620000 1474.320000 1136.720000 1474.800000 ;
+ RECT 1135.620000 1479.760000 1136.720000 1480.240000 ;
+ RECT 1135.620000 1485.200000 1136.720000 1485.680000 ;
+ RECT 1135.620000 1490.640000 1136.720000 1491.120000 ;
+ RECT 1135.620000 1496.080000 1136.720000 1496.560000 ;
+ RECT 1090.620000 1474.320000 1091.720000 1474.800000 ;
+ RECT 1090.620000 1479.760000 1091.720000 1480.240000 ;
+ RECT 1090.620000 1485.200000 1091.720000 1485.680000 ;
+ RECT 1090.620000 1490.640000 1091.720000 1491.120000 ;
+ RECT 1090.620000 1496.080000 1091.720000 1496.560000 ;
+ RECT 1135.620000 1452.560000 1136.720000 1453.040000 ;
+ RECT 1135.620000 1458.000000 1136.720000 1458.480000 ;
+ RECT 1135.620000 1463.440000 1136.720000 1463.920000 ;
+ RECT 1135.620000 1468.880000 1136.720000 1469.360000 ;
+ RECT 1090.620000 1452.560000 1091.720000 1453.040000 ;
+ RECT 1090.620000 1458.000000 1091.720000 1458.480000 ;
+ RECT 1090.620000 1463.440000 1091.720000 1463.920000 ;
+ RECT 1090.620000 1468.880000 1091.720000 1469.360000 ;
+ RECT 1041.790000 1496.080000 1042.790000 1496.560000 ;
+ RECT 1045.455000 1496.080000 1046.720000 1496.560000 ;
+ RECT 1041.790000 1485.200000 1042.790000 1485.680000 ;
+ RECT 1045.455000 1485.200000 1046.720000 1485.680000 ;
+ RECT 1041.790000 1490.640000 1042.790000 1491.120000 ;
+ RECT 1045.455000 1490.640000 1046.720000 1491.120000 ;
+ RECT 1041.790000 1479.760000 1042.790000 1480.240000 ;
+ RECT 1045.455000 1479.760000 1046.720000 1480.240000 ;
+ RECT 1041.790000 1474.320000 1042.790000 1474.800000 ;
+ RECT 1045.455000 1474.320000 1046.720000 1474.800000 ;
+ RECT 1041.790000 1468.880000 1042.790000 1469.360000 ;
+ RECT 1045.455000 1468.880000 1046.720000 1469.360000 ;
+ RECT 1041.790000 1463.440000 1042.790000 1463.920000 ;
+ RECT 1045.455000 1463.440000 1046.720000 1463.920000 ;
+ RECT 1041.790000 1458.000000 1042.790000 1458.480000 ;
+ RECT 1045.455000 1458.000000 1046.720000 1458.480000 ;
+ RECT 1041.790000 1452.560000 1042.790000 1453.040000 ;
+ RECT 1045.455000 1452.560000 1046.720000 1453.040000 ;
+ RECT 1225.620000 1436.240000 1226.720000 1436.720000 ;
+ RECT 1225.620000 1441.680000 1226.720000 1442.160000 ;
+ RECT 1238.430000 1436.240000 1239.430000 1436.720000 ;
+ RECT 1238.430000 1441.680000 1239.430000 1442.160000 ;
+ RECT 1238.430000 1425.360000 1239.430000 1425.840000 ;
+ RECT 1238.430000 1430.800000 1239.430000 1431.280000 ;
+ RECT 1225.620000 1430.800000 1226.720000 1431.280000 ;
+ RECT 1225.620000 1425.360000 1226.720000 1425.840000 ;
+ RECT 1225.620000 1414.480000 1226.720000 1414.960000 ;
+ RECT 1225.620000 1419.920000 1226.720000 1420.400000 ;
+ RECT 1238.430000 1414.480000 1239.430000 1414.960000 ;
+ RECT 1238.430000 1419.920000 1239.430000 1420.400000 ;
+ RECT 1238.430000 1403.600000 1239.430000 1404.080000 ;
+ RECT 1238.430000 1398.160000 1239.430000 1398.640000 ;
+ RECT 1238.430000 1409.040000 1239.430000 1409.520000 ;
+ RECT 1225.620000 1409.040000 1226.720000 1409.520000 ;
+ RECT 1225.620000 1403.600000 1226.720000 1404.080000 ;
+ RECT 1225.620000 1398.160000 1226.720000 1398.640000 ;
+ RECT 1180.620000 1425.360000 1181.720000 1425.840000 ;
+ RECT 1180.620000 1430.800000 1181.720000 1431.280000 ;
+ RECT 1180.620000 1436.240000 1181.720000 1436.720000 ;
+ RECT 1180.620000 1441.680000 1181.720000 1442.160000 ;
+ RECT 1180.620000 1398.160000 1181.720000 1398.640000 ;
+ RECT 1180.620000 1403.600000 1181.720000 1404.080000 ;
+ RECT 1180.620000 1409.040000 1181.720000 1409.520000 ;
+ RECT 1180.620000 1414.480000 1181.720000 1414.960000 ;
+ RECT 1180.620000 1419.920000 1181.720000 1420.400000 ;
+ RECT 1225.620000 1387.280000 1226.720000 1387.760000 ;
+ RECT 1225.620000 1392.720000 1226.720000 1393.200000 ;
+ RECT 1238.430000 1387.280000 1239.430000 1387.760000 ;
+ RECT 1238.430000 1392.720000 1239.430000 1393.200000 ;
+ RECT 1225.620000 1376.400000 1226.720000 1376.880000 ;
+ RECT 1225.620000 1381.840000 1226.720000 1382.320000 ;
+ RECT 1238.430000 1376.400000 1239.430000 1376.880000 ;
+ RECT 1238.430000 1381.840000 1239.430000 1382.320000 ;
+ RECT 1238.430000 1365.520000 1239.430000 1366.000000 ;
+ RECT 1238.430000 1360.080000 1239.430000 1360.560000 ;
+ RECT 1238.430000 1370.960000 1239.430000 1371.440000 ;
+ RECT 1225.620000 1370.960000 1226.720000 1371.440000 ;
+ RECT 1225.620000 1365.520000 1226.720000 1366.000000 ;
+ RECT 1225.620000 1360.080000 1226.720000 1360.560000 ;
+ RECT 1225.620000 1354.640000 1226.720000 1355.120000 ;
+ RECT 1238.430000 1354.640000 1239.430000 1355.120000 ;
+ RECT 1180.620000 1376.400000 1181.720000 1376.880000 ;
+ RECT 1180.620000 1381.840000 1181.720000 1382.320000 ;
+ RECT 1180.620000 1387.280000 1181.720000 1387.760000 ;
+ RECT 1180.620000 1392.720000 1181.720000 1393.200000 ;
+ RECT 1180.620000 1354.640000 1181.720000 1355.120000 ;
+ RECT 1180.620000 1360.080000 1181.720000 1360.560000 ;
+ RECT 1180.620000 1365.520000 1181.720000 1366.000000 ;
+ RECT 1180.620000 1370.960000 1181.720000 1371.440000 ;
+ RECT 1135.620000 1425.360000 1136.720000 1425.840000 ;
+ RECT 1135.620000 1430.800000 1136.720000 1431.280000 ;
+ RECT 1135.620000 1436.240000 1136.720000 1436.720000 ;
+ RECT 1135.620000 1441.680000 1136.720000 1442.160000 ;
+ RECT 1090.620000 1425.360000 1091.720000 1425.840000 ;
+ RECT 1090.620000 1430.800000 1091.720000 1431.280000 ;
+ RECT 1090.620000 1436.240000 1091.720000 1436.720000 ;
+ RECT 1090.620000 1441.680000 1091.720000 1442.160000 ;
+ RECT 1135.620000 1398.160000 1136.720000 1398.640000 ;
+ RECT 1135.620000 1403.600000 1136.720000 1404.080000 ;
+ RECT 1135.620000 1409.040000 1136.720000 1409.520000 ;
+ RECT 1135.620000 1414.480000 1136.720000 1414.960000 ;
+ RECT 1135.620000 1419.920000 1136.720000 1420.400000 ;
+ RECT 1090.620000 1398.160000 1091.720000 1398.640000 ;
+ RECT 1090.620000 1403.600000 1091.720000 1404.080000 ;
+ RECT 1090.620000 1409.040000 1091.720000 1409.520000 ;
+ RECT 1090.620000 1414.480000 1091.720000 1414.960000 ;
+ RECT 1090.620000 1419.920000 1091.720000 1420.400000 ;
+ RECT 1041.790000 1441.680000 1042.790000 1442.160000 ;
+ RECT 1045.455000 1441.680000 1046.720000 1442.160000 ;
+ RECT 1041.790000 1436.240000 1042.790000 1436.720000 ;
+ RECT 1045.455000 1436.240000 1046.720000 1436.720000 ;
+ RECT 1041.790000 1430.800000 1042.790000 1431.280000 ;
+ RECT 1045.455000 1430.800000 1046.720000 1431.280000 ;
+ RECT 1041.790000 1425.360000 1042.790000 1425.840000 ;
+ RECT 1045.455000 1425.360000 1046.720000 1425.840000 ;
+ RECT 1041.790000 1419.920000 1042.790000 1420.400000 ;
+ RECT 1045.455000 1419.920000 1046.720000 1420.400000 ;
+ RECT 1041.790000 1414.480000 1042.790000 1414.960000 ;
+ RECT 1045.455000 1414.480000 1046.720000 1414.960000 ;
+ RECT 1041.790000 1403.600000 1042.790000 1404.080000 ;
+ RECT 1045.455000 1403.600000 1046.720000 1404.080000 ;
+ RECT 1041.790000 1409.040000 1042.790000 1409.520000 ;
+ RECT 1045.455000 1409.040000 1046.720000 1409.520000 ;
+ RECT 1041.790000 1398.160000 1042.790000 1398.640000 ;
+ RECT 1045.455000 1398.160000 1046.720000 1398.640000 ;
+ RECT 1135.620000 1376.400000 1136.720000 1376.880000 ;
+ RECT 1135.620000 1381.840000 1136.720000 1382.320000 ;
+ RECT 1135.620000 1387.280000 1136.720000 1387.760000 ;
+ RECT 1135.620000 1392.720000 1136.720000 1393.200000 ;
+ RECT 1090.620000 1376.400000 1091.720000 1376.880000 ;
+ RECT 1090.620000 1381.840000 1091.720000 1382.320000 ;
+ RECT 1090.620000 1387.280000 1091.720000 1387.760000 ;
+ RECT 1090.620000 1392.720000 1091.720000 1393.200000 ;
+ RECT 1135.620000 1354.640000 1136.720000 1355.120000 ;
+ RECT 1135.620000 1360.080000 1136.720000 1360.560000 ;
+ RECT 1135.620000 1365.520000 1136.720000 1366.000000 ;
+ RECT 1135.620000 1370.960000 1136.720000 1371.440000 ;
+ RECT 1090.620000 1354.640000 1091.720000 1355.120000 ;
+ RECT 1090.620000 1360.080000 1091.720000 1360.560000 ;
+ RECT 1090.620000 1365.520000 1091.720000 1366.000000 ;
+ RECT 1090.620000 1370.960000 1091.720000 1371.440000 ;
+ RECT 1041.790000 1392.720000 1042.790000 1393.200000 ;
+ RECT 1045.455000 1392.720000 1046.720000 1393.200000 ;
+ RECT 1041.790000 1387.280000 1042.790000 1387.760000 ;
+ RECT 1045.455000 1387.280000 1046.720000 1387.760000 ;
+ RECT 1041.790000 1381.840000 1042.790000 1382.320000 ;
+ RECT 1045.455000 1381.840000 1046.720000 1382.320000 ;
+ RECT 1041.790000 1376.400000 1042.790000 1376.880000 ;
+ RECT 1045.455000 1376.400000 1046.720000 1376.880000 ;
+ RECT 1041.790000 1370.960000 1042.790000 1371.440000 ;
+ RECT 1045.455000 1370.960000 1046.720000 1371.440000 ;
+ RECT 1041.790000 1360.080000 1042.790000 1360.560000 ;
+ RECT 1045.455000 1360.080000 1046.720000 1360.560000 ;
+ RECT 1041.790000 1365.520000 1042.790000 1366.000000 ;
+ RECT 1045.455000 1365.520000 1046.720000 1366.000000 ;
+ RECT 1041.790000 1354.640000 1042.790000 1355.120000 ;
+ RECT 1045.455000 1354.640000 1046.720000 1355.120000 ;
+ RECT 1180.620000 1447.120000 1181.720000 1447.600000 ;
+ RECT 1225.620000 1447.120000 1226.720000 1447.600000 ;
+ RECT 1238.430000 1447.120000 1239.430000 1447.600000 ;
+ RECT 1090.620000 1447.120000 1091.720000 1447.600000 ;
+ RECT 1135.620000 1447.120000 1136.720000 1447.600000 ;
+ RECT 1041.790000 1447.120000 1042.790000 1447.600000 ;
+ RECT 1045.455000 1447.120000 1046.720000 1447.600000 ;
+ RECT 1040.560000 1543.880000 1240.660000 1544.880000 ;
+ RECT 1040.560000 1348.310000 1240.660000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 1347.060000 1042.790000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 1546.320000 1042.790000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 1347.060000 1239.430000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 1546.320000 1239.430000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1348.310000 1041.560000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1348.310000 1240.660000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1543.880000 1041.560000 1544.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1543.880000 1240.660000 1544.880000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 1339.340000 1046.720000 1339.820000 ;
+ RECT 1045.455000 1328.460000 1046.720000 1328.940000 ;
+ RECT 1045.455000 1333.900000 1046.720000 1334.380000 ;
+ RECT 1045.455000 1323.020000 1046.720000 1323.500000 ;
+ RECT 1045.455000 1317.580000 1046.720000 1318.060000 ;
+ RECT 1045.455000 1312.140000 1046.720000 1312.620000 ;
+ RECT 1045.455000 1306.700000 1046.720000 1307.180000 ;
+ RECT 1045.455000 1301.260000 1046.720000 1301.740000 ;
+ RECT 1045.455000 1295.820000 1046.720000 1296.300000 ;
+ RECT 1045.455000 1284.940000 1046.720000 1285.420000 ;
+ RECT 1045.455000 1290.380000 1046.720000 1290.860000 ;
+ RECT 1045.455000 1279.500000 1046.720000 1279.980000 ;
+ RECT 1045.455000 1274.060000 1046.720000 1274.540000 ;
+ RECT 1045.455000 1268.620000 1046.720000 1269.100000 ;
+ RECT 1045.455000 1263.180000 1046.720000 1263.660000 ;
+ RECT 1045.455000 1257.740000 1046.720000 1258.220000 ;
+ RECT 1045.455000 1252.300000 1046.720000 1252.780000 ;
+ RECT 1045.455000 1241.420000 1046.720000 1241.900000 ;
+ RECT 1045.455000 1235.980000 1046.720000 1236.460000 ;
+ RECT 1045.455000 1230.540000 1046.720000 1231.020000 ;
+ RECT 1045.455000 1225.100000 1046.720000 1225.580000 ;
+ RECT 1045.455000 1219.660000 1046.720000 1220.140000 ;
+ RECT 1045.455000 1214.220000 1046.720000 1214.700000 ;
+ RECT 1045.455000 1203.340000 1046.720000 1203.820000 ;
+ RECT 1045.455000 1208.780000 1046.720000 1209.260000 ;
+ RECT 1045.455000 1197.900000 1046.720000 1198.380000 ;
+ RECT 1045.455000 1192.460000 1046.720000 1192.940000 ;
+ RECT 1045.455000 1187.020000 1046.720000 1187.500000 ;
+ RECT 1045.455000 1181.580000 1046.720000 1182.060000 ;
+ RECT 1045.455000 1176.140000 1046.720000 1176.620000 ;
+ RECT 1045.455000 1170.700000 1046.720000 1171.180000 ;
+ RECT 1045.455000 1159.820000 1046.720000 1160.300000 ;
+ RECT 1045.455000 1165.260000 1046.720000 1165.740000 ;
+ RECT 1045.455000 1154.380000 1046.720000 1154.860000 ;
+ RECT 1045.455000 1246.860000 1046.720000 1247.340000 ;
+ RECT 1225.620000 1148.050000 1226.720000 1344.620000 ;
+ RECT 1180.620000 1148.050000 1181.720000 1344.620000 ;
+ RECT 1238.430000 1146.800000 1239.430000 1347.060000 ;
+ RECT 1135.620000 1148.050000 1136.720000 1344.620000 ;
+ RECT 1090.620000 1148.050000 1091.720000 1344.620000 ;
+ RECT 1045.620000 1148.050000 1046.720000 1344.620000 ;
+ RECT 1041.790000 1146.800000 1042.790000 1347.060000 ;
+ LAYER met3 ;
+ RECT 1225.620000 1339.340000 1226.720000 1339.820000 ;
+ RECT 1238.430000 1339.340000 1239.430000 1339.820000 ;
+ RECT 1238.430000 1328.460000 1239.430000 1328.940000 ;
+ RECT 1238.430000 1323.020000 1239.430000 1323.500000 ;
+ RECT 1238.430000 1333.900000 1239.430000 1334.380000 ;
+ RECT 1225.620000 1333.900000 1226.720000 1334.380000 ;
+ RECT 1225.620000 1328.460000 1226.720000 1328.940000 ;
+ RECT 1225.620000 1323.020000 1226.720000 1323.500000 ;
+ RECT 1225.620000 1312.140000 1226.720000 1312.620000 ;
+ RECT 1225.620000 1317.580000 1226.720000 1318.060000 ;
+ RECT 1238.430000 1312.140000 1239.430000 1312.620000 ;
+ RECT 1238.430000 1317.580000 1239.430000 1318.060000 ;
+ RECT 1225.620000 1301.260000 1226.720000 1301.740000 ;
+ RECT 1225.620000 1306.700000 1226.720000 1307.180000 ;
+ RECT 1238.430000 1301.260000 1239.430000 1301.740000 ;
+ RECT 1238.430000 1306.700000 1239.430000 1307.180000 ;
+ RECT 1180.620000 1323.020000 1181.720000 1323.500000 ;
+ RECT 1180.620000 1328.460000 1181.720000 1328.940000 ;
+ RECT 1180.620000 1333.900000 1181.720000 1334.380000 ;
+ RECT 1180.620000 1339.340000 1181.720000 1339.820000 ;
+ RECT 1180.620000 1306.700000 1181.720000 1307.180000 ;
+ RECT 1180.620000 1301.260000 1181.720000 1301.740000 ;
+ RECT 1180.620000 1312.140000 1181.720000 1312.620000 ;
+ RECT 1180.620000 1317.580000 1181.720000 1318.060000 ;
+ RECT 1238.430000 1290.380000 1239.430000 1290.860000 ;
+ RECT 1238.430000 1284.940000 1239.430000 1285.420000 ;
+ RECT 1238.430000 1295.820000 1239.430000 1296.300000 ;
+ RECT 1225.620000 1295.820000 1226.720000 1296.300000 ;
+ RECT 1225.620000 1290.380000 1226.720000 1290.860000 ;
+ RECT 1225.620000 1284.940000 1226.720000 1285.420000 ;
+ RECT 1225.620000 1274.060000 1226.720000 1274.540000 ;
+ RECT 1225.620000 1279.500000 1226.720000 1279.980000 ;
+ RECT 1238.430000 1274.060000 1239.430000 1274.540000 ;
+ RECT 1238.430000 1279.500000 1239.430000 1279.980000 ;
+ RECT 1238.430000 1263.180000 1239.430000 1263.660000 ;
+ RECT 1238.430000 1268.620000 1239.430000 1269.100000 ;
+ RECT 1225.620000 1268.620000 1226.720000 1269.100000 ;
+ RECT 1225.620000 1263.180000 1226.720000 1263.660000 ;
+ RECT 1225.620000 1252.300000 1226.720000 1252.780000 ;
+ RECT 1225.620000 1257.740000 1226.720000 1258.220000 ;
+ RECT 1238.430000 1252.300000 1239.430000 1252.780000 ;
+ RECT 1238.430000 1257.740000 1239.430000 1258.220000 ;
+ RECT 1180.620000 1274.060000 1181.720000 1274.540000 ;
+ RECT 1180.620000 1279.500000 1181.720000 1279.980000 ;
+ RECT 1180.620000 1284.940000 1181.720000 1285.420000 ;
+ RECT 1180.620000 1290.380000 1181.720000 1290.860000 ;
+ RECT 1180.620000 1295.820000 1181.720000 1296.300000 ;
+ RECT 1180.620000 1252.300000 1181.720000 1252.780000 ;
+ RECT 1180.620000 1257.740000 1181.720000 1258.220000 ;
+ RECT 1180.620000 1263.180000 1181.720000 1263.660000 ;
+ RECT 1180.620000 1268.620000 1181.720000 1269.100000 ;
+ RECT 1135.620000 1328.460000 1136.720000 1328.940000 ;
+ RECT 1135.620000 1323.020000 1136.720000 1323.500000 ;
+ RECT 1135.620000 1333.900000 1136.720000 1334.380000 ;
+ RECT 1135.620000 1339.340000 1136.720000 1339.820000 ;
+ RECT 1090.620000 1323.020000 1091.720000 1323.500000 ;
+ RECT 1090.620000 1328.460000 1091.720000 1328.940000 ;
+ RECT 1090.620000 1333.900000 1091.720000 1334.380000 ;
+ RECT 1090.620000 1339.340000 1091.720000 1339.820000 ;
+ RECT 1135.620000 1301.260000 1136.720000 1301.740000 ;
+ RECT 1135.620000 1306.700000 1136.720000 1307.180000 ;
+ RECT 1135.620000 1312.140000 1136.720000 1312.620000 ;
+ RECT 1135.620000 1317.580000 1136.720000 1318.060000 ;
+ RECT 1090.620000 1301.260000 1091.720000 1301.740000 ;
+ RECT 1090.620000 1306.700000 1091.720000 1307.180000 ;
+ RECT 1090.620000 1312.140000 1091.720000 1312.620000 ;
+ RECT 1090.620000 1317.580000 1091.720000 1318.060000 ;
+ RECT 1041.790000 1339.340000 1042.790000 1339.820000 ;
+ RECT 1045.455000 1339.340000 1046.720000 1339.820000 ;
+ RECT 1041.790000 1328.460000 1042.790000 1328.940000 ;
+ RECT 1045.455000 1328.460000 1046.720000 1328.940000 ;
+ RECT 1041.790000 1333.900000 1042.790000 1334.380000 ;
+ RECT 1045.455000 1333.900000 1046.720000 1334.380000 ;
+ RECT 1041.790000 1323.020000 1042.790000 1323.500000 ;
+ RECT 1045.455000 1323.020000 1046.720000 1323.500000 ;
+ RECT 1041.790000 1317.580000 1042.790000 1318.060000 ;
+ RECT 1045.455000 1317.580000 1046.720000 1318.060000 ;
+ RECT 1041.790000 1312.140000 1042.790000 1312.620000 ;
+ RECT 1045.455000 1312.140000 1046.720000 1312.620000 ;
+ RECT 1041.790000 1306.700000 1042.790000 1307.180000 ;
+ RECT 1045.455000 1306.700000 1046.720000 1307.180000 ;
+ RECT 1041.790000 1301.260000 1042.790000 1301.740000 ;
+ RECT 1045.455000 1301.260000 1046.720000 1301.740000 ;
+ RECT 1135.620000 1274.060000 1136.720000 1274.540000 ;
+ RECT 1135.620000 1279.500000 1136.720000 1279.980000 ;
+ RECT 1135.620000 1284.940000 1136.720000 1285.420000 ;
+ RECT 1135.620000 1290.380000 1136.720000 1290.860000 ;
+ RECT 1135.620000 1295.820000 1136.720000 1296.300000 ;
+ RECT 1090.620000 1274.060000 1091.720000 1274.540000 ;
+ RECT 1090.620000 1279.500000 1091.720000 1279.980000 ;
+ RECT 1090.620000 1284.940000 1091.720000 1285.420000 ;
+ RECT 1090.620000 1290.380000 1091.720000 1290.860000 ;
+ RECT 1090.620000 1295.820000 1091.720000 1296.300000 ;
+ RECT 1135.620000 1252.300000 1136.720000 1252.780000 ;
+ RECT 1135.620000 1257.740000 1136.720000 1258.220000 ;
+ RECT 1135.620000 1263.180000 1136.720000 1263.660000 ;
+ RECT 1135.620000 1268.620000 1136.720000 1269.100000 ;
+ RECT 1090.620000 1252.300000 1091.720000 1252.780000 ;
+ RECT 1090.620000 1257.740000 1091.720000 1258.220000 ;
+ RECT 1090.620000 1263.180000 1091.720000 1263.660000 ;
+ RECT 1090.620000 1268.620000 1091.720000 1269.100000 ;
+ RECT 1041.790000 1295.820000 1042.790000 1296.300000 ;
+ RECT 1045.455000 1295.820000 1046.720000 1296.300000 ;
+ RECT 1041.790000 1284.940000 1042.790000 1285.420000 ;
+ RECT 1045.455000 1284.940000 1046.720000 1285.420000 ;
+ RECT 1041.790000 1290.380000 1042.790000 1290.860000 ;
+ RECT 1045.455000 1290.380000 1046.720000 1290.860000 ;
+ RECT 1041.790000 1279.500000 1042.790000 1279.980000 ;
+ RECT 1045.455000 1279.500000 1046.720000 1279.980000 ;
+ RECT 1041.790000 1274.060000 1042.790000 1274.540000 ;
+ RECT 1045.455000 1274.060000 1046.720000 1274.540000 ;
+ RECT 1041.790000 1268.620000 1042.790000 1269.100000 ;
+ RECT 1045.455000 1268.620000 1046.720000 1269.100000 ;
+ RECT 1041.790000 1263.180000 1042.790000 1263.660000 ;
+ RECT 1045.455000 1263.180000 1046.720000 1263.660000 ;
+ RECT 1041.790000 1257.740000 1042.790000 1258.220000 ;
+ RECT 1045.455000 1257.740000 1046.720000 1258.220000 ;
+ RECT 1041.790000 1252.300000 1042.790000 1252.780000 ;
+ RECT 1045.455000 1252.300000 1046.720000 1252.780000 ;
+ RECT 1225.620000 1235.980000 1226.720000 1236.460000 ;
+ RECT 1225.620000 1241.420000 1226.720000 1241.900000 ;
+ RECT 1238.430000 1235.980000 1239.430000 1236.460000 ;
+ RECT 1238.430000 1241.420000 1239.430000 1241.900000 ;
+ RECT 1238.430000 1225.100000 1239.430000 1225.580000 ;
+ RECT 1238.430000 1230.540000 1239.430000 1231.020000 ;
+ RECT 1225.620000 1230.540000 1226.720000 1231.020000 ;
+ RECT 1225.620000 1225.100000 1226.720000 1225.580000 ;
+ RECT 1225.620000 1214.220000 1226.720000 1214.700000 ;
+ RECT 1225.620000 1219.660000 1226.720000 1220.140000 ;
+ RECT 1238.430000 1214.220000 1239.430000 1214.700000 ;
+ RECT 1238.430000 1219.660000 1239.430000 1220.140000 ;
+ RECT 1238.430000 1203.340000 1239.430000 1203.820000 ;
+ RECT 1238.430000 1197.900000 1239.430000 1198.380000 ;
+ RECT 1238.430000 1208.780000 1239.430000 1209.260000 ;
+ RECT 1225.620000 1208.780000 1226.720000 1209.260000 ;
+ RECT 1225.620000 1203.340000 1226.720000 1203.820000 ;
+ RECT 1225.620000 1197.900000 1226.720000 1198.380000 ;
+ RECT 1180.620000 1225.100000 1181.720000 1225.580000 ;
+ RECT 1180.620000 1230.540000 1181.720000 1231.020000 ;
+ RECT 1180.620000 1235.980000 1181.720000 1236.460000 ;
+ RECT 1180.620000 1241.420000 1181.720000 1241.900000 ;
+ RECT 1180.620000 1197.900000 1181.720000 1198.380000 ;
+ RECT 1180.620000 1203.340000 1181.720000 1203.820000 ;
+ RECT 1180.620000 1208.780000 1181.720000 1209.260000 ;
+ RECT 1180.620000 1214.220000 1181.720000 1214.700000 ;
+ RECT 1180.620000 1219.660000 1181.720000 1220.140000 ;
+ RECT 1225.620000 1187.020000 1226.720000 1187.500000 ;
+ RECT 1225.620000 1192.460000 1226.720000 1192.940000 ;
+ RECT 1238.430000 1187.020000 1239.430000 1187.500000 ;
+ RECT 1238.430000 1192.460000 1239.430000 1192.940000 ;
+ RECT 1225.620000 1176.140000 1226.720000 1176.620000 ;
+ RECT 1225.620000 1181.580000 1226.720000 1182.060000 ;
+ RECT 1238.430000 1176.140000 1239.430000 1176.620000 ;
+ RECT 1238.430000 1181.580000 1239.430000 1182.060000 ;
+ RECT 1238.430000 1165.260000 1239.430000 1165.740000 ;
+ RECT 1238.430000 1159.820000 1239.430000 1160.300000 ;
+ RECT 1238.430000 1170.700000 1239.430000 1171.180000 ;
+ RECT 1225.620000 1170.700000 1226.720000 1171.180000 ;
+ RECT 1225.620000 1165.260000 1226.720000 1165.740000 ;
+ RECT 1225.620000 1159.820000 1226.720000 1160.300000 ;
+ RECT 1225.620000 1154.380000 1226.720000 1154.860000 ;
+ RECT 1238.430000 1154.380000 1239.430000 1154.860000 ;
+ RECT 1180.620000 1176.140000 1181.720000 1176.620000 ;
+ RECT 1180.620000 1181.580000 1181.720000 1182.060000 ;
+ RECT 1180.620000 1187.020000 1181.720000 1187.500000 ;
+ RECT 1180.620000 1192.460000 1181.720000 1192.940000 ;
+ RECT 1180.620000 1154.380000 1181.720000 1154.860000 ;
+ RECT 1180.620000 1159.820000 1181.720000 1160.300000 ;
+ RECT 1180.620000 1165.260000 1181.720000 1165.740000 ;
+ RECT 1180.620000 1170.700000 1181.720000 1171.180000 ;
+ RECT 1135.620000 1225.100000 1136.720000 1225.580000 ;
+ RECT 1135.620000 1230.540000 1136.720000 1231.020000 ;
+ RECT 1135.620000 1235.980000 1136.720000 1236.460000 ;
+ RECT 1135.620000 1241.420000 1136.720000 1241.900000 ;
+ RECT 1090.620000 1225.100000 1091.720000 1225.580000 ;
+ RECT 1090.620000 1230.540000 1091.720000 1231.020000 ;
+ RECT 1090.620000 1235.980000 1091.720000 1236.460000 ;
+ RECT 1090.620000 1241.420000 1091.720000 1241.900000 ;
+ RECT 1135.620000 1197.900000 1136.720000 1198.380000 ;
+ RECT 1135.620000 1203.340000 1136.720000 1203.820000 ;
+ RECT 1135.620000 1208.780000 1136.720000 1209.260000 ;
+ RECT 1135.620000 1214.220000 1136.720000 1214.700000 ;
+ RECT 1135.620000 1219.660000 1136.720000 1220.140000 ;
+ RECT 1090.620000 1197.900000 1091.720000 1198.380000 ;
+ RECT 1090.620000 1203.340000 1091.720000 1203.820000 ;
+ RECT 1090.620000 1208.780000 1091.720000 1209.260000 ;
+ RECT 1090.620000 1214.220000 1091.720000 1214.700000 ;
+ RECT 1090.620000 1219.660000 1091.720000 1220.140000 ;
+ RECT 1041.790000 1241.420000 1042.790000 1241.900000 ;
+ RECT 1045.455000 1241.420000 1046.720000 1241.900000 ;
+ RECT 1041.790000 1235.980000 1042.790000 1236.460000 ;
+ RECT 1045.455000 1235.980000 1046.720000 1236.460000 ;
+ RECT 1041.790000 1230.540000 1042.790000 1231.020000 ;
+ RECT 1045.455000 1230.540000 1046.720000 1231.020000 ;
+ RECT 1041.790000 1225.100000 1042.790000 1225.580000 ;
+ RECT 1045.455000 1225.100000 1046.720000 1225.580000 ;
+ RECT 1041.790000 1219.660000 1042.790000 1220.140000 ;
+ RECT 1045.455000 1219.660000 1046.720000 1220.140000 ;
+ RECT 1041.790000 1214.220000 1042.790000 1214.700000 ;
+ RECT 1045.455000 1214.220000 1046.720000 1214.700000 ;
+ RECT 1041.790000 1203.340000 1042.790000 1203.820000 ;
+ RECT 1045.455000 1203.340000 1046.720000 1203.820000 ;
+ RECT 1041.790000 1208.780000 1042.790000 1209.260000 ;
+ RECT 1045.455000 1208.780000 1046.720000 1209.260000 ;
+ RECT 1041.790000 1197.900000 1042.790000 1198.380000 ;
+ RECT 1045.455000 1197.900000 1046.720000 1198.380000 ;
+ RECT 1135.620000 1176.140000 1136.720000 1176.620000 ;
+ RECT 1135.620000 1181.580000 1136.720000 1182.060000 ;
+ RECT 1135.620000 1187.020000 1136.720000 1187.500000 ;
+ RECT 1135.620000 1192.460000 1136.720000 1192.940000 ;
+ RECT 1090.620000 1176.140000 1091.720000 1176.620000 ;
+ RECT 1090.620000 1181.580000 1091.720000 1182.060000 ;
+ RECT 1090.620000 1187.020000 1091.720000 1187.500000 ;
+ RECT 1090.620000 1192.460000 1091.720000 1192.940000 ;
+ RECT 1135.620000 1154.380000 1136.720000 1154.860000 ;
+ RECT 1135.620000 1159.820000 1136.720000 1160.300000 ;
+ RECT 1135.620000 1165.260000 1136.720000 1165.740000 ;
+ RECT 1135.620000 1170.700000 1136.720000 1171.180000 ;
+ RECT 1090.620000 1154.380000 1091.720000 1154.860000 ;
+ RECT 1090.620000 1159.820000 1091.720000 1160.300000 ;
+ RECT 1090.620000 1165.260000 1091.720000 1165.740000 ;
+ RECT 1090.620000 1170.700000 1091.720000 1171.180000 ;
+ RECT 1041.790000 1192.460000 1042.790000 1192.940000 ;
+ RECT 1045.455000 1192.460000 1046.720000 1192.940000 ;
+ RECT 1041.790000 1187.020000 1042.790000 1187.500000 ;
+ RECT 1045.455000 1187.020000 1046.720000 1187.500000 ;
+ RECT 1041.790000 1181.580000 1042.790000 1182.060000 ;
+ RECT 1045.455000 1181.580000 1046.720000 1182.060000 ;
+ RECT 1041.790000 1176.140000 1042.790000 1176.620000 ;
+ RECT 1045.455000 1176.140000 1046.720000 1176.620000 ;
+ RECT 1041.790000 1170.700000 1042.790000 1171.180000 ;
+ RECT 1045.455000 1170.700000 1046.720000 1171.180000 ;
+ RECT 1041.790000 1159.820000 1042.790000 1160.300000 ;
+ RECT 1045.455000 1159.820000 1046.720000 1160.300000 ;
+ RECT 1041.790000 1165.260000 1042.790000 1165.740000 ;
+ RECT 1045.455000 1165.260000 1046.720000 1165.740000 ;
+ RECT 1041.790000 1154.380000 1042.790000 1154.860000 ;
+ RECT 1045.455000 1154.380000 1046.720000 1154.860000 ;
+ RECT 1180.620000 1246.860000 1181.720000 1247.340000 ;
+ RECT 1225.620000 1246.860000 1226.720000 1247.340000 ;
+ RECT 1238.430000 1246.860000 1239.430000 1247.340000 ;
+ RECT 1090.620000 1246.860000 1091.720000 1247.340000 ;
+ RECT 1135.620000 1246.860000 1136.720000 1247.340000 ;
+ RECT 1041.790000 1246.860000 1042.790000 1247.340000 ;
+ RECT 1045.455000 1246.860000 1046.720000 1247.340000 ;
+ RECT 1040.560000 1343.620000 1240.660000 1344.620000 ;
+ RECT 1040.560000 1148.050000 1240.660000 1149.050000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 1146.800000 1042.790000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 1346.060000 1042.790000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 1146.800000 1239.430000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 1346.060000 1239.430000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1148.050000 1041.560000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1148.050000 1240.660000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1343.620000 1041.560000 1344.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1343.620000 1240.660000 1344.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 1139.080000 1046.720000 1139.560000 ;
+ RECT 1045.455000 1128.200000 1046.720000 1128.680000 ;
+ RECT 1045.455000 1133.640000 1046.720000 1134.120000 ;
+ RECT 1045.455000 1122.760000 1046.720000 1123.240000 ;
+ RECT 1045.455000 1117.320000 1046.720000 1117.800000 ;
+ RECT 1045.455000 1111.880000 1046.720000 1112.360000 ;
+ RECT 1045.455000 1106.440000 1046.720000 1106.920000 ;
+ RECT 1045.455000 1101.000000 1046.720000 1101.480000 ;
+ RECT 1045.455000 1095.560000 1046.720000 1096.040000 ;
+ RECT 1045.455000 1084.680000 1046.720000 1085.160000 ;
+ RECT 1045.455000 1090.120000 1046.720000 1090.600000 ;
+ RECT 1045.455000 1079.240000 1046.720000 1079.720000 ;
+ RECT 1045.455000 1073.800000 1046.720000 1074.280000 ;
+ RECT 1045.455000 1068.360000 1046.720000 1068.840000 ;
+ RECT 1045.455000 1062.920000 1046.720000 1063.400000 ;
+ RECT 1045.455000 1057.480000 1046.720000 1057.960000 ;
+ RECT 1045.455000 1052.040000 1046.720000 1052.520000 ;
+ RECT 1045.455000 1041.160000 1046.720000 1041.640000 ;
+ RECT 1045.455000 1035.720000 1046.720000 1036.200000 ;
+ RECT 1045.455000 1030.280000 1046.720000 1030.760000 ;
+ RECT 1045.455000 1024.840000 1046.720000 1025.320000 ;
+ RECT 1045.455000 1019.400000 1046.720000 1019.880000 ;
+ RECT 1045.455000 1013.960000 1046.720000 1014.440000 ;
+ RECT 1045.455000 1003.080000 1046.720000 1003.560000 ;
+ RECT 1045.455000 1008.520000 1046.720000 1009.000000 ;
+ RECT 1045.455000 997.640000 1046.720000 998.120000 ;
+ RECT 1045.455000 992.200000 1046.720000 992.680000 ;
+ RECT 1045.455000 986.760000 1046.720000 987.240000 ;
+ RECT 1045.455000 981.320000 1046.720000 981.800000 ;
+ RECT 1045.455000 975.880000 1046.720000 976.360000 ;
+ RECT 1045.455000 970.440000 1046.720000 970.920000 ;
+ RECT 1045.455000 959.560000 1046.720000 960.040000 ;
+ RECT 1045.455000 965.000000 1046.720000 965.480000 ;
+ RECT 1045.455000 954.120000 1046.720000 954.600000 ;
+ RECT 1045.455000 1046.600000 1046.720000 1047.080000 ;
+ RECT 1225.620000 947.790000 1226.720000 1144.360000 ;
+ RECT 1180.620000 947.790000 1181.720000 1144.360000 ;
+ RECT 1238.430000 946.540000 1239.430000 1146.800000 ;
+ RECT 1135.620000 947.790000 1136.720000 1144.360000 ;
+ RECT 1090.620000 947.790000 1091.720000 1144.360000 ;
+ RECT 1045.620000 947.790000 1046.720000 1144.360000 ;
+ RECT 1041.790000 946.540000 1042.790000 1146.800000 ;
+ LAYER met3 ;
+ RECT 1225.620000 1139.080000 1226.720000 1139.560000 ;
+ RECT 1238.430000 1139.080000 1239.430000 1139.560000 ;
+ RECT 1238.430000 1128.200000 1239.430000 1128.680000 ;
+ RECT 1238.430000 1122.760000 1239.430000 1123.240000 ;
+ RECT 1238.430000 1133.640000 1239.430000 1134.120000 ;
+ RECT 1225.620000 1133.640000 1226.720000 1134.120000 ;
+ RECT 1225.620000 1128.200000 1226.720000 1128.680000 ;
+ RECT 1225.620000 1122.760000 1226.720000 1123.240000 ;
+ RECT 1225.620000 1111.880000 1226.720000 1112.360000 ;
+ RECT 1225.620000 1117.320000 1226.720000 1117.800000 ;
+ RECT 1238.430000 1111.880000 1239.430000 1112.360000 ;
+ RECT 1238.430000 1117.320000 1239.430000 1117.800000 ;
+ RECT 1225.620000 1101.000000 1226.720000 1101.480000 ;
+ RECT 1225.620000 1106.440000 1226.720000 1106.920000 ;
+ RECT 1238.430000 1101.000000 1239.430000 1101.480000 ;
+ RECT 1238.430000 1106.440000 1239.430000 1106.920000 ;
+ RECT 1180.620000 1122.760000 1181.720000 1123.240000 ;
+ RECT 1180.620000 1128.200000 1181.720000 1128.680000 ;
+ RECT 1180.620000 1133.640000 1181.720000 1134.120000 ;
+ RECT 1180.620000 1139.080000 1181.720000 1139.560000 ;
+ RECT 1180.620000 1106.440000 1181.720000 1106.920000 ;
+ RECT 1180.620000 1101.000000 1181.720000 1101.480000 ;
+ RECT 1180.620000 1111.880000 1181.720000 1112.360000 ;
+ RECT 1180.620000 1117.320000 1181.720000 1117.800000 ;
+ RECT 1238.430000 1090.120000 1239.430000 1090.600000 ;
+ RECT 1238.430000 1084.680000 1239.430000 1085.160000 ;
+ RECT 1238.430000 1095.560000 1239.430000 1096.040000 ;
+ RECT 1225.620000 1095.560000 1226.720000 1096.040000 ;
+ RECT 1225.620000 1090.120000 1226.720000 1090.600000 ;
+ RECT 1225.620000 1084.680000 1226.720000 1085.160000 ;
+ RECT 1225.620000 1073.800000 1226.720000 1074.280000 ;
+ RECT 1225.620000 1079.240000 1226.720000 1079.720000 ;
+ RECT 1238.430000 1073.800000 1239.430000 1074.280000 ;
+ RECT 1238.430000 1079.240000 1239.430000 1079.720000 ;
+ RECT 1238.430000 1062.920000 1239.430000 1063.400000 ;
+ RECT 1238.430000 1068.360000 1239.430000 1068.840000 ;
+ RECT 1225.620000 1068.360000 1226.720000 1068.840000 ;
+ RECT 1225.620000 1062.920000 1226.720000 1063.400000 ;
+ RECT 1225.620000 1052.040000 1226.720000 1052.520000 ;
+ RECT 1225.620000 1057.480000 1226.720000 1057.960000 ;
+ RECT 1238.430000 1052.040000 1239.430000 1052.520000 ;
+ RECT 1238.430000 1057.480000 1239.430000 1057.960000 ;
+ RECT 1180.620000 1073.800000 1181.720000 1074.280000 ;
+ RECT 1180.620000 1079.240000 1181.720000 1079.720000 ;
+ RECT 1180.620000 1084.680000 1181.720000 1085.160000 ;
+ RECT 1180.620000 1090.120000 1181.720000 1090.600000 ;
+ RECT 1180.620000 1095.560000 1181.720000 1096.040000 ;
+ RECT 1180.620000 1052.040000 1181.720000 1052.520000 ;
+ RECT 1180.620000 1057.480000 1181.720000 1057.960000 ;
+ RECT 1180.620000 1062.920000 1181.720000 1063.400000 ;
+ RECT 1180.620000 1068.360000 1181.720000 1068.840000 ;
+ RECT 1135.620000 1128.200000 1136.720000 1128.680000 ;
+ RECT 1135.620000 1122.760000 1136.720000 1123.240000 ;
+ RECT 1135.620000 1133.640000 1136.720000 1134.120000 ;
+ RECT 1135.620000 1139.080000 1136.720000 1139.560000 ;
+ RECT 1090.620000 1122.760000 1091.720000 1123.240000 ;
+ RECT 1090.620000 1128.200000 1091.720000 1128.680000 ;
+ RECT 1090.620000 1133.640000 1091.720000 1134.120000 ;
+ RECT 1090.620000 1139.080000 1091.720000 1139.560000 ;
+ RECT 1135.620000 1101.000000 1136.720000 1101.480000 ;
+ RECT 1135.620000 1106.440000 1136.720000 1106.920000 ;
+ RECT 1135.620000 1111.880000 1136.720000 1112.360000 ;
+ RECT 1135.620000 1117.320000 1136.720000 1117.800000 ;
+ RECT 1090.620000 1101.000000 1091.720000 1101.480000 ;
+ RECT 1090.620000 1106.440000 1091.720000 1106.920000 ;
+ RECT 1090.620000 1111.880000 1091.720000 1112.360000 ;
+ RECT 1090.620000 1117.320000 1091.720000 1117.800000 ;
+ RECT 1041.790000 1139.080000 1042.790000 1139.560000 ;
+ RECT 1045.455000 1139.080000 1046.720000 1139.560000 ;
+ RECT 1041.790000 1128.200000 1042.790000 1128.680000 ;
+ RECT 1045.455000 1128.200000 1046.720000 1128.680000 ;
+ RECT 1041.790000 1133.640000 1042.790000 1134.120000 ;
+ RECT 1045.455000 1133.640000 1046.720000 1134.120000 ;
+ RECT 1041.790000 1122.760000 1042.790000 1123.240000 ;
+ RECT 1045.455000 1122.760000 1046.720000 1123.240000 ;
+ RECT 1041.790000 1117.320000 1042.790000 1117.800000 ;
+ RECT 1045.455000 1117.320000 1046.720000 1117.800000 ;
+ RECT 1041.790000 1111.880000 1042.790000 1112.360000 ;
+ RECT 1045.455000 1111.880000 1046.720000 1112.360000 ;
+ RECT 1041.790000 1106.440000 1042.790000 1106.920000 ;
+ RECT 1045.455000 1106.440000 1046.720000 1106.920000 ;
+ RECT 1041.790000 1101.000000 1042.790000 1101.480000 ;
+ RECT 1045.455000 1101.000000 1046.720000 1101.480000 ;
+ RECT 1135.620000 1073.800000 1136.720000 1074.280000 ;
+ RECT 1135.620000 1079.240000 1136.720000 1079.720000 ;
+ RECT 1135.620000 1084.680000 1136.720000 1085.160000 ;
+ RECT 1135.620000 1090.120000 1136.720000 1090.600000 ;
+ RECT 1135.620000 1095.560000 1136.720000 1096.040000 ;
+ RECT 1090.620000 1073.800000 1091.720000 1074.280000 ;
+ RECT 1090.620000 1079.240000 1091.720000 1079.720000 ;
+ RECT 1090.620000 1084.680000 1091.720000 1085.160000 ;
+ RECT 1090.620000 1090.120000 1091.720000 1090.600000 ;
+ RECT 1090.620000 1095.560000 1091.720000 1096.040000 ;
+ RECT 1135.620000 1052.040000 1136.720000 1052.520000 ;
+ RECT 1135.620000 1057.480000 1136.720000 1057.960000 ;
+ RECT 1135.620000 1062.920000 1136.720000 1063.400000 ;
+ RECT 1135.620000 1068.360000 1136.720000 1068.840000 ;
+ RECT 1090.620000 1052.040000 1091.720000 1052.520000 ;
+ RECT 1090.620000 1057.480000 1091.720000 1057.960000 ;
+ RECT 1090.620000 1062.920000 1091.720000 1063.400000 ;
+ RECT 1090.620000 1068.360000 1091.720000 1068.840000 ;
+ RECT 1041.790000 1095.560000 1042.790000 1096.040000 ;
+ RECT 1045.455000 1095.560000 1046.720000 1096.040000 ;
+ RECT 1041.790000 1084.680000 1042.790000 1085.160000 ;
+ RECT 1045.455000 1084.680000 1046.720000 1085.160000 ;
+ RECT 1041.790000 1090.120000 1042.790000 1090.600000 ;
+ RECT 1045.455000 1090.120000 1046.720000 1090.600000 ;
+ RECT 1041.790000 1079.240000 1042.790000 1079.720000 ;
+ RECT 1045.455000 1079.240000 1046.720000 1079.720000 ;
+ RECT 1041.790000 1073.800000 1042.790000 1074.280000 ;
+ RECT 1045.455000 1073.800000 1046.720000 1074.280000 ;
+ RECT 1041.790000 1068.360000 1042.790000 1068.840000 ;
+ RECT 1045.455000 1068.360000 1046.720000 1068.840000 ;
+ RECT 1041.790000 1062.920000 1042.790000 1063.400000 ;
+ RECT 1045.455000 1062.920000 1046.720000 1063.400000 ;
+ RECT 1041.790000 1057.480000 1042.790000 1057.960000 ;
+ RECT 1045.455000 1057.480000 1046.720000 1057.960000 ;
+ RECT 1041.790000 1052.040000 1042.790000 1052.520000 ;
+ RECT 1045.455000 1052.040000 1046.720000 1052.520000 ;
+ RECT 1225.620000 1035.720000 1226.720000 1036.200000 ;
+ RECT 1225.620000 1041.160000 1226.720000 1041.640000 ;
+ RECT 1238.430000 1035.720000 1239.430000 1036.200000 ;
+ RECT 1238.430000 1041.160000 1239.430000 1041.640000 ;
+ RECT 1238.430000 1024.840000 1239.430000 1025.320000 ;
+ RECT 1238.430000 1030.280000 1239.430000 1030.760000 ;
+ RECT 1225.620000 1030.280000 1226.720000 1030.760000 ;
+ RECT 1225.620000 1024.840000 1226.720000 1025.320000 ;
+ RECT 1225.620000 1013.960000 1226.720000 1014.440000 ;
+ RECT 1225.620000 1019.400000 1226.720000 1019.880000 ;
+ RECT 1238.430000 1013.960000 1239.430000 1014.440000 ;
+ RECT 1238.430000 1019.400000 1239.430000 1019.880000 ;
+ RECT 1238.430000 1003.080000 1239.430000 1003.560000 ;
+ RECT 1238.430000 997.640000 1239.430000 998.120000 ;
+ RECT 1238.430000 1008.520000 1239.430000 1009.000000 ;
+ RECT 1225.620000 1008.520000 1226.720000 1009.000000 ;
+ RECT 1225.620000 1003.080000 1226.720000 1003.560000 ;
+ RECT 1225.620000 997.640000 1226.720000 998.120000 ;
+ RECT 1180.620000 1024.840000 1181.720000 1025.320000 ;
+ RECT 1180.620000 1030.280000 1181.720000 1030.760000 ;
+ RECT 1180.620000 1035.720000 1181.720000 1036.200000 ;
+ RECT 1180.620000 1041.160000 1181.720000 1041.640000 ;
+ RECT 1180.620000 997.640000 1181.720000 998.120000 ;
+ RECT 1180.620000 1003.080000 1181.720000 1003.560000 ;
+ RECT 1180.620000 1008.520000 1181.720000 1009.000000 ;
+ RECT 1180.620000 1013.960000 1181.720000 1014.440000 ;
+ RECT 1180.620000 1019.400000 1181.720000 1019.880000 ;
+ RECT 1225.620000 986.760000 1226.720000 987.240000 ;
+ RECT 1225.620000 992.200000 1226.720000 992.680000 ;
+ RECT 1238.430000 986.760000 1239.430000 987.240000 ;
+ RECT 1238.430000 992.200000 1239.430000 992.680000 ;
+ RECT 1225.620000 975.880000 1226.720000 976.360000 ;
+ RECT 1225.620000 981.320000 1226.720000 981.800000 ;
+ RECT 1238.430000 975.880000 1239.430000 976.360000 ;
+ RECT 1238.430000 981.320000 1239.430000 981.800000 ;
+ RECT 1238.430000 965.000000 1239.430000 965.480000 ;
+ RECT 1238.430000 959.560000 1239.430000 960.040000 ;
+ RECT 1238.430000 970.440000 1239.430000 970.920000 ;
+ RECT 1225.620000 970.440000 1226.720000 970.920000 ;
+ RECT 1225.620000 965.000000 1226.720000 965.480000 ;
+ RECT 1225.620000 959.560000 1226.720000 960.040000 ;
+ RECT 1225.620000 954.120000 1226.720000 954.600000 ;
+ RECT 1238.430000 954.120000 1239.430000 954.600000 ;
+ RECT 1180.620000 975.880000 1181.720000 976.360000 ;
+ RECT 1180.620000 981.320000 1181.720000 981.800000 ;
+ RECT 1180.620000 986.760000 1181.720000 987.240000 ;
+ RECT 1180.620000 992.200000 1181.720000 992.680000 ;
+ RECT 1180.620000 954.120000 1181.720000 954.600000 ;
+ RECT 1180.620000 959.560000 1181.720000 960.040000 ;
+ RECT 1180.620000 965.000000 1181.720000 965.480000 ;
+ RECT 1180.620000 970.440000 1181.720000 970.920000 ;
+ RECT 1135.620000 1024.840000 1136.720000 1025.320000 ;
+ RECT 1135.620000 1030.280000 1136.720000 1030.760000 ;
+ RECT 1135.620000 1035.720000 1136.720000 1036.200000 ;
+ RECT 1135.620000 1041.160000 1136.720000 1041.640000 ;
+ RECT 1090.620000 1024.840000 1091.720000 1025.320000 ;
+ RECT 1090.620000 1030.280000 1091.720000 1030.760000 ;
+ RECT 1090.620000 1035.720000 1091.720000 1036.200000 ;
+ RECT 1090.620000 1041.160000 1091.720000 1041.640000 ;
+ RECT 1135.620000 997.640000 1136.720000 998.120000 ;
+ RECT 1135.620000 1003.080000 1136.720000 1003.560000 ;
+ RECT 1135.620000 1008.520000 1136.720000 1009.000000 ;
+ RECT 1135.620000 1013.960000 1136.720000 1014.440000 ;
+ RECT 1135.620000 1019.400000 1136.720000 1019.880000 ;
+ RECT 1090.620000 997.640000 1091.720000 998.120000 ;
+ RECT 1090.620000 1003.080000 1091.720000 1003.560000 ;
+ RECT 1090.620000 1008.520000 1091.720000 1009.000000 ;
+ RECT 1090.620000 1013.960000 1091.720000 1014.440000 ;
+ RECT 1090.620000 1019.400000 1091.720000 1019.880000 ;
+ RECT 1041.790000 1041.160000 1042.790000 1041.640000 ;
+ RECT 1045.455000 1041.160000 1046.720000 1041.640000 ;
+ RECT 1041.790000 1035.720000 1042.790000 1036.200000 ;
+ RECT 1045.455000 1035.720000 1046.720000 1036.200000 ;
+ RECT 1041.790000 1030.280000 1042.790000 1030.760000 ;
+ RECT 1045.455000 1030.280000 1046.720000 1030.760000 ;
+ RECT 1041.790000 1024.840000 1042.790000 1025.320000 ;
+ RECT 1045.455000 1024.840000 1046.720000 1025.320000 ;
+ RECT 1041.790000 1019.400000 1042.790000 1019.880000 ;
+ RECT 1045.455000 1019.400000 1046.720000 1019.880000 ;
+ RECT 1041.790000 1013.960000 1042.790000 1014.440000 ;
+ RECT 1045.455000 1013.960000 1046.720000 1014.440000 ;
+ RECT 1041.790000 1003.080000 1042.790000 1003.560000 ;
+ RECT 1045.455000 1003.080000 1046.720000 1003.560000 ;
+ RECT 1041.790000 1008.520000 1042.790000 1009.000000 ;
+ RECT 1045.455000 1008.520000 1046.720000 1009.000000 ;
+ RECT 1041.790000 997.640000 1042.790000 998.120000 ;
+ RECT 1045.455000 997.640000 1046.720000 998.120000 ;
+ RECT 1135.620000 975.880000 1136.720000 976.360000 ;
+ RECT 1135.620000 981.320000 1136.720000 981.800000 ;
+ RECT 1135.620000 986.760000 1136.720000 987.240000 ;
+ RECT 1135.620000 992.200000 1136.720000 992.680000 ;
+ RECT 1090.620000 975.880000 1091.720000 976.360000 ;
+ RECT 1090.620000 981.320000 1091.720000 981.800000 ;
+ RECT 1090.620000 986.760000 1091.720000 987.240000 ;
+ RECT 1090.620000 992.200000 1091.720000 992.680000 ;
+ RECT 1135.620000 954.120000 1136.720000 954.600000 ;
+ RECT 1135.620000 959.560000 1136.720000 960.040000 ;
+ RECT 1135.620000 965.000000 1136.720000 965.480000 ;
+ RECT 1135.620000 970.440000 1136.720000 970.920000 ;
+ RECT 1090.620000 954.120000 1091.720000 954.600000 ;
+ RECT 1090.620000 959.560000 1091.720000 960.040000 ;
+ RECT 1090.620000 965.000000 1091.720000 965.480000 ;
+ RECT 1090.620000 970.440000 1091.720000 970.920000 ;
+ RECT 1041.790000 992.200000 1042.790000 992.680000 ;
+ RECT 1045.455000 992.200000 1046.720000 992.680000 ;
+ RECT 1041.790000 986.760000 1042.790000 987.240000 ;
+ RECT 1045.455000 986.760000 1046.720000 987.240000 ;
+ RECT 1041.790000 981.320000 1042.790000 981.800000 ;
+ RECT 1045.455000 981.320000 1046.720000 981.800000 ;
+ RECT 1041.790000 975.880000 1042.790000 976.360000 ;
+ RECT 1045.455000 975.880000 1046.720000 976.360000 ;
+ RECT 1041.790000 970.440000 1042.790000 970.920000 ;
+ RECT 1045.455000 970.440000 1046.720000 970.920000 ;
+ RECT 1041.790000 959.560000 1042.790000 960.040000 ;
+ RECT 1045.455000 959.560000 1046.720000 960.040000 ;
+ RECT 1041.790000 965.000000 1042.790000 965.480000 ;
+ RECT 1045.455000 965.000000 1046.720000 965.480000 ;
+ RECT 1041.790000 954.120000 1042.790000 954.600000 ;
+ RECT 1045.455000 954.120000 1046.720000 954.600000 ;
+ RECT 1180.620000 1046.600000 1181.720000 1047.080000 ;
+ RECT 1225.620000 1046.600000 1226.720000 1047.080000 ;
+ RECT 1238.430000 1046.600000 1239.430000 1047.080000 ;
+ RECT 1090.620000 1046.600000 1091.720000 1047.080000 ;
+ RECT 1135.620000 1046.600000 1136.720000 1047.080000 ;
+ RECT 1041.790000 1046.600000 1042.790000 1047.080000 ;
+ RECT 1045.455000 1046.600000 1046.720000 1047.080000 ;
+ RECT 1040.560000 1143.360000 1240.660000 1144.360000 ;
+ RECT 1040.560000 947.790000 1240.660000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 946.540000 1042.790000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 1145.800000 1042.790000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 946.540000 1239.430000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 1145.800000 1239.430000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 947.790000 1041.560000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 947.790000 1240.660000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1143.360000 1041.560000 1144.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1143.360000 1240.660000 1144.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 938.820000 1046.720000 939.300000 ;
+ RECT 1045.455000 927.940000 1046.720000 928.420000 ;
+ RECT 1045.455000 933.380000 1046.720000 933.860000 ;
+ RECT 1045.455000 922.500000 1046.720000 922.980000 ;
+ RECT 1045.455000 917.060000 1046.720000 917.540000 ;
+ RECT 1045.455000 911.620000 1046.720000 912.100000 ;
+ RECT 1045.455000 906.180000 1046.720000 906.660000 ;
+ RECT 1045.455000 900.740000 1046.720000 901.220000 ;
+ RECT 1045.455000 895.300000 1046.720000 895.780000 ;
+ RECT 1045.455000 884.420000 1046.720000 884.900000 ;
+ RECT 1045.455000 889.860000 1046.720000 890.340000 ;
+ RECT 1045.455000 878.980000 1046.720000 879.460000 ;
+ RECT 1045.455000 873.540000 1046.720000 874.020000 ;
+ RECT 1045.455000 868.100000 1046.720000 868.580000 ;
+ RECT 1045.455000 862.660000 1046.720000 863.140000 ;
+ RECT 1045.455000 857.220000 1046.720000 857.700000 ;
+ RECT 1045.455000 851.780000 1046.720000 852.260000 ;
+ RECT 1045.455000 840.900000 1046.720000 841.380000 ;
+ RECT 1045.455000 835.460000 1046.720000 835.940000 ;
+ RECT 1045.455000 830.020000 1046.720000 830.500000 ;
+ RECT 1045.455000 824.580000 1046.720000 825.060000 ;
+ RECT 1045.455000 819.140000 1046.720000 819.620000 ;
+ RECT 1045.455000 813.700000 1046.720000 814.180000 ;
+ RECT 1045.455000 802.820000 1046.720000 803.300000 ;
+ RECT 1045.455000 808.260000 1046.720000 808.740000 ;
+ RECT 1045.455000 797.380000 1046.720000 797.860000 ;
+ RECT 1045.455000 791.940000 1046.720000 792.420000 ;
+ RECT 1045.455000 786.500000 1046.720000 786.980000 ;
+ RECT 1045.455000 781.060000 1046.720000 781.540000 ;
+ RECT 1045.455000 775.620000 1046.720000 776.100000 ;
+ RECT 1045.455000 770.180000 1046.720000 770.660000 ;
+ RECT 1045.455000 759.300000 1046.720000 759.780000 ;
+ RECT 1045.455000 764.740000 1046.720000 765.220000 ;
+ RECT 1045.455000 753.860000 1046.720000 754.340000 ;
+ RECT 1045.455000 846.340000 1046.720000 846.820000 ;
+ RECT 1225.620000 747.530000 1226.720000 944.100000 ;
+ RECT 1180.620000 747.530000 1181.720000 944.100000 ;
+ RECT 1238.430000 746.280000 1239.430000 946.540000 ;
+ RECT 1135.620000 747.530000 1136.720000 944.100000 ;
+ RECT 1090.620000 747.530000 1091.720000 944.100000 ;
+ RECT 1045.620000 747.530000 1046.720000 944.100000 ;
+ RECT 1041.790000 746.280000 1042.790000 946.540000 ;
+ LAYER met3 ;
+ RECT 1225.620000 938.820000 1226.720000 939.300000 ;
+ RECT 1238.430000 938.820000 1239.430000 939.300000 ;
+ RECT 1238.430000 927.940000 1239.430000 928.420000 ;
+ RECT 1238.430000 922.500000 1239.430000 922.980000 ;
+ RECT 1238.430000 933.380000 1239.430000 933.860000 ;
+ RECT 1225.620000 933.380000 1226.720000 933.860000 ;
+ RECT 1225.620000 927.940000 1226.720000 928.420000 ;
+ RECT 1225.620000 922.500000 1226.720000 922.980000 ;
+ RECT 1225.620000 911.620000 1226.720000 912.100000 ;
+ RECT 1225.620000 917.060000 1226.720000 917.540000 ;
+ RECT 1238.430000 911.620000 1239.430000 912.100000 ;
+ RECT 1238.430000 917.060000 1239.430000 917.540000 ;
+ RECT 1225.620000 900.740000 1226.720000 901.220000 ;
+ RECT 1225.620000 906.180000 1226.720000 906.660000 ;
+ RECT 1238.430000 900.740000 1239.430000 901.220000 ;
+ RECT 1238.430000 906.180000 1239.430000 906.660000 ;
+ RECT 1180.620000 922.500000 1181.720000 922.980000 ;
+ RECT 1180.620000 927.940000 1181.720000 928.420000 ;
+ RECT 1180.620000 933.380000 1181.720000 933.860000 ;
+ RECT 1180.620000 938.820000 1181.720000 939.300000 ;
+ RECT 1180.620000 906.180000 1181.720000 906.660000 ;
+ RECT 1180.620000 900.740000 1181.720000 901.220000 ;
+ RECT 1180.620000 911.620000 1181.720000 912.100000 ;
+ RECT 1180.620000 917.060000 1181.720000 917.540000 ;
+ RECT 1238.430000 889.860000 1239.430000 890.340000 ;
+ RECT 1238.430000 884.420000 1239.430000 884.900000 ;
+ RECT 1238.430000 895.300000 1239.430000 895.780000 ;
+ RECT 1225.620000 895.300000 1226.720000 895.780000 ;
+ RECT 1225.620000 889.860000 1226.720000 890.340000 ;
+ RECT 1225.620000 884.420000 1226.720000 884.900000 ;
+ RECT 1225.620000 873.540000 1226.720000 874.020000 ;
+ RECT 1225.620000 878.980000 1226.720000 879.460000 ;
+ RECT 1238.430000 873.540000 1239.430000 874.020000 ;
+ RECT 1238.430000 878.980000 1239.430000 879.460000 ;
+ RECT 1238.430000 862.660000 1239.430000 863.140000 ;
+ RECT 1238.430000 868.100000 1239.430000 868.580000 ;
+ RECT 1225.620000 868.100000 1226.720000 868.580000 ;
+ RECT 1225.620000 862.660000 1226.720000 863.140000 ;
+ RECT 1225.620000 851.780000 1226.720000 852.260000 ;
+ RECT 1225.620000 857.220000 1226.720000 857.700000 ;
+ RECT 1238.430000 851.780000 1239.430000 852.260000 ;
+ RECT 1238.430000 857.220000 1239.430000 857.700000 ;
+ RECT 1180.620000 873.540000 1181.720000 874.020000 ;
+ RECT 1180.620000 878.980000 1181.720000 879.460000 ;
+ RECT 1180.620000 884.420000 1181.720000 884.900000 ;
+ RECT 1180.620000 889.860000 1181.720000 890.340000 ;
+ RECT 1180.620000 895.300000 1181.720000 895.780000 ;
+ RECT 1180.620000 851.780000 1181.720000 852.260000 ;
+ RECT 1180.620000 857.220000 1181.720000 857.700000 ;
+ RECT 1180.620000 862.660000 1181.720000 863.140000 ;
+ RECT 1180.620000 868.100000 1181.720000 868.580000 ;
+ RECT 1135.620000 927.940000 1136.720000 928.420000 ;
+ RECT 1135.620000 922.500000 1136.720000 922.980000 ;
+ RECT 1135.620000 933.380000 1136.720000 933.860000 ;
+ RECT 1135.620000 938.820000 1136.720000 939.300000 ;
+ RECT 1090.620000 922.500000 1091.720000 922.980000 ;
+ RECT 1090.620000 927.940000 1091.720000 928.420000 ;
+ RECT 1090.620000 933.380000 1091.720000 933.860000 ;
+ RECT 1090.620000 938.820000 1091.720000 939.300000 ;
+ RECT 1135.620000 900.740000 1136.720000 901.220000 ;
+ RECT 1135.620000 906.180000 1136.720000 906.660000 ;
+ RECT 1135.620000 911.620000 1136.720000 912.100000 ;
+ RECT 1135.620000 917.060000 1136.720000 917.540000 ;
+ RECT 1090.620000 900.740000 1091.720000 901.220000 ;
+ RECT 1090.620000 906.180000 1091.720000 906.660000 ;
+ RECT 1090.620000 911.620000 1091.720000 912.100000 ;
+ RECT 1090.620000 917.060000 1091.720000 917.540000 ;
+ RECT 1041.790000 938.820000 1042.790000 939.300000 ;
+ RECT 1045.455000 938.820000 1046.720000 939.300000 ;
+ RECT 1041.790000 927.940000 1042.790000 928.420000 ;
+ RECT 1045.455000 927.940000 1046.720000 928.420000 ;
+ RECT 1041.790000 933.380000 1042.790000 933.860000 ;
+ RECT 1045.455000 933.380000 1046.720000 933.860000 ;
+ RECT 1041.790000 922.500000 1042.790000 922.980000 ;
+ RECT 1045.455000 922.500000 1046.720000 922.980000 ;
+ RECT 1041.790000 917.060000 1042.790000 917.540000 ;
+ RECT 1045.455000 917.060000 1046.720000 917.540000 ;
+ RECT 1041.790000 911.620000 1042.790000 912.100000 ;
+ RECT 1045.455000 911.620000 1046.720000 912.100000 ;
+ RECT 1041.790000 906.180000 1042.790000 906.660000 ;
+ RECT 1045.455000 906.180000 1046.720000 906.660000 ;
+ RECT 1041.790000 900.740000 1042.790000 901.220000 ;
+ RECT 1045.455000 900.740000 1046.720000 901.220000 ;
+ RECT 1135.620000 873.540000 1136.720000 874.020000 ;
+ RECT 1135.620000 878.980000 1136.720000 879.460000 ;
+ RECT 1135.620000 884.420000 1136.720000 884.900000 ;
+ RECT 1135.620000 889.860000 1136.720000 890.340000 ;
+ RECT 1135.620000 895.300000 1136.720000 895.780000 ;
+ RECT 1090.620000 873.540000 1091.720000 874.020000 ;
+ RECT 1090.620000 878.980000 1091.720000 879.460000 ;
+ RECT 1090.620000 884.420000 1091.720000 884.900000 ;
+ RECT 1090.620000 889.860000 1091.720000 890.340000 ;
+ RECT 1090.620000 895.300000 1091.720000 895.780000 ;
+ RECT 1135.620000 851.780000 1136.720000 852.260000 ;
+ RECT 1135.620000 857.220000 1136.720000 857.700000 ;
+ RECT 1135.620000 862.660000 1136.720000 863.140000 ;
+ RECT 1135.620000 868.100000 1136.720000 868.580000 ;
+ RECT 1090.620000 851.780000 1091.720000 852.260000 ;
+ RECT 1090.620000 857.220000 1091.720000 857.700000 ;
+ RECT 1090.620000 862.660000 1091.720000 863.140000 ;
+ RECT 1090.620000 868.100000 1091.720000 868.580000 ;
+ RECT 1041.790000 895.300000 1042.790000 895.780000 ;
+ RECT 1045.455000 895.300000 1046.720000 895.780000 ;
+ RECT 1041.790000 884.420000 1042.790000 884.900000 ;
+ RECT 1045.455000 884.420000 1046.720000 884.900000 ;
+ RECT 1041.790000 889.860000 1042.790000 890.340000 ;
+ RECT 1045.455000 889.860000 1046.720000 890.340000 ;
+ RECT 1041.790000 878.980000 1042.790000 879.460000 ;
+ RECT 1045.455000 878.980000 1046.720000 879.460000 ;
+ RECT 1041.790000 873.540000 1042.790000 874.020000 ;
+ RECT 1045.455000 873.540000 1046.720000 874.020000 ;
+ RECT 1041.790000 868.100000 1042.790000 868.580000 ;
+ RECT 1045.455000 868.100000 1046.720000 868.580000 ;
+ RECT 1041.790000 862.660000 1042.790000 863.140000 ;
+ RECT 1045.455000 862.660000 1046.720000 863.140000 ;
+ RECT 1041.790000 857.220000 1042.790000 857.700000 ;
+ RECT 1045.455000 857.220000 1046.720000 857.700000 ;
+ RECT 1041.790000 851.780000 1042.790000 852.260000 ;
+ RECT 1045.455000 851.780000 1046.720000 852.260000 ;
+ RECT 1225.620000 835.460000 1226.720000 835.940000 ;
+ RECT 1225.620000 840.900000 1226.720000 841.380000 ;
+ RECT 1238.430000 835.460000 1239.430000 835.940000 ;
+ RECT 1238.430000 840.900000 1239.430000 841.380000 ;
+ RECT 1238.430000 824.580000 1239.430000 825.060000 ;
+ RECT 1238.430000 830.020000 1239.430000 830.500000 ;
+ RECT 1225.620000 830.020000 1226.720000 830.500000 ;
+ RECT 1225.620000 824.580000 1226.720000 825.060000 ;
+ RECT 1225.620000 813.700000 1226.720000 814.180000 ;
+ RECT 1225.620000 819.140000 1226.720000 819.620000 ;
+ RECT 1238.430000 813.700000 1239.430000 814.180000 ;
+ RECT 1238.430000 819.140000 1239.430000 819.620000 ;
+ RECT 1238.430000 802.820000 1239.430000 803.300000 ;
+ RECT 1238.430000 797.380000 1239.430000 797.860000 ;
+ RECT 1238.430000 808.260000 1239.430000 808.740000 ;
+ RECT 1225.620000 808.260000 1226.720000 808.740000 ;
+ RECT 1225.620000 802.820000 1226.720000 803.300000 ;
+ RECT 1225.620000 797.380000 1226.720000 797.860000 ;
+ RECT 1180.620000 824.580000 1181.720000 825.060000 ;
+ RECT 1180.620000 830.020000 1181.720000 830.500000 ;
+ RECT 1180.620000 835.460000 1181.720000 835.940000 ;
+ RECT 1180.620000 840.900000 1181.720000 841.380000 ;
+ RECT 1180.620000 797.380000 1181.720000 797.860000 ;
+ RECT 1180.620000 802.820000 1181.720000 803.300000 ;
+ RECT 1180.620000 808.260000 1181.720000 808.740000 ;
+ RECT 1180.620000 813.700000 1181.720000 814.180000 ;
+ RECT 1180.620000 819.140000 1181.720000 819.620000 ;
+ RECT 1225.620000 786.500000 1226.720000 786.980000 ;
+ RECT 1225.620000 791.940000 1226.720000 792.420000 ;
+ RECT 1238.430000 786.500000 1239.430000 786.980000 ;
+ RECT 1238.430000 791.940000 1239.430000 792.420000 ;
+ RECT 1225.620000 775.620000 1226.720000 776.100000 ;
+ RECT 1225.620000 781.060000 1226.720000 781.540000 ;
+ RECT 1238.430000 775.620000 1239.430000 776.100000 ;
+ RECT 1238.430000 781.060000 1239.430000 781.540000 ;
+ RECT 1238.430000 764.740000 1239.430000 765.220000 ;
+ RECT 1238.430000 759.300000 1239.430000 759.780000 ;
+ RECT 1238.430000 770.180000 1239.430000 770.660000 ;
+ RECT 1225.620000 770.180000 1226.720000 770.660000 ;
+ RECT 1225.620000 764.740000 1226.720000 765.220000 ;
+ RECT 1225.620000 759.300000 1226.720000 759.780000 ;
+ RECT 1225.620000 753.860000 1226.720000 754.340000 ;
+ RECT 1238.430000 753.860000 1239.430000 754.340000 ;
+ RECT 1180.620000 775.620000 1181.720000 776.100000 ;
+ RECT 1180.620000 781.060000 1181.720000 781.540000 ;
+ RECT 1180.620000 786.500000 1181.720000 786.980000 ;
+ RECT 1180.620000 791.940000 1181.720000 792.420000 ;
+ RECT 1180.620000 753.860000 1181.720000 754.340000 ;
+ RECT 1180.620000 759.300000 1181.720000 759.780000 ;
+ RECT 1180.620000 764.740000 1181.720000 765.220000 ;
+ RECT 1180.620000 770.180000 1181.720000 770.660000 ;
+ RECT 1135.620000 824.580000 1136.720000 825.060000 ;
+ RECT 1135.620000 830.020000 1136.720000 830.500000 ;
+ RECT 1135.620000 835.460000 1136.720000 835.940000 ;
+ RECT 1135.620000 840.900000 1136.720000 841.380000 ;
+ RECT 1090.620000 824.580000 1091.720000 825.060000 ;
+ RECT 1090.620000 830.020000 1091.720000 830.500000 ;
+ RECT 1090.620000 835.460000 1091.720000 835.940000 ;
+ RECT 1090.620000 840.900000 1091.720000 841.380000 ;
+ RECT 1135.620000 797.380000 1136.720000 797.860000 ;
+ RECT 1135.620000 802.820000 1136.720000 803.300000 ;
+ RECT 1135.620000 808.260000 1136.720000 808.740000 ;
+ RECT 1135.620000 813.700000 1136.720000 814.180000 ;
+ RECT 1135.620000 819.140000 1136.720000 819.620000 ;
+ RECT 1090.620000 797.380000 1091.720000 797.860000 ;
+ RECT 1090.620000 802.820000 1091.720000 803.300000 ;
+ RECT 1090.620000 808.260000 1091.720000 808.740000 ;
+ RECT 1090.620000 813.700000 1091.720000 814.180000 ;
+ RECT 1090.620000 819.140000 1091.720000 819.620000 ;
+ RECT 1041.790000 840.900000 1042.790000 841.380000 ;
+ RECT 1045.455000 840.900000 1046.720000 841.380000 ;
+ RECT 1041.790000 835.460000 1042.790000 835.940000 ;
+ RECT 1045.455000 835.460000 1046.720000 835.940000 ;
+ RECT 1041.790000 830.020000 1042.790000 830.500000 ;
+ RECT 1045.455000 830.020000 1046.720000 830.500000 ;
+ RECT 1041.790000 824.580000 1042.790000 825.060000 ;
+ RECT 1045.455000 824.580000 1046.720000 825.060000 ;
+ RECT 1041.790000 819.140000 1042.790000 819.620000 ;
+ RECT 1045.455000 819.140000 1046.720000 819.620000 ;
+ RECT 1041.790000 813.700000 1042.790000 814.180000 ;
+ RECT 1045.455000 813.700000 1046.720000 814.180000 ;
+ RECT 1041.790000 802.820000 1042.790000 803.300000 ;
+ RECT 1045.455000 802.820000 1046.720000 803.300000 ;
+ RECT 1041.790000 808.260000 1042.790000 808.740000 ;
+ RECT 1045.455000 808.260000 1046.720000 808.740000 ;
+ RECT 1041.790000 797.380000 1042.790000 797.860000 ;
+ RECT 1045.455000 797.380000 1046.720000 797.860000 ;
+ RECT 1135.620000 775.620000 1136.720000 776.100000 ;
+ RECT 1135.620000 781.060000 1136.720000 781.540000 ;
+ RECT 1135.620000 786.500000 1136.720000 786.980000 ;
+ RECT 1135.620000 791.940000 1136.720000 792.420000 ;
+ RECT 1090.620000 775.620000 1091.720000 776.100000 ;
+ RECT 1090.620000 781.060000 1091.720000 781.540000 ;
+ RECT 1090.620000 786.500000 1091.720000 786.980000 ;
+ RECT 1090.620000 791.940000 1091.720000 792.420000 ;
+ RECT 1135.620000 753.860000 1136.720000 754.340000 ;
+ RECT 1135.620000 759.300000 1136.720000 759.780000 ;
+ RECT 1135.620000 764.740000 1136.720000 765.220000 ;
+ RECT 1135.620000 770.180000 1136.720000 770.660000 ;
+ RECT 1090.620000 753.860000 1091.720000 754.340000 ;
+ RECT 1090.620000 759.300000 1091.720000 759.780000 ;
+ RECT 1090.620000 764.740000 1091.720000 765.220000 ;
+ RECT 1090.620000 770.180000 1091.720000 770.660000 ;
+ RECT 1041.790000 791.940000 1042.790000 792.420000 ;
+ RECT 1045.455000 791.940000 1046.720000 792.420000 ;
+ RECT 1041.790000 786.500000 1042.790000 786.980000 ;
+ RECT 1045.455000 786.500000 1046.720000 786.980000 ;
+ RECT 1041.790000 781.060000 1042.790000 781.540000 ;
+ RECT 1045.455000 781.060000 1046.720000 781.540000 ;
+ RECT 1041.790000 775.620000 1042.790000 776.100000 ;
+ RECT 1045.455000 775.620000 1046.720000 776.100000 ;
+ RECT 1041.790000 770.180000 1042.790000 770.660000 ;
+ RECT 1045.455000 770.180000 1046.720000 770.660000 ;
+ RECT 1041.790000 759.300000 1042.790000 759.780000 ;
+ RECT 1045.455000 759.300000 1046.720000 759.780000 ;
+ RECT 1041.790000 764.740000 1042.790000 765.220000 ;
+ RECT 1045.455000 764.740000 1046.720000 765.220000 ;
+ RECT 1041.790000 753.860000 1042.790000 754.340000 ;
+ RECT 1045.455000 753.860000 1046.720000 754.340000 ;
+ RECT 1180.620000 846.340000 1181.720000 846.820000 ;
+ RECT 1225.620000 846.340000 1226.720000 846.820000 ;
+ RECT 1238.430000 846.340000 1239.430000 846.820000 ;
+ RECT 1090.620000 846.340000 1091.720000 846.820000 ;
+ RECT 1135.620000 846.340000 1136.720000 846.820000 ;
+ RECT 1041.790000 846.340000 1042.790000 846.820000 ;
+ RECT 1045.455000 846.340000 1046.720000 846.820000 ;
+ RECT 1040.560000 943.100000 1240.660000 944.100000 ;
+ RECT 1040.560000 747.530000 1240.660000 748.530000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 746.280000 1042.790000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 945.540000 1042.790000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 746.280000 1239.430000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 945.540000 1239.430000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 747.530000 1041.560000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 747.530000 1240.660000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 943.100000 1041.560000 944.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 943.100000 1240.660000 944.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 738.560000 1046.720000 739.040000 ;
+ RECT 1045.455000 727.680000 1046.720000 728.160000 ;
+ RECT 1045.455000 733.120000 1046.720000 733.600000 ;
+ RECT 1045.455000 722.240000 1046.720000 722.720000 ;
+ RECT 1045.455000 716.800000 1046.720000 717.280000 ;
+ RECT 1045.455000 711.360000 1046.720000 711.840000 ;
+ RECT 1045.455000 705.920000 1046.720000 706.400000 ;
+ RECT 1045.455000 700.480000 1046.720000 700.960000 ;
+ RECT 1045.455000 695.040000 1046.720000 695.520000 ;
+ RECT 1045.455000 684.160000 1046.720000 684.640000 ;
+ RECT 1045.455000 689.600000 1046.720000 690.080000 ;
+ RECT 1045.455000 678.720000 1046.720000 679.200000 ;
+ RECT 1045.455000 673.280000 1046.720000 673.760000 ;
+ RECT 1045.455000 667.840000 1046.720000 668.320000 ;
+ RECT 1045.455000 662.400000 1046.720000 662.880000 ;
+ RECT 1045.455000 656.960000 1046.720000 657.440000 ;
+ RECT 1045.455000 651.520000 1046.720000 652.000000 ;
+ RECT 1045.455000 640.640000 1046.720000 641.120000 ;
+ RECT 1045.455000 635.200000 1046.720000 635.680000 ;
+ RECT 1045.455000 629.760000 1046.720000 630.240000 ;
+ RECT 1045.455000 624.320000 1046.720000 624.800000 ;
+ RECT 1045.455000 618.880000 1046.720000 619.360000 ;
+ RECT 1045.455000 613.440000 1046.720000 613.920000 ;
+ RECT 1045.455000 602.560000 1046.720000 603.040000 ;
+ RECT 1045.455000 608.000000 1046.720000 608.480000 ;
+ RECT 1045.455000 597.120000 1046.720000 597.600000 ;
+ RECT 1045.455000 591.680000 1046.720000 592.160000 ;
+ RECT 1045.455000 586.240000 1046.720000 586.720000 ;
+ RECT 1045.455000 580.800000 1046.720000 581.280000 ;
+ RECT 1045.455000 575.360000 1046.720000 575.840000 ;
+ RECT 1045.455000 569.920000 1046.720000 570.400000 ;
+ RECT 1045.455000 559.040000 1046.720000 559.520000 ;
+ RECT 1045.455000 564.480000 1046.720000 564.960000 ;
+ RECT 1045.455000 553.600000 1046.720000 554.080000 ;
+ RECT 1045.455000 646.080000 1046.720000 646.560000 ;
+ RECT 1225.620000 547.270000 1226.720000 743.840000 ;
+ RECT 1180.620000 547.270000 1181.720000 743.840000 ;
+ RECT 1238.430000 546.020000 1239.430000 746.280000 ;
+ RECT 1135.620000 547.270000 1136.720000 743.840000 ;
+ RECT 1090.620000 547.270000 1091.720000 743.840000 ;
+ RECT 1045.620000 547.270000 1046.720000 743.840000 ;
+ RECT 1041.790000 546.020000 1042.790000 746.280000 ;
+ LAYER met3 ;
+ RECT 1225.620000 738.560000 1226.720000 739.040000 ;
+ RECT 1238.430000 738.560000 1239.430000 739.040000 ;
+ RECT 1238.430000 727.680000 1239.430000 728.160000 ;
+ RECT 1238.430000 722.240000 1239.430000 722.720000 ;
+ RECT 1238.430000 733.120000 1239.430000 733.600000 ;
+ RECT 1225.620000 733.120000 1226.720000 733.600000 ;
+ RECT 1225.620000 727.680000 1226.720000 728.160000 ;
+ RECT 1225.620000 722.240000 1226.720000 722.720000 ;
+ RECT 1225.620000 711.360000 1226.720000 711.840000 ;
+ RECT 1225.620000 716.800000 1226.720000 717.280000 ;
+ RECT 1238.430000 711.360000 1239.430000 711.840000 ;
+ RECT 1238.430000 716.800000 1239.430000 717.280000 ;
+ RECT 1225.620000 700.480000 1226.720000 700.960000 ;
+ RECT 1225.620000 705.920000 1226.720000 706.400000 ;
+ RECT 1238.430000 700.480000 1239.430000 700.960000 ;
+ RECT 1238.430000 705.920000 1239.430000 706.400000 ;
+ RECT 1180.620000 722.240000 1181.720000 722.720000 ;
+ RECT 1180.620000 727.680000 1181.720000 728.160000 ;
+ RECT 1180.620000 733.120000 1181.720000 733.600000 ;
+ RECT 1180.620000 738.560000 1181.720000 739.040000 ;
+ RECT 1180.620000 705.920000 1181.720000 706.400000 ;
+ RECT 1180.620000 700.480000 1181.720000 700.960000 ;
+ RECT 1180.620000 711.360000 1181.720000 711.840000 ;
+ RECT 1180.620000 716.800000 1181.720000 717.280000 ;
+ RECT 1238.430000 689.600000 1239.430000 690.080000 ;
+ RECT 1238.430000 684.160000 1239.430000 684.640000 ;
+ RECT 1238.430000 695.040000 1239.430000 695.520000 ;
+ RECT 1225.620000 695.040000 1226.720000 695.520000 ;
+ RECT 1225.620000 689.600000 1226.720000 690.080000 ;
+ RECT 1225.620000 684.160000 1226.720000 684.640000 ;
+ RECT 1225.620000 673.280000 1226.720000 673.760000 ;
+ RECT 1225.620000 678.720000 1226.720000 679.200000 ;
+ RECT 1238.430000 673.280000 1239.430000 673.760000 ;
+ RECT 1238.430000 678.720000 1239.430000 679.200000 ;
+ RECT 1238.430000 662.400000 1239.430000 662.880000 ;
+ RECT 1238.430000 667.840000 1239.430000 668.320000 ;
+ RECT 1225.620000 667.840000 1226.720000 668.320000 ;
+ RECT 1225.620000 662.400000 1226.720000 662.880000 ;
+ RECT 1225.620000 651.520000 1226.720000 652.000000 ;
+ RECT 1225.620000 656.960000 1226.720000 657.440000 ;
+ RECT 1238.430000 651.520000 1239.430000 652.000000 ;
+ RECT 1238.430000 656.960000 1239.430000 657.440000 ;
+ RECT 1180.620000 673.280000 1181.720000 673.760000 ;
+ RECT 1180.620000 678.720000 1181.720000 679.200000 ;
+ RECT 1180.620000 684.160000 1181.720000 684.640000 ;
+ RECT 1180.620000 689.600000 1181.720000 690.080000 ;
+ RECT 1180.620000 695.040000 1181.720000 695.520000 ;
+ RECT 1180.620000 651.520000 1181.720000 652.000000 ;
+ RECT 1180.620000 656.960000 1181.720000 657.440000 ;
+ RECT 1180.620000 662.400000 1181.720000 662.880000 ;
+ RECT 1180.620000 667.840000 1181.720000 668.320000 ;
+ RECT 1135.620000 727.680000 1136.720000 728.160000 ;
+ RECT 1135.620000 722.240000 1136.720000 722.720000 ;
+ RECT 1135.620000 733.120000 1136.720000 733.600000 ;
+ RECT 1135.620000 738.560000 1136.720000 739.040000 ;
+ RECT 1090.620000 722.240000 1091.720000 722.720000 ;
+ RECT 1090.620000 727.680000 1091.720000 728.160000 ;
+ RECT 1090.620000 733.120000 1091.720000 733.600000 ;
+ RECT 1090.620000 738.560000 1091.720000 739.040000 ;
+ RECT 1135.620000 700.480000 1136.720000 700.960000 ;
+ RECT 1135.620000 705.920000 1136.720000 706.400000 ;
+ RECT 1135.620000 711.360000 1136.720000 711.840000 ;
+ RECT 1135.620000 716.800000 1136.720000 717.280000 ;
+ RECT 1090.620000 700.480000 1091.720000 700.960000 ;
+ RECT 1090.620000 705.920000 1091.720000 706.400000 ;
+ RECT 1090.620000 711.360000 1091.720000 711.840000 ;
+ RECT 1090.620000 716.800000 1091.720000 717.280000 ;
+ RECT 1041.790000 738.560000 1042.790000 739.040000 ;
+ RECT 1045.455000 738.560000 1046.720000 739.040000 ;
+ RECT 1041.790000 727.680000 1042.790000 728.160000 ;
+ RECT 1045.455000 727.680000 1046.720000 728.160000 ;
+ RECT 1041.790000 733.120000 1042.790000 733.600000 ;
+ RECT 1045.455000 733.120000 1046.720000 733.600000 ;
+ RECT 1041.790000 722.240000 1042.790000 722.720000 ;
+ RECT 1045.455000 722.240000 1046.720000 722.720000 ;
+ RECT 1041.790000 716.800000 1042.790000 717.280000 ;
+ RECT 1045.455000 716.800000 1046.720000 717.280000 ;
+ RECT 1041.790000 711.360000 1042.790000 711.840000 ;
+ RECT 1045.455000 711.360000 1046.720000 711.840000 ;
+ RECT 1041.790000 705.920000 1042.790000 706.400000 ;
+ RECT 1045.455000 705.920000 1046.720000 706.400000 ;
+ RECT 1041.790000 700.480000 1042.790000 700.960000 ;
+ RECT 1045.455000 700.480000 1046.720000 700.960000 ;
+ RECT 1135.620000 673.280000 1136.720000 673.760000 ;
+ RECT 1135.620000 678.720000 1136.720000 679.200000 ;
+ RECT 1135.620000 684.160000 1136.720000 684.640000 ;
+ RECT 1135.620000 689.600000 1136.720000 690.080000 ;
+ RECT 1135.620000 695.040000 1136.720000 695.520000 ;
+ RECT 1090.620000 673.280000 1091.720000 673.760000 ;
+ RECT 1090.620000 678.720000 1091.720000 679.200000 ;
+ RECT 1090.620000 684.160000 1091.720000 684.640000 ;
+ RECT 1090.620000 689.600000 1091.720000 690.080000 ;
+ RECT 1090.620000 695.040000 1091.720000 695.520000 ;
+ RECT 1135.620000 651.520000 1136.720000 652.000000 ;
+ RECT 1135.620000 656.960000 1136.720000 657.440000 ;
+ RECT 1135.620000 662.400000 1136.720000 662.880000 ;
+ RECT 1135.620000 667.840000 1136.720000 668.320000 ;
+ RECT 1090.620000 651.520000 1091.720000 652.000000 ;
+ RECT 1090.620000 656.960000 1091.720000 657.440000 ;
+ RECT 1090.620000 662.400000 1091.720000 662.880000 ;
+ RECT 1090.620000 667.840000 1091.720000 668.320000 ;
+ RECT 1041.790000 695.040000 1042.790000 695.520000 ;
+ RECT 1045.455000 695.040000 1046.720000 695.520000 ;
+ RECT 1041.790000 684.160000 1042.790000 684.640000 ;
+ RECT 1045.455000 684.160000 1046.720000 684.640000 ;
+ RECT 1041.790000 689.600000 1042.790000 690.080000 ;
+ RECT 1045.455000 689.600000 1046.720000 690.080000 ;
+ RECT 1041.790000 678.720000 1042.790000 679.200000 ;
+ RECT 1045.455000 678.720000 1046.720000 679.200000 ;
+ RECT 1041.790000 673.280000 1042.790000 673.760000 ;
+ RECT 1045.455000 673.280000 1046.720000 673.760000 ;
+ RECT 1041.790000 667.840000 1042.790000 668.320000 ;
+ RECT 1045.455000 667.840000 1046.720000 668.320000 ;
+ RECT 1041.790000 662.400000 1042.790000 662.880000 ;
+ RECT 1045.455000 662.400000 1046.720000 662.880000 ;
+ RECT 1041.790000 656.960000 1042.790000 657.440000 ;
+ RECT 1045.455000 656.960000 1046.720000 657.440000 ;
+ RECT 1041.790000 651.520000 1042.790000 652.000000 ;
+ RECT 1045.455000 651.520000 1046.720000 652.000000 ;
+ RECT 1225.620000 635.200000 1226.720000 635.680000 ;
+ RECT 1225.620000 640.640000 1226.720000 641.120000 ;
+ RECT 1238.430000 635.200000 1239.430000 635.680000 ;
+ RECT 1238.430000 640.640000 1239.430000 641.120000 ;
+ RECT 1238.430000 624.320000 1239.430000 624.800000 ;
+ RECT 1238.430000 629.760000 1239.430000 630.240000 ;
+ RECT 1225.620000 629.760000 1226.720000 630.240000 ;
+ RECT 1225.620000 624.320000 1226.720000 624.800000 ;
+ RECT 1225.620000 613.440000 1226.720000 613.920000 ;
+ RECT 1225.620000 618.880000 1226.720000 619.360000 ;
+ RECT 1238.430000 613.440000 1239.430000 613.920000 ;
+ RECT 1238.430000 618.880000 1239.430000 619.360000 ;
+ RECT 1238.430000 602.560000 1239.430000 603.040000 ;
+ RECT 1238.430000 597.120000 1239.430000 597.600000 ;
+ RECT 1238.430000 608.000000 1239.430000 608.480000 ;
+ RECT 1225.620000 608.000000 1226.720000 608.480000 ;
+ RECT 1225.620000 602.560000 1226.720000 603.040000 ;
+ RECT 1225.620000 597.120000 1226.720000 597.600000 ;
+ RECT 1180.620000 624.320000 1181.720000 624.800000 ;
+ RECT 1180.620000 629.760000 1181.720000 630.240000 ;
+ RECT 1180.620000 635.200000 1181.720000 635.680000 ;
+ RECT 1180.620000 640.640000 1181.720000 641.120000 ;
+ RECT 1180.620000 597.120000 1181.720000 597.600000 ;
+ RECT 1180.620000 602.560000 1181.720000 603.040000 ;
+ RECT 1180.620000 608.000000 1181.720000 608.480000 ;
+ RECT 1180.620000 613.440000 1181.720000 613.920000 ;
+ RECT 1180.620000 618.880000 1181.720000 619.360000 ;
+ RECT 1225.620000 586.240000 1226.720000 586.720000 ;
+ RECT 1225.620000 591.680000 1226.720000 592.160000 ;
+ RECT 1238.430000 586.240000 1239.430000 586.720000 ;
+ RECT 1238.430000 591.680000 1239.430000 592.160000 ;
+ RECT 1225.620000 575.360000 1226.720000 575.840000 ;
+ RECT 1225.620000 580.800000 1226.720000 581.280000 ;
+ RECT 1238.430000 575.360000 1239.430000 575.840000 ;
+ RECT 1238.430000 580.800000 1239.430000 581.280000 ;
+ RECT 1238.430000 564.480000 1239.430000 564.960000 ;
+ RECT 1238.430000 559.040000 1239.430000 559.520000 ;
+ RECT 1238.430000 569.920000 1239.430000 570.400000 ;
+ RECT 1225.620000 569.920000 1226.720000 570.400000 ;
+ RECT 1225.620000 564.480000 1226.720000 564.960000 ;
+ RECT 1225.620000 559.040000 1226.720000 559.520000 ;
+ RECT 1225.620000 553.600000 1226.720000 554.080000 ;
+ RECT 1238.430000 553.600000 1239.430000 554.080000 ;
+ RECT 1180.620000 575.360000 1181.720000 575.840000 ;
+ RECT 1180.620000 580.800000 1181.720000 581.280000 ;
+ RECT 1180.620000 586.240000 1181.720000 586.720000 ;
+ RECT 1180.620000 591.680000 1181.720000 592.160000 ;
+ RECT 1180.620000 553.600000 1181.720000 554.080000 ;
+ RECT 1180.620000 559.040000 1181.720000 559.520000 ;
+ RECT 1180.620000 564.480000 1181.720000 564.960000 ;
+ RECT 1180.620000 569.920000 1181.720000 570.400000 ;
+ RECT 1135.620000 624.320000 1136.720000 624.800000 ;
+ RECT 1135.620000 629.760000 1136.720000 630.240000 ;
+ RECT 1135.620000 635.200000 1136.720000 635.680000 ;
+ RECT 1135.620000 640.640000 1136.720000 641.120000 ;
+ RECT 1090.620000 624.320000 1091.720000 624.800000 ;
+ RECT 1090.620000 629.760000 1091.720000 630.240000 ;
+ RECT 1090.620000 635.200000 1091.720000 635.680000 ;
+ RECT 1090.620000 640.640000 1091.720000 641.120000 ;
+ RECT 1135.620000 597.120000 1136.720000 597.600000 ;
+ RECT 1135.620000 602.560000 1136.720000 603.040000 ;
+ RECT 1135.620000 608.000000 1136.720000 608.480000 ;
+ RECT 1135.620000 613.440000 1136.720000 613.920000 ;
+ RECT 1135.620000 618.880000 1136.720000 619.360000 ;
+ RECT 1090.620000 597.120000 1091.720000 597.600000 ;
+ RECT 1090.620000 602.560000 1091.720000 603.040000 ;
+ RECT 1090.620000 608.000000 1091.720000 608.480000 ;
+ RECT 1090.620000 613.440000 1091.720000 613.920000 ;
+ RECT 1090.620000 618.880000 1091.720000 619.360000 ;
+ RECT 1041.790000 640.640000 1042.790000 641.120000 ;
+ RECT 1045.455000 640.640000 1046.720000 641.120000 ;
+ RECT 1041.790000 635.200000 1042.790000 635.680000 ;
+ RECT 1045.455000 635.200000 1046.720000 635.680000 ;
+ RECT 1041.790000 629.760000 1042.790000 630.240000 ;
+ RECT 1045.455000 629.760000 1046.720000 630.240000 ;
+ RECT 1041.790000 624.320000 1042.790000 624.800000 ;
+ RECT 1045.455000 624.320000 1046.720000 624.800000 ;
+ RECT 1041.790000 618.880000 1042.790000 619.360000 ;
+ RECT 1045.455000 618.880000 1046.720000 619.360000 ;
+ RECT 1041.790000 613.440000 1042.790000 613.920000 ;
+ RECT 1045.455000 613.440000 1046.720000 613.920000 ;
+ RECT 1041.790000 602.560000 1042.790000 603.040000 ;
+ RECT 1045.455000 602.560000 1046.720000 603.040000 ;
+ RECT 1041.790000 608.000000 1042.790000 608.480000 ;
+ RECT 1045.455000 608.000000 1046.720000 608.480000 ;
+ RECT 1041.790000 597.120000 1042.790000 597.600000 ;
+ RECT 1045.455000 597.120000 1046.720000 597.600000 ;
+ RECT 1135.620000 575.360000 1136.720000 575.840000 ;
+ RECT 1135.620000 580.800000 1136.720000 581.280000 ;
+ RECT 1135.620000 586.240000 1136.720000 586.720000 ;
+ RECT 1135.620000 591.680000 1136.720000 592.160000 ;
+ RECT 1090.620000 575.360000 1091.720000 575.840000 ;
+ RECT 1090.620000 580.800000 1091.720000 581.280000 ;
+ RECT 1090.620000 586.240000 1091.720000 586.720000 ;
+ RECT 1090.620000 591.680000 1091.720000 592.160000 ;
+ RECT 1135.620000 553.600000 1136.720000 554.080000 ;
+ RECT 1135.620000 559.040000 1136.720000 559.520000 ;
+ RECT 1135.620000 564.480000 1136.720000 564.960000 ;
+ RECT 1135.620000 569.920000 1136.720000 570.400000 ;
+ RECT 1090.620000 553.600000 1091.720000 554.080000 ;
+ RECT 1090.620000 559.040000 1091.720000 559.520000 ;
+ RECT 1090.620000 564.480000 1091.720000 564.960000 ;
+ RECT 1090.620000 569.920000 1091.720000 570.400000 ;
+ RECT 1041.790000 591.680000 1042.790000 592.160000 ;
+ RECT 1045.455000 591.680000 1046.720000 592.160000 ;
+ RECT 1041.790000 586.240000 1042.790000 586.720000 ;
+ RECT 1045.455000 586.240000 1046.720000 586.720000 ;
+ RECT 1041.790000 580.800000 1042.790000 581.280000 ;
+ RECT 1045.455000 580.800000 1046.720000 581.280000 ;
+ RECT 1041.790000 575.360000 1042.790000 575.840000 ;
+ RECT 1045.455000 575.360000 1046.720000 575.840000 ;
+ RECT 1041.790000 569.920000 1042.790000 570.400000 ;
+ RECT 1045.455000 569.920000 1046.720000 570.400000 ;
+ RECT 1041.790000 559.040000 1042.790000 559.520000 ;
+ RECT 1045.455000 559.040000 1046.720000 559.520000 ;
+ RECT 1041.790000 564.480000 1042.790000 564.960000 ;
+ RECT 1045.455000 564.480000 1046.720000 564.960000 ;
+ RECT 1041.790000 553.600000 1042.790000 554.080000 ;
+ RECT 1045.455000 553.600000 1046.720000 554.080000 ;
+ RECT 1180.620000 646.080000 1181.720000 646.560000 ;
+ RECT 1225.620000 646.080000 1226.720000 646.560000 ;
+ RECT 1238.430000 646.080000 1239.430000 646.560000 ;
+ RECT 1090.620000 646.080000 1091.720000 646.560000 ;
+ RECT 1135.620000 646.080000 1136.720000 646.560000 ;
+ RECT 1041.790000 646.080000 1042.790000 646.560000 ;
+ RECT 1045.455000 646.080000 1046.720000 646.560000 ;
+ RECT 1040.560000 742.840000 1240.660000 743.840000 ;
+ RECT 1040.560000 547.270000 1240.660000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 546.020000 1042.790000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 745.280000 1042.790000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 546.020000 1239.430000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 745.280000 1239.430000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 547.270000 1041.560000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 547.270000 1240.660000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 742.840000 1041.560000 743.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 742.840000 1240.660000 743.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 538.300000 1046.720000 538.780000 ;
+ RECT 1045.455000 527.420000 1046.720000 527.900000 ;
+ RECT 1045.455000 532.860000 1046.720000 533.340000 ;
+ RECT 1045.455000 521.980000 1046.720000 522.460000 ;
+ RECT 1045.455000 516.540000 1046.720000 517.020000 ;
+ RECT 1045.455000 511.100000 1046.720000 511.580000 ;
+ RECT 1045.455000 505.660000 1046.720000 506.140000 ;
+ RECT 1045.455000 500.220000 1046.720000 500.700000 ;
+ RECT 1045.455000 494.780000 1046.720000 495.260000 ;
+ RECT 1045.455000 483.900000 1046.720000 484.380000 ;
+ RECT 1045.455000 489.340000 1046.720000 489.820000 ;
+ RECT 1045.455000 478.460000 1046.720000 478.940000 ;
+ RECT 1045.455000 473.020000 1046.720000 473.500000 ;
+ RECT 1045.455000 467.580000 1046.720000 468.060000 ;
+ RECT 1045.455000 462.140000 1046.720000 462.620000 ;
+ RECT 1045.455000 456.700000 1046.720000 457.180000 ;
+ RECT 1045.455000 451.260000 1046.720000 451.740000 ;
+ RECT 1045.455000 440.380000 1046.720000 440.860000 ;
+ RECT 1045.455000 434.940000 1046.720000 435.420000 ;
+ RECT 1045.455000 429.500000 1046.720000 429.980000 ;
+ RECT 1045.455000 424.060000 1046.720000 424.540000 ;
+ RECT 1045.455000 418.620000 1046.720000 419.100000 ;
+ RECT 1045.455000 413.180000 1046.720000 413.660000 ;
+ RECT 1045.455000 402.300000 1046.720000 402.780000 ;
+ RECT 1045.455000 407.740000 1046.720000 408.220000 ;
+ RECT 1045.455000 396.860000 1046.720000 397.340000 ;
+ RECT 1045.455000 391.420000 1046.720000 391.900000 ;
+ RECT 1045.455000 385.980000 1046.720000 386.460000 ;
+ RECT 1045.455000 380.540000 1046.720000 381.020000 ;
+ RECT 1045.455000 375.100000 1046.720000 375.580000 ;
+ RECT 1045.455000 369.660000 1046.720000 370.140000 ;
+ RECT 1045.455000 358.780000 1046.720000 359.260000 ;
+ RECT 1045.455000 364.220000 1046.720000 364.700000 ;
+ RECT 1045.455000 353.340000 1046.720000 353.820000 ;
+ RECT 1045.455000 445.820000 1046.720000 446.300000 ;
+ RECT 1225.620000 347.010000 1226.720000 543.580000 ;
+ RECT 1180.620000 347.010000 1181.720000 543.580000 ;
+ RECT 1238.430000 345.760000 1239.430000 546.020000 ;
+ RECT 1135.620000 347.010000 1136.720000 543.580000 ;
+ RECT 1090.620000 347.010000 1091.720000 543.580000 ;
+ RECT 1045.620000 347.010000 1046.720000 543.580000 ;
+ RECT 1041.790000 345.760000 1042.790000 546.020000 ;
+ LAYER met3 ;
+ RECT 1225.620000 538.300000 1226.720000 538.780000 ;
+ RECT 1238.430000 538.300000 1239.430000 538.780000 ;
+ RECT 1238.430000 527.420000 1239.430000 527.900000 ;
+ RECT 1238.430000 521.980000 1239.430000 522.460000 ;
+ RECT 1238.430000 532.860000 1239.430000 533.340000 ;
+ RECT 1225.620000 532.860000 1226.720000 533.340000 ;
+ RECT 1225.620000 527.420000 1226.720000 527.900000 ;
+ RECT 1225.620000 521.980000 1226.720000 522.460000 ;
+ RECT 1225.620000 511.100000 1226.720000 511.580000 ;
+ RECT 1225.620000 516.540000 1226.720000 517.020000 ;
+ RECT 1238.430000 511.100000 1239.430000 511.580000 ;
+ RECT 1238.430000 516.540000 1239.430000 517.020000 ;
+ RECT 1225.620000 500.220000 1226.720000 500.700000 ;
+ RECT 1225.620000 505.660000 1226.720000 506.140000 ;
+ RECT 1238.430000 500.220000 1239.430000 500.700000 ;
+ RECT 1238.430000 505.660000 1239.430000 506.140000 ;
+ RECT 1180.620000 521.980000 1181.720000 522.460000 ;
+ RECT 1180.620000 527.420000 1181.720000 527.900000 ;
+ RECT 1180.620000 532.860000 1181.720000 533.340000 ;
+ RECT 1180.620000 538.300000 1181.720000 538.780000 ;
+ RECT 1180.620000 505.660000 1181.720000 506.140000 ;
+ RECT 1180.620000 500.220000 1181.720000 500.700000 ;
+ RECT 1180.620000 511.100000 1181.720000 511.580000 ;
+ RECT 1180.620000 516.540000 1181.720000 517.020000 ;
+ RECT 1238.430000 489.340000 1239.430000 489.820000 ;
+ RECT 1238.430000 483.900000 1239.430000 484.380000 ;
+ RECT 1238.430000 494.780000 1239.430000 495.260000 ;
+ RECT 1225.620000 494.780000 1226.720000 495.260000 ;
+ RECT 1225.620000 489.340000 1226.720000 489.820000 ;
+ RECT 1225.620000 483.900000 1226.720000 484.380000 ;
+ RECT 1225.620000 473.020000 1226.720000 473.500000 ;
+ RECT 1225.620000 478.460000 1226.720000 478.940000 ;
+ RECT 1238.430000 473.020000 1239.430000 473.500000 ;
+ RECT 1238.430000 478.460000 1239.430000 478.940000 ;
+ RECT 1238.430000 462.140000 1239.430000 462.620000 ;
+ RECT 1238.430000 467.580000 1239.430000 468.060000 ;
+ RECT 1225.620000 467.580000 1226.720000 468.060000 ;
+ RECT 1225.620000 462.140000 1226.720000 462.620000 ;
+ RECT 1225.620000 451.260000 1226.720000 451.740000 ;
+ RECT 1225.620000 456.700000 1226.720000 457.180000 ;
+ RECT 1238.430000 451.260000 1239.430000 451.740000 ;
+ RECT 1238.430000 456.700000 1239.430000 457.180000 ;
+ RECT 1180.620000 473.020000 1181.720000 473.500000 ;
+ RECT 1180.620000 478.460000 1181.720000 478.940000 ;
+ RECT 1180.620000 483.900000 1181.720000 484.380000 ;
+ RECT 1180.620000 489.340000 1181.720000 489.820000 ;
+ RECT 1180.620000 494.780000 1181.720000 495.260000 ;
+ RECT 1180.620000 451.260000 1181.720000 451.740000 ;
+ RECT 1180.620000 456.700000 1181.720000 457.180000 ;
+ RECT 1180.620000 462.140000 1181.720000 462.620000 ;
+ RECT 1180.620000 467.580000 1181.720000 468.060000 ;
+ RECT 1135.620000 527.420000 1136.720000 527.900000 ;
+ RECT 1135.620000 521.980000 1136.720000 522.460000 ;
+ RECT 1135.620000 532.860000 1136.720000 533.340000 ;
+ RECT 1135.620000 538.300000 1136.720000 538.780000 ;
+ RECT 1090.620000 521.980000 1091.720000 522.460000 ;
+ RECT 1090.620000 527.420000 1091.720000 527.900000 ;
+ RECT 1090.620000 532.860000 1091.720000 533.340000 ;
+ RECT 1090.620000 538.300000 1091.720000 538.780000 ;
+ RECT 1135.620000 500.220000 1136.720000 500.700000 ;
+ RECT 1135.620000 505.660000 1136.720000 506.140000 ;
+ RECT 1135.620000 511.100000 1136.720000 511.580000 ;
+ RECT 1135.620000 516.540000 1136.720000 517.020000 ;
+ RECT 1090.620000 500.220000 1091.720000 500.700000 ;
+ RECT 1090.620000 505.660000 1091.720000 506.140000 ;
+ RECT 1090.620000 511.100000 1091.720000 511.580000 ;
+ RECT 1090.620000 516.540000 1091.720000 517.020000 ;
+ RECT 1041.790000 538.300000 1042.790000 538.780000 ;
+ RECT 1045.455000 538.300000 1046.720000 538.780000 ;
+ RECT 1041.790000 527.420000 1042.790000 527.900000 ;
+ RECT 1045.455000 527.420000 1046.720000 527.900000 ;
+ RECT 1041.790000 532.860000 1042.790000 533.340000 ;
+ RECT 1045.455000 532.860000 1046.720000 533.340000 ;
+ RECT 1041.790000 521.980000 1042.790000 522.460000 ;
+ RECT 1045.455000 521.980000 1046.720000 522.460000 ;
+ RECT 1041.790000 516.540000 1042.790000 517.020000 ;
+ RECT 1045.455000 516.540000 1046.720000 517.020000 ;
+ RECT 1041.790000 511.100000 1042.790000 511.580000 ;
+ RECT 1045.455000 511.100000 1046.720000 511.580000 ;
+ RECT 1041.790000 505.660000 1042.790000 506.140000 ;
+ RECT 1045.455000 505.660000 1046.720000 506.140000 ;
+ RECT 1041.790000 500.220000 1042.790000 500.700000 ;
+ RECT 1045.455000 500.220000 1046.720000 500.700000 ;
+ RECT 1135.620000 473.020000 1136.720000 473.500000 ;
+ RECT 1135.620000 478.460000 1136.720000 478.940000 ;
+ RECT 1135.620000 483.900000 1136.720000 484.380000 ;
+ RECT 1135.620000 489.340000 1136.720000 489.820000 ;
+ RECT 1135.620000 494.780000 1136.720000 495.260000 ;
+ RECT 1090.620000 473.020000 1091.720000 473.500000 ;
+ RECT 1090.620000 478.460000 1091.720000 478.940000 ;
+ RECT 1090.620000 483.900000 1091.720000 484.380000 ;
+ RECT 1090.620000 489.340000 1091.720000 489.820000 ;
+ RECT 1090.620000 494.780000 1091.720000 495.260000 ;
+ RECT 1135.620000 451.260000 1136.720000 451.740000 ;
+ RECT 1135.620000 456.700000 1136.720000 457.180000 ;
+ RECT 1135.620000 462.140000 1136.720000 462.620000 ;
+ RECT 1135.620000 467.580000 1136.720000 468.060000 ;
+ RECT 1090.620000 451.260000 1091.720000 451.740000 ;
+ RECT 1090.620000 456.700000 1091.720000 457.180000 ;
+ RECT 1090.620000 462.140000 1091.720000 462.620000 ;
+ RECT 1090.620000 467.580000 1091.720000 468.060000 ;
+ RECT 1041.790000 494.780000 1042.790000 495.260000 ;
+ RECT 1045.455000 494.780000 1046.720000 495.260000 ;
+ RECT 1041.790000 483.900000 1042.790000 484.380000 ;
+ RECT 1045.455000 483.900000 1046.720000 484.380000 ;
+ RECT 1041.790000 489.340000 1042.790000 489.820000 ;
+ RECT 1045.455000 489.340000 1046.720000 489.820000 ;
+ RECT 1041.790000 478.460000 1042.790000 478.940000 ;
+ RECT 1045.455000 478.460000 1046.720000 478.940000 ;
+ RECT 1041.790000 473.020000 1042.790000 473.500000 ;
+ RECT 1045.455000 473.020000 1046.720000 473.500000 ;
+ RECT 1041.790000 467.580000 1042.790000 468.060000 ;
+ RECT 1045.455000 467.580000 1046.720000 468.060000 ;
+ RECT 1041.790000 462.140000 1042.790000 462.620000 ;
+ RECT 1045.455000 462.140000 1046.720000 462.620000 ;
+ RECT 1041.790000 456.700000 1042.790000 457.180000 ;
+ RECT 1045.455000 456.700000 1046.720000 457.180000 ;
+ RECT 1041.790000 451.260000 1042.790000 451.740000 ;
+ RECT 1045.455000 451.260000 1046.720000 451.740000 ;
+ RECT 1225.620000 434.940000 1226.720000 435.420000 ;
+ RECT 1225.620000 440.380000 1226.720000 440.860000 ;
+ RECT 1238.430000 434.940000 1239.430000 435.420000 ;
+ RECT 1238.430000 440.380000 1239.430000 440.860000 ;
+ RECT 1238.430000 424.060000 1239.430000 424.540000 ;
+ RECT 1238.430000 429.500000 1239.430000 429.980000 ;
+ RECT 1225.620000 429.500000 1226.720000 429.980000 ;
+ RECT 1225.620000 424.060000 1226.720000 424.540000 ;
+ RECT 1225.620000 413.180000 1226.720000 413.660000 ;
+ RECT 1225.620000 418.620000 1226.720000 419.100000 ;
+ RECT 1238.430000 413.180000 1239.430000 413.660000 ;
+ RECT 1238.430000 418.620000 1239.430000 419.100000 ;
+ RECT 1238.430000 402.300000 1239.430000 402.780000 ;
+ RECT 1238.430000 396.860000 1239.430000 397.340000 ;
+ RECT 1238.430000 407.740000 1239.430000 408.220000 ;
+ RECT 1225.620000 407.740000 1226.720000 408.220000 ;
+ RECT 1225.620000 402.300000 1226.720000 402.780000 ;
+ RECT 1225.620000 396.860000 1226.720000 397.340000 ;
+ RECT 1180.620000 424.060000 1181.720000 424.540000 ;
+ RECT 1180.620000 429.500000 1181.720000 429.980000 ;
+ RECT 1180.620000 434.940000 1181.720000 435.420000 ;
+ RECT 1180.620000 440.380000 1181.720000 440.860000 ;
+ RECT 1180.620000 396.860000 1181.720000 397.340000 ;
+ RECT 1180.620000 402.300000 1181.720000 402.780000 ;
+ RECT 1180.620000 407.740000 1181.720000 408.220000 ;
+ RECT 1180.620000 413.180000 1181.720000 413.660000 ;
+ RECT 1180.620000 418.620000 1181.720000 419.100000 ;
+ RECT 1225.620000 385.980000 1226.720000 386.460000 ;
+ RECT 1225.620000 391.420000 1226.720000 391.900000 ;
+ RECT 1238.430000 385.980000 1239.430000 386.460000 ;
+ RECT 1238.430000 391.420000 1239.430000 391.900000 ;
+ RECT 1225.620000 375.100000 1226.720000 375.580000 ;
+ RECT 1225.620000 380.540000 1226.720000 381.020000 ;
+ RECT 1238.430000 375.100000 1239.430000 375.580000 ;
+ RECT 1238.430000 380.540000 1239.430000 381.020000 ;
+ RECT 1238.430000 364.220000 1239.430000 364.700000 ;
+ RECT 1238.430000 358.780000 1239.430000 359.260000 ;
+ RECT 1238.430000 369.660000 1239.430000 370.140000 ;
+ RECT 1225.620000 369.660000 1226.720000 370.140000 ;
+ RECT 1225.620000 364.220000 1226.720000 364.700000 ;
+ RECT 1225.620000 358.780000 1226.720000 359.260000 ;
+ RECT 1225.620000 353.340000 1226.720000 353.820000 ;
+ RECT 1238.430000 353.340000 1239.430000 353.820000 ;
+ RECT 1180.620000 375.100000 1181.720000 375.580000 ;
+ RECT 1180.620000 380.540000 1181.720000 381.020000 ;
+ RECT 1180.620000 385.980000 1181.720000 386.460000 ;
+ RECT 1180.620000 391.420000 1181.720000 391.900000 ;
+ RECT 1180.620000 353.340000 1181.720000 353.820000 ;
+ RECT 1180.620000 358.780000 1181.720000 359.260000 ;
+ RECT 1180.620000 364.220000 1181.720000 364.700000 ;
+ RECT 1180.620000 369.660000 1181.720000 370.140000 ;
+ RECT 1135.620000 424.060000 1136.720000 424.540000 ;
+ RECT 1135.620000 429.500000 1136.720000 429.980000 ;
+ RECT 1135.620000 434.940000 1136.720000 435.420000 ;
+ RECT 1135.620000 440.380000 1136.720000 440.860000 ;
+ RECT 1090.620000 424.060000 1091.720000 424.540000 ;
+ RECT 1090.620000 429.500000 1091.720000 429.980000 ;
+ RECT 1090.620000 434.940000 1091.720000 435.420000 ;
+ RECT 1090.620000 440.380000 1091.720000 440.860000 ;
+ RECT 1135.620000 396.860000 1136.720000 397.340000 ;
+ RECT 1135.620000 402.300000 1136.720000 402.780000 ;
+ RECT 1135.620000 407.740000 1136.720000 408.220000 ;
+ RECT 1135.620000 413.180000 1136.720000 413.660000 ;
+ RECT 1135.620000 418.620000 1136.720000 419.100000 ;
+ RECT 1090.620000 396.860000 1091.720000 397.340000 ;
+ RECT 1090.620000 402.300000 1091.720000 402.780000 ;
+ RECT 1090.620000 407.740000 1091.720000 408.220000 ;
+ RECT 1090.620000 413.180000 1091.720000 413.660000 ;
+ RECT 1090.620000 418.620000 1091.720000 419.100000 ;
+ RECT 1041.790000 440.380000 1042.790000 440.860000 ;
+ RECT 1045.455000 440.380000 1046.720000 440.860000 ;
+ RECT 1041.790000 434.940000 1042.790000 435.420000 ;
+ RECT 1045.455000 434.940000 1046.720000 435.420000 ;
+ RECT 1041.790000 429.500000 1042.790000 429.980000 ;
+ RECT 1045.455000 429.500000 1046.720000 429.980000 ;
+ RECT 1041.790000 424.060000 1042.790000 424.540000 ;
+ RECT 1045.455000 424.060000 1046.720000 424.540000 ;
+ RECT 1041.790000 418.620000 1042.790000 419.100000 ;
+ RECT 1045.455000 418.620000 1046.720000 419.100000 ;
+ RECT 1041.790000 413.180000 1042.790000 413.660000 ;
+ RECT 1045.455000 413.180000 1046.720000 413.660000 ;
+ RECT 1041.790000 402.300000 1042.790000 402.780000 ;
+ RECT 1045.455000 402.300000 1046.720000 402.780000 ;
+ RECT 1041.790000 407.740000 1042.790000 408.220000 ;
+ RECT 1045.455000 407.740000 1046.720000 408.220000 ;
+ RECT 1041.790000 396.860000 1042.790000 397.340000 ;
+ RECT 1045.455000 396.860000 1046.720000 397.340000 ;
+ RECT 1135.620000 375.100000 1136.720000 375.580000 ;
+ RECT 1135.620000 380.540000 1136.720000 381.020000 ;
+ RECT 1135.620000 385.980000 1136.720000 386.460000 ;
+ RECT 1135.620000 391.420000 1136.720000 391.900000 ;
+ RECT 1090.620000 375.100000 1091.720000 375.580000 ;
+ RECT 1090.620000 380.540000 1091.720000 381.020000 ;
+ RECT 1090.620000 385.980000 1091.720000 386.460000 ;
+ RECT 1090.620000 391.420000 1091.720000 391.900000 ;
+ RECT 1135.620000 353.340000 1136.720000 353.820000 ;
+ RECT 1135.620000 358.780000 1136.720000 359.260000 ;
+ RECT 1135.620000 364.220000 1136.720000 364.700000 ;
+ RECT 1135.620000 369.660000 1136.720000 370.140000 ;
+ RECT 1090.620000 353.340000 1091.720000 353.820000 ;
+ RECT 1090.620000 358.780000 1091.720000 359.260000 ;
+ RECT 1090.620000 364.220000 1091.720000 364.700000 ;
+ RECT 1090.620000 369.660000 1091.720000 370.140000 ;
+ RECT 1041.790000 391.420000 1042.790000 391.900000 ;
+ RECT 1045.455000 391.420000 1046.720000 391.900000 ;
+ RECT 1041.790000 385.980000 1042.790000 386.460000 ;
+ RECT 1045.455000 385.980000 1046.720000 386.460000 ;
+ RECT 1041.790000 380.540000 1042.790000 381.020000 ;
+ RECT 1045.455000 380.540000 1046.720000 381.020000 ;
+ RECT 1041.790000 375.100000 1042.790000 375.580000 ;
+ RECT 1045.455000 375.100000 1046.720000 375.580000 ;
+ RECT 1041.790000 369.660000 1042.790000 370.140000 ;
+ RECT 1045.455000 369.660000 1046.720000 370.140000 ;
+ RECT 1041.790000 358.780000 1042.790000 359.260000 ;
+ RECT 1045.455000 358.780000 1046.720000 359.260000 ;
+ RECT 1041.790000 364.220000 1042.790000 364.700000 ;
+ RECT 1045.455000 364.220000 1046.720000 364.700000 ;
+ RECT 1041.790000 353.340000 1042.790000 353.820000 ;
+ RECT 1045.455000 353.340000 1046.720000 353.820000 ;
+ RECT 1180.620000 445.820000 1181.720000 446.300000 ;
+ RECT 1225.620000 445.820000 1226.720000 446.300000 ;
+ RECT 1238.430000 445.820000 1239.430000 446.300000 ;
+ RECT 1090.620000 445.820000 1091.720000 446.300000 ;
+ RECT 1135.620000 445.820000 1136.720000 446.300000 ;
+ RECT 1041.790000 445.820000 1042.790000 446.300000 ;
+ RECT 1045.455000 445.820000 1046.720000 446.300000 ;
+ RECT 1040.560000 542.580000 1240.660000 543.580000 ;
+ RECT 1040.560000 347.010000 1240.660000 348.010000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 345.760000 1042.790000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 545.020000 1042.790000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 345.760000 1239.430000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 545.020000 1239.430000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 347.010000 1041.560000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 347.010000 1240.660000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 542.580000 1041.560000 543.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 542.580000 1240.660000 543.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 338.040000 1046.720000 338.520000 ;
+ RECT 1045.455000 327.160000 1046.720000 327.640000 ;
+ RECT 1045.455000 332.600000 1046.720000 333.080000 ;
+ RECT 1045.455000 321.720000 1046.720000 322.200000 ;
+ RECT 1045.455000 316.280000 1046.720000 316.760000 ;
+ RECT 1045.455000 310.840000 1046.720000 311.320000 ;
+ RECT 1045.455000 305.400000 1046.720000 305.880000 ;
+ RECT 1045.455000 299.960000 1046.720000 300.440000 ;
+ RECT 1045.455000 294.520000 1046.720000 295.000000 ;
+ RECT 1045.455000 283.640000 1046.720000 284.120000 ;
+ RECT 1045.455000 289.080000 1046.720000 289.560000 ;
+ RECT 1045.455000 278.200000 1046.720000 278.680000 ;
+ RECT 1045.455000 272.760000 1046.720000 273.240000 ;
+ RECT 1045.455000 267.320000 1046.720000 267.800000 ;
+ RECT 1045.455000 261.880000 1046.720000 262.360000 ;
+ RECT 1045.455000 256.440000 1046.720000 256.920000 ;
+ RECT 1045.455000 251.000000 1046.720000 251.480000 ;
+ RECT 1045.455000 240.120000 1046.720000 240.600000 ;
+ RECT 1045.455000 234.680000 1046.720000 235.160000 ;
+ RECT 1045.455000 229.240000 1046.720000 229.720000 ;
+ RECT 1045.455000 223.800000 1046.720000 224.280000 ;
+ RECT 1045.455000 218.360000 1046.720000 218.840000 ;
+ RECT 1045.455000 212.920000 1046.720000 213.400000 ;
+ RECT 1045.455000 202.040000 1046.720000 202.520000 ;
+ RECT 1045.455000 207.480000 1046.720000 207.960000 ;
+ RECT 1045.455000 196.600000 1046.720000 197.080000 ;
+ RECT 1045.455000 191.160000 1046.720000 191.640000 ;
+ RECT 1045.455000 185.720000 1046.720000 186.200000 ;
+ RECT 1045.455000 180.280000 1046.720000 180.760000 ;
+ RECT 1045.455000 174.840000 1046.720000 175.320000 ;
+ RECT 1045.455000 169.400000 1046.720000 169.880000 ;
+ RECT 1045.455000 158.520000 1046.720000 159.000000 ;
+ RECT 1045.455000 163.960000 1046.720000 164.440000 ;
+ RECT 1045.455000 153.080000 1046.720000 153.560000 ;
+ RECT 1045.455000 245.560000 1046.720000 246.040000 ;
+ RECT 1225.620000 146.750000 1226.720000 343.320000 ;
+ RECT 1180.620000 146.750000 1181.720000 343.320000 ;
+ RECT 1238.430000 145.500000 1239.430000 345.760000 ;
+ RECT 1135.620000 146.750000 1136.720000 343.320000 ;
+ RECT 1090.620000 146.750000 1091.720000 343.320000 ;
+ RECT 1045.620000 146.750000 1046.720000 343.320000 ;
+ RECT 1041.790000 145.500000 1042.790000 345.760000 ;
+ LAYER met3 ;
+ RECT 1225.620000 338.040000 1226.720000 338.520000 ;
+ RECT 1238.430000 338.040000 1239.430000 338.520000 ;
+ RECT 1238.430000 327.160000 1239.430000 327.640000 ;
+ RECT 1238.430000 321.720000 1239.430000 322.200000 ;
+ RECT 1238.430000 332.600000 1239.430000 333.080000 ;
+ RECT 1225.620000 332.600000 1226.720000 333.080000 ;
+ RECT 1225.620000 327.160000 1226.720000 327.640000 ;
+ RECT 1225.620000 321.720000 1226.720000 322.200000 ;
+ RECT 1225.620000 310.840000 1226.720000 311.320000 ;
+ RECT 1225.620000 316.280000 1226.720000 316.760000 ;
+ RECT 1238.430000 310.840000 1239.430000 311.320000 ;
+ RECT 1238.430000 316.280000 1239.430000 316.760000 ;
+ RECT 1225.620000 299.960000 1226.720000 300.440000 ;
+ RECT 1225.620000 305.400000 1226.720000 305.880000 ;
+ RECT 1238.430000 299.960000 1239.430000 300.440000 ;
+ RECT 1238.430000 305.400000 1239.430000 305.880000 ;
+ RECT 1180.620000 321.720000 1181.720000 322.200000 ;
+ RECT 1180.620000 327.160000 1181.720000 327.640000 ;
+ RECT 1180.620000 332.600000 1181.720000 333.080000 ;
+ RECT 1180.620000 338.040000 1181.720000 338.520000 ;
+ RECT 1180.620000 305.400000 1181.720000 305.880000 ;
+ RECT 1180.620000 299.960000 1181.720000 300.440000 ;
+ RECT 1180.620000 310.840000 1181.720000 311.320000 ;
+ RECT 1180.620000 316.280000 1181.720000 316.760000 ;
+ RECT 1238.430000 289.080000 1239.430000 289.560000 ;
+ RECT 1238.430000 283.640000 1239.430000 284.120000 ;
+ RECT 1238.430000 294.520000 1239.430000 295.000000 ;
+ RECT 1225.620000 294.520000 1226.720000 295.000000 ;
+ RECT 1225.620000 289.080000 1226.720000 289.560000 ;
+ RECT 1225.620000 283.640000 1226.720000 284.120000 ;
+ RECT 1225.620000 272.760000 1226.720000 273.240000 ;
+ RECT 1225.620000 278.200000 1226.720000 278.680000 ;
+ RECT 1238.430000 272.760000 1239.430000 273.240000 ;
+ RECT 1238.430000 278.200000 1239.430000 278.680000 ;
+ RECT 1238.430000 261.880000 1239.430000 262.360000 ;
+ RECT 1238.430000 267.320000 1239.430000 267.800000 ;
+ RECT 1225.620000 267.320000 1226.720000 267.800000 ;
+ RECT 1225.620000 261.880000 1226.720000 262.360000 ;
+ RECT 1225.620000 251.000000 1226.720000 251.480000 ;
+ RECT 1225.620000 256.440000 1226.720000 256.920000 ;
+ RECT 1238.430000 251.000000 1239.430000 251.480000 ;
+ RECT 1238.430000 256.440000 1239.430000 256.920000 ;
+ RECT 1180.620000 272.760000 1181.720000 273.240000 ;
+ RECT 1180.620000 278.200000 1181.720000 278.680000 ;
+ RECT 1180.620000 283.640000 1181.720000 284.120000 ;
+ RECT 1180.620000 289.080000 1181.720000 289.560000 ;
+ RECT 1180.620000 294.520000 1181.720000 295.000000 ;
+ RECT 1180.620000 251.000000 1181.720000 251.480000 ;
+ RECT 1180.620000 256.440000 1181.720000 256.920000 ;
+ RECT 1180.620000 261.880000 1181.720000 262.360000 ;
+ RECT 1180.620000 267.320000 1181.720000 267.800000 ;
+ RECT 1135.620000 327.160000 1136.720000 327.640000 ;
+ RECT 1135.620000 321.720000 1136.720000 322.200000 ;
+ RECT 1135.620000 332.600000 1136.720000 333.080000 ;
+ RECT 1135.620000 338.040000 1136.720000 338.520000 ;
+ RECT 1090.620000 321.720000 1091.720000 322.200000 ;
+ RECT 1090.620000 327.160000 1091.720000 327.640000 ;
+ RECT 1090.620000 332.600000 1091.720000 333.080000 ;
+ RECT 1090.620000 338.040000 1091.720000 338.520000 ;
+ RECT 1135.620000 299.960000 1136.720000 300.440000 ;
+ RECT 1135.620000 305.400000 1136.720000 305.880000 ;
+ RECT 1135.620000 310.840000 1136.720000 311.320000 ;
+ RECT 1135.620000 316.280000 1136.720000 316.760000 ;
+ RECT 1090.620000 299.960000 1091.720000 300.440000 ;
+ RECT 1090.620000 305.400000 1091.720000 305.880000 ;
+ RECT 1090.620000 310.840000 1091.720000 311.320000 ;
+ RECT 1090.620000 316.280000 1091.720000 316.760000 ;
+ RECT 1041.790000 338.040000 1042.790000 338.520000 ;
+ RECT 1045.455000 338.040000 1046.720000 338.520000 ;
+ RECT 1041.790000 327.160000 1042.790000 327.640000 ;
+ RECT 1045.455000 327.160000 1046.720000 327.640000 ;
+ RECT 1041.790000 332.600000 1042.790000 333.080000 ;
+ RECT 1045.455000 332.600000 1046.720000 333.080000 ;
+ RECT 1041.790000 321.720000 1042.790000 322.200000 ;
+ RECT 1045.455000 321.720000 1046.720000 322.200000 ;
+ RECT 1041.790000 316.280000 1042.790000 316.760000 ;
+ RECT 1045.455000 316.280000 1046.720000 316.760000 ;
+ RECT 1041.790000 310.840000 1042.790000 311.320000 ;
+ RECT 1045.455000 310.840000 1046.720000 311.320000 ;
+ RECT 1041.790000 305.400000 1042.790000 305.880000 ;
+ RECT 1045.455000 305.400000 1046.720000 305.880000 ;
+ RECT 1041.790000 299.960000 1042.790000 300.440000 ;
+ RECT 1045.455000 299.960000 1046.720000 300.440000 ;
+ RECT 1135.620000 272.760000 1136.720000 273.240000 ;
+ RECT 1135.620000 278.200000 1136.720000 278.680000 ;
+ RECT 1135.620000 283.640000 1136.720000 284.120000 ;
+ RECT 1135.620000 289.080000 1136.720000 289.560000 ;
+ RECT 1135.620000 294.520000 1136.720000 295.000000 ;
+ RECT 1090.620000 272.760000 1091.720000 273.240000 ;
+ RECT 1090.620000 278.200000 1091.720000 278.680000 ;
+ RECT 1090.620000 283.640000 1091.720000 284.120000 ;
+ RECT 1090.620000 289.080000 1091.720000 289.560000 ;
+ RECT 1090.620000 294.520000 1091.720000 295.000000 ;
+ RECT 1135.620000 251.000000 1136.720000 251.480000 ;
+ RECT 1135.620000 256.440000 1136.720000 256.920000 ;
+ RECT 1135.620000 261.880000 1136.720000 262.360000 ;
+ RECT 1135.620000 267.320000 1136.720000 267.800000 ;
+ RECT 1090.620000 251.000000 1091.720000 251.480000 ;
+ RECT 1090.620000 256.440000 1091.720000 256.920000 ;
+ RECT 1090.620000 261.880000 1091.720000 262.360000 ;
+ RECT 1090.620000 267.320000 1091.720000 267.800000 ;
+ RECT 1041.790000 294.520000 1042.790000 295.000000 ;
+ RECT 1045.455000 294.520000 1046.720000 295.000000 ;
+ RECT 1041.790000 283.640000 1042.790000 284.120000 ;
+ RECT 1045.455000 283.640000 1046.720000 284.120000 ;
+ RECT 1041.790000 289.080000 1042.790000 289.560000 ;
+ RECT 1045.455000 289.080000 1046.720000 289.560000 ;
+ RECT 1041.790000 278.200000 1042.790000 278.680000 ;
+ RECT 1045.455000 278.200000 1046.720000 278.680000 ;
+ RECT 1041.790000 272.760000 1042.790000 273.240000 ;
+ RECT 1045.455000 272.760000 1046.720000 273.240000 ;
+ RECT 1041.790000 267.320000 1042.790000 267.800000 ;
+ RECT 1045.455000 267.320000 1046.720000 267.800000 ;
+ RECT 1041.790000 261.880000 1042.790000 262.360000 ;
+ RECT 1045.455000 261.880000 1046.720000 262.360000 ;
+ RECT 1041.790000 256.440000 1042.790000 256.920000 ;
+ RECT 1045.455000 256.440000 1046.720000 256.920000 ;
+ RECT 1041.790000 251.000000 1042.790000 251.480000 ;
+ RECT 1045.455000 251.000000 1046.720000 251.480000 ;
+ RECT 1225.620000 234.680000 1226.720000 235.160000 ;
+ RECT 1225.620000 240.120000 1226.720000 240.600000 ;
+ RECT 1238.430000 234.680000 1239.430000 235.160000 ;
+ RECT 1238.430000 240.120000 1239.430000 240.600000 ;
+ RECT 1238.430000 223.800000 1239.430000 224.280000 ;
+ RECT 1238.430000 229.240000 1239.430000 229.720000 ;
+ RECT 1225.620000 229.240000 1226.720000 229.720000 ;
+ RECT 1225.620000 223.800000 1226.720000 224.280000 ;
+ RECT 1225.620000 212.920000 1226.720000 213.400000 ;
+ RECT 1225.620000 218.360000 1226.720000 218.840000 ;
+ RECT 1238.430000 212.920000 1239.430000 213.400000 ;
+ RECT 1238.430000 218.360000 1239.430000 218.840000 ;
+ RECT 1238.430000 202.040000 1239.430000 202.520000 ;
+ RECT 1238.430000 196.600000 1239.430000 197.080000 ;
+ RECT 1238.430000 207.480000 1239.430000 207.960000 ;
+ RECT 1225.620000 207.480000 1226.720000 207.960000 ;
+ RECT 1225.620000 202.040000 1226.720000 202.520000 ;
+ RECT 1225.620000 196.600000 1226.720000 197.080000 ;
+ RECT 1180.620000 223.800000 1181.720000 224.280000 ;
+ RECT 1180.620000 229.240000 1181.720000 229.720000 ;
+ RECT 1180.620000 234.680000 1181.720000 235.160000 ;
+ RECT 1180.620000 240.120000 1181.720000 240.600000 ;
+ RECT 1180.620000 196.600000 1181.720000 197.080000 ;
+ RECT 1180.620000 202.040000 1181.720000 202.520000 ;
+ RECT 1180.620000 207.480000 1181.720000 207.960000 ;
+ RECT 1180.620000 212.920000 1181.720000 213.400000 ;
+ RECT 1180.620000 218.360000 1181.720000 218.840000 ;
+ RECT 1225.620000 185.720000 1226.720000 186.200000 ;
+ RECT 1225.620000 191.160000 1226.720000 191.640000 ;
+ RECT 1238.430000 185.720000 1239.430000 186.200000 ;
+ RECT 1238.430000 191.160000 1239.430000 191.640000 ;
+ RECT 1225.620000 174.840000 1226.720000 175.320000 ;
+ RECT 1225.620000 180.280000 1226.720000 180.760000 ;
+ RECT 1238.430000 174.840000 1239.430000 175.320000 ;
+ RECT 1238.430000 180.280000 1239.430000 180.760000 ;
+ RECT 1238.430000 163.960000 1239.430000 164.440000 ;
+ RECT 1238.430000 158.520000 1239.430000 159.000000 ;
+ RECT 1238.430000 169.400000 1239.430000 169.880000 ;
+ RECT 1225.620000 169.400000 1226.720000 169.880000 ;
+ RECT 1225.620000 163.960000 1226.720000 164.440000 ;
+ RECT 1225.620000 158.520000 1226.720000 159.000000 ;
+ RECT 1225.620000 153.080000 1226.720000 153.560000 ;
+ RECT 1238.430000 153.080000 1239.430000 153.560000 ;
+ RECT 1180.620000 174.840000 1181.720000 175.320000 ;
+ RECT 1180.620000 180.280000 1181.720000 180.760000 ;
+ RECT 1180.620000 185.720000 1181.720000 186.200000 ;
+ RECT 1180.620000 191.160000 1181.720000 191.640000 ;
+ RECT 1180.620000 153.080000 1181.720000 153.560000 ;
+ RECT 1180.620000 158.520000 1181.720000 159.000000 ;
+ RECT 1180.620000 163.960000 1181.720000 164.440000 ;
+ RECT 1180.620000 169.400000 1181.720000 169.880000 ;
+ RECT 1135.620000 223.800000 1136.720000 224.280000 ;
+ RECT 1135.620000 229.240000 1136.720000 229.720000 ;
+ RECT 1135.620000 234.680000 1136.720000 235.160000 ;
+ RECT 1135.620000 240.120000 1136.720000 240.600000 ;
+ RECT 1090.620000 223.800000 1091.720000 224.280000 ;
+ RECT 1090.620000 229.240000 1091.720000 229.720000 ;
+ RECT 1090.620000 234.680000 1091.720000 235.160000 ;
+ RECT 1090.620000 240.120000 1091.720000 240.600000 ;
+ RECT 1135.620000 196.600000 1136.720000 197.080000 ;
+ RECT 1135.620000 202.040000 1136.720000 202.520000 ;
+ RECT 1135.620000 207.480000 1136.720000 207.960000 ;
+ RECT 1135.620000 212.920000 1136.720000 213.400000 ;
+ RECT 1135.620000 218.360000 1136.720000 218.840000 ;
+ RECT 1090.620000 196.600000 1091.720000 197.080000 ;
+ RECT 1090.620000 202.040000 1091.720000 202.520000 ;
+ RECT 1090.620000 207.480000 1091.720000 207.960000 ;
+ RECT 1090.620000 212.920000 1091.720000 213.400000 ;
+ RECT 1090.620000 218.360000 1091.720000 218.840000 ;
+ RECT 1041.790000 240.120000 1042.790000 240.600000 ;
+ RECT 1045.455000 240.120000 1046.720000 240.600000 ;
+ RECT 1041.790000 234.680000 1042.790000 235.160000 ;
+ RECT 1045.455000 234.680000 1046.720000 235.160000 ;
+ RECT 1041.790000 229.240000 1042.790000 229.720000 ;
+ RECT 1045.455000 229.240000 1046.720000 229.720000 ;
+ RECT 1041.790000 223.800000 1042.790000 224.280000 ;
+ RECT 1045.455000 223.800000 1046.720000 224.280000 ;
+ RECT 1041.790000 218.360000 1042.790000 218.840000 ;
+ RECT 1045.455000 218.360000 1046.720000 218.840000 ;
+ RECT 1041.790000 212.920000 1042.790000 213.400000 ;
+ RECT 1045.455000 212.920000 1046.720000 213.400000 ;
+ RECT 1041.790000 202.040000 1042.790000 202.520000 ;
+ RECT 1045.455000 202.040000 1046.720000 202.520000 ;
+ RECT 1041.790000 207.480000 1042.790000 207.960000 ;
+ RECT 1045.455000 207.480000 1046.720000 207.960000 ;
+ RECT 1041.790000 196.600000 1042.790000 197.080000 ;
+ RECT 1045.455000 196.600000 1046.720000 197.080000 ;
+ RECT 1135.620000 174.840000 1136.720000 175.320000 ;
+ RECT 1135.620000 180.280000 1136.720000 180.760000 ;
+ RECT 1135.620000 185.720000 1136.720000 186.200000 ;
+ RECT 1135.620000 191.160000 1136.720000 191.640000 ;
+ RECT 1090.620000 174.840000 1091.720000 175.320000 ;
+ RECT 1090.620000 180.280000 1091.720000 180.760000 ;
+ RECT 1090.620000 185.720000 1091.720000 186.200000 ;
+ RECT 1090.620000 191.160000 1091.720000 191.640000 ;
+ RECT 1135.620000 153.080000 1136.720000 153.560000 ;
+ RECT 1135.620000 158.520000 1136.720000 159.000000 ;
+ RECT 1135.620000 163.960000 1136.720000 164.440000 ;
+ RECT 1135.620000 169.400000 1136.720000 169.880000 ;
+ RECT 1090.620000 153.080000 1091.720000 153.560000 ;
+ RECT 1090.620000 158.520000 1091.720000 159.000000 ;
+ RECT 1090.620000 163.960000 1091.720000 164.440000 ;
+ RECT 1090.620000 169.400000 1091.720000 169.880000 ;
+ RECT 1041.790000 191.160000 1042.790000 191.640000 ;
+ RECT 1045.455000 191.160000 1046.720000 191.640000 ;
+ RECT 1041.790000 185.720000 1042.790000 186.200000 ;
+ RECT 1045.455000 185.720000 1046.720000 186.200000 ;
+ RECT 1041.790000 180.280000 1042.790000 180.760000 ;
+ RECT 1045.455000 180.280000 1046.720000 180.760000 ;
+ RECT 1041.790000 174.840000 1042.790000 175.320000 ;
+ RECT 1045.455000 174.840000 1046.720000 175.320000 ;
+ RECT 1041.790000 169.400000 1042.790000 169.880000 ;
+ RECT 1045.455000 169.400000 1046.720000 169.880000 ;
+ RECT 1041.790000 158.520000 1042.790000 159.000000 ;
+ RECT 1045.455000 158.520000 1046.720000 159.000000 ;
+ RECT 1041.790000 163.960000 1042.790000 164.440000 ;
+ RECT 1045.455000 163.960000 1046.720000 164.440000 ;
+ RECT 1041.790000 153.080000 1042.790000 153.560000 ;
+ RECT 1045.455000 153.080000 1046.720000 153.560000 ;
+ RECT 1180.620000 245.560000 1181.720000 246.040000 ;
+ RECT 1225.620000 245.560000 1226.720000 246.040000 ;
+ RECT 1238.430000 245.560000 1239.430000 246.040000 ;
+ RECT 1090.620000 245.560000 1091.720000 246.040000 ;
+ RECT 1135.620000 245.560000 1136.720000 246.040000 ;
+ RECT 1041.790000 245.560000 1042.790000 246.040000 ;
+ RECT 1045.455000 245.560000 1046.720000 246.040000 ;
+ RECT 1040.560000 342.320000 1240.660000 343.320000 ;
+ RECT 1040.560000 146.750000 1240.660000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 145.500000 1042.790000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 344.760000 1042.790000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 145.500000 1239.430000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 344.760000 1239.430000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 146.750000 1041.560000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 146.750000 1240.660000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 342.320000 1041.560000 343.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 342.320000 1240.660000 343.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 139.140000 1046.720000 139.620000 ;
+ RECT 1045.455000 133.700000 1046.720000 134.180000 ;
+ RECT 1045.455000 128.260000 1046.720000 128.740000 ;
+ RECT 1045.455000 122.820000 1046.720000 123.300000 ;
+ RECT 1041.790000 115.240000 1042.790000 145.500000 ;
+ RECT 1238.430000 115.240000 1239.430000 145.500000 ;
+ RECT 1045.620000 116.490000 1046.720000 143.740000 ;
+ RECT 1090.620000 116.490000 1091.720000 143.740000 ;
+ RECT 1135.620000 116.490000 1136.720000 143.740000 ;
+ RECT 1180.620000 116.490000 1181.720000 143.740000 ;
+ RECT 1225.620000 116.490000 1226.720000 143.740000 ;
+ LAYER met3 ;
+ RECT 1238.430000 139.140000 1239.430000 139.620000 ;
+ RECT 1238.430000 133.700000 1239.430000 134.180000 ;
+ RECT 1225.620000 139.140000 1226.720000 139.620000 ;
+ RECT 1225.620000 133.700000 1226.720000 134.180000 ;
+ RECT 1180.620000 133.700000 1181.720000 134.180000 ;
+ RECT 1180.620000 139.140000 1181.720000 139.620000 ;
+ RECT 1135.620000 133.700000 1136.720000 134.180000 ;
+ RECT 1090.620000 133.700000 1091.720000 134.180000 ;
+ RECT 1135.620000 139.140000 1136.720000 139.620000 ;
+ RECT 1090.620000 139.140000 1091.720000 139.620000 ;
+ RECT 1045.455000 139.140000 1046.720000 139.620000 ;
+ RECT 1041.790000 139.140000 1042.790000 139.620000 ;
+ RECT 1045.455000 133.700000 1046.720000 134.180000 ;
+ RECT 1041.790000 133.700000 1042.790000 134.180000 ;
+ RECT 1238.430000 128.260000 1239.430000 128.740000 ;
+ RECT 1238.430000 122.820000 1239.430000 123.300000 ;
+ RECT 1225.620000 128.260000 1226.720000 128.740000 ;
+ RECT 1225.620000 122.820000 1226.720000 123.300000 ;
+ RECT 1180.620000 122.820000 1181.720000 123.300000 ;
+ RECT 1180.620000 128.260000 1181.720000 128.740000 ;
+ RECT 1135.620000 122.820000 1136.720000 123.300000 ;
+ RECT 1090.620000 122.820000 1091.720000 123.300000 ;
+ RECT 1135.620000 128.260000 1136.720000 128.740000 ;
+ RECT 1090.620000 128.260000 1091.720000 128.740000 ;
+ RECT 1045.455000 128.260000 1046.720000 128.740000 ;
+ RECT 1041.790000 128.260000 1042.790000 128.740000 ;
+ RECT 1045.455000 122.820000 1046.720000 123.300000 ;
+ RECT 1041.790000 122.820000 1042.790000 123.300000 ;
+ RECT 1040.560000 142.740000 1240.660000 143.740000 ;
+ RECT 1040.560000 116.490000 1240.660000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 116.490000 1041.560000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 116.490000 1240.660000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 142.740000 1041.560000 143.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 142.740000 1240.660000 143.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 115.240000 1042.790000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 144.500000 1042.790000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 115.240000 1239.430000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 144.500000 1239.430000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 3341.940000 1046.720000 3342.420000 ;
+ RECT 1045.455000 3331.060000 1046.720000 3331.540000 ;
+ RECT 1045.455000 3336.500000 1046.720000 3336.980000 ;
+ RECT 1045.455000 3325.620000 1046.720000 3326.100000 ;
+ RECT 1045.455000 3320.180000 1046.720000 3320.660000 ;
+ RECT 1045.455000 3314.740000 1046.720000 3315.220000 ;
+ RECT 1045.455000 3309.300000 1046.720000 3309.780000 ;
+ RECT 1045.455000 3303.860000 1046.720000 3304.340000 ;
+ RECT 1045.455000 3298.420000 1046.720000 3298.900000 ;
+ RECT 1045.455000 3287.540000 1046.720000 3288.020000 ;
+ RECT 1045.455000 3292.980000 1046.720000 3293.460000 ;
+ RECT 1045.455000 3282.100000 1046.720000 3282.580000 ;
+ RECT 1045.455000 3276.660000 1046.720000 3277.140000 ;
+ RECT 1045.455000 3271.220000 1046.720000 3271.700000 ;
+ RECT 1045.455000 3265.780000 1046.720000 3266.260000 ;
+ RECT 1045.455000 3260.340000 1046.720000 3260.820000 ;
+ RECT 1045.455000 3254.900000 1046.720000 3255.380000 ;
+ RECT 1045.455000 3244.020000 1046.720000 3244.500000 ;
+ RECT 1045.455000 3238.580000 1046.720000 3239.060000 ;
+ RECT 1045.455000 3233.140000 1046.720000 3233.620000 ;
+ RECT 1045.455000 3227.700000 1046.720000 3228.180000 ;
+ RECT 1045.455000 3222.260000 1046.720000 3222.740000 ;
+ RECT 1045.455000 3216.820000 1046.720000 3217.300000 ;
+ RECT 1045.455000 3205.940000 1046.720000 3206.420000 ;
+ RECT 1045.455000 3211.380000 1046.720000 3211.860000 ;
+ RECT 1045.455000 3200.500000 1046.720000 3200.980000 ;
+ RECT 1045.455000 3195.060000 1046.720000 3195.540000 ;
+ RECT 1045.455000 3189.620000 1046.720000 3190.100000 ;
+ RECT 1045.455000 3184.180000 1046.720000 3184.660000 ;
+ RECT 1045.455000 3178.740000 1046.720000 3179.220000 ;
+ RECT 1045.455000 3173.300000 1046.720000 3173.780000 ;
+ RECT 1045.455000 3162.420000 1046.720000 3162.900000 ;
+ RECT 1045.455000 3167.860000 1046.720000 3168.340000 ;
+ RECT 1045.455000 3156.980000 1046.720000 3157.460000 ;
+ RECT 1045.455000 3249.460000 1046.720000 3249.940000 ;
+ RECT 1225.620000 3150.650000 1226.720000 3347.220000 ;
+ RECT 1180.620000 3150.650000 1181.720000 3347.220000 ;
+ RECT 1238.430000 3149.400000 1239.430000 3349.660000 ;
+ RECT 1135.620000 3150.650000 1136.720000 3347.220000 ;
+ RECT 1090.620000 3150.650000 1091.720000 3347.220000 ;
+ RECT 1045.620000 3150.650000 1046.720000 3347.220000 ;
+ RECT 1041.790000 3149.400000 1042.790000 3349.660000 ;
+ LAYER met3 ;
+ RECT 1225.620000 3341.940000 1226.720000 3342.420000 ;
+ RECT 1238.430000 3341.940000 1239.430000 3342.420000 ;
+ RECT 1238.430000 3331.060000 1239.430000 3331.540000 ;
+ RECT 1238.430000 3325.620000 1239.430000 3326.100000 ;
+ RECT 1238.430000 3336.500000 1239.430000 3336.980000 ;
+ RECT 1225.620000 3336.500000 1226.720000 3336.980000 ;
+ RECT 1225.620000 3331.060000 1226.720000 3331.540000 ;
+ RECT 1225.620000 3325.620000 1226.720000 3326.100000 ;
+ RECT 1225.620000 3314.740000 1226.720000 3315.220000 ;
+ RECT 1225.620000 3320.180000 1226.720000 3320.660000 ;
+ RECT 1238.430000 3314.740000 1239.430000 3315.220000 ;
+ RECT 1238.430000 3320.180000 1239.430000 3320.660000 ;
+ RECT 1225.620000 3303.860000 1226.720000 3304.340000 ;
+ RECT 1225.620000 3309.300000 1226.720000 3309.780000 ;
+ RECT 1238.430000 3303.860000 1239.430000 3304.340000 ;
+ RECT 1238.430000 3309.300000 1239.430000 3309.780000 ;
+ RECT 1180.620000 3325.620000 1181.720000 3326.100000 ;
+ RECT 1180.620000 3331.060000 1181.720000 3331.540000 ;
+ RECT 1180.620000 3336.500000 1181.720000 3336.980000 ;
+ RECT 1180.620000 3341.940000 1181.720000 3342.420000 ;
+ RECT 1180.620000 3309.300000 1181.720000 3309.780000 ;
+ RECT 1180.620000 3303.860000 1181.720000 3304.340000 ;
+ RECT 1180.620000 3314.740000 1181.720000 3315.220000 ;
+ RECT 1180.620000 3320.180000 1181.720000 3320.660000 ;
+ RECT 1238.430000 3292.980000 1239.430000 3293.460000 ;
+ RECT 1238.430000 3287.540000 1239.430000 3288.020000 ;
+ RECT 1238.430000 3298.420000 1239.430000 3298.900000 ;
+ RECT 1225.620000 3298.420000 1226.720000 3298.900000 ;
+ RECT 1225.620000 3292.980000 1226.720000 3293.460000 ;
+ RECT 1225.620000 3287.540000 1226.720000 3288.020000 ;
+ RECT 1225.620000 3276.660000 1226.720000 3277.140000 ;
+ RECT 1225.620000 3282.100000 1226.720000 3282.580000 ;
+ RECT 1238.430000 3276.660000 1239.430000 3277.140000 ;
+ RECT 1238.430000 3282.100000 1239.430000 3282.580000 ;
+ RECT 1238.430000 3265.780000 1239.430000 3266.260000 ;
+ RECT 1238.430000 3271.220000 1239.430000 3271.700000 ;
+ RECT 1225.620000 3271.220000 1226.720000 3271.700000 ;
+ RECT 1225.620000 3265.780000 1226.720000 3266.260000 ;
+ RECT 1225.620000 3254.900000 1226.720000 3255.380000 ;
+ RECT 1225.620000 3260.340000 1226.720000 3260.820000 ;
+ RECT 1238.430000 3254.900000 1239.430000 3255.380000 ;
+ RECT 1238.430000 3260.340000 1239.430000 3260.820000 ;
+ RECT 1180.620000 3276.660000 1181.720000 3277.140000 ;
+ RECT 1180.620000 3282.100000 1181.720000 3282.580000 ;
+ RECT 1180.620000 3287.540000 1181.720000 3288.020000 ;
+ RECT 1180.620000 3292.980000 1181.720000 3293.460000 ;
+ RECT 1180.620000 3298.420000 1181.720000 3298.900000 ;
+ RECT 1180.620000 3254.900000 1181.720000 3255.380000 ;
+ RECT 1180.620000 3260.340000 1181.720000 3260.820000 ;
+ RECT 1180.620000 3265.780000 1181.720000 3266.260000 ;
+ RECT 1180.620000 3271.220000 1181.720000 3271.700000 ;
+ RECT 1135.620000 3331.060000 1136.720000 3331.540000 ;
+ RECT 1135.620000 3325.620000 1136.720000 3326.100000 ;
+ RECT 1135.620000 3336.500000 1136.720000 3336.980000 ;
+ RECT 1135.620000 3341.940000 1136.720000 3342.420000 ;
+ RECT 1090.620000 3325.620000 1091.720000 3326.100000 ;
+ RECT 1090.620000 3331.060000 1091.720000 3331.540000 ;
+ RECT 1090.620000 3336.500000 1091.720000 3336.980000 ;
+ RECT 1090.620000 3341.940000 1091.720000 3342.420000 ;
+ RECT 1135.620000 3303.860000 1136.720000 3304.340000 ;
+ RECT 1135.620000 3309.300000 1136.720000 3309.780000 ;
+ RECT 1135.620000 3314.740000 1136.720000 3315.220000 ;
+ RECT 1135.620000 3320.180000 1136.720000 3320.660000 ;
+ RECT 1090.620000 3303.860000 1091.720000 3304.340000 ;
+ RECT 1090.620000 3309.300000 1091.720000 3309.780000 ;
+ RECT 1090.620000 3314.740000 1091.720000 3315.220000 ;
+ RECT 1090.620000 3320.180000 1091.720000 3320.660000 ;
+ RECT 1041.790000 3341.940000 1042.790000 3342.420000 ;
+ RECT 1045.455000 3341.940000 1046.720000 3342.420000 ;
+ RECT 1041.790000 3331.060000 1042.790000 3331.540000 ;
+ RECT 1045.455000 3331.060000 1046.720000 3331.540000 ;
+ RECT 1041.790000 3336.500000 1042.790000 3336.980000 ;
+ RECT 1045.455000 3336.500000 1046.720000 3336.980000 ;
+ RECT 1041.790000 3325.620000 1042.790000 3326.100000 ;
+ RECT 1045.455000 3325.620000 1046.720000 3326.100000 ;
+ RECT 1041.790000 3320.180000 1042.790000 3320.660000 ;
+ RECT 1045.455000 3320.180000 1046.720000 3320.660000 ;
+ RECT 1041.790000 3314.740000 1042.790000 3315.220000 ;
+ RECT 1045.455000 3314.740000 1046.720000 3315.220000 ;
+ RECT 1041.790000 3309.300000 1042.790000 3309.780000 ;
+ RECT 1045.455000 3309.300000 1046.720000 3309.780000 ;
+ RECT 1041.790000 3303.860000 1042.790000 3304.340000 ;
+ RECT 1045.455000 3303.860000 1046.720000 3304.340000 ;
+ RECT 1135.620000 3276.660000 1136.720000 3277.140000 ;
+ RECT 1135.620000 3282.100000 1136.720000 3282.580000 ;
+ RECT 1135.620000 3287.540000 1136.720000 3288.020000 ;
+ RECT 1135.620000 3292.980000 1136.720000 3293.460000 ;
+ RECT 1135.620000 3298.420000 1136.720000 3298.900000 ;
+ RECT 1090.620000 3276.660000 1091.720000 3277.140000 ;
+ RECT 1090.620000 3282.100000 1091.720000 3282.580000 ;
+ RECT 1090.620000 3287.540000 1091.720000 3288.020000 ;
+ RECT 1090.620000 3292.980000 1091.720000 3293.460000 ;
+ RECT 1090.620000 3298.420000 1091.720000 3298.900000 ;
+ RECT 1135.620000 3254.900000 1136.720000 3255.380000 ;
+ RECT 1135.620000 3260.340000 1136.720000 3260.820000 ;
+ RECT 1135.620000 3265.780000 1136.720000 3266.260000 ;
+ RECT 1135.620000 3271.220000 1136.720000 3271.700000 ;
+ RECT 1090.620000 3254.900000 1091.720000 3255.380000 ;
+ RECT 1090.620000 3260.340000 1091.720000 3260.820000 ;
+ RECT 1090.620000 3265.780000 1091.720000 3266.260000 ;
+ RECT 1090.620000 3271.220000 1091.720000 3271.700000 ;
+ RECT 1041.790000 3298.420000 1042.790000 3298.900000 ;
+ RECT 1045.455000 3298.420000 1046.720000 3298.900000 ;
+ RECT 1041.790000 3287.540000 1042.790000 3288.020000 ;
+ RECT 1045.455000 3287.540000 1046.720000 3288.020000 ;
+ RECT 1041.790000 3292.980000 1042.790000 3293.460000 ;
+ RECT 1045.455000 3292.980000 1046.720000 3293.460000 ;
+ RECT 1041.790000 3282.100000 1042.790000 3282.580000 ;
+ RECT 1045.455000 3282.100000 1046.720000 3282.580000 ;
+ RECT 1041.790000 3276.660000 1042.790000 3277.140000 ;
+ RECT 1045.455000 3276.660000 1046.720000 3277.140000 ;
+ RECT 1041.790000 3271.220000 1042.790000 3271.700000 ;
+ RECT 1045.455000 3271.220000 1046.720000 3271.700000 ;
+ RECT 1041.790000 3265.780000 1042.790000 3266.260000 ;
+ RECT 1045.455000 3265.780000 1046.720000 3266.260000 ;
+ RECT 1041.790000 3260.340000 1042.790000 3260.820000 ;
+ RECT 1045.455000 3260.340000 1046.720000 3260.820000 ;
+ RECT 1041.790000 3254.900000 1042.790000 3255.380000 ;
+ RECT 1045.455000 3254.900000 1046.720000 3255.380000 ;
+ RECT 1225.620000 3238.580000 1226.720000 3239.060000 ;
+ RECT 1225.620000 3244.020000 1226.720000 3244.500000 ;
+ RECT 1238.430000 3238.580000 1239.430000 3239.060000 ;
+ RECT 1238.430000 3244.020000 1239.430000 3244.500000 ;
+ RECT 1238.430000 3227.700000 1239.430000 3228.180000 ;
+ RECT 1238.430000 3233.140000 1239.430000 3233.620000 ;
+ RECT 1225.620000 3233.140000 1226.720000 3233.620000 ;
+ RECT 1225.620000 3227.700000 1226.720000 3228.180000 ;
+ RECT 1225.620000 3216.820000 1226.720000 3217.300000 ;
+ RECT 1225.620000 3222.260000 1226.720000 3222.740000 ;
+ RECT 1238.430000 3216.820000 1239.430000 3217.300000 ;
+ RECT 1238.430000 3222.260000 1239.430000 3222.740000 ;
+ RECT 1238.430000 3205.940000 1239.430000 3206.420000 ;
+ RECT 1238.430000 3200.500000 1239.430000 3200.980000 ;
+ RECT 1238.430000 3211.380000 1239.430000 3211.860000 ;
+ RECT 1225.620000 3211.380000 1226.720000 3211.860000 ;
+ RECT 1225.620000 3205.940000 1226.720000 3206.420000 ;
+ RECT 1225.620000 3200.500000 1226.720000 3200.980000 ;
+ RECT 1180.620000 3227.700000 1181.720000 3228.180000 ;
+ RECT 1180.620000 3233.140000 1181.720000 3233.620000 ;
+ RECT 1180.620000 3238.580000 1181.720000 3239.060000 ;
+ RECT 1180.620000 3244.020000 1181.720000 3244.500000 ;
+ RECT 1180.620000 3200.500000 1181.720000 3200.980000 ;
+ RECT 1180.620000 3205.940000 1181.720000 3206.420000 ;
+ RECT 1180.620000 3211.380000 1181.720000 3211.860000 ;
+ RECT 1180.620000 3216.820000 1181.720000 3217.300000 ;
+ RECT 1180.620000 3222.260000 1181.720000 3222.740000 ;
+ RECT 1225.620000 3189.620000 1226.720000 3190.100000 ;
+ RECT 1225.620000 3195.060000 1226.720000 3195.540000 ;
+ RECT 1238.430000 3189.620000 1239.430000 3190.100000 ;
+ RECT 1238.430000 3195.060000 1239.430000 3195.540000 ;
+ RECT 1225.620000 3178.740000 1226.720000 3179.220000 ;
+ RECT 1225.620000 3184.180000 1226.720000 3184.660000 ;
+ RECT 1238.430000 3178.740000 1239.430000 3179.220000 ;
+ RECT 1238.430000 3184.180000 1239.430000 3184.660000 ;
+ RECT 1238.430000 3167.860000 1239.430000 3168.340000 ;
+ RECT 1238.430000 3162.420000 1239.430000 3162.900000 ;
+ RECT 1238.430000 3173.300000 1239.430000 3173.780000 ;
+ RECT 1225.620000 3173.300000 1226.720000 3173.780000 ;
+ RECT 1225.620000 3167.860000 1226.720000 3168.340000 ;
+ RECT 1225.620000 3162.420000 1226.720000 3162.900000 ;
+ RECT 1225.620000 3156.980000 1226.720000 3157.460000 ;
+ RECT 1238.430000 3156.980000 1239.430000 3157.460000 ;
+ RECT 1180.620000 3178.740000 1181.720000 3179.220000 ;
+ RECT 1180.620000 3184.180000 1181.720000 3184.660000 ;
+ RECT 1180.620000 3189.620000 1181.720000 3190.100000 ;
+ RECT 1180.620000 3195.060000 1181.720000 3195.540000 ;
+ RECT 1180.620000 3156.980000 1181.720000 3157.460000 ;
+ RECT 1180.620000 3162.420000 1181.720000 3162.900000 ;
+ RECT 1180.620000 3167.860000 1181.720000 3168.340000 ;
+ RECT 1180.620000 3173.300000 1181.720000 3173.780000 ;
+ RECT 1135.620000 3227.700000 1136.720000 3228.180000 ;
+ RECT 1135.620000 3233.140000 1136.720000 3233.620000 ;
+ RECT 1135.620000 3238.580000 1136.720000 3239.060000 ;
+ RECT 1135.620000 3244.020000 1136.720000 3244.500000 ;
+ RECT 1090.620000 3227.700000 1091.720000 3228.180000 ;
+ RECT 1090.620000 3233.140000 1091.720000 3233.620000 ;
+ RECT 1090.620000 3238.580000 1091.720000 3239.060000 ;
+ RECT 1090.620000 3244.020000 1091.720000 3244.500000 ;
+ RECT 1135.620000 3200.500000 1136.720000 3200.980000 ;
+ RECT 1135.620000 3205.940000 1136.720000 3206.420000 ;
+ RECT 1135.620000 3211.380000 1136.720000 3211.860000 ;
+ RECT 1135.620000 3216.820000 1136.720000 3217.300000 ;
+ RECT 1135.620000 3222.260000 1136.720000 3222.740000 ;
+ RECT 1090.620000 3200.500000 1091.720000 3200.980000 ;
+ RECT 1090.620000 3205.940000 1091.720000 3206.420000 ;
+ RECT 1090.620000 3211.380000 1091.720000 3211.860000 ;
+ RECT 1090.620000 3216.820000 1091.720000 3217.300000 ;
+ RECT 1090.620000 3222.260000 1091.720000 3222.740000 ;
+ RECT 1041.790000 3244.020000 1042.790000 3244.500000 ;
+ RECT 1045.455000 3244.020000 1046.720000 3244.500000 ;
+ RECT 1041.790000 3238.580000 1042.790000 3239.060000 ;
+ RECT 1045.455000 3238.580000 1046.720000 3239.060000 ;
+ RECT 1041.790000 3233.140000 1042.790000 3233.620000 ;
+ RECT 1045.455000 3233.140000 1046.720000 3233.620000 ;
+ RECT 1041.790000 3227.700000 1042.790000 3228.180000 ;
+ RECT 1045.455000 3227.700000 1046.720000 3228.180000 ;
+ RECT 1041.790000 3222.260000 1042.790000 3222.740000 ;
+ RECT 1045.455000 3222.260000 1046.720000 3222.740000 ;
+ RECT 1041.790000 3216.820000 1042.790000 3217.300000 ;
+ RECT 1045.455000 3216.820000 1046.720000 3217.300000 ;
+ RECT 1041.790000 3205.940000 1042.790000 3206.420000 ;
+ RECT 1045.455000 3205.940000 1046.720000 3206.420000 ;
+ RECT 1041.790000 3211.380000 1042.790000 3211.860000 ;
+ RECT 1045.455000 3211.380000 1046.720000 3211.860000 ;
+ RECT 1041.790000 3200.500000 1042.790000 3200.980000 ;
+ RECT 1045.455000 3200.500000 1046.720000 3200.980000 ;
+ RECT 1135.620000 3178.740000 1136.720000 3179.220000 ;
+ RECT 1135.620000 3184.180000 1136.720000 3184.660000 ;
+ RECT 1135.620000 3189.620000 1136.720000 3190.100000 ;
+ RECT 1135.620000 3195.060000 1136.720000 3195.540000 ;
+ RECT 1090.620000 3178.740000 1091.720000 3179.220000 ;
+ RECT 1090.620000 3184.180000 1091.720000 3184.660000 ;
+ RECT 1090.620000 3189.620000 1091.720000 3190.100000 ;
+ RECT 1090.620000 3195.060000 1091.720000 3195.540000 ;
+ RECT 1135.620000 3156.980000 1136.720000 3157.460000 ;
+ RECT 1135.620000 3162.420000 1136.720000 3162.900000 ;
+ RECT 1135.620000 3167.860000 1136.720000 3168.340000 ;
+ RECT 1135.620000 3173.300000 1136.720000 3173.780000 ;
+ RECT 1090.620000 3156.980000 1091.720000 3157.460000 ;
+ RECT 1090.620000 3162.420000 1091.720000 3162.900000 ;
+ RECT 1090.620000 3167.860000 1091.720000 3168.340000 ;
+ RECT 1090.620000 3173.300000 1091.720000 3173.780000 ;
+ RECT 1041.790000 3195.060000 1042.790000 3195.540000 ;
+ RECT 1045.455000 3195.060000 1046.720000 3195.540000 ;
+ RECT 1041.790000 3189.620000 1042.790000 3190.100000 ;
+ RECT 1045.455000 3189.620000 1046.720000 3190.100000 ;
+ RECT 1041.790000 3184.180000 1042.790000 3184.660000 ;
+ RECT 1045.455000 3184.180000 1046.720000 3184.660000 ;
+ RECT 1041.790000 3178.740000 1042.790000 3179.220000 ;
+ RECT 1045.455000 3178.740000 1046.720000 3179.220000 ;
+ RECT 1041.790000 3173.300000 1042.790000 3173.780000 ;
+ RECT 1045.455000 3173.300000 1046.720000 3173.780000 ;
+ RECT 1041.790000 3162.420000 1042.790000 3162.900000 ;
+ RECT 1045.455000 3162.420000 1046.720000 3162.900000 ;
+ RECT 1041.790000 3167.860000 1042.790000 3168.340000 ;
+ RECT 1045.455000 3167.860000 1046.720000 3168.340000 ;
+ RECT 1041.790000 3156.980000 1042.790000 3157.460000 ;
+ RECT 1045.455000 3156.980000 1046.720000 3157.460000 ;
+ RECT 1180.620000 3249.460000 1181.720000 3249.940000 ;
+ RECT 1225.620000 3249.460000 1226.720000 3249.940000 ;
+ RECT 1238.430000 3249.460000 1239.430000 3249.940000 ;
+ RECT 1090.620000 3249.460000 1091.720000 3249.940000 ;
+ RECT 1135.620000 3249.460000 1136.720000 3249.940000 ;
+ RECT 1041.790000 3249.460000 1042.790000 3249.940000 ;
+ RECT 1045.455000 3249.460000 1046.720000 3249.940000 ;
+ RECT 1040.560000 3346.220000 1240.660000 3347.220000 ;
+ RECT 1040.560000 3150.650000 1240.660000 3151.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 3149.400000 1042.790000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 3348.660000 1042.790000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 3149.400000 1239.430000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 3348.660000 1239.430000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 3150.650000 1041.560000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 3150.650000 1240.660000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 3346.220000 1041.560000 3347.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 3346.220000 1240.660000 3347.220000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 3141.680000 1046.720000 3142.160000 ;
+ RECT 1045.455000 3130.800000 1046.720000 3131.280000 ;
+ RECT 1045.455000 3136.240000 1046.720000 3136.720000 ;
+ RECT 1045.455000 3125.360000 1046.720000 3125.840000 ;
+ RECT 1045.455000 3119.920000 1046.720000 3120.400000 ;
+ RECT 1045.455000 3114.480000 1046.720000 3114.960000 ;
+ RECT 1045.455000 3109.040000 1046.720000 3109.520000 ;
+ RECT 1045.455000 3103.600000 1046.720000 3104.080000 ;
+ RECT 1045.455000 3098.160000 1046.720000 3098.640000 ;
+ RECT 1045.455000 3087.280000 1046.720000 3087.760000 ;
+ RECT 1045.455000 3092.720000 1046.720000 3093.200000 ;
+ RECT 1045.455000 3081.840000 1046.720000 3082.320000 ;
+ RECT 1045.455000 3076.400000 1046.720000 3076.880000 ;
+ RECT 1045.455000 3070.960000 1046.720000 3071.440000 ;
+ RECT 1045.455000 3065.520000 1046.720000 3066.000000 ;
+ RECT 1045.455000 3060.080000 1046.720000 3060.560000 ;
+ RECT 1045.455000 3054.640000 1046.720000 3055.120000 ;
+ RECT 1045.455000 3043.760000 1046.720000 3044.240000 ;
+ RECT 1045.455000 3038.320000 1046.720000 3038.800000 ;
+ RECT 1045.455000 3032.880000 1046.720000 3033.360000 ;
+ RECT 1045.455000 3027.440000 1046.720000 3027.920000 ;
+ RECT 1045.455000 3022.000000 1046.720000 3022.480000 ;
+ RECT 1045.455000 3016.560000 1046.720000 3017.040000 ;
+ RECT 1045.455000 3005.680000 1046.720000 3006.160000 ;
+ RECT 1045.455000 3011.120000 1046.720000 3011.600000 ;
+ RECT 1045.455000 3000.240000 1046.720000 3000.720000 ;
+ RECT 1045.455000 2994.800000 1046.720000 2995.280000 ;
+ RECT 1045.455000 2989.360000 1046.720000 2989.840000 ;
+ RECT 1045.455000 2983.920000 1046.720000 2984.400000 ;
+ RECT 1045.455000 2978.480000 1046.720000 2978.960000 ;
+ RECT 1045.455000 2973.040000 1046.720000 2973.520000 ;
+ RECT 1045.455000 2962.160000 1046.720000 2962.640000 ;
+ RECT 1045.455000 2967.600000 1046.720000 2968.080000 ;
+ RECT 1045.455000 2956.720000 1046.720000 2957.200000 ;
+ RECT 1045.455000 3049.200000 1046.720000 3049.680000 ;
+ RECT 1225.620000 2950.390000 1226.720000 3146.960000 ;
+ RECT 1180.620000 2950.390000 1181.720000 3146.960000 ;
+ RECT 1238.430000 2949.140000 1239.430000 3149.400000 ;
+ RECT 1135.620000 2950.390000 1136.720000 3146.960000 ;
+ RECT 1090.620000 2950.390000 1091.720000 3146.960000 ;
+ RECT 1045.620000 2950.390000 1046.720000 3146.960000 ;
+ RECT 1041.790000 2949.140000 1042.790000 3149.400000 ;
+ LAYER met3 ;
+ RECT 1225.620000 3141.680000 1226.720000 3142.160000 ;
+ RECT 1238.430000 3141.680000 1239.430000 3142.160000 ;
+ RECT 1238.430000 3130.800000 1239.430000 3131.280000 ;
+ RECT 1238.430000 3125.360000 1239.430000 3125.840000 ;
+ RECT 1238.430000 3136.240000 1239.430000 3136.720000 ;
+ RECT 1225.620000 3136.240000 1226.720000 3136.720000 ;
+ RECT 1225.620000 3130.800000 1226.720000 3131.280000 ;
+ RECT 1225.620000 3125.360000 1226.720000 3125.840000 ;
+ RECT 1225.620000 3114.480000 1226.720000 3114.960000 ;
+ RECT 1225.620000 3119.920000 1226.720000 3120.400000 ;
+ RECT 1238.430000 3114.480000 1239.430000 3114.960000 ;
+ RECT 1238.430000 3119.920000 1239.430000 3120.400000 ;
+ RECT 1225.620000 3103.600000 1226.720000 3104.080000 ;
+ RECT 1225.620000 3109.040000 1226.720000 3109.520000 ;
+ RECT 1238.430000 3103.600000 1239.430000 3104.080000 ;
+ RECT 1238.430000 3109.040000 1239.430000 3109.520000 ;
+ RECT 1180.620000 3125.360000 1181.720000 3125.840000 ;
+ RECT 1180.620000 3130.800000 1181.720000 3131.280000 ;
+ RECT 1180.620000 3136.240000 1181.720000 3136.720000 ;
+ RECT 1180.620000 3141.680000 1181.720000 3142.160000 ;
+ RECT 1180.620000 3109.040000 1181.720000 3109.520000 ;
+ RECT 1180.620000 3103.600000 1181.720000 3104.080000 ;
+ RECT 1180.620000 3114.480000 1181.720000 3114.960000 ;
+ RECT 1180.620000 3119.920000 1181.720000 3120.400000 ;
+ RECT 1238.430000 3092.720000 1239.430000 3093.200000 ;
+ RECT 1238.430000 3087.280000 1239.430000 3087.760000 ;
+ RECT 1238.430000 3098.160000 1239.430000 3098.640000 ;
+ RECT 1225.620000 3098.160000 1226.720000 3098.640000 ;
+ RECT 1225.620000 3092.720000 1226.720000 3093.200000 ;
+ RECT 1225.620000 3087.280000 1226.720000 3087.760000 ;
+ RECT 1225.620000 3076.400000 1226.720000 3076.880000 ;
+ RECT 1225.620000 3081.840000 1226.720000 3082.320000 ;
+ RECT 1238.430000 3076.400000 1239.430000 3076.880000 ;
+ RECT 1238.430000 3081.840000 1239.430000 3082.320000 ;
+ RECT 1238.430000 3065.520000 1239.430000 3066.000000 ;
+ RECT 1238.430000 3070.960000 1239.430000 3071.440000 ;
+ RECT 1225.620000 3070.960000 1226.720000 3071.440000 ;
+ RECT 1225.620000 3065.520000 1226.720000 3066.000000 ;
+ RECT 1225.620000 3054.640000 1226.720000 3055.120000 ;
+ RECT 1225.620000 3060.080000 1226.720000 3060.560000 ;
+ RECT 1238.430000 3054.640000 1239.430000 3055.120000 ;
+ RECT 1238.430000 3060.080000 1239.430000 3060.560000 ;
+ RECT 1180.620000 3076.400000 1181.720000 3076.880000 ;
+ RECT 1180.620000 3081.840000 1181.720000 3082.320000 ;
+ RECT 1180.620000 3087.280000 1181.720000 3087.760000 ;
+ RECT 1180.620000 3092.720000 1181.720000 3093.200000 ;
+ RECT 1180.620000 3098.160000 1181.720000 3098.640000 ;
+ RECT 1180.620000 3054.640000 1181.720000 3055.120000 ;
+ RECT 1180.620000 3060.080000 1181.720000 3060.560000 ;
+ RECT 1180.620000 3065.520000 1181.720000 3066.000000 ;
+ RECT 1180.620000 3070.960000 1181.720000 3071.440000 ;
+ RECT 1135.620000 3130.800000 1136.720000 3131.280000 ;
+ RECT 1135.620000 3125.360000 1136.720000 3125.840000 ;
+ RECT 1135.620000 3136.240000 1136.720000 3136.720000 ;
+ RECT 1135.620000 3141.680000 1136.720000 3142.160000 ;
+ RECT 1090.620000 3125.360000 1091.720000 3125.840000 ;
+ RECT 1090.620000 3130.800000 1091.720000 3131.280000 ;
+ RECT 1090.620000 3136.240000 1091.720000 3136.720000 ;
+ RECT 1090.620000 3141.680000 1091.720000 3142.160000 ;
+ RECT 1135.620000 3103.600000 1136.720000 3104.080000 ;
+ RECT 1135.620000 3109.040000 1136.720000 3109.520000 ;
+ RECT 1135.620000 3114.480000 1136.720000 3114.960000 ;
+ RECT 1135.620000 3119.920000 1136.720000 3120.400000 ;
+ RECT 1090.620000 3103.600000 1091.720000 3104.080000 ;
+ RECT 1090.620000 3109.040000 1091.720000 3109.520000 ;
+ RECT 1090.620000 3114.480000 1091.720000 3114.960000 ;
+ RECT 1090.620000 3119.920000 1091.720000 3120.400000 ;
+ RECT 1041.790000 3141.680000 1042.790000 3142.160000 ;
+ RECT 1045.455000 3141.680000 1046.720000 3142.160000 ;
+ RECT 1041.790000 3130.800000 1042.790000 3131.280000 ;
+ RECT 1045.455000 3130.800000 1046.720000 3131.280000 ;
+ RECT 1041.790000 3136.240000 1042.790000 3136.720000 ;
+ RECT 1045.455000 3136.240000 1046.720000 3136.720000 ;
+ RECT 1041.790000 3125.360000 1042.790000 3125.840000 ;
+ RECT 1045.455000 3125.360000 1046.720000 3125.840000 ;
+ RECT 1041.790000 3119.920000 1042.790000 3120.400000 ;
+ RECT 1045.455000 3119.920000 1046.720000 3120.400000 ;
+ RECT 1041.790000 3114.480000 1042.790000 3114.960000 ;
+ RECT 1045.455000 3114.480000 1046.720000 3114.960000 ;
+ RECT 1041.790000 3109.040000 1042.790000 3109.520000 ;
+ RECT 1045.455000 3109.040000 1046.720000 3109.520000 ;
+ RECT 1041.790000 3103.600000 1042.790000 3104.080000 ;
+ RECT 1045.455000 3103.600000 1046.720000 3104.080000 ;
+ RECT 1135.620000 3076.400000 1136.720000 3076.880000 ;
+ RECT 1135.620000 3081.840000 1136.720000 3082.320000 ;
+ RECT 1135.620000 3087.280000 1136.720000 3087.760000 ;
+ RECT 1135.620000 3092.720000 1136.720000 3093.200000 ;
+ RECT 1135.620000 3098.160000 1136.720000 3098.640000 ;
+ RECT 1090.620000 3076.400000 1091.720000 3076.880000 ;
+ RECT 1090.620000 3081.840000 1091.720000 3082.320000 ;
+ RECT 1090.620000 3087.280000 1091.720000 3087.760000 ;
+ RECT 1090.620000 3092.720000 1091.720000 3093.200000 ;
+ RECT 1090.620000 3098.160000 1091.720000 3098.640000 ;
+ RECT 1135.620000 3054.640000 1136.720000 3055.120000 ;
+ RECT 1135.620000 3060.080000 1136.720000 3060.560000 ;
+ RECT 1135.620000 3065.520000 1136.720000 3066.000000 ;
+ RECT 1135.620000 3070.960000 1136.720000 3071.440000 ;
+ RECT 1090.620000 3054.640000 1091.720000 3055.120000 ;
+ RECT 1090.620000 3060.080000 1091.720000 3060.560000 ;
+ RECT 1090.620000 3065.520000 1091.720000 3066.000000 ;
+ RECT 1090.620000 3070.960000 1091.720000 3071.440000 ;
+ RECT 1041.790000 3098.160000 1042.790000 3098.640000 ;
+ RECT 1045.455000 3098.160000 1046.720000 3098.640000 ;
+ RECT 1041.790000 3087.280000 1042.790000 3087.760000 ;
+ RECT 1045.455000 3087.280000 1046.720000 3087.760000 ;
+ RECT 1041.790000 3092.720000 1042.790000 3093.200000 ;
+ RECT 1045.455000 3092.720000 1046.720000 3093.200000 ;
+ RECT 1041.790000 3081.840000 1042.790000 3082.320000 ;
+ RECT 1045.455000 3081.840000 1046.720000 3082.320000 ;
+ RECT 1041.790000 3076.400000 1042.790000 3076.880000 ;
+ RECT 1045.455000 3076.400000 1046.720000 3076.880000 ;
+ RECT 1041.790000 3070.960000 1042.790000 3071.440000 ;
+ RECT 1045.455000 3070.960000 1046.720000 3071.440000 ;
+ RECT 1041.790000 3065.520000 1042.790000 3066.000000 ;
+ RECT 1045.455000 3065.520000 1046.720000 3066.000000 ;
+ RECT 1041.790000 3060.080000 1042.790000 3060.560000 ;
+ RECT 1045.455000 3060.080000 1046.720000 3060.560000 ;
+ RECT 1041.790000 3054.640000 1042.790000 3055.120000 ;
+ RECT 1045.455000 3054.640000 1046.720000 3055.120000 ;
+ RECT 1225.620000 3038.320000 1226.720000 3038.800000 ;
+ RECT 1225.620000 3043.760000 1226.720000 3044.240000 ;
+ RECT 1238.430000 3038.320000 1239.430000 3038.800000 ;
+ RECT 1238.430000 3043.760000 1239.430000 3044.240000 ;
+ RECT 1238.430000 3027.440000 1239.430000 3027.920000 ;
+ RECT 1238.430000 3032.880000 1239.430000 3033.360000 ;
+ RECT 1225.620000 3032.880000 1226.720000 3033.360000 ;
+ RECT 1225.620000 3027.440000 1226.720000 3027.920000 ;
+ RECT 1225.620000 3016.560000 1226.720000 3017.040000 ;
+ RECT 1225.620000 3022.000000 1226.720000 3022.480000 ;
+ RECT 1238.430000 3016.560000 1239.430000 3017.040000 ;
+ RECT 1238.430000 3022.000000 1239.430000 3022.480000 ;
+ RECT 1238.430000 3005.680000 1239.430000 3006.160000 ;
+ RECT 1238.430000 3000.240000 1239.430000 3000.720000 ;
+ RECT 1238.430000 3011.120000 1239.430000 3011.600000 ;
+ RECT 1225.620000 3011.120000 1226.720000 3011.600000 ;
+ RECT 1225.620000 3005.680000 1226.720000 3006.160000 ;
+ RECT 1225.620000 3000.240000 1226.720000 3000.720000 ;
+ RECT 1180.620000 3027.440000 1181.720000 3027.920000 ;
+ RECT 1180.620000 3032.880000 1181.720000 3033.360000 ;
+ RECT 1180.620000 3038.320000 1181.720000 3038.800000 ;
+ RECT 1180.620000 3043.760000 1181.720000 3044.240000 ;
+ RECT 1180.620000 3000.240000 1181.720000 3000.720000 ;
+ RECT 1180.620000 3005.680000 1181.720000 3006.160000 ;
+ RECT 1180.620000 3011.120000 1181.720000 3011.600000 ;
+ RECT 1180.620000 3016.560000 1181.720000 3017.040000 ;
+ RECT 1180.620000 3022.000000 1181.720000 3022.480000 ;
+ RECT 1225.620000 2989.360000 1226.720000 2989.840000 ;
+ RECT 1225.620000 2994.800000 1226.720000 2995.280000 ;
+ RECT 1238.430000 2989.360000 1239.430000 2989.840000 ;
+ RECT 1238.430000 2994.800000 1239.430000 2995.280000 ;
+ RECT 1225.620000 2978.480000 1226.720000 2978.960000 ;
+ RECT 1225.620000 2983.920000 1226.720000 2984.400000 ;
+ RECT 1238.430000 2978.480000 1239.430000 2978.960000 ;
+ RECT 1238.430000 2983.920000 1239.430000 2984.400000 ;
+ RECT 1238.430000 2967.600000 1239.430000 2968.080000 ;
+ RECT 1238.430000 2962.160000 1239.430000 2962.640000 ;
+ RECT 1238.430000 2973.040000 1239.430000 2973.520000 ;
+ RECT 1225.620000 2973.040000 1226.720000 2973.520000 ;
+ RECT 1225.620000 2967.600000 1226.720000 2968.080000 ;
+ RECT 1225.620000 2962.160000 1226.720000 2962.640000 ;
+ RECT 1225.620000 2956.720000 1226.720000 2957.200000 ;
+ RECT 1238.430000 2956.720000 1239.430000 2957.200000 ;
+ RECT 1180.620000 2978.480000 1181.720000 2978.960000 ;
+ RECT 1180.620000 2983.920000 1181.720000 2984.400000 ;
+ RECT 1180.620000 2989.360000 1181.720000 2989.840000 ;
+ RECT 1180.620000 2994.800000 1181.720000 2995.280000 ;
+ RECT 1180.620000 2956.720000 1181.720000 2957.200000 ;
+ RECT 1180.620000 2962.160000 1181.720000 2962.640000 ;
+ RECT 1180.620000 2967.600000 1181.720000 2968.080000 ;
+ RECT 1180.620000 2973.040000 1181.720000 2973.520000 ;
+ RECT 1135.620000 3027.440000 1136.720000 3027.920000 ;
+ RECT 1135.620000 3032.880000 1136.720000 3033.360000 ;
+ RECT 1135.620000 3038.320000 1136.720000 3038.800000 ;
+ RECT 1135.620000 3043.760000 1136.720000 3044.240000 ;
+ RECT 1090.620000 3027.440000 1091.720000 3027.920000 ;
+ RECT 1090.620000 3032.880000 1091.720000 3033.360000 ;
+ RECT 1090.620000 3038.320000 1091.720000 3038.800000 ;
+ RECT 1090.620000 3043.760000 1091.720000 3044.240000 ;
+ RECT 1135.620000 3000.240000 1136.720000 3000.720000 ;
+ RECT 1135.620000 3005.680000 1136.720000 3006.160000 ;
+ RECT 1135.620000 3011.120000 1136.720000 3011.600000 ;
+ RECT 1135.620000 3016.560000 1136.720000 3017.040000 ;
+ RECT 1135.620000 3022.000000 1136.720000 3022.480000 ;
+ RECT 1090.620000 3000.240000 1091.720000 3000.720000 ;
+ RECT 1090.620000 3005.680000 1091.720000 3006.160000 ;
+ RECT 1090.620000 3011.120000 1091.720000 3011.600000 ;
+ RECT 1090.620000 3016.560000 1091.720000 3017.040000 ;
+ RECT 1090.620000 3022.000000 1091.720000 3022.480000 ;
+ RECT 1041.790000 3043.760000 1042.790000 3044.240000 ;
+ RECT 1045.455000 3043.760000 1046.720000 3044.240000 ;
+ RECT 1041.790000 3038.320000 1042.790000 3038.800000 ;
+ RECT 1045.455000 3038.320000 1046.720000 3038.800000 ;
+ RECT 1041.790000 3032.880000 1042.790000 3033.360000 ;
+ RECT 1045.455000 3032.880000 1046.720000 3033.360000 ;
+ RECT 1041.790000 3027.440000 1042.790000 3027.920000 ;
+ RECT 1045.455000 3027.440000 1046.720000 3027.920000 ;
+ RECT 1041.790000 3022.000000 1042.790000 3022.480000 ;
+ RECT 1045.455000 3022.000000 1046.720000 3022.480000 ;
+ RECT 1041.790000 3016.560000 1042.790000 3017.040000 ;
+ RECT 1045.455000 3016.560000 1046.720000 3017.040000 ;
+ RECT 1041.790000 3005.680000 1042.790000 3006.160000 ;
+ RECT 1045.455000 3005.680000 1046.720000 3006.160000 ;
+ RECT 1041.790000 3011.120000 1042.790000 3011.600000 ;
+ RECT 1045.455000 3011.120000 1046.720000 3011.600000 ;
+ RECT 1041.790000 3000.240000 1042.790000 3000.720000 ;
+ RECT 1045.455000 3000.240000 1046.720000 3000.720000 ;
+ RECT 1135.620000 2978.480000 1136.720000 2978.960000 ;
+ RECT 1135.620000 2983.920000 1136.720000 2984.400000 ;
+ RECT 1135.620000 2989.360000 1136.720000 2989.840000 ;
+ RECT 1135.620000 2994.800000 1136.720000 2995.280000 ;
+ RECT 1090.620000 2978.480000 1091.720000 2978.960000 ;
+ RECT 1090.620000 2983.920000 1091.720000 2984.400000 ;
+ RECT 1090.620000 2989.360000 1091.720000 2989.840000 ;
+ RECT 1090.620000 2994.800000 1091.720000 2995.280000 ;
+ RECT 1135.620000 2956.720000 1136.720000 2957.200000 ;
+ RECT 1135.620000 2962.160000 1136.720000 2962.640000 ;
+ RECT 1135.620000 2967.600000 1136.720000 2968.080000 ;
+ RECT 1135.620000 2973.040000 1136.720000 2973.520000 ;
+ RECT 1090.620000 2956.720000 1091.720000 2957.200000 ;
+ RECT 1090.620000 2962.160000 1091.720000 2962.640000 ;
+ RECT 1090.620000 2967.600000 1091.720000 2968.080000 ;
+ RECT 1090.620000 2973.040000 1091.720000 2973.520000 ;
+ RECT 1041.790000 2994.800000 1042.790000 2995.280000 ;
+ RECT 1045.455000 2994.800000 1046.720000 2995.280000 ;
+ RECT 1041.790000 2989.360000 1042.790000 2989.840000 ;
+ RECT 1045.455000 2989.360000 1046.720000 2989.840000 ;
+ RECT 1041.790000 2983.920000 1042.790000 2984.400000 ;
+ RECT 1045.455000 2983.920000 1046.720000 2984.400000 ;
+ RECT 1041.790000 2978.480000 1042.790000 2978.960000 ;
+ RECT 1045.455000 2978.480000 1046.720000 2978.960000 ;
+ RECT 1041.790000 2973.040000 1042.790000 2973.520000 ;
+ RECT 1045.455000 2973.040000 1046.720000 2973.520000 ;
+ RECT 1041.790000 2962.160000 1042.790000 2962.640000 ;
+ RECT 1045.455000 2962.160000 1046.720000 2962.640000 ;
+ RECT 1041.790000 2967.600000 1042.790000 2968.080000 ;
+ RECT 1045.455000 2967.600000 1046.720000 2968.080000 ;
+ RECT 1041.790000 2956.720000 1042.790000 2957.200000 ;
+ RECT 1045.455000 2956.720000 1046.720000 2957.200000 ;
+ RECT 1180.620000 3049.200000 1181.720000 3049.680000 ;
+ RECT 1225.620000 3049.200000 1226.720000 3049.680000 ;
+ RECT 1238.430000 3049.200000 1239.430000 3049.680000 ;
+ RECT 1090.620000 3049.200000 1091.720000 3049.680000 ;
+ RECT 1135.620000 3049.200000 1136.720000 3049.680000 ;
+ RECT 1041.790000 3049.200000 1042.790000 3049.680000 ;
+ RECT 1045.455000 3049.200000 1046.720000 3049.680000 ;
+ RECT 1040.560000 3145.960000 1240.660000 3146.960000 ;
+ RECT 1040.560000 2950.390000 1240.660000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 2949.140000 1042.790000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 3148.400000 1042.790000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 2949.140000 1239.430000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 3148.400000 1239.430000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2950.390000 1041.560000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2950.390000 1240.660000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 3145.960000 1041.560000 3146.960000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 3145.960000 1240.660000 3146.960000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 2941.420000 1046.720000 2941.900000 ;
+ RECT 1045.455000 2930.540000 1046.720000 2931.020000 ;
+ RECT 1045.455000 2935.980000 1046.720000 2936.460000 ;
+ RECT 1045.455000 2925.100000 1046.720000 2925.580000 ;
+ RECT 1045.455000 2919.660000 1046.720000 2920.140000 ;
+ RECT 1045.455000 2914.220000 1046.720000 2914.700000 ;
+ RECT 1045.455000 2908.780000 1046.720000 2909.260000 ;
+ RECT 1045.455000 2903.340000 1046.720000 2903.820000 ;
+ RECT 1045.455000 2897.900000 1046.720000 2898.380000 ;
+ RECT 1045.455000 2887.020000 1046.720000 2887.500000 ;
+ RECT 1045.455000 2892.460000 1046.720000 2892.940000 ;
+ RECT 1045.455000 2881.580000 1046.720000 2882.060000 ;
+ RECT 1045.455000 2876.140000 1046.720000 2876.620000 ;
+ RECT 1045.455000 2870.700000 1046.720000 2871.180000 ;
+ RECT 1045.455000 2865.260000 1046.720000 2865.740000 ;
+ RECT 1045.455000 2859.820000 1046.720000 2860.300000 ;
+ RECT 1045.455000 2854.380000 1046.720000 2854.860000 ;
+ RECT 1045.455000 2843.500000 1046.720000 2843.980000 ;
+ RECT 1045.455000 2838.060000 1046.720000 2838.540000 ;
+ RECT 1045.455000 2832.620000 1046.720000 2833.100000 ;
+ RECT 1045.455000 2827.180000 1046.720000 2827.660000 ;
+ RECT 1045.455000 2821.740000 1046.720000 2822.220000 ;
+ RECT 1045.455000 2816.300000 1046.720000 2816.780000 ;
+ RECT 1045.455000 2805.420000 1046.720000 2805.900000 ;
+ RECT 1045.455000 2810.860000 1046.720000 2811.340000 ;
+ RECT 1045.455000 2799.980000 1046.720000 2800.460000 ;
+ RECT 1045.455000 2794.540000 1046.720000 2795.020000 ;
+ RECT 1045.455000 2789.100000 1046.720000 2789.580000 ;
+ RECT 1045.455000 2783.660000 1046.720000 2784.140000 ;
+ RECT 1045.455000 2778.220000 1046.720000 2778.700000 ;
+ RECT 1045.455000 2772.780000 1046.720000 2773.260000 ;
+ RECT 1045.455000 2761.900000 1046.720000 2762.380000 ;
+ RECT 1045.455000 2767.340000 1046.720000 2767.820000 ;
+ RECT 1045.455000 2756.460000 1046.720000 2756.940000 ;
+ RECT 1045.455000 2848.940000 1046.720000 2849.420000 ;
+ RECT 1225.620000 2750.130000 1226.720000 2946.700000 ;
+ RECT 1180.620000 2750.130000 1181.720000 2946.700000 ;
+ RECT 1238.430000 2748.880000 1239.430000 2949.140000 ;
+ RECT 1135.620000 2750.130000 1136.720000 2946.700000 ;
+ RECT 1090.620000 2750.130000 1091.720000 2946.700000 ;
+ RECT 1045.620000 2750.130000 1046.720000 2946.700000 ;
+ RECT 1041.790000 2748.880000 1042.790000 2949.140000 ;
+ LAYER met3 ;
+ RECT 1225.620000 2941.420000 1226.720000 2941.900000 ;
+ RECT 1238.430000 2941.420000 1239.430000 2941.900000 ;
+ RECT 1238.430000 2930.540000 1239.430000 2931.020000 ;
+ RECT 1238.430000 2925.100000 1239.430000 2925.580000 ;
+ RECT 1238.430000 2935.980000 1239.430000 2936.460000 ;
+ RECT 1225.620000 2935.980000 1226.720000 2936.460000 ;
+ RECT 1225.620000 2930.540000 1226.720000 2931.020000 ;
+ RECT 1225.620000 2925.100000 1226.720000 2925.580000 ;
+ RECT 1225.620000 2914.220000 1226.720000 2914.700000 ;
+ RECT 1225.620000 2919.660000 1226.720000 2920.140000 ;
+ RECT 1238.430000 2914.220000 1239.430000 2914.700000 ;
+ RECT 1238.430000 2919.660000 1239.430000 2920.140000 ;
+ RECT 1225.620000 2903.340000 1226.720000 2903.820000 ;
+ RECT 1225.620000 2908.780000 1226.720000 2909.260000 ;
+ RECT 1238.430000 2903.340000 1239.430000 2903.820000 ;
+ RECT 1238.430000 2908.780000 1239.430000 2909.260000 ;
+ RECT 1180.620000 2925.100000 1181.720000 2925.580000 ;
+ RECT 1180.620000 2930.540000 1181.720000 2931.020000 ;
+ RECT 1180.620000 2935.980000 1181.720000 2936.460000 ;
+ RECT 1180.620000 2941.420000 1181.720000 2941.900000 ;
+ RECT 1180.620000 2908.780000 1181.720000 2909.260000 ;
+ RECT 1180.620000 2903.340000 1181.720000 2903.820000 ;
+ RECT 1180.620000 2914.220000 1181.720000 2914.700000 ;
+ RECT 1180.620000 2919.660000 1181.720000 2920.140000 ;
+ RECT 1238.430000 2892.460000 1239.430000 2892.940000 ;
+ RECT 1238.430000 2887.020000 1239.430000 2887.500000 ;
+ RECT 1238.430000 2897.900000 1239.430000 2898.380000 ;
+ RECT 1225.620000 2897.900000 1226.720000 2898.380000 ;
+ RECT 1225.620000 2892.460000 1226.720000 2892.940000 ;
+ RECT 1225.620000 2887.020000 1226.720000 2887.500000 ;
+ RECT 1225.620000 2876.140000 1226.720000 2876.620000 ;
+ RECT 1225.620000 2881.580000 1226.720000 2882.060000 ;
+ RECT 1238.430000 2876.140000 1239.430000 2876.620000 ;
+ RECT 1238.430000 2881.580000 1239.430000 2882.060000 ;
+ RECT 1238.430000 2865.260000 1239.430000 2865.740000 ;
+ RECT 1238.430000 2870.700000 1239.430000 2871.180000 ;
+ RECT 1225.620000 2870.700000 1226.720000 2871.180000 ;
+ RECT 1225.620000 2865.260000 1226.720000 2865.740000 ;
+ RECT 1225.620000 2854.380000 1226.720000 2854.860000 ;
+ RECT 1225.620000 2859.820000 1226.720000 2860.300000 ;
+ RECT 1238.430000 2854.380000 1239.430000 2854.860000 ;
+ RECT 1238.430000 2859.820000 1239.430000 2860.300000 ;
+ RECT 1180.620000 2876.140000 1181.720000 2876.620000 ;
+ RECT 1180.620000 2881.580000 1181.720000 2882.060000 ;
+ RECT 1180.620000 2887.020000 1181.720000 2887.500000 ;
+ RECT 1180.620000 2892.460000 1181.720000 2892.940000 ;
+ RECT 1180.620000 2897.900000 1181.720000 2898.380000 ;
+ RECT 1180.620000 2854.380000 1181.720000 2854.860000 ;
+ RECT 1180.620000 2859.820000 1181.720000 2860.300000 ;
+ RECT 1180.620000 2865.260000 1181.720000 2865.740000 ;
+ RECT 1180.620000 2870.700000 1181.720000 2871.180000 ;
+ RECT 1135.620000 2930.540000 1136.720000 2931.020000 ;
+ RECT 1135.620000 2925.100000 1136.720000 2925.580000 ;
+ RECT 1135.620000 2935.980000 1136.720000 2936.460000 ;
+ RECT 1135.620000 2941.420000 1136.720000 2941.900000 ;
+ RECT 1090.620000 2925.100000 1091.720000 2925.580000 ;
+ RECT 1090.620000 2930.540000 1091.720000 2931.020000 ;
+ RECT 1090.620000 2935.980000 1091.720000 2936.460000 ;
+ RECT 1090.620000 2941.420000 1091.720000 2941.900000 ;
+ RECT 1135.620000 2903.340000 1136.720000 2903.820000 ;
+ RECT 1135.620000 2908.780000 1136.720000 2909.260000 ;
+ RECT 1135.620000 2914.220000 1136.720000 2914.700000 ;
+ RECT 1135.620000 2919.660000 1136.720000 2920.140000 ;
+ RECT 1090.620000 2903.340000 1091.720000 2903.820000 ;
+ RECT 1090.620000 2908.780000 1091.720000 2909.260000 ;
+ RECT 1090.620000 2914.220000 1091.720000 2914.700000 ;
+ RECT 1090.620000 2919.660000 1091.720000 2920.140000 ;
+ RECT 1041.790000 2941.420000 1042.790000 2941.900000 ;
+ RECT 1045.455000 2941.420000 1046.720000 2941.900000 ;
+ RECT 1041.790000 2930.540000 1042.790000 2931.020000 ;
+ RECT 1045.455000 2930.540000 1046.720000 2931.020000 ;
+ RECT 1041.790000 2935.980000 1042.790000 2936.460000 ;
+ RECT 1045.455000 2935.980000 1046.720000 2936.460000 ;
+ RECT 1041.790000 2925.100000 1042.790000 2925.580000 ;
+ RECT 1045.455000 2925.100000 1046.720000 2925.580000 ;
+ RECT 1041.790000 2919.660000 1042.790000 2920.140000 ;
+ RECT 1045.455000 2919.660000 1046.720000 2920.140000 ;
+ RECT 1041.790000 2914.220000 1042.790000 2914.700000 ;
+ RECT 1045.455000 2914.220000 1046.720000 2914.700000 ;
+ RECT 1041.790000 2908.780000 1042.790000 2909.260000 ;
+ RECT 1045.455000 2908.780000 1046.720000 2909.260000 ;
+ RECT 1041.790000 2903.340000 1042.790000 2903.820000 ;
+ RECT 1045.455000 2903.340000 1046.720000 2903.820000 ;
+ RECT 1135.620000 2876.140000 1136.720000 2876.620000 ;
+ RECT 1135.620000 2881.580000 1136.720000 2882.060000 ;
+ RECT 1135.620000 2887.020000 1136.720000 2887.500000 ;
+ RECT 1135.620000 2892.460000 1136.720000 2892.940000 ;
+ RECT 1135.620000 2897.900000 1136.720000 2898.380000 ;
+ RECT 1090.620000 2876.140000 1091.720000 2876.620000 ;
+ RECT 1090.620000 2881.580000 1091.720000 2882.060000 ;
+ RECT 1090.620000 2887.020000 1091.720000 2887.500000 ;
+ RECT 1090.620000 2892.460000 1091.720000 2892.940000 ;
+ RECT 1090.620000 2897.900000 1091.720000 2898.380000 ;
+ RECT 1135.620000 2854.380000 1136.720000 2854.860000 ;
+ RECT 1135.620000 2859.820000 1136.720000 2860.300000 ;
+ RECT 1135.620000 2865.260000 1136.720000 2865.740000 ;
+ RECT 1135.620000 2870.700000 1136.720000 2871.180000 ;
+ RECT 1090.620000 2854.380000 1091.720000 2854.860000 ;
+ RECT 1090.620000 2859.820000 1091.720000 2860.300000 ;
+ RECT 1090.620000 2865.260000 1091.720000 2865.740000 ;
+ RECT 1090.620000 2870.700000 1091.720000 2871.180000 ;
+ RECT 1041.790000 2897.900000 1042.790000 2898.380000 ;
+ RECT 1045.455000 2897.900000 1046.720000 2898.380000 ;
+ RECT 1041.790000 2887.020000 1042.790000 2887.500000 ;
+ RECT 1045.455000 2887.020000 1046.720000 2887.500000 ;
+ RECT 1041.790000 2892.460000 1042.790000 2892.940000 ;
+ RECT 1045.455000 2892.460000 1046.720000 2892.940000 ;
+ RECT 1041.790000 2881.580000 1042.790000 2882.060000 ;
+ RECT 1045.455000 2881.580000 1046.720000 2882.060000 ;
+ RECT 1041.790000 2876.140000 1042.790000 2876.620000 ;
+ RECT 1045.455000 2876.140000 1046.720000 2876.620000 ;
+ RECT 1041.790000 2870.700000 1042.790000 2871.180000 ;
+ RECT 1045.455000 2870.700000 1046.720000 2871.180000 ;
+ RECT 1041.790000 2865.260000 1042.790000 2865.740000 ;
+ RECT 1045.455000 2865.260000 1046.720000 2865.740000 ;
+ RECT 1041.790000 2859.820000 1042.790000 2860.300000 ;
+ RECT 1045.455000 2859.820000 1046.720000 2860.300000 ;
+ RECT 1041.790000 2854.380000 1042.790000 2854.860000 ;
+ RECT 1045.455000 2854.380000 1046.720000 2854.860000 ;
+ RECT 1225.620000 2838.060000 1226.720000 2838.540000 ;
+ RECT 1225.620000 2843.500000 1226.720000 2843.980000 ;
+ RECT 1238.430000 2838.060000 1239.430000 2838.540000 ;
+ RECT 1238.430000 2843.500000 1239.430000 2843.980000 ;
+ RECT 1238.430000 2827.180000 1239.430000 2827.660000 ;
+ RECT 1238.430000 2832.620000 1239.430000 2833.100000 ;
+ RECT 1225.620000 2832.620000 1226.720000 2833.100000 ;
+ RECT 1225.620000 2827.180000 1226.720000 2827.660000 ;
+ RECT 1225.620000 2816.300000 1226.720000 2816.780000 ;
+ RECT 1225.620000 2821.740000 1226.720000 2822.220000 ;
+ RECT 1238.430000 2816.300000 1239.430000 2816.780000 ;
+ RECT 1238.430000 2821.740000 1239.430000 2822.220000 ;
+ RECT 1238.430000 2805.420000 1239.430000 2805.900000 ;
+ RECT 1238.430000 2799.980000 1239.430000 2800.460000 ;
+ RECT 1238.430000 2810.860000 1239.430000 2811.340000 ;
+ RECT 1225.620000 2810.860000 1226.720000 2811.340000 ;
+ RECT 1225.620000 2805.420000 1226.720000 2805.900000 ;
+ RECT 1225.620000 2799.980000 1226.720000 2800.460000 ;
+ RECT 1180.620000 2827.180000 1181.720000 2827.660000 ;
+ RECT 1180.620000 2832.620000 1181.720000 2833.100000 ;
+ RECT 1180.620000 2838.060000 1181.720000 2838.540000 ;
+ RECT 1180.620000 2843.500000 1181.720000 2843.980000 ;
+ RECT 1180.620000 2799.980000 1181.720000 2800.460000 ;
+ RECT 1180.620000 2805.420000 1181.720000 2805.900000 ;
+ RECT 1180.620000 2810.860000 1181.720000 2811.340000 ;
+ RECT 1180.620000 2816.300000 1181.720000 2816.780000 ;
+ RECT 1180.620000 2821.740000 1181.720000 2822.220000 ;
+ RECT 1225.620000 2789.100000 1226.720000 2789.580000 ;
+ RECT 1225.620000 2794.540000 1226.720000 2795.020000 ;
+ RECT 1238.430000 2789.100000 1239.430000 2789.580000 ;
+ RECT 1238.430000 2794.540000 1239.430000 2795.020000 ;
+ RECT 1225.620000 2778.220000 1226.720000 2778.700000 ;
+ RECT 1225.620000 2783.660000 1226.720000 2784.140000 ;
+ RECT 1238.430000 2778.220000 1239.430000 2778.700000 ;
+ RECT 1238.430000 2783.660000 1239.430000 2784.140000 ;
+ RECT 1238.430000 2767.340000 1239.430000 2767.820000 ;
+ RECT 1238.430000 2761.900000 1239.430000 2762.380000 ;
+ RECT 1238.430000 2772.780000 1239.430000 2773.260000 ;
+ RECT 1225.620000 2772.780000 1226.720000 2773.260000 ;
+ RECT 1225.620000 2767.340000 1226.720000 2767.820000 ;
+ RECT 1225.620000 2761.900000 1226.720000 2762.380000 ;
+ RECT 1225.620000 2756.460000 1226.720000 2756.940000 ;
+ RECT 1238.430000 2756.460000 1239.430000 2756.940000 ;
+ RECT 1180.620000 2778.220000 1181.720000 2778.700000 ;
+ RECT 1180.620000 2783.660000 1181.720000 2784.140000 ;
+ RECT 1180.620000 2789.100000 1181.720000 2789.580000 ;
+ RECT 1180.620000 2794.540000 1181.720000 2795.020000 ;
+ RECT 1180.620000 2756.460000 1181.720000 2756.940000 ;
+ RECT 1180.620000 2761.900000 1181.720000 2762.380000 ;
+ RECT 1180.620000 2767.340000 1181.720000 2767.820000 ;
+ RECT 1180.620000 2772.780000 1181.720000 2773.260000 ;
+ RECT 1135.620000 2827.180000 1136.720000 2827.660000 ;
+ RECT 1135.620000 2832.620000 1136.720000 2833.100000 ;
+ RECT 1135.620000 2838.060000 1136.720000 2838.540000 ;
+ RECT 1135.620000 2843.500000 1136.720000 2843.980000 ;
+ RECT 1090.620000 2827.180000 1091.720000 2827.660000 ;
+ RECT 1090.620000 2832.620000 1091.720000 2833.100000 ;
+ RECT 1090.620000 2838.060000 1091.720000 2838.540000 ;
+ RECT 1090.620000 2843.500000 1091.720000 2843.980000 ;
+ RECT 1135.620000 2799.980000 1136.720000 2800.460000 ;
+ RECT 1135.620000 2805.420000 1136.720000 2805.900000 ;
+ RECT 1135.620000 2810.860000 1136.720000 2811.340000 ;
+ RECT 1135.620000 2816.300000 1136.720000 2816.780000 ;
+ RECT 1135.620000 2821.740000 1136.720000 2822.220000 ;
+ RECT 1090.620000 2799.980000 1091.720000 2800.460000 ;
+ RECT 1090.620000 2805.420000 1091.720000 2805.900000 ;
+ RECT 1090.620000 2810.860000 1091.720000 2811.340000 ;
+ RECT 1090.620000 2816.300000 1091.720000 2816.780000 ;
+ RECT 1090.620000 2821.740000 1091.720000 2822.220000 ;
+ RECT 1041.790000 2843.500000 1042.790000 2843.980000 ;
+ RECT 1045.455000 2843.500000 1046.720000 2843.980000 ;
+ RECT 1041.790000 2838.060000 1042.790000 2838.540000 ;
+ RECT 1045.455000 2838.060000 1046.720000 2838.540000 ;
+ RECT 1041.790000 2832.620000 1042.790000 2833.100000 ;
+ RECT 1045.455000 2832.620000 1046.720000 2833.100000 ;
+ RECT 1041.790000 2827.180000 1042.790000 2827.660000 ;
+ RECT 1045.455000 2827.180000 1046.720000 2827.660000 ;
+ RECT 1041.790000 2821.740000 1042.790000 2822.220000 ;
+ RECT 1045.455000 2821.740000 1046.720000 2822.220000 ;
+ RECT 1041.790000 2816.300000 1042.790000 2816.780000 ;
+ RECT 1045.455000 2816.300000 1046.720000 2816.780000 ;
+ RECT 1041.790000 2805.420000 1042.790000 2805.900000 ;
+ RECT 1045.455000 2805.420000 1046.720000 2805.900000 ;
+ RECT 1041.790000 2810.860000 1042.790000 2811.340000 ;
+ RECT 1045.455000 2810.860000 1046.720000 2811.340000 ;
+ RECT 1041.790000 2799.980000 1042.790000 2800.460000 ;
+ RECT 1045.455000 2799.980000 1046.720000 2800.460000 ;
+ RECT 1135.620000 2778.220000 1136.720000 2778.700000 ;
+ RECT 1135.620000 2783.660000 1136.720000 2784.140000 ;
+ RECT 1135.620000 2789.100000 1136.720000 2789.580000 ;
+ RECT 1135.620000 2794.540000 1136.720000 2795.020000 ;
+ RECT 1090.620000 2778.220000 1091.720000 2778.700000 ;
+ RECT 1090.620000 2783.660000 1091.720000 2784.140000 ;
+ RECT 1090.620000 2789.100000 1091.720000 2789.580000 ;
+ RECT 1090.620000 2794.540000 1091.720000 2795.020000 ;
+ RECT 1135.620000 2756.460000 1136.720000 2756.940000 ;
+ RECT 1135.620000 2761.900000 1136.720000 2762.380000 ;
+ RECT 1135.620000 2767.340000 1136.720000 2767.820000 ;
+ RECT 1135.620000 2772.780000 1136.720000 2773.260000 ;
+ RECT 1090.620000 2756.460000 1091.720000 2756.940000 ;
+ RECT 1090.620000 2761.900000 1091.720000 2762.380000 ;
+ RECT 1090.620000 2767.340000 1091.720000 2767.820000 ;
+ RECT 1090.620000 2772.780000 1091.720000 2773.260000 ;
+ RECT 1041.790000 2794.540000 1042.790000 2795.020000 ;
+ RECT 1045.455000 2794.540000 1046.720000 2795.020000 ;
+ RECT 1041.790000 2789.100000 1042.790000 2789.580000 ;
+ RECT 1045.455000 2789.100000 1046.720000 2789.580000 ;
+ RECT 1041.790000 2783.660000 1042.790000 2784.140000 ;
+ RECT 1045.455000 2783.660000 1046.720000 2784.140000 ;
+ RECT 1041.790000 2778.220000 1042.790000 2778.700000 ;
+ RECT 1045.455000 2778.220000 1046.720000 2778.700000 ;
+ RECT 1041.790000 2772.780000 1042.790000 2773.260000 ;
+ RECT 1045.455000 2772.780000 1046.720000 2773.260000 ;
+ RECT 1041.790000 2761.900000 1042.790000 2762.380000 ;
+ RECT 1045.455000 2761.900000 1046.720000 2762.380000 ;
+ RECT 1041.790000 2767.340000 1042.790000 2767.820000 ;
+ RECT 1045.455000 2767.340000 1046.720000 2767.820000 ;
+ RECT 1041.790000 2756.460000 1042.790000 2756.940000 ;
+ RECT 1045.455000 2756.460000 1046.720000 2756.940000 ;
+ RECT 1180.620000 2848.940000 1181.720000 2849.420000 ;
+ RECT 1225.620000 2848.940000 1226.720000 2849.420000 ;
+ RECT 1238.430000 2848.940000 1239.430000 2849.420000 ;
+ RECT 1090.620000 2848.940000 1091.720000 2849.420000 ;
+ RECT 1135.620000 2848.940000 1136.720000 2849.420000 ;
+ RECT 1041.790000 2848.940000 1042.790000 2849.420000 ;
+ RECT 1045.455000 2848.940000 1046.720000 2849.420000 ;
+ RECT 1040.560000 2945.700000 1240.660000 2946.700000 ;
+ RECT 1040.560000 2750.130000 1240.660000 2751.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 2748.880000 1042.790000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 2948.140000 1042.790000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 2748.880000 1239.430000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 2948.140000 1239.430000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2750.130000 1041.560000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2750.130000 1240.660000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2945.700000 1041.560000 2946.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2945.700000 1240.660000 2946.700000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 2741.160000 1046.720000 2741.640000 ;
+ RECT 1045.455000 2730.280000 1046.720000 2730.760000 ;
+ RECT 1045.455000 2735.720000 1046.720000 2736.200000 ;
+ RECT 1045.455000 2724.840000 1046.720000 2725.320000 ;
+ RECT 1045.455000 2719.400000 1046.720000 2719.880000 ;
+ RECT 1045.455000 2713.960000 1046.720000 2714.440000 ;
+ RECT 1045.455000 2708.520000 1046.720000 2709.000000 ;
+ RECT 1045.455000 2703.080000 1046.720000 2703.560000 ;
+ RECT 1045.455000 2697.640000 1046.720000 2698.120000 ;
+ RECT 1045.455000 2686.760000 1046.720000 2687.240000 ;
+ RECT 1045.455000 2692.200000 1046.720000 2692.680000 ;
+ RECT 1045.455000 2681.320000 1046.720000 2681.800000 ;
+ RECT 1045.455000 2675.880000 1046.720000 2676.360000 ;
+ RECT 1045.455000 2670.440000 1046.720000 2670.920000 ;
+ RECT 1045.455000 2665.000000 1046.720000 2665.480000 ;
+ RECT 1045.455000 2659.560000 1046.720000 2660.040000 ;
+ RECT 1045.455000 2654.120000 1046.720000 2654.600000 ;
+ RECT 1045.455000 2643.240000 1046.720000 2643.720000 ;
+ RECT 1045.455000 2637.800000 1046.720000 2638.280000 ;
+ RECT 1045.455000 2632.360000 1046.720000 2632.840000 ;
+ RECT 1045.455000 2626.920000 1046.720000 2627.400000 ;
+ RECT 1045.455000 2621.480000 1046.720000 2621.960000 ;
+ RECT 1045.455000 2616.040000 1046.720000 2616.520000 ;
+ RECT 1045.455000 2605.160000 1046.720000 2605.640000 ;
+ RECT 1045.455000 2610.600000 1046.720000 2611.080000 ;
+ RECT 1045.455000 2599.720000 1046.720000 2600.200000 ;
+ RECT 1045.455000 2594.280000 1046.720000 2594.760000 ;
+ RECT 1045.455000 2588.840000 1046.720000 2589.320000 ;
+ RECT 1045.455000 2583.400000 1046.720000 2583.880000 ;
+ RECT 1045.455000 2577.960000 1046.720000 2578.440000 ;
+ RECT 1045.455000 2572.520000 1046.720000 2573.000000 ;
+ RECT 1045.455000 2561.640000 1046.720000 2562.120000 ;
+ RECT 1045.455000 2567.080000 1046.720000 2567.560000 ;
+ RECT 1045.455000 2556.200000 1046.720000 2556.680000 ;
+ RECT 1045.455000 2648.680000 1046.720000 2649.160000 ;
+ RECT 1225.620000 2549.870000 1226.720000 2746.440000 ;
+ RECT 1180.620000 2549.870000 1181.720000 2746.440000 ;
+ RECT 1238.430000 2548.620000 1239.430000 2748.880000 ;
+ RECT 1135.620000 2549.870000 1136.720000 2746.440000 ;
+ RECT 1090.620000 2549.870000 1091.720000 2746.440000 ;
+ RECT 1045.620000 2549.870000 1046.720000 2746.440000 ;
+ RECT 1041.790000 2548.620000 1042.790000 2748.880000 ;
+ LAYER met3 ;
+ RECT 1225.620000 2741.160000 1226.720000 2741.640000 ;
+ RECT 1238.430000 2741.160000 1239.430000 2741.640000 ;
+ RECT 1238.430000 2730.280000 1239.430000 2730.760000 ;
+ RECT 1238.430000 2724.840000 1239.430000 2725.320000 ;
+ RECT 1238.430000 2735.720000 1239.430000 2736.200000 ;
+ RECT 1225.620000 2735.720000 1226.720000 2736.200000 ;
+ RECT 1225.620000 2730.280000 1226.720000 2730.760000 ;
+ RECT 1225.620000 2724.840000 1226.720000 2725.320000 ;
+ RECT 1225.620000 2713.960000 1226.720000 2714.440000 ;
+ RECT 1225.620000 2719.400000 1226.720000 2719.880000 ;
+ RECT 1238.430000 2713.960000 1239.430000 2714.440000 ;
+ RECT 1238.430000 2719.400000 1239.430000 2719.880000 ;
+ RECT 1225.620000 2703.080000 1226.720000 2703.560000 ;
+ RECT 1225.620000 2708.520000 1226.720000 2709.000000 ;
+ RECT 1238.430000 2703.080000 1239.430000 2703.560000 ;
+ RECT 1238.430000 2708.520000 1239.430000 2709.000000 ;
+ RECT 1180.620000 2724.840000 1181.720000 2725.320000 ;
+ RECT 1180.620000 2730.280000 1181.720000 2730.760000 ;
+ RECT 1180.620000 2735.720000 1181.720000 2736.200000 ;
+ RECT 1180.620000 2741.160000 1181.720000 2741.640000 ;
+ RECT 1180.620000 2708.520000 1181.720000 2709.000000 ;
+ RECT 1180.620000 2703.080000 1181.720000 2703.560000 ;
+ RECT 1180.620000 2713.960000 1181.720000 2714.440000 ;
+ RECT 1180.620000 2719.400000 1181.720000 2719.880000 ;
+ RECT 1238.430000 2692.200000 1239.430000 2692.680000 ;
+ RECT 1238.430000 2686.760000 1239.430000 2687.240000 ;
+ RECT 1238.430000 2697.640000 1239.430000 2698.120000 ;
+ RECT 1225.620000 2697.640000 1226.720000 2698.120000 ;
+ RECT 1225.620000 2692.200000 1226.720000 2692.680000 ;
+ RECT 1225.620000 2686.760000 1226.720000 2687.240000 ;
+ RECT 1225.620000 2675.880000 1226.720000 2676.360000 ;
+ RECT 1225.620000 2681.320000 1226.720000 2681.800000 ;
+ RECT 1238.430000 2675.880000 1239.430000 2676.360000 ;
+ RECT 1238.430000 2681.320000 1239.430000 2681.800000 ;
+ RECT 1238.430000 2665.000000 1239.430000 2665.480000 ;
+ RECT 1238.430000 2670.440000 1239.430000 2670.920000 ;
+ RECT 1225.620000 2670.440000 1226.720000 2670.920000 ;
+ RECT 1225.620000 2665.000000 1226.720000 2665.480000 ;
+ RECT 1225.620000 2654.120000 1226.720000 2654.600000 ;
+ RECT 1225.620000 2659.560000 1226.720000 2660.040000 ;
+ RECT 1238.430000 2654.120000 1239.430000 2654.600000 ;
+ RECT 1238.430000 2659.560000 1239.430000 2660.040000 ;
+ RECT 1180.620000 2675.880000 1181.720000 2676.360000 ;
+ RECT 1180.620000 2681.320000 1181.720000 2681.800000 ;
+ RECT 1180.620000 2686.760000 1181.720000 2687.240000 ;
+ RECT 1180.620000 2692.200000 1181.720000 2692.680000 ;
+ RECT 1180.620000 2697.640000 1181.720000 2698.120000 ;
+ RECT 1180.620000 2654.120000 1181.720000 2654.600000 ;
+ RECT 1180.620000 2659.560000 1181.720000 2660.040000 ;
+ RECT 1180.620000 2665.000000 1181.720000 2665.480000 ;
+ RECT 1180.620000 2670.440000 1181.720000 2670.920000 ;
+ RECT 1135.620000 2730.280000 1136.720000 2730.760000 ;
+ RECT 1135.620000 2724.840000 1136.720000 2725.320000 ;
+ RECT 1135.620000 2735.720000 1136.720000 2736.200000 ;
+ RECT 1135.620000 2741.160000 1136.720000 2741.640000 ;
+ RECT 1090.620000 2724.840000 1091.720000 2725.320000 ;
+ RECT 1090.620000 2730.280000 1091.720000 2730.760000 ;
+ RECT 1090.620000 2735.720000 1091.720000 2736.200000 ;
+ RECT 1090.620000 2741.160000 1091.720000 2741.640000 ;
+ RECT 1135.620000 2703.080000 1136.720000 2703.560000 ;
+ RECT 1135.620000 2708.520000 1136.720000 2709.000000 ;
+ RECT 1135.620000 2713.960000 1136.720000 2714.440000 ;
+ RECT 1135.620000 2719.400000 1136.720000 2719.880000 ;
+ RECT 1090.620000 2703.080000 1091.720000 2703.560000 ;
+ RECT 1090.620000 2708.520000 1091.720000 2709.000000 ;
+ RECT 1090.620000 2713.960000 1091.720000 2714.440000 ;
+ RECT 1090.620000 2719.400000 1091.720000 2719.880000 ;
+ RECT 1041.790000 2741.160000 1042.790000 2741.640000 ;
+ RECT 1045.455000 2741.160000 1046.720000 2741.640000 ;
+ RECT 1041.790000 2730.280000 1042.790000 2730.760000 ;
+ RECT 1045.455000 2730.280000 1046.720000 2730.760000 ;
+ RECT 1041.790000 2735.720000 1042.790000 2736.200000 ;
+ RECT 1045.455000 2735.720000 1046.720000 2736.200000 ;
+ RECT 1041.790000 2724.840000 1042.790000 2725.320000 ;
+ RECT 1045.455000 2724.840000 1046.720000 2725.320000 ;
+ RECT 1041.790000 2719.400000 1042.790000 2719.880000 ;
+ RECT 1045.455000 2719.400000 1046.720000 2719.880000 ;
+ RECT 1041.790000 2713.960000 1042.790000 2714.440000 ;
+ RECT 1045.455000 2713.960000 1046.720000 2714.440000 ;
+ RECT 1041.790000 2708.520000 1042.790000 2709.000000 ;
+ RECT 1045.455000 2708.520000 1046.720000 2709.000000 ;
+ RECT 1041.790000 2703.080000 1042.790000 2703.560000 ;
+ RECT 1045.455000 2703.080000 1046.720000 2703.560000 ;
+ RECT 1135.620000 2675.880000 1136.720000 2676.360000 ;
+ RECT 1135.620000 2681.320000 1136.720000 2681.800000 ;
+ RECT 1135.620000 2686.760000 1136.720000 2687.240000 ;
+ RECT 1135.620000 2692.200000 1136.720000 2692.680000 ;
+ RECT 1135.620000 2697.640000 1136.720000 2698.120000 ;
+ RECT 1090.620000 2675.880000 1091.720000 2676.360000 ;
+ RECT 1090.620000 2681.320000 1091.720000 2681.800000 ;
+ RECT 1090.620000 2686.760000 1091.720000 2687.240000 ;
+ RECT 1090.620000 2692.200000 1091.720000 2692.680000 ;
+ RECT 1090.620000 2697.640000 1091.720000 2698.120000 ;
+ RECT 1135.620000 2654.120000 1136.720000 2654.600000 ;
+ RECT 1135.620000 2659.560000 1136.720000 2660.040000 ;
+ RECT 1135.620000 2665.000000 1136.720000 2665.480000 ;
+ RECT 1135.620000 2670.440000 1136.720000 2670.920000 ;
+ RECT 1090.620000 2654.120000 1091.720000 2654.600000 ;
+ RECT 1090.620000 2659.560000 1091.720000 2660.040000 ;
+ RECT 1090.620000 2665.000000 1091.720000 2665.480000 ;
+ RECT 1090.620000 2670.440000 1091.720000 2670.920000 ;
+ RECT 1041.790000 2697.640000 1042.790000 2698.120000 ;
+ RECT 1045.455000 2697.640000 1046.720000 2698.120000 ;
+ RECT 1041.790000 2686.760000 1042.790000 2687.240000 ;
+ RECT 1045.455000 2686.760000 1046.720000 2687.240000 ;
+ RECT 1041.790000 2692.200000 1042.790000 2692.680000 ;
+ RECT 1045.455000 2692.200000 1046.720000 2692.680000 ;
+ RECT 1041.790000 2681.320000 1042.790000 2681.800000 ;
+ RECT 1045.455000 2681.320000 1046.720000 2681.800000 ;
+ RECT 1041.790000 2675.880000 1042.790000 2676.360000 ;
+ RECT 1045.455000 2675.880000 1046.720000 2676.360000 ;
+ RECT 1041.790000 2670.440000 1042.790000 2670.920000 ;
+ RECT 1045.455000 2670.440000 1046.720000 2670.920000 ;
+ RECT 1041.790000 2665.000000 1042.790000 2665.480000 ;
+ RECT 1045.455000 2665.000000 1046.720000 2665.480000 ;
+ RECT 1041.790000 2659.560000 1042.790000 2660.040000 ;
+ RECT 1045.455000 2659.560000 1046.720000 2660.040000 ;
+ RECT 1041.790000 2654.120000 1042.790000 2654.600000 ;
+ RECT 1045.455000 2654.120000 1046.720000 2654.600000 ;
+ RECT 1225.620000 2637.800000 1226.720000 2638.280000 ;
+ RECT 1225.620000 2643.240000 1226.720000 2643.720000 ;
+ RECT 1238.430000 2637.800000 1239.430000 2638.280000 ;
+ RECT 1238.430000 2643.240000 1239.430000 2643.720000 ;
+ RECT 1238.430000 2626.920000 1239.430000 2627.400000 ;
+ RECT 1238.430000 2632.360000 1239.430000 2632.840000 ;
+ RECT 1225.620000 2632.360000 1226.720000 2632.840000 ;
+ RECT 1225.620000 2626.920000 1226.720000 2627.400000 ;
+ RECT 1225.620000 2616.040000 1226.720000 2616.520000 ;
+ RECT 1225.620000 2621.480000 1226.720000 2621.960000 ;
+ RECT 1238.430000 2616.040000 1239.430000 2616.520000 ;
+ RECT 1238.430000 2621.480000 1239.430000 2621.960000 ;
+ RECT 1238.430000 2605.160000 1239.430000 2605.640000 ;
+ RECT 1238.430000 2599.720000 1239.430000 2600.200000 ;
+ RECT 1238.430000 2610.600000 1239.430000 2611.080000 ;
+ RECT 1225.620000 2610.600000 1226.720000 2611.080000 ;
+ RECT 1225.620000 2605.160000 1226.720000 2605.640000 ;
+ RECT 1225.620000 2599.720000 1226.720000 2600.200000 ;
+ RECT 1180.620000 2626.920000 1181.720000 2627.400000 ;
+ RECT 1180.620000 2632.360000 1181.720000 2632.840000 ;
+ RECT 1180.620000 2637.800000 1181.720000 2638.280000 ;
+ RECT 1180.620000 2643.240000 1181.720000 2643.720000 ;
+ RECT 1180.620000 2599.720000 1181.720000 2600.200000 ;
+ RECT 1180.620000 2605.160000 1181.720000 2605.640000 ;
+ RECT 1180.620000 2610.600000 1181.720000 2611.080000 ;
+ RECT 1180.620000 2616.040000 1181.720000 2616.520000 ;
+ RECT 1180.620000 2621.480000 1181.720000 2621.960000 ;
+ RECT 1225.620000 2588.840000 1226.720000 2589.320000 ;
+ RECT 1225.620000 2594.280000 1226.720000 2594.760000 ;
+ RECT 1238.430000 2588.840000 1239.430000 2589.320000 ;
+ RECT 1238.430000 2594.280000 1239.430000 2594.760000 ;
+ RECT 1225.620000 2577.960000 1226.720000 2578.440000 ;
+ RECT 1225.620000 2583.400000 1226.720000 2583.880000 ;
+ RECT 1238.430000 2577.960000 1239.430000 2578.440000 ;
+ RECT 1238.430000 2583.400000 1239.430000 2583.880000 ;
+ RECT 1238.430000 2567.080000 1239.430000 2567.560000 ;
+ RECT 1238.430000 2561.640000 1239.430000 2562.120000 ;
+ RECT 1238.430000 2572.520000 1239.430000 2573.000000 ;
+ RECT 1225.620000 2572.520000 1226.720000 2573.000000 ;
+ RECT 1225.620000 2567.080000 1226.720000 2567.560000 ;
+ RECT 1225.620000 2561.640000 1226.720000 2562.120000 ;
+ RECT 1225.620000 2556.200000 1226.720000 2556.680000 ;
+ RECT 1238.430000 2556.200000 1239.430000 2556.680000 ;
+ RECT 1180.620000 2577.960000 1181.720000 2578.440000 ;
+ RECT 1180.620000 2583.400000 1181.720000 2583.880000 ;
+ RECT 1180.620000 2588.840000 1181.720000 2589.320000 ;
+ RECT 1180.620000 2594.280000 1181.720000 2594.760000 ;
+ RECT 1180.620000 2556.200000 1181.720000 2556.680000 ;
+ RECT 1180.620000 2561.640000 1181.720000 2562.120000 ;
+ RECT 1180.620000 2567.080000 1181.720000 2567.560000 ;
+ RECT 1180.620000 2572.520000 1181.720000 2573.000000 ;
+ RECT 1135.620000 2626.920000 1136.720000 2627.400000 ;
+ RECT 1135.620000 2632.360000 1136.720000 2632.840000 ;
+ RECT 1135.620000 2637.800000 1136.720000 2638.280000 ;
+ RECT 1135.620000 2643.240000 1136.720000 2643.720000 ;
+ RECT 1090.620000 2626.920000 1091.720000 2627.400000 ;
+ RECT 1090.620000 2632.360000 1091.720000 2632.840000 ;
+ RECT 1090.620000 2637.800000 1091.720000 2638.280000 ;
+ RECT 1090.620000 2643.240000 1091.720000 2643.720000 ;
+ RECT 1135.620000 2599.720000 1136.720000 2600.200000 ;
+ RECT 1135.620000 2605.160000 1136.720000 2605.640000 ;
+ RECT 1135.620000 2610.600000 1136.720000 2611.080000 ;
+ RECT 1135.620000 2616.040000 1136.720000 2616.520000 ;
+ RECT 1135.620000 2621.480000 1136.720000 2621.960000 ;
+ RECT 1090.620000 2599.720000 1091.720000 2600.200000 ;
+ RECT 1090.620000 2605.160000 1091.720000 2605.640000 ;
+ RECT 1090.620000 2610.600000 1091.720000 2611.080000 ;
+ RECT 1090.620000 2616.040000 1091.720000 2616.520000 ;
+ RECT 1090.620000 2621.480000 1091.720000 2621.960000 ;
+ RECT 1041.790000 2643.240000 1042.790000 2643.720000 ;
+ RECT 1045.455000 2643.240000 1046.720000 2643.720000 ;
+ RECT 1041.790000 2637.800000 1042.790000 2638.280000 ;
+ RECT 1045.455000 2637.800000 1046.720000 2638.280000 ;
+ RECT 1041.790000 2632.360000 1042.790000 2632.840000 ;
+ RECT 1045.455000 2632.360000 1046.720000 2632.840000 ;
+ RECT 1041.790000 2626.920000 1042.790000 2627.400000 ;
+ RECT 1045.455000 2626.920000 1046.720000 2627.400000 ;
+ RECT 1041.790000 2621.480000 1042.790000 2621.960000 ;
+ RECT 1045.455000 2621.480000 1046.720000 2621.960000 ;
+ RECT 1041.790000 2616.040000 1042.790000 2616.520000 ;
+ RECT 1045.455000 2616.040000 1046.720000 2616.520000 ;
+ RECT 1041.790000 2605.160000 1042.790000 2605.640000 ;
+ RECT 1045.455000 2605.160000 1046.720000 2605.640000 ;
+ RECT 1041.790000 2610.600000 1042.790000 2611.080000 ;
+ RECT 1045.455000 2610.600000 1046.720000 2611.080000 ;
+ RECT 1041.790000 2599.720000 1042.790000 2600.200000 ;
+ RECT 1045.455000 2599.720000 1046.720000 2600.200000 ;
+ RECT 1135.620000 2577.960000 1136.720000 2578.440000 ;
+ RECT 1135.620000 2583.400000 1136.720000 2583.880000 ;
+ RECT 1135.620000 2588.840000 1136.720000 2589.320000 ;
+ RECT 1135.620000 2594.280000 1136.720000 2594.760000 ;
+ RECT 1090.620000 2577.960000 1091.720000 2578.440000 ;
+ RECT 1090.620000 2583.400000 1091.720000 2583.880000 ;
+ RECT 1090.620000 2588.840000 1091.720000 2589.320000 ;
+ RECT 1090.620000 2594.280000 1091.720000 2594.760000 ;
+ RECT 1135.620000 2556.200000 1136.720000 2556.680000 ;
+ RECT 1135.620000 2561.640000 1136.720000 2562.120000 ;
+ RECT 1135.620000 2567.080000 1136.720000 2567.560000 ;
+ RECT 1135.620000 2572.520000 1136.720000 2573.000000 ;
+ RECT 1090.620000 2556.200000 1091.720000 2556.680000 ;
+ RECT 1090.620000 2561.640000 1091.720000 2562.120000 ;
+ RECT 1090.620000 2567.080000 1091.720000 2567.560000 ;
+ RECT 1090.620000 2572.520000 1091.720000 2573.000000 ;
+ RECT 1041.790000 2594.280000 1042.790000 2594.760000 ;
+ RECT 1045.455000 2594.280000 1046.720000 2594.760000 ;
+ RECT 1041.790000 2588.840000 1042.790000 2589.320000 ;
+ RECT 1045.455000 2588.840000 1046.720000 2589.320000 ;
+ RECT 1041.790000 2583.400000 1042.790000 2583.880000 ;
+ RECT 1045.455000 2583.400000 1046.720000 2583.880000 ;
+ RECT 1041.790000 2577.960000 1042.790000 2578.440000 ;
+ RECT 1045.455000 2577.960000 1046.720000 2578.440000 ;
+ RECT 1041.790000 2572.520000 1042.790000 2573.000000 ;
+ RECT 1045.455000 2572.520000 1046.720000 2573.000000 ;
+ RECT 1041.790000 2561.640000 1042.790000 2562.120000 ;
+ RECT 1045.455000 2561.640000 1046.720000 2562.120000 ;
+ RECT 1041.790000 2567.080000 1042.790000 2567.560000 ;
+ RECT 1045.455000 2567.080000 1046.720000 2567.560000 ;
+ RECT 1041.790000 2556.200000 1042.790000 2556.680000 ;
+ RECT 1045.455000 2556.200000 1046.720000 2556.680000 ;
+ RECT 1180.620000 2648.680000 1181.720000 2649.160000 ;
+ RECT 1225.620000 2648.680000 1226.720000 2649.160000 ;
+ RECT 1238.430000 2648.680000 1239.430000 2649.160000 ;
+ RECT 1090.620000 2648.680000 1091.720000 2649.160000 ;
+ RECT 1135.620000 2648.680000 1136.720000 2649.160000 ;
+ RECT 1041.790000 2648.680000 1042.790000 2649.160000 ;
+ RECT 1045.455000 2648.680000 1046.720000 2649.160000 ;
+ RECT 1040.560000 2745.440000 1240.660000 2746.440000 ;
+ RECT 1040.560000 2549.870000 1240.660000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 2548.620000 1042.790000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 2747.880000 1042.790000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 2548.620000 1239.430000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 2747.880000 1239.430000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2549.870000 1041.560000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2549.870000 1240.660000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2745.440000 1041.560000 2746.440000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2745.440000 1240.660000 2746.440000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 2540.900000 1046.720000 2541.380000 ;
+ RECT 1045.455000 2530.020000 1046.720000 2530.500000 ;
+ RECT 1045.455000 2535.460000 1046.720000 2535.940000 ;
+ RECT 1045.455000 2524.580000 1046.720000 2525.060000 ;
+ RECT 1045.455000 2519.140000 1046.720000 2519.620000 ;
+ RECT 1045.455000 2513.700000 1046.720000 2514.180000 ;
+ RECT 1045.455000 2508.260000 1046.720000 2508.740000 ;
+ RECT 1045.455000 2502.820000 1046.720000 2503.300000 ;
+ RECT 1045.455000 2497.380000 1046.720000 2497.860000 ;
+ RECT 1045.455000 2486.500000 1046.720000 2486.980000 ;
+ RECT 1045.455000 2491.940000 1046.720000 2492.420000 ;
+ RECT 1045.455000 2481.060000 1046.720000 2481.540000 ;
+ RECT 1045.455000 2475.620000 1046.720000 2476.100000 ;
+ RECT 1045.455000 2470.180000 1046.720000 2470.660000 ;
+ RECT 1045.455000 2464.740000 1046.720000 2465.220000 ;
+ RECT 1045.455000 2459.300000 1046.720000 2459.780000 ;
+ RECT 1045.455000 2453.860000 1046.720000 2454.340000 ;
+ RECT 1045.455000 2442.980000 1046.720000 2443.460000 ;
+ RECT 1045.455000 2437.540000 1046.720000 2438.020000 ;
+ RECT 1045.455000 2432.100000 1046.720000 2432.580000 ;
+ RECT 1045.455000 2426.660000 1046.720000 2427.140000 ;
+ RECT 1045.455000 2421.220000 1046.720000 2421.700000 ;
+ RECT 1045.455000 2415.780000 1046.720000 2416.260000 ;
+ RECT 1045.455000 2404.900000 1046.720000 2405.380000 ;
+ RECT 1045.455000 2410.340000 1046.720000 2410.820000 ;
+ RECT 1045.455000 2399.460000 1046.720000 2399.940000 ;
+ RECT 1045.455000 2394.020000 1046.720000 2394.500000 ;
+ RECT 1045.455000 2388.580000 1046.720000 2389.060000 ;
+ RECT 1045.455000 2383.140000 1046.720000 2383.620000 ;
+ RECT 1045.455000 2377.700000 1046.720000 2378.180000 ;
+ RECT 1045.455000 2372.260000 1046.720000 2372.740000 ;
+ RECT 1045.455000 2361.380000 1046.720000 2361.860000 ;
+ RECT 1045.455000 2366.820000 1046.720000 2367.300000 ;
+ RECT 1045.455000 2355.940000 1046.720000 2356.420000 ;
+ RECT 1045.455000 2448.420000 1046.720000 2448.900000 ;
+ RECT 1225.620000 2349.610000 1226.720000 2546.180000 ;
+ RECT 1180.620000 2349.610000 1181.720000 2546.180000 ;
+ RECT 1238.430000 2348.360000 1239.430000 2548.620000 ;
+ RECT 1135.620000 2349.610000 1136.720000 2546.180000 ;
+ RECT 1090.620000 2349.610000 1091.720000 2546.180000 ;
+ RECT 1045.620000 2349.610000 1046.720000 2546.180000 ;
+ RECT 1041.790000 2348.360000 1042.790000 2548.620000 ;
+ LAYER met3 ;
+ RECT 1225.620000 2540.900000 1226.720000 2541.380000 ;
+ RECT 1238.430000 2540.900000 1239.430000 2541.380000 ;
+ RECT 1238.430000 2530.020000 1239.430000 2530.500000 ;
+ RECT 1238.430000 2524.580000 1239.430000 2525.060000 ;
+ RECT 1238.430000 2535.460000 1239.430000 2535.940000 ;
+ RECT 1225.620000 2535.460000 1226.720000 2535.940000 ;
+ RECT 1225.620000 2530.020000 1226.720000 2530.500000 ;
+ RECT 1225.620000 2524.580000 1226.720000 2525.060000 ;
+ RECT 1225.620000 2513.700000 1226.720000 2514.180000 ;
+ RECT 1225.620000 2519.140000 1226.720000 2519.620000 ;
+ RECT 1238.430000 2513.700000 1239.430000 2514.180000 ;
+ RECT 1238.430000 2519.140000 1239.430000 2519.620000 ;
+ RECT 1225.620000 2502.820000 1226.720000 2503.300000 ;
+ RECT 1225.620000 2508.260000 1226.720000 2508.740000 ;
+ RECT 1238.430000 2502.820000 1239.430000 2503.300000 ;
+ RECT 1238.430000 2508.260000 1239.430000 2508.740000 ;
+ RECT 1180.620000 2524.580000 1181.720000 2525.060000 ;
+ RECT 1180.620000 2530.020000 1181.720000 2530.500000 ;
+ RECT 1180.620000 2535.460000 1181.720000 2535.940000 ;
+ RECT 1180.620000 2540.900000 1181.720000 2541.380000 ;
+ RECT 1180.620000 2508.260000 1181.720000 2508.740000 ;
+ RECT 1180.620000 2502.820000 1181.720000 2503.300000 ;
+ RECT 1180.620000 2513.700000 1181.720000 2514.180000 ;
+ RECT 1180.620000 2519.140000 1181.720000 2519.620000 ;
+ RECT 1238.430000 2491.940000 1239.430000 2492.420000 ;
+ RECT 1238.430000 2486.500000 1239.430000 2486.980000 ;
+ RECT 1238.430000 2497.380000 1239.430000 2497.860000 ;
+ RECT 1225.620000 2497.380000 1226.720000 2497.860000 ;
+ RECT 1225.620000 2491.940000 1226.720000 2492.420000 ;
+ RECT 1225.620000 2486.500000 1226.720000 2486.980000 ;
+ RECT 1225.620000 2475.620000 1226.720000 2476.100000 ;
+ RECT 1225.620000 2481.060000 1226.720000 2481.540000 ;
+ RECT 1238.430000 2475.620000 1239.430000 2476.100000 ;
+ RECT 1238.430000 2481.060000 1239.430000 2481.540000 ;
+ RECT 1238.430000 2464.740000 1239.430000 2465.220000 ;
+ RECT 1238.430000 2470.180000 1239.430000 2470.660000 ;
+ RECT 1225.620000 2470.180000 1226.720000 2470.660000 ;
+ RECT 1225.620000 2464.740000 1226.720000 2465.220000 ;
+ RECT 1225.620000 2453.860000 1226.720000 2454.340000 ;
+ RECT 1225.620000 2459.300000 1226.720000 2459.780000 ;
+ RECT 1238.430000 2453.860000 1239.430000 2454.340000 ;
+ RECT 1238.430000 2459.300000 1239.430000 2459.780000 ;
+ RECT 1180.620000 2475.620000 1181.720000 2476.100000 ;
+ RECT 1180.620000 2481.060000 1181.720000 2481.540000 ;
+ RECT 1180.620000 2486.500000 1181.720000 2486.980000 ;
+ RECT 1180.620000 2491.940000 1181.720000 2492.420000 ;
+ RECT 1180.620000 2497.380000 1181.720000 2497.860000 ;
+ RECT 1180.620000 2453.860000 1181.720000 2454.340000 ;
+ RECT 1180.620000 2459.300000 1181.720000 2459.780000 ;
+ RECT 1180.620000 2464.740000 1181.720000 2465.220000 ;
+ RECT 1180.620000 2470.180000 1181.720000 2470.660000 ;
+ RECT 1135.620000 2530.020000 1136.720000 2530.500000 ;
+ RECT 1135.620000 2524.580000 1136.720000 2525.060000 ;
+ RECT 1135.620000 2535.460000 1136.720000 2535.940000 ;
+ RECT 1135.620000 2540.900000 1136.720000 2541.380000 ;
+ RECT 1090.620000 2524.580000 1091.720000 2525.060000 ;
+ RECT 1090.620000 2530.020000 1091.720000 2530.500000 ;
+ RECT 1090.620000 2535.460000 1091.720000 2535.940000 ;
+ RECT 1090.620000 2540.900000 1091.720000 2541.380000 ;
+ RECT 1135.620000 2502.820000 1136.720000 2503.300000 ;
+ RECT 1135.620000 2508.260000 1136.720000 2508.740000 ;
+ RECT 1135.620000 2513.700000 1136.720000 2514.180000 ;
+ RECT 1135.620000 2519.140000 1136.720000 2519.620000 ;
+ RECT 1090.620000 2502.820000 1091.720000 2503.300000 ;
+ RECT 1090.620000 2508.260000 1091.720000 2508.740000 ;
+ RECT 1090.620000 2513.700000 1091.720000 2514.180000 ;
+ RECT 1090.620000 2519.140000 1091.720000 2519.620000 ;
+ RECT 1041.790000 2540.900000 1042.790000 2541.380000 ;
+ RECT 1045.455000 2540.900000 1046.720000 2541.380000 ;
+ RECT 1041.790000 2530.020000 1042.790000 2530.500000 ;
+ RECT 1045.455000 2530.020000 1046.720000 2530.500000 ;
+ RECT 1041.790000 2535.460000 1042.790000 2535.940000 ;
+ RECT 1045.455000 2535.460000 1046.720000 2535.940000 ;
+ RECT 1041.790000 2524.580000 1042.790000 2525.060000 ;
+ RECT 1045.455000 2524.580000 1046.720000 2525.060000 ;
+ RECT 1041.790000 2519.140000 1042.790000 2519.620000 ;
+ RECT 1045.455000 2519.140000 1046.720000 2519.620000 ;
+ RECT 1041.790000 2513.700000 1042.790000 2514.180000 ;
+ RECT 1045.455000 2513.700000 1046.720000 2514.180000 ;
+ RECT 1041.790000 2508.260000 1042.790000 2508.740000 ;
+ RECT 1045.455000 2508.260000 1046.720000 2508.740000 ;
+ RECT 1041.790000 2502.820000 1042.790000 2503.300000 ;
+ RECT 1045.455000 2502.820000 1046.720000 2503.300000 ;
+ RECT 1135.620000 2475.620000 1136.720000 2476.100000 ;
+ RECT 1135.620000 2481.060000 1136.720000 2481.540000 ;
+ RECT 1135.620000 2486.500000 1136.720000 2486.980000 ;
+ RECT 1135.620000 2491.940000 1136.720000 2492.420000 ;
+ RECT 1135.620000 2497.380000 1136.720000 2497.860000 ;
+ RECT 1090.620000 2475.620000 1091.720000 2476.100000 ;
+ RECT 1090.620000 2481.060000 1091.720000 2481.540000 ;
+ RECT 1090.620000 2486.500000 1091.720000 2486.980000 ;
+ RECT 1090.620000 2491.940000 1091.720000 2492.420000 ;
+ RECT 1090.620000 2497.380000 1091.720000 2497.860000 ;
+ RECT 1135.620000 2453.860000 1136.720000 2454.340000 ;
+ RECT 1135.620000 2459.300000 1136.720000 2459.780000 ;
+ RECT 1135.620000 2464.740000 1136.720000 2465.220000 ;
+ RECT 1135.620000 2470.180000 1136.720000 2470.660000 ;
+ RECT 1090.620000 2453.860000 1091.720000 2454.340000 ;
+ RECT 1090.620000 2459.300000 1091.720000 2459.780000 ;
+ RECT 1090.620000 2464.740000 1091.720000 2465.220000 ;
+ RECT 1090.620000 2470.180000 1091.720000 2470.660000 ;
+ RECT 1041.790000 2497.380000 1042.790000 2497.860000 ;
+ RECT 1045.455000 2497.380000 1046.720000 2497.860000 ;
+ RECT 1041.790000 2486.500000 1042.790000 2486.980000 ;
+ RECT 1045.455000 2486.500000 1046.720000 2486.980000 ;
+ RECT 1041.790000 2491.940000 1042.790000 2492.420000 ;
+ RECT 1045.455000 2491.940000 1046.720000 2492.420000 ;
+ RECT 1041.790000 2481.060000 1042.790000 2481.540000 ;
+ RECT 1045.455000 2481.060000 1046.720000 2481.540000 ;
+ RECT 1041.790000 2475.620000 1042.790000 2476.100000 ;
+ RECT 1045.455000 2475.620000 1046.720000 2476.100000 ;
+ RECT 1041.790000 2470.180000 1042.790000 2470.660000 ;
+ RECT 1045.455000 2470.180000 1046.720000 2470.660000 ;
+ RECT 1041.790000 2464.740000 1042.790000 2465.220000 ;
+ RECT 1045.455000 2464.740000 1046.720000 2465.220000 ;
+ RECT 1041.790000 2459.300000 1042.790000 2459.780000 ;
+ RECT 1045.455000 2459.300000 1046.720000 2459.780000 ;
+ RECT 1041.790000 2453.860000 1042.790000 2454.340000 ;
+ RECT 1045.455000 2453.860000 1046.720000 2454.340000 ;
+ RECT 1225.620000 2437.540000 1226.720000 2438.020000 ;
+ RECT 1225.620000 2442.980000 1226.720000 2443.460000 ;
+ RECT 1238.430000 2437.540000 1239.430000 2438.020000 ;
+ RECT 1238.430000 2442.980000 1239.430000 2443.460000 ;
+ RECT 1238.430000 2426.660000 1239.430000 2427.140000 ;
+ RECT 1238.430000 2432.100000 1239.430000 2432.580000 ;
+ RECT 1225.620000 2432.100000 1226.720000 2432.580000 ;
+ RECT 1225.620000 2426.660000 1226.720000 2427.140000 ;
+ RECT 1225.620000 2415.780000 1226.720000 2416.260000 ;
+ RECT 1225.620000 2421.220000 1226.720000 2421.700000 ;
+ RECT 1238.430000 2415.780000 1239.430000 2416.260000 ;
+ RECT 1238.430000 2421.220000 1239.430000 2421.700000 ;
+ RECT 1238.430000 2404.900000 1239.430000 2405.380000 ;
+ RECT 1238.430000 2399.460000 1239.430000 2399.940000 ;
+ RECT 1238.430000 2410.340000 1239.430000 2410.820000 ;
+ RECT 1225.620000 2410.340000 1226.720000 2410.820000 ;
+ RECT 1225.620000 2404.900000 1226.720000 2405.380000 ;
+ RECT 1225.620000 2399.460000 1226.720000 2399.940000 ;
+ RECT 1180.620000 2426.660000 1181.720000 2427.140000 ;
+ RECT 1180.620000 2432.100000 1181.720000 2432.580000 ;
+ RECT 1180.620000 2437.540000 1181.720000 2438.020000 ;
+ RECT 1180.620000 2442.980000 1181.720000 2443.460000 ;
+ RECT 1180.620000 2399.460000 1181.720000 2399.940000 ;
+ RECT 1180.620000 2404.900000 1181.720000 2405.380000 ;
+ RECT 1180.620000 2410.340000 1181.720000 2410.820000 ;
+ RECT 1180.620000 2415.780000 1181.720000 2416.260000 ;
+ RECT 1180.620000 2421.220000 1181.720000 2421.700000 ;
+ RECT 1225.620000 2388.580000 1226.720000 2389.060000 ;
+ RECT 1225.620000 2394.020000 1226.720000 2394.500000 ;
+ RECT 1238.430000 2388.580000 1239.430000 2389.060000 ;
+ RECT 1238.430000 2394.020000 1239.430000 2394.500000 ;
+ RECT 1225.620000 2377.700000 1226.720000 2378.180000 ;
+ RECT 1225.620000 2383.140000 1226.720000 2383.620000 ;
+ RECT 1238.430000 2377.700000 1239.430000 2378.180000 ;
+ RECT 1238.430000 2383.140000 1239.430000 2383.620000 ;
+ RECT 1238.430000 2366.820000 1239.430000 2367.300000 ;
+ RECT 1238.430000 2361.380000 1239.430000 2361.860000 ;
+ RECT 1238.430000 2372.260000 1239.430000 2372.740000 ;
+ RECT 1225.620000 2372.260000 1226.720000 2372.740000 ;
+ RECT 1225.620000 2366.820000 1226.720000 2367.300000 ;
+ RECT 1225.620000 2361.380000 1226.720000 2361.860000 ;
+ RECT 1225.620000 2355.940000 1226.720000 2356.420000 ;
+ RECT 1238.430000 2355.940000 1239.430000 2356.420000 ;
+ RECT 1180.620000 2377.700000 1181.720000 2378.180000 ;
+ RECT 1180.620000 2383.140000 1181.720000 2383.620000 ;
+ RECT 1180.620000 2388.580000 1181.720000 2389.060000 ;
+ RECT 1180.620000 2394.020000 1181.720000 2394.500000 ;
+ RECT 1180.620000 2355.940000 1181.720000 2356.420000 ;
+ RECT 1180.620000 2361.380000 1181.720000 2361.860000 ;
+ RECT 1180.620000 2366.820000 1181.720000 2367.300000 ;
+ RECT 1180.620000 2372.260000 1181.720000 2372.740000 ;
+ RECT 1135.620000 2426.660000 1136.720000 2427.140000 ;
+ RECT 1135.620000 2432.100000 1136.720000 2432.580000 ;
+ RECT 1135.620000 2437.540000 1136.720000 2438.020000 ;
+ RECT 1135.620000 2442.980000 1136.720000 2443.460000 ;
+ RECT 1090.620000 2426.660000 1091.720000 2427.140000 ;
+ RECT 1090.620000 2432.100000 1091.720000 2432.580000 ;
+ RECT 1090.620000 2437.540000 1091.720000 2438.020000 ;
+ RECT 1090.620000 2442.980000 1091.720000 2443.460000 ;
+ RECT 1135.620000 2399.460000 1136.720000 2399.940000 ;
+ RECT 1135.620000 2404.900000 1136.720000 2405.380000 ;
+ RECT 1135.620000 2410.340000 1136.720000 2410.820000 ;
+ RECT 1135.620000 2415.780000 1136.720000 2416.260000 ;
+ RECT 1135.620000 2421.220000 1136.720000 2421.700000 ;
+ RECT 1090.620000 2399.460000 1091.720000 2399.940000 ;
+ RECT 1090.620000 2404.900000 1091.720000 2405.380000 ;
+ RECT 1090.620000 2410.340000 1091.720000 2410.820000 ;
+ RECT 1090.620000 2415.780000 1091.720000 2416.260000 ;
+ RECT 1090.620000 2421.220000 1091.720000 2421.700000 ;
+ RECT 1041.790000 2442.980000 1042.790000 2443.460000 ;
+ RECT 1045.455000 2442.980000 1046.720000 2443.460000 ;
+ RECT 1041.790000 2437.540000 1042.790000 2438.020000 ;
+ RECT 1045.455000 2437.540000 1046.720000 2438.020000 ;
+ RECT 1041.790000 2432.100000 1042.790000 2432.580000 ;
+ RECT 1045.455000 2432.100000 1046.720000 2432.580000 ;
+ RECT 1041.790000 2426.660000 1042.790000 2427.140000 ;
+ RECT 1045.455000 2426.660000 1046.720000 2427.140000 ;
+ RECT 1041.790000 2421.220000 1042.790000 2421.700000 ;
+ RECT 1045.455000 2421.220000 1046.720000 2421.700000 ;
+ RECT 1041.790000 2415.780000 1042.790000 2416.260000 ;
+ RECT 1045.455000 2415.780000 1046.720000 2416.260000 ;
+ RECT 1041.790000 2404.900000 1042.790000 2405.380000 ;
+ RECT 1045.455000 2404.900000 1046.720000 2405.380000 ;
+ RECT 1041.790000 2410.340000 1042.790000 2410.820000 ;
+ RECT 1045.455000 2410.340000 1046.720000 2410.820000 ;
+ RECT 1041.790000 2399.460000 1042.790000 2399.940000 ;
+ RECT 1045.455000 2399.460000 1046.720000 2399.940000 ;
+ RECT 1135.620000 2377.700000 1136.720000 2378.180000 ;
+ RECT 1135.620000 2383.140000 1136.720000 2383.620000 ;
+ RECT 1135.620000 2388.580000 1136.720000 2389.060000 ;
+ RECT 1135.620000 2394.020000 1136.720000 2394.500000 ;
+ RECT 1090.620000 2377.700000 1091.720000 2378.180000 ;
+ RECT 1090.620000 2383.140000 1091.720000 2383.620000 ;
+ RECT 1090.620000 2388.580000 1091.720000 2389.060000 ;
+ RECT 1090.620000 2394.020000 1091.720000 2394.500000 ;
+ RECT 1135.620000 2355.940000 1136.720000 2356.420000 ;
+ RECT 1135.620000 2361.380000 1136.720000 2361.860000 ;
+ RECT 1135.620000 2366.820000 1136.720000 2367.300000 ;
+ RECT 1135.620000 2372.260000 1136.720000 2372.740000 ;
+ RECT 1090.620000 2355.940000 1091.720000 2356.420000 ;
+ RECT 1090.620000 2361.380000 1091.720000 2361.860000 ;
+ RECT 1090.620000 2366.820000 1091.720000 2367.300000 ;
+ RECT 1090.620000 2372.260000 1091.720000 2372.740000 ;
+ RECT 1041.790000 2394.020000 1042.790000 2394.500000 ;
+ RECT 1045.455000 2394.020000 1046.720000 2394.500000 ;
+ RECT 1041.790000 2388.580000 1042.790000 2389.060000 ;
+ RECT 1045.455000 2388.580000 1046.720000 2389.060000 ;
+ RECT 1041.790000 2383.140000 1042.790000 2383.620000 ;
+ RECT 1045.455000 2383.140000 1046.720000 2383.620000 ;
+ RECT 1041.790000 2377.700000 1042.790000 2378.180000 ;
+ RECT 1045.455000 2377.700000 1046.720000 2378.180000 ;
+ RECT 1041.790000 2372.260000 1042.790000 2372.740000 ;
+ RECT 1045.455000 2372.260000 1046.720000 2372.740000 ;
+ RECT 1041.790000 2361.380000 1042.790000 2361.860000 ;
+ RECT 1045.455000 2361.380000 1046.720000 2361.860000 ;
+ RECT 1041.790000 2366.820000 1042.790000 2367.300000 ;
+ RECT 1045.455000 2366.820000 1046.720000 2367.300000 ;
+ RECT 1041.790000 2355.940000 1042.790000 2356.420000 ;
+ RECT 1045.455000 2355.940000 1046.720000 2356.420000 ;
+ RECT 1180.620000 2448.420000 1181.720000 2448.900000 ;
+ RECT 1225.620000 2448.420000 1226.720000 2448.900000 ;
+ RECT 1238.430000 2448.420000 1239.430000 2448.900000 ;
+ RECT 1090.620000 2448.420000 1091.720000 2448.900000 ;
+ RECT 1135.620000 2448.420000 1136.720000 2448.900000 ;
+ RECT 1041.790000 2448.420000 1042.790000 2448.900000 ;
+ RECT 1045.455000 2448.420000 1046.720000 2448.900000 ;
+ RECT 1040.560000 2545.180000 1240.660000 2546.180000 ;
+ RECT 1040.560000 2349.610000 1240.660000 2350.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 2348.360000 1042.790000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 2547.620000 1042.790000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 2348.360000 1239.430000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 2547.620000 1239.430000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2349.610000 1041.560000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2349.610000 1240.660000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2545.180000 1041.560000 2546.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2545.180000 1240.660000 2546.180000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 2340.640000 1046.720000 2341.120000 ;
+ RECT 1045.455000 2329.760000 1046.720000 2330.240000 ;
+ RECT 1045.455000 2335.200000 1046.720000 2335.680000 ;
+ RECT 1045.455000 2324.320000 1046.720000 2324.800000 ;
+ RECT 1045.455000 2318.880000 1046.720000 2319.360000 ;
+ RECT 1045.455000 2313.440000 1046.720000 2313.920000 ;
+ RECT 1045.455000 2308.000000 1046.720000 2308.480000 ;
+ RECT 1045.455000 2302.560000 1046.720000 2303.040000 ;
+ RECT 1045.455000 2297.120000 1046.720000 2297.600000 ;
+ RECT 1045.455000 2286.240000 1046.720000 2286.720000 ;
+ RECT 1045.455000 2291.680000 1046.720000 2292.160000 ;
+ RECT 1045.455000 2280.800000 1046.720000 2281.280000 ;
+ RECT 1045.455000 2275.360000 1046.720000 2275.840000 ;
+ RECT 1045.455000 2269.920000 1046.720000 2270.400000 ;
+ RECT 1045.455000 2264.480000 1046.720000 2264.960000 ;
+ RECT 1045.455000 2259.040000 1046.720000 2259.520000 ;
+ RECT 1045.455000 2253.600000 1046.720000 2254.080000 ;
+ RECT 1045.455000 2242.720000 1046.720000 2243.200000 ;
+ RECT 1045.455000 2237.280000 1046.720000 2237.760000 ;
+ RECT 1045.455000 2231.840000 1046.720000 2232.320000 ;
+ RECT 1045.455000 2226.400000 1046.720000 2226.880000 ;
+ RECT 1045.455000 2220.960000 1046.720000 2221.440000 ;
+ RECT 1045.455000 2215.520000 1046.720000 2216.000000 ;
+ RECT 1045.455000 2204.640000 1046.720000 2205.120000 ;
+ RECT 1045.455000 2210.080000 1046.720000 2210.560000 ;
+ RECT 1045.455000 2199.200000 1046.720000 2199.680000 ;
+ RECT 1045.455000 2193.760000 1046.720000 2194.240000 ;
+ RECT 1045.455000 2188.320000 1046.720000 2188.800000 ;
+ RECT 1045.455000 2182.880000 1046.720000 2183.360000 ;
+ RECT 1045.455000 2177.440000 1046.720000 2177.920000 ;
+ RECT 1045.455000 2172.000000 1046.720000 2172.480000 ;
+ RECT 1045.455000 2161.120000 1046.720000 2161.600000 ;
+ RECT 1045.455000 2166.560000 1046.720000 2167.040000 ;
+ RECT 1045.455000 2155.680000 1046.720000 2156.160000 ;
+ RECT 1045.455000 2248.160000 1046.720000 2248.640000 ;
+ RECT 1225.620000 2149.350000 1226.720000 2345.920000 ;
+ RECT 1180.620000 2149.350000 1181.720000 2345.920000 ;
+ RECT 1238.430000 2148.100000 1239.430000 2348.360000 ;
+ RECT 1135.620000 2149.350000 1136.720000 2345.920000 ;
+ RECT 1090.620000 2149.350000 1091.720000 2345.920000 ;
+ RECT 1045.620000 2149.350000 1046.720000 2345.920000 ;
+ RECT 1041.790000 2148.100000 1042.790000 2348.360000 ;
+ LAYER met3 ;
+ RECT 1225.620000 2340.640000 1226.720000 2341.120000 ;
+ RECT 1238.430000 2340.640000 1239.430000 2341.120000 ;
+ RECT 1238.430000 2329.760000 1239.430000 2330.240000 ;
+ RECT 1238.430000 2324.320000 1239.430000 2324.800000 ;
+ RECT 1238.430000 2335.200000 1239.430000 2335.680000 ;
+ RECT 1225.620000 2335.200000 1226.720000 2335.680000 ;
+ RECT 1225.620000 2329.760000 1226.720000 2330.240000 ;
+ RECT 1225.620000 2324.320000 1226.720000 2324.800000 ;
+ RECT 1225.620000 2313.440000 1226.720000 2313.920000 ;
+ RECT 1225.620000 2318.880000 1226.720000 2319.360000 ;
+ RECT 1238.430000 2313.440000 1239.430000 2313.920000 ;
+ RECT 1238.430000 2318.880000 1239.430000 2319.360000 ;
+ RECT 1225.620000 2302.560000 1226.720000 2303.040000 ;
+ RECT 1225.620000 2308.000000 1226.720000 2308.480000 ;
+ RECT 1238.430000 2302.560000 1239.430000 2303.040000 ;
+ RECT 1238.430000 2308.000000 1239.430000 2308.480000 ;
+ RECT 1180.620000 2324.320000 1181.720000 2324.800000 ;
+ RECT 1180.620000 2329.760000 1181.720000 2330.240000 ;
+ RECT 1180.620000 2335.200000 1181.720000 2335.680000 ;
+ RECT 1180.620000 2340.640000 1181.720000 2341.120000 ;
+ RECT 1180.620000 2308.000000 1181.720000 2308.480000 ;
+ RECT 1180.620000 2302.560000 1181.720000 2303.040000 ;
+ RECT 1180.620000 2313.440000 1181.720000 2313.920000 ;
+ RECT 1180.620000 2318.880000 1181.720000 2319.360000 ;
+ RECT 1238.430000 2291.680000 1239.430000 2292.160000 ;
+ RECT 1238.430000 2286.240000 1239.430000 2286.720000 ;
+ RECT 1238.430000 2297.120000 1239.430000 2297.600000 ;
+ RECT 1225.620000 2297.120000 1226.720000 2297.600000 ;
+ RECT 1225.620000 2291.680000 1226.720000 2292.160000 ;
+ RECT 1225.620000 2286.240000 1226.720000 2286.720000 ;
+ RECT 1225.620000 2275.360000 1226.720000 2275.840000 ;
+ RECT 1225.620000 2280.800000 1226.720000 2281.280000 ;
+ RECT 1238.430000 2275.360000 1239.430000 2275.840000 ;
+ RECT 1238.430000 2280.800000 1239.430000 2281.280000 ;
+ RECT 1238.430000 2264.480000 1239.430000 2264.960000 ;
+ RECT 1238.430000 2269.920000 1239.430000 2270.400000 ;
+ RECT 1225.620000 2269.920000 1226.720000 2270.400000 ;
+ RECT 1225.620000 2264.480000 1226.720000 2264.960000 ;
+ RECT 1225.620000 2253.600000 1226.720000 2254.080000 ;
+ RECT 1225.620000 2259.040000 1226.720000 2259.520000 ;
+ RECT 1238.430000 2253.600000 1239.430000 2254.080000 ;
+ RECT 1238.430000 2259.040000 1239.430000 2259.520000 ;
+ RECT 1180.620000 2275.360000 1181.720000 2275.840000 ;
+ RECT 1180.620000 2280.800000 1181.720000 2281.280000 ;
+ RECT 1180.620000 2286.240000 1181.720000 2286.720000 ;
+ RECT 1180.620000 2291.680000 1181.720000 2292.160000 ;
+ RECT 1180.620000 2297.120000 1181.720000 2297.600000 ;
+ RECT 1180.620000 2253.600000 1181.720000 2254.080000 ;
+ RECT 1180.620000 2259.040000 1181.720000 2259.520000 ;
+ RECT 1180.620000 2264.480000 1181.720000 2264.960000 ;
+ RECT 1180.620000 2269.920000 1181.720000 2270.400000 ;
+ RECT 1135.620000 2329.760000 1136.720000 2330.240000 ;
+ RECT 1135.620000 2324.320000 1136.720000 2324.800000 ;
+ RECT 1135.620000 2335.200000 1136.720000 2335.680000 ;
+ RECT 1135.620000 2340.640000 1136.720000 2341.120000 ;
+ RECT 1090.620000 2324.320000 1091.720000 2324.800000 ;
+ RECT 1090.620000 2329.760000 1091.720000 2330.240000 ;
+ RECT 1090.620000 2335.200000 1091.720000 2335.680000 ;
+ RECT 1090.620000 2340.640000 1091.720000 2341.120000 ;
+ RECT 1135.620000 2302.560000 1136.720000 2303.040000 ;
+ RECT 1135.620000 2308.000000 1136.720000 2308.480000 ;
+ RECT 1135.620000 2313.440000 1136.720000 2313.920000 ;
+ RECT 1135.620000 2318.880000 1136.720000 2319.360000 ;
+ RECT 1090.620000 2302.560000 1091.720000 2303.040000 ;
+ RECT 1090.620000 2308.000000 1091.720000 2308.480000 ;
+ RECT 1090.620000 2313.440000 1091.720000 2313.920000 ;
+ RECT 1090.620000 2318.880000 1091.720000 2319.360000 ;
+ RECT 1041.790000 2340.640000 1042.790000 2341.120000 ;
+ RECT 1045.455000 2340.640000 1046.720000 2341.120000 ;
+ RECT 1041.790000 2329.760000 1042.790000 2330.240000 ;
+ RECT 1045.455000 2329.760000 1046.720000 2330.240000 ;
+ RECT 1041.790000 2335.200000 1042.790000 2335.680000 ;
+ RECT 1045.455000 2335.200000 1046.720000 2335.680000 ;
+ RECT 1041.790000 2324.320000 1042.790000 2324.800000 ;
+ RECT 1045.455000 2324.320000 1046.720000 2324.800000 ;
+ RECT 1041.790000 2318.880000 1042.790000 2319.360000 ;
+ RECT 1045.455000 2318.880000 1046.720000 2319.360000 ;
+ RECT 1041.790000 2313.440000 1042.790000 2313.920000 ;
+ RECT 1045.455000 2313.440000 1046.720000 2313.920000 ;
+ RECT 1041.790000 2308.000000 1042.790000 2308.480000 ;
+ RECT 1045.455000 2308.000000 1046.720000 2308.480000 ;
+ RECT 1041.790000 2302.560000 1042.790000 2303.040000 ;
+ RECT 1045.455000 2302.560000 1046.720000 2303.040000 ;
+ RECT 1135.620000 2275.360000 1136.720000 2275.840000 ;
+ RECT 1135.620000 2280.800000 1136.720000 2281.280000 ;
+ RECT 1135.620000 2286.240000 1136.720000 2286.720000 ;
+ RECT 1135.620000 2291.680000 1136.720000 2292.160000 ;
+ RECT 1135.620000 2297.120000 1136.720000 2297.600000 ;
+ RECT 1090.620000 2275.360000 1091.720000 2275.840000 ;
+ RECT 1090.620000 2280.800000 1091.720000 2281.280000 ;
+ RECT 1090.620000 2286.240000 1091.720000 2286.720000 ;
+ RECT 1090.620000 2291.680000 1091.720000 2292.160000 ;
+ RECT 1090.620000 2297.120000 1091.720000 2297.600000 ;
+ RECT 1135.620000 2253.600000 1136.720000 2254.080000 ;
+ RECT 1135.620000 2259.040000 1136.720000 2259.520000 ;
+ RECT 1135.620000 2264.480000 1136.720000 2264.960000 ;
+ RECT 1135.620000 2269.920000 1136.720000 2270.400000 ;
+ RECT 1090.620000 2253.600000 1091.720000 2254.080000 ;
+ RECT 1090.620000 2259.040000 1091.720000 2259.520000 ;
+ RECT 1090.620000 2264.480000 1091.720000 2264.960000 ;
+ RECT 1090.620000 2269.920000 1091.720000 2270.400000 ;
+ RECT 1041.790000 2297.120000 1042.790000 2297.600000 ;
+ RECT 1045.455000 2297.120000 1046.720000 2297.600000 ;
+ RECT 1041.790000 2286.240000 1042.790000 2286.720000 ;
+ RECT 1045.455000 2286.240000 1046.720000 2286.720000 ;
+ RECT 1041.790000 2291.680000 1042.790000 2292.160000 ;
+ RECT 1045.455000 2291.680000 1046.720000 2292.160000 ;
+ RECT 1041.790000 2280.800000 1042.790000 2281.280000 ;
+ RECT 1045.455000 2280.800000 1046.720000 2281.280000 ;
+ RECT 1041.790000 2275.360000 1042.790000 2275.840000 ;
+ RECT 1045.455000 2275.360000 1046.720000 2275.840000 ;
+ RECT 1041.790000 2269.920000 1042.790000 2270.400000 ;
+ RECT 1045.455000 2269.920000 1046.720000 2270.400000 ;
+ RECT 1041.790000 2264.480000 1042.790000 2264.960000 ;
+ RECT 1045.455000 2264.480000 1046.720000 2264.960000 ;
+ RECT 1041.790000 2259.040000 1042.790000 2259.520000 ;
+ RECT 1045.455000 2259.040000 1046.720000 2259.520000 ;
+ RECT 1041.790000 2253.600000 1042.790000 2254.080000 ;
+ RECT 1045.455000 2253.600000 1046.720000 2254.080000 ;
+ RECT 1225.620000 2237.280000 1226.720000 2237.760000 ;
+ RECT 1225.620000 2242.720000 1226.720000 2243.200000 ;
+ RECT 1238.430000 2237.280000 1239.430000 2237.760000 ;
+ RECT 1238.430000 2242.720000 1239.430000 2243.200000 ;
+ RECT 1238.430000 2226.400000 1239.430000 2226.880000 ;
+ RECT 1238.430000 2231.840000 1239.430000 2232.320000 ;
+ RECT 1225.620000 2231.840000 1226.720000 2232.320000 ;
+ RECT 1225.620000 2226.400000 1226.720000 2226.880000 ;
+ RECT 1225.620000 2215.520000 1226.720000 2216.000000 ;
+ RECT 1225.620000 2220.960000 1226.720000 2221.440000 ;
+ RECT 1238.430000 2215.520000 1239.430000 2216.000000 ;
+ RECT 1238.430000 2220.960000 1239.430000 2221.440000 ;
+ RECT 1238.430000 2204.640000 1239.430000 2205.120000 ;
+ RECT 1238.430000 2199.200000 1239.430000 2199.680000 ;
+ RECT 1238.430000 2210.080000 1239.430000 2210.560000 ;
+ RECT 1225.620000 2210.080000 1226.720000 2210.560000 ;
+ RECT 1225.620000 2204.640000 1226.720000 2205.120000 ;
+ RECT 1225.620000 2199.200000 1226.720000 2199.680000 ;
+ RECT 1180.620000 2226.400000 1181.720000 2226.880000 ;
+ RECT 1180.620000 2231.840000 1181.720000 2232.320000 ;
+ RECT 1180.620000 2237.280000 1181.720000 2237.760000 ;
+ RECT 1180.620000 2242.720000 1181.720000 2243.200000 ;
+ RECT 1180.620000 2199.200000 1181.720000 2199.680000 ;
+ RECT 1180.620000 2204.640000 1181.720000 2205.120000 ;
+ RECT 1180.620000 2210.080000 1181.720000 2210.560000 ;
+ RECT 1180.620000 2215.520000 1181.720000 2216.000000 ;
+ RECT 1180.620000 2220.960000 1181.720000 2221.440000 ;
+ RECT 1225.620000 2188.320000 1226.720000 2188.800000 ;
+ RECT 1225.620000 2193.760000 1226.720000 2194.240000 ;
+ RECT 1238.430000 2188.320000 1239.430000 2188.800000 ;
+ RECT 1238.430000 2193.760000 1239.430000 2194.240000 ;
+ RECT 1225.620000 2177.440000 1226.720000 2177.920000 ;
+ RECT 1225.620000 2182.880000 1226.720000 2183.360000 ;
+ RECT 1238.430000 2177.440000 1239.430000 2177.920000 ;
+ RECT 1238.430000 2182.880000 1239.430000 2183.360000 ;
+ RECT 1238.430000 2166.560000 1239.430000 2167.040000 ;
+ RECT 1238.430000 2161.120000 1239.430000 2161.600000 ;
+ RECT 1238.430000 2172.000000 1239.430000 2172.480000 ;
+ RECT 1225.620000 2172.000000 1226.720000 2172.480000 ;
+ RECT 1225.620000 2166.560000 1226.720000 2167.040000 ;
+ RECT 1225.620000 2161.120000 1226.720000 2161.600000 ;
+ RECT 1225.620000 2155.680000 1226.720000 2156.160000 ;
+ RECT 1238.430000 2155.680000 1239.430000 2156.160000 ;
+ RECT 1180.620000 2177.440000 1181.720000 2177.920000 ;
+ RECT 1180.620000 2182.880000 1181.720000 2183.360000 ;
+ RECT 1180.620000 2188.320000 1181.720000 2188.800000 ;
+ RECT 1180.620000 2193.760000 1181.720000 2194.240000 ;
+ RECT 1180.620000 2155.680000 1181.720000 2156.160000 ;
+ RECT 1180.620000 2161.120000 1181.720000 2161.600000 ;
+ RECT 1180.620000 2166.560000 1181.720000 2167.040000 ;
+ RECT 1180.620000 2172.000000 1181.720000 2172.480000 ;
+ RECT 1135.620000 2226.400000 1136.720000 2226.880000 ;
+ RECT 1135.620000 2231.840000 1136.720000 2232.320000 ;
+ RECT 1135.620000 2237.280000 1136.720000 2237.760000 ;
+ RECT 1135.620000 2242.720000 1136.720000 2243.200000 ;
+ RECT 1090.620000 2226.400000 1091.720000 2226.880000 ;
+ RECT 1090.620000 2231.840000 1091.720000 2232.320000 ;
+ RECT 1090.620000 2237.280000 1091.720000 2237.760000 ;
+ RECT 1090.620000 2242.720000 1091.720000 2243.200000 ;
+ RECT 1135.620000 2199.200000 1136.720000 2199.680000 ;
+ RECT 1135.620000 2204.640000 1136.720000 2205.120000 ;
+ RECT 1135.620000 2210.080000 1136.720000 2210.560000 ;
+ RECT 1135.620000 2215.520000 1136.720000 2216.000000 ;
+ RECT 1135.620000 2220.960000 1136.720000 2221.440000 ;
+ RECT 1090.620000 2199.200000 1091.720000 2199.680000 ;
+ RECT 1090.620000 2204.640000 1091.720000 2205.120000 ;
+ RECT 1090.620000 2210.080000 1091.720000 2210.560000 ;
+ RECT 1090.620000 2215.520000 1091.720000 2216.000000 ;
+ RECT 1090.620000 2220.960000 1091.720000 2221.440000 ;
+ RECT 1041.790000 2242.720000 1042.790000 2243.200000 ;
+ RECT 1045.455000 2242.720000 1046.720000 2243.200000 ;
+ RECT 1041.790000 2237.280000 1042.790000 2237.760000 ;
+ RECT 1045.455000 2237.280000 1046.720000 2237.760000 ;
+ RECT 1041.790000 2231.840000 1042.790000 2232.320000 ;
+ RECT 1045.455000 2231.840000 1046.720000 2232.320000 ;
+ RECT 1041.790000 2226.400000 1042.790000 2226.880000 ;
+ RECT 1045.455000 2226.400000 1046.720000 2226.880000 ;
+ RECT 1041.790000 2220.960000 1042.790000 2221.440000 ;
+ RECT 1045.455000 2220.960000 1046.720000 2221.440000 ;
+ RECT 1041.790000 2215.520000 1042.790000 2216.000000 ;
+ RECT 1045.455000 2215.520000 1046.720000 2216.000000 ;
+ RECT 1041.790000 2204.640000 1042.790000 2205.120000 ;
+ RECT 1045.455000 2204.640000 1046.720000 2205.120000 ;
+ RECT 1041.790000 2210.080000 1042.790000 2210.560000 ;
+ RECT 1045.455000 2210.080000 1046.720000 2210.560000 ;
+ RECT 1041.790000 2199.200000 1042.790000 2199.680000 ;
+ RECT 1045.455000 2199.200000 1046.720000 2199.680000 ;
+ RECT 1135.620000 2177.440000 1136.720000 2177.920000 ;
+ RECT 1135.620000 2182.880000 1136.720000 2183.360000 ;
+ RECT 1135.620000 2188.320000 1136.720000 2188.800000 ;
+ RECT 1135.620000 2193.760000 1136.720000 2194.240000 ;
+ RECT 1090.620000 2177.440000 1091.720000 2177.920000 ;
+ RECT 1090.620000 2182.880000 1091.720000 2183.360000 ;
+ RECT 1090.620000 2188.320000 1091.720000 2188.800000 ;
+ RECT 1090.620000 2193.760000 1091.720000 2194.240000 ;
+ RECT 1135.620000 2155.680000 1136.720000 2156.160000 ;
+ RECT 1135.620000 2161.120000 1136.720000 2161.600000 ;
+ RECT 1135.620000 2166.560000 1136.720000 2167.040000 ;
+ RECT 1135.620000 2172.000000 1136.720000 2172.480000 ;
+ RECT 1090.620000 2155.680000 1091.720000 2156.160000 ;
+ RECT 1090.620000 2161.120000 1091.720000 2161.600000 ;
+ RECT 1090.620000 2166.560000 1091.720000 2167.040000 ;
+ RECT 1090.620000 2172.000000 1091.720000 2172.480000 ;
+ RECT 1041.790000 2193.760000 1042.790000 2194.240000 ;
+ RECT 1045.455000 2193.760000 1046.720000 2194.240000 ;
+ RECT 1041.790000 2188.320000 1042.790000 2188.800000 ;
+ RECT 1045.455000 2188.320000 1046.720000 2188.800000 ;
+ RECT 1041.790000 2182.880000 1042.790000 2183.360000 ;
+ RECT 1045.455000 2182.880000 1046.720000 2183.360000 ;
+ RECT 1041.790000 2177.440000 1042.790000 2177.920000 ;
+ RECT 1045.455000 2177.440000 1046.720000 2177.920000 ;
+ RECT 1041.790000 2172.000000 1042.790000 2172.480000 ;
+ RECT 1045.455000 2172.000000 1046.720000 2172.480000 ;
+ RECT 1041.790000 2161.120000 1042.790000 2161.600000 ;
+ RECT 1045.455000 2161.120000 1046.720000 2161.600000 ;
+ RECT 1041.790000 2166.560000 1042.790000 2167.040000 ;
+ RECT 1045.455000 2166.560000 1046.720000 2167.040000 ;
+ RECT 1041.790000 2155.680000 1042.790000 2156.160000 ;
+ RECT 1045.455000 2155.680000 1046.720000 2156.160000 ;
+ RECT 1180.620000 2248.160000 1181.720000 2248.640000 ;
+ RECT 1225.620000 2248.160000 1226.720000 2248.640000 ;
+ RECT 1238.430000 2248.160000 1239.430000 2248.640000 ;
+ RECT 1090.620000 2248.160000 1091.720000 2248.640000 ;
+ RECT 1135.620000 2248.160000 1136.720000 2248.640000 ;
+ RECT 1041.790000 2248.160000 1042.790000 2248.640000 ;
+ RECT 1045.455000 2248.160000 1046.720000 2248.640000 ;
+ RECT 1040.560000 2344.920000 1240.660000 2345.920000 ;
+ RECT 1040.560000 2149.350000 1240.660000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 2148.100000 1042.790000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 2347.360000 1042.790000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 2148.100000 1239.430000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 2347.360000 1239.430000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2149.350000 1041.560000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2149.350000 1240.660000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2344.920000 1041.560000 2345.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2344.920000 1240.660000 2345.920000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 2140.380000 1046.720000 2140.860000 ;
+ RECT 1045.455000 2129.500000 1046.720000 2129.980000 ;
+ RECT 1045.455000 2134.940000 1046.720000 2135.420000 ;
+ RECT 1045.455000 2124.060000 1046.720000 2124.540000 ;
+ RECT 1045.455000 2118.620000 1046.720000 2119.100000 ;
+ RECT 1045.455000 2113.180000 1046.720000 2113.660000 ;
+ RECT 1045.455000 2107.740000 1046.720000 2108.220000 ;
+ RECT 1045.455000 2102.300000 1046.720000 2102.780000 ;
+ RECT 1045.455000 2096.860000 1046.720000 2097.340000 ;
+ RECT 1045.455000 2085.980000 1046.720000 2086.460000 ;
+ RECT 1045.455000 2091.420000 1046.720000 2091.900000 ;
+ RECT 1045.455000 2080.540000 1046.720000 2081.020000 ;
+ RECT 1045.455000 2075.100000 1046.720000 2075.580000 ;
+ RECT 1045.455000 2069.660000 1046.720000 2070.140000 ;
+ RECT 1045.455000 2064.220000 1046.720000 2064.700000 ;
+ RECT 1045.455000 2058.780000 1046.720000 2059.260000 ;
+ RECT 1045.455000 2053.340000 1046.720000 2053.820000 ;
+ RECT 1045.455000 2042.460000 1046.720000 2042.940000 ;
+ RECT 1045.455000 2037.020000 1046.720000 2037.500000 ;
+ RECT 1045.455000 2031.580000 1046.720000 2032.060000 ;
+ RECT 1045.455000 2026.140000 1046.720000 2026.620000 ;
+ RECT 1045.455000 2020.700000 1046.720000 2021.180000 ;
+ RECT 1045.455000 2015.260000 1046.720000 2015.740000 ;
+ RECT 1045.455000 2004.380000 1046.720000 2004.860000 ;
+ RECT 1045.455000 2009.820000 1046.720000 2010.300000 ;
+ RECT 1045.455000 1998.940000 1046.720000 1999.420000 ;
+ RECT 1045.455000 1993.500000 1046.720000 1993.980000 ;
+ RECT 1045.455000 1988.060000 1046.720000 1988.540000 ;
+ RECT 1045.455000 1982.620000 1046.720000 1983.100000 ;
+ RECT 1045.455000 1977.180000 1046.720000 1977.660000 ;
+ RECT 1045.455000 1971.740000 1046.720000 1972.220000 ;
+ RECT 1045.455000 1960.860000 1046.720000 1961.340000 ;
+ RECT 1045.455000 1966.300000 1046.720000 1966.780000 ;
+ RECT 1045.455000 1955.420000 1046.720000 1955.900000 ;
+ RECT 1045.455000 2047.900000 1046.720000 2048.380000 ;
+ RECT 1225.620000 1949.090000 1226.720000 2145.660000 ;
+ RECT 1180.620000 1949.090000 1181.720000 2145.660000 ;
+ RECT 1238.430000 1947.840000 1239.430000 2148.100000 ;
+ RECT 1135.620000 1949.090000 1136.720000 2145.660000 ;
+ RECT 1090.620000 1949.090000 1091.720000 2145.660000 ;
+ RECT 1045.620000 1949.090000 1046.720000 2145.660000 ;
+ RECT 1041.790000 1947.840000 1042.790000 2148.100000 ;
+ LAYER met3 ;
+ RECT 1225.620000 2140.380000 1226.720000 2140.860000 ;
+ RECT 1238.430000 2140.380000 1239.430000 2140.860000 ;
+ RECT 1238.430000 2129.500000 1239.430000 2129.980000 ;
+ RECT 1238.430000 2124.060000 1239.430000 2124.540000 ;
+ RECT 1238.430000 2134.940000 1239.430000 2135.420000 ;
+ RECT 1225.620000 2134.940000 1226.720000 2135.420000 ;
+ RECT 1225.620000 2129.500000 1226.720000 2129.980000 ;
+ RECT 1225.620000 2124.060000 1226.720000 2124.540000 ;
+ RECT 1225.620000 2113.180000 1226.720000 2113.660000 ;
+ RECT 1225.620000 2118.620000 1226.720000 2119.100000 ;
+ RECT 1238.430000 2113.180000 1239.430000 2113.660000 ;
+ RECT 1238.430000 2118.620000 1239.430000 2119.100000 ;
+ RECT 1225.620000 2102.300000 1226.720000 2102.780000 ;
+ RECT 1225.620000 2107.740000 1226.720000 2108.220000 ;
+ RECT 1238.430000 2102.300000 1239.430000 2102.780000 ;
+ RECT 1238.430000 2107.740000 1239.430000 2108.220000 ;
+ RECT 1180.620000 2124.060000 1181.720000 2124.540000 ;
+ RECT 1180.620000 2129.500000 1181.720000 2129.980000 ;
+ RECT 1180.620000 2134.940000 1181.720000 2135.420000 ;
+ RECT 1180.620000 2140.380000 1181.720000 2140.860000 ;
+ RECT 1180.620000 2107.740000 1181.720000 2108.220000 ;
+ RECT 1180.620000 2102.300000 1181.720000 2102.780000 ;
+ RECT 1180.620000 2113.180000 1181.720000 2113.660000 ;
+ RECT 1180.620000 2118.620000 1181.720000 2119.100000 ;
+ RECT 1238.430000 2091.420000 1239.430000 2091.900000 ;
+ RECT 1238.430000 2085.980000 1239.430000 2086.460000 ;
+ RECT 1238.430000 2096.860000 1239.430000 2097.340000 ;
+ RECT 1225.620000 2096.860000 1226.720000 2097.340000 ;
+ RECT 1225.620000 2091.420000 1226.720000 2091.900000 ;
+ RECT 1225.620000 2085.980000 1226.720000 2086.460000 ;
+ RECT 1225.620000 2075.100000 1226.720000 2075.580000 ;
+ RECT 1225.620000 2080.540000 1226.720000 2081.020000 ;
+ RECT 1238.430000 2075.100000 1239.430000 2075.580000 ;
+ RECT 1238.430000 2080.540000 1239.430000 2081.020000 ;
+ RECT 1238.430000 2064.220000 1239.430000 2064.700000 ;
+ RECT 1238.430000 2069.660000 1239.430000 2070.140000 ;
+ RECT 1225.620000 2069.660000 1226.720000 2070.140000 ;
+ RECT 1225.620000 2064.220000 1226.720000 2064.700000 ;
+ RECT 1225.620000 2053.340000 1226.720000 2053.820000 ;
+ RECT 1225.620000 2058.780000 1226.720000 2059.260000 ;
+ RECT 1238.430000 2053.340000 1239.430000 2053.820000 ;
+ RECT 1238.430000 2058.780000 1239.430000 2059.260000 ;
+ RECT 1180.620000 2075.100000 1181.720000 2075.580000 ;
+ RECT 1180.620000 2080.540000 1181.720000 2081.020000 ;
+ RECT 1180.620000 2085.980000 1181.720000 2086.460000 ;
+ RECT 1180.620000 2091.420000 1181.720000 2091.900000 ;
+ RECT 1180.620000 2096.860000 1181.720000 2097.340000 ;
+ RECT 1180.620000 2053.340000 1181.720000 2053.820000 ;
+ RECT 1180.620000 2058.780000 1181.720000 2059.260000 ;
+ RECT 1180.620000 2064.220000 1181.720000 2064.700000 ;
+ RECT 1180.620000 2069.660000 1181.720000 2070.140000 ;
+ RECT 1135.620000 2129.500000 1136.720000 2129.980000 ;
+ RECT 1135.620000 2124.060000 1136.720000 2124.540000 ;
+ RECT 1135.620000 2134.940000 1136.720000 2135.420000 ;
+ RECT 1135.620000 2140.380000 1136.720000 2140.860000 ;
+ RECT 1090.620000 2124.060000 1091.720000 2124.540000 ;
+ RECT 1090.620000 2129.500000 1091.720000 2129.980000 ;
+ RECT 1090.620000 2134.940000 1091.720000 2135.420000 ;
+ RECT 1090.620000 2140.380000 1091.720000 2140.860000 ;
+ RECT 1135.620000 2102.300000 1136.720000 2102.780000 ;
+ RECT 1135.620000 2107.740000 1136.720000 2108.220000 ;
+ RECT 1135.620000 2113.180000 1136.720000 2113.660000 ;
+ RECT 1135.620000 2118.620000 1136.720000 2119.100000 ;
+ RECT 1090.620000 2102.300000 1091.720000 2102.780000 ;
+ RECT 1090.620000 2107.740000 1091.720000 2108.220000 ;
+ RECT 1090.620000 2113.180000 1091.720000 2113.660000 ;
+ RECT 1090.620000 2118.620000 1091.720000 2119.100000 ;
+ RECT 1041.790000 2140.380000 1042.790000 2140.860000 ;
+ RECT 1045.455000 2140.380000 1046.720000 2140.860000 ;
+ RECT 1041.790000 2129.500000 1042.790000 2129.980000 ;
+ RECT 1045.455000 2129.500000 1046.720000 2129.980000 ;
+ RECT 1041.790000 2134.940000 1042.790000 2135.420000 ;
+ RECT 1045.455000 2134.940000 1046.720000 2135.420000 ;
+ RECT 1041.790000 2124.060000 1042.790000 2124.540000 ;
+ RECT 1045.455000 2124.060000 1046.720000 2124.540000 ;
+ RECT 1041.790000 2118.620000 1042.790000 2119.100000 ;
+ RECT 1045.455000 2118.620000 1046.720000 2119.100000 ;
+ RECT 1041.790000 2113.180000 1042.790000 2113.660000 ;
+ RECT 1045.455000 2113.180000 1046.720000 2113.660000 ;
+ RECT 1041.790000 2107.740000 1042.790000 2108.220000 ;
+ RECT 1045.455000 2107.740000 1046.720000 2108.220000 ;
+ RECT 1041.790000 2102.300000 1042.790000 2102.780000 ;
+ RECT 1045.455000 2102.300000 1046.720000 2102.780000 ;
+ RECT 1135.620000 2075.100000 1136.720000 2075.580000 ;
+ RECT 1135.620000 2080.540000 1136.720000 2081.020000 ;
+ RECT 1135.620000 2085.980000 1136.720000 2086.460000 ;
+ RECT 1135.620000 2091.420000 1136.720000 2091.900000 ;
+ RECT 1135.620000 2096.860000 1136.720000 2097.340000 ;
+ RECT 1090.620000 2075.100000 1091.720000 2075.580000 ;
+ RECT 1090.620000 2080.540000 1091.720000 2081.020000 ;
+ RECT 1090.620000 2085.980000 1091.720000 2086.460000 ;
+ RECT 1090.620000 2091.420000 1091.720000 2091.900000 ;
+ RECT 1090.620000 2096.860000 1091.720000 2097.340000 ;
+ RECT 1135.620000 2053.340000 1136.720000 2053.820000 ;
+ RECT 1135.620000 2058.780000 1136.720000 2059.260000 ;
+ RECT 1135.620000 2064.220000 1136.720000 2064.700000 ;
+ RECT 1135.620000 2069.660000 1136.720000 2070.140000 ;
+ RECT 1090.620000 2053.340000 1091.720000 2053.820000 ;
+ RECT 1090.620000 2058.780000 1091.720000 2059.260000 ;
+ RECT 1090.620000 2064.220000 1091.720000 2064.700000 ;
+ RECT 1090.620000 2069.660000 1091.720000 2070.140000 ;
+ RECT 1041.790000 2096.860000 1042.790000 2097.340000 ;
+ RECT 1045.455000 2096.860000 1046.720000 2097.340000 ;
+ RECT 1041.790000 2085.980000 1042.790000 2086.460000 ;
+ RECT 1045.455000 2085.980000 1046.720000 2086.460000 ;
+ RECT 1041.790000 2091.420000 1042.790000 2091.900000 ;
+ RECT 1045.455000 2091.420000 1046.720000 2091.900000 ;
+ RECT 1041.790000 2080.540000 1042.790000 2081.020000 ;
+ RECT 1045.455000 2080.540000 1046.720000 2081.020000 ;
+ RECT 1041.790000 2075.100000 1042.790000 2075.580000 ;
+ RECT 1045.455000 2075.100000 1046.720000 2075.580000 ;
+ RECT 1041.790000 2069.660000 1042.790000 2070.140000 ;
+ RECT 1045.455000 2069.660000 1046.720000 2070.140000 ;
+ RECT 1041.790000 2064.220000 1042.790000 2064.700000 ;
+ RECT 1045.455000 2064.220000 1046.720000 2064.700000 ;
+ RECT 1041.790000 2058.780000 1042.790000 2059.260000 ;
+ RECT 1045.455000 2058.780000 1046.720000 2059.260000 ;
+ RECT 1041.790000 2053.340000 1042.790000 2053.820000 ;
+ RECT 1045.455000 2053.340000 1046.720000 2053.820000 ;
+ RECT 1225.620000 2037.020000 1226.720000 2037.500000 ;
+ RECT 1225.620000 2042.460000 1226.720000 2042.940000 ;
+ RECT 1238.430000 2037.020000 1239.430000 2037.500000 ;
+ RECT 1238.430000 2042.460000 1239.430000 2042.940000 ;
+ RECT 1238.430000 2026.140000 1239.430000 2026.620000 ;
+ RECT 1238.430000 2031.580000 1239.430000 2032.060000 ;
+ RECT 1225.620000 2031.580000 1226.720000 2032.060000 ;
+ RECT 1225.620000 2026.140000 1226.720000 2026.620000 ;
+ RECT 1225.620000 2015.260000 1226.720000 2015.740000 ;
+ RECT 1225.620000 2020.700000 1226.720000 2021.180000 ;
+ RECT 1238.430000 2015.260000 1239.430000 2015.740000 ;
+ RECT 1238.430000 2020.700000 1239.430000 2021.180000 ;
+ RECT 1238.430000 2004.380000 1239.430000 2004.860000 ;
+ RECT 1238.430000 1998.940000 1239.430000 1999.420000 ;
+ RECT 1238.430000 2009.820000 1239.430000 2010.300000 ;
+ RECT 1225.620000 2009.820000 1226.720000 2010.300000 ;
+ RECT 1225.620000 2004.380000 1226.720000 2004.860000 ;
+ RECT 1225.620000 1998.940000 1226.720000 1999.420000 ;
+ RECT 1180.620000 2026.140000 1181.720000 2026.620000 ;
+ RECT 1180.620000 2031.580000 1181.720000 2032.060000 ;
+ RECT 1180.620000 2037.020000 1181.720000 2037.500000 ;
+ RECT 1180.620000 2042.460000 1181.720000 2042.940000 ;
+ RECT 1180.620000 1998.940000 1181.720000 1999.420000 ;
+ RECT 1180.620000 2004.380000 1181.720000 2004.860000 ;
+ RECT 1180.620000 2009.820000 1181.720000 2010.300000 ;
+ RECT 1180.620000 2015.260000 1181.720000 2015.740000 ;
+ RECT 1180.620000 2020.700000 1181.720000 2021.180000 ;
+ RECT 1225.620000 1988.060000 1226.720000 1988.540000 ;
+ RECT 1225.620000 1993.500000 1226.720000 1993.980000 ;
+ RECT 1238.430000 1988.060000 1239.430000 1988.540000 ;
+ RECT 1238.430000 1993.500000 1239.430000 1993.980000 ;
+ RECT 1225.620000 1977.180000 1226.720000 1977.660000 ;
+ RECT 1225.620000 1982.620000 1226.720000 1983.100000 ;
+ RECT 1238.430000 1977.180000 1239.430000 1977.660000 ;
+ RECT 1238.430000 1982.620000 1239.430000 1983.100000 ;
+ RECT 1238.430000 1966.300000 1239.430000 1966.780000 ;
+ RECT 1238.430000 1960.860000 1239.430000 1961.340000 ;
+ RECT 1238.430000 1971.740000 1239.430000 1972.220000 ;
+ RECT 1225.620000 1971.740000 1226.720000 1972.220000 ;
+ RECT 1225.620000 1966.300000 1226.720000 1966.780000 ;
+ RECT 1225.620000 1960.860000 1226.720000 1961.340000 ;
+ RECT 1225.620000 1955.420000 1226.720000 1955.900000 ;
+ RECT 1238.430000 1955.420000 1239.430000 1955.900000 ;
+ RECT 1180.620000 1977.180000 1181.720000 1977.660000 ;
+ RECT 1180.620000 1982.620000 1181.720000 1983.100000 ;
+ RECT 1180.620000 1988.060000 1181.720000 1988.540000 ;
+ RECT 1180.620000 1993.500000 1181.720000 1993.980000 ;
+ RECT 1180.620000 1955.420000 1181.720000 1955.900000 ;
+ RECT 1180.620000 1960.860000 1181.720000 1961.340000 ;
+ RECT 1180.620000 1966.300000 1181.720000 1966.780000 ;
+ RECT 1180.620000 1971.740000 1181.720000 1972.220000 ;
+ RECT 1135.620000 2026.140000 1136.720000 2026.620000 ;
+ RECT 1135.620000 2031.580000 1136.720000 2032.060000 ;
+ RECT 1135.620000 2037.020000 1136.720000 2037.500000 ;
+ RECT 1135.620000 2042.460000 1136.720000 2042.940000 ;
+ RECT 1090.620000 2026.140000 1091.720000 2026.620000 ;
+ RECT 1090.620000 2031.580000 1091.720000 2032.060000 ;
+ RECT 1090.620000 2037.020000 1091.720000 2037.500000 ;
+ RECT 1090.620000 2042.460000 1091.720000 2042.940000 ;
+ RECT 1135.620000 1998.940000 1136.720000 1999.420000 ;
+ RECT 1135.620000 2004.380000 1136.720000 2004.860000 ;
+ RECT 1135.620000 2009.820000 1136.720000 2010.300000 ;
+ RECT 1135.620000 2015.260000 1136.720000 2015.740000 ;
+ RECT 1135.620000 2020.700000 1136.720000 2021.180000 ;
+ RECT 1090.620000 1998.940000 1091.720000 1999.420000 ;
+ RECT 1090.620000 2004.380000 1091.720000 2004.860000 ;
+ RECT 1090.620000 2009.820000 1091.720000 2010.300000 ;
+ RECT 1090.620000 2015.260000 1091.720000 2015.740000 ;
+ RECT 1090.620000 2020.700000 1091.720000 2021.180000 ;
+ RECT 1041.790000 2042.460000 1042.790000 2042.940000 ;
+ RECT 1045.455000 2042.460000 1046.720000 2042.940000 ;
+ RECT 1041.790000 2037.020000 1042.790000 2037.500000 ;
+ RECT 1045.455000 2037.020000 1046.720000 2037.500000 ;
+ RECT 1041.790000 2031.580000 1042.790000 2032.060000 ;
+ RECT 1045.455000 2031.580000 1046.720000 2032.060000 ;
+ RECT 1041.790000 2026.140000 1042.790000 2026.620000 ;
+ RECT 1045.455000 2026.140000 1046.720000 2026.620000 ;
+ RECT 1041.790000 2020.700000 1042.790000 2021.180000 ;
+ RECT 1045.455000 2020.700000 1046.720000 2021.180000 ;
+ RECT 1041.790000 2015.260000 1042.790000 2015.740000 ;
+ RECT 1045.455000 2015.260000 1046.720000 2015.740000 ;
+ RECT 1041.790000 2004.380000 1042.790000 2004.860000 ;
+ RECT 1045.455000 2004.380000 1046.720000 2004.860000 ;
+ RECT 1041.790000 2009.820000 1042.790000 2010.300000 ;
+ RECT 1045.455000 2009.820000 1046.720000 2010.300000 ;
+ RECT 1041.790000 1998.940000 1042.790000 1999.420000 ;
+ RECT 1045.455000 1998.940000 1046.720000 1999.420000 ;
+ RECT 1135.620000 1977.180000 1136.720000 1977.660000 ;
+ RECT 1135.620000 1982.620000 1136.720000 1983.100000 ;
+ RECT 1135.620000 1988.060000 1136.720000 1988.540000 ;
+ RECT 1135.620000 1993.500000 1136.720000 1993.980000 ;
+ RECT 1090.620000 1977.180000 1091.720000 1977.660000 ;
+ RECT 1090.620000 1982.620000 1091.720000 1983.100000 ;
+ RECT 1090.620000 1988.060000 1091.720000 1988.540000 ;
+ RECT 1090.620000 1993.500000 1091.720000 1993.980000 ;
+ RECT 1135.620000 1955.420000 1136.720000 1955.900000 ;
+ RECT 1135.620000 1960.860000 1136.720000 1961.340000 ;
+ RECT 1135.620000 1966.300000 1136.720000 1966.780000 ;
+ RECT 1135.620000 1971.740000 1136.720000 1972.220000 ;
+ RECT 1090.620000 1955.420000 1091.720000 1955.900000 ;
+ RECT 1090.620000 1960.860000 1091.720000 1961.340000 ;
+ RECT 1090.620000 1966.300000 1091.720000 1966.780000 ;
+ RECT 1090.620000 1971.740000 1091.720000 1972.220000 ;
+ RECT 1041.790000 1993.500000 1042.790000 1993.980000 ;
+ RECT 1045.455000 1993.500000 1046.720000 1993.980000 ;
+ RECT 1041.790000 1988.060000 1042.790000 1988.540000 ;
+ RECT 1045.455000 1988.060000 1046.720000 1988.540000 ;
+ RECT 1041.790000 1982.620000 1042.790000 1983.100000 ;
+ RECT 1045.455000 1982.620000 1046.720000 1983.100000 ;
+ RECT 1041.790000 1977.180000 1042.790000 1977.660000 ;
+ RECT 1045.455000 1977.180000 1046.720000 1977.660000 ;
+ RECT 1041.790000 1971.740000 1042.790000 1972.220000 ;
+ RECT 1045.455000 1971.740000 1046.720000 1972.220000 ;
+ RECT 1041.790000 1960.860000 1042.790000 1961.340000 ;
+ RECT 1045.455000 1960.860000 1046.720000 1961.340000 ;
+ RECT 1041.790000 1966.300000 1042.790000 1966.780000 ;
+ RECT 1045.455000 1966.300000 1046.720000 1966.780000 ;
+ RECT 1041.790000 1955.420000 1042.790000 1955.900000 ;
+ RECT 1045.455000 1955.420000 1046.720000 1955.900000 ;
+ RECT 1180.620000 2047.900000 1181.720000 2048.380000 ;
+ RECT 1225.620000 2047.900000 1226.720000 2048.380000 ;
+ RECT 1238.430000 2047.900000 1239.430000 2048.380000 ;
+ RECT 1090.620000 2047.900000 1091.720000 2048.380000 ;
+ RECT 1135.620000 2047.900000 1136.720000 2048.380000 ;
+ RECT 1041.790000 2047.900000 1042.790000 2048.380000 ;
+ RECT 1045.455000 2047.900000 1046.720000 2048.380000 ;
+ RECT 1040.560000 2144.660000 1240.660000 2145.660000 ;
+ RECT 1040.560000 1949.090000 1240.660000 1950.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 1947.840000 1042.790000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 2147.100000 1042.790000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 1947.840000 1239.430000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 2147.100000 1239.430000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1949.090000 1041.560000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1949.090000 1240.660000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2144.660000 1041.560000 2145.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2144.660000 1240.660000 2145.660000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 1940.120000 1046.720000 1940.600000 ;
+ RECT 1045.455000 1929.240000 1046.720000 1929.720000 ;
+ RECT 1045.455000 1934.680000 1046.720000 1935.160000 ;
+ RECT 1045.455000 1923.800000 1046.720000 1924.280000 ;
+ RECT 1045.455000 1918.360000 1046.720000 1918.840000 ;
+ RECT 1045.455000 1912.920000 1046.720000 1913.400000 ;
+ RECT 1045.455000 1907.480000 1046.720000 1907.960000 ;
+ RECT 1045.455000 1902.040000 1046.720000 1902.520000 ;
+ RECT 1045.455000 1896.600000 1046.720000 1897.080000 ;
+ RECT 1045.455000 1885.720000 1046.720000 1886.200000 ;
+ RECT 1045.455000 1891.160000 1046.720000 1891.640000 ;
+ RECT 1045.455000 1880.280000 1046.720000 1880.760000 ;
+ RECT 1045.455000 1874.840000 1046.720000 1875.320000 ;
+ RECT 1045.455000 1869.400000 1046.720000 1869.880000 ;
+ RECT 1045.455000 1863.960000 1046.720000 1864.440000 ;
+ RECT 1045.455000 1858.520000 1046.720000 1859.000000 ;
+ RECT 1045.455000 1853.080000 1046.720000 1853.560000 ;
+ RECT 1045.455000 1842.200000 1046.720000 1842.680000 ;
+ RECT 1045.455000 1836.760000 1046.720000 1837.240000 ;
+ RECT 1045.455000 1831.320000 1046.720000 1831.800000 ;
+ RECT 1045.455000 1825.880000 1046.720000 1826.360000 ;
+ RECT 1045.455000 1820.440000 1046.720000 1820.920000 ;
+ RECT 1045.455000 1815.000000 1046.720000 1815.480000 ;
+ RECT 1045.455000 1804.120000 1046.720000 1804.600000 ;
+ RECT 1045.455000 1809.560000 1046.720000 1810.040000 ;
+ RECT 1045.455000 1798.680000 1046.720000 1799.160000 ;
+ RECT 1045.455000 1793.240000 1046.720000 1793.720000 ;
+ RECT 1045.455000 1787.800000 1046.720000 1788.280000 ;
+ RECT 1045.455000 1782.360000 1046.720000 1782.840000 ;
+ RECT 1045.455000 1776.920000 1046.720000 1777.400000 ;
+ RECT 1045.455000 1771.480000 1046.720000 1771.960000 ;
+ RECT 1045.455000 1760.600000 1046.720000 1761.080000 ;
+ RECT 1045.455000 1766.040000 1046.720000 1766.520000 ;
+ RECT 1045.455000 1755.160000 1046.720000 1755.640000 ;
+ RECT 1045.455000 1847.640000 1046.720000 1848.120000 ;
+ RECT 1225.620000 1748.830000 1226.720000 1945.400000 ;
+ RECT 1180.620000 1748.830000 1181.720000 1945.400000 ;
+ RECT 1238.430000 1747.580000 1239.430000 1947.840000 ;
+ RECT 1135.620000 1748.830000 1136.720000 1945.400000 ;
+ RECT 1090.620000 1748.830000 1091.720000 1945.400000 ;
+ RECT 1045.620000 1748.830000 1046.720000 1945.400000 ;
+ RECT 1041.790000 1747.580000 1042.790000 1947.840000 ;
+ LAYER met3 ;
+ RECT 1225.620000 1940.120000 1226.720000 1940.600000 ;
+ RECT 1238.430000 1940.120000 1239.430000 1940.600000 ;
+ RECT 1238.430000 1929.240000 1239.430000 1929.720000 ;
+ RECT 1238.430000 1923.800000 1239.430000 1924.280000 ;
+ RECT 1238.430000 1934.680000 1239.430000 1935.160000 ;
+ RECT 1225.620000 1934.680000 1226.720000 1935.160000 ;
+ RECT 1225.620000 1929.240000 1226.720000 1929.720000 ;
+ RECT 1225.620000 1923.800000 1226.720000 1924.280000 ;
+ RECT 1225.620000 1912.920000 1226.720000 1913.400000 ;
+ RECT 1225.620000 1918.360000 1226.720000 1918.840000 ;
+ RECT 1238.430000 1912.920000 1239.430000 1913.400000 ;
+ RECT 1238.430000 1918.360000 1239.430000 1918.840000 ;
+ RECT 1225.620000 1902.040000 1226.720000 1902.520000 ;
+ RECT 1225.620000 1907.480000 1226.720000 1907.960000 ;
+ RECT 1238.430000 1902.040000 1239.430000 1902.520000 ;
+ RECT 1238.430000 1907.480000 1239.430000 1907.960000 ;
+ RECT 1180.620000 1923.800000 1181.720000 1924.280000 ;
+ RECT 1180.620000 1929.240000 1181.720000 1929.720000 ;
+ RECT 1180.620000 1934.680000 1181.720000 1935.160000 ;
+ RECT 1180.620000 1940.120000 1181.720000 1940.600000 ;
+ RECT 1180.620000 1907.480000 1181.720000 1907.960000 ;
+ RECT 1180.620000 1902.040000 1181.720000 1902.520000 ;
+ RECT 1180.620000 1912.920000 1181.720000 1913.400000 ;
+ RECT 1180.620000 1918.360000 1181.720000 1918.840000 ;
+ RECT 1238.430000 1891.160000 1239.430000 1891.640000 ;
+ RECT 1238.430000 1885.720000 1239.430000 1886.200000 ;
+ RECT 1238.430000 1896.600000 1239.430000 1897.080000 ;
+ RECT 1225.620000 1896.600000 1226.720000 1897.080000 ;
+ RECT 1225.620000 1891.160000 1226.720000 1891.640000 ;
+ RECT 1225.620000 1885.720000 1226.720000 1886.200000 ;
+ RECT 1225.620000 1874.840000 1226.720000 1875.320000 ;
+ RECT 1225.620000 1880.280000 1226.720000 1880.760000 ;
+ RECT 1238.430000 1874.840000 1239.430000 1875.320000 ;
+ RECT 1238.430000 1880.280000 1239.430000 1880.760000 ;
+ RECT 1238.430000 1863.960000 1239.430000 1864.440000 ;
+ RECT 1238.430000 1869.400000 1239.430000 1869.880000 ;
+ RECT 1225.620000 1869.400000 1226.720000 1869.880000 ;
+ RECT 1225.620000 1863.960000 1226.720000 1864.440000 ;
+ RECT 1225.620000 1853.080000 1226.720000 1853.560000 ;
+ RECT 1225.620000 1858.520000 1226.720000 1859.000000 ;
+ RECT 1238.430000 1853.080000 1239.430000 1853.560000 ;
+ RECT 1238.430000 1858.520000 1239.430000 1859.000000 ;
+ RECT 1180.620000 1874.840000 1181.720000 1875.320000 ;
+ RECT 1180.620000 1880.280000 1181.720000 1880.760000 ;
+ RECT 1180.620000 1885.720000 1181.720000 1886.200000 ;
+ RECT 1180.620000 1891.160000 1181.720000 1891.640000 ;
+ RECT 1180.620000 1896.600000 1181.720000 1897.080000 ;
+ RECT 1180.620000 1853.080000 1181.720000 1853.560000 ;
+ RECT 1180.620000 1858.520000 1181.720000 1859.000000 ;
+ RECT 1180.620000 1863.960000 1181.720000 1864.440000 ;
+ RECT 1180.620000 1869.400000 1181.720000 1869.880000 ;
+ RECT 1135.620000 1929.240000 1136.720000 1929.720000 ;
+ RECT 1135.620000 1923.800000 1136.720000 1924.280000 ;
+ RECT 1135.620000 1934.680000 1136.720000 1935.160000 ;
+ RECT 1135.620000 1940.120000 1136.720000 1940.600000 ;
+ RECT 1090.620000 1923.800000 1091.720000 1924.280000 ;
+ RECT 1090.620000 1929.240000 1091.720000 1929.720000 ;
+ RECT 1090.620000 1934.680000 1091.720000 1935.160000 ;
+ RECT 1090.620000 1940.120000 1091.720000 1940.600000 ;
+ RECT 1135.620000 1902.040000 1136.720000 1902.520000 ;
+ RECT 1135.620000 1907.480000 1136.720000 1907.960000 ;
+ RECT 1135.620000 1912.920000 1136.720000 1913.400000 ;
+ RECT 1135.620000 1918.360000 1136.720000 1918.840000 ;
+ RECT 1090.620000 1902.040000 1091.720000 1902.520000 ;
+ RECT 1090.620000 1907.480000 1091.720000 1907.960000 ;
+ RECT 1090.620000 1912.920000 1091.720000 1913.400000 ;
+ RECT 1090.620000 1918.360000 1091.720000 1918.840000 ;
+ RECT 1041.790000 1940.120000 1042.790000 1940.600000 ;
+ RECT 1045.455000 1940.120000 1046.720000 1940.600000 ;
+ RECT 1041.790000 1929.240000 1042.790000 1929.720000 ;
+ RECT 1045.455000 1929.240000 1046.720000 1929.720000 ;
+ RECT 1041.790000 1934.680000 1042.790000 1935.160000 ;
+ RECT 1045.455000 1934.680000 1046.720000 1935.160000 ;
+ RECT 1041.790000 1923.800000 1042.790000 1924.280000 ;
+ RECT 1045.455000 1923.800000 1046.720000 1924.280000 ;
+ RECT 1041.790000 1918.360000 1042.790000 1918.840000 ;
+ RECT 1045.455000 1918.360000 1046.720000 1918.840000 ;
+ RECT 1041.790000 1912.920000 1042.790000 1913.400000 ;
+ RECT 1045.455000 1912.920000 1046.720000 1913.400000 ;
+ RECT 1041.790000 1907.480000 1042.790000 1907.960000 ;
+ RECT 1045.455000 1907.480000 1046.720000 1907.960000 ;
+ RECT 1041.790000 1902.040000 1042.790000 1902.520000 ;
+ RECT 1045.455000 1902.040000 1046.720000 1902.520000 ;
+ RECT 1135.620000 1874.840000 1136.720000 1875.320000 ;
+ RECT 1135.620000 1880.280000 1136.720000 1880.760000 ;
+ RECT 1135.620000 1885.720000 1136.720000 1886.200000 ;
+ RECT 1135.620000 1891.160000 1136.720000 1891.640000 ;
+ RECT 1135.620000 1896.600000 1136.720000 1897.080000 ;
+ RECT 1090.620000 1874.840000 1091.720000 1875.320000 ;
+ RECT 1090.620000 1880.280000 1091.720000 1880.760000 ;
+ RECT 1090.620000 1885.720000 1091.720000 1886.200000 ;
+ RECT 1090.620000 1891.160000 1091.720000 1891.640000 ;
+ RECT 1090.620000 1896.600000 1091.720000 1897.080000 ;
+ RECT 1135.620000 1853.080000 1136.720000 1853.560000 ;
+ RECT 1135.620000 1858.520000 1136.720000 1859.000000 ;
+ RECT 1135.620000 1863.960000 1136.720000 1864.440000 ;
+ RECT 1135.620000 1869.400000 1136.720000 1869.880000 ;
+ RECT 1090.620000 1853.080000 1091.720000 1853.560000 ;
+ RECT 1090.620000 1858.520000 1091.720000 1859.000000 ;
+ RECT 1090.620000 1863.960000 1091.720000 1864.440000 ;
+ RECT 1090.620000 1869.400000 1091.720000 1869.880000 ;
+ RECT 1041.790000 1896.600000 1042.790000 1897.080000 ;
+ RECT 1045.455000 1896.600000 1046.720000 1897.080000 ;
+ RECT 1041.790000 1885.720000 1042.790000 1886.200000 ;
+ RECT 1045.455000 1885.720000 1046.720000 1886.200000 ;
+ RECT 1041.790000 1891.160000 1042.790000 1891.640000 ;
+ RECT 1045.455000 1891.160000 1046.720000 1891.640000 ;
+ RECT 1041.790000 1880.280000 1042.790000 1880.760000 ;
+ RECT 1045.455000 1880.280000 1046.720000 1880.760000 ;
+ RECT 1041.790000 1874.840000 1042.790000 1875.320000 ;
+ RECT 1045.455000 1874.840000 1046.720000 1875.320000 ;
+ RECT 1041.790000 1869.400000 1042.790000 1869.880000 ;
+ RECT 1045.455000 1869.400000 1046.720000 1869.880000 ;
+ RECT 1041.790000 1863.960000 1042.790000 1864.440000 ;
+ RECT 1045.455000 1863.960000 1046.720000 1864.440000 ;
+ RECT 1041.790000 1858.520000 1042.790000 1859.000000 ;
+ RECT 1045.455000 1858.520000 1046.720000 1859.000000 ;
+ RECT 1041.790000 1853.080000 1042.790000 1853.560000 ;
+ RECT 1045.455000 1853.080000 1046.720000 1853.560000 ;
+ RECT 1225.620000 1836.760000 1226.720000 1837.240000 ;
+ RECT 1225.620000 1842.200000 1226.720000 1842.680000 ;
+ RECT 1238.430000 1836.760000 1239.430000 1837.240000 ;
+ RECT 1238.430000 1842.200000 1239.430000 1842.680000 ;
+ RECT 1238.430000 1825.880000 1239.430000 1826.360000 ;
+ RECT 1238.430000 1831.320000 1239.430000 1831.800000 ;
+ RECT 1225.620000 1831.320000 1226.720000 1831.800000 ;
+ RECT 1225.620000 1825.880000 1226.720000 1826.360000 ;
+ RECT 1225.620000 1815.000000 1226.720000 1815.480000 ;
+ RECT 1225.620000 1820.440000 1226.720000 1820.920000 ;
+ RECT 1238.430000 1815.000000 1239.430000 1815.480000 ;
+ RECT 1238.430000 1820.440000 1239.430000 1820.920000 ;
+ RECT 1238.430000 1804.120000 1239.430000 1804.600000 ;
+ RECT 1238.430000 1798.680000 1239.430000 1799.160000 ;
+ RECT 1238.430000 1809.560000 1239.430000 1810.040000 ;
+ RECT 1225.620000 1809.560000 1226.720000 1810.040000 ;
+ RECT 1225.620000 1804.120000 1226.720000 1804.600000 ;
+ RECT 1225.620000 1798.680000 1226.720000 1799.160000 ;
+ RECT 1180.620000 1825.880000 1181.720000 1826.360000 ;
+ RECT 1180.620000 1831.320000 1181.720000 1831.800000 ;
+ RECT 1180.620000 1836.760000 1181.720000 1837.240000 ;
+ RECT 1180.620000 1842.200000 1181.720000 1842.680000 ;
+ RECT 1180.620000 1798.680000 1181.720000 1799.160000 ;
+ RECT 1180.620000 1804.120000 1181.720000 1804.600000 ;
+ RECT 1180.620000 1809.560000 1181.720000 1810.040000 ;
+ RECT 1180.620000 1815.000000 1181.720000 1815.480000 ;
+ RECT 1180.620000 1820.440000 1181.720000 1820.920000 ;
+ RECT 1225.620000 1787.800000 1226.720000 1788.280000 ;
+ RECT 1225.620000 1793.240000 1226.720000 1793.720000 ;
+ RECT 1238.430000 1787.800000 1239.430000 1788.280000 ;
+ RECT 1238.430000 1793.240000 1239.430000 1793.720000 ;
+ RECT 1225.620000 1776.920000 1226.720000 1777.400000 ;
+ RECT 1225.620000 1782.360000 1226.720000 1782.840000 ;
+ RECT 1238.430000 1776.920000 1239.430000 1777.400000 ;
+ RECT 1238.430000 1782.360000 1239.430000 1782.840000 ;
+ RECT 1238.430000 1766.040000 1239.430000 1766.520000 ;
+ RECT 1238.430000 1760.600000 1239.430000 1761.080000 ;
+ RECT 1238.430000 1771.480000 1239.430000 1771.960000 ;
+ RECT 1225.620000 1771.480000 1226.720000 1771.960000 ;
+ RECT 1225.620000 1766.040000 1226.720000 1766.520000 ;
+ RECT 1225.620000 1760.600000 1226.720000 1761.080000 ;
+ RECT 1225.620000 1755.160000 1226.720000 1755.640000 ;
+ RECT 1238.430000 1755.160000 1239.430000 1755.640000 ;
+ RECT 1180.620000 1776.920000 1181.720000 1777.400000 ;
+ RECT 1180.620000 1782.360000 1181.720000 1782.840000 ;
+ RECT 1180.620000 1787.800000 1181.720000 1788.280000 ;
+ RECT 1180.620000 1793.240000 1181.720000 1793.720000 ;
+ RECT 1180.620000 1755.160000 1181.720000 1755.640000 ;
+ RECT 1180.620000 1760.600000 1181.720000 1761.080000 ;
+ RECT 1180.620000 1766.040000 1181.720000 1766.520000 ;
+ RECT 1180.620000 1771.480000 1181.720000 1771.960000 ;
+ RECT 1135.620000 1825.880000 1136.720000 1826.360000 ;
+ RECT 1135.620000 1831.320000 1136.720000 1831.800000 ;
+ RECT 1135.620000 1836.760000 1136.720000 1837.240000 ;
+ RECT 1135.620000 1842.200000 1136.720000 1842.680000 ;
+ RECT 1090.620000 1825.880000 1091.720000 1826.360000 ;
+ RECT 1090.620000 1831.320000 1091.720000 1831.800000 ;
+ RECT 1090.620000 1836.760000 1091.720000 1837.240000 ;
+ RECT 1090.620000 1842.200000 1091.720000 1842.680000 ;
+ RECT 1135.620000 1798.680000 1136.720000 1799.160000 ;
+ RECT 1135.620000 1804.120000 1136.720000 1804.600000 ;
+ RECT 1135.620000 1809.560000 1136.720000 1810.040000 ;
+ RECT 1135.620000 1815.000000 1136.720000 1815.480000 ;
+ RECT 1135.620000 1820.440000 1136.720000 1820.920000 ;
+ RECT 1090.620000 1798.680000 1091.720000 1799.160000 ;
+ RECT 1090.620000 1804.120000 1091.720000 1804.600000 ;
+ RECT 1090.620000 1809.560000 1091.720000 1810.040000 ;
+ RECT 1090.620000 1815.000000 1091.720000 1815.480000 ;
+ RECT 1090.620000 1820.440000 1091.720000 1820.920000 ;
+ RECT 1041.790000 1842.200000 1042.790000 1842.680000 ;
+ RECT 1045.455000 1842.200000 1046.720000 1842.680000 ;
+ RECT 1041.790000 1836.760000 1042.790000 1837.240000 ;
+ RECT 1045.455000 1836.760000 1046.720000 1837.240000 ;
+ RECT 1041.790000 1831.320000 1042.790000 1831.800000 ;
+ RECT 1045.455000 1831.320000 1046.720000 1831.800000 ;
+ RECT 1041.790000 1825.880000 1042.790000 1826.360000 ;
+ RECT 1045.455000 1825.880000 1046.720000 1826.360000 ;
+ RECT 1041.790000 1820.440000 1042.790000 1820.920000 ;
+ RECT 1045.455000 1820.440000 1046.720000 1820.920000 ;
+ RECT 1041.790000 1815.000000 1042.790000 1815.480000 ;
+ RECT 1045.455000 1815.000000 1046.720000 1815.480000 ;
+ RECT 1041.790000 1804.120000 1042.790000 1804.600000 ;
+ RECT 1045.455000 1804.120000 1046.720000 1804.600000 ;
+ RECT 1041.790000 1809.560000 1042.790000 1810.040000 ;
+ RECT 1045.455000 1809.560000 1046.720000 1810.040000 ;
+ RECT 1041.790000 1798.680000 1042.790000 1799.160000 ;
+ RECT 1045.455000 1798.680000 1046.720000 1799.160000 ;
+ RECT 1135.620000 1776.920000 1136.720000 1777.400000 ;
+ RECT 1135.620000 1782.360000 1136.720000 1782.840000 ;
+ RECT 1135.620000 1787.800000 1136.720000 1788.280000 ;
+ RECT 1135.620000 1793.240000 1136.720000 1793.720000 ;
+ RECT 1090.620000 1776.920000 1091.720000 1777.400000 ;
+ RECT 1090.620000 1782.360000 1091.720000 1782.840000 ;
+ RECT 1090.620000 1787.800000 1091.720000 1788.280000 ;
+ RECT 1090.620000 1793.240000 1091.720000 1793.720000 ;
+ RECT 1135.620000 1755.160000 1136.720000 1755.640000 ;
+ RECT 1135.620000 1760.600000 1136.720000 1761.080000 ;
+ RECT 1135.620000 1766.040000 1136.720000 1766.520000 ;
+ RECT 1135.620000 1771.480000 1136.720000 1771.960000 ;
+ RECT 1090.620000 1755.160000 1091.720000 1755.640000 ;
+ RECT 1090.620000 1760.600000 1091.720000 1761.080000 ;
+ RECT 1090.620000 1766.040000 1091.720000 1766.520000 ;
+ RECT 1090.620000 1771.480000 1091.720000 1771.960000 ;
+ RECT 1041.790000 1793.240000 1042.790000 1793.720000 ;
+ RECT 1045.455000 1793.240000 1046.720000 1793.720000 ;
+ RECT 1041.790000 1787.800000 1042.790000 1788.280000 ;
+ RECT 1045.455000 1787.800000 1046.720000 1788.280000 ;
+ RECT 1041.790000 1782.360000 1042.790000 1782.840000 ;
+ RECT 1045.455000 1782.360000 1046.720000 1782.840000 ;
+ RECT 1041.790000 1776.920000 1042.790000 1777.400000 ;
+ RECT 1045.455000 1776.920000 1046.720000 1777.400000 ;
+ RECT 1041.790000 1771.480000 1042.790000 1771.960000 ;
+ RECT 1045.455000 1771.480000 1046.720000 1771.960000 ;
+ RECT 1041.790000 1760.600000 1042.790000 1761.080000 ;
+ RECT 1045.455000 1760.600000 1046.720000 1761.080000 ;
+ RECT 1041.790000 1766.040000 1042.790000 1766.520000 ;
+ RECT 1045.455000 1766.040000 1046.720000 1766.520000 ;
+ RECT 1041.790000 1755.160000 1042.790000 1755.640000 ;
+ RECT 1045.455000 1755.160000 1046.720000 1755.640000 ;
+ RECT 1180.620000 1847.640000 1181.720000 1848.120000 ;
+ RECT 1225.620000 1847.640000 1226.720000 1848.120000 ;
+ RECT 1238.430000 1847.640000 1239.430000 1848.120000 ;
+ RECT 1090.620000 1847.640000 1091.720000 1848.120000 ;
+ RECT 1135.620000 1847.640000 1136.720000 1848.120000 ;
+ RECT 1041.790000 1847.640000 1042.790000 1848.120000 ;
+ RECT 1045.455000 1847.640000 1046.720000 1848.120000 ;
+ RECT 1040.560000 1944.400000 1240.660000 1945.400000 ;
+ RECT 1040.560000 1748.830000 1240.660000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 1747.580000 1042.790000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 1946.840000 1042.790000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 1747.580000 1239.430000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 1946.840000 1239.430000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1748.830000 1041.560000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1748.830000 1240.660000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1944.400000 1041.560000 1945.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1944.400000 1240.660000 1945.400000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1045.455000 1739.860000 1046.720000 1740.340000 ;
+ RECT 1045.455000 1728.980000 1046.720000 1729.460000 ;
+ RECT 1045.455000 1734.420000 1046.720000 1734.900000 ;
+ RECT 1045.455000 1723.540000 1046.720000 1724.020000 ;
+ RECT 1045.455000 1718.100000 1046.720000 1718.580000 ;
+ RECT 1045.455000 1712.660000 1046.720000 1713.140000 ;
+ RECT 1045.455000 1707.220000 1046.720000 1707.700000 ;
+ RECT 1045.455000 1701.780000 1046.720000 1702.260000 ;
+ RECT 1045.455000 1696.340000 1046.720000 1696.820000 ;
+ RECT 1045.455000 1685.460000 1046.720000 1685.940000 ;
+ RECT 1045.455000 1690.900000 1046.720000 1691.380000 ;
+ RECT 1045.455000 1680.020000 1046.720000 1680.500000 ;
+ RECT 1045.455000 1674.580000 1046.720000 1675.060000 ;
+ RECT 1045.455000 1669.140000 1046.720000 1669.620000 ;
+ RECT 1045.455000 1663.700000 1046.720000 1664.180000 ;
+ RECT 1045.455000 1658.260000 1046.720000 1658.740000 ;
+ RECT 1045.455000 1652.820000 1046.720000 1653.300000 ;
+ RECT 1045.455000 1641.940000 1046.720000 1642.420000 ;
+ RECT 1045.455000 1636.500000 1046.720000 1636.980000 ;
+ RECT 1045.455000 1631.060000 1046.720000 1631.540000 ;
+ RECT 1045.455000 1625.620000 1046.720000 1626.100000 ;
+ RECT 1045.455000 1620.180000 1046.720000 1620.660000 ;
+ RECT 1045.455000 1614.740000 1046.720000 1615.220000 ;
+ RECT 1045.455000 1603.860000 1046.720000 1604.340000 ;
+ RECT 1045.455000 1609.300000 1046.720000 1609.780000 ;
+ RECT 1045.455000 1598.420000 1046.720000 1598.900000 ;
+ RECT 1045.455000 1592.980000 1046.720000 1593.460000 ;
+ RECT 1045.455000 1587.540000 1046.720000 1588.020000 ;
+ RECT 1045.455000 1582.100000 1046.720000 1582.580000 ;
+ RECT 1045.455000 1576.660000 1046.720000 1577.140000 ;
+ RECT 1045.455000 1571.220000 1046.720000 1571.700000 ;
+ RECT 1045.455000 1560.340000 1046.720000 1560.820000 ;
+ RECT 1045.455000 1565.780000 1046.720000 1566.260000 ;
+ RECT 1045.455000 1554.900000 1046.720000 1555.380000 ;
+ RECT 1045.455000 1647.380000 1046.720000 1647.860000 ;
+ RECT 1225.620000 1548.570000 1226.720000 1745.140000 ;
+ RECT 1180.620000 1548.570000 1181.720000 1745.140000 ;
+ RECT 1238.430000 1547.320000 1239.430000 1747.580000 ;
+ RECT 1135.620000 1548.570000 1136.720000 1745.140000 ;
+ RECT 1090.620000 1548.570000 1091.720000 1745.140000 ;
+ RECT 1045.620000 1548.570000 1046.720000 1745.140000 ;
+ RECT 1041.790000 1547.320000 1042.790000 1747.580000 ;
+ LAYER met3 ;
+ RECT 1225.620000 1739.860000 1226.720000 1740.340000 ;
+ RECT 1238.430000 1739.860000 1239.430000 1740.340000 ;
+ RECT 1238.430000 1728.980000 1239.430000 1729.460000 ;
+ RECT 1238.430000 1723.540000 1239.430000 1724.020000 ;
+ RECT 1238.430000 1734.420000 1239.430000 1734.900000 ;
+ RECT 1225.620000 1734.420000 1226.720000 1734.900000 ;
+ RECT 1225.620000 1728.980000 1226.720000 1729.460000 ;
+ RECT 1225.620000 1723.540000 1226.720000 1724.020000 ;
+ RECT 1225.620000 1712.660000 1226.720000 1713.140000 ;
+ RECT 1225.620000 1718.100000 1226.720000 1718.580000 ;
+ RECT 1238.430000 1712.660000 1239.430000 1713.140000 ;
+ RECT 1238.430000 1718.100000 1239.430000 1718.580000 ;
+ RECT 1225.620000 1701.780000 1226.720000 1702.260000 ;
+ RECT 1225.620000 1707.220000 1226.720000 1707.700000 ;
+ RECT 1238.430000 1701.780000 1239.430000 1702.260000 ;
+ RECT 1238.430000 1707.220000 1239.430000 1707.700000 ;
+ RECT 1180.620000 1723.540000 1181.720000 1724.020000 ;
+ RECT 1180.620000 1728.980000 1181.720000 1729.460000 ;
+ RECT 1180.620000 1734.420000 1181.720000 1734.900000 ;
+ RECT 1180.620000 1739.860000 1181.720000 1740.340000 ;
+ RECT 1180.620000 1707.220000 1181.720000 1707.700000 ;
+ RECT 1180.620000 1701.780000 1181.720000 1702.260000 ;
+ RECT 1180.620000 1712.660000 1181.720000 1713.140000 ;
+ RECT 1180.620000 1718.100000 1181.720000 1718.580000 ;
+ RECT 1238.430000 1690.900000 1239.430000 1691.380000 ;
+ RECT 1238.430000 1685.460000 1239.430000 1685.940000 ;
+ RECT 1238.430000 1696.340000 1239.430000 1696.820000 ;
+ RECT 1225.620000 1696.340000 1226.720000 1696.820000 ;
+ RECT 1225.620000 1690.900000 1226.720000 1691.380000 ;
+ RECT 1225.620000 1685.460000 1226.720000 1685.940000 ;
+ RECT 1225.620000 1674.580000 1226.720000 1675.060000 ;
+ RECT 1225.620000 1680.020000 1226.720000 1680.500000 ;
+ RECT 1238.430000 1674.580000 1239.430000 1675.060000 ;
+ RECT 1238.430000 1680.020000 1239.430000 1680.500000 ;
+ RECT 1238.430000 1663.700000 1239.430000 1664.180000 ;
+ RECT 1238.430000 1669.140000 1239.430000 1669.620000 ;
+ RECT 1225.620000 1669.140000 1226.720000 1669.620000 ;
+ RECT 1225.620000 1663.700000 1226.720000 1664.180000 ;
+ RECT 1225.620000 1652.820000 1226.720000 1653.300000 ;
+ RECT 1225.620000 1658.260000 1226.720000 1658.740000 ;
+ RECT 1238.430000 1652.820000 1239.430000 1653.300000 ;
+ RECT 1238.430000 1658.260000 1239.430000 1658.740000 ;
+ RECT 1180.620000 1674.580000 1181.720000 1675.060000 ;
+ RECT 1180.620000 1680.020000 1181.720000 1680.500000 ;
+ RECT 1180.620000 1685.460000 1181.720000 1685.940000 ;
+ RECT 1180.620000 1690.900000 1181.720000 1691.380000 ;
+ RECT 1180.620000 1696.340000 1181.720000 1696.820000 ;
+ RECT 1180.620000 1652.820000 1181.720000 1653.300000 ;
+ RECT 1180.620000 1658.260000 1181.720000 1658.740000 ;
+ RECT 1180.620000 1663.700000 1181.720000 1664.180000 ;
+ RECT 1180.620000 1669.140000 1181.720000 1669.620000 ;
+ RECT 1135.620000 1728.980000 1136.720000 1729.460000 ;
+ RECT 1135.620000 1723.540000 1136.720000 1724.020000 ;
+ RECT 1135.620000 1734.420000 1136.720000 1734.900000 ;
+ RECT 1135.620000 1739.860000 1136.720000 1740.340000 ;
+ RECT 1090.620000 1723.540000 1091.720000 1724.020000 ;
+ RECT 1090.620000 1728.980000 1091.720000 1729.460000 ;
+ RECT 1090.620000 1734.420000 1091.720000 1734.900000 ;
+ RECT 1090.620000 1739.860000 1091.720000 1740.340000 ;
+ RECT 1135.620000 1701.780000 1136.720000 1702.260000 ;
+ RECT 1135.620000 1707.220000 1136.720000 1707.700000 ;
+ RECT 1135.620000 1712.660000 1136.720000 1713.140000 ;
+ RECT 1135.620000 1718.100000 1136.720000 1718.580000 ;
+ RECT 1090.620000 1701.780000 1091.720000 1702.260000 ;
+ RECT 1090.620000 1707.220000 1091.720000 1707.700000 ;
+ RECT 1090.620000 1712.660000 1091.720000 1713.140000 ;
+ RECT 1090.620000 1718.100000 1091.720000 1718.580000 ;
+ RECT 1041.790000 1739.860000 1042.790000 1740.340000 ;
+ RECT 1045.455000 1739.860000 1046.720000 1740.340000 ;
+ RECT 1041.790000 1728.980000 1042.790000 1729.460000 ;
+ RECT 1045.455000 1728.980000 1046.720000 1729.460000 ;
+ RECT 1041.790000 1734.420000 1042.790000 1734.900000 ;
+ RECT 1045.455000 1734.420000 1046.720000 1734.900000 ;
+ RECT 1041.790000 1723.540000 1042.790000 1724.020000 ;
+ RECT 1045.455000 1723.540000 1046.720000 1724.020000 ;
+ RECT 1041.790000 1718.100000 1042.790000 1718.580000 ;
+ RECT 1045.455000 1718.100000 1046.720000 1718.580000 ;
+ RECT 1041.790000 1712.660000 1042.790000 1713.140000 ;
+ RECT 1045.455000 1712.660000 1046.720000 1713.140000 ;
+ RECT 1041.790000 1707.220000 1042.790000 1707.700000 ;
+ RECT 1045.455000 1707.220000 1046.720000 1707.700000 ;
+ RECT 1041.790000 1701.780000 1042.790000 1702.260000 ;
+ RECT 1045.455000 1701.780000 1046.720000 1702.260000 ;
+ RECT 1135.620000 1674.580000 1136.720000 1675.060000 ;
+ RECT 1135.620000 1680.020000 1136.720000 1680.500000 ;
+ RECT 1135.620000 1685.460000 1136.720000 1685.940000 ;
+ RECT 1135.620000 1690.900000 1136.720000 1691.380000 ;
+ RECT 1135.620000 1696.340000 1136.720000 1696.820000 ;
+ RECT 1090.620000 1674.580000 1091.720000 1675.060000 ;
+ RECT 1090.620000 1680.020000 1091.720000 1680.500000 ;
+ RECT 1090.620000 1685.460000 1091.720000 1685.940000 ;
+ RECT 1090.620000 1690.900000 1091.720000 1691.380000 ;
+ RECT 1090.620000 1696.340000 1091.720000 1696.820000 ;
+ RECT 1135.620000 1652.820000 1136.720000 1653.300000 ;
+ RECT 1135.620000 1658.260000 1136.720000 1658.740000 ;
+ RECT 1135.620000 1663.700000 1136.720000 1664.180000 ;
+ RECT 1135.620000 1669.140000 1136.720000 1669.620000 ;
+ RECT 1090.620000 1652.820000 1091.720000 1653.300000 ;
+ RECT 1090.620000 1658.260000 1091.720000 1658.740000 ;
+ RECT 1090.620000 1663.700000 1091.720000 1664.180000 ;
+ RECT 1090.620000 1669.140000 1091.720000 1669.620000 ;
+ RECT 1041.790000 1696.340000 1042.790000 1696.820000 ;
+ RECT 1045.455000 1696.340000 1046.720000 1696.820000 ;
+ RECT 1041.790000 1685.460000 1042.790000 1685.940000 ;
+ RECT 1045.455000 1685.460000 1046.720000 1685.940000 ;
+ RECT 1041.790000 1690.900000 1042.790000 1691.380000 ;
+ RECT 1045.455000 1690.900000 1046.720000 1691.380000 ;
+ RECT 1041.790000 1680.020000 1042.790000 1680.500000 ;
+ RECT 1045.455000 1680.020000 1046.720000 1680.500000 ;
+ RECT 1041.790000 1674.580000 1042.790000 1675.060000 ;
+ RECT 1045.455000 1674.580000 1046.720000 1675.060000 ;
+ RECT 1041.790000 1669.140000 1042.790000 1669.620000 ;
+ RECT 1045.455000 1669.140000 1046.720000 1669.620000 ;
+ RECT 1041.790000 1663.700000 1042.790000 1664.180000 ;
+ RECT 1045.455000 1663.700000 1046.720000 1664.180000 ;
+ RECT 1041.790000 1658.260000 1042.790000 1658.740000 ;
+ RECT 1045.455000 1658.260000 1046.720000 1658.740000 ;
+ RECT 1041.790000 1652.820000 1042.790000 1653.300000 ;
+ RECT 1045.455000 1652.820000 1046.720000 1653.300000 ;
+ RECT 1225.620000 1636.500000 1226.720000 1636.980000 ;
+ RECT 1225.620000 1641.940000 1226.720000 1642.420000 ;
+ RECT 1238.430000 1636.500000 1239.430000 1636.980000 ;
+ RECT 1238.430000 1641.940000 1239.430000 1642.420000 ;
+ RECT 1238.430000 1625.620000 1239.430000 1626.100000 ;
+ RECT 1238.430000 1631.060000 1239.430000 1631.540000 ;
+ RECT 1225.620000 1631.060000 1226.720000 1631.540000 ;
+ RECT 1225.620000 1625.620000 1226.720000 1626.100000 ;
+ RECT 1225.620000 1614.740000 1226.720000 1615.220000 ;
+ RECT 1225.620000 1620.180000 1226.720000 1620.660000 ;
+ RECT 1238.430000 1614.740000 1239.430000 1615.220000 ;
+ RECT 1238.430000 1620.180000 1239.430000 1620.660000 ;
+ RECT 1238.430000 1603.860000 1239.430000 1604.340000 ;
+ RECT 1238.430000 1598.420000 1239.430000 1598.900000 ;
+ RECT 1238.430000 1609.300000 1239.430000 1609.780000 ;
+ RECT 1225.620000 1609.300000 1226.720000 1609.780000 ;
+ RECT 1225.620000 1603.860000 1226.720000 1604.340000 ;
+ RECT 1225.620000 1598.420000 1226.720000 1598.900000 ;
+ RECT 1180.620000 1625.620000 1181.720000 1626.100000 ;
+ RECT 1180.620000 1631.060000 1181.720000 1631.540000 ;
+ RECT 1180.620000 1636.500000 1181.720000 1636.980000 ;
+ RECT 1180.620000 1641.940000 1181.720000 1642.420000 ;
+ RECT 1180.620000 1598.420000 1181.720000 1598.900000 ;
+ RECT 1180.620000 1603.860000 1181.720000 1604.340000 ;
+ RECT 1180.620000 1609.300000 1181.720000 1609.780000 ;
+ RECT 1180.620000 1614.740000 1181.720000 1615.220000 ;
+ RECT 1180.620000 1620.180000 1181.720000 1620.660000 ;
+ RECT 1225.620000 1587.540000 1226.720000 1588.020000 ;
+ RECT 1225.620000 1592.980000 1226.720000 1593.460000 ;
+ RECT 1238.430000 1587.540000 1239.430000 1588.020000 ;
+ RECT 1238.430000 1592.980000 1239.430000 1593.460000 ;
+ RECT 1225.620000 1576.660000 1226.720000 1577.140000 ;
+ RECT 1225.620000 1582.100000 1226.720000 1582.580000 ;
+ RECT 1238.430000 1576.660000 1239.430000 1577.140000 ;
+ RECT 1238.430000 1582.100000 1239.430000 1582.580000 ;
+ RECT 1238.430000 1565.780000 1239.430000 1566.260000 ;
+ RECT 1238.430000 1560.340000 1239.430000 1560.820000 ;
+ RECT 1238.430000 1571.220000 1239.430000 1571.700000 ;
+ RECT 1225.620000 1571.220000 1226.720000 1571.700000 ;
+ RECT 1225.620000 1565.780000 1226.720000 1566.260000 ;
+ RECT 1225.620000 1560.340000 1226.720000 1560.820000 ;
+ RECT 1225.620000 1554.900000 1226.720000 1555.380000 ;
+ RECT 1238.430000 1554.900000 1239.430000 1555.380000 ;
+ RECT 1180.620000 1576.660000 1181.720000 1577.140000 ;
+ RECT 1180.620000 1582.100000 1181.720000 1582.580000 ;
+ RECT 1180.620000 1587.540000 1181.720000 1588.020000 ;
+ RECT 1180.620000 1592.980000 1181.720000 1593.460000 ;
+ RECT 1180.620000 1554.900000 1181.720000 1555.380000 ;
+ RECT 1180.620000 1560.340000 1181.720000 1560.820000 ;
+ RECT 1180.620000 1565.780000 1181.720000 1566.260000 ;
+ RECT 1180.620000 1571.220000 1181.720000 1571.700000 ;
+ RECT 1135.620000 1625.620000 1136.720000 1626.100000 ;
+ RECT 1135.620000 1631.060000 1136.720000 1631.540000 ;
+ RECT 1135.620000 1636.500000 1136.720000 1636.980000 ;
+ RECT 1135.620000 1641.940000 1136.720000 1642.420000 ;
+ RECT 1090.620000 1625.620000 1091.720000 1626.100000 ;
+ RECT 1090.620000 1631.060000 1091.720000 1631.540000 ;
+ RECT 1090.620000 1636.500000 1091.720000 1636.980000 ;
+ RECT 1090.620000 1641.940000 1091.720000 1642.420000 ;
+ RECT 1135.620000 1598.420000 1136.720000 1598.900000 ;
+ RECT 1135.620000 1603.860000 1136.720000 1604.340000 ;
+ RECT 1135.620000 1609.300000 1136.720000 1609.780000 ;
+ RECT 1135.620000 1614.740000 1136.720000 1615.220000 ;
+ RECT 1135.620000 1620.180000 1136.720000 1620.660000 ;
+ RECT 1090.620000 1598.420000 1091.720000 1598.900000 ;
+ RECT 1090.620000 1603.860000 1091.720000 1604.340000 ;
+ RECT 1090.620000 1609.300000 1091.720000 1609.780000 ;
+ RECT 1090.620000 1614.740000 1091.720000 1615.220000 ;
+ RECT 1090.620000 1620.180000 1091.720000 1620.660000 ;
+ RECT 1041.790000 1641.940000 1042.790000 1642.420000 ;
+ RECT 1045.455000 1641.940000 1046.720000 1642.420000 ;
+ RECT 1041.790000 1636.500000 1042.790000 1636.980000 ;
+ RECT 1045.455000 1636.500000 1046.720000 1636.980000 ;
+ RECT 1041.790000 1631.060000 1042.790000 1631.540000 ;
+ RECT 1045.455000 1631.060000 1046.720000 1631.540000 ;
+ RECT 1041.790000 1625.620000 1042.790000 1626.100000 ;
+ RECT 1045.455000 1625.620000 1046.720000 1626.100000 ;
+ RECT 1041.790000 1620.180000 1042.790000 1620.660000 ;
+ RECT 1045.455000 1620.180000 1046.720000 1620.660000 ;
+ RECT 1041.790000 1614.740000 1042.790000 1615.220000 ;
+ RECT 1045.455000 1614.740000 1046.720000 1615.220000 ;
+ RECT 1041.790000 1603.860000 1042.790000 1604.340000 ;
+ RECT 1045.455000 1603.860000 1046.720000 1604.340000 ;
+ RECT 1041.790000 1609.300000 1042.790000 1609.780000 ;
+ RECT 1045.455000 1609.300000 1046.720000 1609.780000 ;
+ RECT 1041.790000 1598.420000 1042.790000 1598.900000 ;
+ RECT 1045.455000 1598.420000 1046.720000 1598.900000 ;
+ RECT 1135.620000 1576.660000 1136.720000 1577.140000 ;
+ RECT 1135.620000 1582.100000 1136.720000 1582.580000 ;
+ RECT 1135.620000 1587.540000 1136.720000 1588.020000 ;
+ RECT 1135.620000 1592.980000 1136.720000 1593.460000 ;
+ RECT 1090.620000 1576.660000 1091.720000 1577.140000 ;
+ RECT 1090.620000 1582.100000 1091.720000 1582.580000 ;
+ RECT 1090.620000 1587.540000 1091.720000 1588.020000 ;
+ RECT 1090.620000 1592.980000 1091.720000 1593.460000 ;
+ RECT 1135.620000 1554.900000 1136.720000 1555.380000 ;
+ RECT 1135.620000 1560.340000 1136.720000 1560.820000 ;
+ RECT 1135.620000 1565.780000 1136.720000 1566.260000 ;
+ RECT 1135.620000 1571.220000 1136.720000 1571.700000 ;
+ RECT 1090.620000 1554.900000 1091.720000 1555.380000 ;
+ RECT 1090.620000 1560.340000 1091.720000 1560.820000 ;
+ RECT 1090.620000 1565.780000 1091.720000 1566.260000 ;
+ RECT 1090.620000 1571.220000 1091.720000 1571.700000 ;
+ RECT 1041.790000 1592.980000 1042.790000 1593.460000 ;
+ RECT 1045.455000 1592.980000 1046.720000 1593.460000 ;
+ RECT 1041.790000 1587.540000 1042.790000 1588.020000 ;
+ RECT 1045.455000 1587.540000 1046.720000 1588.020000 ;
+ RECT 1041.790000 1582.100000 1042.790000 1582.580000 ;
+ RECT 1045.455000 1582.100000 1046.720000 1582.580000 ;
+ RECT 1041.790000 1576.660000 1042.790000 1577.140000 ;
+ RECT 1045.455000 1576.660000 1046.720000 1577.140000 ;
+ RECT 1041.790000 1571.220000 1042.790000 1571.700000 ;
+ RECT 1045.455000 1571.220000 1046.720000 1571.700000 ;
+ RECT 1041.790000 1560.340000 1042.790000 1560.820000 ;
+ RECT 1045.455000 1560.340000 1046.720000 1560.820000 ;
+ RECT 1041.790000 1565.780000 1042.790000 1566.260000 ;
+ RECT 1045.455000 1565.780000 1046.720000 1566.260000 ;
+ RECT 1041.790000 1554.900000 1042.790000 1555.380000 ;
+ RECT 1045.455000 1554.900000 1046.720000 1555.380000 ;
+ RECT 1180.620000 1647.380000 1181.720000 1647.860000 ;
+ RECT 1225.620000 1647.380000 1226.720000 1647.860000 ;
+ RECT 1238.430000 1647.380000 1239.430000 1647.860000 ;
+ RECT 1090.620000 1647.380000 1091.720000 1647.860000 ;
+ RECT 1135.620000 1647.380000 1136.720000 1647.860000 ;
+ RECT 1041.790000 1647.380000 1042.790000 1647.860000 ;
+ RECT 1045.455000 1647.380000 1046.720000 1647.860000 ;
+ RECT 1040.560000 1744.140000 1240.660000 1745.140000 ;
+ RECT 1040.560000 1548.570000 1240.660000 1549.570000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 1547.320000 1042.790000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1041.790000 1746.580000 1042.790000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 1547.320000 1239.430000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1238.430000 1746.580000 1239.430000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1548.570000 1041.560000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1548.570000 1240.660000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1744.140000 1041.560000 1745.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1744.140000 1240.660000 1745.140000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 3373.560000 1246.820000 3374.040000 ;
+ RECT 1245.555000 3368.120000 1246.820000 3368.600000 ;
+ RECT 1245.555000 3362.680000 1246.820000 3363.160000 ;
+ RECT 1245.555000 3357.240000 1246.820000 3357.720000 ;
+ RECT 1241.890000 3349.660000 1242.890000 3379.920000 ;
+ RECT 1438.530000 3349.660000 1439.530000 3379.920000 ;
+ RECT 1245.720000 3350.910000 1246.820000 3378.160000 ;
+ RECT 1290.720000 3350.910000 1291.820000 3378.160000 ;
+ RECT 1335.720000 3350.910000 1336.820000 3378.160000 ;
+ RECT 1380.720000 3350.910000 1381.820000 3378.160000 ;
+ RECT 1425.720000 3350.910000 1426.820000 3378.160000 ;
+ LAYER met3 ;
+ RECT 1438.530000 3373.560000 1439.530000 3374.040000 ;
+ RECT 1438.530000 3368.120000 1439.530000 3368.600000 ;
+ RECT 1425.720000 3373.560000 1426.820000 3374.040000 ;
+ RECT 1425.720000 3368.120000 1426.820000 3368.600000 ;
+ RECT 1380.720000 3368.120000 1381.820000 3368.600000 ;
+ RECT 1380.720000 3373.560000 1381.820000 3374.040000 ;
+ RECT 1335.720000 3368.120000 1336.820000 3368.600000 ;
+ RECT 1290.720000 3368.120000 1291.820000 3368.600000 ;
+ RECT 1335.720000 3373.560000 1336.820000 3374.040000 ;
+ RECT 1290.720000 3373.560000 1291.820000 3374.040000 ;
+ RECT 1245.555000 3373.560000 1246.820000 3374.040000 ;
+ RECT 1241.890000 3373.560000 1242.890000 3374.040000 ;
+ RECT 1245.555000 3368.120000 1246.820000 3368.600000 ;
+ RECT 1241.890000 3368.120000 1242.890000 3368.600000 ;
+ RECT 1438.530000 3362.680000 1439.530000 3363.160000 ;
+ RECT 1438.530000 3357.240000 1439.530000 3357.720000 ;
+ RECT 1425.720000 3362.680000 1426.820000 3363.160000 ;
+ RECT 1425.720000 3357.240000 1426.820000 3357.720000 ;
+ RECT 1380.720000 3357.240000 1381.820000 3357.720000 ;
+ RECT 1380.720000 3362.680000 1381.820000 3363.160000 ;
+ RECT 1335.720000 3357.240000 1336.820000 3357.720000 ;
+ RECT 1290.720000 3357.240000 1291.820000 3357.720000 ;
+ RECT 1335.720000 3362.680000 1336.820000 3363.160000 ;
+ RECT 1290.720000 3362.680000 1291.820000 3363.160000 ;
+ RECT 1245.555000 3362.680000 1246.820000 3363.160000 ;
+ RECT 1241.890000 3362.680000 1242.890000 3363.160000 ;
+ RECT 1245.555000 3357.240000 1246.820000 3357.720000 ;
+ RECT 1241.890000 3357.240000 1242.890000 3357.720000 ;
+ RECT 1240.660000 3377.160000 1440.760000 3378.160000 ;
+ RECT 1240.660000 3350.910000 1440.760000 3351.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 3349.660000 1242.890000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 3378.920000 1242.890000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 3349.660000 1439.530000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 3378.920000 1439.530000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 3350.910000 1241.660000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 3350.910000 1440.760000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 3377.160000 1241.660000 3378.160000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 3377.160000 1440.760000 3378.160000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 1539.600000 1246.820000 1540.080000 ;
+ RECT 1245.555000 1528.720000 1246.820000 1529.200000 ;
+ RECT 1245.555000 1534.160000 1246.820000 1534.640000 ;
+ RECT 1245.555000 1523.280000 1246.820000 1523.760000 ;
+ RECT 1245.555000 1517.840000 1246.820000 1518.320000 ;
+ RECT 1245.555000 1512.400000 1246.820000 1512.880000 ;
+ RECT 1245.555000 1506.960000 1246.820000 1507.440000 ;
+ RECT 1245.555000 1501.520000 1246.820000 1502.000000 ;
+ RECT 1245.555000 1496.080000 1246.820000 1496.560000 ;
+ RECT 1245.555000 1485.200000 1246.820000 1485.680000 ;
+ RECT 1245.555000 1490.640000 1246.820000 1491.120000 ;
+ RECT 1245.555000 1479.760000 1246.820000 1480.240000 ;
+ RECT 1245.555000 1474.320000 1246.820000 1474.800000 ;
+ RECT 1245.555000 1468.880000 1246.820000 1469.360000 ;
+ RECT 1245.555000 1463.440000 1246.820000 1463.920000 ;
+ RECT 1245.555000 1458.000000 1246.820000 1458.480000 ;
+ RECT 1245.555000 1452.560000 1246.820000 1453.040000 ;
+ RECT 1245.555000 1441.680000 1246.820000 1442.160000 ;
+ RECT 1245.555000 1436.240000 1246.820000 1436.720000 ;
+ RECT 1245.555000 1430.800000 1246.820000 1431.280000 ;
+ RECT 1245.555000 1425.360000 1246.820000 1425.840000 ;
+ RECT 1245.555000 1419.920000 1246.820000 1420.400000 ;
+ RECT 1245.555000 1414.480000 1246.820000 1414.960000 ;
+ RECT 1245.555000 1403.600000 1246.820000 1404.080000 ;
+ RECT 1245.555000 1409.040000 1246.820000 1409.520000 ;
+ RECT 1245.555000 1398.160000 1246.820000 1398.640000 ;
+ RECT 1245.555000 1392.720000 1246.820000 1393.200000 ;
+ RECT 1245.555000 1387.280000 1246.820000 1387.760000 ;
+ RECT 1245.555000 1381.840000 1246.820000 1382.320000 ;
+ RECT 1245.555000 1376.400000 1246.820000 1376.880000 ;
+ RECT 1245.555000 1370.960000 1246.820000 1371.440000 ;
+ RECT 1245.555000 1360.080000 1246.820000 1360.560000 ;
+ RECT 1245.555000 1365.520000 1246.820000 1366.000000 ;
+ RECT 1245.555000 1354.640000 1246.820000 1355.120000 ;
+ RECT 1245.555000 1447.120000 1246.820000 1447.600000 ;
+ RECT 1425.720000 1348.310000 1426.820000 1544.880000 ;
+ RECT 1380.720000 1348.310000 1381.820000 1544.880000 ;
+ RECT 1438.530000 1347.060000 1439.530000 1547.320000 ;
+ RECT 1335.720000 1348.310000 1336.820000 1544.880000 ;
+ RECT 1290.720000 1348.310000 1291.820000 1544.880000 ;
+ RECT 1245.720000 1348.310000 1246.820000 1544.880000 ;
+ RECT 1241.890000 1347.060000 1242.890000 1547.320000 ;
+ LAYER met3 ;
+ RECT 1425.720000 1539.600000 1426.820000 1540.080000 ;
+ RECT 1438.530000 1539.600000 1439.530000 1540.080000 ;
+ RECT 1438.530000 1528.720000 1439.530000 1529.200000 ;
+ RECT 1438.530000 1523.280000 1439.530000 1523.760000 ;
+ RECT 1438.530000 1534.160000 1439.530000 1534.640000 ;
+ RECT 1425.720000 1534.160000 1426.820000 1534.640000 ;
+ RECT 1425.720000 1528.720000 1426.820000 1529.200000 ;
+ RECT 1425.720000 1523.280000 1426.820000 1523.760000 ;
+ RECT 1425.720000 1512.400000 1426.820000 1512.880000 ;
+ RECT 1425.720000 1517.840000 1426.820000 1518.320000 ;
+ RECT 1438.530000 1512.400000 1439.530000 1512.880000 ;
+ RECT 1438.530000 1517.840000 1439.530000 1518.320000 ;
+ RECT 1425.720000 1501.520000 1426.820000 1502.000000 ;
+ RECT 1425.720000 1506.960000 1426.820000 1507.440000 ;
+ RECT 1438.530000 1501.520000 1439.530000 1502.000000 ;
+ RECT 1438.530000 1506.960000 1439.530000 1507.440000 ;
+ RECT 1380.720000 1523.280000 1381.820000 1523.760000 ;
+ RECT 1380.720000 1528.720000 1381.820000 1529.200000 ;
+ RECT 1380.720000 1534.160000 1381.820000 1534.640000 ;
+ RECT 1380.720000 1539.600000 1381.820000 1540.080000 ;
+ RECT 1380.720000 1506.960000 1381.820000 1507.440000 ;
+ RECT 1380.720000 1501.520000 1381.820000 1502.000000 ;
+ RECT 1380.720000 1512.400000 1381.820000 1512.880000 ;
+ RECT 1380.720000 1517.840000 1381.820000 1518.320000 ;
+ RECT 1438.530000 1490.640000 1439.530000 1491.120000 ;
+ RECT 1438.530000 1485.200000 1439.530000 1485.680000 ;
+ RECT 1438.530000 1496.080000 1439.530000 1496.560000 ;
+ RECT 1425.720000 1496.080000 1426.820000 1496.560000 ;
+ RECT 1425.720000 1490.640000 1426.820000 1491.120000 ;
+ RECT 1425.720000 1485.200000 1426.820000 1485.680000 ;
+ RECT 1425.720000 1474.320000 1426.820000 1474.800000 ;
+ RECT 1425.720000 1479.760000 1426.820000 1480.240000 ;
+ RECT 1438.530000 1474.320000 1439.530000 1474.800000 ;
+ RECT 1438.530000 1479.760000 1439.530000 1480.240000 ;
+ RECT 1438.530000 1463.440000 1439.530000 1463.920000 ;
+ RECT 1438.530000 1468.880000 1439.530000 1469.360000 ;
+ RECT 1425.720000 1468.880000 1426.820000 1469.360000 ;
+ RECT 1425.720000 1463.440000 1426.820000 1463.920000 ;
+ RECT 1425.720000 1452.560000 1426.820000 1453.040000 ;
+ RECT 1425.720000 1458.000000 1426.820000 1458.480000 ;
+ RECT 1438.530000 1452.560000 1439.530000 1453.040000 ;
+ RECT 1438.530000 1458.000000 1439.530000 1458.480000 ;
+ RECT 1380.720000 1474.320000 1381.820000 1474.800000 ;
+ RECT 1380.720000 1479.760000 1381.820000 1480.240000 ;
+ RECT 1380.720000 1485.200000 1381.820000 1485.680000 ;
+ RECT 1380.720000 1490.640000 1381.820000 1491.120000 ;
+ RECT 1380.720000 1496.080000 1381.820000 1496.560000 ;
+ RECT 1380.720000 1452.560000 1381.820000 1453.040000 ;
+ RECT 1380.720000 1458.000000 1381.820000 1458.480000 ;
+ RECT 1380.720000 1463.440000 1381.820000 1463.920000 ;
+ RECT 1380.720000 1468.880000 1381.820000 1469.360000 ;
+ RECT 1335.720000 1528.720000 1336.820000 1529.200000 ;
+ RECT 1335.720000 1523.280000 1336.820000 1523.760000 ;
+ RECT 1335.720000 1534.160000 1336.820000 1534.640000 ;
+ RECT 1335.720000 1539.600000 1336.820000 1540.080000 ;
+ RECT 1290.720000 1523.280000 1291.820000 1523.760000 ;
+ RECT 1290.720000 1528.720000 1291.820000 1529.200000 ;
+ RECT 1290.720000 1534.160000 1291.820000 1534.640000 ;
+ RECT 1290.720000 1539.600000 1291.820000 1540.080000 ;
+ RECT 1335.720000 1501.520000 1336.820000 1502.000000 ;
+ RECT 1335.720000 1506.960000 1336.820000 1507.440000 ;
+ RECT 1335.720000 1512.400000 1336.820000 1512.880000 ;
+ RECT 1335.720000 1517.840000 1336.820000 1518.320000 ;
+ RECT 1290.720000 1501.520000 1291.820000 1502.000000 ;
+ RECT 1290.720000 1506.960000 1291.820000 1507.440000 ;
+ RECT 1290.720000 1512.400000 1291.820000 1512.880000 ;
+ RECT 1290.720000 1517.840000 1291.820000 1518.320000 ;
+ RECT 1241.890000 1539.600000 1242.890000 1540.080000 ;
+ RECT 1245.555000 1539.600000 1246.820000 1540.080000 ;
+ RECT 1241.890000 1528.720000 1242.890000 1529.200000 ;
+ RECT 1245.555000 1528.720000 1246.820000 1529.200000 ;
+ RECT 1241.890000 1534.160000 1242.890000 1534.640000 ;
+ RECT 1245.555000 1534.160000 1246.820000 1534.640000 ;
+ RECT 1241.890000 1523.280000 1242.890000 1523.760000 ;
+ RECT 1245.555000 1523.280000 1246.820000 1523.760000 ;
+ RECT 1241.890000 1517.840000 1242.890000 1518.320000 ;
+ RECT 1245.555000 1517.840000 1246.820000 1518.320000 ;
+ RECT 1241.890000 1512.400000 1242.890000 1512.880000 ;
+ RECT 1245.555000 1512.400000 1246.820000 1512.880000 ;
+ RECT 1241.890000 1506.960000 1242.890000 1507.440000 ;
+ RECT 1245.555000 1506.960000 1246.820000 1507.440000 ;
+ RECT 1241.890000 1501.520000 1242.890000 1502.000000 ;
+ RECT 1245.555000 1501.520000 1246.820000 1502.000000 ;
+ RECT 1335.720000 1474.320000 1336.820000 1474.800000 ;
+ RECT 1335.720000 1479.760000 1336.820000 1480.240000 ;
+ RECT 1335.720000 1485.200000 1336.820000 1485.680000 ;
+ RECT 1335.720000 1490.640000 1336.820000 1491.120000 ;
+ RECT 1335.720000 1496.080000 1336.820000 1496.560000 ;
+ RECT 1290.720000 1474.320000 1291.820000 1474.800000 ;
+ RECT 1290.720000 1479.760000 1291.820000 1480.240000 ;
+ RECT 1290.720000 1485.200000 1291.820000 1485.680000 ;
+ RECT 1290.720000 1490.640000 1291.820000 1491.120000 ;
+ RECT 1290.720000 1496.080000 1291.820000 1496.560000 ;
+ RECT 1335.720000 1452.560000 1336.820000 1453.040000 ;
+ RECT 1335.720000 1458.000000 1336.820000 1458.480000 ;
+ RECT 1335.720000 1463.440000 1336.820000 1463.920000 ;
+ RECT 1335.720000 1468.880000 1336.820000 1469.360000 ;
+ RECT 1290.720000 1452.560000 1291.820000 1453.040000 ;
+ RECT 1290.720000 1458.000000 1291.820000 1458.480000 ;
+ RECT 1290.720000 1463.440000 1291.820000 1463.920000 ;
+ RECT 1290.720000 1468.880000 1291.820000 1469.360000 ;
+ RECT 1241.890000 1496.080000 1242.890000 1496.560000 ;
+ RECT 1245.555000 1496.080000 1246.820000 1496.560000 ;
+ RECT 1241.890000 1485.200000 1242.890000 1485.680000 ;
+ RECT 1245.555000 1485.200000 1246.820000 1485.680000 ;
+ RECT 1241.890000 1490.640000 1242.890000 1491.120000 ;
+ RECT 1245.555000 1490.640000 1246.820000 1491.120000 ;
+ RECT 1241.890000 1479.760000 1242.890000 1480.240000 ;
+ RECT 1245.555000 1479.760000 1246.820000 1480.240000 ;
+ RECT 1241.890000 1474.320000 1242.890000 1474.800000 ;
+ RECT 1245.555000 1474.320000 1246.820000 1474.800000 ;
+ RECT 1241.890000 1468.880000 1242.890000 1469.360000 ;
+ RECT 1245.555000 1468.880000 1246.820000 1469.360000 ;
+ RECT 1241.890000 1463.440000 1242.890000 1463.920000 ;
+ RECT 1245.555000 1463.440000 1246.820000 1463.920000 ;
+ RECT 1241.890000 1458.000000 1242.890000 1458.480000 ;
+ RECT 1245.555000 1458.000000 1246.820000 1458.480000 ;
+ RECT 1241.890000 1452.560000 1242.890000 1453.040000 ;
+ RECT 1245.555000 1452.560000 1246.820000 1453.040000 ;
+ RECT 1425.720000 1436.240000 1426.820000 1436.720000 ;
+ RECT 1425.720000 1441.680000 1426.820000 1442.160000 ;
+ RECT 1438.530000 1436.240000 1439.530000 1436.720000 ;
+ RECT 1438.530000 1441.680000 1439.530000 1442.160000 ;
+ RECT 1438.530000 1425.360000 1439.530000 1425.840000 ;
+ RECT 1438.530000 1430.800000 1439.530000 1431.280000 ;
+ RECT 1425.720000 1430.800000 1426.820000 1431.280000 ;
+ RECT 1425.720000 1425.360000 1426.820000 1425.840000 ;
+ RECT 1425.720000 1414.480000 1426.820000 1414.960000 ;
+ RECT 1425.720000 1419.920000 1426.820000 1420.400000 ;
+ RECT 1438.530000 1414.480000 1439.530000 1414.960000 ;
+ RECT 1438.530000 1419.920000 1439.530000 1420.400000 ;
+ RECT 1438.530000 1403.600000 1439.530000 1404.080000 ;
+ RECT 1438.530000 1398.160000 1439.530000 1398.640000 ;
+ RECT 1438.530000 1409.040000 1439.530000 1409.520000 ;
+ RECT 1425.720000 1409.040000 1426.820000 1409.520000 ;
+ RECT 1425.720000 1403.600000 1426.820000 1404.080000 ;
+ RECT 1425.720000 1398.160000 1426.820000 1398.640000 ;
+ RECT 1380.720000 1425.360000 1381.820000 1425.840000 ;
+ RECT 1380.720000 1430.800000 1381.820000 1431.280000 ;
+ RECT 1380.720000 1436.240000 1381.820000 1436.720000 ;
+ RECT 1380.720000 1441.680000 1381.820000 1442.160000 ;
+ RECT 1380.720000 1398.160000 1381.820000 1398.640000 ;
+ RECT 1380.720000 1403.600000 1381.820000 1404.080000 ;
+ RECT 1380.720000 1409.040000 1381.820000 1409.520000 ;
+ RECT 1380.720000 1414.480000 1381.820000 1414.960000 ;
+ RECT 1380.720000 1419.920000 1381.820000 1420.400000 ;
+ RECT 1425.720000 1387.280000 1426.820000 1387.760000 ;
+ RECT 1425.720000 1392.720000 1426.820000 1393.200000 ;
+ RECT 1438.530000 1387.280000 1439.530000 1387.760000 ;
+ RECT 1438.530000 1392.720000 1439.530000 1393.200000 ;
+ RECT 1425.720000 1376.400000 1426.820000 1376.880000 ;
+ RECT 1425.720000 1381.840000 1426.820000 1382.320000 ;
+ RECT 1438.530000 1376.400000 1439.530000 1376.880000 ;
+ RECT 1438.530000 1381.840000 1439.530000 1382.320000 ;
+ RECT 1438.530000 1365.520000 1439.530000 1366.000000 ;
+ RECT 1438.530000 1360.080000 1439.530000 1360.560000 ;
+ RECT 1438.530000 1370.960000 1439.530000 1371.440000 ;
+ RECT 1425.720000 1370.960000 1426.820000 1371.440000 ;
+ RECT 1425.720000 1365.520000 1426.820000 1366.000000 ;
+ RECT 1425.720000 1360.080000 1426.820000 1360.560000 ;
+ RECT 1425.720000 1354.640000 1426.820000 1355.120000 ;
+ RECT 1438.530000 1354.640000 1439.530000 1355.120000 ;
+ RECT 1380.720000 1376.400000 1381.820000 1376.880000 ;
+ RECT 1380.720000 1381.840000 1381.820000 1382.320000 ;
+ RECT 1380.720000 1387.280000 1381.820000 1387.760000 ;
+ RECT 1380.720000 1392.720000 1381.820000 1393.200000 ;
+ RECT 1380.720000 1354.640000 1381.820000 1355.120000 ;
+ RECT 1380.720000 1360.080000 1381.820000 1360.560000 ;
+ RECT 1380.720000 1365.520000 1381.820000 1366.000000 ;
+ RECT 1380.720000 1370.960000 1381.820000 1371.440000 ;
+ RECT 1335.720000 1425.360000 1336.820000 1425.840000 ;
+ RECT 1335.720000 1430.800000 1336.820000 1431.280000 ;
+ RECT 1335.720000 1436.240000 1336.820000 1436.720000 ;
+ RECT 1335.720000 1441.680000 1336.820000 1442.160000 ;
+ RECT 1290.720000 1425.360000 1291.820000 1425.840000 ;
+ RECT 1290.720000 1430.800000 1291.820000 1431.280000 ;
+ RECT 1290.720000 1436.240000 1291.820000 1436.720000 ;
+ RECT 1290.720000 1441.680000 1291.820000 1442.160000 ;
+ RECT 1335.720000 1398.160000 1336.820000 1398.640000 ;
+ RECT 1335.720000 1403.600000 1336.820000 1404.080000 ;
+ RECT 1335.720000 1409.040000 1336.820000 1409.520000 ;
+ RECT 1335.720000 1414.480000 1336.820000 1414.960000 ;
+ RECT 1335.720000 1419.920000 1336.820000 1420.400000 ;
+ RECT 1290.720000 1398.160000 1291.820000 1398.640000 ;
+ RECT 1290.720000 1403.600000 1291.820000 1404.080000 ;
+ RECT 1290.720000 1409.040000 1291.820000 1409.520000 ;
+ RECT 1290.720000 1414.480000 1291.820000 1414.960000 ;
+ RECT 1290.720000 1419.920000 1291.820000 1420.400000 ;
+ RECT 1241.890000 1441.680000 1242.890000 1442.160000 ;
+ RECT 1245.555000 1441.680000 1246.820000 1442.160000 ;
+ RECT 1241.890000 1436.240000 1242.890000 1436.720000 ;
+ RECT 1245.555000 1436.240000 1246.820000 1436.720000 ;
+ RECT 1241.890000 1430.800000 1242.890000 1431.280000 ;
+ RECT 1245.555000 1430.800000 1246.820000 1431.280000 ;
+ RECT 1241.890000 1425.360000 1242.890000 1425.840000 ;
+ RECT 1245.555000 1425.360000 1246.820000 1425.840000 ;
+ RECT 1241.890000 1419.920000 1242.890000 1420.400000 ;
+ RECT 1245.555000 1419.920000 1246.820000 1420.400000 ;
+ RECT 1241.890000 1414.480000 1242.890000 1414.960000 ;
+ RECT 1245.555000 1414.480000 1246.820000 1414.960000 ;
+ RECT 1241.890000 1403.600000 1242.890000 1404.080000 ;
+ RECT 1245.555000 1403.600000 1246.820000 1404.080000 ;
+ RECT 1241.890000 1409.040000 1242.890000 1409.520000 ;
+ RECT 1245.555000 1409.040000 1246.820000 1409.520000 ;
+ RECT 1241.890000 1398.160000 1242.890000 1398.640000 ;
+ RECT 1245.555000 1398.160000 1246.820000 1398.640000 ;
+ RECT 1335.720000 1376.400000 1336.820000 1376.880000 ;
+ RECT 1335.720000 1381.840000 1336.820000 1382.320000 ;
+ RECT 1335.720000 1387.280000 1336.820000 1387.760000 ;
+ RECT 1335.720000 1392.720000 1336.820000 1393.200000 ;
+ RECT 1290.720000 1376.400000 1291.820000 1376.880000 ;
+ RECT 1290.720000 1381.840000 1291.820000 1382.320000 ;
+ RECT 1290.720000 1387.280000 1291.820000 1387.760000 ;
+ RECT 1290.720000 1392.720000 1291.820000 1393.200000 ;
+ RECT 1335.720000 1354.640000 1336.820000 1355.120000 ;
+ RECT 1335.720000 1360.080000 1336.820000 1360.560000 ;
+ RECT 1335.720000 1365.520000 1336.820000 1366.000000 ;
+ RECT 1335.720000 1370.960000 1336.820000 1371.440000 ;
+ RECT 1290.720000 1354.640000 1291.820000 1355.120000 ;
+ RECT 1290.720000 1360.080000 1291.820000 1360.560000 ;
+ RECT 1290.720000 1365.520000 1291.820000 1366.000000 ;
+ RECT 1290.720000 1370.960000 1291.820000 1371.440000 ;
+ RECT 1241.890000 1392.720000 1242.890000 1393.200000 ;
+ RECT 1245.555000 1392.720000 1246.820000 1393.200000 ;
+ RECT 1241.890000 1387.280000 1242.890000 1387.760000 ;
+ RECT 1245.555000 1387.280000 1246.820000 1387.760000 ;
+ RECT 1241.890000 1381.840000 1242.890000 1382.320000 ;
+ RECT 1245.555000 1381.840000 1246.820000 1382.320000 ;
+ RECT 1241.890000 1376.400000 1242.890000 1376.880000 ;
+ RECT 1245.555000 1376.400000 1246.820000 1376.880000 ;
+ RECT 1241.890000 1370.960000 1242.890000 1371.440000 ;
+ RECT 1245.555000 1370.960000 1246.820000 1371.440000 ;
+ RECT 1241.890000 1360.080000 1242.890000 1360.560000 ;
+ RECT 1245.555000 1360.080000 1246.820000 1360.560000 ;
+ RECT 1241.890000 1365.520000 1242.890000 1366.000000 ;
+ RECT 1245.555000 1365.520000 1246.820000 1366.000000 ;
+ RECT 1241.890000 1354.640000 1242.890000 1355.120000 ;
+ RECT 1245.555000 1354.640000 1246.820000 1355.120000 ;
+ RECT 1380.720000 1447.120000 1381.820000 1447.600000 ;
+ RECT 1425.720000 1447.120000 1426.820000 1447.600000 ;
+ RECT 1438.530000 1447.120000 1439.530000 1447.600000 ;
+ RECT 1290.720000 1447.120000 1291.820000 1447.600000 ;
+ RECT 1335.720000 1447.120000 1336.820000 1447.600000 ;
+ RECT 1241.890000 1447.120000 1242.890000 1447.600000 ;
+ RECT 1245.555000 1447.120000 1246.820000 1447.600000 ;
+ RECT 1240.660000 1543.880000 1440.760000 1544.880000 ;
+ RECT 1240.660000 1348.310000 1440.760000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 1347.060000 1242.890000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 1546.320000 1242.890000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 1347.060000 1439.530000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 1546.320000 1439.530000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1348.310000 1241.660000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1348.310000 1440.760000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1543.880000 1241.660000 1544.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1543.880000 1440.760000 1544.880000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 1339.340000 1246.820000 1339.820000 ;
+ RECT 1245.555000 1328.460000 1246.820000 1328.940000 ;
+ RECT 1245.555000 1333.900000 1246.820000 1334.380000 ;
+ RECT 1245.555000 1323.020000 1246.820000 1323.500000 ;
+ RECT 1245.555000 1317.580000 1246.820000 1318.060000 ;
+ RECT 1245.555000 1312.140000 1246.820000 1312.620000 ;
+ RECT 1245.555000 1306.700000 1246.820000 1307.180000 ;
+ RECT 1245.555000 1301.260000 1246.820000 1301.740000 ;
+ RECT 1245.555000 1295.820000 1246.820000 1296.300000 ;
+ RECT 1245.555000 1284.940000 1246.820000 1285.420000 ;
+ RECT 1245.555000 1290.380000 1246.820000 1290.860000 ;
+ RECT 1245.555000 1279.500000 1246.820000 1279.980000 ;
+ RECT 1245.555000 1274.060000 1246.820000 1274.540000 ;
+ RECT 1245.555000 1268.620000 1246.820000 1269.100000 ;
+ RECT 1245.555000 1263.180000 1246.820000 1263.660000 ;
+ RECT 1245.555000 1257.740000 1246.820000 1258.220000 ;
+ RECT 1245.555000 1252.300000 1246.820000 1252.780000 ;
+ RECT 1245.555000 1241.420000 1246.820000 1241.900000 ;
+ RECT 1245.555000 1235.980000 1246.820000 1236.460000 ;
+ RECT 1245.555000 1230.540000 1246.820000 1231.020000 ;
+ RECT 1245.555000 1225.100000 1246.820000 1225.580000 ;
+ RECT 1245.555000 1219.660000 1246.820000 1220.140000 ;
+ RECT 1245.555000 1214.220000 1246.820000 1214.700000 ;
+ RECT 1245.555000 1203.340000 1246.820000 1203.820000 ;
+ RECT 1245.555000 1208.780000 1246.820000 1209.260000 ;
+ RECT 1245.555000 1197.900000 1246.820000 1198.380000 ;
+ RECT 1245.555000 1192.460000 1246.820000 1192.940000 ;
+ RECT 1245.555000 1187.020000 1246.820000 1187.500000 ;
+ RECT 1245.555000 1181.580000 1246.820000 1182.060000 ;
+ RECT 1245.555000 1176.140000 1246.820000 1176.620000 ;
+ RECT 1245.555000 1170.700000 1246.820000 1171.180000 ;
+ RECT 1245.555000 1159.820000 1246.820000 1160.300000 ;
+ RECT 1245.555000 1165.260000 1246.820000 1165.740000 ;
+ RECT 1245.555000 1154.380000 1246.820000 1154.860000 ;
+ RECT 1245.555000 1246.860000 1246.820000 1247.340000 ;
+ RECT 1425.720000 1148.050000 1426.820000 1344.620000 ;
+ RECT 1380.720000 1148.050000 1381.820000 1344.620000 ;
+ RECT 1438.530000 1146.800000 1439.530000 1347.060000 ;
+ RECT 1335.720000 1148.050000 1336.820000 1344.620000 ;
+ RECT 1290.720000 1148.050000 1291.820000 1344.620000 ;
+ RECT 1245.720000 1148.050000 1246.820000 1344.620000 ;
+ RECT 1241.890000 1146.800000 1242.890000 1347.060000 ;
+ LAYER met3 ;
+ RECT 1425.720000 1339.340000 1426.820000 1339.820000 ;
+ RECT 1438.530000 1339.340000 1439.530000 1339.820000 ;
+ RECT 1438.530000 1328.460000 1439.530000 1328.940000 ;
+ RECT 1438.530000 1323.020000 1439.530000 1323.500000 ;
+ RECT 1438.530000 1333.900000 1439.530000 1334.380000 ;
+ RECT 1425.720000 1333.900000 1426.820000 1334.380000 ;
+ RECT 1425.720000 1328.460000 1426.820000 1328.940000 ;
+ RECT 1425.720000 1323.020000 1426.820000 1323.500000 ;
+ RECT 1425.720000 1312.140000 1426.820000 1312.620000 ;
+ RECT 1425.720000 1317.580000 1426.820000 1318.060000 ;
+ RECT 1438.530000 1312.140000 1439.530000 1312.620000 ;
+ RECT 1438.530000 1317.580000 1439.530000 1318.060000 ;
+ RECT 1425.720000 1301.260000 1426.820000 1301.740000 ;
+ RECT 1425.720000 1306.700000 1426.820000 1307.180000 ;
+ RECT 1438.530000 1301.260000 1439.530000 1301.740000 ;
+ RECT 1438.530000 1306.700000 1439.530000 1307.180000 ;
+ RECT 1380.720000 1323.020000 1381.820000 1323.500000 ;
+ RECT 1380.720000 1328.460000 1381.820000 1328.940000 ;
+ RECT 1380.720000 1333.900000 1381.820000 1334.380000 ;
+ RECT 1380.720000 1339.340000 1381.820000 1339.820000 ;
+ RECT 1380.720000 1306.700000 1381.820000 1307.180000 ;
+ RECT 1380.720000 1301.260000 1381.820000 1301.740000 ;
+ RECT 1380.720000 1312.140000 1381.820000 1312.620000 ;
+ RECT 1380.720000 1317.580000 1381.820000 1318.060000 ;
+ RECT 1438.530000 1290.380000 1439.530000 1290.860000 ;
+ RECT 1438.530000 1284.940000 1439.530000 1285.420000 ;
+ RECT 1438.530000 1295.820000 1439.530000 1296.300000 ;
+ RECT 1425.720000 1295.820000 1426.820000 1296.300000 ;
+ RECT 1425.720000 1290.380000 1426.820000 1290.860000 ;
+ RECT 1425.720000 1284.940000 1426.820000 1285.420000 ;
+ RECT 1425.720000 1274.060000 1426.820000 1274.540000 ;
+ RECT 1425.720000 1279.500000 1426.820000 1279.980000 ;
+ RECT 1438.530000 1274.060000 1439.530000 1274.540000 ;
+ RECT 1438.530000 1279.500000 1439.530000 1279.980000 ;
+ RECT 1438.530000 1263.180000 1439.530000 1263.660000 ;
+ RECT 1438.530000 1268.620000 1439.530000 1269.100000 ;
+ RECT 1425.720000 1268.620000 1426.820000 1269.100000 ;
+ RECT 1425.720000 1263.180000 1426.820000 1263.660000 ;
+ RECT 1425.720000 1252.300000 1426.820000 1252.780000 ;
+ RECT 1425.720000 1257.740000 1426.820000 1258.220000 ;
+ RECT 1438.530000 1252.300000 1439.530000 1252.780000 ;
+ RECT 1438.530000 1257.740000 1439.530000 1258.220000 ;
+ RECT 1380.720000 1274.060000 1381.820000 1274.540000 ;
+ RECT 1380.720000 1279.500000 1381.820000 1279.980000 ;
+ RECT 1380.720000 1284.940000 1381.820000 1285.420000 ;
+ RECT 1380.720000 1290.380000 1381.820000 1290.860000 ;
+ RECT 1380.720000 1295.820000 1381.820000 1296.300000 ;
+ RECT 1380.720000 1252.300000 1381.820000 1252.780000 ;
+ RECT 1380.720000 1257.740000 1381.820000 1258.220000 ;
+ RECT 1380.720000 1263.180000 1381.820000 1263.660000 ;
+ RECT 1380.720000 1268.620000 1381.820000 1269.100000 ;
+ RECT 1335.720000 1328.460000 1336.820000 1328.940000 ;
+ RECT 1335.720000 1323.020000 1336.820000 1323.500000 ;
+ RECT 1335.720000 1333.900000 1336.820000 1334.380000 ;
+ RECT 1335.720000 1339.340000 1336.820000 1339.820000 ;
+ RECT 1290.720000 1323.020000 1291.820000 1323.500000 ;
+ RECT 1290.720000 1328.460000 1291.820000 1328.940000 ;
+ RECT 1290.720000 1333.900000 1291.820000 1334.380000 ;
+ RECT 1290.720000 1339.340000 1291.820000 1339.820000 ;
+ RECT 1335.720000 1301.260000 1336.820000 1301.740000 ;
+ RECT 1335.720000 1306.700000 1336.820000 1307.180000 ;
+ RECT 1335.720000 1312.140000 1336.820000 1312.620000 ;
+ RECT 1335.720000 1317.580000 1336.820000 1318.060000 ;
+ RECT 1290.720000 1301.260000 1291.820000 1301.740000 ;
+ RECT 1290.720000 1306.700000 1291.820000 1307.180000 ;
+ RECT 1290.720000 1312.140000 1291.820000 1312.620000 ;
+ RECT 1290.720000 1317.580000 1291.820000 1318.060000 ;
+ RECT 1241.890000 1339.340000 1242.890000 1339.820000 ;
+ RECT 1245.555000 1339.340000 1246.820000 1339.820000 ;
+ RECT 1241.890000 1328.460000 1242.890000 1328.940000 ;
+ RECT 1245.555000 1328.460000 1246.820000 1328.940000 ;
+ RECT 1241.890000 1333.900000 1242.890000 1334.380000 ;
+ RECT 1245.555000 1333.900000 1246.820000 1334.380000 ;
+ RECT 1241.890000 1323.020000 1242.890000 1323.500000 ;
+ RECT 1245.555000 1323.020000 1246.820000 1323.500000 ;
+ RECT 1241.890000 1317.580000 1242.890000 1318.060000 ;
+ RECT 1245.555000 1317.580000 1246.820000 1318.060000 ;
+ RECT 1241.890000 1312.140000 1242.890000 1312.620000 ;
+ RECT 1245.555000 1312.140000 1246.820000 1312.620000 ;
+ RECT 1241.890000 1306.700000 1242.890000 1307.180000 ;
+ RECT 1245.555000 1306.700000 1246.820000 1307.180000 ;
+ RECT 1241.890000 1301.260000 1242.890000 1301.740000 ;
+ RECT 1245.555000 1301.260000 1246.820000 1301.740000 ;
+ RECT 1335.720000 1274.060000 1336.820000 1274.540000 ;
+ RECT 1335.720000 1279.500000 1336.820000 1279.980000 ;
+ RECT 1335.720000 1284.940000 1336.820000 1285.420000 ;
+ RECT 1335.720000 1290.380000 1336.820000 1290.860000 ;
+ RECT 1335.720000 1295.820000 1336.820000 1296.300000 ;
+ RECT 1290.720000 1274.060000 1291.820000 1274.540000 ;
+ RECT 1290.720000 1279.500000 1291.820000 1279.980000 ;
+ RECT 1290.720000 1284.940000 1291.820000 1285.420000 ;
+ RECT 1290.720000 1290.380000 1291.820000 1290.860000 ;
+ RECT 1290.720000 1295.820000 1291.820000 1296.300000 ;
+ RECT 1335.720000 1252.300000 1336.820000 1252.780000 ;
+ RECT 1335.720000 1257.740000 1336.820000 1258.220000 ;
+ RECT 1335.720000 1263.180000 1336.820000 1263.660000 ;
+ RECT 1335.720000 1268.620000 1336.820000 1269.100000 ;
+ RECT 1290.720000 1252.300000 1291.820000 1252.780000 ;
+ RECT 1290.720000 1257.740000 1291.820000 1258.220000 ;
+ RECT 1290.720000 1263.180000 1291.820000 1263.660000 ;
+ RECT 1290.720000 1268.620000 1291.820000 1269.100000 ;
+ RECT 1241.890000 1295.820000 1242.890000 1296.300000 ;
+ RECT 1245.555000 1295.820000 1246.820000 1296.300000 ;
+ RECT 1241.890000 1284.940000 1242.890000 1285.420000 ;
+ RECT 1245.555000 1284.940000 1246.820000 1285.420000 ;
+ RECT 1241.890000 1290.380000 1242.890000 1290.860000 ;
+ RECT 1245.555000 1290.380000 1246.820000 1290.860000 ;
+ RECT 1241.890000 1279.500000 1242.890000 1279.980000 ;
+ RECT 1245.555000 1279.500000 1246.820000 1279.980000 ;
+ RECT 1241.890000 1274.060000 1242.890000 1274.540000 ;
+ RECT 1245.555000 1274.060000 1246.820000 1274.540000 ;
+ RECT 1241.890000 1268.620000 1242.890000 1269.100000 ;
+ RECT 1245.555000 1268.620000 1246.820000 1269.100000 ;
+ RECT 1241.890000 1263.180000 1242.890000 1263.660000 ;
+ RECT 1245.555000 1263.180000 1246.820000 1263.660000 ;
+ RECT 1241.890000 1257.740000 1242.890000 1258.220000 ;
+ RECT 1245.555000 1257.740000 1246.820000 1258.220000 ;
+ RECT 1241.890000 1252.300000 1242.890000 1252.780000 ;
+ RECT 1245.555000 1252.300000 1246.820000 1252.780000 ;
+ RECT 1425.720000 1235.980000 1426.820000 1236.460000 ;
+ RECT 1425.720000 1241.420000 1426.820000 1241.900000 ;
+ RECT 1438.530000 1235.980000 1439.530000 1236.460000 ;
+ RECT 1438.530000 1241.420000 1439.530000 1241.900000 ;
+ RECT 1438.530000 1225.100000 1439.530000 1225.580000 ;
+ RECT 1438.530000 1230.540000 1439.530000 1231.020000 ;
+ RECT 1425.720000 1230.540000 1426.820000 1231.020000 ;
+ RECT 1425.720000 1225.100000 1426.820000 1225.580000 ;
+ RECT 1425.720000 1214.220000 1426.820000 1214.700000 ;
+ RECT 1425.720000 1219.660000 1426.820000 1220.140000 ;
+ RECT 1438.530000 1214.220000 1439.530000 1214.700000 ;
+ RECT 1438.530000 1219.660000 1439.530000 1220.140000 ;
+ RECT 1438.530000 1203.340000 1439.530000 1203.820000 ;
+ RECT 1438.530000 1197.900000 1439.530000 1198.380000 ;
+ RECT 1438.530000 1208.780000 1439.530000 1209.260000 ;
+ RECT 1425.720000 1208.780000 1426.820000 1209.260000 ;
+ RECT 1425.720000 1203.340000 1426.820000 1203.820000 ;
+ RECT 1425.720000 1197.900000 1426.820000 1198.380000 ;
+ RECT 1380.720000 1225.100000 1381.820000 1225.580000 ;
+ RECT 1380.720000 1230.540000 1381.820000 1231.020000 ;
+ RECT 1380.720000 1235.980000 1381.820000 1236.460000 ;
+ RECT 1380.720000 1241.420000 1381.820000 1241.900000 ;
+ RECT 1380.720000 1197.900000 1381.820000 1198.380000 ;
+ RECT 1380.720000 1203.340000 1381.820000 1203.820000 ;
+ RECT 1380.720000 1208.780000 1381.820000 1209.260000 ;
+ RECT 1380.720000 1214.220000 1381.820000 1214.700000 ;
+ RECT 1380.720000 1219.660000 1381.820000 1220.140000 ;
+ RECT 1425.720000 1187.020000 1426.820000 1187.500000 ;
+ RECT 1425.720000 1192.460000 1426.820000 1192.940000 ;
+ RECT 1438.530000 1187.020000 1439.530000 1187.500000 ;
+ RECT 1438.530000 1192.460000 1439.530000 1192.940000 ;
+ RECT 1425.720000 1176.140000 1426.820000 1176.620000 ;
+ RECT 1425.720000 1181.580000 1426.820000 1182.060000 ;
+ RECT 1438.530000 1176.140000 1439.530000 1176.620000 ;
+ RECT 1438.530000 1181.580000 1439.530000 1182.060000 ;
+ RECT 1438.530000 1165.260000 1439.530000 1165.740000 ;
+ RECT 1438.530000 1159.820000 1439.530000 1160.300000 ;
+ RECT 1438.530000 1170.700000 1439.530000 1171.180000 ;
+ RECT 1425.720000 1170.700000 1426.820000 1171.180000 ;
+ RECT 1425.720000 1165.260000 1426.820000 1165.740000 ;
+ RECT 1425.720000 1159.820000 1426.820000 1160.300000 ;
+ RECT 1425.720000 1154.380000 1426.820000 1154.860000 ;
+ RECT 1438.530000 1154.380000 1439.530000 1154.860000 ;
+ RECT 1380.720000 1176.140000 1381.820000 1176.620000 ;
+ RECT 1380.720000 1181.580000 1381.820000 1182.060000 ;
+ RECT 1380.720000 1187.020000 1381.820000 1187.500000 ;
+ RECT 1380.720000 1192.460000 1381.820000 1192.940000 ;
+ RECT 1380.720000 1154.380000 1381.820000 1154.860000 ;
+ RECT 1380.720000 1159.820000 1381.820000 1160.300000 ;
+ RECT 1380.720000 1165.260000 1381.820000 1165.740000 ;
+ RECT 1380.720000 1170.700000 1381.820000 1171.180000 ;
+ RECT 1335.720000 1225.100000 1336.820000 1225.580000 ;
+ RECT 1335.720000 1230.540000 1336.820000 1231.020000 ;
+ RECT 1335.720000 1235.980000 1336.820000 1236.460000 ;
+ RECT 1335.720000 1241.420000 1336.820000 1241.900000 ;
+ RECT 1290.720000 1225.100000 1291.820000 1225.580000 ;
+ RECT 1290.720000 1230.540000 1291.820000 1231.020000 ;
+ RECT 1290.720000 1235.980000 1291.820000 1236.460000 ;
+ RECT 1290.720000 1241.420000 1291.820000 1241.900000 ;
+ RECT 1335.720000 1197.900000 1336.820000 1198.380000 ;
+ RECT 1335.720000 1203.340000 1336.820000 1203.820000 ;
+ RECT 1335.720000 1208.780000 1336.820000 1209.260000 ;
+ RECT 1335.720000 1214.220000 1336.820000 1214.700000 ;
+ RECT 1335.720000 1219.660000 1336.820000 1220.140000 ;
+ RECT 1290.720000 1197.900000 1291.820000 1198.380000 ;
+ RECT 1290.720000 1203.340000 1291.820000 1203.820000 ;
+ RECT 1290.720000 1208.780000 1291.820000 1209.260000 ;
+ RECT 1290.720000 1214.220000 1291.820000 1214.700000 ;
+ RECT 1290.720000 1219.660000 1291.820000 1220.140000 ;
+ RECT 1241.890000 1241.420000 1242.890000 1241.900000 ;
+ RECT 1245.555000 1241.420000 1246.820000 1241.900000 ;
+ RECT 1241.890000 1235.980000 1242.890000 1236.460000 ;
+ RECT 1245.555000 1235.980000 1246.820000 1236.460000 ;
+ RECT 1241.890000 1230.540000 1242.890000 1231.020000 ;
+ RECT 1245.555000 1230.540000 1246.820000 1231.020000 ;
+ RECT 1241.890000 1225.100000 1242.890000 1225.580000 ;
+ RECT 1245.555000 1225.100000 1246.820000 1225.580000 ;
+ RECT 1241.890000 1219.660000 1242.890000 1220.140000 ;
+ RECT 1245.555000 1219.660000 1246.820000 1220.140000 ;
+ RECT 1241.890000 1214.220000 1242.890000 1214.700000 ;
+ RECT 1245.555000 1214.220000 1246.820000 1214.700000 ;
+ RECT 1241.890000 1203.340000 1242.890000 1203.820000 ;
+ RECT 1245.555000 1203.340000 1246.820000 1203.820000 ;
+ RECT 1241.890000 1208.780000 1242.890000 1209.260000 ;
+ RECT 1245.555000 1208.780000 1246.820000 1209.260000 ;
+ RECT 1241.890000 1197.900000 1242.890000 1198.380000 ;
+ RECT 1245.555000 1197.900000 1246.820000 1198.380000 ;
+ RECT 1335.720000 1176.140000 1336.820000 1176.620000 ;
+ RECT 1335.720000 1181.580000 1336.820000 1182.060000 ;
+ RECT 1335.720000 1187.020000 1336.820000 1187.500000 ;
+ RECT 1335.720000 1192.460000 1336.820000 1192.940000 ;
+ RECT 1290.720000 1176.140000 1291.820000 1176.620000 ;
+ RECT 1290.720000 1181.580000 1291.820000 1182.060000 ;
+ RECT 1290.720000 1187.020000 1291.820000 1187.500000 ;
+ RECT 1290.720000 1192.460000 1291.820000 1192.940000 ;
+ RECT 1335.720000 1154.380000 1336.820000 1154.860000 ;
+ RECT 1335.720000 1159.820000 1336.820000 1160.300000 ;
+ RECT 1335.720000 1165.260000 1336.820000 1165.740000 ;
+ RECT 1335.720000 1170.700000 1336.820000 1171.180000 ;
+ RECT 1290.720000 1154.380000 1291.820000 1154.860000 ;
+ RECT 1290.720000 1159.820000 1291.820000 1160.300000 ;
+ RECT 1290.720000 1165.260000 1291.820000 1165.740000 ;
+ RECT 1290.720000 1170.700000 1291.820000 1171.180000 ;
+ RECT 1241.890000 1192.460000 1242.890000 1192.940000 ;
+ RECT 1245.555000 1192.460000 1246.820000 1192.940000 ;
+ RECT 1241.890000 1187.020000 1242.890000 1187.500000 ;
+ RECT 1245.555000 1187.020000 1246.820000 1187.500000 ;
+ RECT 1241.890000 1181.580000 1242.890000 1182.060000 ;
+ RECT 1245.555000 1181.580000 1246.820000 1182.060000 ;
+ RECT 1241.890000 1176.140000 1242.890000 1176.620000 ;
+ RECT 1245.555000 1176.140000 1246.820000 1176.620000 ;
+ RECT 1241.890000 1170.700000 1242.890000 1171.180000 ;
+ RECT 1245.555000 1170.700000 1246.820000 1171.180000 ;
+ RECT 1241.890000 1159.820000 1242.890000 1160.300000 ;
+ RECT 1245.555000 1159.820000 1246.820000 1160.300000 ;
+ RECT 1241.890000 1165.260000 1242.890000 1165.740000 ;
+ RECT 1245.555000 1165.260000 1246.820000 1165.740000 ;
+ RECT 1241.890000 1154.380000 1242.890000 1154.860000 ;
+ RECT 1245.555000 1154.380000 1246.820000 1154.860000 ;
+ RECT 1380.720000 1246.860000 1381.820000 1247.340000 ;
+ RECT 1425.720000 1246.860000 1426.820000 1247.340000 ;
+ RECT 1438.530000 1246.860000 1439.530000 1247.340000 ;
+ RECT 1290.720000 1246.860000 1291.820000 1247.340000 ;
+ RECT 1335.720000 1246.860000 1336.820000 1247.340000 ;
+ RECT 1241.890000 1246.860000 1242.890000 1247.340000 ;
+ RECT 1245.555000 1246.860000 1246.820000 1247.340000 ;
+ RECT 1240.660000 1343.620000 1440.760000 1344.620000 ;
+ RECT 1240.660000 1148.050000 1440.760000 1149.050000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 1146.800000 1242.890000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 1346.060000 1242.890000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 1146.800000 1439.530000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 1346.060000 1439.530000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1148.050000 1241.660000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1148.050000 1440.760000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1343.620000 1241.660000 1344.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1343.620000 1440.760000 1344.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 1139.080000 1246.820000 1139.560000 ;
+ RECT 1245.555000 1128.200000 1246.820000 1128.680000 ;
+ RECT 1245.555000 1133.640000 1246.820000 1134.120000 ;
+ RECT 1245.555000 1122.760000 1246.820000 1123.240000 ;
+ RECT 1245.555000 1117.320000 1246.820000 1117.800000 ;
+ RECT 1245.555000 1111.880000 1246.820000 1112.360000 ;
+ RECT 1245.555000 1106.440000 1246.820000 1106.920000 ;
+ RECT 1245.555000 1101.000000 1246.820000 1101.480000 ;
+ RECT 1245.555000 1095.560000 1246.820000 1096.040000 ;
+ RECT 1245.555000 1084.680000 1246.820000 1085.160000 ;
+ RECT 1245.555000 1090.120000 1246.820000 1090.600000 ;
+ RECT 1245.555000 1079.240000 1246.820000 1079.720000 ;
+ RECT 1245.555000 1073.800000 1246.820000 1074.280000 ;
+ RECT 1245.555000 1068.360000 1246.820000 1068.840000 ;
+ RECT 1245.555000 1062.920000 1246.820000 1063.400000 ;
+ RECT 1245.555000 1057.480000 1246.820000 1057.960000 ;
+ RECT 1245.555000 1052.040000 1246.820000 1052.520000 ;
+ RECT 1245.555000 1041.160000 1246.820000 1041.640000 ;
+ RECT 1245.555000 1035.720000 1246.820000 1036.200000 ;
+ RECT 1245.555000 1030.280000 1246.820000 1030.760000 ;
+ RECT 1245.555000 1024.840000 1246.820000 1025.320000 ;
+ RECT 1245.555000 1019.400000 1246.820000 1019.880000 ;
+ RECT 1245.555000 1013.960000 1246.820000 1014.440000 ;
+ RECT 1245.555000 1003.080000 1246.820000 1003.560000 ;
+ RECT 1245.555000 1008.520000 1246.820000 1009.000000 ;
+ RECT 1245.555000 997.640000 1246.820000 998.120000 ;
+ RECT 1245.555000 992.200000 1246.820000 992.680000 ;
+ RECT 1245.555000 986.760000 1246.820000 987.240000 ;
+ RECT 1245.555000 981.320000 1246.820000 981.800000 ;
+ RECT 1245.555000 975.880000 1246.820000 976.360000 ;
+ RECT 1245.555000 970.440000 1246.820000 970.920000 ;
+ RECT 1245.555000 959.560000 1246.820000 960.040000 ;
+ RECT 1245.555000 965.000000 1246.820000 965.480000 ;
+ RECT 1245.555000 954.120000 1246.820000 954.600000 ;
+ RECT 1245.555000 1046.600000 1246.820000 1047.080000 ;
+ RECT 1425.720000 947.790000 1426.820000 1144.360000 ;
+ RECT 1380.720000 947.790000 1381.820000 1144.360000 ;
+ RECT 1438.530000 946.540000 1439.530000 1146.800000 ;
+ RECT 1335.720000 947.790000 1336.820000 1144.360000 ;
+ RECT 1290.720000 947.790000 1291.820000 1144.360000 ;
+ RECT 1245.720000 947.790000 1246.820000 1144.360000 ;
+ RECT 1241.890000 946.540000 1242.890000 1146.800000 ;
+ LAYER met3 ;
+ RECT 1425.720000 1139.080000 1426.820000 1139.560000 ;
+ RECT 1438.530000 1139.080000 1439.530000 1139.560000 ;
+ RECT 1438.530000 1128.200000 1439.530000 1128.680000 ;
+ RECT 1438.530000 1122.760000 1439.530000 1123.240000 ;
+ RECT 1438.530000 1133.640000 1439.530000 1134.120000 ;
+ RECT 1425.720000 1133.640000 1426.820000 1134.120000 ;
+ RECT 1425.720000 1128.200000 1426.820000 1128.680000 ;
+ RECT 1425.720000 1122.760000 1426.820000 1123.240000 ;
+ RECT 1425.720000 1111.880000 1426.820000 1112.360000 ;
+ RECT 1425.720000 1117.320000 1426.820000 1117.800000 ;
+ RECT 1438.530000 1111.880000 1439.530000 1112.360000 ;
+ RECT 1438.530000 1117.320000 1439.530000 1117.800000 ;
+ RECT 1425.720000 1101.000000 1426.820000 1101.480000 ;
+ RECT 1425.720000 1106.440000 1426.820000 1106.920000 ;
+ RECT 1438.530000 1101.000000 1439.530000 1101.480000 ;
+ RECT 1438.530000 1106.440000 1439.530000 1106.920000 ;
+ RECT 1380.720000 1122.760000 1381.820000 1123.240000 ;
+ RECT 1380.720000 1128.200000 1381.820000 1128.680000 ;
+ RECT 1380.720000 1133.640000 1381.820000 1134.120000 ;
+ RECT 1380.720000 1139.080000 1381.820000 1139.560000 ;
+ RECT 1380.720000 1106.440000 1381.820000 1106.920000 ;
+ RECT 1380.720000 1101.000000 1381.820000 1101.480000 ;
+ RECT 1380.720000 1111.880000 1381.820000 1112.360000 ;
+ RECT 1380.720000 1117.320000 1381.820000 1117.800000 ;
+ RECT 1438.530000 1090.120000 1439.530000 1090.600000 ;
+ RECT 1438.530000 1084.680000 1439.530000 1085.160000 ;
+ RECT 1438.530000 1095.560000 1439.530000 1096.040000 ;
+ RECT 1425.720000 1095.560000 1426.820000 1096.040000 ;
+ RECT 1425.720000 1090.120000 1426.820000 1090.600000 ;
+ RECT 1425.720000 1084.680000 1426.820000 1085.160000 ;
+ RECT 1425.720000 1073.800000 1426.820000 1074.280000 ;
+ RECT 1425.720000 1079.240000 1426.820000 1079.720000 ;
+ RECT 1438.530000 1073.800000 1439.530000 1074.280000 ;
+ RECT 1438.530000 1079.240000 1439.530000 1079.720000 ;
+ RECT 1438.530000 1062.920000 1439.530000 1063.400000 ;
+ RECT 1438.530000 1068.360000 1439.530000 1068.840000 ;
+ RECT 1425.720000 1068.360000 1426.820000 1068.840000 ;
+ RECT 1425.720000 1062.920000 1426.820000 1063.400000 ;
+ RECT 1425.720000 1052.040000 1426.820000 1052.520000 ;
+ RECT 1425.720000 1057.480000 1426.820000 1057.960000 ;
+ RECT 1438.530000 1052.040000 1439.530000 1052.520000 ;
+ RECT 1438.530000 1057.480000 1439.530000 1057.960000 ;
+ RECT 1380.720000 1073.800000 1381.820000 1074.280000 ;
+ RECT 1380.720000 1079.240000 1381.820000 1079.720000 ;
+ RECT 1380.720000 1084.680000 1381.820000 1085.160000 ;
+ RECT 1380.720000 1090.120000 1381.820000 1090.600000 ;
+ RECT 1380.720000 1095.560000 1381.820000 1096.040000 ;
+ RECT 1380.720000 1052.040000 1381.820000 1052.520000 ;
+ RECT 1380.720000 1057.480000 1381.820000 1057.960000 ;
+ RECT 1380.720000 1062.920000 1381.820000 1063.400000 ;
+ RECT 1380.720000 1068.360000 1381.820000 1068.840000 ;
+ RECT 1335.720000 1128.200000 1336.820000 1128.680000 ;
+ RECT 1335.720000 1122.760000 1336.820000 1123.240000 ;
+ RECT 1335.720000 1133.640000 1336.820000 1134.120000 ;
+ RECT 1335.720000 1139.080000 1336.820000 1139.560000 ;
+ RECT 1290.720000 1122.760000 1291.820000 1123.240000 ;
+ RECT 1290.720000 1128.200000 1291.820000 1128.680000 ;
+ RECT 1290.720000 1133.640000 1291.820000 1134.120000 ;
+ RECT 1290.720000 1139.080000 1291.820000 1139.560000 ;
+ RECT 1335.720000 1101.000000 1336.820000 1101.480000 ;
+ RECT 1335.720000 1106.440000 1336.820000 1106.920000 ;
+ RECT 1335.720000 1111.880000 1336.820000 1112.360000 ;
+ RECT 1335.720000 1117.320000 1336.820000 1117.800000 ;
+ RECT 1290.720000 1101.000000 1291.820000 1101.480000 ;
+ RECT 1290.720000 1106.440000 1291.820000 1106.920000 ;
+ RECT 1290.720000 1111.880000 1291.820000 1112.360000 ;
+ RECT 1290.720000 1117.320000 1291.820000 1117.800000 ;
+ RECT 1241.890000 1139.080000 1242.890000 1139.560000 ;
+ RECT 1245.555000 1139.080000 1246.820000 1139.560000 ;
+ RECT 1241.890000 1128.200000 1242.890000 1128.680000 ;
+ RECT 1245.555000 1128.200000 1246.820000 1128.680000 ;
+ RECT 1241.890000 1133.640000 1242.890000 1134.120000 ;
+ RECT 1245.555000 1133.640000 1246.820000 1134.120000 ;
+ RECT 1241.890000 1122.760000 1242.890000 1123.240000 ;
+ RECT 1245.555000 1122.760000 1246.820000 1123.240000 ;
+ RECT 1241.890000 1117.320000 1242.890000 1117.800000 ;
+ RECT 1245.555000 1117.320000 1246.820000 1117.800000 ;
+ RECT 1241.890000 1111.880000 1242.890000 1112.360000 ;
+ RECT 1245.555000 1111.880000 1246.820000 1112.360000 ;
+ RECT 1241.890000 1106.440000 1242.890000 1106.920000 ;
+ RECT 1245.555000 1106.440000 1246.820000 1106.920000 ;
+ RECT 1241.890000 1101.000000 1242.890000 1101.480000 ;
+ RECT 1245.555000 1101.000000 1246.820000 1101.480000 ;
+ RECT 1335.720000 1073.800000 1336.820000 1074.280000 ;
+ RECT 1335.720000 1079.240000 1336.820000 1079.720000 ;
+ RECT 1335.720000 1084.680000 1336.820000 1085.160000 ;
+ RECT 1335.720000 1090.120000 1336.820000 1090.600000 ;
+ RECT 1335.720000 1095.560000 1336.820000 1096.040000 ;
+ RECT 1290.720000 1073.800000 1291.820000 1074.280000 ;
+ RECT 1290.720000 1079.240000 1291.820000 1079.720000 ;
+ RECT 1290.720000 1084.680000 1291.820000 1085.160000 ;
+ RECT 1290.720000 1090.120000 1291.820000 1090.600000 ;
+ RECT 1290.720000 1095.560000 1291.820000 1096.040000 ;
+ RECT 1335.720000 1052.040000 1336.820000 1052.520000 ;
+ RECT 1335.720000 1057.480000 1336.820000 1057.960000 ;
+ RECT 1335.720000 1062.920000 1336.820000 1063.400000 ;
+ RECT 1335.720000 1068.360000 1336.820000 1068.840000 ;
+ RECT 1290.720000 1052.040000 1291.820000 1052.520000 ;
+ RECT 1290.720000 1057.480000 1291.820000 1057.960000 ;
+ RECT 1290.720000 1062.920000 1291.820000 1063.400000 ;
+ RECT 1290.720000 1068.360000 1291.820000 1068.840000 ;
+ RECT 1241.890000 1095.560000 1242.890000 1096.040000 ;
+ RECT 1245.555000 1095.560000 1246.820000 1096.040000 ;
+ RECT 1241.890000 1084.680000 1242.890000 1085.160000 ;
+ RECT 1245.555000 1084.680000 1246.820000 1085.160000 ;
+ RECT 1241.890000 1090.120000 1242.890000 1090.600000 ;
+ RECT 1245.555000 1090.120000 1246.820000 1090.600000 ;
+ RECT 1241.890000 1079.240000 1242.890000 1079.720000 ;
+ RECT 1245.555000 1079.240000 1246.820000 1079.720000 ;
+ RECT 1241.890000 1073.800000 1242.890000 1074.280000 ;
+ RECT 1245.555000 1073.800000 1246.820000 1074.280000 ;
+ RECT 1241.890000 1068.360000 1242.890000 1068.840000 ;
+ RECT 1245.555000 1068.360000 1246.820000 1068.840000 ;
+ RECT 1241.890000 1062.920000 1242.890000 1063.400000 ;
+ RECT 1245.555000 1062.920000 1246.820000 1063.400000 ;
+ RECT 1241.890000 1057.480000 1242.890000 1057.960000 ;
+ RECT 1245.555000 1057.480000 1246.820000 1057.960000 ;
+ RECT 1241.890000 1052.040000 1242.890000 1052.520000 ;
+ RECT 1245.555000 1052.040000 1246.820000 1052.520000 ;
+ RECT 1425.720000 1035.720000 1426.820000 1036.200000 ;
+ RECT 1425.720000 1041.160000 1426.820000 1041.640000 ;
+ RECT 1438.530000 1035.720000 1439.530000 1036.200000 ;
+ RECT 1438.530000 1041.160000 1439.530000 1041.640000 ;
+ RECT 1438.530000 1024.840000 1439.530000 1025.320000 ;
+ RECT 1438.530000 1030.280000 1439.530000 1030.760000 ;
+ RECT 1425.720000 1030.280000 1426.820000 1030.760000 ;
+ RECT 1425.720000 1024.840000 1426.820000 1025.320000 ;
+ RECT 1425.720000 1013.960000 1426.820000 1014.440000 ;
+ RECT 1425.720000 1019.400000 1426.820000 1019.880000 ;
+ RECT 1438.530000 1013.960000 1439.530000 1014.440000 ;
+ RECT 1438.530000 1019.400000 1439.530000 1019.880000 ;
+ RECT 1438.530000 1003.080000 1439.530000 1003.560000 ;
+ RECT 1438.530000 997.640000 1439.530000 998.120000 ;
+ RECT 1438.530000 1008.520000 1439.530000 1009.000000 ;
+ RECT 1425.720000 1008.520000 1426.820000 1009.000000 ;
+ RECT 1425.720000 1003.080000 1426.820000 1003.560000 ;
+ RECT 1425.720000 997.640000 1426.820000 998.120000 ;
+ RECT 1380.720000 1024.840000 1381.820000 1025.320000 ;
+ RECT 1380.720000 1030.280000 1381.820000 1030.760000 ;
+ RECT 1380.720000 1035.720000 1381.820000 1036.200000 ;
+ RECT 1380.720000 1041.160000 1381.820000 1041.640000 ;
+ RECT 1380.720000 997.640000 1381.820000 998.120000 ;
+ RECT 1380.720000 1003.080000 1381.820000 1003.560000 ;
+ RECT 1380.720000 1008.520000 1381.820000 1009.000000 ;
+ RECT 1380.720000 1013.960000 1381.820000 1014.440000 ;
+ RECT 1380.720000 1019.400000 1381.820000 1019.880000 ;
+ RECT 1425.720000 986.760000 1426.820000 987.240000 ;
+ RECT 1425.720000 992.200000 1426.820000 992.680000 ;
+ RECT 1438.530000 986.760000 1439.530000 987.240000 ;
+ RECT 1438.530000 992.200000 1439.530000 992.680000 ;
+ RECT 1425.720000 975.880000 1426.820000 976.360000 ;
+ RECT 1425.720000 981.320000 1426.820000 981.800000 ;
+ RECT 1438.530000 975.880000 1439.530000 976.360000 ;
+ RECT 1438.530000 981.320000 1439.530000 981.800000 ;
+ RECT 1438.530000 965.000000 1439.530000 965.480000 ;
+ RECT 1438.530000 959.560000 1439.530000 960.040000 ;
+ RECT 1438.530000 970.440000 1439.530000 970.920000 ;
+ RECT 1425.720000 970.440000 1426.820000 970.920000 ;
+ RECT 1425.720000 965.000000 1426.820000 965.480000 ;
+ RECT 1425.720000 959.560000 1426.820000 960.040000 ;
+ RECT 1425.720000 954.120000 1426.820000 954.600000 ;
+ RECT 1438.530000 954.120000 1439.530000 954.600000 ;
+ RECT 1380.720000 975.880000 1381.820000 976.360000 ;
+ RECT 1380.720000 981.320000 1381.820000 981.800000 ;
+ RECT 1380.720000 986.760000 1381.820000 987.240000 ;
+ RECT 1380.720000 992.200000 1381.820000 992.680000 ;
+ RECT 1380.720000 954.120000 1381.820000 954.600000 ;
+ RECT 1380.720000 959.560000 1381.820000 960.040000 ;
+ RECT 1380.720000 965.000000 1381.820000 965.480000 ;
+ RECT 1380.720000 970.440000 1381.820000 970.920000 ;
+ RECT 1335.720000 1024.840000 1336.820000 1025.320000 ;
+ RECT 1335.720000 1030.280000 1336.820000 1030.760000 ;
+ RECT 1335.720000 1035.720000 1336.820000 1036.200000 ;
+ RECT 1335.720000 1041.160000 1336.820000 1041.640000 ;
+ RECT 1290.720000 1024.840000 1291.820000 1025.320000 ;
+ RECT 1290.720000 1030.280000 1291.820000 1030.760000 ;
+ RECT 1290.720000 1035.720000 1291.820000 1036.200000 ;
+ RECT 1290.720000 1041.160000 1291.820000 1041.640000 ;
+ RECT 1335.720000 997.640000 1336.820000 998.120000 ;
+ RECT 1335.720000 1003.080000 1336.820000 1003.560000 ;
+ RECT 1335.720000 1008.520000 1336.820000 1009.000000 ;
+ RECT 1335.720000 1013.960000 1336.820000 1014.440000 ;
+ RECT 1335.720000 1019.400000 1336.820000 1019.880000 ;
+ RECT 1290.720000 997.640000 1291.820000 998.120000 ;
+ RECT 1290.720000 1003.080000 1291.820000 1003.560000 ;
+ RECT 1290.720000 1008.520000 1291.820000 1009.000000 ;
+ RECT 1290.720000 1013.960000 1291.820000 1014.440000 ;
+ RECT 1290.720000 1019.400000 1291.820000 1019.880000 ;
+ RECT 1241.890000 1041.160000 1242.890000 1041.640000 ;
+ RECT 1245.555000 1041.160000 1246.820000 1041.640000 ;
+ RECT 1241.890000 1035.720000 1242.890000 1036.200000 ;
+ RECT 1245.555000 1035.720000 1246.820000 1036.200000 ;
+ RECT 1241.890000 1030.280000 1242.890000 1030.760000 ;
+ RECT 1245.555000 1030.280000 1246.820000 1030.760000 ;
+ RECT 1241.890000 1024.840000 1242.890000 1025.320000 ;
+ RECT 1245.555000 1024.840000 1246.820000 1025.320000 ;
+ RECT 1241.890000 1019.400000 1242.890000 1019.880000 ;
+ RECT 1245.555000 1019.400000 1246.820000 1019.880000 ;
+ RECT 1241.890000 1013.960000 1242.890000 1014.440000 ;
+ RECT 1245.555000 1013.960000 1246.820000 1014.440000 ;
+ RECT 1241.890000 1003.080000 1242.890000 1003.560000 ;
+ RECT 1245.555000 1003.080000 1246.820000 1003.560000 ;
+ RECT 1241.890000 1008.520000 1242.890000 1009.000000 ;
+ RECT 1245.555000 1008.520000 1246.820000 1009.000000 ;
+ RECT 1241.890000 997.640000 1242.890000 998.120000 ;
+ RECT 1245.555000 997.640000 1246.820000 998.120000 ;
+ RECT 1335.720000 975.880000 1336.820000 976.360000 ;
+ RECT 1335.720000 981.320000 1336.820000 981.800000 ;
+ RECT 1335.720000 986.760000 1336.820000 987.240000 ;
+ RECT 1335.720000 992.200000 1336.820000 992.680000 ;
+ RECT 1290.720000 975.880000 1291.820000 976.360000 ;
+ RECT 1290.720000 981.320000 1291.820000 981.800000 ;
+ RECT 1290.720000 986.760000 1291.820000 987.240000 ;
+ RECT 1290.720000 992.200000 1291.820000 992.680000 ;
+ RECT 1335.720000 954.120000 1336.820000 954.600000 ;
+ RECT 1335.720000 959.560000 1336.820000 960.040000 ;
+ RECT 1335.720000 965.000000 1336.820000 965.480000 ;
+ RECT 1335.720000 970.440000 1336.820000 970.920000 ;
+ RECT 1290.720000 954.120000 1291.820000 954.600000 ;
+ RECT 1290.720000 959.560000 1291.820000 960.040000 ;
+ RECT 1290.720000 965.000000 1291.820000 965.480000 ;
+ RECT 1290.720000 970.440000 1291.820000 970.920000 ;
+ RECT 1241.890000 992.200000 1242.890000 992.680000 ;
+ RECT 1245.555000 992.200000 1246.820000 992.680000 ;
+ RECT 1241.890000 986.760000 1242.890000 987.240000 ;
+ RECT 1245.555000 986.760000 1246.820000 987.240000 ;
+ RECT 1241.890000 981.320000 1242.890000 981.800000 ;
+ RECT 1245.555000 981.320000 1246.820000 981.800000 ;
+ RECT 1241.890000 975.880000 1242.890000 976.360000 ;
+ RECT 1245.555000 975.880000 1246.820000 976.360000 ;
+ RECT 1241.890000 970.440000 1242.890000 970.920000 ;
+ RECT 1245.555000 970.440000 1246.820000 970.920000 ;
+ RECT 1241.890000 959.560000 1242.890000 960.040000 ;
+ RECT 1245.555000 959.560000 1246.820000 960.040000 ;
+ RECT 1241.890000 965.000000 1242.890000 965.480000 ;
+ RECT 1245.555000 965.000000 1246.820000 965.480000 ;
+ RECT 1241.890000 954.120000 1242.890000 954.600000 ;
+ RECT 1245.555000 954.120000 1246.820000 954.600000 ;
+ RECT 1380.720000 1046.600000 1381.820000 1047.080000 ;
+ RECT 1425.720000 1046.600000 1426.820000 1047.080000 ;
+ RECT 1438.530000 1046.600000 1439.530000 1047.080000 ;
+ RECT 1290.720000 1046.600000 1291.820000 1047.080000 ;
+ RECT 1335.720000 1046.600000 1336.820000 1047.080000 ;
+ RECT 1241.890000 1046.600000 1242.890000 1047.080000 ;
+ RECT 1245.555000 1046.600000 1246.820000 1047.080000 ;
+ RECT 1240.660000 1143.360000 1440.760000 1144.360000 ;
+ RECT 1240.660000 947.790000 1440.760000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 946.540000 1242.890000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 1145.800000 1242.890000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 946.540000 1439.530000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 1145.800000 1439.530000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 947.790000 1241.660000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 947.790000 1440.760000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1143.360000 1241.660000 1144.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1143.360000 1440.760000 1144.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 938.820000 1246.820000 939.300000 ;
+ RECT 1245.555000 927.940000 1246.820000 928.420000 ;
+ RECT 1245.555000 933.380000 1246.820000 933.860000 ;
+ RECT 1245.555000 922.500000 1246.820000 922.980000 ;
+ RECT 1245.555000 917.060000 1246.820000 917.540000 ;
+ RECT 1245.555000 911.620000 1246.820000 912.100000 ;
+ RECT 1245.555000 906.180000 1246.820000 906.660000 ;
+ RECT 1245.555000 900.740000 1246.820000 901.220000 ;
+ RECT 1245.555000 895.300000 1246.820000 895.780000 ;
+ RECT 1245.555000 884.420000 1246.820000 884.900000 ;
+ RECT 1245.555000 889.860000 1246.820000 890.340000 ;
+ RECT 1245.555000 878.980000 1246.820000 879.460000 ;
+ RECT 1245.555000 873.540000 1246.820000 874.020000 ;
+ RECT 1245.555000 868.100000 1246.820000 868.580000 ;
+ RECT 1245.555000 862.660000 1246.820000 863.140000 ;
+ RECT 1245.555000 857.220000 1246.820000 857.700000 ;
+ RECT 1245.555000 851.780000 1246.820000 852.260000 ;
+ RECT 1245.555000 840.900000 1246.820000 841.380000 ;
+ RECT 1245.555000 835.460000 1246.820000 835.940000 ;
+ RECT 1245.555000 830.020000 1246.820000 830.500000 ;
+ RECT 1245.555000 824.580000 1246.820000 825.060000 ;
+ RECT 1245.555000 819.140000 1246.820000 819.620000 ;
+ RECT 1245.555000 813.700000 1246.820000 814.180000 ;
+ RECT 1245.555000 802.820000 1246.820000 803.300000 ;
+ RECT 1245.555000 808.260000 1246.820000 808.740000 ;
+ RECT 1245.555000 797.380000 1246.820000 797.860000 ;
+ RECT 1245.555000 791.940000 1246.820000 792.420000 ;
+ RECT 1245.555000 786.500000 1246.820000 786.980000 ;
+ RECT 1245.555000 781.060000 1246.820000 781.540000 ;
+ RECT 1245.555000 775.620000 1246.820000 776.100000 ;
+ RECT 1245.555000 770.180000 1246.820000 770.660000 ;
+ RECT 1245.555000 759.300000 1246.820000 759.780000 ;
+ RECT 1245.555000 764.740000 1246.820000 765.220000 ;
+ RECT 1245.555000 753.860000 1246.820000 754.340000 ;
+ RECT 1245.555000 846.340000 1246.820000 846.820000 ;
+ RECT 1425.720000 747.530000 1426.820000 944.100000 ;
+ RECT 1380.720000 747.530000 1381.820000 944.100000 ;
+ RECT 1438.530000 746.280000 1439.530000 946.540000 ;
+ RECT 1335.720000 747.530000 1336.820000 944.100000 ;
+ RECT 1290.720000 747.530000 1291.820000 944.100000 ;
+ RECT 1245.720000 747.530000 1246.820000 944.100000 ;
+ RECT 1241.890000 746.280000 1242.890000 946.540000 ;
+ LAYER met3 ;
+ RECT 1425.720000 938.820000 1426.820000 939.300000 ;
+ RECT 1438.530000 938.820000 1439.530000 939.300000 ;
+ RECT 1438.530000 927.940000 1439.530000 928.420000 ;
+ RECT 1438.530000 922.500000 1439.530000 922.980000 ;
+ RECT 1438.530000 933.380000 1439.530000 933.860000 ;
+ RECT 1425.720000 933.380000 1426.820000 933.860000 ;
+ RECT 1425.720000 927.940000 1426.820000 928.420000 ;
+ RECT 1425.720000 922.500000 1426.820000 922.980000 ;
+ RECT 1425.720000 911.620000 1426.820000 912.100000 ;
+ RECT 1425.720000 917.060000 1426.820000 917.540000 ;
+ RECT 1438.530000 911.620000 1439.530000 912.100000 ;
+ RECT 1438.530000 917.060000 1439.530000 917.540000 ;
+ RECT 1425.720000 900.740000 1426.820000 901.220000 ;
+ RECT 1425.720000 906.180000 1426.820000 906.660000 ;
+ RECT 1438.530000 900.740000 1439.530000 901.220000 ;
+ RECT 1438.530000 906.180000 1439.530000 906.660000 ;
+ RECT 1380.720000 922.500000 1381.820000 922.980000 ;
+ RECT 1380.720000 927.940000 1381.820000 928.420000 ;
+ RECT 1380.720000 933.380000 1381.820000 933.860000 ;
+ RECT 1380.720000 938.820000 1381.820000 939.300000 ;
+ RECT 1380.720000 906.180000 1381.820000 906.660000 ;
+ RECT 1380.720000 900.740000 1381.820000 901.220000 ;
+ RECT 1380.720000 911.620000 1381.820000 912.100000 ;
+ RECT 1380.720000 917.060000 1381.820000 917.540000 ;
+ RECT 1438.530000 889.860000 1439.530000 890.340000 ;
+ RECT 1438.530000 884.420000 1439.530000 884.900000 ;
+ RECT 1438.530000 895.300000 1439.530000 895.780000 ;
+ RECT 1425.720000 895.300000 1426.820000 895.780000 ;
+ RECT 1425.720000 889.860000 1426.820000 890.340000 ;
+ RECT 1425.720000 884.420000 1426.820000 884.900000 ;
+ RECT 1425.720000 873.540000 1426.820000 874.020000 ;
+ RECT 1425.720000 878.980000 1426.820000 879.460000 ;
+ RECT 1438.530000 873.540000 1439.530000 874.020000 ;
+ RECT 1438.530000 878.980000 1439.530000 879.460000 ;
+ RECT 1438.530000 862.660000 1439.530000 863.140000 ;
+ RECT 1438.530000 868.100000 1439.530000 868.580000 ;
+ RECT 1425.720000 868.100000 1426.820000 868.580000 ;
+ RECT 1425.720000 862.660000 1426.820000 863.140000 ;
+ RECT 1425.720000 851.780000 1426.820000 852.260000 ;
+ RECT 1425.720000 857.220000 1426.820000 857.700000 ;
+ RECT 1438.530000 851.780000 1439.530000 852.260000 ;
+ RECT 1438.530000 857.220000 1439.530000 857.700000 ;
+ RECT 1380.720000 873.540000 1381.820000 874.020000 ;
+ RECT 1380.720000 878.980000 1381.820000 879.460000 ;
+ RECT 1380.720000 884.420000 1381.820000 884.900000 ;
+ RECT 1380.720000 889.860000 1381.820000 890.340000 ;
+ RECT 1380.720000 895.300000 1381.820000 895.780000 ;
+ RECT 1380.720000 851.780000 1381.820000 852.260000 ;
+ RECT 1380.720000 857.220000 1381.820000 857.700000 ;
+ RECT 1380.720000 862.660000 1381.820000 863.140000 ;
+ RECT 1380.720000 868.100000 1381.820000 868.580000 ;
+ RECT 1335.720000 927.940000 1336.820000 928.420000 ;
+ RECT 1335.720000 922.500000 1336.820000 922.980000 ;
+ RECT 1335.720000 933.380000 1336.820000 933.860000 ;
+ RECT 1335.720000 938.820000 1336.820000 939.300000 ;
+ RECT 1290.720000 922.500000 1291.820000 922.980000 ;
+ RECT 1290.720000 927.940000 1291.820000 928.420000 ;
+ RECT 1290.720000 933.380000 1291.820000 933.860000 ;
+ RECT 1290.720000 938.820000 1291.820000 939.300000 ;
+ RECT 1335.720000 900.740000 1336.820000 901.220000 ;
+ RECT 1335.720000 906.180000 1336.820000 906.660000 ;
+ RECT 1335.720000 911.620000 1336.820000 912.100000 ;
+ RECT 1335.720000 917.060000 1336.820000 917.540000 ;
+ RECT 1290.720000 900.740000 1291.820000 901.220000 ;
+ RECT 1290.720000 906.180000 1291.820000 906.660000 ;
+ RECT 1290.720000 911.620000 1291.820000 912.100000 ;
+ RECT 1290.720000 917.060000 1291.820000 917.540000 ;
+ RECT 1241.890000 938.820000 1242.890000 939.300000 ;
+ RECT 1245.555000 938.820000 1246.820000 939.300000 ;
+ RECT 1241.890000 927.940000 1242.890000 928.420000 ;
+ RECT 1245.555000 927.940000 1246.820000 928.420000 ;
+ RECT 1241.890000 933.380000 1242.890000 933.860000 ;
+ RECT 1245.555000 933.380000 1246.820000 933.860000 ;
+ RECT 1241.890000 922.500000 1242.890000 922.980000 ;
+ RECT 1245.555000 922.500000 1246.820000 922.980000 ;
+ RECT 1241.890000 917.060000 1242.890000 917.540000 ;
+ RECT 1245.555000 917.060000 1246.820000 917.540000 ;
+ RECT 1241.890000 911.620000 1242.890000 912.100000 ;
+ RECT 1245.555000 911.620000 1246.820000 912.100000 ;
+ RECT 1241.890000 906.180000 1242.890000 906.660000 ;
+ RECT 1245.555000 906.180000 1246.820000 906.660000 ;
+ RECT 1241.890000 900.740000 1242.890000 901.220000 ;
+ RECT 1245.555000 900.740000 1246.820000 901.220000 ;
+ RECT 1335.720000 873.540000 1336.820000 874.020000 ;
+ RECT 1335.720000 878.980000 1336.820000 879.460000 ;
+ RECT 1335.720000 884.420000 1336.820000 884.900000 ;
+ RECT 1335.720000 889.860000 1336.820000 890.340000 ;
+ RECT 1335.720000 895.300000 1336.820000 895.780000 ;
+ RECT 1290.720000 873.540000 1291.820000 874.020000 ;
+ RECT 1290.720000 878.980000 1291.820000 879.460000 ;
+ RECT 1290.720000 884.420000 1291.820000 884.900000 ;
+ RECT 1290.720000 889.860000 1291.820000 890.340000 ;
+ RECT 1290.720000 895.300000 1291.820000 895.780000 ;
+ RECT 1335.720000 851.780000 1336.820000 852.260000 ;
+ RECT 1335.720000 857.220000 1336.820000 857.700000 ;
+ RECT 1335.720000 862.660000 1336.820000 863.140000 ;
+ RECT 1335.720000 868.100000 1336.820000 868.580000 ;
+ RECT 1290.720000 851.780000 1291.820000 852.260000 ;
+ RECT 1290.720000 857.220000 1291.820000 857.700000 ;
+ RECT 1290.720000 862.660000 1291.820000 863.140000 ;
+ RECT 1290.720000 868.100000 1291.820000 868.580000 ;
+ RECT 1241.890000 895.300000 1242.890000 895.780000 ;
+ RECT 1245.555000 895.300000 1246.820000 895.780000 ;
+ RECT 1241.890000 884.420000 1242.890000 884.900000 ;
+ RECT 1245.555000 884.420000 1246.820000 884.900000 ;
+ RECT 1241.890000 889.860000 1242.890000 890.340000 ;
+ RECT 1245.555000 889.860000 1246.820000 890.340000 ;
+ RECT 1241.890000 878.980000 1242.890000 879.460000 ;
+ RECT 1245.555000 878.980000 1246.820000 879.460000 ;
+ RECT 1241.890000 873.540000 1242.890000 874.020000 ;
+ RECT 1245.555000 873.540000 1246.820000 874.020000 ;
+ RECT 1241.890000 868.100000 1242.890000 868.580000 ;
+ RECT 1245.555000 868.100000 1246.820000 868.580000 ;
+ RECT 1241.890000 862.660000 1242.890000 863.140000 ;
+ RECT 1245.555000 862.660000 1246.820000 863.140000 ;
+ RECT 1241.890000 857.220000 1242.890000 857.700000 ;
+ RECT 1245.555000 857.220000 1246.820000 857.700000 ;
+ RECT 1241.890000 851.780000 1242.890000 852.260000 ;
+ RECT 1245.555000 851.780000 1246.820000 852.260000 ;
+ RECT 1425.720000 835.460000 1426.820000 835.940000 ;
+ RECT 1425.720000 840.900000 1426.820000 841.380000 ;
+ RECT 1438.530000 835.460000 1439.530000 835.940000 ;
+ RECT 1438.530000 840.900000 1439.530000 841.380000 ;
+ RECT 1438.530000 824.580000 1439.530000 825.060000 ;
+ RECT 1438.530000 830.020000 1439.530000 830.500000 ;
+ RECT 1425.720000 830.020000 1426.820000 830.500000 ;
+ RECT 1425.720000 824.580000 1426.820000 825.060000 ;
+ RECT 1425.720000 813.700000 1426.820000 814.180000 ;
+ RECT 1425.720000 819.140000 1426.820000 819.620000 ;
+ RECT 1438.530000 813.700000 1439.530000 814.180000 ;
+ RECT 1438.530000 819.140000 1439.530000 819.620000 ;
+ RECT 1438.530000 802.820000 1439.530000 803.300000 ;
+ RECT 1438.530000 797.380000 1439.530000 797.860000 ;
+ RECT 1438.530000 808.260000 1439.530000 808.740000 ;
+ RECT 1425.720000 808.260000 1426.820000 808.740000 ;
+ RECT 1425.720000 802.820000 1426.820000 803.300000 ;
+ RECT 1425.720000 797.380000 1426.820000 797.860000 ;
+ RECT 1380.720000 824.580000 1381.820000 825.060000 ;
+ RECT 1380.720000 830.020000 1381.820000 830.500000 ;
+ RECT 1380.720000 835.460000 1381.820000 835.940000 ;
+ RECT 1380.720000 840.900000 1381.820000 841.380000 ;
+ RECT 1380.720000 797.380000 1381.820000 797.860000 ;
+ RECT 1380.720000 802.820000 1381.820000 803.300000 ;
+ RECT 1380.720000 808.260000 1381.820000 808.740000 ;
+ RECT 1380.720000 813.700000 1381.820000 814.180000 ;
+ RECT 1380.720000 819.140000 1381.820000 819.620000 ;
+ RECT 1425.720000 786.500000 1426.820000 786.980000 ;
+ RECT 1425.720000 791.940000 1426.820000 792.420000 ;
+ RECT 1438.530000 786.500000 1439.530000 786.980000 ;
+ RECT 1438.530000 791.940000 1439.530000 792.420000 ;
+ RECT 1425.720000 775.620000 1426.820000 776.100000 ;
+ RECT 1425.720000 781.060000 1426.820000 781.540000 ;
+ RECT 1438.530000 775.620000 1439.530000 776.100000 ;
+ RECT 1438.530000 781.060000 1439.530000 781.540000 ;
+ RECT 1438.530000 764.740000 1439.530000 765.220000 ;
+ RECT 1438.530000 759.300000 1439.530000 759.780000 ;
+ RECT 1438.530000 770.180000 1439.530000 770.660000 ;
+ RECT 1425.720000 770.180000 1426.820000 770.660000 ;
+ RECT 1425.720000 764.740000 1426.820000 765.220000 ;
+ RECT 1425.720000 759.300000 1426.820000 759.780000 ;
+ RECT 1425.720000 753.860000 1426.820000 754.340000 ;
+ RECT 1438.530000 753.860000 1439.530000 754.340000 ;
+ RECT 1380.720000 775.620000 1381.820000 776.100000 ;
+ RECT 1380.720000 781.060000 1381.820000 781.540000 ;
+ RECT 1380.720000 786.500000 1381.820000 786.980000 ;
+ RECT 1380.720000 791.940000 1381.820000 792.420000 ;
+ RECT 1380.720000 753.860000 1381.820000 754.340000 ;
+ RECT 1380.720000 759.300000 1381.820000 759.780000 ;
+ RECT 1380.720000 764.740000 1381.820000 765.220000 ;
+ RECT 1380.720000 770.180000 1381.820000 770.660000 ;
+ RECT 1335.720000 824.580000 1336.820000 825.060000 ;
+ RECT 1335.720000 830.020000 1336.820000 830.500000 ;
+ RECT 1335.720000 835.460000 1336.820000 835.940000 ;
+ RECT 1335.720000 840.900000 1336.820000 841.380000 ;
+ RECT 1290.720000 824.580000 1291.820000 825.060000 ;
+ RECT 1290.720000 830.020000 1291.820000 830.500000 ;
+ RECT 1290.720000 835.460000 1291.820000 835.940000 ;
+ RECT 1290.720000 840.900000 1291.820000 841.380000 ;
+ RECT 1335.720000 797.380000 1336.820000 797.860000 ;
+ RECT 1335.720000 802.820000 1336.820000 803.300000 ;
+ RECT 1335.720000 808.260000 1336.820000 808.740000 ;
+ RECT 1335.720000 813.700000 1336.820000 814.180000 ;
+ RECT 1335.720000 819.140000 1336.820000 819.620000 ;
+ RECT 1290.720000 797.380000 1291.820000 797.860000 ;
+ RECT 1290.720000 802.820000 1291.820000 803.300000 ;
+ RECT 1290.720000 808.260000 1291.820000 808.740000 ;
+ RECT 1290.720000 813.700000 1291.820000 814.180000 ;
+ RECT 1290.720000 819.140000 1291.820000 819.620000 ;
+ RECT 1241.890000 840.900000 1242.890000 841.380000 ;
+ RECT 1245.555000 840.900000 1246.820000 841.380000 ;
+ RECT 1241.890000 835.460000 1242.890000 835.940000 ;
+ RECT 1245.555000 835.460000 1246.820000 835.940000 ;
+ RECT 1241.890000 830.020000 1242.890000 830.500000 ;
+ RECT 1245.555000 830.020000 1246.820000 830.500000 ;
+ RECT 1241.890000 824.580000 1242.890000 825.060000 ;
+ RECT 1245.555000 824.580000 1246.820000 825.060000 ;
+ RECT 1241.890000 819.140000 1242.890000 819.620000 ;
+ RECT 1245.555000 819.140000 1246.820000 819.620000 ;
+ RECT 1241.890000 813.700000 1242.890000 814.180000 ;
+ RECT 1245.555000 813.700000 1246.820000 814.180000 ;
+ RECT 1241.890000 802.820000 1242.890000 803.300000 ;
+ RECT 1245.555000 802.820000 1246.820000 803.300000 ;
+ RECT 1241.890000 808.260000 1242.890000 808.740000 ;
+ RECT 1245.555000 808.260000 1246.820000 808.740000 ;
+ RECT 1241.890000 797.380000 1242.890000 797.860000 ;
+ RECT 1245.555000 797.380000 1246.820000 797.860000 ;
+ RECT 1335.720000 775.620000 1336.820000 776.100000 ;
+ RECT 1335.720000 781.060000 1336.820000 781.540000 ;
+ RECT 1335.720000 786.500000 1336.820000 786.980000 ;
+ RECT 1335.720000 791.940000 1336.820000 792.420000 ;
+ RECT 1290.720000 775.620000 1291.820000 776.100000 ;
+ RECT 1290.720000 781.060000 1291.820000 781.540000 ;
+ RECT 1290.720000 786.500000 1291.820000 786.980000 ;
+ RECT 1290.720000 791.940000 1291.820000 792.420000 ;
+ RECT 1335.720000 753.860000 1336.820000 754.340000 ;
+ RECT 1335.720000 759.300000 1336.820000 759.780000 ;
+ RECT 1335.720000 764.740000 1336.820000 765.220000 ;
+ RECT 1335.720000 770.180000 1336.820000 770.660000 ;
+ RECT 1290.720000 753.860000 1291.820000 754.340000 ;
+ RECT 1290.720000 759.300000 1291.820000 759.780000 ;
+ RECT 1290.720000 764.740000 1291.820000 765.220000 ;
+ RECT 1290.720000 770.180000 1291.820000 770.660000 ;
+ RECT 1241.890000 791.940000 1242.890000 792.420000 ;
+ RECT 1245.555000 791.940000 1246.820000 792.420000 ;
+ RECT 1241.890000 786.500000 1242.890000 786.980000 ;
+ RECT 1245.555000 786.500000 1246.820000 786.980000 ;
+ RECT 1241.890000 781.060000 1242.890000 781.540000 ;
+ RECT 1245.555000 781.060000 1246.820000 781.540000 ;
+ RECT 1241.890000 775.620000 1242.890000 776.100000 ;
+ RECT 1245.555000 775.620000 1246.820000 776.100000 ;
+ RECT 1241.890000 770.180000 1242.890000 770.660000 ;
+ RECT 1245.555000 770.180000 1246.820000 770.660000 ;
+ RECT 1241.890000 759.300000 1242.890000 759.780000 ;
+ RECT 1245.555000 759.300000 1246.820000 759.780000 ;
+ RECT 1241.890000 764.740000 1242.890000 765.220000 ;
+ RECT 1245.555000 764.740000 1246.820000 765.220000 ;
+ RECT 1241.890000 753.860000 1242.890000 754.340000 ;
+ RECT 1245.555000 753.860000 1246.820000 754.340000 ;
+ RECT 1380.720000 846.340000 1381.820000 846.820000 ;
+ RECT 1425.720000 846.340000 1426.820000 846.820000 ;
+ RECT 1438.530000 846.340000 1439.530000 846.820000 ;
+ RECT 1290.720000 846.340000 1291.820000 846.820000 ;
+ RECT 1335.720000 846.340000 1336.820000 846.820000 ;
+ RECT 1241.890000 846.340000 1242.890000 846.820000 ;
+ RECT 1245.555000 846.340000 1246.820000 846.820000 ;
+ RECT 1240.660000 943.100000 1440.760000 944.100000 ;
+ RECT 1240.660000 747.530000 1440.760000 748.530000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 746.280000 1242.890000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 945.540000 1242.890000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 746.280000 1439.530000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 945.540000 1439.530000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 747.530000 1241.660000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 747.530000 1440.760000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 943.100000 1241.660000 944.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 943.100000 1440.760000 944.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 738.560000 1246.820000 739.040000 ;
+ RECT 1245.555000 727.680000 1246.820000 728.160000 ;
+ RECT 1245.555000 733.120000 1246.820000 733.600000 ;
+ RECT 1245.555000 722.240000 1246.820000 722.720000 ;
+ RECT 1245.555000 716.800000 1246.820000 717.280000 ;
+ RECT 1245.555000 711.360000 1246.820000 711.840000 ;
+ RECT 1245.555000 705.920000 1246.820000 706.400000 ;
+ RECT 1245.555000 700.480000 1246.820000 700.960000 ;
+ RECT 1245.555000 695.040000 1246.820000 695.520000 ;
+ RECT 1245.555000 684.160000 1246.820000 684.640000 ;
+ RECT 1245.555000 689.600000 1246.820000 690.080000 ;
+ RECT 1245.555000 678.720000 1246.820000 679.200000 ;
+ RECT 1245.555000 673.280000 1246.820000 673.760000 ;
+ RECT 1245.555000 667.840000 1246.820000 668.320000 ;
+ RECT 1245.555000 662.400000 1246.820000 662.880000 ;
+ RECT 1245.555000 656.960000 1246.820000 657.440000 ;
+ RECT 1245.555000 651.520000 1246.820000 652.000000 ;
+ RECT 1245.555000 640.640000 1246.820000 641.120000 ;
+ RECT 1245.555000 635.200000 1246.820000 635.680000 ;
+ RECT 1245.555000 629.760000 1246.820000 630.240000 ;
+ RECT 1245.555000 624.320000 1246.820000 624.800000 ;
+ RECT 1245.555000 618.880000 1246.820000 619.360000 ;
+ RECT 1245.555000 613.440000 1246.820000 613.920000 ;
+ RECT 1245.555000 602.560000 1246.820000 603.040000 ;
+ RECT 1245.555000 608.000000 1246.820000 608.480000 ;
+ RECT 1245.555000 597.120000 1246.820000 597.600000 ;
+ RECT 1245.555000 591.680000 1246.820000 592.160000 ;
+ RECT 1245.555000 586.240000 1246.820000 586.720000 ;
+ RECT 1245.555000 580.800000 1246.820000 581.280000 ;
+ RECT 1245.555000 575.360000 1246.820000 575.840000 ;
+ RECT 1245.555000 569.920000 1246.820000 570.400000 ;
+ RECT 1245.555000 559.040000 1246.820000 559.520000 ;
+ RECT 1245.555000 564.480000 1246.820000 564.960000 ;
+ RECT 1245.555000 553.600000 1246.820000 554.080000 ;
+ RECT 1245.555000 646.080000 1246.820000 646.560000 ;
+ RECT 1425.720000 547.270000 1426.820000 743.840000 ;
+ RECT 1380.720000 547.270000 1381.820000 743.840000 ;
+ RECT 1438.530000 546.020000 1439.530000 746.280000 ;
+ RECT 1335.720000 547.270000 1336.820000 743.840000 ;
+ RECT 1290.720000 547.270000 1291.820000 743.840000 ;
+ RECT 1245.720000 547.270000 1246.820000 743.840000 ;
+ RECT 1241.890000 546.020000 1242.890000 746.280000 ;
+ LAYER met3 ;
+ RECT 1425.720000 738.560000 1426.820000 739.040000 ;
+ RECT 1438.530000 738.560000 1439.530000 739.040000 ;
+ RECT 1438.530000 727.680000 1439.530000 728.160000 ;
+ RECT 1438.530000 722.240000 1439.530000 722.720000 ;
+ RECT 1438.530000 733.120000 1439.530000 733.600000 ;
+ RECT 1425.720000 733.120000 1426.820000 733.600000 ;
+ RECT 1425.720000 727.680000 1426.820000 728.160000 ;
+ RECT 1425.720000 722.240000 1426.820000 722.720000 ;
+ RECT 1425.720000 711.360000 1426.820000 711.840000 ;
+ RECT 1425.720000 716.800000 1426.820000 717.280000 ;
+ RECT 1438.530000 711.360000 1439.530000 711.840000 ;
+ RECT 1438.530000 716.800000 1439.530000 717.280000 ;
+ RECT 1425.720000 700.480000 1426.820000 700.960000 ;
+ RECT 1425.720000 705.920000 1426.820000 706.400000 ;
+ RECT 1438.530000 700.480000 1439.530000 700.960000 ;
+ RECT 1438.530000 705.920000 1439.530000 706.400000 ;
+ RECT 1380.720000 722.240000 1381.820000 722.720000 ;
+ RECT 1380.720000 727.680000 1381.820000 728.160000 ;
+ RECT 1380.720000 733.120000 1381.820000 733.600000 ;
+ RECT 1380.720000 738.560000 1381.820000 739.040000 ;
+ RECT 1380.720000 705.920000 1381.820000 706.400000 ;
+ RECT 1380.720000 700.480000 1381.820000 700.960000 ;
+ RECT 1380.720000 711.360000 1381.820000 711.840000 ;
+ RECT 1380.720000 716.800000 1381.820000 717.280000 ;
+ RECT 1438.530000 689.600000 1439.530000 690.080000 ;
+ RECT 1438.530000 684.160000 1439.530000 684.640000 ;
+ RECT 1438.530000 695.040000 1439.530000 695.520000 ;
+ RECT 1425.720000 695.040000 1426.820000 695.520000 ;
+ RECT 1425.720000 689.600000 1426.820000 690.080000 ;
+ RECT 1425.720000 684.160000 1426.820000 684.640000 ;
+ RECT 1425.720000 673.280000 1426.820000 673.760000 ;
+ RECT 1425.720000 678.720000 1426.820000 679.200000 ;
+ RECT 1438.530000 673.280000 1439.530000 673.760000 ;
+ RECT 1438.530000 678.720000 1439.530000 679.200000 ;
+ RECT 1438.530000 662.400000 1439.530000 662.880000 ;
+ RECT 1438.530000 667.840000 1439.530000 668.320000 ;
+ RECT 1425.720000 667.840000 1426.820000 668.320000 ;
+ RECT 1425.720000 662.400000 1426.820000 662.880000 ;
+ RECT 1425.720000 651.520000 1426.820000 652.000000 ;
+ RECT 1425.720000 656.960000 1426.820000 657.440000 ;
+ RECT 1438.530000 651.520000 1439.530000 652.000000 ;
+ RECT 1438.530000 656.960000 1439.530000 657.440000 ;
+ RECT 1380.720000 673.280000 1381.820000 673.760000 ;
+ RECT 1380.720000 678.720000 1381.820000 679.200000 ;
+ RECT 1380.720000 684.160000 1381.820000 684.640000 ;
+ RECT 1380.720000 689.600000 1381.820000 690.080000 ;
+ RECT 1380.720000 695.040000 1381.820000 695.520000 ;
+ RECT 1380.720000 651.520000 1381.820000 652.000000 ;
+ RECT 1380.720000 656.960000 1381.820000 657.440000 ;
+ RECT 1380.720000 662.400000 1381.820000 662.880000 ;
+ RECT 1380.720000 667.840000 1381.820000 668.320000 ;
+ RECT 1335.720000 727.680000 1336.820000 728.160000 ;
+ RECT 1335.720000 722.240000 1336.820000 722.720000 ;
+ RECT 1335.720000 733.120000 1336.820000 733.600000 ;
+ RECT 1335.720000 738.560000 1336.820000 739.040000 ;
+ RECT 1290.720000 722.240000 1291.820000 722.720000 ;
+ RECT 1290.720000 727.680000 1291.820000 728.160000 ;
+ RECT 1290.720000 733.120000 1291.820000 733.600000 ;
+ RECT 1290.720000 738.560000 1291.820000 739.040000 ;
+ RECT 1335.720000 700.480000 1336.820000 700.960000 ;
+ RECT 1335.720000 705.920000 1336.820000 706.400000 ;
+ RECT 1335.720000 711.360000 1336.820000 711.840000 ;
+ RECT 1335.720000 716.800000 1336.820000 717.280000 ;
+ RECT 1290.720000 700.480000 1291.820000 700.960000 ;
+ RECT 1290.720000 705.920000 1291.820000 706.400000 ;
+ RECT 1290.720000 711.360000 1291.820000 711.840000 ;
+ RECT 1290.720000 716.800000 1291.820000 717.280000 ;
+ RECT 1241.890000 738.560000 1242.890000 739.040000 ;
+ RECT 1245.555000 738.560000 1246.820000 739.040000 ;
+ RECT 1241.890000 727.680000 1242.890000 728.160000 ;
+ RECT 1245.555000 727.680000 1246.820000 728.160000 ;
+ RECT 1241.890000 733.120000 1242.890000 733.600000 ;
+ RECT 1245.555000 733.120000 1246.820000 733.600000 ;
+ RECT 1241.890000 722.240000 1242.890000 722.720000 ;
+ RECT 1245.555000 722.240000 1246.820000 722.720000 ;
+ RECT 1241.890000 716.800000 1242.890000 717.280000 ;
+ RECT 1245.555000 716.800000 1246.820000 717.280000 ;
+ RECT 1241.890000 711.360000 1242.890000 711.840000 ;
+ RECT 1245.555000 711.360000 1246.820000 711.840000 ;
+ RECT 1241.890000 705.920000 1242.890000 706.400000 ;
+ RECT 1245.555000 705.920000 1246.820000 706.400000 ;
+ RECT 1241.890000 700.480000 1242.890000 700.960000 ;
+ RECT 1245.555000 700.480000 1246.820000 700.960000 ;
+ RECT 1335.720000 673.280000 1336.820000 673.760000 ;
+ RECT 1335.720000 678.720000 1336.820000 679.200000 ;
+ RECT 1335.720000 684.160000 1336.820000 684.640000 ;
+ RECT 1335.720000 689.600000 1336.820000 690.080000 ;
+ RECT 1335.720000 695.040000 1336.820000 695.520000 ;
+ RECT 1290.720000 673.280000 1291.820000 673.760000 ;
+ RECT 1290.720000 678.720000 1291.820000 679.200000 ;
+ RECT 1290.720000 684.160000 1291.820000 684.640000 ;
+ RECT 1290.720000 689.600000 1291.820000 690.080000 ;
+ RECT 1290.720000 695.040000 1291.820000 695.520000 ;
+ RECT 1335.720000 651.520000 1336.820000 652.000000 ;
+ RECT 1335.720000 656.960000 1336.820000 657.440000 ;
+ RECT 1335.720000 662.400000 1336.820000 662.880000 ;
+ RECT 1335.720000 667.840000 1336.820000 668.320000 ;
+ RECT 1290.720000 651.520000 1291.820000 652.000000 ;
+ RECT 1290.720000 656.960000 1291.820000 657.440000 ;
+ RECT 1290.720000 662.400000 1291.820000 662.880000 ;
+ RECT 1290.720000 667.840000 1291.820000 668.320000 ;
+ RECT 1241.890000 695.040000 1242.890000 695.520000 ;
+ RECT 1245.555000 695.040000 1246.820000 695.520000 ;
+ RECT 1241.890000 684.160000 1242.890000 684.640000 ;
+ RECT 1245.555000 684.160000 1246.820000 684.640000 ;
+ RECT 1241.890000 689.600000 1242.890000 690.080000 ;
+ RECT 1245.555000 689.600000 1246.820000 690.080000 ;
+ RECT 1241.890000 678.720000 1242.890000 679.200000 ;
+ RECT 1245.555000 678.720000 1246.820000 679.200000 ;
+ RECT 1241.890000 673.280000 1242.890000 673.760000 ;
+ RECT 1245.555000 673.280000 1246.820000 673.760000 ;
+ RECT 1241.890000 667.840000 1242.890000 668.320000 ;
+ RECT 1245.555000 667.840000 1246.820000 668.320000 ;
+ RECT 1241.890000 662.400000 1242.890000 662.880000 ;
+ RECT 1245.555000 662.400000 1246.820000 662.880000 ;
+ RECT 1241.890000 656.960000 1242.890000 657.440000 ;
+ RECT 1245.555000 656.960000 1246.820000 657.440000 ;
+ RECT 1241.890000 651.520000 1242.890000 652.000000 ;
+ RECT 1245.555000 651.520000 1246.820000 652.000000 ;
+ RECT 1425.720000 635.200000 1426.820000 635.680000 ;
+ RECT 1425.720000 640.640000 1426.820000 641.120000 ;
+ RECT 1438.530000 635.200000 1439.530000 635.680000 ;
+ RECT 1438.530000 640.640000 1439.530000 641.120000 ;
+ RECT 1438.530000 624.320000 1439.530000 624.800000 ;
+ RECT 1438.530000 629.760000 1439.530000 630.240000 ;
+ RECT 1425.720000 629.760000 1426.820000 630.240000 ;
+ RECT 1425.720000 624.320000 1426.820000 624.800000 ;
+ RECT 1425.720000 613.440000 1426.820000 613.920000 ;
+ RECT 1425.720000 618.880000 1426.820000 619.360000 ;
+ RECT 1438.530000 613.440000 1439.530000 613.920000 ;
+ RECT 1438.530000 618.880000 1439.530000 619.360000 ;
+ RECT 1438.530000 602.560000 1439.530000 603.040000 ;
+ RECT 1438.530000 597.120000 1439.530000 597.600000 ;
+ RECT 1438.530000 608.000000 1439.530000 608.480000 ;
+ RECT 1425.720000 608.000000 1426.820000 608.480000 ;
+ RECT 1425.720000 602.560000 1426.820000 603.040000 ;
+ RECT 1425.720000 597.120000 1426.820000 597.600000 ;
+ RECT 1380.720000 624.320000 1381.820000 624.800000 ;
+ RECT 1380.720000 629.760000 1381.820000 630.240000 ;
+ RECT 1380.720000 635.200000 1381.820000 635.680000 ;
+ RECT 1380.720000 640.640000 1381.820000 641.120000 ;
+ RECT 1380.720000 597.120000 1381.820000 597.600000 ;
+ RECT 1380.720000 602.560000 1381.820000 603.040000 ;
+ RECT 1380.720000 608.000000 1381.820000 608.480000 ;
+ RECT 1380.720000 613.440000 1381.820000 613.920000 ;
+ RECT 1380.720000 618.880000 1381.820000 619.360000 ;
+ RECT 1425.720000 586.240000 1426.820000 586.720000 ;
+ RECT 1425.720000 591.680000 1426.820000 592.160000 ;
+ RECT 1438.530000 586.240000 1439.530000 586.720000 ;
+ RECT 1438.530000 591.680000 1439.530000 592.160000 ;
+ RECT 1425.720000 575.360000 1426.820000 575.840000 ;
+ RECT 1425.720000 580.800000 1426.820000 581.280000 ;
+ RECT 1438.530000 575.360000 1439.530000 575.840000 ;
+ RECT 1438.530000 580.800000 1439.530000 581.280000 ;
+ RECT 1438.530000 564.480000 1439.530000 564.960000 ;
+ RECT 1438.530000 559.040000 1439.530000 559.520000 ;
+ RECT 1438.530000 569.920000 1439.530000 570.400000 ;
+ RECT 1425.720000 569.920000 1426.820000 570.400000 ;
+ RECT 1425.720000 564.480000 1426.820000 564.960000 ;
+ RECT 1425.720000 559.040000 1426.820000 559.520000 ;
+ RECT 1425.720000 553.600000 1426.820000 554.080000 ;
+ RECT 1438.530000 553.600000 1439.530000 554.080000 ;
+ RECT 1380.720000 575.360000 1381.820000 575.840000 ;
+ RECT 1380.720000 580.800000 1381.820000 581.280000 ;
+ RECT 1380.720000 586.240000 1381.820000 586.720000 ;
+ RECT 1380.720000 591.680000 1381.820000 592.160000 ;
+ RECT 1380.720000 553.600000 1381.820000 554.080000 ;
+ RECT 1380.720000 559.040000 1381.820000 559.520000 ;
+ RECT 1380.720000 564.480000 1381.820000 564.960000 ;
+ RECT 1380.720000 569.920000 1381.820000 570.400000 ;
+ RECT 1335.720000 624.320000 1336.820000 624.800000 ;
+ RECT 1335.720000 629.760000 1336.820000 630.240000 ;
+ RECT 1335.720000 635.200000 1336.820000 635.680000 ;
+ RECT 1335.720000 640.640000 1336.820000 641.120000 ;
+ RECT 1290.720000 624.320000 1291.820000 624.800000 ;
+ RECT 1290.720000 629.760000 1291.820000 630.240000 ;
+ RECT 1290.720000 635.200000 1291.820000 635.680000 ;
+ RECT 1290.720000 640.640000 1291.820000 641.120000 ;
+ RECT 1335.720000 597.120000 1336.820000 597.600000 ;
+ RECT 1335.720000 602.560000 1336.820000 603.040000 ;
+ RECT 1335.720000 608.000000 1336.820000 608.480000 ;
+ RECT 1335.720000 613.440000 1336.820000 613.920000 ;
+ RECT 1335.720000 618.880000 1336.820000 619.360000 ;
+ RECT 1290.720000 597.120000 1291.820000 597.600000 ;
+ RECT 1290.720000 602.560000 1291.820000 603.040000 ;
+ RECT 1290.720000 608.000000 1291.820000 608.480000 ;
+ RECT 1290.720000 613.440000 1291.820000 613.920000 ;
+ RECT 1290.720000 618.880000 1291.820000 619.360000 ;
+ RECT 1241.890000 640.640000 1242.890000 641.120000 ;
+ RECT 1245.555000 640.640000 1246.820000 641.120000 ;
+ RECT 1241.890000 635.200000 1242.890000 635.680000 ;
+ RECT 1245.555000 635.200000 1246.820000 635.680000 ;
+ RECT 1241.890000 629.760000 1242.890000 630.240000 ;
+ RECT 1245.555000 629.760000 1246.820000 630.240000 ;
+ RECT 1241.890000 624.320000 1242.890000 624.800000 ;
+ RECT 1245.555000 624.320000 1246.820000 624.800000 ;
+ RECT 1241.890000 618.880000 1242.890000 619.360000 ;
+ RECT 1245.555000 618.880000 1246.820000 619.360000 ;
+ RECT 1241.890000 613.440000 1242.890000 613.920000 ;
+ RECT 1245.555000 613.440000 1246.820000 613.920000 ;
+ RECT 1241.890000 602.560000 1242.890000 603.040000 ;
+ RECT 1245.555000 602.560000 1246.820000 603.040000 ;
+ RECT 1241.890000 608.000000 1242.890000 608.480000 ;
+ RECT 1245.555000 608.000000 1246.820000 608.480000 ;
+ RECT 1241.890000 597.120000 1242.890000 597.600000 ;
+ RECT 1245.555000 597.120000 1246.820000 597.600000 ;
+ RECT 1335.720000 575.360000 1336.820000 575.840000 ;
+ RECT 1335.720000 580.800000 1336.820000 581.280000 ;
+ RECT 1335.720000 586.240000 1336.820000 586.720000 ;
+ RECT 1335.720000 591.680000 1336.820000 592.160000 ;
+ RECT 1290.720000 575.360000 1291.820000 575.840000 ;
+ RECT 1290.720000 580.800000 1291.820000 581.280000 ;
+ RECT 1290.720000 586.240000 1291.820000 586.720000 ;
+ RECT 1290.720000 591.680000 1291.820000 592.160000 ;
+ RECT 1335.720000 553.600000 1336.820000 554.080000 ;
+ RECT 1335.720000 559.040000 1336.820000 559.520000 ;
+ RECT 1335.720000 564.480000 1336.820000 564.960000 ;
+ RECT 1335.720000 569.920000 1336.820000 570.400000 ;
+ RECT 1290.720000 553.600000 1291.820000 554.080000 ;
+ RECT 1290.720000 559.040000 1291.820000 559.520000 ;
+ RECT 1290.720000 564.480000 1291.820000 564.960000 ;
+ RECT 1290.720000 569.920000 1291.820000 570.400000 ;
+ RECT 1241.890000 591.680000 1242.890000 592.160000 ;
+ RECT 1245.555000 591.680000 1246.820000 592.160000 ;
+ RECT 1241.890000 586.240000 1242.890000 586.720000 ;
+ RECT 1245.555000 586.240000 1246.820000 586.720000 ;
+ RECT 1241.890000 580.800000 1242.890000 581.280000 ;
+ RECT 1245.555000 580.800000 1246.820000 581.280000 ;
+ RECT 1241.890000 575.360000 1242.890000 575.840000 ;
+ RECT 1245.555000 575.360000 1246.820000 575.840000 ;
+ RECT 1241.890000 569.920000 1242.890000 570.400000 ;
+ RECT 1245.555000 569.920000 1246.820000 570.400000 ;
+ RECT 1241.890000 559.040000 1242.890000 559.520000 ;
+ RECT 1245.555000 559.040000 1246.820000 559.520000 ;
+ RECT 1241.890000 564.480000 1242.890000 564.960000 ;
+ RECT 1245.555000 564.480000 1246.820000 564.960000 ;
+ RECT 1241.890000 553.600000 1242.890000 554.080000 ;
+ RECT 1245.555000 553.600000 1246.820000 554.080000 ;
+ RECT 1380.720000 646.080000 1381.820000 646.560000 ;
+ RECT 1425.720000 646.080000 1426.820000 646.560000 ;
+ RECT 1438.530000 646.080000 1439.530000 646.560000 ;
+ RECT 1290.720000 646.080000 1291.820000 646.560000 ;
+ RECT 1335.720000 646.080000 1336.820000 646.560000 ;
+ RECT 1241.890000 646.080000 1242.890000 646.560000 ;
+ RECT 1245.555000 646.080000 1246.820000 646.560000 ;
+ RECT 1240.660000 742.840000 1440.760000 743.840000 ;
+ RECT 1240.660000 547.270000 1440.760000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 546.020000 1242.890000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 745.280000 1242.890000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 546.020000 1439.530000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 745.280000 1439.530000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 547.270000 1241.660000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 547.270000 1440.760000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 742.840000 1241.660000 743.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 742.840000 1440.760000 743.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 538.300000 1246.820000 538.780000 ;
+ RECT 1245.555000 527.420000 1246.820000 527.900000 ;
+ RECT 1245.555000 532.860000 1246.820000 533.340000 ;
+ RECT 1245.555000 521.980000 1246.820000 522.460000 ;
+ RECT 1245.555000 516.540000 1246.820000 517.020000 ;
+ RECT 1245.555000 511.100000 1246.820000 511.580000 ;
+ RECT 1245.555000 505.660000 1246.820000 506.140000 ;
+ RECT 1245.555000 500.220000 1246.820000 500.700000 ;
+ RECT 1245.555000 494.780000 1246.820000 495.260000 ;
+ RECT 1245.555000 483.900000 1246.820000 484.380000 ;
+ RECT 1245.555000 489.340000 1246.820000 489.820000 ;
+ RECT 1245.555000 478.460000 1246.820000 478.940000 ;
+ RECT 1245.555000 473.020000 1246.820000 473.500000 ;
+ RECT 1245.555000 467.580000 1246.820000 468.060000 ;
+ RECT 1245.555000 462.140000 1246.820000 462.620000 ;
+ RECT 1245.555000 456.700000 1246.820000 457.180000 ;
+ RECT 1245.555000 451.260000 1246.820000 451.740000 ;
+ RECT 1245.555000 440.380000 1246.820000 440.860000 ;
+ RECT 1245.555000 434.940000 1246.820000 435.420000 ;
+ RECT 1245.555000 429.500000 1246.820000 429.980000 ;
+ RECT 1245.555000 424.060000 1246.820000 424.540000 ;
+ RECT 1245.555000 418.620000 1246.820000 419.100000 ;
+ RECT 1245.555000 413.180000 1246.820000 413.660000 ;
+ RECT 1245.555000 402.300000 1246.820000 402.780000 ;
+ RECT 1245.555000 407.740000 1246.820000 408.220000 ;
+ RECT 1245.555000 396.860000 1246.820000 397.340000 ;
+ RECT 1245.555000 391.420000 1246.820000 391.900000 ;
+ RECT 1245.555000 385.980000 1246.820000 386.460000 ;
+ RECT 1245.555000 380.540000 1246.820000 381.020000 ;
+ RECT 1245.555000 375.100000 1246.820000 375.580000 ;
+ RECT 1245.555000 369.660000 1246.820000 370.140000 ;
+ RECT 1245.555000 358.780000 1246.820000 359.260000 ;
+ RECT 1245.555000 364.220000 1246.820000 364.700000 ;
+ RECT 1245.555000 353.340000 1246.820000 353.820000 ;
+ RECT 1245.555000 445.820000 1246.820000 446.300000 ;
+ RECT 1425.720000 347.010000 1426.820000 543.580000 ;
+ RECT 1380.720000 347.010000 1381.820000 543.580000 ;
+ RECT 1438.530000 345.760000 1439.530000 546.020000 ;
+ RECT 1335.720000 347.010000 1336.820000 543.580000 ;
+ RECT 1290.720000 347.010000 1291.820000 543.580000 ;
+ RECT 1245.720000 347.010000 1246.820000 543.580000 ;
+ RECT 1241.890000 345.760000 1242.890000 546.020000 ;
+ LAYER met3 ;
+ RECT 1425.720000 538.300000 1426.820000 538.780000 ;
+ RECT 1438.530000 538.300000 1439.530000 538.780000 ;
+ RECT 1438.530000 527.420000 1439.530000 527.900000 ;
+ RECT 1438.530000 521.980000 1439.530000 522.460000 ;
+ RECT 1438.530000 532.860000 1439.530000 533.340000 ;
+ RECT 1425.720000 532.860000 1426.820000 533.340000 ;
+ RECT 1425.720000 527.420000 1426.820000 527.900000 ;
+ RECT 1425.720000 521.980000 1426.820000 522.460000 ;
+ RECT 1425.720000 511.100000 1426.820000 511.580000 ;
+ RECT 1425.720000 516.540000 1426.820000 517.020000 ;
+ RECT 1438.530000 511.100000 1439.530000 511.580000 ;
+ RECT 1438.530000 516.540000 1439.530000 517.020000 ;
+ RECT 1425.720000 500.220000 1426.820000 500.700000 ;
+ RECT 1425.720000 505.660000 1426.820000 506.140000 ;
+ RECT 1438.530000 500.220000 1439.530000 500.700000 ;
+ RECT 1438.530000 505.660000 1439.530000 506.140000 ;
+ RECT 1380.720000 521.980000 1381.820000 522.460000 ;
+ RECT 1380.720000 527.420000 1381.820000 527.900000 ;
+ RECT 1380.720000 532.860000 1381.820000 533.340000 ;
+ RECT 1380.720000 538.300000 1381.820000 538.780000 ;
+ RECT 1380.720000 505.660000 1381.820000 506.140000 ;
+ RECT 1380.720000 500.220000 1381.820000 500.700000 ;
+ RECT 1380.720000 511.100000 1381.820000 511.580000 ;
+ RECT 1380.720000 516.540000 1381.820000 517.020000 ;
+ RECT 1438.530000 489.340000 1439.530000 489.820000 ;
+ RECT 1438.530000 483.900000 1439.530000 484.380000 ;
+ RECT 1438.530000 494.780000 1439.530000 495.260000 ;
+ RECT 1425.720000 494.780000 1426.820000 495.260000 ;
+ RECT 1425.720000 489.340000 1426.820000 489.820000 ;
+ RECT 1425.720000 483.900000 1426.820000 484.380000 ;
+ RECT 1425.720000 473.020000 1426.820000 473.500000 ;
+ RECT 1425.720000 478.460000 1426.820000 478.940000 ;
+ RECT 1438.530000 473.020000 1439.530000 473.500000 ;
+ RECT 1438.530000 478.460000 1439.530000 478.940000 ;
+ RECT 1438.530000 462.140000 1439.530000 462.620000 ;
+ RECT 1438.530000 467.580000 1439.530000 468.060000 ;
+ RECT 1425.720000 467.580000 1426.820000 468.060000 ;
+ RECT 1425.720000 462.140000 1426.820000 462.620000 ;
+ RECT 1425.720000 451.260000 1426.820000 451.740000 ;
+ RECT 1425.720000 456.700000 1426.820000 457.180000 ;
+ RECT 1438.530000 451.260000 1439.530000 451.740000 ;
+ RECT 1438.530000 456.700000 1439.530000 457.180000 ;
+ RECT 1380.720000 473.020000 1381.820000 473.500000 ;
+ RECT 1380.720000 478.460000 1381.820000 478.940000 ;
+ RECT 1380.720000 483.900000 1381.820000 484.380000 ;
+ RECT 1380.720000 489.340000 1381.820000 489.820000 ;
+ RECT 1380.720000 494.780000 1381.820000 495.260000 ;
+ RECT 1380.720000 451.260000 1381.820000 451.740000 ;
+ RECT 1380.720000 456.700000 1381.820000 457.180000 ;
+ RECT 1380.720000 462.140000 1381.820000 462.620000 ;
+ RECT 1380.720000 467.580000 1381.820000 468.060000 ;
+ RECT 1335.720000 527.420000 1336.820000 527.900000 ;
+ RECT 1335.720000 521.980000 1336.820000 522.460000 ;
+ RECT 1335.720000 532.860000 1336.820000 533.340000 ;
+ RECT 1335.720000 538.300000 1336.820000 538.780000 ;
+ RECT 1290.720000 521.980000 1291.820000 522.460000 ;
+ RECT 1290.720000 527.420000 1291.820000 527.900000 ;
+ RECT 1290.720000 532.860000 1291.820000 533.340000 ;
+ RECT 1290.720000 538.300000 1291.820000 538.780000 ;
+ RECT 1335.720000 500.220000 1336.820000 500.700000 ;
+ RECT 1335.720000 505.660000 1336.820000 506.140000 ;
+ RECT 1335.720000 511.100000 1336.820000 511.580000 ;
+ RECT 1335.720000 516.540000 1336.820000 517.020000 ;
+ RECT 1290.720000 500.220000 1291.820000 500.700000 ;
+ RECT 1290.720000 505.660000 1291.820000 506.140000 ;
+ RECT 1290.720000 511.100000 1291.820000 511.580000 ;
+ RECT 1290.720000 516.540000 1291.820000 517.020000 ;
+ RECT 1241.890000 538.300000 1242.890000 538.780000 ;
+ RECT 1245.555000 538.300000 1246.820000 538.780000 ;
+ RECT 1241.890000 527.420000 1242.890000 527.900000 ;
+ RECT 1245.555000 527.420000 1246.820000 527.900000 ;
+ RECT 1241.890000 532.860000 1242.890000 533.340000 ;
+ RECT 1245.555000 532.860000 1246.820000 533.340000 ;
+ RECT 1241.890000 521.980000 1242.890000 522.460000 ;
+ RECT 1245.555000 521.980000 1246.820000 522.460000 ;
+ RECT 1241.890000 516.540000 1242.890000 517.020000 ;
+ RECT 1245.555000 516.540000 1246.820000 517.020000 ;
+ RECT 1241.890000 511.100000 1242.890000 511.580000 ;
+ RECT 1245.555000 511.100000 1246.820000 511.580000 ;
+ RECT 1241.890000 505.660000 1242.890000 506.140000 ;
+ RECT 1245.555000 505.660000 1246.820000 506.140000 ;
+ RECT 1241.890000 500.220000 1242.890000 500.700000 ;
+ RECT 1245.555000 500.220000 1246.820000 500.700000 ;
+ RECT 1335.720000 473.020000 1336.820000 473.500000 ;
+ RECT 1335.720000 478.460000 1336.820000 478.940000 ;
+ RECT 1335.720000 483.900000 1336.820000 484.380000 ;
+ RECT 1335.720000 489.340000 1336.820000 489.820000 ;
+ RECT 1335.720000 494.780000 1336.820000 495.260000 ;
+ RECT 1290.720000 473.020000 1291.820000 473.500000 ;
+ RECT 1290.720000 478.460000 1291.820000 478.940000 ;
+ RECT 1290.720000 483.900000 1291.820000 484.380000 ;
+ RECT 1290.720000 489.340000 1291.820000 489.820000 ;
+ RECT 1290.720000 494.780000 1291.820000 495.260000 ;
+ RECT 1335.720000 451.260000 1336.820000 451.740000 ;
+ RECT 1335.720000 456.700000 1336.820000 457.180000 ;
+ RECT 1335.720000 462.140000 1336.820000 462.620000 ;
+ RECT 1335.720000 467.580000 1336.820000 468.060000 ;
+ RECT 1290.720000 451.260000 1291.820000 451.740000 ;
+ RECT 1290.720000 456.700000 1291.820000 457.180000 ;
+ RECT 1290.720000 462.140000 1291.820000 462.620000 ;
+ RECT 1290.720000 467.580000 1291.820000 468.060000 ;
+ RECT 1241.890000 494.780000 1242.890000 495.260000 ;
+ RECT 1245.555000 494.780000 1246.820000 495.260000 ;
+ RECT 1241.890000 483.900000 1242.890000 484.380000 ;
+ RECT 1245.555000 483.900000 1246.820000 484.380000 ;
+ RECT 1241.890000 489.340000 1242.890000 489.820000 ;
+ RECT 1245.555000 489.340000 1246.820000 489.820000 ;
+ RECT 1241.890000 478.460000 1242.890000 478.940000 ;
+ RECT 1245.555000 478.460000 1246.820000 478.940000 ;
+ RECT 1241.890000 473.020000 1242.890000 473.500000 ;
+ RECT 1245.555000 473.020000 1246.820000 473.500000 ;
+ RECT 1241.890000 467.580000 1242.890000 468.060000 ;
+ RECT 1245.555000 467.580000 1246.820000 468.060000 ;
+ RECT 1241.890000 462.140000 1242.890000 462.620000 ;
+ RECT 1245.555000 462.140000 1246.820000 462.620000 ;
+ RECT 1241.890000 456.700000 1242.890000 457.180000 ;
+ RECT 1245.555000 456.700000 1246.820000 457.180000 ;
+ RECT 1241.890000 451.260000 1242.890000 451.740000 ;
+ RECT 1245.555000 451.260000 1246.820000 451.740000 ;
+ RECT 1425.720000 434.940000 1426.820000 435.420000 ;
+ RECT 1425.720000 440.380000 1426.820000 440.860000 ;
+ RECT 1438.530000 434.940000 1439.530000 435.420000 ;
+ RECT 1438.530000 440.380000 1439.530000 440.860000 ;
+ RECT 1438.530000 424.060000 1439.530000 424.540000 ;
+ RECT 1438.530000 429.500000 1439.530000 429.980000 ;
+ RECT 1425.720000 429.500000 1426.820000 429.980000 ;
+ RECT 1425.720000 424.060000 1426.820000 424.540000 ;
+ RECT 1425.720000 413.180000 1426.820000 413.660000 ;
+ RECT 1425.720000 418.620000 1426.820000 419.100000 ;
+ RECT 1438.530000 413.180000 1439.530000 413.660000 ;
+ RECT 1438.530000 418.620000 1439.530000 419.100000 ;
+ RECT 1438.530000 402.300000 1439.530000 402.780000 ;
+ RECT 1438.530000 396.860000 1439.530000 397.340000 ;
+ RECT 1438.530000 407.740000 1439.530000 408.220000 ;
+ RECT 1425.720000 407.740000 1426.820000 408.220000 ;
+ RECT 1425.720000 402.300000 1426.820000 402.780000 ;
+ RECT 1425.720000 396.860000 1426.820000 397.340000 ;
+ RECT 1380.720000 424.060000 1381.820000 424.540000 ;
+ RECT 1380.720000 429.500000 1381.820000 429.980000 ;
+ RECT 1380.720000 434.940000 1381.820000 435.420000 ;
+ RECT 1380.720000 440.380000 1381.820000 440.860000 ;
+ RECT 1380.720000 396.860000 1381.820000 397.340000 ;
+ RECT 1380.720000 402.300000 1381.820000 402.780000 ;
+ RECT 1380.720000 407.740000 1381.820000 408.220000 ;
+ RECT 1380.720000 413.180000 1381.820000 413.660000 ;
+ RECT 1380.720000 418.620000 1381.820000 419.100000 ;
+ RECT 1425.720000 385.980000 1426.820000 386.460000 ;
+ RECT 1425.720000 391.420000 1426.820000 391.900000 ;
+ RECT 1438.530000 385.980000 1439.530000 386.460000 ;
+ RECT 1438.530000 391.420000 1439.530000 391.900000 ;
+ RECT 1425.720000 375.100000 1426.820000 375.580000 ;
+ RECT 1425.720000 380.540000 1426.820000 381.020000 ;
+ RECT 1438.530000 375.100000 1439.530000 375.580000 ;
+ RECT 1438.530000 380.540000 1439.530000 381.020000 ;
+ RECT 1438.530000 364.220000 1439.530000 364.700000 ;
+ RECT 1438.530000 358.780000 1439.530000 359.260000 ;
+ RECT 1438.530000 369.660000 1439.530000 370.140000 ;
+ RECT 1425.720000 369.660000 1426.820000 370.140000 ;
+ RECT 1425.720000 364.220000 1426.820000 364.700000 ;
+ RECT 1425.720000 358.780000 1426.820000 359.260000 ;
+ RECT 1425.720000 353.340000 1426.820000 353.820000 ;
+ RECT 1438.530000 353.340000 1439.530000 353.820000 ;
+ RECT 1380.720000 375.100000 1381.820000 375.580000 ;
+ RECT 1380.720000 380.540000 1381.820000 381.020000 ;
+ RECT 1380.720000 385.980000 1381.820000 386.460000 ;
+ RECT 1380.720000 391.420000 1381.820000 391.900000 ;
+ RECT 1380.720000 353.340000 1381.820000 353.820000 ;
+ RECT 1380.720000 358.780000 1381.820000 359.260000 ;
+ RECT 1380.720000 364.220000 1381.820000 364.700000 ;
+ RECT 1380.720000 369.660000 1381.820000 370.140000 ;
+ RECT 1335.720000 424.060000 1336.820000 424.540000 ;
+ RECT 1335.720000 429.500000 1336.820000 429.980000 ;
+ RECT 1335.720000 434.940000 1336.820000 435.420000 ;
+ RECT 1335.720000 440.380000 1336.820000 440.860000 ;
+ RECT 1290.720000 424.060000 1291.820000 424.540000 ;
+ RECT 1290.720000 429.500000 1291.820000 429.980000 ;
+ RECT 1290.720000 434.940000 1291.820000 435.420000 ;
+ RECT 1290.720000 440.380000 1291.820000 440.860000 ;
+ RECT 1335.720000 396.860000 1336.820000 397.340000 ;
+ RECT 1335.720000 402.300000 1336.820000 402.780000 ;
+ RECT 1335.720000 407.740000 1336.820000 408.220000 ;
+ RECT 1335.720000 413.180000 1336.820000 413.660000 ;
+ RECT 1335.720000 418.620000 1336.820000 419.100000 ;
+ RECT 1290.720000 396.860000 1291.820000 397.340000 ;
+ RECT 1290.720000 402.300000 1291.820000 402.780000 ;
+ RECT 1290.720000 407.740000 1291.820000 408.220000 ;
+ RECT 1290.720000 413.180000 1291.820000 413.660000 ;
+ RECT 1290.720000 418.620000 1291.820000 419.100000 ;
+ RECT 1241.890000 440.380000 1242.890000 440.860000 ;
+ RECT 1245.555000 440.380000 1246.820000 440.860000 ;
+ RECT 1241.890000 434.940000 1242.890000 435.420000 ;
+ RECT 1245.555000 434.940000 1246.820000 435.420000 ;
+ RECT 1241.890000 429.500000 1242.890000 429.980000 ;
+ RECT 1245.555000 429.500000 1246.820000 429.980000 ;
+ RECT 1241.890000 424.060000 1242.890000 424.540000 ;
+ RECT 1245.555000 424.060000 1246.820000 424.540000 ;
+ RECT 1241.890000 418.620000 1242.890000 419.100000 ;
+ RECT 1245.555000 418.620000 1246.820000 419.100000 ;
+ RECT 1241.890000 413.180000 1242.890000 413.660000 ;
+ RECT 1245.555000 413.180000 1246.820000 413.660000 ;
+ RECT 1241.890000 402.300000 1242.890000 402.780000 ;
+ RECT 1245.555000 402.300000 1246.820000 402.780000 ;
+ RECT 1241.890000 407.740000 1242.890000 408.220000 ;
+ RECT 1245.555000 407.740000 1246.820000 408.220000 ;
+ RECT 1241.890000 396.860000 1242.890000 397.340000 ;
+ RECT 1245.555000 396.860000 1246.820000 397.340000 ;
+ RECT 1335.720000 375.100000 1336.820000 375.580000 ;
+ RECT 1335.720000 380.540000 1336.820000 381.020000 ;
+ RECT 1335.720000 385.980000 1336.820000 386.460000 ;
+ RECT 1335.720000 391.420000 1336.820000 391.900000 ;
+ RECT 1290.720000 375.100000 1291.820000 375.580000 ;
+ RECT 1290.720000 380.540000 1291.820000 381.020000 ;
+ RECT 1290.720000 385.980000 1291.820000 386.460000 ;
+ RECT 1290.720000 391.420000 1291.820000 391.900000 ;
+ RECT 1335.720000 353.340000 1336.820000 353.820000 ;
+ RECT 1335.720000 358.780000 1336.820000 359.260000 ;
+ RECT 1335.720000 364.220000 1336.820000 364.700000 ;
+ RECT 1335.720000 369.660000 1336.820000 370.140000 ;
+ RECT 1290.720000 353.340000 1291.820000 353.820000 ;
+ RECT 1290.720000 358.780000 1291.820000 359.260000 ;
+ RECT 1290.720000 364.220000 1291.820000 364.700000 ;
+ RECT 1290.720000 369.660000 1291.820000 370.140000 ;
+ RECT 1241.890000 391.420000 1242.890000 391.900000 ;
+ RECT 1245.555000 391.420000 1246.820000 391.900000 ;
+ RECT 1241.890000 385.980000 1242.890000 386.460000 ;
+ RECT 1245.555000 385.980000 1246.820000 386.460000 ;
+ RECT 1241.890000 380.540000 1242.890000 381.020000 ;
+ RECT 1245.555000 380.540000 1246.820000 381.020000 ;
+ RECT 1241.890000 375.100000 1242.890000 375.580000 ;
+ RECT 1245.555000 375.100000 1246.820000 375.580000 ;
+ RECT 1241.890000 369.660000 1242.890000 370.140000 ;
+ RECT 1245.555000 369.660000 1246.820000 370.140000 ;
+ RECT 1241.890000 358.780000 1242.890000 359.260000 ;
+ RECT 1245.555000 358.780000 1246.820000 359.260000 ;
+ RECT 1241.890000 364.220000 1242.890000 364.700000 ;
+ RECT 1245.555000 364.220000 1246.820000 364.700000 ;
+ RECT 1241.890000 353.340000 1242.890000 353.820000 ;
+ RECT 1245.555000 353.340000 1246.820000 353.820000 ;
+ RECT 1380.720000 445.820000 1381.820000 446.300000 ;
+ RECT 1425.720000 445.820000 1426.820000 446.300000 ;
+ RECT 1438.530000 445.820000 1439.530000 446.300000 ;
+ RECT 1290.720000 445.820000 1291.820000 446.300000 ;
+ RECT 1335.720000 445.820000 1336.820000 446.300000 ;
+ RECT 1241.890000 445.820000 1242.890000 446.300000 ;
+ RECT 1245.555000 445.820000 1246.820000 446.300000 ;
+ RECT 1240.660000 542.580000 1440.760000 543.580000 ;
+ RECT 1240.660000 347.010000 1440.760000 348.010000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 345.760000 1242.890000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 545.020000 1242.890000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 345.760000 1439.530000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 545.020000 1439.530000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 347.010000 1241.660000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 347.010000 1440.760000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 542.580000 1241.660000 543.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 542.580000 1440.760000 543.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 338.040000 1246.820000 338.520000 ;
+ RECT 1245.555000 327.160000 1246.820000 327.640000 ;
+ RECT 1245.555000 332.600000 1246.820000 333.080000 ;
+ RECT 1245.555000 321.720000 1246.820000 322.200000 ;
+ RECT 1245.555000 316.280000 1246.820000 316.760000 ;
+ RECT 1245.555000 310.840000 1246.820000 311.320000 ;
+ RECT 1245.555000 305.400000 1246.820000 305.880000 ;
+ RECT 1245.555000 299.960000 1246.820000 300.440000 ;
+ RECT 1245.555000 294.520000 1246.820000 295.000000 ;
+ RECT 1245.555000 283.640000 1246.820000 284.120000 ;
+ RECT 1245.555000 289.080000 1246.820000 289.560000 ;
+ RECT 1245.555000 278.200000 1246.820000 278.680000 ;
+ RECT 1245.555000 272.760000 1246.820000 273.240000 ;
+ RECT 1245.555000 267.320000 1246.820000 267.800000 ;
+ RECT 1245.555000 261.880000 1246.820000 262.360000 ;
+ RECT 1245.555000 256.440000 1246.820000 256.920000 ;
+ RECT 1245.555000 251.000000 1246.820000 251.480000 ;
+ RECT 1245.555000 240.120000 1246.820000 240.600000 ;
+ RECT 1245.555000 234.680000 1246.820000 235.160000 ;
+ RECT 1245.555000 229.240000 1246.820000 229.720000 ;
+ RECT 1245.555000 223.800000 1246.820000 224.280000 ;
+ RECT 1245.555000 218.360000 1246.820000 218.840000 ;
+ RECT 1245.555000 212.920000 1246.820000 213.400000 ;
+ RECT 1245.555000 202.040000 1246.820000 202.520000 ;
+ RECT 1245.555000 207.480000 1246.820000 207.960000 ;
+ RECT 1245.555000 196.600000 1246.820000 197.080000 ;
+ RECT 1245.555000 191.160000 1246.820000 191.640000 ;
+ RECT 1245.555000 185.720000 1246.820000 186.200000 ;
+ RECT 1245.555000 180.280000 1246.820000 180.760000 ;
+ RECT 1245.555000 174.840000 1246.820000 175.320000 ;
+ RECT 1245.555000 169.400000 1246.820000 169.880000 ;
+ RECT 1245.555000 158.520000 1246.820000 159.000000 ;
+ RECT 1245.555000 163.960000 1246.820000 164.440000 ;
+ RECT 1245.555000 153.080000 1246.820000 153.560000 ;
+ RECT 1245.555000 245.560000 1246.820000 246.040000 ;
+ RECT 1425.720000 146.750000 1426.820000 343.320000 ;
+ RECT 1380.720000 146.750000 1381.820000 343.320000 ;
+ RECT 1438.530000 145.500000 1439.530000 345.760000 ;
+ RECT 1335.720000 146.750000 1336.820000 343.320000 ;
+ RECT 1290.720000 146.750000 1291.820000 343.320000 ;
+ RECT 1245.720000 146.750000 1246.820000 343.320000 ;
+ RECT 1241.890000 145.500000 1242.890000 345.760000 ;
+ LAYER met3 ;
+ RECT 1425.720000 338.040000 1426.820000 338.520000 ;
+ RECT 1438.530000 338.040000 1439.530000 338.520000 ;
+ RECT 1438.530000 327.160000 1439.530000 327.640000 ;
+ RECT 1438.530000 321.720000 1439.530000 322.200000 ;
+ RECT 1438.530000 332.600000 1439.530000 333.080000 ;
+ RECT 1425.720000 332.600000 1426.820000 333.080000 ;
+ RECT 1425.720000 327.160000 1426.820000 327.640000 ;
+ RECT 1425.720000 321.720000 1426.820000 322.200000 ;
+ RECT 1425.720000 310.840000 1426.820000 311.320000 ;
+ RECT 1425.720000 316.280000 1426.820000 316.760000 ;
+ RECT 1438.530000 310.840000 1439.530000 311.320000 ;
+ RECT 1438.530000 316.280000 1439.530000 316.760000 ;
+ RECT 1425.720000 299.960000 1426.820000 300.440000 ;
+ RECT 1425.720000 305.400000 1426.820000 305.880000 ;
+ RECT 1438.530000 299.960000 1439.530000 300.440000 ;
+ RECT 1438.530000 305.400000 1439.530000 305.880000 ;
+ RECT 1380.720000 321.720000 1381.820000 322.200000 ;
+ RECT 1380.720000 327.160000 1381.820000 327.640000 ;
+ RECT 1380.720000 332.600000 1381.820000 333.080000 ;
+ RECT 1380.720000 338.040000 1381.820000 338.520000 ;
+ RECT 1380.720000 305.400000 1381.820000 305.880000 ;
+ RECT 1380.720000 299.960000 1381.820000 300.440000 ;
+ RECT 1380.720000 310.840000 1381.820000 311.320000 ;
+ RECT 1380.720000 316.280000 1381.820000 316.760000 ;
+ RECT 1438.530000 289.080000 1439.530000 289.560000 ;
+ RECT 1438.530000 283.640000 1439.530000 284.120000 ;
+ RECT 1438.530000 294.520000 1439.530000 295.000000 ;
+ RECT 1425.720000 294.520000 1426.820000 295.000000 ;
+ RECT 1425.720000 289.080000 1426.820000 289.560000 ;
+ RECT 1425.720000 283.640000 1426.820000 284.120000 ;
+ RECT 1425.720000 272.760000 1426.820000 273.240000 ;
+ RECT 1425.720000 278.200000 1426.820000 278.680000 ;
+ RECT 1438.530000 272.760000 1439.530000 273.240000 ;
+ RECT 1438.530000 278.200000 1439.530000 278.680000 ;
+ RECT 1438.530000 261.880000 1439.530000 262.360000 ;
+ RECT 1438.530000 267.320000 1439.530000 267.800000 ;
+ RECT 1425.720000 267.320000 1426.820000 267.800000 ;
+ RECT 1425.720000 261.880000 1426.820000 262.360000 ;
+ RECT 1425.720000 251.000000 1426.820000 251.480000 ;
+ RECT 1425.720000 256.440000 1426.820000 256.920000 ;
+ RECT 1438.530000 251.000000 1439.530000 251.480000 ;
+ RECT 1438.530000 256.440000 1439.530000 256.920000 ;
+ RECT 1380.720000 272.760000 1381.820000 273.240000 ;
+ RECT 1380.720000 278.200000 1381.820000 278.680000 ;
+ RECT 1380.720000 283.640000 1381.820000 284.120000 ;
+ RECT 1380.720000 289.080000 1381.820000 289.560000 ;
+ RECT 1380.720000 294.520000 1381.820000 295.000000 ;
+ RECT 1380.720000 251.000000 1381.820000 251.480000 ;
+ RECT 1380.720000 256.440000 1381.820000 256.920000 ;
+ RECT 1380.720000 261.880000 1381.820000 262.360000 ;
+ RECT 1380.720000 267.320000 1381.820000 267.800000 ;
+ RECT 1335.720000 327.160000 1336.820000 327.640000 ;
+ RECT 1335.720000 321.720000 1336.820000 322.200000 ;
+ RECT 1335.720000 332.600000 1336.820000 333.080000 ;
+ RECT 1335.720000 338.040000 1336.820000 338.520000 ;
+ RECT 1290.720000 321.720000 1291.820000 322.200000 ;
+ RECT 1290.720000 327.160000 1291.820000 327.640000 ;
+ RECT 1290.720000 332.600000 1291.820000 333.080000 ;
+ RECT 1290.720000 338.040000 1291.820000 338.520000 ;
+ RECT 1335.720000 299.960000 1336.820000 300.440000 ;
+ RECT 1335.720000 305.400000 1336.820000 305.880000 ;
+ RECT 1335.720000 310.840000 1336.820000 311.320000 ;
+ RECT 1335.720000 316.280000 1336.820000 316.760000 ;
+ RECT 1290.720000 299.960000 1291.820000 300.440000 ;
+ RECT 1290.720000 305.400000 1291.820000 305.880000 ;
+ RECT 1290.720000 310.840000 1291.820000 311.320000 ;
+ RECT 1290.720000 316.280000 1291.820000 316.760000 ;
+ RECT 1241.890000 338.040000 1242.890000 338.520000 ;
+ RECT 1245.555000 338.040000 1246.820000 338.520000 ;
+ RECT 1241.890000 327.160000 1242.890000 327.640000 ;
+ RECT 1245.555000 327.160000 1246.820000 327.640000 ;
+ RECT 1241.890000 332.600000 1242.890000 333.080000 ;
+ RECT 1245.555000 332.600000 1246.820000 333.080000 ;
+ RECT 1241.890000 321.720000 1242.890000 322.200000 ;
+ RECT 1245.555000 321.720000 1246.820000 322.200000 ;
+ RECT 1241.890000 316.280000 1242.890000 316.760000 ;
+ RECT 1245.555000 316.280000 1246.820000 316.760000 ;
+ RECT 1241.890000 310.840000 1242.890000 311.320000 ;
+ RECT 1245.555000 310.840000 1246.820000 311.320000 ;
+ RECT 1241.890000 305.400000 1242.890000 305.880000 ;
+ RECT 1245.555000 305.400000 1246.820000 305.880000 ;
+ RECT 1241.890000 299.960000 1242.890000 300.440000 ;
+ RECT 1245.555000 299.960000 1246.820000 300.440000 ;
+ RECT 1335.720000 272.760000 1336.820000 273.240000 ;
+ RECT 1335.720000 278.200000 1336.820000 278.680000 ;
+ RECT 1335.720000 283.640000 1336.820000 284.120000 ;
+ RECT 1335.720000 289.080000 1336.820000 289.560000 ;
+ RECT 1335.720000 294.520000 1336.820000 295.000000 ;
+ RECT 1290.720000 272.760000 1291.820000 273.240000 ;
+ RECT 1290.720000 278.200000 1291.820000 278.680000 ;
+ RECT 1290.720000 283.640000 1291.820000 284.120000 ;
+ RECT 1290.720000 289.080000 1291.820000 289.560000 ;
+ RECT 1290.720000 294.520000 1291.820000 295.000000 ;
+ RECT 1335.720000 251.000000 1336.820000 251.480000 ;
+ RECT 1335.720000 256.440000 1336.820000 256.920000 ;
+ RECT 1335.720000 261.880000 1336.820000 262.360000 ;
+ RECT 1335.720000 267.320000 1336.820000 267.800000 ;
+ RECT 1290.720000 251.000000 1291.820000 251.480000 ;
+ RECT 1290.720000 256.440000 1291.820000 256.920000 ;
+ RECT 1290.720000 261.880000 1291.820000 262.360000 ;
+ RECT 1290.720000 267.320000 1291.820000 267.800000 ;
+ RECT 1241.890000 294.520000 1242.890000 295.000000 ;
+ RECT 1245.555000 294.520000 1246.820000 295.000000 ;
+ RECT 1241.890000 283.640000 1242.890000 284.120000 ;
+ RECT 1245.555000 283.640000 1246.820000 284.120000 ;
+ RECT 1241.890000 289.080000 1242.890000 289.560000 ;
+ RECT 1245.555000 289.080000 1246.820000 289.560000 ;
+ RECT 1241.890000 278.200000 1242.890000 278.680000 ;
+ RECT 1245.555000 278.200000 1246.820000 278.680000 ;
+ RECT 1241.890000 272.760000 1242.890000 273.240000 ;
+ RECT 1245.555000 272.760000 1246.820000 273.240000 ;
+ RECT 1241.890000 267.320000 1242.890000 267.800000 ;
+ RECT 1245.555000 267.320000 1246.820000 267.800000 ;
+ RECT 1241.890000 261.880000 1242.890000 262.360000 ;
+ RECT 1245.555000 261.880000 1246.820000 262.360000 ;
+ RECT 1241.890000 256.440000 1242.890000 256.920000 ;
+ RECT 1245.555000 256.440000 1246.820000 256.920000 ;
+ RECT 1241.890000 251.000000 1242.890000 251.480000 ;
+ RECT 1245.555000 251.000000 1246.820000 251.480000 ;
+ RECT 1425.720000 234.680000 1426.820000 235.160000 ;
+ RECT 1425.720000 240.120000 1426.820000 240.600000 ;
+ RECT 1438.530000 234.680000 1439.530000 235.160000 ;
+ RECT 1438.530000 240.120000 1439.530000 240.600000 ;
+ RECT 1438.530000 223.800000 1439.530000 224.280000 ;
+ RECT 1438.530000 229.240000 1439.530000 229.720000 ;
+ RECT 1425.720000 229.240000 1426.820000 229.720000 ;
+ RECT 1425.720000 223.800000 1426.820000 224.280000 ;
+ RECT 1425.720000 212.920000 1426.820000 213.400000 ;
+ RECT 1425.720000 218.360000 1426.820000 218.840000 ;
+ RECT 1438.530000 212.920000 1439.530000 213.400000 ;
+ RECT 1438.530000 218.360000 1439.530000 218.840000 ;
+ RECT 1438.530000 202.040000 1439.530000 202.520000 ;
+ RECT 1438.530000 196.600000 1439.530000 197.080000 ;
+ RECT 1438.530000 207.480000 1439.530000 207.960000 ;
+ RECT 1425.720000 207.480000 1426.820000 207.960000 ;
+ RECT 1425.720000 202.040000 1426.820000 202.520000 ;
+ RECT 1425.720000 196.600000 1426.820000 197.080000 ;
+ RECT 1380.720000 223.800000 1381.820000 224.280000 ;
+ RECT 1380.720000 229.240000 1381.820000 229.720000 ;
+ RECT 1380.720000 234.680000 1381.820000 235.160000 ;
+ RECT 1380.720000 240.120000 1381.820000 240.600000 ;
+ RECT 1380.720000 196.600000 1381.820000 197.080000 ;
+ RECT 1380.720000 202.040000 1381.820000 202.520000 ;
+ RECT 1380.720000 207.480000 1381.820000 207.960000 ;
+ RECT 1380.720000 212.920000 1381.820000 213.400000 ;
+ RECT 1380.720000 218.360000 1381.820000 218.840000 ;
+ RECT 1425.720000 185.720000 1426.820000 186.200000 ;
+ RECT 1425.720000 191.160000 1426.820000 191.640000 ;
+ RECT 1438.530000 185.720000 1439.530000 186.200000 ;
+ RECT 1438.530000 191.160000 1439.530000 191.640000 ;
+ RECT 1425.720000 174.840000 1426.820000 175.320000 ;
+ RECT 1425.720000 180.280000 1426.820000 180.760000 ;
+ RECT 1438.530000 174.840000 1439.530000 175.320000 ;
+ RECT 1438.530000 180.280000 1439.530000 180.760000 ;
+ RECT 1438.530000 163.960000 1439.530000 164.440000 ;
+ RECT 1438.530000 158.520000 1439.530000 159.000000 ;
+ RECT 1438.530000 169.400000 1439.530000 169.880000 ;
+ RECT 1425.720000 169.400000 1426.820000 169.880000 ;
+ RECT 1425.720000 163.960000 1426.820000 164.440000 ;
+ RECT 1425.720000 158.520000 1426.820000 159.000000 ;
+ RECT 1425.720000 153.080000 1426.820000 153.560000 ;
+ RECT 1438.530000 153.080000 1439.530000 153.560000 ;
+ RECT 1380.720000 174.840000 1381.820000 175.320000 ;
+ RECT 1380.720000 180.280000 1381.820000 180.760000 ;
+ RECT 1380.720000 185.720000 1381.820000 186.200000 ;
+ RECT 1380.720000 191.160000 1381.820000 191.640000 ;
+ RECT 1380.720000 153.080000 1381.820000 153.560000 ;
+ RECT 1380.720000 158.520000 1381.820000 159.000000 ;
+ RECT 1380.720000 163.960000 1381.820000 164.440000 ;
+ RECT 1380.720000 169.400000 1381.820000 169.880000 ;
+ RECT 1335.720000 223.800000 1336.820000 224.280000 ;
+ RECT 1335.720000 229.240000 1336.820000 229.720000 ;
+ RECT 1335.720000 234.680000 1336.820000 235.160000 ;
+ RECT 1335.720000 240.120000 1336.820000 240.600000 ;
+ RECT 1290.720000 223.800000 1291.820000 224.280000 ;
+ RECT 1290.720000 229.240000 1291.820000 229.720000 ;
+ RECT 1290.720000 234.680000 1291.820000 235.160000 ;
+ RECT 1290.720000 240.120000 1291.820000 240.600000 ;
+ RECT 1335.720000 196.600000 1336.820000 197.080000 ;
+ RECT 1335.720000 202.040000 1336.820000 202.520000 ;
+ RECT 1335.720000 207.480000 1336.820000 207.960000 ;
+ RECT 1335.720000 212.920000 1336.820000 213.400000 ;
+ RECT 1335.720000 218.360000 1336.820000 218.840000 ;
+ RECT 1290.720000 196.600000 1291.820000 197.080000 ;
+ RECT 1290.720000 202.040000 1291.820000 202.520000 ;
+ RECT 1290.720000 207.480000 1291.820000 207.960000 ;
+ RECT 1290.720000 212.920000 1291.820000 213.400000 ;
+ RECT 1290.720000 218.360000 1291.820000 218.840000 ;
+ RECT 1241.890000 240.120000 1242.890000 240.600000 ;
+ RECT 1245.555000 240.120000 1246.820000 240.600000 ;
+ RECT 1241.890000 234.680000 1242.890000 235.160000 ;
+ RECT 1245.555000 234.680000 1246.820000 235.160000 ;
+ RECT 1241.890000 229.240000 1242.890000 229.720000 ;
+ RECT 1245.555000 229.240000 1246.820000 229.720000 ;
+ RECT 1241.890000 223.800000 1242.890000 224.280000 ;
+ RECT 1245.555000 223.800000 1246.820000 224.280000 ;
+ RECT 1241.890000 218.360000 1242.890000 218.840000 ;
+ RECT 1245.555000 218.360000 1246.820000 218.840000 ;
+ RECT 1241.890000 212.920000 1242.890000 213.400000 ;
+ RECT 1245.555000 212.920000 1246.820000 213.400000 ;
+ RECT 1241.890000 202.040000 1242.890000 202.520000 ;
+ RECT 1245.555000 202.040000 1246.820000 202.520000 ;
+ RECT 1241.890000 207.480000 1242.890000 207.960000 ;
+ RECT 1245.555000 207.480000 1246.820000 207.960000 ;
+ RECT 1241.890000 196.600000 1242.890000 197.080000 ;
+ RECT 1245.555000 196.600000 1246.820000 197.080000 ;
+ RECT 1335.720000 174.840000 1336.820000 175.320000 ;
+ RECT 1335.720000 180.280000 1336.820000 180.760000 ;
+ RECT 1335.720000 185.720000 1336.820000 186.200000 ;
+ RECT 1335.720000 191.160000 1336.820000 191.640000 ;
+ RECT 1290.720000 174.840000 1291.820000 175.320000 ;
+ RECT 1290.720000 180.280000 1291.820000 180.760000 ;
+ RECT 1290.720000 185.720000 1291.820000 186.200000 ;
+ RECT 1290.720000 191.160000 1291.820000 191.640000 ;
+ RECT 1335.720000 153.080000 1336.820000 153.560000 ;
+ RECT 1335.720000 158.520000 1336.820000 159.000000 ;
+ RECT 1335.720000 163.960000 1336.820000 164.440000 ;
+ RECT 1335.720000 169.400000 1336.820000 169.880000 ;
+ RECT 1290.720000 153.080000 1291.820000 153.560000 ;
+ RECT 1290.720000 158.520000 1291.820000 159.000000 ;
+ RECT 1290.720000 163.960000 1291.820000 164.440000 ;
+ RECT 1290.720000 169.400000 1291.820000 169.880000 ;
+ RECT 1241.890000 191.160000 1242.890000 191.640000 ;
+ RECT 1245.555000 191.160000 1246.820000 191.640000 ;
+ RECT 1241.890000 185.720000 1242.890000 186.200000 ;
+ RECT 1245.555000 185.720000 1246.820000 186.200000 ;
+ RECT 1241.890000 180.280000 1242.890000 180.760000 ;
+ RECT 1245.555000 180.280000 1246.820000 180.760000 ;
+ RECT 1241.890000 174.840000 1242.890000 175.320000 ;
+ RECT 1245.555000 174.840000 1246.820000 175.320000 ;
+ RECT 1241.890000 169.400000 1242.890000 169.880000 ;
+ RECT 1245.555000 169.400000 1246.820000 169.880000 ;
+ RECT 1241.890000 158.520000 1242.890000 159.000000 ;
+ RECT 1245.555000 158.520000 1246.820000 159.000000 ;
+ RECT 1241.890000 163.960000 1242.890000 164.440000 ;
+ RECT 1245.555000 163.960000 1246.820000 164.440000 ;
+ RECT 1241.890000 153.080000 1242.890000 153.560000 ;
+ RECT 1245.555000 153.080000 1246.820000 153.560000 ;
+ RECT 1380.720000 245.560000 1381.820000 246.040000 ;
+ RECT 1425.720000 245.560000 1426.820000 246.040000 ;
+ RECT 1438.530000 245.560000 1439.530000 246.040000 ;
+ RECT 1290.720000 245.560000 1291.820000 246.040000 ;
+ RECT 1335.720000 245.560000 1336.820000 246.040000 ;
+ RECT 1241.890000 245.560000 1242.890000 246.040000 ;
+ RECT 1245.555000 245.560000 1246.820000 246.040000 ;
+ RECT 1240.660000 342.320000 1440.760000 343.320000 ;
+ RECT 1240.660000 146.750000 1440.760000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 145.500000 1242.890000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 344.760000 1242.890000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 145.500000 1439.530000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 344.760000 1439.530000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 146.750000 1241.660000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 146.750000 1440.760000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 342.320000 1241.660000 343.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 342.320000 1440.760000 343.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 139.140000 1246.820000 139.620000 ;
+ RECT 1245.555000 133.700000 1246.820000 134.180000 ;
+ RECT 1245.555000 128.260000 1246.820000 128.740000 ;
+ RECT 1245.555000 122.820000 1246.820000 123.300000 ;
+ RECT 1241.890000 115.240000 1242.890000 145.500000 ;
+ RECT 1438.530000 115.240000 1439.530000 145.500000 ;
+ RECT 1245.720000 116.490000 1246.820000 143.740000 ;
+ RECT 1290.720000 116.490000 1291.820000 143.740000 ;
+ RECT 1335.720000 116.490000 1336.820000 143.740000 ;
+ RECT 1380.720000 116.490000 1381.820000 143.740000 ;
+ RECT 1425.720000 116.490000 1426.820000 143.740000 ;
+ LAYER met3 ;
+ RECT 1438.530000 139.140000 1439.530000 139.620000 ;
+ RECT 1438.530000 133.700000 1439.530000 134.180000 ;
+ RECT 1425.720000 139.140000 1426.820000 139.620000 ;
+ RECT 1425.720000 133.700000 1426.820000 134.180000 ;
+ RECT 1380.720000 133.700000 1381.820000 134.180000 ;
+ RECT 1380.720000 139.140000 1381.820000 139.620000 ;
+ RECT 1335.720000 133.700000 1336.820000 134.180000 ;
+ RECT 1290.720000 133.700000 1291.820000 134.180000 ;
+ RECT 1335.720000 139.140000 1336.820000 139.620000 ;
+ RECT 1290.720000 139.140000 1291.820000 139.620000 ;
+ RECT 1245.555000 139.140000 1246.820000 139.620000 ;
+ RECT 1241.890000 139.140000 1242.890000 139.620000 ;
+ RECT 1245.555000 133.700000 1246.820000 134.180000 ;
+ RECT 1241.890000 133.700000 1242.890000 134.180000 ;
+ RECT 1438.530000 128.260000 1439.530000 128.740000 ;
+ RECT 1438.530000 122.820000 1439.530000 123.300000 ;
+ RECT 1425.720000 128.260000 1426.820000 128.740000 ;
+ RECT 1425.720000 122.820000 1426.820000 123.300000 ;
+ RECT 1380.720000 122.820000 1381.820000 123.300000 ;
+ RECT 1380.720000 128.260000 1381.820000 128.740000 ;
+ RECT 1335.720000 122.820000 1336.820000 123.300000 ;
+ RECT 1290.720000 122.820000 1291.820000 123.300000 ;
+ RECT 1335.720000 128.260000 1336.820000 128.740000 ;
+ RECT 1290.720000 128.260000 1291.820000 128.740000 ;
+ RECT 1245.555000 128.260000 1246.820000 128.740000 ;
+ RECT 1241.890000 128.260000 1242.890000 128.740000 ;
+ RECT 1245.555000 122.820000 1246.820000 123.300000 ;
+ RECT 1241.890000 122.820000 1242.890000 123.300000 ;
+ RECT 1240.660000 142.740000 1440.760000 143.740000 ;
+ RECT 1240.660000 116.490000 1440.760000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 116.490000 1241.660000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 116.490000 1440.760000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 142.740000 1241.660000 143.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 142.740000 1440.760000 143.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 115.240000 1242.890000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 144.500000 1242.890000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 115.240000 1439.530000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 144.500000 1439.530000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 3341.940000 1246.820000 3342.420000 ;
+ RECT 1245.555000 3331.060000 1246.820000 3331.540000 ;
+ RECT 1245.555000 3336.500000 1246.820000 3336.980000 ;
+ RECT 1245.555000 3325.620000 1246.820000 3326.100000 ;
+ RECT 1245.555000 3320.180000 1246.820000 3320.660000 ;
+ RECT 1245.555000 3314.740000 1246.820000 3315.220000 ;
+ RECT 1245.555000 3309.300000 1246.820000 3309.780000 ;
+ RECT 1245.555000 3303.860000 1246.820000 3304.340000 ;
+ RECT 1245.555000 3298.420000 1246.820000 3298.900000 ;
+ RECT 1245.555000 3287.540000 1246.820000 3288.020000 ;
+ RECT 1245.555000 3292.980000 1246.820000 3293.460000 ;
+ RECT 1245.555000 3282.100000 1246.820000 3282.580000 ;
+ RECT 1245.555000 3276.660000 1246.820000 3277.140000 ;
+ RECT 1245.555000 3271.220000 1246.820000 3271.700000 ;
+ RECT 1245.555000 3265.780000 1246.820000 3266.260000 ;
+ RECT 1245.555000 3260.340000 1246.820000 3260.820000 ;
+ RECT 1245.555000 3254.900000 1246.820000 3255.380000 ;
+ RECT 1245.555000 3244.020000 1246.820000 3244.500000 ;
+ RECT 1245.555000 3238.580000 1246.820000 3239.060000 ;
+ RECT 1245.555000 3233.140000 1246.820000 3233.620000 ;
+ RECT 1245.555000 3227.700000 1246.820000 3228.180000 ;
+ RECT 1245.555000 3222.260000 1246.820000 3222.740000 ;
+ RECT 1245.555000 3216.820000 1246.820000 3217.300000 ;
+ RECT 1245.555000 3205.940000 1246.820000 3206.420000 ;
+ RECT 1245.555000 3211.380000 1246.820000 3211.860000 ;
+ RECT 1245.555000 3200.500000 1246.820000 3200.980000 ;
+ RECT 1245.555000 3195.060000 1246.820000 3195.540000 ;
+ RECT 1245.555000 3189.620000 1246.820000 3190.100000 ;
+ RECT 1245.555000 3184.180000 1246.820000 3184.660000 ;
+ RECT 1245.555000 3178.740000 1246.820000 3179.220000 ;
+ RECT 1245.555000 3173.300000 1246.820000 3173.780000 ;
+ RECT 1245.555000 3162.420000 1246.820000 3162.900000 ;
+ RECT 1245.555000 3167.860000 1246.820000 3168.340000 ;
+ RECT 1245.555000 3156.980000 1246.820000 3157.460000 ;
+ RECT 1245.555000 3249.460000 1246.820000 3249.940000 ;
+ RECT 1425.720000 3150.650000 1426.820000 3347.220000 ;
+ RECT 1380.720000 3150.650000 1381.820000 3347.220000 ;
+ RECT 1438.530000 3149.400000 1439.530000 3349.660000 ;
+ RECT 1335.720000 3150.650000 1336.820000 3347.220000 ;
+ RECT 1290.720000 3150.650000 1291.820000 3347.220000 ;
+ RECT 1245.720000 3150.650000 1246.820000 3347.220000 ;
+ RECT 1241.890000 3149.400000 1242.890000 3349.660000 ;
+ LAYER met3 ;
+ RECT 1425.720000 3341.940000 1426.820000 3342.420000 ;
+ RECT 1438.530000 3341.940000 1439.530000 3342.420000 ;
+ RECT 1438.530000 3331.060000 1439.530000 3331.540000 ;
+ RECT 1438.530000 3325.620000 1439.530000 3326.100000 ;
+ RECT 1438.530000 3336.500000 1439.530000 3336.980000 ;
+ RECT 1425.720000 3336.500000 1426.820000 3336.980000 ;
+ RECT 1425.720000 3331.060000 1426.820000 3331.540000 ;
+ RECT 1425.720000 3325.620000 1426.820000 3326.100000 ;
+ RECT 1425.720000 3314.740000 1426.820000 3315.220000 ;
+ RECT 1425.720000 3320.180000 1426.820000 3320.660000 ;
+ RECT 1438.530000 3314.740000 1439.530000 3315.220000 ;
+ RECT 1438.530000 3320.180000 1439.530000 3320.660000 ;
+ RECT 1425.720000 3303.860000 1426.820000 3304.340000 ;
+ RECT 1425.720000 3309.300000 1426.820000 3309.780000 ;
+ RECT 1438.530000 3303.860000 1439.530000 3304.340000 ;
+ RECT 1438.530000 3309.300000 1439.530000 3309.780000 ;
+ RECT 1380.720000 3325.620000 1381.820000 3326.100000 ;
+ RECT 1380.720000 3331.060000 1381.820000 3331.540000 ;
+ RECT 1380.720000 3336.500000 1381.820000 3336.980000 ;
+ RECT 1380.720000 3341.940000 1381.820000 3342.420000 ;
+ RECT 1380.720000 3309.300000 1381.820000 3309.780000 ;
+ RECT 1380.720000 3303.860000 1381.820000 3304.340000 ;
+ RECT 1380.720000 3314.740000 1381.820000 3315.220000 ;
+ RECT 1380.720000 3320.180000 1381.820000 3320.660000 ;
+ RECT 1438.530000 3292.980000 1439.530000 3293.460000 ;
+ RECT 1438.530000 3287.540000 1439.530000 3288.020000 ;
+ RECT 1438.530000 3298.420000 1439.530000 3298.900000 ;
+ RECT 1425.720000 3298.420000 1426.820000 3298.900000 ;
+ RECT 1425.720000 3292.980000 1426.820000 3293.460000 ;
+ RECT 1425.720000 3287.540000 1426.820000 3288.020000 ;
+ RECT 1425.720000 3276.660000 1426.820000 3277.140000 ;
+ RECT 1425.720000 3282.100000 1426.820000 3282.580000 ;
+ RECT 1438.530000 3276.660000 1439.530000 3277.140000 ;
+ RECT 1438.530000 3282.100000 1439.530000 3282.580000 ;
+ RECT 1438.530000 3265.780000 1439.530000 3266.260000 ;
+ RECT 1438.530000 3271.220000 1439.530000 3271.700000 ;
+ RECT 1425.720000 3271.220000 1426.820000 3271.700000 ;
+ RECT 1425.720000 3265.780000 1426.820000 3266.260000 ;
+ RECT 1425.720000 3254.900000 1426.820000 3255.380000 ;
+ RECT 1425.720000 3260.340000 1426.820000 3260.820000 ;
+ RECT 1438.530000 3254.900000 1439.530000 3255.380000 ;
+ RECT 1438.530000 3260.340000 1439.530000 3260.820000 ;
+ RECT 1380.720000 3276.660000 1381.820000 3277.140000 ;
+ RECT 1380.720000 3282.100000 1381.820000 3282.580000 ;
+ RECT 1380.720000 3287.540000 1381.820000 3288.020000 ;
+ RECT 1380.720000 3292.980000 1381.820000 3293.460000 ;
+ RECT 1380.720000 3298.420000 1381.820000 3298.900000 ;
+ RECT 1380.720000 3254.900000 1381.820000 3255.380000 ;
+ RECT 1380.720000 3260.340000 1381.820000 3260.820000 ;
+ RECT 1380.720000 3265.780000 1381.820000 3266.260000 ;
+ RECT 1380.720000 3271.220000 1381.820000 3271.700000 ;
+ RECT 1335.720000 3331.060000 1336.820000 3331.540000 ;
+ RECT 1335.720000 3325.620000 1336.820000 3326.100000 ;
+ RECT 1335.720000 3336.500000 1336.820000 3336.980000 ;
+ RECT 1335.720000 3341.940000 1336.820000 3342.420000 ;
+ RECT 1290.720000 3325.620000 1291.820000 3326.100000 ;
+ RECT 1290.720000 3331.060000 1291.820000 3331.540000 ;
+ RECT 1290.720000 3336.500000 1291.820000 3336.980000 ;
+ RECT 1290.720000 3341.940000 1291.820000 3342.420000 ;
+ RECT 1335.720000 3303.860000 1336.820000 3304.340000 ;
+ RECT 1335.720000 3309.300000 1336.820000 3309.780000 ;
+ RECT 1335.720000 3314.740000 1336.820000 3315.220000 ;
+ RECT 1335.720000 3320.180000 1336.820000 3320.660000 ;
+ RECT 1290.720000 3303.860000 1291.820000 3304.340000 ;
+ RECT 1290.720000 3309.300000 1291.820000 3309.780000 ;
+ RECT 1290.720000 3314.740000 1291.820000 3315.220000 ;
+ RECT 1290.720000 3320.180000 1291.820000 3320.660000 ;
+ RECT 1241.890000 3341.940000 1242.890000 3342.420000 ;
+ RECT 1245.555000 3341.940000 1246.820000 3342.420000 ;
+ RECT 1241.890000 3331.060000 1242.890000 3331.540000 ;
+ RECT 1245.555000 3331.060000 1246.820000 3331.540000 ;
+ RECT 1241.890000 3336.500000 1242.890000 3336.980000 ;
+ RECT 1245.555000 3336.500000 1246.820000 3336.980000 ;
+ RECT 1241.890000 3325.620000 1242.890000 3326.100000 ;
+ RECT 1245.555000 3325.620000 1246.820000 3326.100000 ;
+ RECT 1241.890000 3320.180000 1242.890000 3320.660000 ;
+ RECT 1245.555000 3320.180000 1246.820000 3320.660000 ;
+ RECT 1241.890000 3314.740000 1242.890000 3315.220000 ;
+ RECT 1245.555000 3314.740000 1246.820000 3315.220000 ;
+ RECT 1241.890000 3309.300000 1242.890000 3309.780000 ;
+ RECT 1245.555000 3309.300000 1246.820000 3309.780000 ;
+ RECT 1241.890000 3303.860000 1242.890000 3304.340000 ;
+ RECT 1245.555000 3303.860000 1246.820000 3304.340000 ;
+ RECT 1335.720000 3276.660000 1336.820000 3277.140000 ;
+ RECT 1335.720000 3282.100000 1336.820000 3282.580000 ;
+ RECT 1335.720000 3287.540000 1336.820000 3288.020000 ;
+ RECT 1335.720000 3292.980000 1336.820000 3293.460000 ;
+ RECT 1335.720000 3298.420000 1336.820000 3298.900000 ;
+ RECT 1290.720000 3276.660000 1291.820000 3277.140000 ;
+ RECT 1290.720000 3282.100000 1291.820000 3282.580000 ;
+ RECT 1290.720000 3287.540000 1291.820000 3288.020000 ;
+ RECT 1290.720000 3292.980000 1291.820000 3293.460000 ;
+ RECT 1290.720000 3298.420000 1291.820000 3298.900000 ;
+ RECT 1335.720000 3254.900000 1336.820000 3255.380000 ;
+ RECT 1335.720000 3260.340000 1336.820000 3260.820000 ;
+ RECT 1335.720000 3265.780000 1336.820000 3266.260000 ;
+ RECT 1335.720000 3271.220000 1336.820000 3271.700000 ;
+ RECT 1290.720000 3254.900000 1291.820000 3255.380000 ;
+ RECT 1290.720000 3260.340000 1291.820000 3260.820000 ;
+ RECT 1290.720000 3265.780000 1291.820000 3266.260000 ;
+ RECT 1290.720000 3271.220000 1291.820000 3271.700000 ;
+ RECT 1241.890000 3298.420000 1242.890000 3298.900000 ;
+ RECT 1245.555000 3298.420000 1246.820000 3298.900000 ;
+ RECT 1241.890000 3287.540000 1242.890000 3288.020000 ;
+ RECT 1245.555000 3287.540000 1246.820000 3288.020000 ;
+ RECT 1241.890000 3292.980000 1242.890000 3293.460000 ;
+ RECT 1245.555000 3292.980000 1246.820000 3293.460000 ;
+ RECT 1241.890000 3282.100000 1242.890000 3282.580000 ;
+ RECT 1245.555000 3282.100000 1246.820000 3282.580000 ;
+ RECT 1241.890000 3276.660000 1242.890000 3277.140000 ;
+ RECT 1245.555000 3276.660000 1246.820000 3277.140000 ;
+ RECT 1241.890000 3271.220000 1242.890000 3271.700000 ;
+ RECT 1245.555000 3271.220000 1246.820000 3271.700000 ;
+ RECT 1241.890000 3265.780000 1242.890000 3266.260000 ;
+ RECT 1245.555000 3265.780000 1246.820000 3266.260000 ;
+ RECT 1241.890000 3260.340000 1242.890000 3260.820000 ;
+ RECT 1245.555000 3260.340000 1246.820000 3260.820000 ;
+ RECT 1241.890000 3254.900000 1242.890000 3255.380000 ;
+ RECT 1245.555000 3254.900000 1246.820000 3255.380000 ;
+ RECT 1425.720000 3238.580000 1426.820000 3239.060000 ;
+ RECT 1425.720000 3244.020000 1426.820000 3244.500000 ;
+ RECT 1438.530000 3238.580000 1439.530000 3239.060000 ;
+ RECT 1438.530000 3244.020000 1439.530000 3244.500000 ;
+ RECT 1438.530000 3227.700000 1439.530000 3228.180000 ;
+ RECT 1438.530000 3233.140000 1439.530000 3233.620000 ;
+ RECT 1425.720000 3233.140000 1426.820000 3233.620000 ;
+ RECT 1425.720000 3227.700000 1426.820000 3228.180000 ;
+ RECT 1425.720000 3216.820000 1426.820000 3217.300000 ;
+ RECT 1425.720000 3222.260000 1426.820000 3222.740000 ;
+ RECT 1438.530000 3216.820000 1439.530000 3217.300000 ;
+ RECT 1438.530000 3222.260000 1439.530000 3222.740000 ;
+ RECT 1438.530000 3205.940000 1439.530000 3206.420000 ;
+ RECT 1438.530000 3200.500000 1439.530000 3200.980000 ;
+ RECT 1438.530000 3211.380000 1439.530000 3211.860000 ;
+ RECT 1425.720000 3211.380000 1426.820000 3211.860000 ;
+ RECT 1425.720000 3205.940000 1426.820000 3206.420000 ;
+ RECT 1425.720000 3200.500000 1426.820000 3200.980000 ;
+ RECT 1380.720000 3227.700000 1381.820000 3228.180000 ;
+ RECT 1380.720000 3233.140000 1381.820000 3233.620000 ;
+ RECT 1380.720000 3238.580000 1381.820000 3239.060000 ;
+ RECT 1380.720000 3244.020000 1381.820000 3244.500000 ;
+ RECT 1380.720000 3200.500000 1381.820000 3200.980000 ;
+ RECT 1380.720000 3205.940000 1381.820000 3206.420000 ;
+ RECT 1380.720000 3211.380000 1381.820000 3211.860000 ;
+ RECT 1380.720000 3216.820000 1381.820000 3217.300000 ;
+ RECT 1380.720000 3222.260000 1381.820000 3222.740000 ;
+ RECT 1425.720000 3189.620000 1426.820000 3190.100000 ;
+ RECT 1425.720000 3195.060000 1426.820000 3195.540000 ;
+ RECT 1438.530000 3189.620000 1439.530000 3190.100000 ;
+ RECT 1438.530000 3195.060000 1439.530000 3195.540000 ;
+ RECT 1425.720000 3178.740000 1426.820000 3179.220000 ;
+ RECT 1425.720000 3184.180000 1426.820000 3184.660000 ;
+ RECT 1438.530000 3178.740000 1439.530000 3179.220000 ;
+ RECT 1438.530000 3184.180000 1439.530000 3184.660000 ;
+ RECT 1438.530000 3167.860000 1439.530000 3168.340000 ;
+ RECT 1438.530000 3162.420000 1439.530000 3162.900000 ;
+ RECT 1438.530000 3173.300000 1439.530000 3173.780000 ;
+ RECT 1425.720000 3173.300000 1426.820000 3173.780000 ;
+ RECT 1425.720000 3167.860000 1426.820000 3168.340000 ;
+ RECT 1425.720000 3162.420000 1426.820000 3162.900000 ;
+ RECT 1425.720000 3156.980000 1426.820000 3157.460000 ;
+ RECT 1438.530000 3156.980000 1439.530000 3157.460000 ;
+ RECT 1380.720000 3178.740000 1381.820000 3179.220000 ;
+ RECT 1380.720000 3184.180000 1381.820000 3184.660000 ;
+ RECT 1380.720000 3189.620000 1381.820000 3190.100000 ;
+ RECT 1380.720000 3195.060000 1381.820000 3195.540000 ;
+ RECT 1380.720000 3156.980000 1381.820000 3157.460000 ;
+ RECT 1380.720000 3162.420000 1381.820000 3162.900000 ;
+ RECT 1380.720000 3167.860000 1381.820000 3168.340000 ;
+ RECT 1380.720000 3173.300000 1381.820000 3173.780000 ;
+ RECT 1335.720000 3227.700000 1336.820000 3228.180000 ;
+ RECT 1335.720000 3233.140000 1336.820000 3233.620000 ;
+ RECT 1335.720000 3238.580000 1336.820000 3239.060000 ;
+ RECT 1335.720000 3244.020000 1336.820000 3244.500000 ;
+ RECT 1290.720000 3227.700000 1291.820000 3228.180000 ;
+ RECT 1290.720000 3233.140000 1291.820000 3233.620000 ;
+ RECT 1290.720000 3238.580000 1291.820000 3239.060000 ;
+ RECT 1290.720000 3244.020000 1291.820000 3244.500000 ;
+ RECT 1335.720000 3200.500000 1336.820000 3200.980000 ;
+ RECT 1335.720000 3205.940000 1336.820000 3206.420000 ;
+ RECT 1335.720000 3211.380000 1336.820000 3211.860000 ;
+ RECT 1335.720000 3216.820000 1336.820000 3217.300000 ;
+ RECT 1335.720000 3222.260000 1336.820000 3222.740000 ;
+ RECT 1290.720000 3200.500000 1291.820000 3200.980000 ;
+ RECT 1290.720000 3205.940000 1291.820000 3206.420000 ;
+ RECT 1290.720000 3211.380000 1291.820000 3211.860000 ;
+ RECT 1290.720000 3216.820000 1291.820000 3217.300000 ;
+ RECT 1290.720000 3222.260000 1291.820000 3222.740000 ;
+ RECT 1241.890000 3244.020000 1242.890000 3244.500000 ;
+ RECT 1245.555000 3244.020000 1246.820000 3244.500000 ;
+ RECT 1241.890000 3238.580000 1242.890000 3239.060000 ;
+ RECT 1245.555000 3238.580000 1246.820000 3239.060000 ;
+ RECT 1241.890000 3233.140000 1242.890000 3233.620000 ;
+ RECT 1245.555000 3233.140000 1246.820000 3233.620000 ;
+ RECT 1241.890000 3227.700000 1242.890000 3228.180000 ;
+ RECT 1245.555000 3227.700000 1246.820000 3228.180000 ;
+ RECT 1241.890000 3222.260000 1242.890000 3222.740000 ;
+ RECT 1245.555000 3222.260000 1246.820000 3222.740000 ;
+ RECT 1241.890000 3216.820000 1242.890000 3217.300000 ;
+ RECT 1245.555000 3216.820000 1246.820000 3217.300000 ;
+ RECT 1241.890000 3205.940000 1242.890000 3206.420000 ;
+ RECT 1245.555000 3205.940000 1246.820000 3206.420000 ;
+ RECT 1241.890000 3211.380000 1242.890000 3211.860000 ;
+ RECT 1245.555000 3211.380000 1246.820000 3211.860000 ;
+ RECT 1241.890000 3200.500000 1242.890000 3200.980000 ;
+ RECT 1245.555000 3200.500000 1246.820000 3200.980000 ;
+ RECT 1335.720000 3178.740000 1336.820000 3179.220000 ;
+ RECT 1335.720000 3184.180000 1336.820000 3184.660000 ;
+ RECT 1335.720000 3189.620000 1336.820000 3190.100000 ;
+ RECT 1335.720000 3195.060000 1336.820000 3195.540000 ;
+ RECT 1290.720000 3178.740000 1291.820000 3179.220000 ;
+ RECT 1290.720000 3184.180000 1291.820000 3184.660000 ;
+ RECT 1290.720000 3189.620000 1291.820000 3190.100000 ;
+ RECT 1290.720000 3195.060000 1291.820000 3195.540000 ;
+ RECT 1335.720000 3156.980000 1336.820000 3157.460000 ;
+ RECT 1335.720000 3162.420000 1336.820000 3162.900000 ;
+ RECT 1335.720000 3167.860000 1336.820000 3168.340000 ;
+ RECT 1335.720000 3173.300000 1336.820000 3173.780000 ;
+ RECT 1290.720000 3156.980000 1291.820000 3157.460000 ;
+ RECT 1290.720000 3162.420000 1291.820000 3162.900000 ;
+ RECT 1290.720000 3167.860000 1291.820000 3168.340000 ;
+ RECT 1290.720000 3173.300000 1291.820000 3173.780000 ;
+ RECT 1241.890000 3195.060000 1242.890000 3195.540000 ;
+ RECT 1245.555000 3195.060000 1246.820000 3195.540000 ;
+ RECT 1241.890000 3189.620000 1242.890000 3190.100000 ;
+ RECT 1245.555000 3189.620000 1246.820000 3190.100000 ;
+ RECT 1241.890000 3184.180000 1242.890000 3184.660000 ;
+ RECT 1245.555000 3184.180000 1246.820000 3184.660000 ;
+ RECT 1241.890000 3178.740000 1242.890000 3179.220000 ;
+ RECT 1245.555000 3178.740000 1246.820000 3179.220000 ;
+ RECT 1241.890000 3173.300000 1242.890000 3173.780000 ;
+ RECT 1245.555000 3173.300000 1246.820000 3173.780000 ;
+ RECT 1241.890000 3162.420000 1242.890000 3162.900000 ;
+ RECT 1245.555000 3162.420000 1246.820000 3162.900000 ;
+ RECT 1241.890000 3167.860000 1242.890000 3168.340000 ;
+ RECT 1245.555000 3167.860000 1246.820000 3168.340000 ;
+ RECT 1241.890000 3156.980000 1242.890000 3157.460000 ;
+ RECT 1245.555000 3156.980000 1246.820000 3157.460000 ;
+ RECT 1380.720000 3249.460000 1381.820000 3249.940000 ;
+ RECT 1425.720000 3249.460000 1426.820000 3249.940000 ;
+ RECT 1438.530000 3249.460000 1439.530000 3249.940000 ;
+ RECT 1290.720000 3249.460000 1291.820000 3249.940000 ;
+ RECT 1335.720000 3249.460000 1336.820000 3249.940000 ;
+ RECT 1241.890000 3249.460000 1242.890000 3249.940000 ;
+ RECT 1245.555000 3249.460000 1246.820000 3249.940000 ;
+ RECT 1240.660000 3346.220000 1440.760000 3347.220000 ;
+ RECT 1240.660000 3150.650000 1440.760000 3151.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 3149.400000 1242.890000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 3348.660000 1242.890000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 3149.400000 1439.530000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 3348.660000 1439.530000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 3150.650000 1241.660000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 3150.650000 1440.760000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 3346.220000 1241.660000 3347.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 3346.220000 1440.760000 3347.220000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 3141.680000 1246.820000 3142.160000 ;
+ RECT 1245.555000 3130.800000 1246.820000 3131.280000 ;
+ RECT 1245.555000 3136.240000 1246.820000 3136.720000 ;
+ RECT 1245.555000 3125.360000 1246.820000 3125.840000 ;
+ RECT 1245.555000 3119.920000 1246.820000 3120.400000 ;
+ RECT 1245.555000 3114.480000 1246.820000 3114.960000 ;
+ RECT 1245.555000 3109.040000 1246.820000 3109.520000 ;
+ RECT 1245.555000 3103.600000 1246.820000 3104.080000 ;
+ RECT 1245.555000 3098.160000 1246.820000 3098.640000 ;
+ RECT 1245.555000 3087.280000 1246.820000 3087.760000 ;
+ RECT 1245.555000 3092.720000 1246.820000 3093.200000 ;
+ RECT 1245.555000 3081.840000 1246.820000 3082.320000 ;
+ RECT 1245.555000 3076.400000 1246.820000 3076.880000 ;
+ RECT 1245.555000 3070.960000 1246.820000 3071.440000 ;
+ RECT 1245.555000 3065.520000 1246.820000 3066.000000 ;
+ RECT 1245.555000 3060.080000 1246.820000 3060.560000 ;
+ RECT 1245.555000 3054.640000 1246.820000 3055.120000 ;
+ RECT 1245.555000 3043.760000 1246.820000 3044.240000 ;
+ RECT 1245.555000 3038.320000 1246.820000 3038.800000 ;
+ RECT 1245.555000 3032.880000 1246.820000 3033.360000 ;
+ RECT 1245.555000 3027.440000 1246.820000 3027.920000 ;
+ RECT 1245.555000 3022.000000 1246.820000 3022.480000 ;
+ RECT 1245.555000 3016.560000 1246.820000 3017.040000 ;
+ RECT 1245.555000 3005.680000 1246.820000 3006.160000 ;
+ RECT 1245.555000 3011.120000 1246.820000 3011.600000 ;
+ RECT 1245.555000 3000.240000 1246.820000 3000.720000 ;
+ RECT 1245.555000 2994.800000 1246.820000 2995.280000 ;
+ RECT 1245.555000 2989.360000 1246.820000 2989.840000 ;
+ RECT 1245.555000 2983.920000 1246.820000 2984.400000 ;
+ RECT 1245.555000 2978.480000 1246.820000 2978.960000 ;
+ RECT 1245.555000 2973.040000 1246.820000 2973.520000 ;
+ RECT 1245.555000 2962.160000 1246.820000 2962.640000 ;
+ RECT 1245.555000 2967.600000 1246.820000 2968.080000 ;
+ RECT 1245.555000 2956.720000 1246.820000 2957.200000 ;
+ RECT 1245.555000 3049.200000 1246.820000 3049.680000 ;
+ RECT 1425.720000 2950.390000 1426.820000 3146.960000 ;
+ RECT 1380.720000 2950.390000 1381.820000 3146.960000 ;
+ RECT 1438.530000 2949.140000 1439.530000 3149.400000 ;
+ RECT 1335.720000 2950.390000 1336.820000 3146.960000 ;
+ RECT 1290.720000 2950.390000 1291.820000 3146.960000 ;
+ RECT 1245.720000 2950.390000 1246.820000 3146.960000 ;
+ RECT 1241.890000 2949.140000 1242.890000 3149.400000 ;
+ LAYER met3 ;
+ RECT 1425.720000 3141.680000 1426.820000 3142.160000 ;
+ RECT 1438.530000 3141.680000 1439.530000 3142.160000 ;
+ RECT 1438.530000 3130.800000 1439.530000 3131.280000 ;
+ RECT 1438.530000 3125.360000 1439.530000 3125.840000 ;
+ RECT 1438.530000 3136.240000 1439.530000 3136.720000 ;
+ RECT 1425.720000 3136.240000 1426.820000 3136.720000 ;
+ RECT 1425.720000 3130.800000 1426.820000 3131.280000 ;
+ RECT 1425.720000 3125.360000 1426.820000 3125.840000 ;
+ RECT 1425.720000 3114.480000 1426.820000 3114.960000 ;
+ RECT 1425.720000 3119.920000 1426.820000 3120.400000 ;
+ RECT 1438.530000 3114.480000 1439.530000 3114.960000 ;
+ RECT 1438.530000 3119.920000 1439.530000 3120.400000 ;
+ RECT 1425.720000 3103.600000 1426.820000 3104.080000 ;
+ RECT 1425.720000 3109.040000 1426.820000 3109.520000 ;
+ RECT 1438.530000 3103.600000 1439.530000 3104.080000 ;
+ RECT 1438.530000 3109.040000 1439.530000 3109.520000 ;
+ RECT 1380.720000 3125.360000 1381.820000 3125.840000 ;
+ RECT 1380.720000 3130.800000 1381.820000 3131.280000 ;
+ RECT 1380.720000 3136.240000 1381.820000 3136.720000 ;
+ RECT 1380.720000 3141.680000 1381.820000 3142.160000 ;
+ RECT 1380.720000 3109.040000 1381.820000 3109.520000 ;
+ RECT 1380.720000 3103.600000 1381.820000 3104.080000 ;
+ RECT 1380.720000 3114.480000 1381.820000 3114.960000 ;
+ RECT 1380.720000 3119.920000 1381.820000 3120.400000 ;
+ RECT 1438.530000 3092.720000 1439.530000 3093.200000 ;
+ RECT 1438.530000 3087.280000 1439.530000 3087.760000 ;
+ RECT 1438.530000 3098.160000 1439.530000 3098.640000 ;
+ RECT 1425.720000 3098.160000 1426.820000 3098.640000 ;
+ RECT 1425.720000 3092.720000 1426.820000 3093.200000 ;
+ RECT 1425.720000 3087.280000 1426.820000 3087.760000 ;
+ RECT 1425.720000 3076.400000 1426.820000 3076.880000 ;
+ RECT 1425.720000 3081.840000 1426.820000 3082.320000 ;
+ RECT 1438.530000 3076.400000 1439.530000 3076.880000 ;
+ RECT 1438.530000 3081.840000 1439.530000 3082.320000 ;
+ RECT 1438.530000 3065.520000 1439.530000 3066.000000 ;
+ RECT 1438.530000 3070.960000 1439.530000 3071.440000 ;
+ RECT 1425.720000 3070.960000 1426.820000 3071.440000 ;
+ RECT 1425.720000 3065.520000 1426.820000 3066.000000 ;
+ RECT 1425.720000 3054.640000 1426.820000 3055.120000 ;
+ RECT 1425.720000 3060.080000 1426.820000 3060.560000 ;
+ RECT 1438.530000 3054.640000 1439.530000 3055.120000 ;
+ RECT 1438.530000 3060.080000 1439.530000 3060.560000 ;
+ RECT 1380.720000 3076.400000 1381.820000 3076.880000 ;
+ RECT 1380.720000 3081.840000 1381.820000 3082.320000 ;
+ RECT 1380.720000 3087.280000 1381.820000 3087.760000 ;
+ RECT 1380.720000 3092.720000 1381.820000 3093.200000 ;
+ RECT 1380.720000 3098.160000 1381.820000 3098.640000 ;
+ RECT 1380.720000 3054.640000 1381.820000 3055.120000 ;
+ RECT 1380.720000 3060.080000 1381.820000 3060.560000 ;
+ RECT 1380.720000 3065.520000 1381.820000 3066.000000 ;
+ RECT 1380.720000 3070.960000 1381.820000 3071.440000 ;
+ RECT 1335.720000 3130.800000 1336.820000 3131.280000 ;
+ RECT 1335.720000 3125.360000 1336.820000 3125.840000 ;
+ RECT 1335.720000 3136.240000 1336.820000 3136.720000 ;
+ RECT 1335.720000 3141.680000 1336.820000 3142.160000 ;
+ RECT 1290.720000 3125.360000 1291.820000 3125.840000 ;
+ RECT 1290.720000 3130.800000 1291.820000 3131.280000 ;
+ RECT 1290.720000 3136.240000 1291.820000 3136.720000 ;
+ RECT 1290.720000 3141.680000 1291.820000 3142.160000 ;
+ RECT 1335.720000 3103.600000 1336.820000 3104.080000 ;
+ RECT 1335.720000 3109.040000 1336.820000 3109.520000 ;
+ RECT 1335.720000 3114.480000 1336.820000 3114.960000 ;
+ RECT 1335.720000 3119.920000 1336.820000 3120.400000 ;
+ RECT 1290.720000 3103.600000 1291.820000 3104.080000 ;
+ RECT 1290.720000 3109.040000 1291.820000 3109.520000 ;
+ RECT 1290.720000 3114.480000 1291.820000 3114.960000 ;
+ RECT 1290.720000 3119.920000 1291.820000 3120.400000 ;
+ RECT 1241.890000 3141.680000 1242.890000 3142.160000 ;
+ RECT 1245.555000 3141.680000 1246.820000 3142.160000 ;
+ RECT 1241.890000 3130.800000 1242.890000 3131.280000 ;
+ RECT 1245.555000 3130.800000 1246.820000 3131.280000 ;
+ RECT 1241.890000 3136.240000 1242.890000 3136.720000 ;
+ RECT 1245.555000 3136.240000 1246.820000 3136.720000 ;
+ RECT 1241.890000 3125.360000 1242.890000 3125.840000 ;
+ RECT 1245.555000 3125.360000 1246.820000 3125.840000 ;
+ RECT 1241.890000 3119.920000 1242.890000 3120.400000 ;
+ RECT 1245.555000 3119.920000 1246.820000 3120.400000 ;
+ RECT 1241.890000 3114.480000 1242.890000 3114.960000 ;
+ RECT 1245.555000 3114.480000 1246.820000 3114.960000 ;
+ RECT 1241.890000 3109.040000 1242.890000 3109.520000 ;
+ RECT 1245.555000 3109.040000 1246.820000 3109.520000 ;
+ RECT 1241.890000 3103.600000 1242.890000 3104.080000 ;
+ RECT 1245.555000 3103.600000 1246.820000 3104.080000 ;
+ RECT 1335.720000 3076.400000 1336.820000 3076.880000 ;
+ RECT 1335.720000 3081.840000 1336.820000 3082.320000 ;
+ RECT 1335.720000 3087.280000 1336.820000 3087.760000 ;
+ RECT 1335.720000 3092.720000 1336.820000 3093.200000 ;
+ RECT 1335.720000 3098.160000 1336.820000 3098.640000 ;
+ RECT 1290.720000 3076.400000 1291.820000 3076.880000 ;
+ RECT 1290.720000 3081.840000 1291.820000 3082.320000 ;
+ RECT 1290.720000 3087.280000 1291.820000 3087.760000 ;
+ RECT 1290.720000 3092.720000 1291.820000 3093.200000 ;
+ RECT 1290.720000 3098.160000 1291.820000 3098.640000 ;
+ RECT 1335.720000 3054.640000 1336.820000 3055.120000 ;
+ RECT 1335.720000 3060.080000 1336.820000 3060.560000 ;
+ RECT 1335.720000 3065.520000 1336.820000 3066.000000 ;
+ RECT 1335.720000 3070.960000 1336.820000 3071.440000 ;
+ RECT 1290.720000 3054.640000 1291.820000 3055.120000 ;
+ RECT 1290.720000 3060.080000 1291.820000 3060.560000 ;
+ RECT 1290.720000 3065.520000 1291.820000 3066.000000 ;
+ RECT 1290.720000 3070.960000 1291.820000 3071.440000 ;
+ RECT 1241.890000 3098.160000 1242.890000 3098.640000 ;
+ RECT 1245.555000 3098.160000 1246.820000 3098.640000 ;
+ RECT 1241.890000 3087.280000 1242.890000 3087.760000 ;
+ RECT 1245.555000 3087.280000 1246.820000 3087.760000 ;
+ RECT 1241.890000 3092.720000 1242.890000 3093.200000 ;
+ RECT 1245.555000 3092.720000 1246.820000 3093.200000 ;
+ RECT 1241.890000 3081.840000 1242.890000 3082.320000 ;
+ RECT 1245.555000 3081.840000 1246.820000 3082.320000 ;
+ RECT 1241.890000 3076.400000 1242.890000 3076.880000 ;
+ RECT 1245.555000 3076.400000 1246.820000 3076.880000 ;
+ RECT 1241.890000 3070.960000 1242.890000 3071.440000 ;
+ RECT 1245.555000 3070.960000 1246.820000 3071.440000 ;
+ RECT 1241.890000 3065.520000 1242.890000 3066.000000 ;
+ RECT 1245.555000 3065.520000 1246.820000 3066.000000 ;
+ RECT 1241.890000 3060.080000 1242.890000 3060.560000 ;
+ RECT 1245.555000 3060.080000 1246.820000 3060.560000 ;
+ RECT 1241.890000 3054.640000 1242.890000 3055.120000 ;
+ RECT 1245.555000 3054.640000 1246.820000 3055.120000 ;
+ RECT 1425.720000 3038.320000 1426.820000 3038.800000 ;
+ RECT 1425.720000 3043.760000 1426.820000 3044.240000 ;
+ RECT 1438.530000 3038.320000 1439.530000 3038.800000 ;
+ RECT 1438.530000 3043.760000 1439.530000 3044.240000 ;
+ RECT 1438.530000 3027.440000 1439.530000 3027.920000 ;
+ RECT 1438.530000 3032.880000 1439.530000 3033.360000 ;
+ RECT 1425.720000 3032.880000 1426.820000 3033.360000 ;
+ RECT 1425.720000 3027.440000 1426.820000 3027.920000 ;
+ RECT 1425.720000 3016.560000 1426.820000 3017.040000 ;
+ RECT 1425.720000 3022.000000 1426.820000 3022.480000 ;
+ RECT 1438.530000 3016.560000 1439.530000 3017.040000 ;
+ RECT 1438.530000 3022.000000 1439.530000 3022.480000 ;
+ RECT 1438.530000 3005.680000 1439.530000 3006.160000 ;
+ RECT 1438.530000 3000.240000 1439.530000 3000.720000 ;
+ RECT 1438.530000 3011.120000 1439.530000 3011.600000 ;
+ RECT 1425.720000 3011.120000 1426.820000 3011.600000 ;
+ RECT 1425.720000 3005.680000 1426.820000 3006.160000 ;
+ RECT 1425.720000 3000.240000 1426.820000 3000.720000 ;
+ RECT 1380.720000 3027.440000 1381.820000 3027.920000 ;
+ RECT 1380.720000 3032.880000 1381.820000 3033.360000 ;
+ RECT 1380.720000 3038.320000 1381.820000 3038.800000 ;
+ RECT 1380.720000 3043.760000 1381.820000 3044.240000 ;
+ RECT 1380.720000 3000.240000 1381.820000 3000.720000 ;
+ RECT 1380.720000 3005.680000 1381.820000 3006.160000 ;
+ RECT 1380.720000 3011.120000 1381.820000 3011.600000 ;
+ RECT 1380.720000 3016.560000 1381.820000 3017.040000 ;
+ RECT 1380.720000 3022.000000 1381.820000 3022.480000 ;
+ RECT 1425.720000 2989.360000 1426.820000 2989.840000 ;
+ RECT 1425.720000 2994.800000 1426.820000 2995.280000 ;
+ RECT 1438.530000 2989.360000 1439.530000 2989.840000 ;
+ RECT 1438.530000 2994.800000 1439.530000 2995.280000 ;
+ RECT 1425.720000 2978.480000 1426.820000 2978.960000 ;
+ RECT 1425.720000 2983.920000 1426.820000 2984.400000 ;
+ RECT 1438.530000 2978.480000 1439.530000 2978.960000 ;
+ RECT 1438.530000 2983.920000 1439.530000 2984.400000 ;
+ RECT 1438.530000 2967.600000 1439.530000 2968.080000 ;
+ RECT 1438.530000 2962.160000 1439.530000 2962.640000 ;
+ RECT 1438.530000 2973.040000 1439.530000 2973.520000 ;
+ RECT 1425.720000 2973.040000 1426.820000 2973.520000 ;
+ RECT 1425.720000 2967.600000 1426.820000 2968.080000 ;
+ RECT 1425.720000 2962.160000 1426.820000 2962.640000 ;
+ RECT 1425.720000 2956.720000 1426.820000 2957.200000 ;
+ RECT 1438.530000 2956.720000 1439.530000 2957.200000 ;
+ RECT 1380.720000 2978.480000 1381.820000 2978.960000 ;
+ RECT 1380.720000 2983.920000 1381.820000 2984.400000 ;
+ RECT 1380.720000 2989.360000 1381.820000 2989.840000 ;
+ RECT 1380.720000 2994.800000 1381.820000 2995.280000 ;
+ RECT 1380.720000 2956.720000 1381.820000 2957.200000 ;
+ RECT 1380.720000 2962.160000 1381.820000 2962.640000 ;
+ RECT 1380.720000 2967.600000 1381.820000 2968.080000 ;
+ RECT 1380.720000 2973.040000 1381.820000 2973.520000 ;
+ RECT 1335.720000 3027.440000 1336.820000 3027.920000 ;
+ RECT 1335.720000 3032.880000 1336.820000 3033.360000 ;
+ RECT 1335.720000 3038.320000 1336.820000 3038.800000 ;
+ RECT 1335.720000 3043.760000 1336.820000 3044.240000 ;
+ RECT 1290.720000 3027.440000 1291.820000 3027.920000 ;
+ RECT 1290.720000 3032.880000 1291.820000 3033.360000 ;
+ RECT 1290.720000 3038.320000 1291.820000 3038.800000 ;
+ RECT 1290.720000 3043.760000 1291.820000 3044.240000 ;
+ RECT 1335.720000 3000.240000 1336.820000 3000.720000 ;
+ RECT 1335.720000 3005.680000 1336.820000 3006.160000 ;
+ RECT 1335.720000 3011.120000 1336.820000 3011.600000 ;
+ RECT 1335.720000 3016.560000 1336.820000 3017.040000 ;
+ RECT 1335.720000 3022.000000 1336.820000 3022.480000 ;
+ RECT 1290.720000 3000.240000 1291.820000 3000.720000 ;
+ RECT 1290.720000 3005.680000 1291.820000 3006.160000 ;
+ RECT 1290.720000 3011.120000 1291.820000 3011.600000 ;
+ RECT 1290.720000 3016.560000 1291.820000 3017.040000 ;
+ RECT 1290.720000 3022.000000 1291.820000 3022.480000 ;
+ RECT 1241.890000 3043.760000 1242.890000 3044.240000 ;
+ RECT 1245.555000 3043.760000 1246.820000 3044.240000 ;
+ RECT 1241.890000 3038.320000 1242.890000 3038.800000 ;
+ RECT 1245.555000 3038.320000 1246.820000 3038.800000 ;
+ RECT 1241.890000 3032.880000 1242.890000 3033.360000 ;
+ RECT 1245.555000 3032.880000 1246.820000 3033.360000 ;
+ RECT 1241.890000 3027.440000 1242.890000 3027.920000 ;
+ RECT 1245.555000 3027.440000 1246.820000 3027.920000 ;
+ RECT 1241.890000 3022.000000 1242.890000 3022.480000 ;
+ RECT 1245.555000 3022.000000 1246.820000 3022.480000 ;
+ RECT 1241.890000 3016.560000 1242.890000 3017.040000 ;
+ RECT 1245.555000 3016.560000 1246.820000 3017.040000 ;
+ RECT 1241.890000 3005.680000 1242.890000 3006.160000 ;
+ RECT 1245.555000 3005.680000 1246.820000 3006.160000 ;
+ RECT 1241.890000 3011.120000 1242.890000 3011.600000 ;
+ RECT 1245.555000 3011.120000 1246.820000 3011.600000 ;
+ RECT 1241.890000 3000.240000 1242.890000 3000.720000 ;
+ RECT 1245.555000 3000.240000 1246.820000 3000.720000 ;
+ RECT 1335.720000 2978.480000 1336.820000 2978.960000 ;
+ RECT 1335.720000 2983.920000 1336.820000 2984.400000 ;
+ RECT 1335.720000 2989.360000 1336.820000 2989.840000 ;
+ RECT 1335.720000 2994.800000 1336.820000 2995.280000 ;
+ RECT 1290.720000 2978.480000 1291.820000 2978.960000 ;
+ RECT 1290.720000 2983.920000 1291.820000 2984.400000 ;
+ RECT 1290.720000 2989.360000 1291.820000 2989.840000 ;
+ RECT 1290.720000 2994.800000 1291.820000 2995.280000 ;
+ RECT 1335.720000 2956.720000 1336.820000 2957.200000 ;
+ RECT 1335.720000 2962.160000 1336.820000 2962.640000 ;
+ RECT 1335.720000 2967.600000 1336.820000 2968.080000 ;
+ RECT 1335.720000 2973.040000 1336.820000 2973.520000 ;
+ RECT 1290.720000 2956.720000 1291.820000 2957.200000 ;
+ RECT 1290.720000 2962.160000 1291.820000 2962.640000 ;
+ RECT 1290.720000 2967.600000 1291.820000 2968.080000 ;
+ RECT 1290.720000 2973.040000 1291.820000 2973.520000 ;
+ RECT 1241.890000 2994.800000 1242.890000 2995.280000 ;
+ RECT 1245.555000 2994.800000 1246.820000 2995.280000 ;
+ RECT 1241.890000 2989.360000 1242.890000 2989.840000 ;
+ RECT 1245.555000 2989.360000 1246.820000 2989.840000 ;
+ RECT 1241.890000 2983.920000 1242.890000 2984.400000 ;
+ RECT 1245.555000 2983.920000 1246.820000 2984.400000 ;
+ RECT 1241.890000 2978.480000 1242.890000 2978.960000 ;
+ RECT 1245.555000 2978.480000 1246.820000 2978.960000 ;
+ RECT 1241.890000 2973.040000 1242.890000 2973.520000 ;
+ RECT 1245.555000 2973.040000 1246.820000 2973.520000 ;
+ RECT 1241.890000 2962.160000 1242.890000 2962.640000 ;
+ RECT 1245.555000 2962.160000 1246.820000 2962.640000 ;
+ RECT 1241.890000 2967.600000 1242.890000 2968.080000 ;
+ RECT 1245.555000 2967.600000 1246.820000 2968.080000 ;
+ RECT 1241.890000 2956.720000 1242.890000 2957.200000 ;
+ RECT 1245.555000 2956.720000 1246.820000 2957.200000 ;
+ RECT 1380.720000 3049.200000 1381.820000 3049.680000 ;
+ RECT 1425.720000 3049.200000 1426.820000 3049.680000 ;
+ RECT 1438.530000 3049.200000 1439.530000 3049.680000 ;
+ RECT 1290.720000 3049.200000 1291.820000 3049.680000 ;
+ RECT 1335.720000 3049.200000 1336.820000 3049.680000 ;
+ RECT 1241.890000 3049.200000 1242.890000 3049.680000 ;
+ RECT 1245.555000 3049.200000 1246.820000 3049.680000 ;
+ RECT 1240.660000 3145.960000 1440.760000 3146.960000 ;
+ RECT 1240.660000 2950.390000 1440.760000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 2949.140000 1242.890000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 3148.400000 1242.890000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 2949.140000 1439.530000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 3148.400000 1439.530000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2950.390000 1241.660000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2950.390000 1440.760000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 3145.960000 1241.660000 3146.960000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 3145.960000 1440.760000 3146.960000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 2941.420000 1246.820000 2941.900000 ;
+ RECT 1245.555000 2930.540000 1246.820000 2931.020000 ;
+ RECT 1245.555000 2935.980000 1246.820000 2936.460000 ;
+ RECT 1245.555000 2925.100000 1246.820000 2925.580000 ;
+ RECT 1245.555000 2919.660000 1246.820000 2920.140000 ;
+ RECT 1245.555000 2914.220000 1246.820000 2914.700000 ;
+ RECT 1245.555000 2908.780000 1246.820000 2909.260000 ;
+ RECT 1245.555000 2903.340000 1246.820000 2903.820000 ;
+ RECT 1245.555000 2897.900000 1246.820000 2898.380000 ;
+ RECT 1245.555000 2887.020000 1246.820000 2887.500000 ;
+ RECT 1245.555000 2892.460000 1246.820000 2892.940000 ;
+ RECT 1245.555000 2881.580000 1246.820000 2882.060000 ;
+ RECT 1245.555000 2876.140000 1246.820000 2876.620000 ;
+ RECT 1245.555000 2870.700000 1246.820000 2871.180000 ;
+ RECT 1245.555000 2865.260000 1246.820000 2865.740000 ;
+ RECT 1245.555000 2859.820000 1246.820000 2860.300000 ;
+ RECT 1245.555000 2854.380000 1246.820000 2854.860000 ;
+ RECT 1245.555000 2843.500000 1246.820000 2843.980000 ;
+ RECT 1245.555000 2838.060000 1246.820000 2838.540000 ;
+ RECT 1245.555000 2832.620000 1246.820000 2833.100000 ;
+ RECT 1245.555000 2827.180000 1246.820000 2827.660000 ;
+ RECT 1245.555000 2821.740000 1246.820000 2822.220000 ;
+ RECT 1245.555000 2816.300000 1246.820000 2816.780000 ;
+ RECT 1245.555000 2805.420000 1246.820000 2805.900000 ;
+ RECT 1245.555000 2810.860000 1246.820000 2811.340000 ;
+ RECT 1245.555000 2799.980000 1246.820000 2800.460000 ;
+ RECT 1245.555000 2794.540000 1246.820000 2795.020000 ;
+ RECT 1245.555000 2789.100000 1246.820000 2789.580000 ;
+ RECT 1245.555000 2783.660000 1246.820000 2784.140000 ;
+ RECT 1245.555000 2778.220000 1246.820000 2778.700000 ;
+ RECT 1245.555000 2772.780000 1246.820000 2773.260000 ;
+ RECT 1245.555000 2761.900000 1246.820000 2762.380000 ;
+ RECT 1245.555000 2767.340000 1246.820000 2767.820000 ;
+ RECT 1245.555000 2756.460000 1246.820000 2756.940000 ;
+ RECT 1245.555000 2848.940000 1246.820000 2849.420000 ;
+ RECT 1425.720000 2750.130000 1426.820000 2946.700000 ;
+ RECT 1380.720000 2750.130000 1381.820000 2946.700000 ;
+ RECT 1438.530000 2748.880000 1439.530000 2949.140000 ;
+ RECT 1335.720000 2750.130000 1336.820000 2946.700000 ;
+ RECT 1290.720000 2750.130000 1291.820000 2946.700000 ;
+ RECT 1245.720000 2750.130000 1246.820000 2946.700000 ;
+ RECT 1241.890000 2748.880000 1242.890000 2949.140000 ;
+ LAYER met3 ;
+ RECT 1425.720000 2941.420000 1426.820000 2941.900000 ;
+ RECT 1438.530000 2941.420000 1439.530000 2941.900000 ;
+ RECT 1438.530000 2930.540000 1439.530000 2931.020000 ;
+ RECT 1438.530000 2925.100000 1439.530000 2925.580000 ;
+ RECT 1438.530000 2935.980000 1439.530000 2936.460000 ;
+ RECT 1425.720000 2935.980000 1426.820000 2936.460000 ;
+ RECT 1425.720000 2930.540000 1426.820000 2931.020000 ;
+ RECT 1425.720000 2925.100000 1426.820000 2925.580000 ;
+ RECT 1425.720000 2914.220000 1426.820000 2914.700000 ;
+ RECT 1425.720000 2919.660000 1426.820000 2920.140000 ;
+ RECT 1438.530000 2914.220000 1439.530000 2914.700000 ;
+ RECT 1438.530000 2919.660000 1439.530000 2920.140000 ;
+ RECT 1425.720000 2903.340000 1426.820000 2903.820000 ;
+ RECT 1425.720000 2908.780000 1426.820000 2909.260000 ;
+ RECT 1438.530000 2903.340000 1439.530000 2903.820000 ;
+ RECT 1438.530000 2908.780000 1439.530000 2909.260000 ;
+ RECT 1380.720000 2925.100000 1381.820000 2925.580000 ;
+ RECT 1380.720000 2930.540000 1381.820000 2931.020000 ;
+ RECT 1380.720000 2935.980000 1381.820000 2936.460000 ;
+ RECT 1380.720000 2941.420000 1381.820000 2941.900000 ;
+ RECT 1380.720000 2908.780000 1381.820000 2909.260000 ;
+ RECT 1380.720000 2903.340000 1381.820000 2903.820000 ;
+ RECT 1380.720000 2914.220000 1381.820000 2914.700000 ;
+ RECT 1380.720000 2919.660000 1381.820000 2920.140000 ;
+ RECT 1438.530000 2892.460000 1439.530000 2892.940000 ;
+ RECT 1438.530000 2887.020000 1439.530000 2887.500000 ;
+ RECT 1438.530000 2897.900000 1439.530000 2898.380000 ;
+ RECT 1425.720000 2897.900000 1426.820000 2898.380000 ;
+ RECT 1425.720000 2892.460000 1426.820000 2892.940000 ;
+ RECT 1425.720000 2887.020000 1426.820000 2887.500000 ;
+ RECT 1425.720000 2876.140000 1426.820000 2876.620000 ;
+ RECT 1425.720000 2881.580000 1426.820000 2882.060000 ;
+ RECT 1438.530000 2876.140000 1439.530000 2876.620000 ;
+ RECT 1438.530000 2881.580000 1439.530000 2882.060000 ;
+ RECT 1438.530000 2865.260000 1439.530000 2865.740000 ;
+ RECT 1438.530000 2870.700000 1439.530000 2871.180000 ;
+ RECT 1425.720000 2870.700000 1426.820000 2871.180000 ;
+ RECT 1425.720000 2865.260000 1426.820000 2865.740000 ;
+ RECT 1425.720000 2854.380000 1426.820000 2854.860000 ;
+ RECT 1425.720000 2859.820000 1426.820000 2860.300000 ;
+ RECT 1438.530000 2854.380000 1439.530000 2854.860000 ;
+ RECT 1438.530000 2859.820000 1439.530000 2860.300000 ;
+ RECT 1380.720000 2876.140000 1381.820000 2876.620000 ;
+ RECT 1380.720000 2881.580000 1381.820000 2882.060000 ;
+ RECT 1380.720000 2887.020000 1381.820000 2887.500000 ;
+ RECT 1380.720000 2892.460000 1381.820000 2892.940000 ;
+ RECT 1380.720000 2897.900000 1381.820000 2898.380000 ;
+ RECT 1380.720000 2854.380000 1381.820000 2854.860000 ;
+ RECT 1380.720000 2859.820000 1381.820000 2860.300000 ;
+ RECT 1380.720000 2865.260000 1381.820000 2865.740000 ;
+ RECT 1380.720000 2870.700000 1381.820000 2871.180000 ;
+ RECT 1335.720000 2930.540000 1336.820000 2931.020000 ;
+ RECT 1335.720000 2925.100000 1336.820000 2925.580000 ;
+ RECT 1335.720000 2935.980000 1336.820000 2936.460000 ;
+ RECT 1335.720000 2941.420000 1336.820000 2941.900000 ;
+ RECT 1290.720000 2925.100000 1291.820000 2925.580000 ;
+ RECT 1290.720000 2930.540000 1291.820000 2931.020000 ;
+ RECT 1290.720000 2935.980000 1291.820000 2936.460000 ;
+ RECT 1290.720000 2941.420000 1291.820000 2941.900000 ;
+ RECT 1335.720000 2903.340000 1336.820000 2903.820000 ;
+ RECT 1335.720000 2908.780000 1336.820000 2909.260000 ;
+ RECT 1335.720000 2914.220000 1336.820000 2914.700000 ;
+ RECT 1335.720000 2919.660000 1336.820000 2920.140000 ;
+ RECT 1290.720000 2903.340000 1291.820000 2903.820000 ;
+ RECT 1290.720000 2908.780000 1291.820000 2909.260000 ;
+ RECT 1290.720000 2914.220000 1291.820000 2914.700000 ;
+ RECT 1290.720000 2919.660000 1291.820000 2920.140000 ;
+ RECT 1241.890000 2941.420000 1242.890000 2941.900000 ;
+ RECT 1245.555000 2941.420000 1246.820000 2941.900000 ;
+ RECT 1241.890000 2930.540000 1242.890000 2931.020000 ;
+ RECT 1245.555000 2930.540000 1246.820000 2931.020000 ;
+ RECT 1241.890000 2935.980000 1242.890000 2936.460000 ;
+ RECT 1245.555000 2935.980000 1246.820000 2936.460000 ;
+ RECT 1241.890000 2925.100000 1242.890000 2925.580000 ;
+ RECT 1245.555000 2925.100000 1246.820000 2925.580000 ;
+ RECT 1241.890000 2919.660000 1242.890000 2920.140000 ;
+ RECT 1245.555000 2919.660000 1246.820000 2920.140000 ;
+ RECT 1241.890000 2914.220000 1242.890000 2914.700000 ;
+ RECT 1245.555000 2914.220000 1246.820000 2914.700000 ;
+ RECT 1241.890000 2908.780000 1242.890000 2909.260000 ;
+ RECT 1245.555000 2908.780000 1246.820000 2909.260000 ;
+ RECT 1241.890000 2903.340000 1242.890000 2903.820000 ;
+ RECT 1245.555000 2903.340000 1246.820000 2903.820000 ;
+ RECT 1335.720000 2876.140000 1336.820000 2876.620000 ;
+ RECT 1335.720000 2881.580000 1336.820000 2882.060000 ;
+ RECT 1335.720000 2887.020000 1336.820000 2887.500000 ;
+ RECT 1335.720000 2892.460000 1336.820000 2892.940000 ;
+ RECT 1335.720000 2897.900000 1336.820000 2898.380000 ;
+ RECT 1290.720000 2876.140000 1291.820000 2876.620000 ;
+ RECT 1290.720000 2881.580000 1291.820000 2882.060000 ;
+ RECT 1290.720000 2887.020000 1291.820000 2887.500000 ;
+ RECT 1290.720000 2892.460000 1291.820000 2892.940000 ;
+ RECT 1290.720000 2897.900000 1291.820000 2898.380000 ;
+ RECT 1335.720000 2854.380000 1336.820000 2854.860000 ;
+ RECT 1335.720000 2859.820000 1336.820000 2860.300000 ;
+ RECT 1335.720000 2865.260000 1336.820000 2865.740000 ;
+ RECT 1335.720000 2870.700000 1336.820000 2871.180000 ;
+ RECT 1290.720000 2854.380000 1291.820000 2854.860000 ;
+ RECT 1290.720000 2859.820000 1291.820000 2860.300000 ;
+ RECT 1290.720000 2865.260000 1291.820000 2865.740000 ;
+ RECT 1290.720000 2870.700000 1291.820000 2871.180000 ;
+ RECT 1241.890000 2897.900000 1242.890000 2898.380000 ;
+ RECT 1245.555000 2897.900000 1246.820000 2898.380000 ;
+ RECT 1241.890000 2887.020000 1242.890000 2887.500000 ;
+ RECT 1245.555000 2887.020000 1246.820000 2887.500000 ;
+ RECT 1241.890000 2892.460000 1242.890000 2892.940000 ;
+ RECT 1245.555000 2892.460000 1246.820000 2892.940000 ;
+ RECT 1241.890000 2881.580000 1242.890000 2882.060000 ;
+ RECT 1245.555000 2881.580000 1246.820000 2882.060000 ;
+ RECT 1241.890000 2876.140000 1242.890000 2876.620000 ;
+ RECT 1245.555000 2876.140000 1246.820000 2876.620000 ;
+ RECT 1241.890000 2870.700000 1242.890000 2871.180000 ;
+ RECT 1245.555000 2870.700000 1246.820000 2871.180000 ;
+ RECT 1241.890000 2865.260000 1242.890000 2865.740000 ;
+ RECT 1245.555000 2865.260000 1246.820000 2865.740000 ;
+ RECT 1241.890000 2859.820000 1242.890000 2860.300000 ;
+ RECT 1245.555000 2859.820000 1246.820000 2860.300000 ;
+ RECT 1241.890000 2854.380000 1242.890000 2854.860000 ;
+ RECT 1245.555000 2854.380000 1246.820000 2854.860000 ;
+ RECT 1425.720000 2838.060000 1426.820000 2838.540000 ;
+ RECT 1425.720000 2843.500000 1426.820000 2843.980000 ;
+ RECT 1438.530000 2838.060000 1439.530000 2838.540000 ;
+ RECT 1438.530000 2843.500000 1439.530000 2843.980000 ;
+ RECT 1438.530000 2827.180000 1439.530000 2827.660000 ;
+ RECT 1438.530000 2832.620000 1439.530000 2833.100000 ;
+ RECT 1425.720000 2832.620000 1426.820000 2833.100000 ;
+ RECT 1425.720000 2827.180000 1426.820000 2827.660000 ;
+ RECT 1425.720000 2816.300000 1426.820000 2816.780000 ;
+ RECT 1425.720000 2821.740000 1426.820000 2822.220000 ;
+ RECT 1438.530000 2816.300000 1439.530000 2816.780000 ;
+ RECT 1438.530000 2821.740000 1439.530000 2822.220000 ;
+ RECT 1438.530000 2805.420000 1439.530000 2805.900000 ;
+ RECT 1438.530000 2799.980000 1439.530000 2800.460000 ;
+ RECT 1438.530000 2810.860000 1439.530000 2811.340000 ;
+ RECT 1425.720000 2810.860000 1426.820000 2811.340000 ;
+ RECT 1425.720000 2805.420000 1426.820000 2805.900000 ;
+ RECT 1425.720000 2799.980000 1426.820000 2800.460000 ;
+ RECT 1380.720000 2827.180000 1381.820000 2827.660000 ;
+ RECT 1380.720000 2832.620000 1381.820000 2833.100000 ;
+ RECT 1380.720000 2838.060000 1381.820000 2838.540000 ;
+ RECT 1380.720000 2843.500000 1381.820000 2843.980000 ;
+ RECT 1380.720000 2799.980000 1381.820000 2800.460000 ;
+ RECT 1380.720000 2805.420000 1381.820000 2805.900000 ;
+ RECT 1380.720000 2810.860000 1381.820000 2811.340000 ;
+ RECT 1380.720000 2816.300000 1381.820000 2816.780000 ;
+ RECT 1380.720000 2821.740000 1381.820000 2822.220000 ;
+ RECT 1425.720000 2789.100000 1426.820000 2789.580000 ;
+ RECT 1425.720000 2794.540000 1426.820000 2795.020000 ;
+ RECT 1438.530000 2789.100000 1439.530000 2789.580000 ;
+ RECT 1438.530000 2794.540000 1439.530000 2795.020000 ;
+ RECT 1425.720000 2778.220000 1426.820000 2778.700000 ;
+ RECT 1425.720000 2783.660000 1426.820000 2784.140000 ;
+ RECT 1438.530000 2778.220000 1439.530000 2778.700000 ;
+ RECT 1438.530000 2783.660000 1439.530000 2784.140000 ;
+ RECT 1438.530000 2767.340000 1439.530000 2767.820000 ;
+ RECT 1438.530000 2761.900000 1439.530000 2762.380000 ;
+ RECT 1438.530000 2772.780000 1439.530000 2773.260000 ;
+ RECT 1425.720000 2772.780000 1426.820000 2773.260000 ;
+ RECT 1425.720000 2767.340000 1426.820000 2767.820000 ;
+ RECT 1425.720000 2761.900000 1426.820000 2762.380000 ;
+ RECT 1425.720000 2756.460000 1426.820000 2756.940000 ;
+ RECT 1438.530000 2756.460000 1439.530000 2756.940000 ;
+ RECT 1380.720000 2778.220000 1381.820000 2778.700000 ;
+ RECT 1380.720000 2783.660000 1381.820000 2784.140000 ;
+ RECT 1380.720000 2789.100000 1381.820000 2789.580000 ;
+ RECT 1380.720000 2794.540000 1381.820000 2795.020000 ;
+ RECT 1380.720000 2756.460000 1381.820000 2756.940000 ;
+ RECT 1380.720000 2761.900000 1381.820000 2762.380000 ;
+ RECT 1380.720000 2767.340000 1381.820000 2767.820000 ;
+ RECT 1380.720000 2772.780000 1381.820000 2773.260000 ;
+ RECT 1335.720000 2827.180000 1336.820000 2827.660000 ;
+ RECT 1335.720000 2832.620000 1336.820000 2833.100000 ;
+ RECT 1335.720000 2838.060000 1336.820000 2838.540000 ;
+ RECT 1335.720000 2843.500000 1336.820000 2843.980000 ;
+ RECT 1290.720000 2827.180000 1291.820000 2827.660000 ;
+ RECT 1290.720000 2832.620000 1291.820000 2833.100000 ;
+ RECT 1290.720000 2838.060000 1291.820000 2838.540000 ;
+ RECT 1290.720000 2843.500000 1291.820000 2843.980000 ;
+ RECT 1335.720000 2799.980000 1336.820000 2800.460000 ;
+ RECT 1335.720000 2805.420000 1336.820000 2805.900000 ;
+ RECT 1335.720000 2810.860000 1336.820000 2811.340000 ;
+ RECT 1335.720000 2816.300000 1336.820000 2816.780000 ;
+ RECT 1335.720000 2821.740000 1336.820000 2822.220000 ;
+ RECT 1290.720000 2799.980000 1291.820000 2800.460000 ;
+ RECT 1290.720000 2805.420000 1291.820000 2805.900000 ;
+ RECT 1290.720000 2810.860000 1291.820000 2811.340000 ;
+ RECT 1290.720000 2816.300000 1291.820000 2816.780000 ;
+ RECT 1290.720000 2821.740000 1291.820000 2822.220000 ;
+ RECT 1241.890000 2843.500000 1242.890000 2843.980000 ;
+ RECT 1245.555000 2843.500000 1246.820000 2843.980000 ;
+ RECT 1241.890000 2838.060000 1242.890000 2838.540000 ;
+ RECT 1245.555000 2838.060000 1246.820000 2838.540000 ;
+ RECT 1241.890000 2832.620000 1242.890000 2833.100000 ;
+ RECT 1245.555000 2832.620000 1246.820000 2833.100000 ;
+ RECT 1241.890000 2827.180000 1242.890000 2827.660000 ;
+ RECT 1245.555000 2827.180000 1246.820000 2827.660000 ;
+ RECT 1241.890000 2821.740000 1242.890000 2822.220000 ;
+ RECT 1245.555000 2821.740000 1246.820000 2822.220000 ;
+ RECT 1241.890000 2816.300000 1242.890000 2816.780000 ;
+ RECT 1245.555000 2816.300000 1246.820000 2816.780000 ;
+ RECT 1241.890000 2805.420000 1242.890000 2805.900000 ;
+ RECT 1245.555000 2805.420000 1246.820000 2805.900000 ;
+ RECT 1241.890000 2810.860000 1242.890000 2811.340000 ;
+ RECT 1245.555000 2810.860000 1246.820000 2811.340000 ;
+ RECT 1241.890000 2799.980000 1242.890000 2800.460000 ;
+ RECT 1245.555000 2799.980000 1246.820000 2800.460000 ;
+ RECT 1335.720000 2778.220000 1336.820000 2778.700000 ;
+ RECT 1335.720000 2783.660000 1336.820000 2784.140000 ;
+ RECT 1335.720000 2789.100000 1336.820000 2789.580000 ;
+ RECT 1335.720000 2794.540000 1336.820000 2795.020000 ;
+ RECT 1290.720000 2778.220000 1291.820000 2778.700000 ;
+ RECT 1290.720000 2783.660000 1291.820000 2784.140000 ;
+ RECT 1290.720000 2789.100000 1291.820000 2789.580000 ;
+ RECT 1290.720000 2794.540000 1291.820000 2795.020000 ;
+ RECT 1335.720000 2756.460000 1336.820000 2756.940000 ;
+ RECT 1335.720000 2761.900000 1336.820000 2762.380000 ;
+ RECT 1335.720000 2767.340000 1336.820000 2767.820000 ;
+ RECT 1335.720000 2772.780000 1336.820000 2773.260000 ;
+ RECT 1290.720000 2756.460000 1291.820000 2756.940000 ;
+ RECT 1290.720000 2761.900000 1291.820000 2762.380000 ;
+ RECT 1290.720000 2767.340000 1291.820000 2767.820000 ;
+ RECT 1290.720000 2772.780000 1291.820000 2773.260000 ;
+ RECT 1241.890000 2794.540000 1242.890000 2795.020000 ;
+ RECT 1245.555000 2794.540000 1246.820000 2795.020000 ;
+ RECT 1241.890000 2789.100000 1242.890000 2789.580000 ;
+ RECT 1245.555000 2789.100000 1246.820000 2789.580000 ;
+ RECT 1241.890000 2783.660000 1242.890000 2784.140000 ;
+ RECT 1245.555000 2783.660000 1246.820000 2784.140000 ;
+ RECT 1241.890000 2778.220000 1242.890000 2778.700000 ;
+ RECT 1245.555000 2778.220000 1246.820000 2778.700000 ;
+ RECT 1241.890000 2772.780000 1242.890000 2773.260000 ;
+ RECT 1245.555000 2772.780000 1246.820000 2773.260000 ;
+ RECT 1241.890000 2761.900000 1242.890000 2762.380000 ;
+ RECT 1245.555000 2761.900000 1246.820000 2762.380000 ;
+ RECT 1241.890000 2767.340000 1242.890000 2767.820000 ;
+ RECT 1245.555000 2767.340000 1246.820000 2767.820000 ;
+ RECT 1241.890000 2756.460000 1242.890000 2756.940000 ;
+ RECT 1245.555000 2756.460000 1246.820000 2756.940000 ;
+ RECT 1380.720000 2848.940000 1381.820000 2849.420000 ;
+ RECT 1425.720000 2848.940000 1426.820000 2849.420000 ;
+ RECT 1438.530000 2848.940000 1439.530000 2849.420000 ;
+ RECT 1290.720000 2848.940000 1291.820000 2849.420000 ;
+ RECT 1335.720000 2848.940000 1336.820000 2849.420000 ;
+ RECT 1241.890000 2848.940000 1242.890000 2849.420000 ;
+ RECT 1245.555000 2848.940000 1246.820000 2849.420000 ;
+ RECT 1240.660000 2945.700000 1440.760000 2946.700000 ;
+ RECT 1240.660000 2750.130000 1440.760000 2751.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 2748.880000 1242.890000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 2948.140000 1242.890000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 2748.880000 1439.530000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 2948.140000 1439.530000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2750.130000 1241.660000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2750.130000 1440.760000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2945.700000 1241.660000 2946.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2945.700000 1440.760000 2946.700000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 2741.160000 1246.820000 2741.640000 ;
+ RECT 1245.555000 2730.280000 1246.820000 2730.760000 ;
+ RECT 1245.555000 2735.720000 1246.820000 2736.200000 ;
+ RECT 1245.555000 2724.840000 1246.820000 2725.320000 ;
+ RECT 1245.555000 2719.400000 1246.820000 2719.880000 ;
+ RECT 1245.555000 2713.960000 1246.820000 2714.440000 ;
+ RECT 1245.555000 2708.520000 1246.820000 2709.000000 ;
+ RECT 1245.555000 2703.080000 1246.820000 2703.560000 ;
+ RECT 1245.555000 2697.640000 1246.820000 2698.120000 ;
+ RECT 1245.555000 2686.760000 1246.820000 2687.240000 ;
+ RECT 1245.555000 2692.200000 1246.820000 2692.680000 ;
+ RECT 1245.555000 2681.320000 1246.820000 2681.800000 ;
+ RECT 1245.555000 2675.880000 1246.820000 2676.360000 ;
+ RECT 1245.555000 2670.440000 1246.820000 2670.920000 ;
+ RECT 1245.555000 2665.000000 1246.820000 2665.480000 ;
+ RECT 1245.555000 2659.560000 1246.820000 2660.040000 ;
+ RECT 1245.555000 2654.120000 1246.820000 2654.600000 ;
+ RECT 1245.555000 2643.240000 1246.820000 2643.720000 ;
+ RECT 1245.555000 2637.800000 1246.820000 2638.280000 ;
+ RECT 1245.555000 2632.360000 1246.820000 2632.840000 ;
+ RECT 1245.555000 2626.920000 1246.820000 2627.400000 ;
+ RECT 1245.555000 2621.480000 1246.820000 2621.960000 ;
+ RECT 1245.555000 2616.040000 1246.820000 2616.520000 ;
+ RECT 1245.555000 2605.160000 1246.820000 2605.640000 ;
+ RECT 1245.555000 2610.600000 1246.820000 2611.080000 ;
+ RECT 1245.555000 2599.720000 1246.820000 2600.200000 ;
+ RECT 1245.555000 2594.280000 1246.820000 2594.760000 ;
+ RECT 1245.555000 2588.840000 1246.820000 2589.320000 ;
+ RECT 1245.555000 2583.400000 1246.820000 2583.880000 ;
+ RECT 1245.555000 2577.960000 1246.820000 2578.440000 ;
+ RECT 1245.555000 2572.520000 1246.820000 2573.000000 ;
+ RECT 1245.555000 2561.640000 1246.820000 2562.120000 ;
+ RECT 1245.555000 2567.080000 1246.820000 2567.560000 ;
+ RECT 1245.555000 2556.200000 1246.820000 2556.680000 ;
+ RECT 1245.555000 2648.680000 1246.820000 2649.160000 ;
+ RECT 1425.720000 2549.870000 1426.820000 2746.440000 ;
+ RECT 1380.720000 2549.870000 1381.820000 2746.440000 ;
+ RECT 1438.530000 2548.620000 1439.530000 2748.880000 ;
+ RECT 1335.720000 2549.870000 1336.820000 2746.440000 ;
+ RECT 1290.720000 2549.870000 1291.820000 2746.440000 ;
+ RECT 1245.720000 2549.870000 1246.820000 2746.440000 ;
+ RECT 1241.890000 2548.620000 1242.890000 2748.880000 ;
+ LAYER met3 ;
+ RECT 1425.720000 2741.160000 1426.820000 2741.640000 ;
+ RECT 1438.530000 2741.160000 1439.530000 2741.640000 ;
+ RECT 1438.530000 2730.280000 1439.530000 2730.760000 ;
+ RECT 1438.530000 2724.840000 1439.530000 2725.320000 ;
+ RECT 1438.530000 2735.720000 1439.530000 2736.200000 ;
+ RECT 1425.720000 2735.720000 1426.820000 2736.200000 ;
+ RECT 1425.720000 2730.280000 1426.820000 2730.760000 ;
+ RECT 1425.720000 2724.840000 1426.820000 2725.320000 ;
+ RECT 1425.720000 2713.960000 1426.820000 2714.440000 ;
+ RECT 1425.720000 2719.400000 1426.820000 2719.880000 ;
+ RECT 1438.530000 2713.960000 1439.530000 2714.440000 ;
+ RECT 1438.530000 2719.400000 1439.530000 2719.880000 ;
+ RECT 1425.720000 2703.080000 1426.820000 2703.560000 ;
+ RECT 1425.720000 2708.520000 1426.820000 2709.000000 ;
+ RECT 1438.530000 2703.080000 1439.530000 2703.560000 ;
+ RECT 1438.530000 2708.520000 1439.530000 2709.000000 ;
+ RECT 1380.720000 2724.840000 1381.820000 2725.320000 ;
+ RECT 1380.720000 2730.280000 1381.820000 2730.760000 ;
+ RECT 1380.720000 2735.720000 1381.820000 2736.200000 ;
+ RECT 1380.720000 2741.160000 1381.820000 2741.640000 ;
+ RECT 1380.720000 2708.520000 1381.820000 2709.000000 ;
+ RECT 1380.720000 2703.080000 1381.820000 2703.560000 ;
+ RECT 1380.720000 2713.960000 1381.820000 2714.440000 ;
+ RECT 1380.720000 2719.400000 1381.820000 2719.880000 ;
+ RECT 1438.530000 2692.200000 1439.530000 2692.680000 ;
+ RECT 1438.530000 2686.760000 1439.530000 2687.240000 ;
+ RECT 1438.530000 2697.640000 1439.530000 2698.120000 ;
+ RECT 1425.720000 2697.640000 1426.820000 2698.120000 ;
+ RECT 1425.720000 2692.200000 1426.820000 2692.680000 ;
+ RECT 1425.720000 2686.760000 1426.820000 2687.240000 ;
+ RECT 1425.720000 2675.880000 1426.820000 2676.360000 ;
+ RECT 1425.720000 2681.320000 1426.820000 2681.800000 ;
+ RECT 1438.530000 2675.880000 1439.530000 2676.360000 ;
+ RECT 1438.530000 2681.320000 1439.530000 2681.800000 ;
+ RECT 1438.530000 2665.000000 1439.530000 2665.480000 ;
+ RECT 1438.530000 2670.440000 1439.530000 2670.920000 ;
+ RECT 1425.720000 2670.440000 1426.820000 2670.920000 ;
+ RECT 1425.720000 2665.000000 1426.820000 2665.480000 ;
+ RECT 1425.720000 2654.120000 1426.820000 2654.600000 ;
+ RECT 1425.720000 2659.560000 1426.820000 2660.040000 ;
+ RECT 1438.530000 2654.120000 1439.530000 2654.600000 ;
+ RECT 1438.530000 2659.560000 1439.530000 2660.040000 ;
+ RECT 1380.720000 2675.880000 1381.820000 2676.360000 ;
+ RECT 1380.720000 2681.320000 1381.820000 2681.800000 ;
+ RECT 1380.720000 2686.760000 1381.820000 2687.240000 ;
+ RECT 1380.720000 2692.200000 1381.820000 2692.680000 ;
+ RECT 1380.720000 2697.640000 1381.820000 2698.120000 ;
+ RECT 1380.720000 2654.120000 1381.820000 2654.600000 ;
+ RECT 1380.720000 2659.560000 1381.820000 2660.040000 ;
+ RECT 1380.720000 2665.000000 1381.820000 2665.480000 ;
+ RECT 1380.720000 2670.440000 1381.820000 2670.920000 ;
+ RECT 1335.720000 2730.280000 1336.820000 2730.760000 ;
+ RECT 1335.720000 2724.840000 1336.820000 2725.320000 ;
+ RECT 1335.720000 2735.720000 1336.820000 2736.200000 ;
+ RECT 1335.720000 2741.160000 1336.820000 2741.640000 ;
+ RECT 1290.720000 2724.840000 1291.820000 2725.320000 ;
+ RECT 1290.720000 2730.280000 1291.820000 2730.760000 ;
+ RECT 1290.720000 2735.720000 1291.820000 2736.200000 ;
+ RECT 1290.720000 2741.160000 1291.820000 2741.640000 ;
+ RECT 1335.720000 2703.080000 1336.820000 2703.560000 ;
+ RECT 1335.720000 2708.520000 1336.820000 2709.000000 ;
+ RECT 1335.720000 2713.960000 1336.820000 2714.440000 ;
+ RECT 1335.720000 2719.400000 1336.820000 2719.880000 ;
+ RECT 1290.720000 2703.080000 1291.820000 2703.560000 ;
+ RECT 1290.720000 2708.520000 1291.820000 2709.000000 ;
+ RECT 1290.720000 2713.960000 1291.820000 2714.440000 ;
+ RECT 1290.720000 2719.400000 1291.820000 2719.880000 ;
+ RECT 1241.890000 2741.160000 1242.890000 2741.640000 ;
+ RECT 1245.555000 2741.160000 1246.820000 2741.640000 ;
+ RECT 1241.890000 2730.280000 1242.890000 2730.760000 ;
+ RECT 1245.555000 2730.280000 1246.820000 2730.760000 ;
+ RECT 1241.890000 2735.720000 1242.890000 2736.200000 ;
+ RECT 1245.555000 2735.720000 1246.820000 2736.200000 ;
+ RECT 1241.890000 2724.840000 1242.890000 2725.320000 ;
+ RECT 1245.555000 2724.840000 1246.820000 2725.320000 ;
+ RECT 1241.890000 2719.400000 1242.890000 2719.880000 ;
+ RECT 1245.555000 2719.400000 1246.820000 2719.880000 ;
+ RECT 1241.890000 2713.960000 1242.890000 2714.440000 ;
+ RECT 1245.555000 2713.960000 1246.820000 2714.440000 ;
+ RECT 1241.890000 2708.520000 1242.890000 2709.000000 ;
+ RECT 1245.555000 2708.520000 1246.820000 2709.000000 ;
+ RECT 1241.890000 2703.080000 1242.890000 2703.560000 ;
+ RECT 1245.555000 2703.080000 1246.820000 2703.560000 ;
+ RECT 1335.720000 2675.880000 1336.820000 2676.360000 ;
+ RECT 1335.720000 2681.320000 1336.820000 2681.800000 ;
+ RECT 1335.720000 2686.760000 1336.820000 2687.240000 ;
+ RECT 1335.720000 2692.200000 1336.820000 2692.680000 ;
+ RECT 1335.720000 2697.640000 1336.820000 2698.120000 ;
+ RECT 1290.720000 2675.880000 1291.820000 2676.360000 ;
+ RECT 1290.720000 2681.320000 1291.820000 2681.800000 ;
+ RECT 1290.720000 2686.760000 1291.820000 2687.240000 ;
+ RECT 1290.720000 2692.200000 1291.820000 2692.680000 ;
+ RECT 1290.720000 2697.640000 1291.820000 2698.120000 ;
+ RECT 1335.720000 2654.120000 1336.820000 2654.600000 ;
+ RECT 1335.720000 2659.560000 1336.820000 2660.040000 ;
+ RECT 1335.720000 2665.000000 1336.820000 2665.480000 ;
+ RECT 1335.720000 2670.440000 1336.820000 2670.920000 ;
+ RECT 1290.720000 2654.120000 1291.820000 2654.600000 ;
+ RECT 1290.720000 2659.560000 1291.820000 2660.040000 ;
+ RECT 1290.720000 2665.000000 1291.820000 2665.480000 ;
+ RECT 1290.720000 2670.440000 1291.820000 2670.920000 ;
+ RECT 1241.890000 2697.640000 1242.890000 2698.120000 ;
+ RECT 1245.555000 2697.640000 1246.820000 2698.120000 ;
+ RECT 1241.890000 2686.760000 1242.890000 2687.240000 ;
+ RECT 1245.555000 2686.760000 1246.820000 2687.240000 ;
+ RECT 1241.890000 2692.200000 1242.890000 2692.680000 ;
+ RECT 1245.555000 2692.200000 1246.820000 2692.680000 ;
+ RECT 1241.890000 2681.320000 1242.890000 2681.800000 ;
+ RECT 1245.555000 2681.320000 1246.820000 2681.800000 ;
+ RECT 1241.890000 2675.880000 1242.890000 2676.360000 ;
+ RECT 1245.555000 2675.880000 1246.820000 2676.360000 ;
+ RECT 1241.890000 2670.440000 1242.890000 2670.920000 ;
+ RECT 1245.555000 2670.440000 1246.820000 2670.920000 ;
+ RECT 1241.890000 2665.000000 1242.890000 2665.480000 ;
+ RECT 1245.555000 2665.000000 1246.820000 2665.480000 ;
+ RECT 1241.890000 2659.560000 1242.890000 2660.040000 ;
+ RECT 1245.555000 2659.560000 1246.820000 2660.040000 ;
+ RECT 1241.890000 2654.120000 1242.890000 2654.600000 ;
+ RECT 1245.555000 2654.120000 1246.820000 2654.600000 ;
+ RECT 1425.720000 2637.800000 1426.820000 2638.280000 ;
+ RECT 1425.720000 2643.240000 1426.820000 2643.720000 ;
+ RECT 1438.530000 2637.800000 1439.530000 2638.280000 ;
+ RECT 1438.530000 2643.240000 1439.530000 2643.720000 ;
+ RECT 1438.530000 2626.920000 1439.530000 2627.400000 ;
+ RECT 1438.530000 2632.360000 1439.530000 2632.840000 ;
+ RECT 1425.720000 2632.360000 1426.820000 2632.840000 ;
+ RECT 1425.720000 2626.920000 1426.820000 2627.400000 ;
+ RECT 1425.720000 2616.040000 1426.820000 2616.520000 ;
+ RECT 1425.720000 2621.480000 1426.820000 2621.960000 ;
+ RECT 1438.530000 2616.040000 1439.530000 2616.520000 ;
+ RECT 1438.530000 2621.480000 1439.530000 2621.960000 ;
+ RECT 1438.530000 2605.160000 1439.530000 2605.640000 ;
+ RECT 1438.530000 2599.720000 1439.530000 2600.200000 ;
+ RECT 1438.530000 2610.600000 1439.530000 2611.080000 ;
+ RECT 1425.720000 2610.600000 1426.820000 2611.080000 ;
+ RECT 1425.720000 2605.160000 1426.820000 2605.640000 ;
+ RECT 1425.720000 2599.720000 1426.820000 2600.200000 ;
+ RECT 1380.720000 2626.920000 1381.820000 2627.400000 ;
+ RECT 1380.720000 2632.360000 1381.820000 2632.840000 ;
+ RECT 1380.720000 2637.800000 1381.820000 2638.280000 ;
+ RECT 1380.720000 2643.240000 1381.820000 2643.720000 ;
+ RECT 1380.720000 2599.720000 1381.820000 2600.200000 ;
+ RECT 1380.720000 2605.160000 1381.820000 2605.640000 ;
+ RECT 1380.720000 2610.600000 1381.820000 2611.080000 ;
+ RECT 1380.720000 2616.040000 1381.820000 2616.520000 ;
+ RECT 1380.720000 2621.480000 1381.820000 2621.960000 ;
+ RECT 1425.720000 2588.840000 1426.820000 2589.320000 ;
+ RECT 1425.720000 2594.280000 1426.820000 2594.760000 ;
+ RECT 1438.530000 2588.840000 1439.530000 2589.320000 ;
+ RECT 1438.530000 2594.280000 1439.530000 2594.760000 ;
+ RECT 1425.720000 2577.960000 1426.820000 2578.440000 ;
+ RECT 1425.720000 2583.400000 1426.820000 2583.880000 ;
+ RECT 1438.530000 2577.960000 1439.530000 2578.440000 ;
+ RECT 1438.530000 2583.400000 1439.530000 2583.880000 ;
+ RECT 1438.530000 2567.080000 1439.530000 2567.560000 ;
+ RECT 1438.530000 2561.640000 1439.530000 2562.120000 ;
+ RECT 1438.530000 2572.520000 1439.530000 2573.000000 ;
+ RECT 1425.720000 2572.520000 1426.820000 2573.000000 ;
+ RECT 1425.720000 2567.080000 1426.820000 2567.560000 ;
+ RECT 1425.720000 2561.640000 1426.820000 2562.120000 ;
+ RECT 1425.720000 2556.200000 1426.820000 2556.680000 ;
+ RECT 1438.530000 2556.200000 1439.530000 2556.680000 ;
+ RECT 1380.720000 2577.960000 1381.820000 2578.440000 ;
+ RECT 1380.720000 2583.400000 1381.820000 2583.880000 ;
+ RECT 1380.720000 2588.840000 1381.820000 2589.320000 ;
+ RECT 1380.720000 2594.280000 1381.820000 2594.760000 ;
+ RECT 1380.720000 2556.200000 1381.820000 2556.680000 ;
+ RECT 1380.720000 2561.640000 1381.820000 2562.120000 ;
+ RECT 1380.720000 2567.080000 1381.820000 2567.560000 ;
+ RECT 1380.720000 2572.520000 1381.820000 2573.000000 ;
+ RECT 1335.720000 2626.920000 1336.820000 2627.400000 ;
+ RECT 1335.720000 2632.360000 1336.820000 2632.840000 ;
+ RECT 1335.720000 2637.800000 1336.820000 2638.280000 ;
+ RECT 1335.720000 2643.240000 1336.820000 2643.720000 ;
+ RECT 1290.720000 2626.920000 1291.820000 2627.400000 ;
+ RECT 1290.720000 2632.360000 1291.820000 2632.840000 ;
+ RECT 1290.720000 2637.800000 1291.820000 2638.280000 ;
+ RECT 1290.720000 2643.240000 1291.820000 2643.720000 ;
+ RECT 1335.720000 2599.720000 1336.820000 2600.200000 ;
+ RECT 1335.720000 2605.160000 1336.820000 2605.640000 ;
+ RECT 1335.720000 2610.600000 1336.820000 2611.080000 ;
+ RECT 1335.720000 2616.040000 1336.820000 2616.520000 ;
+ RECT 1335.720000 2621.480000 1336.820000 2621.960000 ;
+ RECT 1290.720000 2599.720000 1291.820000 2600.200000 ;
+ RECT 1290.720000 2605.160000 1291.820000 2605.640000 ;
+ RECT 1290.720000 2610.600000 1291.820000 2611.080000 ;
+ RECT 1290.720000 2616.040000 1291.820000 2616.520000 ;
+ RECT 1290.720000 2621.480000 1291.820000 2621.960000 ;
+ RECT 1241.890000 2643.240000 1242.890000 2643.720000 ;
+ RECT 1245.555000 2643.240000 1246.820000 2643.720000 ;
+ RECT 1241.890000 2637.800000 1242.890000 2638.280000 ;
+ RECT 1245.555000 2637.800000 1246.820000 2638.280000 ;
+ RECT 1241.890000 2632.360000 1242.890000 2632.840000 ;
+ RECT 1245.555000 2632.360000 1246.820000 2632.840000 ;
+ RECT 1241.890000 2626.920000 1242.890000 2627.400000 ;
+ RECT 1245.555000 2626.920000 1246.820000 2627.400000 ;
+ RECT 1241.890000 2621.480000 1242.890000 2621.960000 ;
+ RECT 1245.555000 2621.480000 1246.820000 2621.960000 ;
+ RECT 1241.890000 2616.040000 1242.890000 2616.520000 ;
+ RECT 1245.555000 2616.040000 1246.820000 2616.520000 ;
+ RECT 1241.890000 2605.160000 1242.890000 2605.640000 ;
+ RECT 1245.555000 2605.160000 1246.820000 2605.640000 ;
+ RECT 1241.890000 2610.600000 1242.890000 2611.080000 ;
+ RECT 1245.555000 2610.600000 1246.820000 2611.080000 ;
+ RECT 1241.890000 2599.720000 1242.890000 2600.200000 ;
+ RECT 1245.555000 2599.720000 1246.820000 2600.200000 ;
+ RECT 1335.720000 2577.960000 1336.820000 2578.440000 ;
+ RECT 1335.720000 2583.400000 1336.820000 2583.880000 ;
+ RECT 1335.720000 2588.840000 1336.820000 2589.320000 ;
+ RECT 1335.720000 2594.280000 1336.820000 2594.760000 ;
+ RECT 1290.720000 2577.960000 1291.820000 2578.440000 ;
+ RECT 1290.720000 2583.400000 1291.820000 2583.880000 ;
+ RECT 1290.720000 2588.840000 1291.820000 2589.320000 ;
+ RECT 1290.720000 2594.280000 1291.820000 2594.760000 ;
+ RECT 1335.720000 2556.200000 1336.820000 2556.680000 ;
+ RECT 1335.720000 2561.640000 1336.820000 2562.120000 ;
+ RECT 1335.720000 2567.080000 1336.820000 2567.560000 ;
+ RECT 1335.720000 2572.520000 1336.820000 2573.000000 ;
+ RECT 1290.720000 2556.200000 1291.820000 2556.680000 ;
+ RECT 1290.720000 2561.640000 1291.820000 2562.120000 ;
+ RECT 1290.720000 2567.080000 1291.820000 2567.560000 ;
+ RECT 1290.720000 2572.520000 1291.820000 2573.000000 ;
+ RECT 1241.890000 2594.280000 1242.890000 2594.760000 ;
+ RECT 1245.555000 2594.280000 1246.820000 2594.760000 ;
+ RECT 1241.890000 2588.840000 1242.890000 2589.320000 ;
+ RECT 1245.555000 2588.840000 1246.820000 2589.320000 ;
+ RECT 1241.890000 2583.400000 1242.890000 2583.880000 ;
+ RECT 1245.555000 2583.400000 1246.820000 2583.880000 ;
+ RECT 1241.890000 2577.960000 1242.890000 2578.440000 ;
+ RECT 1245.555000 2577.960000 1246.820000 2578.440000 ;
+ RECT 1241.890000 2572.520000 1242.890000 2573.000000 ;
+ RECT 1245.555000 2572.520000 1246.820000 2573.000000 ;
+ RECT 1241.890000 2561.640000 1242.890000 2562.120000 ;
+ RECT 1245.555000 2561.640000 1246.820000 2562.120000 ;
+ RECT 1241.890000 2567.080000 1242.890000 2567.560000 ;
+ RECT 1245.555000 2567.080000 1246.820000 2567.560000 ;
+ RECT 1241.890000 2556.200000 1242.890000 2556.680000 ;
+ RECT 1245.555000 2556.200000 1246.820000 2556.680000 ;
+ RECT 1380.720000 2648.680000 1381.820000 2649.160000 ;
+ RECT 1425.720000 2648.680000 1426.820000 2649.160000 ;
+ RECT 1438.530000 2648.680000 1439.530000 2649.160000 ;
+ RECT 1290.720000 2648.680000 1291.820000 2649.160000 ;
+ RECT 1335.720000 2648.680000 1336.820000 2649.160000 ;
+ RECT 1241.890000 2648.680000 1242.890000 2649.160000 ;
+ RECT 1245.555000 2648.680000 1246.820000 2649.160000 ;
+ RECT 1240.660000 2745.440000 1440.760000 2746.440000 ;
+ RECT 1240.660000 2549.870000 1440.760000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 2548.620000 1242.890000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 2747.880000 1242.890000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 2548.620000 1439.530000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 2747.880000 1439.530000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2549.870000 1241.660000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2549.870000 1440.760000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2745.440000 1241.660000 2746.440000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2745.440000 1440.760000 2746.440000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 2540.900000 1246.820000 2541.380000 ;
+ RECT 1245.555000 2530.020000 1246.820000 2530.500000 ;
+ RECT 1245.555000 2535.460000 1246.820000 2535.940000 ;
+ RECT 1245.555000 2524.580000 1246.820000 2525.060000 ;
+ RECT 1245.555000 2519.140000 1246.820000 2519.620000 ;
+ RECT 1245.555000 2513.700000 1246.820000 2514.180000 ;
+ RECT 1245.555000 2508.260000 1246.820000 2508.740000 ;
+ RECT 1245.555000 2502.820000 1246.820000 2503.300000 ;
+ RECT 1245.555000 2497.380000 1246.820000 2497.860000 ;
+ RECT 1245.555000 2486.500000 1246.820000 2486.980000 ;
+ RECT 1245.555000 2491.940000 1246.820000 2492.420000 ;
+ RECT 1245.555000 2481.060000 1246.820000 2481.540000 ;
+ RECT 1245.555000 2475.620000 1246.820000 2476.100000 ;
+ RECT 1245.555000 2470.180000 1246.820000 2470.660000 ;
+ RECT 1245.555000 2464.740000 1246.820000 2465.220000 ;
+ RECT 1245.555000 2459.300000 1246.820000 2459.780000 ;
+ RECT 1245.555000 2453.860000 1246.820000 2454.340000 ;
+ RECT 1245.555000 2442.980000 1246.820000 2443.460000 ;
+ RECT 1245.555000 2437.540000 1246.820000 2438.020000 ;
+ RECT 1245.555000 2432.100000 1246.820000 2432.580000 ;
+ RECT 1245.555000 2426.660000 1246.820000 2427.140000 ;
+ RECT 1245.555000 2421.220000 1246.820000 2421.700000 ;
+ RECT 1245.555000 2415.780000 1246.820000 2416.260000 ;
+ RECT 1245.555000 2404.900000 1246.820000 2405.380000 ;
+ RECT 1245.555000 2410.340000 1246.820000 2410.820000 ;
+ RECT 1245.555000 2399.460000 1246.820000 2399.940000 ;
+ RECT 1245.555000 2394.020000 1246.820000 2394.500000 ;
+ RECT 1245.555000 2388.580000 1246.820000 2389.060000 ;
+ RECT 1245.555000 2383.140000 1246.820000 2383.620000 ;
+ RECT 1245.555000 2377.700000 1246.820000 2378.180000 ;
+ RECT 1245.555000 2372.260000 1246.820000 2372.740000 ;
+ RECT 1245.555000 2361.380000 1246.820000 2361.860000 ;
+ RECT 1245.555000 2366.820000 1246.820000 2367.300000 ;
+ RECT 1245.555000 2355.940000 1246.820000 2356.420000 ;
+ RECT 1245.555000 2448.420000 1246.820000 2448.900000 ;
+ RECT 1425.720000 2349.610000 1426.820000 2546.180000 ;
+ RECT 1380.720000 2349.610000 1381.820000 2546.180000 ;
+ RECT 1438.530000 2348.360000 1439.530000 2548.620000 ;
+ RECT 1335.720000 2349.610000 1336.820000 2546.180000 ;
+ RECT 1290.720000 2349.610000 1291.820000 2546.180000 ;
+ RECT 1245.720000 2349.610000 1246.820000 2546.180000 ;
+ RECT 1241.890000 2348.360000 1242.890000 2548.620000 ;
+ LAYER met3 ;
+ RECT 1425.720000 2540.900000 1426.820000 2541.380000 ;
+ RECT 1438.530000 2540.900000 1439.530000 2541.380000 ;
+ RECT 1438.530000 2530.020000 1439.530000 2530.500000 ;
+ RECT 1438.530000 2524.580000 1439.530000 2525.060000 ;
+ RECT 1438.530000 2535.460000 1439.530000 2535.940000 ;
+ RECT 1425.720000 2535.460000 1426.820000 2535.940000 ;
+ RECT 1425.720000 2530.020000 1426.820000 2530.500000 ;
+ RECT 1425.720000 2524.580000 1426.820000 2525.060000 ;
+ RECT 1425.720000 2513.700000 1426.820000 2514.180000 ;
+ RECT 1425.720000 2519.140000 1426.820000 2519.620000 ;
+ RECT 1438.530000 2513.700000 1439.530000 2514.180000 ;
+ RECT 1438.530000 2519.140000 1439.530000 2519.620000 ;
+ RECT 1425.720000 2502.820000 1426.820000 2503.300000 ;
+ RECT 1425.720000 2508.260000 1426.820000 2508.740000 ;
+ RECT 1438.530000 2502.820000 1439.530000 2503.300000 ;
+ RECT 1438.530000 2508.260000 1439.530000 2508.740000 ;
+ RECT 1380.720000 2524.580000 1381.820000 2525.060000 ;
+ RECT 1380.720000 2530.020000 1381.820000 2530.500000 ;
+ RECT 1380.720000 2535.460000 1381.820000 2535.940000 ;
+ RECT 1380.720000 2540.900000 1381.820000 2541.380000 ;
+ RECT 1380.720000 2508.260000 1381.820000 2508.740000 ;
+ RECT 1380.720000 2502.820000 1381.820000 2503.300000 ;
+ RECT 1380.720000 2513.700000 1381.820000 2514.180000 ;
+ RECT 1380.720000 2519.140000 1381.820000 2519.620000 ;
+ RECT 1438.530000 2491.940000 1439.530000 2492.420000 ;
+ RECT 1438.530000 2486.500000 1439.530000 2486.980000 ;
+ RECT 1438.530000 2497.380000 1439.530000 2497.860000 ;
+ RECT 1425.720000 2497.380000 1426.820000 2497.860000 ;
+ RECT 1425.720000 2491.940000 1426.820000 2492.420000 ;
+ RECT 1425.720000 2486.500000 1426.820000 2486.980000 ;
+ RECT 1425.720000 2475.620000 1426.820000 2476.100000 ;
+ RECT 1425.720000 2481.060000 1426.820000 2481.540000 ;
+ RECT 1438.530000 2475.620000 1439.530000 2476.100000 ;
+ RECT 1438.530000 2481.060000 1439.530000 2481.540000 ;
+ RECT 1438.530000 2464.740000 1439.530000 2465.220000 ;
+ RECT 1438.530000 2470.180000 1439.530000 2470.660000 ;
+ RECT 1425.720000 2470.180000 1426.820000 2470.660000 ;
+ RECT 1425.720000 2464.740000 1426.820000 2465.220000 ;
+ RECT 1425.720000 2453.860000 1426.820000 2454.340000 ;
+ RECT 1425.720000 2459.300000 1426.820000 2459.780000 ;
+ RECT 1438.530000 2453.860000 1439.530000 2454.340000 ;
+ RECT 1438.530000 2459.300000 1439.530000 2459.780000 ;
+ RECT 1380.720000 2475.620000 1381.820000 2476.100000 ;
+ RECT 1380.720000 2481.060000 1381.820000 2481.540000 ;
+ RECT 1380.720000 2486.500000 1381.820000 2486.980000 ;
+ RECT 1380.720000 2491.940000 1381.820000 2492.420000 ;
+ RECT 1380.720000 2497.380000 1381.820000 2497.860000 ;
+ RECT 1380.720000 2453.860000 1381.820000 2454.340000 ;
+ RECT 1380.720000 2459.300000 1381.820000 2459.780000 ;
+ RECT 1380.720000 2464.740000 1381.820000 2465.220000 ;
+ RECT 1380.720000 2470.180000 1381.820000 2470.660000 ;
+ RECT 1335.720000 2530.020000 1336.820000 2530.500000 ;
+ RECT 1335.720000 2524.580000 1336.820000 2525.060000 ;
+ RECT 1335.720000 2535.460000 1336.820000 2535.940000 ;
+ RECT 1335.720000 2540.900000 1336.820000 2541.380000 ;
+ RECT 1290.720000 2524.580000 1291.820000 2525.060000 ;
+ RECT 1290.720000 2530.020000 1291.820000 2530.500000 ;
+ RECT 1290.720000 2535.460000 1291.820000 2535.940000 ;
+ RECT 1290.720000 2540.900000 1291.820000 2541.380000 ;
+ RECT 1335.720000 2502.820000 1336.820000 2503.300000 ;
+ RECT 1335.720000 2508.260000 1336.820000 2508.740000 ;
+ RECT 1335.720000 2513.700000 1336.820000 2514.180000 ;
+ RECT 1335.720000 2519.140000 1336.820000 2519.620000 ;
+ RECT 1290.720000 2502.820000 1291.820000 2503.300000 ;
+ RECT 1290.720000 2508.260000 1291.820000 2508.740000 ;
+ RECT 1290.720000 2513.700000 1291.820000 2514.180000 ;
+ RECT 1290.720000 2519.140000 1291.820000 2519.620000 ;
+ RECT 1241.890000 2540.900000 1242.890000 2541.380000 ;
+ RECT 1245.555000 2540.900000 1246.820000 2541.380000 ;
+ RECT 1241.890000 2530.020000 1242.890000 2530.500000 ;
+ RECT 1245.555000 2530.020000 1246.820000 2530.500000 ;
+ RECT 1241.890000 2535.460000 1242.890000 2535.940000 ;
+ RECT 1245.555000 2535.460000 1246.820000 2535.940000 ;
+ RECT 1241.890000 2524.580000 1242.890000 2525.060000 ;
+ RECT 1245.555000 2524.580000 1246.820000 2525.060000 ;
+ RECT 1241.890000 2519.140000 1242.890000 2519.620000 ;
+ RECT 1245.555000 2519.140000 1246.820000 2519.620000 ;
+ RECT 1241.890000 2513.700000 1242.890000 2514.180000 ;
+ RECT 1245.555000 2513.700000 1246.820000 2514.180000 ;
+ RECT 1241.890000 2508.260000 1242.890000 2508.740000 ;
+ RECT 1245.555000 2508.260000 1246.820000 2508.740000 ;
+ RECT 1241.890000 2502.820000 1242.890000 2503.300000 ;
+ RECT 1245.555000 2502.820000 1246.820000 2503.300000 ;
+ RECT 1335.720000 2475.620000 1336.820000 2476.100000 ;
+ RECT 1335.720000 2481.060000 1336.820000 2481.540000 ;
+ RECT 1335.720000 2486.500000 1336.820000 2486.980000 ;
+ RECT 1335.720000 2491.940000 1336.820000 2492.420000 ;
+ RECT 1335.720000 2497.380000 1336.820000 2497.860000 ;
+ RECT 1290.720000 2475.620000 1291.820000 2476.100000 ;
+ RECT 1290.720000 2481.060000 1291.820000 2481.540000 ;
+ RECT 1290.720000 2486.500000 1291.820000 2486.980000 ;
+ RECT 1290.720000 2491.940000 1291.820000 2492.420000 ;
+ RECT 1290.720000 2497.380000 1291.820000 2497.860000 ;
+ RECT 1335.720000 2453.860000 1336.820000 2454.340000 ;
+ RECT 1335.720000 2459.300000 1336.820000 2459.780000 ;
+ RECT 1335.720000 2464.740000 1336.820000 2465.220000 ;
+ RECT 1335.720000 2470.180000 1336.820000 2470.660000 ;
+ RECT 1290.720000 2453.860000 1291.820000 2454.340000 ;
+ RECT 1290.720000 2459.300000 1291.820000 2459.780000 ;
+ RECT 1290.720000 2464.740000 1291.820000 2465.220000 ;
+ RECT 1290.720000 2470.180000 1291.820000 2470.660000 ;
+ RECT 1241.890000 2497.380000 1242.890000 2497.860000 ;
+ RECT 1245.555000 2497.380000 1246.820000 2497.860000 ;
+ RECT 1241.890000 2486.500000 1242.890000 2486.980000 ;
+ RECT 1245.555000 2486.500000 1246.820000 2486.980000 ;
+ RECT 1241.890000 2491.940000 1242.890000 2492.420000 ;
+ RECT 1245.555000 2491.940000 1246.820000 2492.420000 ;
+ RECT 1241.890000 2481.060000 1242.890000 2481.540000 ;
+ RECT 1245.555000 2481.060000 1246.820000 2481.540000 ;
+ RECT 1241.890000 2475.620000 1242.890000 2476.100000 ;
+ RECT 1245.555000 2475.620000 1246.820000 2476.100000 ;
+ RECT 1241.890000 2470.180000 1242.890000 2470.660000 ;
+ RECT 1245.555000 2470.180000 1246.820000 2470.660000 ;
+ RECT 1241.890000 2464.740000 1242.890000 2465.220000 ;
+ RECT 1245.555000 2464.740000 1246.820000 2465.220000 ;
+ RECT 1241.890000 2459.300000 1242.890000 2459.780000 ;
+ RECT 1245.555000 2459.300000 1246.820000 2459.780000 ;
+ RECT 1241.890000 2453.860000 1242.890000 2454.340000 ;
+ RECT 1245.555000 2453.860000 1246.820000 2454.340000 ;
+ RECT 1425.720000 2437.540000 1426.820000 2438.020000 ;
+ RECT 1425.720000 2442.980000 1426.820000 2443.460000 ;
+ RECT 1438.530000 2437.540000 1439.530000 2438.020000 ;
+ RECT 1438.530000 2442.980000 1439.530000 2443.460000 ;
+ RECT 1438.530000 2426.660000 1439.530000 2427.140000 ;
+ RECT 1438.530000 2432.100000 1439.530000 2432.580000 ;
+ RECT 1425.720000 2432.100000 1426.820000 2432.580000 ;
+ RECT 1425.720000 2426.660000 1426.820000 2427.140000 ;
+ RECT 1425.720000 2415.780000 1426.820000 2416.260000 ;
+ RECT 1425.720000 2421.220000 1426.820000 2421.700000 ;
+ RECT 1438.530000 2415.780000 1439.530000 2416.260000 ;
+ RECT 1438.530000 2421.220000 1439.530000 2421.700000 ;
+ RECT 1438.530000 2404.900000 1439.530000 2405.380000 ;
+ RECT 1438.530000 2399.460000 1439.530000 2399.940000 ;
+ RECT 1438.530000 2410.340000 1439.530000 2410.820000 ;
+ RECT 1425.720000 2410.340000 1426.820000 2410.820000 ;
+ RECT 1425.720000 2404.900000 1426.820000 2405.380000 ;
+ RECT 1425.720000 2399.460000 1426.820000 2399.940000 ;
+ RECT 1380.720000 2426.660000 1381.820000 2427.140000 ;
+ RECT 1380.720000 2432.100000 1381.820000 2432.580000 ;
+ RECT 1380.720000 2437.540000 1381.820000 2438.020000 ;
+ RECT 1380.720000 2442.980000 1381.820000 2443.460000 ;
+ RECT 1380.720000 2399.460000 1381.820000 2399.940000 ;
+ RECT 1380.720000 2404.900000 1381.820000 2405.380000 ;
+ RECT 1380.720000 2410.340000 1381.820000 2410.820000 ;
+ RECT 1380.720000 2415.780000 1381.820000 2416.260000 ;
+ RECT 1380.720000 2421.220000 1381.820000 2421.700000 ;
+ RECT 1425.720000 2388.580000 1426.820000 2389.060000 ;
+ RECT 1425.720000 2394.020000 1426.820000 2394.500000 ;
+ RECT 1438.530000 2388.580000 1439.530000 2389.060000 ;
+ RECT 1438.530000 2394.020000 1439.530000 2394.500000 ;
+ RECT 1425.720000 2377.700000 1426.820000 2378.180000 ;
+ RECT 1425.720000 2383.140000 1426.820000 2383.620000 ;
+ RECT 1438.530000 2377.700000 1439.530000 2378.180000 ;
+ RECT 1438.530000 2383.140000 1439.530000 2383.620000 ;
+ RECT 1438.530000 2366.820000 1439.530000 2367.300000 ;
+ RECT 1438.530000 2361.380000 1439.530000 2361.860000 ;
+ RECT 1438.530000 2372.260000 1439.530000 2372.740000 ;
+ RECT 1425.720000 2372.260000 1426.820000 2372.740000 ;
+ RECT 1425.720000 2366.820000 1426.820000 2367.300000 ;
+ RECT 1425.720000 2361.380000 1426.820000 2361.860000 ;
+ RECT 1425.720000 2355.940000 1426.820000 2356.420000 ;
+ RECT 1438.530000 2355.940000 1439.530000 2356.420000 ;
+ RECT 1380.720000 2377.700000 1381.820000 2378.180000 ;
+ RECT 1380.720000 2383.140000 1381.820000 2383.620000 ;
+ RECT 1380.720000 2388.580000 1381.820000 2389.060000 ;
+ RECT 1380.720000 2394.020000 1381.820000 2394.500000 ;
+ RECT 1380.720000 2355.940000 1381.820000 2356.420000 ;
+ RECT 1380.720000 2361.380000 1381.820000 2361.860000 ;
+ RECT 1380.720000 2366.820000 1381.820000 2367.300000 ;
+ RECT 1380.720000 2372.260000 1381.820000 2372.740000 ;
+ RECT 1335.720000 2426.660000 1336.820000 2427.140000 ;
+ RECT 1335.720000 2432.100000 1336.820000 2432.580000 ;
+ RECT 1335.720000 2437.540000 1336.820000 2438.020000 ;
+ RECT 1335.720000 2442.980000 1336.820000 2443.460000 ;
+ RECT 1290.720000 2426.660000 1291.820000 2427.140000 ;
+ RECT 1290.720000 2432.100000 1291.820000 2432.580000 ;
+ RECT 1290.720000 2437.540000 1291.820000 2438.020000 ;
+ RECT 1290.720000 2442.980000 1291.820000 2443.460000 ;
+ RECT 1335.720000 2399.460000 1336.820000 2399.940000 ;
+ RECT 1335.720000 2404.900000 1336.820000 2405.380000 ;
+ RECT 1335.720000 2410.340000 1336.820000 2410.820000 ;
+ RECT 1335.720000 2415.780000 1336.820000 2416.260000 ;
+ RECT 1335.720000 2421.220000 1336.820000 2421.700000 ;
+ RECT 1290.720000 2399.460000 1291.820000 2399.940000 ;
+ RECT 1290.720000 2404.900000 1291.820000 2405.380000 ;
+ RECT 1290.720000 2410.340000 1291.820000 2410.820000 ;
+ RECT 1290.720000 2415.780000 1291.820000 2416.260000 ;
+ RECT 1290.720000 2421.220000 1291.820000 2421.700000 ;
+ RECT 1241.890000 2442.980000 1242.890000 2443.460000 ;
+ RECT 1245.555000 2442.980000 1246.820000 2443.460000 ;
+ RECT 1241.890000 2437.540000 1242.890000 2438.020000 ;
+ RECT 1245.555000 2437.540000 1246.820000 2438.020000 ;
+ RECT 1241.890000 2432.100000 1242.890000 2432.580000 ;
+ RECT 1245.555000 2432.100000 1246.820000 2432.580000 ;
+ RECT 1241.890000 2426.660000 1242.890000 2427.140000 ;
+ RECT 1245.555000 2426.660000 1246.820000 2427.140000 ;
+ RECT 1241.890000 2421.220000 1242.890000 2421.700000 ;
+ RECT 1245.555000 2421.220000 1246.820000 2421.700000 ;
+ RECT 1241.890000 2415.780000 1242.890000 2416.260000 ;
+ RECT 1245.555000 2415.780000 1246.820000 2416.260000 ;
+ RECT 1241.890000 2404.900000 1242.890000 2405.380000 ;
+ RECT 1245.555000 2404.900000 1246.820000 2405.380000 ;
+ RECT 1241.890000 2410.340000 1242.890000 2410.820000 ;
+ RECT 1245.555000 2410.340000 1246.820000 2410.820000 ;
+ RECT 1241.890000 2399.460000 1242.890000 2399.940000 ;
+ RECT 1245.555000 2399.460000 1246.820000 2399.940000 ;
+ RECT 1335.720000 2377.700000 1336.820000 2378.180000 ;
+ RECT 1335.720000 2383.140000 1336.820000 2383.620000 ;
+ RECT 1335.720000 2388.580000 1336.820000 2389.060000 ;
+ RECT 1335.720000 2394.020000 1336.820000 2394.500000 ;
+ RECT 1290.720000 2377.700000 1291.820000 2378.180000 ;
+ RECT 1290.720000 2383.140000 1291.820000 2383.620000 ;
+ RECT 1290.720000 2388.580000 1291.820000 2389.060000 ;
+ RECT 1290.720000 2394.020000 1291.820000 2394.500000 ;
+ RECT 1335.720000 2355.940000 1336.820000 2356.420000 ;
+ RECT 1335.720000 2361.380000 1336.820000 2361.860000 ;
+ RECT 1335.720000 2366.820000 1336.820000 2367.300000 ;
+ RECT 1335.720000 2372.260000 1336.820000 2372.740000 ;
+ RECT 1290.720000 2355.940000 1291.820000 2356.420000 ;
+ RECT 1290.720000 2361.380000 1291.820000 2361.860000 ;
+ RECT 1290.720000 2366.820000 1291.820000 2367.300000 ;
+ RECT 1290.720000 2372.260000 1291.820000 2372.740000 ;
+ RECT 1241.890000 2394.020000 1242.890000 2394.500000 ;
+ RECT 1245.555000 2394.020000 1246.820000 2394.500000 ;
+ RECT 1241.890000 2388.580000 1242.890000 2389.060000 ;
+ RECT 1245.555000 2388.580000 1246.820000 2389.060000 ;
+ RECT 1241.890000 2383.140000 1242.890000 2383.620000 ;
+ RECT 1245.555000 2383.140000 1246.820000 2383.620000 ;
+ RECT 1241.890000 2377.700000 1242.890000 2378.180000 ;
+ RECT 1245.555000 2377.700000 1246.820000 2378.180000 ;
+ RECT 1241.890000 2372.260000 1242.890000 2372.740000 ;
+ RECT 1245.555000 2372.260000 1246.820000 2372.740000 ;
+ RECT 1241.890000 2361.380000 1242.890000 2361.860000 ;
+ RECT 1245.555000 2361.380000 1246.820000 2361.860000 ;
+ RECT 1241.890000 2366.820000 1242.890000 2367.300000 ;
+ RECT 1245.555000 2366.820000 1246.820000 2367.300000 ;
+ RECT 1241.890000 2355.940000 1242.890000 2356.420000 ;
+ RECT 1245.555000 2355.940000 1246.820000 2356.420000 ;
+ RECT 1380.720000 2448.420000 1381.820000 2448.900000 ;
+ RECT 1425.720000 2448.420000 1426.820000 2448.900000 ;
+ RECT 1438.530000 2448.420000 1439.530000 2448.900000 ;
+ RECT 1290.720000 2448.420000 1291.820000 2448.900000 ;
+ RECT 1335.720000 2448.420000 1336.820000 2448.900000 ;
+ RECT 1241.890000 2448.420000 1242.890000 2448.900000 ;
+ RECT 1245.555000 2448.420000 1246.820000 2448.900000 ;
+ RECT 1240.660000 2545.180000 1440.760000 2546.180000 ;
+ RECT 1240.660000 2349.610000 1440.760000 2350.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 2348.360000 1242.890000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 2547.620000 1242.890000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 2348.360000 1439.530000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 2547.620000 1439.530000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2349.610000 1241.660000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2349.610000 1440.760000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2545.180000 1241.660000 2546.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2545.180000 1440.760000 2546.180000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 2340.640000 1246.820000 2341.120000 ;
+ RECT 1245.555000 2329.760000 1246.820000 2330.240000 ;
+ RECT 1245.555000 2335.200000 1246.820000 2335.680000 ;
+ RECT 1245.555000 2324.320000 1246.820000 2324.800000 ;
+ RECT 1245.555000 2318.880000 1246.820000 2319.360000 ;
+ RECT 1245.555000 2313.440000 1246.820000 2313.920000 ;
+ RECT 1245.555000 2308.000000 1246.820000 2308.480000 ;
+ RECT 1245.555000 2302.560000 1246.820000 2303.040000 ;
+ RECT 1245.555000 2297.120000 1246.820000 2297.600000 ;
+ RECT 1245.555000 2286.240000 1246.820000 2286.720000 ;
+ RECT 1245.555000 2291.680000 1246.820000 2292.160000 ;
+ RECT 1245.555000 2280.800000 1246.820000 2281.280000 ;
+ RECT 1245.555000 2275.360000 1246.820000 2275.840000 ;
+ RECT 1245.555000 2269.920000 1246.820000 2270.400000 ;
+ RECT 1245.555000 2264.480000 1246.820000 2264.960000 ;
+ RECT 1245.555000 2259.040000 1246.820000 2259.520000 ;
+ RECT 1245.555000 2253.600000 1246.820000 2254.080000 ;
+ RECT 1245.555000 2242.720000 1246.820000 2243.200000 ;
+ RECT 1245.555000 2237.280000 1246.820000 2237.760000 ;
+ RECT 1245.555000 2231.840000 1246.820000 2232.320000 ;
+ RECT 1245.555000 2226.400000 1246.820000 2226.880000 ;
+ RECT 1245.555000 2220.960000 1246.820000 2221.440000 ;
+ RECT 1245.555000 2215.520000 1246.820000 2216.000000 ;
+ RECT 1245.555000 2204.640000 1246.820000 2205.120000 ;
+ RECT 1245.555000 2210.080000 1246.820000 2210.560000 ;
+ RECT 1245.555000 2199.200000 1246.820000 2199.680000 ;
+ RECT 1245.555000 2193.760000 1246.820000 2194.240000 ;
+ RECT 1245.555000 2188.320000 1246.820000 2188.800000 ;
+ RECT 1245.555000 2182.880000 1246.820000 2183.360000 ;
+ RECT 1245.555000 2177.440000 1246.820000 2177.920000 ;
+ RECT 1245.555000 2172.000000 1246.820000 2172.480000 ;
+ RECT 1245.555000 2161.120000 1246.820000 2161.600000 ;
+ RECT 1245.555000 2166.560000 1246.820000 2167.040000 ;
+ RECT 1245.555000 2155.680000 1246.820000 2156.160000 ;
+ RECT 1245.555000 2248.160000 1246.820000 2248.640000 ;
+ RECT 1425.720000 2149.350000 1426.820000 2345.920000 ;
+ RECT 1380.720000 2149.350000 1381.820000 2345.920000 ;
+ RECT 1438.530000 2148.100000 1439.530000 2348.360000 ;
+ RECT 1335.720000 2149.350000 1336.820000 2345.920000 ;
+ RECT 1290.720000 2149.350000 1291.820000 2345.920000 ;
+ RECT 1245.720000 2149.350000 1246.820000 2345.920000 ;
+ RECT 1241.890000 2148.100000 1242.890000 2348.360000 ;
+ LAYER met3 ;
+ RECT 1425.720000 2340.640000 1426.820000 2341.120000 ;
+ RECT 1438.530000 2340.640000 1439.530000 2341.120000 ;
+ RECT 1438.530000 2329.760000 1439.530000 2330.240000 ;
+ RECT 1438.530000 2324.320000 1439.530000 2324.800000 ;
+ RECT 1438.530000 2335.200000 1439.530000 2335.680000 ;
+ RECT 1425.720000 2335.200000 1426.820000 2335.680000 ;
+ RECT 1425.720000 2329.760000 1426.820000 2330.240000 ;
+ RECT 1425.720000 2324.320000 1426.820000 2324.800000 ;
+ RECT 1425.720000 2313.440000 1426.820000 2313.920000 ;
+ RECT 1425.720000 2318.880000 1426.820000 2319.360000 ;
+ RECT 1438.530000 2313.440000 1439.530000 2313.920000 ;
+ RECT 1438.530000 2318.880000 1439.530000 2319.360000 ;
+ RECT 1425.720000 2302.560000 1426.820000 2303.040000 ;
+ RECT 1425.720000 2308.000000 1426.820000 2308.480000 ;
+ RECT 1438.530000 2302.560000 1439.530000 2303.040000 ;
+ RECT 1438.530000 2308.000000 1439.530000 2308.480000 ;
+ RECT 1380.720000 2324.320000 1381.820000 2324.800000 ;
+ RECT 1380.720000 2329.760000 1381.820000 2330.240000 ;
+ RECT 1380.720000 2335.200000 1381.820000 2335.680000 ;
+ RECT 1380.720000 2340.640000 1381.820000 2341.120000 ;
+ RECT 1380.720000 2308.000000 1381.820000 2308.480000 ;
+ RECT 1380.720000 2302.560000 1381.820000 2303.040000 ;
+ RECT 1380.720000 2313.440000 1381.820000 2313.920000 ;
+ RECT 1380.720000 2318.880000 1381.820000 2319.360000 ;
+ RECT 1438.530000 2291.680000 1439.530000 2292.160000 ;
+ RECT 1438.530000 2286.240000 1439.530000 2286.720000 ;
+ RECT 1438.530000 2297.120000 1439.530000 2297.600000 ;
+ RECT 1425.720000 2297.120000 1426.820000 2297.600000 ;
+ RECT 1425.720000 2291.680000 1426.820000 2292.160000 ;
+ RECT 1425.720000 2286.240000 1426.820000 2286.720000 ;
+ RECT 1425.720000 2275.360000 1426.820000 2275.840000 ;
+ RECT 1425.720000 2280.800000 1426.820000 2281.280000 ;
+ RECT 1438.530000 2275.360000 1439.530000 2275.840000 ;
+ RECT 1438.530000 2280.800000 1439.530000 2281.280000 ;
+ RECT 1438.530000 2264.480000 1439.530000 2264.960000 ;
+ RECT 1438.530000 2269.920000 1439.530000 2270.400000 ;
+ RECT 1425.720000 2269.920000 1426.820000 2270.400000 ;
+ RECT 1425.720000 2264.480000 1426.820000 2264.960000 ;
+ RECT 1425.720000 2253.600000 1426.820000 2254.080000 ;
+ RECT 1425.720000 2259.040000 1426.820000 2259.520000 ;
+ RECT 1438.530000 2253.600000 1439.530000 2254.080000 ;
+ RECT 1438.530000 2259.040000 1439.530000 2259.520000 ;
+ RECT 1380.720000 2275.360000 1381.820000 2275.840000 ;
+ RECT 1380.720000 2280.800000 1381.820000 2281.280000 ;
+ RECT 1380.720000 2286.240000 1381.820000 2286.720000 ;
+ RECT 1380.720000 2291.680000 1381.820000 2292.160000 ;
+ RECT 1380.720000 2297.120000 1381.820000 2297.600000 ;
+ RECT 1380.720000 2253.600000 1381.820000 2254.080000 ;
+ RECT 1380.720000 2259.040000 1381.820000 2259.520000 ;
+ RECT 1380.720000 2264.480000 1381.820000 2264.960000 ;
+ RECT 1380.720000 2269.920000 1381.820000 2270.400000 ;
+ RECT 1335.720000 2329.760000 1336.820000 2330.240000 ;
+ RECT 1335.720000 2324.320000 1336.820000 2324.800000 ;
+ RECT 1335.720000 2335.200000 1336.820000 2335.680000 ;
+ RECT 1335.720000 2340.640000 1336.820000 2341.120000 ;
+ RECT 1290.720000 2324.320000 1291.820000 2324.800000 ;
+ RECT 1290.720000 2329.760000 1291.820000 2330.240000 ;
+ RECT 1290.720000 2335.200000 1291.820000 2335.680000 ;
+ RECT 1290.720000 2340.640000 1291.820000 2341.120000 ;
+ RECT 1335.720000 2302.560000 1336.820000 2303.040000 ;
+ RECT 1335.720000 2308.000000 1336.820000 2308.480000 ;
+ RECT 1335.720000 2313.440000 1336.820000 2313.920000 ;
+ RECT 1335.720000 2318.880000 1336.820000 2319.360000 ;
+ RECT 1290.720000 2302.560000 1291.820000 2303.040000 ;
+ RECT 1290.720000 2308.000000 1291.820000 2308.480000 ;
+ RECT 1290.720000 2313.440000 1291.820000 2313.920000 ;
+ RECT 1290.720000 2318.880000 1291.820000 2319.360000 ;
+ RECT 1241.890000 2340.640000 1242.890000 2341.120000 ;
+ RECT 1245.555000 2340.640000 1246.820000 2341.120000 ;
+ RECT 1241.890000 2329.760000 1242.890000 2330.240000 ;
+ RECT 1245.555000 2329.760000 1246.820000 2330.240000 ;
+ RECT 1241.890000 2335.200000 1242.890000 2335.680000 ;
+ RECT 1245.555000 2335.200000 1246.820000 2335.680000 ;
+ RECT 1241.890000 2324.320000 1242.890000 2324.800000 ;
+ RECT 1245.555000 2324.320000 1246.820000 2324.800000 ;
+ RECT 1241.890000 2318.880000 1242.890000 2319.360000 ;
+ RECT 1245.555000 2318.880000 1246.820000 2319.360000 ;
+ RECT 1241.890000 2313.440000 1242.890000 2313.920000 ;
+ RECT 1245.555000 2313.440000 1246.820000 2313.920000 ;
+ RECT 1241.890000 2308.000000 1242.890000 2308.480000 ;
+ RECT 1245.555000 2308.000000 1246.820000 2308.480000 ;
+ RECT 1241.890000 2302.560000 1242.890000 2303.040000 ;
+ RECT 1245.555000 2302.560000 1246.820000 2303.040000 ;
+ RECT 1335.720000 2275.360000 1336.820000 2275.840000 ;
+ RECT 1335.720000 2280.800000 1336.820000 2281.280000 ;
+ RECT 1335.720000 2286.240000 1336.820000 2286.720000 ;
+ RECT 1335.720000 2291.680000 1336.820000 2292.160000 ;
+ RECT 1335.720000 2297.120000 1336.820000 2297.600000 ;
+ RECT 1290.720000 2275.360000 1291.820000 2275.840000 ;
+ RECT 1290.720000 2280.800000 1291.820000 2281.280000 ;
+ RECT 1290.720000 2286.240000 1291.820000 2286.720000 ;
+ RECT 1290.720000 2291.680000 1291.820000 2292.160000 ;
+ RECT 1290.720000 2297.120000 1291.820000 2297.600000 ;
+ RECT 1335.720000 2253.600000 1336.820000 2254.080000 ;
+ RECT 1335.720000 2259.040000 1336.820000 2259.520000 ;
+ RECT 1335.720000 2264.480000 1336.820000 2264.960000 ;
+ RECT 1335.720000 2269.920000 1336.820000 2270.400000 ;
+ RECT 1290.720000 2253.600000 1291.820000 2254.080000 ;
+ RECT 1290.720000 2259.040000 1291.820000 2259.520000 ;
+ RECT 1290.720000 2264.480000 1291.820000 2264.960000 ;
+ RECT 1290.720000 2269.920000 1291.820000 2270.400000 ;
+ RECT 1241.890000 2297.120000 1242.890000 2297.600000 ;
+ RECT 1245.555000 2297.120000 1246.820000 2297.600000 ;
+ RECT 1241.890000 2286.240000 1242.890000 2286.720000 ;
+ RECT 1245.555000 2286.240000 1246.820000 2286.720000 ;
+ RECT 1241.890000 2291.680000 1242.890000 2292.160000 ;
+ RECT 1245.555000 2291.680000 1246.820000 2292.160000 ;
+ RECT 1241.890000 2280.800000 1242.890000 2281.280000 ;
+ RECT 1245.555000 2280.800000 1246.820000 2281.280000 ;
+ RECT 1241.890000 2275.360000 1242.890000 2275.840000 ;
+ RECT 1245.555000 2275.360000 1246.820000 2275.840000 ;
+ RECT 1241.890000 2269.920000 1242.890000 2270.400000 ;
+ RECT 1245.555000 2269.920000 1246.820000 2270.400000 ;
+ RECT 1241.890000 2264.480000 1242.890000 2264.960000 ;
+ RECT 1245.555000 2264.480000 1246.820000 2264.960000 ;
+ RECT 1241.890000 2259.040000 1242.890000 2259.520000 ;
+ RECT 1245.555000 2259.040000 1246.820000 2259.520000 ;
+ RECT 1241.890000 2253.600000 1242.890000 2254.080000 ;
+ RECT 1245.555000 2253.600000 1246.820000 2254.080000 ;
+ RECT 1425.720000 2237.280000 1426.820000 2237.760000 ;
+ RECT 1425.720000 2242.720000 1426.820000 2243.200000 ;
+ RECT 1438.530000 2237.280000 1439.530000 2237.760000 ;
+ RECT 1438.530000 2242.720000 1439.530000 2243.200000 ;
+ RECT 1438.530000 2226.400000 1439.530000 2226.880000 ;
+ RECT 1438.530000 2231.840000 1439.530000 2232.320000 ;
+ RECT 1425.720000 2231.840000 1426.820000 2232.320000 ;
+ RECT 1425.720000 2226.400000 1426.820000 2226.880000 ;
+ RECT 1425.720000 2215.520000 1426.820000 2216.000000 ;
+ RECT 1425.720000 2220.960000 1426.820000 2221.440000 ;
+ RECT 1438.530000 2215.520000 1439.530000 2216.000000 ;
+ RECT 1438.530000 2220.960000 1439.530000 2221.440000 ;
+ RECT 1438.530000 2204.640000 1439.530000 2205.120000 ;
+ RECT 1438.530000 2199.200000 1439.530000 2199.680000 ;
+ RECT 1438.530000 2210.080000 1439.530000 2210.560000 ;
+ RECT 1425.720000 2210.080000 1426.820000 2210.560000 ;
+ RECT 1425.720000 2204.640000 1426.820000 2205.120000 ;
+ RECT 1425.720000 2199.200000 1426.820000 2199.680000 ;
+ RECT 1380.720000 2226.400000 1381.820000 2226.880000 ;
+ RECT 1380.720000 2231.840000 1381.820000 2232.320000 ;
+ RECT 1380.720000 2237.280000 1381.820000 2237.760000 ;
+ RECT 1380.720000 2242.720000 1381.820000 2243.200000 ;
+ RECT 1380.720000 2199.200000 1381.820000 2199.680000 ;
+ RECT 1380.720000 2204.640000 1381.820000 2205.120000 ;
+ RECT 1380.720000 2210.080000 1381.820000 2210.560000 ;
+ RECT 1380.720000 2215.520000 1381.820000 2216.000000 ;
+ RECT 1380.720000 2220.960000 1381.820000 2221.440000 ;
+ RECT 1425.720000 2188.320000 1426.820000 2188.800000 ;
+ RECT 1425.720000 2193.760000 1426.820000 2194.240000 ;
+ RECT 1438.530000 2188.320000 1439.530000 2188.800000 ;
+ RECT 1438.530000 2193.760000 1439.530000 2194.240000 ;
+ RECT 1425.720000 2177.440000 1426.820000 2177.920000 ;
+ RECT 1425.720000 2182.880000 1426.820000 2183.360000 ;
+ RECT 1438.530000 2177.440000 1439.530000 2177.920000 ;
+ RECT 1438.530000 2182.880000 1439.530000 2183.360000 ;
+ RECT 1438.530000 2166.560000 1439.530000 2167.040000 ;
+ RECT 1438.530000 2161.120000 1439.530000 2161.600000 ;
+ RECT 1438.530000 2172.000000 1439.530000 2172.480000 ;
+ RECT 1425.720000 2172.000000 1426.820000 2172.480000 ;
+ RECT 1425.720000 2166.560000 1426.820000 2167.040000 ;
+ RECT 1425.720000 2161.120000 1426.820000 2161.600000 ;
+ RECT 1425.720000 2155.680000 1426.820000 2156.160000 ;
+ RECT 1438.530000 2155.680000 1439.530000 2156.160000 ;
+ RECT 1380.720000 2177.440000 1381.820000 2177.920000 ;
+ RECT 1380.720000 2182.880000 1381.820000 2183.360000 ;
+ RECT 1380.720000 2188.320000 1381.820000 2188.800000 ;
+ RECT 1380.720000 2193.760000 1381.820000 2194.240000 ;
+ RECT 1380.720000 2155.680000 1381.820000 2156.160000 ;
+ RECT 1380.720000 2161.120000 1381.820000 2161.600000 ;
+ RECT 1380.720000 2166.560000 1381.820000 2167.040000 ;
+ RECT 1380.720000 2172.000000 1381.820000 2172.480000 ;
+ RECT 1335.720000 2226.400000 1336.820000 2226.880000 ;
+ RECT 1335.720000 2231.840000 1336.820000 2232.320000 ;
+ RECT 1335.720000 2237.280000 1336.820000 2237.760000 ;
+ RECT 1335.720000 2242.720000 1336.820000 2243.200000 ;
+ RECT 1290.720000 2226.400000 1291.820000 2226.880000 ;
+ RECT 1290.720000 2231.840000 1291.820000 2232.320000 ;
+ RECT 1290.720000 2237.280000 1291.820000 2237.760000 ;
+ RECT 1290.720000 2242.720000 1291.820000 2243.200000 ;
+ RECT 1335.720000 2199.200000 1336.820000 2199.680000 ;
+ RECT 1335.720000 2204.640000 1336.820000 2205.120000 ;
+ RECT 1335.720000 2210.080000 1336.820000 2210.560000 ;
+ RECT 1335.720000 2215.520000 1336.820000 2216.000000 ;
+ RECT 1335.720000 2220.960000 1336.820000 2221.440000 ;
+ RECT 1290.720000 2199.200000 1291.820000 2199.680000 ;
+ RECT 1290.720000 2204.640000 1291.820000 2205.120000 ;
+ RECT 1290.720000 2210.080000 1291.820000 2210.560000 ;
+ RECT 1290.720000 2215.520000 1291.820000 2216.000000 ;
+ RECT 1290.720000 2220.960000 1291.820000 2221.440000 ;
+ RECT 1241.890000 2242.720000 1242.890000 2243.200000 ;
+ RECT 1245.555000 2242.720000 1246.820000 2243.200000 ;
+ RECT 1241.890000 2237.280000 1242.890000 2237.760000 ;
+ RECT 1245.555000 2237.280000 1246.820000 2237.760000 ;
+ RECT 1241.890000 2231.840000 1242.890000 2232.320000 ;
+ RECT 1245.555000 2231.840000 1246.820000 2232.320000 ;
+ RECT 1241.890000 2226.400000 1242.890000 2226.880000 ;
+ RECT 1245.555000 2226.400000 1246.820000 2226.880000 ;
+ RECT 1241.890000 2220.960000 1242.890000 2221.440000 ;
+ RECT 1245.555000 2220.960000 1246.820000 2221.440000 ;
+ RECT 1241.890000 2215.520000 1242.890000 2216.000000 ;
+ RECT 1245.555000 2215.520000 1246.820000 2216.000000 ;
+ RECT 1241.890000 2204.640000 1242.890000 2205.120000 ;
+ RECT 1245.555000 2204.640000 1246.820000 2205.120000 ;
+ RECT 1241.890000 2210.080000 1242.890000 2210.560000 ;
+ RECT 1245.555000 2210.080000 1246.820000 2210.560000 ;
+ RECT 1241.890000 2199.200000 1242.890000 2199.680000 ;
+ RECT 1245.555000 2199.200000 1246.820000 2199.680000 ;
+ RECT 1335.720000 2177.440000 1336.820000 2177.920000 ;
+ RECT 1335.720000 2182.880000 1336.820000 2183.360000 ;
+ RECT 1335.720000 2188.320000 1336.820000 2188.800000 ;
+ RECT 1335.720000 2193.760000 1336.820000 2194.240000 ;
+ RECT 1290.720000 2177.440000 1291.820000 2177.920000 ;
+ RECT 1290.720000 2182.880000 1291.820000 2183.360000 ;
+ RECT 1290.720000 2188.320000 1291.820000 2188.800000 ;
+ RECT 1290.720000 2193.760000 1291.820000 2194.240000 ;
+ RECT 1335.720000 2155.680000 1336.820000 2156.160000 ;
+ RECT 1335.720000 2161.120000 1336.820000 2161.600000 ;
+ RECT 1335.720000 2166.560000 1336.820000 2167.040000 ;
+ RECT 1335.720000 2172.000000 1336.820000 2172.480000 ;
+ RECT 1290.720000 2155.680000 1291.820000 2156.160000 ;
+ RECT 1290.720000 2161.120000 1291.820000 2161.600000 ;
+ RECT 1290.720000 2166.560000 1291.820000 2167.040000 ;
+ RECT 1290.720000 2172.000000 1291.820000 2172.480000 ;
+ RECT 1241.890000 2193.760000 1242.890000 2194.240000 ;
+ RECT 1245.555000 2193.760000 1246.820000 2194.240000 ;
+ RECT 1241.890000 2188.320000 1242.890000 2188.800000 ;
+ RECT 1245.555000 2188.320000 1246.820000 2188.800000 ;
+ RECT 1241.890000 2182.880000 1242.890000 2183.360000 ;
+ RECT 1245.555000 2182.880000 1246.820000 2183.360000 ;
+ RECT 1241.890000 2177.440000 1242.890000 2177.920000 ;
+ RECT 1245.555000 2177.440000 1246.820000 2177.920000 ;
+ RECT 1241.890000 2172.000000 1242.890000 2172.480000 ;
+ RECT 1245.555000 2172.000000 1246.820000 2172.480000 ;
+ RECT 1241.890000 2161.120000 1242.890000 2161.600000 ;
+ RECT 1245.555000 2161.120000 1246.820000 2161.600000 ;
+ RECT 1241.890000 2166.560000 1242.890000 2167.040000 ;
+ RECT 1245.555000 2166.560000 1246.820000 2167.040000 ;
+ RECT 1241.890000 2155.680000 1242.890000 2156.160000 ;
+ RECT 1245.555000 2155.680000 1246.820000 2156.160000 ;
+ RECT 1380.720000 2248.160000 1381.820000 2248.640000 ;
+ RECT 1425.720000 2248.160000 1426.820000 2248.640000 ;
+ RECT 1438.530000 2248.160000 1439.530000 2248.640000 ;
+ RECT 1290.720000 2248.160000 1291.820000 2248.640000 ;
+ RECT 1335.720000 2248.160000 1336.820000 2248.640000 ;
+ RECT 1241.890000 2248.160000 1242.890000 2248.640000 ;
+ RECT 1245.555000 2248.160000 1246.820000 2248.640000 ;
+ RECT 1240.660000 2344.920000 1440.760000 2345.920000 ;
+ RECT 1240.660000 2149.350000 1440.760000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 2148.100000 1242.890000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 2347.360000 1242.890000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 2148.100000 1439.530000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 2347.360000 1439.530000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2149.350000 1241.660000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2149.350000 1440.760000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2344.920000 1241.660000 2345.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2344.920000 1440.760000 2345.920000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 2140.380000 1246.820000 2140.860000 ;
+ RECT 1245.555000 2129.500000 1246.820000 2129.980000 ;
+ RECT 1245.555000 2134.940000 1246.820000 2135.420000 ;
+ RECT 1245.555000 2124.060000 1246.820000 2124.540000 ;
+ RECT 1245.555000 2118.620000 1246.820000 2119.100000 ;
+ RECT 1245.555000 2113.180000 1246.820000 2113.660000 ;
+ RECT 1245.555000 2107.740000 1246.820000 2108.220000 ;
+ RECT 1245.555000 2102.300000 1246.820000 2102.780000 ;
+ RECT 1245.555000 2096.860000 1246.820000 2097.340000 ;
+ RECT 1245.555000 2085.980000 1246.820000 2086.460000 ;
+ RECT 1245.555000 2091.420000 1246.820000 2091.900000 ;
+ RECT 1245.555000 2080.540000 1246.820000 2081.020000 ;
+ RECT 1245.555000 2075.100000 1246.820000 2075.580000 ;
+ RECT 1245.555000 2069.660000 1246.820000 2070.140000 ;
+ RECT 1245.555000 2064.220000 1246.820000 2064.700000 ;
+ RECT 1245.555000 2058.780000 1246.820000 2059.260000 ;
+ RECT 1245.555000 2053.340000 1246.820000 2053.820000 ;
+ RECT 1245.555000 2042.460000 1246.820000 2042.940000 ;
+ RECT 1245.555000 2037.020000 1246.820000 2037.500000 ;
+ RECT 1245.555000 2031.580000 1246.820000 2032.060000 ;
+ RECT 1245.555000 2026.140000 1246.820000 2026.620000 ;
+ RECT 1245.555000 2020.700000 1246.820000 2021.180000 ;
+ RECT 1245.555000 2015.260000 1246.820000 2015.740000 ;
+ RECT 1245.555000 2004.380000 1246.820000 2004.860000 ;
+ RECT 1245.555000 2009.820000 1246.820000 2010.300000 ;
+ RECT 1245.555000 1998.940000 1246.820000 1999.420000 ;
+ RECT 1245.555000 1993.500000 1246.820000 1993.980000 ;
+ RECT 1245.555000 1988.060000 1246.820000 1988.540000 ;
+ RECT 1245.555000 1982.620000 1246.820000 1983.100000 ;
+ RECT 1245.555000 1977.180000 1246.820000 1977.660000 ;
+ RECT 1245.555000 1971.740000 1246.820000 1972.220000 ;
+ RECT 1245.555000 1960.860000 1246.820000 1961.340000 ;
+ RECT 1245.555000 1966.300000 1246.820000 1966.780000 ;
+ RECT 1245.555000 1955.420000 1246.820000 1955.900000 ;
+ RECT 1245.555000 2047.900000 1246.820000 2048.380000 ;
+ RECT 1425.720000 1949.090000 1426.820000 2145.660000 ;
+ RECT 1380.720000 1949.090000 1381.820000 2145.660000 ;
+ RECT 1438.530000 1947.840000 1439.530000 2148.100000 ;
+ RECT 1335.720000 1949.090000 1336.820000 2145.660000 ;
+ RECT 1290.720000 1949.090000 1291.820000 2145.660000 ;
+ RECT 1245.720000 1949.090000 1246.820000 2145.660000 ;
+ RECT 1241.890000 1947.840000 1242.890000 2148.100000 ;
+ LAYER met3 ;
+ RECT 1425.720000 2140.380000 1426.820000 2140.860000 ;
+ RECT 1438.530000 2140.380000 1439.530000 2140.860000 ;
+ RECT 1438.530000 2129.500000 1439.530000 2129.980000 ;
+ RECT 1438.530000 2124.060000 1439.530000 2124.540000 ;
+ RECT 1438.530000 2134.940000 1439.530000 2135.420000 ;
+ RECT 1425.720000 2134.940000 1426.820000 2135.420000 ;
+ RECT 1425.720000 2129.500000 1426.820000 2129.980000 ;
+ RECT 1425.720000 2124.060000 1426.820000 2124.540000 ;
+ RECT 1425.720000 2113.180000 1426.820000 2113.660000 ;
+ RECT 1425.720000 2118.620000 1426.820000 2119.100000 ;
+ RECT 1438.530000 2113.180000 1439.530000 2113.660000 ;
+ RECT 1438.530000 2118.620000 1439.530000 2119.100000 ;
+ RECT 1425.720000 2102.300000 1426.820000 2102.780000 ;
+ RECT 1425.720000 2107.740000 1426.820000 2108.220000 ;
+ RECT 1438.530000 2102.300000 1439.530000 2102.780000 ;
+ RECT 1438.530000 2107.740000 1439.530000 2108.220000 ;
+ RECT 1380.720000 2124.060000 1381.820000 2124.540000 ;
+ RECT 1380.720000 2129.500000 1381.820000 2129.980000 ;
+ RECT 1380.720000 2134.940000 1381.820000 2135.420000 ;
+ RECT 1380.720000 2140.380000 1381.820000 2140.860000 ;
+ RECT 1380.720000 2107.740000 1381.820000 2108.220000 ;
+ RECT 1380.720000 2102.300000 1381.820000 2102.780000 ;
+ RECT 1380.720000 2113.180000 1381.820000 2113.660000 ;
+ RECT 1380.720000 2118.620000 1381.820000 2119.100000 ;
+ RECT 1438.530000 2091.420000 1439.530000 2091.900000 ;
+ RECT 1438.530000 2085.980000 1439.530000 2086.460000 ;
+ RECT 1438.530000 2096.860000 1439.530000 2097.340000 ;
+ RECT 1425.720000 2096.860000 1426.820000 2097.340000 ;
+ RECT 1425.720000 2091.420000 1426.820000 2091.900000 ;
+ RECT 1425.720000 2085.980000 1426.820000 2086.460000 ;
+ RECT 1425.720000 2075.100000 1426.820000 2075.580000 ;
+ RECT 1425.720000 2080.540000 1426.820000 2081.020000 ;
+ RECT 1438.530000 2075.100000 1439.530000 2075.580000 ;
+ RECT 1438.530000 2080.540000 1439.530000 2081.020000 ;
+ RECT 1438.530000 2064.220000 1439.530000 2064.700000 ;
+ RECT 1438.530000 2069.660000 1439.530000 2070.140000 ;
+ RECT 1425.720000 2069.660000 1426.820000 2070.140000 ;
+ RECT 1425.720000 2064.220000 1426.820000 2064.700000 ;
+ RECT 1425.720000 2053.340000 1426.820000 2053.820000 ;
+ RECT 1425.720000 2058.780000 1426.820000 2059.260000 ;
+ RECT 1438.530000 2053.340000 1439.530000 2053.820000 ;
+ RECT 1438.530000 2058.780000 1439.530000 2059.260000 ;
+ RECT 1380.720000 2075.100000 1381.820000 2075.580000 ;
+ RECT 1380.720000 2080.540000 1381.820000 2081.020000 ;
+ RECT 1380.720000 2085.980000 1381.820000 2086.460000 ;
+ RECT 1380.720000 2091.420000 1381.820000 2091.900000 ;
+ RECT 1380.720000 2096.860000 1381.820000 2097.340000 ;
+ RECT 1380.720000 2053.340000 1381.820000 2053.820000 ;
+ RECT 1380.720000 2058.780000 1381.820000 2059.260000 ;
+ RECT 1380.720000 2064.220000 1381.820000 2064.700000 ;
+ RECT 1380.720000 2069.660000 1381.820000 2070.140000 ;
+ RECT 1335.720000 2129.500000 1336.820000 2129.980000 ;
+ RECT 1335.720000 2124.060000 1336.820000 2124.540000 ;
+ RECT 1335.720000 2134.940000 1336.820000 2135.420000 ;
+ RECT 1335.720000 2140.380000 1336.820000 2140.860000 ;
+ RECT 1290.720000 2124.060000 1291.820000 2124.540000 ;
+ RECT 1290.720000 2129.500000 1291.820000 2129.980000 ;
+ RECT 1290.720000 2134.940000 1291.820000 2135.420000 ;
+ RECT 1290.720000 2140.380000 1291.820000 2140.860000 ;
+ RECT 1335.720000 2102.300000 1336.820000 2102.780000 ;
+ RECT 1335.720000 2107.740000 1336.820000 2108.220000 ;
+ RECT 1335.720000 2113.180000 1336.820000 2113.660000 ;
+ RECT 1335.720000 2118.620000 1336.820000 2119.100000 ;
+ RECT 1290.720000 2102.300000 1291.820000 2102.780000 ;
+ RECT 1290.720000 2107.740000 1291.820000 2108.220000 ;
+ RECT 1290.720000 2113.180000 1291.820000 2113.660000 ;
+ RECT 1290.720000 2118.620000 1291.820000 2119.100000 ;
+ RECT 1241.890000 2140.380000 1242.890000 2140.860000 ;
+ RECT 1245.555000 2140.380000 1246.820000 2140.860000 ;
+ RECT 1241.890000 2129.500000 1242.890000 2129.980000 ;
+ RECT 1245.555000 2129.500000 1246.820000 2129.980000 ;
+ RECT 1241.890000 2134.940000 1242.890000 2135.420000 ;
+ RECT 1245.555000 2134.940000 1246.820000 2135.420000 ;
+ RECT 1241.890000 2124.060000 1242.890000 2124.540000 ;
+ RECT 1245.555000 2124.060000 1246.820000 2124.540000 ;
+ RECT 1241.890000 2118.620000 1242.890000 2119.100000 ;
+ RECT 1245.555000 2118.620000 1246.820000 2119.100000 ;
+ RECT 1241.890000 2113.180000 1242.890000 2113.660000 ;
+ RECT 1245.555000 2113.180000 1246.820000 2113.660000 ;
+ RECT 1241.890000 2107.740000 1242.890000 2108.220000 ;
+ RECT 1245.555000 2107.740000 1246.820000 2108.220000 ;
+ RECT 1241.890000 2102.300000 1242.890000 2102.780000 ;
+ RECT 1245.555000 2102.300000 1246.820000 2102.780000 ;
+ RECT 1335.720000 2075.100000 1336.820000 2075.580000 ;
+ RECT 1335.720000 2080.540000 1336.820000 2081.020000 ;
+ RECT 1335.720000 2085.980000 1336.820000 2086.460000 ;
+ RECT 1335.720000 2091.420000 1336.820000 2091.900000 ;
+ RECT 1335.720000 2096.860000 1336.820000 2097.340000 ;
+ RECT 1290.720000 2075.100000 1291.820000 2075.580000 ;
+ RECT 1290.720000 2080.540000 1291.820000 2081.020000 ;
+ RECT 1290.720000 2085.980000 1291.820000 2086.460000 ;
+ RECT 1290.720000 2091.420000 1291.820000 2091.900000 ;
+ RECT 1290.720000 2096.860000 1291.820000 2097.340000 ;
+ RECT 1335.720000 2053.340000 1336.820000 2053.820000 ;
+ RECT 1335.720000 2058.780000 1336.820000 2059.260000 ;
+ RECT 1335.720000 2064.220000 1336.820000 2064.700000 ;
+ RECT 1335.720000 2069.660000 1336.820000 2070.140000 ;
+ RECT 1290.720000 2053.340000 1291.820000 2053.820000 ;
+ RECT 1290.720000 2058.780000 1291.820000 2059.260000 ;
+ RECT 1290.720000 2064.220000 1291.820000 2064.700000 ;
+ RECT 1290.720000 2069.660000 1291.820000 2070.140000 ;
+ RECT 1241.890000 2096.860000 1242.890000 2097.340000 ;
+ RECT 1245.555000 2096.860000 1246.820000 2097.340000 ;
+ RECT 1241.890000 2085.980000 1242.890000 2086.460000 ;
+ RECT 1245.555000 2085.980000 1246.820000 2086.460000 ;
+ RECT 1241.890000 2091.420000 1242.890000 2091.900000 ;
+ RECT 1245.555000 2091.420000 1246.820000 2091.900000 ;
+ RECT 1241.890000 2080.540000 1242.890000 2081.020000 ;
+ RECT 1245.555000 2080.540000 1246.820000 2081.020000 ;
+ RECT 1241.890000 2075.100000 1242.890000 2075.580000 ;
+ RECT 1245.555000 2075.100000 1246.820000 2075.580000 ;
+ RECT 1241.890000 2069.660000 1242.890000 2070.140000 ;
+ RECT 1245.555000 2069.660000 1246.820000 2070.140000 ;
+ RECT 1241.890000 2064.220000 1242.890000 2064.700000 ;
+ RECT 1245.555000 2064.220000 1246.820000 2064.700000 ;
+ RECT 1241.890000 2058.780000 1242.890000 2059.260000 ;
+ RECT 1245.555000 2058.780000 1246.820000 2059.260000 ;
+ RECT 1241.890000 2053.340000 1242.890000 2053.820000 ;
+ RECT 1245.555000 2053.340000 1246.820000 2053.820000 ;
+ RECT 1425.720000 2037.020000 1426.820000 2037.500000 ;
+ RECT 1425.720000 2042.460000 1426.820000 2042.940000 ;
+ RECT 1438.530000 2037.020000 1439.530000 2037.500000 ;
+ RECT 1438.530000 2042.460000 1439.530000 2042.940000 ;
+ RECT 1438.530000 2026.140000 1439.530000 2026.620000 ;
+ RECT 1438.530000 2031.580000 1439.530000 2032.060000 ;
+ RECT 1425.720000 2031.580000 1426.820000 2032.060000 ;
+ RECT 1425.720000 2026.140000 1426.820000 2026.620000 ;
+ RECT 1425.720000 2015.260000 1426.820000 2015.740000 ;
+ RECT 1425.720000 2020.700000 1426.820000 2021.180000 ;
+ RECT 1438.530000 2015.260000 1439.530000 2015.740000 ;
+ RECT 1438.530000 2020.700000 1439.530000 2021.180000 ;
+ RECT 1438.530000 2004.380000 1439.530000 2004.860000 ;
+ RECT 1438.530000 1998.940000 1439.530000 1999.420000 ;
+ RECT 1438.530000 2009.820000 1439.530000 2010.300000 ;
+ RECT 1425.720000 2009.820000 1426.820000 2010.300000 ;
+ RECT 1425.720000 2004.380000 1426.820000 2004.860000 ;
+ RECT 1425.720000 1998.940000 1426.820000 1999.420000 ;
+ RECT 1380.720000 2026.140000 1381.820000 2026.620000 ;
+ RECT 1380.720000 2031.580000 1381.820000 2032.060000 ;
+ RECT 1380.720000 2037.020000 1381.820000 2037.500000 ;
+ RECT 1380.720000 2042.460000 1381.820000 2042.940000 ;
+ RECT 1380.720000 1998.940000 1381.820000 1999.420000 ;
+ RECT 1380.720000 2004.380000 1381.820000 2004.860000 ;
+ RECT 1380.720000 2009.820000 1381.820000 2010.300000 ;
+ RECT 1380.720000 2015.260000 1381.820000 2015.740000 ;
+ RECT 1380.720000 2020.700000 1381.820000 2021.180000 ;
+ RECT 1425.720000 1988.060000 1426.820000 1988.540000 ;
+ RECT 1425.720000 1993.500000 1426.820000 1993.980000 ;
+ RECT 1438.530000 1988.060000 1439.530000 1988.540000 ;
+ RECT 1438.530000 1993.500000 1439.530000 1993.980000 ;
+ RECT 1425.720000 1977.180000 1426.820000 1977.660000 ;
+ RECT 1425.720000 1982.620000 1426.820000 1983.100000 ;
+ RECT 1438.530000 1977.180000 1439.530000 1977.660000 ;
+ RECT 1438.530000 1982.620000 1439.530000 1983.100000 ;
+ RECT 1438.530000 1966.300000 1439.530000 1966.780000 ;
+ RECT 1438.530000 1960.860000 1439.530000 1961.340000 ;
+ RECT 1438.530000 1971.740000 1439.530000 1972.220000 ;
+ RECT 1425.720000 1971.740000 1426.820000 1972.220000 ;
+ RECT 1425.720000 1966.300000 1426.820000 1966.780000 ;
+ RECT 1425.720000 1960.860000 1426.820000 1961.340000 ;
+ RECT 1425.720000 1955.420000 1426.820000 1955.900000 ;
+ RECT 1438.530000 1955.420000 1439.530000 1955.900000 ;
+ RECT 1380.720000 1977.180000 1381.820000 1977.660000 ;
+ RECT 1380.720000 1982.620000 1381.820000 1983.100000 ;
+ RECT 1380.720000 1988.060000 1381.820000 1988.540000 ;
+ RECT 1380.720000 1993.500000 1381.820000 1993.980000 ;
+ RECT 1380.720000 1955.420000 1381.820000 1955.900000 ;
+ RECT 1380.720000 1960.860000 1381.820000 1961.340000 ;
+ RECT 1380.720000 1966.300000 1381.820000 1966.780000 ;
+ RECT 1380.720000 1971.740000 1381.820000 1972.220000 ;
+ RECT 1335.720000 2026.140000 1336.820000 2026.620000 ;
+ RECT 1335.720000 2031.580000 1336.820000 2032.060000 ;
+ RECT 1335.720000 2037.020000 1336.820000 2037.500000 ;
+ RECT 1335.720000 2042.460000 1336.820000 2042.940000 ;
+ RECT 1290.720000 2026.140000 1291.820000 2026.620000 ;
+ RECT 1290.720000 2031.580000 1291.820000 2032.060000 ;
+ RECT 1290.720000 2037.020000 1291.820000 2037.500000 ;
+ RECT 1290.720000 2042.460000 1291.820000 2042.940000 ;
+ RECT 1335.720000 1998.940000 1336.820000 1999.420000 ;
+ RECT 1335.720000 2004.380000 1336.820000 2004.860000 ;
+ RECT 1335.720000 2009.820000 1336.820000 2010.300000 ;
+ RECT 1335.720000 2015.260000 1336.820000 2015.740000 ;
+ RECT 1335.720000 2020.700000 1336.820000 2021.180000 ;
+ RECT 1290.720000 1998.940000 1291.820000 1999.420000 ;
+ RECT 1290.720000 2004.380000 1291.820000 2004.860000 ;
+ RECT 1290.720000 2009.820000 1291.820000 2010.300000 ;
+ RECT 1290.720000 2015.260000 1291.820000 2015.740000 ;
+ RECT 1290.720000 2020.700000 1291.820000 2021.180000 ;
+ RECT 1241.890000 2042.460000 1242.890000 2042.940000 ;
+ RECT 1245.555000 2042.460000 1246.820000 2042.940000 ;
+ RECT 1241.890000 2037.020000 1242.890000 2037.500000 ;
+ RECT 1245.555000 2037.020000 1246.820000 2037.500000 ;
+ RECT 1241.890000 2031.580000 1242.890000 2032.060000 ;
+ RECT 1245.555000 2031.580000 1246.820000 2032.060000 ;
+ RECT 1241.890000 2026.140000 1242.890000 2026.620000 ;
+ RECT 1245.555000 2026.140000 1246.820000 2026.620000 ;
+ RECT 1241.890000 2020.700000 1242.890000 2021.180000 ;
+ RECT 1245.555000 2020.700000 1246.820000 2021.180000 ;
+ RECT 1241.890000 2015.260000 1242.890000 2015.740000 ;
+ RECT 1245.555000 2015.260000 1246.820000 2015.740000 ;
+ RECT 1241.890000 2004.380000 1242.890000 2004.860000 ;
+ RECT 1245.555000 2004.380000 1246.820000 2004.860000 ;
+ RECT 1241.890000 2009.820000 1242.890000 2010.300000 ;
+ RECT 1245.555000 2009.820000 1246.820000 2010.300000 ;
+ RECT 1241.890000 1998.940000 1242.890000 1999.420000 ;
+ RECT 1245.555000 1998.940000 1246.820000 1999.420000 ;
+ RECT 1335.720000 1977.180000 1336.820000 1977.660000 ;
+ RECT 1335.720000 1982.620000 1336.820000 1983.100000 ;
+ RECT 1335.720000 1988.060000 1336.820000 1988.540000 ;
+ RECT 1335.720000 1993.500000 1336.820000 1993.980000 ;
+ RECT 1290.720000 1977.180000 1291.820000 1977.660000 ;
+ RECT 1290.720000 1982.620000 1291.820000 1983.100000 ;
+ RECT 1290.720000 1988.060000 1291.820000 1988.540000 ;
+ RECT 1290.720000 1993.500000 1291.820000 1993.980000 ;
+ RECT 1335.720000 1955.420000 1336.820000 1955.900000 ;
+ RECT 1335.720000 1960.860000 1336.820000 1961.340000 ;
+ RECT 1335.720000 1966.300000 1336.820000 1966.780000 ;
+ RECT 1335.720000 1971.740000 1336.820000 1972.220000 ;
+ RECT 1290.720000 1955.420000 1291.820000 1955.900000 ;
+ RECT 1290.720000 1960.860000 1291.820000 1961.340000 ;
+ RECT 1290.720000 1966.300000 1291.820000 1966.780000 ;
+ RECT 1290.720000 1971.740000 1291.820000 1972.220000 ;
+ RECT 1241.890000 1993.500000 1242.890000 1993.980000 ;
+ RECT 1245.555000 1993.500000 1246.820000 1993.980000 ;
+ RECT 1241.890000 1988.060000 1242.890000 1988.540000 ;
+ RECT 1245.555000 1988.060000 1246.820000 1988.540000 ;
+ RECT 1241.890000 1982.620000 1242.890000 1983.100000 ;
+ RECT 1245.555000 1982.620000 1246.820000 1983.100000 ;
+ RECT 1241.890000 1977.180000 1242.890000 1977.660000 ;
+ RECT 1245.555000 1977.180000 1246.820000 1977.660000 ;
+ RECT 1241.890000 1971.740000 1242.890000 1972.220000 ;
+ RECT 1245.555000 1971.740000 1246.820000 1972.220000 ;
+ RECT 1241.890000 1960.860000 1242.890000 1961.340000 ;
+ RECT 1245.555000 1960.860000 1246.820000 1961.340000 ;
+ RECT 1241.890000 1966.300000 1242.890000 1966.780000 ;
+ RECT 1245.555000 1966.300000 1246.820000 1966.780000 ;
+ RECT 1241.890000 1955.420000 1242.890000 1955.900000 ;
+ RECT 1245.555000 1955.420000 1246.820000 1955.900000 ;
+ RECT 1380.720000 2047.900000 1381.820000 2048.380000 ;
+ RECT 1425.720000 2047.900000 1426.820000 2048.380000 ;
+ RECT 1438.530000 2047.900000 1439.530000 2048.380000 ;
+ RECT 1290.720000 2047.900000 1291.820000 2048.380000 ;
+ RECT 1335.720000 2047.900000 1336.820000 2048.380000 ;
+ RECT 1241.890000 2047.900000 1242.890000 2048.380000 ;
+ RECT 1245.555000 2047.900000 1246.820000 2048.380000 ;
+ RECT 1240.660000 2144.660000 1440.760000 2145.660000 ;
+ RECT 1240.660000 1949.090000 1440.760000 1950.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 1947.840000 1242.890000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 2147.100000 1242.890000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 1947.840000 1439.530000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 2147.100000 1439.530000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1949.090000 1241.660000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1949.090000 1440.760000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2144.660000 1241.660000 2145.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2144.660000 1440.760000 2145.660000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 1940.120000 1246.820000 1940.600000 ;
+ RECT 1245.555000 1929.240000 1246.820000 1929.720000 ;
+ RECT 1245.555000 1934.680000 1246.820000 1935.160000 ;
+ RECT 1245.555000 1923.800000 1246.820000 1924.280000 ;
+ RECT 1245.555000 1918.360000 1246.820000 1918.840000 ;
+ RECT 1245.555000 1912.920000 1246.820000 1913.400000 ;
+ RECT 1245.555000 1907.480000 1246.820000 1907.960000 ;
+ RECT 1245.555000 1902.040000 1246.820000 1902.520000 ;
+ RECT 1245.555000 1896.600000 1246.820000 1897.080000 ;
+ RECT 1245.555000 1885.720000 1246.820000 1886.200000 ;
+ RECT 1245.555000 1891.160000 1246.820000 1891.640000 ;
+ RECT 1245.555000 1880.280000 1246.820000 1880.760000 ;
+ RECT 1245.555000 1874.840000 1246.820000 1875.320000 ;
+ RECT 1245.555000 1869.400000 1246.820000 1869.880000 ;
+ RECT 1245.555000 1863.960000 1246.820000 1864.440000 ;
+ RECT 1245.555000 1858.520000 1246.820000 1859.000000 ;
+ RECT 1245.555000 1853.080000 1246.820000 1853.560000 ;
+ RECT 1245.555000 1842.200000 1246.820000 1842.680000 ;
+ RECT 1245.555000 1836.760000 1246.820000 1837.240000 ;
+ RECT 1245.555000 1831.320000 1246.820000 1831.800000 ;
+ RECT 1245.555000 1825.880000 1246.820000 1826.360000 ;
+ RECT 1245.555000 1820.440000 1246.820000 1820.920000 ;
+ RECT 1245.555000 1815.000000 1246.820000 1815.480000 ;
+ RECT 1245.555000 1804.120000 1246.820000 1804.600000 ;
+ RECT 1245.555000 1809.560000 1246.820000 1810.040000 ;
+ RECT 1245.555000 1798.680000 1246.820000 1799.160000 ;
+ RECT 1245.555000 1793.240000 1246.820000 1793.720000 ;
+ RECT 1245.555000 1787.800000 1246.820000 1788.280000 ;
+ RECT 1245.555000 1782.360000 1246.820000 1782.840000 ;
+ RECT 1245.555000 1776.920000 1246.820000 1777.400000 ;
+ RECT 1245.555000 1771.480000 1246.820000 1771.960000 ;
+ RECT 1245.555000 1760.600000 1246.820000 1761.080000 ;
+ RECT 1245.555000 1766.040000 1246.820000 1766.520000 ;
+ RECT 1245.555000 1755.160000 1246.820000 1755.640000 ;
+ RECT 1245.555000 1847.640000 1246.820000 1848.120000 ;
+ RECT 1425.720000 1748.830000 1426.820000 1945.400000 ;
+ RECT 1380.720000 1748.830000 1381.820000 1945.400000 ;
+ RECT 1438.530000 1747.580000 1439.530000 1947.840000 ;
+ RECT 1335.720000 1748.830000 1336.820000 1945.400000 ;
+ RECT 1290.720000 1748.830000 1291.820000 1945.400000 ;
+ RECT 1245.720000 1748.830000 1246.820000 1945.400000 ;
+ RECT 1241.890000 1747.580000 1242.890000 1947.840000 ;
+ LAYER met3 ;
+ RECT 1425.720000 1940.120000 1426.820000 1940.600000 ;
+ RECT 1438.530000 1940.120000 1439.530000 1940.600000 ;
+ RECT 1438.530000 1929.240000 1439.530000 1929.720000 ;
+ RECT 1438.530000 1923.800000 1439.530000 1924.280000 ;
+ RECT 1438.530000 1934.680000 1439.530000 1935.160000 ;
+ RECT 1425.720000 1934.680000 1426.820000 1935.160000 ;
+ RECT 1425.720000 1929.240000 1426.820000 1929.720000 ;
+ RECT 1425.720000 1923.800000 1426.820000 1924.280000 ;
+ RECT 1425.720000 1912.920000 1426.820000 1913.400000 ;
+ RECT 1425.720000 1918.360000 1426.820000 1918.840000 ;
+ RECT 1438.530000 1912.920000 1439.530000 1913.400000 ;
+ RECT 1438.530000 1918.360000 1439.530000 1918.840000 ;
+ RECT 1425.720000 1902.040000 1426.820000 1902.520000 ;
+ RECT 1425.720000 1907.480000 1426.820000 1907.960000 ;
+ RECT 1438.530000 1902.040000 1439.530000 1902.520000 ;
+ RECT 1438.530000 1907.480000 1439.530000 1907.960000 ;
+ RECT 1380.720000 1923.800000 1381.820000 1924.280000 ;
+ RECT 1380.720000 1929.240000 1381.820000 1929.720000 ;
+ RECT 1380.720000 1934.680000 1381.820000 1935.160000 ;
+ RECT 1380.720000 1940.120000 1381.820000 1940.600000 ;
+ RECT 1380.720000 1907.480000 1381.820000 1907.960000 ;
+ RECT 1380.720000 1902.040000 1381.820000 1902.520000 ;
+ RECT 1380.720000 1912.920000 1381.820000 1913.400000 ;
+ RECT 1380.720000 1918.360000 1381.820000 1918.840000 ;
+ RECT 1438.530000 1891.160000 1439.530000 1891.640000 ;
+ RECT 1438.530000 1885.720000 1439.530000 1886.200000 ;
+ RECT 1438.530000 1896.600000 1439.530000 1897.080000 ;
+ RECT 1425.720000 1896.600000 1426.820000 1897.080000 ;
+ RECT 1425.720000 1891.160000 1426.820000 1891.640000 ;
+ RECT 1425.720000 1885.720000 1426.820000 1886.200000 ;
+ RECT 1425.720000 1874.840000 1426.820000 1875.320000 ;
+ RECT 1425.720000 1880.280000 1426.820000 1880.760000 ;
+ RECT 1438.530000 1874.840000 1439.530000 1875.320000 ;
+ RECT 1438.530000 1880.280000 1439.530000 1880.760000 ;
+ RECT 1438.530000 1863.960000 1439.530000 1864.440000 ;
+ RECT 1438.530000 1869.400000 1439.530000 1869.880000 ;
+ RECT 1425.720000 1869.400000 1426.820000 1869.880000 ;
+ RECT 1425.720000 1863.960000 1426.820000 1864.440000 ;
+ RECT 1425.720000 1853.080000 1426.820000 1853.560000 ;
+ RECT 1425.720000 1858.520000 1426.820000 1859.000000 ;
+ RECT 1438.530000 1853.080000 1439.530000 1853.560000 ;
+ RECT 1438.530000 1858.520000 1439.530000 1859.000000 ;
+ RECT 1380.720000 1874.840000 1381.820000 1875.320000 ;
+ RECT 1380.720000 1880.280000 1381.820000 1880.760000 ;
+ RECT 1380.720000 1885.720000 1381.820000 1886.200000 ;
+ RECT 1380.720000 1891.160000 1381.820000 1891.640000 ;
+ RECT 1380.720000 1896.600000 1381.820000 1897.080000 ;
+ RECT 1380.720000 1853.080000 1381.820000 1853.560000 ;
+ RECT 1380.720000 1858.520000 1381.820000 1859.000000 ;
+ RECT 1380.720000 1863.960000 1381.820000 1864.440000 ;
+ RECT 1380.720000 1869.400000 1381.820000 1869.880000 ;
+ RECT 1335.720000 1929.240000 1336.820000 1929.720000 ;
+ RECT 1335.720000 1923.800000 1336.820000 1924.280000 ;
+ RECT 1335.720000 1934.680000 1336.820000 1935.160000 ;
+ RECT 1335.720000 1940.120000 1336.820000 1940.600000 ;
+ RECT 1290.720000 1923.800000 1291.820000 1924.280000 ;
+ RECT 1290.720000 1929.240000 1291.820000 1929.720000 ;
+ RECT 1290.720000 1934.680000 1291.820000 1935.160000 ;
+ RECT 1290.720000 1940.120000 1291.820000 1940.600000 ;
+ RECT 1335.720000 1902.040000 1336.820000 1902.520000 ;
+ RECT 1335.720000 1907.480000 1336.820000 1907.960000 ;
+ RECT 1335.720000 1912.920000 1336.820000 1913.400000 ;
+ RECT 1335.720000 1918.360000 1336.820000 1918.840000 ;
+ RECT 1290.720000 1902.040000 1291.820000 1902.520000 ;
+ RECT 1290.720000 1907.480000 1291.820000 1907.960000 ;
+ RECT 1290.720000 1912.920000 1291.820000 1913.400000 ;
+ RECT 1290.720000 1918.360000 1291.820000 1918.840000 ;
+ RECT 1241.890000 1940.120000 1242.890000 1940.600000 ;
+ RECT 1245.555000 1940.120000 1246.820000 1940.600000 ;
+ RECT 1241.890000 1929.240000 1242.890000 1929.720000 ;
+ RECT 1245.555000 1929.240000 1246.820000 1929.720000 ;
+ RECT 1241.890000 1934.680000 1242.890000 1935.160000 ;
+ RECT 1245.555000 1934.680000 1246.820000 1935.160000 ;
+ RECT 1241.890000 1923.800000 1242.890000 1924.280000 ;
+ RECT 1245.555000 1923.800000 1246.820000 1924.280000 ;
+ RECT 1241.890000 1918.360000 1242.890000 1918.840000 ;
+ RECT 1245.555000 1918.360000 1246.820000 1918.840000 ;
+ RECT 1241.890000 1912.920000 1242.890000 1913.400000 ;
+ RECT 1245.555000 1912.920000 1246.820000 1913.400000 ;
+ RECT 1241.890000 1907.480000 1242.890000 1907.960000 ;
+ RECT 1245.555000 1907.480000 1246.820000 1907.960000 ;
+ RECT 1241.890000 1902.040000 1242.890000 1902.520000 ;
+ RECT 1245.555000 1902.040000 1246.820000 1902.520000 ;
+ RECT 1335.720000 1874.840000 1336.820000 1875.320000 ;
+ RECT 1335.720000 1880.280000 1336.820000 1880.760000 ;
+ RECT 1335.720000 1885.720000 1336.820000 1886.200000 ;
+ RECT 1335.720000 1891.160000 1336.820000 1891.640000 ;
+ RECT 1335.720000 1896.600000 1336.820000 1897.080000 ;
+ RECT 1290.720000 1874.840000 1291.820000 1875.320000 ;
+ RECT 1290.720000 1880.280000 1291.820000 1880.760000 ;
+ RECT 1290.720000 1885.720000 1291.820000 1886.200000 ;
+ RECT 1290.720000 1891.160000 1291.820000 1891.640000 ;
+ RECT 1290.720000 1896.600000 1291.820000 1897.080000 ;
+ RECT 1335.720000 1853.080000 1336.820000 1853.560000 ;
+ RECT 1335.720000 1858.520000 1336.820000 1859.000000 ;
+ RECT 1335.720000 1863.960000 1336.820000 1864.440000 ;
+ RECT 1335.720000 1869.400000 1336.820000 1869.880000 ;
+ RECT 1290.720000 1853.080000 1291.820000 1853.560000 ;
+ RECT 1290.720000 1858.520000 1291.820000 1859.000000 ;
+ RECT 1290.720000 1863.960000 1291.820000 1864.440000 ;
+ RECT 1290.720000 1869.400000 1291.820000 1869.880000 ;
+ RECT 1241.890000 1896.600000 1242.890000 1897.080000 ;
+ RECT 1245.555000 1896.600000 1246.820000 1897.080000 ;
+ RECT 1241.890000 1885.720000 1242.890000 1886.200000 ;
+ RECT 1245.555000 1885.720000 1246.820000 1886.200000 ;
+ RECT 1241.890000 1891.160000 1242.890000 1891.640000 ;
+ RECT 1245.555000 1891.160000 1246.820000 1891.640000 ;
+ RECT 1241.890000 1880.280000 1242.890000 1880.760000 ;
+ RECT 1245.555000 1880.280000 1246.820000 1880.760000 ;
+ RECT 1241.890000 1874.840000 1242.890000 1875.320000 ;
+ RECT 1245.555000 1874.840000 1246.820000 1875.320000 ;
+ RECT 1241.890000 1869.400000 1242.890000 1869.880000 ;
+ RECT 1245.555000 1869.400000 1246.820000 1869.880000 ;
+ RECT 1241.890000 1863.960000 1242.890000 1864.440000 ;
+ RECT 1245.555000 1863.960000 1246.820000 1864.440000 ;
+ RECT 1241.890000 1858.520000 1242.890000 1859.000000 ;
+ RECT 1245.555000 1858.520000 1246.820000 1859.000000 ;
+ RECT 1241.890000 1853.080000 1242.890000 1853.560000 ;
+ RECT 1245.555000 1853.080000 1246.820000 1853.560000 ;
+ RECT 1425.720000 1836.760000 1426.820000 1837.240000 ;
+ RECT 1425.720000 1842.200000 1426.820000 1842.680000 ;
+ RECT 1438.530000 1836.760000 1439.530000 1837.240000 ;
+ RECT 1438.530000 1842.200000 1439.530000 1842.680000 ;
+ RECT 1438.530000 1825.880000 1439.530000 1826.360000 ;
+ RECT 1438.530000 1831.320000 1439.530000 1831.800000 ;
+ RECT 1425.720000 1831.320000 1426.820000 1831.800000 ;
+ RECT 1425.720000 1825.880000 1426.820000 1826.360000 ;
+ RECT 1425.720000 1815.000000 1426.820000 1815.480000 ;
+ RECT 1425.720000 1820.440000 1426.820000 1820.920000 ;
+ RECT 1438.530000 1815.000000 1439.530000 1815.480000 ;
+ RECT 1438.530000 1820.440000 1439.530000 1820.920000 ;
+ RECT 1438.530000 1804.120000 1439.530000 1804.600000 ;
+ RECT 1438.530000 1798.680000 1439.530000 1799.160000 ;
+ RECT 1438.530000 1809.560000 1439.530000 1810.040000 ;
+ RECT 1425.720000 1809.560000 1426.820000 1810.040000 ;
+ RECT 1425.720000 1804.120000 1426.820000 1804.600000 ;
+ RECT 1425.720000 1798.680000 1426.820000 1799.160000 ;
+ RECT 1380.720000 1825.880000 1381.820000 1826.360000 ;
+ RECT 1380.720000 1831.320000 1381.820000 1831.800000 ;
+ RECT 1380.720000 1836.760000 1381.820000 1837.240000 ;
+ RECT 1380.720000 1842.200000 1381.820000 1842.680000 ;
+ RECT 1380.720000 1798.680000 1381.820000 1799.160000 ;
+ RECT 1380.720000 1804.120000 1381.820000 1804.600000 ;
+ RECT 1380.720000 1809.560000 1381.820000 1810.040000 ;
+ RECT 1380.720000 1815.000000 1381.820000 1815.480000 ;
+ RECT 1380.720000 1820.440000 1381.820000 1820.920000 ;
+ RECT 1425.720000 1787.800000 1426.820000 1788.280000 ;
+ RECT 1425.720000 1793.240000 1426.820000 1793.720000 ;
+ RECT 1438.530000 1787.800000 1439.530000 1788.280000 ;
+ RECT 1438.530000 1793.240000 1439.530000 1793.720000 ;
+ RECT 1425.720000 1776.920000 1426.820000 1777.400000 ;
+ RECT 1425.720000 1782.360000 1426.820000 1782.840000 ;
+ RECT 1438.530000 1776.920000 1439.530000 1777.400000 ;
+ RECT 1438.530000 1782.360000 1439.530000 1782.840000 ;
+ RECT 1438.530000 1766.040000 1439.530000 1766.520000 ;
+ RECT 1438.530000 1760.600000 1439.530000 1761.080000 ;
+ RECT 1438.530000 1771.480000 1439.530000 1771.960000 ;
+ RECT 1425.720000 1771.480000 1426.820000 1771.960000 ;
+ RECT 1425.720000 1766.040000 1426.820000 1766.520000 ;
+ RECT 1425.720000 1760.600000 1426.820000 1761.080000 ;
+ RECT 1425.720000 1755.160000 1426.820000 1755.640000 ;
+ RECT 1438.530000 1755.160000 1439.530000 1755.640000 ;
+ RECT 1380.720000 1776.920000 1381.820000 1777.400000 ;
+ RECT 1380.720000 1782.360000 1381.820000 1782.840000 ;
+ RECT 1380.720000 1787.800000 1381.820000 1788.280000 ;
+ RECT 1380.720000 1793.240000 1381.820000 1793.720000 ;
+ RECT 1380.720000 1755.160000 1381.820000 1755.640000 ;
+ RECT 1380.720000 1760.600000 1381.820000 1761.080000 ;
+ RECT 1380.720000 1766.040000 1381.820000 1766.520000 ;
+ RECT 1380.720000 1771.480000 1381.820000 1771.960000 ;
+ RECT 1335.720000 1825.880000 1336.820000 1826.360000 ;
+ RECT 1335.720000 1831.320000 1336.820000 1831.800000 ;
+ RECT 1335.720000 1836.760000 1336.820000 1837.240000 ;
+ RECT 1335.720000 1842.200000 1336.820000 1842.680000 ;
+ RECT 1290.720000 1825.880000 1291.820000 1826.360000 ;
+ RECT 1290.720000 1831.320000 1291.820000 1831.800000 ;
+ RECT 1290.720000 1836.760000 1291.820000 1837.240000 ;
+ RECT 1290.720000 1842.200000 1291.820000 1842.680000 ;
+ RECT 1335.720000 1798.680000 1336.820000 1799.160000 ;
+ RECT 1335.720000 1804.120000 1336.820000 1804.600000 ;
+ RECT 1335.720000 1809.560000 1336.820000 1810.040000 ;
+ RECT 1335.720000 1815.000000 1336.820000 1815.480000 ;
+ RECT 1335.720000 1820.440000 1336.820000 1820.920000 ;
+ RECT 1290.720000 1798.680000 1291.820000 1799.160000 ;
+ RECT 1290.720000 1804.120000 1291.820000 1804.600000 ;
+ RECT 1290.720000 1809.560000 1291.820000 1810.040000 ;
+ RECT 1290.720000 1815.000000 1291.820000 1815.480000 ;
+ RECT 1290.720000 1820.440000 1291.820000 1820.920000 ;
+ RECT 1241.890000 1842.200000 1242.890000 1842.680000 ;
+ RECT 1245.555000 1842.200000 1246.820000 1842.680000 ;
+ RECT 1241.890000 1836.760000 1242.890000 1837.240000 ;
+ RECT 1245.555000 1836.760000 1246.820000 1837.240000 ;
+ RECT 1241.890000 1831.320000 1242.890000 1831.800000 ;
+ RECT 1245.555000 1831.320000 1246.820000 1831.800000 ;
+ RECT 1241.890000 1825.880000 1242.890000 1826.360000 ;
+ RECT 1245.555000 1825.880000 1246.820000 1826.360000 ;
+ RECT 1241.890000 1820.440000 1242.890000 1820.920000 ;
+ RECT 1245.555000 1820.440000 1246.820000 1820.920000 ;
+ RECT 1241.890000 1815.000000 1242.890000 1815.480000 ;
+ RECT 1245.555000 1815.000000 1246.820000 1815.480000 ;
+ RECT 1241.890000 1804.120000 1242.890000 1804.600000 ;
+ RECT 1245.555000 1804.120000 1246.820000 1804.600000 ;
+ RECT 1241.890000 1809.560000 1242.890000 1810.040000 ;
+ RECT 1245.555000 1809.560000 1246.820000 1810.040000 ;
+ RECT 1241.890000 1798.680000 1242.890000 1799.160000 ;
+ RECT 1245.555000 1798.680000 1246.820000 1799.160000 ;
+ RECT 1335.720000 1776.920000 1336.820000 1777.400000 ;
+ RECT 1335.720000 1782.360000 1336.820000 1782.840000 ;
+ RECT 1335.720000 1787.800000 1336.820000 1788.280000 ;
+ RECT 1335.720000 1793.240000 1336.820000 1793.720000 ;
+ RECT 1290.720000 1776.920000 1291.820000 1777.400000 ;
+ RECT 1290.720000 1782.360000 1291.820000 1782.840000 ;
+ RECT 1290.720000 1787.800000 1291.820000 1788.280000 ;
+ RECT 1290.720000 1793.240000 1291.820000 1793.720000 ;
+ RECT 1335.720000 1755.160000 1336.820000 1755.640000 ;
+ RECT 1335.720000 1760.600000 1336.820000 1761.080000 ;
+ RECT 1335.720000 1766.040000 1336.820000 1766.520000 ;
+ RECT 1335.720000 1771.480000 1336.820000 1771.960000 ;
+ RECT 1290.720000 1755.160000 1291.820000 1755.640000 ;
+ RECT 1290.720000 1760.600000 1291.820000 1761.080000 ;
+ RECT 1290.720000 1766.040000 1291.820000 1766.520000 ;
+ RECT 1290.720000 1771.480000 1291.820000 1771.960000 ;
+ RECT 1241.890000 1793.240000 1242.890000 1793.720000 ;
+ RECT 1245.555000 1793.240000 1246.820000 1793.720000 ;
+ RECT 1241.890000 1787.800000 1242.890000 1788.280000 ;
+ RECT 1245.555000 1787.800000 1246.820000 1788.280000 ;
+ RECT 1241.890000 1782.360000 1242.890000 1782.840000 ;
+ RECT 1245.555000 1782.360000 1246.820000 1782.840000 ;
+ RECT 1241.890000 1776.920000 1242.890000 1777.400000 ;
+ RECT 1245.555000 1776.920000 1246.820000 1777.400000 ;
+ RECT 1241.890000 1771.480000 1242.890000 1771.960000 ;
+ RECT 1245.555000 1771.480000 1246.820000 1771.960000 ;
+ RECT 1241.890000 1760.600000 1242.890000 1761.080000 ;
+ RECT 1245.555000 1760.600000 1246.820000 1761.080000 ;
+ RECT 1241.890000 1766.040000 1242.890000 1766.520000 ;
+ RECT 1245.555000 1766.040000 1246.820000 1766.520000 ;
+ RECT 1241.890000 1755.160000 1242.890000 1755.640000 ;
+ RECT 1245.555000 1755.160000 1246.820000 1755.640000 ;
+ RECT 1380.720000 1847.640000 1381.820000 1848.120000 ;
+ RECT 1425.720000 1847.640000 1426.820000 1848.120000 ;
+ RECT 1438.530000 1847.640000 1439.530000 1848.120000 ;
+ RECT 1290.720000 1847.640000 1291.820000 1848.120000 ;
+ RECT 1335.720000 1847.640000 1336.820000 1848.120000 ;
+ RECT 1241.890000 1847.640000 1242.890000 1848.120000 ;
+ RECT 1245.555000 1847.640000 1246.820000 1848.120000 ;
+ RECT 1240.660000 1944.400000 1440.760000 1945.400000 ;
+ RECT 1240.660000 1748.830000 1440.760000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 1747.580000 1242.890000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 1946.840000 1242.890000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 1747.580000 1439.530000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 1946.840000 1439.530000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1748.830000 1241.660000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1748.830000 1440.760000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1944.400000 1241.660000 1945.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1944.400000 1440.760000 1945.400000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1245.555000 1739.860000 1246.820000 1740.340000 ;
+ RECT 1245.555000 1728.980000 1246.820000 1729.460000 ;
+ RECT 1245.555000 1734.420000 1246.820000 1734.900000 ;
+ RECT 1245.555000 1723.540000 1246.820000 1724.020000 ;
+ RECT 1245.555000 1718.100000 1246.820000 1718.580000 ;
+ RECT 1245.555000 1712.660000 1246.820000 1713.140000 ;
+ RECT 1245.555000 1707.220000 1246.820000 1707.700000 ;
+ RECT 1245.555000 1701.780000 1246.820000 1702.260000 ;
+ RECT 1245.555000 1696.340000 1246.820000 1696.820000 ;
+ RECT 1245.555000 1685.460000 1246.820000 1685.940000 ;
+ RECT 1245.555000 1690.900000 1246.820000 1691.380000 ;
+ RECT 1245.555000 1680.020000 1246.820000 1680.500000 ;
+ RECT 1245.555000 1674.580000 1246.820000 1675.060000 ;
+ RECT 1245.555000 1669.140000 1246.820000 1669.620000 ;
+ RECT 1245.555000 1663.700000 1246.820000 1664.180000 ;
+ RECT 1245.555000 1658.260000 1246.820000 1658.740000 ;
+ RECT 1245.555000 1652.820000 1246.820000 1653.300000 ;
+ RECT 1245.555000 1641.940000 1246.820000 1642.420000 ;
+ RECT 1245.555000 1636.500000 1246.820000 1636.980000 ;
+ RECT 1245.555000 1631.060000 1246.820000 1631.540000 ;
+ RECT 1245.555000 1625.620000 1246.820000 1626.100000 ;
+ RECT 1245.555000 1620.180000 1246.820000 1620.660000 ;
+ RECT 1245.555000 1614.740000 1246.820000 1615.220000 ;
+ RECT 1245.555000 1603.860000 1246.820000 1604.340000 ;
+ RECT 1245.555000 1609.300000 1246.820000 1609.780000 ;
+ RECT 1245.555000 1598.420000 1246.820000 1598.900000 ;
+ RECT 1245.555000 1592.980000 1246.820000 1593.460000 ;
+ RECT 1245.555000 1587.540000 1246.820000 1588.020000 ;
+ RECT 1245.555000 1582.100000 1246.820000 1582.580000 ;
+ RECT 1245.555000 1576.660000 1246.820000 1577.140000 ;
+ RECT 1245.555000 1571.220000 1246.820000 1571.700000 ;
+ RECT 1245.555000 1560.340000 1246.820000 1560.820000 ;
+ RECT 1245.555000 1565.780000 1246.820000 1566.260000 ;
+ RECT 1245.555000 1554.900000 1246.820000 1555.380000 ;
+ RECT 1245.555000 1647.380000 1246.820000 1647.860000 ;
+ RECT 1425.720000 1548.570000 1426.820000 1745.140000 ;
+ RECT 1380.720000 1548.570000 1381.820000 1745.140000 ;
+ RECT 1438.530000 1547.320000 1439.530000 1747.580000 ;
+ RECT 1335.720000 1548.570000 1336.820000 1745.140000 ;
+ RECT 1290.720000 1548.570000 1291.820000 1745.140000 ;
+ RECT 1245.720000 1548.570000 1246.820000 1745.140000 ;
+ RECT 1241.890000 1547.320000 1242.890000 1747.580000 ;
+ LAYER met3 ;
+ RECT 1425.720000 1739.860000 1426.820000 1740.340000 ;
+ RECT 1438.530000 1739.860000 1439.530000 1740.340000 ;
+ RECT 1438.530000 1728.980000 1439.530000 1729.460000 ;
+ RECT 1438.530000 1723.540000 1439.530000 1724.020000 ;
+ RECT 1438.530000 1734.420000 1439.530000 1734.900000 ;
+ RECT 1425.720000 1734.420000 1426.820000 1734.900000 ;
+ RECT 1425.720000 1728.980000 1426.820000 1729.460000 ;
+ RECT 1425.720000 1723.540000 1426.820000 1724.020000 ;
+ RECT 1425.720000 1712.660000 1426.820000 1713.140000 ;
+ RECT 1425.720000 1718.100000 1426.820000 1718.580000 ;
+ RECT 1438.530000 1712.660000 1439.530000 1713.140000 ;
+ RECT 1438.530000 1718.100000 1439.530000 1718.580000 ;
+ RECT 1425.720000 1701.780000 1426.820000 1702.260000 ;
+ RECT 1425.720000 1707.220000 1426.820000 1707.700000 ;
+ RECT 1438.530000 1701.780000 1439.530000 1702.260000 ;
+ RECT 1438.530000 1707.220000 1439.530000 1707.700000 ;
+ RECT 1380.720000 1723.540000 1381.820000 1724.020000 ;
+ RECT 1380.720000 1728.980000 1381.820000 1729.460000 ;
+ RECT 1380.720000 1734.420000 1381.820000 1734.900000 ;
+ RECT 1380.720000 1739.860000 1381.820000 1740.340000 ;
+ RECT 1380.720000 1707.220000 1381.820000 1707.700000 ;
+ RECT 1380.720000 1701.780000 1381.820000 1702.260000 ;
+ RECT 1380.720000 1712.660000 1381.820000 1713.140000 ;
+ RECT 1380.720000 1718.100000 1381.820000 1718.580000 ;
+ RECT 1438.530000 1690.900000 1439.530000 1691.380000 ;
+ RECT 1438.530000 1685.460000 1439.530000 1685.940000 ;
+ RECT 1438.530000 1696.340000 1439.530000 1696.820000 ;
+ RECT 1425.720000 1696.340000 1426.820000 1696.820000 ;
+ RECT 1425.720000 1690.900000 1426.820000 1691.380000 ;
+ RECT 1425.720000 1685.460000 1426.820000 1685.940000 ;
+ RECT 1425.720000 1674.580000 1426.820000 1675.060000 ;
+ RECT 1425.720000 1680.020000 1426.820000 1680.500000 ;
+ RECT 1438.530000 1674.580000 1439.530000 1675.060000 ;
+ RECT 1438.530000 1680.020000 1439.530000 1680.500000 ;
+ RECT 1438.530000 1663.700000 1439.530000 1664.180000 ;
+ RECT 1438.530000 1669.140000 1439.530000 1669.620000 ;
+ RECT 1425.720000 1669.140000 1426.820000 1669.620000 ;
+ RECT 1425.720000 1663.700000 1426.820000 1664.180000 ;
+ RECT 1425.720000 1652.820000 1426.820000 1653.300000 ;
+ RECT 1425.720000 1658.260000 1426.820000 1658.740000 ;
+ RECT 1438.530000 1652.820000 1439.530000 1653.300000 ;
+ RECT 1438.530000 1658.260000 1439.530000 1658.740000 ;
+ RECT 1380.720000 1674.580000 1381.820000 1675.060000 ;
+ RECT 1380.720000 1680.020000 1381.820000 1680.500000 ;
+ RECT 1380.720000 1685.460000 1381.820000 1685.940000 ;
+ RECT 1380.720000 1690.900000 1381.820000 1691.380000 ;
+ RECT 1380.720000 1696.340000 1381.820000 1696.820000 ;
+ RECT 1380.720000 1652.820000 1381.820000 1653.300000 ;
+ RECT 1380.720000 1658.260000 1381.820000 1658.740000 ;
+ RECT 1380.720000 1663.700000 1381.820000 1664.180000 ;
+ RECT 1380.720000 1669.140000 1381.820000 1669.620000 ;
+ RECT 1335.720000 1728.980000 1336.820000 1729.460000 ;
+ RECT 1335.720000 1723.540000 1336.820000 1724.020000 ;
+ RECT 1335.720000 1734.420000 1336.820000 1734.900000 ;
+ RECT 1335.720000 1739.860000 1336.820000 1740.340000 ;
+ RECT 1290.720000 1723.540000 1291.820000 1724.020000 ;
+ RECT 1290.720000 1728.980000 1291.820000 1729.460000 ;
+ RECT 1290.720000 1734.420000 1291.820000 1734.900000 ;
+ RECT 1290.720000 1739.860000 1291.820000 1740.340000 ;
+ RECT 1335.720000 1701.780000 1336.820000 1702.260000 ;
+ RECT 1335.720000 1707.220000 1336.820000 1707.700000 ;
+ RECT 1335.720000 1712.660000 1336.820000 1713.140000 ;
+ RECT 1335.720000 1718.100000 1336.820000 1718.580000 ;
+ RECT 1290.720000 1701.780000 1291.820000 1702.260000 ;
+ RECT 1290.720000 1707.220000 1291.820000 1707.700000 ;
+ RECT 1290.720000 1712.660000 1291.820000 1713.140000 ;
+ RECT 1290.720000 1718.100000 1291.820000 1718.580000 ;
+ RECT 1241.890000 1739.860000 1242.890000 1740.340000 ;
+ RECT 1245.555000 1739.860000 1246.820000 1740.340000 ;
+ RECT 1241.890000 1728.980000 1242.890000 1729.460000 ;
+ RECT 1245.555000 1728.980000 1246.820000 1729.460000 ;
+ RECT 1241.890000 1734.420000 1242.890000 1734.900000 ;
+ RECT 1245.555000 1734.420000 1246.820000 1734.900000 ;
+ RECT 1241.890000 1723.540000 1242.890000 1724.020000 ;
+ RECT 1245.555000 1723.540000 1246.820000 1724.020000 ;
+ RECT 1241.890000 1718.100000 1242.890000 1718.580000 ;
+ RECT 1245.555000 1718.100000 1246.820000 1718.580000 ;
+ RECT 1241.890000 1712.660000 1242.890000 1713.140000 ;
+ RECT 1245.555000 1712.660000 1246.820000 1713.140000 ;
+ RECT 1241.890000 1707.220000 1242.890000 1707.700000 ;
+ RECT 1245.555000 1707.220000 1246.820000 1707.700000 ;
+ RECT 1241.890000 1701.780000 1242.890000 1702.260000 ;
+ RECT 1245.555000 1701.780000 1246.820000 1702.260000 ;
+ RECT 1335.720000 1674.580000 1336.820000 1675.060000 ;
+ RECT 1335.720000 1680.020000 1336.820000 1680.500000 ;
+ RECT 1335.720000 1685.460000 1336.820000 1685.940000 ;
+ RECT 1335.720000 1690.900000 1336.820000 1691.380000 ;
+ RECT 1335.720000 1696.340000 1336.820000 1696.820000 ;
+ RECT 1290.720000 1674.580000 1291.820000 1675.060000 ;
+ RECT 1290.720000 1680.020000 1291.820000 1680.500000 ;
+ RECT 1290.720000 1685.460000 1291.820000 1685.940000 ;
+ RECT 1290.720000 1690.900000 1291.820000 1691.380000 ;
+ RECT 1290.720000 1696.340000 1291.820000 1696.820000 ;
+ RECT 1335.720000 1652.820000 1336.820000 1653.300000 ;
+ RECT 1335.720000 1658.260000 1336.820000 1658.740000 ;
+ RECT 1335.720000 1663.700000 1336.820000 1664.180000 ;
+ RECT 1335.720000 1669.140000 1336.820000 1669.620000 ;
+ RECT 1290.720000 1652.820000 1291.820000 1653.300000 ;
+ RECT 1290.720000 1658.260000 1291.820000 1658.740000 ;
+ RECT 1290.720000 1663.700000 1291.820000 1664.180000 ;
+ RECT 1290.720000 1669.140000 1291.820000 1669.620000 ;
+ RECT 1241.890000 1696.340000 1242.890000 1696.820000 ;
+ RECT 1245.555000 1696.340000 1246.820000 1696.820000 ;
+ RECT 1241.890000 1685.460000 1242.890000 1685.940000 ;
+ RECT 1245.555000 1685.460000 1246.820000 1685.940000 ;
+ RECT 1241.890000 1690.900000 1242.890000 1691.380000 ;
+ RECT 1245.555000 1690.900000 1246.820000 1691.380000 ;
+ RECT 1241.890000 1680.020000 1242.890000 1680.500000 ;
+ RECT 1245.555000 1680.020000 1246.820000 1680.500000 ;
+ RECT 1241.890000 1674.580000 1242.890000 1675.060000 ;
+ RECT 1245.555000 1674.580000 1246.820000 1675.060000 ;
+ RECT 1241.890000 1669.140000 1242.890000 1669.620000 ;
+ RECT 1245.555000 1669.140000 1246.820000 1669.620000 ;
+ RECT 1241.890000 1663.700000 1242.890000 1664.180000 ;
+ RECT 1245.555000 1663.700000 1246.820000 1664.180000 ;
+ RECT 1241.890000 1658.260000 1242.890000 1658.740000 ;
+ RECT 1245.555000 1658.260000 1246.820000 1658.740000 ;
+ RECT 1241.890000 1652.820000 1242.890000 1653.300000 ;
+ RECT 1245.555000 1652.820000 1246.820000 1653.300000 ;
+ RECT 1425.720000 1636.500000 1426.820000 1636.980000 ;
+ RECT 1425.720000 1641.940000 1426.820000 1642.420000 ;
+ RECT 1438.530000 1636.500000 1439.530000 1636.980000 ;
+ RECT 1438.530000 1641.940000 1439.530000 1642.420000 ;
+ RECT 1438.530000 1625.620000 1439.530000 1626.100000 ;
+ RECT 1438.530000 1631.060000 1439.530000 1631.540000 ;
+ RECT 1425.720000 1631.060000 1426.820000 1631.540000 ;
+ RECT 1425.720000 1625.620000 1426.820000 1626.100000 ;
+ RECT 1425.720000 1614.740000 1426.820000 1615.220000 ;
+ RECT 1425.720000 1620.180000 1426.820000 1620.660000 ;
+ RECT 1438.530000 1614.740000 1439.530000 1615.220000 ;
+ RECT 1438.530000 1620.180000 1439.530000 1620.660000 ;
+ RECT 1438.530000 1603.860000 1439.530000 1604.340000 ;
+ RECT 1438.530000 1598.420000 1439.530000 1598.900000 ;
+ RECT 1438.530000 1609.300000 1439.530000 1609.780000 ;
+ RECT 1425.720000 1609.300000 1426.820000 1609.780000 ;
+ RECT 1425.720000 1603.860000 1426.820000 1604.340000 ;
+ RECT 1425.720000 1598.420000 1426.820000 1598.900000 ;
+ RECT 1380.720000 1625.620000 1381.820000 1626.100000 ;
+ RECT 1380.720000 1631.060000 1381.820000 1631.540000 ;
+ RECT 1380.720000 1636.500000 1381.820000 1636.980000 ;
+ RECT 1380.720000 1641.940000 1381.820000 1642.420000 ;
+ RECT 1380.720000 1598.420000 1381.820000 1598.900000 ;
+ RECT 1380.720000 1603.860000 1381.820000 1604.340000 ;
+ RECT 1380.720000 1609.300000 1381.820000 1609.780000 ;
+ RECT 1380.720000 1614.740000 1381.820000 1615.220000 ;
+ RECT 1380.720000 1620.180000 1381.820000 1620.660000 ;
+ RECT 1425.720000 1587.540000 1426.820000 1588.020000 ;
+ RECT 1425.720000 1592.980000 1426.820000 1593.460000 ;
+ RECT 1438.530000 1587.540000 1439.530000 1588.020000 ;
+ RECT 1438.530000 1592.980000 1439.530000 1593.460000 ;
+ RECT 1425.720000 1576.660000 1426.820000 1577.140000 ;
+ RECT 1425.720000 1582.100000 1426.820000 1582.580000 ;
+ RECT 1438.530000 1576.660000 1439.530000 1577.140000 ;
+ RECT 1438.530000 1582.100000 1439.530000 1582.580000 ;
+ RECT 1438.530000 1565.780000 1439.530000 1566.260000 ;
+ RECT 1438.530000 1560.340000 1439.530000 1560.820000 ;
+ RECT 1438.530000 1571.220000 1439.530000 1571.700000 ;
+ RECT 1425.720000 1571.220000 1426.820000 1571.700000 ;
+ RECT 1425.720000 1565.780000 1426.820000 1566.260000 ;
+ RECT 1425.720000 1560.340000 1426.820000 1560.820000 ;
+ RECT 1425.720000 1554.900000 1426.820000 1555.380000 ;
+ RECT 1438.530000 1554.900000 1439.530000 1555.380000 ;
+ RECT 1380.720000 1576.660000 1381.820000 1577.140000 ;
+ RECT 1380.720000 1582.100000 1381.820000 1582.580000 ;
+ RECT 1380.720000 1587.540000 1381.820000 1588.020000 ;
+ RECT 1380.720000 1592.980000 1381.820000 1593.460000 ;
+ RECT 1380.720000 1554.900000 1381.820000 1555.380000 ;
+ RECT 1380.720000 1560.340000 1381.820000 1560.820000 ;
+ RECT 1380.720000 1565.780000 1381.820000 1566.260000 ;
+ RECT 1380.720000 1571.220000 1381.820000 1571.700000 ;
+ RECT 1335.720000 1625.620000 1336.820000 1626.100000 ;
+ RECT 1335.720000 1631.060000 1336.820000 1631.540000 ;
+ RECT 1335.720000 1636.500000 1336.820000 1636.980000 ;
+ RECT 1335.720000 1641.940000 1336.820000 1642.420000 ;
+ RECT 1290.720000 1625.620000 1291.820000 1626.100000 ;
+ RECT 1290.720000 1631.060000 1291.820000 1631.540000 ;
+ RECT 1290.720000 1636.500000 1291.820000 1636.980000 ;
+ RECT 1290.720000 1641.940000 1291.820000 1642.420000 ;
+ RECT 1335.720000 1598.420000 1336.820000 1598.900000 ;
+ RECT 1335.720000 1603.860000 1336.820000 1604.340000 ;
+ RECT 1335.720000 1609.300000 1336.820000 1609.780000 ;
+ RECT 1335.720000 1614.740000 1336.820000 1615.220000 ;
+ RECT 1335.720000 1620.180000 1336.820000 1620.660000 ;
+ RECT 1290.720000 1598.420000 1291.820000 1598.900000 ;
+ RECT 1290.720000 1603.860000 1291.820000 1604.340000 ;
+ RECT 1290.720000 1609.300000 1291.820000 1609.780000 ;
+ RECT 1290.720000 1614.740000 1291.820000 1615.220000 ;
+ RECT 1290.720000 1620.180000 1291.820000 1620.660000 ;
+ RECT 1241.890000 1641.940000 1242.890000 1642.420000 ;
+ RECT 1245.555000 1641.940000 1246.820000 1642.420000 ;
+ RECT 1241.890000 1636.500000 1242.890000 1636.980000 ;
+ RECT 1245.555000 1636.500000 1246.820000 1636.980000 ;
+ RECT 1241.890000 1631.060000 1242.890000 1631.540000 ;
+ RECT 1245.555000 1631.060000 1246.820000 1631.540000 ;
+ RECT 1241.890000 1625.620000 1242.890000 1626.100000 ;
+ RECT 1245.555000 1625.620000 1246.820000 1626.100000 ;
+ RECT 1241.890000 1620.180000 1242.890000 1620.660000 ;
+ RECT 1245.555000 1620.180000 1246.820000 1620.660000 ;
+ RECT 1241.890000 1614.740000 1242.890000 1615.220000 ;
+ RECT 1245.555000 1614.740000 1246.820000 1615.220000 ;
+ RECT 1241.890000 1603.860000 1242.890000 1604.340000 ;
+ RECT 1245.555000 1603.860000 1246.820000 1604.340000 ;
+ RECT 1241.890000 1609.300000 1242.890000 1609.780000 ;
+ RECT 1245.555000 1609.300000 1246.820000 1609.780000 ;
+ RECT 1241.890000 1598.420000 1242.890000 1598.900000 ;
+ RECT 1245.555000 1598.420000 1246.820000 1598.900000 ;
+ RECT 1335.720000 1576.660000 1336.820000 1577.140000 ;
+ RECT 1335.720000 1582.100000 1336.820000 1582.580000 ;
+ RECT 1335.720000 1587.540000 1336.820000 1588.020000 ;
+ RECT 1335.720000 1592.980000 1336.820000 1593.460000 ;
+ RECT 1290.720000 1576.660000 1291.820000 1577.140000 ;
+ RECT 1290.720000 1582.100000 1291.820000 1582.580000 ;
+ RECT 1290.720000 1587.540000 1291.820000 1588.020000 ;
+ RECT 1290.720000 1592.980000 1291.820000 1593.460000 ;
+ RECT 1335.720000 1554.900000 1336.820000 1555.380000 ;
+ RECT 1335.720000 1560.340000 1336.820000 1560.820000 ;
+ RECT 1335.720000 1565.780000 1336.820000 1566.260000 ;
+ RECT 1335.720000 1571.220000 1336.820000 1571.700000 ;
+ RECT 1290.720000 1554.900000 1291.820000 1555.380000 ;
+ RECT 1290.720000 1560.340000 1291.820000 1560.820000 ;
+ RECT 1290.720000 1565.780000 1291.820000 1566.260000 ;
+ RECT 1290.720000 1571.220000 1291.820000 1571.700000 ;
+ RECT 1241.890000 1592.980000 1242.890000 1593.460000 ;
+ RECT 1245.555000 1592.980000 1246.820000 1593.460000 ;
+ RECT 1241.890000 1587.540000 1242.890000 1588.020000 ;
+ RECT 1245.555000 1587.540000 1246.820000 1588.020000 ;
+ RECT 1241.890000 1582.100000 1242.890000 1582.580000 ;
+ RECT 1245.555000 1582.100000 1246.820000 1582.580000 ;
+ RECT 1241.890000 1576.660000 1242.890000 1577.140000 ;
+ RECT 1245.555000 1576.660000 1246.820000 1577.140000 ;
+ RECT 1241.890000 1571.220000 1242.890000 1571.700000 ;
+ RECT 1245.555000 1571.220000 1246.820000 1571.700000 ;
+ RECT 1241.890000 1560.340000 1242.890000 1560.820000 ;
+ RECT 1245.555000 1560.340000 1246.820000 1560.820000 ;
+ RECT 1241.890000 1565.780000 1242.890000 1566.260000 ;
+ RECT 1245.555000 1565.780000 1246.820000 1566.260000 ;
+ RECT 1241.890000 1554.900000 1242.890000 1555.380000 ;
+ RECT 1245.555000 1554.900000 1246.820000 1555.380000 ;
+ RECT 1380.720000 1647.380000 1381.820000 1647.860000 ;
+ RECT 1425.720000 1647.380000 1426.820000 1647.860000 ;
+ RECT 1438.530000 1647.380000 1439.530000 1647.860000 ;
+ RECT 1290.720000 1647.380000 1291.820000 1647.860000 ;
+ RECT 1335.720000 1647.380000 1336.820000 1647.860000 ;
+ RECT 1241.890000 1647.380000 1242.890000 1647.860000 ;
+ RECT 1245.555000 1647.380000 1246.820000 1647.860000 ;
+ RECT 1240.660000 1744.140000 1440.760000 1745.140000 ;
+ RECT 1240.660000 1548.570000 1440.760000 1549.570000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 1547.320000 1242.890000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1241.890000 1746.580000 1242.890000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 1547.320000 1439.530000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1438.530000 1746.580000 1439.530000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1548.570000 1241.660000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1548.570000 1440.760000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1744.140000 1241.660000 1745.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1744.140000 1440.760000 1745.140000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1450.655000 3373.560000 1451.920000 3374.040000 ;
+ RECT 1450.655000 3368.120000 1451.920000 3368.600000 ;
+ RECT 1450.655000 3362.680000 1451.920000 3363.160000 ;
+ RECT 1450.655000 3357.240000 1451.920000 3357.720000 ;
+ RECT 1446.990000 3349.660000 1447.990000 3379.920000 ;
+ RECT 1643.630000 3349.660000 1644.630000 3379.920000 ;
+ RECT 1450.820000 3350.910000 1451.920000 3378.160000 ;
+ RECT 1495.820000 3350.910000 1496.920000 3378.160000 ;
+ RECT 1540.820000 3350.910000 1541.920000 3378.160000 ;
+ RECT 1585.820000 3350.910000 1586.920000 3378.160000 ;
+ RECT 1630.820000 3350.910000 1631.920000 3378.160000 ;
+ LAYER met3 ;
+ RECT 1643.630000 3373.560000 1644.630000 3374.040000 ;
+ RECT 1643.630000 3368.120000 1644.630000 3368.600000 ;
+ RECT 1630.820000 3373.560000 1631.920000 3374.040000 ;
+ RECT 1630.820000 3368.120000 1631.920000 3368.600000 ;
+ RECT 1585.820000 3368.120000 1586.920000 3368.600000 ;
+ RECT 1585.820000 3373.560000 1586.920000 3374.040000 ;
+ RECT 1540.820000 3368.120000 1541.920000 3368.600000 ;
+ RECT 1495.820000 3368.120000 1496.920000 3368.600000 ;
+ RECT 1540.820000 3373.560000 1541.920000 3374.040000 ;
+ RECT 1495.820000 3373.560000 1496.920000 3374.040000 ;
+ RECT 1450.655000 3373.560000 1451.920000 3374.040000 ;
+ RECT 1446.990000 3373.560000 1447.990000 3374.040000 ;
+ RECT 1450.655000 3368.120000 1451.920000 3368.600000 ;
+ RECT 1446.990000 3368.120000 1447.990000 3368.600000 ;
+ RECT 1643.630000 3362.680000 1644.630000 3363.160000 ;
+ RECT 1643.630000 3357.240000 1644.630000 3357.720000 ;
+ RECT 1630.820000 3362.680000 1631.920000 3363.160000 ;
+ RECT 1630.820000 3357.240000 1631.920000 3357.720000 ;
+ RECT 1585.820000 3357.240000 1586.920000 3357.720000 ;
+ RECT 1585.820000 3362.680000 1586.920000 3363.160000 ;
+ RECT 1540.820000 3357.240000 1541.920000 3357.720000 ;
+ RECT 1495.820000 3357.240000 1496.920000 3357.720000 ;
+ RECT 1540.820000 3362.680000 1541.920000 3363.160000 ;
+ RECT 1495.820000 3362.680000 1496.920000 3363.160000 ;
+ RECT 1450.655000 3362.680000 1451.920000 3363.160000 ;
+ RECT 1446.990000 3362.680000 1447.990000 3363.160000 ;
+ RECT 1450.655000 3357.240000 1451.920000 3357.720000 ;
+ RECT 1446.990000 3357.240000 1447.990000 3357.720000 ;
+ RECT 1445.760000 3377.160000 1645.860000 3378.160000 ;
+ RECT 1445.760000 3350.910000 1645.860000 3351.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 3349.660000 1447.990000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 3378.920000 1447.990000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 3349.660000 1644.630000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 3378.920000 1644.630000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 3350.910000 1446.760000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 3350.910000 1645.860000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 3377.160000 1446.760000 3378.160000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 3377.160000 1645.860000 3378.160000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1450.655000 1334.920000 1451.920000 1335.400000 ;
+ RECT 1450.655000 1340.360000 1451.920000 1340.840000 ;
+ RECT 1450.655000 1329.480000 1451.920000 1329.960000 ;
+ RECT 1450.655000 1324.040000 1451.920000 1324.520000 ;
+ RECT 1450.655000 1318.600000 1451.920000 1319.080000 ;
+ RECT 1450.655000 1313.160000 1451.920000 1313.640000 ;
+ RECT 1450.655000 1307.720000 1451.920000 1308.200000 ;
+ RECT 1450.655000 1302.280000 1451.920000 1302.760000 ;
+ RECT 1450.655000 1291.400000 1451.920000 1291.880000 ;
+ RECT 1450.655000 1285.960000 1451.920000 1286.440000 ;
+ RECT 1450.655000 1280.520000 1451.920000 1281.000000 ;
+ RECT 1450.655000 1275.080000 1451.920000 1275.560000 ;
+ RECT 1450.655000 1269.640000 1451.920000 1270.120000 ;
+ RECT 1450.655000 1264.200000 1451.920000 1264.680000 ;
+ RECT 1450.655000 1253.320000 1451.920000 1253.800000 ;
+ RECT 1450.655000 1258.760000 1451.920000 1259.240000 ;
+ RECT 1450.655000 1247.880000 1451.920000 1248.360000 ;
+ RECT 1450.655000 1296.840000 1451.920000 1297.320000 ;
+ RECT 1450.655000 1242.440000 1451.920000 1242.920000 ;
+ RECT 1450.655000 1237.000000 1451.920000 1237.480000 ;
+ RECT 1450.655000 1231.560000 1451.920000 1232.040000 ;
+ RECT 1450.655000 1226.120000 1451.920000 1226.600000 ;
+ RECT 1450.655000 1220.680000 1451.920000 1221.160000 ;
+ RECT 1450.655000 1209.800000 1451.920000 1210.280000 ;
+ RECT 1450.655000 1215.240000 1451.920000 1215.720000 ;
+ RECT 1450.655000 1204.360000 1451.920000 1204.840000 ;
+ RECT 1450.655000 1198.920000 1451.920000 1199.400000 ;
+ RECT 1450.655000 1193.480000 1451.920000 1193.960000 ;
+ RECT 1450.655000 1188.040000 1451.920000 1188.520000 ;
+ RECT 1450.655000 1182.600000 1451.920000 1183.080000 ;
+ RECT 1450.655000 1177.160000 1451.920000 1177.640000 ;
+ RECT 1450.655000 1166.280000 1451.920000 1166.760000 ;
+ RECT 1450.655000 1160.840000 1451.920000 1161.320000 ;
+ RECT 1450.655000 1155.400000 1451.920000 1155.880000 ;
+ RECT 1450.655000 1149.960000 1451.920000 1150.440000 ;
+ RECT 1450.655000 1171.720000 1451.920000 1172.200000 ;
+ RECT 1450.655000 1144.520000 1451.920000 1145.000000 ;
+ RECT 1450.655000 1139.080000 1451.920000 1139.560000 ;
+ RECT 1450.655000 1128.200000 1451.920000 1128.680000 ;
+ RECT 1450.655000 1133.640000 1451.920000 1134.120000 ;
+ RECT 1450.655000 1122.760000 1451.920000 1123.240000 ;
+ RECT 1450.655000 1117.320000 1451.920000 1117.800000 ;
+ RECT 1450.655000 1111.880000 1451.920000 1112.360000 ;
+ RECT 1450.655000 1106.440000 1451.920000 1106.920000 ;
+ RECT 1450.655000 1101.000000 1451.920000 1101.480000 ;
+ RECT 1450.655000 1095.560000 1451.920000 1096.040000 ;
+ RECT 1450.655000 1084.680000 1451.920000 1085.160000 ;
+ RECT 1450.655000 1090.120000 1451.920000 1090.600000 ;
+ RECT 1450.655000 1079.240000 1451.920000 1079.720000 ;
+ RECT 1450.655000 1073.800000 1451.920000 1074.280000 ;
+ RECT 1450.655000 1068.360000 1451.920000 1068.840000 ;
+ RECT 1450.655000 1062.920000 1451.920000 1063.400000 ;
+ RECT 1450.655000 1057.480000 1451.920000 1057.960000 ;
+ RECT 1450.655000 1052.040000 1451.920000 1052.520000 ;
+ RECT 1450.655000 1041.160000 1451.920000 1041.640000 ;
+ RECT 1450.655000 1035.720000 1451.920000 1036.200000 ;
+ RECT 1450.655000 1030.280000 1451.920000 1030.760000 ;
+ RECT 1450.655000 1024.840000 1451.920000 1025.320000 ;
+ RECT 1450.655000 1019.400000 1451.920000 1019.880000 ;
+ RECT 1450.655000 1013.960000 1451.920000 1014.440000 ;
+ RECT 1450.655000 1003.080000 1451.920000 1003.560000 ;
+ RECT 1450.655000 1008.520000 1451.920000 1009.000000 ;
+ RECT 1450.655000 997.640000 1451.920000 998.120000 ;
+ RECT 1450.655000 992.200000 1451.920000 992.680000 ;
+ RECT 1450.655000 986.760000 1451.920000 987.240000 ;
+ RECT 1450.655000 981.320000 1451.920000 981.800000 ;
+ RECT 1450.655000 975.880000 1451.920000 976.360000 ;
+ RECT 1450.655000 970.440000 1451.920000 970.920000 ;
+ RECT 1450.655000 959.560000 1451.920000 960.040000 ;
+ RECT 1450.655000 965.000000 1451.920000 965.480000 ;
+ RECT 1450.655000 954.120000 1451.920000 954.600000 ;
+ RECT 1450.655000 1046.600000 1451.920000 1047.080000 ;
+ RECT 1446.990000 946.540000 1447.990000 1347.060000 ;
+ RECT 1643.630000 946.540000 1644.630000 1347.060000 ;
+ RECT 1450.820000 947.790000 1451.920000 1345.130000 ;
+ RECT 1495.820000 947.790000 1496.920000 1345.130000 ;
+ RECT 1540.820000 947.790000 1541.920000 1345.130000 ;
+ RECT 1585.820000 947.790000 1586.920000 1345.130000 ;
+ RECT 1630.820000 947.790000 1631.920000 1345.130000 ;
+ LAYER met3 ;
+ RECT 1630.820000 1334.920000 1631.920000 1335.400000 ;
+ RECT 1630.820000 1340.360000 1631.920000 1340.840000 ;
+ RECT 1643.630000 1334.920000 1644.630000 1335.400000 ;
+ RECT 1643.630000 1340.360000 1644.630000 1340.840000 ;
+ RECT 1630.820000 1324.040000 1631.920000 1324.520000 ;
+ RECT 1630.820000 1329.480000 1631.920000 1329.960000 ;
+ RECT 1643.630000 1324.040000 1644.630000 1324.520000 ;
+ RECT 1643.630000 1329.480000 1644.630000 1329.960000 ;
+ RECT 1643.630000 1313.160000 1644.630000 1313.640000 ;
+ RECT 1643.630000 1318.600000 1644.630000 1319.080000 ;
+ RECT 1630.820000 1318.600000 1631.920000 1319.080000 ;
+ RECT 1630.820000 1313.160000 1631.920000 1313.640000 ;
+ RECT 1630.820000 1302.280000 1631.920000 1302.760000 ;
+ RECT 1630.820000 1307.720000 1631.920000 1308.200000 ;
+ RECT 1643.630000 1302.280000 1644.630000 1302.760000 ;
+ RECT 1643.630000 1307.720000 1644.630000 1308.200000 ;
+ RECT 1585.820000 1324.040000 1586.920000 1324.520000 ;
+ RECT 1585.820000 1329.480000 1586.920000 1329.960000 ;
+ RECT 1585.820000 1334.920000 1586.920000 1335.400000 ;
+ RECT 1585.820000 1340.360000 1586.920000 1340.840000 ;
+ RECT 1585.820000 1307.720000 1586.920000 1308.200000 ;
+ RECT 1585.820000 1302.280000 1586.920000 1302.760000 ;
+ RECT 1585.820000 1313.160000 1586.920000 1313.640000 ;
+ RECT 1585.820000 1318.600000 1586.920000 1319.080000 ;
+ RECT 1630.820000 1285.960000 1631.920000 1286.440000 ;
+ RECT 1630.820000 1291.400000 1631.920000 1291.880000 ;
+ RECT 1643.630000 1285.960000 1644.630000 1286.440000 ;
+ RECT 1643.630000 1291.400000 1644.630000 1291.880000 ;
+ RECT 1643.630000 1275.080000 1644.630000 1275.560000 ;
+ RECT 1643.630000 1280.520000 1644.630000 1281.000000 ;
+ RECT 1630.820000 1280.520000 1631.920000 1281.000000 ;
+ RECT 1630.820000 1275.080000 1631.920000 1275.560000 ;
+ RECT 1630.820000 1264.200000 1631.920000 1264.680000 ;
+ RECT 1630.820000 1269.640000 1631.920000 1270.120000 ;
+ RECT 1643.630000 1264.200000 1644.630000 1264.680000 ;
+ RECT 1643.630000 1269.640000 1644.630000 1270.120000 ;
+ RECT 1643.630000 1253.320000 1644.630000 1253.800000 ;
+ RECT 1643.630000 1247.880000 1644.630000 1248.360000 ;
+ RECT 1643.630000 1258.760000 1644.630000 1259.240000 ;
+ RECT 1630.820000 1258.760000 1631.920000 1259.240000 ;
+ RECT 1630.820000 1253.320000 1631.920000 1253.800000 ;
+ RECT 1630.820000 1247.880000 1631.920000 1248.360000 ;
+ RECT 1585.820000 1275.080000 1586.920000 1275.560000 ;
+ RECT 1585.820000 1280.520000 1586.920000 1281.000000 ;
+ RECT 1585.820000 1285.960000 1586.920000 1286.440000 ;
+ RECT 1585.820000 1291.400000 1586.920000 1291.880000 ;
+ RECT 1585.820000 1247.880000 1586.920000 1248.360000 ;
+ RECT 1585.820000 1253.320000 1586.920000 1253.800000 ;
+ RECT 1585.820000 1258.760000 1586.920000 1259.240000 ;
+ RECT 1585.820000 1264.200000 1586.920000 1264.680000 ;
+ RECT 1585.820000 1269.640000 1586.920000 1270.120000 ;
+ RECT 1630.820000 1296.840000 1631.920000 1297.320000 ;
+ RECT 1585.820000 1296.840000 1586.920000 1297.320000 ;
+ RECT 1643.630000 1296.840000 1644.630000 1297.320000 ;
+ RECT 1630.820000 1237.000000 1631.920000 1237.480000 ;
+ RECT 1630.820000 1242.440000 1631.920000 1242.920000 ;
+ RECT 1643.630000 1237.000000 1644.630000 1237.480000 ;
+ RECT 1643.630000 1242.440000 1644.630000 1242.920000 ;
+ RECT 1630.820000 1226.120000 1631.920000 1226.600000 ;
+ RECT 1630.820000 1231.560000 1631.920000 1232.040000 ;
+ RECT 1643.630000 1226.120000 1644.630000 1226.600000 ;
+ RECT 1643.630000 1231.560000 1644.630000 1232.040000 ;
+ RECT 1643.630000 1215.240000 1644.630000 1215.720000 ;
+ RECT 1643.630000 1209.800000 1644.630000 1210.280000 ;
+ RECT 1643.630000 1220.680000 1644.630000 1221.160000 ;
+ RECT 1630.820000 1220.680000 1631.920000 1221.160000 ;
+ RECT 1630.820000 1215.240000 1631.920000 1215.720000 ;
+ RECT 1630.820000 1209.800000 1631.920000 1210.280000 ;
+ RECT 1630.820000 1198.920000 1631.920000 1199.400000 ;
+ RECT 1630.820000 1204.360000 1631.920000 1204.840000 ;
+ RECT 1643.630000 1198.920000 1644.630000 1199.400000 ;
+ RECT 1643.630000 1204.360000 1644.630000 1204.840000 ;
+ RECT 1585.820000 1226.120000 1586.920000 1226.600000 ;
+ RECT 1585.820000 1231.560000 1586.920000 1232.040000 ;
+ RECT 1585.820000 1237.000000 1586.920000 1237.480000 ;
+ RECT 1585.820000 1242.440000 1586.920000 1242.920000 ;
+ RECT 1585.820000 1198.920000 1586.920000 1199.400000 ;
+ RECT 1585.820000 1204.360000 1586.920000 1204.840000 ;
+ RECT 1585.820000 1209.800000 1586.920000 1210.280000 ;
+ RECT 1585.820000 1215.240000 1586.920000 1215.720000 ;
+ RECT 1585.820000 1220.680000 1586.920000 1221.160000 ;
+ RECT 1643.630000 1188.040000 1644.630000 1188.520000 ;
+ RECT 1643.630000 1193.480000 1644.630000 1193.960000 ;
+ RECT 1630.820000 1193.480000 1631.920000 1193.960000 ;
+ RECT 1630.820000 1188.040000 1631.920000 1188.520000 ;
+ RECT 1630.820000 1177.160000 1631.920000 1177.640000 ;
+ RECT 1630.820000 1182.600000 1631.920000 1183.080000 ;
+ RECT 1643.630000 1177.160000 1644.630000 1177.640000 ;
+ RECT 1643.630000 1182.600000 1644.630000 1183.080000 ;
+ RECT 1630.820000 1160.840000 1631.920000 1161.320000 ;
+ RECT 1630.820000 1166.280000 1631.920000 1166.760000 ;
+ RECT 1643.630000 1160.840000 1644.630000 1161.320000 ;
+ RECT 1643.630000 1166.280000 1644.630000 1166.760000 ;
+ RECT 1643.630000 1149.960000 1644.630000 1150.440000 ;
+ RECT 1643.630000 1155.400000 1644.630000 1155.880000 ;
+ RECT 1630.820000 1155.400000 1631.920000 1155.880000 ;
+ RECT 1630.820000 1149.960000 1631.920000 1150.440000 ;
+ RECT 1630.820000 1171.720000 1631.920000 1172.200000 ;
+ RECT 1643.630000 1171.720000 1644.630000 1172.200000 ;
+ RECT 1585.820000 1177.160000 1586.920000 1177.640000 ;
+ RECT 1585.820000 1182.600000 1586.920000 1183.080000 ;
+ RECT 1585.820000 1188.040000 1586.920000 1188.520000 ;
+ RECT 1585.820000 1193.480000 1586.920000 1193.960000 ;
+ RECT 1585.820000 1149.960000 1586.920000 1150.440000 ;
+ RECT 1585.820000 1155.400000 1586.920000 1155.880000 ;
+ RECT 1585.820000 1160.840000 1586.920000 1161.320000 ;
+ RECT 1585.820000 1166.280000 1586.920000 1166.760000 ;
+ RECT 1585.820000 1171.720000 1586.920000 1172.200000 ;
+ RECT 1540.820000 1329.480000 1541.920000 1329.960000 ;
+ RECT 1540.820000 1324.040000 1541.920000 1324.520000 ;
+ RECT 1540.820000 1334.920000 1541.920000 1335.400000 ;
+ RECT 1540.820000 1340.360000 1541.920000 1340.840000 ;
+ RECT 1495.820000 1324.040000 1496.920000 1324.520000 ;
+ RECT 1495.820000 1329.480000 1496.920000 1329.960000 ;
+ RECT 1495.820000 1334.920000 1496.920000 1335.400000 ;
+ RECT 1495.820000 1340.360000 1496.920000 1340.840000 ;
+ RECT 1540.820000 1302.280000 1541.920000 1302.760000 ;
+ RECT 1540.820000 1307.720000 1541.920000 1308.200000 ;
+ RECT 1540.820000 1313.160000 1541.920000 1313.640000 ;
+ RECT 1540.820000 1318.600000 1541.920000 1319.080000 ;
+ RECT 1495.820000 1302.280000 1496.920000 1302.760000 ;
+ RECT 1495.820000 1307.720000 1496.920000 1308.200000 ;
+ RECT 1495.820000 1313.160000 1496.920000 1313.640000 ;
+ RECT 1495.820000 1318.600000 1496.920000 1319.080000 ;
+ RECT 1446.990000 1334.920000 1447.990000 1335.400000 ;
+ RECT 1450.655000 1334.920000 1451.920000 1335.400000 ;
+ RECT 1446.990000 1340.360000 1447.990000 1340.840000 ;
+ RECT 1450.655000 1340.360000 1451.920000 1340.840000 ;
+ RECT 1446.990000 1329.480000 1447.990000 1329.960000 ;
+ RECT 1450.655000 1329.480000 1451.920000 1329.960000 ;
+ RECT 1446.990000 1324.040000 1447.990000 1324.520000 ;
+ RECT 1450.655000 1324.040000 1451.920000 1324.520000 ;
+ RECT 1446.990000 1318.600000 1447.990000 1319.080000 ;
+ RECT 1450.655000 1318.600000 1451.920000 1319.080000 ;
+ RECT 1446.990000 1313.160000 1447.990000 1313.640000 ;
+ RECT 1450.655000 1313.160000 1451.920000 1313.640000 ;
+ RECT 1446.990000 1307.720000 1447.990000 1308.200000 ;
+ RECT 1450.655000 1307.720000 1451.920000 1308.200000 ;
+ RECT 1446.990000 1302.280000 1447.990000 1302.760000 ;
+ RECT 1450.655000 1302.280000 1451.920000 1302.760000 ;
+ RECT 1540.820000 1275.080000 1541.920000 1275.560000 ;
+ RECT 1540.820000 1280.520000 1541.920000 1281.000000 ;
+ RECT 1540.820000 1285.960000 1541.920000 1286.440000 ;
+ RECT 1540.820000 1291.400000 1541.920000 1291.880000 ;
+ RECT 1495.820000 1275.080000 1496.920000 1275.560000 ;
+ RECT 1495.820000 1280.520000 1496.920000 1281.000000 ;
+ RECT 1495.820000 1285.960000 1496.920000 1286.440000 ;
+ RECT 1495.820000 1291.400000 1496.920000 1291.880000 ;
+ RECT 1540.820000 1247.880000 1541.920000 1248.360000 ;
+ RECT 1540.820000 1253.320000 1541.920000 1253.800000 ;
+ RECT 1540.820000 1258.760000 1541.920000 1259.240000 ;
+ RECT 1540.820000 1264.200000 1541.920000 1264.680000 ;
+ RECT 1540.820000 1269.640000 1541.920000 1270.120000 ;
+ RECT 1495.820000 1247.880000 1496.920000 1248.360000 ;
+ RECT 1495.820000 1253.320000 1496.920000 1253.800000 ;
+ RECT 1495.820000 1258.760000 1496.920000 1259.240000 ;
+ RECT 1495.820000 1264.200000 1496.920000 1264.680000 ;
+ RECT 1495.820000 1269.640000 1496.920000 1270.120000 ;
+ RECT 1446.990000 1291.400000 1447.990000 1291.880000 ;
+ RECT 1450.655000 1291.400000 1451.920000 1291.880000 ;
+ RECT 1446.990000 1285.960000 1447.990000 1286.440000 ;
+ RECT 1450.655000 1285.960000 1451.920000 1286.440000 ;
+ RECT 1446.990000 1280.520000 1447.990000 1281.000000 ;
+ RECT 1450.655000 1280.520000 1451.920000 1281.000000 ;
+ RECT 1446.990000 1275.080000 1447.990000 1275.560000 ;
+ RECT 1450.655000 1275.080000 1451.920000 1275.560000 ;
+ RECT 1446.990000 1269.640000 1447.990000 1270.120000 ;
+ RECT 1450.655000 1269.640000 1451.920000 1270.120000 ;
+ RECT 1446.990000 1264.200000 1447.990000 1264.680000 ;
+ RECT 1450.655000 1264.200000 1451.920000 1264.680000 ;
+ RECT 1446.990000 1253.320000 1447.990000 1253.800000 ;
+ RECT 1450.655000 1253.320000 1451.920000 1253.800000 ;
+ RECT 1446.990000 1258.760000 1447.990000 1259.240000 ;
+ RECT 1450.655000 1258.760000 1451.920000 1259.240000 ;
+ RECT 1446.990000 1247.880000 1447.990000 1248.360000 ;
+ RECT 1450.655000 1247.880000 1451.920000 1248.360000 ;
+ RECT 1540.820000 1296.840000 1541.920000 1297.320000 ;
+ RECT 1495.820000 1296.840000 1496.920000 1297.320000 ;
+ RECT 1446.990000 1296.840000 1447.990000 1297.320000 ;
+ RECT 1450.655000 1296.840000 1451.920000 1297.320000 ;
+ RECT 1540.820000 1226.120000 1541.920000 1226.600000 ;
+ RECT 1540.820000 1231.560000 1541.920000 1232.040000 ;
+ RECT 1540.820000 1237.000000 1541.920000 1237.480000 ;
+ RECT 1540.820000 1242.440000 1541.920000 1242.920000 ;
+ RECT 1495.820000 1226.120000 1496.920000 1226.600000 ;
+ RECT 1495.820000 1231.560000 1496.920000 1232.040000 ;
+ RECT 1495.820000 1237.000000 1496.920000 1237.480000 ;
+ RECT 1495.820000 1242.440000 1496.920000 1242.920000 ;
+ RECT 1540.820000 1198.920000 1541.920000 1199.400000 ;
+ RECT 1540.820000 1204.360000 1541.920000 1204.840000 ;
+ RECT 1540.820000 1209.800000 1541.920000 1210.280000 ;
+ RECT 1540.820000 1215.240000 1541.920000 1215.720000 ;
+ RECT 1540.820000 1220.680000 1541.920000 1221.160000 ;
+ RECT 1495.820000 1198.920000 1496.920000 1199.400000 ;
+ RECT 1495.820000 1204.360000 1496.920000 1204.840000 ;
+ RECT 1495.820000 1209.800000 1496.920000 1210.280000 ;
+ RECT 1495.820000 1215.240000 1496.920000 1215.720000 ;
+ RECT 1495.820000 1220.680000 1496.920000 1221.160000 ;
+ RECT 1446.990000 1242.440000 1447.990000 1242.920000 ;
+ RECT 1450.655000 1242.440000 1451.920000 1242.920000 ;
+ RECT 1446.990000 1237.000000 1447.990000 1237.480000 ;
+ RECT 1450.655000 1237.000000 1451.920000 1237.480000 ;
+ RECT 1446.990000 1231.560000 1447.990000 1232.040000 ;
+ RECT 1450.655000 1231.560000 1451.920000 1232.040000 ;
+ RECT 1446.990000 1226.120000 1447.990000 1226.600000 ;
+ RECT 1450.655000 1226.120000 1451.920000 1226.600000 ;
+ RECT 1446.990000 1220.680000 1447.990000 1221.160000 ;
+ RECT 1450.655000 1220.680000 1451.920000 1221.160000 ;
+ RECT 1446.990000 1209.800000 1447.990000 1210.280000 ;
+ RECT 1450.655000 1209.800000 1451.920000 1210.280000 ;
+ RECT 1446.990000 1215.240000 1447.990000 1215.720000 ;
+ RECT 1450.655000 1215.240000 1451.920000 1215.720000 ;
+ RECT 1446.990000 1204.360000 1447.990000 1204.840000 ;
+ RECT 1450.655000 1204.360000 1451.920000 1204.840000 ;
+ RECT 1446.990000 1198.920000 1447.990000 1199.400000 ;
+ RECT 1450.655000 1198.920000 1451.920000 1199.400000 ;
+ RECT 1540.820000 1177.160000 1541.920000 1177.640000 ;
+ RECT 1540.820000 1182.600000 1541.920000 1183.080000 ;
+ RECT 1540.820000 1188.040000 1541.920000 1188.520000 ;
+ RECT 1540.820000 1193.480000 1541.920000 1193.960000 ;
+ RECT 1495.820000 1177.160000 1496.920000 1177.640000 ;
+ RECT 1495.820000 1182.600000 1496.920000 1183.080000 ;
+ RECT 1495.820000 1188.040000 1496.920000 1188.520000 ;
+ RECT 1495.820000 1193.480000 1496.920000 1193.960000 ;
+ RECT 1540.820000 1149.960000 1541.920000 1150.440000 ;
+ RECT 1540.820000 1155.400000 1541.920000 1155.880000 ;
+ RECT 1540.820000 1160.840000 1541.920000 1161.320000 ;
+ RECT 1540.820000 1166.280000 1541.920000 1166.760000 ;
+ RECT 1495.820000 1149.960000 1496.920000 1150.440000 ;
+ RECT 1495.820000 1155.400000 1496.920000 1155.880000 ;
+ RECT 1495.820000 1160.840000 1496.920000 1161.320000 ;
+ RECT 1495.820000 1166.280000 1496.920000 1166.760000 ;
+ RECT 1540.820000 1171.720000 1541.920000 1172.200000 ;
+ RECT 1495.820000 1171.720000 1496.920000 1172.200000 ;
+ RECT 1446.990000 1193.480000 1447.990000 1193.960000 ;
+ RECT 1450.655000 1193.480000 1451.920000 1193.960000 ;
+ RECT 1446.990000 1188.040000 1447.990000 1188.520000 ;
+ RECT 1450.655000 1188.040000 1451.920000 1188.520000 ;
+ RECT 1446.990000 1182.600000 1447.990000 1183.080000 ;
+ RECT 1450.655000 1182.600000 1451.920000 1183.080000 ;
+ RECT 1446.990000 1177.160000 1447.990000 1177.640000 ;
+ RECT 1450.655000 1177.160000 1451.920000 1177.640000 ;
+ RECT 1446.990000 1166.280000 1447.990000 1166.760000 ;
+ RECT 1450.655000 1166.280000 1451.920000 1166.760000 ;
+ RECT 1446.990000 1160.840000 1447.990000 1161.320000 ;
+ RECT 1450.655000 1160.840000 1451.920000 1161.320000 ;
+ RECT 1446.990000 1155.400000 1447.990000 1155.880000 ;
+ RECT 1450.655000 1155.400000 1451.920000 1155.880000 ;
+ RECT 1446.990000 1149.960000 1447.990000 1150.440000 ;
+ RECT 1450.655000 1149.960000 1451.920000 1150.440000 ;
+ RECT 1446.990000 1171.720000 1447.990000 1172.200000 ;
+ RECT 1450.655000 1171.720000 1451.920000 1172.200000 ;
+ RECT 1630.820000 1139.080000 1631.920000 1139.560000 ;
+ RECT 1630.820000 1144.520000 1631.920000 1145.000000 ;
+ RECT 1643.630000 1139.080000 1644.630000 1139.560000 ;
+ RECT 1643.630000 1144.520000 1644.630000 1145.000000 ;
+ RECT 1643.630000 1128.200000 1644.630000 1128.680000 ;
+ RECT 1643.630000 1122.760000 1644.630000 1123.240000 ;
+ RECT 1643.630000 1133.640000 1644.630000 1134.120000 ;
+ RECT 1630.820000 1133.640000 1631.920000 1134.120000 ;
+ RECT 1630.820000 1128.200000 1631.920000 1128.680000 ;
+ RECT 1630.820000 1122.760000 1631.920000 1123.240000 ;
+ RECT 1630.820000 1111.880000 1631.920000 1112.360000 ;
+ RECT 1630.820000 1117.320000 1631.920000 1117.800000 ;
+ RECT 1643.630000 1111.880000 1644.630000 1112.360000 ;
+ RECT 1643.630000 1117.320000 1644.630000 1117.800000 ;
+ RECT 1630.820000 1101.000000 1631.920000 1101.480000 ;
+ RECT 1630.820000 1106.440000 1631.920000 1106.920000 ;
+ RECT 1643.630000 1101.000000 1644.630000 1101.480000 ;
+ RECT 1643.630000 1106.440000 1644.630000 1106.920000 ;
+ RECT 1585.820000 1122.760000 1586.920000 1123.240000 ;
+ RECT 1585.820000 1128.200000 1586.920000 1128.680000 ;
+ RECT 1585.820000 1133.640000 1586.920000 1134.120000 ;
+ RECT 1585.820000 1139.080000 1586.920000 1139.560000 ;
+ RECT 1585.820000 1144.520000 1586.920000 1145.000000 ;
+ RECT 1585.820000 1101.000000 1586.920000 1101.480000 ;
+ RECT 1585.820000 1106.440000 1586.920000 1106.920000 ;
+ RECT 1585.820000 1111.880000 1586.920000 1112.360000 ;
+ RECT 1585.820000 1117.320000 1586.920000 1117.800000 ;
+ RECT 1643.630000 1090.120000 1644.630000 1090.600000 ;
+ RECT 1643.630000 1084.680000 1644.630000 1085.160000 ;
+ RECT 1643.630000 1095.560000 1644.630000 1096.040000 ;
+ RECT 1630.820000 1095.560000 1631.920000 1096.040000 ;
+ RECT 1630.820000 1090.120000 1631.920000 1090.600000 ;
+ RECT 1630.820000 1084.680000 1631.920000 1085.160000 ;
+ RECT 1630.820000 1073.800000 1631.920000 1074.280000 ;
+ RECT 1630.820000 1079.240000 1631.920000 1079.720000 ;
+ RECT 1643.630000 1073.800000 1644.630000 1074.280000 ;
+ RECT 1643.630000 1079.240000 1644.630000 1079.720000 ;
+ RECT 1643.630000 1062.920000 1644.630000 1063.400000 ;
+ RECT 1643.630000 1068.360000 1644.630000 1068.840000 ;
+ RECT 1630.820000 1068.360000 1631.920000 1068.840000 ;
+ RECT 1630.820000 1062.920000 1631.920000 1063.400000 ;
+ RECT 1630.820000 1052.040000 1631.920000 1052.520000 ;
+ RECT 1630.820000 1057.480000 1631.920000 1057.960000 ;
+ RECT 1643.630000 1052.040000 1644.630000 1052.520000 ;
+ RECT 1643.630000 1057.480000 1644.630000 1057.960000 ;
+ RECT 1585.820000 1073.800000 1586.920000 1074.280000 ;
+ RECT 1585.820000 1079.240000 1586.920000 1079.720000 ;
+ RECT 1585.820000 1084.680000 1586.920000 1085.160000 ;
+ RECT 1585.820000 1090.120000 1586.920000 1090.600000 ;
+ RECT 1585.820000 1095.560000 1586.920000 1096.040000 ;
+ RECT 1585.820000 1052.040000 1586.920000 1052.520000 ;
+ RECT 1585.820000 1057.480000 1586.920000 1057.960000 ;
+ RECT 1585.820000 1062.920000 1586.920000 1063.400000 ;
+ RECT 1585.820000 1068.360000 1586.920000 1068.840000 ;
+ RECT 1630.820000 1035.720000 1631.920000 1036.200000 ;
+ RECT 1630.820000 1041.160000 1631.920000 1041.640000 ;
+ RECT 1643.630000 1035.720000 1644.630000 1036.200000 ;
+ RECT 1643.630000 1041.160000 1644.630000 1041.640000 ;
+ RECT 1643.630000 1024.840000 1644.630000 1025.320000 ;
+ RECT 1643.630000 1030.280000 1644.630000 1030.760000 ;
+ RECT 1630.820000 1030.280000 1631.920000 1030.760000 ;
+ RECT 1630.820000 1024.840000 1631.920000 1025.320000 ;
+ RECT 1630.820000 1013.960000 1631.920000 1014.440000 ;
+ RECT 1630.820000 1019.400000 1631.920000 1019.880000 ;
+ RECT 1643.630000 1013.960000 1644.630000 1014.440000 ;
+ RECT 1643.630000 1019.400000 1644.630000 1019.880000 ;
+ RECT 1643.630000 1003.080000 1644.630000 1003.560000 ;
+ RECT 1643.630000 997.640000 1644.630000 998.120000 ;
+ RECT 1643.630000 1008.520000 1644.630000 1009.000000 ;
+ RECT 1630.820000 1008.520000 1631.920000 1009.000000 ;
+ RECT 1630.820000 1003.080000 1631.920000 1003.560000 ;
+ RECT 1630.820000 997.640000 1631.920000 998.120000 ;
+ RECT 1585.820000 1024.840000 1586.920000 1025.320000 ;
+ RECT 1585.820000 1030.280000 1586.920000 1030.760000 ;
+ RECT 1585.820000 1035.720000 1586.920000 1036.200000 ;
+ RECT 1585.820000 1041.160000 1586.920000 1041.640000 ;
+ RECT 1585.820000 997.640000 1586.920000 998.120000 ;
+ RECT 1585.820000 1003.080000 1586.920000 1003.560000 ;
+ RECT 1585.820000 1008.520000 1586.920000 1009.000000 ;
+ RECT 1585.820000 1013.960000 1586.920000 1014.440000 ;
+ RECT 1585.820000 1019.400000 1586.920000 1019.880000 ;
+ RECT 1630.820000 986.760000 1631.920000 987.240000 ;
+ RECT 1630.820000 992.200000 1631.920000 992.680000 ;
+ RECT 1643.630000 986.760000 1644.630000 987.240000 ;
+ RECT 1643.630000 992.200000 1644.630000 992.680000 ;
+ RECT 1630.820000 975.880000 1631.920000 976.360000 ;
+ RECT 1630.820000 981.320000 1631.920000 981.800000 ;
+ RECT 1643.630000 975.880000 1644.630000 976.360000 ;
+ RECT 1643.630000 981.320000 1644.630000 981.800000 ;
+ RECT 1643.630000 965.000000 1644.630000 965.480000 ;
+ RECT 1643.630000 959.560000 1644.630000 960.040000 ;
+ RECT 1643.630000 970.440000 1644.630000 970.920000 ;
+ RECT 1630.820000 970.440000 1631.920000 970.920000 ;
+ RECT 1630.820000 965.000000 1631.920000 965.480000 ;
+ RECT 1630.820000 959.560000 1631.920000 960.040000 ;
+ RECT 1630.820000 954.120000 1631.920000 954.600000 ;
+ RECT 1643.630000 954.120000 1644.630000 954.600000 ;
+ RECT 1585.820000 975.880000 1586.920000 976.360000 ;
+ RECT 1585.820000 981.320000 1586.920000 981.800000 ;
+ RECT 1585.820000 986.760000 1586.920000 987.240000 ;
+ RECT 1585.820000 992.200000 1586.920000 992.680000 ;
+ RECT 1585.820000 954.120000 1586.920000 954.600000 ;
+ RECT 1585.820000 959.560000 1586.920000 960.040000 ;
+ RECT 1585.820000 965.000000 1586.920000 965.480000 ;
+ RECT 1585.820000 970.440000 1586.920000 970.920000 ;
+ RECT 1630.820000 1046.600000 1631.920000 1047.080000 ;
+ RECT 1585.820000 1046.600000 1586.920000 1047.080000 ;
+ RECT 1643.630000 1046.600000 1644.630000 1047.080000 ;
+ RECT 1540.820000 1122.760000 1541.920000 1123.240000 ;
+ RECT 1540.820000 1128.200000 1541.920000 1128.680000 ;
+ RECT 1540.820000 1133.640000 1541.920000 1134.120000 ;
+ RECT 1540.820000 1139.080000 1541.920000 1139.560000 ;
+ RECT 1540.820000 1144.520000 1541.920000 1145.000000 ;
+ RECT 1495.820000 1122.760000 1496.920000 1123.240000 ;
+ RECT 1495.820000 1128.200000 1496.920000 1128.680000 ;
+ RECT 1495.820000 1133.640000 1496.920000 1134.120000 ;
+ RECT 1495.820000 1139.080000 1496.920000 1139.560000 ;
+ RECT 1495.820000 1144.520000 1496.920000 1145.000000 ;
+ RECT 1540.820000 1101.000000 1541.920000 1101.480000 ;
+ RECT 1540.820000 1106.440000 1541.920000 1106.920000 ;
+ RECT 1540.820000 1111.880000 1541.920000 1112.360000 ;
+ RECT 1540.820000 1117.320000 1541.920000 1117.800000 ;
+ RECT 1495.820000 1101.000000 1496.920000 1101.480000 ;
+ RECT 1495.820000 1106.440000 1496.920000 1106.920000 ;
+ RECT 1495.820000 1111.880000 1496.920000 1112.360000 ;
+ RECT 1495.820000 1117.320000 1496.920000 1117.800000 ;
+ RECT 1446.990000 1144.520000 1447.990000 1145.000000 ;
+ RECT 1450.655000 1144.520000 1451.920000 1145.000000 ;
+ RECT 1446.990000 1139.080000 1447.990000 1139.560000 ;
+ RECT 1450.655000 1139.080000 1451.920000 1139.560000 ;
+ RECT 1446.990000 1128.200000 1447.990000 1128.680000 ;
+ RECT 1450.655000 1128.200000 1451.920000 1128.680000 ;
+ RECT 1446.990000 1133.640000 1447.990000 1134.120000 ;
+ RECT 1450.655000 1133.640000 1451.920000 1134.120000 ;
+ RECT 1446.990000 1122.760000 1447.990000 1123.240000 ;
+ RECT 1450.655000 1122.760000 1451.920000 1123.240000 ;
+ RECT 1446.990000 1117.320000 1447.990000 1117.800000 ;
+ RECT 1450.655000 1117.320000 1451.920000 1117.800000 ;
+ RECT 1446.990000 1111.880000 1447.990000 1112.360000 ;
+ RECT 1450.655000 1111.880000 1451.920000 1112.360000 ;
+ RECT 1446.990000 1106.440000 1447.990000 1106.920000 ;
+ RECT 1450.655000 1106.440000 1451.920000 1106.920000 ;
+ RECT 1446.990000 1101.000000 1447.990000 1101.480000 ;
+ RECT 1450.655000 1101.000000 1451.920000 1101.480000 ;
+ RECT 1540.820000 1073.800000 1541.920000 1074.280000 ;
+ RECT 1540.820000 1079.240000 1541.920000 1079.720000 ;
+ RECT 1540.820000 1084.680000 1541.920000 1085.160000 ;
+ RECT 1540.820000 1090.120000 1541.920000 1090.600000 ;
+ RECT 1540.820000 1095.560000 1541.920000 1096.040000 ;
+ RECT 1495.820000 1073.800000 1496.920000 1074.280000 ;
+ RECT 1495.820000 1079.240000 1496.920000 1079.720000 ;
+ RECT 1495.820000 1084.680000 1496.920000 1085.160000 ;
+ RECT 1495.820000 1090.120000 1496.920000 1090.600000 ;
+ RECT 1495.820000 1095.560000 1496.920000 1096.040000 ;
+ RECT 1540.820000 1052.040000 1541.920000 1052.520000 ;
+ RECT 1540.820000 1057.480000 1541.920000 1057.960000 ;
+ RECT 1540.820000 1062.920000 1541.920000 1063.400000 ;
+ RECT 1540.820000 1068.360000 1541.920000 1068.840000 ;
+ RECT 1495.820000 1052.040000 1496.920000 1052.520000 ;
+ RECT 1495.820000 1057.480000 1496.920000 1057.960000 ;
+ RECT 1495.820000 1062.920000 1496.920000 1063.400000 ;
+ RECT 1495.820000 1068.360000 1496.920000 1068.840000 ;
+ RECT 1446.990000 1095.560000 1447.990000 1096.040000 ;
+ RECT 1450.655000 1095.560000 1451.920000 1096.040000 ;
+ RECT 1446.990000 1084.680000 1447.990000 1085.160000 ;
+ RECT 1450.655000 1084.680000 1451.920000 1085.160000 ;
+ RECT 1446.990000 1090.120000 1447.990000 1090.600000 ;
+ RECT 1450.655000 1090.120000 1451.920000 1090.600000 ;
+ RECT 1446.990000 1079.240000 1447.990000 1079.720000 ;
+ RECT 1450.655000 1079.240000 1451.920000 1079.720000 ;
+ RECT 1446.990000 1073.800000 1447.990000 1074.280000 ;
+ RECT 1450.655000 1073.800000 1451.920000 1074.280000 ;
+ RECT 1446.990000 1068.360000 1447.990000 1068.840000 ;
+ RECT 1450.655000 1068.360000 1451.920000 1068.840000 ;
+ RECT 1446.990000 1062.920000 1447.990000 1063.400000 ;
+ RECT 1450.655000 1062.920000 1451.920000 1063.400000 ;
+ RECT 1446.990000 1057.480000 1447.990000 1057.960000 ;
+ RECT 1450.655000 1057.480000 1451.920000 1057.960000 ;
+ RECT 1446.990000 1052.040000 1447.990000 1052.520000 ;
+ RECT 1450.655000 1052.040000 1451.920000 1052.520000 ;
+ RECT 1540.820000 1024.840000 1541.920000 1025.320000 ;
+ RECT 1540.820000 1030.280000 1541.920000 1030.760000 ;
+ RECT 1540.820000 1035.720000 1541.920000 1036.200000 ;
+ RECT 1540.820000 1041.160000 1541.920000 1041.640000 ;
+ RECT 1495.820000 1024.840000 1496.920000 1025.320000 ;
+ RECT 1495.820000 1030.280000 1496.920000 1030.760000 ;
+ RECT 1495.820000 1035.720000 1496.920000 1036.200000 ;
+ RECT 1495.820000 1041.160000 1496.920000 1041.640000 ;
+ RECT 1540.820000 997.640000 1541.920000 998.120000 ;
+ RECT 1540.820000 1003.080000 1541.920000 1003.560000 ;
+ RECT 1540.820000 1008.520000 1541.920000 1009.000000 ;
+ RECT 1540.820000 1013.960000 1541.920000 1014.440000 ;
+ RECT 1540.820000 1019.400000 1541.920000 1019.880000 ;
+ RECT 1495.820000 997.640000 1496.920000 998.120000 ;
+ RECT 1495.820000 1003.080000 1496.920000 1003.560000 ;
+ RECT 1495.820000 1008.520000 1496.920000 1009.000000 ;
+ RECT 1495.820000 1013.960000 1496.920000 1014.440000 ;
+ RECT 1495.820000 1019.400000 1496.920000 1019.880000 ;
+ RECT 1446.990000 1041.160000 1447.990000 1041.640000 ;
+ RECT 1450.655000 1041.160000 1451.920000 1041.640000 ;
+ RECT 1446.990000 1035.720000 1447.990000 1036.200000 ;
+ RECT 1450.655000 1035.720000 1451.920000 1036.200000 ;
+ RECT 1446.990000 1030.280000 1447.990000 1030.760000 ;
+ RECT 1450.655000 1030.280000 1451.920000 1030.760000 ;
+ RECT 1446.990000 1024.840000 1447.990000 1025.320000 ;
+ RECT 1450.655000 1024.840000 1451.920000 1025.320000 ;
+ RECT 1446.990000 1019.400000 1447.990000 1019.880000 ;
+ RECT 1450.655000 1019.400000 1451.920000 1019.880000 ;
+ RECT 1446.990000 1013.960000 1447.990000 1014.440000 ;
+ RECT 1450.655000 1013.960000 1451.920000 1014.440000 ;
+ RECT 1446.990000 1003.080000 1447.990000 1003.560000 ;
+ RECT 1450.655000 1003.080000 1451.920000 1003.560000 ;
+ RECT 1446.990000 1008.520000 1447.990000 1009.000000 ;
+ RECT 1450.655000 1008.520000 1451.920000 1009.000000 ;
+ RECT 1446.990000 997.640000 1447.990000 998.120000 ;
+ RECT 1450.655000 997.640000 1451.920000 998.120000 ;
+ RECT 1540.820000 975.880000 1541.920000 976.360000 ;
+ RECT 1540.820000 981.320000 1541.920000 981.800000 ;
+ RECT 1540.820000 986.760000 1541.920000 987.240000 ;
+ RECT 1540.820000 992.200000 1541.920000 992.680000 ;
+ RECT 1495.820000 975.880000 1496.920000 976.360000 ;
+ RECT 1495.820000 981.320000 1496.920000 981.800000 ;
+ RECT 1495.820000 986.760000 1496.920000 987.240000 ;
+ RECT 1495.820000 992.200000 1496.920000 992.680000 ;
+ RECT 1540.820000 954.120000 1541.920000 954.600000 ;
+ RECT 1540.820000 959.560000 1541.920000 960.040000 ;
+ RECT 1540.820000 965.000000 1541.920000 965.480000 ;
+ RECT 1540.820000 970.440000 1541.920000 970.920000 ;
+ RECT 1495.820000 954.120000 1496.920000 954.600000 ;
+ RECT 1495.820000 959.560000 1496.920000 960.040000 ;
+ RECT 1495.820000 965.000000 1496.920000 965.480000 ;
+ RECT 1495.820000 970.440000 1496.920000 970.920000 ;
+ RECT 1446.990000 992.200000 1447.990000 992.680000 ;
+ RECT 1450.655000 992.200000 1451.920000 992.680000 ;
+ RECT 1446.990000 986.760000 1447.990000 987.240000 ;
+ RECT 1450.655000 986.760000 1451.920000 987.240000 ;
+ RECT 1446.990000 981.320000 1447.990000 981.800000 ;
+ RECT 1450.655000 981.320000 1451.920000 981.800000 ;
+ RECT 1446.990000 975.880000 1447.990000 976.360000 ;
+ RECT 1450.655000 975.880000 1451.920000 976.360000 ;
+ RECT 1446.990000 970.440000 1447.990000 970.920000 ;
+ RECT 1450.655000 970.440000 1451.920000 970.920000 ;
+ RECT 1446.990000 959.560000 1447.990000 960.040000 ;
+ RECT 1450.655000 959.560000 1451.920000 960.040000 ;
+ RECT 1446.990000 965.000000 1447.990000 965.480000 ;
+ RECT 1450.655000 965.000000 1451.920000 965.480000 ;
+ RECT 1446.990000 954.120000 1447.990000 954.600000 ;
+ RECT 1450.655000 954.120000 1451.920000 954.600000 ;
+ RECT 1540.820000 1046.600000 1541.920000 1047.080000 ;
+ RECT 1495.820000 1046.600000 1496.920000 1047.080000 ;
+ RECT 1446.990000 1046.600000 1447.990000 1047.080000 ;
+ RECT 1450.655000 1046.600000 1451.920000 1047.080000 ;
+ RECT 1445.760000 1344.130000 1645.860000 1345.130000 ;
+ RECT 1445.760000 947.790000 1645.860000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 946.540000 1447.990000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 1346.060000 1447.990000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 946.540000 1644.630000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 1346.060000 1644.630000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 947.790000 1446.760000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 947.790000 1645.860000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 1344.130000 1446.760000 1345.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 1344.130000 1645.860000 1345.130000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1450.655000 934.400000 1451.920000 934.880000 ;
+ RECT 1450.655000 939.840000 1451.920000 940.320000 ;
+ RECT 1450.655000 928.960000 1451.920000 929.440000 ;
+ RECT 1450.655000 923.520000 1451.920000 924.000000 ;
+ RECT 1450.655000 918.080000 1451.920000 918.560000 ;
+ RECT 1450.655000 912.640000 1451.920000 913.120000 ;
+ RECT 1450.655000 907.200000 1451.920000 907.680000 ;
+ RECT 1450.655000 901.760000 1451.920000 902.240000 ;
+ RECT 1450.655000 890.880000 1451.920000 891.360000 ;
+ RECT 1450.655000 885.440000 1451.920000 885.920000 ;
+ RECT 1450.655000 880.000000 1451.920000 880.480000 ;
+ RECT 1450.655000 874.560000 1451.920000 875.040000 ;
+ RECT 1450.655000 869.120000 1451.920000 869.600000 ;
+ RECT 1450.655000 863.680000 1451.920000 864.160000 ;
+ RECT 1450.655000 852.800000 1451.920000 853.280000 ;
+ RECT 1450.655000 858.240000 1451.920000 858.720000 ;
+ RECT 1450.655000 847.360000 1451.920000 847.840000 ;
+ RECT 1450.655000 896.320000 1451.920000 896.800000 ;
+ RECT 1450.655000 841.920000 1451.920000 842.400000 ;
+ RECT 1450.655000 836.480000 1451.920000 836.960000 ;
+ RECT 1450.655000 831.040000 1451.920000 831.520000 ;
+ RECT 1450.655000 825.600000 1451.920000 826.080000 ;
+ RECT 1450.655000 820.160000 1451.920000 820.640000 ;
+ RECT 1450.655000 809.280000 1451.920000 809.760000 ;
+ RECT 1450.655000 814.720000 1451.920000 815.200000 ;
+ RECT 1450.655000 803.840000 1451.920000 804.320000 ;
+ RECT 1450.655000 798.400000 1451.920000 798.880000 ;
+ RECT 1450.655000 792.960000 1451.920000 793.440000 ;
+ RECT 1450.655000 787.520000 1451.920000 788.000000 ;
+ RECT 1450.655000 782.080000 1451.920000 782.560000 ;
+ RECT 1450.655000 776.640000 1451.920000 777.120000 ;
+ RECT 1450.655000 765.760000 1451.920000 766.240000 ;
+ RECT 1450.655000 760.320000 1451.920000 760.800000 ;
+ RECT 1450.655000 754.880000 1451.920000 755.360000 ;
+ RECT 1450.655000 749.440000 1451.920000 749.920000 ;
+ RECT 1450.655000 771.200000 1451.920000 771.680000 ;
+ RECT 1450.655000 744.000000 1451.920000 744.480000 ;
+ RECT 1450.655000 738.560000 1451.920000 739.040000 ;
+ RECT 1450.655000 727.680000 1451.920000 728.160000 ;
+ RECT 1450.655000 733.120000 1451.920000 733.600000 ;
+ RECT 1450.655000 722.240000 1451.920000 722.720000 ;
+ RECT 1450.655000 716.800000 1451.920000 717.280000 ;
+ RECT 1450.655000 711.360000 1451.920000 711.840000 ;
+ RECT 1450.655000 705.920000 1451.920000 706.400000 ;
+ RECT 1450.655000 700.480000 1451.920000 700.960000 ;
+ RECT 1450.655000 695.040000 1451.920000 695.520000 ;
+ RECT 1450.655000 684.160000 1451.920000 684.640000 ;
+ RECT 1450.655000 689.600000 1451.920000 690.080000 ;
+ RECT 1450.655000 678.720000 1451.920000 679.200000 ;
+ RECT 1450.655000 673.280000 1451.920000 673.760000 ;
+ RECT 1450.655000 667.840000 1451.920000 668.320000 ;
+ RECT 1450.655000 662.400000 1451.920000 662.880000 ;
+ RECT 1450.655000 656.960000 1451.920000 657.440000 ;
+ RECT 1450.655000 651.520000 1451.920000 652.000000 ;
+ RECT 1450.655000 640.640000 1451.920000 641.120000 ;
+ RECT 1450.655000 635.200000 1451.920000 635.680000 ;
+ RECT 1450.655000 629.760000 1451.920000 630.240000 ;
+ RECT 1450.655000 624.320000 1451.920000 624.800000 ;
+ RECT 1450.655000 618.880000 1451.920000 619.360000 ;
+ RECT 1450.655000 613.440000 1451.920000 613.920000 ;
+ RECT 1450.655000 602.560000 1451.920000 603.040000 ;
+ RECT 1450.655000 608.000000 1451.920000 608.480000 ;
+ RECT 1450.655000 597.120000 1451.920000 597.600000 ;
+ RECT 1450.655000 591.680000 1451.920000 592.160000 ;
+ RECT 1450.655000 586.240000 1451.920000 586.720000 ;
+ RECT 1450.655000 580.800000 1451.920000 581.280000 ;
+ RECT 1450.655000 575.360000 1451.920000 575.840000 ;
+ RECT 1450.655000 569.920000 1451.920000 570.400000 ;
+ RECT 1450.655000 559.040000 1451.920000 559.520000 ;
+ RECT 1450.655000 564.480000 1451.920000 564.960000 ;
+ RECT 1450.655000 553.600000 1451.920000 554.080000 ;
+ RECT 1450.655000 646.080000 1451.920000 646.560000 ;
+ RECT 1446.990000 546.020000 1447.990000 946.540000 ;
+ RECT 1643.630000 546.020000 1644.630000 946.540000 ;
+ RECT 1450.820000 547.270000 1451.920000 944.610000 ;
+ RECT 1495.820000 547.270000 1496.920000 944.610000 ;
+ RECT 1540.820000 547.270000 1541.920000 944.610000 ;
+ RECT 1585.820000 547.270000 1586.920000 944.610000 ;
+ RECT 1630.820000 547.270000 1631.920000 944.610000 ;
+ LAYER met3 ;
+ RECT 1630.820000 934.400000 1631.920000 934.880000 ;
+ RECT 1630.820000 939.840000 1631.920000 940.320000 ;
+ RECT 1643.630000 934.400000 1644.630000 934.880000 ;
+ RECT 1643.630000 939.840000 1644.630000 940.320000 ;
+ RECT 1630.820000 923.520000 1631.920000 924.000000 ;
+ RECT 1630.820000 928.960000 1631.920000 929.440000 ;
+ RECT 1643.630000 923.520000 1644.630000 924.000000 ;
+ RECT 1643.630000 928.960000 1644.630000 929.440000 ;
+ RECT 1643.630000 912.640000 1644.630000 913.120000 ;
+ RECT 1643.630000 918.080000 1644.630000 918.560000 ;
+ RECT 1630.820000 918.080000 1631.920000 918.560000 ;
+ RECT 1630.820000 912.640000 1631.920000 913.120000 ;
+ RECT 1630.820000 901.760000 1631.920000 902.240000 ;
+ RECT 1630.820000 907.200000 1631.920000 907.680000 ;
+ RECT 1643.630000 901.760000 1644.630000 902.240000 ;
+ RECT 1643.630000 907.200000 1644.630000 907.680000 ;
+ RECT 1585.820000 923.520000 1586.920000 924.000000 ;
+ RECT 1585.820000 928.960000 1586.920000 929.440000 ;
+ RECT 1585.820000 934.400000 1586.920000 934.880000 ;
+ RECT 1585.820000 939.840000 1586.920000 940.320000 ;
+ RECT 1585.820000 907.200000 1586.920000 907.680000 ;
+ RECT 1585.820000 901.760000 1586.920000 902.240000 ;
+ RECT 1585.820000 912.640000 1586.920000 913.120000 ;
+ RECT 1585.820000 918.080000 1586.920000 918.560000 ;
+ RECT 1630.820000 885.440000 1631.920000 885.920000 ;
+ RECT 1630.820000 890.880000 1631.920000 891.360000 ;
+ RECT 1643.630000 885.440000 1644.630000 885.920000 ;
+ RECT 1643.630000 890.880000 1644.630000 891.360000 ;
+ RECT 1643.630000 874.560000 1644.630000 875.040000 ;
+ RECT 1643.630000 880.000000 1644.630000 880.480000 ;
+ RECT 1630.820000 880.000000 1631.920000 880.480000 ;
+ RECT 1630.820000 874.560000 1631.920000 875.040000 ;
+ RECT 1630.820000 863.680000 1631.920000 864.160000 ;
+ RECT 1630.820000 869.120000 1631.920000 869.600000 ;
+ RECT 1643.630000 863.680000 1644.630000 864.160000 ;
+ RECT 1643.630000 869.120000 1644.630000 869.600000 ;
+ RECT 1643.630000 852.800000 1644.630000 853.280000 ;
+ RECT 1643.630000 847.360000 1644.630000 847.840000 ;
+ RECT 1643.630000 858.240000 1644.630000 858.720000 ;
+ RECT 1630.820000 858.240000 1631.920000 858.720000 ;
+ RECT 1630.820000 852.800000 1631.920000 853.280000 ;
+ RECT 1630.820000 847.360000 1631.920000 847.840000 ;
+ RECT 1585.820000 874.560000 1586.920000 875.040000 ;
+ RECT 1585.820000 880.000000 1586.920000 880.480000 ;
+ RECT 1585.820000 885.440000 1586.920000 885.920000 ;
+ RECT 1585.820000 890.880000 1586.920000 891.360000 ;
+ RECT 1585.820000 847.360000 1586.920000 847.840000 ;
+ RECT 1585.820000 852.800000 1586.920000 853.280000 ;
+ RECT 1585.820000 858.240000 1586.920000 858.720000 ;
+ RECT 1585.820000 863.680000 1586.920000 864.160000 ;
+ RECT 1585.820000 869.120000 1586.920000 869.600000 ;
+ RECT 1630.820000 896.320000 1631.920000 896.800000 ;
+ RECT 1585.820000 896.320000 1586.920000 896.800000 ;
+ RECT 1643.630000 896.320000 1644.630000 896.800000 ;
+ RECT 1630.820000 836.480000 1631.920000 836.960000 ;
+ RECT 1630.820000 841.920000 1631.920000 842.400000 ;
+ RECT 1643.630000 836.480000 1644.630000 836.960000 ;
+ RECT 1643.630000 841.920000 1644.630000 842.400000 ;
+ RECT 1630.820000 825.600000 1631.920000 826.080000 ;
+ RECT 1630.820000 831.040000 1631.920000 831.520000 ;
+ RECT 1643.630000 825.600000 1644.630000 826.080000 ;
+ RECT 1643.630000 831.040000 1644.630000 831.520000 ;
+ RECT 1643.630000 814.720000 1644.630000 815.200000 ;
+ RECT 1643.630000 809.280000 1644.630000 809.760000 ;
+ RECT 1643.630000 820.160000 1644.630000 820.640000 ;
+ RECT 1630.820000 820.160000 1631.920000 820.640000 ;
+ RECT 1630.820000 814.720000 1631.920000 815.200000 ;
+ RECT 1630.820000 809.280000 1631.920000 809.760000 ;
+ RECT 1630.820000 798.400000 1631.920000 798.880000 ;
+ RECT 1630.820000 803.840000 1631.920000 804.320000 ;
+ RECT 1643.630000 798.400000 1644.630000 798.880000 ;
+ RECT 1643.630000 803.840000 1644.630000 804.320000 ;
+ RECT 1585.820000 825.600000 1586.920000 826.080000 ;
+ RECT 1585.820000 831.040000 1586.920000 831.520000 ;
+ RECT 1585.820000 836.480000 1586.920000 836.960000 ;
+ RECT 1585.820000 841.920000 1586.920000 842.400000 ;
+ RECT 1585.820000 798.400000 1586.920000 798.880000 ;
+ RECT 1585.820000 803.840000 1586.920000 804.320000 ;
+ RECT 1585.820000 809.280000 1586.920000 809.760000 ;
+ RECT 1585.820000 814.720000 1586.920000 815.200000 ;
+ RECT 1585.820000 820.160000 1586.920000 820.640000 ;
+ RECT 1643.630000 787.520000 1644.630000 788.000000 ;
+ RECT 1643.630000 792.960000 1644.630000 793.440000 ;
+ RECT 1630.820000 792.960000 1631.920000 793.440000 ;
+ RECT 1630.820000 787.520000 1631.920000 788.000000 ;
+ RECT 1630.820000 776.640000 1631.920000 777.120000 ;
+ RECT 1630.820000 782.080000 1631.920000 782.560000 ;
+ RECT 1643.630000 776.640000 1644.630000 777.120000 ;
+ RECT 1643.630000 782.080000 1644.630000 782.560000 ;
+ RECT 1630.820000 760.320000 1631.920000 760.800000 ;
+ RECT 1630.820000 765.760000 1631.920000 766.240000 ;
+ RECT 1643.630000 760.320000 1644.630000 760.800000 ;
+ RECT 1643.630000 765.760000 1644.630000 766.240000 ;
+ RECT 1643.630000 749.440000 1644.630000 749.920000 ;
+ RECT 1643.630000 754.880000 1644.630000 755.360000 ;
+ RECT 1630.820000 754.880000 1631.920000 755.360000 ;
+ RECT 1630.820000 749.440000 1631.920000 749.920000 ;
+ RECT 1630.820000 771.200000 1631.920000 771.680000 ;
+ RECT 1643.630000 771.200000 1644.630000 771.680000 ;
+ RECT 1585.820000 776.640000 1586.920000 777.120000 ;
+ RECT 1585.820000 782.080000 1586.920000 782.560000 ;
+ RECT 1585.820000 787.520000 1586.920000 788.000000 ;
+ RECT 1585.820000 792.960000 1586.920000 793.440000 ;
+ RECT 1585.820000 749.440000 1586.920000 749.920000 ;
+ RECT 1585.820000 754.880000 1586.920000 755.360000 ;
+ RECT 1585.820000 760.320000 1586.920000 760.800000 ;
+ RECT 1585.820000 765.760000 1586.920000 766.240000 ;
+ RECT 1585.820000 771.200000 1586.920000 771.680000 ;
+ RECT 1540.820000 928.960000 1541.920000 929.440000 ;
+ RECT 1540.820000 923.520000 1541.920000 924.000000 ;
+ RECT 1540.820000 934.400000 1541.920000 934.880000 ;
+ RECT 1540.820000 939.840000 1541.920000 940.320000 ;
+ RECT 1495.820000 923.520000 1496.920000 924.000000 ;
+ RECT 1495.820000 928.960000 1496.920000 929.440000 ;
+ RECT 1495.820000 934.400000 1496.920000 934.880000 ;
+ RECT 1495.820000 939.840000 1496.920000 940.320000 ;
+ RECT 1540.820000 901.760000 1541.920000 902.240000 ;
+ RECT 1540.820000 907.200000 1541.920000 907.680000 ;
+ RECT 1540.820000 912.640000 1541.920000 913.120000 ;
+ RECT 1540.820000 918.080000 1541.920000 918.560000 ;
+ RECT 1495.820000 901.760000 1496.920000 902.240000 ;
+ RECT 1495.820000 907.200000 1496.920000 907.680000 ;
+ RECT 1495.820000 912.640000 1496.920000 913.120000 ;
+ RECT 1495.820000 918.080000 1496.920000 918.560000 ;
+ RECT 1446.990000 934.400000 1447.990000 934.880000 ;
+ RECT 1450.655000 934.400000 1451.920000 934.880000 ;
+ RECT 1446.990000 939.840000 1447.990000 940.320000 ;
+ RECT 1450.655000 939.840000 1451.920000 940.320000 ;
+ RECT 1446.990000 928.960000 1447.990000 929.440000 ;
+ RECT 1450.655000 928.960000 1451.920000 929.440000 ;
+ RECT 1446.990000 923.520000 1447.990000 924.000000 ;
+ RECT 1450.655000 923.520000 1451.920000 924.000000 ;
+ RECT 1446.990000 918.080000 1447.990000 918.560000 ;
+ RECT 1450.655000 918.080000 1451.920000 918.560000 ;
+ RECT 1446.990000 912.640000 1447.990000 913.120000 ;
+ RECT 1450.655000 912.640000 1451.920000 913.120000 ;
+ RECT 1446.990000 907.200000 1447.990000 907.680000 ;
+ RECT 1450.655000 907.200000 1451.920000 907.680000 ;
+ RECT 1446.990000 901.760000 1447.990000 902.240000 ;
+ RECT 1450.655000 901.760000 1451.920000 902.240000 ;
+ RECT 1540.820000 874.560000 1541.920000 875.040000 ;
+ RECT 1540.820000 880.000000 1541.920000 880.480000 ;
+ RECT 1540.820000 885.440000 1541.920000 885.920000 ;
+ RECT 1540.820000 890.880000 1541.920000 891.360000 ;
+ RECT 1495.820000 874.560000 1496.920000 875.040000 ;
+ RECT 1495.820000 880.000000 1496.920000 880.480000 ;
+ RECT 1495.820000 885.440000 1496.920000 885.920000 ;
+ RECT 1495.820000 890.880000 1496.920000 891.360000 ;
+ RECT 1540.820000 847.360000 1541.920000 847.840000 ;
+ RECT 1540.820000 852.800000 1541.920000 853.280000 ;
+ RECT 1540.820000 858.240000 1541.920000 858.720000 ;
+ RECT 1540.820000 863.680000 1541.920000 864.160000 ;
+ RECT 1540.820000 869.120000 1541.920000 869.600000 ;
+ RECT 1495.820000 847.360000 1496.920000 847.840000 ;
+ RECT 1495.820000 852.800000 1496.920000 853.280000 ;
+ RECT 1495.820000 858.240000 1496.920000 858.720000 ;
+ RECT 1495.820000 863.680000 1496.920000 864.160000 ;
+ RECT 1495.820000 869.120000 1496.920000 869.600000 ;
+ RECT 1446.990000 890.880000 1447.990000 891.360000 ;
+ RECT 1450.655000 890.880000 1451.920000 891.360000 ;
+ RECT 1446.990000 885.440000 1447.990000 885.920000 ;
+ RECT 1450.655000 885.440000 1451.920000 885.920000 ;
+ RECT 1446.990000 880.000000 1447.990000 880.480000 ;
+ RECT 1450.655000 880.000000 1451.920000 880.480000 ;
+ RECT 1446.990000 874.560000 1447.990000 875.040000 ;
+ RECT 1450.655000 874.560000 1451.920000 875.040000 ;
+ RECT 1446.990000 869.120000 1447.990000 869.600000 ;
+ RECT 1450.655000 869.120000 1451.920000 869.600000 ;
+ RECT 1446.990000 863.680000 1447.990000 864.160000 ;
+ RECT 1450.655000 863.680000 1451.920000 864.160000 ;
+ RECT 1446.990000 852.800000 1447.990000 853.280000 ;
+ RECT 1450.655000 852.800000 1451.920000 853.280000 ;
+ RECT 1446.990000 858.240000 1447.990000 858.720000 ;
+ RECT 1450.655000 858.240000 1451.920000 858.720000 ;
+ RECT 1446.990000 847.360000 1447.990000 847.840000 ;
+ RECT 1450.655000 847.360000 1451.920000 847.840000 ;
+ RECT 1540.820000 896.320000 1541.920000 896.800000 ;
+ RECT 1495.820000 896.320000 1496.920000 896.800000 ;
+ RECT 1446.990000 896.320000 1447.990000 896.800000 ;
+ RECT 1450.655000 896.320000 1451.920000 896.800000 ;
+ RECT 1540.820000 825.600000 1541.920000 826.080000 ;
+ RECT 1540.820000 831.040000 1541.920000 831.520000 ;
+ RECT 1540.820000 836.480000 1541.920000 836.960000 ;
+ RECT 1540.820000 841.920000 1541.920000 842.400000 ;
+ RECT 1495.820000 825.600000 1496.920000 826.080000 ;
+ RECT 1495.820000 831.040000 1496.920000 831.520000 ;
+ RECT 1495.820000 836.480000 1496.920000 836.960000 ;
+ RECT 1495.820000 841.920000 1496.920000 842.400000 ;
+ RECT 1540.820000 798.400000 1541.920000 798.880000 ;
+ RECT 1540.820000 803.840000 1541.920000 804.320000 ;
+ RECT 1540.820000 809.280000 1541.920000 809.760000 ;
+ RECT 1540.820000 814.720000 1541.920000 815.200000 ;
+ RECT 1540.820000 820.160000 1541.920000 820.640000 ;
+ RECT 1495.820000 798.400000 1496.920000 798.880000 ;
+ RECT 1495.820000 803.840000 1496.920000 804.320000 ;
+ RECT 1495.820000 809.280000 1496.920000 809.760000 ;
+ RECT 1495.820000 814.720000 1496.920000 815.200000 ;
+ RECT 1495.820000 820.160000 1496.920000 820.640000 ;
+ RECT 1446.990000 841.920000 1447.990000 842.400000 ;
+ RECT 1450.655000 841.920000 1451.920000 842.400000 ;
+ RECT 1446.990000 836.480000 1447.990000 836.960000 ;
+ RECT 1450.655000 836.480000 1451.920000 836.960000 ;
+ RECT 1446.990000 831.040000 1447.990000 831.520000 ;
+ RECT 1450.655000 831.040000 1451.920000 831.520000 ;
+ RECT 1446.990000 825.600000 1447.990000 826.080000 ;
+ RECT 1450.655000 825.600000 1451.920000 826.080000 ;
+ RECT 1446.990000 820.160000 1447.990000 820.640000 ;
+ RECT 1450.655000 820.160000 1451.920000 820.640000 ;
+ RECT 1446.990000 809.280000 1447.990000 809.760000 ;
+ RECT 1450.655000 809.280000 1451.920000 809.760000 ;
+ RECT 1446.990000 814.720000 1447.990000 815.200000 ;
+ RECT 1450.655000 814.720000 1451.920000 815.200000 ;
+ RECT 1446.990000 803.840000 1447.990000 804.320000 ;
+ RECT 1450.655000 803.840000 1451.920000 804.320000 ;
+ RECT 1446.990000 798.400000 1447.990000 798.880000 ;
+ RECT 1450.655000 798.400000 1451.920000 798.880000 ;
+ RECT 1540.820000 776.640000 1541.920000 777.120000 ;
+ RECT 1540.820000 782.080000 1541.920000 782.560000 ;
+ RECT 1540.820000 787.520000 1541.920000 788.000000 ;
+ RECT 1540.820000 792.960000 1541.920000 793.440000 ;
+ RECT 1495.820000 776.640000 1496.920000 777.120000 ;
+ RECT 1495.820000 782.080000 1496.920000 782.560000 ;
+ RECT 1495.820000 787.520000 1496.920000 788.000000 ;
+ RECT 1495.820000 792.960000 1496.920000 793.440000 ;
+ RECT 1540.820000 749.440000 1541.920000 749.920000 ;
+ RECT 1540.820000 754.880000 1541.920000 755.360000 ;
+ RECT 1540.820000 760.320000 1541.920000 760.800000 ;
+ RECT 1540.820000 765.760000 1541.920000 766.240000 ;
+ RECT 1495.820000 749.440000 1496.920000 749.920000 ;
+ RECT 1495.820000 754.880000 1496.920000 755.360000 ;
+ RECT 1495.820000 760.320000 1496.920000 760.800000 ;
+ RECT 1495.820000 765.760000 1496.920000 766.240000 ;
+ RECT 1540.820000 771.200000 1541.920000 771.680000 ;
+ RECT 1495.820000 771.200000 1496.920000 771.680000 ;
+ RECT 1446.990000 792.960000 1447.990000 793.440000 ;
+ RECT 1450.655000 792.960000 1451.920000 793.440000 ;
+ RECT 1446.990000 787.520000 1447.990000 788.000000 ;
+ RECT 1450.655000 787.520000 1451.920000 788.000000 ;
+ RECT 1446.990000 782.080000 1447.990000 782.560000 ;
+ RECT 1450.655000 782.080000 1451.920000 782.560000 ;
+ RECT 1446.990000 776.640000 1447.990000 777.120000 ;
+ RECT 1450.655000 776.640000 1451.920000 777.120000 ;
+ RECT 1446.990000 765.760000 1447.990000 766.240000 ;
+ RECT 1450.655000 765.760000 1451.920000 766.240000 ;
+ RECT 1446.990000 760.320000 1447.990000 760.800000 ;
+ RECT 1450.655000 760.320000 1451.920000 760.800000 ;
+ RECT 1446.990000 754.880000 1447.990000 755.360000 ;
+ RECT 1450.655000 754.880000 1451.920000 755.360000 ;
+ RECT 1446.990000 749.440000 1447.990000 749.920000 ;
+ RECT 1450.655000 749.440000 1451.920000 749.920000 ;
+ RECT 1446.990000 771.200000 1447.990000 771.680000 ;
+ RECT 1450.655000 771.200000 1451.920000 771.680000 ;
+ RECT 1630.820000 738.560000 1631.920000 739.040000 ;
+ RECT 1630.820000 744.000000 1631.920000 744.480000 ;
+ RECT 1643.630000 738.560000 1644.630000 739.040000 ;
+ RECT 1643.630000 744.000000 1644.630000 744.480000 ;
+ RECT 1643.630000 727.680000 1644.630000 728.160000 ;
+ RECT 1643.630000 722.240000 1644.630000 722.720000 ;
+ RECT 1643.630000 733.120000 1644.630000 733.600000 ;
+ RECT 1630.820000 733.120000 1631.920000 733.600000 ;
+ RECT 1630.820000 727.680000 1631.920000 728.160000 ;
+ RECT 1630.820000 722.240000 1631.920000 722.720000 ;
+ RECT 1630.820000 711.360000 1631.920000 711.840000 ;
+ RECT 1630.820000 716.800000 1631.920000 717.280000 ;
+ RECT 1643.630000 711.360000 1644.630000 711.840000 ;
+ RECT 1643.630000 716.800000 1644.630000 717.280000 ;
+ RECT 1630.820000 700.480000 1631.920000 700.960000 ;
+ RECT 1630.820000 705.920000 1631.920000 706.400000 ;
+ RECT 1643.630000 700.480000 1644.630000 700.960000 ;
+ RECT 1643.630000 705.920000 1644.630000 706.400000 ;
+ RECT 1585.820000 722.240000 1586.920000 722.720000 ;
+ RECT 1585.820000 727.680000 1586.920000 728.160000 ;
+ RECT 1585.820000 733.120000 1586.920000 733.600000 ;
+ RECT 1585.820000 738.560000 1586.920000 739.040000 ;
+ RECT 1585.820000 744.000000 1586.920000 744.480000 ;
+ RECT 1585.820000 700.480000 1586.920000 700.960000 ;
+ RECT 1585.820000 705.920000 1586.920000 706.400000 ;
+ RECT 1585.820000 711.360000 1586.920000 711.840000 ;
+ RECT 1585.820000 716.800000 1586.920000 717.280000 ;
+ RECT 1643.630000 689.600000 1644.630000 690.080000 ;
+ RECT 1643.630000 684.160000 1644.630000 684.640000 ;
+ RECT 1643.630000 695.040000 1644.630000 695.520000 ;
+ RECT 1630.820000 695.040000 1631.920000 695.520000 ;
+ RECT 1630.820000 689.600000 1631.920000 690.080000 ;
+ RECT 1630.820000 684.160000 1631.920000 684.640000 ;
+ RECT 1630.820000 673.280000 1631.920000 673.760000 ;
+ RECT 1630.820000 678.720000 1631.920000 679.200000 ;
+ RECT 1643.630000 673.280000 1644.630000 673.760000 ;
+ RECT 1643.630000 678.720000 1644.630000 679.200000 ;
+ RECT 1643.630000 662.400000 1644.630000 662.880000 ;
+ RECT 1643.630000 667.840000 1644.630000 668.320000 ;
+ RECT 1630.820000 667.840000 1631.920000 668.320000 ;
+ RECT 1630.820000 662.400000 1631.920000 662.880000 ;
+ RECT 1630.820000 651.520000 1631.920000 652.000000 ;
+ RECT 1630.820000 656.960000 1631.920000 657.440000 ;
+ RECT 1643.630000 651.520000 1644.630000 652.000000 ;
+ RECT 1643.630000 656.960000 1644.630000 657.440000 ;
+ RECT 1585.820000 673.280000 1586.920000 673.760000 ;
+ RECT 1585.820000 678.720000 1586.920000 679.200000 ;
+ RECT 1585.820000 684.160000 1586.920000 684.640000 ;
+ RECT 1585.820000 689.600000 1586.920000 690.080000 ;
+ RECT 1585.820000 695.040000 1586.920000 695.520000 ;
+ RECT 1585.820000 651.520000 1586.920000 652.000000 ;
+ RECT 1585.820000 656.960000 1586.920000 657.440000 ;
+ RECT 1585.820000 662.400000 1586.920000 662.880000 ;
+ RECT 1585.820000 667.840000 1586.920000 668.320000 ;
+ RECT 1630.820000 635.200000 1631.920000 635.680000 ;
+ RECT 1630.820000 640.640000 1631.920000 641.120000 ;
+ RECT 1643.630000 635.200000 1644.630000 635.680000 ;
+ RECT 1643.630000 640.640000 1644.630000 641.120000 ;
+ RECT 1643.630000 624.320000 1644.630000 624.800000 ;
+ RECT 1643.630000 629.760000 1644.630000 630.240000 ;
+ RECT 1630.820000 629.760000 1631.920000 630.240000 ;
+ RECT 1630.820000 624.320000 1631.920000 624.800000 ;
+ RECT 1630.820000 613.440000 1631.920000 613.920000 ;
+ RECT 1630.820000 618.880000 1631.920000 619.360000 ;
+ RECT 1643.630000 613.440000 1644.630000 613.920000 ;
+ RECT 1643.630000 618.880000 1644.630000 619.360000 ;
+ RECT 1643.630000 602.560000 1644.630000 603.040000 ;
+ RECT 1643.630000 597.120000 1644.630000 597.600000 ;
+ RECT 1643.630000 608.000000 1644.630000 608.480000 ;
+ RECT 1630.820000 608.000000 1631.920000 608.480000 ;
+ RECT 1630.820000 602.560000 1631.920000 603.040000 ;
+ RECT 1630.820000 597.120000 1631.920000 597.600000 ;
+ RECT 1585.820000 624.320000 1586.920000 624.800000 ;
+ RECT 1585.820000 629.760000 1586.920000 630.240000 ;
+ RECT 1585.820000 635.200000 1586.920000 635.680000 ;
+ RECT 1585.820000 640.640000 1586.920000 641.120000 ;
+ RECT 1585.820000 597.120000 1586.920000 597.600000 ;
+ RECT 1585.820000 602.560000 1586.920000 603.040000 ;
+ RECT 1585.820000 608.000000 1586.920000 608.480000 ;
+ RECT 1585.820000 613.440000 1586.920000 613.920000 ;
+ RECT 1585.820000 618.880000 1586.920000 619.360000 ;
+ RECT 1630.820000 586.240000 1631.920000 586.720000 ;
+ RECT 1630.820000 591.680000 1631.920000 592.160000 ;
+ RECT 1643.630000 586.240000 1644.630000 586.720000 ;
+ RECT 1643.630000 591.680000 1644.630000 592.160000 ;
+ RECT 1630.820000 575.360000 1631.920000 575.840000 ;
+ RECT 1630.820000 580.800000 1631.920000 581.280000 ;
+ RECT 1643.630000 575.360000 1644.630000 575.840000 ;
+ RECT 1643.630000 580.800000 1644.630000 581.280000 ;
+ RECT 1643.630000 564.480000 1644.630000 564.960000 ;
+ RECT 1643.630000 559.040000 1644.630000 559.520000 ;
+ RECT 1643.630000 569.920000 1644.630000 570.400000 ;
+ RECT 1630.820000 569.920000 1631.920000 570.400000 ;
+ RECT 1630.820000 564.480000 1631.920000 564.960000 ;
+ RECT 1630.820000 559.040000 1631.920000 559.520000 ;
+ RECT 1630.820000 553.600000 1631.920000 554.080000 ;
+ RECT 1643.630000 553.600000 1644.630000 554.080000 ;
+ RECT 1585.820000 575.360000 1586.920000 575.840000 ;
+ RECT 1585.820000 580.800000 1586.920000 581.280000 ;
+ RECT 1585.820000 586.240000 1586.920000 586.720000 ;
+ RECT 1585.820000 591.680000 1586.920000 592.160000 ;
+ RECT 1585.820000 553.600000 1586.920000 554.080000 ;
+ RECT 1585.820000 559.040000 1586.920000 559.520000 ;
+ RECT 1585.820000 564.480000 1586.920000 564.960000 ;
+ RECT 1585.820000 569.920000 1586.920000 570.400000 ;
+ RECT 1630.820000 646.080000 1631.920000 646.560000 ;
+ RECT 1585.820000 646.080000 1586.920000 646.560000 ;
+ RECT 1643.630000 646.080000 1644.630000 646.560000 ;
+ RECT 1540.820000 722.240000 1541.920000 722.720000 ;
+ RECT 1540.820000 727.680000 1541.920000 728.160000 ;
+ RECT 1540.820000 733.120000 1541.920000 733.600000 ;
+ RECT 1540.820000 738.560000 1541.920000 739.040000 ;
+ RECT 1540.820000 744.000000 1541.920000 744.480000 ;
+ RECT 1495.820000 722.240000 1496.920000 722.720000 ;
+ RECT 1495.820000 727.680000 1496.920000 728.160000 ;
+ RECT 1495.820000 733.120000 1496.920000 733.600000 ;
+ RECT 1495.820000 738.560000 1496.920000 739.040000 ;
+ RECT 1495.820000 744.000000 1496.920000 744.480000 ;
+ RECT 1540.820000 700.480000 1541.920000 700.960000 ;
+ RECT 1540.820000 705.920000 1541.920000 706.400000 ;
+ RECT 1540.820000 711.360000 1541.920000 711.840000 ;
+ RECT 1540.820000 716.800000 1541.920000 717.280000 ;
+ RECT 1495.820000 700.480000 1496.920000 700.960000 ;
+ RECT 1495.820000 705.920000 1496.920000 706.400000 ;
+ RECT 1495.820000 711.360000 1496.920000 711.840000 ;
+ RECT 1495.820000 716.800000 1496.920000 717.280000 ;
+ RECT 1446.990000 744.000000 1447.990000 744.480000 ;
+ RECT 1450.655000 744.000000 1451.920000 744.480000 ;
+ RECT 1446.990000 738.560000 1447.990000 739.040000 ;
+ RECT 1450.655000 738.560000 1451.920000 739.040000 ;
+ RECT 1446.990000 727.680000 1447.990000 728.160000 ;
+ RECT 1450.655000 727.680000 1451.920000 728.160000 ;
+ RECT 1446.990000 733.120000 1447.990000 733.600000 ;
+ RECT 1450.655000 733.120000 1451.920000 733.600000 ;
+ RECT 1446.990000 722.240000 1447.990000 722.720000 ;
+ RECT 1450.655000 722.240000 1451.920000 722.720000 ;
+ RECT 1446.990000 716.800000 1447.990000 717.280000 ;
+ RECT 1450.655000 716.800000 1451.920000 717.280000 ;
+ RECT 1446.990000 711.360000 1447.990000 711.840000 ;
+ RECT 1450.655000 711.360000 1451.920000 711.840000 ;
+ RECT 1446.990000 705.920000 1447.990000 706.400000 ;
+ RECT 1450.655000 705.920000 1451.920000 706.400000 ;
+ RECT 1446.990000 700.480000 1447.990000 700.960000 ;
+ RECT 1450.655000 700.480000 1451.920000 700.960000 ;
+ RECT 1540.820000 673.280000 1541.920000 673.760000 ;
+ RECT 1540.820000 678.720000 1541.920000 679.200000 ;
+ RECT 1540.820000 684.160000 1541.920000 684.640000 ;
+ RECT 1540.820000 689.600000 1541.920000 690.080000 ;
+ RECT 1540.820000 695.040000 1541.920000 695.520000 ;
+ RECT 1495.820000 673.280000 1496.920000 673.760000 ;
+ RECT 1495.820000 678.720000 1496.920000 679.200000 ;
+ RECT 1495.820000 684.160000 1496.920000 684.640000 ;
+ RECT 1495.820000 689.600000 1496.920000 690.080000 ;
+ RECT 1495.820000 695.040000 1496.920000 695.520000 ;
+ RECT 1540.820000 651.520000 1541.920000 652.000000 ;
+ RECT 1540.820000 656.960000 1541.920000 657.440000 ;
+ RECT 1540.820000 662.400000 1541.920000 662.880000 ;
+ RECT 1540.820000 667.840000 1541.920000 668.320000 ;
+ RECT 1495.820000 651.520000 1496.920000 652.000000 ;
+ RECT 1495.820000 656.960000 1496.920000 657.440000 ;
+ RECT 1495.820000 662.400000 1496.920000 662.880000 ;
+ RECT 1495.820000 667.840000 1496.920000 668.320000 ;
+ RECT 1446.990000 695.040000 1447.990000 695.520000 ;
+ RECT 1450.655000 695.040000 1451.920000 695.520000 ;
+ RECT 1446.990000 684.160000 1447.990000 684.640000 ;
+ RECT 1450.655000 684.160000 1451.920000 684.640000 ;
+ RECT 1446.990000 689.600000 1447.990000 690.080000 ;
+ RECT 1450.655000 689.600000 1451.920000 690.080000 ;
+ RECT 1446.990000 678.720000 1447.990000 679.200000 ;
+ RECT 1450.655000 678.720000 1451.920000 679.200000 ;
+ RECT 1446.990000 673.280000 1447.990000 673.760000 ;
+ RECT 1450.655000 673.280000 1451.920000 673.760000 ;
+ RECT 1446.990000 667.840000 1447.990000 668.320000 ;
+ RECT 1450.655000 667.840000 1451.920000 668.320000 ;
+ RECT 1446.990000 662.400000 1447.990000 662.880000 ;
+ RECT 1450.655000 662.400000 1451.920000 662.880000 ;
+ RECT 1446.990000 656.960000 1447.990000 657.440000 ;
+ RECT 1450.655000 656.960000 1451.920000 657.440000 ;
+ RECT 1446.990000 651.520000 1447.990000 652.000000 ;
+ RECT 1450.655000 651.520000 1451.920000 652.000000 ;
+ RECT 1540.820000 624.320000 1541.920000 624.800000 ;
+ RECT 1540.820000 629.760000 1541.920000 630.240000 ;
+ RECT 1540.820000 635.200000 1541.920000 635.680000 ;
+ RECT 1540.820000 640.640000 1541.920000 641.120000 ;
+ RECT 1495.820000 624.320000 1496.920000 624.800000 ;
+ RECT 1495.820000 629.760000 1496.920000 630.240000 ;
+ RECT 1495.820000 635.200000 1496.920000 635.680000 ;
+ RECT 1495.820000 640.640000 1496.920000 641.120000 ;
+ RECT 1540.820000 597.120000 1541.920000 597.600000 ;
+ RECT 1540.820000 602.560000 1541.920000 603.040000 ;
+ RECT 1540.820000 608.000000 1541.920000 608.480000 ;
+ RECT 1540.820000 613.440000 1541.920000 613.920000 ;
+ RECT 1540.820000 618.880000 1541.920000 619.360000 ;
+ RECT 1495.820000 597.120000 1496.920000 597.600000 ;
+ RECT 1495.820000 602.560000 1496.920000 603.040000 ;
+ RECT 1495.820000 608.000000 1496.920000 608.480000 ;
+ RECT 1495.820000 613.440000 1496.920000 613.920000 ;
+ RECT 1495.820000 618.880000 1496.920000 619.360000 ;
+ RECT 1446.990000 640.640000 1447.990000 641.120000 ;
+ RECT 1450.655000 640.640000 1451.920000 641.120000 ;
+ RECT 1446.990000 635.200000 1447.990000 635.680000 ;
+ RECT 1450.655000 635.200000 1451.920000 635.680000 ;
+ RECT 1446.990000 629.760000 1447.990000 630.240000 ;
+ RECT 1450.655000 629.760000 1451.920000 630.240000 ;
+ RECT 1446.990000 624.320000 1447.990000 624.800000 ;
+ RECT 1450.655000 624.320000 1451.920000 624.800000 ;
+ RECT 1446.990000 618.880000 1447.990000 619.360000 ;
+ RECT 1450.655000 618.880000 1451.920000 619.360000 ;
+ RECT 1446.990000 613.440000 1447.990000 613.920000 ;
+ RECT 1450.655000 613.440000 1451.920000 613.920000 ;
+ RECT 1446.990000 602.560000 1447.990000 603.040000 ;
+ RECT 1450.655000 602.560000 1451.920000 603.040000 ;
+ RECT 1446.990000 608.000000 1447.990000 608.480000 ;
+ RECT 1450.655000 608.000000 1451.920000 608.480000 ;
+ RECT 1446.990000 597.120000 1447.990000 597.600000 ;
+ RECT 1450.655000 597.120000 1451.920000 597.600000 ;
+ RECT 1540.820000 575.360000 1541.920000 575.840000 ;
+ RECT 1540.820000 580.800000 1541.920000 581.280000 ;
+ RECT 1540.820000 586.240000 1541.920000 586.720000 ;
+ RECT 1540.820000 591.680000 1541.920000 592.160000 ;
+ RECT 1495.820000 575.360000 1496.920000 575.840000 ;
+ RECT 1495.820000 580.800000 1496.920000 581.280000 ;
+ RECT 1495.820000 586.240000 1496.920000 586.720000 ;
+ RECT 1495.820000 591.680000 1496.920000 592.160000 ;
+ RECT 1540.820000 553.600000 1541.920000 554.080000 ;
+ RECT 1540.820000 559.040000 1541.920000 559.520000 ;
+ RECT 1540.820000 564.480000 1541.920000 564.960000 ;
+ RECT 1540.820000 569.920000 1541.920000 570.400000 ;
+ RECT 1495.820000 553.600000 1496.920000 554.080000 ;
+ RECT 1495.820000 559.040000 1496.920000 559.520000 ;
+ RECT 1495.820000 564.480000 1496.920000 564.960000 ;
+ RECT 1495.820000 569.920000 1496.920000 570.400000 ;
+ RECT 1446.990000 591.680000 1447.990000 592.160000 ;
+ RECT 1450.655000 591.680000 1451.920000 592.160000 ;
+ RECT 1446.990000 586.240000 1447.990000 586.720000 ;
+ RECT 1450.655000 586.240000 1451.920000 586.720000 ;
+ RECT 1446.990000 580.800000 1447.990000 581.280000 ;
+ RECT 1450.655000 580.800000 1451.920000 581.280000 ;
+ RECT 1446.990000 575.360000 1447.990000 575.840000 ;
+ RECT 1450.655000 575.360000 1451.920000 575.840000 ;
+ RECT 1446.990000 569.920000 1447.990000 570.400000 ;
+ RECT 1450.655000 569.920000 1451.920000 570.400000 ;
+ RECT 1446.990000 559.040000 1447.990000 559.520000 ;
+ RECT 1450.655000 559.040000 1451.920000 559.520000 ;
+ RECT 1446.990000 564.480000 1447.990000 564.960000 ;
+ RECT 1450.655000 564.480000 1451.920000 564.960000 ;
+ RECT 1446.990000 553.600000 1447.990000 554.080000 ;
+ RECT 1450.655000 553.600000 1451.920000 554.080000 ;
+ RECT 1540.820000 646.080000 1541.920000 646.560000 ;
+ RECT 1495.820000 646.080000 1496.920000 646.560000 ;
+ RECT 1446.990000 646.080000 1447.990000 646.560000 ;
+ RECT 1450.655000 646.080000 1451.920000 646.560000 ;
+ RECT 1445.760000 943.610000 1645.860000 944.610000 ;
+ RECT 1445.760000 547.270000 1645.860000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 546.020000 1447.990000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 945.540000 1447.990000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 546.020000 1644.630000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 945.540000 1644.630000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 547.270000 1446.760000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 547.270000 1645.860000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 943.610000 1446.760000 944.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 943.610000 1645.860000 944.610000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1450.655000 533.880000 1451.920000 534.360000 ;
+ RECT 1450.655000 539.320000 1451.920000 539.800000 ;
+ RECT 1450.655000 528.440000 1451.920000 528.920000 ;
+ RECT 1450.655000 523.000000 1451.920000 523.480000 ;
+ RECT 1450.655000 517.560000 1451.920000 518.040000 ;
+ RECT 1450.655000 512.120000 1451.920000 512.600000 ;
+ RECT 1450.655000 506.680000 1451.920000 507.160000 ;
+ RECT 1450.655000 501.240000 1451.920000 501.720000 ;
+ RECT 1450.655000 490.360000 1451.920000 490.840000 ;
+ RECT 1450.655000 484.920000 1451.920000 485.400000 ;
+ RECT 1450.655000 479.480000 1451.920000 479.960000 ;
+ RECT 1450.655000 474.040000 1451.920000 474.520000 ;
+ RECT 1450.655000 468.600000 1451.920000 469.080000 ;
+ RECT 1450.655000 463.160000 1451.920000 463.640000 ;
+ RECT 1450.655000 452.280000 1451.920000 452.760000 ;
+ RECT 1450.655000 457.720000 1451.920000 458.200000 ;
+ RECT 1450.655000 446.840000 1451.920000 447.320000 ;
+ RECT 1450.655000 495.800000 1451.920000 496.280000 ;
+ RECT 1450.655000 441.400000 1451.920000 441.880000 ;
+ RECT 1450.655000 435.960000 1451.920000 436.440000 ;
+ RECT 1450.655000 430.520000 1451.920000 431.000000 ;
+ RECT 1450.655000 425.080000 1451.920000 425.560000 ;
+ RECT 1450.655000 419.640000 1451.920000 420.120000 ;
+ RECT 1450.655000 408.760000 1451.920000 409.240000 ;
+ RECT 1450.655000 414.200000 1451.920000 414.680000 ;
+ RECT 1450.655000 403.320000 1451.920000 403.800000 ;
+ RECT 1450.655000 397.880000 1451.920000 398.360000 ;
+ RECT 1450.655000 392.440000 1451.920000 392.920000 ;
+ RECT 1450.655000 387.000000 1451.920000 387.480000 ;
+ RECT 1450.655000 381.560000 1451.920000 382.040000 ;
+ RECT 1450.655000 376.120000 1451.920000 376.600000 ;
+ RECT 1450.655000 365.240000 1451.920000 365.720000 ;
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+ RECT 1630.820000 251.000000 1631.920000 251.480000 ;
+ RECT 1630.820000 256.440000 1631.920000 256.920000 ;
+ RECT 1643.630000 251.000000 1644.630000 251.480000 ;
+ RECT 1643.630000 256.440000 1644.630000 256.920000 ;
+ RECT 1585.820000 272.760000 1586.920000 273.240000 ;
+ RECT 1585.820000 278.200000 1586.920000 278.680000 ;
+ RECT 1585.820000 283.640000 1586.920000 284.120000 ;
+ RECT 1585.820000 289.080000 1586.920000 289.560000 ;
+ RECT 1585.820000 294.520000 1586.920000 295.000000 ;
+ RECT 1585.820000 251.000000 1586.920000 251.480000 ;
+ RECT 1585.820000 256.440000 1586.920000 256.920000 ;
+ RECT 1585.820000 261.880000 1586.920000 262.360000 ;
+ RECT 1585.820000 267.320000 1586.920000 267.800000 ;
+ RECT 1630.820000 234.680000 1631.920000 235.160000 ;
+ RECT 1630.820000 240.120000 1631.920000 240.600000 ;
+ RECT 1643.630000 234.680000 1644.630000 235.160000 ;
+ RECT 1643.630000 240.120000 1644.630000 240.600000 ;
+ RECT 1643.630000 223.800000 1644.630000 224.280000 ;
+ RECT 1643.630000 229.240000 1644.630000 229.720000 ;
+ RECT 1630.820000 229.240000 1631.920000 229.720000 ;
+ RECT 1630.820000 223.800000 1631.920000 224.280000 ;
+ RECT 1630.820000 212.920000 1631.920000 213.400000 ;
+ RECT 1630.820000 218.360000 1631.920000 218.840000 ;
+ RECT 1643.630000 212.920000 1644.630000 213.400000 ;
+ RECT 1643.630000 218.360000 1644.630000 218.840000 ;
+ RECT 1643.630000 202.040000 1644.630000 202.520000 ;
+ RECT 1643.630000 196.600000 1644.630000 197.080000 ;
+ RECT 1643.630000 207.480000 1644.630000 207.960000 ;
+ RECT 1630.820000 207.480000 1631.920000 207.960000 ;
+ RECT 1630.820000 202.040000 1631.920000 202.520000 ;
+ RECT 1630.820000 196.600000 1631.920000 197.080000 ;
+ RECT 1585.820000 223.800000 1586.920000 224.280000 ;
+ RECT 1585.820000 229.240000 1586.920000 229.720000 ;
+ RECT 1585.820000 234.680000 1586.920000 235.160000 ;
+ RECT 1585.820000 240.120000 1586.920000 240.600000 ;
+ RECT 1585.820000 196.600000 1586.920000 197.080000 ;
+ RECT 1585.820000 202.040000 1586.920000 202.520000 ;
+ RECT 1585.820000 207.480000 1586.920000 207.960000 ;
+ RECT 1585.820000 212.920000 1586.920000 213.400000 ;
+ RECT 1585.820000 218.360000 1586.920000 218.840000 ;
+ RECT 1630.820000 185.720000 1631.920000 186.200000 ;
+ RECT 1630.820000 191.160000 1631.920000 191.640000 ;
+ RECT 1643.630000 185.720000 1644.630000 186.200000 ;
+ RECT 1643.630000 191.160000 1644.630000 191.640000 ;
+ RECT 1630.820000 174.840000 1631.920000 175.320000 ;
+ RECT 1630.820000 180.280000 1631.920000 180.760000 ;
+ RECT 1643.630000 174.840000 1644.630000 175.320000 ;
+ RECT 1643.630000 180.280000 1644.630000 180.760000 ;
+ RECT 1643.630000 163.960000 1644.630000 164.440000 ;
+ RECT 1643.630000 158.520000 1644.630000 159.000000 ;
+ RECT 1643.630000 169.400000 1644.630000 169.880000 ;
+ RECT 1630.820000 169.400000 1631.920000 169.880000 ;
+ RECT 1630.820000 163.960000 1631.920000 164.440000 ;
+ RECT 1630.820000 158.520000 1631.920000 159.000000 ;
+ RECT 1630.820000 153.080000 1631.920000 153.560000 ;
+ RECT 1643.630000 153.080000 1644.630000 153.560000 ;
+ RECT 1585.820000 174.840000 1586.920000 175.320000 ;
+ RECT 1585.820000 180.280000 1586.920000 180.760000 ;
+ RECT 1585.820000 185.720000 1586.920000 186.200000 ;
+ RECT 1585.820000 191.160000 1586.920000 191.640000 ;
+ RECT 1585.820000 153.080000 1586.920000 153.560000 ;
+ RECT 1585.820000 158.520000 1586.920000 159.000000 ;
+ RECT 1585.820000 163.960000 1586.920000 164.440000 ;
+ RECT 1585.820000 169.400000 1586.920000 169.880000 ;
+ RECT 1630.820000 245.560000 1631.920000 246.040000 ;
+ RECT 1585.820000 245.560000 1586.920000 246.040000 ;
+ RECT 1643.630000 245.560000 1644.630000 246.040000 ;
+ RECT 1540.820000 321.720000 1541.920000 322.200000 ;
+ RECT 1540.820000 327.160000 1541.920000 327.640000 ;
+ RECT 1540.820000 332.600000 1541.920000 333.080000 ;
+ RECT 1540.820000 338.040000 1541.920000 338.520000 ;
+ RECT 1540.820000 343.480000 1541.920000 343.960000 ;
+ RECT 1495.820000 321.720000 1496.920000 322.200000 ;
+ RECT 1495.820000 327.160000 1496.920000 327.640000 ;
+ RECT 1495.820000 332.600000 1496.920000 333.080000 ;
+ RECT 1495.820000 338.040000 1496.920000 338.520000 ;
+ RECT 1495.820000 343.480000 1496.920000 343.960000 ;
+ RECT 1540.820000 299.960000 1541.920000 300.440000 ;
+ RECT 1540.820000 305.400000 1541.920000 305.880000 ;
+ RECT 1540.820000 310.840000 1541.920000 311.320000 ;
+ RECT 1540.820000 316.280000 1541.920000 316.760000 ;
+ RECT 1495.820000 299.960000 1496.920000 300.440000 ;
+ RECT 1495.820000 305.400000 1496.920000 305.880000 ;
+ RECT 1495.820000 310.840000 1496.920000 311.320000 ;
+ RECT 1495.820000 316.280000 1496.920000 316.760000 ;
+ RECT 1446.990000 343.480000 1447.990000 343.960000 ;
+ RECT 1450.655000 343.480000 1451.920000 343.960000 ;
+ RECT 1446.990000 338.040000 1447.990000 338.520000 ;
+ RECT 1450.655000 338.040000 1451.920000 338.520000 ;
+ RECT 1446.990000 327.160000 1447.990000 327.640000 ;
+ RECT 1450.655000 327.160000 1451.920000 327.640000 ;
+ RECT 1446.990000 332.600000 1447.990000 333.080000 ;
+ RECT 1450.655000 332.600000 1451.920000 333.080000 ;
+ RECT 1446.990000 321.720000 1447.990000 322.200000 ;
+ RECT 1450.655000 321.720000 1451.920000 322.200000 ;
+ RECT 1446.990000 316.280000 1447.990000 316.760000 ;
+ RECT 1450.655000 316.280000 1451.920000 316.760000 ;
+ RECT 1446.990000 310.840000 1447.990000 311.320000 ;
+ RECT 1450.655000 310.840000 1451.920000 311.320000 ;
+ RECT 1446.990000 305.400000 1447.990000 305.880000 ;
+ RECT 1450.655000 305.400000 1451.920000 305.880000 ;
+ RECT 1446.990000 299.960000 1447.990000 300.440000 ;
+ RECT 1450.655000 299.960000 1451.920000 300.440000 ;
+ RECT 1540.820000 272.760000 1541.920000 273.240000 ;
+ RECT 1540.820000 278.200000 1541.920000 278.680000 ;
+ RECT 1540.820000 283.640000 1541.920000 284.120000 ;
+ RECT 1540.820000 289.080000 1541.920000 289.560000 ;
+ RECT 1540.820000 294.520000 1541.920000 295.000000 ;
+ RECT 1495.820000 272.760000 1496.920000 273.240000 ;
+ RECT 1495.820000 278.200000 1496.920000 278.680000 ;
+ RECT 1495.820000 283.640000 1496.920000 284.120000 ;
+ RECT 1495.820000 289.080000 1496.920000 289.560000 ;
+ RECT 1495.820000 294.520000 1496.920000 295.000000 ;
+ RECT 1540.820000 251.000000 1541.920000 251.480000 ;
+ RECT 1540.820000 256.440000 1541.920000 256.920000 ;
+ RECT 1540.820000 261.880000 1541.920000 262.360000 ;
+ RECT 1540.820000 267.320000 1541.920000 267.800000 ;
+ RECT 1495.820000 251.000000 1496.920000 251.480000 ;
+ RECT 1495.820000 256.440000 1496.920000 256.920000 ;
+ RECT 1495.820000 261.880000 1496.920000 262.360000 ;
+ RECT 1495.820000 267.320000 1496.920000 267.800000 ;
+ RECT 1446.990000 294.520000 1447.990000 295.000000 ;
+ RECT 1450.655000 294.520000 1451.920000 295.000000 ;
+ RECT 1446.990000 283.640000 1447.990000 284.120000 ;
+ RECT 1450.655000 283.640000 1451.920000 284.120000 ;
+ RECT 1446.990000 289.080000 1447.990000 289.560000 ;
+ RECT 1450.655000 289.080000 1451.920000 289.560000 ;
+ RECT 1446.990000 278.200000 1447.990000 278.680000 ;
+ RECT 1450.655000 278.200000 1451.920000 278.680000 ;
+ RECT 1446.990000 272.760000 1447.990000 273.240000 ;
+ RECT 1450.655000 272.760000 1451.920000 273.240000 ;
+ RECT 1446.990000 267.320000 1447.990000 267.800000 ;
+ RECT 1450.655000 267.320000 1451.920000 267.800000 ;
+ RECT 1446.990000 261.880000 1447.990000 262.360000 ;
+ RECT 1450.655000 261.880000 1451.920000 262.360000 ;
+ RECT 1446.990000 256.440000 1447.990000 256.920000 ;
+ RECT 1450.655000 256.440000 1451.920000 256.920000 ;
+ RECT 1446.990000 251.000000 1447.990000 251.480000 ;
+ RECT 1450.655000 251.000000 1451.920000 251.480000 ;
+ RECT 1540.820000 223.800000 1541.920000 224.280000 ;
+ RECT 1540.820000 229.240000 1541.920000 229.720000 ;
+ RECT 1540.820000 234.680000 1541.920000 235.160000 ;
+ RECT 1540.820000 240.120000 1541.920000 240.600000 ;
+ RECT 1495.820000 223.800000 1496.920000 224.280000 ;
+ RECT 1495.820000 229.240000 1496.920000 229.720000 ;
+ RECT 1495.820000 234.680000 1496.920000 235.160000 ;
+ RECT 1495.820000 240.120000 1496.920000 240.600000 ;
+ RECT 1540.820000 196.600000 1541.920000 197.080000 ;
+ RECT 1540.820000 202.040000 1541.920000 202.520000 ;
+ RECT 1540.820000 207.480000 1541.920000 207.960000 ;
+ RECT 1540.820000 212.920000 1541.920000 213.400000 ;
+ RECT 1540.820000 218.360000 1541.920000 218.840000 ;
+ RECT 1495.820000 196.600000 1496.920000 197.080000 ;
+ RECT 1495.820000 202.040000 1496.920000 202.520000 ;
+ RECT 1495.820000 207.480000 1496.920000 207.960000 ;
+ RECT 1495.820000 212.920000 1496.920000 213.400000 ;
+ RECT 1495.820000 218.360000 1496.920000 218.840000 ;
+ RECT 1446.990000 240.120000 1447.990000 240.600000 ;
+ RECT 1450.655000 240.120000 1451.920000 240.600000 ;
+ RECT 1446.990000 234.680000 1447.990000 235.160000 ;
+ RECT 1450.655000 234.680000 1451.920000 235.160000 ;
+ RECT 1446.990000 229.240000 1447.990000 229.720000 ;
+ RECT 1450.655000 229.240000 1451.920000 229.720000 ;
+ RECT 1446.990000 223.800000 1447.990000 224.280000 ;
+ RECT 1450.655000 223.800000 1451.920000 224.280000 ;
+ RECT 1446.990000 218.360000 1447.990000 218.840000 ;
+ RECT 1450.655000 218.360000 1451.920000 218.840000 ;
+ RECT 1446.990000 212.920000 1447.990000 213.400000 ;
+ RECT 1450.655000 212.920000 1451.920000 213.400000 ;
+ RECT 1446.990000 202.040000 1447.990000 202.520000 ;
+ RECT 1450.655000 202.040000 1451.920000 202.520000 ;
+ RECT 1446.990000 207.480000 1447.990000 207.960000 ;
+ RECT 1450.655000 207.480000 1451.920000 207.960000 ;
+ RECT 1446.990000 196.600000 1447.990000 197.080000 ;
+ RECT 1450.655000 196.600000 1451.920000 197.080000 ;
+ RECT 1540.820000 174.840000 1541.920000 175.320000 ;
+ RECT 1540.820000 180.280000 1541.920000 180.760000 ;
+ RECT 1540.820000 185.720000 1541.920000 186.200000 ;
+ RECT 1540.820000 191.160000 1541.920000 191.640000 ;
+ RECT 1495.820000 174.840000 1496.920000 175.320000 ;
+ RECT 1495.820000 180.280000 1496.920000 180.760000 ;
+ RECT 1495.820000 185.720000 1496.920000 186.200000 ;
+ RECT 1495.820000 191.160000 1496.920000 191.640000 ;
+ RECT 1540.820000 153.080000 1541.920000 153.560000 ;
+ RECT 1540.820000 158.520000 1541.920000 159.000000 ;
+ RECT 1540.820000 163.960000 1541.920000 164.440000 ;
+ RECT 1540.820000 169.400000 1541.920000 169.880000 ;
+ RECT 1495.820000 153.080000 1496.920000 153.560000 ;
+ RECT 1495.820000 158.520000 1496.920000 159.000000 ;
+ RECT 1495.820000 163.960000 1496.920000 164.440000 ;
+ RECT 1495.820000 169.400000 1496.920000 169.880000 ;
+ RECT 1446.990000 191.160000 1447.990000 191.640000 ;
+ RECT 1450.655000 191.160000 1451.920000 191.640000 ;
+ RECT 1446.990000 185.720000 1447.990000 186.200000 ;
+ RECT 1450.655000 185.720000 1451.920000 186.200000 ;
+ RECT 1446.990000 180.280000 1447.990000 180.760000 ;
+ RECT 1450.655000 180.280000 1451.920000 180.760000 ;
+ RECT 1446.990000 174.840000 1447.990000 175.320000 ;
+ RECT 1450.655000 174.840000 1451.920000 175.320000 ;
+ RECT 1446.990000 169.400000 1447.990000 169.880000 ;
+ RECT 1450.655000 169.400000 1451.920000 169.880000 ;
+ RECT 1446.990000 158.520000 1447.990000 159.000000 ;
+ RECT 1450.655000 158.520000 1451.920000 159.000000 ;
+ RECT 1446.990000 163.960000 1447.990000 164.440000 ;
+ RECT 1450.655000 163.960000 1451.920000 164.440000 ;
+ RECT 1446.990000 153.080000 1447.990000 153.560000 ;
+ RECT 1450.655000 153.080000 1451.920000 153.560000 ;
+ RECT 1540.820000 245.560000 1541.920000 246.040000 ;
+ RECT 1495.820000 245.560000 1496.920000 246.040000 ;
+ RECT 1446.990000 245.560000 1447.990000 246.040000 ;
+ RECT 1450.655000 245.560000 1451.920000 246.040000 ;
+ RECT 1445.760000 543.090000 1645.860000 544.090000 ;
+ RECT 1445.760000 146.750000 1645.860000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 145.500000 1447.990000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 545.020000 1447.990000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 145.500000 1644.630000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 545.020000 1644.630000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 146.750000 1446.760000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 146.750000 1645.860000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 543.090000 1446.760000 544.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 543.090000 1645.860000 544.090000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'S_term_DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1450.655000 139.140000 1451.920000 139.620000 ;
+ RECT 1450.655000 133.700000 1451.920000 134.180000 ;
+ RECT 1450.655000 128.260000 1451.920000 128.740000 ;
+ RECT 1450.655000 122.820000 1451.920000 123.300000 ;
+ RECT 1446.990000 115.240000 1447.990000 145.500000 ;
+ RECT 1643.630000 115.240000 1644.630000 145.500000 ;
+ RECT 1450.820000 116.490000 1451.920000 143.740000 ;
+ RECT 1495.820000 116.490000 1496.920000 143.740000 ;
+ RECT 1540.820000 116.490000 1541.920000 143.740000 ;
+ RECT 1585.820000 116.490000 1586.920000 143.740000 ;
+ RECT 1630.820000 116.490000 1631.920000 143.740000 ;
+ LAYER met3 ;
+ RECT 1643.630000 139.140000 1644.630000 139.620000 ;
+ RECT 1643.630000 133.700000 1644.630000 134.180000 ;
+ RECT 1630.820000 139.140000 1631.920000 139.620000 ;
+ RECT 1630.820000 133.700000 1631.920000 134.180000 ;
+ RECT 1585.820000 133.700000 1586.920000 134.180000 ;
+ RECT 1585.820000 139.140000 1586.920000 139.620000 ;
+ RECT 1540.820000 133.700000 1541.920000 134.180000 ;
+ RECT 1495.820000 133.700000 1496.920000 134.180000 ;
+ RECT 1540.820000 139.140000 1541.920000 139.620000 ;
+ RECT 1495.820000 139.140000 1496.920000 139.620000 ;
+ RECT 1450.655000 139.140000 1451.920000 139.620000 ;
+ RECT 1446.990000 139.140000 1447.990000 139.620000 ;
+ RECT 1450.655000 133.700000 1451.920000 134.180000 ;
+ RECT 1446.990000 133.700000 1447.990000 134.180000 ;
+ RECT 1643.630000 128.260000 1644.630000 128.740000 ;
+ RECT 1643.630000 122.820000 1644.630000 123.300000 ;
+ RECT 1630.820000 128.260000 1631.920000 128.740000 ;
+ RECT 1630.820000 122.820000 1631.920000 123.300000 ;
+ RECT 1585.820000 122.820000 1586.920000 123.300000 ;
+ RECT 1585.820000 128.260000 1586.920000 128.740000 ;
+ RECT 1540.820000 122.820000 1541.920000 123.300000 ;
+ RECT 1495.820000 122.820000 1496.920000 123.300000 ;
+ RECT 1540.820000 128.260000 1541.920000 128.740000 ;
+ RECT 1495.820000 128.260000 1496.920000 128.740000 ;
+ RECT 1450.655000 128.260000 1451.920000 128.740000 ;
+ RECT 1446.990000 128.260000 1447.990000 128.740000 ;
+ RECT 1450.655000 122.820000 1451.920000 123.300000 ;
+ RECT 1446.990000 122.820000 1447.990000 123.300000 ;
+ RECT 1445.760000 142.740000 1645.860000 143.740000 ;
+ RECT 1445.760000 116.490000 1645.860000 117.490000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 115.240000 1447.990000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 144.500000 1447.990000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 115.240000 1644.630000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 144.500000 1644.630000 145.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 116.490000 1446.760000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 116.490000 1645.860000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 142.740000 1446.760000 143.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 142.740000 1645.860000 143.740000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1450.655000 3337.520000 1451.920000 3338.000000 ;
+ RECT 1450.655000 3342.960000 1451.920000 3343.440000 ;
+ RECT 1450.655000 3332.080000 1451.920000 3332.560000 ;
+ RECT 1450.655000 3326.640000 1451.920000 3327.120000 ;
+ RECT 1450.655000 3321.200000 1451.920000 3321.680000 ;
+ RECT 1450.655000 3315.760000 1451.920000 3316.240000 ;
+ RECT 1450.655000 3310.320000 1451.920000 3310.800000 ;
+ RECT 1450.655000 3304.880000 1451.920000 3305.360000 ;
+ RECT 1450.655000 3294.000000 1451.920000 3294.480000 ;
+ RECT 1450.655000 3288.560000 1451.920000 3289.040000 ;
+ RECT 1450.655000 3283.120000 1451.920000 3283.600000 ;
+ RECT 1450.655000 3277.680000 1451.920000 3278.160000 ;
+ RECT 1450.655000 3272.240000 1451.920000 3272.720000 ;
+ RECT 1450.655000 3266.800000 1451.920000 3267.280000 ;
+ RECT 1450.655000 3255.920000 1451.920000 3256.400000 ;
+ RECT 1450.655000 3261.360000 1451.920000 3261.840000 ;
+ RECT 1450.655000 3250.480000 1451.920000 3250.960000 ;
+ RECT 1450.655000 3299.440000 1451.920000 3299.920000 ;
+ RECT 1450.655000 3245.040000 1451.920000 3245.520000 ;
+ RECT 1450.655000 3239.600000 1451.920000 3240.080000 ;
+ RECT 1450.655000 3234.160000 1451.920000 3234.640000 ;
+ RECT 1450.655000 3228.720000 1451.920000 3229.200000 ;
+ RECT 1450.655000 3223.280000 1451.920000 3223.760000 ;
+ RECT 1450.655000 3212.400000 1451.920000 3212.880000 ;
+ RECT 1450.655000 3217.840000 1451.920000 3218.320000 ;
+ RECT 1450.655000 3206.960000 1451.920000 3207.440000 ;
+ RECT 1450.655000 3201.520000 1451.920000 3202.000000 ;
+ RECT 1450.655000 3196.080000 1451.920000 3196.560000 ;
+ RECT 1450.655000 3190.640000 1451.920000 3191.120000 ;
+ RECT 1450.655000 3185.200000 1451.920000 3185.680000 ;
+ RECT 1450.655000 3179.760000 1451.920000 3180.240000 ;
+ RECT 1450.655000 3168.880000 1451.920000 3169.360000 ;
+ RECT 1450.655000 3163.440000 1451.920000 3163.920000 ;
+ RECT 1450.655000 3158.000000 1451.920000 3158.480000 ;
+ RECT 1450.655000 3152.560000 1451.920000 3153.040000 ;
+ RECT 1450.655000 3174.320000 1451.920000 3174.800000 ;
+ RECT 1450.655000 3147.120000 1451.920000 3147.600000 ;
+ RECT 1450.655000 3141.680000 1451.920000 3142.160000 ;
+ RECT 1450.655000 3130.800000 1451.920000 3131.280000 ;
+ RECT 1450.655000 3136.240000 1451.920000 3136.720000 ;
+ RECT 1450.655000 3125.360000 1451.920000 3125.840000 ;
+ RECT 1450.655000 3119.920000 1451.920000 3120.400000 ;
+ RECT 1450.655000 3114.480000 1451.920000 3114.960000 ;
+ RECT 1450.655000 3109.040000 1451.920000 3109.520000 ;
+ RECT 1450.655000 3103.600000 1451.920000 3104.080000 ;
+ RECT 1450.655000 3098.160000 1451.920000 3098.640000 ;
+ RECT 1450.655000 3087.280000 1451.920000 3087.760000 ;
+ RECT 1450.655000 3092.720000 1451.920000 3093.200000 ;
+ RECT 1450.655000 3081.840000 1451.920000 3082.320000 ;
+ RECT 1450.655000 3076.400000 1451.920000 3076.880000 ;
+ RECT 1450.655000 3070.960000 1451.920000 3071.440000 ;
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+ LAYER met3 ;
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+ RECT 1630.820000 3092.720000 1631.920000 3093.200000 ;
+ RECT 1630.820000 3087.280000 1631.920000 3087.760000 ;
+ RECT 1630.820000 3076.400000 1631.920000 3076.880000 ;
+ RECT 1630.820000 3081.840000 1631.920000 3082.320000 ;
+ RECT 1643.630000 3076.400000 1644.630000 3076.880000 ;
+ RECT 1643.630000 3081.840000 1644.630000 3082.320000 ;
+ RECT 1643.630000 3065.520000 1644.630000 3066.000000 ;
+ RECT 1643.630000 3070.960000 1644.630000 3071.440000 ;
+ RECT 1630.820000 3070.960000 1631.920000 3071.440000 ;
+ RECT 1630.820000 3065.520000 1631.920000 3066.000000 ;
+ RECT 1630.820000 3054.640000 1631.920000 3055.120000 ;
+ RECT 1630.820000 3060.080000 1631.920000 3060.560000 ;
+ RECT 1643.630000 3054.640000 1644.630000 3055.120000 ;
+ RECT 1643.630000 3060.080000 1644.630000 3060.560000 ;
+ RECT 1585.820000 3076.400000 1586.920000 3076.880000 ;
+ RECT 1585.820000 3081.840000 1586.920000 3082.320000 ;
+ RECT 1585.820000 3087.280000 1586.920000 3087.760000 ;
+ RECT 1585.820000 3092.720000 1586.920000 3093.200000 ;
+ RECT 1585.820000 3098.160000 1586.920000 3098.640000 ;
+ RECT 1585.820000 3054.640000 1586.920000 3055.120000 ;
+ RECT 1585.820000 3060.080000 1586.920000 3060.560000 ;
+ RECT 1585.820000 3065.520000 1586.920000 3066.000000 ;
+ RECT 1585.820000 3070.960000 1586.920000 3071.440000 ;
+ RECT 1630.820000 3038.320000 1631.920000 3038.800000 ;
+ RECT 1630.820000 3043.760000 1631.920000 3044.240000 ;
+ RECT 1643.630000 3038.320000 1644.630000 3038.800000 ;
+ RECT 1643.630000 3043.760000 1644.630000 3044.240000 ;
+ RECT 1643.630000 3027.440000 1644.630000 3027.920000 ;
+ RECT 1643.630000 3032.880000 1644.630000 3033.360000 ;
+ RECT 1630.820000 3032.880000 1631.920000 3033.360000 ;
+ RECT 1630.820000 3027.440000 1631.920000 3027.920000 ;
+ RECT 1630.820000 3016.560000 1631.920000 3017.040000 ;
+ RECT 1630.820000 3022.000000 1631.920000 3022.480000 ;
+ RECT 1643.630000 3016.560000 1644.630000 3017.040000 ;
+ RECT 1643.630000 3022.000000 1644.630000 3022.480000 ;
+ RECT 1643.630000 3005.680000 1644.630000 3006.160000 ;
+ RECT 1643.630000 3000.240000 1644.630000 3000.720000 ;
+ RECT 1643.630000 3011.120000 1644.630000 3011.600000 ;
+ RECT 1630.820000 3011.120000 1631.920000 3011.600000 ;
+ RECT 1630.820000 3005.680000 1631.920000 3006.160000 ;
+ RECT 1630.820000 3000.240000 1631.920000 3000.720000 ;
+ RECT 1585.820000 3027.440000 1586.920000 3027.920000 ;
+ RECT 1585.820000 3032.880000 1586.920000 3033.360000 ;
+ RECT 1585.820000 3038.320000 1586.920000 3038.800000 ;
+ RECT 1585.820000 3043.760000 1586.920000 3044.240000 ;
+ RECT 1585.820000 3000.240000 1586.920000 3000.720000 ;
+ RECT 1585.820000 3005.680000 1586.920000 3006.160000 ;
+ RECT 1585.820000 3011.120000 1586.920000 3011.600000 ;
+ RECT 1585.820000 3016.560000 1586.920000 3017.040000 ;
+ RECT 1585.820000 3022.000000 1586.920000 3022.480000 ;
+ RECT 1630.820000 2989.360000 1631.920000 2989.840000 ;
+ RECT 1630.820000 2994.800000 1631.920000 2995.280000 ;
+ RECT 1643.630000 2989.360000 1644.630000 2989.840000 ;
+ RECT 1643.630000 2994.800000 1644.630000 2995.280000 ;
+ RECT 1630.820000 2978.480000 1631.920000 2978.960000 ;
+ RECT 1630.820000 2983.920000 1631.920000 2984.400000 ;
+ RECT 1643.630000 2978.480000 1644.630000 2978.960000 ;
+ RECT 1643.630000 2983.920000 1644.630000 2984.400000 ;
+ RECT 1643.630000 2967.600000 1644.630000 2968.080000 ;
+ RECT 1643.630000 2962.160000 1644.630000 2962.640000 ;
+ RECT 1643.630000 2973.040000 1644.630000 2973.520000 ;
+ RECT 1630.820000 2973.040000 1631.920000 2973.520000 ;
+ RECT 1630.820000 2967.600000 1631.920000 2968.080000 ;
+ RECT 1630.820000 2962.160000 1631.920000 2962.640000 ;
+ RECT 1630.820000 2956.720000 1631.920000 2957.200000 ;
+ RECT 1643.630000 2956.720000 1644.630000 2957.200000 ;
+ RECT 1585.820000 2978.480000 1586.920000 2978.960000 ;
+ RECT 1585.820000 2983.920000 1586.920000 2984.400000 ;
+ RECT 1585.820000 2989.360000 1586.920000 2989.840000 ;
+ RECT 1585.820000 2994.800000 1586.920000 2995.280000 ;
+ RECT 1585.820000 2956.720000 1586.920000 2957.200000 ;
+ RECT 1585.820000 2962.160000 1586.920000 2962.640000 ;
+ RECT 1585.820000 2967.600000 1586.920000 2968.080000 ;
+ RECT 1585.820000 2973.040000 1586.920000 2973.520000 ;
+ RECT 1630.820000 3049.200000 1631.920000 3049.680000 ;
+ RECT 1585.820000 3049.200000 1586.920000 3049.680000 ;
+ RECT 1643.630000 3049.200000 1644.630000 3049.680000 ;
+ RECT 1540.820000 3125.360000 1541.920000 3125.840000 ;
+ RECT 1540.820000 3130.800000 1541.920000 3131.280000 ;
+ RECT 1540.820000 3136.240000 1541.920000 3136.720000 ;
+ RECT 1540.820000 3141.680000 1541.920000 3142.160000 ;
+ RECT 1540.820000 3147.120000 1541.920000 3147.600000 ;
+ RECT 1495.820000 3125.360000 1496.920000 3125.840000 ;
+ RECT 1495.820000 3130.800000 1496.920000 3131.280000 ;
+ RECT 1495.820000 3136.240000 1496.920000 3136.720000 ;
+ RECT 1495.820000 3141.680000 1496.920000 3142.160000 ;
+ RECT 1495.820000 3147.120000 1496.920000 3147.600000 ;
+ RECT 1540.820000 3103.600000 1541.920000 3104.080000 ;
+ RECT 1540.820000 3109.040000 1541.920000 3109.520000 ;
+ RECT 1540.820000 3114.480000 1541.920000 3114.960000 ;
+ RECT 1540.820000 3119.920000 1541.920000 3120.400000 ;
+ RECT 1495.820000 3103.600000 1496.920000 3104.080000 ;
+ RECT 1495.820000 3109.040000 1496.920000 3109.520000 ;
+ RECT 1495.820000 3114.480000 1496.920000 3114.960000 ;
+ RECT 1495.820000 3119.920000 1496.920000 3120.400000 ;
+ RECT 1446.990000 3147.120000 1447.990000 3147.600000 ;
+ RECT 1450.655000 3147.120000 1451.920000 3147.600000 ;
+ RECT 1446.990000 3141.680000 1447.990000 3142.160000 ;
+ RECT 1450.655000 3141.680000 1451.920000 3142.160000 ;
+ RECT 1446.990000 3130.800000 1447.990000 3131.280000 ;
+ RECT 1450.655000 3130.800000 1451.920000 3131.280000 ;
+ RECT 1446.990000 3136.240000 1447.990000 3136.720000 ;
+ RECT 1450.655000 3136.240000 1451.920000 3136.720000 ;
+ RECT 1446.990000 3125.360000 1447.990000 3125.840000 ;
+ RECT 1450.655000 3125.360000 1451.920000 3125.840000 ;
+ RECT 1446.990000 3119.920000 1447.990000 3120.400000 ;
+ RECT 1450.655000 3119.920000 1451.920000 3120.400000 ;
+ RECT 1446.990000 3114.480000 1447.990000 3114.960000 ;
+ RECT 1450.655000 3114.480000 1451.920000 3114.960000 ;
+ RECT 1446.990000 3109.040000 1447.990000 3109.520000 ;
+ RECT 1450.655000 3109.040000 1451.920000 3109.520000 ;
+ RECT 1446.990000 3103.600000 1447.990000 3104.080000 ;
+ RECT 1450.655000 3103.600000 1451.920000 3104.080000 ;
+ RECT 1540.820000 3076.400000 1541.920000 3076.880000 ;
+ RECT 1540.820000 3081.840000 1541.920000 3082.320000 ;
+ RECT 1540.820000 3087.280000 1541.920000 3087.760000 ;
+ RECT 1540.820000 3092.720000 1541.920000 3093.200000 ;
+ RECT 1540.820000 3098.160000 1541.920000 3098.640000 ;
+ RECT 1495.820000 3076.400000 1496.920000 3076.880000 ;
+ RECT 1495.820000 3081.840000 1496.920000 3082.320000 ;
+ RECT 1495.820000 3087.280000 1496.920000 3087.760000 ;
+ RECT 1495.820000 3092.720000 1496.920000 3093.200000 ;
+ RECT 1495.820000 3098.160000 1496.920000 3098.640000 ;
+ RECT 1540.820000 3054.640000 1541.920000 3055.120000 ;
+ RECT 1540.820000 3060.080000 1541.920000 3060.560000 ;
+ RECT 1540.820000 3065.520000 1541.920000 3066.000000 ;
+ RECT 1540.820000 3070.960000 1541.920000 3071.440000 ;
+ RECT 1495.820000 3054.640000 1496.920000 3055.120000 ;
+ RECT 1495.820000 3060.080000 1496.920000 3060.560000 ;
+ RECT 1495.820000 3065.520000 1496.920000 3066.000000 ;
+ RECT 1495.820000 3070.960000 1496.920000 3071.440000 ;
+ RECT 1446.990000 3098.160000 1447.990000 3098.640000 ;
+ RECT 1450.655000 3098.160000 1451.920000 3098.640000 ;
+ RECT 1446.990000 3087.280000 1447.990000 3087.760000 ;
+ RECT 1450.655000 3087.280000 1451.920000 3087.760000 ;
+ RECT 1446.990000 3092.720000 1447.990000 3093.200000 ;
+ RECT 1450.655000 3092.720000 1451.920000 3093.200000 ;
+ RECT 1446.990000 3081.840000 1447.990000 3082.320000 ;
+ RECT 1450.655000 3081.840000 1451.920000 3082.320000 ;
+ RECT 1446.990000 3076.400000 1447.990000 3076.880000 ;
+ RECT 1450.655000 3076.400000 1451.920000 3076.880000 ;
+ RECT 1446.990000 3070.960000 1447.990000 3071.440000 ;
+ RECT 1450.655000 3070.960000 1451.920000 3071.440000 ;
+ RECT 1446.990000 3065.520000 1447.990000 3066.000000 ;
+ RECT 1450.655000 3065.520000 1451.920000 3066.000000 ;
+ RECT 1446.990000 3060.080000 1447.990000 3060.560000 ;
+ RECT 1450.655000 3060.080000 1451.920000 3060.560000 ;
+ RECT 1446.990000 3054.640000 1447.990000 3055.120000 ;
+ RECT 1450.655000 3054.640000 1451.920000 3055.120000 ;
+ RECT 1540.820000 3027.440000 1541.920000 3027.920000 ;
+ RECT 1540.820000 3032.880000 1541.920000 3033.360000 ;
+ RECT 1540.820000 3038.320000 1541.920000 3038.800000 ;
+ RECT 1540.820000 3043.760000 1541.920000 3044.240000 ;
+ RECT 1495.820000 3027.440000 1496.920000 3027.920000 ;
+ RECT 1495.820000 3032.880000 1496.920000 3033.360000 ;
+ RECT 1495.820000 3038.320000 1496.920000 3038.800000 ;
+ RECT 1495.820000 3043.760000 1496.920000 3044.240000 ;
+ RECT 1540.820000 3000.240000 1541.920000 3000.720000 ;
+ RECT 1540.820000 3005.680000 1541.920000 3006.160000 ;
+ RECT 1540.820000 3011.120000 1541.920000 3011.600000 ;
+ RECT 1540.820000 3016.560000 1541.920000 3017.040000 ;
+ RECT 1540.820000 3022.000000 1541.920000 3022.480000 ;
+ RECT 1495.820000 3000.240000 1496.920000 3000.720000 ;
+ RECT 1495.820000 3005.680000 1496.920000 3006.160000 ;
+ RECT 1495.820000 3011.120000 1496.920000 3011.600000 ;
+ RECT 1495.820000 3016.560000 1496.920000 3017.040000 ;
+ RECT 1495.820000 3022.000000 1496.920000 3022.480000 ;
+ RECT 1446.990000 3043.760000 1447.990000 3044.240000 ;
+ RECT 1450.655000 3043.760000 1451.920000 3044.240000 ;
+ RECT 1446.990000 3038.320000 1447.990000 3038.800000 ;
+ RECT 1450.655000 3038.320000 1451.920000 3038.800000 ;
+ RECT 1446.990000 3032.880000 1447.990000 3033.360000 ;
+ RECT 1450.655000 3032.880000 1451.920000 3033.360000 ;
+ RECT 1446.990000 3027.440000 1447.990000 3027.920000 ;
+ RECT 1450.655000 3027.440000 1451.920000 3027.920000 ;
+ RECT 1446.990000 3022.000000 1447.990000 3022.480000 ;
+ RECT 1450.655000 3022.000000 1451.920000 3022.480000 ;
+ RECT 1446.990000 3016.560000 1447.990000 3017.040000 ;
+ RECT 1450.655000 3016.560000 1451.920000 3017.040000 ;
+ RECT 1446.990000 3005.680000 1447.990000 3006.160000 ;
+ RECT 1450.655000 3005.680000 1451.920000 3006.160000 ;
+ RECT 1446.990000 3011.120000 1447.990000 3011.600000 ;
+ RECT 1450.655000 3011.120000 1451.920000 3011.600000 ;
+ RECT 1446.990000 3000.240000 1447.990000 3000.720000 ;
+ RECT 1450.655000 3000.240000 1451.920000 3000.720000 ;
+ RECT 1540.820000 2978.480000 1541.920000 2978.960000 ;
+ RECT 1540.820000 2983.920000 1541.920000 2984.400000 ;
+ RECT 1540.820000 2989.360000 1541.920000 2989.840000 ;
+ RECT 1540.820000 2994.800000 1541.920000 2995.280000 ;
+ RECT 1495.820000 2978.480000 1496.920000 2978.960000 ;
+ RECT 1495.820000 2983.920000 1496.920000 2984.400000 ;
+ RECT 1495.820000 2989.360000 1496.920000 2989.840000 ;
+ RECT 1495.820000 2994.800000 1496.920000 2995.280000 ;
+ RECT 1540.820000 2956.720000 1541.920000 2957.200000 ;
+ RECT 1540.820000 2962.160000 1541.920000 2962.640000 ;
+ RECT 1540.820000 2967.600000 1541.920000 2968.080000 ;
+ RECT 1540.820000 2973.040000 1541.920000 2973.520000 ;
+ RECT 1495.820000 2956.720000 1496.920000 2957.200000 ;
+ RECT 1495.820000 2962.160000 1496.920000 2962.640000 ;
+ RECT 1495.820000 2967.600000 1496.920000 2968.080000 ;
+ RECT 1495.820000 2973.040000 1496.920000 2973.520000 ;
+ RECT 1446.990000 2994.800000 1447.990000 2995.280000 ;
+ RECT 1450.655000 2994.800000 1451.920000 2995.280000 ;
+ RECT 1446.990000 2989.360000 1447.990000 2989.840000 ;
+ RECT 1450.655000 2989.360000 1451.920000 2989.840000 ;
+ RECT 1446.990000 2983.920000 1447.990000 2984.400000 ;
+ RECT 1450.655000 2983.920000 1451.920000 2984.400000 ;
+ RECT 1446.990000 2978.480000 1447.990000 2978.960000 ;
+ RECT 1450.655000 2978.480000 1451.920000 2978.960000 ;
+ RECT 1446.990000 2973.040000 1447.990000 2973.520000 ;
+ RECT 1450.655000 2973.040000 1451.920000 2973.520000 ;
+ RECT 1446.990000 2962.160000 1447.990000 2962.640000 ;
+ RECT 1450.655000 2962.160000 1451.920000 2962.640000 ;
+ RECT 1446.990000 2967.600000 1447.990000 2968.080000 ;
+ RECT 1450.655000 2967.600000 1451.920000 2968.080000 ;
+ RECT 1446.990000 2956.720000 1447.990000 2957.200000 ;
+ RECT 1450.655000 2956.720000 1451.920000 2957.200000 ;
+ RECT 1540.820000 3049.200000 1541.920000 3049.680000 ;
+ RECT 1495.820000 3049.200000 1496.920000 3049.680000 ;
+ RECT 1446.990000 3049.200000 1447.990000 3049.680000 ;
+ RECT 1450.655000 3049.200000 1451.920000 3049.680000 ;
+ RECT 1445.760000 3346.730000 1645.860000 3347.730000 ;
+ RECT 1445.760000 2950.390000 1645.860000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 2949.140000 1447.990000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 3348.660000 1447.990000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 2949.140000 1644.630000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 3348.660000 1644.630000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2950.390000 1446.760000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2950.390000 1645.860000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 3346.730000 1446.760000 3347.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 3346.730000 1645.860000 3347.730000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1450.655000 2937.000000 1451.920000 2937.480000 ;
+ RECT 1450.655000 2942.440000 1451.920000 2942.920000 ;
+ RECT 1450.655000 2931.560000 1451.920000 2932.040000 ;
+ RECT 1450.655000 2926.120000 1451.920000 2926.600000 ;
+ RECT 1450.655000 2920.680000 1451.920000 2921.160000 ;
+ RECT 1450.655000 2915.240000 1451.920000 2915.720000 ;
+ RECT 1450.655000 2909.800000 1451.920000 2910.280000 ;
+ RECT 1450.655000 2904.360000 1451.920000 2904.840000 ;
+ RECT 1450.655000 2893.480000 1451.920000 2893.960000 ;
+ RECT 1450.655000 2888.040000 1451.920000 2888.520000 ;
+ RECT 1450.655000 2882.600000 1451.920000 2883.080000 ;
+ RECT 1450.655000 2877.160000 1451.920000 2877.640000 ;
+ RECT 1450.655000 2871.720000 1451.920000 2872.200000 ;
+ RECT 1450.655000 2866.280000 1451.920000 2866.760000 ;
+ RECT 1450.655000 2855.400000 1451.920000 2855.880000 ;
+ RECT 1450.655000 2860.840000 1451.920000 2861.320000 ;
+ RECT 1450.655000 2849.960000 1451.920000 2850.440000 ;
+ RECT 1450.655000 2898.920000 1451.920000 2899.400000 ;
+ RECT 1450.655000 2844.520000 1451.920000 2845.000000 ;
+ RECT 1450.655000 2839.080000 1451.920000 2839.560000 ;
+ RECT 1450.655000 2833.640000 1451.920000 2834.120000 ;
+ RECT 1450.655000 2828.200000 1451.920000 2828.680000 ;
+ RECT 1450.655000 2822.760000 1451.920000 2823.240000 ;
+ RECT 1450.655000 2811.880000 1451.920000 2812.360000 ;
+ RECT 1450.655000 2817.320000 1451.920000 2817.800000 ;
+ RECT 1450.655000 2806.440000 1451.920000 2806.920000 ;
+ RECT 1450.655000 2801.000000 1451.920000 2801.480000 ;
+ RECT 1450.655000 2795.560000 1451.920000 2796.040000 ;
+ RECT 1450.655000 2790.120000 1451.920000 2790.600000 ;
+ RECT 1450.655000 2784.680000 1451.920000 2785.160000 ;
+ RECT 1450.655000 2779.240000 1451.920000 2779.720000 ;
+ RECT 1450.655000 2768.360000 1451.920000 2768.840000 ;
+ RECT 1450.655000 2762.920000 1451.920000 2763.400000 ;
+ RECT 1450.655000 2757.480000 1451.920000 2757.960000 ;
+ RECT 1450.655000 2752.040000 1451.920000 2752.520000 ;
+ RECT 1450.655000 2773.800000 1451.920000 2774.280000 ;
+ RECT 1450.655000 2746.600000 1451.920000 2747.080000 ;
+ RECT 1450.655000 2741.160000 1451.920000 2741.640000 ;
+ RECT 1450.655000 2730.280000 1451.920000 2730.760000 ;
+ RECT 1450.655000 2735.720000 1451.920000 2736.200000 ;
+ RECT 1450.655000 2724.840000 1451.920000 2725.320000 ;
+ RECT 1450.655000 2719.400000 1451.920000 2719.880000 ;
+ RECT 1450.655000 2713.960000 1451.920000 2714.440000 ;
+ RECT 1450.655000 2708.520000 1451.920000 2709.000000 ;
+ RECT 1450.655000 2703.080000 1451.920000 2703.560000 ;
+ RECT 1450.655000 2697.640000 1451.920000 2698.120000 ;
+ RECT 1450.655000 2686.760000 1451.920000 2687.240000 ;
+ RECT 1450.655000 2692.200000 1451.920000 2692.680000 ;
+ RECT 1450.655000 2681.320000 1451.920000 2681.800000 ;
+ RECT 1450.655000 2675.880000 1451.920000 2676.360000 ;
+ RECT 1450.655000 2670.440000 1451.920000 2670.920000 ;
+ RECT 1450.655000 2665.000000 1451.920000 2665.480000 ;
+ RECT 1450.655000 2659.560000 1451.920000 2660.040000 ;
+ RECT 1450.655000 2654.120000 1451.920000 2654.600000 ;
+ RECT 1450.655000 2643.240000 1451.920000 2643.720000 ;
+ RECT 1450.655000 2637.800000 1451.920000 2638.280000 ;
+ RECT 1450.655000 2632.360000 1451.920000 2632.840000 ;
+ RECT 1450.655000 2626.920000 1451.920000 2627.400000 ;
+ RECT 1450.655000 2621.480000 1451.920000 2621.960000 ;
+ RECT 1450.655000 2616.040000 1451.920000 2616.520000 ;
+ RECT 1450.655000 2605.160000 1451.920000 2605.640000 ;
+ RECT 1450.655000 2610.600000 1451.920000 2611.080000 ;
+ RECT 1450.655000 2599.720000 1451.920000 2600.200000 ;
+ RECT 1450.655000 2594.280000 1451.920000 2594.760000 ;
+ RECT 1450.655000 2588.840000 1451.920000 2589.320000 ;
+ RECT 1450.655000 2583.400000 1451.920000 2583.880000 ;
+ RECT 1450.655000 2577.960000 1451.920000 2578.440000 ;
+ RECT 1450.655000 2572.520000 1451.920000 2573.000000 ;
+ RECT 1450.655000 2561.640000 1451.920000 2562.120000 ;
+ RECT 1450.655000 2567.080000 1451.920000 2567.560000 ;
+ RECT 1450.655000 2556.200000 1451.920000 2556.680000 ;
+ RECT 1450.655000 2648.680000 1451.920000 2649.160000 ;
+ RECT 1446.990000 2548.620000 1447.990000 2949.140000 ;
+ RECT 1643.630000 2548.620000 1644.630000 2949.140000 ;
+ RECT 1450.820000 2549.870000 1451.920000 2947.210000 ;
+ RECT 1495.820000 2549.870000 1496.920000 2947.210000 ;
+ RECT 1540.820000 2549.870000 1541.920000 2947.210000 ;
+ RECT 1585.820000 2549.870000 1586.920000 2947.210000 ;
+ RECT 1630.820000 2549.870000 1631.920000 2947.210000 ;
+ LAYER met3 ;
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+ RECT 1643.630000 2937.000000 1644.630000 2937.480000 ;
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+ RECT 1630.820000 2888.040000 1631.920000 2888.520000 ;
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+ RECT 1643.630000 2643.240000 1644.630000 2643.720000 ;
+ RECT 1643.630000 2626.920000 1644.630000 2627.400000 ;
+ RECT 1643.630000 2632.360000 1644.630000 2632.840000 ;
+ RECT 1630.820000 2632.360000 1631.920000 2632.840000 ;
+ RECT 1630.820000 2626.920000 1631.920000 2627.400000 ;
+ RECT 1630.820000 2616.040000 1631.920000 2616.520000 ;
+ RECT 1630.820000 2621.480000 1631.920000 2621.960000 ;
+ RECT 1643.630000 2616.040000 1644.630000 2616.520000 ;
+ RECT 1643.630000 2621.480000 1644.630000 2621.960000 ;
+ RECT 1643.630000 2605.160000 1644.630000 2605.640000 ;
+ RECT 1643.630000 2599.720000 1644.630000 2600.200000 ;
+ RECT 1643.630000 2610.600000 1644.630000 2611.080000 ;
+ RECT 1630.820000 2610.600000 1631.920000 2611.080000 ;
+ RECT 1630.820000 2605.160000 1631.920000 2605.640000 ;
+ RECT 1630.820000 2599.720000 1631.920000 2600.200000 ;
+ RECT 1585.820000 2626.920000 1586.920000 2627.400000 ;
+ RECT 1585.820000 2632.360000 1586.920000 2632.840000 ;
+ RECT 1585.820000 2637.800000 1586.920000 2638.280000 ;
+ RECT 1585.820000 2643.240000 1586.920000 2643.720000 ;
+ RECT 1585.820000 2599.720000 1586.920000 2600.200000 ;
+ RECT 1585.820000 2605.160000 1586.920000 2605.640000 ;
+ RECT 1585.820000 2610.600000 1586.920000 2611.080000 ;
+ RECT 1585.820000 2616.040000 1586.920000 2616.520000 ;
+ RECT 1585.820000 2621.480000 1586.920000 2621.960000 ;
+ RECT 1630.820000 2588.840000 1631.920000 2589.320000 ;
+ RECT 1630.820000 2594.280000 1631.920000 2594.760000 ;
+ RECT 1643.630000 2588.840000 1644.630000 2589.320000 ;
+ RECT 1643.630000 2594.280000 1644.630000 2594.760000 ;
+ RECT 1630.820000 2577.960000 1631.920000 2578.440000 ;
+ RECT 1630.820000 2583.400000 1631.920000 2583.880000 ;
+ RECT 1643.630000 2577.960000 1644.630000 2578.440000 ;
+ RECT 1643.630000 2583.400000 1644.630000 2583.880000 ;
+ RECT 1643.630000 2567.080000 1644.630000 2567.560000 ;
+ RECT 1643.630000 2561.640000 1644.630000 2562.120000 ;
+ RECT 1643.630000 2572.520000 1644.630000 2573.000000 ;
+ RECT 1630.820000 2572.520000 1631.920000 2573.000000 ;
+ RECT 1630.820000 2567.080000 1631.920000 2567.560000 ;
+ RECT 1630.820000 2561.640000 1631.920000 2562.120000 ;
+ RECT 1630.820000 2556.200000 1631.920000 2556.680000 ;
+ RECT 1643.630000 2556.200000 1644.630000 2556.680000 ;
+ RECT 1585.820000 2577.960000 1586.920000 2578.440000 ;
+ RECT 1585.820000 2583.400000 1586.920000 2583.880000 ;
+ RECT 1585.820000 2588.840000 1586.920000 2589.320000 ;
+ RECT 1585.820000 2594.280000 1586.920000 2594.760000 ;
+ RECT 1585.820000 2556.200000 1586.920000 2556.680000 ;
+ RECT 1585.820000 2561.640000 1586.920000 2562.120000 ;
+ RECT 1585.820000 2567.080000 1586.920000 2567.560000 ;
+ RECT 1585.820000 2572.520000 1586.920000 2573.000000 ;
+ RECT 1630.820000 2648.680000 1631.920000 2649.160000 ;
+ RECT 1585.820000 2648.680000 1586.920000 2649.160000 ;
+ RECT 1643.630000 2648.680000 1644.630000 2649.160000 ;
+ RECT 1540.820000 2724.840000 1541.920000 2725.320000 ;
+ RECT 1540.820000 2730.280000 1541.920000 2730.760000 ;
+ RECT 1540.820000 2735.720000 1541.920000 2736.200000 ;
+ RECT 1540.820000 2741.160000 1541.920000 2741.640000 ;
+ RECT 1540.820000 2746.600000 1541.920000 2747.080000 ;
+ RECT 1495.820000 2724.840000 1496.920000 2725.320000 ;
+ RECT 1495.820000 2730.280000 1496.920000 2730.760000 ;
+ RECT 1495.820000 2735.720000 1496.920000 2736.200000 ;
+ RECT 1495.820000 2741.160000 1496.920000 2741.640000 ;
+ RECT 1495.820000 2746.600000 1496.920000 2747.080000 ;
+ RECT 1540.820000 2703.080000 1541.920000 2703.560000 ;
+ RECT 1540.820000 2708.520000 1541.920000 2709.000000 ;
+ RECT 1540.820000 2713.960000 1541.920000 2714.440000 ;
+ RECT 1540.820000 2719.400000 1541.920000 2719.880000 ;
+ RECT 1495.820000 2703.080000 1496.920000 2703.560000 ;
+ RECT 1495.820000 2708.520000 1496.920000 2709.000000 ;
+ RECT 1495.820000 2713.960000 1496.920000 2714.440000 ;
+ RECT 1495.820000 2719.400000 1496.920000 2719.880000 ;
+ RECT 1446.990000 2746.600000 1447.990000 2747.080000 ;
+ RECT 1450.655000 2746.600000 1451.920000 2747.080000 ;
+ RECT 1446.990000 2741.160000 1447.990000 2741.640000 ;
+ RECT 1450.655000 2741.160000 1451.920000 2741.640000 ;
+ RECT 1446.990000 2730.280000 1447.990000 2730.760000 ;
+ RECT 1450.655000 2730.280000 1451.920000 2730.760000 ;
+ RECT 1446.990000 2735.720000 1447.990000 2736.200000 ;
+ RECT 1450.655000 2735.720000 1451.920000 2736.200000 ;
+ RECT 1446.990000 2724.840000 1447.990000 2725.320000 ;
+ RECT 1450.655000 2724.840000 1451.920000 2725.320000 ;
+ RECT 1446.990000 2719.400000 1447.990000 2719.880000 ;
+ RECT 1450.655000 2719.400000 1451.920000 2719.880000 ;
+ RECT 1446.990000 2713.960000 1447.990000 2714.440000 ;
+ RECT 1450.655000 2713.960000 1451.920000 2714.440000 ;
+ RECT 1446.990000 2708.520000 1447.990000 2709.000000 ;
+ RECT 1450.655000 2708.520000 1451.920000 2709.000000 ;
+ RECT 1446.990000 2703.080000 1447.990000 2703.560000 ;
+ RECT 1450.655000 2703.080000 1451.920000 2703.560000 ;
+ RECT 1540.820000 2675.880000 1541.920000 2676.360000 ;
+ RECT 1540.820000 2681.320000 1541.920000 2681.800000 ;
+ RECT 1540.820000 2686.760000 1541.920000 2687.240000 ;
+ RECT 1540.820000 2692.200000 1541.920000 2692.680000 ;
+ RECT 1540.820000 2697.640000 1541.920000 2698.120000 ;
+ RECT 1495.820000 2675.880000 1496.920000 2676.360000 ;
+ RECT 1495.820000 2681.320000 1496.920000 2681.800000 ;
+ RECT 1495.820000 2686.760000 1496.920000 2687.240000 ;
+ RECT 1495.820000 2692.200000 1496.920000 2692.680000 ;
+ RECT 1495.820000 2697.640000 1496.920000 2698.120000 ;
+ RECT 1540.820000 2654.120000 1541.920000 2654.600000 ;
+ RECT 1540.820000 2659.560000 1541.920000 2660.040000 ;
+ RECT 1540.820000 2665.000000 1541.920000 2665.480000 ;
+ RECT 1540.820000 2670.440000 1541.920000 2670.920000 ;
+ RECT 1495.820000 2654.120000 1496.920000 2654.600000 ;
+ RECT 1495.820000 2659.560000 1496.920000 2660.040000 ;
+ RECT 1495.820000 2665.000000 1496.920000 2665.480000 ;
+ RECT 1495.820000 2670.440000 1496.920000 2670.920000 ;
+ RECT 1446.990000 2697.640000 1447.990000 2698.120000 ;
+ RECT 1450.655000 2697.640000 1451.920000 2698.120000 ;
+ RECT 1446.990000 2686.760000 1447.990000 2687.240000 ;
+ RECT 1450.655000 2686.760000 1451.920000 2687.240000 ;
+ RECT 1446.990000 2692.200000 1447.990000 2692.680000 ;
+ RECT 1450.655000 2692.200000 1451.920000 2692.680000 ;
+ RECT 1446.990000 2681.320000 1447.990000 2681.800000 ;
+ RECT 1450.655000 2681.320000 1451.920000 2681.800000 ;
+ RECT 1446.990000 2675.880000 1447.990000 2676.360000 ;
+ RECT 1450.655000 2675.880000 1451.920000 2676.360000 ;
+ RECT 1446.990000 2670.440000 1447.990000 2670.920000 ;
+ RECT 1450.655000 2670.440000 1451.920000 2670.920000 ;
+ RECT 1446.990000 2665.000000 1447.990000 2665.480000 ;
+ RECT 1450.655000 2665.000000 1451.920000 2665.480000 ;
+ RECT 1446.990000 2659.560000 1447.990000 2660.040000 ;
+ RECT 1450.655000 2659.560000 1451.920000 2660.040000 ;
+ RECT 1446.990000 2654.120000 1447.990000 2654.600000 ;
+ RECT 1450.655000 2654.120000 1451.920000 2654.600000 ;
+ RECT 1540.820000 2626.920000 1541.920000 2627.400000 ;
+ RECT 1540.820000 2632.360000 1541.920000 2632.840000 ;
+ RECT 1540.820000 2637.800000 1541.920000 2638.280000 ;
+ RECT 1540.820000 2643.240000 1541.920000 2643.720000 ;
+ RECT 1495.820000 2626.920000 1496.920000 2627.400000 ;
+ RECT 1495.820000 2632.360000 1496.920000 2632.840000 ;
+ RECT 1495.820000 2637.800000 1496.920000 2638.280000 ;
+ RECT 1495.820000 2643.240000 1496.920000 2643.720000 ;
+ RECT 1540.820000 2599.720000 1541.920000 2600.200000 ;
+ RECT 1540.820000 2605.160000 1541.920000 2605.640000 ;
+ RECT 1540.820000 2610.600000 1541.920000 2611.080000 ;
+ RECT 1540.820000 2616.040000 1541.920000 2616.520000 ;
+ RECT 1540.820000 2621.480000 1541.920000 2621.960000 ;
+ RECT 1495.820000 2599.720000 1496.920000 2600.200000 ;
+ RECT 1495.820000 2605.160000 1496.920000 2605.640000 ;
+ RECT 1495.820000 2610.600000 1496.920000 2611.080000 ;
+ RECT 1495.820000 2616.040000 1496.920000 2616.520000 ;
+ RECT 1495.820000 2621.480000 1496.920000 2621.960000 ;
+ RECT 1446.990000 2643.240000 1447.990000 2643.720000 ;
+ RECT 1450.655000 2643.240000 1451.920000 2643.720000 ;
+ RECT 1446.990000 2637.800000 1447.990000 2638.280000 ;
+ RECT 1450.655000 2637.800000 1451.920000 2638.280000 ;
+ RECT 1446.990000 2632.360000 1447.990000 2632.840000 ;
+ RECT 1450.655000 2632.360000 1451.920000 2632.840000 ;
+ RECT 1446.990000 2626.920000 1447.990000 2627.400000 ;
+ RECT 1450.655000 2626.920000 1451.920000 2627.400000 ;
+ RECT 1446.990000 2621.480000 1447.990000 2621.960000 ;
+ RECT 1450.655000 2621.480000 1451.920000 2621.960000 ;
+ RECT 1446.990000 2616.040000 1447.990000 2616.520000 ;
+ RECT 1450.655000 2616.040000 1451.920000 2616.520000 ;
+ RECT 1446.990000 2605.160000 1447.990000 2605.640000 ;
+ RECT 1450.655000 2605.160000 1451.920000 2605.640000 ;
+ RECT 1446.990000 2610.600000 1447.990000 2611.080000 ;
+ RECT 1450.655000 2610.600000 1451.920000 2611.080000 ;
+ RECT 1446.990000 2599.720000 1447.990000 2600.200000 ;
+ RECT 1450.655000 2599.720000 1451.920000 2600.200000 ;
+ RECT 1540.820000 2577.960000 1541.920000 2578.440000 ;
+ RECT 1540.820000 2583.400000 1541.920000 2583.880000 ;
+ RECT 1540.820000 2588.840000 1541.920000 2589.320000 ;
+ RECT 1540.820000 2594.280000 1541.920000 2594.760000 ;
+ RECT 1495.820000 2577.960000 1496.920000 2578.440000 ;
+ RECT 1495.820000 2583.400000 1496.920000 2583.880000 ;
+ RECT 1495.820000 2588.840000 1496.920000 2589.320000 ;
+ RECT 1495.820000 2594.280000 1496.920000 2594.760000 ;
+ RECT 1540.820000 2556.200000 1541.920000 2556.680000 ;
+ RECT 1540.820000 2561.640000 1541.920000 2562.120000 ;
+ RECT 1540.820000 2567.080000 1541.920000 2567.560000 ;
+ RECT 1540.820000 2572.520000 1541.920000 2573.000000 ;
+ RECT 1495.820000 2556.200000 1496.920000 2556.680000 ;
+ RECT 1495.820000 2561.640000 1496.920000 2562.120000 ;
+ RECT 1495.820000 2567.080000 1496.920000 2567.560000 ;
+ RECT 1495.820000 2572.520000 1496.920000 2573.000000 ;
+ RECT 1446.990000 2594.280000 1447.990000 2594.760000 ;
+ RECT 1450.655000 2594.280000 1451.920000 2594.760000 ;
+ RECT 1446.990000 2588.840000 1447.990000 2589.320000 ;
+ RECT 1450.655000 2588.840000 1451.920000 2589.320000 ;
+ RECT 1446.990000 2583.400000 1447.990000 2583.880000 ;
+ RECT 1450.655000 2583.400000 1451.920000 2583.880000 ;
+ RECT 1446.990000 2577.960000 1447.990000 2578.440000 ;
+ RECT 1450.655000 2577.960000 1451.920000 2578.440000 ;
+ RECT 1446.990000 2572.520000 1447.990000 2573.000000 ;
+ RECT 1450.655000 2572.520000 1451.920000 2573.000000 ;
+ RECT 1446.990000 2561.640000 1447.990000 2562.120000 ;
+ RECT 1450.655000 2561.640000 1451.920000 2562.120000 ;
+ RECT 1446.990000 2567.080000 1447.990000 2567.560000 ;
+ RECT 1450.655000 2567.080000 1451.920000 2567.560000 ;
+ RECT 1446.990000 2556.200000 1447.990000 2556.680000 ;
+ RECT 1450.655000 2556.200000 1451.920000 2556.680000 ;
+ RECT 1540.820000 2648.680000 1541.920000 2649.160000 ;
+ RECT 1495.820000 2648.680000 1496.920000 2649.160000 ;
+ RECT 1446.990000 2648.680000 1447.990000 2649.160000 ;
+ RECT 1450.655000 2648.680000 1451.920000 2649.160000 ;
+ RECT 1445.760000 2946.210000 1645.860000 2947.210000 ;
+ RECT 1445.760000 2549.870000 1645.860000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 2548.620000 1447.990000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 2948.140000 1447.990000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 2548.620000 1644.630000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 2948.140000 1644.630000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2549.870000 1446.760000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2549.870000 1645.860000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2946.210000 1446.760000 2947.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2946.210000 1645.860000 2947.210000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1450.655000 2536.480000 1451.920000 2536.960000 ;
+ RECT 1450.655000 2541.920000 1451.920000 2542.400000 ;
+ RECT 1450.655000 2531.040000 1451.920000 2531.520000 ;
+ RECT 1450.655000 2525.600000 1451.920000 2526.080000 ;
+ RECT 1450.655000 2520.160000 1451.920000 2520.640000 ;
+ RECT 1450.655000 2514.720000 1451.920000 2515.200000 ;
+ RECT 1450.655000 2509.280000 1451.920000 2509.760000 ;
+ RECT 1450.655000 2503.840000 1451.920000 2504.320000 ;
+ RECT 1450.655000 2492.960000 1451.920000 2493.440000 ;
+ RECT 1450.655000 2487.520000 1451.920000 2488.000000 ;
+ RECT 1450.655000 2482.080000 1451.920000 2482.560000 ;
+ RECT 1450.655000 2476.640000 1451.920000 2477.120000 ;
+ RECT 1450.655000 2471.200000 1451.920000 2471.680000 ;
+ RECT 1450.655000 2465.760000 1451.920000 2466.240000 ;
+ RECT 1450.655000 2454.880000 1451.920000 2455.360000 ;
+ RECT 1450.655000 2460.320000 1451.920000 2460.800000 ;
+ RECT 1450.655000 2449.440000 1451.920000 2449.920000 ;
+ RECT 1450.655000 2498.400000 1451.920000 2498.880000 ;
+ RECT 1450.655000 2444.000000 1451.920000 2444.480000 ;
+ RECT 1450.655000 2438.560000 1451.920000 2439.040000 ;
+ RECT 1450.655000 2433.120000 1451.920000 2433.600000 ;
+ RECT 1450.655000 2427.680000 1451.920000 2428.160000 ;
+ RECT 1450.655000 2422.240000 1451.920000 2422.720000 ;
+ RECT 1450.655000 2411.360000 1451.920000 2411.840000 ;
+ RECT 1450.655000 2416.800000 1451.920000 2417.280000 ;
+ RECT 1450.655000 2405.920000 1451.920000 2406.400000 ;
+ RECT 1450.655000 2400.480000 1451.920000 2400.960000 ;
+ RECT 1450.655000 2395.040000 1451.920000 2395.520000 ;
+ RECT 1450.655000 2389.600000 1451.920000 2390.080000 ;
+ RECT 1450.655000 2384.160000 1451.920000 2384.640000 ;
+ RECT 1450.655000 2378.720000 1451.920000 2379.200000 ;
+ RECT 1450.655000 2367.840000 1451.920000 2368.320000 ;
+ RECT 1450.655000 2362.400000 1451.920000 2362.880000 ;
+ RECT 1450.655000 2356.960000 1451.920000 2357.440000 ;
+ RECT 1450.655000 2351.520000 1451.920000 2352.000000 ;
+ RECT 1450.655000 2373.280000 1451.920000 2373.760000 ;
+ RECT 1450.655000 2346.080000 1451.920000 2346.560000 ;
+ RECT 1450.655000 2340.640000 1451.920000 2341.120000 ;
+ RECT 1450.655000 2329.760000 1451.920000 2330.240000 ;
+ RECT 1450.655000 2335.200000 1451.920000 2335.680000 ;
+ RECT 1450.655000 2324.320000 1451.920000 2324.800000 ;
+ RECT 1450.655000 2318.880000 1451.920000 2319.360000 ;
+ RECT 1450.655000 2313.440000 1451.920000 2313.920000 ;
+ RECT 1450.655000 2308.000000 1451.920000 2308.480000 ;
+ RECT 1450.655000 2302.560000 1451.920000 2303.040000 ;
+ RECT 1450.655000 2297.120000 1451.920000 2297.600000 ;
+ RECT 1450.655000 2286.240000 1451.920000 2286.720000 ;
+ RECT 1450.655000 2291.680000 1451.920000 2292.160000 ;
+ RECT 1450.655000 2280.800000 1451.920000 2281.280000 ;
+ RECT 1450.655000 2275.360000 1451.920000 2275.840000 ;
+ RECT 1450.655000 2269.920000 1451.920000 2270.400000 ;
+ RECT 1450.655000 2264.480000 1451.920000 2264.960000 ;
+ RECT 1450.655000 2259.040000 1451.920000 2259.520000 ;
+ RECT 1450.655000 2253.600000 1451.920000 2254.080000 ;
+ RECT 1450.655000 2242.720000 1451.920000 2243.200000 ;
+ RECT 1450.655000 2237.280000 1451.920000 2237.760000 ;
+ RECT 1450.655000 2231.840000 1451.920000 2232.320000 ;
+ RECT 1450.655000 2226.400000 1451.920000 2226.880000 ;
+ RECT 1450.655000 2220.960000 1451.920000 2221.440000 ;
+ RECT 1450.655000 2215.520000 1451.920000 2216.000000 ;
+ RECT 1450.655000 2204.640000 1451.920000 2205.120000 ;
+ RECT 1450.655000 2210.080000 1451.920000 2210.560000 ;
+ RECT 1450.655000 2199.200000 1451.920000 2199.680000 ;
+ RECT 1450.655000 2193.760000 1451.920000 2194.240000 ;
+ RECT 1450.655000 2188.320000 1451.920000 2188.800000 ;
+ RECT 1450.655000 2182.880000 1451.920000 2183.360000 ;
+ RECT 1450.655000 2177.440000 1451.920000 2177.920000 ;
+ RECT 1450.655000 2172.000000 1451.920000 2172.480000 ;
+ RECT 1450.655000 2161.120000 1451.920000 2161.600000 ;
+ RECT 1450.655000 2166.560000 1451.920000 2167.040000 ;
+ RECT 1450.655000 2155.680000 1451.920000 2156.160000 ;
+ RECT 1450.655000 2248.160000 1451.920000 2248.640000 ;
+ RECT 1446.990000 2148.100000 1447.990000 2548.620000 ;
+ RECT 1643.630000 2148.100000 1644.630000 2548.620000 ;
+ RECT 1450.820000 2149.350000 1451.920000 2546.690000 ;
+ RECT 1495.820000 2149.350000 1496.920000 2546.690000 ;
+ RECT 1540.820000 2149.350000 1541.920000 2546.690000 ;
+ RECT 1585.820000 2149.350000 1586.920000 2546.690000 ;
+ RECT 1630.820000 2149.350000 1631.920000 2546.690000 ;
+ LAYER met3 ;
+ RECT 1630.820000 2536.480000 1631.920000 2536.960000 ;
+ RECT 1630.820000 2541.920000 1631.920000 2542.400000 ;
+ RECT 1643.630000 2536.480000 1644.630000 2536.960000 ;
+ RECT 1643.630000 2541.920000 1644.630000 2542.400000 ;
+ RECT 1630.820000 2525.600000 1631.920000 2526.080000 ;
+ RECT 1630.820000 2531.040000 1631.920000 2531.520000 ;
+ RECT 1643.630000 2525.600000 1644.630000 2526.080000 ;
+ RECT 1643.630000 2531.040000 1644.630000 2531.520000 ;
+ RECT 1643.630000 2514.720000 1644.630000 2515.200000 ;
+ RECT 1643.630000 2520.160000 1644.630000 2520.640000 ;
+ RECT 1630.820000 2520.160000 1631.920000 2520.640000 ;
+ RECT 1630.820000 2514.720000 1631.920000 2515.200000 ;
+ RECT 1630.820000 2503.840000 1631.920000 2504.320000 ;
+ RECT 1630.820000 2509.280000 1631.920000 2509.760000 ;
+ RECT 1643.630000 2503.840000 1644.630000 2504.320000 ;
+ RECT 1643.630000 2509.280000 1644.630000 2509.760000 ;
+ RECT 1585.820000 2525.600000 1586.920000 2526.080000 ;
+ RECT 1585.820000 2531.040000 1586.920000 2531.520000 ;
+ RECT 1585.820000 2536.480000 1586.920000 2536.960000 ;
+ RECT 1585.820000 2541.920000 1586.920000 2542.400000 ;
+ RECT 1585.820000 2509.280000 1586.920000 2509.760000 ;
+ RECT 1585.820000 2503.840000 1586.920000 2504.320000 ;
+ RECT 1585.820000 2514.720000 1586.920000 2515.200000 ;
+ RECT 1585.820000 2520.160000 1586.920000 2520.640000 ;
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+ RECT 1643.630000 2193.760000 1644.630000 2194.240000 ;
+ RECT 1630.820000 2177.440000 1631.920000 2177.920000 ;
+ RECT 1630.820000 2182.880000 1631.920000 2183.360000 ;
+ RECT 1643.630000 2177.440000 1644.630000 2177.920000 ;
+ RECT 1643.630000 2182.880000 1644.630000 2183.360000 ;
+ RECT 1643.630000 2166.560000 1644.630000 2167.040000 ;
+ RECT 1643.630000 2161.120000 1644.630000 2161.600000 ;
+ RECT 1643.630000 2172.000000 1644.630000 2172.480000 ;
+ RECT 1630.820000 2172.000000 1631.920000 2172.480000 ;
+ RECT 1630.820000 2166.560000 1631.920000 2167.040000 ;
+ RECT 1630.820000 2161.120000 1631.920000 2161.600000 ;
+ RECT 1630.820000 2155.680000 1631.920000 2156.160000 ;
+ RECT 1643.630000 2155.680000 1644.630000 2156.160000 ;
+ RECT 1585.820000 2177.440000 1586.920000 2177.920000 ;
+ RECT 1585.820000 2182.880000 1586.920000 2183.360000 ;
+ RECT 1585.820000 2188.320000 1586.920000 2188.800000 ;
+ RECT 1585.820000 2193.760000 1586.920000 2194.240000 ;
+ RECT 1585.820000 2155.680000 1586.920000 2156.160000 ;
+ RECT 1585.820000 2161.120000 1586.920000 2161.600000 ;
+ RECT 1585.820000 2166.560000 1586.920000 2167.040000 ;
+ RECT 1585.820000 2172.000000 1586.920000 2172.480000 ;
+ RECT 1630.820000 2248.160000 1631.920000 2248.640000 ;
+ RECT 1585.820000 2248.160000 1586.920000 2248.640000 ;
+ RECT 1643.630000 2248.160000 1644.630000 2248.640000 ;
+ RECT 1540.820000 2324.320000 1541.920000 2324.800000 ;
+ RECT 1540.820000 2329.760000 1541.920000 2330.240000 ;
+ RECT 1540.820000 2335.200000 1541.920000 2335.680000 ;
+ RECT 1540.820000 2340.640000 1541.920000 2341.120000 ;
+ RECT 1540.820000 2346.080000 1541.920000 2346.560000 ;
+ RECT 1495.820000 2324.320000 1496.920000 2324.800000 ;
+ RECT 1495.820000 2329.760000 1496.920000 2330.240000 ;
+ RECT 1495.820000 2335.200000 1496.920000 2335.680000 ;
+ RECT 1495.820000 2340.640000 1496.920000 2341.120000 ;
+ RECT 1495.820000 2346.080000 1496.920000 2346.560000 ;
+ RECT 1540.820000 2302.560000 1541.920000 2303.040000 ;
+ RECT 1540.820000 2308.000000 1541.920000 2308.480000 ;
+ RECT 1540.820000 2313.440000 1541.920000 2313.920000 ;
+ RECT 1540.820000 2318.880000 1541.920000 2319.360000 ;
+ RECT 1495.820000 2302.560000 1496.920000 2303.040000 ;
+ RECT 1495.820000 2308.000000 1496.920000 2308.480000 ;
+ RECT 1495.820000 2313.440000 1496.920000 2313.920000 ;
+ RECT 1495.820000 2318.880000 1496.920000 2319.360000 ;
+ RECT 1446.990000 2346.080000 1447.990000 2346.560000 ;
+ RECT 1450.655000 2346.080000 1451.920000 2346.560000 ;
+ RECT 1446.990000 2340.640000 1447.990000 2341.120000 ;
+ RECT 1450.655000 2340.640000 1451.920000 2341.120000 ;
+ RECT 1446.990000 2329.760000 1447.990000 2330.240000 ;
+ RECT 1450.655000 2329.760000 1451.920000 2330.240000 ;
+ RECT 1446.990000 2335.200000 1447.990000 2335.680000 ;
+ RECT 1450.655000 2335.200000 1451.920000 2335.680000 ;
+ RECT 1446.990000 2324.320000 1447.990000 2324.800000 ;
+ RECT 1450.655000 2324.320000 1451.920000 2324.800000 ;
+ RECT 1446.990000 2318.880000 1447.990000 2319.360000 ;
+ RECT 1450.655000 2318.880000 1451.920000 2319.360000 ;
+ RECT 1446.990000 2313.440000 1447.990000 2313.920000 ;
+ RECT 1450.655000 2313.440000 1451.920000 2313.920000 ;
+ RECT 1446.990000 2308.000000 1447.990000 2308.480000 ;
+ RECT 1450.655000 2308.000000 1451.920000 2308.480000 ;
+ RECT 1446.990000 2302.560000 1447.990000 2303.040000 ;
+ RECT 1450.655000 2302.560000 1451.920000 2303.040000 ;
+ RECT 1540.820000 2275.360000 1541.920000 2275.840000 ;
+ RECT 1540.820000 2280.800000 1541.920000 2281.280000 ;
+ RECT 1540.820000 2286.240000 1541.920000 2286.720000 ;
+ RECT 1540.820000 2291.680000 1541.920000 2292.160000 ;
+ RECT 1540.820000 2297.120000 1541.920000 2297.600000 ;
+ RECT 1495.820000 2275.360000 1496.920000 2275.840000 ;
+ RECT 1495.820000 2280.800000 1496.920000 2281.280000 ;
+ RECT 1495.820000 2286.240000 1496.920000 2286.720000 ;
+ RECT 1495.820000 2291.680000 1496.920000 2292.160000 ;
+ RECT 1495.820000 2297.120000 1496.920000 2297.600000 ;
+ RECT 1540.820000 2253.600000 1541.920000 2254.080000 ;
+ RECT 1540.820000 2259.040000 1541.920000 2259.520000 ;
+ RECT 1540.820000 2264.480000 1541.920000 2264.960000 ;
+ RECT 1540.820000 2269.920000 1541.920000 2270.400000 ;
+ RECT 1495.820000 2253.600000 1496.920000 2254.080000 ;
+ RECT 1495.820000 2259.040000 1496.920000 2259.520000 ;
+ RECT 1495.820000 2264.480000 1496.920000 2264.960000 ;
+ RECT 1495.820000 2269.920000 1496.920000 2270.400000 ;
+ RECT 1446.990000 2297.120000 1447.990000 2297.600000 ;
+ RECT 1450.655000 2297.120000 1451.920000 2297.600000 ;
+ RECT 1446.990000 2286.240000 1447.990000 2286.720000 ;
+ RECT 1450.655000 2286.240000 1451.920000 2286.720000 ;
+ RECT 1446.990000 2291.680000 1447.990000 2292.160000 ;
+ RECT 1450.655000 2291.680000 1451.920000 2292.160000 ;
+ RECT 1446.990000 2280.800000 1447.990000 2281.280000 ;
+ RECT 1450.655000 2280.800000 1451.920000 2281.280000 ;
+ RECT 1446.990000 2275.360000 1447.990000 2275.840000 ;
+ RECT 1450.655000 2275.360000 1451.920000 2275.840000 ;
+ RECT 1446.990000 2269.920000 1447.990000 2270.400000 ;
+ RECT 1450.655000 2269.920000 1451.920000 2270.400000 ;
+ RECT 1446.990000 2264.480000 1447.990000 2264.960000 ;
+ RECT 1450.655000 2264.480000 1451.920000 2264.960000 ;
+ RECT 1446.990000 2259.040000 1447.990000 2259.520000 ;
+ RECT 1450.655000 2259.040000 1451.920000 2259.520000 ;
+ RECT 1446.990000 2253.600000 1447.990000 2254.080000 ;
+ RECT 1450.655000 2253.600000 1451.920000 2254.080000 ;
+ RECT 1540.820000 2226.400000 1541.920000 2226.880000 ;
+ RECT 1540.820000 2231.840000 1541.920000 2232.320000 ;
+ RECT 1540.820000 2237.280000 1541.920000 2237.760000 ;
+ RECT 1540.820000 2242.720000 1541.920000 2243.200000 ;
+ RECT 1495.820000 2226.400000 1496.920000 2226.880000 ;
+ RECT 1495.820000 2231.840000 1496.920000 2232.320000 ;
+ RECT 1495.820000 2237.280000 1496.920000 2237.760000 ;
+ RECT 1495.820000 2242.720000 1496.920000 2243.200000 ;
+ RECT 1540.820000 2199.200000 1541.920000 2199.680000 ;
+ RECT 1540.820000 2204.640000 1541.920000 2205.120000 ;
+ RECT 1540.820000 2210.080000 1541.920000 2210.560000 ;
+ RECT 1540.820000 2215.520000 1541.920000 2216.000000 ;
+ RECT 1540.820000 2220.960000 1541.920000 2221.440000 ;
+ RECT 1495.820000 2199.200000 1496.920000 2199.680000 ;
+ RECT 1495.820000 2204.640000 1496.920000 2205.120000 ;
+ RECT 1495.820000 2210.080000 1496.920000 2210.560000 ;
+ RECT 1495.820000 2215.520000 1496.920000 2216.000000 ;
+ RECT 1495.820000 2220.960000 1496.920000 2221.440000 ;
+ RECT 1446.990000 2242.720000 1447.990000 2243.200000 ;
+ RECT 1450.655000 2242.720000 1451.920000 2243.200000 ;
+ RECT 1446.990000 2237.280000 1447.990000 2237.760000 ;
+ RECT 1450.655000 2237.280000 1451.920000 2237.760000 ;
+ RECT 1446.990000 2231.840000 1447.990000 2232.320000 ;
+ RECT 1450.655000 2231.840000 1451.920000 2232.320000 ;
+ RECT 1446.990000 2226.400000 1447.990000 2226.880000 ;
+ RECT 1450.655000 2226.400000 1451.920000 2226.880000 ;
+ RECT 1446.990000 2220.960000 1447.990000 2221.440000 ;
+ RECT 1450.655000 2220.960000 1451.920000 2221.440000 ;
+ RECT 1446.990000 2215.520000 1447.990000 2216.000000 ;
+ RECT 1450.655000 2215.520000 1451.920000 2216.000000 ;
+ RECT 1446.990000 2204.640000 1447.990000 2205.120000 ;
+ RECT 1450.655000 2204.640000 1451.920000 2205.120000 ;
+ RECT 1446.990000 2210.080000 1447.990000 2210.560000 ;
+ RECT 1450.655000 2210.080000 1451.920000 2210.560000 ;
+ RECT 1446.990000 2199.200000 1447.990000 2199.680000 ;
+ RECT 1450.655000 2199.200000 1451.920000 2199.680000 ;
+ RECT 1540.820000 2177.440000 1541.920000 2177.920000 ;
+ RECT 1540.820000 2182.880000 1541.920000 2183.360000 ;
+ RECT 1540.820000 2188.320000 1541.920000 2188.800000 ;
+ RECT 1540.820000 2193.760000 1541.920000 2194.240000 ;
+ RECT 1495.820000 2177.440000 1496.920000 2177.920000 ;
+ RECT 1495.820000 2182.880000 1496.920000 2183.360000 ;
+ RECT 1495.820000 2188.320000 1496.920000 2188.800000 ;
+ RECT 1495.820000 2193.760000 1496.920000 2194.240000 ;
+ RECT 1540.820000 2155.680000 1541.920000 2156.160000 ;
+ RECT 1540.820000 2161.120000 1541.920000 2161.600000 ;
+ RECT 1540.820000 2166.560000 1541.920000 2167.040000 ;
+ RECT 1540.820000 2172.000000 1541.920000 2172.480000 ;
+ RECT 1495.820000 2155.680000 1496.920000 2156.160000 ;
+ RECT 1495.820000 2161.120000 1496.920000 2161.600000 ;
+ RECT 1495.820000 2166.560000 1496.920000 2167.040000 ;
+ RECT 1495.820000 2172.000000 1496.920000 2172.480000 ;
+ RECT 1446.990000 2193.760000 1447.990000 2194.240000 ;
+ RECT 1450.655000 2193.760000 1451.920000 2194.240000 ;
+ RECT 1446.990000 2188.320000 1447.990000 2188.800000 ;
+ RECT 1450.655000 2188.320000 1451.920000 2188.800000 ;
+ RECT 1446.990000 2182.880000 1447.990000 2183.360000 ;
+ RECT 1450.655000 2182.880000 1451.920000 2183.360000 ;
+ RECT 1446.990000 2177.440000 1447.990000 2177.920000 ;
+ RECT 1450.655000 2177.440000 1451.920000 2177.920000 ;
+ RECT 1446.990000 2172.000000 1447.990000 2172.480000 ;
+ RECT 1450.655000 2172.000000 1451.920000 2172.480000 ;
+ RECT 1446.990000 2161.120000 1447.990000 2161.600000 ;
+ RECT 1450.655000 2161.120000 1451.920000 2161.600000 ;
+ RECT 1446.990000 2166.560000 1447.990000 2167.040000 ;
+ RECT 1450.655000 2166.560000 1451.920000 2167.040000 ;
+ RECT 1446.990000 2155.680000 1447.990000 2156.160000 ;
+ RECT 1450.655000 2155.680000 1451.920000 2156.160000 ;
+ RECT 1540.820000 2248.160000 1541.920000 2248.640000 ;
+ RECT 1495.820000 2248.160000 1496.920000 2248.640000 ;
+ RECT 1446.990000 2248.160000 1447.990000 2248.640000 ;
+ RECT 1450.655000 2248.160000 1451.920000 2248.640000 ;
+ RECT 1445.760000 2545.690000 1645.860000 2546.690000 ;
+ RECT 1445.760000 2149.350000 1645.860000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 2148.100000 1447.990000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 2547.620000 1447.990000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 2148.100000 1644.630000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 2547.620000 1644.630000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2149.350000 1446.760000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2149.350000 1645.860000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2545.690000 1446.760000 2546.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2545.690000 1645.860000 2546.690000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1450.655000 2135.960000 1451.920000 2136.440000 ;
+ RECT 1450.655000 2141.400000 1451.920000 2141.880000 ;
+ RECT 1450.655000 2130.520000 1451.920000 2131.000000 ;
+ RECT 1450.655000 2125.080000 1451.920000 2125.560000 ;
+ RECT 1450.655000 2119.640000 1451.920000 2120.120000 ;
+ RECT 1450.655000 2114.200000 1451.920000 2114.680000 ;
+ RECT 1450.655000 2108.760000 1451.920000 2109.240000 ;
+ RECT 1450.655000 2103.320000 1451.920000 2103.800000 ;
+ RECT 1450.655000 2092.440000 1451.920000 2092.920000 ;
+ RECT 1450.655000 2087.000000 1451.920000 2087.480000 ;
+ RECT 1450.655000 2081.560000 1451.920000 2082.040000 ;
+ RECT 1450.655000 2076.120000 1451.920000 2076.600000 ;
+ RECT 1450.655000 2070.680000 1451.920000 2071.160000 ;
+ RECT 1450.655000 2065.240000 1451.920000 2065.720000 ;
+ RECT 1450.655000 2054.360000 1451.920000 2054.840000 ;
+ RECT 1450.655000 2059.800000 1451.920000 2060.280000 ;
+ RECT 1450.655000 2048.920000 1451.920000 2049.400000 ;
+ RECT 1450.655000 2097.880000 1451.920000 2098.360000 ;
+ RECT 1450.655000 2043.480000 1451.920000 2043.960000 ;
+ RECT 1450.655000 2038.040000 1451.920000 2038.520000 ;
+ RECT 1450.655000 2032.600000 1451.920000 2033.080000 ;
+ RECT 1450.655000 2027.160000 1451.920000 2027.640000 ;
+ RECT 1450.655000 2021.720000 1451.920000 2022.200000 ;
+ RECT 1450.655000 2010.840000 1451.920000 2011.320000 ;
+ RECT 1450.655000 2016.280000 1451.920000 2016.760000 ;
+ RECT 1450.655000 2005.400000 1451.920000 2005.880000 ;
+ RECT 1450.655000 1999.960000 1451.920000 2000.440000 ;
+ RECT 1450.655000 1994.520000 1451.920000 1995.000000 ;
+ RECT 1450.655000 1989.080000 1451.920000 1989.560000 ;
+ RECT 1450.655000 1983.640000 1451.920000 1984.120000 ;
+ RECT 1450.655000 1978.200000 1451.920000 1978.680000 ;
+ RECT 1450.655000 1967.320000 1451.920000 1967.800000 ;
+ RECT 1450.655000 1961.880000 1451.920000 1962.360000 ;
+ RECT 1450.655000 1956.440000 1451.920000 1956.920000 ;
+ RECT 1450.655000 1951.000000 1451.920000 1951.480000 ;
+ RECT 1450.655000 1972.760000 1451.920000 1973.240000 ;
+ RECT 1450.655000 1945.560000 1451.920000 1946.040000 ;
+ RECT 1450.655000 1940.120000 1451.920000 1940.600000 ;
+ RECT 1450.655000 1929.240000 1451.920000 1929.720000 ;
+ RECT 1450.655000 1934.680000 1451.920000 1935.160000 ;
+ RECT 1450.655000 1923.800000 1451.920000 1924.280000 ;
+ RECT 1450.655000 1918.360000 1451.920000 1918.840000 ;
+ RECT 1450.655000 1912.920000 1451.920000 1913.400000 ;
+ RECT 1450.655000 1907.480000 1451.920000 1907.960000 ;
+ RECT 1450.655000 1902.040000 1451.920000 1902.520000 ;
+ RECT 1450.655000 1896.600000 1451.920000 1897.080000 ;
+ RECT 1450.655000 1885.720000 1451.920000 1886.200000 ;
+ RECT 1450.655000 1891.160000 1451.920000 1891.640000 ;
+ RECT 1450.655000 1880.280000 1451.920000 1880.760000 ;
+ RECT 1450.655000 1874.840000 1451.920000 1875.320000 ;
+ RECT 1450.655000 1869.400000 1451.920000 1869.880000 ;
+ RECT 1450.655000 1863.960000 1451.920000 1864.440000 ;
+ RECT 1450.655000 1858.520000 1451.920000 1859.000000 ;
+ RECT 1450.655000 1853.080000 1451.920000 1853.560000 ;
+ RECT 1450.655000 1842.200000 1451.920000 1842.680000 ;
+ RECT 1450.655000 1836.760000 1451.920000 1837.240000 ;
+ RECT 1450.655000 1831.320000 1451.920000 1831.800000 ;
+ RECT 1450.655000 1825.880000 1451.920000 1826.360000 ;
+ RECT 1450.655000 1820.440000 1451.920000 1820.920000 ;
+ RECT 1450.655000 1815.000000 1451.920000 1815.480000 ;
+ RECT 1450.655000 1804.120000 1451.920000 1804.600000 ;
+ RECT 1450.655000 1809.560000 1451.920000 1810.040000 ;
+ RECT 1450.655000 1798.680000 1451.920000 1799.160000 ;
+ RECT 1450.655000 1793.240000 1451.920000 1793.720000 ;
+ RECT 1450.655000 1787.800000 1451.920000 1788.280000 ;
+ RECT 1450.655000 1782.360000 1451.920000 1782.840000 ;
+ RECT 1450.655000 1776.920000 1451.920000 1777.400000 ;
+ RECT 1450.655000 1771.480000 1451.920000 1771.960000 ;
+ RECT 1450.655000 1760.600000 1451.920000 1761.080000 ;
+ RECT 1450.655000 1766.040000 1451.920000 1766.520000 ;
+ RECT 1450.655000 1755.160000 1451.920000 1755.640000 ;
+ RECT 1450.655000 1847.640000 1451.920000 1848.120000 ;
+ RECT 1446.990000 1747.580000 1447.990000 2148.100000 ;
+ RECT 1643.630000 1747.580000 1644.630000 2148.100000 ;
+ RECT 1450.820000 1748.830000 1451.920000 2146.170000 ;
+ RECT 1495.820000 1748.830000 1496.920000 2146.170000 ;
+ RECT 1540.820000 1748.830000 1541.920000 2146.170000 ;
+ RECT 1585.820000 1748.830000 1586.920000 2146.170000 ;
+ RECT 1630.820000 1748.830000 1631.920000 2146.170000 ;
+ LAYER met3 ;
+ RECT 1630.820000 2135.960000 1631.920000 2136.440000 ;
+ RECT 1630.820000 2141.400000 1631.920000 2141.880000 ;
+ RECT 1643.630000 2135.960000 1644.630000 2136.440000 ;
+ RECT 1643.630000 2141.400000 1644.630000 2141.880000 ;
+ RECT 1630.820000 2125.080000 1631.920000 2125.560000 ;
+ RECT 1630.820000 2130.520000 1631.920000 2131.000000 ;
+ RECT 1643.630000 2125.080000 1644.630000 2125.560000 ;
+ RECT 1643.630000 2130.520000 1644.630000 2131.000000 ;
+ RECT 1643.630000 2114.200000 1644.630000 2114.680000 ;
+ RECT 1643.630000 2119.640000 1644.630000 2120.120000 ;
+ RECT 1630.820000 2119.640000 1631.920000 2120.120000 ;
+ RECT 1630.820000 2114.200000 1631.920000 2114.680000 ;
+ RECT 1630.820000 2103.320000 1631.920000 2103.800000 ;
+ RECT 1630.820000 2108.760000 1631.920000 2109.240000 ;
+ RECT 1643.630000 2103.320000 1644.630000 2103.800000 ;
+ RECT 1643.630000 2108.760000 1644.630000 2109.240000 ;
+ RECT 1585.820000 2125.080000 1586.920000 2125.560000 ;
+ RECT 1585.820000 2130.520000 1586.920000 2131.000000 ;
+ RECT 1585.820000 2135.960000 1586.920000 2136.440000 ;
+ RECT 1585.820000 2141.400000 1586.920000 2141.880000 ;
+ RECT 1585.820000 2108.760000 1586.920000 2109.240000 ;
+ RECT 1585.820000 2103.320000 1586.920000 2103.800000 ;
+ RECT 1585.820000 2114.200000 1586.920000 2114.680000 ;
+ RECT 1585.820000 2119.640000 1586.920000 2120.120000 ;
+ RECT 1630.820000 2087.000000 1631.920000 2087.480000 ;
+ RECT 1630.820000 2092.440000 1631.920000 2092.920000 ;
+ RECT 1643.630000 2087.000000 1644.630000 2087.480000 ;
+ RECT 1643.630000 2092.440000 1644.630000 2092.920000 ;
+ RECT 1643.630000 2076.120000 1644.630000 2076.600000 ;
+ RECT 1643.630000 2081.560000 1644.630000 2082.040000 ;
+ RECT 1630.820000 2081.560000 1631.920000 2082.040000 ;
+ RECT 1630.820000 2076.120000 1631.920000 2076.600000 ;
+ RECT 1630.820000 2065.240000 1631.920000 2065.720000 ;
+ RECT 1630.820000 2070.680000 1631.920000 2071.160000 ;
+ RECT 1643.630000 2065.240000 1644.630000 2065.720000 ;
+ RECT 1643.630000 2070.680000 1644.630000 2071.160000 ;
+ RECT 1643.630000 2054.360000 1644.630000 2054.840000 ;
+ RECT 1643.630000 2048.920000 1644.630000 2049.400000 ;
+ RECT 1643.630000 2059.800000 1644.630000 2060.280000 ;
+ RECT 1630.820000 2059.800000 1631.920000 2060.280000 ;
+ RECT 1630.820000 2054.360000 1631.920000 2054.840000 ;
+ RECT 1630.820000 2048.920000 1631.920000 2049.400000 ;
+ RECT 1585.820000 2076.120000 1586.920000 2076.600000 ;
+ RECT 1585.820000 2081.560000 1586.920000 2082.040000 ;
+ RECT 1585.820000 2087.000000 1586.920000 2087.480000 ;
+ RECT 1585.820000 2092.440000 1586.920000 2092.920000 ;
+ RECT 1585.820000 2048.920000 1586.920000 2049.400000 ;
+ RECT 1585.820000 2054.360000 1586.920000 2054.840000 ;
+ RECT 1585.820000 2059.800000 1586.920000 2060.280000 ;
+ RECT 1585.820000 2065.240000 1586.920000 2065.720000 ;
+ RECT 1585.820000 2070.680000 1586.920000 2071.160000 ;
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+ RECT 1450.655000 1945.560000 1451.920000 1946.040000 ;
+ RECT 1446.990000 1940.120000 1447.990000 1940.600000 ;
+ RECT 1450.655000 1940.120000 1451.920000 1940.600000 ;
+ RECT 1446.990000 1929.240000 1447.990000 1929.720000 ;
+ RECT 1450.655000 1929.240000 1451.920000 1929.720000 ;
+ RECT 1446.990000 1934.680000 1447.990000 1935.160000 ;
+ RECT 1450.655000 1934.680000 1451.920000 1935.160000 ;
+ RECT 1446.990000 1923.800000 1447.990000 1924.280000 ;
+ RECT 1450.655000 1923.800000 1451.920000 1924.280000 ;
+ RECT 1446.990000 1918.360000 1447.990000 1918.840000 ;
+ RECT 1450.655000 1918.360000 1451.920000 1918.840000 ;
+ RECT 1446.990000 1912.920000 1447.990000 1913.400000 ;
+ RECT 1450.655000 1912.920000 1451.920000 1913.400000 ;
+ RECT 1446.990000 1907.480000 1447.990000 1907.960000 ;
+ RECT 1450.655000 1907.480000 1451.920000 1907.960000 ;
+ RECT 1446.990000 1902.040000 1447.990000 1902.520000 ;
+ RECT 1450.655000 1902.040000 1451.920000 1902.520000 ;
+ RECT 1540.820000 1874.840000 1541.920000 1875.320000 ;
+ RECT 1540.820000 1880.280000 1541.920000 1880.760000 ;
+ RECT 1540.820000 1885.720000 1541.920000 1886.200000 ;
+ RECT 1540.820000 1891.160000 1541.920000 1891.640000 ;
+ RECT 1540.820000 1896.600000 1541.920000 1897.080000 ;
+ RECT 1495.820000 1874.840000 1496.920000 1875.320000 ;
+ RECT 1495.820000 1880.280000 1496.920000 1880.760000 ;
+ RECT 1495.820000 1885.720000 1496.920000 1886.200000 ;
+ RECT 1495.820000 1891.160000 1496.920000 1891.640000 ;
+ RECT 1495.820000 1896.600000 1496.920000 1897.080000 ;
+ RECT 1540.820000 1853.080000 1541.920000 1853.560000 ;
+ RECT 1540.820000 1858.520000 1541.920000 1859.000000 ;
+ RECT 1540.820000 1863.960000 1541.920000 1864.440000 ;
+ RECT 1540.820000 1869.400000 1541.920000 1869.880000 ;
+ RECT 1495.820000 1853.080000 1496.920000 1853.560000 ;
+ RECT 1495.820000 1858.520000 1496.920000 1859.000000 ;
+ RECT 1495.820000 1863.960000 1496.920000 1864.440000 ;
+ RECT 1495.820000 1869.400000 1496.920000 1869.880000 ;
+ RECT 1446.990000 1896.600000 1447.990000 1897.080000 ;
+ RECT 1450.655000 1896.600000 1451.920000 1897.080000 ;
+ RECT 1446.990000 1885.720000 1447.990000 1886.200000 ;
+ RECT 1450.655000 1885.720000 1451.920000 1886.200000 ;
+ RECT 1446.990000 1891.160000 1447.990000 1891.640000 ;
+ RECT 1450.655000 1891.160000 1451.920000 1891.640000 ;
+ RECT 1446.990000 1880.280000 1447.990000 1880.760000 ;
+ RECT 1450.655000 1880.280000 1451.920000 1880.760000 ;
+ RECT 1446.990000 1874.840000 1447.990000 1875.320000 ;
+ RECT 1450.655000 1874.840000 1451.920000 1875.320000 ;
+ RECT 1446.990000 1869.400000 1447.990000 1869.880000 ;
+ RECT 1450.655000 1869.400000 1451.920000 1869.880000 ;
+ RECT 1446.990000 1863.960000 1447.990000 1864.440000 ;
+ RECT 1450.655000 1863.960000 1451.920000 1864.440000 ;
+ RECT 1446.990000 1858.520000 1447.990000 1859.000000 ;
+ RECT 1450.655000 1858.520000 1451.920000 1859.000000 ;
+ RECT 1446.990000 1853.080000 1447.990000 1853.560000 ;
+ RECT 1450.655000 1853.080000 1451.920000 1853.560000 ;
+ RECT 1540.820000 1825.880000 1541.920000 1826.360000 ;
+ RECT 1540.820000 1831.320000 1541.920000 1831.800000 ;
+ RECT 1540.820000 1836.760000 1541.920000 1837.240000 ;
+ RECT 1540.820000 1842.200000 1541.920000 1842.680000 ;
+ RECT 1495.820000 1825.880000 1496.920000 1826.360000 ;
+ RECT 1495.820000 1831.320000 1496.920000 1831.800000 ;
+ RECT 1495.820000 1836.760000 1496.920000 1837.240000 ;
+ RECT 1495.820000 1842.200000 1496.920000 1842.680000 ;
+ RECT 1540.820000 1798.680000 1541.920000 1799.160000 ;
+ RECT 1540.820000 1804.120000 1541.920000 1804.600000 ;
+ RECT 1540.820000 1809.560000 1541.920000 1810.040000 ;
+ RECT 1540.820000 1815.000000 1541.920000 1815.480000 ;
+ RECT 1540.820000 1820.440000 1541.920000 1820.920000 ;
+ RECT 1495.820000 1798.680000 1496.920000 1799.160000 ;
+ RECT 1495.820000 1804.120000 1496.920000 1804.600000 ;
+ RECT 1495.820000 1809.560000 1496.920000 1810.040000 ;
+ RECT 1495.820000 1815.000000 1496.920000 1815.480000 ;
+ RECT 1495.820000 1820.440000 1496.920000 1820.920000 ;
+ RECT 1446.990000 1842.200000 1447.990000 1842.680000 ;
+ RECT 1450.655000 1842.200000 1451.920000 1842.680000 ;
+ RECT 1446.990000 1836.760000 1447.990000 1837.240000 ;
+ RECT 1450.655000 1836.760000 1451.920000 1837.240000 ;
+ RECT 1446.990000 1831.320000 1447.990000 1831.800000 ;
+ RECT 1450.655000 1831.320000 1451.920000 1831.800000 ;
+ RECT 1446.990000 1825.880000 1447.990000 1826.360000 ;
+ RECT 1450.655000 1825.880000 1451.920000 1826.360000 ;
+ RECT 1446.990000 1820.440000 1447.990000 1820.920000 ;
+ RECT 1450.655000 1820.440000 1451.920000 1820.920000 ;
+ RECT 1446.990000 1815.000000 1447.990000 1815.480000 ;
+ RECT 1450.655000 1815.000000 1451.920000 1815.480000 ;
+ RECT 1446.990000 1804.120000 1447.990000 1804.600000 ;
+ RECT 1450.655000 1804.120000 1451.920000 1804.600000 ;
+ RECT 1446.990000 1809.560000 1447.990000 1810.040000 ;
+ RECT 1450.655000 1809.560000 1451.920000 1810.040000 ;
+ RECT 1446.990000 1798.680000 1447.990000 1799.160000 ;
+ RECT 1450.655000 1798.680000 1451.920000 1799.160000 ;
+ RECT 1540.820000 1776.920000 1541.920000 1777.400000 ;
+ RECT 1540.820000 1782.360000 1541.920000 1782.840000 ;
+ RECT 1540.820000 1787.800000 1541.920000 1788.280000 ;
+ RECT 1540.820000 1793.240000 1541.920000 1793.720000 ;
+ RECT 1495.820000 1776.920000 1496.920000 1777.400000 ;
+ RECT 1495.820000 1782.360000 1496.920000 1782.840000 ;
+ RECT 1495.820000 1787.800000 1496.920000 1788.280000 ;
+ RECT 1495.820000 1793.240000 1496.920000 1793.720000 ;
+ RECT 1540.820000 1755.160000 1541.920000 1755.640000 ;
+ RECT 1540.820000 1760.600000 1541.920000 1761.080000 ;
+ RECT 1540.820000 1766.040000 1541.920000 1766.520000 ;
+ RECT 1540.820000 1771.480000 1541.920000 1771.960000 ;
+ RECT 1495.820000 1755.160000 1496.920000 1755.640000 ;
+ RECT 1495.820000 1760.600000 1496.920000 1761.080000 ;
+ RECT 1495.820000 1766.040000 1496.920000 1766.520000 ;
+ RECT 1495.820000 1771.480000 1496.920000 1771.960000 ;
+ RECT 1446.990000 1793.240000 1447.990000 1793.720000 ;
+ RECT 1450.655000 1793.240000 1451.920000 1793.720000 ;
+ RECT 1446.990000 1787.800000 1447.990000 1788.280000 ;
+ RECT 1450.655000 1787.800000 1451.920000 1788.280000 ;
+ RECT 1446.990000 1782.360000 1447.990000 1782.840000 ;
+ RECT 1450.655000 1782.360000 1451.920000 1782.840000 ;
+ RECT 1446.990000 1776.920000 1447.990000 1777.400000 ;
+ RECT 1450.655000 1776.920000 1451.920000 1777.400000 ;
+ RECT 1446.990000 1771.480000 1447.990000 1771.960000 ;
+ RECT 1450.655000 1771.480000 1451.920000 1771.960000 ;
+ RECT 1446.990000 1760.600000 1447.990000 1761.080000 ;
+ RECT 1450.655000 1760.600000 1451.920000 1761.080000 ;
+ RECT 1446.990000 1766.040000 1447.990000 1766.520000 ;
+ RECT 1450.655000 1766.040000 1451.920000 1766.520000 ;
+ RECT 1446.990000 1755.160000 1447.990000 1755.640000 ;
+ RECT 1450.655000 1755.160000 1451.920000 1755.640000 ;
+ RECT 1540.820000 1847.640000 1541.920000 1848.120000 ;
+ RECT 1495.820000 1847.640000 1496.920000 1848.120000 ;
+ RECT 1446.990000 1847.640000 1447.990000 1848.120000 ;
+ RECT 1450.655000 1847.640000 1451.920000 1848.120000 ;
+ RECT 1445.760000 2145.170000 1645.860000 2146.170000 ;
+ RECT 1445.760000 1748.830000 1645.860000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 1747.580000 1447.990000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 2147.100000 1447.990000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 1747.580000 1644.630000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 2147.100000 1644.630000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 1748.830000 1446.760000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 1748.830000 1645.860000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2145.170000 1446.760000 2146.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2145.170000 1645.860000 2146.170000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1450.655000 1735.440000 1451.920000 1735.920000 ;
+ RECT 1450.655000 1740.880000 1451.920000 1741.360000 ;
+ RECT 1450.655000 1730.000000 1451.920000 1730.480000 ;
+ RECT 1450.655000 1724.560000 1451.920000 1725.040000 ;
+ RECT 1450.655000 1719.120000 1451.920000 1719.600000 ;
+ RECT 1450.655000 1713.680000 1451.920000 1714.160000 ;
+ RECT 1450.655000 1708.240000 1451.920000 1708.720000 ;
+ RECT 1450.655000 1702.800000 1451.920000 1703.280000 ;
+ RECT 1450.655000 1691.920000 1451.920000 1692.400000 ;
+ RECT 1450.655000 1686.480000 1451.920000 1686.960000 ;
+ RECT 1450.655000 1681.040000 1451.920000 1681.520000 ;
+ RECT 1450.655000 1675.600000 1451.920000 1676.080000 ;
+ RECT 1450.655000 1670.160000 1451.920000 1670.640000 ;
+ RECT 1450.655000 1664.720000 1451.920000 1665.200000 ;
+ RECT 1450.655000 1653.840000 1451.920000 1654.320000 ;
+ RECT 1450.655000 1659.280000 1451.920000 1659.760000 ;
+ RECT 1450.655000 1648.400000 1451.920000 1648.880000 ;
+ RECT 1450.655000 1697.360000 1451.920000 1697.840000 ;
+ RECT 1450.655000 1642.960000 1451.920000 1643.440000 ;
+ RECT 1450.655000 1637.520000 1451.920000 1638.000000 ;
+ RECT 1450.655000 1632.080000 1451.920000 1632.560000 ;
+ RECT 1450.655000 1626.640000 1451.920000 1627.120000 ;
+ RECT 1450.655000 1621.200000 1451.920000 1621.680000 ;
+ RECT 1450.655000 1610.320000 1451.920000 1610.800000 ;
+ RECT 1450.655000 1615.760000 1451.920000 1616.240000 ;
+ RECT 1450.655000 1604.880000 1451.920000 1605.360000 ;
+ RECT 1450.655000 1599.440000 1451.920000 1599.920000 ;
+ RECT 1450.655000 1594.000000 1451.920000 1594.480000 ;
+ RECT 1450.655000 1588.560000 1451.920000 1589.040000 ;
+ RECT 1450.655000 1583.120000 1451.920000 1583.600000 ;
+ RECT 1450.655000 1577.680000 1451.920000 1578.160000 ;
+ RECT 1450.655000 1566.800000 1451.920000 1567.280000 ;
+ RECT 1450.655000 1561.360000 1451.920000 1561.840000 ;
+ RECT 1450.655000 1555.920000 1451.920000 1556.400000 ;
+ RECT 1450.655000 1550.480000 1451.920000 1550.960000 ;
+ RECT 1450.655000 1572.240000 1451.920000 1572.720000 ;
+ RECT 1450.655000 1545.040000 1451.920000 1545.520000 ;
+ RECT 1450.655000 1539.600000 1451.920000 1540.080000 ;
+ RECT 1450.655000 1528.720000 1451.920000 1529.200000 ;
+ RECT 1450.655000 1534.160000 1451.920000 1534.640000 ;
+ RECT 1450.655000 1523.280000 1451.920000 1523.760000 ;
+ RECT 1450.655000 1517.840000 1451.920000 1518.320000 ;
+ RECT 1450.655000 1512.400000 1451.920000 1512.880000 ;
+ RECT 1450.655000 1506.960000 1451.920000 1507.440000 ;
+ RECT 1450.655000 1501.520000 1451.920000 1502.000000 ;
+ RECT 1450.655000 1496.080000 1451.920000 1496.560000 ;
+ RECT 1450.655000 1485.200000 1451.920000 1485.680000 ;
+ RECT 1450.655000 1490.640000 1451.920000 1491.120000 ;
+ RECT 1450.655000 1479.760000 1451.920000 1480.240000 ;
+ RECT 1450.655000 1474.320000 1451.920000 1474.800000 ;
+ RECT 1450.655000 1468.880000 1451.920000 1469.360000 ;
+ RECT 1450.655000 1463.440000 1451.920000 1463.920000 ;
+ RECT 1450.655000 1458.000000 1451.920000 1458.480000 ;
+ RECT 1450.655000 1452.560000 1451.920000 1453.040000 ;
+ RECT 1450.655000 1441.680000 1451.920000 1442.160000 ;
+ RECT 1450.655000 1436.240000 1451.920000 1436.720000 ;
+ RECT 1450.655000 1430.800000 1451.920000 1431.280000 ;
+ RECT 1450.655000 1425.360000 1451.920000 1425.840000 ;
+ RECT 1450.655000 1419.920000 1451.920000 1420.400000 ;
+ RECT 1450.655000 1414.480000 1451.920000 1414.960000 ;
+ RECT 1450.655000 1403.600000 1451.920000 1404.080000 ;
+ RECT 1450.655000 1409.040000 1451.920000 1409.520000 ;
+ RECT 1450.655000 1398.160000 1451.920000 1398.640000 ;
+ RECT 1450.655000 1392.720000 1451.920000 1393.200000 ;
+ RECT 1450.655000 1387.280000 1451.920000 1387.760000 ;
+ RECT 1450.655000 1381.840000 1451.920000 1382.320000 ;
+ RECT 1450.655000 1376.400000 1451.920000 1376.880000 ;
+ RECT 1450.655000 1370.960000 1451.920000 1371.440000 ;
+ RECT 1450.655000 1360.080000 1451.920000 1360.560000 ;
+ RECT 1450.655000 1365.520000 1451.920000 1366.000000 ;
+ RECT 1450.655000 1354.640000 1451.920000 1355.120000 ;
+ RECT 1450.655000 1447.120000 1451.920000 1447.600000 ;
+ RECT 1446.990000 1347.060000 1447.990000 1747.580000 ;
+ RECT 1643.630000 1347.060000 1644.630000 1747.580000 ;
+ RECT 1450.820000 1348.310000 1451.920000 1745.650000 ;
+ RECT 1495.820000 1348.310000 1496.920000 1745.650000 ;
+ RECT 1540.820000 1348.310000 1541.920000 1745.650000 ;
+ RECT 1585.820000 1348.310000 1586.920000 1745.650000 ;
+ RECT 1630.820000 1348.310000 1631.920000 1745.650000 ;
+ LAYER met3 ;
+ RECT 1630.820000 1735.440000 1631.920000 1735.920000 ;
+ RECT 1630.820000 1740.880000 1631.920000 1741.360000 ;
+ RECT 1643.630000 1735.440000 1644.630000 1735.920000 ;
+ RECT 1643.630000 1740.880000 1644.630000 1741.360000 ;
+ RECT 1630.820000 1724.560000 1631.920000 1725.040000 ;
+ RECT 1630.820000 1730.000000 1631.920000 1730.480000 ;
+ RECT 1643.630000 1724.560000 1644.630000 1725.040000 ;
+ RECT 1643.630000 1730.000000 1644.630000 1730.480000 ;
+ RECT 1643.630000 1713.680000 1644.630000 1714.160000 ;
+ RECT 1643.630000 1719.120000 1644.630000 1719.600000 ;
+ RECT 1630.820000 1719.120000 1631.920000 1719.600000 ;
+ RECT 1630.820000 1713.680000 1631.920000 1714.160000 ;
+ RECT 1630.820000 1702.800000 1631.920000 1703.280000 ;
+ RECT 1630.820000 1708.240000 1631.920000 1708.720000 ;
+ RECT 1643.630000 1702.800000 1644.630000 1703.280000 ;
+ RECT 1643.630000 1708.240000 1644.630000 1708.720000 ;
+ RECT 1585.820000 1724.560000 1586.920000 1725.040000 ;
+ RECT 1585.820000 1730.000000 1586.920000 1730.480000 ;
+ RECT 1585.820000 1735.440000 1586.920000 1735.920000 ;
+ RECT 1585.820000 1740.880000 1586.920000 1741.360000 ;
+ RECT 1585.820000 1708.240000 1586.920000 1708.720000 ;
+ RECT 1585.820000 1702.800000 1586.920000 1703.280000 ;
+ RECT 1585.820000 1713.680000 1586.920000 1714.160000 ;
+ RECT 1585.820000 1719.120000 1586.920000 1719.600000 ;
+ RECT 1630.820000 1686.480000 1631.920000 1686.960000 ;
+ RECT 1630.820000 1691.920000 1631.920000 1692.400000 ;
+ RECT 1643.630000 1686.480000 1644.630000 1686.960000 ;
+ RECT 1643.630000 1691.920000 1644.630000 1692.400000 ;
+ RECT 1643.630000 1675.600000 1644.630000 1676.080000 ;
+ RECT 1643.630000 1681.040000 1644.630000 1681.520000 ;
+ RECT 1630.820000 1681.040000 1631.920000 1681.520000 ;
+ RECT 1630.820000 1675.600000 1631.920000 1676.080000 ;
+ RECT 1630.820000 1664.720000 1631.920000 1665.200000 ;
+ RECT 1630.820000 1670.160000 1631.920000 1670.640000 ;
+ RECT 1643.630000 1664.720000 1644.630000 1665.200000 ;
+ RECT 1643.630000 1670.160000 1644.630000 1670.640000 ;
+ RECT 1643.630000 1653.840000 1644.630000 1654.320000 ;
+ RECT 1643.630000 1648.400000 1644.630000 1648.880000 ;
+ RECT 1643.630000 1659.280000 1644.630000 1659.760000 ;
+ RECT 1630.820000 1659.280000 1631.920000 1659.760000 ;
+ RECT 1630.820000 1653.840000 1631.920000 1654.320000 ;
+ RECT 1630.820000 1648.400000 1631.920000 1648.880000 ;
+ RECT 1585.820000 1675.600000 1586.920000 1676.080000 ;
+ RECT 1585.820000 1681.040000 1586.920000 1681.520000 ;
+ RECT 1585.820000 1686.480000 1586.920000 1686.960000 ;
+ RECT 1585.820000 1691.920000 1586.920000 1692.400000 ;
+ RECT 1585.820000 1648.400000 1586.920000 1648.880000 ;
+ RECT 1585.820000 1653.840000 1586.920000 1654.320000 ;
+ RECT 1585.820000 1659.280000 1586.920000 1659.760000 ;
+ RECT 1585.820000 1664.720000 1586.920000 1665.200000 ;
+ RECT 1585.820000 1670.160000 1586.920000 1670.640000 ;
+ RECT 1630.820000 1697.360000 1631.920000 1697.840000 ;
+ RECT 1585.820000 1697.360000 1586.920000 1697.840000 ;
+ RECT 1643.630000 1697.360000 1644.630000 1697.840000 ;
+ RECT 1630.820000 1637.520000 1631.920000 1638.000000 ;
+ RECT 1630.820000 1642.960000 1631.920000 1643.440000 ;
+ RECT 1643.630000 1637.520000 1644.630000 1638.000000 ;
+ RECT 1643.630000 1642.960000 1644.630000 1643.440000 ;
+ RECT 1630.820000 1626.640000 1631.920000 1627.120000 ;
+ RECT 1630.820000 1632.080000 1631.920000 1632.560000 ;
+ RECT 1643.630000 1626.640000 1644.630000 1627.120000 ;
+ RECT 1643.630000 1632.080000 1644.630000 1632.560000 ;
+ RECT 1643.630000 1615.760000 1644.630000 1616.240000 ;
+ RECT 1643.630000 1610.320000 1644.630000 1610.800000 ;
+ RECT 1643.630000 1621.200000 1644.630000 1621.680000 ;
+ RECT 1630.820000 1621.200000 1631.920000 1621.680000 ;
+ RECT 1630.820000 1615.760000 1631.920000 1616.240000 ;
+ RECT 1630.820000 1610.320000 1631.920000 1610.800000 ;
+ RECT 1630.820000 1599.440000 1631.920000 1599.920000 ;
+ RECT 1630.820000 1604.880000 1631.920000 1605.360000 ;
+ RECT 1643.630000 1599.440000 1644.630000 1599.920000 ;
+ RECT 1643.630000 1604.880000 1644.630000 1605.360000 ;
+ RECT 1585.820000 1626.640000 1586.920000 1627.120000 ;
+ RECT 1585.820000 1632.080000 1586.920000 1632.560000 ;
+ RECT 1585.820000 1637.520000 1586.920000 1638.000000 ;
+ RECT 1585.820000 1642.960000 1586.920000 1643.440000 ;
+ RECT 1585.820000 1599.440000 1586.920000 1599.920000 ;
+ RECT 1585.820000 1604.880000 1586.920000 1605.360000 ;
+ RECT 1585.820000 1610.320000 1586.920000 1610.800000 ;
+ RECT 1585.820000 1615.760000 1586.920000 1616.240000 ;
+ RECT 1585.820000 1621.200000 1586.920000 1621.680000 ;
+ RECT 1643.630000 1588.560000 1644.630000 1589.040000 ;
+ RECT 1643.630000 1594.000000 1644.630000 1594.480000 ;
+ RECT 1630.820000 1594.000000 1631.920000 1594.480000 ;
+ RECT 1630.820000 1588.560000 1631.920000 1589.040000 ;
+ RECT 1630.820000 1577.680000 1631.920000 1578.160000 ;
+ RECT 1630.820000 1583.120000 1631.920000 1583.600000 ;
+ RECT 1643.630000 1577.680000 1644.630000 1578.160000 ;
+ RECT 1643.630000 1583.120000 1644.630000 1583.600000 ;
+ RECT 1630.820000 1561.360000 1631.920000 1561.840000 ;
+ RECT 1630.820000 1566.800000 1631.920000 1567.280000 ;
+ RECT 1643.630000 1561.360000 1644.630000 1561.840000 ;
+ RECT 1643.630000 1566.800000 1644.630000 1567.280000 ;
+ RECT 1643.630000 1550.480000 1644.630000 1550.960000 ;
+ RECT 1643.630000 1555.920000 1644.630000 1556.400000 ;
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+ RECT 1540.820000 1458.000000 1541.920000 1458.480000 ;
+ RECT 1540.820000 1463.440000 1541.920000 1463.920000 ;
+ RECT 1540.820000 1468.880000 1541.920000 1469.360000 ;
+ RECT 1495.820000 1452.560000 1496.920000 1453.040000 ;
+ RECT 1495.820000 1458.000000 1496.920000 1458.480000 ;
+ RECT 1495.820000 1463.440000 1496.920000 1463.920000 ;
+ RECT 1495.820000 1468.880000 1496.920000 1469.360000 ;
+ RECT 1446.990000 1496.080000 1447.990000 1496.560000 ;
+ RECT 1450.655000 1496.080000 1451.920000 1496.560000 ;
+ RECT 1446.990000 1485.200000 1447.990000 1485.680000 ;
+ RECT 1450.655000 1485.200000 1451.920000 1485.680000 ;
+ RECT 1446.990000 1490.640000 1447.990000 1491.120000 ;
+ RECT 1450.655000 1490.640000 1451.920000 1491.120000 ;
+ RECT 1446.990000 1479.760000 1447.990000 1480.240000 ;
+ RECT 1450.655000 1479.760000 1451.920000 1480.240000 ;
+ RECT 1446.990000 1474.320000 1447.990000 1474.800000 ;
+ RECT 1450.655000 1474.320000 1451.920000 1474.800000 ;
+ RECT 1446.990000 1468.880000 1447.990000 1469.360000 ;
+ RECT 1450.655000 1468.880000 1451.920000 1469.360000 ;
+ RECT 1446.990000 1463.440000 1447.990000 1463.920000 ;
+ RECT 1450.655000 1463.440000 1451.920000 1463.920000 ;
+ RECT 1446.990000 1458.000000 1447.990000 1458.480000 ;
+ RECT 1450.655000 1458.000000 1451.920000 1458.480000 ;
+ RECT 1446.990000 1452.560000 1447.990000 1453.040000 ;
+ RECT 1450.655000 1452.560000 1451.920000 1453.040000 ;
+ RECT 1540.820000 1425.360000 1541.920000 1425.840000 ;
+ RECT 1540.820000 1430.800000 1541.920000 1431.280000 ;
+ RECT 1540.820000 1436.240000 1541.920000 1436.720000 ;
+ RECT 1540.820000 1441.680000 1541.920000 1442.160000 ;
+ RECT 1495.820000 1425.360000 1496.920000 1425.840000 ;
+ RECT 1495.820000 1430.800000 1496.920000 1431.280000 ;
+ RECT 1495.820000 1436.240000 1496.920000 1436.720000 ;
+ RECT 1495.820000 1441.680000 1496.920000 1442.160000 ;
+ RECT 1540.820000 1398.160000 1541.920000 1398.640000 ;
+ RECT 1540.820000 1403.600000 1541.920000 1404.080000 ;
+ RECT 1540.820000 1409.040000 1541.920000 1409.520000 ;
+ RECT 1540.820000 1414.480000 1541.920000 1414.960000 ;
+ RECT 1540.820000 1419.920000 1541.920000 1420.400000 ;
+ RECT 1495.820000 1398.160000 1496.920000 1398.640000 ;
+ RECT 1495.820000 1403.600000 1496.920000 1404.080000 ;
+ RECT 1495.820000 1409.040000 1496.920000 1409.520000 ;
+ RECT 1495.820000 1414.480000 1496.920000 1414.960000 ;
+ RECT 1495.820000 1419.920000 1496.920000 1420.400000 ;
+ RECT 1446.990000 1441.680000 1447.990000 1442.160000 ;
+ RECT 1450.655000 1441.680000 1451.920000 1442.160000 ;
+ RECT 1446.990000 1436.240000 1447.990000 1436.720000 ;
+ RECT 1450.655000 1436.240000 1451.920000 1436.720000 ;
+ RECT 1446.990000 1430.800000 1447.990000 1431.280000 ;
+ RECT 1450.655000 1430.800000 1451.920000 1431.280000 ;
+ RECT 1446.990000 1425.360000 1447.990000 1425.840000 ;
+ RECT 1450.655000 1425.360000 1451.920000 1425.840000 ;
+ RECT 1446.990000 1419.920000 1447.990000 1420.400000 ;
+ RECT 1450.655000 1419.920000 1451.920000 1420.400000 ;
+ RECT 1446.990000 1414.480000 1447.990000 1414.960000 ;
+ RECT 1450.655000 1414.480000 1451.920000 1414.960000 ;
+ RECT 1446.990000 1403.600000 1447.990000 1404.080000 ;
+ RECT 1450.655000 1403.600000 1451.920000 1404.080000 ;
+ RECT 1446.990000 1409.040000 1447.990000 1409.520000 ;
+ RECT 1450.655000 1409.040000 1451.920000 1409.520000 ;
+ RECT 1446.990000 1398.160000 1447.990000 1398.640000 ;
+ RECT 1450.655000 1398.160000 1451.920000 1398.640000 ;
+ RECT 1540.820000 1376.400000 1541.920000 1376.880000 ;
+ RECT 1540.820000 1381.840000 1541.920000 1382.320000 ;
+ RECT 1540.820000 1387.280000 1541.920000 1387.760000 ;
+ RECT 1540.820000 1392.720000 1541.920000 1393.200000 ;
+ RECT 1495.820000 1376.400000 1496.920000 1376.880000 ;
+ RECT 1495.820000 1381.840000 1496.920000 1382.320000 ;
+ RECT 1495.820000 1387.280000 1496.920000 1387.760000 ;
+ RECT 1495.820000 1392.720000 1496.920000 1393.200000 ;
+ RECT 1540.820000 1354.640000 1541.920000 1355.120000 ;
+ RECT 1540.820000 1360.080000 1541.920000 1360.560000 ;
+ RECT 1540.820000 1365.520000 1541.920000 1366.000000 ;
+ RECT 1540.820000 1370.960000 1541.920000 1371.440000 ;
+ RECT 1495.820000 1354.640000 1496.920000 1355.120000 ;
+ RECT 1495.820000 1360.080000 1496.920000 1360.560000 ;
+ RECT 1495.820000 1365.520000 1496.920000 1366.000000 ;
+ RECT 1495.820000 1370.960000 1496.920000 1371.440000 ;
+ RECT 1446.990000 1392.720000 1447.990000 1393.200000 ;
+ RECT 1450.655000 1392.720000 1451.920000 1393.200000 ;
+ RECT 1446.990000 1387.280000 1447.990000 1387.760000 ;
+ RECT 1450.655000 1387.280000 1451.920000 1387.760000 ;
+ RECT 1446.990000 1381.840000 1447.990000 1382.320000 ;
+ RECT 1450.655000 1381.840000 1451.920000 1382.320000 ;
+ RECT 1446.990000 1376.400000 1447.990000 1376.880000 ;
+ RECT 1450.655000 1376.400000 1451.920000 1376.880000 ;
+ RECT 1446.990000 1370.960000 1447.990000 1371.440000 ;
+ RECT 1450.655000 1370.960000 1451.920000 1371.440000 ;
+ RECT 1446.990000 1360.080000 1447.990000 1360.560000 ;
+ RECT 1450.655000 1360.080000 1451.920000 1360.560000 ;
+ RECT 1446.990000 1365.520000 1447.990000 1366.000000 ;
+ RECT 1450.655000 1365.520000 1451.920000 1366.000000 ;
+ RECT 1446.990000 1354.640000 1447.990000 1355.120000 ;
+ RECT 1450.655000 1354.640000 1451.920000 1355.120000 ;
+ RECT 1540.820000 1447.120000 1541.920000 1447.600000 ;
+ RECT 1495.820000 1447.120000 1496.920000 1447.600000 ;
+ RECT 1446.990000 1447.120000 1447.990000 1447.600000 ;
+ RECT 1450.655000 1447.120000 1451.920000 1447.600000 ;
+ RECT 1445.760000 1744.650000 1645.860000 1745.650000 ;
+ RECT 1445.760000 1348.310000 1645.860000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 1347.060000 1447.990000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1446.990000 1746.580000 1447.990000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 1347.060000 1644.630000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1643.630000 1746.580000 1644.630000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 1348.310000 1446.760000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 1348.310000 1645.860000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 1744.650000 1446.760000 1745.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 1744.650000 1645.860000 1745.650000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 3373.560000 1657.020000 3374.040000 ;
+ RECT 1655.755000 3368.120000 1657.020000 3368.600000 ;
+ RECT 1655.755000 3362.680000 1657.020000 3363.160000 ;
+ RECT 1655.755000 3357.240000 1657.020000 3357.720000 ;
+ RECT 1652.090000 3349.660000 1653.090000 3379.920000 ;
+ RECT 1848.730000 3349.660000 1849.730000 3379.920000 ;
+ RECT 1655.920000 3350.910000 1657.020000 3378.160000 ;
+ RECT 1700.920000 3350.910000 1702.020000 3378.160000 ;
+ RECT 1745.920000 3350.910000 1747.020000 3378.160000 ;
+ RECT 1790.920000 3350.910000 1792.020000 3378.160000 ;
+ RECT 1835.920000 3350.910000 1837.020000 3378.160000 ;
+ LAYER met3 ;
+ RECT 1848.730000 3373.560000 1849.730000 3374.040000 ;
+ RECT 1848.730000 3368.120000 1849.730000 3368.600000 ;
+ RECT 1835.920000 3373.560000 1837.020000 3374.040000 ;
+ RECT 1835.920000 3368.120000 1837.020000 3368.600000 ;
+ RECT 1790.920000 3368.120000 1792.020000 3368.600000 ;
+ RECT 1790.920000 3373.560000 1792.020000 3374.040000 ;
+ RECT 1745.920000 3368.120000 1747.020000 3368.600000 ;
+ RECT 1700.920000 3368.120000 1702.020000 3368.600000 ;
+ RECT 1745.920000 3373.560000 1747.020000 3374.040000 ;
+ RECT 1700.920000 3373.560000 1702.020000 3374.040000 ;
+ RECT 1655.755000 3373.560000 1657.020000 3374.040000 ;
+ RECT 1652.090000 3373.560000 1653.090000 3374.040000 ;
+ RECT 1655.755000 3368.120000 1657.020000 3368.600000 ;
+ RECT 1652.090000 3368.120000 1653.090000 3368.600000 ;
+ RECT 1848.730000 3362.680000 1849.730000 3363.160000 ;
+ RECT 1848.730000 3357.240000 1849.730000 3357.720000 ;
+ RECT 1835.920000 3362.680000 1837.020000 3363.160000 ;
+ RECT 1835.920000 3357.240000 1837.020000 3357.720000 ;
+ RECT 1790.920000 3357.240000 1792.020000 3357.720000 ;
+ RECT 1790.920000 3362.680000 1792.020000 3363.160000 ;
+ RECT 1745.920000 3357.240000 1747.020000 3357.720000 ;
+ RECT 1700.920000 3357.240000 1702.020000 3357.720000 ;
+ RECT 1745.920000 3362.680000 1747.020000 3363.160000 ;
+ RECT 1700.920000 3362.680000 1702.020000 3363.160000 ;
+ RECT 1655.755000 3362.680000 1657.020000 3363.160000 ;
+ RECT 1652.090000 3362.680000 1653.090000 3363.160000 ;
+ RECT 1655.755000 3357.240000 1657.020000 3357.720000 ;
+ RECT 1652.090000 3357.240000 1653.090000 3357.720000 ;
+ RECT 1650.860000 3377.160000 1850.960000 3378.160000 ;
+ RECT 1650.860000 3350.910000 1850.960000 3351.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 3349.660000 1653.090000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 3378.920000 1653.090000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 3349.660000 1849.730000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 3378.920000 1849.730000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 3350.910000 1651.860000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 3350.910000 1850.960000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 3377.160000 1651.860000 3378.160000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 3377.160000 1850.960000 3378.160000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 1539.600000 1657.020000 1540.080000 ;
+ RECT 1655.755000 1528.720000 1657.020000 1529.200000 ;
+ RECT 1655.755000 1534.160000 1657.020000 1534.640000 ;
+ RECT 1655.755000 1523.280000 1657.020000 1523.760000 ;
+ RECT 1655.755000 1517.840000 1657.020000 1518.320000 ;
+ RECT 1655.755000 1512.400000 1657.020000 1512.880000 ;
+ RECT 1655.755000 1506.960000 1657.020000 1507.440000 ;
+ RECT 1655.755000 1501.520000 1657.020000 1502.000000 ;
+ RECT 1655.755000 1496.080000 1657.020000 1496.560000 ;
+ RECT 1655.755000 1485.200000 1657.020000 1485.680000 ;
+ RECT 1655.755000 1490.640000 1657.020000 1491.120000 ;
+ RECT 1655.755000 1479.760000 1657.020000 1480.240000 ;
+ RECT 1655.755000 1474.320000 1657.020000 1474.800000 ;
+ RECT 1655.755000 1468.880000 1657.020000 1469.360000 ;
+ RECT 1655.755000 1463.440000 1657.020000 1463.920000 ;
+ RECT 1655.755000 1458.000000 1657.020000 1458.480000 ;
+ RECT 1655.755000 1452.560000 1657.020000 1453.040000 ;
+ RECT 1655.755000 1441.680000 1657.020000 1442.160000 ;
+ RECT 1655.755000 1436.240000 1657.020000 1436.720000 ;
+ RECT 1655.755000 1430.800000 1657.020000 1431.280000 ;
+ RECT 1655.755000 1425.360000 1657.020000 1425.840000 ;
+ RECT 1655.755000 1419.920000 1657.020000 1420.400000 ;
+ RECT 1655.755000 1414.480000 1657.020000 1414.960000 ;
+ RECT 1655.755000 1403.600000 1657.020000 1404.080000 ;
+ RECT 1655.755000 1409.040000 1657.020000 1409.520000 ;
+ RECT 1655.755000 1398.160000 1657.020000 1398.640000 ;
+ RECT 1655.755000 1392.720000 1657.020000 1393.200000 ;
+ RECT 1655.755000 1387.280000 1657.020000 1387.760000 ;
+ RECT 1655.755000 1381.840000 1657.020000 1382.320000 ;
+ RECT 1655.755000 1376.400000 1657.020000 1376.880000 ;
+ RECT 1655.755000 1370.960000 1657.020000 1371.440000 ;
+ RECT 1655.755000 1360.080000 1657.020000 1360.560000 ;
+ RECT 1655.755000 1365.520000 1657.020000 1366.000000 ;
+ RECT 1655.755000 1354.640000 1657.020000 1355.120000 ;
+ RECT 1655.755000 1447.120000 1657.020000 1447.600000 ;
+ RECT 1835.920000 1348.310000 1837.020000 1544.880000 ;
+ RECT 1790.920000 1348.310000 1792.020000 1544.880000 ;
+ RECT 1848.730000 1347.060000 1849.730000 1547.320000 ;
+ RECT 1745.920000 1348.310000 1747.020000 1544.880000 ;
+ RECT 1700.920000 1348.310000 1702.020000 1544.880000 ;
+ RECT 1655.920000 1348.310000 1657.020000 1544.880000 ;
+ RECT 1652.090000 1347.060000 1653.090000 1547.320000 ;
+ LAYER met3 ;
+ RECT 1835.920000 1539.600000 1837.020000 1540.080000 ;
+ RECT 1848.730000 1539.600000 1849.730000 1540.080000 ;
+ RECT 1848.730000 1528.720000 1849.730000 1529.200000 ;
+ RECT 1848.730000 1523.280000 1849.730000 1523.760000 ;
+ RECT 1848.730000 1534.160000 1849.730000 1534.640000 ;
+ RECT 1835.920000 1534.160000 1837.020000 1534.640000 ;
+ RECT 1835.920000 1528.720000 1837.020000 1529.200000 ;
+ RECT 1835.920000 1523.280000 1837.020000 1523.760000 ;
+ RECT 1835.920000 1512.400000 1837.020000 1512.880000 ;
+ RECT 1835.920000 1517.840000 1837.020000 1518.320000 ;
+ RECT 1848.730000 1512.400000 1849.730000 1512.880000 ;
+ RECT 1848.730000 1517.840000 1849.730000 1518.320000 ;
+ RECT 1835.920000 1501.520000 1837.020000 1502.000000 ;
+ RECT 1835.920000 1506.960000 1837.020000 1507.440000 ;
+ RECT 1848.730000 1501.520000 1849.730000 1502.000000 ;
+ RECT 1848.730000 1506.960000 1849.730000 1507.440000 ;
+ RECT 1790.920000 1523.280000 1792.020000 1523.760000 ;
+ RECT 1790.920000 1528.720000 1792.020000 1529.200000 ;
+ RECT 1790.920000 1534.160000 1792.020000 1534.640000 ;
+ RECT 1790.920000 1539.600000 1792.020000 1540.080000 ;
+ RECT 1790.920000 1506.960000 1792.020000 1507.440000 ;
+ RECT 1790.920000 1501.520000 1792.020000 1502.000000 ;
+ RECT 1790.920000 1512.400000 1792.020000 1512.880000 ;
+ RECT 1790.920000 1517.840000 1792.020000 1518.320000 ;
+ RECT 1848.730000 1490.640000 1849.730000 1491.120000 ;
+ RECT 1848.730000 1485.200000 1849.730000 1485.680000 ;
+ RECT 1848.730000 1496.080000 1849.730000 1496.560000 ;
+ RECT 1835.920000 1496.080000 1837.020000 1496.560000 ;
+ RECT 1835.920000 1490.640000 1837.020000 1491.120000 ;
+ RECT 1835.920000 1485.200000 1837.020000 1485.680000 ;
+ RECT 1835.920000 1474.320000 1837.020000 1474.800000 ;
+ RECT 1835.920000 1479.760000 1837.020000 1480.240000 ;
+ RECT 1848.730000 1474.320000 1849.730000 1474.800000 ;
+ RECT 1848.730000 1479.760000 1849.730000 1480.240000 ;
+ RECT 1848.730000 1463.440000 1849.730000 1463.920000 ;
+ RECT 1848.730000 1468.880000 1849.730000 1469.360000 ;
+ RECT 1835.920000 1468.880000 1837.020000 1469.360000 ;
+ RECT 1835.920000 1463.440000 1837.020000 1463.920000 ;
+ RECT 1835.920000 1452.560000 1837.020000 1453.040000 ;
+ RECT 1835.920000 1458.000000 1837.020000 1458.480000 ;
+ RECT 1848.730000 1452.560000 1849.730000 1453.040000 ;
+ RECT 1848.730000 1458.000000 1849.730000 1458.480000 ;
+ RECT 1790.920000 1474.320000 1792.020000 1474.800000 ;
+ RECT 1790.920000 1479.760000 1792.020000 1480.240000 ;
+ RECT 1790.920000 1485.200000 1792.020000 1485.680000 ;
+ RECT 1790.920000 1490.640000 1792.020000 1491.120000 ;
+ RECT 1790.920000 1496.080000 1792.020000 1496.560000 ;
+ RECT 1790.920000 1452.560000 1792.020000 1453.040000 ;
+ RECT 1790.920000 1458.000000 1792.020000 1458.480000 ;
+ RECT 1790.920000 1463.440000 1792.020000 1463.920000 ;
+ RECT 1790.920000 1468.880000 1792.020000 1469.360000 ;
+ RECT 1745.920000 1528.720000 1747.020000 1529.200000 ;
+ RECT 1745.920000 1523.280000 1747.020000 1523.760000 ;
+ RECT 1745.920000 1534.160000 1747.020000 1534.640000 ;
+ RECT 1745.920000 1539.600000 1747.020000 1540.080000 ;
+ RECT 1700.920000 1523.280000 1702.020000 1523.760000 ;
+ RECT 1700.920000 1528.720000 1702.020000 1529.200000 ;
+ RECT 1700.920000 1534.160000 1702.020000 1534.640000 ;
+ RECT 1700.920000 1539.600000 1702.020000 1540.080000 ;
+ RECT 1745.920000 1501.520000 1747.020000 1502.000000 ;
+ RECT 1745.920000 1506.960000 1747.020000 1507.440000 ;
+ RECT 1745.920000 1512.400000 1747.020000 1512.880000 ;
+ RECT 1745.920000 1517.840000 1747.020000 1518.320000 ;
+ RECT 1700.920000 1501.520000 1702.020000 1502.000000 ;
+ RECT 1700.920000 1506.960000 1702.020000 1507.440000 ;
+ RECT 1700.920000 1512.400000 1702.020000 1512.880000 ;
+ RECT 1700.920000 1517.840000 1702.020000 1518.320000 ;
+ RECT 1652.090000 1539.600000 1653.090000 1540.080000 ;
+ RECT 1655.755000 1539.600000 1657.020000 1540.080000 ;
+ RECT 1652.090000 1528.720000 1653.090000 1529.200000 ;
+ RECT 1655.755000 1528.720000 1657.020000 1529.200000 ;
+ RECT 1652.090000 1534.160000 1653.090000 1534.640000 ;
+ RECT 1655.755000 1534.160000 1657.020000 1534.640000 ;
+ RECT 1652.090000 1523.280000 1653.090000 1523.760000 ;
+ RECT 1655.755000 1523.280000 1657.020000 1523.760000 ;
+ RECT 1652.090000 1517.840000 1653.090000 1518.320000 ;
+ RECT 1655.755000 1517.840000 1657.020000 1518.320000 ;
+ RECT 1652.090000 1512.400000 1653.090000 1512.880000 ;
+ RECT 1655.755000 1512.400000 1657.020000 1512.880000 ;
+ RECT 1652.090000 1506.960000 1653.090000 1507.440000 ;
+ RECT 1655.755000 1506.960000 1657.020000 1507.440000 ;
+ RECT 1652.090000 1501.520000 1653.090000 1502.000000 ;
+ RECT 1655.755000 1501.520000 1657.020000 1502.000000 ;
+ RECT 1745.920000 1474.320000 1747.020000 1474.800000 ;
+ RECT 1745.920000 1479.760000 1747.020000 1480.240000 ;
+ RECT 1745.920000 1485.200000 1747.020000 1485.680000 ;
+ RECT 1745.920000 1490.640000 1747.020000 1491.120000 ;
+ RECT 1745.920000 1496.080000 1747.020000 1496.560000 ;
+ RECT 1700.920000 1474.320000 1702.020000 1474.800000 ;
+ RECT 1700.920000 1479.760000 1702.020000 1480.240000 ;
+ RECT 1700.920000 1485.200000 1702.020000 1485.680000 ;
+ RECT 1700.920000 1490.640000 1702.020000 1491.120000 ;
+ RECT 1700.920000 1496.080000 1702.020000 1496.560000 ;
+ RECT 1745.920000 1452.560000 1747.020000 1453.040000 ;
+ RECT 1745.920000 1458.000000 1747.020000 1458.480000 ;
+ RECT 1745.920000 1463.440000 1747.020000 1463.920000 ;
+ RECT 1745.920000 1468.880000 1747.020000 1469.360000 ;
+ RECT 1700.920000 1452.560000 1702.020000 1453.040000 ;
+ RECT 1700.920000 1458.000000 1702.020000 1458.480000 ;
+ RECT 1700.920000 1463.440000 1702.020000 1463.920000 ;
+ RECT 1700.920000 1468.880000 1702.020000 1469.360000 ;
+ RECT 1652.090000 1496.080000 1653.090000 1496.560000 ;
+ RECT 1655.755000 1496.080000 1657.020000 1496.560000 ;
+ RECT 1652.090000 1485.200000 1653.090000 1485.680000 ;
+ RECT 1655.755000 1485.200000 1657.020000 1485.680000 ;
+ RECT 1652.090000 1490.640000 1653.090000 1491.120000 ;
+ RECT 1655.755000 1490.640000 1657.020000 1491.120000 ;
+ RECT 1652.090000 1479.760000 1653.090000 1480.240000 ;
+ RECT 1655.755000 1479.760000 1657.020000 1480.240000 ;
+ RECT 1652.090000 1474.320000 1653.090000 1474.800000 ;
+ RECT 1655.755000 1474.320000 1657.020000 1474.800000 ;
+ RECT 1652.090000 1468.880000 1653.090000 1469.360000 ;
+ RECT 1655.755000 1468.880000 1657.020000 1469.360000 ;
+ RECT 1652.090000 1463.440000 1653.090000 1463.920000 ;
+ RECT 1655.755000 1463.440000 1657.020000 1463.920000 ;
+ RECT 1652.090000 1458.000000 1653.090000 1458.480000 ;
+ RECT 1655.755000 1458.000000 1657.020000 1458.480000 ;
+ RECT 1652.090000 1452.560000 1653.090000 1453.040000 ;
+ RECT 1655.755000 1452.560000 1657.020000 1453.040000 ;
+ RECT 1835.920000 1436.240000 1837.020000 1436.720000 ;
+ RECT 1835.920000 1441.680000 1837.020000 1442.160000 ;
+ RECT 1848.730000 1436.240000 1849.730000 1436.720000 ;
+ RECT 1848.730000 1441.680000 1849.730000 1442.160000 ;
+ RECT 1848.730000 1425.360000 1849.730000 1425.840000 ;
+ RECT 1848.730000 1430.800000 1849.730000 1431.280000 ;
+ RECT 1835.920000 1430.800000 1837.020000 1431.280000 ;
+ RECT 1835.920000 1425.360000 1837.020000 1425.840000 ;
+ RECT 1835.920000 1414.480000 1837.020000 1414.960000 ;
+ RECT 1835.920000 1419.920000 1837.020000 1420.400000 ;
+ RECT 1848.730000 1414.480000 1849.730000 1414.960000 ;
+ RECT 1848.730000 1419.920000 1849.730000 1420.400000 ;
+ RECT 1848.730000 1403.600000 1849.730000 1404.080000 ;
+ RECT 1848.730000 1398.160000 1849.730000 1398.640000 ;
+ RECT 1848.730000 1409.040000 1849.730000 1409.520000 ;
+ RECT 1835.920000 1409.040000 1837.020000 1409.520000 ;
+ RECT 1835.920000 1403.600000 1837.020000 1404.080000 ;
+ RECT 1835.920000 1398.160000 1837.020000 1398.640000 ;
+ RECT 1790.920000 1425.360000 1792.020000 1425.840000 ;
+ RECT 1790.920000 1430.800000 1792.020000 1431.280000 ;
+ RECT 1790.920000 1436.240000 1792.020000 1436.720000 ;
+ RECT 1790.920000 1441.680000 1792.020000 1442.160000 ;
+ RECT 1790.920000 1398.160000 1792.020000 1398.640000 ;
+ RECT 1790.920000 1403.600000 1792.020000 1404.080000 ;
+ RECT 1790.920000 1409.040000 1792.020000 1409.520000 ;
+ RECT 1790.920000 1414.480000 1792.020000 1414.960000 ;
+ RECT 1790.920000 1419.920000 1792.020000 1420.400000 ;
+ RECT 1835.920000 1387.280000 1837.020000 1387.760000 ;
+ RECT 1835.920000 1392.720000 1837.020000 1393.200000 ;
+ RECT 1848.730000 1387.280000 1849.730000 1387.760000 ;
+ RECT 1848.730000 1392.720000 1849.730000 1393.200000 ;
+ RECT 1835.920000 1376.400000 1837.020000 1376.880000 ;
+ RECT 1835.920000 1381.840000 1837.020000 1382.320000 ;
+ RECT 1848.730000 1376.400000 1849.730000 1376.880000 ;
+ RECT 1848.730000 1381.840000 1849.730000 1382.320000 ;
+ RECT 1848.730000 1365.520000 1849.730000 1366.000000 ;
+ RECT 1848.730000 1360.080000 1849.730000 1360.560000 ;
+ RECT 1848.730000 1370.960000 1849.730000 1371.440000 ;
+ RECT 1835.920000 1370.960000 1837.020000 1371.440000 ;
+ RECT 1835.920000 1365.520000 1837.020000 1366.000000 ;
+ RECT 1835.920000 1360.080000 1837.020000 1360.560000 ;
+ RECT 1835.920000 1354.640000 1837.020000 1355.120000 ;
+ RECT 1848.730000 1354.640000 1849.730000 1355.120000 ;
+ RECT 1790.920000 1376.400000 1792.020000 1376.880000 ;
+ RECT 1790.920000 1381.840000 1792.020000 1382.320000 ;
+ RECT 1790.920000 1387.280000 1792.020000 1387.760000 ;
+ RECT 1790.920000 1392.720000 1792.020000 1393.200000 ;
+ RECT 1790.920000 1354.640000 1792.020000 1355.120000 ;
+ RECT 1790.920000 1360.080000 1792.020000 1360.560000 ;
+ RECT 1790.920000 1365.520000 1792.020000 1366.000000 ;
+ RECT 1790.920000 1370.960000 1792.020000 1371.440000 ;
+ RECT 1745.920000 1425.360000 1747.020000 1425.840000 ;
+ RECT 1745.920000 1430.800000 1747.020000 1431.280000 ;
+ RECT 1745.920000 1436.240000 1747.020000 1436.720000 ;
+ RECT 1745.920000 1441.680000 1747.020000 1442.160000 ;
+ RECT 1700.920000 1425.360000 1702.020000 1425.840000 ;
+ RECT 1700.920000 1430.800000 1702.020000 1431.280000 ;
+ RECT 1700.920000 1436.240000 1702.020000 1436.720000 ;
+ RECT 1700.920000 1441.680000 1702.020000 1442.160000 ;
+ RECT 1745.920000 1398.160000 1747.020000 1398.640000 ;
+ RECT 1745.920000 1403.600000 1747.020000 1404.080000 ;
+ RECT 1745.920000 1409.040000 1747.020000 1409.520000 ;
+ RECT 1745.920000 1414.480000 1747.020000 1414.960000 ;
+ RECT 1745.920000 1419.920000 1747.020000 1420.400000 ;
+ RECT 1700.920000 1398.160000 1702.020000 1398.640000 ;
+ RECT 1700.920000 1403.600000 1702.020000 1404.080000 ;
+ RECT 1700.920000 1409.040000 1702.020000 1409.520000 ;
+ RECT 1700.920000 1414.480000 1702.020000 1414.960000 ;
+ RECT 1700.920000 1419.920000 1702.020000 1420.400000 ;
+ RECT 1652.090000 1441.680000 1653.090000 1442.160000 ;
+ RECT 1655.755000 1441.680000 1657.020000 1442.160000 ;
+ RECT 1652.090000 1436.240000 1653.090000 1436.720000 ;
+ RECT 1655.755000 1436.240000 1657.020000 1436.720000 ;
+ RECT 1652.090000 1430.800000 1653.090000 1431.280000 ;
+ RECT 1655.755000 1430.800000 1657.020000 1431.280000 ;
+ RECT 1652.090000 1425.360000 1653.090000 1425.840000 ;
+ RECT 1655.755000 1425.360000 1657.020000 1425.840000 ;
+ RECT 1652.090000 1419.920000 1653.090000 1420.400000 ;
+ RECT 1655.755000 1419.920000 1657.020000 1420.400000 ;
+ RECT 1652.090000 1414.480000 1653.090000 1414.960000 ;
+ RECT 1655.755000 1414.480000 1657.020000 1414.960000 ;
+ RECT 1652.090000 1403.600000 1653.090000 1404.080000 ;
+ RECT 1655.755000 1403.600000 1657.020000 1404.080000 ;
+ RECT 1652.090000 1409.040000 1653.090000 1409.520000 ;
+ RECT 1655.755000 1409.040000 1657.020000 1409.520000 ;
+ RECT 1652.090000 1398.160000 1653.090000 1398.640000 ;
+ RECT 1655.755000 1398.160000 1657.020000 1398.640000 ;
+ RECT 1745.920000 1376.400000 1747.020000 1376.880000 ;
+ RECT 1745.920000 1381.840000 1747.020000 1382.320000 ;
+ RECT 1745.920000 1387.280000 1747.020000 1387.760000 ;
+ RECT 1745.920000 1392.720000 1747.020000 1393.200000 ;
+ RECT 1700.920000 1376.400000 1702.020000 1376.880000 ;
+ RECT 1700.920000 1381.840000 1702.020000 1382.320000 ;
+ RECT 1700.920000 1387.280000 1702.020000 1387.760000 ;
+ RECT 1700.920000 1392.720000 1702.020000 1393.200000 ;
+ RECT 1745.920000 1354.640000 1747.020000 1355.120000 ;
+ RECT 1745.920000 1360.080000 1747.020000 1360.560000 ;
+ RECT 1745.920000 1365.520000 1747.020000 1366.000000 ;
+ RECT 1745.920000 1370.960000 1747.020000 1371.440000 ;
+ RECT 1700.920000 1354.640000 1702.020000 1355.120000 ;
+ RECT 1700.920000 1360.080000 1702.020000 1360.560000 ;
+ RECT 1700.920000 1365.520000 1702.020000 1366.000000 ;
+ RECT 1700.920000 1370.960000 1702.020000 1371.440000 ;
+ RECT 1652.090000 1392.720000 1653.090000 1393.200000 ;
+ RECT 1655.755000 1392.720000 1657.020000 1393.200000 ;
+ RECT 1652.090000 1387.280000 1653.090000 1387.760000 ;
+ RECT 1655.755000 1387.280000 1657.020000 1387.760000 ;
+ RECT 1652.090000 1381.840000 1653.090000 1382.320000 ;
+ RECT 1655.755000 1381.840000 1657.020000 1382.320000 ;
+ RECT 1652.090000 1376.400000 1653.090000 1376.880000 ;
+ RECT 1655.755000 1376.400000 1657.020000 1376.880000 ;
+ RECT 1652.090000 1370.960000 1653.090000 1371.440000 ;
+ RECT 1655.755000 1370.960000 1657.020000 1371.440000 ;
+ RECT 1652.090000 1360.080000 1653.090000 1360.560000 ;
+ RECT 1655.755000 1360.080000 1657.020000 1360.560000 ;
+ RECT 1652.090000 1365.520000 1653.090000 1366.000000 ;
+ RECT 1655.755000 1365.520000 1657.020000 1366.000000 ;
+ RECT 1652.090000 1354.640000 1653.090000 1355.120000 ;
+ RECT 1655.755000 1354.640000 1657.020000 1355.120000 ;
+ RECT 1790.920000 1447.120000 1792.020000 1447.600000 ;
+ RECT 1835.920000 1447.120000 1837.020000 1447.600000 ;
+ RECT 1848.730000 1447.120000 1849.730000 1447.600000 ;
+ RECT 1700.920000 1447.120000 1702.020000 1447.600000 ;
+ RECT 1745.920000 1447.120000 1747.020000 1447.600000 ;
+ RECT 1652.090000 1447.120000 1653.090000 1447.600000 ;
+ RECT 1655.755000 1447.120000 1657.020000 1447.600000 ;
+ RECT 1650.860000 1543.880000 1850.960000 1544.880000 ;
+ RECT 1650.860000 1348.310000 1850.960000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 1347.060000 1653.090000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 1546.320000 1653.090000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 1347.060000 1849.730000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 1546.320000 1849.730000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1348.310000 1651.860000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1348.310000 1850.960000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1543.880000 1651.860000 1544.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1543.880000 1850.960000 1544.880000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 1339.340000 1657.020000 1339.820000 ;
+ RECT 1655.755000 1328.460000 1657.020000 1328.940000 ;
+ RECT 1655.755000 1333.900000 1657.020000 1334.380000 ;
+ RECT 1655.755000 1323.020000 1657.020000 1323.500000 ;
+ RECT 1655.755000 1317.580000 1657.020000 1318.060000 ;
+ RECT 1655.755000 1312.140000 1657.020000 1312.620000 ;
+ RECT 1655.755000 1306.700000 1657.020000 1307.180000 ;
+ RECT 1655.755000 1301.260000 1657.020000 1301.740000 ;
+ RECT 1655.755000 1295.820000 1657.020000 1296.300000 ;
+ RECT 1655.755000 1284.940000 1657.020000 1285.420000 ;
+ RECT 1655.755000 1290.380000 1657.020000 1290.860000 ;
+ RECT 1655.755000 1279.500000 1657.020000 1279.980000 ;
+ RECT 1655.755000 1274.060000 1657.020000 1274.540000 ;
+ RECT 1655.755000 1268.620000 1657.020000 1269.100000 ;
+ RECT 1655.755000 1263.180000 1657.020000 1263.660000 ;
+ RECT 1655.755000 1257.740000 1657.020000 1258.220000 ;
+ RECT 1655.755000 1252.300000 1657.020000 1252.780000 ;
+ RECT 1655.755000 1241.420000 1657.020000 1241.900000 ;
+ RECT 1655.755000 1235.980000 1657.020000 1236.460000 ;
+ RECT 1655.755000 1230.540000 1657.020000 1231.020000 ;
+ RECT 1655.755000 1225.100000 1657.020000 1225.580000 ;
+ RECT 1655.755000 1219.660000 1657.020000 1220.140000 ;
+ RECT 1655.755000 1214.220000 1657.020000 1214.700000 ;
+ RECT 1655.755000 1203.340000 1657.020000 1203.820000 ;
+ RECT 1655.755000 1208.780000 1657.020000 1209.260000 ;
+ RECT 1655.755000 1197.900000 1657.020000 1198.380000 ;
+ RECT 1655.755000 1192.460000 1657.020000 1192.940000 ;
+ RECT 1655.755000 1187.020000 1657.020000 1187.500000 ;
+ RECT 1655.755000 1181.580000 1657.020000 1182.060000 ;
+ RECT 1655.755000 1176.140000 1657.020000 1176.620000 ;
+ RECT 1655.755000 1170.700000 1657.020000 1171.180000 ;
+ RECT 1655.755000 1159.820000 1657.020000 1160.300000 ;
+ RECT 1655.755000 1165.260000 1657.020000 1165.740000 ;
+ RECT 1655.755000 1154.380000 1657.020000 1154.860000 ;
+ RECT 1655.755000 1246.860000 1657.020000 1247.340000 ;
+ RECT 1835.920000 1148.050000 1837.020000 1344.620000 ;
+ RECT 1790.920000 1148.050000 1792.020000 1344.620000 ;
+ RECT 1848.730000 1146.800000 1849.730000 1347.060000 ;
+ RECT 1745.920000 1148.050000 1747.020000 1344.620000 ;
+ RECT 1700.920000 1148.050000 1702.020000 1344.620000 ;
+ RECT 1655.920000 1148.050000 1657.020000 1344.620000 ;
+ RECT 1652.090000 1146.800000 1653.090000 1347.060000 ;
+ LAYER met3 ;
+ RECT 1835.920000 1339.340000 1837.020000 1339.820000 ;
+ RECT 1848.730000 1339.340000 1849.730000 1339.820000 ;
+ RECT 1848.730000 1328.460000 1849.730000 1328.940000 ;
+ RECT 1848.730000 1323.020000 1849.730000 1323.500000 ;
+ RECT 1848.730000 1333.900000 1849.730000 1334.380000 ;
+ RECT 1835.920000 1333.900000 1837.020000 1334.380000 ;
+ RECT 1835.920000 1328.460000 1837.020000 1328.940000 ;
+ RECT 1835.920000 1323.020000 1837.020000 1323.500000 ;
+ RECT 1835.920000 1312.140000 1837.020000 1312.620000 ;
+ RECT 1835.920000 1317.580000 1837.020000 1318.060000 ;
+ RECT 1848.730000 1312.140000 1849.730000 1312.620000 ;
+ RECT 1848.730000 1317.580000 1849.730000 1318.060000 ;
+ RECT 1835.920000 1301.260000 1837.020000 1301.740000 ;
+ RECT 1835.920000 1306.700000 1837.020000 1307.180000 ;
+ RECT 1848.730000 1301.260000 1849.730000 1301.740000 ;
+ RECT 1848.730000 1306.700000 1849.730000 1307.180000 ;
+ RECT 1790.920000 1323.020000 1792.020000 1323.500000 ;
+ RECT 1790.920000 1328.460000 1792.020000 1328.940000 ;
+ RECT 1790.920000 1333.900000 1792.020000 1334.380000 ;
+ RECT 1790.920000 1339.340000 1792.020000 1339.820000 ;
+ RECT 1790.920000 1306.700000 1792.020000 1307.180000 ;
+ RECT 1790.920000 1301.260000 1792.020000 1301.740000 ;
+ RECT 1790.920000 1312.140000 1792.020000 1312.620000 ;
+ RECT 1790.920000 1317.580000 1792.020000 1318.060000 ;
+ RECT 1848.730000 1290.380000 1849.730000 1290.860000 ;
+ RECT 1848.730000 1284.940000 1849.730000 1285.420000 ;
+ RECT 1848.730000 1295.820000 1849.730000 1296.300000 ;
+ RECT 1835.920000 1295.820000 1837.020000 1296.300000 ;
+ RECT 1835.920000 1290.380000 1837.020000 1290.860000 ;
+ RECT 1835.920000 1284.940000 1837.020000 1285.420000 ;
+ RECT 1835.920000 1274.060000 1837.020000 1274.540000 ;
+ RECT 1835.920000 1279.500000 1837.020000 1279.980000 ;
+ RECT 1848.730000 1274.060000 1849.730000 1274.540000 ;
+ RECT 1848.730000 1279.500000 1849.730000 1279.980000 ;
+ RECT 1848.730000 1263.180000 1849.730000 1263.660000 ;
+ RECT 1848.730000 1268.620000 1849.730000 1269.100000 ;
+ RECT 1835.920000 1268.620000 1837.020000 1269.100000 ;
+ RECT 1835.920000 1263.180000 1837.020000 1263.660000 ;
+ RECT 1835.920000 1252.300000 1837.020000 1252.780000 ;
+ RECT 1835.920000 1257.740000 1837.020000 1258.220000 ;
+ RECT 1848.730000 1252.300000 1849.730000 1252.780000 ;
+ RECT 1848.730000 1257.740000 1849.730000 1258.220000 ;
+ RECT 1790.920000 1274.060000 1792.020000 1274.540000 ;
+ RECT 1790.920000 1279.500000 1792.020000 1279.980000 ;
+ RECT 1790.920000 1284.940000 1792.020000 1285.420000 ;
+ RECT 1790.920000 1290.380000 1792.020000 1290.860000 ;
+ RECT 1790.920000 1295.820000 1792.020000 1296.300000 ;
+ RECT 1790.920000 1252.300000 1792.020000 1252.780000 ;
+ RECT 1790.920000 1257.740000 1792.020000 1258.220000 ;
+ RECT 1790.920000 1263.180000 1792.020000 1263.660000 ;
+ RECT 1790.920000 1268.620000 1792.020000 1269.100000 ;
+ RECT 1745.920000 1328.460000 1747.020000 1328.940000 ;
+ RECT 1745.920000 1323.020000 1747.020000 1323.500000 ;
+ RECT 1745.920000 1333.900000 1747.020000 1334.380000 ;
+ RECT 1745.920000 1339.340000 1747.020000 1339.820000 ;
+ RECT 1700.920000 1323.020000 1702.020000 1323.500000 ;
+ RECT 1700.920000 1328.460000 1702.020000 1328.940000 ;
+ RECT 1700.920000 1333.900000 1702.020000 1334.380000 ;
+ RECT 1700.920000 1339.340000 1702.020000 1339.820000 ;
+ RECT 1745.920000 1301.260000 1747.020000 1301.740000 ;
+ RECT 1745.920000 1306.700000 1747.020000 1307.180000 ;
+ RECT 1745.920000 1312.140000 1747.020000 1312.620000 ;
+ RECT 1745.920000 1317.580000 1747.020000 1318.060000 ;
+ RECT 1700.920000 1301.260000 1702.020000 1301.740000 ;
+ RECT 1700.920000 1306.700000 1702.020000 1307.180000 ;
+ RECT 1700.920000 1312.140000 1702.020000 1312.620000 ;
+ RECT 1700.920000 1317.580000 1702.020000 1318.060000 ;
+ RECT 1652.090000 1339.340000 1653.090000 1339.820000 ;
+ RECT 1655.755000 1339.340000 1657.020000 1339.820000 ;
+ RECT 1652.090000 1328.460000 1653.090000 1328.940000 ;
+ RECT 1655.755000 1328.460000 1657.020000 1328.940000 ;
+ RECT 1652.090000 1333.900000 1653.090000 1334.380000 ;
+ RECT 1655.755000 1333.900000 1657.020000 1334.380000 ;
+ RECT 1652.090000 1323.020000 1653.090000 1323.500000 ;
+ RECT 1655.755000 1323.020000 1657.020000 1323.500000 ;
+ RECT 1652.090000 1317.580000 1653.090000 1318.060000 ;
+ RECT 1655.755000 1317.580000 1657.020000 1318.060000 ;
+ RECT 1652.090000 1312.140000 1653.090000 1312.620000 ;
+ RECT 1655.755000 1312.140000 1657.020000 1312.620000 ;
+ RECT 1652.090000 1306.700000 1653.090000 1307.180000 ;
+ RECT 1655.755000 1306.700000 1657.020000 1307.180000 ;
+ RECT 1652.090000 1301.260000 1653.090000 1301.740000 ;
+ RECT 1655.755000 1301.260000 1657.020000 1301.740000 ;
+ RECT 1745.920000 1274.060000 1747.020000 1274.540000 ;
+ RECT 1745.920000 1279.500000 1747.020000 1279.980000 ;
+ RECT 1745.920000 1284.940000 1747.020000 1285.420000 ;
+ RECT 1745.920000 1290.380000 1747.020000 1290.860000 ;
+ RECT 1745.920000 1295.820000 1747.020000 1296.300000 ;
+ RECT 1700.920000 1274.060000 1702.020000 1274.540000 ;
+ RECT 1700.920000 1279.500000 1702.020000 1279.980000 ;
+ RECT 1700.920000 1284.940000 1702.020000 1285.420000 ;
+ RECT 1700.920000 1290.380000 1702.020000 1290.860000 ;
+ RECT 1700.920000 1295.820000 1702.020000 1296.300000 ;
+ RECT 1745.920000 1252.300000 1747.020000 1252.780000 ;
+ RECT 1745.920000 1257.740000 1747.020000 1258.220000 ;
+ RECT 1745.920000 1263.180000 1747.020000 1263.660000 ;
+ RECT 1745.920000 1268.620000 1747.020000 1269.100000 ;
+ RECT 1700.920000 1252.300000 1702.020000 1252.780000 ;
+ RECT 1700.920000 1257.740000 1702.020000 1258.220000 ;
+ RECT 1700.920000 1263.180000 1702.020000 1263.660000 ;
+ RECT 1700.920000 1268.620000 1702.020000 1269.100000 ;
+ RECT 1652.090000 1295.820000 1653.090000 1296.300000 ;
+ RECT 1655.755000 1295.820000 1657.020000 1296.300000 ;
+ RECT 1652.090000 1284.940000 1653.090000 1285.420000 ;
+ RECT 1655.755000 1284.940000 1657.020000 1285.420000 ;
+ RECT 1652.090000 1290.380000 1653.090000 1290.860000 ;
+ RECT 1655.755000 1290.380000 1657.020000 1290.860000 ;
+ RECT 1652.090000 1279.500000 1653.090000 1279.980000 ;
+ RECT 1655.755000 1279.500000 1657.020000 1279.980000 ;
+ RECT 1652.090000 1274.060000 1653.090000 1274.540000 ;
+ RECT 1655.755000 1274.060000 1657.020000 1274.540000 ;
+ RECT 1652.090000 1268.620000 1653.090000 1269.100000 ;
+ RECT 1655.755000 1268.620000 1657.020000 1269.100000 ;
+ RECT 1652.090000 1263.180000 1653.090000 1263.660000 ;
+ RECT 1655.755000 1263.180000 1657.020000 1263.660000 ;
+ RECT 1652.090000 1257.740000 1653.090000 1258.220000 ;
+ RECT 1655.755000 1257.740000 1657.020000 1258.220000 ;
+ RECT 1652.090000 1252.300000 1653.090000 1252.780000 ;
+ RECT 1655.755000 1252.300000 1657.020000 1252.780000 ;
+ RECT 1835.920000 1235.980000 1837.020000 1236.460000 ;
+ RECT 1835.920000 1241.420000 1837.020000 1241.900000 ;
+ RECT 1848.730000 1235.980000 1849.730000 1236.460000 ;
+ RECT 1848.730000 1241.420000 1849.730000 1241.900000 ;
+ RECT 1848.730000 1225.100000 1849.730000 1225.580000 ;
+ RECT 1848.730000 1230.540000 1849.730000 1231.020000 ;
+ RECT 1835.920000 1230.540000 1837.020000 1231.020000 ;
+ RECT 1835.920000 1225.100000 1837.020000 1225.580000 ;
+ RECT 1835.920000 1214.220000 1837.020000 1214.700000 ;
+ RECT 1835.920000 1219.660000 1837.020000 1220.140000 ;
+ RECT 1848.730000 1214.220000 1849.730000 1214.700000 ;
+ RECT 1848.730000 1219.660000 1849.730000 1220.140000 ;
+ RECT 1848.730000 1203.340000 1849.730000 1203.820000 ;
+ RECT 1848.730000 1197.900000 1849.730000 1198.380000 ;
+ RECT 1848.730000 1208.780000 1849.730000 1209.260000 ;
+ RECT 1835.920000 1208.780000 1837.020000 1209.260000 ;
+ RECT 1835.920000 1203.340000 1837.020000 1203.820000 ;
+ RECT 1835.920000 1197.900000 1837.020000 1198.380000 ;
+ RECT 1790.920000 1225.100000 1792.020000 1225.580000 ;
+ RECT 1790.920000 1230.540000 1792.020000 1231.020000 ;
+ RECT 1790.920000 1235.980000 1792.020000 1236.460000 ;
+ RECT 1790.920000 1241.420000 1792.020000 1241.900000 ;
+ RECT 1790.920000 1197.900000 1792.020000 1198.380000 ;
+ RECT 1790.920000 1203.340000 1792.020000 1203.820000 ;
+ RECT 1790.920000 1208.780000 1792.020000 1209.260000 ;
+ RECT 1790.920000 1214.220000 1792.020000 1214.700000 ;
+ RECT 1790.920000 1219.660000 1792.020000 1220.140000 ;
+ RECT 1835.920000 1187.020000 1837.020000 1187.500000 ;
+ RECT 1835.920000 1192.460000 1837.020000 1192.940000 ;
+ RECT 1848.730000 1187.020000 1849.730000 1187.500000 ;
+ RECT 1848.730000 1192.460000 1849.730000 1192.940000 ;
+ RECT 1835.920000 1176.140000 1837.020000 1176.620000 ;
+ RECT 1835.920000 1181.580000 1837.020000 1182.060000 ;
+ RECT 1848.730000 1176.140000 1849.730000 1176.620000 ;
+ RECT 1848.730000 1181.580000 1849.730000 1182.060000 ;
+ RECT 1848.730000 1165.260000 1849.730000 1165.740000 ;
+ RECT 1848.730000 1159.820000 1849.730000 1160.300000 ;
+ RECT 1848.730000 1170.700000 1849.730000 1171.180000 ;
+ RECT 1835.920000 1170.700000 1837.020000 1171.180000 ;
+ RECT 1835.920000 1165.260000 1837.020000 1165.740000 ;
+ RECT 1835.920000 1159.820000 1837.020000 1160.300000 ;
+ RECT 1835.920000 1154.380000 1837.020000 1154.860000 ;
+ RECT 1848.730000 1154.380000 1849.730000 1154.860000 ;
+ RECT 1790.920000 1176.140000 1792.020000 1176.620000 ;
+ RECT 1790.920000 1181.580000 1792.020000 1182.060000 ;
+ RECT 1790.920000 1187.020000 1792.020000 1187.500000 ;
+ RECT 1790.920000 1192.460000 1792.020000 1192.940000 ;
+ RECT 1790.920000 1154.380000 1792.020000 1154.860000 ;
+ RECT 1790.920000 1159.820000 1792.020000 1160.300000 ;
+ RECT 1790.920000 1165.260000 1792.020000 1165.740000 ;
+ RECT 1790.920000 1170.700000 1792.020000 1171.180000 ;
+ RECT 1745.920000 1225.100000 1747.020000 1225.580000 ;
+ RECT 1745.920000 1230.540000 1747.020000 1231.020000 ;
+ RECT 1745.920000 1235.980000 1747.020000 1236.460000 ;
+ RECT 1745.920000 1241.420000 1747.020000 1241.900000 ;
+ RECT 1700.920000 1225.100000 1702.020000 1225.580000 ;
+ RECT 1700.920000 1230.540000 1702.020000 1231.020000 ;
+ RECT 1700.920000 1235.980000 1702.020000 1236.460000 ;
+ RECT 1700.920000 1241.420000 1702.020000 1241.900000 ;
+ RECT 1745.920000 1197.900000 1747.020000 1198.380000 ;
+ RECT 1745.920000 1203.340000 1747.020000 1203.820000 ;
+ RECT 1745.920000 1208.780000 1747.020000 1209.260000 ;
+ RECT 1745.920000 1214.220000 1747.020000 1214.700000 ;
+ RECT 1745.920000 1219.660000 1747.020000 1220.140000 ;
+ RECT 1700.920000 1197.900000 1702.020000 1198.380000 ;
+ RECT 1700.920000 1203.340000 1702.020000 1203.820000 ;
+ RECT 1700.920000 1208.780000 1702.020000 1209.260000 ;
+ RECT 1700.920000 1214.220000 1702.020000 1214.700000 ;
+ RECT 1700.920000 1219.660000 1702.020000 1220.140000 ;
+ RECT 1652.090000 1241.420000 1653.090000 1241.900000 ;
+ RECT 1655.755000 1241.420000 1657.020000 1241.900000 ;
+ RECT 1652.090000 1235.980000 1653.090000 1236.460000 ;
+ RECT 1655.755000 1235.980000 1657.020000 1236.460000 ;
+ RECT 1652.090000 1230.540000 1653.090000 1231.020000 ;
+ RECT 1655.755000 1230.540000 1657.020000 1231.020000 ;
+ RECT 1652.090000 1225.100000 1653.090000 1225.580000 ;
+ RECT 1655.755000 1225.100000 1657.020000 1225.580000 ;
+ RECT 1652.090000 1219.660000 1653.090000 1220.140000 ;
+ RECT 1655.755000 1219.660000 1657.020000 1220.140000 ;
+ RECT 1652.090000 1214.220000 1653.090000 1214.700000 ;
+ RECT 1655.755000 1214.220000 1657.020000 1214.700000 ;
+ RECT 1652.090000 1203.340000 1653.090000 1203.820000 ;
+ RECT 1655.755000 1203.340000 1657.020000 1203.820000 ;
+ RECT 1652.090000 1208.780000 1653.090000 1209.260000 ;
+ RECT 1655.755000 1208.780000 1657.020000 1209.260000 ;
+ RECT 1652.090000 1197.900000 1653.090000 1198.380000 ;
+ RECT 1655.755000 1197.900000 1657.020000 1198.380000 ;
+ RECT 1745.920000 1176.140000 1747.020000 1176.620000 ;
+ RECT 1745.920000 1181.580000 1747.020000 1182.060000 ;
+ RECT 1745.920000 1187.020000 1747.020000 1187.500000 ;
+ RECT 1745.920000 1192.460000 1747.020000 1192.940000 ;
+ RECT 1700.920000 1176.140000 1702.020000 1176.620000 ;
+ RECT 1700.920000 1181.580000 1702.020000 1182.060000 ;
+ RECT 1700.920000 1187.020000 1702.020000 1187.500000 ;
+ RECT 1700.920000 1192.460000 1702.020000 1192.940000 ;
+ RECT 1745.920000 1154.380000 1747.020000 1154.860000 ;
+ RECT 1745.920000 1159.820000 1747.020000 1160.300000 ;
+ RECT 1745.920000 1165.260000 1747.020000 1165.740000 ;
+ RECT 1745.920000 1170.700000 1747.020000 1171.180000 ;
+ RECT 1700.920000 1154.380000 1702.020000 1154.860000 ;
+ RECT 1700.920000 1159.820000 1702.020000 1160.300000 ;
+ RECT 1700.920000 1165.260000 1702.020000 1165.740000 ;
+ RECT 1700.920000 1170.700000 1702.020000 1171.180000 ;
+ RECT 1652.090000 1192.460000 1653.090000 1192.940000 ;
+ RECT 1655.755000 1192.460000 1657.020000 1192.940000 ;
+ RECT 1652.090000 1187.020000 1653.090000 1187.500000 ;
+ RECT 1655.755000 1187.020000 1657.020000 1187.500000 ;
+ RECT 1652.090000 1181.580000 1653.090000 1182.060000 ;
+ RECT 1655.755000 1181.580000 1657.020000 1182.060000 ;
+ RECT 1652.090000 1176.140000 1653.090000 1176.620000 ;
+ RECT 1655.755000 1176.140000 1657.020000 1176.620000 ;
+ RECT 1652.090000 1170.700000 1653.090000 1171.180000 ;
+ RECT 1655.755000 1170.700000 1657.020000 1171.180000 ;
+ RECT 1652.090000 1159.820000 1653.090000 1160.300000 ;
+ RECT 1655.755000 1159.820000 1657.020000 1160.300000 ;
+ RECT 1652.090000 1165.260000 1653.090000 1165.740000 ;
+ RECT 1655.755000 1165.260000 1657.020000 1165.740000 ;
+ RECT 1652.090000 1154.380000 1653.090000 1154.860000 ;
+ RECT 1655.755000 1154.380000 1657.020000 1154.860000 ;
+ RECT 1790.920000 1246.860000 1792.020000 1247.340000 ;
+ RECT 1835.920000 1246.860000 1837.020000 1247.340000 ;
+ RECT 1848.730000 1246.860000 1849.730000 1247.340000 ;
+ RECT 1700.920000 1246.860000 1702.020000 1247.340000 ;
+ RECT 1745.920000 1246.860000 1747.020000 1247.340000 ;
+ RECT 1652.090000 1246.860000 1653.090000 1247.340000 ;
+ RECT 1655.755000 1246.860000 1657.020000 1247.340000 ;
+ RECT 1650.860000 1343.620000 1850.960000 1344.620000 ;
+ RECT 1650.860000 1148.050000 1850.960000 1149.050000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 1146.800000 1653.090000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 1346.060000 1653.090000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 1146.800000 1849.730000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 1346.060000 1849.730000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1148.050000 1651.860000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1148.050000 1850.960000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1343.620000 1651.860000 1344.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1343.620000 1850.960000 1344.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 1139.080000 1657.020000 1139.560000 ;
+ RECT 1655.755000 1128.200000 1657.020000 1128.680000 ;
+ RECT 1655.755000 1133.640000 1657.020000 1134.120000 ;
+ RECT 1655.755000 1122.760000 1657.020000 1123.240000 ;
+ RECT 1655.755000 1117.320000 1657.020000 1117.800000 ;
+ RECT 1655.755000 1111.880000 1657.020000 1112.360000 ;
+ RECT 1655.755000 1106.440000 1657.020000 1106.920000 ;
+ RECT 1655.755000 1101.000000 1657.020000 1101.480000 ;
+ RECT 1655.755000 1095.560000 1657.020000 1096.040000 ;
+ RECT 1655.755000 1084.680000 1657.020000 1085.160000 ;
+ RECT 1655.755000 1090.120000 1657.020000 1090.600000 ;
+ RECT 1655.755000 1079.240000 1657.020000 1079.720000 ;
+ RECT 1655.755000 1073.800000 1657.020000 1074.280000 ;
+ RECT 1655.755000 1068.360000 1657.020000 1068.840000 ;
+ RECT 1655.755000 1062.920000 1657.020000 1063.400000 ;
+ RECT 1655.755000 1057.480000 1657.020000 1057.960000 ;
+ RECT 1655.755000 1052.040000 1657.020000 1052.520000 ;
+ RECT 1655.755000 1041.160000 1657.020000 1041.640000 ;
+ RECT 1655.755000 1035.720000 1657.020000 1036.200000 ;
+ RECT 1655.755000 1030.280000 1657.020000 1030.760000 ;
+ RECT 1655.755000 1024.840000 1657.020000 1025.320000 ;
+ RECT 1655.755000 1019.400000 1657.020000 1019.880000 ;
+ RECT 1655.755000 1013.960000 1657.020000 1014.440000 ;
+ RECT 1655.755000 1003.080000 1657.020000 1003.560000 ;
+ RECT 1655.755000 1008.520000 1657.020000 1009.000000 ;
+ RECT 1655.755000 997.640000 1657.020000 998.120000 ;
+ RECT 1655.755000 992.200000 1657.020000 992.680000 ;
+ RECT 1655.755000 986.760000 1657.020000 987.240000 ;
+ RECT 1655.755000 981.320000 1657.020000 981.800000 ;
+ RECT 1655.755000 975.880000 1657.020000 976.360000 ;
+ RECT 1655.755000 970.440000 1657.020000 970.920000 ;
+ RECT 1655.755000 959.560000 1657.020000 960.040000 ;
+ RECT 1655.755000 965.000000 1657.020000 965.480000 ;
+ RECT 1655.755000 954.120000 1657.020000 954.600000 ;
+ RECT 1655.755000 1046.600000 1657.020000 1047.080000 ;
+ RECT 1835.920000 947.790000 1837.020000 1144.360000 ;
+ RECT 1790.920000 947.790000 1792.020000 1144.360000 ;
+ RECT 1848.730000 946.540000 1849.730000 1146.800000 ;
+ RECT 1745.920000 947.790000 1747.020000 1144.360000 ;
+ RECT 1700.920000 947.790000 1702.020000 1144.360000 ;
+ RECT 1655.920000 947.790000 1657.020000 1144.360000 ;
+ RECT 1652.090000 946.540000 1653.090000 1146.800000 ;
+ LAYER met3 ;
+ RECT 1835.920000 1139.080000 1837.020000 1139.560000 ;
+ RECT 1848.730000 1139.080000 1849.730000 1139.560000 ;
+ RECT 1848.730000 1128.200000 1849.730000 1128.680000 ;
+ RECT 1848.730000 1122.760000 1849.730000 1123.240000 ;
+ RECT 1848.730000 1133.640000 1849.730000 1134.120000 ;
+ RECT 1835.920000 1133.640000 1837.020000 1134.120000 ;
+ RECT 1835.920000 1128.200000 1837.020000 1128.680000 ;
+ RECT 1835.920000 1122.760000 1837.020000 1123.240000 ;
+ RECT 1835.920000 1111.880000 1837.020000 1112.360000 ;
+ RECT 1835.920000 1117.320000 1837.020000 1117.800000 ;
+ RECT 1848.730000 1111.880000 1849.730000 1112.360000 ;
+ RECT 1848.730000 1117.320000 1849.730000 1117.800000 ;
+ RECT 1835.920000 1101.000000 1837.020000 1101.480000 ;
+ RECT 1835.920000 1106.440000 1837.020000 1106.920000 ;
+ RECT 1848.730000 1101.000000 1849.730000 1101.480000 ;
+ RECT 1848.730000 1106.440000 1849.730000 1106.920000 ;
+ RECT 1790.920000 1122.760000 1792.020000 1123.240000 ;
+ RECT 1790.920000 1128.200000 1792.020000 1128.680000 ;
+ RECT 1790.920000 1133.640000 1792.020000 1134.120000 ;
+ RECT 1790.920000 1139.080000 1792.020000 1139.560000 ;
+ RECT 1790.920000 1106.440000 1792.020000 1106.920000 ;
+ RECT 1790.920000 1101.000000 1792.020000 1101.480000 ;
+ RECT 1790.920000 1111.880000 1792.020000 1112.360000 ;
+ RECT 1790.920000 1117.320000 1792.020000 1117.800000 ;
+ RECT 1848.730000 1090.120000 1849.730000 1090.600000 ;
+ RECT 1848.730000 1084.680000 1849.730000 1085.160000 ;
+ RECT 1848.730000 1095.560000 1849.730000 1096.040000 ;
+ RECT 1835.920000 1095.560000 1837.020000 1096.040000 ;
+ RECT 1835.920000 1090.120000 1837.020000 1090.600000 ;
+ RECT 1835.920000 1084.680000 1837.020000 1085.160000 ;
+ RECT 1835.920000 1073.800000 1837.020000 1074.280000 ;
+ RECT 1835.920000 1079.240000 1837.020000 1079.720000 ;
+ RECT 1848.730000 1073.800000 1849.730000 1074.280000 ;
+ RECT 1848.730000 1079.240000 1849.730000 1079.720000 ;
+ RECT 1848.730000 1062.920000 1849.730000 1063.400000 ;
+ RECT 1848.730000 1068.360000 1849.730000 1068.840000 ;
+ RECT 1835.920000 1068.360000 1837.020000 1068.840000 ;
+ RECT 1835.920000 1062.920000 1837.020000 1063.400000 ;
+ RECT 1835.920000 1052.040000 1837.020000 1052.520000 ;
+ RECT 1835.920000 1057.480000 1837.020000 1057.960000 ;
+ RECT 1848.730000 1052.040000 1849.730000 1052.520000 ;
+ RECT 1848.730000 1057.480000 1849.730000 1057.960000 ;
+ RECT 1790.920000 1073.800000 1792.020000 1074.280000 ;
+ RECT 1790.920000 1079.240000 1792.020000 1079.720000 ;
+ RECT 1790.920000 1084.680000 1792.020000 1085.160000 ;
+ RECT 1790.920000 1090.120000 1792.020000 1090.600000 ;
+ RECT 1790.920000 1095.560000 1792.020000 1096.040000 ;
+ RECT 1790.920000 1052.040000 1792.020000 1052.520000 ;
+ RECT 1790.920000 1057.480000 1792.020000 1057.960000 ;
+ RECT 1790.920000 1062.920000 1792.020000 1063.400000 ;
+ RECT 1790.920000 1068.360000 1792.020000 1068.840000 ;
+ RECT 1745.920000 1128.200000 1747.020000 1128.680000 ;
+ RECT 1745.920000 1122.760000 1747.020000 1123.240000 ;
+ RECT 1745.920000 1133.640000 1747.020000 1134.120000 ;
+ RECT 1745.920000 1139.080000 1747.020000 1139.560000 ;
+ RECT 1700.920000 1122.760000 1702.020000 1123.240000 ;
+ RECT 1700.920000 1128.200000 1702.020000 1128.680000 ;
+ RECT 1700.920000 1133.640000 1702.020000 1134.120000 ;
+ RECT 1700.920000 1139.080000 1702.020000 1139.560000 ;
+ RECT 1745.920000 1101.000000 1747.020000 1101.480000 ;
+ RECT 1745.920000 1106.440000 1747.020000 1106.920000 ;
+ RECT 1745.920000 1111.880000 1747.020000 1112.360000 ;
+ RECT 1745.920000 1117.320000 1747.020000 1117.800000 ;
+ RECT 1700.920000 1101.000000 1702.020000 1101.480000 ;
+ RECT 1700.920000 1106.440000 1702.020000 1106.920000 ;
+ RECT 1700.920000 1111.880000 1702.020000 1112.360000 ;
+ RECT 1700.920000 1117.320000 1702.020000 1117.800000 ;
+ RECT 1652.090000 1139.080000 1653.090000 1139.560000 ;
+ RECT 1655.755000 1139.080000 1657.020000 1139.560000 ;
+ RECT 1652.090000 1128.200000 1653.090000 1128.680000 ;
+ RECT 1655.755000 1128.200000 1657.020000 1128.680000 ;
+ RECT 1652.090000 1133.640000 1653.090000 1134.120000 ;
+ RECT 1655.755000 1133.640000 1657.020000 1134.120000 ;
+ RECT 1652.090000 1122.760000 1653.090000 1123.240000 ;
+ RECT 1655.755000 1122.760000 1657.020000 1123.240000 ;
+ RECT 1652.090000 1117.320000 1653.090000 1117.800000 ;
+ RECT 1655.755000 1117.320000 1657.020000 1117.800000 ;
+ RECT 1652.090000 1111.880000 1653.090000 1112.360000 ;
+ RECT 1655.755000 1111.880000 1657.020000 1112.360000 ;
+ RECT 1652.090000 1106.440000 1653.090000 1106.920000 ;
+ RECT 1655.755000 1106.440000 1657.020000 1106.920000 ;
+ RECT 1652.090000 1101.000000 1653.090000 1101.480000 ;
+ RECT 1655.755000 1101.000000 1657.020000 1101.480000 ;
+ RECT 1745.920000 1073.800000 1747.020000 1074.280000 ;
+ RECT 1745.920000 1079.240000 1747.020000 1079.720000 ;
+ RECT 1745.920000 1084.680000 1747.020000 1085.160000 ;
+ RECT 1745.920000 1090.120000 1747.020000 1090.600000 ;
+ RECT 1745.920000 1095.560000 1747.020000 1096.040000 ;
+ RECT 1700.920000 1073.800000 1702.020000 1074.280000 ;
+ RECT 1700.920000 1079.240000 1702.020000 1079.720000 ;
+ RECT 1700.920000 1084.680000 1702.020000 1085.160000 ;
+ RECT 1700.920000 1090.120000 1702.020000 1090.600000 ;
+ RECT 1700.920000 1095.560000 1702.020000 1096.040000 ;
+ RECT 1745.920000 1052.040000 1747.020000 1052.520000 ;
+ RECT 1745.920000 1057.480000 1747.020000 1057.960000 ;
+ RECT 1745.920000 1062.920000 1747.020000 1063.400000 ;
+ RECT 1745.920000 1068.360000 1747.020000 1068.840000 ;
+ RECT 1700.920000 1052.040000 1702.020000 1052.520000 ;
+ RECT 1700.920000 1057.480000 1702.020000 1057.960000 ;
+ RECT 1700.920000 1062.920000 1702.020000 1063.400000 ;
+ RECT 1700.920000 1068.360000 1702.020000 1068.840000 ;
+ RECT 1652.090000 1095.560000 1653.090000 1096.040000 ;
+ RECT 1655.755000 1095.560000 1657.020000 1096.040000 ;
+ RECT 1652.090000 1084.680000 1653.090000 1085.160000 ;
+ RECT 1655.755000 1084.680000 1657.020000 1085.160000 ;
+ RECT 1652.090000 1090.120000 1653.090000 1090.600000 ;
+ RECT 1655.755000 1090.120000 1657.020000 1090.600000 ;
+ RECT 1652.090000 1079.240000 1653.090000 1079.720000 ;
+ RECT 1655.755000 1079.240000 1657.020000 1079.720000 ;
+ RECT 1652.090000 1073.800000 1653.090000 1074.280000 ;
+ RECT 1655.755000 1073.800000 1657.020000 1074.280000 ;
+ RECT 1652.090000 1068.360000 1653.090000 1068.840000 ;
+ RECT 1655.755000 1068.360000 1657.020000 1068.840000 ;
+ RECT 1652.090000 1062.920000 1653.090000 1063.400000 ;
+ RECT 1655.755000 1062.920000 1657.020000 1063.400000 ;
+ RECT 1652.090000 1057.480000 1653.090000 1057.960000 ;
+ RECT 1655.755000 1057.480000 1657.020000 1057.960000 ;
+ RECT 1652.090000 1052.040000 1653.090000 1052.520000 ;
+ RECT 1655.755000 1052.040000 1657.020000 1052.520000 ;
+ RECT 1835.920000 1035.720000 1837.020000 1036.200000 ;
+ RECT 1835.920000 1041.160000 1837.020000 1041.640000 ;
+ RECT 1848.730000 1035.720000 1849.730000 1036.200000 ;
+ RECT 1848.730000 1041.160000 1849.730000 1041.640000 ;
+ RECT 1848.730000 1024.840000 1849.730000 1025.320000 ;
+ RECT 1848.730000 1030.280000 1849.730000 1030.760000 ;
+ RECT 1835.920000 1030.280000 1837.020000 1030.760000 ;
+ RECT 1835.920000 1024.840000 1837.020000 1025.320000 ;
+ RECT 1835.920000 1013.960000 1837.020000 1014.440000 ;
+ RECT 1835.920000 1019.400000 1837.020000 1019.880000 ;
+ RECT 1848.730000 1013.960000 1849.730000 1014.440000 ;
+ RECT 1848.730000 1019.400000 1849.730000 1019.880000 ;
+ RECT 1848.730000 1003.080000 1849.730000 1003.560000 ;
+ RECT 1848.730000 997.640000 1849.730000 998.120000 ;
+ RECT 1848.730000 1008.520000 1849.730000 1009.000000 ;
+ RECT 1835.920000 1008.520000 1837.020000 1009.000000 ;
+ RECT 1835.920000 1003.080000 1837.020000 1003.560000 ;
+ RECT 1835.920000 997.640000 1837.020000 998.120000 ;
+ RECT 1790.920000 1024.840000 1792.020000 1025.320000 ;
+ RECT 1790.920000 1030.280000 1792.020000 1030.760000 ;
+ RECT 1790.920000 1035.720000 1792.020000 1036.200000 ;
+ RECT 1790.920000 1041.160000 1792.020000 1041.640000 ;
+ RECT 1790.920000 997.640000 1792.020000 998.120000 ;
+ RECT 1790.920000 1003.080000 1792.020000 1003.560000 ;
+ RECT 1790.920000 1008.520000 1792.020000 1009.000000 ;
+ RECT 1790.920000 1013.960000 1792.020000 1014.440000 ;
+ RECT 1790.920000 1019.400000 1792.020000 1019.880000 ;
+ RECT 1835.920000 986.760000 1837.020000 987.240000 ;
+ RECT 1835.920000 992.200000 1837.020000 992.680000 ;
+ RECT 1848.730000 986.760000 1849.730000 987.240000 ;
+ RECT 1848.730000 992.200000 1849.730000 992.680000 ;
+ RECT 1835.920000 975.880000 1837.020000 976.360000 ;
+ RECT 1835.920000 981.320000 1837.020000 981.800000 ;
+ RECT 1848.730000 975.880000 1849.730000 976.360000 ;
+ RECT 1848.730000 981.320000 1849.730000 981.800000 ;
+ RECT 1848.730000 965.000000 1849.730000 965.480000 ;
+ RECT 1848.730000 959.560000 1849.730000 960.040000 ;
+ RECT 1848.730000 970.440000 1849.730000 970.920000 ;
+ RECT 1835.920000 970.440000 1837.020000 970.920000 ;
+ RECT 1835.920000 965.000000 1837.020000 965.480000 ;
+ RECT 1835.920000 959.560000 1837.020000 960.040000 ;
+ RECT 1835.920000 954.120000 1837.020000 954.600000 ;
+ RECT 1848.730000 954.120000 1849.730000 954.600000 ;
+ RECT 1790.920000 975.880000 1792.020000 976.360000 ;
+ RECT 1790.920000 981.320000 1792.020000 981.800000 ;
+ RECT 1790.920000 986.760000 1792.020000 987.240000 ;
+ RECT 1790.920000 992.200000 1792.020000 992.680000 ;
+ RECT 1790.920000 954.120000 1792.020000 954.600000 ;
+ RECT 1790.920000 959.560000 1792.020000 960.040000 ;
+ RECT 1790.920000 965.000000 1792.020000 965.480000 ;
+ RECT 1790.920000 970.440000 1792.020000 970.920000 ;
+ RECT 1745.920000 1024.840000 1747.020000 1025.320000 ;
+ RECT 1745.920000 1030.280000 1747.020000 1030.760000 ;
+ RECT 1745.920000 1035.720000 1747.020000 1036.200000 ;
+ RECT 1745.920000 1041.160000 1747.020000 1041.640000 ;
+ RECT 1700.920000 1024.840000 1702.020000 1025.320000 ;
+ RECT 1700.920000 1030.280000 1702.020000 1030.760000 ;
+ RECT 1700.920000 1035.720000 1702.020000 1036.200000 ;
+ RECT 1700.920000 1041.160000 1702.020000 1041.640000 ;
+ RECT 1745.920000 997.640000 1747.020000 998.120000 ;
+ RECT 1745.920000 1003.080000 1747.020000 1003.560000 ;
+ RECT 1745.920000 1008.520000 1747.020000 1009.000000 ;
+ RECT 1745.920000 1013.960000 1747.020000 1014.440000 ;
+ RECT 1745.920000 1019.400000 1747.020000 1019.880000 ;
+ RECT 1700.920000 997.640000 1702.020000 998.120000 ;
+ RECT 1700.920000 1003.080000 1702.020000 1003.560000 ;
+ RECT 1700.920000 1008.520000 1702.020000 1009.000000 ;
+ RECT 1700.920000 1013.960000 1702.020000 1014.440000 ;
+ RECT 1700.920000 1019.400000 1702.020000 1019.880000 ;
+ RECT 1652.090000 1041.160000 1653.090000 1041.640000 ;
+ RECT 1655.755000 1041.160000 1657.020000 1041.640000 ;
+ RECT 1652.090000 1035.720000 1653.090000 1036.200000 ;
+ RECT 1655.755000 1035.720000 1657.020000 1036.200000 ;
+ RECT 1652.090000 1030.280000 1653.090000 1030.760000 ;
+ RECT 1655.755000 1030.280000 1657.020000 1030.760000 ;
+ RECT 1652.090000 1024.840000 1653.090000 1025.320000 ;
+ RECT 1655.755000 1024.840000 1657.020000 1025.320000 ;
+ RECT 1652.090000 1019.400000 1653.090000 1019.880000 ;
+ RECT 1655.755000 1019.400000 1657.020000 1019.880000 ;
+ RECT 1652.090000 1013.960000 1653.090000 1014.440000 ;
+ RECT 1655.755000 1013.960000 1657.020000 1014.440000 ;
+ RECT 1652.090000 1003.080000 1653.090000 1003.560000 ;
+ RECT 1655.755000 1003.080000 1657.020000 1003.560000 ;
+ RECT 1652.090000 1008.520000 1653.090000 1009.000000 ;
+ RECT 1655.755000 1008.520000 1657.020000 1009.000000 ;
+ RECT 1652.090000 997.640000 1653.090000 998.120000 ;
+ RECT 1655.755000 997.640000 1657.020000 998.120000 ;
+ RECT 1745.920000 975.880000 1747.020000 976.360000 ;
+ RECT 1745.920000 981.320000 1747.020000 981.800000 ;
+ RECT 1745.920000 986.760000 1747.020000 987.240000 ;
+ RECT 1745.920000 992.200000 1747.020000 992.680000 ;
+ RECT 1700.920000 975.880000 1702.020000 976.360000 ;
+ RECT 1700.920000 981.320000 1702.020000 981.800000 ;
+ RECT 1700.920000 986.760000 1702.020000 987.240000 ;
+ RECT 1700.920000 992.200000 1702.020000 992.680000 ;
+ RECT 1745.920000 954.120000 1747.020000 954.600000 ;
+ RECT 1745.920000 959.560000 1747.020000 960.040000 ;
+ RECT 1745.920000 965.000000 1747.020000 965.480000 ;
+ RECT 1745.920000 970.440000 1747.020000 970.920000 ;
+ RECT 1700.920000 954.120000 1702.020000 954.600000 ;
+ RECT 1700.920000 959.560000 1702.020000 960.040000 ;
+ RECT 1700.920000 965.000000 1702.020000 965.480000 ;
+ RECT 1700.920000 970.440000 1702.020000 970.920000 ;
+ RECT 1652.090000 992.200000 1653.090000 992.680000 ;
+ RECT 1655.755000 992.200000 1657.020000 992.680000 ;
+ RECT 1652.090000 986.760000 1653.090000 987.240000 ;
+ RECT 1655.755000 986.760000 1657.020000 987.240000 ;
+ RECT 1652.090000 981.320000 1653.090000 981.800000 ;
+ RECT 1655.755000 981.320000 1657.020000 981.800000 ;
+ RECT 1652.090000 975.880000 1653.090000 976.360000 ;
+ RECT 1655.755000 975.880000 1657.020000 976.360000 ;
+ RECT 1652.090000 970.440000 1653.090000 970.920000 ;
+ RECT 1655.755000 970.440000 1657.020000 970.920000 ;
+ RECT 1652.090000 959.560000 1653.090000 960.040000 ;
+ RECT 1655.755000 959.560000 1657.020000 960.040000 ;
+ RECT 1652.090000 965.000000 1653.090000 965.480000 ;
+ RECT 1655.755000 965.000000 1657.020000 965.480000 ;
+ RECT 1652.090000 954.120000 1653.090000 954.600000 ;
+ RECT 1655.755000 954.120000 1657.020000 954.600000 ;
+ RECT 1790.920000 1046.600000 1792.020000 1047.080000 ;
+ RECT 1835.920000 1046.600000 1837.020000 1047.080000 ;
+ RECT 1848.730000 1046.600000 1849.730000 1047.080000 ;
+ RECT 1700.920000 1046.600000 1702.020000 1047.080000 ;
+ RECT 1745.920000 1046.600000 1747.020000 1047.080000 ;
+ RECT 1652.090000 1046.600000 1653.090000 1047.080000 ;
+ RECT 1655.755000 1046.600000 1657.020000 1047.080000 ;
+ RECT 1650.860000 1143.360000 1850.960000 1144.360000 ;
+ RECT 1650.860000 947.790000 1850.960000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 946.540000 1653.090000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 1145.800000 1653.090000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 946.540000 1849.730000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 1145.800000 1849.730000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 947.790000 1651.860000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 947.790000 1850.960000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1143.360000 1651.860000 1144.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1143.360000 1850.960000 1144.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 938.820000 1657.020000 939.300000 ;
+ RECT 1655.755000 927.940000 1657.020000 928.420000 ;
+ RECT 1655.755000 933.380000 1657.020000 933.860000 ;
+ RECT 1655.755000 922.500000 1657.020000 922.980000 ;
+ RECT 1655.755000 917.060000 1657.020000 917.540000 ;
+ RECT 1655.755000 911.620000 1657.020000 912.100000 ;
+ RECT 1655.755000 906.180000 1657.020000 906.660000 ;
+ RECT 1655.755000 900.740000 1657.020000 901.220000 ;
+ RECT 1655.755000 895.300000 1657.020000 895.780000 ;
+ RECT 1655.755000 884.420000 1657.020000 884.900000 ;
+ RECT 1655.755000 889.860000 1657.020000 890.340000 ;
+ RECT 1655.755000 878.980000 1657.020000 879.460000 ;
+ RECT 1655.755000 873.540000 1657.020000 874.020000 ;
+ RECT 1655.755000 868.100000 1657.020000 868.580000 ;
+ RECT 1655.755000 862.660000 1657.020000 863.140000 ;
+ RECT 1655.755000 857.220000 1657.020000 857.700000 ;
+ RECT 1655.755000 851.780000 1657.020000 852.260000 ;
+ RECT 1655.755000 840.900000 1657.020000 841.380000 ;
+ RECT 1655.755000 835.460000 1657.020000 835.940000 ;
+ RECT 1655.755000 830.020000 1657.020000 830.500000 ;
+ RECT 1655.755000 824.580000 1657.020000 825.060000 ;
+ RECT 1655.755000 819.140000 1657.020000 819.620000 ;
+ RECT 1655.755000 813.700000 1657.020000 814.180000 ;
+ RECT 1655.755000 802.820000 1657.020000 803.300000 ;
+ RECT 1655.755000 808.260000 1657.020000 808.740000 ;
+ RECT 1655.755000 797.380000 1657.020000 797.860000 ;
+ RECT 1655.755000 791.940000 1657.020000 792.420000 ;
+ RECT 1655.755000 786.500000 1657.020000 786.980000 ;
+ RECT 1655.755000 781.060000 1657.020000 781.540000 ;
+ RECT 1655.755000 775.620000 1657.020000 776.100000 ;
+ RECT 1655.755000 770.180000 1657.020000 770.660000 ;
+ RECT 1655.755000 759.300000 1657.020000 759.780000 ;
+ RECT 1655.755000 764.740000 1657.020000 765.220000 ;
+ RECT 1655.755000 753.860000 1657.020000 754.340000 ;
+ RECT 1655.755000 846.340000 1657.020000 846.820000 ;
+ RECT 1835.920000 747.530000 1837.020000 944.100000 ;
+ RECT 1790.920000 747.530000 1792.020000 944.100000 ;
+ RECT 1848.730000 746.280000 1849.730000 946.540000 ;
+ RECT 1745.920000 747.530000 1747.020000 944.100000 ;
+ RECT 1700.920000 747.530000 1702.020000 944.100000 ;
+ RECT 1655.920000 747.530000 1657.020000 944.100000 ;
+ RECT 1652.090000 746.280000 1653.090000 946.540000 ;
+ LAYER met3 ;
+ RECT 1835.920000 938.820000 1837.020000 939.300000 ;
+ RECT 1848.730000 938.820000 1849.730000 939.300000 ;
+ RECT 1848.730000 927.940000 1849.730000 928.420000 ;
+ RECT 1848.730000 922.500000 1849.730000 922.980000 ;
+ RECT 1848.730000 933.380000 1849.730000 933.860000 ;
+ RECT 1835.920000 933.380000 1837.020000 933.860000 ;
+ RECT 1835.920000 927.940000 1837.020000 928.420000 ;
+ RECT 1835.920000 922.500000 1837.020000 922.980000 ;
+ RECT 1835.920000 911.620000 1837.020000 912.100000 ;
+ RECT 1835.920000 917.060000 1837.020000 917.540000 ;
+ RECT 1848.730000 911.620000 1849.730000 912.100000 ;
+ RECT 1848.730000 917.060000 1849.730000 917.540000 ;
+ RECT 1835.920000 900.740000 1837.020000 901.220000 ;
+ RECT 1835.920000 906.180000 1837.020000 906.660000 ;
+ RECT 1848.730000 900.740000 1849.730000 901.220000 ;
+ RECT 1848.730000 906.180000 1849.730000 906.660000 ;
+ RECT 1790.920000 922.500000 1792.020000 922.980000 ;
+ RECT 1790.920000 927.940000 1792.020000 928.420000 ;
+ RECT 1790.920000 933.380000 1792.020000 933.860000 ;
+ RECT 1790.920000 938.820000 1792.020000 939.300000 ;
+ RECT 1790.920000 906.180000 1792.020000 906.660000 ;
+ RECT 1790.920000 900.740000 1792.020000 901.220000 ;
+ RECT 1790.920000 911.620000 1792.020000 912.100000 ;
+ RECT 1790.920000 917.060000 1792.020000 917.540000 ;
+ RECT 1848.730000 889.860000 1849.730000 890.340000 ;
+ RECT 1848.730000 884.420000 1849.730000 884.900000 ;
+ RECT 1848.730000 895.300000 1849.730000 895.780000 ;
+ RECT 1835.920000 895.300000 1837.020000 895.780000 ;
+ RECT 1835.920000 889.860000 1837.020000 890.340000 ;
+ RECT 1835.920000 884.420000 1837.020000 884.900000 ;
+ RECT 1835.920000 873.540000 1837.020000 874.020000 ;
+ RECT 1835.920000 878.980000 1837.020000 879.460000 ;
+ RECT 1848.730000 873.540000 1849.730000 874.020000 ;
+ RECT 1848.730000 878.980000 1849.730000 879.460000 ;
+ RECT 1848.730000 862.660000 1849.730000 863.140000 ;
+ RECT 1848.730000 868.100000 1849.730000 868.580000 ;
+ RECT 1835.920000 868.100000 1837.020000 868.580000 ;
+ RECT 1835.920000 862.660000 1837.020000 863.140000 ;
+ RECT 1835.920000 851.780000 1837.020000 852.260000 ;
+ RECT 1835.920000 857.220000 1837.020000 857.700000 ;
+ RECT 1848.730000 851.780000 1849.730000 852.260000 ;
+ RECT 1848.730000 857.220000 1849.730000 857.700000 ;
+ RECT 1790.920000 873.540000 1792.020000 874.020000 ;
+ RECT 1790.920000 878.980000 1792.020000 879.460000 ;
+ RECT 1790.920000 884.420000 1792.020000 884.900000 ;
+ RECT 1790.920000 889.860000 1792.020000 890.340000 ;
+ RECT 1790.920000 895.300000 1792.020000 895.780000 ;
+ RECT 1790.920000 851.780000 1792.020000 852.260000 ;
+ RECT 1790.920000 857.220000 1792.020000 857.700000 ;
+ RECT 1790.920000 862.660000 1792.020000 863.140000 ;
+ RECT 1790.920000 868.100000 1792.020000 868.580000 ;
+ RECT 1745.920000 927.940000 1747.020000 928.420000 ;
+ RECT 1745.920000 922.500000 1747.020000 922.980000 ;
+ RECT 1745.920000 933.380000 1747.020000 933.860000 ;
+ RECT 1745.920000 938.820000 1747.020000 939.300000 ;
+ RECT 1700.920000 922.500000 1702.020000 922.980000 ;
+ RECT 1700.920000 927.940000 1702.020000 928.420000 ;
+ RECT 1700.920000 933.380000 1702.020000 933.860000 ;
+ RECT 1700.920000 938.820000 1702.020000 939.300000 ;
+ RECT 1745.920000 900.740000 1747.020000 901.220000 ;
+ RECT 1745.920000 906.180000 1747.020000 906.660000 ;
+ RECT 1745.920000 911.620000 1747.020000 912.100000 ;
+ RECT 1745.920000 917.060000 1747.020000 917.540000 ;
+ RECT 1700.920000 900.740000 1702.020000 901.220000 ;
+ RECT 1700.920000 906.180000 1702.020000 906.660000 ;
+ RECT 1700.920000 911.620000 1702.020000 912.100000 ;
+ RECT 1700.920000 917.060000 1702.020000 917.540000 ;
+ RECT 1652.090000 938.820000 1653.090000 939.300000 ;
+ RECT 1655.755000 938.820000 1657.020000 939.300000 ;
+ RECT 1652.090000 927.940000 1653.090000 928.420000 ;
+ RECT 1655.755000 927.940000 1657.020000 928.420000 ;
+ RECT 1652.090000 933.380000 1653.090000 933.860000 ;
+ RECT 1655.755000 933.380000 1657.020000 933.860000 ;
+ RECT 1652.090000 922.500000 1653.090000 922.980000 ;
+ RECT 1655.755000 922.500000 1657.020000 922.980000 ;
+ RECT 1652.090000 917.060000 1653.090000 917.540000 ;
+ RECT 1655.755000 917.060000 1657.020000 917.540000 ;
+ RECT 1652.090000 911.620000 1653.090000 912.100000 ;
+ RECT 1655.755000 911.620000 1657.020000 912.100000 ;
+ RECT 1652.090000 906.180000 1653.090000 906.660000 ;
+ RECT 1655.755000 906.180000 1657.020000 906.660000 ;
+ RECT 1652.090000 900.740000 1653.090000 901.220000 ;
+ RECT 1655.755000 900.740000 1657.020000 901.220000 ;
+ RECT 1745.920000 873.540000 1747.020000 874.020000 ;
+ RECT 1745.920000 878.980000 1747.020000 879.460000 ;
+ RECT 1745.920000 884.420000 1747.020000 884.900000 ;
+ RECT 1745.920000 889.860000 1747.020000 890.340000 ;
+ RECT 1745.920000 895.300000 1747.020000 895.780000 ;
+ RECT 1700.920000 873.540000 1702.020000 874.020000 ;
+ RECT 1700.920000 878.980000 1702.020000 879.460000 ;
+ RECT 1700.920000 884.420000 1702.020000 884.900000 ;
+ RECT 1700.920000 889.860000 1702.020000 890.340000 ;
+ RECT 1700.920000 895.300000 1702.020000 895.780000 ;
+ RECT 1745.920000 851.780000 1747.020000 852.260000 ;
+ RECT 1745.920000 857.220000 1747.020000 857.700000 ;
+ RECT 1745.920000 862.660000 1747.020000 863.140000 ;
+ RECT 1745.920000 868.100000 1747.020000 868.580000 ;
+ RECT 1700.920000 851.780000 1702.020000 852.260000 ;
+ RECT 1700.920000 857.220000 1702.020000 857.700000 ;
+ RECT 1700.920000 862.660000 1702.020000 863.140000 ;
+ RECT 1700.920000 868.100000 1702.020000 868.580000 ;
+ RECT 1652.090000 895.300000 1653.090000 895.780000 ;
+ RECT 1655.755000 895.300000 1657.020000 895.780000 ;
+ RECT 1652.090000 884.420000 1653.090000 884.900000 ;
+ RECT 1655.755000 884.420000 1657.020000 884.900000 ;
+ RECT 1652.090000 889.860000 1653.090000 890.340000 ;
+ RECT 1655.755000 889.860000 1657.020000 890.340000 ;
+ RECT 1652.090000 878.980000 1653.090000 879.460000 ;
+ RECT 1655.755000 878.980000 1657.020000 879.460000 ;
+ RECT 1652.090000 873.540000 1653.090000 874.020000 ;
+ RECT 1655.755000 873.540000 1657.020000 874.020000 ;
+ RECT 1652.090000 868.100000 1653.090000 868.580000 ;
+ RECT 1655.755000 868.100000 1657.020000 868.580000 ;
+ RECT 1652.090000 862.660000 1653.090000 863.140000 ;
+ RECT 1655.755000 862.660000 1657.020000 863.140000 ;
+ RECT 1652.090000 857.220000 1653.090000 857.700000 ;
+ RECT 1655.755000 857.220000 1657.020000 857.700000 ;
+ RECT 1652.090000 851.780000 1653.090000 852.260000 ;
+ RECT 1655.755000 851.780000 1657.020000 852.260000 ;
+ RECT 1835.920000 835.460000 1837.020000 835.940000 ;
+ RECT 1835.920000 840.900000 1837.020000 841.380000 ;
+ RECT 1848.730000 835.460000 1849.730000 835.940000 ;
+ RECT 1848.730000 840.900000 1849.730000 841.380000 ;
+ RECT 1848.730000 824.580000 1849.730000 825.060000 ;
+ RECT 1848.730000 830.020000 1849.730000 830.500000 ;
+ RECT 1835.920000 830.020000 1837.020000 830.500000 ;
+ RECT 1835.920000 824.580000 1837.020000 825.060000 ;
+ RECT 1835.920000 813.700000 1837.020000 814.180000 ;
+ RECT 1835.920000 819.140000 1837.020000 819.620000 ;
+ RECT 1848.730000 813.700000 1849.730000 814.180000 ;
+ RECT 1848.730000 819.140000 1849.730000 819.620000 ;
+ RECT 1848.730000 802.820000 1849.730000 803.300000 ;
+ RECT 1848.730000 797.380000 1849.730000 797.860000 ;
+ RECT 1848.730000 808.260000 1849.730000 808.740000 ;
+ RECT 1835.920000 808.260000 1837.020000 808.740000 ;
+ RECT 1835.920000 802.820000 1837.020000 803.300000 ;
+ RECT 1835.920000 797.380000 1837.020000 797.860000 ;
+ RECT 1790.920000 824.580000 1792.020000 825.060000 ;
+ RECT 1790.920000 830.020000 1792.020000 830.500000 ;
+ RECT 1790.920000 835.460000 1792.020000 835.940000 ;
+ RECT 1790.920000 840.900000 1792.020000 841.380000 ;
+ RECT 1790.920000 797.380000 1792.020000 797.860000 ;
+ RECT 1790.920000 802.820000 1792.020000 803.300000 ;
+ RECT 1790.920000 808.260000 1792.020000 808.740000 ;
+ RECT 1790.920000 813.700000 1792.020000 814.180000 ;
+ RECT 1790.920000 819.140000 1792.020000 819.620000 ;
+ RECT 1835.920000 786.500000 1837.020000 786.980000 ;
+ RECT 1835.920000 791.940000 1837.020000 792.420000 ;
+ RECT 1848.730000 786.500000 1849.730000 786.980000 ;
+ RECT 1848.730000 791.940000 1849.730000 792.420000 ;
+ RECT 1835.920000 775.620000 1837.020000 776.100000 ;
+ RECT 1835.920000 781.060000 1837.020000 781.540000 ;
+ RECT 1848.730000 775.620000 1849.730000 776.100000 ;
+ RECT 1848.730000 781.060000 1849.730000 781.540000 ;
+ RECT 1848.730000 764.740000 1849.730000 765.220000 ;
+ RECT 1848.730000 759.300000 1849.730000 759.780000 ;
+ RECT 1848.730000 770.180000 1849.730000 770.660000 ;
+ RECT 1835.920000 770.180000 1837.020000 770.660000 ;
+ RECT 1835.920000 764.740000 1837.020000 765.220000 ;
+ RECT 1835.920000 759.300000 1837.020000 759.780000 ;
+ RECT 1835.920000 753.860000 1837.020000 754.340000 ;
+ RECT 1848.730000 753.860000 1849.730000 754.340000 ;
+ RECT 1790.920000 775.620000 1792.020000 776.100000 ;
+ RECT 1790.920000 781.060000 1792.020000 781.540000 ;
+ RECT 1790.920000 786.500000 1792.020000 786.980000 ;
+ RECT 1790.920000 791.940000 1792.020000 792.420000 ;
+ RECT 1790.920000 753.860000 1792.020000 754.340000 ;
+ RECT 1790.920000 759.300000 1792.020000 759.780000 ;
+ RECT 1790.920000 764.740000 1792.020000 765.220000 ;
+ RECT 1790.920000 770.180000 1792.020000 770.660000 ;
+ RECT 1745.920000 824.580000 1747.020000 825.060000 ;
+ RECT 1745.920000 830.020000 1747.020000 830.500000 ;
+ RECT 1745.920000 835.460000 1747.020000 835.940000 ;
+ RECT 1745.920000 840.900000 1747.020000 841.380000 ;
+ RECT 1700.920000 824.580000 1702.020000 825.060000 ;
+ RECT 1700.920000 830.020000 1702.020000 830.500000 ;
+ RECT 1700.920000 835.460000 1702.020000 835.940000 ;
+ RECT 1700.920000 840.900000 1702.020000 841.380000 ;
+ RECT 1745.920000 797.380000 1747.020000 797.860000 ;
+ RECT 1745.920000 802.820000 1747.020000 803.300000 ;
+ RECT 1745.920000 808.260000 1747.020000 808.740000 ;
+ RECT 1745.920000 813.700000 1747.020000 814.180000 ;
+ RECT 1745.920000 819.140000 1747.020000 819.620000 ;
+ RECT 1700.920000 797.380000 1702.020000 797.860000 ;
+ RECT 1700.920000 802.820000 1702.020000 803.300000 ;
+ RECT 1700.920000 808.260000 1702.020000 808.740000 ;
+ RECT 1700.920000 813.700000 1702.020000 814.180000 ;
+ RECT 1700.920000 819.140000 1702.020000 819.620000 ;
+ RECT 1652.090000 840.900000 1653.090000 841.380000 ;
+ RECT 1655.755000 840.900000 1657.020000 841.380000 ;
+ RECT 1652.090000 835.460000 1653.090000 835.940000 ;
+ RECT 1655.755000 835.460000 1657.020000 835.940000 ;
+ RECT 1652.090000 830.020000 1653.090000 830.500000 ;
+ RECT 1655.755000 830.020000 1657.020000 830.500000 ;
+ RECT 1652.090000 824.580000 1653.090000 825.060000 ;
+ RECT 1655.755000 824.580000 1657.020000 825.060000 ;
+ RECT 1652.090000 819.140000 1653.090000 819.620000 ;
+ RECT 1655.755000 819.140000 1657.020000 819.620000 ;
+ RECT 1652.090000 813.700000 1653.090000 814.180000 ;
+ RECT 1655.755000 813.700000 1657.020000 814.180000 ;
+ RECT 1652.090000 802.820000 1653.090000 803.300000 ;
+ RECT 1655.755000 802.820000 1657.020000 803.300000 ;
+ RECT 1652.090000 808.260000 1653.090000 808.740000 ;
+ RECT 1655.755000 808.260000 1657.020000 808.740000 ;
+ RECT 1652.090000 797.380000 1653.090000 797.860000 ;
+ RECT 1655.755000 797.380000 1657.020000 797.860000 ;
+ RECT 1745.920000 775.620000 1747.020000 776.100000 ;
+ RECT 1745.920000 781.060000 1747.020000 781.540000 ;
+ RECT 1745.920000 786.500000 1747.020000 786.980000 ;
+ RECT 1745.920000 791.940000 1747.020000 792.420000 ;
+ RECT 1700.920000 775.620000 1702.020000 776.100000 ;
+ RECT 1700.920000 781.060000 1702.020000 781.540000 ;
+ RECT 1700.920000 786.500000 1702.020000 786.980000 ;
+ RECT 1700.920000 791.940000 1702.020000 792.420000 ;
+ RECT 1745.920000 753.860000 1747.020000 754.340000 ;
+ RECT 1745.920000 759.300000 1747.020000 759.780000 ;
+ RECT 1745.920000 764.740000 1747.020000 765.220000 ;
+ RECT 1745.920000 770.180000 1747.020000 770.660000 ;
+ RECT 1700.920000 753.860000 1702.020000 754.340000 ;
+ RECT 1700.920000 759.300000 1702.020000 759.780000 ;
+ RECT 1700.920000 764.740000 1702.020000 765.220000 ;
+ RECT 1700.920000 770.180000 1702.020000 770.660000 ;
+ RECT 1652.090000 791.940000 1653.090000 792.420000 ;
+ RECT 1655.755000 791.940000 1657.020000 792.420000 ;
+ RECT 1652.090000 786.500000 1653.090000 786.980000 ;
+ RECT 1655.755000 786.500000 1657.020000 786.980000 ;
+ RECT 1652.090000 781.060000 1653.090000 781.540000 ;
+ RECT 1655.755000 781.060000 1657.020000 781.540000 ;
+ RECT 1652.090000 775.620000 1653.090000 776.100000 ;
+ RECT 1655.755000 775.620000 1657.020000 776.100000 ;
+ RECT 1652.090000 770.180000 1653.090000 770.660000 ;
+ RECT 1655.755000 770.180000 1657.020000 770.660000 ;
+ RECT 1652.090000 759.300000 1653.090000 759.780000 ;
+ RECT 1655.755000 759.300000 1657.020000 759.780000 ;
+ RECT 1652.090000 764.740000 1653.090000 765.220000 ;
+ RECT 1655.755000 764.740000 1657.020000 765.220000 ;
+ RECT 1652.090000 753.860000 1653.090000 754.340000 ;
+ RECT 1655.755000 753.860000 1657.020000 754.340000 ;
+ RECT 1790.920000 846.340000 1792.020000 846.820000 ;
+ RECT 1835.920000 846.340000 1837.020000 846.820000 ;
+ RECT 1848.730000 846.340000 1849.730000 846.820000 ;
+ RECT 1700.920000 846.340000 1702.020000 846.820000 ;
+ RECT 1745.920000 846.340000 1747.020000 846.820000 ;
+ RECT 1652.090000 846.340000 1653.090000 846.820000 ;
+ RECT 1655.755000 846.340000 1657.020000 846.820000 ;
+ RECT 1650.860000 943.100000 1850.960000 944.100000 ;
+ RECT 1650.860000 747.530000 1850.960000 748.530000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 746.280000 1653.090000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 945.540000 1653.090000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 746.280000 1849.730000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 945.540000 1849.730000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 747.530000 1651.860000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 747.530000 1850.960000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 943.100000 1651.860000 944.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 943.100000 1850.960000 944.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 738.560000 1657.020000 739.040000 ;
+ RECT 1655.755000 727.680000 1657.020000 728.160000 ;
+ RECT 1655.755000 733.120000 1657.020000 733.600000 ;
+ RECT 1655.755000 722.240000 1657.020000 722.720000 ;
+ RECT 1655.755000 716.800000 1657.020000 717.280000 ;
+ RECT 1655.755000 711.360000 1657.020000 711.840000 ;
+ RECT 1655.755000 705.920000 1657.020000 706.400000 ;
+ RECT 1655.755000 700.480000 1657.020000 700.960000 ;
+ RECT 1655.755000 695.040000 1657.020000 695.520000 ;
+ RECT 1655.755000 684.160000 1657.020000 684.640000 ;
+ RECT 1655.755000 689.600000 1657.020000 690.080000 ;
+ RECT 1655.755000 678.720000 1657.020000 679.200000 ;
+ RECT 1655.755000 673.280000 1657.020000 673.760000 ;
+ RECT 1655.755000 667.840000 1657.020000 668.320000 ;
+ RECT 1655.755000 662.400000 1657.020000 662.880000 ;
+ RECT 1655.755000 656.960000 1657.020000 657.440000 ;
+ RECT 1655.755000 651.520000 1657.020000 652.000000 ;
+ RECT 1655.755000 640.640000 1657.020000 641.120000 ;
+ RECT 1655.755000 635.200000 1657.020000 635.680000 ;
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+ RECT 1655.755000 624.320000 1657.020000 624.800000 ;
+ RECT 1655.755000 618.880000 1657.020000 619.360000 ;
+ RECT 1655.755000 613.440000 1657.020000 613.920000 ;
+ RECT 1655.755000 602.560000 1657.020000 603.040000 ;
+ RECT 1655.755000 608.000000 1657.020000 608.480000 ;
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+ RECT 1655.755000 586.240000 1657.020000 586.720000 ;
+ RECT 1655.755000 580.800000 1657.020000 581.280000 ;
+ RECT 1655.755000 575.360000 1657.020000 575.840000 ;
+ RECT 1655.755000 569.920000 1657.020000 570.400000 ;
+ RECT 1655.755000 559.040000 1657.020000 559.520000 ;
+ RECT 1655.755000 564.480000 1657.020000 564.960000 ;
+ RECT 1655.755000 553.600000 1657.020000 554.080000 ;
+ RECT 1655.755000 646.080000 1657.020000 646.560000 ;
+ RECT 1835.920000 547.270000 1837.020000 743.840000 ;
+ RECT 1790.920000 547.270000 1792.020000 743.840000 ;
+ RECT 1848.730000 546.020000 1849.730000 746.280000 ;
+ RECT 1745.920000 547.270000 1747.020000 743.840000 ;
+ RECT 1700.920000 547.270000 1702.020000 743.840000 ;
+ RECT 1655.920000 547.270000 1657.020000 743.840000 ;
+ RECT 1652.090000 546.020000 1653.090000 746.280000 ;
+ LAYER met3 ;
+ RECT 1835.920000 738.560000 1837.020000 739.040000 ;
+ RECT 1848.730000 738.560000 1849.730000 739.040000 ;
+ RECT 1848.730000 727.680000 1849.730000 728.160000 ;
+ RECT 1848.730000 722.240000 1849.730000 722.720000 ;
+ RECT 1848.730000 733.120000 1849.730000 733.600000 ;
+ RECT 1835.920000 733.120000 1837.020000 733.600000 ;
+ RECT 1835.920000 727.680000 1837.020000 728.160000 ;
+ RECT 1835.920000 722.240000 1837.020000 722.720000 ;
+ RECT 1835.920000 711.360000 1837.020000 711.840000 ;
+ RECT 1835.920000 716.800000 1837.020000 717.280000 ;
+ RECT 1848.730000 711.360000 1849.730000 711.840000 ;
+ RECT 1848.730000 716.800000 1849.730000 717.280000 ;
+ RECT 1835.920000 700.480000 1837.020000 700.960000 ;
+ RECT 1835.920000 705.920000 1837.020000 706.400000 ;
+ RECT 1848.730000 700.480000 1849.730000 700.960000 ;
+ RECT 1848.730000 705.920000 1849.730000 706.400000 ;
+ RECT 1790.920000 722.240000 1792.020000 722.720000 ;
+ RECT 1790.920000 727.680000 1792.020000 728.160000 ;
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+ RECT 1790.920000 705.920000 1792.020000 706.400000 ;
+ RECT 1790.920000 700.480000 1792.020000 700.960000 ;
+ RECT 1790.920000 711.360000 1792.020000 711.840000 ;
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+ RECT 1848.730000 689.600000 1849.730000 690.080000 ;
+ RECT 1848.730000 684.160000 1849.730000 684.640000 ;
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+ RECT 1835.920000 684.160000 1837.020000 684.640000 ;
+ RECT 1835.920000 673.280000 1837.020000 673.760000 ;
+ RECT 1835.920000 678.720000 1837.020000 679.200000 ;
+ RECT 1848.730000 673.280000 1849.730000 673.760000 ;
+ RECT 1848.730000 678.720000 1849.730000 679.200000 ;
+ RECT 1848.730000 662.400000 1849.730000 662.880000 ;
+ RECT 1848.730000 667.840000 1849.730000 668.320000 ;
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+ RECT 1848.730000 651.520000 1849.730000 652.000000 ;
+ RECT 1848.730000 656.960000 1849.730000 657.440000 ;
+ RECT 1790.920000 673.280000 1792.020000 673.760000 ;
+ RECT 1790.920000 678.720000 1792.020000 679.200000 ;
+ RECT 1790.920000 684.160000 1792.020000 684.640000 ;
+ RECT 1790.920000 689.600000 1792.020000 690.080000 ;
+ RECT 1790.920000 695.040000 1792.020000 695.520000 ;
+ RECT 1790.920000 651.520000 1792.020000 652.000000 ;
+ RECT 1790.920000 656.960000 1792.020000 657.440000 ;
+ RECT 1790.920000 662.400000 1792.020000 662.880000 ;
+ RECT 1790.920000 667.840000 1792.020000 668.320000 ;
+ RECT 1745.920000 727.680000 1747.020000 728.160000 ;
+ RECT 1745.920000 722.240000 1747.020000 722.720000 ;
+ RECT 1745.920000 733.120000 1747.020000 733.600000 ;
+ RECT 1745.920000 738.560000 1747.020000 739.040000 ;
+ RECT 1700.920000 722.240000 1702.020000 722.720000 ;
+ RECT 1700.920000 727.680000 1702.020000 728.160000 ;
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+ RECT 1745.920000 700.480000 1747.020000 700.960000 ;
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+ RECT 1745.920000 711.360000 1747.020000 711.840000 ;
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+ RECT 1700.920000 700.480000 1702.020000 700.960000 ;
+ RECT 1700.920000 705.920000 1702.020000 706.400000 ;
+ RECT 1700.920000 711.360000 1702.020000 711.840000 ;
+ RECT 1700.920000 716.800000 1702.020000 717.280000 ;
+ RECT 1652.090000 738.560000 1653.090000 739.040000 ;
+ RECT 1655.755000 738.560000 1657.020000 739.040000 ;
+ RECT 1652.090000 727.680000 1653.090000 728.160000 ;
+ RECT 1655.755000 727.680000 1657.020000 728.160000 ;
+ RECT 1652.090000 733.120000 1653.090000 733.600000 ;
+ RECT 1655.755000 733.120000 1657.020000 733.600000 ;
+ RECT 1652.090000 722.240000 1653.090000 722.720000 ;
+ RECT 1655.755000 722.240000 1657.020000 722.720000 ;
+ RECT 1652.090000 716.800000 1653.090000 717.280000 ;
+ RECT 1655.755000 716.800000 1657.020000 717.280000 ;
+ RECT 1652.090000 711.360000 1653.090000 711.840000 ;
+ RECT 1655.755000 711.360000 1657.020000 711.840000 ;
+ RECT 1652.090000 705.920000 1653.090000 706.400000 ;
+ RECT 1655.755000 705.920000 1657.020000 706.400000 ;
+ RECT 1652.090000 700.480000 1653.090000 700.960000 ;
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+ RECT 1745.920000 673.280000 1747.020000 673.760000 ;
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+ RECT 1745.920000 667.840000 1747.020000 668.320000 ;
+ RECT 1700.920000 651.520000 1702.020000 652.000000 ;
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+ RECT 1700.920000 662.400000 1702.020000 662.880000 ;
+ RECT 1700.920000 667.840000 1702.020000 668.320000 ;
+ RECT 1652.090000 695.040000 1653.090000 695.520000 ;
+ RECT 1655.755000 695.040000 1657.020000 695.520000 ;
+ RECT 1652.090000 684.160000 1653.090000 684.640000 ;
+ RECT 1655.755000 684.160000 1657.020000 684.640000 ;
+ RECT 1652.090000 689.600000 1653.090000 690.080000 ;
+ RECT 1655.755000 689.600000 1657.020000 690.080000 ;
+ RECT 1652.090000 678.720000 1653.090000 679.200000 ;
+ RECT 1655.755000 678.720000 1657.020000 679.200000 ;
+ RECT 1652.090000 673.280000 1653.090000 673.760000 ;
+ RECT 1655.755000 673.280000 1657.020000 673.760000 ;
+ RECT 1652.090000 667.840000 1653.090000 668.320000 ;
+ RECT 1655.755000 667.840000 1657.020000 668.320000 ;
+ RECT 1652.090000 662.400000 1653.090000 662.880000 ;
+ RECT 1655.755000 662.400000 1657.020000 662.880000 ;
+ RECT 1652.090000 656.960000 1653.090000 657.440000 ;
+ RECT 1655.755000 656.960000 1657.020000 657.440000 ;
+ RECT 1652.090000 651.520000 1653.090000 652.000000 ;
+ RECT 1655.755000 651.520000 1657.020000 652.000000 ;
+ RECT 1835.920000 635.200000 1837.020000 635.680000 ;
+ RECT 1835.920000 640.640000 1837.020000 641.120000 ;
+ RECT 1848.730000 635.200000 1849.730000 635.680000 ;
+ RECT 1848.730000 640.640000 1849.730000 641.120000 ;
+ RECT 1848.730000 624.320000 1849.730000 624.800000 ;
+ RECT 1848.730000 629.760000 1849.730000 630.240000 ;
+ RECT 1835.920000 629.760000 1837.020000 630.240000 ;
+ RECT 1835.920000 624.320000 1837.020000 624.800000 ;
+ RECT 1835.920000 613.440000 1837.020000 613.920000 ;
+ RECT 1835.920000 618.880000 1837.020000 619.360000 ;
+ RECT 1848.730000 613.440000 1849.730000 613.920000 ;
+ RECT 1848.730000 618.880000 1849.730000 619.360000 ;
+ RECT 1848.730000 602.560000 1849.730000 603.040000 ;
+ RECT 1848.730000 597.120000 1849.730000 597.600000 ;
+ RECT 1848.730000 608.000000 1849.730000 608.480000 ;
+ RECT 1835.920000 608.000000 1837.020000 608.480000 ;
+ RECT 1835.920000 602.560000 1837.020000 603.040000 ;
+ RECT 1835.920000 597.120000 1837.020000 597.600000 ;
+ RECT 1790.920000 624.320000 1792.020000 624.800000 ;
+ RECT 1790.920000 629.760000 1792.020000 630.240000 ;
+ RECT 1790.920000 635.200000 1792.020000 635.680000 ;
+ RECT 1790.920000 640.640000 1792.020000 641.120000 ;
+ RECT 1790.920000 597.120000 1792.020000 597.600000 ;
+ RECT 1790.920000 602.560000 1792.020000 603.040000 ;
+ RECT 1790.920000 608.000000 1792.020000 608.480000 ;
+ RECT 1790.920000 613.440000 1792.020000 613.920000 ;
+ RECT 1790.920000 618.880000 1792.020000 619.360000 ;
+ RECT 1835.920000 586.240000 1837.020000 586.720000 ;
+ RECT 1835.920000 591.680000 1837.020000 592.160000 ;
+ RECT 1848.730000 586.240000 1849.730000 586.720000 ;
+ RECT 1848.730000 591.680000 1849.730000 592.160000 ;
+ RECT 1835.920000 575.360000 1837.020000 575.840000 ;
+ RECT 1835.920000 580.800000 1837.020000 581.280000 ;
+ RECT 1848.730000 575.360000 1849.730000 575.840000 ;
+ RECT 1848.730000 580.800000 1849.730000 581.280000 ;
+ RECT 1848.730000 564.480000 1849.730000 564.960000 ;
+ RECT 1848.730000 559.040000 1849.730000 559.520000 ;
+ RECT 1848.730000 569.920000 1849.730000 570.400000 ;
+ RECT 1835.920000 569.920000 1837.020000 570.400000 ;
+ RECT 1835.920000 564.480000 1837.020000 564.960000 ;
+ RECT 1835.920000 559.040000 1837.020000 559.520000 ;
+ RECT 1835.920000 553.600000 1837.020000 554.080000 ;
+ RECT 1848.730000 553.600000 1849.730000 554.080000 ;
+ RECT 1790.920000 575.360000 1792.020000 575.840000 ;
+ RECT 1790.920000 580.800000 1792.020000 581.280000 ;
+ RECT 1790.920000 586.240000 1792.020000 586.720000 ;
+ RECT 1790.920000 591.680000 1792.020000 592.160000 ;
+ RECT 1790.920000 553.600000 1792.020000 554.080000 ;
+ RECT 1790.920000 559.040000 1792.020000 559.520000 ;
+ RECT 1790.920000 564.480000 1792.020000 564.960000 ;
+ RECT 1790.920000 569.920000 1792.020000 570.400000 ;
+ RECT 1745.920000 624.320000 1747.020000 624.800000 ;
+ RECT 1745.920000 629.760000 1747.020000 630.240000 ;
+ RECT 1745.920000 635.200000 1747.020000 635.680000 ;
+ RECT 1745.920000 640.640000 1747.020000 641.120000 ;
+ RECT 1700.920000 624.320000 1702.020000 624.800000 ;
+ RECT 1700.920000 629.760000 1702.020000 630.240000 ;
+ RECT 1700.920000 635.200000 1702.020000 635.680000 ;
+ RECT 1700.920000 640.640000 1702.020000 641.120000 ;
+ RECT 1745.920000 597.120000 1747.020000 597.600000 ;
+ RECT 1745.920000 602.560000 1747.020000 603.040000 ;
+ RECT 1745.920000 608.000000 1747.020000 608.480000 ;
+ RECT 1745.920000 613.440000 1747.020000 613.920000 ;
+ RECT 1745.920000 618.880000 1747.020000 619.360000 ;
+ RECT 1700.920000 597.120000 1702.020000 597.600000 ;
+ RECT 1700.920000 602.560000 1702.020000 603.040000 ;
+ RECT 1700.920000 608.000000 1702.020000 608.480000 ;
+ RECT 1700.920000 613.440000 1702.020000 613.920000 ;
+ RECT 1700.920000 618.880000 1702.020000 619.360000 ;
+ RECT 1652.090000 640.640000 1653.090000 641.120000 ;
+ RECT 1655.755000 640.640000 1657.020000 641.120000 ;
+ RECT 1652.090000 635.200000 1653.090000 635.680000 ;
+ RECT 1655.755000 635.200000 1657.020000 635.680000 ;
+ RECT 1652.090000 629.760000 1653.090000 630.240000 ;
+ RECT 1655.755000 629.760000 1657.020000 630.240000 ;
+ RECT 1652.090000 624.320000 1653.090000 624.800000 ;
+ RECT 1655.755000 624.320000 1657.020000 624.800000 ;
+ RECT 1652.090000 618.880000 1653.090000 619.360000 ;
+ RECT 1655.755000 618.880000 1657.020000 619.360000 ;
+ RECT 1652.090000 613.440000 1653.090000 613.920000 ;
+ RECT 1655.755000 613.440000 1657.020000 613.920000 ;
+ RECT 1652.090000 602.560000 1653.090000 603.040000 ;
+ RECT 1655.755000 602.560000 1657.020000 603.040000 ;
+ RECT 1652.090000 608.000000 1653.090000 608.480000 ;
+ RECT 1655.755000 608.000000 1657.020000 608.480000 ;
+ RECT 1652.090000 597.120000 1653.090000 597.600000 ;
+ RECT 1655.755000 597.120000 1657.020000 597.600000 ;
+ RECT 1745.920000 575.360000 1747.020000 575.840000 ;
+ RECT 1745.920000 580.800000 1747.020000 581.280000 ;
+ RECT 1745.920000 586.240000 1747.020000 586.720000 ;
+ RECT 1745.920000 591.680000 1747.020000 592.160000 ;
+ RECT 1700.920000 575.360000 1702.020000 575.840000 ;
+ RECT 1700.920000 580.800000 1702.020000 581.280000 ;
+ RECT 1700.920000 586.240000 1702.020000 586.720000 ;
+ RECT 1700.920000 591.680000 1702.020000 592.160000 ;
+ RECT 1745.920000 553.600000 1747.020000 554.080000 ;
+ RECT 1745.920000 559.040000 1747.020000 559.520000 ;
+ RECT 1745.920000 564.480000 1747.020000 564.960000 ;
+ RECT 1745.920000 569.920000 1747.020000 570.400000 ;
+ RECT 1700.920000 553.600000 1702.020000 554.080000 ;
+ RECT 1700.920000 559.040000 1702.020000 559.520000 ;
+ RECT 1700.920000 564.480000 1702.020000 564.960000 ;
+ RECT 1700.920000 569.920000 1702.020000 570.400000 ;
+ RECT 1652.090000 591.680000 1653.090000 592.160000 ;
+ RECT 1655.755000 591.680000 1657.020000 592.160000 ;
+ RECT 1652.090000 586.240000 1653.090000 586.720000 ;
+ RECT 1655.755000 586.240000 1657.020000 586.720000 ;
+ RECT 1652.090000 580.800000 1653.090000 581.280000 ;
+ RECT 1655.755000 580.800000 1657.020000 581.280000 ;
+ RECT 1652.090000 575.360000 1653.090000 575.840000 ;
+ RECT 1655.755000 575.360000 1657.020000 575.840000 ;
+ RECT 1652.090000 569.920000 1653.090000 570.400000 ;
+ RECT 1655.755000 569.920000 1657.020000 570.400000 ;
+ RECT 1652.090000 559.040000 1653.090000 559.520000 ;
+ RECT 1655.755000 559.040000 1657.020000 559.520000 ;
+ RECT 1652.090000 564.480000 1653.090000 564.960000 ;
+ RECT 1655.755000 564.480000 1657.020000 564.960000 ;
+ RECT 1652.090000 553.600000 1653.090000 554.080000 ;
+ RECT 1655.755000 553.600000 1657.020000 554.080000 ;
+ RECT 1790.920000 646.080000 1792.020000 646.560000 ;
+ RECT 1835.920000 646.080000 1837.020000 646.560000 ;
+ RECT 1848.730000 646.080000 1849.730000 646.560000 ;
+ RECT 1700.920000 646.080000 1702.020000 646.560000 ;
+ RECT 1745.920000 646.080000 1747.020000 646.560000 ;
+ RECT 1652.090000 646.080000 1653.090000 646.560000 ;
+ RECT 1655.755000 646.080000 1657.020000 646.560000 ;
+ RECT 1650.860000 742.840000 1850.960000 743.840000 ;
+ RECT 1650.860000 547.270000 1850.960000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 546.020000 1653.090000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 745.280000 1653.090000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 546.020000 1849.730000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 745.280000 1849.730000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 547.270000 1651.860000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 547.270000 1850.960000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 742.840000 1651.860000 743.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 742.840000 1850.960000 743.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 538.300000 1657.020000 538.780000 ;
+ RECT 1655.755000 527.420000 1657.020000 527.900000 ;
+ RECT 1655.755000 532.860000 1657.020000 533.340000 ;
+ RECT 1655.755000 521.980000 1657.020000 522.460000 ;
+ RECT 1655.755000 516.540000 1657.020000 517.020000 ;
+ RECT 1655.755000 511.100000 1657.020000 511.580000 ;
+ RECT 1655.755000 505.660000 1657.020000 506.140000 ;
+ RECT 1655.755000 500.220000 1657.020000 500.700000 ;
+ RECT 1655.755000 494.780000 1657.020000 495.260000 ;
+ RECT 1655.755000 483.900000 1657.020000 484.380000 ;
+ RECT 1655.755000 489.340000 1657.020000 489.820000 ;
+ RECT 1655.755000 478.460000 1657.020000 478.940000 ;
+ RECT 1655.755000 473.020000 1657.020000 473.500000 ;
+ RECT 1655.755000 467.580000 1657.020000 468.060000 ;
+ RECT 1655.755000 462.140000 1657.020000 462.620000 ;
+ RECT 1655.755000 456.700000 1657.020000 457.180000 ;
+ RECT 1655.755000 451.260000 1657.020000 451.740000 ;
+ RECT 1655.755000 440.380000 1657.020000 440.860000 ;
+ RECT 1655.755000 434.940000 1657.020000 435.420000 ;
+ RECT 1655.755000 429.500000 1657.020000 429.980000 ;
+ RECT 1655.755000 424.060000 1657.020000 424.540000 ;
+ RECT 1655.755000 418.620000 1657.020000 419.100000 ;
+ RECT 1655.755000 413.180000 1657.020000 413.660000 ;
+ RECT 1655.755000 402.300000 1657.020000 402.780000 ;
+ RECT 1655.755000 407.740000 1657.020000 408.220000 ;
+ RECT 1655.755000 396.860000 1657.020000 397.340000 ;
+ RECT 1655.755000 391.420000 1657.020000 391.900000 ;
+ RECT 1655.755000 385.980000 1657.020000 386.460000 ;
+ RECT 1655.755000 380.540000 1657.020000 381.020000 ;
+ RECT 1655.755000 375.100000 1657.020000 375.580000 ;
+ RECT 1655.755000 369.660000 1657.020000 370.140000 ;
+ RECT 1655.755000 358.780000 1657.020000 359.260000 ;
+ RECT 1655.755000 364.220000 1657.020000 364.700000 ;
+ RECT 1655.755000 353.340000 1657.020000 353.820000 ;
+ RECT 1655.755000 445.820000 1657.020000 446.300000 ;
+ RECT 1835.920000 347.010000 1837.020000 543.580000 ;
+ RECT 1790.920000 347.010000 1792.020000 543.580000 ;
+ RECT 1848.730000 345.760000 1849.730000 546.020000 ;
+ RECT 1745.920000 347.010000 1747.020000 543.580000 ;
+ RECT 1700.920000 347.010000 1702.020000 543.580000 ;
+ RECT 1655.920000 347.010000 1657.020000 543.580000 ;
+ RECT 1652.090000 345.760000 1653.090000 546.020000 ;
+ LAYER met3 ;
+ RECT 1835.920000 538.300000 1837.020000 538.780000 ;
+ RECT 1848.730000 538.300000 1849.730000 538.780000 ;
+ RECT 1848.730000 527.420000 1849.730000 527.900000 ;
+ RECT 1848.730000 521.980000 1849.730000 522.460000 ;
+ RECT 1848.730000 532.860000 1849.730000 533.340000 ;
+ RECT 1835.920000 532.860000 1837.020000 533.340000 ;
+ RECT 1835.920000 527.420000 1837.020000 527.900000 ;
+ RECT 1835.920000 521.980000 1837.020000 522.460000 ;
+ RECT 1835.920000 511.100000 1837.020000 511.580000 ;
+ RECT 1835.920000 516.540000 1837.020000 517.020000 ;
+ RECT 1848.730000 511.100000 1849.730000 511.580000 ;
+ RECT 1848.730000 516.540000 1849.730000 517.020000 ;
+ RECT 1835.920000 500.220000 1837.020000 500.700000 ;
+ RECT 1835.920000 505.660000 1837.020000 506.140000 ;
+ RECT 1848.730000 500.220000 1849.730000 500.700000 ;
+ RECT 1848.730000 505.660000 1849.730000 506.140000 ;
+ RECT 1790.920000 521.980000 1792.020000 522.460000 ;
+ RECT 1790.920000 527.420000 1792.020000 527.900000 ;
+ RECT 1790.920000 532.860000 1792.020000 533.340000 ;
+ RECT 1790.920000 538.300000 1792.020000 538.780000 ;
+ RECT 1790.920000 505.660000 1792.020000 506.140000 ;
+ RECT 1790.920000 500.220000 1792.020000 500.700000 ;
+ RECT 1790.920000 511.100000 1792.020000 511.580000 ;
+ RECT 1790.920000 516.540000 1792.020000 517.020000 ;
+ RECT 1848.730000 489.340000 1849.730000 489.820000 ;
+ RECT 1848.730000 483.900000 1849.730000 484.380000 ;
+ RECT 1848.730000 494.780000 1849.730000 495.260000 ;
+ RECT 1835.920000 494.780000 1837.020000 495.260000 ;
+ RECT 1835.920000 489.340000 1837.020000 489.820000 ;
+ RECT 1835.920000 483.900000 1837.020000 484.380000 ;
+ RECT 1835.920000 473.020000 1837.020000 473.500000 ;
+ RECT 1835.920000 478.460000 1837.020000 478.940000 ;
+ RECT 1848.730000 473.020000 1849.730000 473.500000 ;
+ RECT 1848.730000 478.460000 1849.730000 478.940000 ;
+ RECT 1848.730000 462.140000 1849.730000 462.620000 ;
+ RECT 1848.730000 467.580000 1849.730000 468.060000 ;
+ RECT 1835.920000 467.580000 1837.020000 468.060000 ;
+ RECT 1835.920000 462.140000 1837.020000 462.620000 ;
+ RECT 1835.920000 451.260000 1837.020000 451.740000 ;
+ RECT 1835.920000 456.700000 1837.020000 457.180000 ;
+ RECT 1848.730000 451.260000 1849.730000 451.740000 ;
+ RECT 1848.730000 456.700000 1849.730000 457.180000 ;
+ RECT 1790.920000 473.020000 1792.020000 473.500000 ;
+ RECT 1790.920000 478.460000 1792.020000 478.940000 ;
+ RECT 1790.920000 483.900000 1792.020000 484.380000 ;
+ RECT 1790.920000 489.340000 1792.020000 489.820000 ;
+ RECT 1790.920000 494.780000 1792.020000 495.260000 ;
+ RECT 1790.920000 451.260000 1792.020000 451.740000 ;
+ RECT 1790.920000 456.700000 1792.020000 457.180000 ;
+ RECT 1790.920000 462.140000 1792.020000 462.620000 ;
+ RECT 1790.920000 467.580000 1792.020000 468.060000 ;
+ RECT 1745.920000 527.420000 1747.020000 527.900000 ;
+ RECT 1745.920000 521.980000 1747.020000 522.460000 ;
+ RECT 1745.920000 532.860000 1747.020000 533.340000 ;
+ RECT 1745.920000 538.300000 1747.020000 538.780000 ;
+ RECT 1700.920000 521.980000 1702.020000 522.460000 ;
+ RECT 1700.920000 527.420000 1702.020000 527.900000 ;
+ RECT 1700.920000 532.860000 1702.020000 533.340000 ;
+ RECT 1700.920000 538.300000 1702.020000 538.780000 ;
+ RECT 1745.920000 500.220000 1747.020000 500.700000 ;
+ RECT 1745.920000 505.660000 1747.020000 506.140000 ;
+ RECT 1745.920000 511.100000 1747.020000 511.580000 ;
+ RECT 1745.920000 516.540000 1747.020000 517.020000 ;
+ RECT 1700.920000 500.220000 1702.020000 500.700000 ;
+ RECT 1700.920000 505.660000 1702.020000 506.140000 ;
+ RECT 1700.920000 511.100000 1702.020000 511.580000 ;
+ RECT 1700.920000 516.540000 1702.020000 517.020000 ;
+ RECT 1652.090000 538.300000 1653.090000 538.780000 ;
+ RECT 1655.755000 538.300000 1657.020000 538.780000 ;
+ RECT 1652.090000 527.420000 1653.090000 527.900000 ;
+ RECT 1655.755000 527.420000 1657.020000 527.900000 ;
+ RECT 1652.090000 532.860000 1653.090000 533.340000 ;
+ RECT 1655.755000 532.860000 1657.020000 533.340000 ;
+ RECT 1652.090000 521.980000 1653.090000 522.460000 ;
+ RECT 1655.755000 521.980000 1657.020000 522.460000 ;
+ RECT 1652.090000 516.540000 1653.090000 517.020000 ;
+ RECT 1655.755000 516.540000 1657.020000 517.020000 ;
+ RECT 1652.090000 511.100000 1653.090000 511.580000 ;
+ RECT 1655.755000 511.100000 1657.020000 511.580000 ;
+ RECT 1652.090000 505.660000 1653.090000 506.140000 ;
+ RECT 1655.755000 505.660000 1657.020000 506.140000 ;
+ RECT 1652.090000 500.220000 1653.090000 500.700000 ;
+ RECT 1655.755000 500.220000 1657.020000 500.700000 ;
+ RECT 1745.920000 473.020000 1747.020000 473.500000 ;
+ RECT 1745.920000 478.460000 1747.020000 478.940000 ;
+ RECT 1745.920000 483.900000 1747.020000 484.380000 ;
+ RECT 1745.920000 489.340000 1747.020000 489.820000 ;
+ RECT 1745.920000 494.780000 1747.020000 495.260000 ;
+ RECT 1700.920000 473.020000 1702.020000 473.500000 ;
+ RECT 1700.920000 478.460000 1702.020000 478.940000 ;
+ RECT 1700.920000 483.900000 1702.020000 484.380000 ;
+ RECT 1700.920000 489.340000 1702.020000 489.820000 ;
+ RECT 1700.920000 494.780000 1702.020000 495.260000 ;
+ RECT 1745.920000 451.260000 1747.020000 451.740000 ;
+ RECT 1745.920000 456.700000 1747.020000 457.180000 ;
+ RECT 1745.920000 462.140000 1747.020000 462.620000 ;
+ RECT 1745.920000 467.580000 1747.020000 468.060000 ;
+ RECT 1700.920000 451.260000 1702.020000 451.740000 ;
+ RECT 1700.920000 456.700000 1702.020000 457.180000 ;
+ RECT 1700.920000 462.140000 1702.020000 462.620000 ;
+ RECT 1700.920000 467.580000 1702.020000 468.060000 ;
+ RECT 1652.090000 494.780000 1653.090000 495.260000 ;
+ RECT 1655.755000 494.780000 1657.020000 495.260000 ;
+ RECT 1652.090000 483.900000 1653.090000 484.380000 ;
+ RECT 1655.755000 483.900000 1657.020000 484.380000 ;
+ RECT 1652.090000 489.340000 1653.090000 489.820000 ;
+ RECT 1655.755000 489.340000 1657.020000 489.820000 ;
+ RECT 1652.090000 478.460000 1653.090000 478.940000 ;
+ RECT 1655.755000 478.460000 1657.020000 478.940000 ;
+ RECT 1652.090000 473.020000 1653.090000 473.500000 ;
+ RECT 1655.755000 473.020000 1657.020000 473.500000 ;
+ RECT 1652.090000 467.580000 1653.090000 468.060000 ;
+ RECT 1655.755000 467.580000 1657.020000 468.060000 ;
+ RECT 1652.090000 462.140000 1653.090000 462.620000 ;
+ RECT 1655.755000 462.140000 1657.020000 462.620000 ;
+ RECT 1652.090000 456.700000 1653.090000 457.180000 ;
+ RECT 1655.755000 456.700000 1657.020000 457.180000 ;
+ RECT 1652.090000 451.260000 1653.090000 451.740000 ;
+ RECT 1655.755000 451.260000 1657.020000 451.740000 ;
+ RECT 1835.920000 434.940000 1837.020000 435.420000 ;
+ RECT 1835.920000 440.380000 1837.020000 440.860000 ;
+ RECT 1848.730000 434.940000 1849.730000 435.420000 ;
+ RECT 1848.730000 440.380000 1849.730000 440.860000 ;
+ RECT 1848.730000 424.060000 1849.730000 424.540000 ;
+ RECT 1848.730000 429.500000 1849.730000 429.980000 ;
+ RECT 1835.920000 429.500000 1837.020000 429.980000 ;
+ RECT 1835.920000 424.060000 1837.020000 424.540000 ;
+ RECT 1835.920000 413.180000 1837.020000 413.660000 ;
+ RECT 1835.920000 418.620000 1837.020000 419.100000 ;
+ RECT 1848.730000 413.180000 1849.730000 413.660000 ;
+ RECT 1848.730000 418.620000 1849.730000 419.100000 ;
+ RECT 1848.730000 402.300000 1849.730000 402.780000 ;
+ RECT 1848.730000 396.860000 1849.730000 397.340000 ;
+ RECT 1848.730000 407.740000 1849.730000 408.220000 ;
+ RECT 1835.920000 407.740000 1837.020000 408.220000 ;
+ RECT 1835.920000 402.300000 1837.020000 402.780000 ;
+ RECT 1835.920000 396.860000 1837.020000 397.340000 ;
+ RECT 1790.920000 424.060000 1792.020000 424.540000 ;
+ RECT 1790.920000 429.500000 1792.020000 429.980000 ;
+ RECT 1790.920000 434.940000 1792.020000 435.420000 ;
+ RECT 1790.920000 440.380000 1792.020000 440.860000 ;
+ RECT 1790.920000 396.860000 1792.020000 397.340000 ;
+ RECT 1790.920000 402.300000 1792.020000 402.780000 ;
+ RECT 1790.920000 407.740000 1792.020000 408.220000 ;
+ RECT 1790.920000 413.180000 1792.020000 413.660000 ;
+ RECT 1790.920000 418.620000 1792.020000 419.100000 ;
+ RECT 1835.920000 385.980000 1837.020000 386.460000 ;
+ RECT 1835.920000 391.420000 1837.020000 391.900000 ;
+ RECT 1848.730000 385.980000 1849.730000 386.460000 ;
+ RECT 1848.730000 391.420000 1849.730000 391.900000 ;
+ RECT 1835.920000 375.100000 1837.020000 375.580000 ;
+ RECT 1835.920000 380.540000 1837.020000 381.020000 ;
+ RECT 1848.730000 375.100000 1849.730000 375.580000 ;
+ RECT 1848.730000 380.540000 1849.730000 381.020000 ;
+ RECT 1848.730000 364.220000 1849.730000 364.700000 ;
+ RECT 1848.730000 358.780000 1849.730000 359.260000 ;
+ RECT 1848.730000 369.660000 1849.730000 370.140000 ;
+ RECT 1835.920000 369.660000 1837.020000 370.140000 ;
+ RECT 1835.920000 364.220000 1837.020000 364.700000 ;
+ RECT 1835.920000 358.780000 1837.020000 359.260000 ;
+ RECT 1835.920000 353.340000 1837.020000 353.820000 ;
+ RECT 1848.730000 353.340000 1849.730000 353.820000 ;
+ RECT 1790.920000 375.100000 1792.020000 375.580000 ;
+ RECT 1790.920000 380.540000 1792.020000 381.020000 ;
+ RECT 1790.920000 385.980000 1792.020000 386.460000 ;
+ RECT 1790.920000 391.420000 1792.020000 391.900000 ;
+ RECT 1790.920000 353.340000 1792.020000 353.820000 ;
+ RECT 1790.920000 358.780000 1792.020000 359.260000 ;
+ RECT 1790.920000 364.220000 1792.020000 364.700000 ;
+ RECT 1790.920000 369.660000 1792.020000 370.140000 ;
+ RECT 1745.920000 424.060000 1747.020000 424.540000 ;
+ RECT 1745.920000 429.500000 1747.020000 429.980000 ;
+ RECT 1745.920000 434.940000 1747.020000 435.420000 ;
+ RECT 1745.920000 440.380000 1747.020000 440.860000 ;
+ RECT 1700.920000 424.060000 1702.020000 424.540000 ;
+ RECT 1700.920000 429.500000 1702.020000 429.980000 ;
+ RECT 1700.920000 434.940000 1702.020000 435.420000 ;
+ RECT 1700.920000 440.380000 1702.020000 440.860000 ;
+ RECT 1745.920000 396.860000 1747.020000 397.340000 ;
+ RECT 1745.920000 402.300000 1747.020000 402.780000 ;
+ RECT 1745.920000 407.740000 1747.020000 408.220000 ;
+ RECT 1745.920000 413.180000 1747.020000 413.660000 ;
+ RECT 1745.920000 418.620000 1747.020000 419.100000 ;
+ RECT 1700.920000 396.860000 1702.020000 397.340000 ;
+ RECT 1700.920000 402.300000 1702.020000 402.780000 ;
+ RECT 1700.920000 407.740000 1702.020000 408.220000 ;
+ RECT 1700.920000 413.180000 1702.020000 413.660000 ;
+ RECT 1700.920000 418.620000 1702.020000 419.100000 ;
+ RECT 1652.090000 440.380000 1653.090000 440.860000 ;
+ RECT 1655.755000 440.380000 1657.020000 440.860000 ;
+ RECT 1652.090000 434.940000 1653.090000 435.420000 ;
+ RECT 1655.755000 434.940000 1657.020000 435.420000 ;
+ RECT 1652.090000 429.500000 1653.090000 429.980000 ;
+ RECT 1655.755000 429.500000 1657.020000 429.980000 ;
+ RECT 1652.090000 424.060000 1653.090000 424.540000 ;
+ RECT 1655.755000 424.060000 1657.020000 424.540000 ;
+ RECT 1652.090000 418.620000 1653.090000 419.100000 ;
+ RECT 1655.755000 418.620000 1657.020000 419.100000 ;
+ RECT 1652.090000 413.180000 1653.090000 413.660000 ;
+ RECT 1655.755000 413.180000 1657.020000 413.660000 ;
+ RECT 1652.090000 402.300000 1653.090000 402.780000 ;
+ RECT 1655.755000 402.300000 1657.020000 402.780000 ;
+ RECT 1652.090000 407.740000 1653.090000 408.220000 ;
+ RECT 1655.755000 407.740000 1657.020000 408.220000 ;
+ RECT 1652.090000 396.860000 1653.090000 397.340000 ;
+ RECT 1655.755000 396.860000 1657.020000 397.340000 ;
+ RECT 1745.920000 375.100000 1747.020000 375.580000 ;
+ RECT 1745.920000 380.540000 1747.020000 381.020000 ;
+ RECT 1745.920000 385.980000 1747.020000 386.460000 ;
+ RECT 1745.920000 391.420000 1747.020000 391.900000 ;
+ RECT 1700.920000 375.100000 1702.020000 375.580000 ;
+ RECT 1700.920000 380.540000 1702.020000 381.020000 ;
+ RECT 1700.920000 385.980000 1702.020000 386.460000 ;
+ RECT 1700.920000 391.420000 1702.020000 391.900000 ;
+ RECT 1745.920000 353.340000 1747.020000 353.820000 ;
+ RECT 1745.920000 358.780000 1747.020000 359.260000 ;
+ RECT 1745.920000 364.220000 1747.020000 364.700000 ;
+ RECT 1745.920000 369.660000 1747.020000 370.140000 ;
+ RECT 1700.920000 353.340000 1702.020000 353.820000 ;
+ RECT 1700.920000 358.780000 1702.020000 359.260000 ;
+ RECT 1700.920000 364.220000 1702.020000 364.700000 ;
+ RECT 1700.920000 369.660000 1702.020000 370.140000 ;
+ RECT 1652.090000 391.420000 1653.090000 391.900000 ;
+ RECT 1655.755000 391.420000 1657.020000 391.900000 ;
+ RECT 1652.090000 385.980000 1653.090000 386.460000 ;
+ RECT 1655.755000 385.980000 1657.020000 386.460000 ;
+ RECT 1652.090000 380.540000 1653.090000 381.020000 ;
+ RECT 1655.755000 380.540000 1657.020000 381.020000 ;
+ RECT 1652.090000 375.100000 1653.090000 375.580000 ;
+ RECT 1655.755000 375.100000 1657.020000 375.580000 ;
+ RECT 1652.090000 369.660000 1653.090000 370.140000 ;
+ RECT 1655.755000 369.660000 1657.020000 370.140000 ;
+ RECT 1652.090000 358.780000 1653.090000 359.260000 ;
+ RECT 1655.755000 358.780000 1657.020000 359.260000 ;
+ RECT 1652.090000 364.220000 1653.090000 364.700000 ;
+ RECT 1655.755000 364.220000 1657.020000 364.700000 ;
+ RECT 1652.090000 353.340000 1653.090000 353.820000 ;
+ RECT 1655.755000 353.340000 1657.020000 353.820000 ;
+ RECT 1790.920000 445.820000 1792.020000 446.300000 ;
+ RECT 1835.920000 445.820000 1837.020000 446.300000 ;
+ RECT 1848.730000 445.820000 1849.730000 446.300000 ;
+ RECT 1700.920000 445.820000 1702.020000 446.300000 ;
+ RECT 1745.920000 445.820000 1747.020000 446.300000 ;
+ RECT 1652.090000 445.820000 1653.090000 446.300000 ;
+ RECT 1655.755000 445.820000 1657.020000 446.300000 ;
+ RECT 1650.860000 542.580000 1850.960000 543.580000 ;
+ RECT 1650.860000 347.010000 1850.960000 348.010000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 345.760000 1653.090000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 545.020000 1653.090000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 345.760000 1849.730000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 545.020000 1849.730000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 347.010000 1651.860000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 347.010000 1850.960000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 542.580000 1651.860000 543.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 542.580000 1850.960000 543.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 338.040000 1657.020000 338.520000 ;
+ RECT 1655.755000 327.160000 1657.020000 327.640000 ;
+ RECT 1655.755000 332.600000 1657.020000 333.080000 ;
+ RECT 1655.755000 321.720000 1657.020000 322.200000 ;
+ RECT 1655.755000 316.280000 1657.020000 316.760000 ;
+ RECT 1655.755000 310.840000 1657.020000 311.320000 ;
+ RECT 1655.755000 305.400000 1657.020000 305.880000 ;
+ RECT 1655.755000 299.960000 1657.020000 300.440000 ;
+ RECT 1655.755000 294.520000 1657.020000 295.000000 ;
+ RECT 1655.755000 283.640000 1657.020000 284.120000 ;
+ RECT 1655.755000 289.080000 1657.020000 289.560000 ;
+ RECT 1655.755000 278.200000 1657.020000 278.680000 ;
+ RECT 1655.755000 272.760000 1657.020000 273.240000 ;
+ RECT 1655.755000 267.320000 1657.020000 267.800000 ;
+ RECT 1655.755000 261.880000 1657.020000 262.360000 ;
+ RECT 1655.755000 256.440000 1657.020000 256.920000 ;
+ RECT 1655.755000 251.000000 1657.020000 251.480000 ;
+ RECT 1655.755000 240.120000 1657.020000 240.600000 ;
+ RECT 1655.755000 234.680000 1657.020000 235.160000 ;
+ RECT 1655.755000 229.240000 1657.020000 229.720000 ;
+ RECT 1655.755000 223.800000 1657.020000 224.280000 ;
+ RECT 1655.755000 218.360000 1657.020000 218.840000 ;
+ RECT 1655.755000 212.920000 1657.020000 213.400000 ;
+ RECT 1655.755000 202.040000 1657.020000 202.520000 ;
+ RECT 1655.755000 207.480000 1657.020000 207.960000 ;
+ RECT 1655.755000 196.600000 1657.020000 197.080000 ;
+ RECT 1655.755000 191.160000 1657.020000 191.640000 ;
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+ RECT 1655.755000 174.840000 1657.020000 175.320000 ;
+ RECT 1655.755000 169.400000 1657.020000 169.880000 ;
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+ RECT 1655.755000 163.960000 1657.020000 164.440000 ;
+ RECT 1655.755000 153.080000 1657.020000 153.560000 ;
+ RECT 1655.755000 245.560000 1657.020000 246.040000 ;
+ RECT 1835.920000 146.750000 1837.020000 343.320000 ;
+ RECT 1790.920000 146.750000 1792.020000 343.320000 ;
+ RECT 1848.730000 145.500000 1849.730000 345.760000 ;
+ RECT 1745.920000 146.750000 1747.020000 343.320000 ;
+ RECT 1700.920000 146.750000 1702.020000 343.320000 ;
+ RECT 1655.920000 146.750000 1657.020000 343.320000 ;
+ RECT 1652.090000 145.500000 1653.090000 345.760000 ;
+ LAYER met3 ;
+ RECT 1835.920000 338.040000 1837.020000 338.520000 ;
+ RECT 1848.730000 338.040000 1849.730000 338.520000 ;
+ RECT 1848.730000 327.160000 1849.730000 327.640000 ;
+ RECT 1848.730000 321.720000 1849.730000 322.200000 ;
+ RECT 1848.730000 332.600000 1849.730000 333.080000 ;
+ RECT 1835.920000 332.600000 1837.020000 333.080000 ;
+ RECT 1835.920000 327.160000 1837.020000 327.640000 ;
+ RECT 1835.920000 321.720000 1837.020000 322.200000 ;
+ RECT 1835.920000 310.840000 1837.020000 311.320000 ;
+ RECT 1835.920000 316.280000 1837.020000 316.760000 ;
+ RECT 1848.730000 310.840000 1849.730000 311.320000 ;
+ RECT 1848.730000 316.280000 1849.730000 316.760000 ;
+ RECT 1835.920000 299.960000 1837.020000 300.440000 ;
+ RECT 1835.920000 305.400000 1837.020000 305.880000 ;
+ RECT 1848.730000 299.960000 1849.730000 300.440000 ;
+ RECT 1848.730000 305.400000 1849.730000 305.880000 ;
+ RECT 1790.920000 321.720000 1792.020000 322.200000 ;
+ RECT 1790.920000 327.160000 1792.020000 327.640000 ;
+ RECT 1790.920000 332.600000 1792.020000 333.080000 ;
+ RECT 1790.920000 338.040000 1792.020000 338.520000 ;
+ RECT 1790.920000 305.400000 1792.020000 305.880000 ;
+ RECT 1790.920000 299.960000 1792.020000 300.440000 ;
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+ RECT 1790.920000 316.280000 1792.020000 316.760000 ;
+ RECT 1848.730000 289.080000 1849.730000 289.560000 ;
+ RECT 1848.730000 283.640000 1849.730000 284.120000 ;
+ RECT 1848.730000 294.520000 1849.730000 295.000000 ;
+ RECT 1835.920000 294.520000 1837.020000 295.000000 ;
+ RECT 1835.920000 289.080000 1837.020000 289.560000 ;
+ RECT 1835.920000 283.640000 1837.020000 284.120000 ;
+ RECT 1835.920000 272.760000 1837.020000 273.240000 ;
+ RECT 1835.920000 278.200000 1837.020000 278.680000 ;
+ RECT 1848.730000 272.760000 1849.730000 273.240000 ;
+ RECT 1848.730000 278.200000 1849.730000 278.680000 ;
+ RECT 1848.730000 261.880000 1849.730000 262.360000 ;
+ RECT 1848.730000 267.320000 1849.730000 267.800000 ;
+ RECT 1835.920000 267.320000 1837.020000 267.800000 ;
+ RECT 1835.920000 261.880000 1837.020000 262.360000 ;
+ RECT 1835.920000 251.000000 1837.020000 251.480000 ;
+ RECT 1835.920000 256.440000 1837.020000 256.920000 ;
+ RECT 1848.730000 251.000000 1849.730000 251.480000 ;
+ RECT 1848.730000 256.440000 1849.730000 256.920000 ;
+ RECT 1790.920000 272.760000 1792.020000 273.240000 ;
+ RECT 1790.920000 278.200000 1792.020000 278.680000 ;
+ RECT 1790.920000 283.640000 1792.020000 284.120000 ;
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+ RECT 1790.920000 251.000000 1792.020000 251.480000 ;
+ RECT 1790.920000 256.440000 1792.020000 256.920000 ;
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+ RECT 1745.920000 321.720000 1747.020000 322.200000 ;
+ RECT 1745.920000 332.600000 1747.020000 333.080000 ;
+ RECT 1745.920000 338.040000 1747.020000 338.520000 ;
+ RECT 1700.920000 321.720000 1702.020000 322.200000 ;
+ RECT 1700.920000 327.160000 1702.020000 327.640000 ;
+ RECT 1700.920000 332.600000 1702.020000 333.080000 ;
+ RECT 1700.920000 338.040000 1702.020000 338.520000 ;
+ RECT 1745.920000 299.960000 1747.020000 300.440000 ;
+ RECT 1745.920000 305.400000 1747.020000 305.880000 ;
+ RECT 1745.920000 310.840000 1747.020000 311.320000 ;
+ RECT 1745.920000 316.280000 1747.020000 316.760000 ;
+ RECT 1700.920000 299.960000 1702.020000 300.440000 ;
+ RECT 1700.920000 305.400000 1702.020000 305.880000 ;
+ RECT 1700.920000 310.840000 1702.020000 311.320000 ;
+ RECT 1700.920000 316.280000 1702.020000 316.760000 ;
+ RECT 1652.090000 338.040000 1653.090000 338.520000 ;
+ RECT 1655.755000 338.040000 1657.020000 338.520000 ;
+ RECT 1652.090000 327.160000 1653.090000 327.640000 ;
+ RECT 1655.755000 327.160000 1657.020000 327.640000 ;
+ RECT 1652.090000 332.600000 1653.090000 333.080000 ;
+ RECT 1655.755000 332.600000 1657.020000 333.080000 ;
+ RECT 1652.090000 321.720000 1653.090000 322.200000 ;
+ RECT 1655.755000 321.720000 1657.020000 322.200000 ;
+ RECT 1652.090000 316.280000 1653.090000 316.760000 ;
+ RECT 1655.755000 316.280000 1657.020000 316.760000 ;
+ RECT 1652.090000 310.840000 1653.090000 311.320000 ;
+ RECT 1655.755000 310.840000 1657.020000 311.320000 ;
+ RECT 1652.090000 305.400000 1653.090000 305.880000 ;
+ RECT 1655.755000 305.400000 1657.020000 305.880000 ;
+ RECT 1652.090000 299.960000 1653.090000 300.440000 ;
+ RECT 1655.755000 299.960000 1657.020000 300.440000 ;
+ RECT 1745.920000 272.760000 1747.020000 273.240000 ;
+ RECT 1745.920000 278.200000 1747.020000 278.680000 ;
+ RECT 1745.920000 283.640000 1747.020000 284.120000 ;
+ RECT 1745.920000 289.080000 1747.020000 289.560000 ;
+ RECT 1745.920000 294.520000 1747.020000 295.000000 ;
+ RECT 1700.920000 272.760000 1702.020000 273.240000 ;
+ RECT 1700.920000 278.200000 1702.020000 278.680000 ;
+ RECT 1700.920000 283.640000 1702.020000 284.120000 ;
+ RECT 1700.920000 289.080000 1702.020000 289.560000 ;
+ RECT 1700.920000 294.520000 1702.020000 295.000000 ;
+ RECT 1745.920000 251.000000 1747.020000 251.480000 ;
+ RECT 1745.920000 256.440000 1747.020000 256.920000 ;
+ RECT 1745.920000 261.880000 1747.020000 262.360000 ;
+ RECT 1745.920000 267.320000 1747.020000 267.800000 ;
+ RECT 1700.920000 251.000000 1702.020000 251.480000 ;
+ RECT 1700.920000 256.440000 1702.020000 256.920000 ;
+ RECT 1700.920000 261.880000 1702.020000 262.360000 ;
+ RECT 1700.920000 267.320000 1702.020000 267.800000 ;
+ RECT 1652.090000 294.520000 1653.090000 295.000000 ;
+ RECT 1655.755000 294.520000 1657.020000 295.000000 ;
+ RECT 1652.090000 283.640000 1653.090000 284.120000 ;
+ RECT 1655.755000 283.640000 1657.020000 284.120000 ;
+ RECT 1652.090000 289.080000 1653.090000 289.560000 ;
+ RECT 1655.755000 289.080000 1657.020000 289.560000 ;
+ RECT 1652.090000 278.200000 1653.090000 278.680000 ;
+ RECT 1655.755000 278.200000 1657.020000 278.680000 ;
+ RECT 1652.090000 272.760000 1653.090000 273.240000 ;
+ RECT 1655.755000 272.760000 1657.020000 273.240000 ;
+ RECT 1652.090000 267.320000 1653.090000 267.800000 ;
+ RECT 1655.755000 267.320000 1657.020000 267.800000 ;
+ RECT 1652.090000 261.880000 1653.090000 262.360000 ;
+ RECT 1655.755000 261.880000 1657.020000 262.360000 ;
+ RECT 1652.090000 256.440000 1653.090000 256.920000 ;
+ RECT 1655.755000 256.440000 1657.020000 256.920000 ;
+ RECT 1652.090000 251.000000 1653.090000 251.480000 ;
+ RECT 1655.755000 251.000000 1657.020000 251.480000 ;
+ RECT 1835.920000 234.680000 1837.020000 235.160000 ;
+ RECT 1835.920000 240.120000 1837.020000 240.600000 ;
+ RECT 1848.730000 234.680000 1849.730000 235.160000 ;
+ RECT 1848.730000 240.120000 1849.730000 240.600000 ;
+ RECT 1848.730000 223.800000 1849.730000 224.280000 ;
+ RECT 1848.730000 229.240000 1849.730000 229.720000 ;
+ RECT 1835.920000 229.240000 1837.020000 229.720000 ;
+ RECT 1835.920000 223.800000 1837.020000 224.280000 ;
+ RECT 1835.920000 212.920000 1837.020000 213.400000 ;
+ RECT 1835.920000 218.360000 1837.020000 218.840000 ;
+ RECT 1848.730000 212.920000 1849.730000 213.400000 ;
+ RECT 1848.730000 218.360000 1849.730000 218.840000 ;
+ RECT 1848.730000 202.040000 1849.730000 202.520000 ;
+ RECT 1848.730000 196.600000 1849.730000 197.080000 ;
+ RECT 1848.730000 207.480000 1849.730000 207.960000 ;
+ RECT 1835.920000 207.480000 1837.020000 207.960000 ;
+ RECT 1835.920000 202.040000 1837.020000 202.520000 ;
+ RECT 1835.920000 196.600000 1837.020000 197.080000 ;
+ RECT 1790.920000 223.800000 1792.020000 224.280000 ;
+ RECT 1790.920000 229.240000 1792.020000 229.720000 ;
+ RECT 1790.920000 234.680000 1792.020000 235.160000 ;
+ RECT 1790.920000 240.120000 1792.020000 240.600000 ;
+ RECT 1790.920000 196.600000 1792.020000 197.080000 ;
+ RECT 1790.920000 202.040000 1792.020000 202.520000 ;
+ RECT 1790.920000 207.480000 1792.020000 207.960000 ;
+ RECT 1790.920000 212.920000 1792.020000 213.400000 ;
+ RECT 1790.920000 218.360000 1792.020000 218.840000 ;
+ RECT 1835.920000 185.720000 1837.020000 186.200000 ;
+ RECT 1835.920000 191.160000 1837.020000 191.640000 ;
+ RECT 1848.730000 185.720000 1849.730000 186.200000 ;
+ RECT 1848.730000 191.160000 1849.730000 191.640000 ;
+ RECT 1835.920000 174.840000 1837.020000 175.320000 ;
+ RECT 1835.920000 180.280000 1837.020000 180.760000 ;
+ RECT 1848.730000 174.840000 1849.730000 175.320000 ;
+ RECT 1848.730000 180.280000 1849.730000 180.760000 ;
+ RECT 1848.730000 163.960000 1849.730000 164.440000 ;
+ RECT 1848.730000 158.520000 1849.730000 159.000000 ;
+ RECT 1848.730000 169.400000 1849.730000 169.880000 ;
+ RECT 1835.920000 169.400000 1837.020000 169.880000 ;
+ RECT 1835.920000 163.960000 1837.020000 164.440000 ;
+ RECT 1835.920000 158.520000 1837.020000 159.000000 ;
+ RECT 1835.920000 153.080000 1837.020000 153.560000 ;
+ RECT 1848.730000 153.080000 1849.730000 153.560000 ;
+ RECT 1790.920000 174.840000 1792.020000 175.320000 ;
+ RECT 1790.920000 180.280000 1792.020000 180.760000 ;
+ RECT 1790.920000 185.720000 1792.020000 186.200000 ;
+ RECT 1790.920000 191.160000 1792.020000 191.640000 ;
+ RECT 1790.920000 153.080000 1792.020000 153.560000 ;
+ RECT 1790.920000 158.520000 1792.020000 159.000000 ;
+ RECT 1790.920000 163.960000 1792.020000 164.440000 ;
+ RECT 1790.920000 169.400000 1792.020000 169.880000 ;
+ RECT 1745.920000 223.800000 1747.020000 224.280000 ;
+ RECT 1745.920000 229.240000 1747.020000 229.720000 ;
+ RECT 1745.920000 234.680000 1747.020000 235.160000 ;
+ RECT 1745.920000 240.120000 1747.020000 240.600000 ;
+ RECT 1700.920000 223.800000 1702.020000 224.280000 ;
+ RECT 1700.920000 229.240000 1702.020000 229.720000 ;
+ RECT 1700.920000 234.680000 1702.020000 235.160000 ;
+ RECT 1700.920000 240.120000 1702.020000 240.600000 ;
+ RECT 1745.920000 196.600000 1747.020000 197.080000 ;
+ RECT 1745.920000 202.040000 1747.020000 202.520000 ;
+ RECT 1745.920000 207.480000 1747.020000 207.960000 ;
+ RECT 1745.920000 212.920000 1747.020000 213.400000 ;
+ RECT 1745.920000 218.360000 1747.020000 218.840000 ;
+ RECT 1700.920000 196.600000 1702.020000 197.080000 ;
+ RECT 1700.920000 202.040000 1702.020000 202.520000 ;
+ RECT 1700.920000 207.480000 1702.020000 207.960000 ;
+ RECT 1700.920000 212.920000 1702.020000 213.400000 ;
+ RECT 1700.920000 218.360000 1702.020000 218.840000 ;
+ RECT 1652.090000 240.120000 1653.090000 240.600000 ;
+ RECT 1655.755000 240.120000 1657.020000 240.600000 ;
+ RECT 1652.090000 234.680000 1653.090000 235.160000 ;
+ RECT 1655.755000 234.680000 1657.020000 235.160000 ;
+ RECT 1652.090000 229.240000 1653.090000 229.720000 ;
+ RECT 1655.755000 229.240000 1657.020000 229.720000 ;
+ RECT 1652.090000 223.800000 1653.090000 224.280000 ;
+ RECT 1655.755000 223.800000 1657.020000 224.280000 ;
+ RECT 1652.090000 218.360000 1653.090000 218.840000 ;
+ RECT 1655.755000 218.360000 1657.020000 218.840000 ;
+ RECT 1652.090000 212.920000 1653.090000 213.400000 ;
+ RECT 1655.755000 212.920000 1657.020000 213.400000 ;
+ RECT 1652.090000 202.040000 1653.090000 202.520000 ;
+ RECT 1655.755000 202.040000 1657.020000 202.520000 ;
+ RECT 1652.090000 207.480000 1653.090000 207.960000 ;
+ RECT 1655.755000 207.480000 1657.020000 207.960000 ;
+ RECT 1652.090000 196.600000 1653.090000 197.080000 ;
+ RECT 1655.755000 196.600000 1657.020000 197.080000 ;
+ RECT 1745.920000 174.840000 1747.020000 175.320000 ;
+ RECT 1745.920000 180.280000 1747.020000 180.760000 ;
+ RECT 1745.920000 185.720000 1747.020000 186.200000 ;
+ RECT 1745.920000 191.160000 1747.020000 191.640000 ;
+ RECT 1700.920000 174.840000 1702.020000 175.320000 ;
+ RECT 1700.920000 180.280000 1702.020000 180.760000 ;
+ RECT 1700.920000 185.720000 1702.020000 186.200000 ;
+ RECT 1700.920000 191.160000 1702.020000 191.640000 ;
+ RECT 1745.920000 153.080000 1747.020000 153.560000 ;
+ RECT 1745.920000 158.520000 1747.020000 159.000000 ;
+ RECT 1745.920000 163.960000 1747.020000 164.440000 ;
+ RECT 1745.920000 169.400000 1747.020000 169.880000 ;
+ RECT 1700.920000 153.080000 1702.020000 153.560000 ;
+ RECT 1700.920000 158.520000 1702.020000 159.000000 ;
+ RECT 1700.920000 163.960000 1702.020000 164.440000 ;
+ RECT 1700.920000 169.400000 1702.020000 169.880000 ;
+ RECT 1652.090000 191.160000 1653.090000 191.640000 ;
+ RECT 1655.755000 191.160000 1657.020000 191.640000 ;
+ RECT 1652.090000 185.720000 1653.090000 186.200000 ;
+ RECT 1655.755000 185.720000 1657.020000 186.200000 ;
+ RECT 1652.090000 180.280000 1653.090000 180.760000 ;
+ RECT 1655.755000 180.280000 1657.020000 180.760000 ;
+ RECT 1652.090000 174.840000 1653.090000 175.320000 ;
+ RECT 1655.755000 174.840000 1657.020000 175.320000 ;
+ RECT 1652.090000 169.400000 1653.090000 169.880000 ;
+ RECT 1655.755000 169.400000 1657.020000 169.880000 ;
+ RECT 1652.090000 158.520000 1653.090000 159.000000 ;
+ RECT 1655.755000 158.520000 1657.020000 159.000000 ;
+ RECT 1652.090000 163.960000 1653.090000 164.440000 ;
+ RECT 1655.755000 163.960000 1657.020000 164.440000 ;
+ RECT 1652.090000 153.080000 1653.090000 153.560000 ;
+ RECT 1655.755000 153.080000 1657.020000 153.560000 ;
+ RECT 1790.920000 245.560000 1792.020000 246.040000 ;
+ RECT 1835.920000 245.560000 1837.020000 246.040000 ;
+ RECT 1848.730000 245.560000 1849.730000 246.040000 ;
+ RECT 1700.920000 245.560000 1702.020000 246.040000 ;
+ RECT 1745.920000 245.560000 1747.020000 246.040000 ;
+ RECT 1652.090000 245.560000 1653.090000 246.040000 ;
+ RECT 1655.755000 245.560000 1657.020000 246.040000 ;
+ RECT 1650.860000 342.320000 1850.960000 343.320000 ;
+ RECT 1650.860000 146.750000 1850.960000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 145.500000 1653.090000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 344.760000 1653.090000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 145.500000 1849.730000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 344.760000 1849.730000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 146.750000 1651.860000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 146.750000 1850.960000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 342.320000 1651.860000 343.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 342.320000 1850.960000 343.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 139.140000 1657.020000 139.620000 ;
+ RECT 1655.755000 133.700000 1657.020000 134.180000 ;
+ RECT 1655.755000 128.260000 1657.020000 128.740000 ;
+ RECT 1655.755000 122.820000 1657.020000 123.300000 ;
+ RECT 1652.090000 115.240000 1653.090000 145.500000 ;
+ RECT 1848.730000 115.240000 1849.730000 145.500000 ;
+ RECT 1655.920000 116.490000 1657.020000 143.740000 ;
+ RECT 1700.920000 116.490000 1702.020000 143.740000 ;
+ RECT 1745.920000 116.490000 1747.020000 143.740000 ;
+ RECT 1790.920000 116.490000 1792.020000 143.740000 ;
+ RECT 1835.920000 116.490000 1837.020000 143.740000 ;
+ LAYER met3 ;
+ RECT 1848.730000 139.140000 1849.730000 139.620000 ;
+ RECT 1848.730000 133.700000 1849.730000 134.180000 ;
+ RECT 1835.920000 139.140000 1837.020000 139.620000 ;
+ RECT 1835.920000 133.700000 1837.020000 134.180000 ;
+ RECT 1790.920000 133.700000 1792.020000 134.180000 ;
+ RECT 1790.920000 139.140000 1792.020000 139.620000 ;
+ RECT 1745.920000 133.700000 1747.020000 134.180000 ;
+ RECT 1700.920000 133.700000 1702.020000 134.180000 ;
+ RECT 1745.920000 139.140000 1747.020000 139.620000 ;
+ RECT 1700.920000 139.140000 1702.020000 139.620000 ;
+ RECT 1655.755000 139.140000 1657.020000 139.620000 ;
+ RECT 1652.090000 139.140000 1653.090000 139.620000 ;
+ RECT 1655.755000 133.700000 1657.020000 134.180000 ;
+ RECT 1652.090000 133.700000 1653.090000 134.180000 ;
+ RECT 1848.730000 128.260000 1849.730000 128.740000 ;
+ RECT 1848.730000 122.820000 1849.730000 123.300000 ;
+ RECT 1835.920000 128.260000 1837.020000 128.740000 ;
+ RECT 1835.920000 122.820000 1837.020000 123.300000 ;
+ RECT 1790.920000 122.820000 1792.020000 123.300000 ;
+ RECT 1790.920000 128.260000 1792.020000 128.740000 ;
+ RECT 1745.920000 122.820000 1747.020000 123.300000 ;
+ RECT 1700.920000 122.820000 1702.020000 123.300000 ;
+ RECT 1745.920000 128.260000 1747.020000 128.740000 ;
+ RECT 1700.920000 128.260000 1702.020000 128.740000 ;
+ RECT 1655.755000 128.260000 1657.020000 128.740000 ;
+ RECT 1652.090000 128.260000 1653.090000 128.740000 ;
+ RECT 1655.755000 122.820000 1657.020000 123.300000 ;
+ RECT 1652.090000 122.820000 1653.090000 123.300000 ;
+ RECT 1650.860000 142.740000 1850.960000 143.740000 ;
+ RECT 1650.860000 116.490000 1850.960000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 116.490000 1651.860000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 116.490000 1850.960000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 142.740000 1651.860000 143.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 142.740000 1850.960000 143.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 115.240000 1653.090000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 144.500000 1653.090000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 115.240000 1849.730000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 144.500000 1849.730000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 3341.940000 1657.020000 3342.420000 ;
+ RECT 1655.755000 3331.060000 1657.020000 3331.540000 ;
+ RECT 1655.755000 3336.500000 1657.020000 3336.980000 ;
+ RECT 1655.755000 3325.620000 1657.020000 3326.100000 ;
+ RECT 1655.755000 3320.180000 1657.020000 3320.660000 ;
+ RECT 1655.755000 3314.740000 1657.020000 3315.220000 ;
+ RECT 1655.755000 3309.300000 1657.020000 3309.780000 ;
+ RECT 1655.755000 3303.860000 1657.020000 3304.340000 ;
+ RECT 1655.755000 3298.420000 1657.020000 3298.900000 ;
+ RECT 1655.755000 3287.540000 1657.020000 3288.020000 ;
+ RECT 1655.755000 3292.980000 1657.020000 3293.460000 ;
+ RECT 1655.755000 3282.100000 1657.020000 3282.580000 ;
+ RECT 1655.755000 3276.660000 1657.020000 3277.140000 ;
+ RECT 1655.755000 3271.220000 1657.020000 3271.700000 ;
+ RECT 1655.755000 3265.780000 1657.020000 3266.260000 ;
+ RECT 1655.755000 3260.340000 1657.020000 3260.820000 ;
+ RECT 1655.755000 3254.900000 1657.020000 3255.380000 ;
+ RECT 1655.755000 3244.020000 1657.020000 3244.500000 ;
+ RECT 1655.755000 3238.580000 1657.020000 3239.060000 ;
+ RECT 1655.755000 3233.140000 1657.020000 3233.620000 ;
+ RECT 1655.755000 3227.700000 1657.020000 3228.180000 ;
+ RECT 1655.755000 3222.260000 1657.020000 3222.740000 ;
+ RECT 1655.755000 3216.820000 1657.020000 3217.300000 ;
+ RECT 1655.755000 3205.940000 1657.020000 3206.420000 ;
+ RECT 1655.755000 3211.380000 1657.020000 3211.860000 ;
+ RECT 1655.755000 3200.500000 1657.020000 3200.980000 ;
+ RECT 1655.755000 3195.060000 1657.020000 3195.540000 ;
+ RECT 1655.755000 3189.620000 1657.020000 3190.100000 ;
+ RECT 1655.755000 3184.180000 1657.020000 3184.660000 ;
+ RECT 1655.755000 3178.740000 1657.020000 3179.220000 ;
+ RECT 1655.755000 3173.300000 1657.020000 3173.780000 ;
+ RECT 1655.755000 3162.420000 1657.020000 3162.900000 ;
+ RECT 1655.755000 3167.860000 1657.020000 3168.340000 ;
+ RECT 1655.755000 3156.980000 1657.020000 3157.460000 ;
+ RECT 1655.755000 3249.460000 1657.020000 3249.940000 ;
+ RECT 1835.920000 3150.650000 1837.020000 3347.220000 ;
+ RECT 1790.920000 3150.650000 1792.020000 3347.220000 ;
+ RECT 1848.730000 3149.400000 1849.730000 3349.660000 ;
+ RECT 1745.920000 3150.650000 1747.020000 3347.220000 ;
+ RECT 1700.920000 3150.650000 1702.020000 3347.220000 ;
+ RECT 1655.920000 3150.650000 1657.020000 3347.220000 ;
+ RECT 1652.090000 3149.400000 1653.090000 3349.660000 ;
+ LAYER met3 ;
+ RECT 1835.920000 3341.940000 1837.020000 3342.420000 ;
+ RECT 1848.730000 3341.940000 1849.730000 3342.420000 ;
+ RECT 1848.730000 3331.060000 1849.730000 3331.540000 ;
+ RECT 1848.730000 3325.620000 1849.730000 3326.100000 ;
+ RECT 1848.730000 3336.500000 1849.730000 3336.980000 ;
+ RECT 1835.920000 3336.500000 1837.020000 3336.980000 ;
+ RECT 1835.920000 3331.060000 1837.020000 3331.540000 ;
+ RECT 1835.920000 3325.620000 1837.020000 3326.100000 ;
+ RECT 1835.920000 3314.740000 1837.020000 3315.220000 ;
+ RECT 1835.920000 3320.180000 1837.020000 3320.660000 ;
+ RECT 1848.730000 3314.740000 1849.730000 3315.220000 ;
+ RECT 1848.730000 3320.180000 1849.730000 3320.660000 ;
+ RECT 1835.920000 3303.860000 1837.020000 3304.340000 ;
+ RECT 1835.920000 3309.300000 1837.020000 3309.780000 ;
+ RECT 1848.730000 3303.860000 1849.730000 3304.340000 ;
+ RECT 1848.730000 3309.300000 1849.730000 3309.780000 ;
+ RECT 1790.920000 3325.620000 1792.020000 3326.100000 ;
+ RECT 1790.920000 3331.060000 1792.020000 3331.540000 ;
+ RECT 1790.920000 3336.500000 1792.020000 3336.980000 ;
+ RECT 1790.920000 3341.940000 1792.020000 3342.420000 ;
+ RECT 1790.920000 3309.300000 1792.020000 3309.780000 ;
+ RECT 1790.920000 3303.860000 1792.020000 3304.340000 ;
+ RECT 1790.920000 3314.740000 1792.020000 3315.220000 ;
+ RECT 1790.920000 3320.180000 1792.020000 3320.660000 ;
+ RECT 1848.730000 3292.980000 1849.730000 3293.460000 ;
+ RECT 1848.730000 3287.540000 1849.730000 3288.020000 ;
+ RECT 1848.730000 3298.420000 1849.730000 3298.900000 ;
+ RECT 1835.920000 3298.420000 1837.020000 3298.900000 ;
+ RECT 1835.920000 3292.980000 1837.020000 3293.460000 ;
+ RECT 1835.920000 3287.540000 1837.020000 3288.020000 ;
+ RECT 1835.920000 3276.660000 1837.020000 3277.140000 ;
+ RECT 1835.920000 3282.100000 1837.020000 3282.580000 ;
+ RECT 1848.730000 3276.660000 1849.730000 3277.140000 ;
+ RECT 1848.730000 3282.100000 1849.730000 3282.580000 ;
+ RECT 1848.730000 3265.780000 1849.730000 3266.260000 ;
+ RECT 1848.730000 3271.220000 1849.730000 3271.700000 ;
+ RECT 1835.920000 3271.220000 1837.020000 3271.700000 ;
+ RECT 1835.920000 3265.780000 1837.020000 3266.260000 ;
+ RECT 1835.920000 3254.900000 1837.020000 3255.380000 ;
+ RECT 1835.920000 3260.340000 1837.020000 3260.820000 ;
+ RECT 1848.730000 3254.900000 1849.730000 3255.380000 ;
+ RECT 1848.730000 3260.340000 1849.730000 3260.820000 ;
+ RECT 1790.920000 3276.660000 1792.020000 3277.140000 ;
+ RECT 1790.920000 3282.100000 1792.020000 3282.580000 ;
+ RECT 1790.920000 3287.540000 1792.020000 3288.020000 ;
+ RECT 1790.920000 3292.980000 1792.020000 3293.460000 ;
+ RECT 1790.920000 3298.420000 1792.020000 3298.900000 ;
+ RECT 1790.920000 3254.900000 1792.020000 3255.380000 ;
+ RECT 1790.920000 3260.340000 1792.020000 3260.820000 ;
+ RECT 1790.920000 3265.780000 1792.020000 3266.260000 ;
+ RECT 1790.920000 3271.220000 1792.020000 3271.700000 ;
+ RECT 1745.920000 3331.060000 1747.020000 3331.540000 ;
+ RECT 1745.920000 3325.620000 1747.020000 3326.100000 ;
+ RECT 1745.920000 3336.500000 1747.020000 3336.980000 ;
+ RECT 1745.920000 3341.940000 1747.020000 3342.420000 ;
+ RECT 1700.920000 3325.620000 1702.020000 3326.100000 ;
+ RECT 1700.920000 3331.060000 1702.020000 3331.540000 ;
+ RECT 1700.920000 3336.500000 1702.020000 3336.980000 ;
+ RECT 1700.920000 3341.940000 1702.020000 3342.420000 ;
+ RECT 1745.920000 3303.860000 1747.020000 3304.340000 ;
+ RECT 1745.920000 3309.300000 1747.020000 3309.780000 ;
+ RECT 1745.920000 3314.740000 1747.020000 3315.220000 ;
+ RECT 1745.920000 3320.180000 1747.020000 3320.660000 ;
+ RECT 1700.920000 3303.860000 1702.020000 3304.340000 ;
+ RECT 1700.920000 3309.300000 1702.020000 3309.780000 ;
+ RECT 1700.920000 3314.740000 1702.020000 3315.220000 ;
+ RECT 1700.920000 3320.180000 1702.020000 3320.660000 ;
+ RECT 1652.090000 3341.940000 1653.090000 3342.420000 ;
+ RECT 1655.755000 3341.940000 1657.020000 3342.420000 ;
+ RECT 1652.090000 3331.060000 1653.090000 3331.540000 ;
+ RECT 1655.755000 3331.060000 1657.020000 3331.540000 ;
+ RECT 1652.090000 3336.500000 1653.090000 3336.980000 ;
+ RECT 1655.755000 3336.500000 1657.020000 3336.980000 ;
+ RECT 1652.090000 3325.620000 1653.090000 3326.100000 ;
+ RECT 1655.755000 3325.620000 1657.020000 3326.100000 ;
+ RECT 1652.090000 3320.180000 1653.090000 3320.660000 ;
+ RECT 1655.755000 3320.180000 1657.020000 3320.660000 ;
+ RECT 1652.090000 3314.740000 1653.090000 3315.220000 ;
+ RECT 1655.755000 3314.740000 1657.020000 3315.220000 ;
+ RECT 1652.090000 3309.300000 1653.090000 3309.780000 ;
+ RECT 1655.755000 3309.300000 1657.020000 3309.780000 ;
+ RECT 1652.090000 3303.860000 1653.090000 3304.340000 ;
+ RECT 1655.755000 3303.860000 1657.020000 3304.340000 ;
+ RECT 1745.920000 3276.660000 1747.020000 3277.140000 ;
+ RECT 1745.920000 3282.100000 1747.020000 3282.580000 ;
+ RECT 1745.920000 3287.540000 1747.020000 3288.020000 ;
+ RECT 1745.920000 3292.980000 1747.020000 3293.460000 ;
+ RECT 1745.920000 3298.420000 1747.020000 3298.900000 ;
+ RECT 1700.920000 3276.660000 1702.020000 3277.140000 ;
+ RECT 1700.920000 3282.100000 1702.020000 3282.580000 ;
+ RECT 1700.920000 3287.540000 1702.020000 3288.020000 ;
+ RECT 1700.920000 3292.980000 1702.020000 3293.460000 ;
+ RECT 1700.920000 3298.420000 1702.020000 3298.900000 ;
+ RECT 1745.920000 3254.900000 1747.020000 3255.380000 ;
+ RECT 1745.920000 3260.340000 1747.020000 3260.820000 ;
+ RECT 1745.920000 3265.780000 1747.020000 3266.260000 ;
+ RECT 1745.920000 3271.220000 1747.020000 3271.700000 ;
+ RECT 1700.920000 3254.900000 1702.020000 3255.380000 ;
+ RECT 1700.920000 3260.340000 1702.020000 3260.820000 ;
+ RECT 1700.920000 3265.780000 1702.020000 3266.260000 ;
+ RECT 1700.920000 3271.220000 1702.020000 3271.700000 ;
+ RECT 1652.090000 3298.420000 1653.090000 3298.900000 ;
+ RECT 1655.755000 3298.420000 1657.020000 3298.900000 ;
+ RECT 1652.090000 3287.540000 1653.090000 3288.020000 ;
+ RECT 1655.755000 3287.540000 1657.020000 3288.020000 ;
+ RECT 1652.090000 3292.980000 1653.090000 3293.460000 ;
+ RECT 1655.755000 3292.980000 1657.020000 3293.460000 ;
+ RECT 1652.090000 3282.100000 1653.090000 3282.580000 ;
+ RECT 1655.755000 3282.100000 1657.020000 3282.580000 ;
+ RECT 1652.090000 3276.660000 1653.090000 3277.140000 ;
+ RECT 1655.755000 3276.660000 1657.020000 3277.140000 ;
+ RECT 1652.090000 3271.220000 1653.090000 3271.700000 ;
+ RECT 1655.755000 3271.220000 1657.020000 3271.700000 ;
+ RECT 1652.090000 3265.780000 1653.090000 3266.260000 ;
+ RECT 1655.755000 3265.780000 1657.020000 3266.260000 ;
+ RECT 1652.090000 3260.340000 1653.090000 3260.820000 ;
+ RECT 1655.755000 3260.340000 1657.020000 3260.820000 ;
+ RECT 1652.090000 3254.900000 1653.090000 3255.380000 ;
+ RECT 1655.755000 3254.900000 1657.020000 3255.380000 ;
+ RECT 1835.920000 3238.580000 1837.020000 3239.060000 ;
+ RECT 1835.920000 3244.020000 1837.020000 3244.500000 ;
+ RECT 1848.730000 3238.580000 1849.730000 3239.060000 ;
+ RECT 1848.730000 3244.020000 1849.730000 3244.500000 ;
+ RECT 1848.730000 3227.700000 1849.730000 3228.180000 ;
+ RECT 1848.730000 3233.140000 1849.730000 3233.620000 ;
+ RECT 1835.920000 3233.140000 1837.020000 3233.620000 ;
+ RECT 1835.920000 3227.700000 1837.020000 3228.180000 ;
+ RECT 1835.920000 3216.820000 1837.020000 3217.300000 ;
+ RECT 1835.920000 3222.260000 1837.020000 3222.740000 ;
+ RECT 1848.730000 3216.820000 1849.730000 3217.300000 ;
+ RECT 1848.730000 3222.260000 1849.730000 3222.740000 ;
+ RECT 1848.730000 3205.940000 1849.730000 3206.420000 ;
+ RECT 1848.730000 3200.500000 1849.730000 3200.980000 ;
+ RECT 1848.730000 3211.380000 1849.730000 3211.860000 ;
+ RECT 1835.920000 3211.380000 1837.020000 3211.860000 ;
+ RECT 1835.920000 3205.940000 1837.020000 3206.420000 ;
+ RECT 1835.920000 3200.500000 1837.020000 3200.980000 ;
+ RECT 1790.920000 3227.700000 1792.020000 3228.180000 ;
+ RECT 1790.920000 3233.140000 1792.020000 3233.620000 ;
+ RECT 1790.920000 3238.580000 1792.020000 3239.060000 ;
+ RECT 1790.920000 3244.020000 1792.020000 3244.500000 ;
+ RECT 1790.920000 3200.500000 1792.020000 3200.980000 ;
+ RECT 1790.920000 3205.940000 1792.020000 3206.420000 ;
+ RECT 1790.920000 3211.380000 1792.020000 3211.860000 ;
+ RECT 1790.920000 3216.820000 1792.020000 3217.300000 ;
+ RECT 1790.920000 3222.260000 1792.020000 3222.740000 ;
+ RECT 1835.920000 3189.620000 1837.020000 3190.100000 ;
+ RECT 1835.920000 3195.060000 1837.020000 3195.540000 ;
+ RECT 1848.730000 3189.620000 1849.730000 3190.100000 ;
+ RECT 1848.730000 3195.060000 1849.730000 3195.540000 ;
+ RECT 1835.920000 3178.740000 1837.020000 3179.220000 ;
+ RECT 1835.920000 3184.180000 1837.020000 3184.660000 ;
+ RECT 1848.730000 3178.740000 1849.730000 3179.220000 ;
+ RECT 1848.730000 3184.180000 1849.730000 3184.660000 ;
+ RECT 1848.730000 3167.860000 1849.730000 3168.340000 ;
+ RECT 1848.730000 3162.420000 1849.730000 3162.900000 ;
+ RECT 1848.730000 3173.300000 1849.730000 3173.780000 ;
+ RECT 1835.920000 3173.300000 1837.020000 3173.780000 ;
+ RECT 1835.920000 3167.860000 1837.020000 3168.340000 ;
+ RECT 1835.920000 3162.420000 1837.020000 3162.900000 ;
+ RECT 1835.920000 3156.980000 1837.020000 3157.460000 ;
+ RECT 1848.730000 3156.980000 1849.730000 3157.460000 ;
+ RECT 1790.920000 3178.740000 1792.020000 3179.220000 ;
+ RECT 1790.920000 3184.180000 1792.020000 3184.660000 ;
+ RECT 1790.920000 3189.620000 1792.020000 3190.100000 ;
+ RECT 1790.920000 3195.060000 1792.020000 3195.540000 ;
+ RECT 1790.920000 3156.980000 1792.020000 3157.460000 ;
+ RECT 1790.920000 3162.420000 1792.020000 3162.900000 ;
+ RECT 1790.920000 3167.860000 1792.020000 3168.340000 ;
+ RECT 1790.920000 3173.300000 1792.020000 3173.780000 ;
+ RECT 1745.920000 3227.700000 1747.020000 3228.180000 ;
+ RECT 1745.920000 3233.140000 1747.020000 3233.620000 ;
+ RECT 1745.920000 3238.580000 1747.020000 3239.060000 ;
+ RECT 1745.920000 3244.020000 1747.020000 3244.500000 ;
+ RECT 1700.920000 3227.700000 1702.020000 3228.180000 ;
+ RECT 1700.920000 3233.140000 1702.020000 3233.620000 ;
+ RECT 1700.920000 3238.580000 1702.020000 3239.060000 ;
+ RECT 1700.920000 3244.020000 1702.020000 3244.500000 ;
+ RECT 1745.920000 3200.500000 1747.020000 3200.980000 ;
+ RECT 1745.920000 3205.940000 1747.020000 3206.420000 ;
+ RECT 1745.920000 3211.380000 1747.020000 3211.860000 ;
+ RECT 1745.920000 3216.820000 1747.020000 3217.300000 ;
+ RECT 1745.920000 3222.260000 1747.020000 3222.740000 ;
+ RECT 1700.920000 3200.500000 1702.020000 3200.980000 ;
+ RECT 1700.920000 3205.940000 1702.020000 3206.420000 ;
+ RECT 1700.920000 3211.380000 1702.020000 3211.860000 ;
+ RECT 1700.920000 3216.820000 1702.020000 3217.300000 ;
+ RECT 1700.920000 3222.260000 1702.020000 3222.740000 ;
+ RECT 1652.090000 3244.020000 1653.090000 3244.500000 ;
+ RECT 1655.755000 3244.020000 1657.020000 3244.500000 ;
+ RECT 1652.090000 3238.580000 1653.090000 3239.060000 ;
+ RECT 1655.755000 3238.580000 1657.020000 3239.060000 ;
+ RECT 1652.090000 3233.140000 1653.090000 3233.620000 ;
+ RECT 1655.755000 3233.140000 1657.020000 3233.620000 ;
+ RECT 1652.090000 3227.700000 1653.090000 3228.180000 ;
+ RECT 1655.755000 3227.700000 1657.020000 3228.180000 ;
+ RECT 1652.090000 3222.260000 1653.090000 3222.740000 ;
+ RECT 1655.755000 3222.260000 1657.020000 3222.740000 ;
+ RECT 1652.090000 3216.820000 1653.090000 3217.300000 ;
+ RECT 1655.755000 3216.820000 1657.020000 3217.300000 ;
+ RECT 1652.090000 3205.940000 1653.090000 3206.420000 ;
+ RECT 1655.755000 3205.940000 1657.020000 3206.420000 ;
+ RECT 1652.090000 3211.380000 1653.090000 3211.860000 ;
+ RECT 1655.755000 3211.380000 1657.020000 3211.860000 ;
+ RECT 1652.090000 3200.500000 1653.090000 3200.980000 ;
+ RECT 1655.755000 3200.500000 1657.020000 3200.980000 ;
+ RECT 1745.920000 3178.740000 1747.020000 3179.220000 ;
+ RECT 1745.920000 3184.180000 1747.020000 3184.660000 ;
+ RECT 1745.920000 3189.620000 1747.020000 3190.100000 ;
+ RECT 1745.920000 3195.060000 1747.020000 3195.540000 ;
+ RECT 1700.920000 3178.740000 1702.020000 3179.220000 ;
+ RECT 1700.920000 3184.180000 1702.020000 3184.660000 ;
+ RECT 1700.920000 3189.620000 1702.020000 3190.100000 ;
+ RECT 1700.920000 3195.060000 1702.020000 3195.540000 ;
+ RECT 1745.920000 3156.980000 1747.020000 3157.460000 ;
+ RECT 1745.920000 3162.420000 1747.020000 3162.900000 ;
+ RECT 1745.920000 3167.860000 1747.020000 3168.340000 ;
+ RECT 1745.920000 3173.300000 1747.020000 3173.780000 ;
+ RECT 1700.920000 3156.980000 1702.020000 3157.460000 ;
+ RECT 1700.920000 3162.420000 1702.020000 3162.900000 ;
+ RECT 1700.920000 3167.860000 1702.020000 3168.340000 ;
+ RECT 1700.920000 3173.300000 1702.020000 3173.780000 ;
+ RECT 1652.090000 3195.060000 1653.090000 3195.540000 ;
+ RECT 1655.755000 3195.060000 1657.020000 3195.540000 ;
+ RECT 1652.090000 3189.620000 1653.090000 3190.100000 ;
+ RECT 1655.755000 3189.620000 1657.020000 3190.100000 ;
+ RECT 1652.090000 3184.180000 1653.090000 3184.660000 ;
+ RECT 1655.755000 3184.180000 1657.020000 3184.660000 ;
+ RECT 1652.090000 3178.740000 1653.090000 3179.220000 ;
+ RECT 1655.755000 3178.740000 1657.020000 3179.220000 ;
+ RECT 1652.090000 3173.300000 1653.090000 3173.780000 ;
+ RECT 1655.755000 3173.300000 1657.020000 3173.780000 ;
+ RECT 1652.090000 3162.420000 1653.090000 3162.900000 ;
+ RECT 1655.755000 3162.420000 1657.020000 3162.900000 ;
+ RECT 1652.090000 3167.860000 1653.090000 3168.340000 ;
+ RECT 1655.755000 3167.860000 1657.020000 3168.340000 ;
+ RECT 1652.090000 3156.980000 1653.090000 3157.460000 ;
+ RECT 1655.755000 3156.980000 1657.020000 3157.460000 ;
+ RECT 1790.920000 3249.460000 1792.020000 3249.940000 ;
+ RECT 1835.920000 3249.460000 1837.020000 3249.940000 ;
+ RECT 1848.730000 3249.460000 1849.730000 3249.940000 ;
+ RECT 1700.920000 3249.460000 1702.020000 3249.940000 ;
+ RECT 1745.920000 3249.460000 1747.020000 3249.940000 ;
+ RECT 1652.090000 3249.460000 1653.090000 3249.940000 ;
+ RECT 1655.755000 3249.460000 1657.020000 3249.940000 ;
+ RECT 1650.860000 3346.220000 1850.960000 3347.220000 ;
+ RECT 1650.860000 3150.650000 1850.960000 3151.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 3149.400000 1653.090000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 3348.660000 1653.090000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 3149.400000 1849.730000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 3348.660000 1849.730000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 3150.650000 1651.860000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 3150.650000 1850.960000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 3346.220000 1651.860000 3347.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 3346.220000 1850.960000 3347.220000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 3141.680000 1657.020000 3142.160000 ;
+ RECT 1655.755000 3130.800000 1657.020000 3131.280000 ;
+ RECT 1655.755000 3136.240000 1657.020000 3136.720000 ;
+ RECT 1655.755000 3125.360000 1657.020000 3125.840000 ;
+ RECT 1655.755000 3119.920000 1657.020000 3120.400000 ;
+ RECT 1655.755000 3114.480000 1657.020000 3114.960000 ;
+ RECT 1655.755000 3109.040000 1657.020000 3109.520000 ;
+ RECT 1655.755000 3103.600000 1657.020000 3104.080000 ;
+ RECT 1655.755000 3098.160000 1657.020000 3098.640000 ;
+ RECT 1655.755000 3087.280000 1657.020000 3087.760000 ;
+ RECT 1655.755000 3092.720000 1657.020000 3093.200000 ;
+ RECT 1655.755000 3081.840000 1657.020000 3082.320000 ;
+ RECT 1655.755000 3076.400000 1657.020000 3076.880000 ;
+ RECT 1655.755000 3070.960000 1657.020000 3071.440000 ;
+ RECT 1655.755000 3065.520000 1657.020000 3066.000000 ;
+ RECT 1655.755000 3060.080000 1657.020000 3060.560000 ;
+ RECT 1655.755000 3054.640000 1657.020000 3055.120000 ;
+ RECT 1655.755000 3043.760000 1657.020000 3044.240000 ;
+ RECT 1655.755000 3038.320000 1657.020000 3038.800000 ;
+ RECT 1655.755000 3032.880000 1657.020000 3033.360000 ;
+ RECT 1655.755000 3027.440000 1657.020000 3027.920000 ;
+ RECT 1655.755000 3022.000000 1657.020000 3022.480000 ;
+ RECT 1655.755000 3016.560000 1657.020000 3017.040000 ;
+ RECT 1655.755000 3005.680000 1657.020000 3006.160000 ;
+ RECT 1655.755000 3011.120000 1657.020000 3011.600000 ;
+ RECT 1655.755000 3000.240000 1657.020000 3000.720000 ;
+ RECT 1655.755000 2994.800000 1657.020000 2995.280000 ;
+ RECT 1655.755000 2989.360000 1657.020000 2989.840000 ;
+ RECT 1655.755000 2983.920000 1657.020000 2984.400000 ;
+ RECT 1655.755000 2978.480000 1657.020000 2978.960000 ;
+ RECT 1655.755000 2973.040000 1657.020000 2973.520000 ;
+ RECT 1655.755000 2962.160000 1657.020000 2962.640000 ;
+ RECT 1655.755000 2967.600000 1657.020000 2968.080000 ;
+ RECT 1655.755000 2956.720000 1657.020000 2957.200000 ;
+ RECT 1655.755000 3049.200000 1657.020000 3049.680000 ;
+ RECT 1835.920000 2950.390000 1837.020000 3146.960000 ;
+ RECT 1790.920000 2950.390000 1792.020000 3146.960000 ;
+ RECT 1848.730000 2949.140000 1849.730000 3149.400000 ;
+ RECT 1745.920000 2950.390000 1747.020000 3146.960000 ;
+ RECT 1700.920000 2950.390000 1702.020000 3146.960000 ;
+ RECT 1655.920000 2950.390000 1657.020000 3146.960000 ;
+ RECT 1652.090000 2949.140000 1653.090000 3149.400000 ;
+ LAYER met3 ;
+ RECT 1835.920000 3141.680000 1837.020000 3142.160000 ;
+ RECT 1848.730000 3141.680000 1849.730000 3142.160000 ;
+ RECT 1848.730000 3130.800000 1849.730000 3131.280000 ;
+ RECT 1848.730000 3125.360000 1849.730000 3125.840000 ;
+ RECT 1848.730000 3136.240000 1849.730000 3136.720000 ;
+ RECT 1835.920000 3136.240000 1837.020000 3136.720000 ;
+ RECT 1835.920000 3130.800000 1837.020000 3131.280000 ;
+ RECT 1835.920000 3125.360000 1837.020000 3125.840000 ;
+ RECT 1835.920000 3114.480000 1837.020000 3114.960000 ;
+ RECT 1835.920000 3119.920000 1837.020000 3120.400000 ;
+ RECT 1848.730000 3114.480000 1849.730000 3114.960000 ;
+ RECT 1848.730000 3119.920000 1849.730000 3120.400000 ;
+ RECT 1835.920000 3103.600000 1837.020000 3104.080000 ;
+ RECT 1835.920000 3109.040000 1837.020000 3109.520000 ;
+ RECT 1848.730000 3103.600000 1849.730000 3104.080000 ;
+ RECT 1848.730000 3109.040000 1849.730000 3109.520000 ;
+ RECT 1790.920000 3125.360000 1792.020000 3125.840000 ;
+ RECT 1790.920000 3130.800000 1792.020000 3131.280000 ;
+ RECT 1790.920000 3136.240000 1792.020000 3136.720000 ;
+ RECT 1790.920000 3141.680000 1792.020000 3142.160000 ;
+ RECT 1790.920000 3109.040000 1792.020000 3109.520000 ;
+ RECT 1790.920000 3103.600000 1792.020000 3104.080000 ;
+ RECT 1790.920000 3114.480000 1792.020000 3114.960000 ;
+ RECT 1790.920000 3119.920000 1792.020000 3120.400000 ;
+ RECT 1848.730000 3092.720000 1849.730000 3093.200000 ;
+ RECT 1848.730000 3087.280000 1849.730000 3087.760000 ;
+ RECT 1848.730000 3098.160000 1849.730000 3098.640000 ;
+ RECT 1835.920000 3098.160000 1837.020000 3098.640000 ;
+ RECT 1835.920000 3092.720000 1837.020000 3093.200000 ;
+ RECT 1835.920000 3087.280000 1837.020000 3087.760000 ;
+ RECT 1835.920000 3076.400000 1837.020000 3076.880000 ;
+ RECT 1835.920000 3081.840000 1837.020000 3082.320000 ;
+ RECT 1848.730000 3076.400000 1849.730000 3076.880000 ;
+ RECT 1848.730000 3081.840000 1849.730000 3082.320000 ;
+ RECT 1848.730000 3065.520000 1849.730000 3066.000000 ;
+ RECT 1848.730000 3070.960000 1849.730000 3071.440000 ;
+ RECT 1835.920000 3070.960000 1837.020000 3071.440000 ;
+ RECT 1835.920000 3065.520000 1837.020000 3066.000000 ;
+ RECT 1835.920000 3054.640000 1837.020000 3055.120000 ;
+ RECT 1835.920000 3060.080000 1837.020000 3060.560000 ;
+ RECT 1848.730000 3054.640000 1849.730000 3055.120000 ;
+ RECT 1848.730000 3060.080000 1849.730000 3060.560000 ;
+ RECT 1790.920000 3076.400000 1792.020000 3076.880000 ;
+ RECT 1790.920000 3081.840000 1792.020000 3082.320000 ;
+ RECT 1790.920000 3087.280000 1792.020000 3087.760000 ;
+ RECT 1790.920000 3092.720000 1792.020000 3093.200000 ;
+ RECT 1790.920000 3098.160000 1792.020000 3098.640000 ;
+ RECT 1790.920000 3054.640000 1792.020000 3055.120000 ;
+ RECT 1790.920000 3060.080000 1792.020000 3060.560000 ;
+ RECT 1790.920000 3065.520000 1792.020000 3066.000000 ;
+ RECT 1790.920000 3070.960000 1792.020000 3071.440000 ;
+ RECT 1745.920000 3130.800000 1747.020000 3131.280000 ;
+ RECT 1745.920000 3125.360000 1747.020000 3125.840000 ;
+ RECT 1745.920000 3136.240000 1747.020000 3136.720000 ;
+ RECT 1745.920000 3141.680000 1747.020000 3142.160000 ;
+ RECT 1700.920000 3125.360000 1702.020000 3125.840000 ;
+ RECT 1700.920000 3130.800000 1702.020000 3131.280000 ;
+ RECT 1700.920000 3136.240000 1702.020000 3136.720000 ;
+ RECT 1700.920000 3141.680000 1702.020000 3142.160000 ;
+ RECT 1745.920000 3103.600000 1747.020000 3104.080000 ;
+ RECT 1745.920000 3109.040000 1747.020000 3109.520000 ;
+ RECT 1745.920000 3114.480000 1747.020000 3114.960000 ;
+ RECT 1745.920000 3119.920000 1747.020000 3120.400000 ;
+ RECT 1700.920000 3103.600000 1702.020000 3104.080000 ;
+ RECT 1700.920000 3109.040000 1702.020000 3109.520000 ;
+ RECT 1700.920000 3114.480000 1702.020000 3114.960000 ;
+ RECT 1700.920000 3119.920000 1702.020000 3120.400000 ;
+ RECT 1652.090000 3141.680000 1653.090000 3142.160000 ;
+ RECT 1655.755000 3141.680000 1657.020000 3142.160000 ;
+ RECT 1652.090000 3130.800000 1653.090000 3131.280000 ;
+ RECT 1655.755000 3130.800000 1657.020000 3131.280000 ;
+ RECT 1652.090000 3136.240000 1653.090000 3136.720000 ;
+ RECT 1655.755000 3136.240000 1657.020000 3136.720000 ;
+ RECT 1652.090000 3125.360000 1653.090000 3125.840000 ;
+ RECT 1655.755000 3125.360000 1657.020000 3125.840000 ;
+ RECT 1652.090000 3119.920000 1653.090000 3120.400000 ;
+ RECT 1655.755000 3119.920000 1657.020000 3120.400000 ;
+ RECT 1652.090000 3114.480000 1653.090000 3114.960000 ;
+ RECT 1655.755000 3114.480000 1657.020000 3114.960000 ;
+ RECT 1652.090000 3109.040000 1653.090000 3109.520000 ;
+ RECT 1655.755000 3109.040000 1657.020000 3109.520000 ;
+ RECT 1652.090000 3103.600000 1653.090000 3104.080000 ;
+ RECT 1655.755000 3103.600000 1657.020000 3104.080000 ;
+ RECT 1745.920000 3076.400000 1747.020000 3076.880000 ;
+ RECT 1745.920000 3081.840000 1747.020000 3082.320000 ;
+ RECT 1745.920000 3087.280000 1747.020000 3087.760000 ;
+ RECT 1745.920000 3092.720000 1747.020000 3093.200000 ;
+ RECT 1745.920000 3098.160000 1747.020000 3098.640000 ;
+ RECT 1700.920000 3076.400000 1702.020000 3076.880000 ;
+ RECT 1700.920000 3081.840000 1702.020000 3082.320000 ;
+ RECT 1700.920000 3087.280000 1702.020000 3087.760000 ;
+ RECT 1700.920000 3092.720000 1702.020000 3093.200000 ;
+ RECT 1700.920000 3098.160000 1702.020000 3098.640000 ;
+ RECT 1745.920000 3054.640000 1747.020000 3055.120000 ;
+ RECT 1745.920000 3060.080000 1747.020000 3060.560000 ;
+ RECT 1745.920000 3065.520000 1747.020000 3066.000000 ;
+ RECT 1745.920000 3070.960000 1747.020000 3071.440000 ;
+ RECT 1700.920000 3054.640000 1702.020000 3055.120000 ;
+ RECT 1700.920000 3060.080000 1702.020000 3060.560000 ;
+ RECT 1700.920000 3065.520000 1702.020000 3066.000000 ;
+ RECT 1700.920000 3070.960000 1702.020000 3071.440000 ;
+ RECT 1652.090000 3098.160000 1653.090000 3098.640000 ;
+ RECT 1655.755000 3098.160000 1657.020000 3098.640000 ;
+ RECT 1652.090000 3087.280000 1653.090000 3087.760000 ;
+ RECT 1655.755000 3087.280000 1657.020000 3087.760000 ;
+ RECT 1652.090000 3092.720000 1653.090000 3093.200000 ;
+ RECT 1655.755000 3092.720000 1657.020000 3093.200000 ;
+ RECT 1652.090000 3081.840000 1653.090000 3082.320000 ;
+ RECT 1655.755000 3081.840000 1657.020000 3082.320000 ;
+ RECT 1652.090000 3076.400000 1653.090000 3076.880000 ;
+ RECT 1655.755000 3076.400000 1657.020000 3076.880000 ;
+ RECT 1652.090000 3070.960000 1653.090000 3071.440000 ;
+ RECT 1655.755000 3070.960000 1657.020000 3071.440000 ;
+ RECT 1652.090000 3065.520000 1653.090000 3066.000000 ;
+ RECT 1655.755000 3065.520000 1657.020000 3066.000000 ;
+ RECT 1652.090000 3060.080000 1653.090000 3060.560000 ;
+ RECT 1655.755000 3060.080000 1657.020000 3060.560000 ;
+ RECT 1652.090000 3054.640000 1653.090000 3055.120000 ;
+ RECT 1655.755000 3054.640000 1657.020000 3055.120000 ;
+ RECT 1835.920000 3038.320000 1837.020000 3038.800000 ;
+ RECT 1835.920000 3043.760000 1837.020000 3044.240000 ;
+ RECT 1848.730000 3038.320000 1849.730000 3038.800000 ;
+ RECT 1848.730000 3043.760000 1849.730000 3044.240000 ;
+ RECT 1848.730000 3027.440000 1849.730000 3027.920000 ;
+ RECT 1848.730000 3032.880000 1849.730000 3033.360000 ;
+ RECT 1835.920000 3032.880000 1837.020000 3033.360000 ;
+ RECT 1835.920000 3027.440000 1837.020000 3027.920000 ;
+ RECT 1835.920000 3016.560000 1837.020000 3017.040000 ;
+ RECT 1835.920000 3022.000000 1837.020000 3022.480000 ;
+ RECT 1848.730000 3016.560000 1849.730000 3017.040000 ;
+ RECT 1848.730000 3022.000000 1849.730000 3022.480000 ;
+ RECT 1848.730000 3005.680000 1849.730000 3006.160000 ;
+ RECT 1848.730000 3000.240000 1849.730000 3000.720000 ;
+ RECT 1848.730000 3011.120000 1849.730000 3011.600000 ;
+ RECT 1835.920000 3011.120000 1837.020000 3011.600000 ;
+ RECT 1835.920000 3005.680000 1837.020000 3006.160000 ;
+ RECT 1835.920000 3000.240000 1837.020000 3000.720000 ;
+ RECT 1790.920000 3027.440000 1792.020000 3027.920000 ;
+ RECT 1790.920000 3032.880000 1792.020000 3033.360000 ;
+ RECT 1790.920000 3038.320000 1792.020000 3038.800000 ;
+ RECT 1790.920000 3043.760000 1792.020000 3044.240000 ;
+ RECT 1790.920000 3000.240000 1792.020000 3000.720000 ;
+ RECT 1790.920000 3005.680000 1792.020000 3006.160000 ;
+ RECT 1790.920000 3011.120000 1792.020000 3011.600000 ;
+ RECT 1790.920000 3016.560000 1792.020000 3017.040000 ;
+ RECT 1790.920000 3022.000000 1792.020000 3022.480000 ;
+ RECT 1835.920000 2989.360000 1837.020000 2989.840000 ;
+ RECT 1835.920000 2994.800000 1837.020000 2995.280000 ;
+ RECT 1848.730000 2989.360000 1849.730000 2989.840000 ;
+ RECT 1848.730000 2994.800000 1849.730000 2995.280000 ;
+ RECT 1835.920000 2978.480000 1837.020000 2978.960000 ;
+ RECT 1835.920000 2983.920000 1837.020000 2984.400000 ;
+ RECT 1848.730000 2978.480000 1849.730000 2978.960000 ;
+ RECT 1848.730000 2983.920000 1849.730000 2984.400000 ;
+ RECT 1848.730000 2967.600000 1849.730000 2968.080000 ;
+ RECT 1848.730000 2962.160000 1849.730000 2962.640000 ;
+ RECT 1848.730000 2973.040000 1849.730000 2973.520000 ;
+ RECT 1835.920000 2973.040000 1837.020000 2973.520000 ;
+ RECT 1835.920000 2967.600000 1837.020000 2968.080000 ;
+ RECT 1835.920000 2962.160000 1837.020000 2962.640000 ;
+ RECT 1835.920000 2956.720000 1837.020000 2957.200000 ;
+ RECT 1848.730000 2956.720000 1849.730000 2957.200000 ;
+ RECT 1790.920000 2978.480000 1792.020000 2978.960000 ;
+ RECT 1790.920000 2983.920000 1792.020000 2984.400000 ;
+ RECT 1790.920000 2989.360000 1792.020000 2989.840000 ;
+ RECT 1790.920000 2994.800000 1792.020000 2995.280000 ;
+ RECT 1790.920000 2956.720000 1792.020000 2957.200000 ;
+ RECT 1790.920000 2962.160000 1792.020000 2962.640000 ;
+ RECT 1790.920000 2967.600000 1792.020000 2968.080000 ;
+ RECT 1790.920000 2973.040000 1792.020000 2973.520000 ;
+ RECT 1745.920000 3027.440000 1747.020000 3027.920000 ;
+ RECT 1745.920000 3032.880000 1747.020000 3033.360000 ;
+ RECT 1745.920000 3038.320000 1747.020000 3038.800000 ;
+ RECT 1745.920000 3043.760000 1747.020000 3044.240000 ;
+ RECT 1700.920000 3027.440000 1702.020000 3027.920000 ;
+ RECT 1700.920000 3032.880000 1702.020000 3033.360000 ;
+ RECT 1700.920000 3038.320000 1702.020000 3038.800000 ;
+ RECT 1700.920000 3043.760000 1702.020000 3044.240000 ;
+ RECT 1745.920000 3000.240000 1747.020000 3000.720000 ;
+ RECT 1745.920000 3005.680000 1747.020000 3006.160000 ;
+ RECT 1745.920000 3011.120000 1747.020000 3011.600000 ;
+ RECT 1745.920000 3016.560000 1747.020000 3017.040000 ;
+ RECT 1745.920000 3022.000000 1747.020000 3022.480000 ;
+ RECT 1700.920000 3000.240000 1702.020000 3000.720000 ;
+ RECT 1700.920000 3005.680000 1702.020000 3006.160000 ;
+ RECT 1700.920000 3011.120000 1702.020000 3011.600000 ;
+ RECT 1700.920000 3016.560000 1702.020000 3017.040000 ;
+ RECT 1700.920000 3022.000000 1702.020000 3022.480000 ;
+ RECT 1652.090000 3043.760000 1653.090000 3044.240000 ;
+ RECT 1655.755000 3043.760000 1657.020000 3044.240000 ;
+ RECT 1652.090000 3038.320000 1653.090000 3038.800000 ;
+ RECT 1655.755000 3038.320000 1657.020000 3038.800000 ;
+ RECT 1652.090000 3032.880000 1653.090000 3033.360000 ;
+ RECT 1655.755000 3032.880000 1657.020000 3033.360000 ;
+ RECT 1652.090000 3027.440000 1653.090000 3027.920000 ;
+ RECT 1655.755000 3027.440000 1657.020000 3027.920000 ;
+ RECT 1652.090000 3022.000000 1653.090000 3022.480000 ;
+ RECT 1655.755000 3022.000000 1657.020000 3022.480000 ;
+ RECT 1652.090000 3016.560000 1653.090000 3017.040000 ;
+ RECT 1655.755000 3016.560000 1657.020000 3017.040000 ;
+ RECT 1652.090000 3005.680000 1653.090000 3006.160000 ;
+ RECT 1655.755000 3005.680000 1657.020000 3006.160000 ;
+ RECT 1652.090000 3011.120000 1653.090000 3011.600000 ;
+ RECT 1655.755000 3011.120000 1657.020000 3011.600000 ;
+ RECT 1652.090000 3000.240000 1653.090000 3000.720000 ;
+ RECT 1655.755000 3000.240000 1657.020000 3000.720000 ;
+ RECT 1745.920000 2978.480000 1747.020000 2978.960000 ;
+ RECT 1745.920000 2983.920000 1747.020000 2984.400000 ;
+ RECT 1745.920000 2989.360000 1747.020000 2989.840000 ;
+ RECT 1745.920000 2994.800000 1747.020000 2995.280000 ;
+ RECT 1700.920000 2978.480000 1702.020000 2978.960000 ;
+ RECT 1700.920000 2983.920000 1702.020000 2984.400000 ;
+ RECT 1700.920000 2989.360000 1702.020000 2989.840000 ;
+ RECT 1700.920000 2994.800000 1702.020000 2995.280000 ;
+ RECT 1745.920000 2956.720000 1747.020000 2957.200000 ;
+ RECT 1745.920000 2962.160000 1747.020000 2962.640000 ;
+ RECT 1745.920000 2967.600000 1747.020000 2968.080000 ;
+ RECT 1745.920000 2973.040000 1747.020000 2973.520000 ;
+ RECT 1700.920000 2956.720000 1702.020000 2957.200000 ;
+ RECT 1700.920000 2962.160000 1702.020000 2962.640000 ;
+ RECT 1700.920000 2967.600000 1702.020000 2968.080000 ;
+ RECT 1700.920000 2973.040000 1702.020000 2973.520000 ;
+ RECT 1652.090000 2994.800000 1653.090000 2995.280000 ;
+ RECT 1655.755000 2994.800000 1657.020000 2995.280000 ;
+ RECT 1652.090000 2989.360000 1653.090000 2989.840000 ;
+ RECT 1655.755000 2989.360000 1657.020000 2989.840000 ;
+ RECT 1652.090000 2983.920000 1653.090000 2984.400000 ;
+ RECT 1655.755000 2983.920000 1657.020000 2984.400000 ;
+ RECT 1652.090000 2978.480000 1653.090000 2978.960000 ;
+ RECT 1655.755000 2978.480000 1657.020000 2978.960000 ;
+ RECT 1652.090000 2973.040000 1653.090000 2973.520000 ;
+ RECT 1655.755000 2973.040000 1657.020000 2973.520000 ;
+ RECT 1652.090000 2962.160000 1653.090000 2962.640000 ;
+ RECT 1655.755000 2962.160000 1657.020000 2962.640000 ;
+ RECT 1652.090000 2967.600000 1653.090000 2968.080000 ;
+ RECT 1655.755000 2967.600000 1657.020000 2968.080000 ;
+ RECT 1652.090000 2956.720000 1653.090000 2957.200000 ;
+ RECT 1655.755000 2956.720000 1657.020000 2957.200000 ;
+ RECT 1790.920000 3049.200000 1792.020000 3049.680000 ;
+ RECT 1835.920000 3049.200000 1837.020000 3049.680000 ;
+ RECT 1848.730000 3049.200000 1849.730000 3049.680000 ;
+ RECT 1700.920000 3049.200000 1702.020000 3049.680000 ;
+ RECT 1745.920000 3049.200000 1747.020000 3049.680000 ;
+ RECT 1652.090000 3049.200000 1653.090000 3049.680000 ;
+ RECT 1655.755000 3049.200000 1657.020000 3049.680000 ;
+ RECT 1650.860000 3145.960000 1850.960000 3146.960000 ;
+ RECT 1650.860000 2950.390000 1850.960000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 2949.140000 1653.090000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 3148.400000 1653.090000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 2949.140000 1849.730000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 3148.400000 1849.730000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2950.390000 1651.860000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2950.390000 1850.960000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 3145.960000 1651.860000 3146.960000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 3145.960000 1850.960000 3146.960000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 2941.420000 1657.020000 2941.900000 ;
+ RECT 1655.755000 2930.540000 1657.020000 2931.020000 ;
+ RECT 1655.755000 2935.980000 1657.020000 2936.460000 ;
+ RECT 1655.755000 2925.100000 1657.020000 2925.580000 ;
+ RECT 1655.755000 2919.660000 1657.020000 2920.140000 ;
+ RECT 1655.755000 2914.220000 1657.020000 2914.700000 ;
+ RECT 1655.755000 2908.780000 1657.020000 2909.260000 ;
+ RECT 1655.755000 2903.340000 1657.020000 2903.820000 ;
+ RECT 1655.755000 2897.900000 1657.020000 2898.380000 ;
+ RECT 1655.755000 2887.020000 1657.020000 2887.500000 ;
+ RECT 1655.755000 2892.460000 1657.020000 2892.940000 ;
+ RECT 1655.755000 2881.580000 1657.020000 2882.060000 ;
+ RECT 1655.755000 2876.140000 1657.020000 2876.620000 ;
+ RECT 1655.755000 2870.700000 1657.020000 2871.180000 ;
+ RECT 1655.755000 2865.260000 1657.020000 2865.740000 ;
+ RECT 1655.755000 2859.820000 1657.020000 2860.300000 ;
+ RECT 1655.755000 2854.380000 1657.020000 2854.860000 ;
+ RECT 1655.755000 2843.500000 1657.020000 2843.980000 ;
+ RECT 1655.755000 2838.060000 1657.020000 2838.540000 ;
+ RECT 1655.755000 2832.620000 1657.020000 2833.100000 ;
+ RECT 1655.755000 2827.180000 1657.020000 2827.660000 ;
+ RECT 1655.755000 2821.740000 1657.020000 2822.220000 ;
+ RECT 1655.755000 2816.300000 1657.020000 2816.780000 ;
+ RECT 1655.755000 2805.420000 1657.020000 2805.900000 ;
+ RECT 1655.755000 2810.860000 1657.020000 2811.340000 ;
+ RECT 1655.755000 2799.980000 1657.020000 2800.460000 ;
+ RECT 1655.755000 2794.540000 1657.020000 2795.020000 ;
+ RECT 1655.755000 2789.100000 1657.020000 2789.580000 ;
+ RECT 1655.755000 2783.660000 1657.020000 2784.140000 ;
+ RECT 1655.755000 2778.220000 1657.020000 2778.700000 ;
+ RECT 1655.755000 2772.780000 1657.020000 2773.260000 ;
+ RECT 1655.755000 2761.900000 1657.020000 2762.380000 ;
+ RECT 1655.755000 2767.340000 1657.020000 2767.820000 ;
+ RECT 1655.755000 2756.460000 1657.020000 2756.940000 ;
+ RECT 1655.755000 2848.940000 1657.020000 2849.420000 ;
+ RECT 1835.920000 2750.130000 1837.020000 2946.700000 ;
+ RECT 1790.920000 2750.130000 1792.020000 2946.700000 ;
+ RECT 1848.730000 2748.880000 1849.730000 2949.140000 ;
+ RECT 1745.920000 2750.130000 1747.020000 2946.700000 ;
+ RECT 1700.920000 2750.130000 1702.020000 2946.700000 ;
+ RECT 1655.920000 2750.130000 1657.020000 2946.700000 ;
+ RECT 1652.090000 2748.880000 1653.090000 2949.140000 ;
+ LAYER met3 ;
+ RECT 1835.920000 2941.420000 1837.020000 2941.900000 ;
+ RECT 1848.730000 2941.420000 1849.730000 2941.900000 ;
+ RECT 1848.730000 2930.540000 1849.730000 2931.020000 ;
+ RECT 1848.730000 2925.100000 1849.730000 2925.580000 ;
+ RECT 1848.730000 2935.980000 1849.730000 2936.460000 ;
+ RECT 1835.920000 2935.980000 1837.020000 2936.460000 ;
+ RECT 1835.920000 2930.540000 1837.020000 2931.020000 ;
+ RECT 1835.920000 2925.100000 1837.020000 2925.580000 ;
+ RECT 1835.920000 2914.220000 1837.020000 2914.700000 ;
+ RECT 1835.920000 2919.660000 1837.020000 2920.140000 ;
+ RECT 1848.730000 2914.220000 1849.730000 2914.700000 ;
+ RECT 1848.730000 2919.660000 1849.730000 2920.140000 ;
+ RECT 1835.920000 2903.340000 1837.020000 2903.820000 ;
+ RECT 1835.920000 2908.780000 1837.020000 2909.260000 ;
+ RECT 1848.730000 2903.340000 1849.730000 2903.820000 ;
+ RECT 1848.730000 2908.780000 1849.730000 2909.260000 ;
+ RECT 1790.920000 2925.100000 1792.020000 2925.580000 ;
+ RECT 1790.920000 2930.540000 1792.020000 2931.020000 ;
+ RECT 1790.920000 2935.980000 1792.020000 2936.460000 ;
+ RECT 1790.920000 2941.420000 1792.020000 2941.900000 ;
+ RECT 1790.920000 2908.780000 1792.020000 2909.260000 ;
+ RECT 1790.920000 2903.340000 1792.020000 2903.820000 ;
+ RECT 1790.920000 2914.220000 1792.020000 2914.700000 ;
+ RECT 1790.920000 2919.660000 1792.020000 2920.140000 ;
+ RECT 1848.730000 2892.460000 1849.730000 2892.940000 ;
+ RECT 1848.730000 2887.020000 1849.730000 2887.500000 ;
+ RECT 1848.730000 2897.900000 1849.730000 2898.380000 ;
+ RECT 1835.920000 2897.900000 1837.020000 2898.380000 ;
+ RECT 1835.920000 2892.460000 1837.020000 2892.940000 ;
+ RECT 1835.920000 2887.020000 1837.020000 2887.500000 ;
+ RECT 1835.920000 2876.140000 1837.020000 2876.620000 ;
+ RECT 1835.920000 2881.580000 1837.020000 2882.060000 ;
+ RECT 1848.730000 2876.140000 1849.730000 2876.620000 ;
+ RECT 1848.730000 2881.580000 1849.730000 2882.060000 ;
+ RECT 1848.730000 2865.260000 1849.730000 2865.740000 ;
+ RECT 1848.730000 2870.700000 1849.730000 2871.180000 ;
+ RECT 1835.920000 2870.700000 1837.020000 2871.180000 ;
+ RECT 1835.920000 2865.260000 1837.020000 2865.740000 ;
+ RECT 1835.920000 2854.380000 1837.020000 2854.860000 ;
+ RECT 1835.920000 2859.820000 1837.020000 2860.300000 ;
+ RECT 1848.730000 2854.380000 1849.730000 2854.860000 ;
+ RECT 1848.730000 2859.820000 1849.730000 2860.300000 ;
+ RECT 1790.920000 2876.140000 1792.020000 2876.620000 ;
+ RECT 1790.920000 2881.580000 1792.020000 2882.060000 ;
+ RECT 1790.920000 2887.020000 1792.020000 2887.500000 ;
+ RECT 1790.920000 2892.460000 1792.020000 2892.940000 ;
+ RECT 1790.920000 2897.900000 1792.020000 2898.380000 ;
+ RECT 1790.920000 2854.380000 1792.020000 2854.860000 ;
+ RECT 1790.920000 2859.820000 1792.020000 2860.300000 ;
+ RECT 1790.920000 2865.260000 1792.020000 2865.740000 ;
+ RECT 1790.920000 2870.700000 1792.020000 2871.180000 ;
+ RECT 1745.920000 2930.540000 1747.020000 2931.020000 ;
+ RECT 1745.920000 2925.100000 1747.020000 2925.580000 ;
+ RECT 1745.920000 2935.980000 1747.020000 2936.460000 ;
+ RECT 1745.920000 2941.420000 1747.020000 2941.900000 ;
+ RECT 1700.920000 2925.100000 1702.020000 2925.580000 ;
+ RECT 1700.920000 2930.540000 1702.020000 2931.020000 ;
+ RECT 1700.920000 2935.980000 1702.020000 2936.460000 ;
+ RECT 1700.920000 2941.420000 1702.020000 2941.900000 ;
+ RECT 1745.920000 2903.340000 1747.020000 2903.820000 ;
+ RECT 1745.920000 2908.780000 1747.020000 2909.260000 ;
+ RECT 1745.920000 2914.220000 1747.020000 2914.700000 ;
+ RECT 1745.920000 2919.660000 1747.020000 2920.140000 ;
+ RECT 1700.920000 2903.340000 1702.020000 2903.820000 ;
+ RECT 1700.920000 2908.780000 1702.020000 2909.260000 ;
+ RECT 1700.920000 2914.220000 1702.020000 2914.700000 ;
+ RECT 1700.920000 2919.660000 1702.020000 2920.140000 ;
+ RECT 1652.090000 2941.420000 1653.090000 2941.900000 ;
+ RECT 1655.755000 2941.420000 1657.020000 2941.900000 ;
+ RECT 1652.090000 2930.540000 1653.090000 2931.020000 ;
+ RECT 1655.755000 2930.540000 1657.020000 2931.020000 ;
+ RECT 1652.090000 2935.980000 1653.090000 2936.460000 ;
+ RECT 1655.755000 2935.980000 1657.020000 2936.460000 ;
+ RECT 1652.090000 2925.100000 1653.090000 2925.580000 ;
+ RECT 1655.755000 2925.100000 1657.020000 2925.580000 ;
+ RECT 1652.090000 2919.660000 1653.090000 2920.140000 ;
+ RECT 1655.755000 2919.660000 1657.020000 2920.140000 ;
+ RECT 1652.090000 2914.220000 1653.090000 2914.700000 ;
+ RECT 1655.755000 2914.220000 1657.020000 2914.700000 ;
+ RECT 1652.090000 2908.780000 1653.090000 2909.260000 ;
+ RECT 1655.755000 2908.780000 1657.020000 2909.260000 ;
+ RECT 1652.090000 2903.340000 1653.090000 2903.820000 ;
+ RECT 1655.755000 2903.340000 1657.020000 2903.820000 ;
+ RECT 1745.920000 2876.140000 1747.020000 2876.620000 ;
+ RECT 1745.920000 2881.580000 1747.020000 2882.060000 ;
+ RECT 1745.920000 2887.020000 1747.020000 2887.500000 ;
+ RECT 1745.920000 2892.460000 1747.020000 2892.940000 ;
+ RECT 1745.920000 2897.900000 1747.020000 2898.380000 ;
+ RECT 1700.920000 2876.140000 1702.020000 2876.620000 ;
+ RECT 1700.920000 2881.580000 1702.020000 2882.060000 ;
+ RECT 1700.920000 2887.020000 1702.020000 2887.500000 ;
+ RECT 1700.920000 2892.460000 1702.020000 2892.940000 ;
+ RECT 1700.920000 2897.900000 1702.020000 2898.380000 ;
+ RECT 1745.920000 2854.380000 1747.020000 2854.860000 ;
+ RECT 1745.920000 2859.820000 1747.020000 2860.300000 ;
+ RECT 1745.920000 2865.260000 1747.020000 2865.740000 ;
+ RECT 1745.920000 2870.700000 1747.020000 2871.180000 ;
+ RECT 1700.920000 2854.380000 1702.020000 2854.860000 ;
+ RECT 1700.920000 2859.820000 1702.020000 2860.300000 ;
+ RECT 1700.920000 2865.260000 1702.020000 2865.740000 ;
+ RECT 1700.920000 2870.700000 1702.020000 2871.180000 ;
+ RECT 1652.090000 2897.900000 1653.090000 2898.380000 ;
+ RECT 1655.755000 2897.900000 1657.020000 2898.380000 ;
+ RECT 1652.090000 2887.020000 1653.090000 2887.500000 ;
+ RECT 1655.755000 2887.020000 1657.020000 2887.500000 ;
+ RECT 1652.090000 2892.460000 1653.090000 2892.940000 ;
+ RECT 1655.755000 2892.460000 1657.020000 2892.940000 ;
+ RECT 1652.090000 2881.580000 1653.090000 2882.060000 ;
+ RECT 1655.755000 2881.580000 1657.020000 2882.060000 ;
+ RECT 1652.090000 2876.140000 1653.090000 2876.620000 ;
+ RECT 1655.755000 2876.140000 1657.020000 2876.620000 ;
+ RECT 1652.090000 2870.700000 1653.090000 2871.180000 ;
+ RECT 1655.755000 2870.700000 1657.020000 2871.180000 ;
+ RECT 1652.090000 2865.260000 1653.090000 2865.740000 ;
+ RECT 1655.755000 2865.260000 1657.020000 2865.740000 ;
+ RECT 1652.090000 2859.820000 1653.090000 2860.300000 ;
+ RECT 1655.755000 2859.820000 1657.020000 2860.300000 ;
+ RECT 1652.090000 2854.380000 1653.090000 2854.860000 ;
+ RECT 1655.755000 2854.380000 1657.020000 2854.860000 ;
+ RECT 1835.920000 2838.060000 1837.020000 2838.540000 ;
+ RECT 1835.920000 2843.500000 1837.020000 2843.980000 ;
+ RECT 1848.730000 2838.060000 1849.730000 2838.540000 ;
+ RECT 1848.730000 2843.500000 1849.730000 2843.980000 ;
+ RECT 1848.730000 2827.180000 1849.730000 2827.660000 ;
+ RECT 1848.730000 2832.620000 1849.730000 2833.100000 ;
+ RECT 1835.920000 2832.620000 1837.020000 2833.100000 ;
+ RECT 1835.920000 2827.180000 1837.020000 2827.660000 ;
+ RECT 1835.920000 2816.300000 1837.020000 2816.780000 ;
+ RECT 1835.920000 2821.740000 1837.020000 2822.220000 ;
+ RECT 1848.730000 2816.300000 1849.730000 2816.780000 ;
+ RECT 1848.730000 2821.740000 1849.730000 2822.220000 ;
+ RECT 1848.730000 2805.420000 1849.730000 2805.900000 ;
+ RECT 1848.730000 2799.980000 1849.730000 2800.460000 ;
+ RECT 1848.730000 2810.860000 1849.730000 2811.340000 ;
+ RECT 1835.920000 2810.860000 1837.020000 2811.340000 ;
+ RECT 1835.920000 2805.420000 1837.020000 2805.900000 ;
+ RECT 1835.920000 2799.980000 1837.020000 2800.460000 ;
+ RECT 1790.920000 2827.180000 1792.020000 2827.660000 ;
+ RECT 1790.920000 2832.620000 1792.020000 2833.100000 ;
+ RECT 1790.920000 2838.060000 1792.020000 2838.540000 ;
+ RECT 1790.920000 2843.500000 1792.020000 2843.980000 ;
+ RECT 1790.920000 2799.980000 1792.020000 2800.460000 ;
+ RECT 1790.920000 2805.420000 1792.020000 2805.900000 ;
+ RECT 1790.920000 2810.860000 1792.020000 2811.340000 ;
+ RECT 1790.920000 2816.300000 1792.020000 2816.780000 ;
+ RECT 1790.920000 2821.740000 1792.020000 2822.220000 ;
+ RECT 1835.920000 2789.100000 1837.020000 2789.580000 ;
+ RECT 1835.920000 2794.540000 1837.020000 2795.020000 ;
+ RECT 1848.730000 2789.100000 1849.730000 2789.580000 ;
+ RECT 1848.730000 2794.540000 1849.730000 2795.020000 ;
+ RECT 1835.920000 2778.220000 1837.020000 2778.700000 ;
+ RECT 1835.920000 2783.660000 1837.020000 2784.140000 ;
+ RECT 1848.730000 2778.220000 1849.730000 2778.700000 ;
+ RECT 1848.730000 2783.660000 1849.730000 2784.140000 ;
+ RECT 1848.730000 2767.340000 1849.730000 2767.820000 ;
+ RECT 1848.730000 2761.900000 1849.730000 2762.380000 ;
+ RECT 1848.730000 2772.780000 1849.730000 2773.260000 ;
+ RECT 1835.920000 2772.780000 1837.020000 2773.260000 ;
+ RECT 1835.920000 2767.340000 1837.020000 2767.820000 ;
+ RECT 1835.920000 2761.900000 1837.020000 2762.380000 ;
+ RECT 1835.920000 2756.460000 1837.020000 2756.940000 ;
+ RECT 1848.730000 2756.460000 1849.730000 2756.940000 ;
+ RECT 1790.920000 2778.220000 1792.020000 2778.700000 ;
+ RECT 1790.920000 2783.660000 1792.020000 2784.140000 ;
+ RECT 1790.920000 2789.100000 1792.020000 2789.580000 ;
+ RECT 1790.920000 2794.540000 1792.020000 2795.020000 ;
+ RECT 1790.920000 2756.460000 1792.020000 2756.940000 ;
+ RECT 1790.920000 2761.900000 1792.020000 2762.380000 ;
+ RECT 1790.920000 2767.340000 1792.020000 2767.820000 ;
+ RECT 1790.920000 2772.780000 1792.020000 2773.260000 ;
+ RECT 1745.920000 2827.180000 1747.020000 2827.660000 ;
+ RECT 1745.920000 2832.620000 1747.020000 2833.100000 ;
+ RECT 1745.920000 2838.060000 1747.020000 2838.540000 ;
+ RECT 1745.920000 2843.500000 1747.020000 2843.980000 ;
+ RECT 1700.920000 2827.180000 1702.020000 2827.660000 ;
+ RECT 1700.920000 2832.620000 1702.020000 2833.100000 ;
+ RECT 1700.920000 2838.060000 1702.020000 2838.540000 ;
+ RECT 1700.920000 2843.500000 1702.020000 2843.980000 ;
+ RECT 1745.920000 2799.980000 1747.020000 2800.460000 ;
+ RECT 1745.920000 2805.420000 1747.020000 2805.900000 ;
+ RECT 1745.920000 2810.860000 1747.020000 2811.340000 ;
+ RECT 1745.920000 2816.300000 1747.020000 2816.780000 ;
+ RECT 1745.920000 2821.740000 1747.020000 2822.220000 ;
+ RECT 1700.920000 2799.980000 1702.020000 2800.460000 ;
+ RECT 1700.920000 2805.420000 1702.020000 2805.900000 ;
+ RECT 1700.920000 2810.860000 1702.020000 2811.340000 ;
+ RECT 1700.920000 2816.300000 1702.020000 2816.780000 ;
+ RECT 1700.920000 2821.740000 1702.020000 2822.220000 ;
+ RECT 1652.090000 2843.500000 1653.090000 2843.980000 ;
+ RECT 1655.755000 2843.500000 1657.020000 2843.980000 ;
+ RECT 1652.090000 2838.060000 1653.090000 2838.540000 ;
+ RECT 1655.755000 2838.060000 1657.020000 2838.540000 ;
+ RECT 1652.090000 2832.620000 1653.090000 2833.100000 ;
+ RECT 1655.755000 2832.620000 1657.020000 2833.100000 ;
+ RECT 1652.090000 2827.180000 1653.090000 2827.660000 ;
+ RECT 1655.755000 2827.180000 1657.020000 2827.660000 ;
+ RECT 1652.090000 2821.740000 1653.090000 2822.220000 ;
+ RECT 1655.755000 2821.740000 1657.020000 2822.220000 ;
+ RECT 1652.090000 2816.300000 1653.090000 2816.780000 ;
+ RECT 1655.755000 2816.300000 1657.020000 2816.780000 ;
+ RECT 1652.090000 2805.420000 1653.090000 2805.900000 ;
+ RECT 1655.755000 2805.420000 1657.020000 2805.900000 ;
+ RECT 1652.090000 2810.860000 1653.090000 2811.340000 ;
+ RECT 1655.755000 2810.860000 1657.020000 2811.340000 ;
+ RECT 1652.090000 2799.980000 1653.090000 2800.460000 ;
+ RECT 1655.755000 2799.980000 1657.020000 2800.460000 ;
+ RECT 1745.920000 2778.220000 1747.020000 2778.700000 ;
+ RECT 1745.920000 2783.660000 1747.020000 2784.140000 ;
+ RECT 1745.920000 2789.100000 1747.020000 2789.580000 ;
+ RECT 1745.920000 2794.540000 1747.020000 2795.020000 ;
+ RECT 1700.920000 2778.220000 1702.020000 2778.700000 ;
+ RECT 1700.920000 2783.660000 1702.020000 2784.140000 ;
+ RECT 1700.920000 2789.100000 1702.020000 2789.580000 ;
+ RECT 1700.920000 2794.540000 1702.020000 2795.020000 ;
+ RECT 1745.920000 2756.460000 1747.020000 2756.940000 ;
+ RECT 1745.920000 2761.900000 1747.020000 2762.380000 ;
+ RECT 1745.920000 2767.340000 1747.020000 2767.820000 ;
+ RECT 1745.920000 2772.780000 1747.020000 2773.260000 ;
+ RECT 1700.920000 2756.460000 1702.020000 2756.940000 ;
+ RECT 1700.920000 2761.900000 1702.020000 2762.380000 ;
+ RECT 1700.920000 2767.340000 1702.020000 2767.820000 ;
+ RECT 1700.920000 2772.780000 1702.020000 2773.260000 ;
+ RECT 1652.090000 2794.540000 1653.090000 2795.020000 ;
+ RECT 1655.755000 2794.540000 1657.020000 2795.020000 ;
+ RECT 1652.090000 2789.100000 1653.090000 2789.580000 ;
+ RECT 1655.755000 2789.100000 1657.020000 2789.580000 ;
+ RECT 1652.090000 2783.660000 1653.090000 2784.140000 ;
+ RECT 1655.755000 2783.660000 1657.020000 2784.140000 ;
+ RECT 1652.090000 2778.220000 1653.090000 2778.700000 ;
+ RECT 1655.755000 2778.220000 1657.020000 2778.700000 ;
+ RECT 1652.090000 2772.780000 1653.090000 2773.260000 ;
+ RECT 1655.755000 2772.780000 1657.020000 2773.260000 ;
+ RECT 1652.090000 2761.900000 1653.090000 2762.380000 ;
+ RECT 1655.755000 2761.900000 1657.020000 2762.380000 ;
+ RECT 1652.090000 2767.340000 1653.090000 2767.820000 ;
+ RECT 1655.755000 2767.340000 1657.020000 2767.820000 ;
+ RECT 1652.090000 2756.460000 1653.090000 2756.940000 ;
+ RECT 1655.755000 2756.460000 1657.020000 2756.940000 ;
+ RECT 1790.920000 2848.940000 1792.020000 2849.420000 ;
+ RECT 1835.920000 2848.940000 1837.020000 2849.420000 ;
+ RECT 1848.730000 2848.940000 1849.730000 2849.420000 ;
+ RECT 1700.920000 2848.940000 1702.020000 2849.420000 ;
+ RECT 1745.920000 2848.940000 1747.020000 2849.420000 ;
+ RECT 1652.090000 2848.940000 1653.090000 2849.420000 ;
+ RECT 1655.755000 2848.940000 1657.020000 2849.420000 ;
+ RECT 1650.860000 2945.700000 1850.960000 2946.700000 ;
+ RECT 1650.860000 2750.130000 1850.960000 2751.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 2748.880000 1653.090000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 2948.140000 1653.090000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 2748.880000 1849.730000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 2948.140000 1849.730000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2750.130000 1651.860000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2750.130000 1850.960000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2945.700000 1651.860000 2946.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2945.700000 1850.960000 2946.700000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 2741.160000 1657.020000 2741.640000 ;
+ RECT 1655.755000 2730.280000 1657.020000 2730.760000 ;
+ RECT 1655.755000 2735.720000 1657.020000 2736.200000 ;
+ RECT 1655.755000 2724.840000 1657.020000 2725.320000 ;
+ RECT 1655.755000 2719.400000 1657.020000 2719.880000 ;
+ RECT 1655.755000 2713.960000 1657.020000 2714.440000 ;
+ RECT 1655.755000 2708.520000 1657.020000 2709.000000 ;
+ RECT 1655.755000 2703.080000 1657.020000 2703.560000 ;
+ RECT 1655.755000 2697.640000 1657.020000 2698.120000 ;
+ RECT 1655.755000 2686.760000 1657.020000 2687.240000 ;
+ RECT 1655.755000 2692.200000 1657.020000 2692.680000 ;
+ RECT 1655.755000 2681.320000 1657.020000 2681.800000 ;
+ RECT 1655.755000 2675.880000 1657.020000 2676.360000 ;
+ RECT 1655.755000 2670.440000 1657.020000 2670.920000 ;
+ RECT 1655.755000 2665.000000 1657.020000 2665.480000 ;
+ RECT 1655.755000 2659.560000 1657.020000 2660.040000 ;
+ RECT 1655.755000 2654.120000 1657.020000 2654.600000 ;
+ RECT 1655.755000 2643.240000 1657.020000 2643.720000 ;
+ RECT 1655.755000 2637.800000 1657.020000 2638.280000 ;
+ RECT 1655.755000 2632.360000 1657.020000 2632.840000 ;
+ RECT 1655.755000 2626.920000 1657.020000 2627.400000 ;
+ RECT 1655.755000 2621.480000 1657.020000 2621.960000 ;
+ RECT 1655.755000 2616.040000 1657.020000 2616.520000 ;
+ RECT 1655.755000 2605.160000 1657.020000 2605.640000 ;
+ RECT 1655.755000 2610.600000 1657.020000 2611.080000 ;
+ RECT 1655.755000 2599.720000 1657.020000 2600.200000 ;
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+ RECT 1655.755000 2588.840000 1657.020000 2589.320000 ;
+ RECT 1655.755000 2583.400000 1657.020000 2583.880000 ;
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+ RECT 1655.755000 2572.520000 1657.020000 2573.000000 ;
+ RECT 1655.755000 2561.640000 1657.020000 2562.120000 ;
+ RECT 1655.755000 2567.080000 1657.020000 2567.560000 ;
+ RECT 1655.755000 2556.200000 1657.020000 2556.680000 ;
+ RECT 1655.755000 2648.680000 1657.020000 2649.160000 ;
+ RECT 1835.920000 2549.870000 1837.020000 2746.440000 ;
+ RECT 1790.920000 2549.870000 1792.020000 2746.440000 ;
+ RECT 1848.730000 2548.620000 1849.730000 2748.880000 ;
+ RECT 1745.920000 2549.870000 1747.020000 2746.440000 ;
+ RECT 1700.920000 2549.870000 1702.020000 2746.440000 ;
+ RECT 1655.920000 2549.870000 1657.020000 2746.440000 ;
+ RECT 1652.090000 2548.620000 1653.090000 2748.880000 ;
+ LAYER met3 ;
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+ RECT 1848.730000 2741.160000 1849.730000 2741.640000 ;
+ RECT 1848.730000 2730.280000 1849.730000 2730.760000 ;
+ RECT 1848.730000 2724.840000 1849.730000 2725.320000 ;
+ RECT 1848.730000 2735.720000 1849.730000 2736.200000 ;
+ RECT 1835.920000 2735.720000 1837.020000 2736.200000 ;
+ RECT 1835.920000 2730.280000 1837.020000 2730.760000 ;
+ RECT 1835.920000 2724.840000 1837.020000 2725.320000 ;
+ RECT 1835.920000 2713.960000 1837.020000 2714.440000 ;
+ RECT 1835.920000 2719.400000 1837.020000 2719.880000 ;
+ RECT 1848.730000 2713.960000 1849.730000 2714.440000 ;
+ RECT 1848.730000 2719.400000 1849.730000 2719.880000 ;
+ RECT 1835.920000 2703.080000 1837.020000 2703.560000 ;
+ RECT 1835.920000 2708.520000 1837.020000 2709.000000 ;
+ RECT 1848.730000 2703.080000 1849.730000 2703.560000 ;
+ RECT 1848.730000 2708.520000 1849.730000 2709.000000 ;
+ RECT 1790.920000 2724.840000 1792.020000 2725.320000 ;
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+ RECT 1790.920000 2735.720000 1792.020000 2736.200000 ;
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+ RECT 1790.920000 2703.080000 1792.020000 2703.560000 ;
+ RECT 1790.920000 2713.960000 1792.020000 2714.440000 ;
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+ RECT 1848.730000 2692.200000 1849.730000 2692.680000 ;
+ RECT 1848.730000 2686.760000 1849.730000 2687.240000 ;
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+ RECT 1848.730000 2675.880000 1849.730000 2676.360000 ;
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+ RECT 1848.730000 2665.000000 1849.730000 2665.480000 ;
+ RECT 1848.730000 2670.440000 1849.730000 2670.920000 ;
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+ RECT 1848.730000 2659.560000 1849.730000 2660.040000 ;
+ RECT 1790.920000 2675.880000 1792.020000 2676.360000 ;
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+ RECT 1790.920000 2670.440000 1792.020000 2670.920000 ;
+ RECT 1745.920000 2730.280000 1747.020000 2730.760000 ;
+ RECT 1745.920000 2724.840000 1747.020000 2725.320000 ;
+ RECT 1745.920000 2735.720000 1747.020000 2736.200000 ;
+ RECT 1745.920000 2741.160000 1747.020000 2741.640000 ;
+ RECT 1700.920000 2724.840000 1702.020000 2725.320000 ;
+ RECT 1700.920000 2730.280000 1702.020000 2730.760000 ;
+ RECT 1700.920000 2735.720000 1702.020000 2736.200000 ;
+ RECT 1700.920000 2741.160000 1702.020000 2741.640000 ;
+ RECT 1745.920000 2703.080000 1747.020000 2703.560000 ;
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+ RECT 1745.920000 2713.960000 1747.020000 2714.440000 ;
+ RECT 1745.920000 2719.400000 1747.020000 2719.880000 ;
+ RECT 1700.920000 2703.080000 1702.020000 2703.560000 ;
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+ RECT 1700.920000 2713.960000 1702.020000 2714.440000 ;
+ RECT 1700.920000 2719.400000 1702.020000 2719.880000 ;
+ RECT 1652.090000 2741.160000 1653.090000 2741.640000 ;
+ RECT 1655.755000 2741.160000 1657.020000 2741.640000 ;
+ RECT 1652.090000 2730.280000 1653.090000 2730.760000 ;
+ RECT 1655.755000 2730.280000 1657.020000 2730.760000 ;
+ RECT 1652.090000 2735.720000 1653.090000 2736.200000 ;
+ RECT 1655.755000 2735.720000 1657.020000 2736.200000 ;
+ RECT 1652.090000 2724.840000 1653.090000 2725.320000 ;
+ RECT 1655.755000 2724.840000 1657.020000 2725.320000 ;
+ RECT 1652.090000 2719.400000 1653.090000 2719.880000 ;
+ RECT 1655.755000 2719.400000 1657.020000 2719.880000 ;
+ RECT 1652.090000 2713.960000 1653.090000 2714.440000 ;
+ RECT 1655.755000 2713.960000 1657.020000 2714.440000 ;
+ RECT 1652.090000 2708.520000 1653.090000 2709.000000 ;
+ RECT 1655.755000 2708.520000 1657.020000 2709.000000 ;
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+ RECT 1655.755000 2703.080000 1657.020000 2703.560000 ;
+ RECT 1745.920000 2675.880000 1747.020000 2676.360000 ;
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+ RECT 1745.920000 2686.760000 1747.020000 2687.240000 ;
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+ RECT 1700.920000 2686.760000 1702.020000 2687.240000 ;
+ RECT 1700.920000 2692.200000 1702.020000 2692.680000 ;
+ RECT 1700.920000 2697.640000 1702.020000 2698.120000 ;
+ RECT 1745.920000 2654.120000 1747.020000 2654.600000 ;
+ RECT 1745.920000 2659.560000 1747.020000 2660.040000 ;
+ RECT 1745.920000 2665.000000 1747.020000 2665.480000 ;
+ RECT 1745.920000 2670.440000 1747.020000 2670.920000 ;
+ RECT 1700.920000 2654.120000 1702.020000 2654.600000 ;
+ RECT 1700.920000 2659.560000 1702.020000 2660.040000 ;
+ RECT 1700.920000 2665.000000 1702.020000 2665.480000 ;
+ RECT 1700.920000 2670.440000 1702.020000 2670.920000 ;
+ RECT 1652.090000 2697.640000 1653.090000 2698.120000 ;
+ RECT 1655.755000 2697.640000 1657.020000 2698.120000 ;
+ RECT 1652.090000 2686.760000 1653.090000 2687.240000 ;
+ RECT 1655.755000 2686.760000 1657.020000 2687.240000 ;
+ RECT 1652.090000 2692.200000 1653.090000 2692.680000 ;
+ RECT 1655.755000 2692.200000 1657.020000 2692.680000 ;
+ RECT 1652.090000 2681.320000 1653.090000 2681.800000 ;
+ RECT 1655.755000 2681.320000 1657.020000 2681.800000 ;
+ RECT 1652.090000 2675.880000 1653.090000 2676.360000 ;
+ RECT 1655.755000 2675.880000 1657.020000 2676.360000 ;
+ RECT 1652.090000 2670.440000 1653.090000 2670.920000 ;
+ RECT 1655.755000 2670.440000 1657.020000 2670.920000 ;
+ RECT 1652.090000 2665.000000 1653.090000 2665.480000 ;
+ RECT 1655.755000 2665.000000 1657.020000 2665.480000 ;
+ RECT 1652.090000 2659.560000 1653.090000 2660.040000 ;
+ RECT 1655.755000 2659.560000 1657.020000 2660.040000 ;
+ RECT 1652.090000 2654.120000 1653.090000 2654.600000 ;
+ RECT 1655.755000 2654.120000 1657.020000 2654.600000 ;
+ RECT 1835.920000 2637.800000 1837.020000 2638.280000 ;
+ RECT 1835.920000 2643.240000 1837.020000 2643.720000 ;
+ RECT 1848.730000 2637.800000 1849.730000 2638.280000 ;
+ RECT 1848.730000 2643.240000 1849.730000 2643.720000 ;
+ RECT 1848.730000 2626.920000 1849.730000 2627.400000 ;
+ RECT 1848.730000 2632.360000 1849.730000 2632.840000 ;
+ RECT 1835.920000 2632.360000 1837.020000 2632.840000 ;
+ RECT 1835.920000 2626.920000 1837.020000 2627.400000 ;
+ RECT 1835.920000 2616.040000 1837.020000 2616.520000 ;
+ RECT 1835.920000 2621.480000 1837.020000 2621.960000 ;
+ RECT 1848.730000 2616.040000 1849.730000 2616.520000 ;
+ RECT 1848.730000 2621.480000 1849.730000 2621.960000 ;
+ RECT 1848.730000 2605.160000 1849.730000 2605.640000 ;
+ RECT 1848.730000 2599.720000 1849.730000 2600.200000 ;
+ RECT 1848.730000 2610.600000 1849.730000 2611.080000 ;
+ RECT 1835.920000 2610.600000 1837.020000 2611.080000 ;
+ RECT 1835.920000 2605.160000 1837.020000 2605.640000 ;
+ RECT 1835.920000 2599.720000 1837.020000 2600.200000 ;
+ RECT 1790.920000 2626.920000 1792.020000 2627.400000 ;
+ RECT 1790.920000 2632.360000 1792.020000 2632.840000 ;
+ RECT 1790.920000 2637.800000 1792.020000 2638.280000 ;
+ RECT 1790.920000 2643.240000 1792.020000 2643.720000 ;
+ RECT 1790.920000 2599.720000 1792.020000 2600.200000 ;
+ RECT 1790.920000 2605.160000 1792.020000 2605.640000 ;
+ RECT 1790.920000 2610.600000 1792.020000 2611.080000 ;
+ RECT 1790.920000 2616.040000 1792.020000 2616.520000 ;
+ RECT 1790.920000 2621.480000 1792.020000 2621.960000 ;
+ RECT 1835.920000 2588.840000 1837.020000 2589.320000 ;
+ RECT 1835.920000 2594.280000 1837.020000 2594.760000 ;
+ RECT 1848.730000 2588.840000 1849.730000 2589.320000 ;
+ RECT 1848.730000 2594.280000 1849.730000 2594.760000 ;
+ RECT 1835.920000 2577.960000 1837.020000 2578.440000 ;
+ RECT 1835.920000 2583.400000 1837.020000 2583.880000 ;
+ RECT 1848.730000 2577.960000 1849.730000 2578.440000 ;
+ RECT 1848.730000 2583.400000 1849.730000 2583.880000 ;
+ RECT 1848.730000 2567.080000 1849.730000 2567.560000 ;
+ RECT 1848.730000 2561.640000 1849.730000 2562.120000 ;
+ RECT 1848.730000 2572.520000 1849.730000 2573.000000 ;
+ RECT 1835.920000 2572.520000 1837.020000 2573.000000 ;
+ RECT 1835.920000 2567.080000 1837.020000 2567.560000 ;
+ RECT 1835.920000 2561.640000 1837.020000 2562.120000 ;
+ RECT 1835.920000 2556.200000 1837.020000 2556.680000 ;
+ RECT 1848.730000 2556.200000 1849.730000 2556.680000 ;
+ RECT 1790.920000 2577.960000 1792.020000 2578.440000 ;
+ RECT 1790.920000 2583.400000 1792.020000 2583.880000 ;
+ RECT 1790.920000 2588.840000 1792.020000 2589.320000 ;
+ RECT 1790.920000 2594.280000 1792.020000 2594.760000 ;
+ RECT 1790.920000 2556.200000 1792.020000 2556.680000 ;
+ RECT 1790.920000 2561.640000 1792.020000 2562.120000 ;
+ RECT 1790.920000 2567.080000 1792.020000 2567.560000 ;
+ RECT 1790.920000 2572.520000 1792.020000 2573.000000 ;
+ RECT 1745.920000 2626.920000 1747.020000 2627.400000 ;
+ RECT 1745.920000 2632.360000 1747.020000 2632.840000 ;
+ RECT 1745.920000 2637.800000 1747.020000 2638.280000 ;
+ RECT 1745.920000 2643.240000 1747.020000 2643.720000 ;
+ RECT 1700.920000 2626.920000 1702.020000 2627.400000 ;
+ RECT 1700.920000 2632.360000 1702.020000 2632.840000 ;
+ RECT 1700.920000 2637.800000 1702.020000 2638.280000 ;
+ RECT 1700.920000 2643.240000 1702.020000 2643.720000 ;
+ RECT 1745.920000 2599.720000 1747.020000 2600.200000 ;
+ RECT 1745.920000 2605.160000 1747.020000 2605.640000 ;
+ RECT 1745.920000 2610.600000 1747.020000 2611.080000 ;
+ RECT 1745.920000 2616.040000 1747.020000 2616.520000 ;
+ RECT 1745.920000 2621.480000 1747.020000 2621.960000 ;
+ RECT 1700.920000 2599.720000 1702.020000 2600.200000 ;
+ RECT 1700.920000 2605.160000 1702.020000 2605.640000 ;
+ RECT 1700.920000 2610.600000 1702.020000 2611.080000 ;
+ RECT 1700.920000 2616.040000 1702.020000 2616.520000 ;
+ RECT 1700.920000 2621.480000 1702.020000 2621.960000 ;
+ RECT 1652.090000 2643.240000 1653.090000 2643.720000 ;
+ RECT 1655.755000 2643.240000 1657.020000 2643.720000 ;
+ RECT 1652.090000 2637.800000 1653.090000 2638.280000 ;
+ RECT 1655.755000 2637.800000 1657.020000 2638.280000 ;
+ RECT 1652.090000 2632.360000 1653.090000 2632.840000 ;
+ RECT 1655.755000 2632.360000 1657.020000 2632.840000 ;
+ RECT 1652.090000 2626.920000 1653.090000 2627.400000 ;
+ RECT 1655.755000 2626.920000 1657.020000 2627.400000 ;
+ RECT 1652.090000 2621.480000 1653.090000 2621.960000 ;
+ RECT 1655.755000 2621.480000 1657.020000 2621.960000 ;
+ RECT 1652.090000 2616.040000 1653.090000 2616.520000 ;
+ RECT 1655.755000 2616.040000 1657.020000 2616.520000 ;
+ RECT 1652.090000 2605.160000 1653.090000 2605.640000 ;
+ RECT 1655.755000 2605.160000 1657.020000 2605.640000 ;
+ RECT 1652.090000 2610.600000 1653.090000 2611.080000 ;
+ RECT 1655.755000 2610.600000 1657.020000 2611.080000 ;
+ RECT 1652.090000 2599.720000 1653.090000 2600.200000 ;
+ RECT 1655.755000 2599.720000 1657.020000 2600.200000 ;
+ RECT 1745.920000 2577.960000 1747.020000 2578.440000 ;
+ RECT 1745.920000 2583.400000 1747.020000 2583.880000 ;
+ RECT 1745.920000 2588.840000 1747.020000 2589.320000 ;
+ RECT 1745.920000 2594.280000 1747.020000 2594.760000 ;
+ RECT 1700.920000 2577.960000 1702.020000 2578.440000 ;
+ RECT 1700.920000 2583.400000 1702.020000 2583.880000 ;
+ RECT 1700.920000 2588.840000 1702.020000 2589.320000 ;
+ RECT 1700.920000 2594.280000 1702.020000 2594.760000 ;
+ RECT 1745.920000 2556.200000 1747.020000 2556.680000 ;
+ RECT 1745.920000 2561.640000 1747.020000 2562.120000 ;
+ RECT 1745.920000 2567.080000 1747.020000 2567.560000 ;
+ RECT 1745.920000 2572.520000 1747.020000 2573.000000 ;
+ RECT 1700.920000 2556.200000 1702.020000 2556.680000 ;
+ RECT 1700.920000 2561.640000 1702.020000 2562.120000 ;
+ RECT 1700.920000 2567.080000 1702.020000 2567.560000 ;
+ RECT 1700.920000 2572.520000 1702.020000 2573.000000 ;
+ RECT 1652.090000 2594.280000 1653.090000 2594.760000 ;
+ RECT 1655.755000 2594.280000 1657.020000 2594.760000 ;
+ RECT 1652.090000 2588.840000 1653.090000 2589.320000 ;
+ RECT 1655.755000 2588.840000 1657.020000 2589.320000 ;
+ RECT 1652.090000 2583.400000 1653.090000 2583.880000 ;
+ RECT 1655.755000 2583.400000 1657.020000 2583.880000 ;
+ RECT 1652.090000 2577.960000 1653.090000 2578.440000 ;
+ RECT 1655.755000 2577.960000 1657.020000 2578.440000 ;
+ RECT 1652.090000 2572.520000 1653.090000 2573.000000 ;
+ RECT 1655.755000 2572.520000 1657.020000 2573.000000 ;
+ RECT 1652.090000 2561.640000 1653.090000 2562.120000 ;
+ RECT 1655.755000 2561.640000 1657.020000 2562.120000 ;
+ RECT 1652.090000 2567.080000 1653.090000 2567.560000 ;
+ RECT 1655.755000 2567.080000 1657.020000 2567.560000 ;
+ RECT 1652.090000 2556.200000 1653.090000 2556.680000 ;
+ RECT 1655.755000 2556.200000 1657.020000 2556.680000 ;
+ RECT 1790.920000 2648.680000 1792.020000 2649.160000 ;
+ RECT 1835.920000 2648.680000 1837.020000 2649.160000 ;
+ RECT 1848.730000 2648.680000 1849.730000 2649.160000 ;
+ RECT 1700.920000 2648.680000 1702.020000 2649.160000 ;
+ RECT 1745.920000 2648.680000 1747.020000 2649.160000 ;
+ RECT 1652.090000 2648.680000 1653.090000 2649.160000 ;
+ RECT 1655.755000 2648.680000 1657.020000 2649.160000 ;
+ RECT 1650.860000 2745.440000 1850.960000 2746.440000 ;
+ RECT 1650.860000 2549.870000 1850.960000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 2548.620000 1653.090000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 2747.880000 1653.090000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 2548.620000 1849.730000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 2747.880000 1849.730000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2549.870000 1651.860000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2549.870000 1850.960000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2745.440000 1651.860000 2746.440000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2745.440000 1850.960000 2746.440000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 2540.900000 1657.020000 2541.380000 ;
+ RECT 1655.755000 2530.020000 1657.020000 2530.500000 ;
+ RECT 1655.755000 2535.460000 1657.020000 2535.940000 ;
+ RECT 1655.755000 2524.580000 1657.020000 2525.060000 ;
+ RECT 1655.755000 2519.140000 1657.020000 2519.620000 ;
+ RECT 1655.755000 2513.700000 1657.020000 2514.180000 ;
+ RECT 1655.755000 2508.260000 1657.020000 2508.740000 ;
+ RECT 1655.755000 2502.820000 1657.020000 2503.300000 ;
+ RECT 1655.755000 2497.380000 1657.020000 2497.860000 ;
+ RECT 1655.755000 2486.500000 1657.020000 2486.980000 ;
+ RECT 1655.755000 2491.940000 1657.020000 2492.420000 ;
+ RECT 1655.755000 2481.060000 1657.020000 2481.540000 ;
+ RECT 1655.755000 2475.620000 1657.020000 2476.100000 ;
+ RECT 1655.755000 2470.180000 1657.020000 2470.660000 ;
+ RECT 1655.755000 2464.740000 1657.020000 2465.220000 ;
+ RECT 1655.755000 2459.300000 1657.020000 2459.780000 ;
+ RECT 1655.755000 2453.860000 1657.020000 2454.340000 ;
+ RECT 1655.755000 2442.980000 1657.020000 2443.460000 ;
+ RECT 1655.755000 2437.540000 1657.020000 2438.020000 ;
+ RECT 1655.755000 2432.100000 1657.020000 2432.580000 ;
+ RECT 1655.755000 2426.660000 1657.020000 2427.140000 ;
+ RECT 1655.755000 2421.220000 1657.020000 2421.700000 ;
+ RECT 1655.755000 2415.780000 1657.020000 2416.260000 ;
+ RECT 1655.755000 2404.900000 1657.020000 2405.380000 ;
+ RECT 1655.755000 2410.340000 1657.020000 2410.820000 ;
+ RECT 1655.755000 2399.460000 1657.020000 2399.940000 ;
+ RECT 1655.755000 2394.020000 1657.020000 2394.500000 ;
+ RECT 1655.755000 2388.580000 1657.020000 2389.060000 ;
+ RECT 1655.755000 2383.140000 1657.020000 2383.620000 ;
+ RECT 1655.755000 2377.700000 1657.020000 2378.180000 ;
+ RECT 1655.755000 2372.260000 1657.020000 2372.740000 ;
+ RECT 1655.755000 2361.380000 1657.020000 2361.860000 ;
+ RECT 1655.755000 2366.820000 1657.020000 2367.300000 ;
+ RECT 1655.755000 2355.940000 1657.020000 2356.420000 ;
+ RECT 1655.755000 2448.420000 1657.020000 2448.900000 ;
+ RECT 1835.920000 2349.610000 1837.020000 2546.180000 ;
+ RECT 1790.920000 2349.610000 1792.020000 2546.180000 ;
+ RECT 1848.730000 2348.360000 1849.730000 2548.620000 ;
+ RECT 1745.920000 2349.610000 1747.020000 2546.180000 ;
+ RECT 1700.920000 2349.610000 1702.020000 2546.180000 ;
+ RECT 1655.920000 2349.610000 1657.020000 2546.180000 ;
+ RECT 1652.090000 2348.360000 1653.090000 2548.620000 ;
+ LAYER met3 ;
+ RECT 1835.920000 2540.900000 1837.020000 2541.380000 ;
+ RECT 1848.730000 2540.900000 1849.730000 2541.380000 ;
+ RECT 1848.730000 2530.020000 1849.730000 2530.500000 ;
+ RECT 1848.730000 2524.580000 1849.730000 2525.060000 ;
+ RECT 1848.730000 2535.460000 1849.730000 2535.940000 ;
+ RECT 1835.920000 2535.460000 1837.020000 2535.940000 ;
+ RECT 1835.920000 2530.020000 1837.020000 2530.500000 ;
+ RECT 1835.920000 2524.580000 1837.020000 2525.060000 ;
+ RECT 1835.920000 2513.700000 1837.020000 2514.180000 ;
+ RECT 1835.920000 2519.140000 1837.020000 2519.620000 ;
+ RECT 1848.730000 2513.700000 1849.730000 2514.180000 ;
+ RECT 1848.730000 2519.140000 1849.730000 2519.620000 ;
+ RECT 1835.920000 2502.820000 1837.020000 2503.300000 ;
+ RECT 1835.920000 2508.260000 1837.020000 2508.740000 ;
+ RECT 1848.730000 2502.820000 1849.730000 2503.300000 ;
+ RECT 1848.730000 2508.260000 1849.730000 2508.740000 ;
+ RECT 1790.920000 2524.580000 1792.020000 2525.060000 ;
+ RECT 1790.920000 2530.020000 1792.020000 2530.500000 ;
+ RECT 1790.920000 2535.460000 1792.020000 2535.940000 ;
+ RECT 1790.920000 2540.900000 1792.020000 2541.380000 ;
+ RECT 1790.920000 2508.260000 1792.020000 2508.740000 ;
+ RECT 1790.920000 2502.820000 1792.020000 2503.300000 ;
+ RECT 1790.920000 2513.700000 1792.020000 2514.180000 ;
+ RECT 1790.920000 2519.140000 1792.020000 2519.620000 ;
+ RECT 1848.730000 2491.940000 1849.730000 2492.420000 ;
+ RECT 1848.730000 2486.500000 1849.730000 2486.980000 ;
+ RECT 1848.730000 2497.380000 1849.730000 2497.860000 ;
+ RECT 1835.920000 2497.380000 1837.020000 2497.860000 ;
+ RECT 1835.920000 2491.940000 1837.020000 2492.420000 ;
+ RECT 1835.920000 2486.500000 1837.020000 2486.980000 ;
+ RECT 1835.920000 2475.620000 1837.020000 2476.100000 ;
+ RECT 1835.920000 2481.060000 1837.020000 2481.540000 ;
+ RECT 1848.730000 2475.620000 1849.730000 2476.100000 ;
+ RECT 1848.730000 2481.060000 1849.730000 2481.540000 ;
+ RECT 1848.730000 2464.740000 1849.730000 2465.220000 ;
+ RECT 1848.730000 2470.180000 1849.730000 2470.660000 ;
+ RECT 1835.920000 2470.180000 1837.020000 2470.660000 ;
+ RECT 1835.920000 2464.740000 1837.020000 2465.220000 ;
+ RECT 1835.920000 2453.860000 1837.020000 2454.340000 ;
+ RECT 1835.920000 2459.300000 1837.020000 2459.780000 ;
+ RECT 1848.730000 2453.860000 1849.730000 2454.340000 ;
+ RECT 1848.730000 2459.300000 1849.730000 2459.780000 ;
+ RECT 1790.920000 2475.620000 1792.020000 2476.100000 ;
+ RECT 1790.920000 2481.060000 1792.020000 2481.540000 ;
+ RECT 1790.920000 2486.500000 1792.020000 2486.980000 ;
+ RECT 1790.920000 2491.940000 1792.020000 2492.420000 ;
+ RECT 1790.920000 2497.380000 1792.020000 2497.860000 ;
+ RECT 1790.920000 2453.860000 1792.020000 2454.340000 ;
+ RECT 1790.920000 2459.300000 1792.020000 2459.780000 ;
+ RECT 1790.920000 2464.740000 1792.020000 2465.220000 ;
+ RECT 1790.920000 2470.180000 1792.020000 2470.660000 ;
+ RECT 1745.920000 2530.020000 1747.020000 2530.500000 ;
+ RECT 1745.920000 2524.580000 1747.020000 2525.060000 ;
+ RECT 1745.920000 2535.460000 1747.020000 2535.940000 ;
+ RECT 1745.920000 2540.900000 1747.020000 2541.380000 ;
+ RECT 1700.920000 2524.580000 1702.020000 2525.060000 ;
+ RECT 1700.920000 2530.020000 1702.020000 2530.500000 ;
+ RECT 1700.920000 2535.460000 1702.020000 2535.940000 ;
+ RECT 1700.920000 2540.900000 1702.020000 2541.380000 ;
+ RECT 1745.920000 2502.820000 1747.020000 2503.300000 ;
+ RECT 1745.920000 2508.260000 1747.020000 2508.740000 ;
+ RECT 1745.920000 2513.700000 1747.020000 2514.180000 ;
+ RECT 1745.920000 2519.140000 1747.020000 2519.620000 ;
+ RECT 1700.920000 2502.820000 1702.020000 2503.300000 ;
+ RECT 1700.920000 2508.260000 1702.020000 2508.740000 ;
+ RECT 1700.920000 2513.700000 1702.020000 2514.180000 ;
+ RECT 1700.920000 2519.140000 1702.020000 2519.620000 ;
+ RECT 1652.090000 2540.900000 1653.090000 2541.380000 ;
+ RECT 1655.755000 2540.900000 1657.020000 2541.380000 ;
+ RECT 1652.090000 2530.020000 1653.090000 2530.500000 ;
+ RECT 1655.755000 2530.020000 1657.020000 2530.500000 ;
+ RECT 1652.090000 2535.460000 1653.090000 2535.940000 ;
+ RECT 1655.755000 2535.460000 1657.020000 2535.940000 ;
+ RECT 1652.090000 2524.580000 1653.090000 2525.060000 ;
+ RECT 1655.755000 2524.580000 1657.020000 2525.060000 ;
+ RECT 1652.090000 2519.140000 1653.090000 2519.620000 ;
+ RECT 1655.755000 2519.140000 1657.020000 2519.620000 ;
+ RECT 1652.090000 2513.700000 1653.090000 2514.180000 ;
+ RECT 1655.755000 2513.700000 1657.020000 2514.180000 ;
+ RECT 1652.090000 2508.260000 1653.090000 2508.740000 ;
+ RECT 1655.755000 2508.260000 1657.020000 2508.740000 ;
+ RECT 1652.090000 2502.820000 1653.090000 2503.300000 ;
+ RECT 1655.755000 2502.820000 1657.020000 2503.300000 ;
+ RECT 1745.920000 2475.620000 1747.020000 2476.100000 ;
+ RECT 1745.920000 2481.060000 1747.020000 2481.540000 ;
+ RECT 1745.920000 2486.500000 1747.020000 2486.980000 ;
+ RECT 1745.920000 2491.940000 1747.020000 2492.420000 ;
+ RECT 1745.920000 2497.380000 1747.020000 2497.860000 ;
+ RECT 1700.920000 2475.620000 1702.020000 2476.100000 ;
+ RECT 1700.920000 2481.060000 1702.020000 2481.540000 ;
+ RECT 1700.920000 2486.500000 1702.020000 2486.980000 ;
+ RECT 1700.920000 2491.940000 1702.020000 2492.420000 ;
+ RECT 1700.920000 2497.380000 1702.020000 2497.860000 ;
+ RECT 1745.920000 2453.860000 1747.020000 2454.340000 ;
+ RECT 1745.920000 2459.300000 1747.020000 2459.780000 ;
+ RECT 1745.920000 2464.740000 1747.020000 2465.220000 ;
+ RECT 1745.920000 2470.180000 1747.020000 2470.660000 ;
+ RECT 1700.920000 2453.860000 1702.020000 2454.340000 ;
+ RECT 1700.920000 2459.300000 1702.020000 2459.780000 ;
+ RECT 1700.920000 2464.740000 1702.020000 2465.220000 ;
+ RECT 1700.920000 2470.180000 1702.020000 2470.660000 ;
+ RECT 1652.090000 2497.380000 1653.090000 2497.860000 ;
+ RECT 1655.755000 2497.380000 1657.020000 2497.860000 ;
+ RECT 1652.090000 2486.500000 1653.090000 2486.980000 ;
+ RECT 1655.755000 2486.500000 1657.020000 2486.980000 ;
+ RECT 1652.090000 2491.940000 1653.090000 2492.420000 ;
+ RECT 1655.755000 2491.940000 1657.020000 2492.420000 ;
+ RECT 1652.090000 2481.060000 1653.090000 2481.540000 ;
+ RECT 1655.755000 2481.060000 1657.020000 2481.540000 ;
+ RECT 1652.090000 2475.620000 1653.090000 2476.100000 ;
+ RECT 1655.755000 2475.620000 1657.020000 2476.100000 ;
+ RECT 1652.090000 2470.180000 1653.090000 2470.660000 ;
+ RECT 1655.755000 2470.180000 1657.020000 2470.660000 ;
+ RECT 1652.090000 2464.740000 1653.090000 2465.220000 ;
+ RECT 1655.755000 2464.740000 1657.020000 2465.220000 ;
+ RECT 1652.090000 2459.300000 1653.090000 2459.780000 ;
+ RECT 1655.755000 2459.300000 1657.020000 2459.780000 ;
+ RECT 1652.090000 2453.860000 1653.090000 2454.340000 ;
+ RECT 1655.755000 2453.860000 1657.020000 2454.340000 ;
+ RECT 1835.920000 2437.540000 1837.020000 2438.020000 ;
+ RECT 1835.920000 2442.980000 1837.020000 2443.460000 ;
+ RECT 1848.730000 2437.540000 1849.730000 2438.020000 ;
+ RECT 1848.730000 2442.980000 1849.730000 2443.460000 ;
+ RECT 1848.730000 2426.660000 1849.730000 2427.140000 ;
+ RECT 1848.730000 2432.100000 1849.730000 2432.580000 ;
+ RECT 1835.920000 2432.100000 1837.020000 2432.580000 ;
+ RECT 1835.920000 2426.660000 1837.020000 2427.140000 ;
+ RECT 1835.920000 2415.780000 1837.020000 2416.260000 ;
+ RECT 1835.920000 2421.220000 1837.020000 2421.700000 ;
+ RECT 1848.730000 2415.780000 1849.730000 2416.260000 ;
+ RECT 1848.730000 2421.220000 1849.730000 2421.700000 ;
+ RECT 1848.730000 2404.900000 1849.730000 2405.380000 ;
+ RECT 1848.730000 2399.460000 1849.730000 2399.940000 ;
+ RECT 1848.730000 2410.340000 1849.730000 2410.820000 ;
+ RECT 1835.920000 2410.340000 1837.020000 2410.820000 ;
+ RECT 1835.920000 2404.900000 1837.020000 2405.380000 ;
+ RECT 1835.920000 2399.460000 1837.020000 2399.940000 ;
+ RECT 1790.920000 2426.660000 1792.020000 2427.140000 ;
+ RECT 1790.920000 2432.100000 1792.020000 2432.580000 ;
+ RECT 1790.920000 2437.540000 1792.020000 2438.020000 ;
+ RECT 1790.920000 2442.980000 1792.020000 2443.460000 ;
+ RECT 1790.920000 2399.460000 1792.020000 2399.940000 ;
+ RECT 1790.920000 2404.900000 1792.020000 2405.380000 ;
+ RECT 1790.920000 2410.340000 1792.020000 2410.820000 ;
+ RECT 1790.920000 2415.780000 1792.020000 2416.260000 ;
+ RECT 1790.920000 2421.220000 1792.020000 2421.700000 ;
+ RECT 1835.920000 2388.580000 1837.020000 2389.060000 ;
+ RECT 1835.920000 2394.020000 1837.020000 2394.500000 ;
+ RECT 1848.730000 2388.580000 1849.730000 2389.060000 ;
+ RECT 1848.730000 2394.020000 1849.730000 2394.500000 ;
+ RECT 1835.920000 2377.700000 1837.020000 2378.180000 ;
+ RECT 1835.920000 2383.140000 1837.020000 2383.620000 ;
+ RECT 1848.730000 2377.700000 1849.730000 2378.180000 ;
+ RECT 1848.730000 2383.140000 1849.730000 2383.620000 ;
+ RECT 1848.730000 2366.820000 1849.730000 2367.300000 ;
+ RECT 1848.730000 2361.380000 1849.730000 2361.860000 ;
+ RECT 1848.730000 2372.260000 1849.730000 2372.740000 ;
+ RECT 1835.920000 2372.260000 1837.020000 2372.740000 ;
+ RECT 1835.920000 2366.820000 1837.020000 2367.300000 ;
+ RECT 1835.920000 2361.380000 1837.020000 2361.860000 ;
+ RECT 1835.920000 2355.940000 1837.020000 2356.420000 ;
+ RECT 1848.730000 2355.940000 1849.730000 2356.420000 ;
+ RECT 1790.920000 2377.700000 1792.020000 2378.180000 ;
+ RECT 1790.920000 2383.140000 1792.020000 2383.620000 ;
+ RECT 1790.920000 2388.580000 1792.020000 2389.060000 ;
+ RECT 1790.920000 2394.020000 1792.020000 2394.500000 ;
+ RECT 1790.920000 2355.940000 1792.020000 2356.420000 ;
+ RECT 1790.920000 2361.380000 1792.020000 2361.860000 ;
+ RECT 1790.920000 2366.820000 1792.020000 2367.300000 ;
+ RECT 1790.920000 2372.260000 1792.020000 2372.740000 ;
+ RECT 1745.920000 2426.660000 1747.020000 2427.140000 ;
+ RECT 1745.920000 2432.100000 1747.020000 2432.580000 ;
+ RECT 1745.920000 2437.540000 1747.020000 2438.020000 ;
+ RECT 1745.920000 2442.980000 1747.020000 2443.460000 ;
+ RECT 1700.920000 2426.660000 1702.020000 2427.140000 ;
+ RECT 1700.920000 2432.100000 1702.020000 2432.580000 ;
+ RECT 1700.920000 2437.540000 1702.020000 2438.020000 ;
+ RECT 1700.920000 2442.980000 1702.020000 2443.460000 ;
+ RECT 1745.920000 2399.460000 1747.020000 2399.940000 ;
+ RECT 1745.920000 2404.900000 1747.020000 2405.380000 ;
+ RECT 1745.920000 2410.340000 1747.020000 2410.820000 ;
+ RECT 1745.920000 2415.780000 1747.020000 2416.260000 ;
+ RECT 1745.920000 2421.220000 1747.020000 2421.700000 ;
+ RECT 1700.920000 2399.460000 1702.020000 2399.940000 ;
+ RECT 1700.920000 2404.900000 1702.020000 2405.380000 ;
+ RECT 1700.920000 2410.340000 1702.020000 2410.820000 ;
+ RECT 1700.920000 2415.780000 1702.020000 2416.260000 ;
+ RECT 1700.920000 2421.220000 1702.020000 2421.700000 ;
+ RECT 1652.090000 2442.980000 1653.090000 2443.460000 ;
+ RECT 1655.755000 2442.980000 1657.020000 2443.460000 ;
+ RECT 1652.090000 2437.540000 1653.090000 2438.020000 ;
+ RECT 1655.755000 2437.540000 1657.020000 2438.020000 ;
+ RECT 1652.090000 2432.100000 1653.090000 2432.580000 ;
+ RECT 1655.755000 2432.100000 1657.020000 2432.580000 ;
+ RECT 1652.090000 2426.660000 1653.090000 2427.140000 ;
+ RECT 1655.755000 2426.660000 1657.020000 2427.140000 ;
+ RECT 1652.090000 2421.220000 1653.090000 2421.700000 ;
+ RECT 1655.755000 2421.220000 1657.020000 2421.700000 ;
+ RECT 1652.090000 2415.780000 1653.090000 2416.260000 ;
+ RECT 1655.755000 2415.780000 1657.020000 2416.260000 ;
+ RECT 1652.090000 2404.900000 1653.090000 2405.380000 ;
+ RECT 1655.755000 2404.900000 1657.020000 2405.380000 ;
+ RECT 1652.090000 2410.340000 1653.090000 2410.820000 ;
+ RECT 1655.755000 2410.340000 1657.020000 2410.820000 ;
+ RECT 1652.090000 2399.460000 1653.090000 2399.940000 ;
+ RECT 1655.755000 2399.460000 1657.020000 2399.940000 ;
+ RECT 1745.920000 2377.700000 1747.020000 2378.180000 ;
+ RECT 1745.920000 2383.140000 1747.020000 2383.620000 ;
+ RECT 1745.920000 2388.580000 1747.020000 2389.060000 ;
+ RECT 1745.920000 2394.020000 1747.020000 2394.500000 ;
+ RECT 1700.920000 2377.700000 1702.020000 2378.180000 ;
+ RECT 1700.920000 2383.140000 1702.020000 2383.620000 ;
+ RECT 1700.920000 2388.580000 1702.020000 2389.060000 ;
+ RECT 1700.920000 2394.020000 1702.020000 2394.500000 ;
+ RECT 1745.920000 2355.940000 1747.020000 2356.420000 ;
+ RECT 1745.920000 2361.380000 1747.020000 2361.860000 ;
+ RECT 1745.920000 2366.820000 1747.020000 2367.300000 ;
+ RECT 1745.920000 2372.260000 1747.020000 2372.740000 ;
+ RECT 1700.920000 2355.940000 1702.020000 2356.420000 ;
+ RECT 1700.920000 2361.380000 1702.020000 2361.860000 ;
+ RECT 1700.920000 2366.820000 1702.020000 2367.300000 ;
+ RECT 1700.920000 2372.260000 1702.020000 2372.740000 ;
+ RECT 1652.090000 2394.020000 1653.090000 2394.500000 ;
+ RECT 1655.755000 2394.020000 1657.020000 2394.500000 ;
+ RECT 1652.090000 2388.580000 1653.090000 2389.060000 ;
+ RECT 1655.755000 2388.580000 1657.020000 2389.060000 ;
+ RECT 1652.090000 2383.140000 1653.090000 2383.620000 ;
+ RECT 1655.755000 2383.140000 1657.020000 2383.620000 ;
+ RECT 1652.090000 2377.700000 1653.090000 2378.180000 ;
+ RECT 1655.755000 2377.700000 1657.020000 2378.180000 ;
+ RECT 1652.090000 2372.260000 1653.090000 2372.740000 ;
+ RECT 1655.755000 2372.260000 1657.020000 2372.740000 ;
+ RECT 1652.090000 2361.380000 1653.090000 2361.860000 ;
+ RECT 1655.755000 2361.380000 1657.020000 2361.860000 ;
+ RECT 1652.090000 2366.820000 1653.090000 2367.300000 ;
+ RECT 1655.755000 2366.820000 1657.020000 2367.300000 ;
+ RECT 1652.090000 2355.940000 1653.090000 2356.420000 ;
+ RECT 1655.755000 2355.940000 1657.020000 2356.420000 ;
+ RECT 1790.920000 2448.420000 1792.020000 2448.900000 ;
+ RECT 1835.920000 2448.420000 1837.020000 2448.900000 ;
+ RECT 1848.730000 2448.420000 1849.730000 2448.900000 ;
+ RECT 1700.920000 2448.420000 1702.020000 2448.900000 ;
+ RECT 1745.920000 2448.420000 1747.020000 2448.900000 ;
+ RECT 1652.090000 2448.420000 1653.090000 2448.900000 ;
+ RECT 1655.755000 2448.420000 1657.020000 2448.900000 ;
+ RECT 1650.860000 2545.180000 1850.960000 2546.180000 ;
+ RECT 1650.860000 2349.610000 1850.960000 2350.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 2348.360000 1653.090000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 2547.620000 1653.090000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 2348.360000 1849.730000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 2547.620000 1849.730000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2349.610000 1651.860000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2349.610000 1850.960000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2545.180000 1651.860000 2546.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2545.180000 1850.960000 2546.180000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 2340.640000 1657.020000 2341.120000 ;
+ RECT 1655.755000 2329.760000 1657.020000 2330.240000 ;
+ RECT 1655.755000 2335.200000 1657.020000 2335.680000 ;
+ RECT 1655.755000 2324.320000 1657.020000 2324.800000 ;
+ RECT 1655.755000 2318.880000 1657.020000 2319.360000 ;
+ RECT 1655.755000 2313.440000 1657.020000 2313.920000 ;
+ RECT 1655.755000 2308.000000 1657.020000 2308.480000 ;
+ RECT 1655.755000 2302.560000 1657.020000 2303.040000 ;
+ RECT 1655.755000 2297.120000 1657.020000 2297.600000 ;
+ RECT 1655.755000 2286.240000 1657.020000 2286.720000 ;
+ RECT 1655.755000 2291.680000 1657.020000 2292.160000 ;
+ RECT 1655.755000 2280.800000 1657.020000 2281.280000 ;
+ RECT 1655.755000 2275.360000 1657.020000 2275.840000 ;
+ RECT 1655.755000 2269.920000 1657.020000 2270.400000 ;
+ RECT 1655.755000 2264.480000 1657.020000 2264.960000 ;
+ RECT 1655.755000 2259.040000 1657.020000 2259.520000 ;
+ RECT 1655.755000 2253.600000 1657.020000 2254.080000 ;
+ RECT 1655.755000 2242.720000 1657.020000 2243.200000 ;
+ RECT 1655.755000 2237.280000 1657.020000 2237.760000 ;
+ RECT 1655.755000 2231.840000 1657.020000 2232.320000 ;
+ RECT 1655.755000 2226.400000 1657.020000 2226.880000 ;
+ RECT 1655.755000 2220.960000 1657.020000 2221.440000 ;
+ RECT 1655.755000 2215.520000 1657.020000 2216.000000 ;
+ RECT 1655.755000 2204.640000 1657.020000 2205.120000 ;
+ RECT 1655.755000 2210.080000 1657.020000 2210.560000 ;
+ RECT 1655.755000 2199.200000 1657.020000 2199.680000 ;
+ RECT 1655.755000 2193.760000 1657.020000 2194.240000 ;
+ RECT 1655.755000 2188.320000 1657.020000 2188.800000 ;
+ RECT 1655.755000 2182.880000 1657.020000 2183.360000 ;
+ RECT 1655.755000 2177.440000 1657.020000 2177.920000 ;
+ RECT 1655.755000 2172.000000 1657.020000 2172.480000 ;
+ RECT 1655.755000 2161.120000 1657.020000 2161.600000 ;
+ RECT 1655.755000 2166.560000 1657.020000 2167.040000 ;
+ RECT 1655.755000 2155.680000 1657.020000 2156.160000 ;
+ RECT 1655.755000 2248.160000 1657.020000 2248.640000 ;
+ RECT 1835.920000 2149.350000 1837.020000 2345.920000 ;
+ RECT 1790.920000 2149.350000 1792.020000 2345.920000 ;
+ RECT 1848.730000 2148.100000 1849.730000 2348.360000 ;
+ RECT 1745.920000 2149.350000 1747.020000 2345.920000 ;
+ RECT 1700.920000 2149.350000 1702.020000 2345.920000 ;
+ RECT 1655.920000 2149.350000 1657.020000 2345.920000 ;
+ RECT 1652.090000 2148.100000 1653.090000 2348.360000 ;
+ LAYER met3 ;
+ RECT 1835.920000 2340.640000 1837.020000 2341.120000 ;
+ RECT 1848.730000 2340.640000 1849.730000 2341.120000 ;
+ RECT 1848.730000 2329.760000 1849.730000 2330.240000 ;
+ RECT 1848.730000 2324.320000 1849.730000 2324.800000 ;
+ RECT 1848.730000 2335.200000 1849.730000 2335.680000 ;
+ RECT 1835.920000 2335.200000 1837.020000 2335.680000 ;
+ RECT 1835.920000 2329.760000 1837.020000 2330.240000 ;
+ RECT 1835.920000 2324.320000 1837.020000 2324.800000 ;
+ RECT 1835.920000 2313.440000 1837.020000 2313.920000 ;
+ RECT 1835.920000 2318.880000 1837.020000 2319.360000 ;
+ RECT 1848.730000 2313.440000 1849.730000 2313.920000 ;
+ RECT 1848.730000 2318.880000 1849.730000 2319.360000 ;
+ RECT 1835.920000 2302.560000 1837.020000 2303.040000 ;
+ RECT 1835.920000 2308.000000 1837.020000 2308.480000 ;
+ RECT 1848.730000 2302.560000 1849.730000 2303.040000 ;
+ RECT 1848.730000 2308.000000 1849.730000 2308.480000 ;
+ RECT 1790.920000 2324.320000 1792.020000 2324.800000 ;
+ RECT 1790.920000 2329.760000 1792.020000 2330.240000 ;
+ RECT 1790.920000 2335.200000 1792.020000 2335.680000 ;
+ RECT 1790.920000 2340.640000 1792.020000 2341.120000 ;
+ RECT 1790.920000 2308.000000 1792.020000 2308.480000 ;
+ RECT 1790.920000 2302.560000 1792.020000 2303.040000 ;
+ RECT 1790.920000 2313.440000 1792.020000 2313.920000 ;
+ RECT 1790.920000 2318.880000 1792.020000 2319.360000 ;
+ RECT 1848.730000 2291.680000 1849.730000 2292.160000 ;
+ RECT 1848.730000 2286.240000 1849.730000 2286.720000 ;
+ RECT 1848.730000 2297.120000 1849.730000 2297.600000 ;
+ RECT 1835.920000 2297.120000 1837.020000 2297.600000 ;
+ RECT 1835.920000 2291.680000 1837.020000 2292.160000 ;
+ RECT 1835.920000 2286.240000 1837.020000 2286.720000 ;
+ RECT 1835.920000 2275.360000 1837.020000 2275.840000 ;
+ RECT 1835.920000 2280.800000 1837.020000 2281.280000 ;
+ RECT 1848.730000 2275.360000 1849.730000 2275.840000 ;
+ RECT 1848.730000 2280.800000 1849.730000 2281.280000 ;
+ RECT 1848.730000 2264.480000 1849.730000 2264.960000 ;
+ RECT 1848.730000 2269.920000 1849.730000 2270.400000 ;
+ RECT 1835.920000 2269.920000 1837.020000 2270.400000 ;
+ RECT 1835.920000 2264.480000 1837.020000 2264.960000 ;
+ RECT 1835.920000 2253.600000 1837.020000 2254.080000 ;
+ RECT 1835.920000 2259.040000 1837.020000 2259.520000 ;
+ RECT 1848.730000 2253.600000 1849.730000 2254.080000 ;
+ RECT 1848.730000 2259.040000 1849.730000 2259.520000 ;
+ RECT 1790.920000 2275.360000 1792.020000 2275.840000 ;
+ RECT 1790.920000 2280.800000 1792.020000 2281.280000 ;
+ RECT 1790.920000 2286.240000 1792.020000 2286.720000 ;
+ RECT 1790.920000 2291.680000 1792.020000 2292.160000 ;
+ RECT 1790.920000 2297.120000 1792.020000 2297.600000 ;
+ RECT 1790.920000 2253.600000 1792.020000 2254.080000 ;
+ RECT 1790.920000 2259.040000 1792.020000 2259.520000 ;
+ RECT 1790.920000 2264.480000 1792.020000 2264.960000 ;
+ RECT 1790.920000 2269.920000 1792.020000 2270.400000 ;
+ RECT 1745.920000 2329.760000 1747.020000 2330.240000 ;
+ RECT 1745.920000 2324.320000 1747.020000 2324.800000 ;
+ RECT 1745.920000 2335.200000 1747.020000 2335.680000 ;
+ RECT 1745.920000 2340.640000 1747.020000 2341.120000 ;
+ RECT 1700.920000 2324.320000 1702.020000 2324.800000 ;
+ RECT 1700.920000 2329.760000 1702.020000 2330.240000 ;
+ RECT 1700.920000 2335.200000 1702.020000 2335.680000 ;
+ RECT 1700.920000 2340.640000 1702.020000 2341.120000 ;
+ RECT 1745.920000 2302.560000 1747.020000 2303.040000 ;
+ RECT 1745.920000 2308.000000 1747.020000 2308.480000 ;
+ RECT 1745.920000 2313.440000 1747.020000 2313.920000 ;
+ RECT 1745.920000 2318.880000 1747.020000 2319.360000 ;
+ RECT 1700.920000 2302.560000 1702.020000 2303.040000 ;
+ RECT 1700.920000 2308.000000 1702.020000 2308.480000 ;
+ RECT 1700.920000 2313.440000 1702.020000 2313.920000 ;
+ RECT 1700.920000 2318.880000 1702.020000 2319.360000 ;
+ RECT 1652.090000 2340.640000 1653.090000 2341.120000 ;
+ RECT 1655.755000 2340.640000 1657.020000 2341.120000 ;
+ RECT 1652.090000 2329.760000 1653.090000 2330.240000 ;
+ RECT 1655.755000 2329.760000 1657.020000 2330.240000 ;
+ RECT 1652.090000 2335.200000 1653.090000 2335.680000 ;
+ RECT 1655.755000 2335.200000 1657.020000 2335.680000 ;
+ RECT 1652.090000 2324.320000 1653.090000 2324.800000 ;
+ RECT 1655.755000 2324.320000 1657.020000 2324.800000 ;
+ RECT 1652.090000 2318.880000 1653.090000 2319.360000 ;
+ RECT 1655.755000 2318.880000 1657.020000 2319.360000 ;
+ RECT 1652.090000 2313.440000 1653.090000 2313.920000 ;
+ RECT 1655.755000 2313.440000 1657.020000 2313.920000 ;
+ RECT 1652.090000 2308.000000 1653.090000 2308.480000 ;
+ RECT 1655.755000 2308.000000 1657.020000 2308.480000 ;
+ RECT 1652.090000 2302.560000 1653.090000 2303.040000 ;
+ RECT 1655.755000 2302.560000 1657.020000 2303.040000 ;
+ RECT 1745.920000 2275.360000 1747.020000 2275.840000 ;
+ RECT 1745.920000 2280.800000 1747.020000 2281.280000 ;
+ RECT 1745.920000 2286.240000 1747.020000 2286.720000 ;
+ RECT 1745.920000 2291.680000 1747.020000 2292.160000 ;
+ RECT 1745.920000 2297.120000 1747.020000 2297.600000 ;
+ RECT 1700.920000 2275.360000 1702.020000 2275.840000 ;
+ RECT 1700.920000 2280.800000 1702.020000 2281.280000 ;
+ RECT 1700.920000 2286.240000 1702.020000 2286.720000 ;
+ RECT 1700.920000 2291.680000 1702.020000 2292.160000 ;
+ RECT 1700.920000 2297.120000 1702.020000 2297.600000 ;
+ RECT 1745.920000 2253.600000 1747.020000 2254.080000 ;
+ RECT 1745.920000 2259.040000 1747.020000 2259.520000 ;
+ RECT 1745.920000 2264.480000 1747.020000 2264.960000 ;
+ RECT 1745.920000 2269.920000 1747.020000 2270.400000 ;
+ RECT 1700.920000 2253.600000 1702.020000 2254.080000 ;
+ RECT 1700.920000 2259.040000 1702.020000 2259.520000 ;
+ RECT 1700.920000 2264.480000 1702.020000 2264.960000 ;
+ RECT 1700.920000 2269.920000 1702.020000 2270.400000 ;
+ RECT 1652.090000 2297.120000 1653.090000 2297.600000 ;
+ RECT 1655.755000 2297.120000 1657.020000 2297.600000 ;
+ RECT 1652.090000 2286.240000 1653.090000 2286.720000 ;
+ RECT 1655.755000 2286.240000 1657.020000 2286.720000 ;
+ RECT 1652.090000 2291.680000 1653.090000 2292.160000 ;
+ RECT 1655.755000 2291.680000 1657.020000 2292.160000 ;
+ RECT 1652.090000 2280.800000 1653.090000 2281.280000 ;
+ RECT 1655.755000 2280.800000 1657.020000 2281.280000 ;
+ RECT 1652.090000 2275.360000 1653.090000 2275.840000 ;
+ RECT 1655.755000 2275.360000 1657.020000 2275.840000 ;
+ RECT 1652.090000 2269.920000 1653.090000 2270.400000 ;
+ RECT 1655.755000 2269.920000 1657.020000 2270.400000 ;
+ RECT 1652.090000 2264.480000 1653.090000 2264.960000 ;
+ RECT 1655.755000 2264.480000 1657.020000 2264.960000 ;
+ RECT 1652.090000 2259.040000 1653.090000 2259.520000 ;
+ RECT 1655.755000 2259.040000 1657.020000 2259.520000 ;
+ RECT 1652.090000 2253.600000 1653.090000 2254.080000 ;
+ RECT 1655.755000 2253.600000 1657.020000 2254.080000 ;
+ RECT 1835.920000 2237.280000 1837.020000 2237.760000 ;
+ RECT 1835.920000 2242.720000 1837.020000 2243.200000 ;
+ RECT 1848.730000 2237.280000 1849.730000 2237.760000 ;
+ RECT 1848.730000 2242.720000 1849.730000 2243.200000 ;
+ RECT 1848.730000 2226.400000 1849.730000 2226.880000 ;
+ RECT 1848.730000 2231.840000 1849.730000 2232.320000 ;
+ RECT 1835.920000 2231.840000 1837.020000 2232.320000 ;
+ RECT 1835.920000 2226.400000 1837.020000 2226.880000 ;
+ RECT 1835.920000 2215.520000 1837.020000 2216.000000 ;
+ RECT 1835.920000 2220.960000 1837.020000 2221.440000 ;
+ RECT 1848.730000 2215.520000 1849.730000 2216.000000 ;
+ RECT 1848.730000 2220.960000 1849.730000 2221.440000 ;
+ RECT 1848.730000 2204.640000 1849.730000 2205.120000 ;
+ RECT 1848.730000 2199.200000 1849.730000 2199.680000 ;
+ RECT 1848.730000 2210.080000 1849.730000 2210.560000 ;
+ RECT 1835.920000 2210.080000 1837.020000 2210.560000 ;
+ RECT 1835.920000 2204.640000 1837.020000 2205.120000 ;
+ RECT 1835.920000 2199.200000 1837.020000 2199.680000 ;
+ RECT 1790.920000 2226.400000 1792.020000 2226.880000 ;
+ RECT 1790.920000 2231.840000 1792.020000 2232.320000 ;
+ RECT 1790.920000 2237.280000 1792.020000 2237.760000 ;
+ RECT 1790.920000 2242.720000 1792.020000 2243.200000 ;
+ RECT 1790.920000 2199.200000 1792.020000 2199.680000 ;
+ RECT 1790.920000 2204.640000 1792.020000 2205.120000 ;
+ RECT 1790.920000 2210.080000 1792.020000 2210.560000 ;
+ RECT 1790.920000 2215.520000 1792.020000 2216.000000 ;
+ RECT 1790.920000 2220.960000 1792.020000 2221.440000 ;
+ RECT 1835.920000 2188.320000 1837.020000 2188.800000 ;
+ RECT 1835.920000 2193.760000 1837.020000 2194.240000 ;
+ RECT 1848.730000 2188.320000 1849.730000 2188.800000 ;
+ RECT 1848.730000 2193.760000 1849.730000 2194.240000 ;
+ RECT 1835.920000 2177.440000 1837.020000 2177.920000 ;
+ RECT 1835.920000 2182.880000 1837.020000 2183.360000 ;
+ RECT 1848.730000 2177.440000 1849.730000 2177.920000 ;
+ RECT 1848.730000 2182.880000 1849.730000 2183.360000 ;
+ RECT 1848.730000 2166.560000 1849.730000 2167.040000 ;
+ RECT 1848.730000 2161.120000 1849.730000 2161.600000 ;
+ RECT 1848.730000 2172.000000 1849.730000 2172.480000 ;
+ RECT 1835.920000 2172.000000 1837.020000 2172.480000 ;
+ RECT 1835.920000 2166.560000 1837.020000 2167.040000 ;
+ RECT 1835.920000 2161.120000 1837.020000 2161.600000 ;
+ RECT 1835.920000 2155.680000 1837.020000 2156.160000 ;
+ RECT 1848.730000 2155.680000 1849.730000 2156.160000 ;
+ RECT 1790.920000 2177.440000 1792.020000 2177.920000 ;
+ RECT 1790.920000 2182.880000 1792.020000 2183.360000 ;
+ RECT 1790.920000 2188.320000 1792.020000 2188.800000 ;
+ RECT 1790.920000 2193.760000 1792.020000 2194.240000 ;
+ RECT 1790.920000 2155.680000 1792.020000 2156.160000 ;
+ RECT 1790.920000 2161.120000 1792.020000 2161.600000 ;
+ RECT 1790.920000 2166.560000 1792.020000 2167.040000 ;
+ RECT 1790.920000 2172.000000 1792.020000 2172.480000 ;
+ RECT 1745.920000 2226.400000 1747.020000 2226.880000 ;
+ RECT 1745.920000 2231.840000 1747.020000 2232.320000 ;
+ RECT 1745.920000 2237.280000 1747.020000 2237.760000 ;
+ RECT 1745.920000 2242.720000 1747.020000 2243.200000 ;
+ RECT 1700.920000 2226.400000 1702.020000 2226.880000 ;
+ RECT 1700.920000 2231.840000 1702.020000 2232.320000 ;
+ RECT 1700.920000 2237.280000 1702.020000 2237.760000 ;
+ RECT 1700.920000 2242.720000 1702.020000 2243.200000 ;
+ RECT 1745.920000 2199.200000 1747.020000 2199.680000 ;
+ RECT 1745.920000 2204.640000 1747.020000 2205.120000 ;
+ RECT 1745.920000 2210.080000 1747.020000 2210.560000 ;
+ RECT 1745.920000 2215.520000 1747.020000 2216.000000 ;
+ RECT 1745.920000 2220.960000 1747.020000 2221.440000 ;
+ RECT 1700.920000 2199.200000 1702.020000 2199.680000 ;
+ RECT 1700.920000 2204.640000 1702.020000 2205.120000 ;
+ RECT 1700.920000 2210.080000 1702.020000 2210.560000 ;
+ RECT 1700.920000 2215.520000 1702.020000 2216.000000 ;
+ RECT 1700.920000 2220.960000 1702.020000 2221.440000 ;
+ RECT 1652.090000 2242.720000 1653.090000 2243.200000 ;
+ RECT 1655.755000 2242.720000 1657.020000 2243.200000 ;
+ RECT 1652.090000 2237.280000 1653.090000 2237.760000 ;
+ RECT 1655.755000 2237.280000 1657.020000 2237.760000 ;
+ RECT 1652.090000 2231.840000 1653.090000 2232.320000 ;
+ RECT 1655.755000 2231.840000 1657.020000 2232.320000 ;
+ RECT 1652.090000 2226.400000 1653.090000 2226.880000 ;
+ RECT 1655.755000 2226.400000 1657.020000 2226.880000 ;
+ RECT 1652.090000 2220.960000 1653.090000 2221.440000 ;
+ RECT 1655.755000 2220.960000 1657.020000 2221.440000 ;
+ RECT 1652.090000 2215.520000 1653.090000 2216.000000 ;
+ RECT 1655.755000 2215.520000 1657.020000 2216.000000 ;
+ RECT 1652.090000 2204.640000 1653.090000 2205.120000 ;
+ RECT 1655.755000 2204.640000 1657.020000 2205.120000 ;
+ RECT 1652.090000 2210.080000 1653.090000 2210.560000 ;
+ RECT 1655.755000 2210.080000 1657.020000 2210.560000 ;
+ RECT 1652.090000 2199.200000 1653.090000 2199.680000 ;
+ RECT 1655.755000 2199.200000 1657.020000 2199.680000 ;
+ RECT 1745.920000 2177.440000 1747.020000 2177.920000 ;
+ RECT 1745.920000 2182.880000 1747.020000 2183.360000 ;
+ RECT 1745.920000 2188.320000 1747.020000 2188.800000 ;
+ RECT 1745.920000 2193.760000 1747.020000 2194.240000 ;
+ RECT 1700.920000 2177.440000 1702.020000 2177.920000 ;
+ RECT 1700.920000 2182.880000 1702.020000 2183.360000 ;
+ RECT 1700.920000 2188.320000 1702.020000 2188.800000 ;
+ RECT 1700.920000 2193.760000 1702.020000 2194.240000 ;
+ RECT 1745.920000 2155.680000 1747.020000 2156.160000 ;
+ RECT 1745.920000 2161.120000 1747.020000 2161.600000 ;
+ RECT 1745.920000 2166.560000 1747.020000 2167.040000 ;
+ RECT 1745.920000 2172.000000 1747.020000 2172.480000 ;
+ RECT 1700.920000 2155.680000 1702.020000 2156.160000 ;
+ RECT 1700.920000 2161.120000 1702.020000 2161.600000 ;
+ RECT 1700.920000 2166.560000 1702.020000 2167.040000 ;
+ RECT 1700.920000 2172.000000 1702.020000 2172.480000 ;
+ RECT 1652.090000 2193.760000 1653.090000 2194.240000 ;
+ RECT 1655.755000 2193.760000 1657.020000 2194.240000 ;
+ RECT 1652.090000 2188.320000 1653.090000 2188.800000 ;
+ RECT 1655.755000 2188.320000 1657.020000 2188.800000 ;
+ RECT 1652.090000 2182.880000 1653.090000 2183.360000 ;
+ RECT 1655.755000 2182.880000 1657.020000 2183.360000 ;
+ RECT 1652.090000 2177.440000 1653.090000 2177.920000 ;
+ RECT 1655.755000 2177.440000 1657.020000 2177.920000 ;
+ RECT 1652.090000 2172.000000 1653.090000 2172.480000 ;
+ RECT 1655.755000 2172.000000 1657.020000 2172.480000 ;
+ RECT 1652.090000 2161.120000 1653.090000 2161.600000 ;
+ RECT 1655.755000 2161.120000 1657.020000 2161.600000 ;
+ RECT 1652.090000 2166.560000 1653.090000 2167.040000 ;
+ RECT 1655.755000 2166.560000 1657.020000 2167.040000 ;
+ RECT 1652.090000 2155.680000 1653.090000 2156.160000 ;
+ RECT 1655.755000 2155.680000 1657.020000 2156.160000 ;
+ RECT 1790.920000 2248.160000 1792.020000 2248.640000 ;
+ RECT 1835.920000 2248.160000 1837.020000 2248.640000 ;
+ RECT 1848.730000 2248.160000 1849.730000 2248.640000 ;
+ RECT 1700.920000 2248.160000 1702.020000 2248.640000 ;
+ RECT 1745.920000 2248.160000 1747.020000 2248.640000 ;
+ RECT 1652.090000 2248.160000 1653.090000 2248.640000 ;
+ RECT 1655.755000 2248.160000 1657.020000 2248.640000 ;
+ RECT 1650.860000 2344.920000 1850.960000 2345.920000 ;
+ RECT 1650.860000 2149.350000 1850.960000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 2148.100000 1653.090000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 2347.360000 1653.090000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 2148.100000 1849.730000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 2347.360000 1849.730000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2149.350000 1651.860000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2149.350000 1850.960000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2344.920000 1651.860000 2345.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2344.920000 1850.960000 2345.920000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 2140.380000 1657.020000 2140.860000 ;
+ RECT 1655.755000 2129.500000 1657.020000 2129.980000 ;
+ RECT 1655.755000 2134.940000 1657.020000 2135.420000 ;
+ RECT 1655.755000 2124.060000 1657.020000 2124.540000 ;
+ RECT 1655.755000 2118.620000 1657.020000 2119.100000 ;
+ RECT 1655.755000 2113.180000 1657.020000 2113.660000 ;
+ RECT 1655.755000 2107.740000 1657.020000 2108.220000 ;
+ RECT 1655.755000 2102.300000 1657.020000 2102.780000 ;
+ RECT 1655.755000 2096.860000 1657.020000 2097.340000 ;
+ RECT 1655.755000 2085.980000 1657.020000 2086.460000 ;
+ RECT 1655.755000 2091.420000 1657.020000 2091.900000 ;
+ RECT 1655.755000 2080.540000 1657.020000 2081.020000 ;
+ RECT 1655.755000 2075.100000 1657.020000 2075.580000 ;
+ RECT 1655.755000 2069.660000 1657.020000 2070.140000 ;
+ RECT 1655.755000 2064.220000 1657.020000 2064.700000 ;
+ RECT 1655.755000 2058.780000 1657.020000 2059.260000 ;
+ RECT 1655.755000 2053.340000 1657.020000 2053.820000 ;
+ RECT 1655.755000 2042.460000 1657.020000 2042.940000 ;
+ RECT 1655.755000 2037.020000 1657.020000 2037.500000 ;
+ RECT 1655.755000 2031.580000 1657.020000 2032.060000 ;
+ RECT 1655.755000 2026.140000 1657.020000 2026.620000 ;
+ RECT 1655.755000 2020.700000 1657.020000 2021.180000 ;
+ RECT 1655.755000 2015.260000 1657.020000 2015.740000 ;
+ RECT 1655.755000 2004.380000 1657.020000 2004.860000 ;
+ RECT 1655.755000 2009.820000 1657.020000 2010.300000 ;
+ RECT 1655.755000 1998.940000 1657.020000 1999.420000 ;
+ RECT 1655.755000 1993.500000 1657.020000 1993.980000 ;
+ RECT 1655.755000 1988.060000 1657.020000 1988.540000 ;
+ RECT 1655.755000 1982.620000 1657.020000 1983.100000 ;
+ RECT 1655.755000 1977.180000 1657.020000 1977.660000 ;
+ RECT 1655.755000 1971.740000 1657.020000 1972.220000 ;
+ RECT 1655.755000 1960.860000 1657.020000 1961.340000 ;
+ RECT 1655.755000 1966.300000 1657.020000 1966.780000 ;
+ RECT 1655.755000 1955.420000 1657.020000 1955.900000 ;
+ RECT 1655.755000 2047.900000 1657.020000 2048.380000 ;
+ RECT 1835.920000 1949.090000 1837.020000 2145.660000 ;
+ RECT 1790.920000 1949.090000 1792.020000 2145.660000 ;
+ RECT 1848.730000 1947.840000 1849.730000 2148.100000 ;
+ RECT 1745.920000 1949.090000 1747.020000 2145.660000 ;
+ RECT 1700.920000 1949.090000 1702.020000 2145.660000 ;
+ RECT 1655.920000 1949.090000 1657.020000 2145.660000 ;
+ RECT 1652.090000 1947.840000 1653.090000 2148.100000 ;
+ LAYER met3 ;
+ RECT 1835.920000 2140.380000 1837.020000 2140.860000 ;
+ RECT 1848.730000 2140.380000 1849.730000 2140.860000 ;
+ RECT 1848.730000 2129.500000 1849.730000 2129.980000 ;
+ RECT 1848.730000 2124.060000 1849.730000 2124.540000 ;
+ RECT 1848.730000 2134.940000 1849.730000 2135.420000 ;
+ RECT 1835.920000 2134.940000 1837.020000 2135.420000 ;
+ RECT 1835.920000 2129.500000 1837.020000 2129.980000 ;
+ RECT 1835.920000 2124.060000 1837.020000 2124.540000 ;
+ RECT 1835.920000 2113.180000 1837.020000 2113.660000 ;
+ RECT 1835.920000 2118.620000 1837.020000 2119.100000 ;
+ RECT 1848.730000 2113.180000 1849.730000 2113.660000 ;
+ RECT 1848.730000 2118.620000 1849.730000 2119.100000 ;
+ RECT 1835.920000 2102.300000 1837.020000 2102.780000 ;
+ RECT 1835.920000 2107.740000 1837.020000 2108.220000 ;
+ RECT 1848.730000 2102.300000 1849.730000 2102.780000 ;
+ RECT 1848.730000 2107.740000 1849.730000 2108.220000 ;
+ RECT 1790.920000 2124.060000 1792.020000 2124.540000 ;
+ RECT 1790.920000 2129.500000 1792.020000 2129.980000 ;
+ RECT 1790.920000 2134.940000 1792.020000 2135.420000 ;
+ RECT 1790.920000 2140.380000 1792.020000 2140.860000 ;
+ RECT 1790.920000 2107.740000 1792.020000 2108.220000 ;
+ RECT 1790.920000 2102.300000 1792.020000 2102.780000 ;
+ RECT 1790.920000 2113.180000 1792.020000 2113.660000 ;
+ RECT 1790.920000 2118.620000 1792.020000 2119.100000 ;
+ RECT 1848.730000 2091.420000 1849.730000 2091.900000 ;
+ RECT 1848.730000 2085.980000 1849.730000 2086.460000 ;
+ RECT 1848.730000 2096.860000 1849.730000 2097.340000 ;
+ RECT 1835.920000 2096.860000 1837.020000 2097.340000 ;
+ RECT 1835.920000 2091.420000 1837.020000 2091.900000 ;
+ RECT 1835.920000 2085.980000 1837.020000 2086.460000 ;
+ RECT 1835.920000 2075.100000 1837.020000 2075.580000 ;
+ RECT 1835.920000 2080.540000 1837.020000 2081.020000 ;
+ RECT 1848.730000 2075.100000 1849.730000 2075.580000 ;
+ RECT 1848.730000 2080.540000 1849.730000 2081.020000 ;
+ RECT 1848.730000 2064.220000 1849.730000 2064.700000 ;
+ RECT 1848.730000 2069.660000 1849.730000 2070.140000 ;
+ RECT 1835.920000 2069.660000 1837.020000 2070.140000 ;
+ RECT 1835.920000 2064.220000 1837.020000 2064.700000 ;
+ RECT 1835.920000 2053.340000 1837.020000 2053.820000 ;
+ RECT 1835.920000 2058.780000 1837.020000 2059.260000 ;
+ RECT 1848.730000 2053.340000 1849.730000 2053.820000 ;
+ RECT 1848.730000 2058.780000 1849.730000 2059.260000 ;
+ RECT 1790.920000 2075.100000 1792.020000 2075.580000 ;
+ RECT 1790.920000 2080.540000 1792.020000 2081.020000 ;
+ RECT 1790.920000 2085.980000 1792.020000 2086.460000 ;
+ RECT 1790.920000 2091.420000 1792.020000 2091.900000 ;
+ RECT 1790.920000 2096.860000 1792.020000 2097.340000 ;
+ RECT 1790.920000 2053.340000 1792.020000 2053.820000 ;
+ RECT 1790.920000 2058.780000 1792.020000 2059.260000 ;
+ RECT 1790.920000 2064.220000 1792.020000 2064.700000 ;
+ RECT 1790.920000 2069.660000 1792.020000 2070.140000 ;
+ RECT 1745.920000 2129.500000 1747.020000 2129.980000 ;
+ RECT 1745.920000 2124.060000 1747.020000 2124.540000 ;
+ RECT 1745.920000 2134.940000 1747.020000 2135.420000 ;
+ RECT 1745.920000 2140.380000 1747.020000 2140.860000 ;
+ RECT 1700.920000 2124.060000 1702.020000 2124.540000 ;
+ RECT 1700.920000 2129.500000 1702.020000 2129.980000 ;
+ RECT 1700.920000 2134.940000 1702.020000 2135.420000 ;
+ RECT 1700.920000 2140.380000 1702.020000 2140.860000 ;
+ RECT 1745.920000 2102.300000 1747.020000 2102.780000 ;
+ RECT 1745.920000 2107.740000 1747.020000 2108.220000 ;
+ RECT 1745.920000 2113.180000 1747.020000 2113.660000 ;
+ RECT 1745.920000 2118.620000 1747.020000 2119.100000 ;
+ RECT 1700.920000 2102.300000 1702.020000 2102.780000 ;
+ RECT 1700.920000 2107.740000 1702.020000 2108.220000 ;
+ RECT 1700.920000 2113.180000 1702.020000 2113.660000 ;
+ RECT 1700.920000 2118.620000 1702.020000 2119.100000 ;
+ RECT 1652.090000 2140.380000 1653.090000 2140.860000 ;
+ RECT 1655.755000 2140.380000 1657.020000 2140.860000 ;
+ RECT 1652.090000 2129.500000 1653.090000 2129.980000 ;
+ RECT 1655.755000 2129.500000 1657.020000 2129.980000 ;
+ RECT 1652.090000 2134.940000 1653.090000 2135.420000 ;
+ RECT 1655.755000 2134.940000 1657.020000 2135.420000 ;
+ RECT 1652.090000 2124.060000 1653.090000 2124.540000 ;
+ RECT 1655.755000 2124.060000 1657.020000 2124.540000 ;
+ RECT 1652.090000 2118.620000 1653.090000 2119.100000 ;
+ RECT 1655.755000 2118.620000 1657.020000 2119.100000 ;
+ RECT 1652.090000 2113.180000 1653.090000 2113.660000 ;
+ RECT 1655.755000 2113.180000 1657.020000 2113.660000 ;
+ RECT 1652.090000 2107.740000 1653.090000 2108.220000 ;
+ RECT 1655.755000 2107.740000 1657.020000 2108.220000 ;
+ RECT 1652.090000 2102.300000 1653.090000 2102.780000 ;
+ RECT 1655.755000 2102.300000 1657.020000 2102.780000 ;
+ RECT 1745.920000 2075.100000 1747.020000 2075.580000 ;
+ RECT 1745.920000 2080.540000 1747.020000 2081.020000 ;
+ RECT 1745.920000 2085.980000 1747.020000 2086.460000 ;
+ RECT 1745.920000 2091.420000 1747.020000 2091.900000 ;
+ RECT 1745.920000 2096.860000 1747.020000 2097.340000 ;
+ RECT 1700.920000 2075.100000 1702.020000 2075.580000 ;
+ RECT 1700.920000 2080.540000 1702.020000 2081.020000 ;
+ RECT 1700.920000 2085.980000 1702.020000 2086.460000 ;
+ RECT 1700.920000 2091.420000 1702.020000 2091.900000 ;
+ RECT 1700.920000 2096.860000 1702.020000 2097.340000 ;
+ RECT 1745.920000 2053.340000 1747.020000 2053.820000 ;
+ RECT 1745.920000 2058.780000 1747.020000 2059.260000 ;
+ RECT 1745.920000 2064.220000 1747.020000 2064.700000 ;
+ RECT 1745.920000 2069.660000 1747.020000 2070.140000 ;
+ RECT 1700.920000 2053.340000 1702.020000 2053.820000 ;
+ RECT 1700.920000 2058.780000 1702.020000 2059.260000 ;
+ RECT 1700.920000 2064.220000 1702.020000 2064.700000 ;
+ RECT 1700.920000 2069.660000 1702.020000 2070.140000 ;
+ RECT 1652.090000 2096.860000 1653.090000 2097.340000 ;
+ RECT 1655.755000 2096.860000 1657.020000 2097.340000 ;
+ RECT 1652.090000 2085.980000 1653.090000 2086.460000 ;
+ RECT 1655.755000 2085.980000 1657.020000 2086.460000 ;
+ RECT 1652.090000 2091.420000 1653.090000 2091.900000 ;
+ RECT 1655.755000 2091.420000 1657.020000 2091.900000 ;
+ RECT 1652.090000 2080.540000 1653.090000 2081.020000 ;
+ RECT 1655.755000 2080.540000 1657.020000 2081.020000 ;
+ RECT 1652.090000 2075.100000 1653.090000 2075.580000 ;
+ RECT 1655.755000 2075.100000 1657.020000 2075.580000 ;
+ RECT 1652.090000 2069.660000 1653.090000 2070.140000 ;
+ RECT 1655.755000 2069.660000 1657.020000 2070.140000 ;
+ RECT 1652.090000 2064.220000 1653.090000 2064.700000 ;
+ RECT 1655.755000 2064.220000 1657.020000 2064.700000 ;
+ RECT 1652.090000 2058.780000 1653.090000 2059.260000 ;
+ RECT 1655.755000 2058.780000 1657.020000 2059.260000 ;
+ RECT 1652.090000 2053.340000 1653.090000 2053.820000 ;
+ RECT 1655.755000 2053.340000 1657.020000 2053.820000 ;
+ RECT 1835.920000 2037.020000 1837.020000 2037.500000 ;
+ RECT 1835.920000 2042.460000 1837.020000 2042.940000 ;
+ RECT 1848.730000 2037.020000 1849.730000 2037.500000 ;
+ RECT 1848.730000 2042.460000 1849.730000 2042.940000 ;
+ RECT 1848.730000 2026.140000 1849.730000 2026.620000 ;
+ RECT 1848.730000 2031.580000 1849.730000 2032.060000 ;
+ RECT 1835.920000 2031.580000 1837.020000 2032.060000 ;
+ RECT 1835.920000 2026.140000 1837.020000 2026.620000 ;
+ RECT 1835.920000 2015.260000 1837.020000 2015.740000 ;
+ RECT 1835.920000 2020.700000 1837.020000 2021.180000 ;
+ RECT 1848.730000 2015.260000 1849.730000 2015.740000 ;
+ RECT 1848.730000 2020.700000 1849.730000 2021.180000 ;
+ RECT 1848.730000 2004.380000 1849.730000 2004.860000 ;
+ RECT 1848.730000 1998.940000 1849.730000 1999.420000 ;
+ RECT 1848.730000 2009.820000 1849.730000 2010.300000 ;
+ RECT 1835.920000 2009.820000 1837.020000 2010.300000 ;
+ RECT 1835.920000 2004.380000 1837.020000 2004.860000 ;
+ RECT 1835.920000 1998.940000 1837.020000 1999.420000 ;
+ RECT 1790.920000 2026.140000 1792.020000 2026.620000 ;
+ RECT 1790.920000 2031.580000 1792.020000 2032.060000 ;
+ RECT 1790.920000 2037.020000 1792.020000 2037.500000 ;
+ RECT 1790.920000 2042.460000 1792.020000 2042.940000 ;
+ RECT 1790.920000 1998.940000 1792.020000 1999.420000 ;
+ RECT 1790.920000 2004.380000 1792.020000 2004.860000 ;
+ RECT 1790.920000 2009.820000 1792.020000 2010.300000 ;
+ RECT 1790.920000 2015.260000 1792.020000 2015.740000 ;
+ RECT 1790.920000 2020.700000 1792.020000 2021.180000 ;
+ RECT 1835.920000 1988.060000 1837.020000 1988.540000 ;
+ RECT 1835.920000 1993.500000 1837.020000 1993.980000 ;
+ RECT 1848.730000 1988.060000 1849.730000 1988.540000 ;
+ RECT 1848.730000 1993.500000 1849.730000 1993.980000 ;
+ RECT 1835.920000 1977.180000 1837.020000 1977.660000 ;
+ RECT 1835.920000 1982.620000 1837.020000 1983.100000 ;
+ RECT 1848.730000 1977.180000 1849.730000 1977.660000 ;
+ RECT 1848.730000 1982.620000 1849.730000 1983.100000 ;
+ RECT 1848.730000 1966.300000 1849.730000 1966.780000 ;
+ RECT 1848.730000 1960.860000 1849.730000 1961.340000 ;
+ RECT 1848.730000 1971.740000 1849.730000 1972.220000 ;
+ RECT 1835.920000 1971.740000 1837.020000 1972.220000 ;
+ RECT 1835.920000 1966.300000 1837.020000 1966.780000 ;
+ RECT 1835.920000 1960.860000 1837.020000 1961.340000 ;
+ RECT 1835.920000 1955.420000 1837.020000 1955.900000 ;
+ RECT 1848.730000 1955.420000 1849.730000 1955.900000 ;
+ RECT 1790.920000 1977.180000 1792.020000 1977.660000 ;
+ RECT 1790.920000 1982.620000 1792.020000 1983.100000 ;
+ RECT 1790.920000 1988.060000 1792.020000 1988.540000 ;
+ RECT 1790.920000 1993.500000 1792.020000 1993.980000 ;
+ RECT 1790.920000 1955.420000 1792.020000 1955.900000 ;
+ RECT 1790.920000 1960.860000 1792.020000 1961.340000 ;
+ RECT 1790.920000 1966.300000 1792.020000 1966.780000 ;
+ RECT 1790.920000 1971.740000 1792.020000 1972.220000 ;
+ RECT 1745.920000 2026.140000 1747.020000 2026.620000 ;
+ RECT 1745.920000 2031.580000 1747.020000 2032.060000 ;
+ RECT 1745.920000 2037.020000 1747.020000 2037.500000 ;
+ RECT 1745.920000 2042.460000 1747.020000 2042.940000 ;
+ RECT 1700.920000 2026.140000 1702.020000 2026.620000 ;
+ RECT 1700.920000 2031.580000 1702.020000 2032.060000 ;
+ RECT 1700.920000 2037.020000 1702.020000 2037.500000 ;
+ RECT 1700.920000 2042.460000 1702.020000 2042.940000 ;
+ RECT 1745.920000 1998.940000 1747.020000 1999.420000 ;
+ RECT 1745.920000 2004.380000 1747.020000 2004.860000 ;
+ RECT 1745.920000 2009.820000 1747.020000 2010.300000 ;
+ RECT 1745.920000 2015.260000 1747.020000 2015.740000 ;
+ RECT 1745.920000 2020.700000 1747.020000 2021.180000 ;
+ RECT 1700.920000 1998.940000 1702.020000 1999.420000 ;
+ RECT 1700.920000 2004.380000 1702.020000 2004.860000 ;
+ RECT 1700.920000 2009.820000 1702.020000 2010.300000 ;
+ RECT 1700.920000 2015.260000 1702.020000 2015.740000 ;
+ RECT 1700.920000 2020.700000 1702.020000 2021.180000 ;
+ RECT 1652.090000 2042.460000 1653.090000 2042.940000 ;
+ RECT 1655.755000 2042.460000 1657.020000 2042.940000 ;
+ RECT 1652.090000 2037.020000 1653.090000 2037.500000 ;
+ RECT 1655.755000 2037.020000 1657.020000 2037.500000 ;
+ RECT 1652.090000 2031.580000 1653.090000 2032.060000 ;
+ RECT 1655.755000 2031.580000 1657.020000 2032.060000 ;
+ RECT 1652.090000 2026.140000 1653.090000 2026.620000 ;
+ RECT 1655.755000 2026.140000 1657.020000 2026.620000 ;
+ RECT 1652.090000 2020.700000 1653.090000 2021.180000 ;
+ RECT 1655.755000 2020.700000 1657.020000 2021.180000 ;
+ RECT 1652.090000 2015.260000 1653.090000 2015.740000 ;
+ RECT 1655.755000 2015.260000 1657.020000 2015.740000 ;
+ RECT 1652.090000 2004.380000 1653.090000 2004.860000 ;
+ RECT 1655.755000 2004.380000 1657.020000 2004.860000 ;
+ RECT 1652.090000 2009.820000 1653.090000 2010.300000 ;
+ RECT 1655.755000 2009.820000 1657.020000 2010.300000 ;
+ RECT 1652.090000 1998.940000 1653.090000 1999.420000 ;
+ RECT 1655.755000 1998.940000 1657.020000 1999.420000 ;
+ RECT 1745.920000 1977.180000 1747.020000 1977.660000 ;
+ RECT 1745.920000 1982.620000 1747.020000 1983.100000 ;
+ RECT 1745.920000 1988.060000 1747.020000 1988.540000 ;
+ RECT 1745.920000 1993.500000 1747.020000 1993.980000 ;
+ RECT 1700.920000 1977.180000 1702.020000 1977.660000 ;
+ RECT 1700.920000 1982.620000 1702.020000 1983.100000 ;
+ RECT 1700.920000 1988.060000 1702.020000 1988.540000 ;
+ RECT 1700.920000 1993.500000 1702.020000 1993.980000 ;
+ RECT 1745.920000 1955.420000 1747.020000 1955.900000 ;
+ RECT 1745.920000 1960.860000 1747.020000 1961.340000 ;
+ RECT 1745.920000 1966.300000 1747.020000 1966.780000 ;
+ RECT 1745.920000 1971.740000 1747.020000 1972.220000 ;
+ RECT 1700.920000 1955.420000 1702.020000 1955.900000 ;
+ RECT 1700.920000 1960.860000 1702.020000 1961.340000 ;
+ RECT 1700.920000 1966.300000 1702.020000 1966.780000 ;
+ RECT 1700.920000 1971.740000 1702.020000 1972.220000 ;
+ RECT 1652.090000 1993.500000 1653.090000 1993.980000 ;
+ RECT 1655.755000 1993.500000 1657.020000 1993.980000 ;
+ RECT 1652.090000 1988.060000 1653.090000 1988.540000 ;
+ RECT 1655.755000 1988.060000 1657.020000 1988.540000 ;
+ RECT 1652.090000 1982.620000 1653.090000 1983.100000 ;
+ RECT 1655.755000 1982.620000 1657.020000 1983.100000 ;
+ RECT 1652.090000 1977.180000 1653.090000 1977.660000 ;
+ RECT 1655.755000 1977.180000 1657.020000 1977.660000 ;
+ RECT 1652.090000 1971.740000 1653.090000 1972.220000 ;
+ RECT 1655.755000 1971.740000 1657.020000 1972.220000 ;
+ RECT 1652.090000 1960.860000 1653.090000 1961.340000 ;
+ RECT 1655.755000 1960.860000 1657.020000 1961.340000 ;
+ RECT 1652.090000 1966.300000 1653.090000 1966.780000 ;
+ RECT 1655.755000 1966.300000 1657.020000 1966.780000 ;
+ RECT 1652.090000 1955.420000 1653.090000 1955.900000 ;
+ RECT 1655.755000 1955.420000 1657.020000 1955.900000 ;
+ RECT 1790.920000 2047.900000 1792.020000 2048.380000 ;
+ RECT 1835.920000 2047.900000 1837.020000 2048.380000 ;
+ RECT 1848.730000 2047.900000 1849.730000 2048.380000 ;
+ RECT 1700.920000 2047.900000 1702.020000 2048.380000 ;
+ RECT 1745.920000 2047.900000 1747.020000 2048.380000 ;
+ RECT 1652.090000 2047.900000 1653.090000 2048.380000 ;
+ RECT 1655.755000 2047.900000 1657.020000 2048.380000 ;
+ RECT 1650.860000 2144.660000 1850.960000 2145.660000 ;
+ RECT 1650.860000 1949.090000 1850.960000 1950.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 1947.840000 1653.090000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 2147.100000 1653.090000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 1947.840000 1849.730000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 2147.100000 1849.730000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1949.090000 1651.860000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1949.090000 1850.960000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2144.660000 1651.860000 2145.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2144.660000 1850.960000 2145.660000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 1940.120000 1657.020000 1940.600000 ;
+ RECT 1655.755000 1929.240000 1657.020000 1929.720000 ;
+ RECT 1655.755000 1934.680000 1657.020000 1935.160000 ;
+ RECT 1655.755000 1923.800000 1657.020000 1924.280000 ;
+ RECT 1655.755000 1918.360000 1657.020000 1918.840000 ;
+ RECT 1655.755000 1912.920000 1657.020000 1913.400000 ;
+ RECT 1655.755000 1907.480000 1657.020000 1907.960000 ;
+ RECT 1655.755000 1902.040000 1657.020000 1902.520000 ;
+ RECT 1655.755000 1896.600000 1657.020000 1897.080000 ;
+ RECT 1655.755000 1885.720000 1657.020000 1886.200000 ;
+ RECT 1655.755000 1891.160000 1657.020000 1891.640000 ;
+ RECT 1655.755000 1880.280000 1657.020000 1880.760000 ;
+ RECT 1655.755000 1874.840000 1657.020000 1875.320000 ;
+ RECT 1655.755000 1869.400000 1657.020000 1869.880000 ;
+ RECT 1655.755000 1863.960000 1657.020000 1864.440000 ;
+ RECT 1655.755000 1858.520000 1657.020000 1859.000000 ;
+ RECT 1655.755000 1853.080000 1657.020000 1853.560000 ;
+ RECT 1655.755000 1842.200000 1657.020000 1842.680000 ;
+ RECT 1655.755000 1836.760000 1657.020000 1837.240000 ;
+ RECT 1655.755000 1831.320000 1657.020000 1831.800000 ;
+ RECT 1655.755000 1825.880000 1657.020000 1826.360000 ;
+ RECT 1655.755000 1820.440000 1657.020000 1820.920000 ;
+ RECT 1655.755000 1815.000000 1657.020000 1815.480000 ;
+ RECT 1655.755000 1804.120000 1657.020000 1804.600000 ;
+ RECT 1655.755000 1809.560000 1657.020000 1810.040000 ;
+ RECT 1655.755000 1798.680000 1657.020000 1799.160000 ;
+ RECT 1655.755000 1793.240000 1657.020000 1793.720000 ;
+ RECT 1655.755000 1787.800000 1657.020000 1788.280000 ;
+ RECT 1655.755000 1782.360000 1657.020000 1782.840000 ;
+ RECT 1655.755000 1776.920000 1657.020000 1777.400000 ;
+ RECT 1655.755000 1771.480000 1657.020000 1771.960000 ;
+ RECT 1655.755000 1760.600000 1657.020000 1761.080000 ;
+ RECT 1655.755000 1766.040000 1657.020000 1766.520000 ;
+ RECT 1655.755000 1755.160000 1657.020000 1755.640000 ;
+ RECT 1655.755000 1847.640000 1657.020000 1848.120000 ;
+ RECT 1835.920000 1748.830000 1837.020000 1945.400000 ;
+ RECT 1790.920000 1748.830000 1792.020000 1945.400000 ;
+ RECT 1848.730000 1747.580000 1849.730000 1947.840000 ;
+ RECT 1745.920000 1748.830000 1747.020000 1945.400000 ;
+ RECT 1700.920000 1748.830000 1702.020000 1945.400000 ;
+ RECT 1655.920000 1748.830000 1657.020000 1945.400000 ;
+ RECT 1652.090000 1747.580000 1653.090000 1947.840000 ;
+ LAYER met3 ;
+ RECT 1835.920000 1940.120000 1837.020000 1940.600000 ;
+ RECT 1848.730000 1940.120000 1849.730000 1940.600000 ;
+ RECT 1848.730000 1929.240000 1849.730000 1929.720000 ;
+ RECT 1848.730000 1923.800000 1849.730000 1924.280000 ;
+ RECT 1848.730000 1934.680000 1849.730000 1935.160000 ;
+ RECT 1835.920000 1934.680000 1837.020000 1935.160000 ;
+ RECT 1835.920000 1929.240000 1837.020000 1929.720000 ;
+ RECT 1835.920000 1923.800000 1837.020000 1924.280000 ;
+ RECT 1835.920000 1912.920000 1837.020000 1913.400000 ;
+ RECT 1835.920000 1918.360000 1837.020000 1918.840000 ;
+ RECT 1848.730000 1912.920000 1849.730000 1913.400000 ;
+ RECT 1848.730000 1918.360000 1849.730000 1918.840000 ;
+ RECT 1835.920000 1902.040000 1837.020000 1902.520000 ;
+ RECT 1835.920000 1907.480000 1837.020000 1907.960000 ;
+ RECT 1848.730000 1902.040000 1849.730000 1902.520000 ;
+ RECT 1848.730000 1907.480000 1849.730000 1907.960000 ;
+ RECT 1790.920000 1923.800000 1792.020000 1924.280000 ;
+ RECT 1790.920000 1929.240000 1792.020000 1929.720000 ;
+ RECT 1790.920000 1934.680000 1792.020000 1935.160000 ;
+ RECT 1790.920000 1940.120000 1792.020000 1940.600000 ;
+ RECT 1790.920000 1907.480000 1792.020000 1907.960000 ;
+ RECT 1790.920000 1902.040000 1792.020000 1902.520000 ;
+ RECT 1790.920000 1912.920000 1792.020000 1913.400000 ;
+ RECT 1790.920000 1918.360000 1792.020000 1918.840000 ;
+ RECT 1848.730000 1891.160000 1849.730000 1891.640000 ;
+ RECT 1848.730000 1885.720000 1849.730000 1886.200000 ;
+ RECT 1848.730000 1896.600000 1849.730000 1897.080000 ;
+ RECT 1835.920000 1896.600000 1837.020000 1897.080000 ;
+ RECT 1835.920000 1891.160000 1837.020000 1891.640000 ;
+ RECT 1835.920000 1885.720000 1837.020000 1886.200000 ;
+ RECT 1835.920000 1874.840000 1837.020000 1875.320000 ;
+ RECT 1835.920000 1880.280000 1837.020000 1880.760000 ;
+ RECT 1848.730000 1874.840000 1849.730000 1875.320000 ;
+ RECT 1848.730000 1880.280000 1849.730000 1880.760000 ;
+ RECT 1848.730000 1863.960000 1849.730000 1864.440000 ;
+ RECT 1848.730000 1869.400000 1849.730000 1869.880000 ;
+ RECT 1835.920000 1869.400000 1837.020000 1869.880000 ;
+ RECT 1835.920000 1863.960000 1837.020000 1864.440000 ;
+ RECT 1835.920000 1853.080000 1837.020000 1853.560000 ;
+ RECT 1835.920000 1858.520000 1837.020000 1859.000000 ;
+ RECT 1848.730000 1853.080000 1849.730000 1853.560000 ;
+ RECT 1848.730000 1858.520000 1849.730000 1859.000000 ;
+ RECT 1790.920000 1874.840000 1792.020000 1875.320000 ;
+ RECT 1790.920000 1880.280000 1792.020000 1880.760000 ;
+ RECT 1790.920000 1885.720000 1792.020000 1886.200000 ;
+ RECT 1790.920000 1891.160000 1792.020000 1891.640000 ;
+ RECT 1790.920000 1896.600000 1792.020000 1897.080000 ;
+ RECT 1790.920000 1853.080000 1792.020000 1853.560000 ;
+ RECT 1790.920000 1858.520000 1792.020000 1859.000000 ;
+ RECT 1790.920000 1863.960000 1792.020000 1864.440000 ;
+ RECT 1790.920000 1869.400000 1792.020000 1869.880000 ;
+ RECT 1745.920000 1929.240000 1747.020000 1929.720000 ;
+ RECT 1745.920000 1923.800000 1747.020000 1924.280000 ;
+ RECT 1745.920000 1934.680000 1747.020000 1935.160000 ;
+ RECT 1745.920000 1940.120000 1747.020000 1940.600000 ;
+ RECT 1700.920000 1923.800000 1702.020000 1924.280000 ;
+ RECT 1700.920000 1929.240000 1702.020000 1929.720000 ;
+ RECT 1700.920000 1934.680000 1702.020000 1935.160000 ;
+ RECT 1700.920000 1940.120000 1702.020000 1940.600000 ;
+ RECT 1745.920000 1902.040000 1747.020000 1902.520000 ;
+ RECT 1745.920000 1907.480000 1747.020000 1907.960000 ;
+ RECT 1745.920000 1912.920000 1747.020000 1913.400000 ;
+ RECT 1745.920000 1918.360000 1747.020000 1918.840000 ;
+ RECT 1700.920000 1902.040000 1702.020000 1902.520000 ;
+ RECT 1700.920000 1907.480000 1702.020000 1907.960000 ;
+ RECT 1700.920000 1912.920000 1702.020000 1913.400000 ;
+ RECT 1700.920000 1918.360000 1702.020000 1918.840000 ;
+ RECT 1652.090000 1940.120000 1653.090000 1940.600000 ;
+ RECT 1655.755000 1940.120000 1657.020000 1940.600000 ;
+ RECT 1652.090000 1929.240000 1653.090000 1929.720000 ;
+ RECT 1655.755000 1929.240000 1657.020000 1929.720000 ;
+ RECT 1652.090000 1934.680000 1653.090000 1935.160000 ;
+ RECT 1655.755000 1934.680000 1657.020000 1935.160000 ;
+ RECT 1652.090000 1923.800000 1653.090000 1924.280000 ;
+ RECT 1655.755000 1923.800000 1657.020000 1924.280000 ;
+ RECT 1652.090000 1918.360000 1653.090000 1918.840000 ;
+ RECT 1655.755000 1918.360000 1657.020000 1918.840000 ;
+ RECT 1652.090000 1912.920000 1653.090000 1913.400000 ;
+ RECT 1655.755000 1912.920000 1657.020000 1913.400000 ;
+ RECT 1652.090000 1907.480000 1653.090000 1907.960000 ;
+ RECT 1655.755000 1907.480000 1657.020000 1907.960000 ;
+ RECT 1652.090000 1902.040000 1653.090000 1902.520000 ;
+ RECT 1655.755000 1902.040000 1657.020000 1902.520000 ;
+ RECT 1745.920000 1874.840000 1747.020000 1875.320000 ;
+ RECT 1745.920000 1880.280000 1747.020000 1880.760000 ;
+ RECT 1745.920000 1885.720000 1747.020000 1886.200000 ;
+ RECT 1745.920000 1891.160000 1747.020000 1891.640000 ;
+ RECT 1745.920000 1896.600000 1747.020000 1897.080000 ;
+ RECT 1700.920000 1874.840000 1702.020000 1875.320000 ;
+ RECT 1700.920000 1880.280000 1702.020000 1880.760000 ;
+ RECT 1700.920000 1885.720000 1702.020000 1886.200000 ;
+ RECT 1700.920000 1891.160000 1702.020000 1891.640000 ;
+ RECT 1700.920000 1896.600000 1702.020000 1897.080000 ;
+ RECT 1745.920000 1853.080000 1747.020000 1853.560000 ;
+ RECT 1745.920000 1858.520000 1747.020000 1859.000000 ;
+ RECT 1745.920000 1863.960000 1747.020000 1864.440000 ;
+ RECT 1745.920000 1869.400000 1747.020000 1869.880000 ;
+ RECT 1700.920000 1853.080000 1702.020000 1853.560000 ;
+ RECT 1700.920000 1858.520000 1702.020000 1859.000000 ;
+ RECT 1700.920000 1863.960000 1702.020000 1864.440000 ;
+ RECT 1700.920000 1869.400000 1702.020000 1869.880000 ;
+ RECT 1652.090000 1896.600000 1653.090000 1897.080000 ;
+ RECT 1655.755000 1896.600000 1657.020000 1897.080000 ;
+ RECT 1652.090000 1885.720000 1653.090000 1886.200000 ;
+ RECT 1655.755000 1885.720000 1657.020000 1886.200000 ;
+ RECT 1652.090000 1891.160000 1653.090000 1891.640000 ;
+ RECT 1655.755000 1891.160000 1657.020000 1891.640000 ;
+ RECT 1652.090000 1880.280000 1653.090000 1880.760000 ;
+ RECT 1655.755000 1880.280000 1657.020000 1880.760000 ;
+ RECT 1652.090000 1874.840000 1653.090000 1875.320000 ;
+ RECT 1655.755000 1874.840000 1657.020000 1875.320000 ;
+ RECT 1652.090000 1869.400000 1653.090000 1869.880000 ;
+ RECT 1655.755000 1869.400000 1657.020000 1869.880000 ;
+ RECT 1652.090000 1863.960000 1653.090000 1864.440000 ;
+ RECT 1655.755000 1863.960000 1657.020000 1864.440000 ;
+ RECT 1652.090000 1858.520000 1653.090000 1859.000000 ;
+ RECT 1655.755000 1858.520000 1657.020000 1859.000000 ;
+ RECT 1652.090000 1853.080000 1653.090000 1853.560000 ;
+ RECT 1655.755000 1853.080000 1657.020000 1853.560000 ;
+ RECT 1835.920000 1836.760000 1837.020000 1837.240000 ;
+ RECT 1835.920000 1842.200000 1837.020000 1842.680000 ;
+ RECT 1848.730000 1836.760000 1849.730000 1837.240000 ;
+ RECT 1848.730000 1842.200000 1849.730000 1842.680000 ;
+ RECT 1848.730000 1825.880000 1849.730000 1826.360000 ;
+ RECT 1848.730000 1831.320000 1849.730000 1831.800000 ;
+ RECT 1835.920000 1831.320000 1837.020000 1831.800000 ;
+ RECT 1835.920000 1825.880000 1837.020000 1826.360000 ;
+ RECT 1835.920000 1815.000000 1837.020000 1815.480000 ;
+ RECT 1835.920000 1820.440000 1837.020000 1820.920000 ;
+ RECT 1848.730000 1815.000000 1849.730000 1815.480000 ;
+ RECT 1848.730000 1820.440000 1849.730000 1820.920000 ;
+ RECT 1848.730000 1804.120000 1849.730000 1804.600000 ;
+ RECT 1848.730000 1798.680000 1849.730000 1799.160000 ;
+ RECT 1848.730000 1809.560000 1849.730000 1810.040000 ;
+ RECT 1835.920000 1809.560000 1837.020000 1810.040000 ;
+ RECT 1835.920000 1804.120000 1837.020000 1804.600000 ;
+ RECT 1835.920000 1798.680000 1837.020000 1799.160000 ;
+ RECT 1790.920000 1825.880000 1792.020000 1826.360000 ;
+ RECT 1790.920000 1831.320000 1792.020000 1831.800000 ;
+ RECT 1790.920000 1836.760000 1792.020000 1837.240000 ;
+ RECT 1790.920000 1842.200000 1792.020000 1842.680000 ;
+ RECT 1790.920000 1798.680000 1792.020000 1799.160000 ;
+ RECT 1790.920000 1804.120000 1792.020000 1804.600000 ;
+ RECT 1790.920000 1809.560000 1792.020000 1810.040000 ;
+ RECT 1790.920000 1815.000000 1792.020000 1815.480000 ;
+ RECT 1790.920000 1820.440000 1792.020000 1820.920000 ;
+ RECT 1835.920000 1787.800000 1837.020000 1788.280000 ;
+ RECT 1835.920000 1793.240000 1837.020000 1793.720000 ;
+ RECT 1848.730000 1787.800000 1849.730000 1788.280000 ;
+ RECT 1848.730000 1793.240000 1849.730000 1793.720000 ;
+ RECT 1835.920000 1776.920000 1837.020000 1777.400000 ;
+ RECT 1835.920000 1782.360000 1837.020000 1782.840000 ;
+ RECT 1848.730000 1776.920000 1849.730000 1777.400000 ;
+ RECT 1848.730000 1782.360000 1849.730000 1782.840000 ;
+ RECT 1848.730000 1766.040000 1849.730000 1766.520000 ;
+ RECT 1848.730000 1760.600000 1849.730000 1761.080000 ;
+ RECT 1848.730000 1771.480000 1849.730000 1771.960000 ;
+ RECT 1835.920000 1771.480000 1837.020000 1771.960000 ;
+ RECT 1835.920000 1766.040000 1837.020000 1766.520000 ;
+ RECT 1835.920000 1760.600000 1837.020000 1761.080000 ;
+ RECT 1835.920000 1755.160000 1837.020000 1755.640000 ;
+ RECT 1848.730000 1755.160000 1849.730000 1755.640000 ;
+ RECT 1790.920000 1776.920000 1792.020000 1777.400000 ;
+ RECT 1790.920000 1782.360000 1792.020000 1782.840000 ;
+ RECT 1790.920000 1787.800000 1792.020000 1788.280000 ;
+ RECT 1790.920000 1793.240000 1792.020000 1793.720000 ;
+ RECT 1790.920000 1755.160000 1792.020000 1755.640000 ;
+ RECT 1790.920000 1760.600000 1792.020000 1761.080000 ;
+ RECT 1790.920000 1766.040000 1792.020000 1766.520000 ;
+ RECT 1790.920000 1771.480000 1792.020000 1771.960000 ;
+ RECT 1745.920000 1825.880000 1747.020000 1826.360000 ;
+ RECT 1745.920000 1831.320000 1747.020000 1831.800000 ;
+ RECT 1745.920000 1836.760000 1747.020000 1837.240000 ;
+ RECT 1745.920000 1842.200000 1747.020000 1842.680000 ;
+ RECT 1700.920000 1825.880000 1702.020000 1826.360000 ;
+ RECT 1700.920000 1831.320000 1702.020000 1831.800000 ;
+ RECT 1700.920000 1836.760000 1702.020000 1837.240000 ;
+ RECT 1700.920000 1842.200000 1702.020000 1842.680000 ;
+ RECT 1745.920000 1798.680000 1747.020000 1799.160000 ;
+ RECT 1745.920000 1804.120000 1747.020000 1804.600000 ;
+ RECT 1745.920000 1809.560000 1747.020000 1810.040000 ;
+ RECT 1745.920000 1815.000000 1747.020000 1815.480000 ;
+ RECT 1745.920000 1820.440000 1747.020000 1820.920000 ;
+ RECT 1700.920000 1798.680000 1702.020000 1799.160000 ;
+ RECT 1700.920000 1804.120000 1702.020000 1804.600000 ;
+ RECT 1700.920000 1809.560000 1702.020000 1810.040000 ;
+ RECT 1700.920000 1815.000000 1702.020000 1815.480000 ;
+ RECT 1700.920000 1820.440000 1702.020000 1820.920000 ;
+ RECT 1652.090000 1842.200000 1653.090000 1842.680000 ;
+ RECT 1655.755000 1842.200000 1657.020000 1842.680000 ;
+ RECT 1652.090000 1836.760000 1653.090000 1837.240000 ;
+ RECT 1655.755000 1836.760000 1657.020000 1837.240000 ;
+ RECT 1652.090000 1831.320000 1653.090000 1831.800000 ;
+ RECT 1655.755000 1831.320000 1657.020000 1831.800000 ;
+ RECT 1652.090000 1825.880000 1653.090000 1826.360000 ;
+ RECT 1655.755000 1825.880000 1657.020000 1826.360000 ;
+ RECT 1652.090000 1820.440000 1653.090000 1820.920000 ;
+ RECT 1655.755000 1820.440000 1657.020000 1820.920000 ;
+ RECT 1652.090000 1815.000000 1653.090000 1815.480000 ;
+ RECT 1655.755000 1815.000000 1657.020000 1815.480000 ;
+ RECT 1652.090000 1804.120000 1653.090000 1804.600000 ;
+ RECT 1655.755000 1804.120000 1657.020000 1804.600000 ;
+ RECT 1652.090000 1809.560000 1653.090000 1810.040000 ;
+ RECT 1655.755000 1809.560000 1657.020000 1810.040000 ;
+ RECT 1652.090000 1798.680000 1653.090000 1799.160000 ;
+ RECT 1655.755000 1798.680000 1657.020000 1799.160000 ;
+ RECT 1745.920000 1776.920000 1747.020000 1777.400000 ;
+ RECT 1745.920000 1782.360000 1747.020000 1782.840000 ;
+ RECT 1745.920000 1787.800000 1747.020000 1788.280000 ;
+ RECT 1745.920000 1793.240000 1747.020000 1793.720000 ;
+ RECT 1700.920000 1776.920000 1702.020000 1777.400000 ;
+ RECT 1700.920000 1782.360000 1702.020000 1782.840000 ;
+ RECT 1700.920000 1787.800000 1702.020000 1788.280000 ;
+ RECT 1700.920000 1793.240000 1702.020000 1793.720000 ;
+ RECT 1745.920000 1755.160000 1747.020000 1755.640000 ;
+ RECT 1745.920000 1760.600000 1747.020000 1761.080000 ;
+ RECT 1745.920000 1766.040000 1747.020000 1766.520000 ;
+ RECT 1745.920000 1771.480000 1747.020000 1771.960000 ;
+ RECT 1700.920000 1755.160000 1702.020000 1755.640000 ;
+ RECT 1700.920000 1760.600000 1702.020000 1761.080000 ;
+ RECT 1700.920000 1766.040000 1702.020000 1766.520000 ;
+ RECT 1700.920000 1771.480000 1702.020000 1771.960000 ;
+ RECT 1652.090000 1793.240000 1653.090000 1793.720000 ;
+ RECT 1655.755000 1793.240000 1657.020000 1793.720000 ;
+ RECT 1652.090000 1787.800000 1653.090000 1788.280000 ;
+ RECT 1655.755000 1787.800000 1657.020000 1788.280000 ;
+ RECT 1652.090000 1782.360000 1653.090000 1782.840000 ;
+ RECT 1655.755000 1782.360000 1657.020000 1782.840000 ;
+ RECT 1652.090000 1776.920000 1653.090000 1777.400000 ;
+ RECT 1655.755000 1776.920000 1657.020000 1777.400000 ;
+ RECT 1652.090000 1771.480000 1653.090000 1771.960000 ;
+ RECT 1655.755000 1771.480000 1657.020000 1771.960000 ;
+ RECT 1652.090000 1760.600000 1653.090000 1761.080000 ;
+ RECT 1655.755000 1760.600000 1657.020000 1761.080000 ;
+ RECT 1652.090000 1766.040000 1653.090000 1766.520000 ;
+ RECT 1655.755000 1766.040000 1657.020000 1766.520000 ;
+ RECT 1652.090000 1755.160000 1653.090000 1755.640000 ;
+ RECT 1655.755000 1755.160000 1657.020000 1755.640000 ;
+ RECT 1790.920000 1847.640000 1792.020000 1848.120000 ;
+ RECT 1835.920000 1847.640000 1837.020000 1848.120000 ;
+ RECT 1848.730000 1847.640000 1849.730000 1848.120000 ;
+ RECT 1700.920000 1847.640000 1702.020000 1848.120000 ;
+ RECT 1745.920000 1847.640000 1747.020000 1848.120000 ;
+ RECT 1652.090000 1847.640000 1653.090000 1848.120000 ;
+ RECT 1655.755000 1847.640000 1657.020000 1848.120000 ;
+ RECT 1650.860000 1944.400000 1850.960000 1945.400000 ;
+ RECT 1650.860000 1748.830000 1850.960000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 1747.580000 1653.090000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 1946.840000 1653.090000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 1747.580000 1849.730000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 1946.840000 1849.730000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1748.830000 1651.860000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1748.830000 1850.960000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1944.400000 1651.860000 1945.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1944.400000 1850.960000 1945.400000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1655.755000 1739.860000 1657.020000 1740.340000 ;
+ RECT 1655.755000 1728.980000 1657.020000 1729.460000 ;
+ RECT 1655.755000 1734.420000 1657.020000 1734.900000 ;
+ RECT 1655.755000 1723.540000 1657.020000 1724.020000 ;
+ RECT 1655.755000 1718.100000 1657.020000 1718.580000 ;
+ RECT 1655.755000 1712.660000 1657.020000 1713.140000 ;
+ RECT 1655.755000 1707.220000 1657.020000 1707.700000 ;
+ RECT 1655.755000 1701.780000 1657.020000 1702.260000 ;
+ RECT 1655.755000 1696.340000 1657.020000 1696.820000 ;
+ RECT 1655.755000 1685.460000 1657.020000 1685.940000 ;
+ RECT 1655.755000 1690.900000 1657.020000 1691.380000 ;
+ RECT 1655.755000 1680.020000 1657.020000 1680.500000 ;
+ RECT 1655.755000 1674.580000 1657.020000 1675.060000 ;
+ RECT 1655.755000 1669.140000 1657.020000 1669.620000 ;
+ RECT 1655.755000 1663.700000 1657.020000 1664.180000 ;
+ RECT 1655.755000 1658.260000 1657.020000 1658.740000 ;
+ RECT 1655.755000 1652.820000 1657.020000 1653.300000 ;
+ RECT 1655.755000 1641.940000 1657.020000 1642.420000 ;
+ RECT 1655.755000 1636.500000 1657.020000 1636.980000 ;
+ RECT 1655.755000 1631.060000 1657.020000 1631.540000 ;
+ RECT 1655.755000 1625.620000 1657.020000 1626.100000 ;
+ RECT 1655.755000 1620.180000 1657.020000 1620.660000 ;
+ RECT 1655.755000 1614.740000 1657.020000 1615.220000 ;
+ RECT 1655.755000 1603.860000 1657.020000 1604.340000 ;
+ RECT 1655.755000 1609.300000 1657.020000 1609.780000 ;
+ RECT 1655.755000 1598.420000 1657.020000 1598.900000 ;
+ RECT 1655.755000 1592.980000 1657.020000 1593.460000 ;
+ RECT 1655.755000 1587.540000 1657.020000 1588.020000 ;
+ RECT 1655.755000 1582.100000 1657.020000 1582.580000 ;
+ RECT 1655.755000 1576.660000 1657.020000 1577.140000 ;
+ RECT 1655.755000 1571.220000 1657.020000 1571.700000 ;
+ RECT 1655.755000 1560.340000 1657.020000 1560.820000 ;
+ RECT 1655.755000 1565.780000 1657.020000 1566.260000 ;
+ RECT 1655.755000 1554.900000 1657.020000 1555.380000 ;
+ RECT 1655.755000 1647.380000 1657.020000 1647.860000 ;
+ RECT 1835.920000 1548.570000 1837.020000 1745.140000 ;
+ RECT 1790.920000 1548.570000 1792.020000 1745.140000 ;
+ RECT 1848.730000 1547.320000 1849.730000 1747.580000 ;
+ RECT 1745.920000 1548.570000 1747.020000 1745.140000 ;
+ RECT 1700.920000 1548.570000 1702.020000 1745.140000 ;
+ RECT 1655.920000 1548.570000 1657.020000 1745.140000 ;
+ RECT 1652.090000 1547.320000 1653.090000 1747.580000 ;
+ LAYER met3 ;
+ RECT 1835.920000 1739.860000 1837.020000 1740.340000 ;
+ RECT 1848.730000 1739.860000 1849.730000 1740.340000 ;
+ RECT 1848.730000 1728.980000 1849.730000 1729.460000 ;
+ RECT 1848.730000 1723.540000 1849.730000 1724.020000 ;
+ RECT 1848.730000 1734.420000 1849.730000 1734.900000 ;
+ RECT 1835.920000 1734.420000 1837.020000 1734.900000 ;
+ RECT 1835.920000 1728.980000 1837.020000 1729.460000 ;
+ RECT 1835.920000 1723.540000 1837.020000 1724.020000 ;
+ RECT 1835.920000 1712.660000 1837.020000 1713.140000 ;
+ RECT 1835.920000 1718.100000 1837.020000 1718.580000 ;
+ RECT 1848.730000 1712.660000 1849.730000 1713.140000 ;
+ RECT 1848.730000 1718.100000 1849.730000 1718.580000 ;
+ RECT 1835.920000 1701.780000 1837.020000 1702.260000 ;
+ RECT 1835.920000 1707.220000 1837.020000 1707.700000 ;
+ RECT 1848.730000 1701.780000 1849.730000 1702.260000 ;
+ RECT 1848.730000 1707.220000 1849.730000 1707.700000 ;
+ RECT 1790.920000 1723.540000 1792.020000 1724.020000 ;
+ RECT 1790.920000 1728.980000 1792.020000 1729.460000 ;
+ RECT 1790.920000 1734.420000 1792.020000 1734.900000 ;
+ RECT 1790.920000 1739.860000 1792.020000 1740.340000 ;
+ RECT 1790.920000 1707.220000 1792.020000 1707.700000 ;
+ RECT 1790.920000 1701.780000 1792.020000 1702.260000 ;
+ RECT 1790.920000 1712.660000 1792.020000 1713.140000 ;
+ RECT 1790.920000 1718.100000 1792.020000 1718.580000 ;
+ RECT 1848.730000 1690.900000 1849.730000 1691.380000 ;
+ RECT 1848.730000 1685.460000 1849.730000 1685.940000 ;
+ RECT 1848.730000 1696.340000 1849.730000 1696.820000 ;
+ RECT 1835.920000 1696.340000 1837.020000 1696.820000 ;
+ RECT 1835.920000 1690.900000 1837.020000 1691.380000 ;
+ RECT 1835.920000 1685.460000 1837.020000 1685.940000 ;
+ RECT 1835.920000 1674.580000 1837.020000 1675.060000 ;
+ RECT 1835.920000 1680.020000 1837.020000 1680.500000 ;
+ RECT 1848.730000 1674.580000 1849.730000 1675.060000 ;
+ RECT 1848.730000 1680.020000 1849.730000 1680.500000 ;
+ RECT 1848.730000 1663.700000 1849.730000 1664.180000 ;
+ RECT 1848.730000 1669.140000 1849.730000 1669.620000 ;
+ RECT 1835.920000 1669.140000 1837.020000 1669.620000 ;
+ RECT 1835.920000 1663.700000 1837.020000 1664.180000 ;
+ RECT 1835.920000 1652.820000 1837.020000 1653.300000 ;
+ RECT 1835.920000 1658.260000 1837.020000 1658.740000 ;
+ RECT 1848.730000 1652.820000 1849.730000 1653.300000 ;
+ RECT 1848.730000 1658.260000 1849.730000 1658.740000 ;
+ RECT 1790.920000 1674.580000 1792.020000 1675.060000 ;
+ RECT 1790.920000 1680.020000 1792.020000 1680.500000 ;
+ RECT 1790.920000 1685.460000 1792.020000 1685.940000 ;
+ RECT 1790.920000 1690.900000 1792.020000 1691.380000 ;
+ RECT 1790.920000 1696.340000 1792.020000 1696.820000 ;
+ RECT 1790.920000 1652.820000 1792.020000 1653.300000 ;
+ RECT 1790.920000 1658.260000 1792.020000 1658.740000 ;
+ RECT 1790.920000 1663.700000 1792.020000 1664.180000 ;
+ RECT 1790.920000 1669.140000 1792.020000 1669.620000 ;
+ RECT 1745.920000 1728.980000 1747.020000 1729.460000 ;
+ RECT 1745.920000 1723.540000 1747.020000 1724.020000 ;
+ RECT 1745.920000 1734.420000 1747.020000 1734.900000 ;
+ RECT 1745.920000 1739.860000 1747.020000 1740.340000 ;
+ RECT 1700.920000 1723.540000 1702.020000 1724.020000 ;
+ RECT 1700.920000 1728.980000 1702.020000 1729.460000 ;
+ RECT 1700.920000 1734.420000 1702.020000 1734.900000 ;
+ RECT 1700.920000 1739.860000 1702.020000 1740.340000 ;
+ RECT 1745.920000 1701.780000 1747.020000 1702.260000 ;
+ RECT 1745.920000 1707.220000 1747.020000 1707.700000 ;
+ RECT 1745.920000 1712.660000 1747.020000 1713.140000 ;
+ RECT 1745.920000 1718.100000 1747.020000 1718.580000 ;
+ RECT 1700.920000 1701.780000 1702.020000 1702.260000 ;
+ RECT 1700.920000 1707.220000 1702.020000 1707.700000 ;
+ RECT 1700.920000 1712.660000 1702.020000 1713.140000 ;
+ RECT 1700.920000 1718.100000 1702.020000 1718.580000 ;
+ RECT 1652.090000 1739.860000 1653.090000 1740.340000 ;
+ RECT 1655.755000 1739.860000 1657.020000 1740.340000 ;
+ RECT 1652.090000 1728.980000 1653.090000 1729.460000 ;
+ RECT 1655.755000 1728.980000 1657.020000 1729.460000 ;
+ RECT 1652.090000 1734.420000 1653.090000 1734.900000 ;
+ RECT 1655.755000 1734.420000 1657.020000 1734.900000 ;
+ RECT 1652.090000 1723.540000 1653.090000 1724.020000 ;
+ RECT 1655.755000 1723.540000 1657.020000 1724.020000 ;
+ RECT 1652.090000 1718.100000 1653.090000 1718.580000 ;
+ RECT 1655.755000 1718.100000 1657.020000 1718.580000 ;
+ RECT 1652.090000 1712.660000 1653.090000 1713.140000 ;
+ RECT 1655.755000 1712.660000 1657.020000 1713.140000 ;
+ RECT 1652.090000 1707.220000 1653.090000 1707.700000 ;
+ RECT 1655.755000 1707.220000 1657.020000 1707.700000 ;
+ RECT 1652.090000 1701.780000 1653.090000 1702.260000 ;
+ RECT 1655.755000 1701.780000 1657.020000 1702.260000 ;
+ RECT 1745.920000 1674.580000 1747.020000 1675.060000 ;
+ RECT 1745.920000 1680.020000 1747.020000 1680.500000 ;
+ RECT 1745.920000 1685.460000 1747.020000 1685.940000 ;
+ RECT 1745.920000 1690.900000 1747.020000 1691.380000 ;
+ RECT 1745.920000 1696.340000 1747.020000 1696.820000 ;
+ RECT 1700.920000 1674.580000 1702.020000 1675.060000 ;
+ RECT 1700.920000 1680.020000 1702.020000 1680.500000 ;
+ RECT 1700.920000 1685.460000 1702.020000 1685.940000 ;
+ RECT 1700.920000 1690.900000 1702.020000 1691.380000 ;
+ RECT 1700.920000 1696.340000 1702.020000 1696.820000 ;
+ RECT 1745.920000 1652.820000 1747.020000 1653.300000 ;
+ RECT 1745.920000 1658.260000 1747.020000 1658.740000 ;
+ RECT 1745.920000 1663.700000 1747.020000 1664.180000 ;
+ RECT 1745.920000 1669.140000 1747.020000 1669.620000 ;
+ RECT 1700.920000 1652.820000 1702.020000 1653.300000 ;
+ RECT 1700.920000 1658.260000 1702.020000 1658.740000 ;
+ RECT 1700.920000 1663.700000 1702.020000 1664.180000 ;
+ RECT 1700.920000 1669.140000 1702.020000 1669.620000 ;
+ RECT 1652.090000 1696.340000 1653.090000 1696.820000 ;
+ RECT 1655.755000 1696.340000 1657.020000 1696.820000 ;
+ RECT 1652.090000 1685.460000 1653.090000 1685.940000 ;
+ RECT 1655.755000 1685.460000 1657.020000 1685.940000 ;
+ RECT 1652.090000 1690.900000 1653.090000 1691.380000 ;
+ RECT 1655.755000 1690.900000 1657.020000 1691.380000 ;
+ RECT 1652.090000 1680.020000 1653.090000 1680.500000 ;
+ RECT 1655.755000 1680.020000 1657.020000 1680.500000 ;
+ RECT 1652.090000 1674.580000 1653.090000 1675.060000 ;
+ RECT 1655.755000 1674.580000 1657.020000 1675.060000 ;
+ RECT 1652.090000 1669.140000 1653.090000 1669.620000 ;
+ RECT 1655.755000 1669.140000 1657.020000 1669.620000 ;
+ RECT 1652.090000 1663.700000 1653.090000 1664.180000 ;
+ RECT 1655.755000 1663.700000 1657.020000 1664.180000 ;
+ RECT 1652.090000 1658.260000 1653.090000 1658.740000 ;
+ RECT 1655.755000 1658.260000 1657.020000 1658.740000 ;
+ RECT 1652.090000 1652.820000 1653.090000 1653.300000 ;
+ RECT 1655.755000 1652.820000 1657.020000 1653.300000 ;
+ RECT 1835.920000 1636.500000 1837.020000 1636.980000 ;
+ RECT 1835.920000 1641.940000 1837.020000 1642.420000 ;
+ RECT 1848.730000 1636.500000 1849.730000 1636.980000 ;
+ RECT 1848.730000 1641.940000 1849.730000 1642.420000 ;
+ RECT 1848.730000 1625.620000 1849.730000 1626.100000 ;
+ RECT 1848.730000 1631.060000 1849.730000 1631.540000 ;
+ RECT 1835.920000 1631.060000 1837.020000 1631.540000 ;
+ RECT 1835.920000 1625.620000 1837.020000 1626.100000 ;
+ RECT 1835.920000 1614.740000 1837.020000 1615.220000 ;
+ RECT 1835.920000 1620.180000 1837.020000 1620.660000 ;
+ RECT 1848.730000 1614.740000 1849.730000 1615.220000 ;
+ RECT 1848.730000 1620.180000 1849.730000 1620.660000 ;
+ RECT 1848.730000 1603.860000 1849.730000 1604.340000 ;
+ RECT 1848.730000 1598.420000 1849.730000 1598.900000 ;
+ RECT 1848.730000 1609.300000 1849.730000 1609.780000 ;
+ RECT 1835.920000 1609.300000 1837.020000 1609.780000 ;
+ RECT 1835.920000 1603.860000 1837.020000 1604.340000 ;
+ RECT 1835.920000 1598.420000 1837.020000 1598.900000 ;
+ RECT 1790.920000 1625.620000 1792.020000 1626.100000 ;
+ RECT 1790.920000 1631.060000 1792.020000 1631.540000 ;
+ RECT 1790.920000 1636.500000 1792.020000 1636.980000 ;
+ RECT 1790.920000 1641.940000 1792.020000 1642.420000 ;
+ RECT 1790.920000 1598.420000 1792.020000 1598.900000 ;
+ RECT 1790.920000 1603.860000 1792.020000 1604.340000 ;
+ RECT 1790.920000 1609.300000 1792.020000 1609.780000 ;
+ RECT 1790.920000 1614.740000 1792.020000 1615.220000 ;
+ RECT 1790.920000 1620.180000 1792.020000 1620.660000 ;
+ RECT 1835.920000 1587.540000 1837.020000 1588.020000 ;
+ RECT 1835.920000 1592.980000 1837.020000 1593.460000 ;
+ RECT 1848.730000 1587.540000 1849.730000 1588.020000 ;
+ RECT 1848.730000 1592.980000 1849.730000 1593.460000 ;
+ RECT 1835.920000 1576.660000 1837.020000 1577.140000 ;
+ RECT 1835.920000 1582.100000 1837.020000 1582.580000 ;
+ RECT 1848.730000 1576.660000 1849.730000 1577.140000 ;
+ RECT 1848.730000 1582.100000 1849.730000 1582.580000 ;
+ RECT 1848.730000 1565.780000 1849.730000 1566.260000 ;
+ RECT 1848.730000 1560.340000 1849.730000 1560.820000 ;
+ RECT 1848.730000 1571.220000 1849.730000 1571.700000 ;
+ RECT 1835.920000 1571.220000 1837.020000 1571.700000 ;
+ RECT 1835.920000 1565.780000 1837.020000 1566.260000 ;
+ RECT 1835.920000 1560.340000 1837.020000 1560.820000 ;
+ RECT 1835.920000 1554.900000 1837.020000 1555.380000 ;
+ RECT 1848.730000 1554.900000 1849.730000 1555.380000 ;
+ RECT 1790.920000 1576.660000 1792.020000 1577.140000 ;
+ RECT 1790.920000 1582.100000 1792.020000 1582.580000 ;
+ RECT 1790.920000 1587.540000 1792.020000 1588.020000 ;
+ RECT 1790.920000 1592.980000 1792.020000 1593.460000 ;
+ RECT 1790.920000 1554.900000 1792.020000 1555.380000 ;
+ RECT 1790.920000 1560.340000 1792.020000 1560.820000 ;
+ RECT 1790.920000 1565.780000 1792.020000 1566.260000 ;
+ RECT 1790.920000 1571.220000 1792.020000 1571.700000 ;
+ RECT 1745.920000 1625.620000 1747.020000 1626.100000 ;
+ RECT 1745.920000 1631.060000 1747.020000 1631.540000 ;
+ RECT 1745.920000 1636.500000 1747.020000 1636.980000 ;
+ RECT 1745.920000 1641.940000 1747.020000 1642.420000 ;
+ RECT 1700.920000 1625.620000 1702.020000 1626.100000 ;
+ RECT 1700.920000 1631.060000 1702.020000 1631.540000 ;
+ RECT 1700.920000 1636.500000 1702.020000 1636.980000 ;
+ RECT 1700.920000 1641.940000 1702.020000 1642.420000 ;
+ RECT 1745.920000 1598.420000 1747.020000 1598.900000 ;
+ RECT 1745.920000 1603.860000 1747.020000 1604.340000 ;
+ RECT 1745.920000 1609.300000 1747.020000 1609.780000 ;
+ RECT 1745.920000 1614.740000 1747.020000 1615.220000 ;
+ RECT 1745.920000 1620.180000 1747.020000 1620.660000 ;
+ RECT 1700.920000 1598.420000 1702.020000 1598.900000 ;
+ RECT 1700.920000 1603.860000 1702.020000 1604.340000 ;
+ RECT 1700.920000 1609.300000 1702.020000 1609.780000 ;
+ RECT 1700.920000 1614.740000 1702.020000 1615.220000 ;
+ RECT 1700.920000 1620.180000 1702.020000 1620.660000 ;
+ RECT 1652.090000 1641.940000 1653.090000 1642.420000 ;
+ RECT 1655.755000 1641.940000 1657.020000 1642.420000 ;
+ RECT 1652.090000 1636.500000 1653.090000 1636.980000 ;
+ RECT 1655.755000 1636.500000 1657.020000 1636.980000 ;
+ RECT 1652.090000 1631.060000 1653.090000 1631.540000 ;
+ RECT 1655.755000 1631.060000 1657.020000 1631.540000 ;
+ RECT 1652.090000 1625.620000 1653.090000 1626.100000 ;
+ RECT 1655.755000 1625.620000 1657.020000 1626.100000 ;
+ RECT 1652.090000 1620.180000 1653.090000 1620.660000 ;
+ RECT 1655.755000 1620.180000 1657.020000 1620.660000 ;
+ RECT 1652.090000 1614.740000 1653.090000 1615.220000 ;
+ RECT 1655.755000 1614.740000 1657.020000 1615.220000 ;
+ RECT 1652.090000 1603.860000 1653.090000 1604.340000 ;
+ RECT 1655.755000 1603.860000 1657.020000 1604.340000 ;
+ RECT 1652.090000 1609.300000 1653.090000 1609.780000 ;
+ RECT 1655.755000 1609.300000 1657.020000 1609.780000 ;
+ RECT 1652.090000 1598.420000 1653.090000 1598.900000 ;
+ RECT 1655.755000 1598.420000 1657.020000 1598.900000 ;
+ RECT 1745.920000 1576.660000 1747.020000 1577.140000 ;
+ RECT 1745.920000 1582.100000 1747.020000 1582.580000 ;
+ RECT 1745.920000 1587.540000 1747.020000 1588.020000 ;
+ RECT 1745.920000 1592.980000 1747.020000 1593.460000 ;
+ RECT 1700.920000 1576.660000 1702.020000 1577.140000 ;
+ RECT 1700.920000 1582.100000 1702.020000 1582.580000 ;
+ RECT 1700.920000 1587.540000 1702.020000 1588.020000 ;
+ RECT 1700.920000 1592.980000 1702.020000 1593.460000 ;
+ RECT 1745.920000 1554.900000 1747.020000 1555.380000 ;
+ RECT 1745.920000 1560.340000 1747.020000 1560.820000 ;
+ RECT 1745.920000 1565.780000 1747.020000 1566.260000 ;
+ RECT 1745.920000 1571.220000 1747.020000 1571.700000 ;
+ RECT 1700.920000 1554.900000 1702.020000 1555.380000 ;
+ RECT 1700.920000 1560.340000 1702.020000 1560.820000 ;
+ RECT 1700.920000 1565.780000 1702.020000 1566.260000 ;
+ RECT 1700.920000 1571.220000 1702.020000 1571.700000 ;
+ RECT 1652.090000 1592.980000 1653.090000 1593.460000 ;
+ RECT 1655.755000 1592.980000 1657.020000 1593.460000 ;
+ RECT 1652.090000 1587.540000 1653.090000 1588.020000 ;
+ RECT 1655.755000 1587.540000 1657.020000 1588.020000 ;
+ RECT 1652.090000 1582.100000 1653.090000 1582.580000 ;
+ RECT 1655.755000 1582.100000 1657.020000 1582.580000 ;
+ RECT 1652.090000 1576.660000 1653.090000 1577.140000 ;
+ RECT 1655.755000 1576.660000 1657.020000 1577.140000 ;
+ RECT 1652.090000 1571.220000 1653.090000 1571.700000 ;
+ RECT 1655.755000 1571.220000 1657.020000 1571.700000 ;
+ RECT 1652.090000 1560.340000 1653.090000 1560.820000 ;
+ RECT 1655.755000 1560.340000 1657.020000 1560.820000 ;
+ RECT 1652.090000 1565.780000 1653.090000 1566.260000 ;
+ RECT 1655.755000 1565.780000 1657.020000 1566.260000 ;
+ RECT 1652.090000 1554.900000 1653.090000 1555.380000 ;
+ RECT 1655.755000 1554.900000 1657.020000 1555.380000 ;
+ RECT 1790.920000 1647.380000 1792.020000 1647.860000 ;
+ RECT 1835.920000 1647.380000 1837.020000 1647.860000 ;
+ RECT 1848.730000 1647.380000 1849.730000 1647.860000 ;
+ RECT 1700.920000 1647.380000 1702.020000 1647.860000 ;
+ RECT 1745.920000 1647.380000 1747.020000 1647.860000 ;
+ RECT 1652.090000 1647.380000 1653.090000 1647.860000 ;
+ RECT 1655.755000 1647.380000 1657.020000 1647.860000 ;
+ RECT 1650.860000 1744.140000 1850.960000 1745.140000 ;
+ RECT 1650.860000 1548.570000 1850.960000 1549.570000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 1547.320000 1653.090000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1652.090000 1746.580000 1653.090000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 1547.320000 1849.730000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1848.730000 1746.580000 1849.730000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1548.570000 1651.860000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1548.570000 1850.960000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1744.140000 1651.860000 1745.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1744.140000 1850.960000 1745.140000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 3373.560000 1857.120000 3374.040000 ;
+ RECT 1855.855000 3368.120000 1857.120000 3368.600000 ;
+ RECT 1855.855000 3362.680000 1857.120000 3363.160000 ;
+ RECT 1855.855000 3357.240000 1857.120000 3357.720000 ;
+ RECT 1852.190000 3349.660000 1853.190000 3379.920000 ;
+ RECT 2048.830000 3349.660000 2049.830000 3379.920000 ;
+ RECT 1856.020000 3350.910000 1857.120000 3378.160000 ;
+ RECT 1901.020000 3350.910000 1902.120000 3378.160000 ;
+ RECT 1946.020000 3350.910000 1947.120000 3378.160000 ;
+ RECT 1991.020000 3350.910000 1992.120000 3378.160000 ;
+ RECT 2036.020000 3350.910000 2037.120000 3378.160000 ;
+ LAYER met3 ;
+ RECT 2048.830000 3373.560000 2049.830000 3374.040000 ;
+ RECT 2048.830000 3368.120000 2049.830000 3368.600000 ;
+ RECT 2036.020000 3373.560000 2037.120000 3374.040000 ;
+ RECT 2036.020000 3368.120000 2037.120000 3368.600000 ;
+ RECT 1991.020000 3368.120000 1992.120000 3368.600000 ;
+ RECT 1991.020000 3373.560000 1992.120000 3374.040000 ;
+ RECT 1946.020000 3368.120000 1947.120000 3368.600000 ;
+ RECT 1901.020000 3368.120000 1902.120000 3368.600000 ;
+ RECT 1946.020000 3373.560000 1947.120000 3374.040000 ;
+ RECT 1901.020000 3373.560000 1902.120000 3374.040000 ;
+ RECT 1855.855000 3373.560000 1857.120000 3374.040000 ;
+ RECT 1852.190000 3373.560000 1853.190000 3374.040000 ;
+ RECT 1855.855000 3368.120000 1857.120000 3368.600000 ;
+ RECT 1852.190000 3368.120000 1853.190000 3368.600000 ;
+ RECT 2048.830000 3362.680000 2049.830000 3363.160000 ;
+ RECT 2048.830000 3357.240000 2049.830000 3357.720000 ;
+ RECT 2036.020000 3362.680000 2037.120000 3363.160000 ;
+ RECT 2036.020000 3357.240000 2037.120000 3357.720000 ;
+ RECT 1991.020000 3357.240000 1992.120000 3357.720000 ;
+ RECT 1991.020000 3362.680000 1992.120000 3363.160000 ;
+ RECT 1946.020000 3357.240000 1947.120000 3357.720000 ;
+ RECT 1901.020000 3357.240000 1902.120000 3357.720000 ;
+ RECT 1946.020000 3362.680000 1947.120000 3363.160000 ;
+ RECT 1901.020000 3362.680000 1902.120000 3363.160000 ;
+ RECT 1855.855000 3362.680000 1857.120000 3363.160000 ;
+ RECT 1852.190000 3362.680000 1853.190000 3363.160000 ;
+ RECT 1855.855000 3357.240000 1857.120000 3357.720000 ;
+ RECT 1852.190000 3357.240000 1853.190000 3357.720000 ;
+ RECT 1850.960000 3377.160000 2051.060000 3378.160000 ;
+ RECT 1850.960000 3350.910000 2051.060000 3351.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 3349.660000 1853.190000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 3378.920000 1853.190000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 3349.660000 2049.830000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 3378.920000 2049.830000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 3350.910000 1851.960000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 3350.910000 2051.060000 3351.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 3377.160000 1851.960000 3378.160000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 3377.160000 2051.060000 3378.160000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 1539.600000 1857.120000 1540.080000 ;
+ RECT 1855.855000 1528.720000 1857.120000 1529.200000 ;
+ RECT 1855.855000 1534.160000 1857.120000 1534.640000 ;
+ RECT 1855.855000 1523.280000 1857.120000 1523.760000 ;
+ RECT 1855.855000 1517.840000 1857.120000 1518.320000 ;
+ RECT 1855.855000 1512.400000 1857.120000 1512.880000 ;
+ RECT 1855.855000 1506.960000 1857.120000 1507.440000 ;
+ RECT 1855.855000 1501.520000 1857.120000 1502.000000 ;
+ RECT 1855.855000 1496.080000 1857.120000 1496.560000 ;
+ RECT 1855.855000 1485.200000 1857.120000 1485.680000 ;
+ RECT 1855.855000 1490.640000 1857.120000 1491.120000 ;
+ RECT 1855.855000 1479.760000 1857.120000 1480.240000 ;
+ RECT 1855.855000 1474.320000 1857.120000 1474.800000 ;
+ RECT 1855.855000 1468.880000 1857.120000 1469.360000 ;
+ RECT 1855.855000 1463.440000 1857.120000 1463.920000 ;
+ RECT 1855.855000 1458.000000 1857.120000 1458.480000 ;
+ RECT 1855.855000 1452.560000 1857.120000 1453.040000 ;
+ RECT 1855.855000 1441.680000 1857.120000 1442.160000 ;
+ RECT 1855.855000 1436.240000 1857.120000 1436.720000 ;
+ RECT 1855.855000 1430.800000 1857.120000 1431.280000 ;
+ RECT 1855.855000 1425.360000 1857.120000 1425.840000 ;
+ RECT 1855.855000 1419.920000 1857.120000 1420.400000 ;
+ RECT 1855.855000 1414.480000 1857.120000 1414.960000 ;
+ RECT 1855.855000 1403.600000 1857.120000 1404.080000 ;
+ RECT 1855.855000 1409.040000 1857.120000 1409.520000 ;
+ RECT 1855.855000 1398.160000 1857.120000 1398.640000 ;
+ RECT 1855.855000 1392.720000 1857.120000 1393.200000 ;
+ RECT 1855.855000 1387.280000 1857.120000 1387.760000 ;
+ RECT 1855.855000 1381.840000 1857.120000 1382.320000 ;
+ RECT 1855.855000 1376.400000 1857.120000 1376.880000 ;
+ RECT 1855.855000 1370.960000 1857.120000 1371.440000 ;
+ RECT 1855.855000 1360.080000 1857.120000 1360.560000 ;
+ RECT 1855.855000 1365.520000 1857.120000 1366.000000 ;
+ RECT 1855.855000 1354.640000 1857.120000 1355.120000 ;
+ RECT 1855.855000 1447.120000 1857.120000 1447.600000 ;
+ RECT 2036.020000 1348.310000 2037.120000 1544.880000 ;
+ RECT 1991.020000 1348.310000 1992.120000 1544.880000 ;
+ RECT 2048.830000 1347.060000 2049.830000 1547.320000 ;
+ RECT 1946.020000 1348.310000 1947.120000 1544.880000 ;
+ RECT 1901.020000 1348.310000 1902.120000 1544.880000 ;
+ RECT 1856.020000 1348.310000 1857.120000 1544.880000 ;
+ RECT 1852.190000 1347.060000 1853.190000 1547.320000 ;
+ LAYER met3 ;
+ RECT 2036.020000 1539.600000 2037.120000 1540.080000 ;
+ RECT 2048.830000 1539.600000 2049.830000 1540.080000 ;
+ RECT 2048.830000 1528.720000 2049.830000 1529.200000 ;
+ RECT 2048.830000 1523.280000 2049.830000 1523.760000 ;
+ RECT 2048.830000 1534.160000 2049.830000 1534.640000 ;
+ RECT 2036.020000 1534.160000 2037.120000 1534.640000 ;
+ RECT 2036.020000 1528.720000 2037.120000 1529.200000 ;
+ RECT 2036.020000 1523.280000 2037.120000 1523.760000 ;
+ RECT 2036.020000 1512.400000 2037.120000 1512.880000 ;
+ RECT 2036.020000 1517.840000 2037.120000 1518.320000 ;
+ RECT 2048.830000 1512.400000 2049.830000 1512.880000 ;
+ RECT 2048.830000 1517.840000 2049.830000 1518.320000 ;
+ RECT 2036.020000 1501.520000 2037.120000 1502.000000 ;
+ RECT 2036.020000 1506.960000 2037.120000 1507.440000 ;
+ RECT 2048.830000 1501.520000 2049.830000 1502.000000 ;
+ RECT 2048.830000 1506.960000 2049.830000 1507.440000 ;
+ RECT 1991.020000 1523.280000 1992.120000 1523.760000 ;
+ RECT 1991.020000 1528.720000 1992.120000 1529.200000 ;
+ RECT 1991.020000 1534.160000 1992.120000 1534.640000 ;
+ RECT 1991.020000 1539.600000 1992.120000 1540.080000 ;
+ RECT 1991.020000 1506.960000 1992.120000 1507.440000 ;
+ RECT 1991.020000 1501.520000 1992.120000 1502.000000 ;
+ RECT 1991.020000 1512.400000 1992.120000 1512.880000 ;
+ RECT 1991.020000 1517.840000 1992.120000 1518.320000 ;
+ RECT 2048.830000 1490.640000 2049.830000 1491.120000 ;
+ RECT 2048.830000 1485.200000 2049.830000 1485.680000 ;
+ RECT 2048.830000 1496.080000 2049.830000 1496.560000 ;
+ RECT 2036.020000 1496.080000 2037.120000 1496.560000 ;
+ RECT 2036.020000 1490.640000 2037.120000 1491.120000 ;
+ RECT 2036.020000 1485.200000 2037.120000 1485.680000 ;
+ RECT 2036.020000 1474.320000 2037.120000 1474.800000 ;
+ RECT 2036.020000 1479.760000 2037.120000 1480.240000 ;
+ RECT 2048.830000 1474.320000 2049.830000 1474.800000 ;
+ RECT 2048.830000 1479.760000 2049.830000 1480.240000 ;
+ RECT 2048.830000 1463.440000 2049.830000 1463.920000 ;
+ RECT 2048.830000 1468.880000 2049.830000 1469.360000 ;
+ RECT 2036.020000 1468.880000 2037.120000 1469.360000 ;
+ RECT 2036.020000 1463.440000 2037.120000 1463.920000 ;
+ RECT 2036.020000 1452.560000 2037.120000 1453.040000 ;
+ RECT 2036.020000 1458.000000 2037.120000 1458.480000 ;
+ RECT 2048.830000 1452.560000 2049.830000 1453.040000 ;
+ RECT 2048.830000 1458.000000 2049.830000 1458.480000 ;
+ RECT 1991.020000 1474.320000 1992.120000 1474.800000 ;
+ RECT 1991.020000 1479.760000 1992.120000 1480.240000 ;
+ RECT 1991.020000 1485.200000 1992.120000 1485.680000 ;
+ RECT 1991.020000 1490.640000 1992.120000 1491.120000 ;
+ RECT 1991.020000 1496.080000 1992.120000 1496.560000 ;
+ RECT 1991.020000 1452.560000 1992.120000 1453.040000 ;
+ RECT 1991.020000 1458.000000 1992.120000 1458.480000 ;
+ RECT 1991.020000 1463.440000 1992.120000 1463.920000 ;
+ RECT 1991.020000 1468.880000 1992.120000 1469.360000 ;
+ RECT 1946.020000 1528.720000 1947.120000 1529.200000 ;
+ RECT 1946.020000 1523.280000 1947.120000 1523.760000 ;
+ RECT 1946.020000 1534.160000 1947.120000 1534.640000 ;
+ RECT 1946.020000 1539.600000 1947.120000 1540.080000 ;
+ RECT 1901.020000 1523.280000 1902.120000 1523.760000 ;
+ RECT 1901.020000 1528.720000 1902.120000 1529.200000 ;
+ RECT 1901.020000 1534.160000 1902.120000 1534.640000 ;
+ RECT 1901.020000 1539.600000 1902.120000 1540.080000 ;
+ RECT 1946.020000 1501.520000 1947.120000 1502.000000 ;
+ RECT 1946.020000 1506.960000 1947.120000 1507.440000 ;
+ RECT 1946.020000 1512.400000 1947.120000 1512.880000 ;
+ RECT 1946.020000 1517.840000 1947.120000 1518.320000 ;
+ RECT 1901.020000 1501.520000 1902.120000 1502.000000 ;
+ RECT 1901.020000 1506.960000 1902.120000 1507.440000 ;
+ RECT 1901.020000 1512.400000 1902.120000 1512.880000 ;
+ RECT 1901.020000 1517.840000 1902.120000 1518.320000 ;
+ RECT 1852.190000 1539.600000 1853.190000 1540.080000 ;
+ RECT 1855.855000 1539.600000 1857.120000 1540.080000 ;
+ RECT 1852.190000 1528.720000 1853.190000 1529.200000 ;
+ RECT 1855.855000 1528.720000 1857.120000 1529.200000 ;
+ RECT 1852.190000 1534.160000 1853.190000 1534.640000 ;
+ RECT 1855.855000 1534.160000 1857.120000 1534.640000 ;
+ RECT 1852.190000 1523.280000 1853.190000 1523.760000 ;
+ RECT 1855.855000 1523.280000 1857.120000 1523.760000 ;
+ RECT 1852.190000 1517.840000 1853.190000 1518.320000 ;
+ RECT 1855.855000 1517.840000 1857.120000 1518.320000 ;
+ RECT 1852.190000 1512.400000 1853.190000 1512.880000 ;
+ RECT 1855.855000 1512.400000 1857.120000 1512.880000 ;
+ RECT 1852.190000 1506.960000 1853.190000 1507.440000 ;
+ RECT 1855.855000 1506.960000 1857.120000 1507.440000 ;
+ RECT 1852.190000 1501.520000 1853.190000 1502.000000 ;
+ RECT 1855.855000 1501.520000 1857.120000 1502.000000 ;
+ RECT 1946.020000 1474.320000 1947.120000 1474.800000 ;
+ RECT 1946.020000 1479.760000 1947.120000 1480.240000 ;
+ RECT 1946.020000 1485.200000 1947.120000 1485.680000 ;
+ RECT 1946.020000 1490.640000 1947.120000 1491.120000 ;
+ RECT 1946.020000 1496.080000 1947.120000 1496.560000 ;
+ RECT 1901.020000 1474.320000 1902.120000 1474.800000 ;
+ RECT 1901.020000 1479.760000 1902.120000 1480.240000 ;
+ RECT 1901.020000 1485.200000 1902.120000 1485.680000 ;
+ RECT 1901.020000 1490.640000 1902.120000 1491.120000 ;
+ RECT 1901.020000 1496.080000 1902.120000 1496.560000 ;
+ RECT 1946.020000 1452.560000 1947.120000 1453.040000 ;
+ RECT 1946.020000 1458.000000 1947.120000 1458.480000 ;
+ RECT 1946.020000 1463.440000 1947.120000 1463.920000 ;
+ RECT 1946.020000 1468.880000 1947.120000 1469.360000 ;
+ RECT 1901.020000 1452.560000 1902.120000 1453.040000 ;
+ RECT 1901.020000 1458.000000 1902.120000 1458.480000 ;
+ RECT 1901.020000 1463.440000 1902.120000 1463.920000 ;
+ RECT 1901.020000 1468.880000 1902.120000 1469.360000 ;
+ RECT 1852.190000 1496.080000 1853.190000 1496.560000 ;
+ RECT 1855.855000 1496.080000 1857.120000 1496.560000 ;
+ RECT 1852.190000 1485.200000 1853.190000 1485.680000 ;
+ RECT 1855.855000 1485.200000 1857.120000 1485.680000 ;
+ RECT 1852.190000 1490.640000 1853.190000 1491.120000 ;
+ RECT 1855.855000 1490.640000 1857.120000 1491.120000 ;
+ RECT 1852.190000 1479.760000 1853.190000 1480.240000 ;
+ RECT 1855.855000 1479.760000 1857.120000 1480.240000 ;
+ RECT 1852.190000 1474.320000 1853.190000 1474.800000 ;
+ RECT 1855.855000 1474.320000 1857.120000 1474.800000 ;
+ RECT 1852.190000 1468.880000 1853.190000 1469.360000 ;
+ RECT 1855.855000 1468.880000 1857.120000 1469.360000 ;
+ RECT 1852.190000 1463.440000 1853.190000 1463.920000 ;
+ RECT 1855.855000 1463.440000 1857.120000 1463.920000 ;
+ RECT 1852.190000 1458.000000 1853.190000 1458.480000 ;
+ RECT 1855.855000 1458.000000 1857.120000 1458.480000 ;
+ RECT 1852.190000 1452.560000 1853.190000 1453.040000 ;
+ RECT 1855.855000 1452.560000 1857.120000 1453.040000 ;
+ RECT 2036.020000 1436.240000 2037.120000 1436.720000 ;
+ RECT 2036.020000 1441.680000 2037.120000 1442.160000 ;
+ RECT 2048.830000 1436.240000 2049.830000 1436.720000 ;
+ RECT 2048.830000 1441.680000 2049.830000 1442.160000 ;
+ RECT 2048.830000 1425.360000 2049.830000 1425.840000 ;
+ RECT 2048.830000 1430.800000 2049.830000 1431.280000 ;
+ RECT 2036.020000 1430.800000 2037.120000 1431.280000 ;
+ RECT 2036.020000 1425.360000 2037.120000 1425.840000 ;
+ RECT 2036.020000 1414.480000 2037.120000 1414.960000 ;
+ RECT 2036.020000 1419.920000 2037.120000 1420.400000 ;
+ RECT 2048.830000 1414.480000 2049.830000 1414.960000 ;
+ RECT 2048.830000 1419.920000 2049.830000 1420.400000 ;
+ RECT 2048.830000 1403.600000 2049.830000 1404.080000 ;
+ RECT 2048.830000 1398.160000 2049.830000 1398.640000 ;
+ RECT 2048.830000 1409.040000 2049.830000 1409.520000 ;
+ RECT 2036.020000 1409.040000 2037.120000 1409.520000 ;
+ RECT 2036.020000 1403.600000 2037.120000 1404.080000 ;
+ RECT 2036.020000 1398.160000 2037.120000 1398.640000 ;
+ RECT 1991.020000 1425.360000 1992.120000 1425.840000 ;
+ RECT 1991.020000 1430.800000 1992.120000 1431.280000 ;
+ RECT 1991.020000 1436.240000 1992.120000 1436.720000 ;
+ RECT 1991.020000 1441.680000 1992.120000 1442.160000 ;
+ RECT 1991.020000 1398.160000 1992.120000 1398.640000 ;
+ RECT 1991.020000 1403.600000 1992.120000 1404.080000 ;
+ RECT 1991.020000 1409.040000 1992.120000 1409.520000 ;
+ RECT 1991.020000 1414.480000 1992.120000 1414.960000 ;
+ RECT 1991.020000 1419.920000 1992.120000 1420.400000 ;
+ RECT 2036.020000 1387.280000 2037.120000 1387.760000 ;
+ RECT 2036.020000 1392.720000 2037.120000 1393.200000 ;
+ RECT 2048.830000 1387.280000 2049.830000 1387.760000 ;
+ RECT 2048.830000 1392.720000 2049.830000 1393.200000 ;
+ RECT 2036.020000 1376.400000 2037.120000 1376.880000 ;
+ RECT 2036.020000 1381.840000 2037.120000 1382.320000 ;
+ RECT 2048.830000 1376.400000 2049.830000 1376.880000 ;
+ RECT 2048.830000 1381.840000 2049.830000 1382.320000 ;
+ RECT 2048.830000 1365.520000 2049.830000 1366.000000 ;
+ RECT 2048.830000 1360.080000 2049.830000 1360.560000 ;
+ RECT 2048.830000 1370.960000 2049.830000 1371.440000 ;
+ RECT 2036.020000 1370.960000 2037.120000 1371.440000 ;
+ RECT 2036.020000 1365.520000 2037.120000 1366.000000 ;
+ RECT 2036.020000 1360.080000 2037.120000 1360.560000 ;
+ RECT 2036.020000 1354.640000 2037.120000 1355.120000 ;
+ RECT 2048.830000 1354.640000 2049.830000 1355.120000 ;
+ RECT 1991.020000 1376.400000 1992.120000 1376.880000 ;
+ RECT 1991.020000 1381.840000 1992.120000 1382.320000 ;
+ RECT 1991.020000 1387.280000 1992.120000 1387.760000 ;
+ RECT 1991.020000 1392.720000 1992.120000 1393.200000 ;
+ RECT 1991.020000 1354.640000 1992.120000 1355.120000 ;
+ RECT 1991.020000 1360.080000 1992.120000 1360.560000 ;
+ RECT 1991.020000 1365.520000 1992.120000 1366.000000 ;
+ RECT 1991.020000 1370.960000 1992.120000 1371.440000 ;
+ RECT 1946.020000 1425.360000 1947.120000 1425.840000 ;
+ RECT 1946.020000 1430.800000 1947.120000 1431.280000 ;
+ RECT 1946.020000 1436.240000 1947.120000 1436.720000 ;
+ RECT 1946.020000 1441.680000 1947.120000 1442.160000 ;
+ RECT 1901.020000 1425.360000 1902.120000 1425.840000 ;
+ RECT 1901.020000 1430.800000 1902.120000 1431.280000 ;
+ RECT 1901.020000 1436.240000 1902.120000 1436.720000 ;
+ RECT 1901.020000 1441.680000 1902.120000 1442.160000 ;
+ RECT 1946.020000 1398.160000 1947.120000 1398.640000 ;
+ RECT 1946.020000 1403.600000 1947.120000 1404.080000 ;
+ RECT 1946.020000 1409.040000 1947.120000 1409.520000 ;
+ RECT 1946.020000 1414.480000 1947.120000 1414.960000 ;
+ RECT 1946.020000 1419.920000 1947.120000 1420.400000 ;
+ RECT 1901.020000 1398.160000 1902.120000 1398.640000 ;
+ RECT 1901.020000 1403.600000 1902.120000 1404.080000 ;
+ RECT 1901.020000 1409.040000 1902.120000 1409.520000 ;
+ RECT 1901.020000 1414.480000 1902.120000 1414.960000 ;
+ RECT 1901.020000 1419.920000 1902.120000 1420.400000 ;
+ RECT 1852.190000 1441.680000 1853.190000 1442.160000 ;
+ RECT 1855.855000 1441.680000 1857.120000 1442.160000 ;
+ RECT 1852.190000 1436.240000 1853.190000 1436.720000 ;
+ RECT 1855.855000 1436.240000 1857.120000 1436.720000 ;
+ RECT 1852.190000 1430.800000 1853.190000 1431.280000 ;
+ RECT 1855.855000 1430.800000 1857.120000 1431.280000 ;
+ RECT 1852.190000 1425.360000 1853.190000 1425.840000 ;
+ RECT 1855.855000 1425.360000 1857.120000 1425.840000 ;
+ RECT 1852.190000 1419.920000 1853.190000 1420.400000 ;
+ RECT 1855.855000 1419.920000 1857.120000 1420.400000 ;
+ RECT 1852.190000 1414.480000 1853.190000 1414.960000 ;
+ RECT 1855.855000 1414.480000 1857.120000 1414.960000 ;
+ RECT 1852.190000 1403.600000 1853.190000 1404.080000 ;
+ RECT 1855.855000 1403.600000 1857.120000 1404.080000 ;
+ RECT 1852.190000 1409.040000 1853.190000 1409.520000 ;
+ RECT 1855.855000 1409.040000 1857.120000 1409.520000 ;
+ RECT 1852.190000 1398.160000 1853.190000 1398.640000 ;
+ RECT 1855.855000 1398.160000 1857.120000 1398.640000 ;
+ RECT 1946.020000 1376.400000 1947.120000 1376.880000 ;
+ RECT 1946.020000 1381.840000 1947.120000 1382.320000 ;
+ RECT 1946.020000 1387.280000 1947.120000 1387.760000 ;
+ RECT 1946.020000 1392.720000 1947.120000 1393.200000 ;
+ RECT 1901.020000 1376.400000 1902.120000 1376.880000 ;
+ RECT 1901.020000 1381.840000 1902.120000 1382.320000 ;
+ RECT 1901.020000 1387.280000 1902.120000 1387.760000 ;
+ RECT 1901.020000 1392.720000 1902.120000 1393.200000 ;
+ RECT 1946.020000 1354.640000 1947.120000 1355.120000 ;
+ RECT 1946.020000 1360.080000 1947.120000 1360.560000 ;
+ RECT 1946.020000 1365.520000 1947.120000 1366.000000 ;
+ RECT 1946.020000 1370.960000 1947.120000 1371.440000 ;
+ RECT 1901.020000 1354.640000 1902.120000 1355.120000 ;
+ RECT 1901.020000 1360.080000 1902.120000 1360.560000 ;
+ RECT 1901.020000 1365.520000 1902.120000 1366.000000 ;
+ RECT 1901.020000 1370.960000 1902.120000 1371.440000 ;
+ RECT 1852.190000 1392.720000 1853.190000 1393.200000 ;
+ RECT 1855.855000 1392.720000 1857.120000 1393.200000 ;
+ RECT 1852.190000 1387.280000 1853.190000 1387.760000 ;
+ RECT 1855.855000 1387.280000 1857.120000 1387.760000 ;
+ RECT 1852.190000 1381.840000 1853.190000 1382.320000 ;
+ RECT 1855.855000 1381.840000 1857.120000 1382.320000 ;
+ RECT 1852.190000 1376.400000 1853.190000 1376.880000 ;
+ RECT 1855.855000 1376.400000 1857.120000 1376.880000 ;
+ RECT 1852.190000 1370.960000 1853.190000 1371.440000 ;
+ RECT 1855.855000 1370.960000 1857.120000 1371.440000 ;
+ RECT 1852.190000 1360.080000 1853.190000 1360.560000 ;
+ RECT 1855.855000 1360.080000 1857.120000 1360.560000 ;
+ RECT 1852.190000 1365.520000 1853.190000 1366.000000 ;
+ RECT 1855.855000 1365.520000 1857.120000 1366.000000 ;
+ RECT 1852.190000 1354.640000 1853.190000 1355.120000 ;
+ RECT 1855.855000 1354.640000 1857.120000 1355.120000 ;
+ RECT 1991.020000 1447.120000 1992.120000 1447.600000 ;
+ RECT 2036.020000 1447.120000 2037.120000 1447.600000 ;
+ RECT 2048.830000 1447.120000 2049.830000 1447.600000 ;
+ RECT 1901.020000 1447.120000 1902.120000 1447.600000 ;
+ RECT 1946.020000 1447.120000 1947.120000 1447.600000 ;
+ RECT 1852.190000 1447.120000 1853.190000 1447.600000 ;
+ RECT 1855.855000 1447.120000 1857.120000 1447.600000 ;
+ RECT 1850.960000 1543.880000 2051.060000 1544.880000 ;
+ RECT 1850.960000 1348.310000 2051.060000 1349.310000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 1347.060000 1853.190000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 1546.320000 1853.190000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 1347.060000 2049.830000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 1546.320000 2049.830000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1348.310000 1851.960000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1348.310000 2051.060000 1349.310000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1543.880000 1851.960000 1544.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1543.880000 2051.060000 1544.880000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 1339.340000 1857.120000 1339.820000 ;
+ RECT 1855.855000 1328.460000 1857.120000 1328.940000 ;
+ RECT 1855.855000 1333.900000 1857.120000 1334.380000 ;
+ RECT 1855.855000 1323.020000 1857.120000 1323.500000 ;
+ RECT 1855.855000 1317.580000 1857.120000 1318.060000 ;
+ RECT 1855.855000 1312.140000 1857.120000 1312.620000 ;
+ RECT 1855.855000 1306.700000 1857.120000 1307.180000 ;
+ RECT 1855.855000 1301.260000 1857.120000 1301.740000 ;
+ RECT 1855.855000 1295.820000 1857.120000 1296.300000 ;
+ RECT 1855.855000 1284.940000 1857.120000 1285.420000 ;
+ RECT 1855.855000 1290.380000 1857.120000 1290.860000 ;
+ RECT 1855.855000 1279.500000 1857.120000 1279.980000 ;
+ RECT 1855.855000 1274.060000 1857.120000 1274.540000 ;
+ RECT 1855.855000 1268.620000 1857.120000 1269.100000 ;
+ RECT 1855.855000 1263.180000 1857.120000 1263.660000 ;
+ RECT 1855.855000 1257.740000 1857.120000 1258.220000 ;
+ RECT 1855.855000 1252.300000 1857.120000 1252.780000 ;
+ RECT 1855.855000 1241.420000 1857.120000 1241.900000 ;
+ RECT 1855.855000 1235.980000 1857.120000 1236.460000 ;
+ RECT 1855.855000 1230.540000 1857.120000 1231.020000 ;
+ RECT 1855.855000 1225.100000 1857.120000 1225.580000 ;
+ RECT 1855.855000 1219.660000 1857.120000 1220.140000 ;
+ RECT 1855.855000 1214.220000 1857.120000 1214.700000 ;
+ RECT 1855.855000 1203.340000 1857.120000 1203.820000 ;
+ RECT 1855.855000 1208.780000 1857.120000 1209.260000 ;
+ RECT 1855.855000 1197.900000 1857.120000 1198.380000 ;
+ RECT 1855.855000 1192.460000 1857.120000 1192.940000 ;
+ RECT 1855.855000 1187.020000 1857.120000 1187.500000 ;
+ RECT 1855.855000 1181.580000 1857.120000 1182.060000 ;
+ RECT 1855.855000 1176.140000 1857.120000 1176.620000 ;
+ RECT 1855.855000 1170.700000 1857.120000 1171.180000 ;
+ RECT 1855.855000 1159.820000 1857.120000 1160.300000 ;
+ RECT 1855.855000 1165.260000 1857.120000 1165.740000 ;
+ RECT 1855.855000 1154.380000 1857.120000 1154.860000 ;
+ RECT 1855.855000 1246.860000 1857.120000 1247.340000 ;
+ RECT 2036.020000 1148.050000 2037.120000 1344.620000 ;
+ RECT 1991.020000 1148.050000 1992.120000 1344.620000 ;
+ RECT 2048.830000 1146.800000 2049.830000 1347.060000 ;
+ RECT 1946.020000 1148.050000 1947.120000 1344.620000 ;
+ RECT 1901.020000 1148.050000 1902.120000 1344.620000 ;
+ RECT 1856.020000 1148.050000 1857.120000 1344.620000 ;
+ RECT 1852.190000 1146.800000 1853.190000 1347.060000 ;
+ LAYER met3 ;
+ RECT 2036.020000 1339.340000 2037.120000 1339.820000 ;
+ RECT 2048.830000 1339.340000 2049.830000 1339.820000 ;
+ RECT 2048.830000 1328.460000 2049.830000 1328.940000 ;
+ RECT 2048.830000 1323.020000 2049.830000 1323.500000 ;
+ RECT 2048.830000 1333.900000 2049.830000 1334.380000 ;
+ RECT 2036.020000 1333.900000 2037.120000 1334.380000 ;
+ RECT 2036.020000 1328.460000 2037.120000 1328.940000 ;
+ RECT 2036.020000 1323.020000 2037.120000 1323.500000 ;
+ RECT 2036.020000 1312.140000 2037.120000 1312.620000 ;
+ RECT 2036.020000 1317.580000 2037.120000 1318.060000 ;
+ RECT 2048.830000 1312.140000 2049.830000 1312.620000 ;
+ RECT 2048.830000 1317.580000 2049.830000 1318.060000 ;
+ RECT 2036.020000 1301.260000 2037.120000 1301.740000 ;
+ RECT 2036.020000 1306.700000 2037.120000 1307.180000 ;
+ RECT 2048.830000 1301.260000 2049.830000 1301.740000 ;
+ RECT 2048.830000 1306.700000 2049.830000 1307.180000 ;
+ RECT 1991.020000 1323.020000 1992.120000 1323.500000 ;
+ RECT 1991.020000 1328.460000 1992.120000 1328.940000 ;
+ RECT 1991.020000 1333.900000 1992.120000 1334.380000 ;
+ RECT 1991.020000 1339.340000 1992.120000 1339.820000 ;
+ RECT 1991.020000 1306.700000 1992.120000 1307.180000 ;
+ RECT 1991.020000 1301.260000 1992.120000 1301.740000 ;
+ RECT 1991.020000 1312.140000 1992.120000 1312.620000 ;
+ RECT 1991.020000 1317.580000 1992.120000 1318.060000 ;
+ RECT 2048.830000 1290.380000 2049.830000 1290.860000 ;
+ RECT 2048.830000 1284.940000 2049.830000 1285.420000 ;
+ RECT 2048.830000 1295.820000 2049.830000 1296.300000 ;
+ RECT 2036.020000 1295.820000 2037.120000 1296.300000 ;
+ RECT 2036.020000 1290.380000 2037.120000 1290.860000 ;
+ RECT 2036.020000 1284.940000 2037.120000 1285.420000 ;
+ RECT 2036.020000 1274.060000 2037.120000 1274.540000 ;
+ RECT 2036.020000 1279.500000 2037.120000 1279.980000 ;
+ RECT 2048.830000 1274.060000 2049.830000 1274.540000 ;
+ RECT 2048.830000 1279.500000 2049.830000 1279.980000 ;
+ RECT 2048.830000 1263.180000 2049.830000 1263.660000 ;
+ RECT 2048.830000 1268.620000 2049.830000 1269.100000 ;
+ RECT 2036.020000 1268.620000 2037.120000 1269.100000 ;
+ RECT 2036.020000 1263.180000 2037.120000 1263.660000 ;
+ RECT 2036.020000 1252.300000 2037.120000 1252.780000 ;
+ RECT 2036.020000 1257.740000 2037.120000 1258.220000 ;
+ RECT 2048.830000 1252.300000 2049.830000 1252.780000 ;
+ RECT 2048.830000 1257.740000 2049.830000 1258.220000 ;
+ RECT 1991.020000 1274.060000 1992.120000 1274.540000 ;
+ RECT 1991.020000 1279.500000 1992.120000 1279.980000 ;
+ RECT 1991.020000 1284.940000 1992.120000 1285.420000 ;
+ RECT 1991.020000 1290.380000 1992.120000 1290.860000 ;
+ RECT 1991.020000 1295.820000 1992.120000 1296.300000 ;
+ RECT 1991.020000 1252.300000 1992.120000 1252.780000 ;
+ RECT 1991.020000 1257.740000 1992.120000 1258.220000 ;
+ RECT 1991.020000 1263.180000 1992.120000 1263.660000 ;
+ RECT 1991.020000 1268.620000 1992.120000 1269.100000 ;
+ RECT 1946.020000 1328.460000 1947.120000 1328.940000 ;
+ RECT 1946.020000 1323.020000 1947.120000 1323.500000 ;
+ RECT 1946.020000 1333.900000 1947.120000 1334.380000 ;
+ RECT 1946.020000 1339.340000 1947.120000 1339.820000 ;
+ RECT 1901.020000 1323.020000 1902.120000 1323.500000 ;
+ RECT 1901.020000 1328.460000 1902.120000 1328.940000 ;
+ RECT 1901.020000 1333.900000 1902.120000 1334.380000 ;
+ RECT 1901.020000 1339.340000 1902.120000 1339.820000 ;
+ RECT 1946.020000 1301.260000 1947.120000 1301.740000 ;
+ RECT 1946.020000 1306.700000 1947.120000 1307.180000 ;
+ RECT 1946.020000 1312.140000 1947.120000 1312.620000 ;
+ RECT 1946.020000 1317.580000 1947.120000 1318.060000 ;
+ RECT 1901.020000 1301.260000 1902.120000 1301.740000 ;
+ RECT 1901.020000 1306.700000 1902.120000 1307.180000 ;
+ RECT 1901.020000 1312.140000 1902.120000 1312.620000 ;
+ RECT 1901.020000 1317.580000 1902.120000 1318.060000 ;
+ RECT 1852.190000 1339.340000 1853.190000 1339.820000 ;
+ RECT 1855.855000 1339.340000 1857.120000 1339.820000 ;
+ RECT 1852.190000 1328.460000 1853.190000 1328.940000 ;
+ RECT 1855.855000 1328.460000 1857.120000 1328.940000 ;
+ RECT 1852.190000 1333.900000 1853.190000 1334.380000 ;
+ RECT 1855.855000 1333.900000 1857.120000 1334.380000 ;
+ RECT 1852.190000 1323.020000 1853.190000 1323.500000 ;
+ RECT 1855.855000 1323.020000 1857.120000 1323.500000 ;
+ RECT 1852.190000 1317.580000 1853.190000 1318.060000 ;
+ RECT 1855.855000 1317.580000 1857.120000 1318.060000 ;
+ RECT 1852.190000 1312.140000 1853.190000 1312.620000 ;
+ RECT 1855.855000 1312.140000 1857.120000 1312.620000 ;
+ RECT 1852.190000 1306.700000 1853.190000 1307.180000 ;
+ RECT 1855.855000 1306.700000 1857.120000 1307.180000 ;
+ RECT 1852.190000 1301.260000 1853.190000 1301.740000 ;
+ RECT 1855.855000 1301.260000 1857.120000 1301.740000 ;
+ RECT 1946.020000 1274.060000 1947.120000 1274.540000 ;
+ RECT 1946.020000 1279.500000 1947.120000 1279.980000 ;
+ RECT 1946.020000 1284.940000 1947.120000 1285.420000 ;
+ RECT 1946.020000 1290.380000 1947.120000 1290.860000 ;
+ RECT 1946.020000 1295.820000 1947.120000 1296.300000 ;
+ RECT 1901.020000 1274.060000 1902.120000 1274.540000 ;
+ RECT 1901.020000 1279.500000 1902.120000 1279.980000 ;
+ RECT 1901.020000 1284.940000 1902.120000 1285.420000 ;
+ RECT 1901.020000 1290.380000 1902.120000 1290.860000 ;
+ RECT 1901.020000 1295.820000 1902.120000 1296.300000 ;
+ RECT 1946.020000 1252.300000 1947.120000 1252.780000 ;
+ RECT 1946.020000 1257.740000 1947.120000 1258.220000 ;
+ RECT 1946.020000 1263.180000 1947.120000 1263.660000 ;
+ RECT 1946.020000 1268.620000 1947.120000 1269.100000 ;
+ RECT 1901.020000 1252.300000 1902.120000 1252.780000 ;
+ RECT 1901.020000 1257.740000 1902.120000 1258.220000 ;
+ RECT 1901.020000 1263.180000 1902.120000 1263.660000 ;
+ RECT 1901.020000 1268.620000 1902.120000 1269.100000 ;
+ RECT 1852.190000 1295.820000 1853.190000 1296.300000 ;
+ RECT 1855.855000 1295.820000 1857.120000 1296.300000 ;
+ RECT 1852.190000 1284.940000 1853.190000 1285.420000 ;
+ RECT 1855.855000 1284.940000 1857.120000 1285.420000 ;
+ RECT 1852.190000 1290.380000 1853.190000 1290.860000 ;
+ RECT 1855.855000 1290.380000 1857.120000 1290.860000 ;
+ RECT 1852.190000 1279.500000 1853.190000 1279.980000 ;
+ RECT 1855.855000 1279.500000 1857.120000 1279.980000 ;
+ RECT 1852.190000 1274.060000 1853.190000 1274.540000 ;
+ RECT 1855.855000 1274.060000 1857.120000 1274.540000 ;
+ RECT 1852.190000 1268.620000 1853.190000 1269.100000 ;
+ RECT 1855.855000 1268.620000 1857.120000 1269.100000 ;
+ RECT 1852.190000 1263.180000 1853.190000 1263.660000 ;
+ RECT 1855.855000 1263.180000 1857.120000 1263.660000 ;
+ RECT 1852.190000 1257.740000 1853.190000 1258.220000 ;
+ RECT 1855.855000 1257.740000 1857.120000 1258.220000 ;
+ RECT 1852.190000 1252.300000 1853.190000 1252.780000 ;
+ RECT 1855.855000 1252.300000 1857.120000 1252.780000 ;
+ RECT 2036.020000 1235.980000 2037.120000 1236.460000 ;
+ RECT 2036.020000 1241.420000 2037.120000 1241.900000 ;
+ RECT 2048.830000 1235.980000 2049.830000 1236.460000 ;
+ RECT 2048.830000 1241.420000 2049.830000 1241.900000 ;
+ RECT 2048.830000 1225.100000 2049.830000 1225.580000 ;
+ RECT 2048.830000 1230.540000 2049.830000 1231.020000 ;
+ RECT 2036.020000 1230.540000 2037.120000 1231.020000 ;
+ RECT 2036.020000 1225.100000 2037.120000 1225.580000 ;
+ RECT 2036.020000 1214.220000 2037.120000 1214.700000 ;
+ RECT 2036.020000 1219.660000 2037.120000 1220.140000 ;
+ RECT 2048.830000 1214.220000 2049.830000 1214.700000 ;
+ RECT 2048.830000 1219.660000 2049.830000 1220.140000 ;
+ RECT 2048.830000 1203.340000 2049.830000 1203.820000 ;
+ RECT 2048.830000 1197.900000 2049.830000 1198.380000 ;
+ RECT 2048.830000 1208.780000 2049.830000 1209.260000 ;
+ RECT 2036.020000 1208.780000 2037.120000 1209.260000 ;
+ RECT 2036.020000 1203.340000 2037.120000 1203.820000 ;
+ RECT 2036.020000 1197.900000 2037.120000 1198.380000 ;
+ RECT 1991.020000 1225.100000 1992.120000 1225.580000 ;
+ RECT 1991.020000 1230.540000 1992.120000 1231.020000 ;
+ RECT 1991.020000 1235.980000 1992.120000 1236.460000 ;
+ RECT 1991.020000 1241.420000 1992.120000 1241.900000 ;
+ RECT 1991.020000 1197.900000 1992.120000 1198.380000 ;
+ RECT 1991.020000 1203.340000 1992.120000 1203.820000 ;
+ RECT 1991.020000 1208.780000 1992.120000 1209.260000 ;
+ RECT 1991.020000 1214.220000 1992.120000 1214.700000 ;
+ RECT 1991.020000 1219.660000 1992.120000 1220.140000 ;
+ RECT 2036.020000 1187.020000 2037.120000 1187.500000 ;
+ RECT 2036.020000 1192.460000 2037.120000 1192.940000 ;
+ RECT 2048.830000 1187.020000 2049.830000 1187.500000 ;
+ RECT 2048.830000 1192.460000 2049.830000 1192.940000 ;
+ RECT 2036.020000 1176.140000 2037.120000 1176.620000 ;
+ RECT 2036.020000 1181.580000 2037.120000 1182.060000 ;
+ RECT 2048.830000 1176.140000 2049.830000 1176.620000 ;
+ RECT 2048.830000 1181.580000 2049.830000 1182.060000 ;
+ RECT 2048.830000 1165.260000 2049.830000 1165.740000 ;
+ RECT 2048.830000 1159.820000 2049.830000 1160.300000 ;
+ RECT 2048.830000 1170.700000 2049.830000 1171.180000 ;
+ RECT 2036.020000 1170.700000 2037.120000 1171.180000 ;
+ RECT 2036.020000 1165.260000 2037.120000 1165.740000 ;
+ RECT 2036.020000 1159.820000 2037.120000 1160.300000 ;
+ RECT 2036.020000 1154.380000 2037.120000 1154.860000 ;
+ RECT 2048.830000 1154.380000 2049.830000 1154.860000 ;
+ RECT 1991.020000 1176.140000 1992.120000 1176.620000 ;
+ RECT 1991.020000 1181.580000 1992.120000 1182.060000 ;
+ RECT 1991.020000 1187.020000 1992.120000 1187.500000 ;
+ RECT 1991.020000 1192.460000 1992.120000 1192.940000 ;
+ RECT 1991.020000 1154.380000 1992.120000 1154.860000 ;
+ RECT 1991.020000 1159.820000 1992.120000 1160.300000 ;
+ RECT 1991.020000 1165.260000 1992.120000 1165.740000 ;
+ RECT 1991.020000 1170.700000 1992.120000 1171.180000 ;
+ RECT 1946.020000 1225.100000 1947.120000 1225.580000 ;
+ RECT 1946.020000 1230.540000 1947.120000 1231.020000 ;
+ RECT 1946.020000 1235.980000 1947.120000 1236.460000 ;
+ RECT 1946.020000 1241.420000 1947.120000 1241.900000 ;
+ RECT 1901.020000 1225.100000 1902.120000 1225.580000 ;
+ RECT 1901.020000 1230.540000 1902.120000 1231.020000 ;
+ RECT 1901.020000 1235.980000 1902.120000 1236.460000 ;
+ RECT 1901.020000 1241.420000 1902.120000 1241.900000 ;
+ RECT 1946.020000 1197.900000 1947.120000 1198.380000 ;
+ RECT 1946.020000 1203.340000 1947.120000 1203.820000 ;
+ RECT 1946.020000 1208.780000 1947.120000 1209.260000 ;
+ RECT 1946.020000 1214.220000 1947.120000 1214.700000 ;
+ RECT 1946.020000 1219.660000 1947.120000 1220.140000 ;
+ RECT 1901.020000 1197.900000 1902.120000 1198.380000 ;
+ RECT 1901.020000 1203.340000 1902.120000 1203.820000 ;
+ RECT 1901.020000 1208.780000 1902.120000 1209.260000 ;
+ RECT 1901.020000 1214.220000 1902.120000 1214.700000 ;
+ RECT 1901.020000 1219.660000 1902.120000 1220.140000 ;
+ RECT 1852.190000 1241.420000 1853.190000 1241.900000 ;
+ RECT 1855.855000 1241.420000 1857.120000 1241.900000 ;
+ RECT 1852.190000 1235.980000 1853.190000 1236.460000 ;
+ RECT 1855.855000 1235.980000 1857.120000 1236.460000 ;
+ RECT 1852.190000 1230.540000 1853.190000 1231.020000 ;
+ RECT 1855.855000 1230.540000 1857.120000 1231.020000 ;
+ RECT 1852.190000 1225.100000 1853.190000 1225.580000 ;
+ RECT 1855.855000 1225.100000 1857.120000 1225.580000 ;
+ RECT 1852.190000 1219.660000 1853.190000 1220.140000 ;
+ RECT 1855.855000 1219.660000 1857.120000 1220.140000 ;
+ RECT 1852.190000 1214.220000 1853.190000 1214.700000 ;
+ RECT 1855.855000 1214.220000 1857.120000 1214.700000 ;
+ RECT 1852.190000 1203.340000 1853.190000 1203.820000 ;
+ RECT 1855.855000 1203.340000 1857.120000 1203.820000 ;
+ RECT 1852.190000 1208.780000 1853.190000 1209.260000 ;
+ RECT 1855.855000 1208.780000 1857.120000 1209.260000 ;
+ RECT 1852.190000 1197.900000 1853.190000 1198.380000 ;
+ RECT 1855.855000 1197.900000 1857.120000 1198.380000 ;
+ RECT 1946.020000 1176.140000 1947.120000 1176.620000 ;
+ RECT 1946.020000 1181.580000 1947.120000 1182.060000 ;
+ RECT 1946.020000 1187.020000 1947.120000 1187.500000 ;
+ RECT 1946.020000 1192.460000 1947.120000 1192.940000 ;
+ RECT 1901.020000 1176.140000 1902.120000 1176.620000 ;
+ RECT 1901.020000 1181.580000 1902.120000 1182.060000 ;
+ RECT 1901.020000 1187.020000 1902.120000 1187.500000 ;
+ RECT 1901.020000 1192.460000 1902.120000 1192.940000 ;
+ RECT 1946.020000 1154.380000 1947.120000 1154.860000 ;
+ RECT 1946.020000 1159.820000 1947.120000 1160.300000 ;
+ RECT 1946.020000 1165.260000 1947.120000 1165.740000 ;
+ RECT 1946.020000 1170.700000 1947.120000 1171.180000 ;
+ RECT 1901.020000 1154.380000 1902.120000 1154.860000 ;
+ RECT 1901.020000 1159.820000 1902.120000 1160.300000 ;
+ RECT 1901.020000 1165.260000 1902.120000 1165.740000 ;
+ RECT 1901.020000 1170.700000 1902.120000 1171.180000 ;
+ RECT 1852.190000 1192.460000 1853.190000 1192.940000 ;
+ RECT 1855.855000 1192.460000 1857.120000 1192.940000 ;
+ RECT 1852.190000 1187.020000 1853.190000 1187.500000 ;
+ RECT 1855.855000 1187.020000 1857.120000 1187.500000 ;
+ RECT 1852.190000 1181.580000 1853.190000 1182.060000 ;
+ RECT 1855.855000 1181.580000 1857.120000 1182.060000 ;
+ RECT 1852.190000 1176.140000 1853.190000 1176.620000 ;
+ RECT 1855.855000 1176.140000 1857.120000 1176.620000 ;
+ RECT 1852.190000 1170.700000 1853.190000 1171.180000 ;
+ RECT 1855.855000 1170.700000 1857.120000 1171.180000 ;
+ RECT 1852.190000 1159.820000 1853.190000 1160.300000 ;
+ RECT 1855.855000 1159.820000 1857.120000 1160.300000 ;
+ RECT 1852.190000 1165.260000 1853.190000 1165.740000 ;
+ RECT 1855.855000 1165.260000 1857.120000 1165.740000 ;
+ RECT 1852.190000 1154.380000 1853.190000 1154.860000 ;
+ RECT 1855.855000 1154.380000 1857.120000 1154.860000 ;
+ RECT 1991.020000 1246.860000 1992.120000 1247.340000 ;
+ RECT 2036.020000 1246.860000 2037.120000 1247.340000 ;
+ RECT 2048.830000 1246.860000 2049.830000 1247.340000 ;
+ RECT 1901.020000 1246.860000 1902.120000 1247.340000 ;
+ RECT 1946.020000 1246.860000 1947.120000 1247.340000 ;
+ RECT 1852.190000 1246.860000 1853.190000 1247.340000 ;
+ RECT 1855.855000 1246.860000 1857.120000 1247.340000 ;
+ RECT 1850.960000 1343.620000 2051.060000 1344.620000 ;
+ RECT 1850.960000 1148.050000 2051.060000 1149.050000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 1146.800000 1853.190000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 1346.060000 1853.190000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 1146.800000 2049.830000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 1346.060000 2049.830000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1148.050000 1851.960000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1148.050000 2051.060000 1149.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1343.620000 1851.960000 1344.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1343.620000 2051.060000 1344.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 1139.080000 1857.120000 1139.560000 ;
+ RECT 1855.855000 1128.200000 1857.120000 1128.680000 ;
+ RECT 1855.855000 1133.640000 1857.120000 1134.120000 ;
+ RECT 1855.855000 1122.760000 1857.120000 1123.240000 ;
+ RECT 1855.855000 1117.320000 1857.120000 1117.800000 ;
+ RECT 1855.855000 1111.880000 1857.120000 1112.360000 ;
+ RECT 1855.855000 1106.440000 1857.120000 1106.920000 ;
+ RECT 1855.855000 1101.000000 1857.120000 1101.480000 ;
+ RECT 1855.855000 1095.560000 1857.120000 1096.040000 ;
+ RECT 1855.855000 1084.680000 1857.120000 1085.160000 ;
+ RECT 1855.855000 1090.120000 1857.120000 1090.600000 ;
+ RECT 1855.855000 1079.240000 1857.120000 1079.720000 ;
+ RECT 1855.855000 1073.800000 1857.120000 1074.280000 ;
+ RECT 1855.855000 1068.360000 1857.120000 1068.840000 ;
+ RECT 1855.855000 1062.920000 1857.120000 1063.400000 ;
+ RECT 1855.855000 1057.480000 1857.120000 1057.960000 ;
+ RECT 1855.855000 1052.040000 1857.120000 1052.520000 ;
+ RECT 1855.855000 1041.160000 1857.120000 1041.640000 ;
+ RECT 1855.855000 1035.720000 1857.120000 1036.200000 ;
+ RECT 1855.855000 1030.280000 1857.120000 1030.760000 ;
+ RECT 1855.855000 1024.840000 1857.120000 1025.320000 ;
+ RECT 1855.855000 1019.400000 1857.120000 1019.880000 ;
+ RECT 1855.855000 1013.960000 1857.120000 1014.440000 ;
+ RECT 1855.855000 1003.080000 1857.120000 1003.560000 ;
+ RECT 1855.855000 1008.520000 1857.120000 1009.000000 ;
+ RECT 1855.855000 997.640000 1857.120000 998.120000 ;
+ RECT 1855.855000 992.200000 1857.120000 992.680000 ;
+ RECT 1855.855000 986.760000 1857.120000 987.240000 ;
+ RECT 1855.855000 981.320000 1857.120000 981.800000 ;
+ RECT 1855.855000 975.880000 1857.120000 976.360000 ;
+ RECT 1855.855000 970.440000 1857.120000 970.920000 ;
+ RECT 1855.855000 959.560000 1857.120000 960.040000 ;
+ RECT 1855.855000 965.000000 1857.120000 965.480000 ;
+ RECT 1855.855000 954.120000 1857.120000 954.600000 ;
+ RECT 1855.855000 1046.600000 1857.120000 1047.080000 ;
+ RECT 2036.020000 947.790000 2037.120000 1144.360000 ;
+ RECT 1991.020000 947.790000 1992.120000 1144.360000 ;
+ RECT 2048.830000 946.540000 2049.830000 1146.800000 ;
+ RECT 1946.020000 947.790000 1947.120000 1144.360000 ;
+ RECT 1901.020000 947.790000 1902.120000 1144.360000 ;
+ RECT 1856.020000 947.790000 1857.120000 1144.360000 ;
+ RECT 1852.190000 946.540000 1853.190000 1146.800000 ;
+ LAYER met3 ;
+ RECT 2036.020000 1139.080000 2037.120000 1139.560000 ;
+ RECT 2048.830000 1139.080000 2049.830000 1139.560000 ;
+ RECT 2048.830000 1128.200000 2049.830000 1128.680000 ;
+ RECT 2048.830000 1122.760000 2049.830000 1123.240000 ;
+ RECT 2048.830000 1133.640000 2049.830000 1134.120000 ;
+ RECT 2036.020000 1133.640000 2037.120000 1134.120000 ;
+ RECT 2036.020000 1128.200000 2037.120000 1128.680000 ;
+ RECT 2036.020000 1122.760000 2037.120000 1123.240000 ;
+ RECT 2036.020000 1111.880000 2037.120000 1112.360000 ;
+ RECT 2036.020000 1117.320000 2037.120000 1117.800000 ;
+ RECT 2048.830000 1111.880000 2049.830000 1112.360000 ;
+ RECT 2048.830000 1117.320000 2049.830000 1117.800000 ;
+ RECT 2036.020000 1101.000000 2037.120000 1101.480000 ;
+ RECT 2036.020000 1106.440000 2037.120000 1106.920000 ;
+ RECT 2048.830000 1101.000000 2049.830000 1101.480000 ;
+ RECT 2048.830000 1106.440000 2049.830000 1106.920000 ;
+ RECT 1991.020000 1122.760000 1992.120000 1123.240000 ;
+ RECT 1991.020000 1128.200000 1992.120000 1128.680000 ;
+ RECT 1991.020000 1133.640000 1992.120000 1134.120000 ;
+ RECT 1991.020000 1139.080000 1992.120000 1139.560000 ;
+ RECT 1991.020000 1106.440000 1992.120000 1106.920000 ;
+ RECT 1991.020000 1101.000000 1992.120000 1101.480000 ;
+ RECT 1991.020000 1111.880000 1992.120000 1112.360000 ;
+ RECT 1991.020000 1117.320000 1992.120000 1117.800000 ;
+ RECT 2048.830000 1090.120000 2049.830000 1090.600000 ;
+ RECT 2048.830000 1084.680000 2049.830000 1085.160000 ;
+ RECT 2048.830000 1095.560000 2049.830000 1096.040000 ;
+ RECT 2036.020000 1095.560000 2037.120000 1096.040000 ;
+ RECT 2036.020000 1090.120000 2037.120000 1090.600000 ;
+ RECT 2036.020000 1084.680000 2037.120000 1085.160000 ;
+ RECT 2036.020000 1073.800000 2037.120000 1074.280000 ;
+ RECT 2036.020000 1079.240000 2037.120000 1079.720000 ;
+ RECT 2048.830000 1073.800000 2049.830000 1074.280000 ;
+ RECT 2048.830000 1079.240000 2049.830000 1079.720000 ;
+ RECT 2048.830000 1062.920000 2049.830000 1063.400000 ;
+ RECT 2048.830000 1068.360000 2049.830000 1068.840000 ;
+ RECT 2036.020000 1068.360000 2037.120000 1068.840000 ;
+ RECT 2036.020000 1062.920000 2037.120000 1063.400000 ;
+ RECT 2036.020000 1052.040000 2037.120000 1052.520000 ;
+ RECT 2036.020000 1057.480000 2037.120000 1057.960000 ;
+ RECT 2048.830000 1052.040000 2049.830000 1052.520000 ;
+ RECT 2048.830000 1057.480000 2049.830000 1057.960000 ;
+ RECT 1991.020000 1073.800000 1992.120000 1074.280000 ;
+ RECT 1991.020000 1079.240000 1992.120000 1079.720000 ;
+ RECT 1991.020000 1084.680000 1992.120000 1085.160000 ;
+ RECT 1991.020000 1090.120000 1992.120000 1090.600000 ;
+ RECT 1991.020000 1095.560000 1992.120000 1096.040000 ;
+ RECT 1991.020000 1052.040000 1992.120000 1052.520000 ;
+ RECT 1991.020000 1057.480000 1992.120000 1057.960000 ;
+ RECT 1991.020000 1062.920000 1992.120000 1063.400000 ;
+ RECT 1991.020000 1068.360000 1992.120000 1068.840000 ;
+ RECT 1946.020000 1128.200000 1947.120000 1128.680000 ;
+ RECT 1946.020000 1122.760000 1947.120000 1123.240000 ;
+ RECT 1946.020000 1133.640000 1947.120000 1134.120000 ;
+ RECT 1946.020000 1139.080000 1947.120000 1139.560000 ;
+ RECT 1901.020000 1122.760000 1902.120000 1123.240000 ;
+ RECT 1901.020000 1128.200000 1902.120000 1128.680000 ;
+ RECT 1901.020000 1133.640000 1902.120000 1134.120000 ;
+ RECT 1901.020000 1139.080000 1902.120000 1139.560000 ;
+ RECT 1946.020000 1101.000000 1947.120000 1101.480000 ;
+ RECT 1946.020000 1106.440000 1947.120000 1106.920000 ;
+ RECT 1946.020000 1111.880000 1947.120000 1112.360000 ;
+ RECT 1946.020000 1117.320000 1947.120000 1117.800000 ;
+ RECT 1901.020000 1101.000000 1902.120000 1101.480000 ;
+ RECT 1901.020000 1106.440000 1902.120000 1106.920000 ;
+ RECT 1901.020000 1111.880000 1902.120000 1112.360000 ;
+ RECT 1901.020000 1117.320000 1902.120000 1117.800000 ;
+ RECT 1852.190000 1139.080000 1853.190000 1139.560000 ;
+ RECT 1855.855000 1139.080000 1857.120000 1139.560000 ;
+ RECT 1852.190000 1128.200000 1853.190000 1128.680000 ;
+ RECT 1855.855000 1128.200000 1857.120000 1128.680000 ;
+ RECT 1852.190000 1133.640000 1853.190000 1134.120000 ;
+ RECT 1855.855000 1133.640000 1857.120000 1134.120000 ;
+ RECT 1852.190000 1122.760000 1853.190000 1123.240000 ;
+ RECT 1855.855000 1122.760000 1857.120000 1123.240000 ;
+ RECT 1852.190000 1117.320000 1853.190000 1117.800000 ;
+ RECT 1855.855000 1117.320000 1857.120000 1117.800000 ;
+ RECT 1852.190000 1111.880000 1853.190000 1112.360000 ;
+ RECT 1855.855000 1111.880000 1857.120000 1112.360000 ;
+ RECT 1852.190000 1106.440000 1853.190000 1106.920000 ;
+ RECT 1855.855000 1106.440000 1857.120000 1106.920000 ;
+ RECT 1852.190000 1101.000000 1853.190000 1101.480000 ;
+ RECT 1855.855000 1101.000000 1857.120000 1101.480000 ;
+ RECT 1946.020000 1073.800000 1947.120000 1074.280000 ;
+ RECT 1946.020000 1079.240000 1947.120000 1079.720000 ;
+ RECT 1946.020000 1084.680000 1947.120000 1085.160000 ;
+ RECT 1946.020000 1090.120000 1947.120000 1090.600000 ;
+ RECT 1946.020000 1095.560000 1947.120000 1096.040000 ;
+ RECT 1901.020000 1073.800000 1902.120000 1074.280000 ;
+ RECT 1901.020000 1079.240000 1902.120000 1079.720000 ;
+ RECT 1901.020000 1084.680000 1902.120000 1085.160000 ;
+ RECT 1901.020000 1090.120000 1902.120000 1090.600000 ;
+ RECT 1901.020000 1095.560000 1902.120000 1096.040000 ;
+ RECT 1946.020000 1052.040000 1947.120000 1052.520000 ;
+ RECT 1946.020000 1057.480000 1947.120000 1057.960000 ;
+ RECT 1946.020000 1062.920000 1947.120000 1063.400000 ;
+ RECT 1946.020000 1068.360000 1947.120000 1068.840000 ;
+ RECT 1901.020000 1052.040000 1902.120000 1052.520000 ;
+ RECT 1901.020000 1057.480000 1902.120000 1057.960000 ;
+ RECT 1901.020000 1062.920000 1902.120000 1063.400000 ;
+ RECT 1901.020000 1068.360000 1902.120000 1068.840000 ;
+ RECT 1852.190000 1095.560000 1853.190000 1096.040000 ;
+ RECT 1855.855000 1095.560000 1857.120000 1096.040000 ;
+ RECT 1852.190000 1084.680000 1853.190000 1085.160000 ;
+ RECT 1855.855000 1084.680000 1857.120000 1085.160000 ;
+ RECT 1852.190000 1090.120000 1853.190000 1090.600000 ;
+ RECT 1855.855000 1090.120000 1857.120000 1090.600000 ;
+ RECT 1852.190000 1079.240000 1853.190000 1079.720000 ;
+ RECT 1855.855000 1079.240000 1857.120000 1079.720000 ;
+ RECT 1852.190000 1073.800000 1853.190000 1074.280000 ;
+ RECT 1855.855000 1073.800000 1857.120000 1074.280000 ;
+ RECT 1852.190000 1068.360000 1853.190000 1068.840000 ;
+ RECT 1855.855000 1068.360000 1857.120000 1068.840000 ;
+ RECT 1852.190000 1062.920000 1853.190000 1063.400000 ;
+ RECT 1855.855000 1062.920000 1857.120000 1063.400000 ;
+ RECT 1852.190000 1057.480000 1853.190000 1057.960000 ;
+ RECT 1855.855000 1057.480000 1857.120000 1057.960000 ;
+ RECT 1852.190000 1052.040000 1853.190000 1052.520000 ;
+ RECT 1855.855000 1052.040000 1857.120000 1052.520000 ;
+ RECT 2036.020000 1035.720000 2037.120000 1036.200000 ;
+ RECT 2036.020000 1041.160000 2037.120000 1041.640000 ;
+ RECT 2048.830000 1035.720000 2049.830000 1036.200000 ;
+ RECT 2048.830000 1041.160000 2049.830000 1041.640000 ;
+ RECT 2048.830000 1024.840000 2049.830000 1025.320000 ;
+ RECT 2048.830000 1030.280000 2049.830000 1030.760000 ;
+ RECT 2036.020000 1030.280000 2037.120000 1030.760000 ;
+ RECT 2036.020000 1024.840000 2037.120000 1025.320000 ;
+ RECT 2036.020000 1013.960000 2037.120000 1014.440000 ;
+ RECT 2036.020000 1019.400000 2037.120000 1019.880000 ;
+ RECT 2048.830000 1013.960000 2049.830000 1014.440000 ;
+ RECT 2048.830000 1019.400000 2049.830000 1019.880000 ;
+ RECT 2048.830000 1003.080000 2049.830000 1003.560000 ;
+ RECT 2048.830000 997.640000 2049.830000 998.120000 ;
+ RECT 2048.830000 1008.520000 2049.830000 1009.000000 ;
+ RECT 2036.020000 1008.520000 2037.120000 1009.000000 ;
+ RECT 2036.020000 1003.080000 2037.120000 1003.560000 ;
+ RECT 2036.020000 997.640000 2037.120000 998.120000 ;
+ RECT 1991.020000 1024.840000 1992.120000 1025.320000 ;
+ RECT 1991.020000 1030.280000 1992.120000 1030.760000 ;
+ RECT 1991.020000 1035.720000 1992.120000 1036.200000 ;
+ RECT 1991.020000 1041.160000 1992.120000 1041.640000 ;
+ RECT 1991.020000 997.640000 1992.120000 998.120000 ;
+ RECT 1991.020000 1003.080000 1992.120000 1003.560000 ;
+ RECT 1991.020000 1008.520000 1992.120000 1009.000000 ;
+ RECT 1991.020000 1013.960000 1992.120000 1014.440000 ;
+ RECT 1991.020000 1019.400000 1992.120000 1019.880000 ;
+ RECT 2036.020000 986.760000 2037.120000 987.240000 ;
+ RECT 2036.020000 992.200000 2037.120000 992.680000 ;
+ RECT 2048.830000 986.760000 2049.830000 987.240000 ;
+ RECT 2048.830000 992.200000 2049.830000 992.680000 ;
+ RECT 2036.020000 975.880000 2037.120000 976.360000 ;
+ RECT 2036.020000 981.320000 2037.120000 981.800000 ;
+ RECT 2048.830000 975.880000 2049.830000 976.360000 ;
+ RECT 2048.830000 981.320000 2049.830000 981.800000 ;
+ RECT 2048.830000 965.000000 2049.830000 965.480000 ;
+ RECT 2048.830000 959.560000 2049.830000 960.040000 ;
+ RECT 2048.830000 970.440000 2049.830000 970.920000 ;
+ RECT 2036.020000 970.440000 2037.120000 970.920000 ;
+ RECT 2036.020000 965.000000 2037.120000 965.480000 ;
+ RECT 2036.020000 959.560000 2037.120000 960.040000 ;
+ RECT 2036.020000 954.120000 2037.120000 954.600000 ;
+ RECT 2048.830000 954.120000 2049.830000 954.600000 ;
+ RECT 1991.020000 975.880000 1992.120000 976.360000 ;
+ RECT 1991.020000 981.320000 1992.120000 981.800000 ;
+ RECT 1991.020000 986.760000 1992.120000 987.240000 ;
+ RECT 1991.020000 992.200000 1992.120000 992.680000 ;
+ RECT 1991.020000 954.120000 1992.120000 954.600000 ;
+ RECT 1991.020000 959.560000 1992.120000 960.040000 ;
+ RECT 1991.020000 965.000000 1992.120000 965.480000 ;
+ RECT 1991.020000 970.440000 1992.120000 970.920000 ;
+ RECT 1946.020000 1024.840000 1947.120000 1025.320000 ;
+ RECT 1946.020000 1030.280000 1947.120000 1030.760000 ;
+ RECT 1946.020000 1035.720000 1947.120000 1036.200000 ;
+ RECT 1946.020000 1041.160000 1947.120000 1041.640000 ;
+ RECT 1901.020000 1024.840000 1902.120000 1025.320000 ;
+ RECT 1901.020000 1030.280000 1902.120000 1030.760000 ;
+ RECT 1901.020000 1035.720000 1902.120000 1036.200000 ;
+ RECT 1901.020000 1041.160000 1902.120000 1041.640000 ;
+ RECT 1946.020000 997.640000 1947.120000 998.120000 ;
+ RECT 1946.020000 1003.080000 1947.120000 1003.560000 ;
+ RECT 1946.020000 1008.520000 1947.120000 1009.000000 ;
+ RECT 1946.020000 1013.960000 1947.120000 1014.440000 ;
+ RECT 1946.020000 1019.400000 1947.120000 1019.880000 ;
+ RECT 1901.020000 997.640000 1902.120000 998.120000 ;
+ RECT 1901.020000 1003.080000 1902.120000 1003.560000 ;
+ RECT 1901.020000 1008.520000 1902.120000 1009.000000 ;
+ RECT 1901.020000 1013.960000 1902.120000 1014.440000 ;
+ RECT 1901.020000 1019.400000 1902.120000 1019.880000 ;
+ RECT 1852.190000 1041.160000 1853.190000 1041.640000 ;
+ RECT 1855.855000 1041.160000 1857.120000 1041.640000 ;
+ RECT 1852.190000 1035.720000 1853.190000 1036.200000 ;
+ RECT 1855.855000 1035.720000 1857.120000 1036.200000 ;
+ RECT 1852.190000 1030.280000 1853.190000 1030.760000 ;
+ RECT 1855.855000 1030.280000 1857.120000 1030.760000 ;
+ RECT 1852.190000 1024.840000 1853.190000 1025.320000 ;
+ RECT 1855.855000 1024.840000 1857.120000 1025.320000 ;
+ RECT 1852.190000 1019.400000 1853.190000 1019.880000 ;
+ RECT 1855.855000 1019.400000 1857.120000 1019.880000 ;
+ RECT 1852.190000 1013.960000 1853.190000 1014.440000 ;
+ RECT 1855.855000 1013.960000 1857.120000 1014.440000 ;
+ RECT 1852.190000 1003.080000 1853.190000 1003.560000 ;
+ RECT 1855.855000 1003.080000 1857.120000 1003.560000 ;
+ RECT 1852.190000 1008.520000 1853.190000 1009.000000 ;
+ RECT 1855.855000 1008.520000 1857.120000 1009.000000 ;
+ RECT 1852.190000 997.640000 1853.190000 998.120000 ;
+ RECT 1855.855000 997.640000 1857.120000 998.120000 ;
+ RECT 1946.020000 975.880000 1947.120000 976.360000 ;
+ RECT 1946.020000 981.320000 1947.120000 981.800000 ;
+ RECT 1946.020000 986.760000 1947.120000 987.240000 ;
+ RECT 1946.020000 992.200000 1947.120000 992.680000 ;
+ RECT 1901.020000 975.880000 1902.120000 976.360000 ;
+ RECT 1901.020000 981.320000 1902.120000 981.800000 ;
+ RECT 1901.020000 986.760000 1902.120000 987.240000 ;
+ RECT 1901.020000 992.200000 1902.120000 992.680000 ;
+ RECT 1946.020000 954.120000 1947.120000 954.600000 ;
+ RECT 1946.020000 959.560000 1947.120000 960.040000 ;
+ RECT 1946.020000 965.000000 1947.120000 965.480000 ;
+ RECT 1946.020000 970.440000 1947.120000 970.920000 ;
+ RECT 1901.020000 954.120000 1902.120000 954.600000 ;
+ RECT 1901.020000 959.560000 1902.120000 960.040000 ;
+ RECT 1901.020000 965.000000 1902.120000 965.480000 ;
+ RECT 1901.020000 970.440000 1902.120000 970.920000 ;
+ RECT 1852.190000 992.200000 1853.190000 992.680000 ;
+ RECT 1855.855000 992.200000 1857.120000 992.680000 ;
+ RECT 1852.190000 986.760000 1853.190000 987.240000 ;
+ RECT 1855.855000 986.760000 1857.120000 987.240000 ;
+ RECT 1852.190000 981.320000 1853.190000 981.800000 ;
+ RECT 1855.855000 981.320000 1857.120000 981.800000 ;
+ RECT 1852.190000 975.880000 1853.190000 976.360000 ;
+ RECT 1855.855000 975.880000 1857.120000 976.360000 ;
+ RECT 1852.190000 970.440000 1853.190000 970.920000 ;
+ RECT 1855.855000 970.440000 1857.120000 970.920000 ;
+ RECT 1852.190000 959.560000 1853.190000 960.040000 ;
+ RECT 1855.855000 959.560000 1857.120000 960.040000 ;
+ RECT 1852.190000 965.000000 1853.190000 965.480000 ;
+ RECT 1855.855000 965.000000 1857.120000 965.480000 ;
+ RECT 1852.190000 954.120000 1853.190000 954.600000 ;
+ RECT 1855.855000 954.120000 1857.120000 954.600000 ;
+ RECT 1991.020000 1046.600000 1992.120000 1047.080000 ;
+ RECT 2036.020000 1046.600000 2037.120000 1047.080000 ;
+ RECT 2048.830000 1046.600000 2049.830000 1047.080000 ;
+ RECT 1901.020000 1046.600000 1902.120000 1047.080000 ;
+ RECT 1946.020000 1046.600000 1947.120000 1047.080000 ;
+ RECT 1852.190000 1046.600000 1853.190000 1047.080000 ;
+ RECT 1855.855000 1046.600000 1857.120000 1047.080000 ;
+ RECT 1850.960000 1143.360000 2051.060000 1144.360000 ;
+ RECT 1850.960000 947.790000 2051.060000 948.790000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 946.540000 1853.190000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 1145.800000 1853.190000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 946.540000 2049.830000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 1145.800000 2049.830000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 947.790000 1851.960000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 947.790000 2051.060000 948.790000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1143.360000 1851.960000 1144.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1143.360000 2051.060000 1144.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 938.820000 1857.120000 939.300000 ;
+ RECT 1855.855000 927.940000 1857.120000 928.420000 ;
+ RECT 1855.855000 933.380000 1857.120000 933.860000 ;
+ RECT 1855.855000 922.500000 1857.120000 922.980000 ;
+ RECT 1855.855000 917.060000 1857.120000 917.540000 ;
+ RECT 1855.855000 911.620000 1857.120000 912.100000 ;
+ RECT 1855.855000 906.180000 1857.120000 906.660000 ;
+ RECT 1855.855000 900.740000 1857.120000 901.220000 ;
+ RECT 1855.855000 895.300000 1857.120000 895.780000 ;
+ RECT 1855.855000 884.420000 1857.120000 884.900000 ;
+ RECT 1855.855000 889.860000 1857.120000 890.340000 ;
+ RECT 1855.855000 878.980000 1857.120000 879.460000 ;
+ RECT 1855.855000 873.540000 1857.120000 874.020000 ;
+ RECT 1855.855000 868.100000 1857.120000 868.580000 ;
+ RECT 1855.855000 862.660000 1857.120000 863.140000 ;
+ RECT 1855.855000 857.220000 1857.120000 857.700000 ;
+ RECT 1855.855000 851.780000 1857.120000 852.260000 ;
+ RECT 1855.855000 840.900000 1857.120000 841.380000 ;
+ RECT 1855.855000 835.460000 1857.120000 835.940000 ;
+ RECT 1855.855000 830.020000 1857.120000 830.500000 ;
+ RECT 1855.855000 824.580000 1857.120000 825.060000 ;
+ RECT 1855.855000 819.140000 1857.120000 819.620000 ;
+ RECT 1855.855000 813.700000 1857.120000 814.180000 ;
+ RECT 1855.855000 802.820000 1857.120000 803.300000 ;
+ RECT 1855.855000 808.260000 1857.120000 808.740000 ;
+ RECT 1855.855000 797.380000 1857.120000 797.860000 ;
+ RECT 1855.855000 791.940000 1857.120000 792.420000 ;
+ RECT 1855.855000 786.500000 1857.120000 786.980000 ;
+ RECT 1855.855000 781.060000 1857.120000 781.540000 ;
+ RECT 1855.855000 775.620000 1857.120000 776.100000 ;
+ RECT 1855.855000 770.180000 1857.120000 770.660000 ;
+ RECT 1855.855000 759.300000 1857.120000 759.780000 ;
+ RECT 1855.855000 764.740000 1857.120000 765.220000 ;
+ RECT 1855.855000 753.860000 1857.120000 754.340000 ;
+ RECT 1855.855000 846.340000 1857.120000 846.820000 ;
+ RECT 2036.020000 747.530000 2037.120000 944.100000 ;
+ RECT 1991.020000 747.530000 1992.120000 944.100000 ;
+ RECT 2048.830000 746.280000 2049.830000 946.540000 ;
+ RECT 1946.020000 747.530000 1947.120000 944.100000 ;
+ RECT 1901.020000 747.530000 1902.120000 944.100000 ;
+ RECT 1856.020000 747.530000 1857.120000 944.100000 ;
+ RECT 1852.190000 746.280000 1853.190000 946.540000 ;
+ LAYER met3 ;
+ RECT 2036.020000 938.820000 2037.120000 939.300000 ;
+ RECT 2048.830000 938.820000 2049.830000 939.300000 ;
+ RECT 2048.830000 927.940000 2049.830000 928.420000 ;
+ RECT 2048.830000 922.500000 2049.830000 922.980000 ;
+ RECT 2048.830000 933.380000 2049.830000 933.860000 ;
+ RECT 2036.020000 933.380000 2037.120000 933.860000 ;
+ RECT 2036.020000 927.940000 2037.120000 928.420000 ;
+ RECT 2036.020000 922.500000 2037.120000 922.980000 ;
+ RECT 2036.020000 911.620000 2037.120000 912.100000 ;
+ RECT 2036.020000 917.060000 2037.120000 917.540000 ;
+ RECT 2048.830000 911.620000 2049.830000 912.100000 ;
+ RECT 2048.830000 917.060000 2049.830000 917.540000 ;
+ RECT 2036.020000 900.740000 2037.120000 901.220000 ;
+ RECT 2036.020000 906.180000 2037.120000 906.660000 ;
+ RECT 2048.830000 900.740000 2049.830000 901.220000 ;
+ RECT 2048.830000 906.180000 2049.830000 906.660000 ;
+ RECT 1991.020000 922.500000 1992.120000 922.980000 ;
+ RECT 1991.020000 927.940000 1992.120000 928.420000 ;
+ RECT 1991.020000 933.380000 1992.120000 933.860000 ;
+ RECT 1991.020000 938.820000 1992.120000 939.300000 ;
+ RECT 1991.020000 906.180000 1992.120000 906.660000 ;
+ RECT 1991.020000 900.740000 1992.120000 901.220000 ;
+ RECT 1991.020000 911.620000 1992.120000 912.100000 ;
+ RECT 1991.020000 917.060000 1992.120000 917.540000 ;
+ RECT 2048.830000 889.860000 2049.830000 890.340000 ;
+ RECT 2048.830000 884.420000 2049.830000 884.900000 ;
+ RECT 2048.830000 895.300000 2049.830000 895.780000 ;
+ RECT 2036.020000 895.300000 2037.120000 895.780000 ;
+ RECT 2036.020000 889.860000 2037.120000 890.340000 ;
+ RECT 2036.020000 884.420000 2037.120000 884.900000 ;
+ RECT 2036.020000 873.540000 2037.120000 874.020000 ;
+ RECT 2036.020000 878.980000 2037.120000 879.460000 ;
+ RECT 2048.830000 873.540000 2049.830000 874.020000 ;
+ RECT 2048.830000 878.980000 2049.830000 879.460000 ;
+ RECT 2048.830000 862.660000 2049.830000 863.140000 ;
+ RECT 2048.830000 868.100000 2049.830000 868.580000 ;
+ RECT 2036.020000 868.100000 2037.120000 868.580000 ;
+ RECT 2036.020000 862.660000 2037.120000 863.140000 ;
+ RECT 2036.020000 851.780000 2037.120000 852.260000 ;
+ RECT 2036.020000 857.220000 2037.120000 857.700000 ;
+ RECT 2048.830000 851.780000 2049.830000 852.260000 ;
+ RECT 2048.830000 857.220000 2049.830000 857.700000 ;
+ RECT 1991.020000 873.540000 1992.120000 874.020000 ;
+ RECT 1991.020000 878.980000 1992.120000 879.460000 ;
+ RECT 1991.020000 884.420000 1992.120000 884.900000 ;
+ RECT 1991.020000 889.860000 1992.120000 890.340000 ;
+ RECT 1991.020000 895.300000 1992.120000 895.780000 ;
+ RECT 1991.020000 851.780000 1992.120000 852.260000 ;
+ RECT 1991.020000 857.220000 1992.120000 857.700000 ;
+ RECT 1991.020000 862.660000 1992.120000 863.140000 ;
+ RECT 1991.020000 868.100000 1992.120000 868.580000 ;
+ RECT 1946.020000 927.940000 1947.120000 928.420000 ;
+ RECT 1946.020000 922.500000 1947.120000 922.980000 ;
+ RECT 1946.020000 933.380000 1947.120000 933.860000 ;
+ RECT 1946.020000 938.820000 1947.120000 939.300000 ;
+ RECT 1901.020000 922.500000 1902.120000 922.980000 ;
+ RECT 1901.020000 927.940000 1902.120000 928.420000 ;
+ RECT 1901.020000 933.380000 1902.120000 933.860000 ;
+ RECT 1901.020000 938.820000 1902.120000 939.300000 ;
+ RECT 1946.020000 900.740000 1947.120000 901.220000 ;
+ RECT 1946.020000 906.180000 1947.120000 906.660000 ;
+ RECT 1946.020000 911.620000 1947.120000 912.100000 ;
+ RECT 1946.020000 917.060000 1947.120000 917.540000 ;
+ RECT 1901.020000 900.740000 1902.120000 901.220000 ;
+ RECT 1901.020000 906.180000 1902.120000 906.660000 ;
+ RECT 1901.020000 911.620000 1902.120000 912.100000 ;
+ RECT 1901.020000 917.060000 1902.120000 917.540000 ;
+ RECT 1852.190000 938.820000 1853.190000 939.300000 ;
+ RECT 1855.855000 938.820000 1857.120000 939.300000 ;
+ RECT 1852.190000 927.940000 1853.190000 928.420000 ;
+ RECT 1855.855000 927.940000 1857.120000 928.420000 ;
+ RECT 1852.190000 933.380000 1853.190000 933.860000 ;
+ RECT 1855.855000 933.380000 1857.120000 933.860000 ;
+ RECT 1852.190000 922.500000 1853.190000 922.980000 ;
+ RECT 1855.855000 922.500000 1857.120000 922.980000 ;
+ RECT 1852.190000 917.060000 1853.190000 917.540000 ;
+ RECT 1855.855000 917.060000 1857.120000 917.540000 ;
+ RECT 1852.190000 911.620000 1853.190000 912.100000 ;
+ RECT 1855.855000 911.620000 1857.120000 912.100000 ;
+ RECT 1852.190000 906.180000 1853.190000 906.660000 ;
+ RECT 1855.855000 906.180000 1857.120000 906.660000 ;
+ RECT 1852.190000 900.740000 1853.190000 901.220000 ;
+ RECT 1855.855000 900.740000 1857.120000 901.220000 ;
+ RECT 1946.020000 873.540000 1947.120000 874.020000 ;
+ RECT 1946.020000 878.980000 1947.120000 879.460000 ;
+ RECT 1946.020000 884.420000 1947.120000 884.900000 ;
+ RECT 1946.020000 889.860000 1947.120000 890.340000 ;
+ RECT 1946.020000 895.300000 1947.120000 895.780000 ;
+ RECT 1901.020000 873.540000 1902.120000 874.020000 ;
+ RECT 1901.020000 878.980000 1902.120000 879.460000 ;
+ RECT 1901.020000 884.420000 1902.120000 884.900000 ;
+ RECT 1901.020000 889.860000 1902.120000 890.340000 ;
+ RECT 1901.020000 895.300000 1902.120000 895.780000 ;
+ RECT 1946.020000 851.780000 1947.120000 852.260000 ;
+ RECT 1946.020000 857.220000 1947.120000 857.700000 ;
+ RECT 1946.020000 862.660000 1947.120000 863.140000 ;
+ RECT 1946.020000 868.100000 1947.120000 868.580000 ;
+ RECT 1901.020000 851.780000 1902.120000 852.260000 ;
+ RECT 1901.020000 857.220000 1902.120000 857.700000 ;
+ RECT 1901.020000 862.660000 1902.120000 863.140000 ;
+ RECT 1901.020000 868.100000 1902.120000 868.580000 ;
+ RECT 1852.190000 895.300000 1853.190000 895.780000 ;
+ RECT 1855.855000 895.300000 1857.120000 895.780000 ;
+ RECT 1852.190000 884.420000 1853.190000 884.900000 ;
+ RECT 1855.855000 884.420000 1857.120000 884.900000 ;
+ RECT 1852.190000 889.860000 1853.190000 890.340000 ;
+ RECT 1855.855000 889.860000 1857.120000 890.340000 ;
+ RECT 1852.190000 878.980000 1853.190000 879.460000 ;
+ RECT 1855.855000 878.980000 1857.120000 879.460000 ;
+ RECT 1852.190000 873.540000 1853.190000 874.020000 ;
+ RECT 1855.855000 873.540000 1857.120000 874.020000 ;
+ RECT 1852.190000 868.100000 1853.190000 868.580000 ;
+ RECT 1855.855000 868.100000 1857.120000 868.580000 ;
+ RECT 1852.190000 862.660000 1853.190000 863.140000 ;
+ RECT 1855.855000 862.660000 1857.120000 863.140000 ;
+ RECT 1852.190000 857.220000 1853.190000 857.700000 ;
+ RECT 1855.855000 857.220000 1857.120000 857.700000 ;
+ RECT 1852.190000 851.780000 1853.190000 852.260000 ;
+ RECT 1855.855000 851.780000 1857.120000 852.260000 ;
+ RECT 2036.020000 835.460000 2037.120000 835.940000 ;
+ RECT 2036.020000 840.900000 2037.120000 841.380000 ;
+ RECT 2048.830000 835.460000 2049.830000 835.940000 ;
+ RECT 2048.830000 840.900000 2049.830000 841.380000 ;
+ RECT 2048.830000 824.580000 2049.830000 825.060000 ;
+ RECT 2048.830000 830.020000 2049.830000 830.500000 ;
+ RECT 2036.020000 830.020000 2037.120000 830.500000 ;
+ RECT 2036.020000 824.580000 2037.120000 825.060000 ;
+ RECT 2036.020000 813.700000 2037.120000 814.180000 ;
+ RECT 2036.020000 819.140000 2037.120000 819.620000 ;
+ RECT 2048.830000 813.700000 2049.830000 814.180000 ;
+ RECT 2048.830000 819.140000 2049.830000 819.620000 ;
+ RECT 2048.830000 802.820000 2049.830000 803.300000 ;
+ RECT 2048.830000 797.380000 2049.830000 797.860000 ;
+ RECT 2048.830000 808.260000 2049.830000 808.740000 ;
+ RECT 2036.020000 808.260000 2037.120000 808.740000 ;
+ RECT 2036.020000 802.820000 2037.120000 803.300000 ;
+ RECT 2036.020000 797.380000 2037.120000 797.860000 ;
+ RECT 1991.020000 824.580000 1992.120000 825.060000 ;
+ RECT 1991.020000 830.020000 1992.120000 830.500000 ;
+ RECT 1991.020000 835.460000 1992.120000 835.940000 ;
+ RECT 1991.020000 840.900000 1992.120000 841.380000 ;
+ RECT 1991.020000 797.380000 1992.120000 797.860000 ;
+ RECT 1991.020000 802.820000 1992.120000 803.300000 ;
+ RECT 1991.020000 808.260000 1992.120000 808.740000 ;
+ RECT 1991.020000 813.700000 1992.120000 814.180000 ;
+ RECT 1991.020000 819.140000 1992.120000 819.620000 ;
+ RECT 2036.020000 786.500000 2037.120000 786.980000 ;
+ RECT 2036.020000 791.940000 2037.120000 792.420000 ;
+ RECT 2048.830000 786.500000 2049.830000 786.980000 ;
+ RECT 2048.830000 791.940000 2049.830000 792.420000 ;
+ RECT 2036.020000 775.620000 2037.120000 776.100000 ;
+ RECT 2036.020000 781.060000 2037.120000 781.540000 ;
+ RECT 2048.830000 775.620000 2049.830000 776.100000 ;
+ RECT 2048.830000 781.060000 2049.830000 781.540000 ;
+ RECT 2048.830000 764.740000 2049.830000 765.220000 ;
+ RECT 2048.830000 759.300000 2049.830000 759.780000 ;
+ RECT 2048.830000 770.180000 2049.830000 770.660000 ;
+ RECT 2036.020000 770.180000 2037.120000 770.660000 ;
+ RECT 2036.020000 764.740000 2037.120000 765.220000 ;
+ RECT 2036.020000 759.300000 2037.120000 759.780000 ;
+ RECT 2036.020000 753.860000 2037.120000 754.340000 ;
+ RECT 2048.830000 753.860000 2049.830000 754.340000 ;
+ RECT 1991.020000 775.620000 1992.120000 776.100000 ;
+ RECT 1991.020000 781.060000 1992.120000 781.540000 ;
+ RECT 1991.020000 786.500000 1992.120000 786.980000 ;
+ RECT 1991.020000 791.940000 1992.120000 792.420000 ;
+ RECT 1991.020000 753.860000 1992.120000 754.340000 ;
+ RECT 1991.020000 759.300000 1992.120000 759.780000 ;
+ RECT 1991.020000 764.740000 1992.120000 765.220000 ;
+ RECT 1991.020000 770.180000 1992.120000 770.660000 ;
+ RECT 1946.020000 824.580000 1947.120000 825.060000 ;
+ RECT 1946.020000 830.020000 1947.120000 830.500000 ;
+ RECT 1946.020000 835.460000 1947.120000 835.940000 ;
+ RECT 1946.020000 840.900000 1947.120000 841.380000 ;
+ RECT 1901.020000 824.580000 1902.120000 825.060000 ;
+ RECT 1901.020000 830.020000 1902.120000 830.500000 ;
+ RECT 1901.020000 835.460000 1902.120000 835.940000 ;
+ RECT 1901.020000 840.900000 1902.120000 841.380000 ;
+ RECT 1946.020000 797.380000 1947.120000 797.860000 ;
+ RECT 1946.020000 802.820000 1947.120000 803.300000 ;
+ RECT 1946.020000 808.260000 1947.120000 808.740000 ;
+ RECT 1946.020000 813.700000 1947.120000 814.180000 ;
+ RECT 1946.020000 819.140000 1947.120000 819.620000 ;
+ RECT 1901.020000 797.380000 1902.120000 797.860000 ;
+ RECT 1901.020000 802.820000 1902.120000 803.300000 ;
+ RECT 1901.020000 808.260000 1902.120000 808.740000 ;
+ RECT 1901.020000 813.700000 1902.120000 814.180000 ;
+ RECT 1901.020000 819.140000 1902.120000 819.620000 ;
+ RECT 1852.190000 840.900000 1853.190000 841.380000 ;
+ RECT 1855.855000 840.900000 1857.120000 841.380000 ;
+ RECT 1852.190000 835.460000 1853.190000 835.940000 ;
+ RECT 1855.855000 835.460000 1857.120000 835.940000 ;
+ RECT 1852.190000 830.020000 1853.190000 830.500000 ;
+ RECT 1855.855000 830.020000 1857.120000 830.500000 ;
+ RECT 1852.190000 824.580000 1853.190000 825.060000 ;
+ RECT 1855.855000 824.580000 1857.120000 825.060000 ;
+ RECT 1852.190000 819.140000 1853.190000 819.620000 ;
+ RECT 1855.855000 819.140000 1857.120000 819.620000 ;
+ RECT 1852.190000 813.700000 1853.190000 814.180000 ;
+ RECT 1855.855000 813.700000 1857.120000 814.180000 ;
+ RECT 1852.190000 802.820000 1853.190000 803.300000 ;
+ RECT 1855.855000 802.820000 1857.120000 803.300000 ;
+ RECT 1852.190000 808.260000 1853.190000 808.740000 ;
+ RECT 1855.855000 808.260000 1857.120000 808.740000 ;
+ RECT 1852.190000 797.380000 1853.190000 797.860000 ;
+ RECT 1855.855000 797.380000 1857.120000 797.860000 ;
+ RECT 1946.020000 775.620000 1947.120000 776.100000 ;
+ RECT 1946.020000 781.060000 1947.120000 781.540000 ;
+ RECT 1946.020000 786.500000 1947.120000 786.980000 ;
+ RECT 1946.020000 791.940000 1947.120000 792.420000 ;
+ RECT 1901.020000 775.620000 1902.120000 776.100000 ;
+ RECT 1901.020000 781.060000 1902.120000 781.540000 ;
+ RECT 1901.020000 786.500000 1902.120000 786.980000 ;
+ RECT 1901.020000 791.940000 1902.120000 792.420000 ;
+ RECT 1946.020000 753.860000 1947.120000 754.340000 ;
+ RECT 1946.020000 759.300000 1947.120000 759.780000 ;
+ RECT 1946.020000 764.740000 1947.120000 765.220000 ;
+ RECT 1946.020000 770.180000 1947.120000 770.660000 ;
+ RECT 1901.020000 753.860000 1902.120000 754.340000 ;
+ RECT 1901.020000 759.300000 1902.120000 759.780000 ;
+ RECT 1901.020000 764.740000 1902.120000 765.220000 ;
+ RECT 1901.020000 770.180000 1902.120000 770.660000 ;
+ RECT 1852.190000 791.940000 1853.190000 792.420000 ;
+ RECT 1855.855000 791.940000 1857.120000 792.420000 ;
+ RECT 1852.190000 786.500000 1853.190000 786.980000 ;
+ RECT 1855.855000 786.500000 1857.120000 786.980000 ;
+ RECT 1852.190000 781.060000 1853.190000 781.540000 ;
+ RECT 1855.855000 781.060000 1857.120000 781.540000 ;
+ RECT 1852.190000 775.620000 1853.190000 776.100000 ;
+ RECT 1855.855000 775.620000 1857.120000 776.100000 ;
+ RECT 1852.190000 770.180000 1853.190000 770.660000 ;
+ RECT 1855.855000 770.180000 1857.120000 770.660000 ;
+ RECT 1852.190000 759.300000 1853.190000 759.780000 ;
+ RECT 1855.855000 759.300000 1857.120000 759.780000 ;
+ RECT 1852.190000 764.740000 1853.190000 765.220000 ;
+ RECT 1855.855000 764.740000 1857.120000 765.220000 ;
+ RECT 1852.190000 753.860000 1853.190000 754.340000 ;
+ RECT 1855.855000 753.860000 1857.120000 754.340000 ;
+ RECT 1991.020000 846.340000 1992.120000 846.820000 ;
+ RECT 2036.020000 846.340000 2037.120000 846.820000 ;
+ RECT 2048.830000 846.340000 2049.830000 846.820000 ;
+ RECT 1901.020000 846.340000 1902.120000 846.820000 ;
+ RECT 1946.020000 846.340000 1947.120000 846.820000 ;
+ RECT 1852.190000 846.340000 1853.190000 846.820000 ;
+ RECT 1855.855000 846.340000 1857.120000 846.820000 ;
+ RECT 1850.960000 943.100000 2051.060000 944.100000 ;
+ RECT 1850.960000 747.530000 2051.060000 748.530000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 746.280000 1853.190000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 945.540000 1853.190000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 746.280000 2049.830000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 945.540000 2049.830000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 747.530000 1851.960000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 747.530000 2051.060000 748.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 943.100000 1851.960000 944.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 943.100000 2051.060000 944.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 738.560000 1857.120000 739.040000 ;
+ RECT 1855.855000 727.680000 1857.120000 728.160000 ;
+ RECT 1855.855000 733.120000 1857.120000 733.600000 ;
+ RECT 1855.855000 722.240000 1857.120000 722.720000 ;
+ RECT 1855.855000 716.800000 1857.120000 717.280000 ;
+ RECT 1855.855000 711.360000 1857.120000 711.840000 ;
+ RECT 1855.855000 705.920000 1857.120000 706.400000 ;
+ RECT 1855.855000 700.480000 1857.120000 700.960000 ;
+ RECT 1855.855000 695.040000 1857.120000 695.520000 ;
+ RECT 1855.855000 684.160000 1857.120000 684.640000 ;
+ RECT 1855.855000 689.600000 1857.120000 690.080000 ;
+ RECT 1855.855000 678.720000 1857.120000 679.200000 ;
+ RECT 1855.855000 673.280000 1857.120000 673.760000 ;
+ RECT 1855.855000 667.840000 1857.120000 668.320000 ;
+ RECT 1855.855000 662.400000 1857.120000 662.880000 ;
+ RECT 1855.855000 656.960000 1857.120000 657.440000 ;
+ RECT 1855.855000 651.520000 1857.120000 652.000000 ;
+ RECT 1855.855000 640.640000 1857.120000 641.120000 ;
+ RECT 1855.855000 635.200000 1857.120000 635.680000 ;
+ RECT 1855.855000 629.760000 1857.120000 630.240000 ;
+ RECT 1855.855000 624.320000 1857.120000 624.800000 ;
+ RECT 1855.855000 618.880000 1857.120000 619.360000 ;
+ RECT 1855.855000 613.440000 1857.120000 613.920000 ;
+ RECT 1855.855000 602.560000 1857.120000 603.040000 ;
+ RECT 1855.855000 608.000000 1857.120000 608.480000 ;
+ RECT 1855.855000 597.120000 1857.120000 597.600000 ;
+ RECT 1855.855000 591.680000 1857.120000 592.160000 ;
+ RECT 1855.855000 586.240000 1857.120000 586.720000 ;
+ RECT 1855.855000 580.800000 1857.120000 581.280000 ;
+ RECT 1855.855000 575.360000 1857.120000 575.840000 ;
+ RECT 1855.855000 569.920000 1857.120000 570.400000 ;
+ RECT 1855.855000 559.040000 1857.120000 559.520000 ;
+ RECT 1855.855000 564.480000 1857.120000 564.960000 ;
+ RECT 1855.855000 553.600000 1857.120000 554.080000 ;
+ RECT 1855.855000 646.080000 1857.120000 646.560000 ;
+ RECT 2036.020000 547.270000 2037.120000 743.840000 ;
+ RECT 1991.020000 547.270000 1992.120000 743.840000 ;
+ RECT 2048.830000 546.020000 2049.830000 746.280000 ;
+ RECT 1946.020000 547.270000 1947.120000 743.840000 ;
+ RECT 1901.020000 547.270000 1902.120000 743.840000 ;
+ RECT 1856.020000 547.270000 1857.120000 743.840000 ;
+ RECT 1852.190000 546.020000 1853.190000 746.280000 ;
+ LAYER met3 ;
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+ RECT 2048.830000 738.560000 2049.830000 739.040000 ;
+ RECT 2048.830000 727.680000 2049.830000 728.160000 ;
+ RECT 2048.830000 722.240000 2049.830000 722.720000 ;
+ RECT 2048.830000 733.120000 2049.830000 733.600000 ;
+ RECT 2036.020000 733.120000 2037.120000 733.600000 ;
+ RECT 2036.020000 727.680000 2037.120000 728.160000 ;
+ RECT 2036.020000 722.240000 2037.120000 722.720000 ;
+ RECT 2036.020000 711.360000 2037.120000 711.840000 ;
+ RECT 2036.020000 716.800000 2037.120000 717.280000 ;
+ RECT 2048.830000 711.360000 2049.830000 711.840000 ;
+ RECT 2048.830000 716.800000 2049.830000 717.280000 ;
+ RECT 2036.020000 700.480000 2037.120000 700.960000 ;
+ RECT 2036.020000 705.920000 2037.120000 706.400000 ;
+ RECT 2048.830000 700.480000 2049.830000 700.960000 ;
+ RECT 2048.830000 705.920000 2049.830000 706.400000 ;
+ RECT 1991.020000 722.240000 1992.120000 722.720000 ;
+ RECT 1991.020000 727.680000 1992.120000 728.160000 ;
+ RECT 1991.020000 733.120000 1992.120000 733.600000 ;
+ RECT 1991.020000 738.560000 1992.120000 739.040000 ;
+ RECT 1991.020000 705.920000 1992.120000 706.400000 ;
+ RECT 1991.020000 700.480000 1992.120000 700.960000 ;
+ RECT 1991.020000 711.360000 1992.120000 711.840000 ;
+ RECT 1991.020000 716.800000 1992.120000 717.280000 ;
+ RECT 2048.830000 689.600000 2049.830000 690.080000 ;
+ RECT 2048.830000 684.160000 2049.830000 684.640000 ;
+ RECT 2048.830000 695.040000 2049.830000 695.520000 ;
+ RECT 2036.020000 695.040000 2037.120000 695.520000 ;
+ RECT 2036.020000 689.600000 2037.120000 690.080000 ;
+ RECT 2036.020000 684.160000 2037.120000 684.640000 ;
+ RECT 2036.020000 673.280000 2037.120000 673.760000 ;
+ RECT 2036.020000 678.720000 2037.120000 679.200000 ;
+ RECT 2048.830000 673.280000 2049.830000 673.760000 ;
+ RECT 2048.830000 678.720000 2049.830000 679.200000 ;
+ RECT 2048.830000 662.400000 2049.830000 662.880000 ;
+ RECT 2048.830000 667.840000 2049.830000 668.320000 ;
+ RECT 2036.020000 667.840000 2037.120000 668.320000 ;
+ RECT 2036.020000 662.400000 2037.120000 662.880000 ;
+ RECT 2036.020000 651.520000 2037.120000 652.000000 ;
+ RECT 2036.020000 656.960000 2037.120000 657.440000 ;
+ RECT 2048.830000 651.520000 2049.830000 652.000000 ;
+ RECT 2048.830000 656.960000 2049.830000 657.440000 ;
+ RECT 1991.020000 673.280000 1992.120000 673.760000 ;
+ RECT 1991.020000 678.720000 1992.120000 679.200000 ;
+ RECT 1991.020000 684.160000 1992.120000 684.640000 ;
+ RECT 1991.020000 689.600000 1992.120000 690.080000 ;
+ RECT 1991.020000 695.040000 1992.120000 695.520000 ;
+ RECT 1991.020000 651.520000 1992.120000 652.000000 ;
+ RECT 1991.020000 656.960000 1992.120000 657.440000 ;
+ RECT 1991.020000 662.400000 1992.120000 662.880000 ;
+ RECT 1991.020000 667.840000 1992.120000 668.320000 ;
+ RECT 1946.020000 727.680000 1947.120000 728.160000 ;
+ RECT 1946.020000 722.240000 1947.120000 722.720000 ;
+ RECT 1946.020000 733.120000 1947.120000 733.600000 ;
+ RECT 1946.020000 738.560000 1947.120000 739.040000 ;
+ RECT 1901.020000 722.240000 1902.120000 722.720000 ;
+ RECT 1901.020000 727.680000 1902.120000 728.160000 ;
+ RECT 1901.020000 733.120000 1902.120000 733.600000 ;
+ RECT 1901.020000 738.560000 1902.120000 739.040000 ;
+ RECT 1946.020000 700.480000 1947.120000 700.960000 ;
+ RECT 1946.020000 705.920000 1947.120000 706.400000 ;
+ RECT 1946.020000 711.360000 1947.120000 711.840000 ;
+ RECT 1946.020000 716.800000 1947.120000 717.280000 ;
+ RECT 1901.020000 700.480000 1902.120000 700.960000 ;
+ RECT 1901.020000 705.920000 1902.120000 706.400000 ;
+ RECT 1901.020000 711.360000 1902.120000 711.840000 ;
+ RECT 1901.020000 716.800000 1902.120000 717.280000 ;
+ RECT 1852.190000 738.560000 1853.190000 739.040000 ;
+ RECT 1855.855000 738.560000 1857.120000 739.040000 ;
+ RECT 1852.190000 727.680000 1853.190000 728.160000 ;
+ RECT 1855.855000 727.680000 1857.120000 728.160000 ;
+ RECT 1852.190000 733.120000 1853.190000 733.600000 ;
+ RECT 1855.855000 733.120000 1857.120000 733.600000 ;
+ RECT 1852.190000 722.240000 1853.190000 722.720000 ;
+ RECT 1855.855000 722.240000 1857.120000 722.720000 ;
+ RECT 1852.190000 716.800000 1853.190000 717.280000 ;
+ RECT 1855.855000 716.800000 1857.120000 717.280000 ;
+ RECT 1852.190000 711.360000 1853.190000 711.840000 ;
+ RECT 1855.855000 711.360000 1857.120000 711.840000 ;
+ RECT 1852.190000 705.920000 1853.190000 706.400000 ;
+ RECT 1855.855000 705.920000 1857.120000 706.400000 ;
+ RECT 1852.190000 700.480000 1853.190000 700.960000 ;
+ RECT 1855.855000 700.480000 1857.120000 700.960000 ;
+ RECT 1946.020000 673.280000 1947.120000 673.760000 ;
+ RECT 1946.020000 678.720000 1947.120000 679.200000 ;
+ RECT 1946.020000 684.160000 1947.120000 684.640000 ;
+ RECT 1946.020000 689.600000 1947.120000 690.080000 ;
+ RECT 1946.020000 695.040000 1947.120000 695.520000 ;
+ RECT 1901.020000 673.280000 1902.120000 673.760000 ;
+ RECT 1901.020000 678.720000 1902.120000 679.200000 ;
+ RECT 1901.020000 684.160000 1902.120000 684.640000 ;
+ RECT 1901.020000 689.600000 1902.120000 690.080000 ;
+ RECT 1901.020000 695.040000 1902.120000 695.520000 ;
+ RECT 1946.020000 651.520000 1947.120000 652.000000 ;
+ RECT 1946.020000 656.960000 1947.120000 657.440000 ;
+ RECT 1946.020000 662.400000 1947.120000 662.880000 ;
+ RECT 1946.020000 667.840000 1947.120000 668.320000 ;
+ RECT 1901.020000 651.520000 1902.120000 652.000000 ;
+ RECT 1901.020000 656.960000 1902.120000 657.440000 ;
+ RECT 1901.020000 662.400000 1902.120000 662.880000 ;
+ RECT 1901.020000 667.840000 1902.120000 668.320000 ;
+ RECT 1852.190000 695.040000 1853.190000 695.520000 ;
+ RECT 1855.855000 695.040000 1857.120000 695.520000 ;
+ RECT 1852.190000 684.160000 1853.190000 684.640000 ;
+ RECT 1855.855000 684.160000 1857.120000 684.640000 ;
+ RECT 1852.190000 689.600000 1853.190000 690.080000 ;
+ RECT 1855.855000 689.600000 1857.120000 690.080000 ;
+ RECT 1852.190000 678.720000 1853.190000 679.200000 ;
+ RECT 1855.855000 678.720000 1857.120000 679.200000 ;
+ RECT 1852.190000 673.280000 1853.190000 673.760000 ;
+ RECT 1855.855000 673.280000 1857.120000 673.760000 ;
+ RECT 1852.190000 667.840000 1853.190000 668.320000 ;
+ RECT 1855.855000 667.840000 1857.120000 668.320000 ;
+ RECT 1852.190000 662.400000 1853.190000 662.880000 ;
+ RECT 1855.855000 662.400000 1857.120000 662.880000 ;
+ RECT 1852.190000 656.960000 1853.190000 657.440000 ;
+ RECT 1855.855000 656.960000 1857.120000 657.440000 ;
+ RECT 1852.190000 651.520000 1853.190000 652.000000 ;
+ RECT 1855.855000 651.520000 1857.120000 652.000000 ;
+ RECT 2036.020000 635.200000 2037.120000 635.680000 ;
+ RECT 2036.020000 640.640000 2037.120000 641.120000 ;
+ RECT 2048.830000 635.200000 2049.830000 635.680000 ;
+ RECT 2048.830000 640.640000 2049.830000 641.120000 ;
+ RECT 2048.830000 624.320000 2049.830000 624.800000 ;
+ RECT 2048.830000 629.760000 2049.830000 630.240000 ;
+ RECT 2036.020000 629.760000 2037.120000 630.240000 ;
+ RECT 2036.020000 624.320000 2037.120000 624.800000 ;
+ RECT 2036.020000 613.440000 2037.120000 613.920000 ;
+ RECT 2036.020000 618.880000 2037.120000 619.360000 ;
+ RECT 2048.830000 613.440000 2049.830000 613.920000 ;
+ RECT 2048.830000 618.880000 2049.830000 619.360000 ;
+ RECT 2048.830000 602.560000 2049.830000 603.040000 ;
+ RECT 2048.830000 597.120000 2049.830000 597.600000 ;
+ RECT 2048.830000 608.000000 2049.830000 608.480000 ;
+ RECT 2036.020000 608.000000 2037.120000 608.480000 ;
+ RECT 2036.020000 602.560000 2037.120000 603.040000 ;
+ RECT 2036.020000 597.120000 2037.120000 597.600000 ;
+ RECT 1991.020000 624.320000 1992.120000 624.800000 ;
+ RECT 1991.020000 629.760000 1992.120000 630.240000 ;
+ RECT 1991.020000 635.200000 1992.120000 635.680000 ;
+ RECT 1991.020000 640.640000 1992.120000 641.120000 ;
+ RECT 1991.020000 597.120000 1992.120000 597.600000 ;
+ RECT 1991.020000 602.560000 1992.120000 603.040000 ;
+ RECT 1991.020000 608.000000 1992.120000 608.480000 ;
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+ RECT 1991.020000 618.880000 1992.120000 619.360000 ;
+ RECT 2036.020000 586.240000 2037.120000 586.720000 ;
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+ RECT 2048.830000 591.680000 2049.830000 592.160000 ;
+ RECT 2036.020000 575.360000 2037.120000 575.840000 ;
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+ RECT 1991.020000 586.240000 1992.120000 586.720000 ;
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+ RECT 1991.020000 559.040000 1992.120000 559.520000 ;
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+ RECT 1991.020000 569.920000 1992.120000 570.400000 ;
+ RECT 1946.020000 624.320000 1947.120000 624.800000 ;
+ RECT 1946.020000 629.760000 1947.120000 630.240000 ;
+ RECT 1946.020000 635.200000 1947.120000 635.680000 ;
+ RECT 1946.020000 640.640000 1947.120000 641.120000 ;
+ RECT 1901.020000 624.320000 1902.120000 624.800000 ;
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+ RECT 1901.020000 640.640000 1902.120000 641.120000 ;
+ RECT 1946.020000 597.120000 1947.120000 597.600000 ;
+ RECT 1946.020000 602.560000 1947.120000 603.040000 ;
+ RECT 1946.020000 608.000000 1947.120000 608.480000 ;
+ RECT 1946.020000 613.440000 1947.120000 613.920000 ;
+ RECT 1946.020000 618.880000 1947.120000 619.360000 ;
+ RECT 1901.020000 597.120000 1902.120000 597.600000 ;
+ RECT 1901.020000 602.560000 1902.120000 603.040000 ;
+ RECT 1901.020000 608.000000 1902.120000 608.480000 ;
+ RECT 1901.020000 613.440000 1902.120000 613.920000 ;
+ RECT 1901.020000 618.880000 1902.120000 619.360000 ;
+ RECT 1852.190000 640.640000 1853.190000 641.120000 ;
+ RECT 1855.855000 640.640000 1857.120000 641.120000 ;
+ RECT 1852.190000 635.200000 1853.190000 635.680000 ;
+ RECT 1855.855000 635.200000 1857.120000 635.680000 ;
+ RECT 1852.190000 629.760000 1853.190000 630.240000 ;
+ RECT 1855.855000 629.760000 1857.120000 630.240000 ;
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+ RECT 1852.190000 618.880000 1853.190000 619.360000 ;
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+ RECT 1852.190000 613.440000 1853.190000 613.920000 ;
+ RECT 1855.855000 613.440000 1857.120000 613.920000 ;
+ RECT 1852.190000 602.560000 1853.190000 603.040000 ;
+ RECT 1855.855000 602.560000 1857.120000 603.040000 ;
+ RECT 1852.190000 608.000000 1853.190000 608.480000 ;
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+ RECT 1855.855000 597.120000 1857.120000 597.600000 ;
+ RECT 1946.020000 575.360000 1947.120000 575.840000 ;
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+ RECT 1946.020000 586.240000 1947.120000 586.720000 ;
+ RECT 1946.020000 591.680000 1947.120000 592.160000 ;
+ RECT 1901.020000 575.360000 1902.120000 575.840000 ;
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+ RECT 1901.020000 586.240000 1902.120000 586.720000 ;
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+ RECT 1946.020000 553.600000 1947.120000 554.080000 ;
+ RECT 1946.020000 559.040000 1947.120000 559.520000 ;
+ RECT 1946.020000 564.480000 1947.120000 564.960000 ;
+ RECT 1946.020000 569.920000 1947.120000 570.400000 ;
+ RECT 1901.020000 553.600000 1902.120000 554.080000 ;
+ RECT 1901.020000 559.040000 1902.120000 559.520000 ;
+ RECT 1901.020000 564.480000 1902.120000 564.960000 ;
+ RECT 1901.020000 569.920000 1902.120000 570.400000 ;
+ RECT 1852.190000 591.680000 1853.190000 592.160000 ;
+ RECT 1855.855000 591.680000 1857.120000 592.160000 ;
+ RECT 1852.190000 586.240000 1853.190000 586.720000 ;
+ RECT 1855.855000 586.240000 1857.120000 586.720000 ;
+ RECT 1852.190000 580.800000 1853.190000 581.280000 ;
+ RECT 1855.855000 580.800000 1857.120000 581.280000 ;
+ RECT 1852.190000 575.360000 1853.190000 575.840000 ;
+ RECT 1855.855000 575.360000 1857.120000 575.840000 ;
+ RECT 1852.190000 569.920000 1853.190000 570.400000 ;
+ RECT 1855.855000 569.920000 1857.120000 570.400000 ;
+ RECT 1852.190000 559.040000 1853.190000 559.520000 ;
+ RECT 1855.855000 559.040000 1857.120000 559.520000 ;
+ RECT 1852.190000 564.480000 1853.190000 564.960000 ;
+ RECT 1855.855000 564.480000 1857.120000 564.960000 ;
+ RECT 1852.190000 553.600000 1853.190000 554.080000 ;
+ RECT 1855.855000 553.600000 1857.120000 554.080000 ;
+ RECT 1991.020000 646.080000 1992.120000 646.560000 ;
+ RECT 2036.020000 646.080000 2037.120000 646.560000 ;
+ RECT 2048.830000 646.080000 2049.830000 646.560000 ;
+ RECT 1901.020000 646.080000 1902.120000 646.560000 ;
+ RECT 1946.020000 646.080000 1947.120000 646.560000 ;
+ RECT 1852.190000 646.080000 1853.190000 646.560000 ;
+ RECT 1855.855000 646.080000 1857.120000 646.560000 ;
+ RECT 1850.960000 742.840000 2051.060000 743.840000 ;
+ RECT 1850.960000 547.270000 2051.060000 548.270000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 546.020000 1853.190000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 745.280000 1853.190000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 546.020000 2049.830000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 745.280000 2049.830000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 547.270000 1851.960000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 547.270000 2051.060000 548.270000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 742.840000 1851.960000 743.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 742.840000 2051.060000 743.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
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+ RECT 1855.855000 532.860000 1857.120000 533.340000 ;
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+ RECT 1855.855000 511.100000 1857.120000 511.580000 ;
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+ RECT 1855.855000 473.020000 1857.120000 473.500000 ;
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+ RECT 2048.830000 345.760000 2049.830000 546.020000 ;
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+ RECT 1901.020000 347.010000 1902.120000 543.580000 ;
+ RECT 1856.020000 347.010000 1857.120000 543.580000 ;
+ RECT 1852.190000 345.760000 1853.190000 546.020000 ;
+ LAYER met3 ;
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+ RECT 1991.020000 538.300000 1992.120000 538.780000 ;
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+ RECT 1991.020000 500.220000 1992.120000 500.700000 ;
+ RECT 1991.020000 511.100000 1992.120000 511.580000 ;
+ RECT 1991.020000 516.540000 1992.120000 517.020000 ;
+ RECT 2048.830000 489.340000 2049.830000 489.820000 ;
+ RECT 2048.830000 483.900000 2049.830000 484.380000 ;
+ RECT 2048.830000 494.780000 2049.830000 495.260000 ;
+ RECT 2036.020000 494.780000 2037.120000 495.260000 ;
+ RECT 2036.020000 489.340000 2037.120000 489.820000 ;
+ RECT 2036.020000 483.900000 2037.120000 484.380000 ;
+ RECT 2036.020000 473.020000 2037.120000 473.500000 ;
+ RECT 2036.020000 478.460000 2037.120000 478.940000 ;
+ RECT 2048.830000 473.020000 2049.830000 473.500000 ;
+ RECT 2048.830000 478.460000 2049.830000 478.940000 ;
+ RECT 2048.830000 462.140000 2049.830000 462.620000 ;
+ RECT 2048.830000 467.580000 2049.830000 468.060000 ;
+ RECT 2036.020000 467.580000 2037.120000 468.060000 ;
+ RECT 2036.020000 462.140000 2037.120000 462.620000 ;
+ RECT 2036.020000 451.260000 2037.120000 451.740000 ;
+ RECT 2036.020000 456.700000 2037.120000 457.180000 ;
+ RECT 2048.830000 451.260000 2049.830000 451.740000 ;
+ RECT 2048.830000 456.700000 2049.830000 457.180000 ;
+ RECT 1991.020000 473.020000 1992.120000 473.500000 ;
+ RECT 1991.020000 478.460000 1992.120000 478.940000 ;
+ RECT 1991.020000 483.900000 1992.120000 484.380000 ;
+ RECT 1991.020000 489.340000 1992.120000 489.820000 ;
+ RECT 1991.020000 494.780000 1992.120000 495.260000 ;
+ RECT 1991.020000 451.260000 1992.120000 451.740000 ;
+ RECT 1991.020000 456.700000 1992.120000 457.180000 ;
+ RECT 1991.020000 462.140000 1992.120000 462.620000 ;
+ RECT 1991.020000 467.580000 1992.120000 468.060000 ;
+ RECT 1946.020000 527.420000 1947.120000 527.900000 ;
+ RECT 1946.020000 521.980000 1947.120000 522.460000 ;
+ RECT 1946.020000 532.860000 1947.120000 533.340000 ;
+ RECT 1946.020000 538.300000 1947.120000 538.780000 ;
+ RECT 1901.020000 521.980000 1902.120000 522.460000 ;
+ RECT 1901.020000 527.420000 1902.120000 527.900000 ;
+ RECT 1901.020000 532.860000 1902.120000 533.340000 ;
+ RECT 1901.020000 538.300000 1902.120000 538.780000 ;
+ RECT 1946.020000 500.220000 1947.120000 500.700000 ;
+ RECT 1946.020000 505.660000 1947.120000 506.140000 ;
+ RECT 1946.020000 511.100000 1947.120000 511.580000 ;
+ RECT 1946.020000 516.540000 1947.120000 517.020000 ;
+ RECT 1901.020000 500.220000 1902.120000 500.700000 ;
+ RECT 1901.020000 505.660000 1902.120000 506.140000 ;
+ RECT 1901.020000 511.100000 1902.120000 511.580000 ;
+ RECT 1901.020000 516.540000 1902.120000 517.020000 ;
+ RECT 1852.190000 538.300000 1853.190000 538.780000 ;
+ RECT 1855.855000 538.300000 1857.120000 538.780000 ;
+ RECT 1852.190000 527.420000 1853.190000 527.900000 ;
+ RECT 1855.855000 527.420000 1857.120000 527.900000 ;
+ RECT 1852.190000 532.860000 1853.190000 533.340000 ;
+ RECT 1855.855000 532.860000 1857.120000 533.340000 ;
+ RECT 1852.190000 521.980000 1853.190000 522.460000 ;
+ RECT 1855.855000 521.980000 1857.120000 522.460000 ;
+ RECT 1852.190000 516.540000 1853.190000 517.020000 ;
+ RECT 1855.855000 516.540000 1857.120000 517.020000 ;
+ RECT 1852.190000 511.100000 1853.190000 511.580000 ;
+ RECT 1855.855000 511.100000 1857.120000 511.580000 ;
+ RECT 1852.190000 505.660000 1853.190000 506.140000 ;
+ RECT 1855.855000 505.660000 1857.120000 506.140000 ;
+ RECT 1852.190000 500.220000 1853.190000 500.700000 ;
+ RECT 1855.855000 500.220000 1857.120000 500.700000 ;
+ RECT 1946.020000 473.020000 1947.120000 473.500000 ;
+ RECT 1946.020000 478.460000 1947.120000 478.940000 ;
+ RECT 1946.020000 483.900000 1947.120000 484.380000 ;
+ RECT 1946.020000 489.340000 1947.120000 489.820000 ;
+ RECT 1946.020000 494.780000 1947.120000 495.260000 ;
+ RECT 1901.020000 473.020000 1902.120000 473.500000 ;
+ RECT 1901.020000 478.460000 1902.120000 478.940000 ;
+ RECT 1901.020000 483.900000 1902.120000 484.380000 ;
+ RECT 1901.020000 489.340000 1902.120000 489.820000 ;
+ RECT 1901.020000 494.780000 1902.120000 495.260000 ;
+ RECT 1946.020000 451.260000 1947.120000 451.740000 ;
+ RECT 1946.020000 456.700000 1947.120000 457.180000 ;
+ RECT 1946.020000 462.140000 1947.120000 462.620000 ;
+ RECT 1946.020000 467.580000 1947.120000 468.060000 ;
+ RECT 1901.020000 451.260000 1902.120000 451.740000 ;
+ RECT 1901.020000 456.700000 1902.120000 457.180000 ;
+ RECT 1901.020000 462.140000 1902.120000 462.620000 ;
+ RECT 1901.020000 467.580000 1902.120000 468.060000 ;
+ RECT 1852.190000 494.780000 1853.190000 495.260000 ;
+ RECT 1855.855000 494.780000 1857.120000 495.260000 ;
+ RECT 1852.190000 483.900000 1853.190000 484.380000 ;
+ RECT 1855.855000 483.900000 1857.120000 484.380000 ;
+ RECT 1852.190000 489.340000 1853.190000 489.820000 ;
+ RECT 1855.855000 489.340000 1857.120000 489.820000 ;
+ RECT 1852.190000 478.460000 1853.190000 478.940000 ;
+ RECT 1855.855000 478.460000 1857.120000 478.940000 ;
+ RECT 1852.190000 473.020000 1853.190000 473.500000 ;
+ RECT 1855.855000 473.020000 1857.120000 473.500000 ;
+ RECT 1852.190000 467.580000 1853.190000 468.060000 ;
+ RECT 1855.855000 467.580000 1857.120000 468.060000 ;
+ RECT 1852.190000 462.140000 1853.190000 462.620000 ;
+ RECT 1855.855000 462.140000 1857.120000 462.620000 ;
+ RECT 1852.190000 456.700000 1853.190000 457.180000 ;
+ RECT 1855.855000 456.700000 1857.120000 457.180000 ;
+ RECT 1852.190000 451.260000 1853.190000 451.740000 ;
+ RECT 1855.855000 451.260000 1857.120000 451.740000 ;
+ RECT 2036.020000 434.940000 2037.120000 435.420000 ;
+ RECT 2036.020000 440.380000 2037.120000 440.860000 ;
+ RECT 2048.830000 434.940000 2049.830000 435.420000 ;
+ RECT 2048.830000 440.380000 2049.830000 440.860000 ;
+ RECT 2048.830000 424.060000 2049.830000 424.540000 ;
+ RECT 2048.830000 429.500000 2049.830000 429.980000 ;
+ RECT 2036.020000 429.500000 2037.120000 429.980000 ;
+ RECT 2036.020000 424.060000 2037.120000 424.540000 ;
+ RECT 2036.020000 413.180000 2037.120000 413.660000 ;
+ RECT 2036.020000 418.620000 2037.120000 419.100000 ;
+ RECT 2048.830000 413.180000 2049.830000 413.660000 ;
+ RECT 2048.830000 418.620000 2049.830000 419.100000 ;
+ RECT 2048.830000 402.300000 2049.830000 402.780000 ;
+ RECT 2048.830000 396.860000 2049.830000 397.340000 ;
+ RECT 2048.830000 407.740000 2049.830000 408.220000 ;
+ RECT 2036.020000 407.740000 2037.120000 408.220000 ;
+ RECT 2036.020000 402.300000 2037.120000 402.780000 ;
+ RECT 2036.020000 396.860000 2037.120000 397.340000 ;
+ RECT 1991.020000 424.060000 1992.120000 424.540000 ;
+ RECT 1991.020000 429.500000 1992.120000 429.980000 ;
+ RECT 1991.020000 434.940000 1992.120000 435.420000 ;
+ RECT 1991.020000 440.380000 1992.120000 440.860000 ;
+ RECT 1991.020000 396.860000 1992.120000 397.340000 ;
+ RECT 1991.020000 402.300000 1992.120000 402.780000 ;
+ RECT 1991.020000 407.740000 1992.120000 408.220000 ;
+ RECT 1991.020000 413.180000 1992.120000 413.660000 ;
+ RECT 1991.020000 418.620000 1992.120000 419.100000 ;
+ RECT 2036.020000 385.980000 2037.120000 386.460000 ;
+ RECT 2036.020000 391.420000 2037.120000 391.900000 ;
+ RECT 2048.830000 385.980000 2049.830000 386.460000 ;
+ RECT 2048.830000 391.420000 2049.830000 391.900000 ;
+ RECT 2036.020000 375.100000 2037.120000 375.580000 ;
+ RECT 2036.020000 380.540000 2037.120000 381.020000 ;
+ RECT 2048.830000 375.100000 2049.830000 375.580000 ;
+ RECT 2048.830000 380.540000 2049.830000 381.020000 ;
+ RECT 2048.830000 364.220000 2049.830000 364.700000 ;
+ RECT 2048.830000 358.780000 2049.830000 359.260000 ;
+ RECT 2048.830000 369.660000 2049.830000 370.140000 ;
+ RECT 2036.020000 369.660000 2037.120000 370.140000 ;
+ RECT 2036.020000 364.220000 2037.120000 364.700000 ;
+ RECT 2036.020000 358.780000 2037.120000 359.260000 ;
+ RECT 2036.020000 353.340000 2037.120000 353.820000 ;
+ RECT 2048.830000 353.340000 2049.830000 353.820000 ;
+ RECT 1991.020000 375.100000 1992.120000 375.580000 ;
+ RECT 1991.020000 380.540000 1992.120000 381.020000 ;
+ RECT 1991.020000 385.980000 1992.120000 386.460000 ;
+ RECT 1991.020000 391.420000 1992.120000 391.900000 ;
+ RECT 1991.020000 353.340000 1992.120000 353.820000 ;
+ RECT 1991.020000 358.780000 1992.120000 359.260000 ;
+ RECT 1991.020000 364.220000 1992.120000 364.700000 ;
+ RECT 1991.020000 369.660000 1992.120000 370.140000 ;
+ RECT 1946.020000 424.060000 1947.120000 424.540000 ;
+ RECT 1946.020000 429.500000 1947.120000 429.980000 ;
+ RECT 1946.020000 434.940000 1947.120000 435.420000 ;
+ RECT 1946.020000 440.380000 1947.120000 440.860000 ;
+ RECT 1901.020000 424.060000 1902.120000 424.540000 ;
+ RECT 1901.020000 429.500000 1902.120000 429.980000 ;
+ RECT 1901.020000 434.940000 1902.120000 435.420000 ;
+ RECT 1901.020000 440.380000 1902.120000 440.860000 ;
+ RECT 1946.020000 396.860000 1947.120000 397.340000 ;
+ RECT 1946.020000 402.300000 1947.120000 402.780000 ;
+ RECT 1946.020000 407.740000 1947.120000 408.220000 ;
+ RECT 1946.020000 413.180000 1947.120000 413.660000 ;
+ RECT 1946.020000 418.620000 1947.120000 419.100000 ;
+ RECT 1901.020000 396.860000 1902.120000 397.340000 ;
+ RECT 1901.020000 402.300000 1902.120000 402.780000 ;
+ RECT 1901.020000 407.740000 1902.120000 408.220000 ;
+ RECT 1901.020000 413.180000 1902.120000 413.660000 ;
+ RECT 1901.020000 418.620000 1902.120000 419.100000 ;
+ RECT 1852.190000 440.380000 1853.190000 440.860000 ;
+ RECT 1855.855000 440.380000 1857.120000 440.860000 ;
+ RECT 1852.190000 434.940000 1853.190000 435.420000 ;
+ RECT 1855.855000 434.940000 1857.120000 435.420000 ;
+ RECT 1852.190000 429.500000 1853.190000 429.980000 ;
+ RECT 1855.855000 429.500000 1857.120000 429.980000 ;
+ RECT 1852.190000 424.060000 1853.190000 424.540000 ;
+ RECT 1855.855000 424.060000 1857.120000 424.540000 ;
+ RECT 1852.190000 418.620000 1853.190000 419.100000 ;
+ RECT 1855.855000 418.620000 1857.120000 419.100000 ;
+ RECT 1852.190000 413.180000 1853.190000 413.660000 ;
+ RECT 1855.855000 413.180000 1857.120000 413.660000 ;
+ RECT 1852.190000 402.300000 1853.190000 402.780000 ;
+ RECT 1855.855000 402.300000 1857.120000 402.780000 ;
+ RECT 1852.190000 407.740000 1853.190000 408.220000 ;
+ RECT 1855.855000 407.740000 1857.120000 408.220000 ;
+ RECT 1852.190000 396.860000 1853.190000 397.340000 ;
+ RECT 1855.855000 396.860000 1857.120000 397.340000 ;
+ RECT 1946.020000 375.100000 1947.120000 375.580000 ;
+ RECT 1946.020000 380.540000 1947.120000 381.020000 ;
+ RECT 1946.020000 385.980000 1947.120000 386.460000 ;
+ RECT 1946.020000 391.420000 1947.120000 391.900000 ;
+ RECT 1901.020000 375.100000 1902.120000 375.580000 ;
+ RECT 1901.020000 380.540000 1902.120000 381.020000 ;
+ RECT 1901.020000 385.980000 1902.120000 386.460000 ;
+ RECT 1901.020000 391.420000 1902.120000 391.900000 ;
+ RECT 1946.020000 353.340000 1947.120000 353.820000 ;
+ RECT 1946.020000 358.780000 1947.120000 359.260000 ;
+ RECT 1946.020000 364.220000 1947.120000 364.700000 ;
+ RECT 1946.020000 369.660000 1947.120000 370.140000 ;
+ RECT 1901.020000 353.340000 1902.120000 353.820000 ;
+ RECT 1901.020000 358.780000 1902.120000 359.260000 ;
+ RECT 1901.020000 364.220000 1902.120000 364.700000 ;
+ RECT 1901.020000 369.660000 1902.120000 370.140000 ;
+ RECT 1852.190000 391.420000 1853.190000 391.900000 ;
+ RECT 1855.855000 391.420000 1857.120000 391.900000 ;
+ RECT 1852.190000 385.980000 1853.190000 386.460000 ;
+ RECT 1855.855000 385.980000 1857.120000 386.460000 ;
+ RECT 1852.190000 380.540000 1853.190000 381.020000 ;
+ RECT 1855.855000 380.540000 1857.120000 381.020000 ;
+ RECT 1852.190000 375.100000 1853.190000 375.580000 ;
+ RECT 1855.855000 375.100000 1857.120000 375.580000 ;
+ RECT 1852.190000 369.660000 1853.190000 370.140000 ;
+ RECT 1855.855000 369.660000 1857.120000 370.140000 ;
+ RECT 1852.190000 358.780000 1853.190000 359.260000 ;
+ RECT 1855.855000 358.780000 1857.120000 359.260000 ;
+ RECT 1852.190000 364.220000 1853.190000 364.700000 ;
+ RECT 1855.855000 364.220000 1857.120000 364.700000 ;
+ RECT 1852.190000 353.340000 1853.190000 353.820000 ;
+ RECT 1855.855000 353.340000 1857.120000 353.820000 ;
+ RECT 1991.020000 445.820000 1992.120000 446.300000 ;
+ RECT 2036.020000 445.820000 2037.120000 446.300000 ;
+ RECT 2048.830000 445.820000 2049.830000 446.300000 ;
+ RECT 1901.020000 445.820000 1902.120000 446.300000 ;
+ RECT 1946.020000 445.820000 1947.120000 446.300000 ;
+ RECT 1852.190000 445.820000 1853.190000 446.300000 ;
+ RECT 1855.855000 445.820000 1857.120000 446.300000 ;
+ RECT 1850.960000 542.580000 2051.060000 543.580000 ;
+ RECT 1850.960000 347.010000 2051.060000 348.010000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 345.760000 1853.190000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 545.020000 1853.190000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 345.760000 2049.830000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 545.020000 2049.830000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 347.010000 1851.960000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 347.010000 2051.060000 348.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 542.580000 1851.960000 543.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 542.580000 2051.060000 543.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 338.040000 1857.120000 338.520000 ;
+ RECT 1855.855000 327.160000 1857.120000 327.640000 ;
+ RECT 1855.855000 332.600000 1857.120000 333.080000 ;
+ RECT 1855.855000 321.720000 1857.120000 322.200000 ;
+ RECT 1855.855000 316.280000 1857.120000 316.760000 ;
+ RECT 1855.855000 310.840000 1857.120000 311.320000 ;
+ RECT 1855.855000 305.400000 1857.120000 305.880000 ;
+ RECT 1855.855000 299.960000 1857.120000 300.440000 ;
+ RECT 1855.855000 294.520000 1857.120000 295.000000 ;
+ RECT 1855.855000 283.640000 1857.120000 284.120000 ;
+ RECT 1855.855000 289.080000 1857.120000 289.560000 ;
+ RECT 1855.855000 278.200000 1857.120000 278.680000 ;
+ RECT 1855.855000 272.760000 1857.120000 273.240000 ;
+ RECT 1855.855000 267.320000 1857.120000 267.800000 ;
+ RECT 1855.855000 261.880000 1857.120000 262.360000 ;
+ RECT 1855.855000 256.440000 1857.120000 256.920000 ;
+ RECT 1855.855000 251.000000 1857.120000 251.480000 ;
+ RECT 1855.855000 240.120000 1857.120000 240.600000 ;
+ RECT 1855.855000 234.680000 1857.120000 235.160000 ;
+ RECT 1855.855000 229.240000 1857.120000 229.720000 ;
+ RECT 1855.855000 223.800000 1857.120000 224.280000 ;
+ RECT 1855.855000 218.360000 1857.120000 218.840000 ;
+ RECT 1855.855000 212.920000 1857.120000 213.400000 ;
+ RECT 1855.855000 202.040000 1857.120000 202.520000 ;
+ RECT 1855.855000 207.480000 1857.120000 207.960000 ;
+ RECT 1855.855000 196.600000 1857.120000 197.080000 ;
+ RECT 1855.855000 191.160000 1857.120000 191.640000 ;
+ RECT 1855.855000 185.720000 1857.120000 186.200000 ;
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+ RECT 1855.855000 169.400000 1857.120000 169.880000 ;
+ RECT 1855.855000 158.520000 1857.120000 159.000000 ;
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+ RECT 1855.855000 153.080000 1857.120000 153.560000 ;
+ RECT 1855.855000 245.560000 1857.120000 246.040000 ;
+ RECT 2036.020000 146.750000 2037.120000 343.320000 ;
+ RECT 1991.020000 146.750000 1992.120000 343.320000 ;
+ RECT 2048.830000 145.500000 2049.830000 345.760000 ;
+ RECT 1946.020000 146.750000 1947.120000 343.320000 ;
+ RECT 1901.020000 146.750000 1902.120000 343.320000 ;
+ RECT 1856.020000 146.750000 1857.120000 343.320000 ;
+ RECT 1852.190000 145.500000 1853.190000 345.760000 ;
+ LAYER met3 ;
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+ RECT 2036.020000 299.960000 2037.120000 300.440000 ;
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+ RECT 2048.830000 299.960000 2049.830000 300.440000 ;
+ RECT 2048.830000 305.400000 2049.830000 305.880000 ;
+ RECT 1991.020000 321.720000 1992.120000 322.200000 ;
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+ RECT 2048.830000 289.080000 2049.830000 289.560000 ;
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+ RECT 2048.830000 261.880000 2049.830000 262.360000 ;
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+ RECT 1991.020000 272.760000 1992.120000 273.240000 ;
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+ RECT 1946.020000 327.160000 1947.120000 327.640000 ;
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+ RECT 1901.020000 338.040000 1902.120000 338.520000 ;
+ RECT 1946.020000 299.960000 1947.120000 300.440000 ;
+ RECT 1946.020000 305.400000 1947.120000 305.880000 ;
+ RECT 1946.020000 310.840000 1947.120000 311.320000 ;
+ RECT 1946.020000 316.280000 1947.120000 316.760000 ;
+ RECT 1901.020000 299.960000 1902.120000 300.440000 ;
+ RECT 1901.020000 305.400000 1902.120000 305.880000 ;
+ RECT 1901.020000 310.840000 1902.120000 311.320000 ;
+ RECT 1901.020000 316.280000 1902.120000 316.760000 ;
+ RECT 1852.190000 338.040000 1853.190000 338.520000 ;
+ RECT 1855.855000 338.040000 1857.120000 338.520000 ;
+ RECT 1852.190000 327.160000 1853.190000 327.640000 ;
+ RECT 1855.855000 327.160000 1857.120000 327.640000 ;
+ RECT 1852.190000 332.600000 1853.190000 333.080000 ;
+ RECT 1855.855000 332.600000 1857.120000 333.080000 ;
+ RECT 1852.190000 321.720000 1853.190000 322.200000 ;
+ RECT 1855.855000 321.720000 1857.120000 322.200000 ;
+ RECT 1852.190000 316.280000 1853.190000 316.760000 ;
+ RECT 1855.855000 316.280000 1857.120000 316.760000 ;
+ RECT 1852.190000 310.840000 1853.190000 311.320000 ;
+ RECT 1855.855000 310.840000 1857.120000 311.320000 ;
+ RECT 1852.190000 305.400000 1853.190000 305.880000 ;
+ RECT 1855.855000 305.400000 1857.120000 305.880000 ;
+ RECT 1852.190000 299.960000 1853.190000 300.440000 ;
+ RECT 1855.855000 299.960000 1857.120000 300.440000 ;
+ RECT 1946.020000 272.760000 1947.120000 273.240000 ;
+ RECT 1946.020000 278.200000 1947.120000 278.680000 ;
+ RECT 1946.020000 283.640000 1947.120000 284.120000 ;
+ RECT 1946.020000 289.080000 1947.120000 289.560000 ;
+ RECT 1946.020000 294.520000 1947.120000 295.000000 ;
+ RECT 1901.020000 272.760000 1902.120000 273.240000 ;
+ RECT 1901.020000 278.200000 1902.120000 278.680000 ;
+ RECT 1901.020000 283.640000 1902.120000 284.120000 ;
+ RECT 1901.020000 289.080000 1902.120000 289.560000 ;
+ RECT 1901.020000 294.520000 1902.120000 295.000000 ;
+ RECT 1946.020000 251.000000 1947.120000 251.480000 ;
+ RECT 1946.020000 256.440000 1947.120000 256.920000 ;
+ RECT 1946.020000 261.880000 1947.120000 262.360000 ;
+ RECT 1946.020000 267.320000 1947.120000 267.800000 ;
+ RECT 1901.020000 251.000000 1902.120000 251.480000 ;
+ RECT 1901.020000 256.440000 1902.120000 256.920000 ;
+ RECT 1901.020000 261.880000 1902.120000 262.360000 ;
+ RECT 1901.020000 267.320000 1902.120000 267.800000 ;
+ RECT 1852.190000 294.520000 1853.190000 295.000000 ;
+ RECT 1855.855000 294.520000 1857.120000 295.000000 ;
+ RECT 1852.190000 283.640000 1853.190000 284.120000 ;
+ RECT 1855.855000 283.640000 1857.120000 284.120000 ;
+ RECT 1852.190000 289.080000 1853.190000 289.560000 ;
+ RECT 1855.855000 289.080000 1857.120000 289.560000 ;
+ RECT 1852.190000 278.200000 1853.190000 278.680000 ;
+ RECT 1855.855000 278.200000 1857.120000 278.680000 ;
+ RECT 1852.190000 272.760000 1853.190000 273.240000 ;
+ RECT 1855.855000 272.760000 1857.120000 273.240000 ;
+ RECT 1852.190000 267.320000 1853.190000 267.800000 ;
+ RECT 1855.855000 267.320000 1857.120000 267.800000 ;
+ RECT 1852.190000 261.880000 1853.190000 262.360000 ;
+ RECT 1855.855000 261.880000 1857.120000 262.360000 ;
+ RECT 1852.190000 256.440000 1853.190000 256.920000 ;
+ RECT 1855.855000 256.440000 1857.120000 256.920000 ;
+ RECT 1852.190000 251.000000 1853.190000 251.480000 ;
+ RECT 1855.855000 251.000000 1857.120000 251.480000 ;
+ RECT 2036.020000 234.680000 2037.120000 235.160000 ;
+ RECT 2036.020000 240.120000 2037.120000 240.600000 ;
+ RECT 2048.830000 234.680000 2049.830000 235.160000 ;
+ RECT 2048.830000 240.120000 2049.830000 240.600000 ;
+ RECT 2048.830000 223.800000 2049.830000 224.280000 ;
+ RECT 2048.830000 229.240000 2049.830000 229.720000 ;
+ RECT 2036.020000 229.240000 2037.120000 229.720000 ;
+ RECT 2036.020000 223.800000 2037.120000 224.280000 ;
+ RECT 2036.020000 212.920000 2037.120000 213.400000 ;
+ RECT 2036.020000 218.360000 2037.120000 218.840000 ;
+ RECT 2048.830000 212.920000 2049.830000 213.400000 ;
+ RECT 2048.830000 218.360000 2049.830000 218.840000 ;
+ RECT 2048.830000 202.040000 2049.830000 202.520000 ;
+ RECT 2048.830000 196.600000 2049.830000 197.080000 ;
+ RECT 2048.830000 207.480000 2049.830000 207.960000 ;
+ RECT 2036.020000 207.480000 2037.120000 207.960000 ;
+ RECT 2036.020000 202.040000 2037.120000 202.520000 ;
+ RECT 2036.020000 196.600000 2037.120000 197.080000 ;
+ RECT 1991.020000 223.800000 1992.120000 224.280000 ;
+ RECT 1991.020000 229.240000 1992.120000 229.720000 ;
+ RECT 1991.020000 234.680000 1992.120000 235.160000 ;
+ RECT 1991.020000 240.120000 1992.120000 240.600000 ;
+ RECT 1991.020000 196.600000 1992.120000 197.080000 ;
+ RECT 1991.020000 202.040000 1992.120000 202.520000 ;
+ RECT 1991.020000 207.480000 1992.120000 207.960000 ;
+ RECT 1991.020000 212.920000 1992.120000 213.400000 ;
+ RECT 1991.020000 218.360000 1992.120000 218.840000 ;
+ RECT 2036.020000 185.720000 2037.120000 186.200000 ;
+ RECT 2036.020000 191.160000 2037.120000 191.640000 ;
+ RECT 2048.830000 185.720000 2049.830000 186.200000 ;
+ RECT 2048.830000 191.160000 2049.830000 191.640000 ;
+ RECT 2036.020000 174.840000 2037.120000 175.320000 ;
+ RECT 2036.020000 180.280000 2037.120000 180.760000 ;
+ RECT 2048.830000 174.840000 2049.830000 175.320000 ;
+ RECT 2048.830000 180.280000 2049.830000 180.760000 ;
+ RECT 2048.830000 163.960000 2049.830000 164.440000 ;
+ RECT 2048.830000 158.520000 2049.830000 159.000000 ;
+ RECT 2048.830000 169.400000 2049.830000 169.880000 ;
+ RECT 2036.020000 169.400000 2037.120000 169.880000 ;
+ RECT 2036.020000 163.960000 2037.120000 164.440000 ;
+ RECT 2036.020000 158.520000 2037.120000 159.000000 ;
+ RECT 2036.020000 153.080000 2037.120000 153.560000 ;
+ RECT 2048.830000 153.080000 2049.830000 153.560000 ;
+ RECT 1991.020000 174.840000 1992.120000 175.320000 ;
+ RECT 1991.020000 180.280000 1992.120000 180.760000 ;
+ RECT 1991.020000 185.720000 1992.120000 186.200000 ;
+ RECT 1991.020000 191.160000 1992.120000 191.640000 ;
+ RECT 1991.020000 153.080000 1992.120000 153.560000 ;
+ RECT 1991.020000 158.520000 1992.120000 159.000000 ;
+ RECT 1991.020000 163.960000 1992.120000 164.440000 ;
+ RECT 1991.020000 169.400000 1992.120000 169.880000 ;
+ RECT 1946.020000 223.800000 1947.120000 224.280000 ;
+ RECT 1946.020000 229.240000 1947.120000 229.720000 ;
+ RECT 1946.020000 234.680000 1947.120000 235.160000 ;
+ RECT 1946.020000 240.120000 1947.120000 240.600000 ;
+ RECT 1901.020000 223.800000 1902.120000 224.280000 ;
+ RECT 1901.020000 229.240000 1902.120000 229.720000 ;
+ RECT 1901.020000 234.680000 1902.120000 235.160000 ;
+ RECT 1901.020000 240.120000 1902.120000 240.600000 ;
+ RECT 1946.020000 196.600000 1947.120000 197.080000 ;
+ RECT 1946.020000 202.040000 1947.120000 202.520000 ;
+ RECT 1946.020000 207.480000 1947.120000 207.960000 ;
+ RECT 1946.020000 212.920000 1947.120000 213.400000 ;
+ RECT 1946.020000 218.360000 1947.120000 218.840000 ;
+ RECT 1901.020000 196.600000 1902.120000 197.080000 ;
+ RECT 1901.020000 202.040000 1902.120000 202.520000 ;
+ RECT 1901.020000 207.480000 1902.120000 207.960000 ;
+ RECT 1901.020000 212.920000 1902.120000 213.400000 ;
+ RECT 1901.020000 218.360000 1902.120000 218.840000 ;
+ RECT 1852.190000 240.120000 1853.190000 240.600000 ;
+ RECT 1855.855000 240.120000 1857.120000 240.600000 ;
+ RECT 1852.190000 234.680000 1853.190000 235.160000 ;
+ RECT 1855.855000 234.680000 1857.120000 235.160000 ;
+ RECT 1852.190000 229.240000 1853.190000 229.720000 ;
+ RECT 1855.855000 229.240000 1857.120000 229.720000 ;
+ RECT 1852.190000 223.800000 1853.190000 224.280000 ;
+ RECT 1855.855000 223.800000 1857.120000 224.280000 ;
+ RECT 1852.190000 218.360000 1853.190000 218.840000 ;
+ RECT 1855.855000 218.360000 1857.120000 218.840000 ;
+ RECT 1852.190000 212.920000 1853.190000 213.400000 ;
+ RECT 1855.855000 212.920000 1857.120000 213.400000 ;
+ RECT 1852.190000 202.040000 1853.190000 202.520000 ;
+ RECT 1855.855000 202.040000 1857.120000 202.520000 ;
+ RECT 1852.190000 207.480000 1853.190000 207.960000 ;
+ RECT 1855.855000 207.480000 1857.120000 207.960000 ;
+ RECT 1852.190000 196.600000 1853.190000 197.080000 ;
+ RECT 1855.855000 196.600000 1857.120000 197.080000 ;
+ RECT 1946.020000 174.840000 1947.120000 175.320000 ;
+ RECT 1946.020000 180.280000 1947.120000 180.760000 ;
+ RECT 1946.020000 185.720000 1947.120000 186.200000 ;
+ RECT 1946.020000 191.160000 1947.120000 191.640000 ;
+ RECT 1901.020000 174.840000 1902.120000 175.320000 ;
+ RECT 1901.020000 180.280000 1902.120000 180.760000 ;
+ RECT 1901.020000 185.720000 1902.120000 186.200000 ;
+ RECT 1901.020000 191.160000 1902.120000 191.640000 ;
+ RECT 1946.020000 153.080000 1947.120000 153.560000 ;
+ RECT 1946.020000 158.520000 1947.120000 159.000000 ;
+ RECT 1946.020000 163.960000 1947.120000 164.440000 ;
+ RECT 1946.020000 169.400000 1947.120000 169.880000 ;
+ RECT 1901.020000 153.080000 1902.120000 153.560000 ;
+ RECT 1901.020000 158.520000 1902.120000 159.000000 ;
+ RECT 1901.020000 163.960000 1902.120000 164.440000 ;
+ RECT 1901.020000 169.400000 1902.120000 169.880000 ;
+ RECT 1852.190000 191.160000 1853.190000 191.640000 ;
+ RECT 1855.855000 191.160000 1857.120000 191.640000 ;
+ RECT 1852.190000 185.720000 1853.190000 186.200000 ;
+ RECT 1855.855000 185.720000 1857.120000 186.200000 ;
+ RECT 1852.190000 180.280000 1853.190000 180.760000 ;
+ RECT 1855.855000 180.280000 1857.120000 180.760000 ;
+ RECT 1852.190000 174.840000 1853.190000 175.320000 ;
+ RECT 1855.855000 174.840000 1857.120000 175.320000 ;
+ RECT 1852.190000 169.400000 1853.190000 169.880000 ;
+ RECT 1855.855000 169.400000 1857.120000 169.880000 ;
+ RECT 1852.190000 158.520000 1853.190000 159.000000 ;
+ RECT 1855.855000 158.520000 1857.120000 159.000000 ;
+ RECT 1852.190000 163.960000 1853.190000 164.440000 ;
+ RECT 1855.855000 163.960000 1857.120000 164.440000 ;
+ RECT 1852.190000 153.080000 1853.190000 153.560000 ;
+ RECT 1855.855000 153.080000 1857.120000 153.560000 ;
+ RECT 1991.020000 245.560000 1992.120000 246.040000 ;
+ RECT 2036.020000 245.560000 2037.120000 246.040000 ;
+ RECT 2048.830000 245.560000 2049.830000 246.040000 ;
+ RECT 1901.020000 245.560000 1902.120000 246.040000 ;
+ RECT 1946.020000 245.560000 1947.120000 246.040000 ;
+ RECT 1852.190000 245.560000 1853.190000 246.040000 ;
+ RECT 1855.855000 245.560000 1857.120000 246.040000 ;
+ RECT 1850.960000 342.320000 2051.060000 343.320000 ;
+ RECT 1850.960000 146.750000 2051.060000 147.750000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 145.500000 1853.190000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 344.760000 1853.190000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 145.500000 2049.830000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 344.760000 2049.830000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 146.750000 1851.960000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 146.750000 2051.060000 147.750000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 342.320000 1851.960000 343.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 342.320000 2051.060000 343.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 139.140000 1857.120000 139.620000 ;
+ RECT 1855.855000 133.700000 1857.120000 134.180000 ;
+ RECT 1855.855000 128.260000 1857.120000 128.740000 ;
+ RECT 1855.855000 122.820000 1857.120000 123.300000 ;
+ RECT 1852.190000 115.240000 1853.190000 145.500000 ;
+ RECT 2048.830000 115.240000 2049.830000 145.500000 ;
+ RECT 1856.020000 116.490000 1857.120000 143.740000 ;
+ RECT 1901.020000 116.490000 1902.120000 143.740000 ;
+ RECT 1946.020000 116.490000 1947.120000 143.740000 ;
+ RECT 1991.020000 116.490000 1992.120000 143.740000 ;
+ RECT 2036.020000 116.490000 2037.120000 143.740000 ;
+ LAYER met3 ;
+ RECT 2048.830000 139.140000 2049.830000 139.620000 ;
+ RECT 2048.830000 133.700000 2049.830000 134.180000 ;
+ RECT 2036.020000 139.140000 2037.120000 139.620000 ;
+ RECT 2036.020000 133.700000 2037.120000 134.180000 ;
+ RECT 1991.020000 133.700000 1992.120000 134.180000 ;
+ RECT 1991.020000 139.140000 1992.120000 139.620000 ;
+ RECT 1946.020000 133.700000 1947.120000 134.180000 ;
+ RECT 1901.020000 133.700000 1902.120000 134.180000 ;
+ RECT 1946.020000 139.140000 1947.120000 139.620000 ;
+ RECT 1901.020000 139.140000 1902.120000 139.620000 ;
+ RECT 1855.855000 139.140000 1857.120000 139.620000 ;
+ RECT 1852.190000 139.140000 1853.190000 139.620000 ;
+ RECT 1855.855000 133.700000 1857.120000 134.180000 ;
+ RECT 1852.190000 133.700000 1853.190000 134.180000 ;
+ RECT 2048.830000 128.260000 2049.830000 128.740000 ;
+ RECT 2048.830000 122.820000 2049.830000 123.300000 ;
+ RECT 2036.020000 128.260000 2037.120000 128.740000 ;
+ RECT 2036.020000 122.820000 2037.120000 123.300000 ;
+ RECT 1991.020000 122.820000 1992.120000 123.300000 ;
+ RECT 1991.020000 128.260000 1992.120000 128.740000 ;
+ RECT 1946.020000 122.820000 1947.120000 123.300000 ;
+ RECT 1901.020000 122.820000 1902.120000 123.300000 ;
+ RECT 1946.020000 128.260000 1947.120000 128.740000 ;
+ RECT 1901.020000 128.260000 1902.120000 128.740000 ;
+ RECT 1855.855000 128.260000 1857.120000 128.740000 ;
+ RECT 1852.190000 128.260000 1853.190000 128.740000 ;
+ RECT 1855.855000 122.820000 1857.120000 123.300000 ;
+ RECT 1852.190000 122.820000 1853.190000 123.300000 ;
+ RECT 1850.960000 142.740000 2051.060000 143.740000 ;
+ RECT 1850.960000 116.490000 2051.060000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 116.490000 1851.960000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 116.490000 2051.060000 117.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 142.740000 1851.960000 143.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 142.740000 2051.060000 143.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 115.240000 1853.190000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 144.500000 1853.190000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 115.240000 2049.830000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 144.500000 2049.830000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 3341.940000 1857.120000 3342.420000 ;
+ RECT 1855.855000 3331.060000 1857.120000 3331.540000 ;
+ RECT 1855.855000 3336.500000 1857.120000 3336.980000 ;
+ RECT 1855.855000 3325.620000 1857.120000 3326.100000 ;
+ RECT 1855.855000 3320.180000 1857.120000 3320.660000 ;
+ RECT 1855.855000 3314.740000 1857.120000 3315.220000 ;
+ RECT 1855.855000 3309.300000 1857.120000 3309.780000 ;
+ RECT 1855.855000 3303.860000 1857.120000 3304.340000 ;
+ RECT 1855.855000 3298.420000 1857.120000 3298.900000 ;
+ RECT 1855.855000 3287.540000 1857.120000 3288.020000 ;
+ RECT 1855.855000 3292.980000 1857.120000 3293.460000 ;
+ RECT 1855.855000 3282.100000 1857.120000 3282.580000 ;
+ RECT 1855.855000 3276.660000 1857.120000 3277.140000 ;
+ RECT 1855.855000 3271.220000 1857.120000 3271.700000 ;
+ RECT 1855.855000 3265.780000 1857.120000 3266.260000 ;
+ RECT 1855.855000 3260.340000 1857.120000 3260.820000 ;
+ RECT 1855.855000 3254.900000 1857.120000 3255.380000 ;
+ RECT 1855.855000 3244.020000 1857.120000 3244.500000 ;
+ RECT 1855.855000 3238.580000 1857.120000 3239.060000 ;
+ RECT 1855.855000 3233.140000 1857.120000 3233.620000 ;
+ RECT 1855.855000 3227.700000 1857.120000 3228.180000 ;
+ RECT 1855.855000 3222.260000 1857.120000 3222.740000 ;
+ RECT 1855.855000 3216.820000 1857.120000 3217.300000 ;
+ RECT 1855.855000 3205.940000 1857.120000 3206.420000 ;
+ RECT 1855.855000 3211.380000 1857.120000 3211.860000 ;
+ RECT 1855.855000 3200.500000 1857.120000 3200.980000 ;
+ RECT 1855.855000 3195.060000 1857.120000 3195.540000 ;
+ RECT 1855.855000 3189.620000 1857.120000 3190.100000 ;
+ RECT 1855.855000 3184.180000 1857.120000 3184.660000 ;
+ RECT 1855.855000 3178.740000 1857.120000 3179.220000 ;
+ RECT 1855.855000 3173.300000 1857.120000 3173.780000 ;
+ RECT 1855.855000 3162.420000 1857.120000 3162.900000 ;
+ RECT 1855.855000 3167.860000 1857.120000 3168.340000 ;
+ RECT 1855.855000 3156.980000 1857.120000 3157.460000 ;
+ RECT 1855.855000 3249.460000 1857.120000 3249.940000 ;
+ RECT 2036.020000 3150.650000 2037.120000 3347.220000 ;
+ RECT 1991.020000 3150.650000 1992.120000 3347.220000 ;
+ RECT 2048.830000 3149.400000 2049.830000 3349.660000 ;
+ RECT 1946.020000 3150.650000 1947.120000 3347.220000 ;
+ RECT 1901.020000 3150.650000 1902.120000 3347.220000 ;
+ RECT 1856.020000 3150.650000 1857.120000 3347.220000 ;
+ RECT 1852.190000 3149.400000 1853.190000 3349.660000 ;
+ LAYER met3 ;
+ RECT 2036.020000 3341.940000 2037.120000 3342.420000 ;
+ RECT 2048.830000 3341.940000 2049.830000 3342.420000 ;
+ RECT 2048.830000 3331.060000 2049.830000 3331.540000 ;
+ RECT 2048.830000 3325.620000 2049.830000 3326.100000 ;
+ RECT 2048.830000 3336.500000 2049.830000 3336.980000 ;
+ RECT 2036.020000 3336.500000 2037.120000 3336.980000 ;
+ RECT 2036.020000 3331.060000 2037.120000 3331.540000 ;
+ RECT 2036.020000 3325.620000 2037.120000 3326.100000 ;
+ RECT 2036.020000 3314.740000 2037.120000 3315.220000 ;
+ RECT 2036.020000 3320.180000 2037.120000 3320.660000 ;
+ RECT 2048.830000 3314.740000 2049.830000 3315.220000 ;
+ RECT 2048.830000 3320.180000 2049.830000 3320.660000 ;
+ RECT 2036.020000 3303.860000 2037.120000 3304.340000 ;
+ RECT 2036.020000 3309.300000 2037.120000 3309.780000 ;
+ RECT 2048.830000 3303.860000 2049.830000 3304.340000 ;
+ RECT 2048.830000 3309.300000 2049.830000 3309.780000 ;
+ RECT 1991.020000 3325.620000 1992.120000 3326.100000 ;
+ RECT 1991.020000 3331.060000 1992.120000 3331.540000 ;
+ RECT 1991.020000 3336.500000 1992.120000 3336.980000 ;
+ RECT 1991.020000 3341.940000 1992.120000 3342.420000 ;
+ RECT 1991.020000 3309.300000 1992.120000 3309.780000 ;
+ RECT 1991.020000 3303.860000 1992.120000 3304.340000 ;
+ RECT 1991.020000 3314.740000 1992.120000 3315.220000 ;
+ RECT 1991.020000 3320.180000 1992.120000 3320.660000 ;
+ RECT 2048.830000 3292.980000 2049.830000 3293.460000 ;
+ RECT 2048.830000 3287.540000 2049.830000 3288.020000 ;
+ RECT 2048.830000 3298.420000 2049.830000 3298.900000 ;
+ RECT 2036.020000 3298.420000 2037.120000 3298.900000 ;
+ RECT 2036.020000 3292.980000 2037.120000 3293.460000 ;
+ RECT 2036.020000 3287.540000 2037.120000 3288.020000 ;
+ RECT 2036.020000 3276.660000 2037.120000 3277.140000 ;
+ RECT 2036.020000 3282.100000 2037.120000 3282.580000 ;
+ RECT 2048.830000 3276.660000 2049.830000 3277.140000 ;
+ RECT 2048.830000 3282.100000 2049.830000 3282.580000 ;
+ RECT 2048.830000 3265.780000 2049.830000 3266.260000 ;
+ RECT 2048.830000 3271.220000 2049.830000 3271.700000 ;
+ RECT 2036.020000 3271.220000 2037.120000 3271.700000 ;
+ RECT 2036.020000 3265.780000 2037.120000 3266.260000 ;
+ RECT 2036.020000 3254.900000 2037.120000 3255.380000 ;
+ RECT 2036.020000 3260.340000 2037.120000 3260.820000 ;
+ RECT 2048.830000 3254.900000 2049.830000 3255.380000 ;
+ RECT 2048.830000 3260.340000 2049.830000 3260.820000 ;
+ RECT 1991.020000 3276.660000 1992.120000 3277.140000 ;
+ RECT 1991.020000 3282.100000 1992.120000 3282.580000 ;
+ RECT 1991.020000 3287.540000 1992.120000 3288.020000 ;
+ RECT 1991.020000 3292.980000 1992.120000 3293.460000 ;
+ RECT 1991.020000 3298.420000 1992.120000 3298.900000 ;
+ RECT 1991.020000 3254.900000 1992.120000 3255.380000 ;
+ RECT 1991.020000 3260.340000 1992.120000 3260.820000 ;
+ RECT 1991.020000 3265.780000 1992.120000 3266.260000 ;
+ RECT 1991.020000 3271.220000 1992.120000 3271.700000 ;
+ RECT 1946.020000 3331.060000 1947.120000 3331.540000 ;
+ RECT 1946.020000 3325.620000 1947.120000 3326.100000 ;
+ RECT 1946.020000 3336.500000 1947.120000 3336.980000 ;
+ RECT 1946.020000 3341.940000 1947.120000 3342.420000 ;
+ RECT 1901.020000 3325.620000 1902.120000 3326.100000 ;
+ RECT 1901.020000 3331.060000 1902.120000 3331.540000 ;
+ RECT 1901.020000 3336.500000 1902.120000 3336.980000 ;
+ RECT 1901.020000 3341.940000 1902.120000 3342.420000 ;
+ RECT 1946.020000 3303.860000 1947.120000 3304.340000 ;
+ RECT 1946.020000 3309.300000 1947.120000 3309.780000 ;
+ RECT 1946.020000 3314.740000 1947.120000 3315.220000 ;
+ RECT 1946.020000 3320.180000 1947.120000 3320.660000 ;
+ RECT 1901.020000 3303.860000 1902.120000 3304.340000 ;
+ RECT 1901.020000 3309.300000 1902.120000 3309.780000 ;
+ RECT 1901.020000 3314.740000 1902.120000 3315.220000 ;
+ RECT 1901.020000 3320.180000 1902.120000 3320.660000 ;
+ RECT 1852.190000 3341.940000 1853.190000 3342.420000 ;
+ RECT 1855.855000 3341.940000 1857.120000 3342.420000 ;
+ RECT 1852.190000 3331.060000 1853.190000 3331.540000 ;
+ RECT 1855.855000 3331.060000 1857.120000 3331.540000 ;
+ RECT 1852.190000 3336.500000 1853.190000 3336.980000 ;
+ RECT 1855.855000 3336.500000 1857.120000 3336.980000 ;
+ RECT 1852.190000 3325.620000 1853.190000 3326.100000 ;
+ RECT 1855.855000 3325.620000 1857.120000 3326.100000 ;
+ RECT 1852.190000 3320.180000 1853.190000 3320.660000 ;
+ RECT 1855.855000 3320.180000 1857.120000 3320.660000 ;
+ RECT 1852.190000 3314.740000 1853.190000 3315.220000 ;
+ RECT 1855.855000 3314.740000 1857.120000 3315.220000 ;
+ RECT 1852.190000 3309.300000 1853.190000 3309.780000 ;
+ RECT 1855.855000 3309.300000 1857.120000 3309.780000 ;
+ RECT 1852.190000 3303.860000 1853.190000 3304.340000 ;
+ RECT 1855.855000 3303.860000 1857.120000 3304.340000 ;
+ RECT 1946.020000 3276.660000 1947.120000 3277.140000 ;
+ RECT 1946.020000 3282.100000 1947.120000 3282.580000 ;
+ RECT 1946.020000 3287.540000 1947.120000 3288.020000 ;
+ RECT 1946.020000 3292.980000 1947.120000 3293.460000 ;
+ RECT 1946.020000 3298.420000 1947.120000 3298.900000 ;
+ RECT 1901.020000 3276.660000 1902.120000 3277.140000 ;
+ RECT 1901.020000 3282.100000 1902.120000 3282.580000 ;
+ RECT 1901.020000 3287.540000 1902.120000 3288.020000 ;
+ RECT 1901.020000 3292.980000 1902.120000 3293.460000 ;
+ RECT 1901.020000 3298.420000 1902.120000 3298.900000 ;
+ RECT 1946.020000 3254.900000 1947.120000 3255.380000 ;
+ RECT 1946.020000 3260.340000 1947.120000 3260.820000 ;
+ RECT 1946.020000 3265.780000 1947.120000 3266.260000 ;
+ RECT 1946.020000 3271.220000 1947.120000 3271.700000 ;
+ RECT 1901.020000 3254.900000 1902.120000 3255.380000 ;
+ RECT 1901.020000 3260.340000 1902.120000 3260.820000 ;
+ RECT 1901.020000 3265.780000 1902.120000 3266.260000 ;
+ RECT 1901.020000 3271.220000 1902.120000 3271.700000 ;
+ RECT 1852.190000 3298.420000 1853.190000 3298.900000 ;
+ RECT 1855.855000 3298.420000 1857.120000 3298.900000 ;
+ RECT 1852.190000 3287.540000 1853.190000 3288.020000 ;
+ RECT 1855.855000 3287.540000 1857.120000 3288.020000 ;
+ RECT 1852.190000 3292.980000 1853.190000 3293.460000 ;
+ RECT 1855.855000 3292.980000 1857.120000 3293.460000 ;
+ RECT 1852.190000 3282.100000 1853.190000 3282.580000 ;
+ RECT 1855.855000 3282.100000 1857.120000 3282.580000 ;
+ RECT 1852.190000 3276.660000 1853.190000 3277.140000 ;
+ RECT 1855.855000 3276.660000 1857.120000 3277.140000 ;
+ RECT 1852.190000 3271.220000 1853.190000 3271.700000 ;
+ RECT 1855.855000 3271.220000 1857.120000 3271.700000 ;
+ RECT 1852.190000 3265.780000 1853.190000 3266.260000 ;
+ RECT 1855.855000 3265.780000 1857.120000 3266.260000 ;
+ RECT 1852.190000 3260.340000 1853.190000 3260.820000 ;
+ RECT 1855.855000 3260.340000 1857.120000 3260.820000 ;
+ RECT 1852.190000 3254.900000 1853.190000 3255.380000 ;
+ RECT 1855.855000 3254.900000 1857.120000 3255.380000 ;
+ RECT 2036.020000 3238.580000 2037.120000 3239.060000 ;
+ RECT 2036.020000 3244.020000 2037.120000 3244.500000 ;
+ RECT 2048.830000 3238.580000 2049.830000 3239.060000 ;
+ RECT 2048.830000 3244.020000 2049.830000 3244.500000 ;
+ RECT 2048.830000 3227.700000 2049.830000 3228.180000 ;
+ RECT 2048.830000 3233.140000 2049.830000 3233.620000 ;
+ RECT 2036.020000 3233.140000 2037.120000 3233.620000 ;
+ RECT 2036.020000 3227.700000 2037.120000 3228.180000 ;
+ RECT 2036.020000 3216.820000 2037.120000 3217.300000 ;
+ RECT 2036.020000 3222.260000 2037.120000 3222.740000 ;
+ RECT 2048.830000 3216.820000 2049.830000 3217.300000 ;
+ RECT 2048.830000 3222.260000 2049.830000 3222.740000 ;
+ RECT 2048.830000 3205.940000 2049.830000 3206.420000 ;
+ RECT 2048.830000 3200.500000 2049.830000 3200.980000 ;
+ RECT 2048.830000 3211.380000 2049.830000 3211.860000 ;
+ RECT 2036.020000 3211.380000 2037.120000 3211.860000 ;
+ RECT 2036.020000 3205.940000 2037.120000 3206.420000 ;
+ RECT 2036.020000 3200.500000 2037.120000 3200.980000 ;
+ RECT 1991.020000 3227.700000 1992.120000 3228.180000 ;
+ RECT 1991.020000 3233.140000 1992.120000 3233.620000 ;
+ RECT 1991.020000 3238.580000 1992.120000 3239.060000 ;
+ RECT 1991.020000 3244.020000 1992.120000 3244.500000 ;
+ RECT 1991.020000 3200.500000 1992.120000 3200.980000 ;
+ RECT 1991.020000 3205.940000 1992.120000 3206.420000 ;
+ RECT 1991.020000 3211.380000 1992.120000 3211.860000 ;
+ RECT 1991.020000 3216.820000 1992.120000 3217.300000 ;
+ RECT 1991.020000 3222.260000 1992.120000 3222.740000 ;
+ RECT 2036.020000 3189.620000 2037.120000 3190.100000 ;
+ RECT 2036.020000 3195.060000 2037.120000 3195.540000 ;
+ RECT 2048.830000 3189.620000 2049.830000 3190.100000 ;
+ RECT 2048.830000 3195.060000 2049.830000 3195.540000 ;
+ RECT 2036.020000 3178.740000 2037.120000 3179.220000 ;
+ RECT 2036.020000 3184.180000 2037.120000 3184.660000 ;
+ RECT 2048.830000 3178.740000 2049.830000 3179.220000 ;
+ RECT 2048.830000 3184.180000 2049.830000 3184.660000 ;
+ RECT 2048.830000 3167.860000 2049.830000 3168.340000 ;
+ RECT 2048.830000 3162.420000 2049.830000 3162.900000 ;
+ RECT 2048.830000 3173.300000 2049.830000 3173.780000 ;
+ RECT 2036.020000 3173.300000 2037.120000 3173.780000 ;
+ RECT 2036.020000 3167.860000 2037.120000 3168.340000 ;
+ RECT 2036.020000 3162.420000 2037.120000 3162.900000 ;
+ RECT 2036.020000 3156.980000 2037.120000 3157.460000 ;
+ RECT 2048.830000 3156.980000 2049.830000 3157.460000 ;
+ RECT 1991.020000 3178.740000 1992.120000 3179.220000 ;
+ RECT 1991.020000 3184.180000 1992.120000 3184.660000 ;
+ RECT 1991.020000 3189.620000 1992.120000 3190.100000 ;
+ RECT 1991.020000 3195.060000 1992.120000 3195.540000 ;
+ RECT 1991.020000 3156.980000 1992.120000 3157.460000 ;
+ RECT 1991.020000 3162.420000 1992.120000 3162.900000 ;
+ RECT 1991.020000 3167.860000 1992.120000 3168.340000 ;
+ RECT 1991.020000 3173.300000 1992.120000 3173.780000 ;
+ RECT 1946.020000 3227.700000 1947.120000 3228.180000 ;
+ RECT 1946.020000 3233.140000 1947.120000 3233.620000 ;
+ RECT 1946.020000 3238.580000 1947.120000 3239.060000 ;
+ RECT 1946.020000 3244.020000 1947.120000 3244.500000 ;
+ RECT 1901.020000 3227.700000 1902.120000 3228.180000 ;
+ RECT 1901.020000 3233.140000 1902.120000 3233.620000 ;
+ RECT 1901.020000 3238.580000 1902.120000 3239.060000 ;
+ RECT 1901.020000 3244.020000 1902.120000 3244.500000 ;
+ RECT 1946.020000 3200.500000 1947.120000 3200.980000 ;
+ RECT 1946.020000 3205.940000 1947.120000 3206.420000 ;
+ RECT 1946.020000 3211.380000 1947.120000 3211.860000 ;
+ RECT 1946.020000 3216.820000 1947.120000 3217.300000 ;
+ RECT 1946.020000 3222.260000 1947.120000 3222.740000 ;
+ RECT 1901.020000 3200.500000 1902.120000 3200.980000 ;
+ RECT 1901.020000 3205.940000 1902.120000 3206.420000 ;
+ RECT 1901.020000 3211.380000 1902.120000 3211.860000 ;
+ RECT 1901.020000 3216.820000 1902.120000 3217.300000 ;
+ RECT 1901.020000 3222.260000 1902.120000 3222.740000 ;
+ RECT 1852.190000 3244.020000 1853.190000 3244.500000 ;
+ RECT 1855.855000 3244.020000 1857.120000 3244.500000 ;
+ RECT 1852.190000 3238.580000 1853.190000 3239.060000 ;
+ RECT 1855.855000 3238.580000 1857.120000 3239.060000 ;
+ RECT 1852.190000 3233.140000 1853.190000 3233.620000 ;
+ RECT 1855.855000 3233.140000 1857.120000 3233.620000 ;
+ RECT 1852.190000 3227.700000 1853.190000 3228.180000 ;
+ RECT 1855.855000 3227.700000 1857.120000 3228.180000 ;
+ RECT 1852.190000 3222.260000 1853.190000 3222.740000 ;
+ RECT 1855.855000 3222.260000 1857.120000 3222.740000 ;
+ RECT 1852.190000 3216.820000 1853.190000 3217.300000 ;
+ RECT 1855.855000 3216.820000 1857.120000 3217.300000 ;
+ RECT 1852.190000 3205.940000 1853.190000 3206.420000 ;
+ RECT 1855.855000 3205.940000 1857.120000 3206.420000 ;
+ RECT 1852.190000 3211.380000 1853.190000 3211.860000 ;
+ RECT 1855.855000 3211.380000 1857.120000 3211.860000 ;
+ RECT 1852.190000 3200.500000 1853.190000 3200.980000 ;
+ RECT 1855.855000 3200.500000 1857.120000 3200.980000 ;
+ RECT 1946.020000 3178.740000 1947.120000 3179.220000 ;
+ RECT 1946.020000 3184.180000 1947.120000 3184.660000 ;
+ RECT 1946.020000 3189.620000 1947.120000 3190.100000 ;
+ RECT 1946.020000 3195.060000 1947.120000 3195.540000 ;
+ RECT 1901.020000 3178.740000 1902.120000 3179.220000 ;
+ RECT 1901.020000 3184.180000 1902.120000 3184.660000 ;
+ RECT 1901.020000 3189.620000 1902.120000 3190.100000 ;
+ RECT 1901.020000 3195.060000 1902.120000 3195.540000 ;
+ RECT 1946.020000 3156.980000 1947.120000 3157.460000 ;
+ RECT 1946.020000 3162.420000 1947.120000 3162.900000 ;
+ RECT 1946.020000 3167.860000 1947.120000 3168.340000 ;
+ RECT 1946.020000 3173.300000 1947.120000 3173.780000 ;
+ RECT 1901.020000 3156.980000 1902.120000 3157.460000 ;
+ RECT 1901.020000 3162.420000 1902.120000 3162.900000 ;
+ RECT 1901.020000 3167.860000 1902.120000 3168.340000 ;
+ RECT 1901.020000 3173.300000 1902.120000 3173.780000 ;
+ RECT 1852.190000 3195.060000 1853.190000 3195.540000 ;
+ RECT 1855.855000 3195.060000 1857.120000 3195.540000 ;
+ RECT 1852.190000 3189.620000 1853.190000 3190.100000 ;
+ RECT 1855.855000 3189.620000 1857.120000 3190.100000 ;
+ RECT 1852.190000 3184.180000 1853.190000 3184.660000 ;
+ RECT 1855.855000 3184.180000 1857.120000 3184.660000 ;
+ RECT 1852.190000 3178.740000 1853.190000 3179.220000 ;
+ RECT 1855.855000 3178.740000 1857.120000 3179.220000 ;
+ RECT 1852.190000 3173.300000 1853.190000 3173.780000 ;
+ RECT 1855.855000 3173.300000 1857.120000 3173.780000 ;
+ RECT 1852.190000 3162.420000 1853.190000 3162.900000 ;
+ RECT 1855.855000 3162.420000 1857.120000 3162.900000 ;
+ RECT 1852.190000 3167.860000 1853.190000 3168.340000 ;
+ RECT 1855.855000 3167.860000 1857.120000 3168.340000 ;
+ RECT 1852.190000 3156.980000 1853.190000 3157.460000 ;
+ RECT 1855.855000 3156.980000 1857.120000 3157.460000 ;
+ RECT 1991.020000 3249.460000 1992.120000 3249.940000 ;
+ RECT 2036.020000 3249.460000 2037.120000 3249.940000 ;
+ RECT 2048.830000 3249.460000 2049.830000 3249.940000 ;
+ RECT 1901.020000 3249.460000 1902.120000 3249.940000 ;
+ RECT 1946.020000 3249.460000 1947.120000 3249.940000 ;
+ RECT 1852.190000 3249.460000 1853.190000 3249.940000 ;
+ RECT 1855.855000 3249.460000 1857.120000 3249.940000 ;
+ RECT 1850.960000 3346.220000 2051.060000 3347.220000 ;
+ RECT 1850.960000 3150.650000 2051.060000 3151.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 3149.400000 1853.190000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 3348.660000 1853.190000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 3149.400000 2049.830000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 3348.660000 2049.830000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 3150.650000 1851.960000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 3150.650000 2051.060000 3151.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 3346.220000 1851.960000 3347.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 3346.220000 2051.060000 3347.220000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 3141.680000 1857.120000 3142.160000 ;
+ RECT 1855.855000 3130.800000 1857.120000 3131.280000 ;
+ RECT 1855.855000 3136.240000 1857.120000 3136.720000 ;
+ RECT 1855.855000 3125.360000 1857.120000 3125.840000 ;
+ RECT 1855.855000 3119.920000 1857.120000 3120.400000 ;
+ RECT 1855.855000 3114.480000 1857.120000 3114.960000 ;
+ RECT 1855.855000 3109.040000 1857.120000 3109.520000 ;
+ RECT 1855.855000 3103.600000 1857.120000 3104.080000 ;
+ RECT 1855.855000 3098.160000 1857.120000 3098.640000 ;
+ RECT 1855.855000 3087.280000 1857.120000 3087.760000 ;
+ RECT 1855.855000 3092.720000 1857.120000 3093.200000 ;
+ RECT 1855.855000 3081.840000 1857.120000 3082.320000 ;
+ RECT 1855.855000 3076.400000 1857.120000 3076.880000 ;
+ RECT 1855.855000 3070.960000 1857.120000 3071.440000 ;
+ RECT 1855.855000 3065.520000 1857.120000 3066.000000 ;
+ RECT 1855.855000 3060.080000 1857.120000 3060.560000 ;
+ RECT 1855.855000 3054.640000 1857.120000 3055.120000 ;
+ RECT 1855.855000 3043.760000 1857.120000 3044.240000 ;
+ RECT 1855.855000 3038.320000 1857.120000 3038.800000 ;
+ RECT 1855.855000 3032.880000 1857.120000 3033.360000 ;
+ RECT 1855.855000 3027.440000 1857.120000 3027.920000 ;
+ RECT 1855.855000 3022.000000 1857.120000 3022.480000 ;
+ RECT 1855.855000 3016.560000 1857.120000 3017.040000 ;
+ RECT 1855.855000 3005.680000 1857.120000 3006.160000 ;
+ RECT 1855.855000 3011.120000 1857.120000 3011.600000 ;
+ RECT 1855.855000 3000.240000 1857.120000 3000.720000 ;
+ RECT 1855.855000 2994.800000 1857.120000 2995.280000 ;
+ RECT 1855.855000 2989.360000 1857.120000 2989.840000 ;
+ RECT 1855.855000 2983.920000 1857.120000 2984.400000 ;
+ RECT 1855.855000 2978.480000 1857.120000 2978.960000 ;
+ RECT 1855.855000 2973.040000 1857.120000 2973.520000 ;
+ RECT 1855.855000 2962.160000 1857.120000 2962.640000 ;
+ RECT 1855.855000 2967.600000 1857.120000 2968.080000 ;
+ RECT 1855.855000 2956.720000 1857.120000 2957.200000 ;
+ RECT 1855.855000 3049.200000 1857.120000 3049.680000 ;
+ RECT 2036.020000 2950.390000 2037.120000 3146.960000 ;
+ RECT 1991.020000 2950.390000 1992.120000 3146.960000 ;
+ RECT 2048.830000 2949.140000 2049.830000 3149.400000 ;
+ RECT 1946.020000 2950.390000 1947.120000 3146.960000 ;
+ RECT 1901.020000 2950.390000 1902.120000 3146.960000 ;
+ RECT 1856.020000 2950.390000 1857.120000 3146.960000 ;
+ RECT 1852.190000 2949.140000 1853.190000 3149.400000 ;
+ LAYER met3 ;
+ RECT 2036.020000 3141.680000 2037.120000 3142.160000 ;
+ RECT 2048.830000 3141.680000 2049.830000 3142.160000 ;
+ RECT 2048.830000 3130.800000 2049.830000 3131.280000 ;
+ RECT 2048.830000 3125.360000 2049.830000 3125.840000 ;
+ RECT 2048.830000 3136.240000 2049.830000 3136.720000 ;
+ RECT 2036.020000 3136.240000 2037.120000 3136.720000 ;
+ RECT 2036.020000 3130.800000 2037.120000 3131.280000 ;
+ RECT 2036.020000 3125.360000 2037.120000 3125.840000 ;
+ RECT 2036.020000 3114.480000 2037.120000 3114.960000 ;
+ RECT 2036.020000 3119.920000 2037.120000 3120.400000 ;
+ RECT 2048.830000 3114.480000 2049.830000 3114.960000 ;
+ RECT 2048.830000 3119.920000 2049.830000 3120.400000 ;
+ RECT 2036.020000 3103.600000 2037.120000 3104.080000 ;
+ RECT 2036.020000 3109.040000 2037.120000 3109.520000 ;
+ RECT 2048.830000 3103.600000 2049.830000 3104.080000 ;
+ RECT 2048.830000 3109.040000 2049.830000 3109.520000 ;
+ RECT 1991.020000 3125.360000 1992.120000 3125.840000 ;
+ RECT 1991.020000 3130.800000 1992.120000 3131.280000 ;
+ RECT 1991.020000 3136.240000 1992.120000 3136.720000 ;
+ RECT 1991.020000 3141.680000 1992.120000 3142.160000 ;
+ RECT 1991.020000 3109.040000 1992.120000 3109.520000 ;
+ RECT 1991.020000 3103.600000 1992.120000 3104.080000 ;
+ RECT 1991.020000 3114.480000 1992.120000 3114.960000 ;
+ RECT 1991.020000 3119.920000 1992.120000 3120.400000 ;
+ RECT 2048.830000 3092.720000 2049.830000 3093.200000 ;
+ RECT 2048.830000 3087.280000 2049.830000 3087.760000 ;
+ RECT 2048.830000 3098.160000 2049.830000 3098.640000 ;
+ RECT 2036.020000 3098.160000 2037.120000 3098.640000 ;
+ RECT 2036.020000 3092.720000 2037.120000 3093.200000 ;
+ RECT 2036.020000 3087.280000 2037.120000 3087.760000 ;
+ RECT 2036.020000 3076.400000 2037.120000 3076.880000 ;
+ RECT 2036.020000 3081.840000 2037.120000 3082.320000 ;
+ RECT 2048.830000 3076.400000 2049.830000 3076.880000 ;
+ RECT 2048.830000 3081.840000 2049.830000 3082.320000 ;
+ RECT 2048.830000 3065.520000 2049.830000 3066.000000 ;
+ RECT 2048.830000 3070.960000 2049.830000 3071.440000 ;
+ RECT 2036.020000 3070.960000 2037.120000 3071.440000 ;
+ RECT 2036.020000 3065.520000 2037.120000 3066.000000 ;
+ RECT 2036.020000 3054.640000 2037.120000 3055.120000 ;
+ RECT 2036.020000 3060.080000 2037.120000 3060.560000 ;
+ RECT 2048.830000 3054.640000 2049.830000 3055.120000 ;
+ RECT 2048.830000 3060.080000 2049.830000 3060.560000 ;
+ RECT 1991.020000 3076.400000 1992.120000 3076.880000 ;
+ RECT 1991.020000 3081.840000 1992.120000 3082.320000 ;
+ RECT 1991.020000 3087.280000 1992.120000 3087.760000 ;
+ RECT 1991.020000 3092.720000 1992.120000 3093.200000 ;
+ RECT 1991.020000 3098.160000 1992.120000 3098.640000 ;
+ RECT 1991.020000 3054.640000 1992.120000 3055.120000 ;
+ RECT 1991.020000 3060.080000 1992.120000 3060.560000 ;
+ RECT 1991.020000 3065.520000 1992.120000 3066.000000 ;
+ RECT 1991.020000 3070.960000 1992.120000 3071.440000 ;
+ RECT 1946.020000 3130.800000 1947.120000 3131.280000 ;
+ RECT 1946.020000 3125.360000 1947.120000 3125.840000 ;
+ RECT 1946.020000 3136.240000 1947.120000 3136.720000 ;
+ RECT 1946.020000 3141.680000 1947.120000 3142.160000 ;
+ RECT 1901.020000 3125.360000 1902.120000 3125.840000 ;
+ RECT 1901.020000 3130.800000 1902.120000 3131.280000 ;
+ RECT 1901.020000 3136.240000 1902.120000 3136.720000 ;
+ RECT 1901.020000 3141.680000 1902.120000 3142.160000 ;
+ RECT 1946.020000 3103.600000 1947.120000 3104.080000 ;
+ RECT 1946.020000 3109.040000 1947.120000 3109.520000 ;
+ RECT 1946.020000 3114.480000 1947.120000 3114.960000 ;
+ RECT 1946.020000 3119.920000 1947.120000 3120.400000 ;
+ RECT 1901.020000 3103.600000 1902.120000 3104.080000 ;
+ RECT 1901.020000 3109.040000 1902.120000 3109.520000 ;
+ RECT 1901.020000 3114.480000 1902.120000 3114.960000 ;
+ RECT 1901.020000 3119.920000 1902.120000 3120.400000 ;
+ RECT 1852.190000 3141.680000 1853.190000 3142.160000 ;
+ RECT 1855.855000 3141.680000 1857.120000 3142.160000 ;
+ RECT 1852.190000 3130.800000 1853.190000 3131.280000 ;
+ RECT 1855.855000 3130.800000 1857.120000 3131.280000 ;
+ RECT 1852.190000 3136.240000 1853.190000 3136.720000 ;
+ RECT 1855.855000 3136.240000 1857.120000 3136.720000 ;
+ RECT 1852.190000 3125.360000 1853.190000 3125.840000 ;
+ RECT 1855.855000 3125.360000 1857.120000 3125.840000 ;
+ RECT 1852.190000 3119.920000 1853.190000 3120.400000 ;
+ RECT 1855.855000 3119.920000 1857.120000 3120.400000 ;
+ RECT 1852.190000 3114.480000 1853.190000 3114.960000 ;
+ RECT 1855.855000 3114.480000 1857.120000 3114.960000 ;
+ RECT 1852.190000 3109.040000 1853.190000 3109.520000 ;
+ RECT 1855.855000 3109.040000 1857.120000 3109.520000 ;
+ RECT 1852.190000 3103.600000 1853.190000 3104.080000 ;
+ RECT 1855.855000 3103.600000 1857.120000 3104.080000 ;
+ RECT 1946.020000 3076.400000 1947.120000 3076.880000 ;
+ RECT 1946.020000 3081.840000 1947.120000 3082.320000 ;
+ RECT 1946.020000 3087.280000 1947.120000 3087.760000 ;
+ RECT 1946.020000 3092.720000 1947.120000 3093.200000 ;
+ RECT 1946.020000 3098.160000 1947.120000 3098.640000 ;
+ RECT 1901.020000 3076.400000 1902.120000 3076.880000 ;
+ RECT 1901.020000 3081.840000 1902.120000 3082.320000 ;
+ RECT 1901.020000 3087.280000 1902.120000 3087.760000 ;
+ RECT 1901.020000 3092.720000 1902.120000 3093.200000 ;
+ RECT 1901.020000 3098.160000 1902.120000 3098.640000 ;
+ RECT 1946.020000 3054.640000 1947.120000 3055.120000 ;
+ RECT 1946.020000 3060.080000 1947.120000 3060.560000 ;
+ RECT 1946.020000 3065.520000 1947.120000 3066.000000 ;
+ RECT 1946.020000 3070.960000 1947.120000 3071.440000 ;
+ RECT 1901.020000 3054.640000 1902.120000 3055.120000 ;
+ RECT 1901.020000 3060.080000 1902.120000 3060.560000 ;
+ RECT 1901.020000 3065.520000 1902.120000 3066.000000 ;
+ RECT 1901.020000 3070.960000 1902.120000 3071.440000 ;
+ RECT 1852.190000 3098.160000 1853.190000 3098.640000 ;
+ RECT 1855.855000 3098.160000 1857.120000 3098.640000 ;
+ RECT 1852.190000 3087.280000 1853.190000 3087.760000 ;
+ RECT 1855.855000 3087.280000 1857.120000 3087.760000 ;
+ RECT 1852.190000 3092.720000 1853.190000 3093.200000 ;
+ RECT 1855.855000 3092.720000 1857.120000 3093.200000 ;
+ RECT 1852.190000 3081.840000 1853.190000 3082.320000 ;
+ RECT 1855.855000 3081.840000 1857.120000 3082.320000 ;
+ RECT 1852.190000 3076.400000 1853.190000 3076.880000 ;
+ RECT 1855.855000 3076.400000 1857.120000 3076.880000 ;
+ RECT 1852.190000 3070.960000 1853.190000 3071.440000 ;
+ RECT 1855.855000 3070.960000 1857.120000 3071.440000 ;
+ RECT 1852.190000 3065.520000 1853.190000 3066.000000 ;
+ RECT 1855.855000 3065.520000 1857.120000 3066.000000 ;
+ RECT 1852.190000 3060.080000 1853.190000 3060.560000 ;
+ RECT 1855.855000 3060.080000 1857.120000 3060.560000 ;
+ RECT 1852.190000 3054.640000 1853.190000 3055.120000 ;
+ RECT 1855.855000 3054.640000 1857.120000 3055.120000 ;
+ RECT 2036.020000 3038.320000 2037.120000 3038.800000 ;
+ RECT 2036.020000 3043.760000 2037.120000 3044.240000 ;
+ RECT 2048.830000 3038.320000 2049.830000 3038.800000 ;
+ RECT 2048.830000 3043.760000 2049.830000 3044.240000 ;
+ RECT 2048.830000 3027.440000 2049.830000 3027.920000 ;
+ RECT 2048.830000 3032.880000 2049.830000 3033.360000 ;
+ RECT 2036.020000 3032.880000 2037.120000 3033.360000 ;
+ RECT 2036.020000 3027.440000 2037.120000 3027.920000 ;
+ RECT 2036.020000 3016.560000 2037.120000 3017.040000 ;
+ RECT 2036.020000 3022.000000 2037.120000 3022.480000 ;
+ RECT 2048.830000 3016.560000 2049.830000 3017.040000 ;
+ RECT 2048.830000 3022.000000 2049.830000 3022.480000 ;
+ RECT 2048.830000 3005.680000 2049.830000 3006.160000 ;
+ RECT 2048.830000 3000.240000 2049.830000 3000.720000 ;
+ RECT 2048.830000 3011.120000 2049.830000 3011.600000 ;
+ RECT 2036.020000 3011.120000 2037.120000 3011.600000 ;
+ RECT 2036.020000 3005.680000 2037.120000 3006.160000 ;
+ RECT 2036.020000 3000.240000 2037.120000 3000.720000 ;
+ RECT 1991.020000 3027.440000 1992.120000 3027.920000 ;
+ RECT 1991.020000 3032.880000 1992.120000 3033.360000 ;
+ RECT 1991.020000 3038.320000 1992.120000 3038.800000 ;
+ RECT 1991.020000 3043.760000 1992.120000 3044.240000 ;
+ RECT 1991.020000 3000.240000 1992.120000 3000.720000 ;
+ RECT 1991.020000 3005.680000 1992.120000 3006.160000 ;
+ RECT 1991.020000 3011.120000 1992.120000 3011.600000 ;
+ RECT 1991.020000 3016.560000 1992.120000 3017.040000 ;
+ RECT 1991.020000 3022.000000 1992.120000 3022.480000 ;
+ RECT 2036.020000 2989.360000 2037.120000 2989.840000 ;
+ RECT 2036.020000 2994.800000 2037.120000 2995.280000 ;
+ RECT 2048.830000 2989.360000 2049.830000 2989.840000 ;
+ RECT 2048.830000 2994.800000 2049.830000 2995.280000 ;
+ RECT 2036.020000 2978.480000 2037.120000 2978.960000 ;
+ RECT 2036.020000 2983.920000 2037.120000 2984.400000 ;
+ RECT 2048.830000 2978.480000 2049.830000 2978.960000 ;
+ RECT 2048.830000 2983.920000 2049.830000 2984.400000 ;
+ RECT 2048.830000 2967.600000 2049.830000 2968.080000 ;
+ RECT 2048.830000 2962.160000 2049.830000 2962.640000 ;
+ RECT 2048.830000 2973.040000 2049.830000 2973.520000 ;
+ RECT 2036.020000 2973.040000 2037.120000 2973.520000 ;
+ RECT 2036.020000 2967.600000 2037.120000 2968.080000 ;
+ RECT 2036.020000 2962.160000 2037.120000 2962.640000 ;
+ RECT 2036.020000 2956.720000 2037.120000 2957.200000 ;
+ RECT 2048.830000 2956.720000 2049.830000 2957.200000 ;
+ RECT 1991.020000 2978.480000 1992.120000 2978.960000 ;
+ RECT 1991.020000 2983.920000 1992.120000 2984.400000 ;
+ RECT 1991.020000 2989.360000 1992.120000 2989.840000 ;
+ RECT 1991.020000 2994.800000 1992.120000 2995.280000 ;
+ RECT 1991.020000 2956.720000 1992.120000 2957.200000 ;
+ RECT 1991.020000 2962.160000 1992.120000 2962.640000 ;
+ RECT 1991.020000 2967.600000 1992.120000 2968.080000 ;
+ RECT 1991.020000 2973.040000 1992.120000 2973.520000 ;
+ RECT 1946.020000 3027.440000 1947.120000 3027.920000 ;
+ RECT 1946.020000 3032.880000 1947.120000 3033.360000 ;
+ RECT 1946.020000 3038.320000 1947.120000 3038.800000 ;
+ RECT 1946.020000 3043.760000 1947.120000 3044.240000 ;
+ RECT 1901.020000 3027.440000 1902.120000 3027.920000 ;
+ RECT 1901.020000 3032.880000 1902.120000 3033.360000 ;
+ RECT 1901.020000 3038.320000 1902.120000 3038.800000 ;
+ RECT 1901.020000 3043.760000 1902.120000 3044.240000 ;
+ RECT 1946.020000 3000.240000 1947.120000 3000.720000 ;
+ RECT 1946.020000 3005.680000 1947.120000 3006.160000 ;
+ RECT 1946.020000 3011.120000 1947.120000 3011.600000 ;
+ RECT 1946.020000 3016.560000 1947.120000 3017.040000 ;
+ RECT 1946.020000 3022.000000 1947.120000 3022.480000 ;
+ RECT 1901.020000 3000.240000 1902.120000 3000.720000 ;
+ RECT 1901.020000 3005.680000 1902.120000 3006.160000 ;
+ RECT 1901.020000 3011.120000 1902.120000 3011.600000 ;
+ RECT 1901.020000 3016.560000 1902.120000 3017.040000 ;
+ RECT 1901.020000 3022.000000 1902.120000 3022.480000 ;
+ RECT 1852.190000 3043.760000 1853.190000 3044.240000 ;
+ RECT 1855.855000 3043.760000 1857.120000 3044.240000 ;
+ RECT 1852.190000 3038.320000 1853.190000 3038.800000 ;
+ RECT 1855.855000 3038.320000 1857.120000 3038.800000 ;
+ RECT 1852.190000 3032.880000 1853.190000 3033.360000 ;
+ RECT 1855.855000 3032.880000 1857.120000 3033.360000 ;
+ RECT 1852.190000 3027.440000 1853.190000 3027.920000 ;
+ RECT 1855.855000 3027.440000 1857.120000 3027.920000 ;
+ RECT 1852.190000 3022.000000 1853.190000 3022.480000 ;
+ RECT 1855.855000 3022.000000 1857.120000 3022.480000 ;
+ RECT 1852.190000 3016.560000 1853.190000 3017.040000 ;
+ RECT 1855.855000 3016.560000 1857.120000 3017.040000 ;
+ RECT 1852.190000 3005.680000 1853.190000 3006.160000 ;
+ RECT 1855.855000 3005.680000 1857.120000 3006.160000 ;
+ RECT 1852.190000 3011.120000 1853.190000 3011.600000 ;
+ RECT 1855.855000 3011.120000 1857.120000 3011.600000 ;
+ RECT 1852.190000 3000.240000 1853.190000 3000.720000 ;
+ RECT 1855.855000 3000.240000 1857.120000 3000.720000 ;
+ RECT 1946.020000 2978.480000 1947.120000 2978.960000 ;
+ RECT 1946.020000 2983.920000 1947.120000 2984.400000 ;
+ RECT 1946.020000 2989.360000 1947.120000 2989.840000 ;
+ RECT 1946.020000 2994.800000 1947.120000 2995.280000 ;
+ RECT 1901.020000 2978.480000 1902.120000 2978.960000 ;
+ RECT 1901.020000 2983.920000 1902.120000 2984.400000 ;
+ RECT 1901.020000 2989.360000 1902.120000 2989.840000 ;
+ RECT 1901.020000 2994.800000 1902.120000 2995.280000 ;
+ RECT 1946.020000 2956.720000 1947.120000 2957.200000 ;
+ RECT 1946.020000 2962.160000 1947.120000 2962.640000 ;
+ RECT 1946.020000 2967.600000 1947.120000 2968.080000 ;
+ RECT 1946.020000 2973.040000 1947.120000 2973.520000 ;
+ RECT 1901.020000 2956.720000 1902.120000 2957.200000 ;
+ RECT 1901.020000 2962.160000 1902.120000 2962.640000 ;
+ RECT 1901.020000 2967.600000 1902.120000 2968.080000 ;
+ RECT 1901.020000 2973.040000 1902.120000 2973.520000 ;
+ RECT 1852.190000 2994.800000 1853.190000 2995.280000 ;
+ RECT 1855.855000 2994.800000 1857.120000 2995.280000 ;
+ RECT 1852.190000 2989.360000 1853.190000 2989.840000 ;
+ RECT 1855.855000 2989.360000 1857.120000 2989.840000 ;
+ RECT 1852.190000 2983.920000 1853.190000 2984.400000 ;
+ RECT 1855.855000 2983.920000 1857.120000 2984.400000 ;
+ RECT 1852.190000 2978.480000 1853.190000 2978.960000 ;
+ RECT 1855.855000 2978.480000 1857.120000 2978.960000 ;
+ RECT 1852.190000 2973.040000 1853.190000 2973.520000 ;
+ RECT 1855.855000 2973.040000 1857.120000 2973.520000 ;
+ RECT 1852.190000 2962.160000 1853.190000 2962.640000 ;
+ RECT 1855.855000 2962.160000 1857.120000 2962.640000 ;
+ RECT 1852.190000 2967.600000 1853.190000 2968.080000 ;
+ RECT 1855.855000 2967.600000 1857.120000 2968.080000 ;
+ RECT 1852.190000 2956.720000 1853.190000 2957.200000 ;
+ RECT 1855.855000 2956.720000 1857.120000 2957.200000 ;
+ RECT 1991.020000 3049.200000 1992.120000 3049.680000 ;
+ RECT 2036.020000 3049.200000 2037.120000 3049.680000 ;
+ RECT 2048.830000 3049.200000 2049.830000 3049.680000 ;
+ RECT 1901.020000 3049.200000 1902.120000 3049.680000 ;
+ RECT 1946.020000 3049.200000 1947.120000 3049.680000 ;
+ RECT 1852.190000 3049.200000 1853.190000 3049.680000 ;
+ RECT 1855.855000 3049.200000 1857.120000 3049.680000 ;
+ RECT 1850.960000 3145.960000 2051.060000 3146.960000 ;
+ RECT 1850.960000 2950.390000 2051.060000 2951.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 2949.140000 1853.190000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 3148.400000 1853.190000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 2949.140000 2049.830000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 3148.400000 2049.830000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2950.390000 1851.960000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2950.390000 2051.060000 2951.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 3145.960000 1851.960000 3146.960000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 3145.960000 2051.060000 3146.960000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 2941.420000 1857.120000 2941.900000 ;
+ RECT 1855.855000 2930.540000 1857.120000 2931.020000 ;
+ RECT 1855.855000 2935.980000 1857.120000 2936.460000 ;
+ RECT 1855.855000 2925.100000 1857.120000 2925.580000 ;
+ RECT 1855.855000 2919.660000 1857.120000 2920.140000 ;
+ RECT 1855.855000 2914.220000 1857.120000 2914.700000 ;
+ RECT 1855.855000 2908.780000 1857.120000 2909.260000 ;
+ RECT 1855.855000 2903.340000 1857.120000 2903.820000 ;
+ RECT 1855.855000 2897.900000 1857.120000 2898.380000 ;
+ RECT 1855.855000 2887.020000 1857.120000 2887.500000 ;
+ RECT 1855.855000 2892.460000 1857.120000 2892.940000 ;
+ RECT 1855.855000 2881.580000 1857.120000 2882.060000 ;
+ RECT 1855.855000 2876.140000 1857.120000 2876.620000 ;
+ RECT 1855.855000 2870.700000 1857.120000 2871.180000 ;
+ RECT 1855.855000 2865.260000 1857.120000 2865.740000 ;
+ RECT 1855.855000 2859.820000 1857.120000 2860.300000 ;
+ RECT 1855.855000 2854.380000 1857.120000 2854.860000 ;
+ RECT 1855.855000 2843.500000 1857.120000 2843.980000 ;
+ RECT 1855.855000 2838.060000 1857.120000 2838.540000 ;
+ RECT 1855.855000 2832.620000 1857.120000 2833.100000 ;
+ RECT 1855.855000 2827.180000 1857.120000 2827.660000 ;
+ RECT 1855.855000 2821.740000 1857.120000 2822.220000 ;
+ RECT 1855.855000 2816.300000 1857.120000 2816.780000 ;
+ RECT 1855.855000 2805.420000 1857.120000 2805.900000 ;
+ RECT 1855.855000 2810.860000 1857.120000 2811.340000 ;
+ RECT 1855.855000 2799.980000 1857.120000 2800.460000 ;
+ RECT 1855.855000 2794.540000 1857.120000 2795.020000 ;
+ RECT 1855.855000 2789.100000 1857.120000 2789.580000 ;
+ RECT 1855.855000 2783.660000 1857.120000 2784.140000 ;
+ RECT 1855.855000 2778.220000 1857.120000 2778.700000 ;
+ RECT 1855.855000 2772.780000 1857.120000 2773.260000 ;
+ RECT 1855.855000 2761.900000 1857.120000 2762.380000 ;
+ RECT 1855.855000 2767.340000 1857.120000 2767.820000 ;
+ RECT 1855.855000 2756.460000 1857.120000 2756.940000 ;
+ RECT 1855.855000 2848.940000 1857.120000 2849.420000 ;
+ RECT 2036.020000 2750.130000 2037.120000 2946.700000 ;
+ RECT 1991.020000 2750.130000 1992.120000 2946.700000 ;
+ RECT 2048.830000 2748.880000 2049.830000 2949.140000 ;
+ RECT 1946.020000 2750.130000 1947.120000 2946.700000 ;
+ RECT 1901.020000 2750.130000 1902.120000 2946.700000 ;
+ RECT 1856.020000 2750.130000 1857.120000 2946.700000 ;
+ RECT 1852.190000 2748.880000 1853.190000 2949.140000 ;
+ LAYER met3 ;
+ RECT 2036.020000 2941.420000 2037.120000 2941.900000 ;
+ RECT 2048.830000 2941.420000 2049.830000 2941.900000 ;
+ RECT 2048.830000 2930.540000 2049.830000 2931.020000 ;
+ RECT 2048.830000 2925.100000 2049.830000 2925.580000 ;
+ RECT 2048.830000 2935.980000 2049.830000 2936.460000 ;
+ RECT 2036.020000 2935.980000 2037.120000 2936.460000 ;
+ RECT 2036.020000 2930.540000 2037.120000 2931.020000 ;
+ RECT 2036.020000 2925.100000 2037.120000 2925.580000 ;
+ RECT 2036.020000 2914.220000 2037.120000 2914.700000 ;
+ RECT 2036.020000 2919.660000 2037.120000 2920.140000 ;
+ RECT 2048.830000 2914.220000 2049.830000 2914.700000 ;
+ RECT 2048.830000 2919.660000 2049.830000 2920.140000 ;
+ RECT 2036.020000 2903.340000 2037.120000 2903.820000 ;
+ RECT 2036.020000 2908.780000 2037.120000 2909.260000 ;
+ RECT 2048.830000 2903.340000 2049.830000 2903.820000 ;
+ RECT 2048.830000 2908.780000 2049.830000 2909.260000 ;
+ RECT 1991.020000 2925.100000 1992.120000 2925.580000 ;
+ RECT 1991.020000 2930.540000 1992.120000 2931.020000 ;
+ RECT 1991.020000 2935.980000 1992.120000 2936.460000 ;
+ RECT 1991.020000 2941.420000 1992.120000 2941.900000 ;
+ RECT 1991.020000 2908.780000 1992.120000 2909.260000 ;
+ RECT 1991.020000 2903.340000 1992.120000 2903.820000 ;
+ RECT 1991.020000 2914.220000 1992.120000 2914.700000 ;
+ RECT 1991.020000 2919.660000 1992.120000 2920.140000 ;
+ RECT 2048.830000 2892.460000 2049.830000 2892.940000 ;
+ RECT 2048.830000 2887.020000 2049.830000 2887.500000 ;
+ RECT 2048.830000 2897.900000 2049.830000 2898.380000 ;
+ RECT 2036.020000 2897.900000 2037.120000 2898.380000 ;
+ RECT 2036.020000 2892.460000 2037.120000 2892.940000 ;
+ RECT 2036.020000 2887.020000 2037.120000 2887.500000 ;
+ RECT 2036.020000 2876.140000 2037.120000 2876.620000 ;
+ RECT 2036.020000 2881.580000 2037.120000 2882.060000 ;
+ RECT 2048.830000 2876.140000 2049.830000 2876.620000 ;
+ RECT 2048.830000 2881.580000 2049.830000 2882.060000 ;
+ RECT 2048.830000 2865.260000 2049.830000 2865.740000 ;
+ RECT 2048.830000 2870.700000 2049.830000 2871.180000 ;
+ RECT 2036.020000 2870.700000 2037.120000 2871.180000 ;
+ RECT 2036.020000 2865.260000 2037.120000 2865.740000 ;
+ RECT 2036.020000 2854.380000 2037.120000 2854.860000 ;
+ RECT 2036.020000 2859.820000 2037.120000 2860.300000 ;
+ RECT 2048.830000 2854.380000 2049.830000 2854.860000 ;
+ RECT 2048.830000 2859.820000 2049.830000 2860.300000 ;
+ RECT 1991.020000 2876.140000 1992.120000 2876.620000 ;
+ RECT 1991.020000 2881.580000 1992.120000 2882.060000 ;
+ RECT 1991.020000 2887.020000 1992.120000 2887.500000 ;
+ RECT 1991.020000 2892.460000 1992.120000 2892.940000 ;
+ RECT 1991.020000 2897.900000 1992.120000 2898.380000 ;
+ RECT 1991.020000 2854.380000 1992.120000 2854.860000 ;
+ RECT 1991.020000 2859.820000 1992.120000 2860.300000 ;
+ RECT 1991.020000 2865.260000 1992.120000 2865.740000 ;
+ RECT 1991.020000 2870.700000 1992.120000 2871.180000 ;
+ RECT 1946.020000 2930.540000 1947.120000 2931.020000 ;
+ RECT 1946.020000 2925.100000 1947.120000 2925.580000 ;
+ RECT 1946.020000 2935.980000 1947.120000 2936.460000 ;
+ RECT 1946.020000 2941.420000 1947.120000 2941.900000 ;
+ RECT 1901.020000 2925.100000 1902.120000 2925.580000 ;
+ RECT 1901.020000 2930.540000 1902.120000 2931.020000 ;
+ RECT 1901.020000 2935.980000 1902.120000 2936.460000 ;
+ RECT 1901.020000 2941.420000 1902.120000 2941.900000 ;
+ RECT 1946.020000 2903.340000 1947.120000 2903.820000 ;
+ RECT 1946.020000 2908.780000 1947.120000 2909.260000 ;
+ RECT 1946.020000 2914.220000 1947.120000 2914.700000 ;
+ RECT 1946.020000 2919.660000 1947.120000 2920.140000 ;
+ RECT 1901.020000 2903.340000 1902.120000 2903.820000 ;
+ RECT 1901.020000 2908.780000 1902.120000 2909.260000 ;
+ RECT 1901.020000 2914.220000 1902.120000 2914.700000 ;
+ RECT 1901.020000 2919.660000 1902.120000 2920.140000 ;
+ RECT 1852.190000 2941.420000 1853.190000 2941.900000 ;
+ RECT 1855.855000 2941.420000 1857.120000 2941.900000 ;
+ RECT 1852.190000 2930.540000 1853.190000 2931.020000 ;
+ RECT 1855.855000 2930.540000 1857.120000 2931.020000 ;
+ RECT 1852.190000 2935.980000 1853.190000 2936.460000 ;
+ RECT 1855.855000 2935.980000 1857.120000 2936.460000 ;
+ RECT 1852.190000 2925.100000 1853.190000 2925.580000 ;
+ RECT 1855.855000 2925.100000 1857.120000 2925.580000 ;
+ RECT 1852.190000 2919.660000 1853.190000 2920.140000 ;
+ RECT 1855.855000 2919.660000 1857.120000 2920.140000 ;
+ RECT 1852.190000 2914.220000 1853.190000 2914.700000 ;
+ RECT 1855.855000 2914.220000 1857.120000 2914.700000 ;
+ RECT 1852.190000 2908.780000 1853.190000 2909.260000 ;
+ RECT 1855.855000 2908.780000 1857.120000 2909.260000 ;
+ RECT 1852.190000 2903.340000 1853.190000 2903.820000 ;
+ RECT 1855.855000 2903.340000 1857.120000 2903.820000 ;
+ RECT 1946.020000 2876.140000 1947.120000 2876.620000 ;
+ RECT 1946.020000 2881.580000 1947.120000 2882.060000 ;
+ RECT 1946.020000 2887.020000 1947.120000 2887.500000 ;
+ RECT 1946.020000 2892.460000 1947.120000 2892.940000 ;
+ RECT 1946.020000 2897.900000 1947.120000 2898.380000 ;
+ RECT 1901.020000 2876.140000 1902.120000 2876.620000 ;
+ RECT 1901.020000 2881.580000 1902.120000 2882.060000 ;
+ RECT 1901.020000 2887.020000 1902.120000 2887.500000 ;
+ RECT 1901.020000 2892.460000 1902.120000 2892.940000 ;
+ RECT 1901.020000 2897.900000 1902.120000 2898.380000 ;
+ RECT 1946.020000 2854.380000 1947.120000 2854.860000 ;
+ RECT 1946.020000 2859.820000 1947.120000 2860.300000 ;
+ RECT 1946.020000 2865.260000 1947.120000 2865.740000 ;
+ RECT 1946.020000 2870.700000 1947.120000 2871.180000 ;
+ RECT 1901.020000 2854.380000 1902.120000 2854.860000 ;
+ RECT 1901.020000 2859.820000 1902.120000 2860.300000 ;
+ RECT 1901.020000 2865.260000 1902.120000 2865.740000 ;
+ RECT 1901.020000 2870.700000 1902.120000 2871.180000 ;
+ RECT 1852.190000 2897.900000 1853.190000 2898.380000 ;
+ RECT 1855.855000 2897.900000 1857.120000 2898.380000 ;
+ RECT 1852.190000 2887.020000 1853.190000 2887.500000 ;
+ RECT 1855.855000 2887.020000 1857.120000 2887.500000 ;
+ RECT 1852.190000 2892.460000 1853.190000 2892.940000 ;
+ RECT 1855.855000 2892.460000 1857.120000 2892.940000 ;
+ RECT 1852.190000 2881.580000 1853.190000 2882.060000 ;
+ RECT 1855.855000 2881.580000 1857.120000 2882.060000 ;
+ RECT 1852.190000 2876.140000 1853.190000 2876.620000 ;
+ RECT 1855.855000 2876.140000 1857.120000 2876.620000 ;
+ RECT 1852.190000 2870.700000 1853.190000 2871.180000 ;
+ RECT 1855.855000 2870.700000 1857.120000 2871.180000 ;
+ RECT 1852.190000 2865.260000 1853.190000 2865.740000 ;
+ RECT 1855.855000 2865.260000 1857.120000 2865.740000 ;
+ RECT 1852.190000 2859.820000 1853.190000 2860.300000 ;
+ RECT 1855.855000 2859.820000 1857.120000 2860.300000 ;
+ RECT 1852.190000 2854.380000 1853.190000 2854.860000 ;
+ RECT 1855.855000 2854.380000 1857.120000 2854.860000 ;
+ RECT 2036.020000 2838.060000 2037.120000 2838.540000 ;
+ RECT 2036.020000 2843.500000 2037.120000 2843.980000 ;
+ RECT 2048.830000 2838.060000 2049.830000 2838.540000 ;
+ RECT 2048.830000 2843.500000 2049.830000 2843.980000 ;
+ RECT 2048.830000 2827.180000 2049.830000 2827.660000 ;
+ RECT 2048.830000 2832.620000 2049.830000 2833.100000 ;
+ RECT 2036.020000 2832.620000 2037.120000 2833.100000 ;
+ RECT 2036.020000 2827.180000 2037.120000 2827.660000 ;
+ RECT 2036.020000 2816.300000 2037.120000 2816.780000 ;
+ RECT 2036.020000 2821.740000 2037.120000 2822.220000 ;
+ RECT 2048.830000 2816.300000 2049.830000 2816.780000 ;
+ RECT 2048.830000 2821.740000 2049.830000 2822.220000 ;
+ RECT 2048.830000 2805.420000 2049.830000 2805.900000 ;
+ RECT 2048.830000 2799.980000 2049.830000 2800.460000 ;
+ RECT 2048.830000 2810.860000 2049.830000 2811.340000 ;
+ RECT 2036.020000 2810.860000 2037.120000 2811.340000 ;
+ RECT 2036.020000 2805.420000 2037.120000 2805.900000 ;
+ RECT 2036.020000 2799.980000 2037.120000 2800.460000 ;
+ RECT 1991.020000 2827.180000 1992.120000 2827.660000 ;
+ RECT 1991.020000 2832.620000 1992.120000 2833.100000 ;
+ RECT 1991.020000 2838.060000 1992.120000 2838.540000 ;
+ RECT 1991.020000 2843.500000 1992.120000 2843.980000 ;
+ RECT 1991.020000 2799.980000 1992.120000 2800.460000 ;
+ RECT 1991.020000 2805.420000 1992.120000 2805.900000 ;
+ RECT 1991.020000 2810.860000 1992.120000 2811.340000 ;
+ RECT 1991.020000 2816.300000 1992.120000 2816.780000 ;
+ RECT 1991.020000 2821.740000 1992.120000 2822.220000 ;
+ RECT 2036.020000 2789.100000 2037.120000 2789.580000 ;
+ RECT 2036.020000 2794.540000 2037.120000 2795.020000 ;
+ RECT 2048.830000 2789.100000 2049.830000 2789.580000 ;
+ RECT 2048.830000 2794.540000 2049.830000 2795.020000 ;
+ RECT 2036.020000 2778.220000 2037.120000 2778.700000 ;
+ RECT 2036.020000 2783.660000 2037.120000 2784.140000 ;
+ RECT 2048.830000 2778.220000 2049.830000 2778.700000 ;
+ RECT 2048.830000 2783.660000 2049.830000 2784.140000 ;
+ RECT 2048.830000 2767.340000 2049.830000 2767.820000 ;
+ RECT 2048.830000 2761.900000 2049.830000 2762.380000 ;
+ RECT 2048.830000 2772.780000 2049.830000 2773.260000 ;
+ RECT 2036.020000 2772.780000 2037.120000 2773.260000 ;
+ RECT 2036.020000 2767.340000 2037.120000 2767.820000 ;
+ RECT 2036.020000 2761.900000 2037.120000 2762.380000 ;
+ RECT 2036.020000 2756.460000 2037.120000 2756.940000 ;
+ RECT 2048.830000 2756.460000 2049.830000 2756.940000 ;
+ RECT 1991.020000 2778.220000 1992.120000 2778.700000 ;
+ RECT 1991.020000 2783.660000 1992.120000 2784.140000 ;
+ RECT 1991.020000 2789.100000 1992.120000 2789.580000 ;
+ RECT 1991.020000 2794.540000 1992.120000 2795.020000 ;
+ RECT 1991.020000 2756.460000 1992.120000 2756.940000 ;
+ RECT 1991.020000 2761.900000 1992.120000 2762.380000 ;
+ RECT 1991.020000 2767.340000 1992.120000 2767.820000 ;
+ RECT 1991.020000 2772.780000 1992.120000 2773.260000 ;
+ RECT 1946.020000 2827.180000 1947.120000 2827.660000 ;
+ RECT 1946.020000 2832.620000 1947.120000 2833.100000 ;
+ RECT 1946.020000 2838.060000 1947.120000 2838.540000 ;
+ RECT 1946.020000 2843.500000 1947.120000 2843.980000 ;
+ RECT 1901.020000 2827.180000 1902.120000 2827.660000 ;
+ RECT 1901.020000 2832.620000 1902.120000 2833.100000 ;
+ RECT 1901.020000 2838.060000 1902.120000 2838.540000 ;
+ RECT 1901.020000 2843.500000 1902.120000 2843.980000 ;
+ RECT 1946.020000 2799.980000 1947.120000 2800.460000 ;
+ RECT 1946.020000 2805.420000 1947.120000 2805.900000 ;
+ RECT 1946.020000 2810.860000 1947.120000 2811.340000 ;
+ RECT 1946.020000 2816.300000 1947.120000 2816.780000 ;
+ RECT 1946.020000 2821.740000 1947.120000 2822.220000 ;
+ RECT 1901.020000 2799.980000 1902.120000 2800.460000 ;
+ RECT 1901.020000 2805.420000 1902.120000 2805.900000 ;
+ RECT 1901.020000 2810.860000 1902.120000 2811.340000 ;
+ RECT 1901.020000 2816.300000 1902.120000 2816.780000 ;
+ RECT 1901.020000 2821.740000 1902.120000 2822.220000 ;
+ RECT 1852.190000 2843.500000 1853.190000 2843.980000 ;
+ RECT 1855.855000 2843.500000 1857.120000 2843.980000 ;
+ RECT 1852.190000 2838.060000 1853.190000 2838.540000 ;
+ RECT 1855.855000 2838.060000 1857.120000 2838.540000 ;
+ RECT 1852.190000 2832.620000 1853.190000 2833.100000 ;
+ RECT 1855.855000 2832.620000 1857.120000 2833.100000 ;
+ RECT 1852.190000 2827.180000 1853.190000 2827.660000 ;
+ RECT 1855.855000 2827.180000 1857.120000 2827.660000 ;
+ RECT 1852.190000 2821.740000 1853.190000 2822.220000 ;
+ RECT 1855.855000 2821.740000 1857.120000 2822.220000 ;
+ RECT 1852.190000 2816.300000 1853.190000 2816.780000 ;
+ RECT 1855.855000 2816.300000 1857.120000 2816.780000 ;
+ RECT 1852.190000 2805.420000 1853.190000 2805.900000 ;
+ RECT 1855.855000 2805.420000 1857.120000 2805.900000 ;
+ RECT 1852.190000 2810.860000 1853.190000 2811.340000 ;
+ RECT 1855.855000 2810.860000 1857.120000 2811.340000 ;
+ RECT 1852.190000 2799.980000 1853.190000 2800.460000 ;
+ RECT 1855.855000 2799.980000 1857.120000 2800.460000 ;
+ RECT 1946.020000 2778.220000 1947.120000 2778.700000 ;
+ RECT 1946.020000 2783.660000 1947.120000 2784.140000 ;
+ RECT 1946.020000 2789.100000 1947.120000 2789.580000 ;
+ RECT 1946.020000 2794.540000 1947.120000 2795.020000 ;
+ RECT 1901.020000 2778.220000 1902.120000 2778.700000 ;
+ RECT 1901.020000 2783.660000 1902.120000 2784.140000 ;
+ RECT 1901.020000 2789.100000 1902.120000 2789.580000 ;
+ RECT 1901.020000 2794.540000 1902.120000 2795.020000 ;
+ RECT 1946.020000 2756.460000 1947.120000 2756.940000 ;
+ RECT 1946.020000 2761.900000 1947.120000 2762.380000 ;
+ RECT 1946.020000 2767.340000 1947.120000 2767.820000 ;
+ RECT 1946.020000 2772.780000 1947.120000 2773.260000 ;
+ RECT 1901.020000 2756.460000 1902.120000 2756.940000 ;
+ RECT 1901.020000 2761.900000 1902.120000 2762.380000 ;
+ RECT 1901.020000 2767.340000 1902.120000 2767.820000 ;
+ RECT 1901.020000 2772.780000 1902.120000 2773.260000 ;
+ RECT 1852.190000 2794.540000 1853.190000 2795.020000 ;
+ RECT 1855.855000 2794.540000 1857.120000 2795.020000 ;
+ RECT 1852.190000 2789.100000 1853.190000 2789.580000 ;
+ RECT 1855.855000 2789.100000 1857.120000 2789.580000 ;
+ RECT 1852.190000 2783.660000 1853.190000 2784.140000 ;
+ RECT 1855.855000 2783.660000 1857.120000 2784.140000 ;
+ RECT 1852.190000 2778.220000 1853.190000 2778.700000 ;
+ RECT 1855.855000 2778.220000 1857.120000 2778.700000 ;
+ RECT 1852.190000 2772.780000 1853.190000 2773.260000 ;
+ RECT 1855.855000 2772.780000 1857.120000 2773.260000 ;
+ RECT 1852.190000 2761.900000 1853.190000 2762.380000 ;
+ RECT 1855.855000 2761.900000 1857.120000 2762.380000 ;
+ RECT 1852.190000 2767.340000 1853.190000 2767.820000 ;
+ RECT 1855.855000 2767.340000 1857.120000 2767.820000 ;
+ RECT 1852.190000 2756.460000 1853.190000 2756.940000 ;
+ RECT 1855.855000 2756.460000 1857.120000 2756.940000 ;
+ RECT 1991.020000 2848.940000 1992.120000 2849.420000 ;
+ RECT 2036.020000 2848.940000 2037.120000 2849.420000 ;
+ RECT 2048.830000 2848.940000 2049.830000 2849.420000 ;
+ RECT 1901.020000 2848.940000 1902.120000 2849.420000 ;
+ RECT 1946.020000 2848.940000 1947.120000 2849.420000 ;
+ RECT 1852.190000 2848.940000 1853.190000 2849.420000 ;
+ RECT 1855.855000 2848.940000 1857.120000 2849.420000 ;
+ RECT 1850.960000 2945.700000 2051.060000 2946.700000 ;
+ RECT 1850.960000 2750.130000 2051.060000 2751.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 2748.880000 1853.190000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 2948.140000 1853.190000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 2748.880000 2049.830000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 2948.140000 2049.830000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2750.130000 1851.960000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2750.130000 2051.060000 2751.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2945.700000 1851.960000 2946.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2945.700000 2051.060000 2946.700000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 2741.160000 1857.120000 2741.640000 ;
+ RECT 1855.855000 2730.280000 1857.120000 2730.760000 ;
+ RECT 1855.855000 2735.720000 1857.120000 2736.200000 ;
+ RECT 1855.855000 2724.840000 1857.120000 2725.320000 ;
+ RECT 1855.855000 2719.400000 1857.120000 2719.880000 ;
+ RECT 1855.855000 2713.960000 1857.120000 2714.440000 ;
+ RECT 1855.855000 2708.520000 1857.120000 2709.000000 ;
+ RECT 1855.855000 2703.080000 1857.120000 2703.560000 ;
+ RECT 1855.855000 2697.640000 1857.120000 2698.120000 ;
+ RECT 1855.855000 2686.760000 1857.120000 2687.240000 ;
+ RECT 1855.855000 2692.200000 1857.120000 2692.680000 ;
+ RECT 1855.855000 2681.320000 1857.120000 2681.800000 ;
+ RECT 1855.855000 2675.880000 1857.120000 2676.360000 ;
+ RECT 1855.855000 2670.440000 1857.120000 2670.920000 ;
+ RECT 1855.855000 2665.000000 1857.120000 2665.480000 ;
+ RECT 1855.855000 2659.560000 1857.120000 2660.040000 ;
+ RECT 1855.855000 2654.120000 1857.120000 2654.600000 ;
+ RECT 1855.855000 2643.240000 1857.120000 2643.720000 ;
+ RECT 1855.855000 2637.800000 1857.120000 2638.280000 ;
+ RECT 1855.855000 2632.360000 1857.120000 2632.840000 ;
+ RECT 1855.855000 2626.920000 1857.120000 2627.400000 ;
+ RECT 1855.855000 2621.480000 1857.120000 2621.960000 ;
+ RECT 1855.855000 2616.040000 1857.120000 2616.520000 ;
+ RECT 1855.855000 2605.160000 1857.120000 2605.640000 ;
+ RECT 1855.855000 2610.600000 1857.120000 2611.080000 ;
+ RECT 1855.855000 2599.720000 1857.120000 2600.200000 ;
+ RECT 1855.855000 2594.280000 1857.120000 2594.760000 ;
+ RECT 1855.855000 2588.840000 1857.120000 2589.320000 ;
+ RECT 1855.855000 2583.400000 1857.120000 2583.880000 ;
+ RECT 1855.855000 2577.960000 1857.120000 2578.440000 ;
+ RECT 1855.855000 2572.520000 1857.120000 2573.000000 ;
+ RECT 1855.855000 2561.640000 1857.120000 2562.120000 ;
+ RECT 1855.855000 2567.080000 1857.120000 2567.560000 ;
+ RECT 1855.855000 2556.200000 1857.120000 2556.680000 ;
+ RECT 1855.855000 2648.680000 1857.120000 2649.160000 ;
+ RECT 2036.020000 2549.870000 2037.120000 2746.440000 ;
+ RECT 1991.020000 2549.870000 1992.120000 2746.440000 ;
+ RECT 2048.830000 2548.620000 2049.830000 2748.880000 ;
+ RECT 1946.020000 2549.870000 1947.120000 2746.440000 ;
+ RECT 1901.020000 2549.870000 1902.120000 2746.440000 ;
+ RECT 1856.020000 2549.870000 1857.120000 2746.440000 ;
+ RECT 1852.190000 2548.620000 1853.190000 2748.880000 ;
+ LAYER met3 ;
+ RECT 2036.020000 2741.160000 2037.120000 2741.640000 ;
+ RECT 2048.830000 2741.160000 2049.830000 2741.640000 ;
+ RECT 2048.830000 2730.280000 2049.830000 2730.760000 ;
+ RECT 2048.830000 2724.840000 2049.830000 2725.320000 ;
+ RECT 2048.830000 2735.720000 2049.830000 2736.200000 ;
+ RECT 2036.020000 2735.720000 2037.120000 2736.200000 ;
+ RECT 2036.020000 2730.280000 2037.120000 2730.760000 ;
+ RECT 2036.020000 2724.840000 2037.120000 2725.320000 ;
+ RECT 2036.020000 2713.960000 2037.120000 2714.440000 ;
+ RECT 2036.020000 2719.400000 2037.120000 2719.880000 ;
+ RECT 2048.830000 2713.960000 2049.830000 2714.440000 ;
+ RECT 2048.830000 2719.400000 2049.830000 2719.880000 ;
+ RECT 2036.020000 2703.080000 2037.120000 2703.560000 ;
+ RECT 2036.020000 2708.520000 2037.120000 2709.000000 ;
+ RECT 2048.830000 2703.080000 2049.830000 2703.560000 ;
+ RECT 2048.830000 2708.520000 2049.830000 2709.000000 ;
+ RECT 1991.020000 2724.840000 1992.120000 2725.320000 ;
+ RECT 1991.020000 2730.280000 1992.120000 2730.760000 ;
+ RECT 1991.020000 2735.720000 1992.120000 2736.200000 ;
+ RECT 1991.020000 2741.160000 1992.120000 2741.640000 ;
+ RECT 1991.020000 2708.520000 1992.120000 2709.000000 ;
+ RECT 1991.020000 2703.080000 1992.120000 2703.560000 ;
+ RECT 1991.020000 2713.960000 1992.120000 2714.440000 ;
+ RECT 1991.020000 2719.400000 1992.120000 2719.880000 ;
+ RECT 2048.830000 2692.200000 2049.830000 2692.680000 ;
+ RECT 2048.830000 2686.760000 2049.830000 2687.240000 ;
+ RECT 2048.830000 2697.640000 2049.830000 2698.120000 ;
+ RECT 2036.020000 2697.640000 2037.120000 2698.120000 ;
+ RECT 2036.020000 2692.200000 2037.120000 2692.680000 ;
+ RECT 2036.020000 2686.760000 2037.120000 2687.240000 ;
+ RECT 2036.020000 2675.880000 2037.120000 2676.360000 ;
+ RECT 2036.020000 2681.320000 2037.120000 2681.800000 ;
+ RECT 2048.830000 2675.880000 2049.830000 2676.360000 ;
+ RECT 2048.830000 2681.320000 2049.830000 2681.800000 ;
+ RECT 2048.830000 2665.000000 2049.830000 2665.480000 ;
+ RECT 2048.830000 2670.440000 2049.830000 2670.920000 ;
+ RECT 2036.020000 2670.440000 2037.120000 2670.920000 ;
+ RECT 2036.020000 2665.000000 2037.120000 2665.480000 ;
+ RECT 2036.020000 2654.120000 2037.120000 2654.600000 ;
+ RECT 2036.020000 2659.560000 2037.120000 2660.040000 ;
+ RECT 2048.830000 2654.120000 2049.830000 2654.600000 ;
+ RECT 2048.830000 2659.560000 2049.830000 2660.040000 ;
+ RECT 1991.020000 2675.880000 1992.120000 2676.360000 ;
+ RECT 1991.020000 2681.320000 1992.120000 2681.800000 ;
+ RECT 1991.020000 2686.760000 1992.120000 2687.240000 ;
+ RECT 1991.020000 2692.200000 1992.120000 2692.680000 ;
+ RECT 1991.020000 2697.640000 1992.120000 2698.120000 ;
+ RECT 1991.020000 2654.120000 1992.120000 2654.600000 ;
+ RECT 1991.020000 2659.560000 1992.120000 2660.040000 ;
+ RECT 1991.020000 2665.000000 1992.120000 2665.480000 ;
+ RECT 1991.020000 2670.440000 1992.120000 2670.920000 ;
+ RECT 1946.020000 2730.280000 1947.120000 2730.760000 ;
+ RECT 1946.020000 2724.840000 1947.120000 2725.320000 ;
+ RECT 1946.020000 2735.720000 1947.120000 2736.200000 ;
+ RECT 1946.020000 2741.160000 1947.120000 2741.640000 ;
+ RECT 1901.020000 2724.840000 1902.120000 2725.320000 ;
+ RECT 1901.020000 2730.280000 1902.120000 2730.760000 ;
+ RECT 1901.020000 2735.720000 1902.120000 2736.200000 ;
+ RECT 1901.020000 2741.160000 1902.120000 2741.640000 ;
+ RECT 1946.020000 2703.080000 1947.120000 2703.560000 ;
+ RECT 1946.020000 2708.520000 1947.120000 2709.000000 ;
+ RECT 1946.020000 2713.960000 1947.120000 2714.440000 ;
+ RECT 1946.020000 2719.400000 1947.120000 2719.880000 ;
+ RECT 1901.020000 2703.080000 1902.120000 2703.560000 ;
+ RECT 1901.020000 2708.520000 1902.120000 2709.000000 ;
+ RECT 1901.020000 2713.960000 1902.120000 2714.440000 ;
+ RECT 1901.020000 2719.400000 1902.120000 2719.880000 ;
+ RECT 1852.190000 2741.160000 1853.190000 2741.640000 ;
+ RECT 1855.855000 2741.160000 1857.120000 2741.640000 ;
+ RECT 1852.190000 2730.280000 1853.190000 2730.760000 ;
+ RECT 1855.855000 2730.280000 1857.120000 2730.760000 ;
+ RECT 1852.190000 2735.720000 1853.190000 2736.200000 ;
+ RECT 1855.855000 2735.720000 1857.120000 2736.200000 ;
+ RECT 1852.190000 2724.840000 1853.190000 2725.320000 ;
+ RECT 1855.855000 2724.840000 1857.120000 2725.320000 ;
+ RECT 1852.190000 2719.400000 1853.190000 2719.880000 ;
+ RECT 1855.855000 2719.400000 1857.120000 2719.880000 ;
+ RECT 1852.190000 2713.960000 1853.190000 2714.440000 ;
+ RECT 1855.855000 2713.960000 1857.120000 2714.440000 ;
+ RECT 1852.190000 2708.520000 1853.190000 2709.000000 ;
+ RECT 1855.855000 2708.520000 1857.120000 2709.000000 ;
+ RECT 1852.190000 2703.080000 1853.190000 2703.560000 ;
+ RECT 1855.855000 2703.080000 1857.120000 2703.560000 ;
+ RECT 1946.020000 2675.880000 1947.120000 2676.360000 ;
+ RECT 1946.020000 2681.320000 1947.120000 2681.800000 ;
+ RECT 1946.020000 2686.760000 1947.120000 2687.240000 ;
+ RECT 1946.020000 2692.200000 1947.120000 2692.680000 ;
+ RECT 1946.020000 2697.640000 1947.120000 2698.120000 ;
+ RECT 1901.020000 2675.880000 1902.120000 2676.360000 ;
+ RECT 1901.020000 2681.320000 1902.120000 2681.800000 ;
+ RECT 1901.020000 2686.760000 1902.120000 2687.240000 ;
+ RECT 1901.020000 2692.200000 1902.120000 2692.680000 ;
+ RECT 1901.020000 2697.640000 1902.120000 2698.120000 ;
+ RECT 1946.020000 2654.120000 1947.120000 2654.600000 ;
+ RECT 1946.020000 2659.560000 1947.120000 2660.040000 ;
+ RECT 1946.020000 2665.000000 1947.120000 2665.480000 ;
+ RECT 1946.020000 2670.440000 1947.120000 2670.920000 ;
+ RECT 1901.020000 2654.120000 1902.120000 2654.600000 ;
+ RECT 1901.020000 2659.560000 1902.120000 2660.040000 ;
+ RECT 1901.020000 2665.000000 1902.120000 2665.480000 ;
+ RECT 1901.020000 2670.440000 1902.120000 2670.920000 ;
+ RECT 1852.190000 2697.640000 1853.190000 2698.120000 ;
+ RECT 1855.855000 2697.640000 1857.120000 2698.120000 ;
+ RECT 1852.190000 2686.760000 1853.190000 2687.240000 ;
+ RECT 1855.855000 2686.760000 1857.120000 2687.240000 ;
+ RECT 1852.190000 2692.200000 1853.190000 2692.680000 ;
+ RECT 1855.855000 2692.200000 1857.120000 2692.680000 ;
+ RECT 1852.190000 2681.320000 1853.190000 2681.800000 ;
+ RECT 1855.855000 2681.320000 1857.120000 2681.800000 ;
+ RECT 1852.190000 2675.880000 1853.190000 2676.360000 ;
+ RECT 1855.855000 2675.880000 1857.120000 2676.360000 ;
+ RECT 1852.190000 2670.440000 1853.190000 2670.920000 ;
+ RECT 1855.855000 2670.440000 1857.120000 2670.920000 ;
+ RECT 1852.190000 2665.000000 1853.190000 2665.480000 ;
+ RECT 1855.855000 2665.000000 1857.120000 2665.480000 ;
+ RECT 1852.190000 2659.560000 1853.190000 2660.040000 ;
+ RECT 1855.855000 2659.560000 1857.120000 2660.040000 ;
+ RECT 1852.190000 2654.120000 1853.190000 2654.600000 ;
+ RECT 1855.855000 2654.120000 1857.120000 2654.600000 ;
+ RECT 2036.020000 2637.800000 2037.120000 2638.280000 ;
+ RECT 2036.020000 2643.240000 2037.120000 2643.720000 ;
+ RECT 2048.830000 2637.800000 2049.830000 2638.280000 ;
+ RECT 2048.830000 2643.240000 2049.830000 2643.720000 ;
+ RECT 2048.830000 2626.920000 2049.830000 2627.400000 ;
+ RECT 2048.830000 2632.360000 2049.830000 2632.840000 ;
+ RECT 2036.020000 2632.360000 2037.120000 2632.840000 ;
+ RECT 2036.020000 2626.920000 2037.120000 2627.400000 ;
+ RECT 2036.020000 2616.040000 2037.120000 2616.520000 ;
+ RECT 2036.020000 2621.480000 2037.120000 2621.960000 ;
+ RECT 2048.830000 2616.040000 2049.830000 2616.520000 ;
+ RECT 2048.830000 2621.480000 2049.830000 2621.960000 ;
+ RECT 2048.830000 2605.160000 2049.830000 2605.640000 ;
+ RECT 2048.830000 2599.720000 2049.830000 2600.200000 ;
+ RECT 2048.830000 2610.600000 2049.830000 2611.080000 ;
+ RECT 2036.020000 2610.600000 2037.120000 2611.080000 ;
+ RECT 2036.020000 2605.160000 2037.120000 2605.640000 ;
+ RECT 2036.020000 2599.720000 2037.120000 2600.200000 ;
+ RECT 1991.020000 2626.920000 1992.120000 2627.400000 ;
+ RECT 1991.020000 2632.360000 1992.120000 2632.840000 ;
+ RECT 1991.020000 2637.800000 1992.120000 2638.280000 ;
+ RECT 1991.020000 2643.240000 1992.120000 2643.720000 ;
+ RECT 1991.020000 2599.720000 1992.120000 2600.200000 ;
+ RECT 1991.020000 2605.160000 1992.120000 2605.640000 ;
+ RECT 1991.020000 2610.600000 1992.120000 2611.080000 ;
+ RECT 1991.020000 2616.040000 1992.120000 2616.520000 ;
+ RECT 1991.020000 2621.480000 1992.120000 2621.960000 ;
+ RECT 2036.020000 2588.840000 2037.120000 2589.320000 ;
+ RECT 2036.020000 2594.280000 2037.120000 2594.760000 ;
+ RECT 2048.830000 2588.840000 2049.830000 2589.320000 ;
+ RECT 2048.830000 2594.280000 2049.830000 2594.760000 ;
+ RECT 2036.020000 2577.960000 2037.120000 2578.440000 ;
+ RECT 2036.020000 2583.400000 2037.120000 2583.880000 ;
+ RECT 2048.830000 2577.960000 2049.830000 2578.440000 ;
+ RECT 2048.830000 2583.400000 2049.830000 2583.880000 ;
+ RECT 2048.830000 2567.080000 2049.830000 2567.560000 ;
+ RECT 2048.830000 2561.640000 2049.830000 2562.120000 ;
+ RECT 2048.830000 2572.520000 2049.830000 2573.000000 ;
+ RECT 2036.020000 2572.520000 2037.120000 2573.000000 ;
+ RECT 2036.020000 2567.080000 2037.120000 2567.560000 ;
+ RECT 2036.020000 2561.640000 2037.120000 2562.120000 ;
+ RECT 2036.020000 2556.200000 2037.120000 2556.680000 ;
+ RECT 2048.830000 2556.200000 2049.830000 2556.680000 ;
+ RECT 1991.020000 2577.960000 1992.120000 2578.440000 ;
+ RECT 1991.020000 2583.400000 1992.120000 2583.880000 ;
+ RECT 1991.020000 2588.840000 1992.120000 2589.320000 ;
+ RECT 1991.020000 2594.280000 1992.120000 2594.760000 ;
+ RECT 1991.020000 2556.200000 1992.120000 2556.680000 ;
+ RECT 1991.020000 2561.640000 1992.120000 2562.120000 ;
+ RECT 1991.020000 2567.080000 1992.120000 2567.560000 ;
+ RECT 1991.020000 2572.520000 1992.120000 2573.000000 ;
+ RECT 1946.020000 2626.920000 1947.120000 2627.400000 ;
+ RECT 1946.020000 2632.360000 1947.120000 2632.840000 ;
+ RECT 1946.020000 2637.800000 1947.120000 2638.280000 ;
+ RECT 1946.020000 2643.240000 1947.120000 2643.720000 ;
+ RECT 1901.020000 2626.920000 1902.120000 2627.400000 ;
+ RECT 1901.020000 2632.360000 1902.120000 2632.840000 ;
+ RECT 1901.020000 2637.800000 1902.120000 2638.280000 ;
+ RECT 1901.020000 2643.240000 1902.120000 2643.720000 ;
+ RECT 1946.020000 2599.720000 1947.120000 2600.200000 ;
+ RECT 1946.020000 2605.160000 1947.120000 2605.640000 ;
+ RECT 1946.020000 2610.600000 1947.120000 2611.080000 ;
+ RECT 1946.020000 2616.040000 1947.120000 2616.520000 ;
+ RECT 1946.020000 2621.480000 1947.120000 2621.960000 ;
+ RECT 1901.020000 2599.720000 1902.120000 2600.200000 ;
+ RECT 1901.020000 2605.160000 1902.120000 2605.640000 ;
+ RECT 1901.020000 2610.600000 1902.120000 2611.080000 ;
+ RECT 1901.020000 2616.040000 1902.120000 2616.520000 ;
+ RECT 1901.020000 2621.480000 1902.120000 2621.960000 ;
+ RECT 1852.190000 2643.240000 1853.190000 2643.720000 ;
+ RECT 1855.855000 2643.240000 1857.120000 2643.720000 ;
+ RECT 1852.190000 2637.800000 1853.190000 2638.280000 ;
+ RECT 1855.855000 2637.800000 1857.120000 2638.280000 ;
+ RECT 1852.190000 2632.360000 1853.190000 2632.840000 ;
+ RECT 1855.855000 2632.360000 1857.120000 2632.840000 ;
+ RECT 1852.190000 2626.920000 1853.190000 2627.400000 ;
+ RECT 1855.855000 2626.920000 1857.120000 2627.400000 ;
+ RECT 1852.190000 2621.480000 1853.190000 2621.960000 ;
+ RECT 1855.855000 2621.480000 1857.120000 2621.960000 ;
+ RECT 1852.190000 2616.040000 1853.190000 2616.520000 ;
+ RECT 1855.855000 2616.040000 1857.120000 2616.520000 ;
+ RECT 1852.190000 2605.160000 1853.190000 2605.640000 ;
+ RECT 1855.855000 2605.160000 1857.120000 2605.640000 ;
+ RECT 1852.190000 2610.600000 1853.190000 2611.080000 ;
+ RECT 1855.855000 2610.600000 1857.120000 2611.080000 ;
+ RECT 1852.190000 2599.720000 1853.190000 2600.200000 ;
+ RECT 1855.855000 2599.720000 1857.120000 2600.200000 ;
+ RECT 1946.020000 2577.960000 1947.120000 2578.440000 ;
+ RECT 1946.020000 2583.400000 1947.120000 2583.880000 ;
+ RECT 1946.020000 2588.840000 1947.120000 2589.320000 ;
+ RECT 1946.020000 2594.280000 1947.120000 2594.760000 ;
+ RECT 1901.020000 2577.960000 1902.120000 2578.440000 ;
+ RECT 1901.020000 2583.400000 1902.120000 2583.880000 ;
+ RECT 1901.020000 2588.840000 1902.120000 2589.320000 ;
+ RECT 1901.020000 2594.280000 1902.120000 2594.760000 ;
+ RECT 1946.020000 2556.200000 1947.120000 2556.680000 ;
+ RECT 1946.020000 2561.640000 1947.120000 2562.120000 ;
+ RECT 1946.020000 2567.080000 1947.120000 2567.560000 ;
+ RECT 1946.020000 2572.520000 1947.120000 2573.000000 ;
+ RECT 1901.020000 2556.200000 1902.120000 2556.680000 ;
+ RECT 1901.020000 2561.640000 1902.120000 2562.120000 ;
+ RECT 1901.020000 2567.080000 1902.120000 2567.560000 ;
+ RECT 1901.020000 2572.520000 1902.120000 2573.000000 ;
+ RECT 1852.190000 2594.280000 1853.190000 2594.760000 ;
+ RECT 1855.855000 2594.280000 1857.120000 2594.760000 ;
+ RECT 1852.190000 2588.840000 1853.190000 2589.320000 ;
+ RECT 1855.855000 2588.840000 1857.120000 2589.320000 ;
+ RECT 1852.190000 2583.400000 1853.190000 2583.880000 ;
+ RECT 1855.855000 2583.400000 1857.120000 2583.880000 ;
+ RECT 1852.190000 2577.960000 1853.190000 2578.440000 ;
+ RECT 1855.855000 2577.960000 1857.120000 2578.440000 ;
+ RECT 1852.190000 2572.520000 1853.190000 2573.000000 ;
+ RECT 1855.855000 2572.520000 1857.120000 2573.000000 ;
+ RECT 1852.190000 2561.640000 1853.190000 2562.120000 ;
+ RECT 1855.855000 2561.640000 1857.120000 2562.120000 ;
+ RECT 1852.190000 2567.080000 1853.190000 2567.560000 ;
+ RECT 1855.855000 2567.080000 1857.120000 2567.560000 ;
+ RECT 1852.190000 2556.200000 1853.190000 2556.680000 ;
+ RECT 1855.855000 2556.200000 1857.120000 2556.680000 ;
+ RECT 1991.020000 2648.680000 1992.120000 2649.160000 ;
+ RECT 2036.020000 2648.680000 2037.120000 2649.160000 ;
+ RECT 2048.830000 2648.680000 2049.830000 2649.160000 ;
+ RECT 1901.020000 2648.680000 1902.120000 2649.160000 ;
+ RECT 1946.020000 2648.680000 1947.120000 2649.160000 ;
+ RECT 1852.190000 2648.680000 1853.190000 2649.160000 ;
+ RECT 1855.855000 2648.680000 1857.120000 2649.160000 ;
+ RECT 1850.960000 2745.440000 2051.060000 2746.440000 ;
+ RECT 1850.960000 2549.870000 2051.060000 2550.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 2548.620000 1853.190000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 2747.880000 1853.190000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 2548.620000 2049.830000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 2747.880000 2049.830000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2549.870000 1851.960000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2549.870000 2051.060000 2550.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2745.440000 1851.960000 2746.440000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2745.440000 2051.060000 2746.440000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 2540.900000 1857.120000 2541.380000 ;
+ RECT 1855.855000 2530.020000 1857.120000 2530.500000 ;
+ RECT 1855.855000 2535.460000 1857.120000 2535.940000 ;
+ RECT 1855.855000 2524.580000 1857.120000 2525.060000 ;
+ RECT 1855.855000 2519.140000 1857.120000 2519.620000 ;
+ RECT 1855.855000 2513.700000 1857.120000 2514.180000 ;
+ RECT 1855.855000 2508.260000 1857.120000 2508.740000 ;
+ RECT 1855.855000 2502.820000 1857.120000 2503.300000 ;
+ RECT 1855.855000 2497.380000 1857.120000 2497.860000 ;
+ RECT 1855.855000 2486.500000 1857.120000 2486.980000 ;
+ RECT 1855.855000 2491.940000 1857.120000 2492.420000 ;
+ RECT 1855.855000 2481.060000 1857.120000 2481.540000 ;
+ RECT 1855.855000 2475.620000 1857.120000 2476.100000 ;
+ RECT 1855.855000 2470.180000 1857.120000 2470.660000 ;
+ RECT 1855.855000 2464.740000 1857.120000 2465.220000 ;
+ RECT 1855.855000 2459.300000 1857.120000 2459.780000 ;
+ RECT 1855.855000 2453.860000 1857.120000 2454.340000 ;
+ RECT 1855.855000 2442.980000 1857.120000 2443.460000 ;
+ RECT 1855.855000 2437.540000 1857.120000 2438.020000 ;
+ RECT 1855.855000 2432.100000 1857.120000 2432.580000 ;
+ RECT 1855.855000 2426.660000 1857.120000 2427.140000 ;
+ RECT 1855.855000 2421.220000 1857.120000 2421.700000 ;
+ RECT 1855.855000 2415.780000 1857.120000 2416.260000 ;
+ RECT 1855.855000 2404.900000 1857.120000 2405.380000 ;
+ RECT 1855.855000 2410.340000 1857.120000 2410.820000 ;
+ RECT 1855.855000 2399.460000 1857.120000 2399.940000 ;
+ RECT 1855.855000 2394.020000 1857.120000 2394.500000 ;
+ RECT 1855.855000 2388.580000 1857.120000 2389.060000 ;
+ RECT 1855.855000 2383.140000 1857.120000 2383.620000 ;
+ RECT 1855.855000 2377.700000 1857.120000 2378.180000 ;
+ RECT 1855.855000 2372.260000 1857.120000 2372.740000 ;
+ RECT 1855.855000 2361.380000 1857.120000 2361.860000 ;
+ RECT 1855.855000 2366.820000 1857.120000 2367.300000 ;
+ RECT 1855.855000 2355.940000 1857.120000 2356.420000 ;
+ RECT 1855.855000 2448.420000 1857.120000 2448.900000 ;
+ RECT 2036.020000 2349.610000 2037.120000 2546.180000 ;
+ RECT 1991.020000 2349.610000 1992.120000 2546.180000 ;
+ RECT 2048.830000 2348.360000 2049.830000 2548.620000 ;
+ RECT 1946.020000 2349.610000 1947.120000 2546.180000 ;
+ RECT 1901.020000 2349.610000 1902.120000 2546.180000 ;
+ RECT 1856.020000 2349.610000 1857.120000 2546.180000 ;
+ RECT 1852.190000 2348.360000 1853.190000 2548.620000 ;
+ LAYER met3 ;
+ RECT 2036.020000 2540.900000 2037.120000 2541.380000 ;
+ RECT 2048.830000 2540.900000 2049.830000 2541.380000 ;
+ RECT 2048.830000 2530.020000 2049.830000 2530.500000 ;
+ RECT 2048.830000 2524.580000 2049.830000 2525.060000 ;
+ RECT 2048.830000 2535.460000 2049.830000 2535.940000 ;
+ RECT 2036.020000 2535.460000 2037.120000 2535.940000 ;
+ RECT 2036.020000 2530.020000 2037.120000 2530.500000 ;
+ RECT 2036.020000 2524.580000 2037.120000 2525.060000 ;
+ RECT 2036.020000 2513.700000 2037.120000 2514.180000 ;
+ RECT 2036.020000 2519.140000 2037.120000 2519.620000 ;
+ RECT 2048.830000 2513.700000 2049.830000 2514.180000 ;
+ RECT 2048.830000 2519.140000 2049.830000 2519.620000 ;
+ RECT 2036.020000 2502.820000 2037.120000 2503.300000 ;
+ RECT 2036.020000 2508.260000 2037.120000 2508.740000 ;
+ RECT 2048.830000 2502.820000 2049.830000 2503.300000 ;
+ RECT 2048.830000 2508.260000 2049.830000 2508.740000 ;
+ RECT 1991.020000 2524.580000 1992.120000 2525.060000 ;
+ RECT 1991.020000 2530.020000 1992.120000 2530.500000 ;
+ RECT 1991.020000 2535.460000 1992.120000 2535.940000 ;
+ RECT 1991.020000 2540.900000 1992.120000 2541.380000 ;
+ RECT 1991.020000 2508.260000 1992.120000 2508.740000 ;
+ RECT 1991.020000 2502.820000 1992.120000 2503.300000 ;
+ RECT 1991.020000 2513.700000 1992.120000 2514.180000 ;
+ RECT 1991.020000 2519.140000 1992.120000 2519.620000 ;
+ RECT 2048.830000 2491.940000 2049.830000 2492.420000 ;
+ RECT 2048.830000 2486.500000 2049.830000 2486.980000 ;
+ RECT 2048.830000 2497.380000 2049.830000 2497.860000 ;
+ RECT 2036.020000 2497.380000 2037.120000 2497.860000 ;
+ RECT 2036.020000 2491.940000 2037.120000 2492.420000 ;
+ RECT 2036.020000 2486.500000 2037.120000 2486.980000 ;
+ RECT 2036.020000 2475.620000 2037.120000 2476.100000 ;
+ RECT 2036.020000 2481.060000 2037.120000 2481.540000 ;
+ RECT 2048.830000 2475.620000 2049.830000 2476.100000 ;
+ RECT 2048.830000 2481.060000 2049.830000 2481.540000 ;
+ RECT 2048.830000 2464.740000 2049.830000 2465.220000 ;
+ RECT 2048.830000 2470.180000 2049.830000 2470.660000 ;
+ RECT 2036.020000 2470.180000 2037.120000 2470.660000 ;
+ RECT 2036.020000 2464.740000 2037.120000 2465.220000 ;
+ RECT 2036.020000 2453.860000 2037.120000 2454.340000 ;
+ RECT 2036.020000 2459.300000 2037.120000 2459.780000 ;
+ RECT 2048.830000 2453.860000 2049.830000 2454.340000 ;
+ RECT 2048.830000 2459.300000 2049.830000 2459.780000 ;
+ RECT 1991.020000 2475.620000 1992.120000 2476.100000 ;
+ RECT 1991.020000 2481.060000 1992.120000 2481.540000 ;
+ RECT 1991.020000 2486.500000 1992.120000 2486.980000 ;
+ RECT 1991.020000 2491.940000 1992.120000 2492.420000 ;
+ RECT 1991.020000 2497.380000 1992.120000 2497.860000 ;
+ RECT 1991.020000 2453.860000 1992.120000 2454.340000 ;
+ RECT 1991.020000 2459.300000 1992.120000 2459.780000 ;
+ RECT 1991.020000 2464.740000 1992.120000 2465.220000 ;
+ RECT 1991.020000 2470.180000 1992.120000 2470.660000 ;
+ RECT 1946.020000 2530.020000 1947.120000 2530.500000 ;
+ RECT 1946.020000 2524.580000 1947.120000 2525.060000 ;
+ RECT 1946.020000 2535.460000 1947.120000 2535.940000 ;
+ RECT 1946.020000 2540.900000 1947.120000 2541.380000 ;
+ RECT 1901.020000 2524.580000 1902.120000 2525.060000 ;
+ RECT 1901.020000 2530.020000 1902.120000 2530.500000 ;
+ RECT 1901.020000 2535.460000 1902.120000 2535.940000 ;
+ RECT 1901.020000 2540.900000 1902.120000 2541.380000 ;
+ RECT 1946.020000 2502.820000 1947.120000 2503.300000 ;
+ RECT 1946.020000 2508.260000 1947.120000 2508.740000 ;
+ RECT 1946.020000 2513.700000 1947.120000 2514.180000 ;
+ RECT 1946.020000 2519.140000 1947.120000 2519.620000 ;
+ RECT 1901.020000 2502.820000 1902.120000 2503.300000 ;
+ RECT 1901.020000 2508.260000 1902.120000 2508.740000 ;
+ RECT 1901.020000 2513.700000 1902.120000 2514.180000 ;
+ RECT 1901.020000 2519.140000 1902.120000 2519.620000 ;
+ RECT 1852.190000 2540.900000 1853.190000 2541.380000 ;
+ RECT 1855.855000 2540.900000 1857.120000 2541.380000 ;
+ RECT 1852.190000 2530.020000 1853.190000 2530.500000 ;
+ RECT 1855.855000 2530.020000 1857.120000 2530.500000 ;
+ RECT 1852.190000 2535.460000 1853.190000 2535.940000 ;
+ RECT 1855.855000 2535.460000 1857.120000 2535.940000 ;
+ RECT 1852.190000 2524.580000 1853.190000 2525.060000 ;
+ RECT 1855.855000 2524.580000 1857.120000 2525.060000 ;
+ RECT 1852.190000 2519.140000 1853.190000 2519.620000 ;
+ RECT 1855.855000 2519.140000 1857.120000 2519.620000 ;
+ RECT 1852.190000 2513.700000 1853.190000 2514.180000 ;
+ RECT 1855.855000 2513.700000 1857.120000 2514.180000 ;
+ RECT 1852.190000 2508.260000 1853.190000 2508.740000 ;
+ RECT 1855.855000 2508.260000 1857.120000 2508.740000 ;
+ RECT 1852.190000 2502.820000 1853.190000 2503.300000 ;
+ RECT 1855.855000 2502.820000 1857.120000 2503.300000 ;
+ RECT 1946.020000 2475.620000 1947.120000 2476.100000 ;
+ RECT 1946.020000 2481.060000 1947.120000 2481.540000 ;
+ RECT 1946.020000 2486.500000 1947.120000 2486.980000 ;
+ RECT 1946.020000 2491.940000 1947.120000 2492.420000 ;
+ RECT 1946.020000 2497.380000 1947.120000 2497.860000 ;
+ RECT 1901.020000 2475.620000 1902.120000 2476.100000 ;
+ RECT 1901.020000 2481.060000 1902.120000 2481.540000 ;
+ RECT 1901.020000 2486.500000 1902.120000 2486.980000 ;
+ RECT 1901.020000 2491.940000 1902.120000 2492.420000 ;
+ RECT 1901.020000 2497.380000 1902.120000 2497.860000 ;
+ RECT 1946.020000 2453.860000 1947.120000 2454.340000 ;
+ RECT 1946.020000 2459.300000 1947.120000 2459.780000 ;
+ RECT 1946.020000 2464.740000 1947.120000 2465.220000 ;
+ RECT 1946.020000 2470.180000 1947.120000 2470.660000 ;
+ RECT 1901.020000 2453.860000 1902.120000 2454.340000 ;
+ RECT 1901.020000 2459.300000 1902.120000 2459.780000 ;
+ RECT 1901.020000 2464.740000 1902.120000 2465.220000 ;
+ RECT 1901.020000 2470.180000 1902.120000 2470.660000 ;
+ RECT 1852.190000 2497.380000 1853.190000 2497.860000 ;
+ RECT 1855.855000 2497.380000 1857.120000 2497.860000 ;
+ RECT 1852.190000 2486.500000 1853.190000 2486.980000 ;
+ RECT 1855.855000 2486.500000 1857.120000 2486.980000 ;
+ RECT 1852.190000 2491.940000 1853.190000 2492.420000 ;
+ RECT 1855.855000 2491.940000 1857.120000 2492.420000 ;
+ RECT 1852.190000 2481.060000 1853.190000 2481.540000 ;
+ RECT 1855.855000 2481.060000 1857.120000 2481.540000 ;
+ RECT 1852.190000 2475.620000 1853.190000 2476.100000 ;
+ RECT 1855.855000 2475.620000 1857.120000 2476.100000 ;
+ RECT 1852.190000 2470.180000 1853.190000 2470.660000 ;
+ RECT 1855.855000 2470.180000 1857.120000 2470.660000 ;
+ RECT 1852.190000 2464.740000 1853.190000 2465.220000 ;
+ RECT 1855.855000 2464.740000 1857.120000 2465.220000 ;
+ RECT 1852.190000 2459.300000 1853.190000 2459.780000 ;
+ RECT 1855.855000 2459.300000 1857.120000 2459.780000 ;
+ RECT 1852.190000 2453.860000 1853.190000 2454.340000 ;
+ RECT 1855.855000 2453.860000 1857.120000 2454.340000 ;
+ RECT 2036.020000 2437.540000 2037.120000 2438.020000 ;
+ RECT 2036.020000 2442.980000 2037.120000 2443.460000 ;
+ RECT 2048.830000 2437.540000 2049.830000 2438.020000 ;
+ RECT 2048.830000 2442.980000 2049.830000 2443.460000 ;
+ RECT 2048.830000 2426.660000 2049.830000 2427.140000 ;
+ RECT 2048.830000 2432.100000 2049.830000 2432.580000 ;
+ RECT 2036.020000 2432.100000 2037.120000 2432.580000 ;
+ RECT 2036.020000 2426.660000 2037.120000 2427.140000 ;
+ RECT 2036.020000 2415.780000 2037.120000 2416.260000 ;
+ RECT 2036.020000 2421.220000 2037.120000 2421.700000 ;
+ RECT 2048.830000 2415.780000 2049.830000 2416.260000 ;
+ RECT 2048.830000 2421.220000 2049.830000 2421.700000 ;
+ RECT 2048.830000 2404.900000 2049.830000 2405.380000 ;
+ RECT 2048.830000 2399.460000 2049.830000 2399.940000 ;
+ RECT 2048.830000 2410.340000 2049.830000 2410.820000 ;
+ RECT 2036.020000 2410.340000 2037.120000 2410.820000 ;
+ RECT 2036.020000 2404.900000 2037.120000 2405.380000 ;
+ RECT 2036.020000 2399.460000 2037.120000 2399.940000 ;
+ RECT 1991.020000 2426.660000 1992.120000 2427.140000 ;
+ RECT 1991.020000 2432.100000 1992.120000 2432.580000 ;
+ RECT 1991.020000 2437.540000 1992.120000 2438.020000 ;
+ RECT 1991.020000 2442.980000 1992.120000 2443.460000 ;
+ RECT 1991.020000 2399.460000 1992.120000 2399.940000 ;
+ RECT 1991.020000 2404.900000 1992.120000 2405.380000 ;
+ RECT 1991.020000 2410.340000 1992.120000 2410.820000 ;
+ RECT 1991.020000 2415.780000 1992.120000 2416.260000 ;
+ RECT 1991.020000 2421.220000 1992.120000 2421.700000 ;
+ RECT 2036.020000 2388.580000 2037.120000 2389.060000 ;
+ RECT 2036.020000 2394.020000 2037.120000 2394.500000 ;
+ RECT 2048.830000 2388.580000 2049.830000 2389.060000 ;
+ RECT 2048.830000 2394.020000 2049.830000 2394.500000 ;
+ RECT 2036.020000 2377.700000 2037.120000 2378.180000 ;
+ RECT 2036.020000 2383.140000 2037.120000 2383.620000 ;
+ RECT 2048.830000 2377.700000 2049.830000 2378.180000 ;
+ RECT 2048.830000 2383.140000 2049.830000 2383.620000 ;
+ RECT 2048.830000 2366.820000 2049.830000 2367.300000 ;
+ RECT 2048.830000 2361.380000 2049.830000 2361.860000 ;
+ RECT 2048.830000 2372.260000 2049.830000 2372.740000 ;
+ RECT 2036.020000 2372.260000 2037.120000 2372.740000 ;
+ RECT 2036.020000 2366.820000 2037.120000 2367.300000 ;
+ RECT 2036.020000 2361.380000 2037.120000 2361.860000 ;
+ RECT 2036.020000 2355.940000 2037.120000 2356.420000 ;
+ RECT 2048.830000 2355.940000 2049.830000 2356.420000 ;
+ RECT 1991.020000 2377.700000 1992.120000 2378.180000 ;
+ RECT 1991.020000 2383.140000 1992.120000 2383.620000 ;
+ RECT 1991.020000 2388.580000 1992.120000 2389.060000 ;
+ RECT 1991.020000 2394.020000 1992.120000 2394.500000 ;
+ RECT 1991.020000 2355.940000 1992.120000 2356.420000 ;
+ RECT 1991.020000 2361.380000 1992.120000 2361.860000 ;
+ RECT 1991.020000 2366.820000 1992.120000 2367.300000 ;
+ RECT 1991.020000 2372.260000 1992.120000 2372.740000 ;
+ RECT 1946.020000 2426.660000 1947.120000 2427.140000 ;
+ RECT 1946.020000 2432.100000 1947.120000 2432.580000 ;
+ RECT 1946.020000 2437.540000 1947.120000 2438.020000 ;
+ RECT 1946.020000 2442.980000 1947.120000 2443.460000 ;
+ RECT 1901.020000 2426.660000 1902.120000 2427.140000 ;
+ RECT 1901.020000 2432.100000 1902.120000 2432.580000 ;
+ RECT 1901.020000 2437.540000 1902.120000 2438.020000 ;
+ RECT 1901.020000 2442.980000 1902.120000 2443.460000 ;
+ RECT 1946.020000 2399.460000 1947.120000 2399.940000 ;
+ RECT 1946.020000 2404.900000 1947.120000 2405.380000 ;
+ RECT 1946.020000 2410.340000 1947.120000 2410.820000 ;
+ RECT 1946.020000 2415.780000 1947.120000 2416.260000 ;
+ RECT 1946.020000 2421.220000 1947.120000 2421.700000 ;
+ RECT 1901.020000 2399.460000 1902.120000 2399.940000 ;
+ RECT 1901.020000 2404.900000 1902.120000 2405.380000 ;
+ RECT 1901.020000 2410.340000 1902.120000 2410.820000 ;
+ RECT 1901.020000 2415.780000 1902.120000 2416.260000 ;
+ RECT 1901.020000 2421.220000 1902.120000 2421.700000 ;
+ RECT 1852.190000 2442.980000 1853.190000 2443.460000 ;
+ RECT 1855.855000 2442.980000 1857.120000 2443.460000 ;
+ RECT 1852.190000 2437.540000 1853.190000 2438.020000 ;
+ RECT 1855.855000 2437.540000 1857.120000 2438.020000 ;
+ RECT 1852.190000 2432.100000 1853.190000 2432.580000 ;
+ RECT 1855.855000 2432.100000 1857.120000 2432.580000 ;
+ RECT 1852.190000 2426.660000 1853.190000 2427.140000 ;
+ RECT 1855.855000 2426.660000 1857.120000 2427.140000 ;
+ RECT 1852.190000 2421.220000 1853.190000 2421.700000 ;
+ RECT 1855.855000 2421.220000 1857.120000 2421.700000 ;
+ RECT 1852.190000 2415.780000 1853.190000 2416.260000 ;
+ RECT 1855.855000 2415.780000 1857.120000 2416.260000 ;
+ RECT 1852.190000 2404.900000 1853.190000 2405.380000 ;
+ RECT 1855.855000 2404.900000 1857.120000 2405.380000 ;
+ RECT 1852.190000 2410.340000 1853.190000 2410.820000 ;
+ RECT 1855.855000 2410.340000 1857.120000 2410.820000 ;
+ RECT 1852.190000 2399.460000 1853.190000 2399.940000 ;
+ RECT 1855.855000 2399.460000 1857.120000 2399.940000 ;
+ RECT 1946.020000 2377.700000 1947.120000 2378.180000 ;
+ RECT 1946.020000 2383.140000 1947.120000 2383.620000 ;
+ RECT 1946.020000 2388.580000 1947.120000 2389.060000 ;
+ RECT 1946.020000 2394.020000 1947.120000 2394.500000 ;
+ RECT 1901.020000 2377.700000 1902.120000 2378.180000 ;
+ RECT 1901.020000 2383.140000 1902.120000 2383.620000 ;
+ RECT 1901.020000 2388.580000 1902.120000 2389.060000 ;
+ RECT 1901.020000 2394.020000 1902.120000 2394.500000 ;
+ RECT 1946.020000 2355.940000 1947.120000 2356.420000 ;
+ RECT 1946.020000 2361.380000 1947.120000 2361.860000 ;
+ RECT 1946.020000 2366.820000 1947.120000 2367.300000 ;
+ RECT 1946.020000 2372.260000 1947.120000 2372.740000 ;
+ RECT 1901.020000 2355.940000 1902.120000 2356.420000 ;
+ RECT 1901.020000 2361.380000 1902.120000 2361.860000 ;
+ RECT 1901.020000 2366.820000 1902.120000 2367.300000 ;
+ RECT 1901.020000 2372.260000 1902.120000 2372.740000 ;
+ RECT 1852.190000 2394.020000 1853.190000 2394.500000 ;
+ RECT 1855.855000 2394.020000 1857.120000 2394.500000 ;
+ RECT 1852.190000 2388.580000 1853.190000 2389.060000 ;
+ RECT 1855.855000 2388.580000 1857.120000 2389.060000 ;
+ RECT 1852.190000 2383.140000 1853.190000 2383.620000 ;
+ RECT 1855.855000 2383.140000 1857.120000 2383.620000 ;
+ RECT 1852.190000 2377.700000 1853.190000 2378.180000 ;
+ RECT 1855.855000 2377.700000 1857.120000 2378.180000 ;
+ RECT 1852.190000 2372.260000 1853.190000 2372.740000 ;
+ RECT 1855.855000 2372.260000 1857.120000 2372.740000 ;
+ RECT 1852.190000 2361.380000 1853.190000 2361.860000 ;
+ RECT 1855.855000 2361.380000 1857.120000 2361.860000 ;
+ RECT 1852.190000 2366.820000 1853.190000 2367.300000 ;
+ RECT 1855.855000 2366.820000 1857.120000 2367.300000 ;
+ RECT 1852.190000 2355.940000 1853.190000 2356.420000 ;
+ RECT 1855.855000 2355.940000 1857.120000 2356.420000 ;
+ RECT 1991.020000 2448.420000 1992.120000 2448.900000 ;
+ RECT 2036.020000 2448.420000 2037.120000 2448.900000 ;
+ RECT 2048.830000 2448.420000 2049.830000 2448.900000 ;
+ RECT 1901.020000 2448.420000 1902.120000 2448.900000 ;
+ RECT 1946.020000 2448.420000 1947.120000 2448.900000 ;
+ RECT 1852.190000 2448.420000 1853.190000 2448.900000 ;
+ RECT 1855.855000 2448.420000 1857.120000 2448.900000 ;
+ RECT 1850.960000 2545.180000 2051.060000 2546.180000 ;
+ RECT 1850.960000 2349.610000 2051.060000 2350.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 2348.360000 1853.190000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 2547.620000 1853.190000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 2348.360000 2049.830000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 2547.620000 2049.830000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2349.610000 1851.960000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2349.610000 2051.060000 2350.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2545.180000 1851.960000 2546.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2545.180000 2051.060000 2546.180000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 2340.640000 1857.120000 2341.120000 ;
+ RECT 1855.855000 2329.760000 1857.120000 2330.240000 ;
+ RECT 1855.855000 2335.200000 1857.120000 2335.680000 ;
+ RECT 1855.855000 2324.320000 1857.120000 2324.800000 ;
+ RECT 1855.855000 2318.880000 1857.120000 2319.360000 ;
+ RECT 1855.855000 2313.440000 1857.120000 2313.920000 ;
+ RECT 1855.855000 2308.000000 1857.120000 2308.480000 ;
+ RECT 1855.855000 2302.560000 1857.120000 2303.040000 ;
+ RECT 1855.855000 2297.120000 1857.120000 2297.600000 ;
+ RECT 1855.855000 2286.240000 1857.120000 2286.720000 ;
+ RECT 1855.855000 2291.680000 1857.120000 2292.160000 ;
+ RECT 1855.855000 2280.800000 1857.120000 2281.280000 ;
+ RECT 1855.855000 2275.360000 1857.120000 2275.840000 ;
+ RECT 1855.855000 2269.920000 1857.120000 2270.400000 ;
+ RECT 1855.855000 2264.480000 1857.120000 2264.960000 ;
+ RECT 1855.855000 2259.040000 1857.120000 2259.520000 ;
+ RECT 1855.855000 2253.600000 1857.120000 2254.080000 ;
+ RECT 1855.855000 2242.720000 1857.120000 2243.200000 ;
+ RECT 1855.855000 2237.280000 1857.120000 2237.760000 ;
+ RECT 1855.855000 2231.840000 1857.120000 2232.320000 ;
+ RECT 1855.855000 2226.400000 1857.120000 2226.880000 ;
+ RECT 1855.855000 2220.960000 1857.120000 2221.440000 ;
+ RECT 1855.855000 2215.520000 1857.120000 2216.000000 ;
+ RECT 1855.855000 2204.640000 1857.120000 2205.120000 ;
+ RECT 1855.855000 2210.080000 1857.120000 2210.560000 ;
+ RECT 1855.855000 2199.200000 1857.120000 2199.680000 ;
+ RECT 1855.855000 2193.760000 1857.120000 2194.240000 ;
+ RECT 1855.855000 2188.320000 1857.120000 2188.800000 ;
+ RECT 1855.855000 2182.880000 1857.120000 2183.360000 ;
+ RECT 1855.855000 2177.440000 1857.120000 2177.920000 ;
+ RECT 1855.855000 2172.000000 1857.120000 2172.480000 ;
+ RECT 1855.855000 2161.120000 1857.120000 2161.600000 ;
+ RECT 1855.855000 2166.560000 1857.120000 2167.040000 ;
+ RECT 1855.855000 2155.680000 1857.120000 2156.160000 ;
+ RECT 1855.855000 2248.160000 1857.120000 2248.640000 ;
+ RECT 2036.020000 2149.350000 2037.120000 2345.920000 ;
+ RECT 1991.020000 2149.350000 1992.120000 2345.920000 ;
+ RECT 2048.830000 2148.100000 2049.830000 2348.360000 ;
+ RECT 1946.020000 2149.350000 1947.120000 2345.920000 ;
+ RECT 1901.020000 2149.350000 1902.120000 2345.920000 ;
+ RECT 1856.020000 2149.350000 1857.120000 2345.920000 ;
+ RECT 1852.190000 2148.100000 1853.190000 2348.360000 ;
+ LAYER met3 ;
+ RECT 2036.020000 2340.640000 2037.120000 2341.120000 ;
+ RECT 2048.830000 2340.640000 2049.830000 2341.120000 ;
+ RECT 2048.830000 2329.760000 2049.830000 2330.240000 ;
+ RECT 2048.830000 2324.320000 2049.830000 2324.800000 ;
+ RECT 2048.830000 2335.200000 2049.830000 2335.680000 ;
+ RECT 2036.020000 2335.200000 2037.120000 2335.680000 ;
+ RECT 2036.020000 2329.760000 2037.120000 2330.240000 ;
+ RECT 2036.020000 2324.320000 2037.120000 2324.800000 ;
+ RECT 2036.020000 2313.440000 2037.120000 2313.920000 ;
+ RECT 2036.020000 2318.880000 2037.120000 2319.360000 ;
+ RECT 2048.830000 2313.440000 2049.830000 2313.920000 ;
+ RECT 2048.830000 2318.880000 2049.830000 2319.360000 ;
+ RECT 2036.020000 2302.560000 2037.120000 2303.040000 ;
+ RECT 2036.020000 2308.000000 2037.120000 2308.480000 ;
+ RECT 2048.830000 2302.560000 2049.830000 2303.040000 ;
+ RECT 2048.830000 2308.000000 2049.830000 2308.480000 ;
+ RECT 1991.020000 2324.320000 1992.120000 2324.800000 ;
+ RECT 1991.020000 2329.760000 1992.120000 2330.240000 ;
+ RECT 1991.020000 2335.200000 1992.120000 2335.680000 ;
+ RECT 1991.020000 2340.640000 1992.120000 2341.120000 ;
+ RECT 1991.020000 2308.000000 1992.120000 2308.480000 ;
+ RECT 1991.020000 2302.560000 1992.120000 2303.040000 ;
+ RECT 1991.020000 2313.440000 1992.120000 2313.920000 ;
+ RECT 1991.020000 2318.880000 1992.120000 2319.360000 ;
+ RECT 2048.830000 2291.680000 2049.830000 2292.160000 ;
+ RECT 2048.830000 2286.240000 2049.830000 2286.720000 ;
+ RECT 2048.830000 2297.120000 2049.830000 2297.600000 ;
+ RECT 2036.020000 2297.120000 2037.120000 2297.600000 ;
+ RECT 2036.020000 2291.680000 2037.120000 2292.160000 ;
+ RECT 2036.020000 2286.240000 2037.120000 2286.720000 ;
+ RECT 2036.020000 2275.360000 2037.120000 2275.840000 ;
+ RECT 2036.020000 2280.800000 2037.120000 2281.280000 ;
+ RECT 2048.830000 2275.360000 2049.830000 2275.840000 ;
+ RECT 2048.830000 2280.800000 2049.830000 2281.280000 ;
+ RECT 2048.830000 2264.480000 2049.830000 2264.960000 ;
+ RECT 2048.830000 2269.920000 2049.830000 2270.400000 ;
+ RECT 2036.020000 2269.920000 2037.120000 2270.400000 ;
+ RECT 2036.020000 2264.480000 2037.120000 2264.960000 ;
+ RECT 2036.020000 2253.600000 2037.120000 2254.080000 ;
+ RECT 2036.020000 2259.040000 2037.120000 2259.520000 ;
+ RECT 2048.830000 2253.600000 2049.830000 2254.080000 ;
+ RECT 2048.830000 2259.040000 2049.830000 2259.520000 ;
+ RECT 1991.020000 2275.360000 1992.120000 2275.840000 ;
+ RECT 1991.020000 2280.800000 1992.120000 2281.280000 ;
+ RECT 1991.020000 2286.240000 1992.120000 2286.720000 ;
+ RECT 1991.020000 2291.680000 1992.120000 2292.160000 ;
+ RECT 1991.020000 2297.120000 1992.120000 2297.600000 ;
+ RECT 1991.020000 2253.600000 1992.120000 2254.080000 ;
+ RECT 1991.020000 2259.040000 1992.120000 2259.520000 ;
+ RECT 1991.020000 2264.480000 1992.120000 2264.960000 ;
+ RECT 1991.020000 2269.920000 1992.120000 2270.400000 ;
+ RECT 1946.020000 2329.760000 1947.120000 2330.240000 ;
+ RECT 1946.020000 2324.320000 1947.120000 2324.800000 ;
+ RECT 1946.020000 2335.200000 1947.120000 2335.680000 ;
+ RECT 1946.020000 2340.640000 1947.120000 2341.120000 ;
+ RECT 1901.020000 2324.320000 1902.120000 2324.800000 ;
+ RECT 1901.020000 2329.760000 1902.120000 2330.240000 ;
+ RECT 1901.020000 2335.200000 1902.120000 2335.680000 ;
+ RECT 1901.020000 2340.640000 1902.120000 2341.120000 ;
+ RECT 1946.020000 2302.560000 1947.120000 2303.040000 ;
+ RECT 1946.020000 2308.000000 1947.120000 2308.480000 ;
+ RECT 1946.020000 2313.440000 1947.120000 2313.920000 ;
+ RECT 1946.020000 2318.880000 1947.120000 2319.360000 ;
+ RECT 1901.020000 2302.560000 1902.120000 2303.040000 ;
+ RECT 1901.020000 2308.000000 1902.120000 2308.480000 ;
+ RECT 1901.020000 2313.440000 1902.120000 2313.920000 ;
+ RECT 1901.020000 2318.880000 1902.120000 2319.360000 ;
+ RECT 1852.190000 2340.640000 1853.190000 2341.120000 ;
+ RECT 1855.855000 2340.640000 1857.120000 2341.120000 ;
+ RECT 1852.190000 2329.760000 1853.190000 2330.240000 ;
+ RECT 1855.855000 2329.760000 1857.120000 2330.240000 ;
+ RECT 1852.190000 2335.200000 1853.190000 2335.680000 ;
+ RECT 1855.855000 2335.200000 1857.120000 2335.680000 ;
+ RECT 1852.190000 2324.320000 1853.190000 2324.800000 ;
+ RECT 1855.855000 2324.320000 1857.120000 2324.800000 ;
+ RECT 1852.190000 2318.880000 1853.190000 2319.360000 ;
+ RECT 1855.855000 2318.880000 1857.120000 2319.360000 ;
+ RECT 1852.190000 2313.440000 1853.190000 2313.920000 ;
+ RECT 1855.855000 2313.440000 1857.120000 2313.920000 ;
+ RECT 1852.190000 2308.000000 1853.190000 2308.480000 ;
+ RECT 1855.855000 2308.000000 1857.120000 2308.480000 ;
+ RECT 1852.190000 2302.560000 1853.190000 2303.040000 ;
+ RECT 1855.855000 2302.560000 1857.120000 2303.040000 ;
+ RECT 1946.020000 2275.360000 1947.120000 2275.840000 ;
+ RECT 1946.020000 2280.800000 1947.120000 2281.280000 ;
+ RECT 1946.020000 2286.240000 1947.120000 2286.720000 ;
+ RECT 1946.020000 2291.680000 1947.120000 2292.160000 ;
+ RECT 1946.020000 2297.120000 1947.120000 2297.600000 ;
+ RECT 1901.020000 2275.360000 1902.120000 2275.840000 ;
+ RECT 1901.020000 2280.800000 1902.120000 2281.280000 ;
+ RECT 1901.020000 2286.240000 1902.120000 2286.720000 ;
+ RECT 1901.020000 2291.680000 1902.120000 2292.160000 ;
+ RECT 1901.020000 2297.120000 1902.120000 2297.600000 ;
+ RECT 1946.020000 2253.600000 1947.120000 2254.080000 ;
+ RECT 1946.020000 2259.040000 1947.120000 2259.520000 ;
+ RECT 1946.020000 2264.480000 1947.120000 2264.960000 ;
+ RECT 1946.020000 2269.920000 1947.120000 2270.400000 ;
+ RECT 1901.020000 2253.600000 1902.120000 2254.080000 ;
+ RECT 1901.020000 2259.040000 1902.120000 2259.520000 ;
+ RECT 1901.020000 2264.480000 1902.120000 2264.960000 ;
+ RECT 1901.020000 2269.920000 1902.120000 2270.400000 ;
+ RECT 1852.190000 2297.120000 1853.190000 2297.600000 ;
+ RECT 1855.855000 2297.120000 1857.120000 2297.600000 ;
+ RECT 1852.190000 2286.240000 1853.190000 2286.720000 ;
+ RECT 1855.855000 2286.240000 1857.120000 2286.720000 ;
+ RECT 1852.190000 2291.680000 1853.190000 2292.160000 ;
+ RECT 1855.855000 2291.680000 1857.120000 2292.160000 ;
+ RECT 1852.190000 2280.800000 1853.190000 2281.280000 ;
+ RECT 1855.855000 2280.800000 1857.120000 2281.280000 ;
+ RECT 1852.190000 2275.360000 1853.190000 2275.840000 ;
+ RECT 1855.855000 2275.360000 1857.120000 2275.840000 ;
+ RECT 1852.190000 2269.920000 1853.190000 2270.400000 ;
+ RECT 1855.855000 2269.920000 1857.120000 2270.400000 ;
+ RECT 1852.190000 2264.480000 1853.190000 2264.960000 ;
+ RECT 1855.855000 2264.480000 1857.120000 2264.960000 ;
+ RECT 1852.190000 2259.040000 1853.190000 2259.520000 ;
+ RECT 1855.855000 2259.040000 1857.120000 2259.520000 ;
+ RECT 1852.190000 2253.600000 1853.190000 2254.080000 ;
+ RECT 1855.855000 2253.600000 1857.120000 2254.080000 ;
+ RECT 2036.020000 2237.280000 2037.120000 2237.760000 ;
+ RECT 2036.020000 2242.720000 2037.120000 2243.200000 ;
+ RECT 2048.830000 2237.280000 2049.830000 2237.760000 ;
+ RECT 2048.830000 2242.720000 2049.830000 2243.200000 ;
+ RECT 2048.830000 2226.400000 2049.830000 2226.880000 ;
+ RECT 2048.830000 2231.840000 2049.830000 2232.320000 ;
+ RECT 2036.020000 2231.840000 2037.120000 2232.320000 ;
+ RECT 2036.020000 2226.400000 2037.120000 2226.880000 ;
+ RECT 2036.020000 2215.520000 2037.120000 2216.000000 ;
+ RECT 2036.020000 2220.960000 2037.120000 2221.440000 ;
+ RECT 2048.830000 2215.520000 2049.830000 2216.000000 ;
+ RECT 2048.830000 2220.960000 2049.830000 2221.440000 ;
+ RECT 2048.830000 2204.640000 2049.830000 2205.120000 ;
+ RECT 2048.830000 2199.200000 2049.830000 2199.680000 ;
+ RECT 2048.830000 2210.080000 2049.830000 2210.560000 ;
+ RECT 2036.020000 2210.080000 2037.120000 2210.560000 ;
+ RECT 2036.020000 2204.640000 2037.120000 2205.120000 ;
+ RECT 2036.020000 2199.200000 2037.120000 2199.680000 ;
+ RECT 1991.020000 2226.400000 1992.120000 2226.880000 ;
+ RECT 1991.020000 2231.840000 1992.120000 2232.320000 ;
+ RECT 1991.020000 2237.280000 1992.120000 2237.760000 ;
+ RECT 1991.020000 2242.720000 1992.120000 2243.200000 ;
+ RECT 1991.020000 2199.200000 1992.120000 2199.680000 ;
+ RECT 1991.020000 2204.640000 1992.120000 2205.120000 ;
+ RECT 1991.020000 2210.080000 1992.120000 2210.560000 ;
+ RECT 1991.020000 2215.520000 1992.120000 2216.000000 ;
+ RECT 1991.020000 2220.960000 1992.120000 2221.440000 ;
+ RECT 2036.020000 2188.320000 2037.120000 2188.800000 ;
+ RECT 2036.020000 2193.760000 2037.120000 2194.240000 ;
+ RECT 2048.830000 2188.320000 2049.830000 2188.800000 ;
+ RECT 2048.830000 2193.760000 2049.830000 2194.240000 ;
+ RECT 2036.020000 2177.440000 2037.120000 2177.920000 ;
+ RECT 2036.020000 2182.880000 2037.120000 2183.360000 ;
+ RECT 2048.830000 2177.440000 2049.830000 2177.920000 ;
+ RECT 2048.830000 2182.880000 2049.830000 2183.360000 ;
+ RECT 2048.830000 2166.560000 2049.830000 2167.040000 ;
+ RECT 2048.830000 2161.120000 2049.830000 2161.600000 ;
+ RECT 2048.830000 2172.000000 2049.830000 2172.480000 ;
+ RECT 2036.020000 2172.000000 2037.120000 2172.480000 ;
+ RECT 2036.020000 2166.560000 2037.120000 2167.040000 ;
+ RECT 2036.020000 2161.120000 2037.120000 2161.600000 ;
+ RECT 2036.020000 2155.680000 2037.120000 2156.160000 ;
+ RECT 2048.830000 2155.680000 2049.830000 2156.160000 ;
+ RECT 1991.020000 2177.440000 1992.120000 2177.920000 ;
+ RECT 1991.020000 2182.880000 1992.120000 2183.360000 ;
+ RECT 1991.020000 2188.320000 1992.120000 2188.800000 ;
+ RECT 1991.020000 2193.760000 1992.120000 2194.240000 ;
+ RECT 1991.020000 2155.680000 1992.120000 2156.160000 ;
+ RECT 1991.020000 2161.120000 1992.120000 2161.600000 ;
+ RECT 1991.020000 2166.560000 1992.120000 2167.040000 ;
+ RECT 1991.020000 2172.000000 1992.120000 2172.480000 ;
+ RECT 1946.020000 2226.400000 1947.120000 2226.880000 ;
+ RECT 1946.020000 2231.840000 1947.120000 2232.320000 ;
+ RECT 1946.020000 2237.280000 1947.120000 2237.760000 ;
+ RECT 1946.020000 2242.720000 1947.120000 2243.200000 ;
+ RECT 1901.020000 2226.400000 1902.120000 2226.880000 ;
+ RECT 1901.020000 2231.840000 1902.120000 2232.320000 ;
+ RECT 1901.020000 2237.280000 1902.120000 2237.760000 ;
+ RECT 1901.020000 2242.720000 1902.120000 2243.200000 ;
+ RECT 1946.020000 2199.200000 1947.120000 2199.680000 ;
+ RECT 1946.020000 2204.640000 1947.120000 2205.120000 ;
+ RECT 1946.020000 2210.080000 1947.120000 2210.560000 ;
+ RECT 1946.020000 2215.520000 1947.120000 2216.000000 ;
+ RECT 1946.020000 2220.960000 1947.120000 2221.440000 ;
+ RECT 1901.020000 2199.200000 1902.120000 2199.680000 ;
+ RECT 1901.020000 2204.640000 1902.120000 2205.120000 ;
+ RECT 1901.020000 2210.080000 1902.120000 2210.560000 ;
+ RECT 1901.020000 2215.520000 1902.120000 2216.000000 ;
+ RECT 1901.020000 2220.960000 1902.120000 2221.440000 ;
+ RECT 1852.190000 2242.720000 1853.190000 2243.200000 ;
+ RECT 1855.855000 2242.720000 1857.120000 2243.200000 ;
+ RECT 1852.190000 2237.280000 1853.190000 2237.760000 ;
+ RECT 1855.855000 2237.280000 1857.120000 2237.760000 ;
+ RECT 1852.190000 2231.840000 1853.190000 2232.320000 ;
+ RECT 1855.855000 2231.840000 1857.120000 2232.320000 ;
+ RECT 1852.190000 2226.400000 1853.190000 2226.880000 ;
+ RECT 1855.855000 2226.400000 1857.120000 2226.880000 ;
+ RECT 1852.190000 2220.960000 1853.190000 2221.440000 ;
+ RECT 1855.855000 2220.960000 1857.120000 2221.440000 ;
+ RECT 1852.190000 2215.520000 1853.190000 2216.000000 ;
+ RECT 1855.855000 2215.520000 1857.120000 2216.000000 ;
+ RECT 1852.190000 2204.640000 1853.190000 2205.120000 ;
+ RECT 1855.855000 2204.640000 1857.120000 2205.120000 ;
+ RECT 1852.190000 2210.080000 1853.190000 2210.560000 ;
+ RECT 1855.855000 2210.080000 1857.120000 2210.560000 ;
+ RECT 1852.190000 2199.200000 1853.190000 2199.680000 ;
+ RECT 1855.855000 2199.200000 1857.120000 2199.680000 ;
+ RECT 1946.020000 2177.440000 1947.120000 2177.920000 ;
+ RECT 1946.020000 2182.880000 1947.120000 2183.360000 ;
+ RECT 1946.020000 2188.320000 1947.120000 2188.800000 ;
+ RECT 1946.020000 2193.760000 1947.120000 2194.240000 ;
+ RECT 1901.020000 2177.440000 1902.120000 2177.920000 ;
+ RECT 1901.020000 2182.880000 1902.120000 2183.360000 ;
+ RECT 1901.020000 2188.320000 1902.120000 2188.800000 ;
+ RECT 1901.020000 2193.760000 1902.120000 2194.240000 ;
+ RECT 1946.020000 2155.680000 1947.120000 2156.160000 ;
+ RECT 1946.020000 2161.120000 1947.120000 2161.600000 ;
+ RECT 1946.020000 2166.560000 1947.120000 2167.040000 ;
+ RECT 1946.020000 2172.000000 1947.120000 2172.480000 ;
+ RECT 1901.020000 2155.680000 1902.120000 2156.160000 ;
+ RECT 1901.020000 2161.120000 1902.120000 2161.600000 ;
+ RECT 1901.020000 2166.560000 1902.120000 2167.040000 ;
+ RECT 1901.020000 2172.000000 1902.120000 2172.480000 ;
+ RECT 1852.190000 2193.760000 1853.190000 2194.240000 ;
+ RECT 1855.855000 2193.760000 1857.120000 2194.240000 ;
+ RECT 1852.190000 2188.320000 1853.190000 2188.800000 ;
+ RECT 1855.855000 2188.320000 1857.120000 2188.800000 ;
+ RECT 1852.190000 2182.880000 1853.190000 2183.360000 ;
+ RECT 1855.855000 2182.880000 1857.120000 2183.360000 ;
+ RECT 1852.190000 2177.440000 1853.190000 2177.920000 ;
+ RECT 1855.855000 2177.440000 1857.120000 2177.920000 ;
+ RECT 1852.190000 2172.000000 1853.190000 2172.480000 ;
+ RECT 1855.855000 2172.000000 1857.120000 2172.480000 ;
+ RECT 1852.190000 2161.120000 1853.190000 2161.600000 ;
+ RECT 1855.855000 2161.120000 1857.120000 2161.600000 ;
+ RECT 1852.190000 2166.560000 1853.190000 2167.040000 ;
+ RECT 1855.855000 2166.560000 1857.120000 2167.040000 ;
+ RECT 1852.190000 2155.680000 1853.190000 2156.160000 ;
+ RECT 1855.855000 2155.680000 1857.120000 2156.160000 ;
+ RECT 1991.020000 2248.160000 1992.120000 2248.640000 ;
+ RECT 2036.020000 2248.160000 2037.120000 2248.640000 ;
+ RECT 2048.830000 2248.160000 2049.830000 2248.640000 ;
+ RECT 1901.020000 2248.160000 1902.120000 2248.640000 ;
+ RECT 1946.020000 2248.160000 1947.120000 2248.640000 ;
+ RECT 1852.190000 2248.160000 1853.190000 2248.640000 ;
+ RECT 1855.855000 2248.160000 1857.120000 2248.640000 ;
+ RECT 1850.960000 2344.920000 2051.060000 2345.920000 ;
+ RECT 1850.960000 2149.350000 2051.060000 2150.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 2148.100000 1853.190000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 2347.360000 1853.190000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 2148.100000 2049.830000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 2347.360000 2049.830000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2149.350000 1851.960000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2149.350000 2051.060000 2150.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2344.920000 1851.960000 2345.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2344.920000 2051.060000 2345.920000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 2140.380000 1857.120000 2140.860000 ;
+ RECT 1855.855000 2129.500000 1857.120000 2129.980000 ;
+ RECT 1855.855000 2134.940000 1857.120000 2135.420000 ;
+ RECT 1855.855000 2124.060000 1857.120000 2124.540000 ;
+ RECT 1855.855000 2118.620000 1857.120000 2119.100000 ;
+ RECT 1855.855000 2113.180000 1857.120000 2113.660000 ;
+ RECT 1855.855000 2107.740000 1857.120000 2108.220000 ;
+ RECT 1855.855000 2102.300000 1857.120000 2102.780000 ;
+ RECT 1855.855000 2096.860000 1857.120000 2097.340000 ;
+ RECT 1855.855000 2085.980000 1857.120000 2086.460000 ;
+ RECT 1855.855000 2091.420000 1857.120000 2091.900000 ;
+ RECT 1855.855000 2080.540000 1857.120000 2081.020000 ;
+ RECT 1855.855000 2075.100000 1857.120000 2075.580000 ;
+ RECT 1855.855000 2069.660000 1857.120000 2070.140000 ;
+ RECT 1855.855000 2064.220000 1857.120000 2064.700000 ;
+ RECT 1855.855000 2058.780000 1857.120000 2059.260000 ;
+ RECT 1855.855000 2053.340000 1857.120000 2053.820000 ;
+ RECT 1855.855000 2042.460000 1857.120000 2042.940000 ;
+ RECT 1855.855000 2037.020000 1857.120000 2037.500000 ;
+ RECT 1855.855000 2031.580000 1857.120000 2032.060000 ;
+ RECT 1855.855000 2026.140000 1857.120000 2026.620000 ;
+ RECT 1855.855000 2020.700000 1857.120000 2021.180000 ;
+ RECT 1855.855000 2015.260000 1857.120000 2015.740000 ;
+ RECT 1855.855000 2004.380000 1857.120000 2004.860000 ;
+ RECT 1855.855000 2009.820000 1857.120000 2010.300000 ;
+ RECT 1855.855000 1998.940000 1857.120000 1999.420000 ;
+ RECT 1855.855000 1993.500000 1857.120000 1993.980000 ;
+ RECT 1855.855000 1988.060000 1857.120000 1988.540000 ;
+ RECT 1855.855000 1982.620000 1857.120000 1983.100000 ;
+ RECT 1855.855000 1977.180000 1857.120000 1977.660000 ;
+ RECT 1855.855000 1971.740000 1857.120000 1972.220000 ;
+ RECT 1855.855000 1960.860000 1857.120000 1961.340000 ;
+ RECT 1855.855000 1966.300000 1857.120000 1966.780000 ;
+ RECT 1855.855000 1955.420000 1857.120000 1955.900000 ;
+ RECT 1855.855000 2047.900000 1857.120000 2048.380000 ;
+ RECT 2036.020000 1949.090000 2037.120000 2145.660000 ;
+ RECT 1991.020000 1949.090000 1992.120000 2145.660000 ;
+ RECT 2048.830000 1947.840000 2049.830000 2148.100000 ;
+ RECT 1946.020000 1949.090000 1947.120000 2145.660000 ;
+ RECT 1901.020000 1949.090000 1902.120000 2145.660000 ;
+ RECT 1856.020000 1949.090000 1857.120000 2145.660000 ;
+ RECT 1852.190000 1947.840000 1853.190000 2148.100000 ;
+ LAYER met3 ;
+ RECT 2036.020000 2140.380000 2037.120000 2140.860000 ;
+ RECT 2048.830000 2140.380000 2049.830000 2140.860000 ;
+ RECT 2048.830000 2129.500000 2049.830000 2129.980000 ;
+ RECT 2048.830000 2124.060000 2049.830000 2124.540000 ;
+ RECT 2048.830000 2134.940000 2049.830000 2135.420000 ;
+ RECT 2036.020000 2134.940000 2037.120000 2135.420000 ;
+ RECT 2036.020000 2129.500000 2037.120000 2129.980000 ;
+ RECT 2036.020000 2124.060000 2037.120000 2124.540000 ;
+ RECT 2036.020000 2113.180000 2037.120000 2113.660000 ;
+ RECT 2036.020000 2118.620000 2037.120000 2119.100000 ;
+ RECT 2048.830000 2113.180000 2049.830000 2113.660000 ;
+ RECT 2048.830000 2118.620000 2049.830000 2119.100000 ;
+ RECT 2036.020000 2102.300000 2037.120000 2102.780000 ;
+ RECT 2036.020000 2107.740000 2037.120000 2108.220000 ;
+ RECT 2048.830000 2102.300000 2049.830000 2102.780000 ;
+ RECT 2048.830000 2107.740000 2049.830000 2108.220000 ;
+ RECT 1991.020000 2124.060000 1992.120000 2124.540000 ;
+ RECT 1991.020000 2129.500000 1992.120000 2129.980000 ;
+ RECT 1991.020000 2134.940000 1992.120000 2135.420000 ;
+ RECT 1991.020000 2140.380000 1992.120000 2140.860000 ;
+ RECT 1991.020000 2107.740000 1992.120000 2108.220000 ;
+ RECT 1991.020000 2102.300000 1992.120000 2102.780000 ;
+ RECT 1991.020000 2113.180000 1992.120000 2113.660000 ;
+ RECT 1991.020000 2118.620000 1992.120000 2119.100000 ;
+ RECT 2048.830000 2091.420000 2049.830000 2091.900000 ;
+ RECT 2048.830000 2085.980000 2049.830000 2086.460000 ;
+ RECT 2048.830000 2096.860000 2049.830000 2097.340000 ;
+ RECT 2036.020000 2096.860000 2037.120000 2097.340000 ;
+ RECT 2036.020000 2091.420000 2037.120000 2091.900000 ;
+ RECT 2036.020000 2085.980000 2037.120000 2086.460000 ;
+ RECT 2036.020000 2075.100000 2037.120000 2075.580000 ;
+ RECT 2036.020000 2080.540000 2037.120000 2081.020000 ;
+ RECT 2048.830000 2075.100000 2049.830000 2075.580000 ;
+ RECT 2048.830000 2080.540000 2049.830000 2081.020000 ;
+ RECT 2048.830000 2064.220000 2049.830000 2064.700000 ;
+ RECT 2048.830000 2069.660000 2049.830000 2070.140000 ;
+ RECT 2036.020000 2069.660000 2037.120000 2070.140000 ;
+ RECT 2036.020000 2064.220000 2037.120000 2064.700000 ;
+ RECT 2036.020000 2053.340000 2037.120000 2053.820000 ;
+ RECT 2036.020000 2058.780000 2037.120000 2059.260000 ;
+ RECT 2048.830000 2053.340000 2049.830000 2053.820000 ;
+ RECT 2048.830000 2058.780000 2049.830000 2059.260000 ;
+ RECT 1991.020000 2075.100000 1992.120000 2075.580000 ;
+ RECT 1991.020000 2080.540000 1992.120000 2081.020000 ;
+ RECT 1991.020000 2085.980000 1992.120000 2086.460000 ;
+ RECT 1991.020000 2091.420000 1992.120000 2091.900000 ;
+ RECT 1991.020000 2096.860000 1992.120000 2097.340000 ;
+ RECT 1991.020000 2053.340000 1992.120000 2053.820000 ;
+ RECT 1991.020000 2058.780000 1992.120000 2059.260000 ;
+ RECT 1991.020000 2064.220000 1992.120000 2064.700000 ;
+ RECT 1991.020000 2069.660000 1992.120000 2070.140000 ;
+ RECT 1946.020000 2129.500000 1947.120000 2129.980000 ;
+ RECT 1946.020000 2124.060000 1947.120000 2124.540000 ;
+ RECT 1946.020000 2134.940000 1947.120000 2135.420000 ;
+ RECT 1946.020000 2140.380000 1947.120000 2140.860000 ;
+ RECT 1901.020000 2124.060000 1902.120000 2124.540000 ;
+ RECT 1901.020000 2129.500000 1902.120000 2129.980000 ;
+ RECT 1901.020000 2134.940000 1902.120000 2135.420000 ;
+ RECT 1901.020000 2140.380000 1902.120000 2140.860000 ;
+ RECT 1946.020000 2102.300000 1947.120000 2102.780000 ;
+ RECT 1946.020000 2107.740000 1947.120000 2108.220000 ;
+ RECT 1946.020000 2113.180000 1947.120000 2113.660000 ;
+ RECT 1946.020000 2118.620000 1947.120000 2119.100000 ;
+ RECT 1901.020000 2102.300000 1902.120000 2102.780000 ;
+ RECT 1901.020000 2107.740000 1902.120000 2108.220000 ;
+ RECT 1901.020000 2113.180000 1902.120000 2113.660000 ;
+ RECT 1901.020000 2118.620000 1902.120000 2119.100000 ;
+ RECT 1852.190000 2140.380000 1853.190000 2140.860000 ;
+ RECT 1855.855000 2140.380000 1857.120000 2140.860000 ;
+ RECT 1852.190000 2129.500000 1853.190000 2129.980000 ;
+ RECT 1855.855000 2129.500000 1857.120000 2129.980000 ;
+ RECT 1852.190000 2134.940000 1853.190000 2135.420000 ;
+ RECT 1855.855000 2134.940000 1857.120000 2135.420000 ;
+ RECT 1852.190000 2124.060000 1853.190000 2124.540000 ;
+ RECT 1855.855000 2124.060000 1857.120000 2124.540000 ;
+ RECT 1852.190000 2118.620000 1853.190000 2119.100000 ;
+ RECT 1855.855000 2118.620000 1857.120000 2119.100000 ;
+ RECT 1852.190000 2113.180000 1853.190000 2113.660000 ;
+ RECT 1855.855000 2113.180000 1857.120000 2113.660000 ;
+ RECT 1852.190000 2107.740000 1853.190000 2108.220000 ;
+ RECT 1855.855000 2107.740000 1857.120000 2108.220000 ;
+ RECT 1852.190000 2102.300000 1853.190000 2102.780000 ;
+ RECT 1855.855000 2102.300000 1857.120000 2102.780000 ;
+ RECT 1946.020000 2075.100000 1947.120000 2075.580000 ;
+ RECT 1946.020000 2080.540000 1947.120000 2081.020000 ;
+ RECT 1946.020000 2085.980000 1947.120000 2086.460000 ;
+ RECT 1946.020000 2091.420000 1947.120000 2091.900000 ;
+ RECT 1946.020000 2096.860000 1947.120000 2097.340000 ;
+ RECT 1901.020000 2075.100000 1902.120000 2075.580000 ;
+ RECT 1901.020000 2080.540000 1902.120000 2081.020000 ;
+ RECT 1901.020000 2085.980000 1902.120000 2086.460000 ;
+ RECT 1901.020000 2091.420000 1902.120000 2091.900000 ;
+ RECT 1901.020000 2096.860000 1902.120000 2097.340000 ;
+ RECT 1946.020000 2053.340000 1947.120000 2053.820000 ;
+ RECT 1946.020000 2058.780000 1947.120000 2059.260000 ;
+ RECT 1946.020000 2064.220000 1947.120000 2064.700000 ;
+ RECT 1946.020000 2069.660000 1947.120000 2070.140000 ;
+ RECT 1901.020000 2053.340000 1902.120000 2053.820000 ;
+ RECT 1901.020000 2058.780000 1902.120000 2059.260000 ;
+ RECT 1901.020000 2064.220000 1902.120000 2064.700000 ;
+ RECT 1901.020000 2069.660000 1902.120000 2070.140000 ;
+ RECT 1852.190000 2096.860000 1853.190000 2097.340000 ;
+ RECT 1855.855000 2096.860000 1857.120000 2097.340000 ;
+ RECT 1852.190000 2085.980000 1853.190000 2086.460000 ;
+ RECT 1855.855000 2085.980000 1857.120000 2086.460000 ;
+ RECT 1852.190000 2091.420000 1853.190000 2091.900000 ;
+ RECT 1855.855000 2091.420000 1857.120000 2091.900000 ;
+ RECT 1852.190000 2080.540000 1853.190000 2081.020000 ;
+ RECT 1855.855000 2080.540000 1857.120000 2081.020000 ;
+ RECT 1852.190000 2075.100000 1853.190000 2075.580000 ;
+ RECT 1855.855000 2075.100000 1857.120000 2075.580000 ;
+ RECT 1852.190000 2069.660000 1853.190000 2070.140000 ;
+ RECT 1855.855000 2069.660000 1857.120000 2070.140000 ;
+ RECT 1852.190000 2064.220000 1853.190000 2064.700000 ;
+ RECT 1855.855000 2064.220000 1857.120000 2064.700000 ;
+ RECT 1852.190000 2058.780000 1853.190000 2059.260000 ;
+ RECT 1855.855000 2058.780000 1857.120000 2059.260000 ;
+ RECT 1852.190000 2053.340000 1853.190000 2053.820000 ;
+ RECT 1855.855000 2053.340000 1857.120000 2053.820000 ;
+ RECT 2036.020000 2037.020000 2037.120000 2037.500000 ;
+ RECT 2036.020000 2042.460000 2037.120000 2042.940000 ;
+ RECT 2048.830000 2037.020000 2049.830000 2037.500000 ;
+ RECT 2048.830000 2042.460000 2049.830000 2042.940000 ;
+ RECT 2048.830000 2026.140000 2049.830000 2026.620000 ;
+ RECT 2048.830000 2031.580000 2049.830000 2032.060000 ;
+ RECT 2036.020000 2031.580000 2037.120000 2032.060000 ;
+ RECT 2036.020000 2026.140000 2037.120000 2026.620000 ;
+ RECT 2036.020000 2015.260000 2037.120000 2015.740000 ;
+ RECT 2036.020000 2020.700000 2037.120000 2021.180000 ;
+ RECT 2048.830000 2015.260000 2049.830000 2015.740000 ;
+ RECT 2048.830000 2020.700000 2049.830000 2021.180000 ;
+ RECT 2048.830000 2004.380000 2049.830000 2004.860000 ;
+ RECT 2048.830000 1998.940000 2049.830000 1999.420000 ;
+ RECT 2048.830000 2009.820000 2049.830000 2010.300000 ;
+ RECT 2036.020000 2009.820000 2037.120000 2010.300000 ;
+ RECT 2036.020000 2004.380000 2037.120000 2004.860000 ;
+ RECT 2036.020000 1998.940000 2037.120000 1999.420000 ;
+ RECT 1991.020000 2026.140000 1992.120000 2026.620000 ;
+ RECT 1991.020000 2031.580000 1992.120000 2032.060000 ;
+ RECT 1991.020000 2037.020000 1992.120000 2037.500000 ;
+ RECT 1991.020000 2042.460000 1992.120000 2042.940000 ;
+ RECT 1991.020000 1998.940000 1992.120000 1999.420000 ;
+ RECT 1991.020000 2004.380000 1992.120000 2004.860000 ;
+ RECT 1991.020000 2009.820000 1992.120000 2010.300000 ;
+ RECT 1991.020000 2015.260000 1992.120000 2015.740000 ;
+ RECT 1991.020000 2020.700000 1992.120000 2021.180000 ;
+ RECT 2036.020000 1988.060000 2037.120000 1988.540000 ;
+ RECT 2036.020000 1993.500000 2037.120000 1993.980000 ;
+ RECT 2048.830000 1988.060000 2049.830000 1988.540000 ;
+ RECT 2048.830000 1993.500000 2049.830000 1993.980000 ;
+ RECT 2036.020000 1977.180000 2037.120000 1977.660000 ;
+ RECT 2036.020000 1982.620000 2037.120000 1983.100000 ;
+ RECT 2048.830000 1977.180000 2049.830000 1977.660000 ;
+ RECT 2048.830000 1982.620000 2049.830000 1983.100000 ;
+ RECT 2048.830000 1966.300000 2049.830000 1966.780000 ;
+ RECT 2048.830000 1960.860000 2049.830000 1961.340000 ;
+ RECT 2048.830000 1971.740000 2049.830000 1972.220000 ;
+ RECT 2036.020000 1971.740000 2037.120000 1972.220000 ;
+ RECT 2036.020000 1966.300000 2037.120000 1966.780000 ;
+ RECT 2036.020000 1960.860000 2037.120000 1961.340000 ;
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+ RECT 1991.020000 1960.860000 1992.120000 1961.340000 ;
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+ RECT 1850.960000 2144.660000 2051.060000 2145.660000 ;
+ RECT 1850.960000 1949.090000 2051.060000 1950.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 1947.840000 1853.190000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 2147.100000 1853.190000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 1947.840000 2049.830000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 2147.100000 2049.830000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1949.090000 1851.960000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1949.090000 2051.060000 1950.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2144.660000 1851.960000 2145.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2144.660000 2051.060000 2145.660000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
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+ RECT 1855.855000 1836.760000 1857.120000 1837.240000 ;
+ RECT 1852.190000 1831.320000 1853.190000 1831.800000 ;
+ RECT 1855.855000 1831.320000 1857.120000 1831.800000 ;
+ RECT 1852.190000 1825.880000 1853.190000 1826.360000 ;
+ RECT 1855.855000 1825.880000 1857.120000 1826.360000 ;
+ RECT 1852.190000 1820.440000 1853.190000 1820.920000 ;
+ RECT 1855.855000 1820.440000 1857.120000 1820.920000 ;
+ RECT 1852.190000 1815.000000 1853.190000 1815.480000 ;
+ RECT 1855.855000 1815.000000 1857.120000 1815.480000 ;
+ RECT 1852.190000 1804.120000 1853.190000 1804.600000 ;
+ RECT 1855.855000 1804.120000 1857.120000 1804.600000 ;
+ RECT 1852.190000 1809.560000 1853.190000 1810.040000 ;
+ RECT 1855.855000 1809.560000 1857.120000 1810.040000 ;
+ RECT 1852.190000 1798.680000 1853.190000 1799.160000 ;
+ RECT 1855.855000 1798.680000 1857.120000 1799.160000 ;
+ RECT 1946.020000 1776.920000 1947.120000 1777.400000 ;
+ RECT 1946.020000 1782.360000 1947.120000 1782.840000 ;
+ RECT 1946.020000 1787.800000 1947.120000 1788.280000 ;
+ RECT 1946.020000 1793.240000 1947.120000 1793.720000 ;
+ RECT 1901.020000 1776.920000 1902.120000 1777.400000 ;
+ RECT 1901.020000 1782.360000 1902.120000 1782.840000 ;
+ RECT 1901.020000 1787.800000 1902.120000 1788.280000 ;
+ RECT 1901.020000 1793.240000 1902.120000 1793.720000 ;
+ RECT 1946.020000 1755.160000 1947.120000 1755.640000 ;
+ RECT 1946.020000 1760.600000 1947.120000 1761.080000 ;
+ RECT 1946.020000 1766.040000 1947.120000 1766.520000 ;
+ RECT 1946.020000 1771.480000 1947.120000 1771.960000 ;
+ RECT 1901.020000 1755.160000 1902.120000 1755.640000 ;
+ RECT 1901.020000 1760.600000 1902.120000 1761.080000 ;
+ RECT 1901.020000 1766.040000 1902.120000 1766.520000 ;
+ RECT 1901.020000 1771.480000 1902.120000 1771.960000 ;
+ RECT 1852.190000 1793.240000 1853.190000 1793.720000 ;
+ RECT 1855.855000 1793.240000 1857.120000 1793.720000 ;
+ RECT 1852.190000 1787.800000 1853.190000 1788.280000 ;
+ RECT 1855.855000 1787.800000 1857.120000 1788.280000 ;
+ RECT 1852.190000 1782.360000 1853.190000 1782.840000 ;
+ RECT 1855.855000 1782.360000 1857.120000 1782.840000 ;
+ RECT 1852.190000 1776.920000 1853.190000 1777.400000 ;
+ RECT 1855.855000 1776.920000 1857.120000 1777.400000 ;
+ RECT 1852.190000 1771.480000 1853.190000 1771.960000 ;
+ RECT 1855.855000 1771.480000 1857.120000 1771.960000 ;
+ RECT 1852.190000 1760.600000 1853.190000 1761.080000 ;
+ RECT 1855.855000 1760.600000 1857.120000 1761.080000 ;
+ RECT 1852.190000 1766.040000 1853.190000 1766.520000 ;
+ RECT 1855.855000 1766.040000 1857.120000 1766.520000 ;
+ RECT 1852.190000 1755.160000 1853.190000 1755.640000 ;
+ RECT 1855.855000 1755.160000 1857.120000 1755.640000 ;
+ RECT 1991.020000 1847.640000 1992.120000 1848.120000 ;
+ RECT 2036.020000 1847.640000 2037.120000 1848.120000 ;
+ RECT 2048.830000 1847.640000 2049.830000 1848.120000 ;
+ RECT 1901.020000 1847.640000 1902.120000 1848.120000 ;
+ RECT 1946.020000 1847.640000 1947.120000 1848.120000 ;
+ RECT 1852.190000 1847.640000 1853.190000 1848.120000 ;
+ RECT 1855.855000 1847.640000 1857.120000 1848.120000 ;
+ RECT 1850.960000 1944.400000 2051.060000 1945.400000 ;
+ RECT 1850.960000 1748.830000 2051.060000 1749.830000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 1747.580000 1853.190000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 1946.840000 1853.190000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 1747.580000 2049.830000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 1946.840000 2049.830000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1748.830000 1851.960000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1748.830000 2051.060000 1749.830000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1944.400000 1851.960000 1945.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1944.400000 2051.060000 1945.400000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1855.855000 1739.860000 1857.120000 1740.340000 ;
+ RECT 1855.855000 1728.980000 1857.120000 1729.460000 ;
+ RECT 1855.855000 1734.420000 1857.120000 1734.900000 ;
+ RECT 1855.855000 1723.540000 1857.120000 1724.020000 ;
+ RECT 1855.855000 1718.100000 1857.120000 1718.580000 ;
+ RECT 1855.855000 1712.660000 1857.120000 1713.140000 ;
+ RECT 1855.855000 1707.220000 1857.120000 1707.700000 ;
+ RECT 1855.855000 1701.780000 1857.120000 1702.260000 ;
+ RECT 1855.855000 1696.340000 1857.120000 1696.820000 ;
+ RECT 1855.855000 1685.460000 1857.120000 1685.940000 ;
+ RECT 1855.855000 1690.900000 1857.120000 1691.380000 ;
+ RECT 1855.855000 1680.020000 1857.120000 1680.500000 ;
+ RECT 1855.855000 1674.580000 1857.120000 1675.060000 ;
+ RECT 1855.855000 1669.140000 1857.120000 1669.620000 ;
+ RECT 1855.855000 1663.700000 1857.120000 1664.180000 ;
+ RECT 1855.855000 1658.260000 1857.120000 1658.740000 ;
+ RECT 1855.855000 1652.820000 1857.120000 1653.300000 ;
+ RECT 1855.855000 1641.940000 1857.120000 1642.420000 ;
+ RECT 1855.855000 1636.500000 1857.120000 1636.980000 ;
+ RECT 1855.855000 1631.060000 1857.120000 1631.540000 ;
+ RECT 1855.855000 1625.620000 1857.120000 1626.100000 ;
+ RECT 1855.855000 1620.180000 1857.120000 1620.660000 ;
+ RECT 1855.855000 1614.740000 1857.120000 1615.220000 ;
+ RECT 1855.855000 1603.860000 1857.120000 1604.340000 ;
+ RECT 1855.855000 1609.300000 1857.120000 1609.780000 ;
+ RECT 1855.855000 1598.420000 1857.120000 1598.900000 ;
+ RECT 1855.855000 1592.980000 1857.120000 1593.460000 ;
+ RECT 1855.855000 1587.540000 1857.120000 1588.020000 ;
+ RECT 1855.855000 1582.100000 1857.120000 1582.580000 ;
+ RECT 1855.855000 1576.660000 1857.120000 1577.140000 ;
+ RECT 1855.855000 1571.220000 1857.120000 1571.700000 ;
+ RECT 1855.855000 1560.340000 1857.120000 1560.820000 ;
+ RECT 1855.855000 1565.780000 1857.120000 1566.260000 ;
+ RECT 1855.855000 1554.900000 1857.120000 1555.380000 ;
+ RECT 1855.855000 1647.380000 1857.120000 1647.860000 ;
+ RECT 2036.020000 1548.570000 2037.120000 1745.140000 ;
+ RECT 1991.020000 1548.570000 1992.120000 1745.140000 ;
+ RECT 2048.830000 1547.320000 2049.830000 1747.580000 ;
+ RECT 1946.020000 1548.570000 1947.120000 1745.140000 ;
+ RECT 1901.020000 1548.570000 1902.120000 1745.140000 ;
+ RECT 1856.020000 1548.570000 1857.120000 1745.140000 ;
+ RECT 1852.190000 1547.320000 1853.190000 1747.580000 ;
+ LAYER met3 ;
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+ RECT 2048.830000 1739.860000 2049.830000 1740.340000 ;
+ RECT 2048.830000 1728.980000 2049.830000 1729.460000 ;
+ RECT 2048.830000 1723.540000 2049.830000 1724.020000 ;
+ RECT 2048.830000 1734.420000 2049.830000 1734.900000 ;
+ RECT 2036.020000 1734.420000 2037.120000 1734.900000 ;
+ RECT 2036.020000 1728.980000 2037.120000 1729.460000 ;
+ RECT 2036.020000 1723.540000 2037.120000 1724.020000 ;
+ RECT 2036.020000 1712.660000 2037.120000 1713.140000 ;
+ RECT 2036.020000 1718.100000 2037.120000 1718.580000 ;
+ RECT 2048.830000 1712.660000 2049.830000 1713.140000 ;
+ RECT 2048.830000 1718.100000 2049.830000 1718.580000 ;
+ RECT 2036.020000 1701.780000 2037.120000 1702.260000 ;
+ RECT 2036.020000 1707.220000 2037.120000 1707.700000 ;
+ RECT 2048.830000 1701.780000 2049.830000 1702.260000 ;
+ RECT 2048.830000 1707.220000 2049.830000 1707.700000 ;
+ RECT 1991.020000 1723.540000 1992.120000 1724.020000 ;
+ RECT 1991.020000 1728.980000 1992.120000 1729.460000 ;
+ RECT 1991.020000 1734.420000 1992.120000 1734.900000 ;
+ RECT 1991.020000 1739.860000 1992.120000 1740.340000 ;
+ RECT 1991.020000 1707.220000 1992.120000 1707.700000 ;
+ RECT 1991.020000 1701.780000 1992.120000 1702.260000 ;
+ RECT 1991.020000 1712.660000 1992.120000 1713.140000 ;
+ RECT 1991.020000 1718.100000 1992.120000 1718.580000 ;
+ RECT 2048.830000 1690.900000 2049.830000 1691.380000 ;
+ RECT 2048.830000 1685.460000 2049.830000 1685.940000 ;
+ RECT 2048.830000 1696.340000 2049.830000 1696.820000 ;
+ RECT 2036.020000 1696.340000 2037.120000 1696.820000 ;
+ RECT 2036.020000 1690.900000 2037.120000 1691.380000 ;
+ RECT 2036.020000 1685.460000 2037.120000 1685.940000 ;
+ RECT 2036.020000 1674.580000 2037.120000 1675.060000 ;
+ RECT 2036.020000 1680.020000 2037.120000 1680.500000 ;
+ RECT 2048.830000 1674.580000 2049.830000 1675.060000 ;
+ RECT 2048.830000 1680.020000 2049.830000 1680.500000 ;
+ RECT 2048.830000 1663.700000 2049.830000 1664.180000 ;
+ RECT 2048.830000 1669.140000 2049.830000 1669.620000 ;
+ RECT 2036.020000 1669.140000 2037.120000 1669.620000 ;
+ RECT 2036.020000 1663.700000 2037.120000 1664.180000 ;
+ RECT 2036.020000 1652.820000 2037.120000 1653.300000 ;
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+ RECT 2048.830000 1652.820000 2049.830000 1653.300000 ;
+ RECT 2048.830000 1658.260000 2049.830000 1658.740000 ;
+ RECT 1991.020000 1674.580000 1992.120000 1675.060000 ;
+ RECT 1991.020000 1680.020000 1992.120000 1680.500000 ;
+ RECT 1991.020000 1685.460000 1992.120000 1685.940000 ;
+ RECT 1991.020000 1690.900000 1992.120000 1691.380000 ;
+ RECT 1991.020000 1696.340000 1992.120000 1696.820000 ;
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+ RECT 1991.020000 1658.260000 1992.120000 1658.740000 ;
+ RECT 1991.020000 1663.700000 1992.120000 1664.180000 ;
+ RECT 1991.020000 1669.140000 1992.120000 1669.620000 ;
+ RECT 1946.020000 1728.980000 1947.120000 1729.460000 ;
+ RECT 1946.020000 1723.540000 1947.120000 1724.020000 ;
+ RECT 1946.020000 1734.420000 1947.120000 1734.900000 ;
+ RECT 1946.020000 1739.860000 1947.120000 1740.340000 ;
+ RECT 1901.020000 1723.540000 1902.120000 1724.020000 ;
+ RECT 1901.020000 1728.980000 1902.120000 1729.460000 ;
+ RECT 1901.020000 1734.420000 1902.120000 1734.900000 ;
+ RECT 1901.020000 1739.860000 1902.120000 1740.340000 ;
+ RECT 1946.020000 1701.780000 1947.120000 1702.260000 ;
+ RECT 1946.020000 1707.220000 1947.120000 1707.700000 ;
+ RECT 1946.020000 1712.660000 1947.120000 1713.140000 ;
+ RECT 1946.020000 1718.100000 1947.120000 1718.580000 ;
+ RECT 1901.020000 1701.780000 1902.120000 1702.260000 ;
+ RECT 1901.020000 1707.220000 1902.120000 1707.700000 ;
+ RECT 1901.020000 1712.660000 1902.120000 1713.140000 ;
+ RECT 1901.020000 1718.100000 1902.120000 1718.580000 ;
+ RECT 1852.190000 1739.860000 1853.190000 1740.340000 ;
+ RECT 1855.855000 1739.860000 1857.120000 1740.340000 ;
+ RECT 1852.190000 1728.980000 1853.190000 1729.460000 ;
+ RECT 1855.855000 1728.980000 1857.120000 1729.460000 ;
+ RECT 1852.190000 1734.420000 1853.190000 1734.900000 ;
+ RECT 1855.855000 1734.420000 1857.120000 1734.900000 ;
+ RECT 1852.190000 1723.540000 1853.190000 1724.020000 ;
+ RECT 1855.855000 1723.540000 1857.120000 1724.020000 ;
+ RECT 1852.190000 1718.100000 1853.190000 1718.580000 ;
+ RECT 1855.855000 1718.100000 1857.120000 1718.580000 ;
+ RECT 1852.190000 1712.660000 1853.190000 1713.140000 ;
+ RECT 1855.855000 1712.660000 1857.120000 1713.140000 ;
+ RECT 1852.190000 1707.220000 1853.190000 1707.700000 ;
+ RECT 1855.855000 1707.220000 1857.120000 1707.700000 ;
+ RECT 1852.190000 1701.780000 1853.190000 1702.260000 ;
+ RECT 1855.855000 1701.780000 1857.120000 1702.260000 ;
+ RECT 1946.020000 1674.580000 1947.120000 1675.060000 ;
+ RECT 1946.020000 1680.020000 1947.120000 1680.500000 ;
+ RECT 1946.020000 1685.460000 1947.120000 1685.940000 ;
+ RECT 1946.020000 1690.900000 1947.120000 1691.380000 ;
+ RECT 1946.020000 1696.340000 1947.120000 1696.820000 ;
+ RECT 1901.020000 1674.580000 1902.120000 1675.060000 ;
+ RECT 1901.020000 1680.020000 1902.120000 1680.500000 ;
+ RECT 1901.020000 1685.460000 1902.120000 1685.940000 ;
+ RECT 1901.020000 1690.900000 1902.120000 1691.380000 ;
+ RECT 1901.020000 1696.340000 1902.120000 1696.820000 ;
+ RECT 1946.020000 1652.820000 1947.120000 1653.300000 ;
+ RECT 1946.020000 1658.260000 1947.120000 1658.740000 ;
+ RECT 1946.020000 1663.700000 1947.120000 1664.180000 ;
+ RECT 1946.020000 1669.140000 1947.120000 1669.620000 ;
+ RECT 1901.020000 1652.820000 1902.120000 1653.300000 ;
+ RECT 1901.020000 1658.260000 1902.120000 1658.740000 ;
+ RECT 1901.020000 1663.700000 1902.120000 1664.180000 ;
+ RECT 1901.020000 1669.140000 1902.120000 1669.620000 ;
+ RECT 1852.190000 1696.340000 1853.190000 1696.820000 ;
+ RECT 1855.855000 1696.340000 1857.120000 1696.820000 ;
+ RECT 1852.190000 1685.460000 1853.190000 1685.940000 ;
+ RECT 1855.855000 1685.460000 1857.120000 1685.940000 ;
+ RECT 1852.190000 1690.900000 1853.190000 1691.380000 ;
+ RECT 1855.855000 1690.900000 1857.120000 1691.380000 ;
+ RECT 1852.190000 1680.020000 1853.190000 1680.500000 ;
+ RECT 1855.855000 1680.020000 1857.120000 1680.500000 ;
+ RECT 1852.190000 1674.580000 1853.190000 1675.060000 ;
+ RECT 1855.855000 1674.580000 1857.120000 1675.060000 ;
+ RECT 1852.190000 1669.140000 1853.190000 1669.620000 ;
+ RECT 1855.855000 1669.140000 1857.120000 1669.620000 ;
+ RECT 1852.190000 1663.700000 1853.190000 1664.180000 ;
+ RECT 1855.855000 1663.700000 1857.120000 1664.180000 ;
+ RECT 1852.190000 1658.260000 1853.190000 1658.740000 ;
+ RECT 1855.855000 1658.260000 1857.120000 1658.740000 ;
+ RECT 1852.190000 1652.820000 1853.190000 1653.300000 ;
+ RECT 1855.855000 1652.820000 1857.120000 1653.300000 ;
+ RECT 2036.020000 1636.500000 2037.120000 1636.980000 ;
+ RECT 2036.020000 1641.940000 2037.120000 1642.420000 ;
+ RECT 2048.830000 1636.500000 2049.830000 1636.980000 ;
+ RECT 2048.830000 1641.940000 2049.830000 1642.420000 ;
+ RECT 2048.830000 1625.620000 2049.830000 1626.100000 ;
+ RECT 2048.830000 1631.060000 2049.830000 1631.540000 ;
+ RECT 2036.020000 1631.060000 2037.120000 1631.540000 ;
+ RECT 2036.020000 1625.620000 2037.120000 1626.100000 ;
+ RECT 2036.020000 1614.740000 2037.120000 1615.220000 ;
+ RECT 2036.020000 1620.180000 2037.120000 1620.660000 ;
+ RECT 2048.830000 1614.740000 2049.830000 1615.220000 ;
+ RECT 2048.830000 1620.180000 2049.830000 1620.660000 ;
+ RECT 2048.830000 1603.860000 2049.830000 1604.340000 ;
+ RECT 2048.830000 1598.420000 2049.830000 1598.900000 ;
+ RECT 2048.830000 1609.300000 2049.830000 1609.780000 ;
+ RECT 2036.020000 1609.300000 2037.120000 1609.780000 ;
+ RECT 2036.020000 1603.860000 2037.120000 1604.340000 ;
+ RECT 2036.020000 1598.420000 2037.120000 1598.900000 ;
+ RECT 1991.020000 1625.620000 1992.120000 1626.100000 ;
+ RECT 1991.020000 1631.060000 1992.120000 1631.540000 ;
+ RECT 1991.020000 1636.500000 1992.120000 1636.980000 ;
+ RECT 1991.020000 1641.940000 1992.120000 1642.420000 ;
+ RECT 1991.020000 1598.420000 1992.120000 1598.900000 ;
+ RECT 1991.020000 1603.860000 1992.120000 1604.340000 ;
+ RECT 1991.020000 1609.300000 1992.120000 1609.780000 ;
+ RECT 1991.020000 1614.740000 1992.120000 1615.220000 ;
+ RECT 1991.020000 1620.180000 1992.120000 1620.660000 ;
+ RECT 2036.020000 1587.540000 2037.120000 1588.020000 ;
+ RECT 2036.020000 1592.980000 2037.120000 1593.460000 ;
+ RECT 2048.830000 1587.540000 2049.830000 1588.020000 ;
+ RECT 2048.830000 1592.980000 2049.830000 1593.460000 ;
+ RECT 2036.020000 1576.660000 2037.120000 1577.140000 ;
+ RECT 2036.020000 1582.100000 2037.120000 1582.580000 ;
+ RECT 2048.830000 1576.660000 2049.830000 1577.140000 ;
+ RECT 2048.830000 1582.100000 2049.830000 1582.580000 ;
+ RECT 2048.830000 1565.780000 2049.830000 1566.260000 ;
+ RECT 2048.830000 1560.340000 2049.830000 1560.820000 ;
+ RECT 2048.830000 1571.220000 2049.830000 1571.700000 ;
+ RECT 2036.020000 1571.220000 2037.120000 1571.700000 ;
+ RECT 2036.020000 1565.780000 2037.120000 1566.260000 ;
+ RECT 2036.020000 1560.340000 2037.120000 1560.820000 ;
+ RECT 2036.020000 1554.900000 2037.120000 1555.380000 ;
+ RECT 2048.830000 1554.900000 2049.830000 1555.380000 ;
+ RECT 1991.020000 1576.660000 1992.120000 1577.140000 ;
+ RECT 1991.020000 1582.100000 1992.120000 1582.580000 ;
+ RECT 1991.020000 1587.540000 1992.120000 1588.020000 ;
+ RECT 1991.020000 1592.980000 1992.120000 1593.460000 ;
+ RECT 1991.020000 1554.900000 1992.120000 1555.380000 ;
+ RECT 1991.020000 1560.340000 1992.120000 1560.820000 ;
+ RECT 1991.020000 1565.780000 1992.120000 1566.260000 ;
+ RECT 1991.020000 1571.220000 1992.120000 1571.700000 ;
+ RECT 1946.020000 1625.620000 1947.120000 1626.100000 ;
+ RECT 1946.020000 1631.060000 1947.120000 1631.540000 ;
+ RECT 1946.020000 1636.500000 1947.120000 1636.980000 ;
+ RECT 1946.020000 1641.940000 1947.120000 1642.420000 ;
+ RECT 1901.020000 1625.620000 1902.120000 1626.100000 ;
+ RECT 1901.020000 1631.060000 1902.120000 1631.540000 ;
+ RECT 1901.020000 1636.500000 1902.120000 1636.980000 ;
+ RECT 1901.020000 1641.940000 1902.120000 1642.420000 ;
+ RECT 1946.020000 1598.420000 1947.120000 1598.900000 ;
+ RECT 1946.020000 1603.860000 1947.120000 1604.340000 ;
+ RECT 1946.020000 1609.300000 1947.120000 1609.780000 ;
+ RECT 1946.020000 1614.740000 1947.120000 1615.220000 ;
+ RECT 1946.020000 1620.180000 1947.120000 1620.660000 ;
+ RECT 1901.020000 1598.420000 1902.120000 1598.900000 ;
+ RECT 1901.020000 1603.860000 1902.120000 1604.340000 ;
+ RECT 1901.020000 1609.300000 1902.120000 1609.780000 ;
+ RECT 1901.020000 1614.740000 1902.120000 1615.220000 ;
+ RECT 1901.020000 1620.180000 1902.120000 1620.660000 ;
+ RECT 1852.190000 1641.940000 1853.190000 1642.420000 ;
+ RECT 1855.855000 1641.940000 1857.120000 1642.420000 ;
+ RECT 1852.190000 1636.500000 1853.190000 1636.980000 ;
+ RECT 1855.855000 1636.500000 1857.120000 1636.980000 ;
+ RECT 1852.190000 1631.060000 1853.190000 1631.540000 ;
+ RECT 1855.855000 1631.060000 1857.120000 1631.540000 ;
+ RECT 1852.190000 1625.620000 1853.190000 1626.100000 ;
+ RECT 1855.855000 1625.620000 1857.120000 1626.100000 ;
+ RECT 1852.190000 1620.180000 1853.190000 1620.660000 ;
+ RECT 1855.855000 1620.180000 1857.120000 1620.660000 ;
+ RECT 1852.190000 1614.740000 1853.190000 1615.220000 ;
+ RECT 1855.855000 1614.740000 1857.120000 1615.220000 ;
+ RECT 1852.190000 1603.860000 1853.190000 1604.340000 ;
+ RECT 1855.855000 1603.860000 1857.120000 1604.340000 ;
+ RECT 1852.190000 1609.300000 1853.190000 1609.780000 ;
+ RECT 1855.855000 1609.300000 1857.120000 1609.780000 ;
+ RECT 1852.190000 1598.420000 1853.190000 1598.900000 ;
+ RECT 1855.855000 1598.420000 1857.120000 1598.900000 ;
+ RECT 1946.020000 1576.660000 1947.120000 1577.140000 ;
+ RECT 1946.020000 1582.100000 1947.120000 1582.580000 ;
+ RECT 1946.020000 1587.540000 1947.120000 1588.020000 ;
+ RECT 1946.020000 1592.980000 1947.120000 1593.460000 ;
+ RECT 1901.020000 1576.660000 1902.120000 1577.140000 ;
+ RECT 1901.020000 1582.100000 1902.120000 1582.580000 ;
+ RECT 1901.020000 1587.540000 1902.120000 1588.020000 ;
+ RECT 1901.020000 1592.980000 1902.120000 1593.460000 ;
+ RECT 1946.020000 1554.900000 1947.120000 1555.380000 ;
+ RECT 1946.020000 1560.340000 1947.120000 1560.820000 ;
+ RECT 1946.020000 1565.780000 1947.120000 1566.260000 ;
+ RECT 1946.020000 1571.220000 1947.120000 1571.700000 ;
+ RECT 1901.020000 1554.900000 1902.120000 1555.380000 ;
+ RECT 1901.020000 1560.340000 1902.120000 1560.820000 ;
+ RECT 1901.020000 1565.780000 1902.120000 1566.260000 ;
+ RECT 1901.020000 1571.220000 1902.120000 1571.700000 ;
+ RECT 1852.190000 1592.980000 1853.190000 1593.460000 ;
+ RECT 1855.855000 1592.980000 1857.120000 1593.460000 ;
+ RECT 1852.190000 1587.540000 1853.190000 1588.020000 ;
+ RECT 1855.855000 1587.540000 1857.120000 1588.020000 ;
+ RECT 1852.190000 1582.100000 1853.190000 1582.580000 ;
+ RECT 1855.855000 1582.100000 1857.120000 1582.580000 ;
+ RECT 1852.190000 1576.660000 1853.190000 1577.140000 ;
+ RECT 1855.855000 1576.660000 1857.120000 1577.140000 ;
+ RECT 1852.190000 1571.220000 1853.190000 1571.700000 ;
+ RECT 1855.855000 1571.220000 1857.120000 1571.700000 ;
+ RECT 1852.190000 1560.340000 1853.190000 1560.820000 ;
+ RECT 1855.855000 1560.340000 1857.120000 1560.820000 ;
+ RECT 1852.190000 1565.780000 1853.190000 1566.260000 ;
+ RECT 1855.855000 1565.780000 1857.120000 1566.260000 ;
+ RECT 1852.190000 1554.900000 1853.190000 1555.380000 ;
+ RECT 1855.855000 1554.900000 1857.120000 1555.380000 ;
+ RECT 1991.020000 1647.380000 1992.120000 1647.860000 ;
+ RECT 2036.020000 1647.380000 2037.120000 1647.860000 ;
+ RECT 2048.830000 1647.380000 2049.830000 1647.860000 ;
+ RECT 1901.020000 1647.380000 1902.120000 1647.860000 ;
+ RECT 1946.020000 1647.380000 1947.120000 1647.860000 ;
+ RECT 1852.190000 1647.380000 1853.190000 1647.860000 ;
+ RECT 1855.855000 1647.380000 1857.120000 1647.860000 ;
+ RECT 1850.960000 1744.140000 2051.060000 1745.140000 ;
+ RECT 1850.960000 1548.570000 2051.060000 1549.570000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 1547.320000 1853.190000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1852.190000 1746.580000 1853.190000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 1547.320000 2049.830000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2048.830000 1746.580000 2049.830000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1548.570000 1851.960000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1548.570000 2051.060000 1549.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1744.140000 1851.960000 1745.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1744.140000 2051.060000 1745.140000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+ END vssd1
+ PIN vccd1
+ DIRECTION INOUT ;
+ USE POWER ;
+
+# P/G power stripe data as pin
+ PORT
+ LAYER met3 ;
+ RECT 6.000000 6.000000 2834.040000 9.000000 ;
+ RECT 239.300000 118.420000 2186.200000 118.900000 ;
+ RECT 154.320000 141.140000 2051.560000 142.140000 ;
+ RECT 439.760000 141.140000 2186.200000 142.140000 ;
+ RECT 154.320000 141.140000 1851.460000 142.140000 ;
+ RECT 639.860000 141.140000 2186.200000 142.140000 ;
+ RECT 839.960000 141.140000 2186.200000 142.140000 ;
+ RECT 1040.060000 141.140000 2186.200000 142.140000 ;
+ RECT 1240.160000 141.140000 2186.200000 142.140000 ;
+ RECT 639.860000 118.090000 2186.200000 119.090000 ;
+ RECT 154.320000 118.090000 1851.460000 119.090000 ;
+ RECT 839.960000 118.090000 2186.200000 119.090000 ;
+ RECT 439.760000 118.090000 2186.200000 119.090000 ;
+ RECT 154.320000 118.090000 2051.560000 119.090000 ;
+ RECT 1240.160000 118.090000 2186.200000 119.090000 ;
+ RECT 154.320000 109.440000 2186.200000 110.440000 ;
+ RECT 239.660000 1342.020000 1444.860000 1343.020000 ;
+ RECT 154.320000 141.140000 440.760000 142.140000 ;
+ RECT 154.320000 141.140000 240.660000 142.140000 ;
+ RECT 154.320000 118.090000 240.660000 119.090000 ;
+ RECT 154.320000 148.350000 160.620000 149.350000 ;
+ RECT 436.730000 118.090000 437.730000 119.090000 ;
+ RECT 437.230000 118.090000 440.760000 119.090000 ;
+ RECT 154.320000 348.510000 236.830000 349.510000 ;
+ RECT 154.320000 348.610000 160.620000 349.610000 ;
+ RECT 154.320000 348.510000 163.450000 349.510000 ;
+ RECT 162.950000 348.510000 163.950000 349.510000 ;
+ RECT 154.320000 340.720000 160.620000 341.720000 ;
+ RECT 236.330000 348.510000 237.330000 349.510000 ;
+ RECT 239.160000 348.610000 239.660000 349.610000 ;
+ RECT 239.160000 340.720000 239.660000 341.720000 ;
+ RECT 154.320000 548.770000 236.830000 549.770000 ;
+ RECT 154.320000 548.770000 163.450000 549.770000 ;
+ RECT 154.320000 548.870000 160.620000 549.870000 ;
+ RECT 154.320000 540.980000 160.620000 541.980000 ;
+ RECT 162.950000 548.770000 163.950000 549.770000 ;
+ RECT 236.330000 548.770000 237.330000 549.770000 ;
+ RECT 239.160000 540.980000 239.660000 541.980000 ;
+ RECT 239.160000 548.870000 239.660000 549.870000 ;
+ RECT 154.320000 749.030000 236.830000 750.030000 ;
+ RECT 154.320000 749.030000 163.450000 750.030000 ;
+ RECT 154.320000 749.130000 160.620000 750.130000 ;
+ RECT 154.320000 741.240000 160.620000 742.240000 ;
+ RECT 162.950000 749.030000 163.950000 750.030000 ;
+ RECT 236.330000 749.030000 237.330000 750.030000 ;
+ RECT 239.160000 749.130000 239.660000 750.130000 ;
+ RECT 239.160000 741.240000 239.660000 742.240000 ;
+ RECT 636.830000 118.090000 637.830000 119.090000 ;
+ RECT 637.330000 118.090000 640.860000 119.090000 ;
+ RECT 636.830000 141.140000 637.830000 142.140000 ;
+ RECT 637.330000 141.140000 640.860000 142.140000 ;
+ RECT 836.930000 118.090000 837.930000 119.090000 ;
+ RECT 837.430000 118.090000 840.960000 119.090000 ;
+ RECT 836.930000 141.140000 837.930000 142.140000 ;
+ RECT 837.430000 141.140000 840.960000 142.140000 ;
+ RECT 1037.530000 141.140000 1041.060000 142.140000 ;
+ RECT 1037.030000 141.140000 1038.030000 142.140000 ;
+ RECT 1037.530000 118.090000 1041.060000 119.090000 ;
+ RECT 1037.030000 118.090000 1038.030000 119.090000 ;
+ RECT 1237.630000 118.090000 1241.160000 119.090000 ;
+ RECT 1237.130000 118.090000 1238.130000 119.090000 ;
+ RECT 1237.130000 141.140000 1238.130000 142.140000 ;
+ RECT 1237.630000 141.140000 1241.160000 142.140000 ;
+ RECT 154.320000 949.290000 236.830000 950.290000 ;
+ RECT 154.320000 949.290000 163.450000 950.290000 ;
+ RECT 154.320000 949.390000 160.620000 950.390000 ;
+ RECT 154.320000 941.500000 160.620000 942.500000 ;
+ RECT 162.950000 949.290000 163.950000 950.290000 ;
+ RECT 236.330000 949.290000 237.330000 950.290000 ;
+ RECT 239.160000 949.390000 239.660000 950.390000 ;
+ RECT 239.160000 941.500000 239.660000 942.500000 ;
+ RECT 154.320000 1149.550000 236.830000 1150.550000 ;
+ RECT 154.320000 1149.550000 163.450000 1150.550000 ;
+ RECT 154.320000 1149.620000 163.450000 1150.620000 ;
+ RECT 154.320000 1149.650000 160.620000 1150.650000 ;
+ RECT 154.320000 1141.760000 160.620000 1142.760000 ;
+ RECT 162.950000 1149.620000 163.950000 1150.620000 ;
+ RECT 162.950000 1149.550000 163.950000 1150.550000 ;
+ RECT 236.330000 1149.550000 237.330000 1150.550000 ;
+ RECT 239.160000 1149.650000 239.660000 1150.650000 ;
+ RECT 239.160000 1141.760000 239.660000 1142.760000 ;
+ RECT 154.320000 1342.020000 160.620000 1343.020000 ;
+ RECT 154.320000 1349.810000 236.830000 1350.810000 ;
+ RECT 154.320000 1349.810000 163.450000 1350.810000 ;
+ RECT 154.320000 1349.910000 160.620000 1350.910000 ;
+ RECT 162.950000 1349.810000 163.950000 1350.810000 ;
+ RECT 236.330000 1349.810000 237.330000 1350.810000 ;
+ RECT 239.160000 1349.910000 239.660000 1350.910000 ;
+ RECT 154.320000 1550.070000 236.830000 1551.070000 ;
+ RECT 154.320000 1550.070000 163.450000 1551.070000 ;
+ RECT 154.320000 1542.280000 160.620000 1543.280000 ;
+ RECT 154.320000 1550.170000 160.620000 1551.170000 ;
+ RECT 162.950000 1550.070000 163.950000 1551.070000 ;
+ RECT 236.330000 1550.070000 237.330000 1551.070000 ;
+ RECT 239.160000 1550.170000 239.660000 1551.170000 ;
+ RECT 239.160000 1542.280000 239.660000 1543.280000 ;
+ RECT 2185.200000 32.460000 2726.720000 33.460000 ;
+ RECT 1444.860000 118.090000 1446.260000 119.090000 ;
+ RECT 1440.260000 141.140000 1441.870000 142.140000 ;
+ RECT 1444.860000 141.140000 1446.260000 142.140000 ;
+ RECT 1649.790000 118.090000 1651.360000 119.090000 ;
+ RECT 1646.530000 141.140000 1647.530000 142.140000 ;
+ RECT 1645.360000 141.140000 1647.030000 142.140000 ;
+ RECT 1649.790000 141.140000 1651.360000 142.140000 ;
+ RECT 2050.560000 141.140000 2186.200000 142.140000 ;
+ RECT 1850.460000 141.140000 1854.030000 142.140000 ;
+ RECT 1853.530000 141.140000 1854.530000 142.140000 ;
+ RECT 2160.500000 118.090000 2186.200000 119.090000 ;
+ RECT 2160.500000 141.140000 2186.200000 142.140000 ;
+ RECT 2157.670000 148.250000 2186.200000 149.250000 ;
+ RECT 2157.170000 148.250000 2158.170000 149.250000 ;
+ RECT 2720.520000 41.110000 2726.720000 41.910000 ;
+ RECT 2720.520000 453.830000 2726.720000 454.630000 ;
+ RECT 1444.360000 1342.020000 1445.360000 1343.020000 ;
+ RECT 1444.360000 1342.670000 1445.360000 1343.670000 ;
+ RECT 1444.860000 1342.670000 1647.030000 1343.670000 ;
+ RECT 1646.530000 1342.670000 1647.530000 1343.670000 ;
+ RECT 1646.530000 1342.020000 1647.530000 1343.020000 ;
+ RECT 1647.030000 1342.020000 2186.200000 1343.020000 ;
+ RECT 239.660000 1742.540000 1444.860000 1743.540000 ;
+ RECT 239.660000 2143.060000 1444.860000 2144.060000 ;
+ RECT 239.660000 2543.580000 1444.860000 2544.580000 ;
+ RECT 639.860000 3352.510000 2186.200000 3353.510000 ;
+ RECT 1240.160000 3375.560000 2186.200000 3376.560000 ;
+ RECT 1040.060000 3375.560000 2186.200000 3376.560000 ;
+ RECT 839.960000 3375.560000 2186.200000 3376.560000 ;
+ RECT 639.860000 3375.560000 2186.200000 3376.560000 ;
+ RECT 439.760000 3375.560000 2186.200000 3376.560000 ;
+ RECT 6.000000 3430.780000 2834.040000 3433.780000 ;
+ RECT 154.320000 1750.330000 236.830000 1751.330000 ;
+ RECT 154.320000 1742.540000 160.620000 1743.540000 ;
+ RECT 154.320000 1750.330000 163.450000 1751.330000 ;
+ RECT 154.320000 1750.430000 160.620000 1751.430000 ;
+ RECT 162.950000 1750.330000 163.950000 1751.330000 ;
+ RECT 236.330000 1750.330000 237.330000 1751.330000 ;
+ RECT 239.160000 1750.430000 239.660000 1751.430000 ;
+ RECT 154.320000 1950.550000 236.830000 1951.550000 ;
+ RECT 154.320000 1950.550000 163.450000 1951.550000 ;
+ RECT 154.320000 1942.800000 160.620000 1943.800000 ;
+ RECT 154.320000 1950.690000 160.620000 1951.690000 ;
+ RECT 162.950000 1950.550000 163.950000 1951.550000 ;
+ RECT 236.330000 1950.550000 237.330000 1951.550000 ;
+ RECT 239.160000 1950.690000 239.660000 1951.690000 ;
+ RECT 239.160000 1942.800000 239.660000 1943.800000 ;
+ RECT 154.320000 2143.060000 160.620000 2144.060000 ;
+ RECT 154.320000 2150.850000 236.830000 2151.850000 ;
+ RECT 154.320000 2150.850000 163.450000 2151.850000 ;
+ RECT 154.320000 2150.950000 160.620000 2151.950000 ;
+ RECT 162.950000 2150.850000 163.950000 2151.850000 ;
+ RECT 236.330000 2150.850000 237.330000 2151.850000 ;
+ RECT 239.160000 2150.950000 239.660000 2151.950000 ;
+ RECT 154.320000 2351.110000 236.830000 2352.110000 ;
+ RECT 154.320000 2351.110000 163.450000 2352.110000 ;
+ RECT 154.320000 2343.320000 160.620000 2344.320000 ;
+ RECT 154.320000 2351.210000 160.620000 2352.210000 ;
+ RECT 162.950000 2351.110000 163.950000 2352.110000 ;
+ RECT 236.330000 2351.110000 237.330000 2352.110000 ;
+ RECT 239.160000 2351.210000 239.660000 2352.210000 ;
+ RECT 239.160000 2343.320000 239.660000 2344.320000 ;
+ RECT 154.320000 2551.370000 236.830000 2552.370000 ;
+ RECT 154.320000 2551.370000 163.450000 2552.370000 ;
+ RECT 154.320000 2543.580000 160.620000 2544.580000 ;
+ RECT 154.320000 2551.470000 160.620000 2552.470000 ;
+ RECT 162.950000 2551.370000 163.950000 2552.370000 ;
+ RECT 236.330000 2551.370000 237.330000 2552.370000 ;
+ RECT 239.160000 2551.470000 239.660000 2552.470000 ;
+ RECT 154.320000 3352.510000 840.960000 3353.510000 ;
+ RECT 154.320000 3352.510000 640.860000 3353.510000 ;
+ RECT 154.320000 3375.560000 640.860000 3376.560000 ;
+ RECT 154.320000 2751.630000 163.450000 2752.630000 ;
+ RECT 154.320000 2743.840000 160.620000 2744.840000 ;
+ RECT 154.320000 2751.730000 160.620000 2752.730000 ;
+ RECT 162.950000 2751.630000 163.950000 2752.630000 ;
+ RECT 239.160000 2751.730000 239.660000 2752.730000 ;
+ RECT 239.160000 2743.840000 239.660000 2744.840000 ;
+ RECT 154.320000 2951.890000 163.450000 2952.890000 ;
+ RECT 154.320000 2944.100000 160.620000 2945.100000 ;
+ RECT 154.320000 2951.990000 160.620000 2952.990000 ;
+ RECT 162.950000 2951.890000 163.950000 2952.890000 ;
+ RECT 239.160000 2951.990000 239.660000 2952.990000 ;
+ RECT 239.160000 2944.100000 239.660000 2945.100000 ;
+ RECT 154.320000 3152.150000 163.450000 3153.150000 ;
+ RECT 154.320000 3152.250000 160.620000 3153.250000 ;
+ RECT 154.320000 3144.360000 160.620000 3145.360000 ;
+ RECT 162.950000 3152.150000 163.950000 3153.150000 ;
+ RECT 239.160000 3144.360000 239.660000 3145.360000 ;
+ RECT 154.320000 3352.510000 440.760000 3353.510000 ;
+ RECT 154.320000 3375.560000 440.760000 3376.560000 ;
+ RECT 154.320000 3375.560000 240.660000 3376.560000 ;
+ RECT 154.320000 3352.510000 240.660000 3353.510000 ;
+ RECT 154.320000 3344.620000 160.620000 3345.620000 ;
+ RECT 239.160000 3344.620000 239.660000 3345.620000 ;
+ RECT 836.930000 3375.560000 837.930000 3376.560000 ;
+ RECT 837.430000 3375.560000 840.960000 3376.560000 ;
+ RECT 1037.030000 3375.560000 1038.030000 3376.560000 ;
+ RECT 1037.530000 3375.560000 1041.060000 3376.560000 ;
+ RECT 1037.030000 3352.510000 1038.030000 3353.510000 ;
+ RECT 1037.530000 3352.510000 1041.060000 3353.510000 ;
+ RECT 1237.130000 3375.560000 1238.130000 3376.560000 ;
+ RECT 1237.630000 3375.560000 1241.160000 3376.560000 ;
+ RECT 1237.130000 3352.510000 1238.130000 3353.510000 ;
+ RECT 1237.630000 3352.510000 1241.160000 3353.510000 ;
+ RECT 1647.030000 1742.540000 2186.200000 1743.540000 ;
+ RECT 1647.030000 2143.310000 2186.200000 2144.310000 ;
+ RECT 1646.530000 2143.310000 1647.530000 2144.310000 ;
+ RECT 1646.530000 2143.710000 1647.530000 2144.710000 ;
+ RECT 1444.860000 2143.710000 1647.030000 2144.710000 ;
+ RECT 1444.360000 2143.710000 1445.360000 2144.710000 ;
+ RECT 1444.360000 2143.060000 1445.360000 2144.060000 ;
+ RECT 1646.530000 1742.540000 1647.530000 1743.540000 ;
+ RECT 1646.530000 1743.150000 1647.530000 1744.150000 ;
+ RECT 1444.860000 1743.150000 1647.030000 1744.150000 ;
+ RECT 1444.360000 1743.150000 1445.360000 1744.150000 ;
+ RECT 1444.360000 1742.540000 1445.360000 1743.540000 ;
+ RECT 1444.360000 2543.580000 1445.360000 2544.580000 ;
+ RECT 1444.360000 2544.230000 1445.360000 2545.230000 ;
+ RECT 1444.860000 2544.230000 1647.030000 2545.230000 ;
+ RECT 1646.530000 2544.230000 1647.530000 2545.230000 ;
+ RECT 1646.530000 2543.580000 1647.530000 2544.580000 ;
+ RECT 1647.030000 2543.580000 2186.200000 2544.580000 ;
+ RECT 1847.820000 3352.510000 1851.460000 3353.510000 ;
+ RECT 1847.820000 3375.560000 1851.460000 3376.560000 ;
+ RECT 1645.360000 3352.510000 2186.200000 3353.510000 ;
+ RECT 1645.360000 3375.560000 2186.200000 3376.560000 ;
+ RECT 1444.360000 3375.560000 1445.360000 3376.560000 ;
+ RECT 1444.860000 3375.560000 1446.260000 3376.560000 ;
+ RECT 1441.370000 3375.560000 1442.370000 3376.560000 ;
+ RECT 1440.260000 3375.560000 1441.870000 3376.560000 ;
+ RECT 1444.360000 3352.510000 1445.360000 3353.510000 ;
+ RECT 1444.860000 3352.510000 1446.260000 3353.510000 ;
+ RECT 1649.790000 3375.560000 1651.360000 3376.560000 ;
+ RECT 1649.790000 3352.510000 1651.360000 3353.510000 ;
+ RECT 1847.320000 3375.560000 1848.320000 3376.560000 ;
+ RECT 1847.320000 3352.510000 1848.320000 3353.510000 ;
+ RECT 1850.460000 3375.560000 2186.200000 3376.560000 ;
+ RECT 2050.560000 3375.560000 2186.200000 3376.560000 ;
+ RECT 2047.420000 3375.560000 2048.420000 3376.560000 ;
+ RECT 2047.920000 3375.560000 2051.560000 3376.560000 ;
+ RECT 2047.420000 3352.510000 2048.420000 3353.510000 ;
+ RECT 2047.920000 3352.510000 2051.560000 3353.510000 ;
+ RECT 2160.500000 3375.560000 2186.200000 3376.560000 ;
+ RECT 2160.500000 3352.510000 2186.200000 3353.510000 ;
+ RECT 2717.690000 2975.450000 2726.720000 2976.250000 ;
+ RECT 2717.290000 2975.450000 2718.090000 2976.250000 ;
+ RECT 2720.520000 3395.510000 2726.720000 3396.310000 ;
+ RECT 6.000000 25.940000 9.000000 26.420000 ;
+ RECT 6.000000 20.500000 9.000000 20.980000 ;
+ RECT 6.000000 15.060000 9.000000 15.540000 ;
+ RECT 6.000000 9.620000 9.000000 10.100000 ;
+ RECT 6.000000 31.380000 9.000000 31.860000 ;
+ RECT 6.000000 36.820000 9.000000 37.300000 ;
+ RECT 6.000000 42.260000 9.000000 42.740000 ;
+ RECT 6.000000 47.700000 9.000000 48.180000 ;
+ RECT 6.000000 53.140000 9.000000 53.620000 ;
+ RECT 6.000000 80.340000 9.000000 80.820000 ;
+ RECT 6.000000 58.580000 9.000000 59.060000 ;
+ RECT 6.000000 64.020000 9.000000 64.500000 ;
+ RECT 6.000000 69.460000 9.000000 69.940000 ;
+ RECT 6.000000 74.900000 9.000000 75.380000 ;
+ RECT 6.000000 85.780000 9.000000 86.260000 ;
+ RECT 6.000000 91.220000 9.000000 91.700000 ;
+ RECT 6.000000 96.660000 9.000000 97.140000 ;
+ RECT 6.000000 102.100000 9.000000 102.580000 ;
+ RECT 6.000000 107.540000 9.000000 108.020000 ;
+ RECT 6.000000 112.980000 9.000000 113.460000 ;
+ RECT 6.000000 118.420000 9.000000 118.900000 ;
+ RECT 6.000000 123.860000 9.000000 124.340000 ;
+ RECT 6.000000 129.300000 9.000000 129.780000 ;
+ RECT 6.000000 134.740000 9.000000 135.220000 ;
+ RECT 6.000000 140.180000 9.000000 140.660000 ;
+ RECT 6.000000 145.620000 9.000000 146.100000 ;
+ RECT 6.000000 151.060000 9.000000 151.540000 ;
+ RECT 6.000000 156.500000 9.000000 156.980000 ;
+ RECT 6.000000 161.940000 9.000000 162.420000 ;
+ RECT 6.000000 167.380000 9.000000 167.860000 ;
+ RECT 6.000000 172.820000 9.000000 173.300000 ;
+ RECT 6.000000 178.260000 9.000000 178.740000 ;
+ RECT 6.000000 183.700000 9.000000 184.180000 ;
+ RECT 6.000000 189.140000 9.000000 189.620000 ;
+ RECT 6.000000 194.580000 9.000000 195.060000 ;
+ RECT 6.000000 200.020000 9.000000 200.500000 ;
+ RECT 6.000000 205.460000 9.000000 205.940000 ;
+ RECT 6.000000 210.900000 9.000000 211.380000 ;
+ RECT 6.000000 216.340000 9.000000 216.820000 ;
+ RECT 6.000000 221.780000 9.000000 222.260000 ;
+ RECT 6.000000 227.220000 9.000000 227.700000 ;
+ RECT 6.000000 232.660000 9.000000 233.140000 ;
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+ RECT 1036.730000 109.440000 1037.730000 3350.160000 ;
+ RECT 1043.390000 109.440000 1044.390000 3350.160000 ;
+ RECT 1243.490000 109.440000 1244.490000 3350.160000 ;
+ RECT 1236.830000 109.440000 1237.830000 3350.160000 ;
+ RECT 2193.830000 32.460000 2194.630000 2980.340000 ;
+ RECT 2193.830000 458.100000 2194.630000 3433.780000 ;
+ RECT 2717.290000 458.100000 2718.090000 3433.780000 ;
+ RECT 1436.930000 109.440000 1437.930000 3350.160000 ;
+ RECT 2831.040000 6.000000 2834.040000 3433.780000 ;
+ RECT 2725.720000 6.000000 2726.720000 3433.780000 ;
+ RECT 2185.200000 6.000000 2186.200000 3433.780000 ;
+ RECT 2157.170000 109.440000 2158.170000 3350.160000 ;
+ RECT 2053.890000 109.440000 2054.890000 3350.160000 ;
+ RECT 2047.230000 109.440000 2048.230000 3350.160000 ;
+ RECT 1853.790000 109.440000 1854.790000 3350.160000 ;
+ RECT 1847.130000 109.440000 1848.130000 3350.160000 ;
+ RECT 1653.690000 109.440000 1654.690000 3350.160000 ;
+ RECT 236.330000 109.440000 237.330000 1147.300000 ;
+ RECT 236.330000 109.440000 237.330000 1347.560000 ;
+ RECT 236.330000 109.440000 237.330000 1547.820000 ;
+ RECT 236.330000 109.440000 237.330000 947.040000 ;
+ RECT 162.950000 109.440000 163.950000 1147.300000 ;
+ RECT 162.950000 109.440000 163.950000 1347.560000 ;
+ RECT 162.950000 109.440000 163.950000 1547.820000 ;
+ RECT 162.950000 109.440000 163.950000 947.040000 ;
+ RECT 162.950000 109.440000 163.950000 546.520000 ;
+ RECT 162.950000 109.440000 163.950000 746.780000 ;
+ RECT 236.330000 109.440000 237.330000 751.380000 ;
+ RECT 236.330000 109.440000 237.330000 746.780000 ;
+ RECT 236.330000 109.440000 237.330000 551.120000 ;
+ RECT 236.330000 109.440000 237.330000 546.520000 ;
+ RECT 162.950000 109.440000 163.950000 346.260000 ;
+ RECT 236.330000 109.440000 237.330000 350.860000 ;
+ RECT 236.330000 109.440000 237.330000 346.260000 ;
+ RECT 162.950000 109.440000 163.950000 146.000000 ;
+ RECT 162.950000 109.440000 163.950000 150.600000 ;
+ RECT 236.330000 109.440000 237.330000 146.000000 ;
+ RECT 242.990000 109.440000 243.990000 115.740000 ;
+ RECT 242.990000 109.440000 243.990000 120.340000 ;
+ RECT 242.990000 144.500000 243.990000 145.000000 ;
+ RECT 436.430000 109.440000 437.430000 115.740000 ;
+ RECT 443.090000 109.440000 444.090000 120.340000 ;
+ RECT 443.090000 109.440000 444.090000 115.740000 ;
+ RECT 436.730000 109.440000 437.730000 118.590000 ;
+ RECT 436.430000 144.500000 437.430000 145.000000 ;
+ RECT 443.090000 144.500000 444.090000 145.000000 ;
+ RECT 162.950000 345.260000 163.950000 349.010000 ;
+ RECT 236.330000 345.260000 237.330000 349.010000 ;
+ RECT 153.300000 548.180000 155.320000 548.660000 ;
+ RECT 162.950000 545.520000 163.950000 549.270000 ;
+ RECT 236.330000 545.520000 237.330000 549.270000 ;
+ RECT 162.950000 745.780000 163.950000 749.530000 ;
+ RECT 236.330000 745.780000 237.330000 749.530000 ;
+ RECT 636.830000 109.440000 637.830000 141.640000 ;
+ RECT 643.190000 109.440000 644.190000 120.340000 ;
+ RECT 636.530000 109.440000 637.530000 115.740000 ;
+ RECT 643.190000 109.440000 644.190000 115.740000 ;
+ RECT 636.830000 109.440000 637.830000 118.590000 ;
+ RECT 643.190000 144.500000 644.190000 145.000000 ;
+ RECT 636.530000 144.500000 637.530000 145.000000 ;
+ RECT 836.930000 109.440000 837.930000 141.640000 ;
+ RECT 843.290000 109.440000 844.290000 120.340000 ;
+ RECT 836.630000 109.440000 837.630000 115.740000 ;
+ RECT 843.290000 109.440000 844.290000 115.740000 ;
+ RECT 836.930000 109.440000 837.930000 118.590000 ;
+ RECT 843.290000 144.500000 844.290000 145.000000 ;
+ RECT 836.630000 144.500000 837.630000 145.000000 ;
+ RECT 1043.390000 109.440000 1044.390000 120.340000 ;
+ RECT 1043.390000 109.440000 1044.390000 115.740000 ;
+ RECT 1043.390000 144.500000 1044.390000 145.000000 ;
+ RECT 1036.730000 144.500000 1037.730000 145.000000 ;
+ RECT 1037.030000 109.440000 1038.030000 141.640000 ;
+ RECT 1037.030000 109.440000 1038.030000 118.590000 ;
+ RECT 1036.730000 109.440000 1037.730000 115.740000 ;
+ RECT 1237.130000 109.440000 1238.130000 141.640000 ;
+ RECT 1243.490000 109.440000 1244.490000 120.340000 ;
+ RECT 1243.490000 109.440000 1244.490000 115.740000 ;
+ RECT 1236.830000 109.440000 1237.830000 115.740000 ;
+ RECT 1237.130000 109.440000 1238.130000 118.590000 ;
+ RECT 1243.490000 144.500000 1244.490000 145.000000 ;
+ RECT 1236.830000 144.500000 1237.830000 145.000000 ;
+ RECT 162.950000 949.790000 163.950000 951.640000 ;
+ RECT 162.950000 946.040000 163.950000 949.790000 ;
+ RECT 236.330000 946.040000 237.330000 949.790000 ;
+ RECT 153.300000 1141.140000 155.320000 1141.620000 ;
+ RECT 162.950000 1150.120000 163.950000 1151.900000 ;
+ RECT 162.950000 1146.300000 163.950000 1150.050000 ;
+ RECT 236.330000 1146.300000 237.330000 1150.050000 ;
+ RECT 162.950000 1350.310000 163.950000 1352.160000 ;
+ RECT 162.950000 1346.560000 163.950000 1350.310000 ;
+ RECT 236.330000 1346.560000 237.330000 1350.310000 ;
+ RECT 162.950000 1550.570000 163.950000 1552.420000 ;
+ RECT 162.950000 1546.820000 163.950000 1550.570000 ;
+ RECT 236.330000 1546.820000 237.330000 1550.570000 ;
+ RECT 1448.590000 109.440000 1449.590000 120.340000 ;
+ RECT 1448.590000 109.440000 1449.590000 115.740000 ;
+ RECT 1436.930000 109.440000 1437.930000 115.740000 ;
+ RECT 1436.930000 144.500000 1437.930000 145.000000 ;
+ RECT 1448.590000 144.500000 1449.590000 145.000000 ;
+ RECT 1646.530000 109.440000 1647.530000 141.640000 ;
+ RECT 1653.690000 109.440000 1654.690000 120.340000 ;
+ RECT 1653.690000 109.440000 1654.690000 115.740000 ;
+ RECT 1642.030000 109.440000 1643.030000 115.740000 ;
+ RECT 1653.690000 144.500000 1654.690000 145.000000 ;
+ RECT 1642.030000 144.500000 1643.030000 145.000000 ;
+ RECT 1847.130000 144.500000 1848.130000 145.000000 ;
+ RECT 1847.130000 109.440000 1848.130000 115.740000 ;
+ RECT 1853.790000 144.500000 1854.790000 145.000000 ;
+ RECT 1853.530000 109.440000 1854.530000 141.640000 ;
+ RECT 1853.790000 109.440000 1854.790000 115.740000 ;
+ RECT 1853.790000 109.440000 1854.790000 120.340000 ;
+ RECT 2047.230000 144.500000 2048.230000 145.000000 ;
+ RECT 2053.890000 144.500000 2054.890000 145.000000 ;
+ RECT 2047.230000 109.440000 2048.230000 115.740000 ;
+ RECT 2053.890000 109.440000 2054.890000 115.740000 ;
+ RECT 2053.890000 109.440000 2054.890000 120.340000 ;
+ RECT 2193.830000 32.460000 2194.630000 43.360000 ;
+ RECT 2193.830000 32.460000 2194.630000 38.660000 ;
+ RECT 2157.170000 145.000000 2158.170000 148.750000 ;
+ RECT 2157.170000 109.440000 2158.170000 115.740000 ;
+ RECT 2694.710000 32.460000 2695.710000 56.530000 ;
+ RECT 2717.290000 32.460000 2718.090000 38.660000 ;
+ RECT 1444.360000 1342.520000 1445.360000 1343.170000 ;
+ RECT 1646.530000 1342.520000 1647.530000 1343.170000 ;
+ RECT 236.330000 2538.420000 237.330000 3433.780000 ;
+ RECT 236.330000 1937.640000 237.330000 3433.780000 ;
+ RECT 236.330000 2137.900000 237.330000 3433.780000 ;
+ RECT 236.330000 2338.160000 237.330000 3433.780000 ;
+ RECT 236.330000 2147.600000 237.330000 2151.350000 ;
+ RECT 162.950000 2147.600000 163.950000 2151.350000 ;
+ RECT 162.950000 1747.080000 163.950000 1750.830000 ;
+ RECT 236.330000 1747.080000 237.330000 1750.830000 ;
+ RECT 153.300000 1951.700000 155.320000 1952.180000 ;
+ RECT 162.950000 1947.340000 163.950000 1951.050000 ;
+ RECT 236.330000 1947.340000 237.330000 1951.050000 ;
+ RECT 162.950000 2347.860000 163.950000 2351.610000 ;
+ RECT 236.330000 2347.860000 237.330000 2351.610000 ;
+ RECT 153.300000 2544.660000 155.320000 2545.140000 ;
+ RECT 162.950000 2548.120000 163.950000 2551.870000 ;
+ RECT 236.330000 2548.120000 237.330000 2551.870000 ;
+ RECT 236.330000 2738.680000 237.330000 3433.780000 ;
+ RECT 236.330000 2748.380000 237.330000 3433.780000 ;
+ RECT 236.330000 2938.940000 237.330000 3433.780000 ;
+ RECT 236.330000 2948.640000 237.330000 3433.780000 ;
+ RECT 162.950000 2748.380000 163.950000 2752.130000 ;
+ RECT 162.950000 2948.640000 163.950000 2952.390000 ;
+ RECT 236.330000 3139.200000 237.330000 3433.780000 ;
+ RECT 236.330000 3148.900000 237.330000 3433.780000 ;
+ RECT 162.950000 3148.900000 163.950000 3152.650000 ;
+ RECT 236.330000 3339.460000 237.330000 3433.780000 ;
+ RECT 162.950000 3349.160000 163.950000 3433.780000 ;
+ RECT 236.330000 3349.160000 237.330000 3433.780000 ;
+ RECT 242.990000 3379.420000 243.990000 3433.780000 ;
+ RECT 242.990000 3371.080000 243.990000 3433.780000 ;
+ RECT 436.430000 3379.420000 437.430000 3433.780000 ;
+ RECT 443.090000 3379.420000 444.090000 3433.780000 ;
+ RECT 443.090000 3371.080000 444.090000 3433.780000 ;
+ RECT 643.190000 3371.080000 644.190000 3433.780000 ;
+ RECT 643.190000 3379.420000 644.190000 3433.780000 ;
+ RECT 636.530000 3379.420000 637.530000 3433.780000 ;
+ RECT 836.930000 3376.060000 837.930000 3433.780000 ;
+ RECT 843.290000 3371.080000 844.290000 3433.780000 ;
+ RECT 843.290000 3379.420000 844.290000 3433.780000 ;
+ RECT 836.630000 3379.420000 837.630000 3433.780000 ;
+ RECT 1037.030000 3353.010000 1038.030000 3433.780000 ;
+ RECT 1037.030000 3376.060000 1038.030000 3433.780000 ;
+ RECT 1043.390000 3371.080000 1044.390000 3433.780000 ;
+ RECT 1043.390000 3379.420000 1044.390000 3433.780000 ;
+ RECT 1036.730000 3379.420000 1037.730000 3433.780000 ;
+ RECT 1237.130000 3353.010000 1238.130000 3433.780000 ;
+ RECT 1237.130000 3376.060000 1238.130000 3433.780000 ;
+ RECT 1236.830000 3379.420000 1237.830000 3433.780000 ;
+ RECT 1243.490000 3379.420000 1244.490000 3433.780000 ;
+ RECT 1646.530000 2143.810000 1647.530000 2144.210000 ;
+ RECT 1444.360000 2143.560000 1445.360000 2144.210000 ;
+ RECT 1646.530000 1743.040000 1647.530000 1743.650000 ;
+ RECT 1444.360000 1743.040000 1445.360000 1743.650000 ;
+ RECT 1444.360000 2544.080000 1445.360000 2544.730000 ;
+ RECT 1646.530000 2544.080000 1647.530000 2544.730000 ;
+ RECT 1444.360000 3353.010000 1445.360000 3433.780000 ;
+ RECT 1441.370000 3376.060000 1442.370000 3433.780000 ;
+ RECT 1444.360000 3376.060000 1445.360000 3433.780000 ;
+ RECT 1436.930000 3379.420000 1437.930000 3433.780000 ;
+ RECT 1448.590000 3379.420000 1449.590000 3433.780000 ;
+ RECT 1436.930000 3371.080000 1437.930000 3433.780000 ;
+ RECT 1448.590000 3350.160000 1449.590000 3350.660000 ;
+ RECT 1642.030000 3371.080000 1643.030000 3433.780000 ;
+ RECT 1642.030000 3379.420000 1643.030000 3433.780000 ;
+ RECT 1653.690000 3379.420000 1654.690000 3433.780000 ;
+ RECT 1642.030000 3350.160000 1643.030000 3350.660000 ;
+ RECT 1847.320000 3353.010000 1848.320000 3433.780000 ;
+ RECT 1847.320000 3376.060000 1848.320000 3433.780000 ;
+ RECT 1847.130000 3371.080000 1848.130000 3433.780000 ;
+ RECT 1847.130000 3379.420000 1848.130000 3433.780000 ;
+ RECT 1853.790000 3379.420000 1854.790000 3433.780000 ;
+ RECT 2047.420000 3353.010000 2048.420000 3433.780000 ;
+ RECT 2047.420000 3376.060000 2048.420000 3433.780000 ;
+ RECT 2047.230000 3371.080000 2048.230000 3433.780000 ;
+ RECT 2047.230000 3379.420000 2048.230000 3433.780000 ;
+ RECT 2053.890000 3379.420000 2054.890000 3433.780000 ;
+ RECT 2157.170000 3379.420000 2158.170000 3433.780000 ;
+ RECT 2157.170000 3371.080000 2158.170000 3433.780000 ;
+ RECT 2193.830000 3399.780000 2194.630000 3433.780000 ;
+ RECT 2717.290000 2975.850000 2718.090000 2980.340000 ;
+ RECT 2694.340000 3384.450000 2696.080000 3433.780000 ;
+ RECT 2717.290000 3393.040000 2718.090000 3433.780000 ;
+ RECT 2717.290000 3399.780000 2718.090000 3433.780000 ;
+ RECT 436.730000 118.090000 437.730000 119.090000 ;
+ RECT 436.430000 109.440000 437.730000 110.440000 ;
+ RECT 153.170000 548.180000 153.670000 548.660000 ;
+ RECT 636.530000 109.440000 637.830000 110.440000 ;
+ RECT 636.830000 141.140000 637.830000 142.140000 ;
+ RECT 836.630000 109.440000 837.930000 110.440000 ;
+ RECT 836.930000 141.140000 837.930000 142.140000 ;
+ RECT 1037.030000 141.140000 1038.030000 142.140000 ;
+ RECT 1036.730000 109.440000 1038.030000 110.440000 ;
+ RECT 1236.830000 109.440000 1238.130000 110.440000 ;
+ RECT 1237.130000 141.140000 1238.130000 142.140000 ;
+ RECT 153.170000 1141.140000 153.670000 1141.620000 ;
+ RECT 1448.590000 120.100000 1449.590000 120.580000 ;
+ RECT 1646.530000 141.140000 1647.530000 142.140000 ;
+ RECT 1853.530000 141.140000 1854.530000 142.140000 ;
+ RECT 1853.530000 109.440000 1854.790000 110.440000 ;
+ RECT 1646.530000 1342.020000 1647.530000 1343.670000 ;
+ RECT 1444.360000 1342.020000 1445.360000 1343.670000 ;
+ RECT 153.170000 1951.700000 153.670000 1952.180000 ;
+ RECT 153.170000 2544.660000 153.670000 2545.140000 ;
+ RECT 162.950000 3152.150000 163.950000 3153.150000 ;
+ RECT 242.990000 3370.840000 243.990000 3371.320000 ;
+ RECT 443.090000 3370.840000 444.090000 3371.320000 ;
+ RECT 643.190000 3370.840000 644.190000 3371.320000 ;
+ RECT 843.290000 3370.840000 844.290000 3371.320000 ;
+ RECT 836.930000 3375.560000 837.930000 3376.560000 ;
+ RECT 836.630000 3398.740000 837.930000 3399.220000 ;
+ RECT 836.630000 3393.300000 837.930000 3393.780000 ;
+ RECT 836.630000 3404.180000 837.930000 3404.660000 ;
+ RECT 836.630000 3409.620000 837.930000 3410.100000 ;
+ RECT 836.630000 3425.940000 837.930000 3426.420000 ;
+ RECT 836.630000 3420.500000 837.930000 3420.980000 ;
+ RECT 836.630000 3415.060000 837.930000 3415.540000 ;
+ RECT 836.630000 3430.780000 837.930000 3433.780000 ;
+ RECT 1043.390000 3370.840000 1044.390000 3371.320000 ;
+ RECT 1037.030000 3352.510000 1038.030000 3353.510000 ;
+ RECT 1036.730000 3398.740000 1038.030000 3399.220000 ;
+ RECT 1036.730000 3393.300000 1038.030000 3393.780000 ;
+ RECT 1036.730000 3409.620000 1038.030000 3410.100000 ;
+ RECT 1036.730000 3404.180000 1038.030000 3404.660000 ;
+ RECT 1036.730000 3425.940000 1038.030000 3426.420000 ;
+ RECT 1036.730000 3415.060000 1038.030000 3415.540000 ;
+ RECT 1036.730000 3420.500000 1038.030000 3420.980000 ;
+ RECT 1036.730000 3430.780000 1038.030000 3433.780000 ;
+ RECT 1237.130000 3352.510000 1238.130000 3353.510000 ;
+ RECT 1236.830000 3398.740000 1238.130000 3399.220000 ;
+ RECT 1236.830000 3393.300000 1238.130000 3393.780000 ;
+ RECT 1236.830000 3404.180000 1238.130000 3404.660000 ;
+ RECT 1236.830000 3409.620000 1238.130000 3410.100000 ;
+ RECT 1236.830000 3425.940000 1238.130000 3426.420000 ;
+ RECT 1236.830000 3420.500000 1238.130000 3420.980000 ;
+ RECT 1236.830000 3415.060000 1238.130000 3415.540000 ;
+ RECT 1236.830000 3430.780000 1238.130000 3433.780000 ;
+ RECT 1646.530000 2143.310000 1647.530000 2144.710000 ;
+ RECT 1646.530000 1742.540000 1647.530000 1744.150000 ;
+ RECT 1444.360000 2143.060000 1445.360000 2144.710000 ;
+ RECT 1444.360000 1742.540000 1445.360000 1744.150000 ;
+ RECT 1646.530000 2543.580000 1647.530000 2545.230000 ;
+ RECT 1444.360000 2543.580000 1445.360000 2545.230000 ;
+ RECT 1444.360000 3352.510000 1445.360000 3353.510000 ;
+ RECT 1441.370000 3375.560000 1442.370000 3376.560000 ;
+ RECT 1436.930000 3370.840000 1437.930000 3371.320000 ;
+ RECT 1642.030000 3370.840000 1643.030000 3371.320000 ;
+ RECT 1847.130000 3370.840000 1848.130000 3371.320000 ;
+ RECT 1847.320000 3352.510000 1848.320000 3353.510000 ;
+ RECT 1847.130000 3398.740000 1848.320000 3399.220000 ;
+ RECT 1847.130000 3393.300000 1848.320000 3393.780000 ;
+ RECT 1847.130000 3404.180000 1848.320000 3404.660000 ;
+ RECT 1847.130000 3409.620000 1848.320000 3410.100000 ;
+ RECT 1847.130000 3425.940000 1848.320000 3426.420000 ;
+ RECT 1847.130000 3420.500000 1848.320000 3420.980000 ;
+ RECT 1847.130000 3415.060000 1848.320000 3415.540000 ;
+ RECT 1847.130000 3430.780000 1848.320000 3433.780000 ;
+ RECT 2047.420000 3352.510000 2048.420000 3353.510000 ;
+ RECT 2047.230000 3370.840000 2048.230000 3371.320000 ;
+ RECT 2047.230000 3398.740000 2048.420000 3399.220000 ;
+ RECT 2047.230000 3393.300000 2048.420000 3393.780000 ;
+ RECT 2047.230000 3404.180000 2048.420000 3404.660000 ;
+ RECT 2047.230000 3409.620000 2048.420000 3410.100000 ;
+ RECT 2047.230000 3425.940000 2048.420000 3426.420000 ;
+ RECT 2047.230000 3420.500000 2048.420000 3420.980000 ;
+ RECT 2047.230000 3415.060000 2048.420000 3415.540000 ;
+ RECT 2047.230000 3430.780000 2048.420000 3433.780000 ;
+ RECT 2157.170000 3370.840000 2158.170000 3371.320000 ;
+ END
+# end of P/G power stripe data as pin
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2694.340000 55.660000 2696.080000 443.640000 ;
+ LAYER met4 ;
+ RECT 2225.820000 55.660000 2227.560000 443.640000 ;
+ LAYER met3 ;
+ RECT 2225.820000 55.660000 2696.080000 57.400000 ;
+ LAYER met3 ;
+ RECT 2225.820000 441.900000 2696.080000 443.640000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 38.260000 2194.630000 458.500000 ;
+ RECT 2717.290000 38.260000 2718.090000 458.500000 ;
+ LAYER met3 ;
+ RECT 2717.290000 451.120000 2718.090000 451.600000 ;
+ RECT 2717.290000 434.800000 2718.090000 435.280000 ;
+ RECT 2717.290000 440.240000 2718.090000 440.720000 ;
+ RECT 2717.290000 445.680000 2718.090000 446.160000 ;
+ RECT 2717.290000 418.480000 2718.090000 418.960000 ;
+ RECT 2717.290000 423.920000 2718.090000 424.400000 ;
+ RECT 2717.290000 429.360000 2718.090000 429.840000 ;
+ RECT 2717.290000 402.160000 2718.090000 402.640000 ;
+ RECT 2717.290000 407.600000 2718.090000 408.080000 ;
+ RECT 2717.290000 413.040000 2718.090000 413.520000 ;
+ RECT 2717.290000 385.840000 2718.090000 386.320000 ;
+ RECT 2717.290000 391.280000 2718.090000 391.760000 ;
+ RECT 2717.290000 396.720000 2718.090000 397.200000 ;
+ RECT 2717.290000 374.960000 2718.090000 375.440000 ;
+ RECT 2717.290000 369.520000 2718.090000 370.000000 ;
+ RECT 2717.290000 347.760000 2718.090000 348.240000 ;
+ RECT 2717.290000 353.200000 2718.090000 353.680000 ;
+ RECT 2717.290000 358.640000 2718.090000 359.120000 ;
+ RECT 2717.290000 364.080000 2718.090000 364.560000 ;
+ RECT 2717.290000 331.440000 2718.090000 331.920000 ;
+ RECT 2717.290000 336.880000 2718.090000 337.360000 ;
+ RECT 2717.290000 342.320000 2718.090000 342.800000 ;
+ RECT 2717.290000 315.120000 2718.090000 315.600000 ;
+ RECT 2717.290000 320.560000 2718.090000 321.040000 ;
+ RECT 2717.290000 326.000000 2718.090000 326.480000 ;
+ RECT 2717.290000 298.800000 2718.090000 299.280000 ;
+ RECT 2717.290000 304.240000 2718.090000 304.720000 ;
+ RECT 2717.290000 309.680000 2718.090000 310.160000 ;
+ RECT 2717.290000 282.480000 2718.090000 282.960000 ;
+ RECT 2717.290000 287.920000 2718.090000 288.400000 ;
+ RECT 2717.290000 293.360000 2718.090000 293.840000 ;
+ RECT 2717.290000 266.160000 2718.090000 266.640000 ;
+ RECT 2717.290000 271.600000 2718.090000 272.080000 ;
+ RECT 2717.290000 277.040000 2718.090000 277.520000 ;
+ RECT 2717.290000 249.840000 2718.090000 250.320000 ;
+ RECT 2717.290000 255.280000 2718.090000 255.760000 ;
+ RECT 2717.290000 260.720000 2718.090000 261.200000 ;
+ RECT 2717.290000 380.400000 2718.090000 380.880000 ;
+ RECT 2193.830000 451.120000 2194.630000 451.600000 ;
+ RECT 2193.830000 434.800000 2194.630000 435.280000 ;
+ RECT 2193.830000 440.240000 2194.630000 440.720000 ;
+ RECT 2193.830000 445.680000 2194.630000 446.160000 ;
+ RECT 2193.830000 418.480000 2194.630000 418.960000 ;
+ RECT 2193.830000 423.920000 2194.630000 424.400000 ;
+ RECT 2193.830000 429.360000 2194.630000 429.840000 ;
+ RECT 2193.830000 402.160000 2194.630000 402.640000 ;
+ RECT 2193.830000 407.600000 2194.630000 408.080000 ;
+ RECT 2193.830000 413.040000 2194.630000 413.520000 ;
+ RECT 2193.830000 385.840000 2194.630000 386.320000 ;
+ RECT 2193.830000 391.280000 2194.630000 391.760000 ;
+ RECT 2193.830000 396.720000 2194.630000 397.200000 ;
+ RECT 2193.830000 374.960000 2194.630000 375.440000 ;
+ RECT 2193.830000 369.520000 2194.630000 370.000000 ;
+ RECT 2193.830000 347.760000 2194.630000 348.240000 ;
+ RECT 2193.830000 353.200000 2194.630000 353.680000 ;
+ RECT 2193.830000 358.640000 2194.630000 359.120000 ;
+ RECT 2193.830000 364.080000 2194.630000 364.560000 ;
+ RECT 2193.830000 331.440000 2194.630000 331.920000 ;
+ RECT 2193.830000 336.880000 2194.630000 337.360000 ;
+ RECT 2193.830000 342.320000 2194.630000 342.800000 ;
+ RECT 2193.830000 315.120000 2194.630000 315.600000 ;
+ RECT 2193.830000 320.560000 2194.630000 321.040000 ;
+ RECT 2193.830000 326.000000 2194.630000 326.480000 ;
+ RECT 2193.830000 298.800000 2194.630000 299.280000 ;
+ RECT 2193.830000 304.240000 2194.630000 304.720000 ;
+ RECT 2193.830000 309.680000 2194.630000 310.160000 ;
+ RECT 2193.830000 282.480000 2194.630000 282.960000 ;
+ RECT 2193.830000 287.920000 2194.630000 288.400000 ;
+ RECT 2193.830000 293.360000 2194.630000 293.840000 ;
+ RECT 2193.830000 266.160000 2194.630000 266.640000 ;
+ RECT 2193.830000 271.600000 2194.630000 272.080000 ;
+ RECT 2193.830000 277.040000 2194.630000 277.520000 ;
+ RECT 2193.830000 249.840000 2194.630000 250.320000 ;
+ RECT 2193.830000 255.280000 2194.630000 255.760000 ;
+ RECT 2193.830000 260.720000 2194.630000 261.200000 ;
+ RECT 2193.830000 380.400000 2194.630000 380.880000 ;
+ RECT 2717.290000 233.520000 2718.090000 234.000000 ;
+ RECT 2717.290000 238.960000 2718.090000 239.440000 ;
+ RECT 2717.290000 244.400000 2718.090000 244.880000 ;
+ RECT 2717.290000 217.200000 2718.090000 217.680000 ;
+ RECT 2717.290000 222.640000 2718.090000 223.120000 ;
+ RECT 2717.290000 228.080000 2718.090000 228.560000 ;
+ RECT 2717.290000 200.880000 2718.090000 201.360000 ;
+ RECT 2717.290000 206.320000 2718.090000 206.800000 ;
+ RECT 2717.290000 211.760000 2718.090000 212.240000 ;
+ RECT 2717.290000 184.560000 2718.090000 185.040000 ;
+ RECT 2717.290000 190.000000 2718.090000 190.480000 ;
+ RECT 2717.290000 195.440000 2718.090000 195.920000 ;
+ RECT 2717.290000 179.120000 2718.090000 179.600000 ;
+ RECT 2717.290000 173.680000 2718.090000 174.160000 ;
+ RECT 2717.290000 168.240000 2718.090000 168.720000 ;
+ RECT 2717.290000 151.920000 2718.090000 152.400000 ;
+ RECT 2717.290000 157.360000 2718.090000 157.840000 ;
+ RECT 2717.290000 162.800000 2718.090000 163.280000 ;
+ RECT 2717.290000 135.600000 2718.090000 136.080000 ;
+ RECT 2717.290000 141.040000 2718.090000 141.520000 ;
+ RECT 2717.290000 146.480000 2718.090000 146.960000 ;
+ RECT 2717.290000 119.280000 2718.090000 119.760000 ;
+ RECT 2717.290000 124.720000 2718.090000 125.200000 ;
+ RECT 2717.290000 130.160000 2718.090000 130.640000 ;
+ RECT 2717.290000 102.960000 2718.090000 103.440000 ;
+ RECT 2717.290000 108.400000 2718.090000 108.880000 ;
+ RECT 2717.290000 113.840000 2718.090000 114.320000 ;
+ RECT 2717.290000 86.640000 2718.090000 87.120000 ;
+ RECT 2717.290000 92.080000 2718.090000 92.560000 ;
+ RECT 2717.290000 97.520000 2718.090000 98.000000 ;
+ RECT 2717.290000 70.320000 2718.090000 70.800000 ;
+ RECT 2717.290000 75.760000 2718.090000 76.240000 ;
+ RECT 2717.290000 81.200000 2718.090000 81.680000 ;
+ RECT 2717.290000 54.000000 2718.090000 54.480000 ;
+ RECT 2717.290000 59.440000 2718.090000 59.920000 ;
+ RECT 2717.290000 64.880000 2718.090000 65.360000 ;
+ RECT 2717.290000 48.560000 2718.090000 49.040000 ;
+ RECT 2717.290000 43.120000 2718.090000 43.600000 ;
+ RECT 2193.830000 244.400000 2194.630000 244.880000 ;
+ RECT 2193.830000 233.520000 2194.630000 234.000000 ;
+ RECT 2193.830000 238.960000 2194.630000 239.440000 ;
+ RECT 2193.830000 217.200000 2194.630000 217.680000 ;
+ RECT 2193.830000 222.640000 2194.630000 223.120000 ;
+ RECT 2193.830000 228.080000 2194.630000 228.560000 ;
+ RECT 2193.830000 200.880000 2194.630000 201.360000 ;
+ RECT 2193.830000 206.320000 2194.630000 206.800000 ;
+ RECT 2193.830000 211.760000 2194.630000 212.240000 ;
+ RECT 2193.830000 184.560000 2194.630000 185.040000 ;
+ RECT 2193.830000 190.000000 2194.630000 190.480000 ;
+ RECT 2193.830000 195.440000 2194.630000 195.920000 ;
+ RECT 2193.830000 179.120000 2194.630000 179.600000 ;
+ RECT 2193.830000 173.680000 2194.630000 174.160000 ;
+ RECT 2193.830000 168.240000 2194.630000 168.720000 ;
+ RECT 2193.830000 151.920000 2194.630000 152.400000 ;
+ RECT 2193.830000 157.360000 2194.630000 157.840000 ;
+ RECT 2193.830000 162.800000 2194.630000 163.280000 ;
+ RECT 2193.830000 141.040000 2194.630000 141.520000 ;
+ RECT 2193.830000 146.480000 2194.630000 146.960000 ;
+ RECT 2193.830000 135.600000 2194.630000 136.080000 ;
+ RECT 2193.830000 119.280000 2194.630000 119.760000 ;
+ RECT 2193.830000 124.720000 2194.630000 125.200000 ;
+ RECT 2193.830000 130.160000 2194.630000 130.640000 ;
+ RECT 2193.830000 102.960000 2194.630000 103.440000 ;
+ RECT 2193.830000 108.400000 2194.630000 108.880000 ;
+ RECT 2193.830000 113.840000 2194.630000 114.320000 ;
+ RECT 2193.830000 92.080000 2194.630000 92.560000 ;
+ RECT 2193.830000 97.520000 2194.630000 98.000000 ;
+ RECT 2193.830000 86.640000 2194.630000 87.120000 ;
+ RECT 2193.830000 70.320000 2194.630000 70.800000 ;
+ RECT 2193.830000 75.760000 2194.630000 76.240000 ;
+ RECT 2193.830000 81.200000 2194.630000 81.680000 ;
+ RECT 2193.830000 64.880000 2194.630000 65.360000 ;
+ RECT 2193.830000 54.000000 2194.630000 54.480000 ;
+ RECT 2193.830000 59.440000 2194.630000 59.920000 ;
+ RECT 2193.830000 43.120000 2194.630000 43.600000 ;
+ RECT 2193.830000 48.560000 2194.630000 49.040000 ;
+ RECT 2193.830000 453.830000 2720.920000 454.630000 ;
+ RECT 2193.830000 41.110000 2720.920000 41.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 38.260000 2194.630000 39.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 457.700000 2194.630000 458.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 38.260000 2718.090000 39.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 457.700000 2718.090000 458.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 41.110000 2720.920000 41.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 453.830000 2720.920000 454.630000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2694.340000 475.900000 2696.080000 863.880000 ;
+ LAYER met4 ;
+ RECT 2225.820000 475.900000 2227.560000 863.880000 ;
+ LAYER met3 ;
+ RECT 2225.820000 475.900000 2696.080000 477.640000 ;
+ LAYER met3 ;
+ RECT 2225.820000 862.140000 2696.080000 863.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 458.500000 2194.630000 878.740000 ;
+ RECT 2717.290000 458.500000 2718.090000 878.740000 ;
+ LAYER met3 ;
+ RECT 2717.290000 871.360000 2718.090000 871.840000 ;
+ RECT 2717.290000 855.040000 2718.090000 855.520000 ;
+ RECT 2717.290000 860.480000 2718.090000 860.960000 ;
+ RECT 2717.290000 865.920000 2718.090000 866.400000 ;
+ RECT 2717.290000 838.720000 2718.090000 839.200000 ;
+ RECT 2717.290000 844.160000 2718.090000 844.640000 ;
+ RECT 2717.290000 849.600000 2718.090000 850.080000 ;
+ RECT 2717.290000 822.400000 2718.090000 822.880000 ;
+ RECT 2717.290000 827.840000 2718.090000 828.320000 ;
+ RECT 2717.290000 833.280000 2718.090000 833.760000 ;
+ RECT 2717.290000 806.080000 2718.090000 806.560000 ;
+ RECT 2717.290000 811.520000 2718.090000 812.000000 ;
+ RECT 2717.290000 816.960000 2718.090000 817.440000 ;
+ RECT 2717.290000 795.200000 2718.090000 795.680000 ;
+ RECT 2717.290000 789.760000 2718.090000 790.240000 ;
+ RECT 2717.290000 768.000000 2718.090000 768.480000 ;
+ RECT 2717.290000 773.440000 2718.090000 773.920000 ;
+ RECT 2717.290000 778.880000 2718.090000 779.360000 ;
+ RECT 2717.290000 784.320000 2718.090000 784.800000 ;
+ RECT 2717.290000 751.680000 2718.090000 752.160000 ;
+ RECT 2717.290000 757.120000 2718.090000 757.600000 ;
+ RECT 2717.290000 762.560000 2718.090000 763.040000 ;
+ RECT 2717.290000 735.360000 2718.090000 735.840000 ;
+ RECT 2717.290000 740.800000 2718.090000 741.280000 ;
+ RECT 2717.290000 746.240000 2718.090000 746.720000 ;
+ RECT 2717.290000 719.040000 2718.090000 719.520000 ;
+ RECT 2717.290000 724.480000 2718.090000 724.960000 ;
+ RECT 2717.290000 729.920000 2718.090000 730.400000 ;
+ RECT 2717.290000 702.720000 2718.090000 703.200000 ;
+ RECT 2717.290000 708.160000 2718.090000 708.640000 ;
+ RECT 2717.290000 713.600000 2718.090000 714.080000 ;
+ RECT 2717.290000 686.400000 2718.090000 686.880000 ;
+ RECT 2717.290000 691.840000 2718.090000 692.320000 ;
+ RECT 2717.290000 697.280000 2718.090000 697.760000 ;
+ RECT 2717.290000 670.080000 2718.090000 670.560000 ;
+ RECT 2717.290000 675.520000 2718.090000 676.000000 ;
+ RECT 2717.290000 680.960000 2718.090000 681.440000 ;
+ RECT 2717.290000 800.640000 2718.090000 801.120000 ;
+ RECT 2193.830000 871.360000 2194.630000 871.840000 ;
+ RECT 2193.830000 855.040000 2194.630000 855.520000 ;
+ RECT 2193.830000 860.480000 2194.630000 860.960000 ;
+ RECT 2193.830000 865.920000 2194.630000 866.400000 ;
+ RECT 2193.830000 838.720000 2194.630000 839.200000 ;
+ RECT 2193.830000 844.160000 2194.630000 844.640000 ;
+ RECT 2193.830000 849.600000 2194.630000 850.080000 ;
+ RECT 2193.830000 822.400000 2194.630000 822.880000 ;
+ RECT 2193.830000 827.840000 2194.630000 828.320000 ;
+ RECT 2193.830000 833.280000 2194.630000 833.760000 ;
+ RECT 2193.830000 806.080000 2194.630000 806.560000 ;
+ RECT 2193.830000 811.520000 2194.630000 812.000000 ;
+ RECT 2193.830000 816.960000 2194.630000 817.440000 ;
+ RECT 2193.830000 795.200000 2194.630000 795.680000 ;
+ RECT 2193.830000 789.760000 2194.630000 790.240000 ;
+ RECT 2193.830000 768.000000 2194.630000 768.480000 ;
+ RECT 2193.830000 773.440000 2194.630000 773.920000 ;
+ RECT 2193.830000 778.880000 2194.630000 779.360000 ;
+ RECT 2193.830000 784.320000 2194.630000 784.800000 ;
+ RECT 2193.830000 751.680000 2194.630000 752.160000 ;
+ RECT 2193.830000 757.120000 2194.630000 757.600000 ;
+ RECT 2193.830000 762.560000 2194.630000 763.040000 ;
+ RECT 2193.830000 735.360000 2194.630000 735.840000 ;
+ RECT 2193.830000 740.800000 2194.630000 741.280000 ;
+ RECT 2193.830000 746.240000 2194.630000 746.720000 ;
+ RECT 2193.830000 719.040000 2194.630000 719.520000 ;
+ RECT 2193.830000 724.480000 2194.630000 724.960000 ;
+ RECT 2193.830000 729.920000 2194.630000 730.400000 ;
+ RECT 2193.830000 702.720000 2194.630000 703.200000 ;
+ RECT 2193.830000 708.160000 2194.630000 708.640000 ;
+ RECT 2193.830000 713.600000 2194.630000 714.080000 ;
+ RECT 2193.830000 686.400000 2194.630000 686.880000 ;
+ RECT 2193.830000 691.840000 2194.630000 692.320000 ;
+ RECT 2193.830000 697.280000 2194.630000 697.760000 ;
+ RECT 2193.830000 670.080000 2194.630000 670.560000 ;
+ RECT 2193.830000 675.520000 2194.630000 676.000000 ;
+ RECT 2193.830000 680.960000 2194.630000 681.440000 ;
+ RECT 2193.830000 800.640000 2194.630000 801.120000 ;
+ RECT 2717.290000 653.760000 2718.090000 654.240000 ;
+ RECT 2717.290000 659.200000 2718.090000 659.680000 ;
+ RECT 2717.290000 664.640000 2718.090000 665.120000 ;
+ RECT 2717.290000 637.440000 2718.090000 637.920000 ;
+ RECT 2717.290000 642.880000 2718.090000 643.360000 ;
+ RECT 2717.290000 648.320000 2718.090000 648.800000 ;
+ RECT 2717.290000 621.120000 2718.090000 621.600000 ;
+ RECT 2717.290000 626.560000 2718.090000 627.040000 ;
+ RECT 2717.290000 632.000000 2718.090000 632.480000 ;
+ RECT 2717.290000 604.800000 2718.090000 605.280000 ;
+ RECT 2717.290000 610.240000 2718.090000 610.720000 ;
+ RECT 2717.290000 615.680000 2718.090000 616.160000 ;
+ RECT 2717.290000 599.360000 2718.090000 599.840000 ;
+ RECT 2717.290000 593.920000 2718.090000 594.400000 ;
+ RECT 2717.290000 588.480000 2718.090000 588.960000 ;
+ RECT 2717.290000 572.160000 2718.090000 572.640000 ;
+ RECT 2717.290000 577.600000 2718.090000 578.080000 ;
+ RECT 2717.290000 583.040000 2718.090000 583.520000 ;
+ RECT 2717.290000 555.840000 2718.090000 556.320000 ;
+ RECT 2717.290000 561.280000 2718.090000 561.760000 ;
+ RECT 2717.290000 566.720000 2718.090000 567.200000 ;
+ RECT 2717.290000 539.520000 2718.090000 540.000000 ;
+ RECT 2717.290000 544.960000 2718.090000 545.440000 ;
+ RECT 2717.290000 550.400000 2718.090000 550.880000 ;
+ RECT 2717.290000 523.200000 2718.090000 523.680000 ;
+ RECT 2717.290000 528.640000 2718.090000 529.120000 ;
+ RECT 2717.290000 534.080000 2718.090000 534.560000 ;
+ RECT 2717.290000 506.880000 2718.090000 507.360000 ;
+ RECT 2717.290000 512.320000 2718.090000 512.800000 ;
+ RECT 2717.290000 517.760000 2718.090000 518.240000 ;
+ RECT 2717.290000 490.560000 2718.090000 491.040000 ;
+ RECT 2717.290000 496.000000 2718.090000 496.480000 ;
+ RECT 2717.290000 501.440000 2718.090000 501.920000 ;
+ RECT 2717.290000 474.240000 2718.090000 474.720000 ;
+ RECT 2717.290000 479.680000 2718.090000 480.160000 ;
+ RECT 2717.290000 485.120000 2718.090000 485.600000 ;
+ RECT 2717.290000 468.800000 2718.090000 469.280000 ;
+ RECT 2717.290000 463.360000 2718.090000 463.840000 ;
+ RECT 2193.830000 664.640000 2194.630000 665.120000 ;
+ RECT 2193.830000 653.760000 2194.630000 654.240000 ;
+ RECT 2193.830000 659.200000 2194.630000 659.680000 ;
+ RECT 2193.830000 637.440000 2194.630000 637.920000 ;
+ RECT 2193.830000 642.880000 2194.630000 643.360000 ;
+ RECT 2193.830000 648.320000 2194.630000 648.800000 ;
+ RECT 2193.830000 621.120000 2194.630000 621.600000 ;
+ RECT 2193.830000 626.560000 2194.630000 627.040000 ;
+ RECT 2193.830000 632.000000 2194.630000 632.480000 ;
+ RECT 2193.830000 604.800000 2194.630000 605.280000 ;
+ RECT 2193.830000 610.240000 2194.630000 610.720000 ;
+ RECT 2193.830000 615.680000 2194.630000 616.160000 ;
+ RECT 2193.830000 599.360000 2194.630000 599.840000 ;
+ RECT 2193.830000 593.920000 2194.630000 594.400000 ;
+ RECT 2193.830000 588.480000 2194.630000 588.960000 ;
+ RECT 2193.830000 572.160000 2194.630000 572.640000 ;
+ RECT 2193.830000 577.600000 2194.630000 578.080000 ;
+ RECT 2193.830000 583.040000 2194.630000 583.520000 ;
+ RECT 2193.830000 561.280000 2194.630000 561.760000 ;
+ RECT 2193.830000 566.720000 2194.630000 567.200000 ;
+ RECT 2193.830000 555.840000 2194.630000 556.320000 ;
+ RECT 2193.830000 539.520000 2194.630000 540.000000 ;
+ RECT 2193.830000 544.960000 2194.630000 545.440000 ;
+ RECT 2193.830000 550.400000 2194.630000 550.880000 ;
+ RECT 2193.830000 523.200000 2194.630000 523.680000 ;
+ RECT 2193.830000 528.640000 2194.630000 529.120000 ;
+ RECT 2193.830000 534.080000 2194.630000 534.560000 ;
+ RECT 2193.830000 512.320000 2194.630000 512.800000 ;
+ RECT 2193.830000 517.760000 2194.630000 518.240000 ;
+ RECT 2193.830000 506.880000 2194.630000 507.360000 ;
+ RECT 2193.830000 490.560000 2194.630000 491.040000 ;
+ RECT 2193.830000 496.000000 2194.630000 496.480000 ;
+ RECT 2193.830000 501.440000 2194.630000 501.920000 ;
+ RECT 2193.830000 485.120000 2194.630000 485.600000 ;
+ RECT 2193.830000 474.240000 2194.630000 474.720000 ;
+ RECT 2193.830000 479.680000 2194.630000 480.160000 ;
+ RECT 2193.830000 463.360000 2194.630000 463.840000 ;
+ RECT 2193.830000 468.800000 2194.630000 469.280000 ;
+ RECT 2193.830000 874.070000 2720.920000 874.870000 ;
+ RECT 2193.830000 461.350000 2720.920000 462.150000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 458.500000 2194.630000 459.300000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 877.940000 2194.630000 878.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 458.500000 2718.090000 459.300000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 877.940000 2718.090000 878.740000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 461.350000 2720.920000 462.150000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 874.070000 2720.920000 874.870000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2694.340000 896.140000 2696.080000 1284.120000 ;
+ LAYER met4 ;
+ RECT 2225.820000 896.140000 2227.560000 1284.120000 ;
+ LAYER met3 ;
+ RECT 2225.820000 896.140000 2696.080000 897.880000 ;
+ LAYER met3 ;
+ RECT 2225.820000 1282.380000 2696.080000 1284.120000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 878.740000 2194.630000 1298.980000 ;
+ RECT 2717.290000 878.740000 2718.090000 1298.980000 ;
+ LAYER met3 ;
+ RECT 2717.290000 1291.600000 2718.090000 1292.080000 ;
+ RECT 2717.290000 1275.280000 2718.090000 1275.760000 ;
+ RECT 2717.290000 1280.720000 2718.090000 1281.200000 ;
+ RECT 2717.290000 1286.160000 2718.090000 1286.640000 ;
+ RECT 2717.290000 1258.960000 2718.090000 1259.440000 ;
+ RECT 2717.290000 1264.400000 2718.090000 1264.880000 ;
+ RECT 2717.290000 1269.840000 2718.090000 1270.320000 ;
+ RECT 2717.290000 1242.640000 2718.090000 1243.120000 ;
+ RECT 2717.290000 1248.080000 2718.090000 1248.560000 ;
+ RECT 2717.290000 1253.520000 2718.090000 1254.000000 ;
+ RECT 2717.290000 1226.320000 2718.090000 1226.800000 ;
+ RECT 2717.290000 1231.760000 2718.090000 1232.240000 ;
+ RECT 2717.290000 1237.200000 2718.090000 1237.680000 ;
+ RECT 2717.290000 1215.440000 2718.090000 1215.920000 ;
+ RECT 2717.290000 1210.000000 2718.090000 1210.480000 ;
+ RECT 2717.290000 1188.240000 2718.090000 1188.720000 ;
+ RECT 2717.290000 1193.680000 2718.090000 1194.160000 ;
+ RECT 2717.290000 1199.120000 2718.090000 1199.600000 ;
+ RECT 2717.290000 1204.560000 2718.090000 1205.040000 ;
+ RECT 2717.290000 1171.920000 2718.090000 1172.400000 ;
+ RECT 2717.290000 1177.360000 2718.090000 1177.840000 ;
+ RECT 2717.290000 1182.800000 2718.090000 1183.280000 ;
+ RECT 2717.290000 1155.600000 2718.090000 1156.080000 ;
+ RECT 2717.290000 1161.040000 2718.090000 1161.520000 ;
+ RECT 2717.290000 1166.480000 2718.090000 1166.960000 ;
+ RECT 2717.290000 1139.280000 2718.090000 1139.760000 ;
+ RECT 2717.290000 1144.720000 2718.090000 1145.200000 ;
+ RECT 2717.290000 1150.160000 2718.090000 1150.640000 ;
+ RECT 2717.290000 1122.960000 2718.090000 1123.440000 ;
+ RECT 2717.290000 1128.400000 2718.090000 1128.880000 ;
+ RECT 2717.290000 1133.840000 2718.090000 1134.320000 ;
+ RECT 2717.290000 1106.640000 2718.090000 1107.120000 ;
+ RECT 2717.290000 1112.080000 2718.090000 1112.560000 ;
+ RECT 2717.290000 1117.520000 2718.090000 1118.000000 ;
+ RECT 2717.290000 1090.320000 2718.090000 1090.800000 ;
+ RECT 2717.290000 1095.760000 2718.090000 1096.240000 ;
+ RECT 2717.290000 1101.200000 2718.090000 1101.680000 ;
+ RECT 2717.290000 1220.880000 2718.090000 1221.360000 ;
+ RECT 2193.830000 1291.600000 2194.630000 1292.080000 ;
+ RECT 2193.830000 1275.280000 2194.630000 1275.760000 ;
+ RECT 2193.830000 1280.720000 2194.630000 1281.200000 ;
+ RECT 2193.830000 1286.160000 2194.630000 1286.640000 ;
+ RECT 2193.830000 1258.960000 2194.630000 1259.440000 ;
+ RECT 2193.830000 1264.400000 2194.630000 1264.880000 ;
+ RECT 2193.830000 1269.840000 2194.630000 1270.320000 ;
+ RECT 2193.830000 1242.640000 2194.630000 1243.120000 ;
+ RECT 2193.830000 1248.080000 2194.630000 1248.560000 ;
+ RECT 2193.830000 1253.520000 2194.630000 1254.000000 ;
+ RECT 2193.830000 1226.320000 2194.630000 1226.800000 ;
+ RECT 2193.830000 1231.760000 2194.630000 1232.240000 ;
+ RECT 2193.830000 1237.200000 2194.630000 1237.680000 ;
+ RECT 2193.830000 1215.440000 2194.630000 1215.920000 ;
+ RECT 2193.830000 1210.000000 2194.630000 1210.480000 ;
+ RECT 2193.830000 1188.240000 2194.630000 1188.720000 ;
+ RECT 2193.830000 1193.680000 2194.630000 1194.160000 ;
+ RECT 2193.830000 1199.120000 2194.630000 1199.600000 ;
+ RECT 2193.830000 1204.560000 2194.630000 1205.040000 ;
+ RECT 2193.830000 1171.920000 2194.630000 1172.400000 ;
+ RECT 2193.830000 1177.360000 2194.630000 1177.840000 ;
+ RECT 2193.830000 1182.800000 2194.630000 1183.280000 ;
+ RECT 2193.830000 1155.600000 2194.630000 1156.080000 ;
+ RECT 2193.830000 1161.040000 2194.630000 1161.520000 ;
+ RECT 2193.830000 1166.480000 2194.630000 1166.960000 ;
+ RECT 2193.830000 1139.280000 2194.630000 1139.760000 ;
+ RECT 2193.830000 1144.720000 2194.630000 1145.200000 ;
+ RECT 2193.830000 1150.160000 2194.630000 1150.640000 ;
+ RECT 2193.830000 1122.960000 2194.630000 1123.440000 ;
+ RECT 2193.830000 1128.400000 2194.630000 1128.880000 ;
+ RECT 2193.830000 1133.840000 2194.630000 1134.320000 ;
+ RECT 2193.830000 1106.640000 2194.630000 1107.120000 ;
+ RECT 2193.830000 1112.080000 2194.630000 1112.560000 ;
+ RECT 2193.830000 1117.520000 2194.630000 1118.000000 ;
+ RECT 2193.830000 1090.320000 2194.630000 1090.800000 ;
+ RECT 2193.830000 1095.760000 2194.630000 1096.240000 ;
+ RECT 2193.830000 1101.200000 2194.630000 1101.680000 ;
+ RECT 2193.830000 1220.880000 2194.630000 1221.360000 ;
+ RECT 2717.290000 1074.000000 2718.090000 1074.480000 ;
+ RECT 2717.290000 1079.440000 2718.090000 1079.920000 ;
+ RECT 2717.290000 1084.880000 2718.090000 1085.360000 ;
+ RECT 2717.290000 1057.680000 2718.090000 1058.160000 ;
+ RECT 2717.290000 1063.120000 2718.090000 1063.600000 ;
+ RECT 2717.290000 1068.560000 2718.090000 1069.040000 ;
+ RECT 2717.290000 1041.360000 2718.090000 1041.840000 ;
+ RECT 2717.290000 1046.800000 2718.090000 1047.280000 ;
+ RECT 2717.290000 1052.240000 2718.090000 1052.720000 ;
+ RECT 2717.290000 1025.040000 2718.090000 1025.520000 ;
+ RECT 2717.290000 1030.480000 2718.090000 1030.960000 ;
+ RECT 2717.290000 1035.920000 2718.090000 1036.400000 ;
+ RECT 2717.290000 1019.600000 2718.090000 1020.080000 ;
+ RECT 2717.290000 1014.160000 2718.090000 1014.640000 ;
+ RECT 2717.290000 1008.720000 2718.090000 1009.200000 ;
+ RECT 2717.290000 992.400000 2718.090000 992.880000 ;
+ RECT 2717.290000 997.840000 2718.090000 998.320000 ;
+ RECT 2717.290000 1003.280000 2718.090000 1003.760000 ;
+ RECT 2717.290000 976.080000 2718.090000 976.560000 ;
+ RECT 2717.290000 981.520000 2718.090000 982.000000 ;
+ RECT 2717.290000 986.960000 2718.090000 987.440000 ;
+ RECT 2717.290000 959.760000 2718.090000 960.240000 ;
+ RECT 2717.290000 965.200000 2718.090000 965.680000 ;
+ RECT 2717.290000 970.640000 2718.090000 971.120000 ;
+ RECT 2717.290000 943.440000 2718.090000 943.920000 ;
+ RECT 2717.290000 948.880000 2718.090000 949.360000 ;
+ RECT 2717.290000 954.320000 2718.090000 954.800000 ;
+ RECT 2717.290000 927.120000 2718.090000 927.600000 ;
+ RECT 2717.290000 932.560000 2718.090000 933.040000 ;
+ RECT 2717.290000 938.000000 2718.090000 938.480000 ;
+ RECT 2717.290000 910.800000 2718.090000 911.280000 ;
+ RECT 2717.290000 916.240000 2718.090000 916.720000 ;
+ RECT 2717.290000 921.680000 2718.090000 922.160000 ;
+ RECT 2717.290000 894.480000 2718.090000 894.960000 ;
+ RECT 2717.290000 899.920000 2718.090000 900.400000 ;
+ RECT 2717.290000 905.360000 2718.090000 905.840000 ;
+ RECT 2717.290000 889.040000 2718.090000 889.520000 ;
+ RECT 2717.290000 883.600000 2718.090000 884.080000 ;
+ RECT 2193.830000 1084.880000 2194.630000 1085.360000 ;
+ RECT 2193.830000 1074.000000 2194.630000 1074.480000 ;
+ RECT 2193.830000 1079.440000 2194.630000 1079.920000 ;
+ RECT 2193.830000 1057.680000 2194.630000 1058.160000 ;
+ RECT 2193.830000 1063.120000 2194.630000 1063.600000 ;
+ RECT 2193.830000 1068.560000 2194.630000 1069.040000 ;
+ RECT 2193.830000 1041.360000 2194.630000 1041.840000 ;
+ RECT 2193.830000 1046.800000 2194.630000 1047.280000 ;
+ RECT 2193.830000 1052.240000 2194.630000 1052.720000 ;
+ RECT 2193.830000 1025.040000 2194.630000 1025.520000 ;
+ RECT 2193.830000 1030.480000 2194.630000 1030.960000 ;
+ RECT 2193.830000 1035.920000 2194.630000 1036.400000 ;
+ RECT 2193.830000 1019.600000 2194.630000 1020.080000 ;
+ RECT 2193.830000 1014.160000 2194.630000 1014.640000 ;
+ RECT 2193.830000 1008.720000 2194.630000 1009.200000 ;
+ RECT 2193.830000 992.400000 2194.630000 992.880000 ;
+ RECT 2193.830000 997.840000 2194.630000 998.320000 ;
+ RECT 2193.830000 1003.280000 2194.630000 1003.760000 ;
+ RECT 2193.830000 981.520000 2194.630000 982.000000 ;
+ RECT 2193.830000 986.960000 2194.630000 987.440000 ;
+ RECT 2193.830000 976.080000 2194.630000 976.560000 ;
+ RECT 2193.830000 959.760000 2194.630000 960.240000 ;
+ RECT 2193.830000 965.200000 2194.630000 965.680000 ;
+ RECT 2193.830000 970.640000 2194.630000 971.120000 ;
+ RECT 2193.830000 943.440000 2194.630000 943.920000 ;
+ RECT 2193.830000 948.880000 2194.630000 949.360000 ;
+ RECT 2193.830000 954.320000 2194.630000 954.800000 ;
+ RECT 2193.830000 932.560000 2194.630000 933.040000 ;
+ RECT 2193.830000 938.000000 2194.630000 938.480000 ;
+ RECT 2193.830000 927.120000 2194.630000 927.600000 ;
+ RECT 2193.830000 910.800000 2194.630000 911.280000 ;
+ RECT 2193.830000 916.240000 2194.630000 916.720000 ;
+ RECT 2193.830000 921.680000 2194.630000 922.160000 ;
+ RECT 2193.830000 905.360000 2194.630000 905.840000 ;
+ RECT 2193.830000 894.480000 2194.630000 894.960000 ;
+ RECT 2193.830000 899.920000 2194.630000 900.400000 ;
+ RECT 2193.830000 883.600000 2194.630000 884.080000 ;
+ RECT 2193.830000 889.040000 2194.630000 889.520000 ;
+ RECT 2193.830000 1294.310000 2720.920000 1295.110000 ;
+ RECT 2193.830000 881.590000 2720.920000 882.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 878.740000 2194.630000 879.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 1298.180000 2194.630000 1298.980000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 878.740000 2718.090000 879.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 1298.180000 2718.090000 1298.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 881.590000 2720.920000 882.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 1294.310000 2720.920000 1295.110000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2694.340000 1316.380000 2696.080000 1704.360000 ;
+ LAYER met4 ;
+ RECT 2225.820000 1316.380000 2227.560000 1704.360000 ;
+ LAYER met3 ;
+ RECT 2225.820000 1316.380000 2696.080000 1318.120000 ;
+ LAYER met3 ;
+ RECT 2225.820000 1702.620000 2696.080000 1704.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 1298.980000 2194.630000 1719.220000 ;
+ RECT 2717.290000 1298.980000 2718.090000 1719.220000 ;
+ LAYER met3 ;
+ RECT 2717.290000 1711.840000 2718.090000 1712.320000 ;
+ RECT 2717.290000 1695.520000 2718.090000 1696.000000 ;
+ RECT 2717.290000 1700.960000 2718.090000 1701.440000 ;
+ RECT 2717.290000 1706.400000 2718.090000 1706.880000 ;
+ RECT 2717.290000 1679.200000 2718.090000 1679.680000 ;
+ RECT 2717.290000 1684.640000 2718.090000 1685.120000 ;
+ RECT 2717.290000 1690.080000 2718.090000 1690.560000 ;
+ RECT 2717.290000 1662.880000 2718.090000 1663.360000 ;
+ RECT 2717.290000 1668.320000 2718.090000 1668.800000 ;
+ RECT 2717.290000 1673.760000 2718.090000 1674.240000 ;
+ RECT 2717.290000 1646.560000 2718.090000 1647.040000 ;
+ RECT 2717.290000 1652.000000 2718.090000 1652.480000 ;
+ RECT 2717.290000 1657.440000 2718.090000 1657.920000 ;
+ RECT 2717.290000 1635.680000 2718.090000 1636.160000 ;
+ RECT 2717.290000 1630.240000 2718.090000 1630.720000 ;
+ RECT 2717.290000 1608.480000 2718.090000 1608.960000 ;
+ RECT 2717.290000 1613.920000 2718.090000 1614.400000 ;
+ RECT 2717.290000 1619.360000 2718.090000 1619.840000 ;
+ RECT 2717.290000 1624.800000 2718.090000 1625.280000 ;
+ RECT 2717.290000 1592.160000 2718.090000 1592.640000 ;
+ RECT 2717.290000 1597.600000 2718.090000 1598.080000 ;
+ RECT 2717.290000 1603.040000 2718.090000 1603.520000 ;
+ RECT 2717.290000 1575.840000 2718.090000 1576.320000 ;
+ RECT 2717.290000 1581.280000 2718.090000 1581.760000 ;
+ RECT 2717.290000 1586.720000 2718.090000 1587.200000 ;
+ RECT 2717.290000 1559.520000 2718.090000 1560.000000 ;
+ RECT 2717.290000 1564.960000 2718.090000 1565.440000 ;
+ RECT 2717.290000 1570.400000 2718.090000 1570.880000 ;
+ RECT 2717.290000 1543.200000 2718.090000 1543.680000 ;
+ RECT 2717.290000 1548.640000 2718.090000 1549.120000 ;
+ RECT 2717.290000 1554.080000 2718.090000 1554.560000 ;
+ RECT 2717.290000 1526.880000 2718.090000 1527.360000 ;
+ RECT 2717.290000 1532.320000 2718.090000 1532.800000 ;
+ RECT 2717.290000 1537.760000 2718.090000 1538.240000 ;
+ RECT 2717.290000 1510.560000 2718.090000 1511.040000 ;
+ RECT 2717.290000 1516.000000 2718.090000 1516.480000 ;
+ RECT 2717.290000 1521.440000 2718.090000 1521.920000 ;
+ RECT 2717.290000 1641.120000 2718.090000 1641.600000 ;
+ RECT 2193.830000 1711.840000 2194.630000 1712.320000 ;
+ RECT 2193.830000 1695.520000 2194.630000 1696.000000 ;
+ RECT 2193.830000 1700.960000 2194.630000 1701.440000 ;
+ RECT 2193.830000 1706.400000 2194.630000 1706.880000 ;
+ RECT 2193.830000 1679.200000 2194.630000 1679.680000 ;
+ RECT 2193.830000 1684.640000 2194.630000 1685.120000 ;
+ RECT 2193.830000 1690.080000 2194.630000 1690.560000 ;
+ RECT 2193.830000 1662.880000 2194.630000 1663.360000 ;
+ RECT 2193.830000 1668.320000 2194.630000 1668.800000 ;
+ RECT 2193.830000 1673.760000 2194.630000 1674.240000 ;
+ RECT 2193.830000 1646.560000 2194.630000 1647.040000 ;
+ RECT 2193.830000 1652.000000 2194.630000 1652.480000 ;
+ RECT 2193.830000 1657.440000 2194.630000 1657.920000 ;
+ RECT 2193.830000 1635.680000 2194.630000 1636.160000 ;
+ RECT 2193.830000 1630.240000 2194.630000 1630.720000 ;
+ RECT 2193.830000 1608.480000 2194.630000 1608.960000 ;
+ RECT 2193.830000 1613.920000 2194.630000 1614.400000 ;
+ RECT 2193.830000 1619.360000 2194.630000 1619.840000 ;
+ RECT 2193.830000 1624.800000 2194.630000 1625.280000 ;
+ RECT 2193.830000 1592.160000 2194.630000 1592.640000 ;
+ RECT 2193.830000 1597.600000 2194.630000 1598.080000 ;
+ RECT 2193.830000 1603.040000 2194.630000 1603.520000 ;
+ RECT 2193.830000 1575.840000 2194.630000 1576.320000 ;
+ RECT 2193.830000 1581.280000 2194.630000 1581.760000 ;
+ RECT 2193.830000 1586.720000 2194.630000 1587.200000 ;
+ RECT 2193.830000 1559.520000 2194.630000 1560.000000 ;
+ RECT 2193.830000 1564.960000 2194.630000 1565.440000 ;
+ RECT 2193.830000 1570.400000 2194.630000 1570.880000 ;
+ RECT 2193.830000 1543.200000 2194.630000 1543.680000 ;
+ RECT 2193.830000 1548.640000 2194.630000 1549.120000 ;
+ RECT 2193.830000 1554.080000 2194.630000 1554.560000 ;
+ RECT 2193.830000 1526.880000 2194.630000 1527.360000 ;
+ RECT 2193.830000 1532.320000 2194.630000 1532.800000 ;
+ RECT 2193.830000 1537.760000 2194.630000 1538.240000 ;
+ RECT 2193.830000 1510.560000 2194.630000 1511.040000 ;
+ RECT 2193.830000 1516.000000 2194.630000 1516.480000 ;
+ RECT 2193.830000 1521.440000 2194.630000 1521.920000 ;
+ RECT 2193.830000 1641.120000 2194.630000 1641.600000 ;
+ RECT 2717.290000 1494.240000 2718.090000 1494.720000 ;
+ RECT 2717.290000 1499.680000 2718.090000 1500.160000 ;
+ RECT 2717.290000 1505.120000 2718.090000 1505.600000 ;
+ RECT 2717.290000 1477.920000 2718.090000 1478.400000 ;
+ RECT 2717.290000 1483.360000 2718.090000 1483.840000 ;
+ RECT 2717.290000 1488.800000 2718.090000 1489.280000 ;
+ RECT 2717.290000 1461.600000 2718.090000 1462.080000 ;
+ RECT 2717.290000 1467.040000 2718.090000 1467.520000 ;
+ RECT 2717.290000 1472.480000 2718.090000 1472.960000 ;
+ RECT 2717.290000 1445.280000 2718.090000 1445.760000 ;
+ RECT 2717.290000 1450.720000 2718.090000 1451.200000 ;
+ RECT 2717.290000 1456.160000 2718.090000 1456.640000 ;
+ RECT 2717.290000 1439.840000 2718.090000 1440.320000 ;
+ RECT 2717.290000 1434.400000 2718.090000 1434.880000 ;
+ RECT 2717.290000 1428.960000 2718.090000 1429.440000 ;
+ RECT 2717.290000 1412.640000 2718.090000 1413.120000 ;
+ RECT 2717.290000 1418.080000 2718.090000 1418.560000 ;
+ RECT 2717.290000 1423.520000 2718.090000 1424.000000 ;
+ RECT 2717.290000 1396.320000 2718.090000 1396.800000 ;
+ RECT 2717.290000 1401.760000 2718.090000 1402.240000 ;
+ RECT 2717.290000 1407.200000 2718.090000 1407.680000 ;
+ RECT 2717.290000 1380.000000 2718.090000 1380.480000 ;
+ RECT 2717.290000 1385.440000 2718.090000 1385.920000 ;
+ RECT 2717.290000 1390.880000 2718.090000 1391.360000 ;
+ RECT 2717.290000 1363.680000 2718.090000 1364.160000 ;
+ RECT 2717.290000 1369.120000 2718.090000 1369.600000 ;
+ RECT 2717.290000 1374.560000 2718.090000 1375.040000 ;
+ RECT 2717.290000 1347.360000 2718.090000 1347.840000 ;
+ RECT 2717.290000 1352.800000 2718.090000 1353.280000 ;
+ RECT 2717.290000 1358.240000 2718.090000 1358.720000 ;
+ RECT 2717.290000 1331.040000 2718.090000 1331.520000 ;
+ RECT 2717.290000 1336.480000 2718.090000 1336.960000 ;
+ RECT 2717.290000 1341.920000 2718.090000 1342.400000 ;
+ RECT 2717.290000 1314.720000 2718.090000 1315.200000 ;
+ RECT 2717.290000 1320.160000 2718.090000 1320.640000 ;
+ RECT 2717.290000 1325.600000 2718.090000 1326.080000 ;
+ RECT 2717.290000 1309.280000 2718.090000 1309.760000 ;
+ RECT 2717.290000 1303.840000 2718.090000 1304.320000 ;
+ RECT 2193.830000 1505.120000 2194.630000 1505.600000 ;
+ RECT 2193.830000 1494.240000 2194.630000 1494.720000 ;
+ RECT 2193.830000 1499.680000 2194.630000 1500.160000 ;
+ RECT 2193.830000 1477.920000 2194.630000 1478.400000 ;
+ RECT 2193.830000 1483.360000 2194.630000 1483.840000 ;
+ RECT 2193.830000 1488.800000 2194.630000 1489.280000 ;
+ RECT 2193.830000 1461.600000 2194.630000 1462.080000 ;
+ RECT 2193.830000 1467.040000 2194.630000 1467.520000 ;
+ RECT 2193.830000 1472.480000 2194.630000 1472.960000 ;
+ RECT 2193.830000 1445.280000 2194.630000 1445.760000 ;
+ RECT 2193.830000 1450.720000 2194.630000 1451.200000 ;
+ RECT 2193.830000 1456.160000 2194.630000 1456.640000 ;
+ RECT 2193.830000 1439.840000 2194.630000 1440.320000 ;
+ RECT 2193.830000 1434.400000 2194.630000 1434.880000 ;
+ RECT 2193.830000 1428.960000 2194.630000 1429.440000 ;
+ RECT 2193.830000 1412.640000 2194.630000 1413.120000 ;
+ RECT 2193.830000 1418.080000 2194.630000 1418.560000 ;
+ RECT 2193.830000 1423.520000 2194.630000 1424.000000 ;
+ RECT 2193.830000 1401.760000 2194.630000 1402.240000 ;
+ RECT 2193.830000 1407.200000 2194.630000 1407.680000 ;
+ RECT 2193.830000 1396.320000 2194.630000 1396.800000 ;
+ RECT 2193.830000 1380.000000 2194.630000 1380.480000 ;
+ RECT 2193.830000 1385.440000 2194.630000 1385.920000 ;
+ RECT 2193.830000 1390.880000 2194.630000 1391.360000 ;
+ RECT 2193.830000 1363.680000 2194.630000 1364.160000 ;
+ RECT 2193.830000 1369.120000 2194.630000 1369.600000 ;
+ RECT 2193.830000 1374.560000 2194.630000 1375.040000 ;
+ RECT 2193.830000 1352.800000 2194.630000 1353.280000 ;
+ RECT 2193.830000 1358.240000 2194.630000 1358.720000 ;
+ RECT 2193.830000 1347.360000 2194.630000 1347.840000 ;
+ RECT 2193.830000 1331.040000 2194.630000 1331.520000 ;
+ RECT 2193.830000 1336.480000 2194.630000 1336.960000 ;
+ RECT 2193.830000 1341.920000 2194.630000 1342.400000 ;
+ RECT 2193.830000 1325.600000 2194.630000 1326.080000 ;
+ RECT 2193.830000 1314.720000 2194.630000 1315.200000 ;
+ RECT 2193.830000 1320.160000 2194.630000 1320.640000 ;
+ RECT 2193.830000 1303.840000 2194.630000 1304.320000 ;
+ RECT 2193.830000 1309.280000 2194.630000 1309.760000 ;
+ RECT 2193.830000 1714.550000 2720.920000 1715.350000 ;
+ RECT 2193.830000 1301.830000 2720.920000 1302.630000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 1298.980000 2194.630000 1299.780000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 1718.420000 2194.630000 1719.220000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 1298.980000 2718.090000 1299.780000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 1718.420000 2718.090000 1719.220000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 1301.830000 2720.920000 1302.630000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 1714.550000 2720.920000 1715.350000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2694.340000 1736.620000 2696.080000 2124.600000 ;
+ LAYER met4 ;
+ RECT 2225.820000 1736.620000 2227.560000 2124.600000 ;
+ LAYER met3 ;
+ RECT 2225.820000 1736.620000 2696.080000 1738.360000 ;
+ LAYER met3 ;
+ RECT 2225.820000 2122.860000 2696.080000 2124.600000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 1719.220000 2194.630000 2139.460000 ;
+ RECT 2717.290000 1719.220000 2718.090000 2139.460000 ;
+ LAYER met3 ;
+ RECT 2717.290000 2132.080000 2718.090000 2132.560000 ;
+ RECT 2717.290000 2115.760000 2718.090000 2116.240000 ;
+ RECT 2717.290000 2121.200000 2718.090000 2121.680000 ;
+ RECT 2717.290000 2126.640000 2718.090000 2127.120000 ;
+ RECT 2717.290000 2099.440000 2718.090000 2099.920000 ;
+ RECT 2717.290000 2104.880000 2718.090000 2105.360000 ;
+ RECT 2717.290000 2110.320000 2718.090000 2110.800000 ;
+ RECT 2717.290000 2083.120000 2718.090000 2083.600000 ;
+ RECT 2717.290000 2088.560000 2718.090000 2089.040000 ;
+ RECT 2717.290000 2094.000000 2718.090000 2094.480000 ;
+ RECT 2717.290000 2066.800000 2718.090000 2067.280000 ;
+ RECT 2717.290000 2072.240000 2718.090000 2072.720000 ;
+ RECT 2717.290000 2077.680000 2718.090000 2078.160000 ;
+ RECT 2717.290000 2055.920000 2718.090000 2056.400000 ;
+ RECT 2717.290000 2050.480000 2718.090000 2050.960000 ;
+ RECT 2717.290000 2028.720000 2718.090000 2029.200000 ;
+ RECT 2717.290000 2034.160000 2718.090000 2034.640000 ;
+ RECT 2717.290000 2039.600000 2718.090000 2040.080000 ;
+ RECT 2717.290000 2045.040000 2718.090000 2045.520000 ;
+ RECT 2717.290000 2012.400000 2718.090000 2012.880000 ;
+ RECT 2717.290000 2017.840000 2718.090000 2018.320000 ;
+ RECT 2717.290000 2023.280000 2718.090000 2023.760000 ;
+ RECT 2717.290000 1996.080000 2718.090000 1996.560000 ;
+ RECT 2717.290000 2001.520000 2718.090000 2002.000000 ;
+ RECT 2717.290000 2006.960000 2718.090000 2007.440000 ;
+ RECT 2717.290000 1979.760000 2718.090000 1980.240000 ;
+ RECT 2717.290000 1985.200000 2718.090000 1985.680000 ;
+ RECT 2717.290000 1990.640000 2718.090000 1991.120000 ;
+ RECT 2717.290000 1963.440000 2718.090000 1963.920000 ;
+ RECT 2717.290000 1968.880000 2718.090000 1969.360000 ;
+ RECT 2717.290000 1974.320000 2718.090000 1974.800000 ;
+ RECT 2717.290000 1947.120000 2718.090000 1947.600000 ;
+ RECT 2717.290000 1952.560000 2718.090000 1953.040000 ;
+ RECT 2717.290000 1958.000000 2718.090000 1958.480000 ;
+ RECT 2717.290000 1930.800000 2718.090000 1931.280000 ;
+ RECT 2717.290000 1936.240000 2718.090000 1936.720000 ;
+ RECT 2717.290000 1941.680000 2718.090000 1942.160000 ;
+ RECT 2717.290000 2061.360000 2718.090000 2061.840000 ;
+ RECT 2193.830000 2132.080000 2194.630000 2132.560000 ;
+ RECT 2193.830000 2115.760000 2194.630000 2116.240000 ;
+ RECT 2193.830000 2121.200000 2194.630000 2121.680000 ;
+ RECT 2193.830000 2126.640000 2194.630000 2127.120000 ;
+ RECT 2193.830000 2099.440000 2194.630000 2099.920000 ;
+ RECT 2193.830000 2104.880000 2194.630000 2105.360000 ;
+ RECT 2193.830000 2110.320000 2194.630000 2110.800000 ;
+ RECT 2193.830000 2083.120000 2194.630000 2083.600000 ;
+ RECT 2193.830000 2088.560000 2194.630000 2089.040000 ;
+ RECT 2193.830000 2094.000000 2194.630000 2094.480000 ;
+ RECT 2193.830000 2066.800000 2194.630000 2067.280000 ;
+ RECT 2193.830000 2072.240000 2194.630000 2072.720000 ;
+ RECT 2193.830000 2077.680000 2194.630000 2078.160000 ;
+ RECT 2193.830000 2055.920000 2194.630000 2056.400000 ;
+ RECT 2193.830000 2050.480000 2194.630000 2050.960000 ;
+ RECT 2193.830000 2028.720000 2194.630000 2029.200000 ;
+ RECT 2193.830000 2034.160000 2194.630000 2034.640000 ;
+ RECT 2193.830000 2039.600000 2194.630000 2040.080000 ;
+ RECT 2193.830000 2045.040000 2194.630000 2045.520000 ;
+ RECT 2193.830000 2012.400000 2194.630000 2012.880000 ;
+ RECT 2193.830000 2017.840000 2194.630000 2018.320000 ;
+ RECT 2193.830000 2023.280000 2194.630000 2023.760000 ;
+ RECT 2193.830000 1996.080000 2194.630000 1996.560000 ;
+ RECT 2193.830000 2001.520000 2194.630000 2002.000000 ;
+ RECT 2193.830000 2006.960000 2194.630000 2007.440000 ;
+ RECT 2193.830000 1979.760000 2194.630000 1980.240000 ;
+ RECT 2193.830000 1985.200000 2194.630000 1985.680000 ;
+ RECT 2193.830000 1990.640000 2194.630000 1991.120000 ;
+ RECT 2193.830000 1963.440000 2194.630000 1963.920000 ;
+ RECT 2193.830000 1968.880000 2194.630000 1969.360000 ;
+ RECT 2193.830000 1974.320000 2194.630000 1974.800000 ;
+ RECT 2193.830000 1947.120000 2194.630000 1947.600000 ;
+ RECT 2193.830000 1952.560000 2194.630000 1953.040000 ;
+ RECT 2193.830000 1958.000000 2194.630000 1958.480000 ;
+ RECT 2193.830000 1930.800000 2194.630000 1931.280000 ;
+ RECT 2193.830000 1936.240000 2194.630000 1936.720000 ;
+ RECT 2193.830000 1941.680000 2194.630000 1942.160000 ;
+ RECT 2193.830000 2061.360000 2194.630000 2061.840000 ;
+ RECT 2717.290000 1914.480000 2718.090000 1914.960000 ;
+ RECT 2717.290000 1919.920000 2718.090000 1920.400000 ;
+ RECT 2717.290000 1925.360000 2718.090000 1925.840000 ;
+ RECT 2717.290000 1898.160000 2718.090000 1898.640000 ;
+ RECT 2717.290000 1903.600000 2718.090000 1904.080000 ;
+ RECT 2717.290000 1909.040000 2718.090000 1909.520000 ;
+ RECT 2717.290000 1881.840000 2718.090000 1882.320000 ;
+ RECT 2717.290000 1887.280000 2718.090000 1887.760000 ;
+ RECT 2717.290000 1892.720000 2718.090000 1893.200000 ;
+ RECT 2717.290000 1865.520000 2718.090000 1866.000000 ;
+ RECT 2717.290000 1870.960000 2718.090000 1871.440000 ;
+ RECT 2717.290000 1876.400000 2718.090000 1876.880000 ;
+ RECT 2717.290000 1860.080000 2718.090000 1860.560000 ;
+ RECT 2717.290000 1854.640000 2718.090000 1855.120000 ;
+ RECT 2717.290000 1849.200000 2718.090000 1849.680000 ;
+ RECT 2717.290000 1832.880000 2718.090000 1833.360000 ;
+ RECT 2717.290000 1838.320000 2718.090000 1838.800000 ;
+ RECT 2717.290000 1843.760000 2718.090000 1844.240000 ;
+ RECT 2717.290000 1816.560000 2718.090000 1817.040000 ;
+ RECT 2717.290000 1822.000000 2718.090000 1822.480000 ;
+ RECT 2717.290000 1827.440000 2718.090000 1827.920000 ;
+ RECT 2717.290000 1800.240000 2718.090000 1800.720000 ;
+ RECT 2717.290000 1805.680000 2718.090000 1806.160000 ;
+ RECT 2717.290000 1811.120000 2718.090000 1811.600000 ;
+ RECT 2717.290000 1783.920000 2718.090000 1784.400000 ;
+ RECT 2717.290000 1789.360000 2718.090000 1789.840000 ;
+ RECT 2717.290000 1794.800000 2718.090000 1795.280000 ;
+ RECT 2717.290000 1767.600000 2718.090000 1768.080000 ;
+ RECT 2717.290000 1773.040000 2718.090000 1773.520000 ;
+ RECT 2717.290000 1778.480000 2718.090000 1778.960000 ;
+ RECT 2717.290000 1751.280000 2718.090000 1751.760000 ;
+ RECT 2717.290000 1756.720000 2718.090000 1757.200000 ;
+ RECT 2717.290000 1762.160000 2718.090000 1762.640000 ;
+ RECT 2717.290000 1734.960000 2718.090000 1735.440000 ;
+ RECT 2717.290000 1740.400000 2718.090000 1740.880000 ;
+ RECT 2717.290000 1745.840000 2718.090000 1746.320000 ;
+ RECT 2717.290000 1729.520000 2718.090000 1730.000000 ;
+ RECT 2717.290000 1724.080000 2718.090000 1724.560000 ;
+ RECT 2193.830000 1925.360000 2194.630000 1925.840000 ;
+ RECT 2193.830000 1914.480000 2194.630000 1914.960000 ;
+ RECT 2193.830000 1919.920000 2194.630000 1920.400000 ;
+ RECT 2193.830000 1898.160000 2194.630000 1898.640000 ;
+ RECT 2193.830000 1903.600000 2194.630000 1904.080000 ;
+ RECT 2193.830000 1909.040000 2194.630000 1909.520000 ;
+ RECT 2193.830000 1881.840000 2194.630000 1882.320000 ;
+ RECT 2193.830000 1887.280000 2194.630000 1887.760000 ;
+ RECT 2193.830000 1892.720000 2194.630000 1893.200000 ;
+ RECT 2193.830000 1865.520000 2194.630000 1866.000000 ;
+ RECT 2193.830000 1870.960000 2194.630000 1871.440000 ;
+ RECT 2193.830000 1876.400000 2194.630000 1876.880000 ;
+ RECT 2193.830000 1860.080000 2194.630000 1860.560000 ;
+ RECT 2193.830000 1854.640000 2194.630000 1855.120000 ;
+ RECT 2193.830000 1849.200000 2194.630000 1849.680000 ;
+ RECT 2193.830000 1832.880000 2194.630000 1833.360000 ;
+ RECT 2193.830000 1838.320000 2194.630000 1838.800000 ;
+ RECT 2193.830000 1843.760000 2194.630000 1844.240000 ;
+ RECT 2193.830000 1822.000000 2194.630000 1822.480000 ;
+ RECT 2193.830000 1827.440000 2194.630000 1827.920000 ;
+ RECT 2193.830000 1816.560000 2194.630000 1817.040000 ;
+ RECT 2193.830000 1800.240000 2194.630000 1800.720000 ;
+ RECT 2193.830000 1805.680000 2194.630000 1806.160000 ;
+ RECT 2193.830000 1811.120000 2194.630000 1811.600000 ;
+ RECT 2193.830000 1783.920000 2194.630000 1784.400000 ;
+ RECT 2193.830000 1789.360000 2194.630000 1789.840000 ;
+ RECT 2193.830000 1794.800000 2194.630000 1795.280000 ;
+ RECT 2193.830000 1773.040000 2194.630000 1773.520000 ;
+ RECT 2193.830000 1778.480000 2194.630000 1778.960000 ;
+ RECT 2193.830000 1767.600000 2194.630000 1768.080000 ;
+ RECT 2193.830000 1751.280000 2194.630000 1751.760000 ;
+ RECT 2193.830000 1756.720000 2194.630000 1757.200000 ;
+ RECT 2193.830000 1762.160000 2194.630000 1762.640000 ;
+ RECT 2193.830000 1745.840000 2194.630000 1746.320000 ;
+ RECT 2193.830000 1734.960000 2194.630000 1735.440000 ;
+ RECT 2193.830000 1740.400000 2194.630000 1740.880000 ;
+ RECT 2193.830000 1724.080000 2194.630000 1724.560000 ;
+ RECT 2193.830000 1729.520000 2194.630000 1730.000000 ;
+ RECT 2193.830000 2134.790000 2720.920000 2135.590000 ;
+ RECT 2193.830000 1722.070000 2720.920000 1722.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 1719.220000 2194.630000 1720.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 2138.660000 2194.630000 2139.460000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 1719.220000 2718.090000 1720.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 2138.660000 2718.090000 2139.460000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 1722.070000 2720.920000 1722.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2134.790000 2720.920000 2135.590000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2694.340000 2156.860000 2696.080000 2544.840000 ;
+ LAYER met4 ;
+ RECT 2225.820000 2156.860000 2227.560000 2544.840000 ;
+ LAYER met3 ;
+ RECT 2225.820000 2156.860000 2696.080000 2158.600000 ;
+ LAYER met3 ;
+ RECT 2225.820000 2543.100000 2696.080000 2544.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 2139.460000 2194.630000 2559.700000 ;
+ RECT 2717.290000 2139.460000 2718.090000 2559.700000 ;
+ LAYER met3 ;
+ RECT 2717.290000 2552.320000 2718.090000 2552.800000 ;
+ RECT 2717.290000 2536.000000 2718.090000 2536.480000 ;
+ RECT 2717.290000 2541.440000 2718.090000 2541.920000 ;
+ RECT 2717.290000 2546.880000 2718.090000 2547.360000 ;
+ RECT 2717.290000 2519.680000 2718.090000 2520.160000 ;
+ RECT 2717.290000 2525.120000 2718.090000 2525.600000 ;
+ RECT 2717.290000 2530.560000 2718.090000 2531.040000 ;
+ RECT 2717.290000 2503.360000 2718.090000 2503.840000 ;
+ RECT 2717.290000 2508.800000 2718.090000 2509.280000 ;
+ RECT 2717.290000 2514.240000 2718.090000 2514.720000 ;
+ RECT 2717.290000 2487.040000 2718.090000 2487.520000 ;
+ RECT 2717.290000 2492.480000 2718.090000 2492.960000 ;
+ RECT 2717.290000 2497.920000 2718.090000 2498.400000 ;
+ RECT 2717.290000 2476.160000 2718.090000 2476.640000 ;
+ RECT 2717.290000 2470.720000 2718.090000 2471.200000 ;
+ RECT 2717.290000 2448.960000 2718.090000 2449.440000 ;
+ RECT 2717.290000 2454.400000 2718.090000 2454.880000 ;
+ RECT 2717.290000 2459.840000 2718.090000 2460.320000 ;
+ RECT 2717.290000 2465.280000 2718.090000 2465.760000 ;
+ RECT 2717.290000 2432.640000 2718.090000 2433.120000 ;
+ RECT 2717.290000 2438.080000 2718.090000 2438.560000 ;
+ RECT 2717.290000 2443.520000 2718.090000 2444.000000 ;
+ RECT 2717.290000 2416.320000 2718.090000 2416.800000 ;
+ RECT 2717.290000 2421.760000 2718.090000 2422.240000 ;
+ RECT 2717.290000 2427.200000 2718.090000 2427.680000 ;
+ RECT 2717.290000 2400.000000 2718.090000 2400.480000 ;
+ RECT 2717.290000 2405.440000 2718.090000 2405.920000 ;
+ RECT 2717.290000 2410.880000 2718.090000 2411.360000 ;
+ RECT 2717.290000 2383.680000 2718.090000 2384.160000 ;
+ RECT 2717.290000 2389.120000 2718.090000 2389.600000 ;
+ RECT 2717.290000 2394.560000 2718.090000 2395.040000 ;
+ RECT 2717.290000 2367.360000 2718.090000 2367.840000 ;
+ RECT 2717.290000 2372.800000 2718.090000 2373.280000 ;
+ RECT 2717.290000 2378.240000 2718.090000 2378.720000 ;
+ RECT 2717.290000 2351.040000 2718.090000 2351.520000 ;
+ RECT 2717.290000 2356.480000 2718.090000 2356.960000 ;
+ RECT 2717.290000 2361.920000 2718.090000 2362.400000 ;
+ RECT 2717.290000 2481.600000 2718.090000 2482.080000 ;
+ RECT 2193.830000 2552.320000 2194.630000 2552.800000 ;
+ RECT 2193.830000 2536.000000 2194.630000 2536.480000 ;
+ RECT 2193.830000 2541.440000 2194.630000 2541.920000 ;
+ RECT 2193.830000 2546.880000 2194.630000 2547.360000 ;
+ RECT 2193.830000 2519.680000 2194.630000 2520.160000 ;
+ RECT 2193.830000 2525.120000 2194.630000 2525.600000 ;
+ RECT 2193.830000 2530.560000 2194.630000 2531.040000 ;
+ RECT 2193.830000 2503.360000 2194.630000 2503.840000 ;
+ RECT 2193.830000 2508.800000 2194.630000 2509.280000 ;
+ RECT 2193.830000 2514.240000 2194.630000 2514.720000 ;
+ RECT 2193.830000 2487.040000 2194.630000 2487.520000 ;
+ RECT 2193.830000 2492.480000 2194.630000 2492.960000 ;
+ RECT 2193.830000 2497.920000 2194.630000 2498.400000 ;
+ RECT 2193.830000 2476.160000 2194.630000 2476.640000 ;
+ RECT 2193.830000 2470.720000 2194.630000 2471.200000 ;
+ RECT 2193.830000 2448.960000 2194.630000 2449.440000 ;
+ RECT 2193.830000 2454.400000 2194.630000 2454.880000 ;
+ RECT 2193.830000 2459.840000 2194.630000 2460.320000 ;
+ RECT 2193.830000 2465.280000 2194.630000 2465.760000 ;
+ RECT 2193.830000 2432.640000 2194.630000 2433.120000 ;
+ RECT 2193.830000 2438.080000 2194.630000 2438.560000 ;
+ RECT 2193.830000 2443.520000 2194.630000 2444.000000 ;
+ RECT 2193.830000 2416.320000 2194.630000 2416.800000 ;
+ RECT 2193.830000 2421.760000 2194.630000 2422.240000 ;
+ RECT 2193.830000 2427.200000 2194.630000 2427.680000 ;
+ RECT 2193.830000 2400.000000 2194.630000 2400.480000 ;
+ RECT 2193.830000 2405.440000 2194.630000 2405.920000 ;
+ RECT 2193.830000 2410.880000 2194.630000 2411.360000 ;
+ RECT 2193.830000 2383.680000 2194.630000 2384.160000 ;
+ RECT 2193.830000 2389.120000 2194.630000 2389.600000 ;
+ RECT 2193.830000 2394.560000 2194.630000 2395.040000 ;
+ RECT 2193.830000 2367.360000 2194.630000 2367.840000 ;
+ RECT 2193.830000 2372.800000 2194.630000 2373.280000 ;
+ RECT 2193.830000 2378.240000 2194.630000 2378.720000 ;
+ RECT 2193.830000 2351.040000 2194.630000 2351.520000 ;
+ RECT 2193.830000 2356.480000 2194.630000 2356.960000 ;
+ RECT 2193.830000 2361.920000 2194.630000 2362.400000 ;
+ RECT 2193.830000 2481.600000 2194.630000 2482.080000 ;
+ RECT 2717.290000 2334.720000 2718.090000 2335.200000 ;
+ RECT 2717.290000 2340.160000 2718.090000 2340.640000 ;
+ RECT 2717.290000 2345.600000 2718.090000 2346.080000 ;
+ RECT 2717.290000 2318.400000 2718.090000 2318.880000 ;
+ RECT 2717.290000 2323.840000 2718.090000 2324.320000 ;
+ RECT 2717.290000 2329.280000 2718.090000 2329.760000 ;
+ RECT 2717.290000 2302.080000 2718.090000 2302.560000 ;
+ RECT 2717.290000 2307.520000 2718.090000 2308.000000 ;
+ RECT 2717.290000 2312.960000 2718.090000 2313.440000 ;
+ RECT 2717.290000 2285.760000 2718.090000 2286.240000 ;
+ RECT 2717.290000 2291.200000 2718.090000 2291.680000 ;
+ RECT 2717.290000 2296.640000 2718.090000 2297.120000 ;
+ RECT 2717.290000 2280.320000 2718.090000 2280.800000 ;
+ RECT 2717.290000 2274.880000 2718.090000 2275.360000 ;
+ RECT 2717.290000 2269.440000 2718.090000 2269.920000 ;
+ RECT 2717.290000 2253.120000 2718.090000 2253.600000 ;
+ RECT 2717.290000 2258.560000 2718.090000 2259.040000 ;
+ RECT 2717.290000 2264.000000 2718.090000 2264.480000 ;
+ RECT 2717.290000 2236.800000 2718.090000 2237.280000 ;
+ RECT 2717.290000 2242.240000 2718.090000 2242.720000 ;
+ RECT 2717.290000 2247.680000 2718.090000 2248.160000 ;
+ RECT 2717.290000 2220.480000 2718.090000 2220.960000 ;
+ RECT 2717.290000 2225.920000 2718.090000 2226.400000 ;
+ RECT 2717.290000 2231.360000 2718.090000 2231.840000 ;
+ RECT 2717.290000 2204.160000 2718.090000 2204.640000 ;
+ RECT 2717.290000 2209.600000 2718.090000 2210.080000 ;
+ RECT 2717.290000 2215.040000 2718.090000 2215.520000 ;
+ RECT 2717.290000 2187.840000 2718.090000 2188.320000 ;
+ RECT 2717.290000 2193.280000 2718.090000 2193.760000 ;
+ RECT 2717.290000 2198.720000 2718.090000 2199.200000 ;
+ RECT 2717.290000 2171.520000 2718.090000 2172.000000 ;
+ RECT 2717.290000 2176.960000 2718.090000 2177.440000 ;
+ RECT 2717.290000 2182.400000 2718.090000 2182.880000 ;
+ RECT 2717.290000 2155.200000 2718.090000 2155.680000 ;
+ RECT 2717.290000 2160.640000 2718.090000 2161.120000 ;
+ RECT 2717.290000 2166.080000 2718.090000 2166.560000 ;
+ RECT 2717.290000 2149.760000 2718.090000 2150.240000 ;
+ RECT 2717.290000 2144.320000 2718.090000 2144.800000 ;
+ RECT 2193.830000 2345.600000 2194.630000 2346.080000 ;
+ RECT 2193.830000 2334.720000 2194.630000 2335.200000 ;
+ RECT 2193.830000 2340.160000 2194.630000 2340.640000 ;
+ RECT 2193.830000 2318.400000 2194.630000 2318.880000 ;
+ RECT 2193.830000 2323.840000 2194.630000 2324.320000 ;
+ RECT 2193.830000 2329.280000 2194.630000 2329.760000 ;
+ RECT 2193.830000 2302.080000 2194.630000 2302.560000 ;
+ RECT 2193.830000 2307.520000 2194.630000 2308.000000 ;
+ RECT 2193.830000 2312.960000 2194.630000 2313.440000 ;
+ RECT 2193.830000 2285.760000 2194.630000 2286.240000 ;
+ RECT 2193.830000 2291.200000 2194.630000 2291.680000 ;
+ RECT 2193.830000 2296.640000 2194.630000 2297.120000 ;
+ RECT 2193.830000 2280.320000 2194.630000 2280.800000 ;
+ RECT 2193.830000 2274.880000 2194.630000 2275.360000 ;
+ RECT 2193.830000 2269.440000 2194.630000 2269.920000 ;
+ RECT 2193.830000 2253.120000 2194.630000 2253.600000 ;
+ RECT 2193.830000 2258.560000 2194.630000 2259.040000 ;
+ RECT 2193.830000 2264.000000 2194.630000 2264.480000 ;
+ RECT 2193.830000 2242.240000 2194.630000 2242.720000 ;
+ RECT 2193.830000 2247.680000 2194.630000 2248.160000 ;
+ RECT 2193.830000 2236.800000 2194.630000 2237.280000 ;
+ RECT 2193.830000 2220.480000 2194.630000 2220.960000 ;
+ RECT 2193.830000 2225.920000 2194.630000 2226.400000 ;
+ RECT 2193.830000 2231.360000 2194.630000 2231.840000 ;
+ RECT 2193.830000 2204.160000 2194.630000 2204.640000 ;
+ RECT 2193.830000 2209.600000 2194.630000 2210.080000 ;
+ RECT 2193.830000 2215.040000 2194.630000 2215.520000 ;
+ RECT 2193.830000 2193.280000 2194.630000 2193.760000 ;
+ RECT 2193.830000 2198.720000 2194.630000 2199.200000 ;
+ RECT 2193.830000 2187.840000 2194.630000 2188.320000 ;
+ RECT 2193.830000 2171.520000 2194.630000 2172.000000 ;
+ RECT 2193.830000 2176.960000 2194.630000 2177.440000 ;
+ RECT 2193.830000 2182.400000 2194.630000 2182.880000 ;
+ RECT 2193.830000 2166.080000 2194.630000 2166.560000 ;
+ RECT 2193.830000 2155.200000 2194.630000 2155.680000 ;
+ RECT 2193.830000 2160.640000 2194.630000 2161.120000 ;
+ RECT 2193.830000 2144.320000 2194.630000 2144.800000 ;
+ RECT 2193.830000 2149.760000 2194.630000 2150.240000 ;
+ RECT 2193.830000 2555.030000 2720.920000 2555.830000 ;
+ RECT 2193.830000 2142.310000 2720.920000 2143.110000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 2139.460000 2194.630000 2140.260000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 2558.900000 2194.630000 2559.700000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 2139.460000 2718.090000 2140.260000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 2558.900000 2718.090000 2559.700000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2142.310000 2720.920000 2143.110000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2555.030000 2720.920000 2555.830000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2694.340000 2577.100000 2696.080000 2965.080000 ;
+ LAYER met4 ;
+ RECT 2225.820000 2577.100000 2227.560000 2965.080000 ;
+ LAYER met3 ;
+ RECT 2225.820000 2577.100000 2696.080000 2578.840000 ;
+ LAYER met3 ;
+ RECT 2225.820000 2963.340000 2696.080000 2965.080000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 2559.700000 2194.630000 2979.940000 ;
+ RECT 2717.290000 2559.700000 2718.090000 2979.940000 ;
+ LAYER met3 ;
+ RECT 2717.290000 2972.560000 2718.090000 2973.040000 ;
+ RECT 2717.290000 2956.240000 2718.090000 2956.720000 ;
+ RECT 2717.290000 2961.680000 2718.090000 2962.160000 ;
+ RECT 2717.290000 2967.120000 2718.090000 2967.600000 ;
+ RECT 2717.290000 2939.920000 2718.090000 2940.400000 ;
+ RECT 2717.290000 2945.360000 2718.090000 2945.840000 ;
+ RECT 2717.290000 2950.800000 2718.090000 2951.280000 ;
+ RECT 2717.290000 2923.600000 2718.090000 2924.080000 ;
+ RECT 2717.290000 2929.040000 2718.090000 2929.520000 ;
+ RECT 2717.290000 2934.480000 2718.090000 2934.960000 ;
+ RECT 2717.290000 2907.280000 2718.090000 2907.760000 ;
+ RECT 2717.290000 2912.720000 2718.090000 2913.200000 ;
+ RECT 2717.290000 2918.160000 2718.090000 2918.640000 ;
+ RECT 2717.290000 2896.400000 2718.090000 2896.880000 ;
+ RECT 2717.290000 2890.960000 2718.090000 2891.440000 ;
+ RECT 2717.290000 2869.200000 2718.090000 2869.680000 ;
+ RECT 2717.290000 2874.640000 2718.090000 2875.120000 ;
+ RECT 2717.290000 2880.080000 2718.090000 2880.560000 ;
+ RECT 2717.290000 2885.520000 2718.090000 2886.000000 ;
+ RECT 2717.290000 2852.880000 2718.090000 2853.360000 ;
+ RECT 2717.290000 2858.320000 2718.090000 2858.800000 ;
+ RECT 2717.290000 2863.760000 2718.090000 2864.240000 ;
+ RECT 2717.290000 2836.560000 2718.090000 2837.040000 ;
+ RECT 2717.290000 2842.000000 2718.090000 2842.480000 ;
+ RECT 2717.290000 2847.440000 2718.090000 2847.920000 ;
+ RECT 2717.290000 2820.240000 2718.090000 2820.720000 ;
+ RECT 2717.290000 2825.680000 2718.090000 2826.160000 ;
+ RECT 2717.290000 2831.120000 2718.090000 2831.600000 ;
+ RECT 2717.290000 2803.920000 2718.090000 2804.400000 ;
+ RECT 2717.290000 2809.360000 2718.090000 2809.840000 ;
+ RECT 2717.290000 2814.800000 2718.090000 2815.280000 ;
+ RECT 2717.290000 2787.600000 2718.090000 2788.080000 ;
+ RECT 2717.290000 2793.040000 2718.090000 2793.520000 ;
+ RECT 2717.290000 2798.480000 2718.090000 2798.960000 ;
+ RECT 2717.290000 2771.280000 2718.090000 2771.760000 ;
+ RECT 2717.290000 2776.720000 2718.090000 2777.200000 ;
+ RECT 2717.290000 2782.160000 2718.090000 2782.640000 ;
+ RECT 2717.290000 2901.840000 2718.090000 2902.320000 ;
+ RECT 2193.830000 2972.560000 2194.630000 2973.040000 ;
+ RECT 2193.830000 2956.240000 2194.630000 2956.720000 ;
+ RECT 2193.830000 2961.680000 2194.630000 2962.160000 ;
+ RECT 2193.830000 2967.120000 2194.630000 2967.600000 ;
+ RECT 2193.830000 2939.920000 2194.630000 2940.400000 ;
+ RECT 2193.830000 2945.360000 2194.630000 2945.840000 ;
+ RECT 2193.830000 2950.800000 2194.630000 2951.280000 ;
+ RECT 2193.830000 2923.600000 2194.630000 2924.080000 ;
+ RECT 2193.830000 2929.040000 2194.630000 2929.520000 ;
+ RECT 2193.830000 2934.480000 2194.630000 2934.960000 ;
+ RECT 2193.830000 2907.280000 2194.630000 2907.760000 ;
+ RECT 2193.830000 2912.720000 2194.630000 2913.200000 ;
+ RECT 2193.830000 2918.160000 2194.630000 2918.640000 ;
+ RECT 2193.830000 2896.400000 2194.630000 2896.880000 ;
+ RECT 2193.830000 2890.960000 2194.630000 2891.440000 ;
+ RECT 2193.830000 2869.200000 2194.630000 2869.680000 ;
+ RECT 2193.830000 2874.640000 2194.630000 2875.120000 ;
+ RECT 2193.830000 2880.080000 2194.630000 2880.560000 ;
+ RECT 2193.830000 2885.520000 2194.630000 2886.000000 ;
+ RECT 2193.830000 2852.880000 2194.630000 2853.360000 ;
+ RECT 2193.830000 2858.320000 2194.630000 2858.800000 ;
+ RECT 2193.830000 2863.760000 2194.630000 2864.240000 ;
+ RECT 2193.830000 2836.560000 2194.630000 2837.040000 ;
+ RECT 2193.830000 2842.000000 2194.630000 2842.480000 ;
+ RECT 2193.830000 2847.440000 2194.630000 2847.920000 ;
+ RECT 2193.830000 2820.240000 2194.630000 2820.720000 ;
+ RECT 2193.830000 2825.680000 2194.630000 2826.160000 ;
+ RECT 2193.830000 2831.120000 2194.630000 2831.600000 ;
+ RECT 2193.830000 2803.920000 2194.630000 2804.400000 ;
+ RECT 2193.830000 2809.360000 2194.630000 2809.840000 ;
+ RECT 2193.830000 2814.800000 2194.630000 2815.280000 ;
+ RECT 2193.830000 2787.600000 2194.630000 2788.080000 ;
+ RECT 2193.830000 2793.040000 2194.630000 2793.520000 ;
+ RECT 2193.830000 2798.480000 2194.630000 2798.960000 ;
+ RECT 2193.830000 2771.280000 2194.630000 2771.760000 ;
+ RECT 2193.830000 2776.720000 2194.630000 2777.200000 ;
+ RECT 2193.830000 2782.160000 2194.630000 2782.640000 ;
+ RECT 2193.830000 2901.840000 2194.630000 2902.320000 ;
+ RECT 2717.290000 2754.960000 2718.090000 2755.440000 ;
+ RECT 2717.290000 2760.400000 2718.090000 2760.880000 ;
+ RECT 2717.290000 2765.840000 2718.090000 2766.320000 ;
+ RECT 2717.290000 2738.640000 2718.090000 2739.120000 ;
+ RECT 2717.290000 2744.080000 2718.090000 2744.560000 ;
+ RECT 2717.290000 2749.520000 2718.090000 2750.000000 ;
+ RECT 2717.290000 2722.320000 2718.090000 2722.800000 ;
+ RECT 2717.290000 2727.760000 2718.090000 2728.240000 ;
+ RECT 2717.290000 2733.200000 2718.090000 2733.680000 ;
+ RECT 2717.290000 2706.000000 2718.090000 2706.480000 ;
+ RECT 2717.290000 2711.440000 2718.090000 2711.920000 ;
+ RECT 2717.290000 2716.880000 2718.090000 2717.360000 ;
+ RECT 2717.290000 2700.560000 2718.090000 2701.040000 ;
+ RECT 2717.290000 2695.120000 2718.090000 2695.600000 ;
+ RECT 2717.290000 2689.680000 2718.090000 2690.160000 ;
+ RECT 2717.290000 2673.360000 2718.090000 2673.840000 ;
+ RECT 2717.290000 2678.800000 2718.090000 2679.280000 ;
+ RECT 2717.290000 2684.240000 2718.090000 2684.720000 ;
+ RECT 2717.290000 2657.040000 2718.090000 2657.520000 ;
+ RECT 2717.290000 2662.480000 2718.090000 2662.960000 ;
+ RECT 2717.290000 2667.920000 2718.090000 2668.400000 ;
+ RECT 2717.290000 2640.720000 2718.090000 2641.200000 ;
+ RECT 2717.290000 2646.160000 2718.090000 2646.640000 ;
+ RECT 2717.290000 2651.600000 2718.090000 2652.080000 ;
+ RECT 2717.290000 2624.400000 2718.090000 2624.880000 ;
+ RECT 2717.290000 2629.840000 2718.090000 2630.320000 ;
+ RECT 2717.290000 2635.280000 2718.090000 2635.760000 ;
+ RECT 2717.290000 2608.080000 2718.090000 2608.560000 ;
+ RECT 2717.290000 2613.520000 2718.090000 2614.000000 ;
+ RECT 2717.290000 2618.960000 2718.090000 2619.440000 ;
+ RECT 2717.290000 2591.760000 2718.090000 2592.240000 ;
+ RECT 2717.290000 2597.200000 2718.090000 2597.680000 ;
+ RECT 2717.290000 2602.640000 2718.090000 2603.120000 ;
+ RECT 2717.290000 2575.440000 2718.090000 2575.920000 ;
+ RECT 2717.290000 2580.880000 2718.090000 2581.360000 ;
+ RECT 2717.290000 2586.320000 2718.090000 2586.800000 ;
+ RECT 2717.290000 2570.000000 2718.090000 2570.480000 ;
+ RECT 2717.290000 2564.560000 2718.090000 2565.040000 ;
+ RECT 2193.830000 2765.840000 2194.630000 2766.320000 ;
+ RECT 2193.830000 2754.960000 2194.630000 2755.440000 ;
+ RECT 2193.830000 2760.400000 2194.630000 2760.880000 ;
+ RECT 2193.830000 2738.640000 2194.630000 2739.120000 ;
+ RECT 2193.830000 2744.080000 2194.630000 2744.560000 ;
+ RECT 2193.830000 2749.520000 2194.630000 2750.000000 ;
+ RECT 2193.830000 2722.320000 2194.630000 2722.800000 ;
+ RECT 2193.830000 2727.760000 2194.630000 2728.240000 ;
+ RECT 2193.830000 2733.200000 2194.630000 2733.680000 ;
+ RECT 2193.830000 2706.000000 2194.630000 2706.480000 ;
+ RECT 2193.830000 2711.440000 2194.630000 2711.920000 ;
+ RECT 2193.830000 2716.880000 2194.630000 2717.360000 ;
+ RECT 2193.830000 2700.560000 2194.630000 2701.040000 ;
+ RECT 2193.830000 2695.120000 2194.630000 2695.600000 ;
+ RECT 2193.830000 2689.680000 2194.630000 2690.160000 ;
+ RECT 2193.830000 2673.360000 2194.630000 2673.840000 ;
+ RECT 2193.830000 2678.800000 2194.630000 2679.280000 ;
+ RECT 2193.830000 2684.240000 2194.630000 2684.720000 ;
+ RECT 2193.830000 2662.480000 2194.630000 2662.960000 ;
+ RECT 2193.830000 2667.920000 2194.630000 2668.400000 ;
+ RECT 2193.830000 2657.040000 2194.630000 2657.520000 ;
+ RECT 2193.830000 2640.720000 2194.630000 2641.200000 ;
+ RECT 2193.830000 2646.160000 2194.630000 2646.640000 ;
+ RECT 2193.830000 2651.600000 2194.630000 2652.080000 ;
+ RECT 2193.830000 2624.400000 2194.630000 2624.880000 ;
+ RECT 2193.830000 2629.840000 2194.630000 2630.320000 ;
+ RECT 2193.830000 2635.280000 2194.630000 2635.760000 ;
+ RECT 2193.830000 2613.520000 2194.630000 2614.000000 ;
+ RECT 2193.830000 2618.960000 2194.630000 2619.440000 ;
+ RECT 2193.830000 2608.080000 2194.630000 2608.560000 ;
+ RECT 2193.830000 2591.760000 2194.630000 2592.240000 ;
+ RECT 2193.830000 2597.200000 2194.630000 2597.680000 ;
+ RECT 2193.830000 2602.640000 2194.630000 2603.120000 ;
+ RECT 2193.830000 2586.320000 2194.630000 2586.800000 ;
+ RECT 2193.830000 2575.440000 2194.630000 2575.920000 ;
+ RECT 2193.830000 2580.880000 2194.630000 2581.360000 ;
+ RECT 2193.830000 2564.560000 2194.630000 2565.040000 ;
+ RECT 2193.830000 2570.000000 2194.630000 2570.480000 ;
+ RECT 2193.830000 2975.270000 2720.920000 2976.070000 ;
+ RECT 2193.830000 2562.550000 2720.920000 2563.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 2559.700000 2194.630000 2560.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 2979.140000 2194.630000 2979.940000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 2559.700000 2718.090000 2560.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 2979.140000 2718.090000 2979.940000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2562.550000 2720.920000 2563.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2975.270000 2720.920000 2976.070000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'BlockRAM_1KB'
+ PORT
+ LAYER met4 ;
+ RECT 2694.340000 2997.340000 2696.080000 3385.320000 ;
+ LAYER met4 ;
+ RECT 2225.820000 2997.340000 2227.560000 3385.320000 ;
+ LAYER met3 ;
+ RECT 2225.820000 2997.340000 2696.080000 2999.080000 ;
+ LAYER met3 ;
+ RECT 2225.820000 3383.580000 2696.080000 3385.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 2979.940000 2194.630000 3400.180000 ;
+ RECT 2717.290000 2979.940000 2718.090000 3400.180000 ;
+ LAYER met3 ;
+ RECT 2717.290000 3392.800000 2718.090000 3393.280000 ;
+ RECT 2717.290000 3376.480000 2718.090000 3376.960000 ;
+ RECT 2717.290000 3381.920000 2718.090000 3382.400000 ;
+ RECT 2717.290000 3387.360000 2718.090000 3387.840000 ;
+ RECT 2717.290000 3360.160000 2718.090000 3360.640000 ;
+ RECT 2717.290000 3365.600000 2718.090000 3366.080000 ;
+ RECT 2717.290000 3371.040000 2718.090000 3371.520000 ;
+ RECT 2717.290000 3343.840000 2718.090000 3344.320000 ;
+ RECT 2717.290000 3349.280000 2718.090000 3349.760000 ;
+ RECT 2717.290000 3354.720000 2718.090000 3355.200000 ;
+ RECT 2717.290000 3327.520000 2718.090000 3328.000000 ;
+ RECT 2717.290000 3332.960000 2718.090000 3333.440000 ;
+ RECT 2717.290000 3338.400000 2718.090000 3338.880000 ;
+ RECT 2717.290000 3316.640000 2718.090000 3317.120000 ;
+ RECT 2717.290000 3311.200000 2718.090000 3311.680000 ;
+ RECT 2717.290000 3289.440000 2718.090000 3289.920000 ;
+ RECT 2717.290000 3294.880000 2718.090000 3295.360000 ;
+ RECT 2717.290000 3300.320000 2718.090000 3300.800000 ;
+ RECT 2717.290000 3305.760000 2718.090000 3306.240000 ;
+ RECT 2717.290000 3273.120000 2718.090000 3273.600000 ;
+ RECT 2717.290000 3278.560000 2718.090000 3279.040000 ;
+ RECT 2717.290000 3284.000000 2718.090000 3284.480000 ;
+ RECT 2717.290000 3256.800000 2718.090000 3257.280000 ;
+ RECT 2717.290000 3262.240000 2718.090000 3262.720000 ;
+ RECT 2717.290000 3267.680000 2718.090000 3268.160000 ;
+ RECT 2717.290000 3240.480000 2718.090000 3240.960000 ;
+ RECT 2717.290000 3245.920000 2718.090000 3246.400000 ;
+ RECT 2717.290000 3251.360000 2718.090000 3251.840000 ;
+ RECT 2717.290000 3224.160000 2718.090000 3224.640000 ;
+ RECT 2717.290000 3229.600000 2718.090000 3230.080000 ;
+ RECT 2717.290000 3235.040000 2718.090000 3235.520000 ;
+ RECT 2717.290000 3207.840000 2718.090000 3208.320000 ;
+ RECT 2717.290000 3213.280000 2718.090000 3213.760000 ;
+ RECT 2717.290000 3218.720000 2718.090000 3219.200000 ;
+ RECT 2717.290000 3191.520000 2718.090000 3192.000000 ;
+ RECT 2717.290000 3196.960000 2718.090000 3197.440000 ;
+ RECT 2717.290000 3202.400000 2718.090000 3202.880000 ;
+ RECT 2717.290000 3322.080000 2718.090000 3322.560000 ;
+ RECT 2193.830000 3392.800000 2194.630000 3393.280000 ;
+ RECT 2193.830000 3376.480000 2194.630000 3376.960000 ;
+ RECT 2193.830000 3381.920000 2194.630000 3382.400000 ;
+ RECT 2193.830000 3387.360000 2194.630000 3387.840000 ;
+ RECT 2193.830000 3360.160000 2194.630000 3360.640000 ;
+ RECT 2193.830000 3365.600000 2194.630000 3366.080000 ;
+ RECT 2193.830000 3371.040000 2194.630000 3371.520000 ;
+ RECT 2193.830000 3343.840000 2194.630000 3344.320000 ;
+ RECT 2193.830000 3349.280000 2194.630000 3349.760000 ;
+ RECT 2193.830000 3354.720000 2194.630000 3355.200000 ;
+ RECT 2193.830000 3327.520000 2194.630000 3328.000000 ;
+ RECT 2193.830000 3332.960000 2194.630000 3333.440000 ;
+ RECT 2193.830000 3338.400000 2194.630000 3338.880000 ;
+ RECT 2193.830000 3316.640000 2194.630000 3317.120000 ;
+ RECT 2193.830000 3311.200000 2194.630000 3311.680000 ;
+ RECT 2193.830000 3289.440000 2194.630000 3289.920000 ;
+ RECT 2193.830000 3294.880000 2194.630000 3295.360000 ;
+ RECT 2193.830000 3300.320000 2194.630000 3300.800000 ;
+ RECT 2193.830000 3305.760000 2194.630000 3306.240000 ;
+ RECT 2193.830000 3273.120000 2194.630000 3273.600000 ;
+ RECT 2193.830000 3278.560000 2194.630000 3279.040000 ;
+ RECT 2193.830000 3284.000000 2194.630000 3284.480000 ;
+ RECT 2193.830000 3256.800000 2194.630000 3257.280000 ;
+ RECT 2193.830000 3262.240000 2194.630000 3262.720000 ;
+ RECT 2193.830000 3267.680000 2194.630000 3268.160000 ;
+ RECT 2193.830000 3240.480000 2194.630000 3240.960000 ;
+ RECT 2193.830000 3245.920000 2194.630000 3246.400000 ;
+ RECT 2193.830000 3251.360000 2194.630000 3251.840000 ;
+ RECT 2193.830000 3224.160000 2194.630000 3224.640000 ;
+ RECT 2193.830000 3229.600000 2194.630000 3230.080000 ;
+ RECT 2193.830000 3235.040000 2194.630000 3235.520000 ;
+ RECT 2193.830000 3207.840000 2194.630000 3208.320000 ;
+ RECT 2193.830000 3213.280000 2194.630000 3213.760000 ;
+ RECT 2193.830000 3218.720000 2194.630000 3219.200000 ;
+ RECT 2193.830000 3191.520000 2194.630000 3192.000000 ;
+ RECT 2193.830000 3196.960000 2194.630000 3197.440000 ;
+ RECT 2193.830000 3202.400000 2194.630000 3202.880000 ;
+ RECT 2193.830000 3322.080000 2194.630000 3322.560000 ;
+ RECT 2717.290000 3175.200000 2718.090000 3175.680000 ;
+ RECT 2717.290000 3180.640000 2718.090000 3181.120000 ;
+ RECT 2717.290000 3186.080000 2718.090000 3186.560000 ;
+ RECT 2717.290000 3158.880000 2718.090000 3159.360000 ;
+ RECT 2717.290000 3164.320000 2718.090000 3164.800000 ;
+ RECT 2717.290000 3169.760000 2718.090000 3170.240000 ;
+ RECT 2717.290000 3142.560000 2718.090000 3143.040000 ;
+ RECT 2717.290000 3148.000000 2718.090000 3148.480000 ;
+ RECT 2717.290000 3153.440000 2718.090000 3153.920000 ;
+ RECT 2717.290000 3126.240000 2718.090000 3126.720000 ;
+ RECT 2717.290000 3131.680000 2718.090000 3132.160000 ;
+ RECT 2717.290000 3137.120000 2718.090000 3137.600000 ;
+ RECT 2717.290000 3120.800000 2718.090000 3121.280000 ;
+ RECT 2717.290000 3115.360000 2718.090000 3115.840000 ;
+ RECT 2717.290000 3109.920000 2718.090000 3110.400000 ;
+ RECT 2717.290000 3093.600000 2718.090000 3094.080000 ;
+ RECT 2717.290000 3099.040000 2718.090000 3099.520000 ;
+ RECT 2717.290000 3104.480000 2718.090000 3104.960000 ;
+ RECT 2717.290000 3077.280000 2718.090000 3077.760000 ;
+ RECT 2717.290000 3082.720000 2718.090000 3083.200000 ;
+ RECT 2717.290000 3088.160000 2718.090000 3088.640000 ;
+ RECT 2717.290000 3060.960000 2718.090000 3061.440000 ;
+ RECT 2717.290000 3066.400000 2718.090000 3066.880000 ;
+ RECT 2717.290000 3071.840000 2718.090000 3072.320000 ;
+ RECT 2717.290000 3044.640000 2718.090000 3045.120000 ;
+ RECT 2717.290000 3050.080000 2718.090000 3050.560000 ;
+ RECT 2717.290000 3055.520000 2718.090000 3056.000000 ;
+ RECT 2717.290000 3028.320000 2718.090000 3028.800000 ;
+ RECT 2717.290000 3033.760000 2718.090000 3034.240000 ;
+ RECT 2717.290000 3039.200000 2718.090000 3039.680000 ;
+ RECT 2717.290000 3012.000000 2718.090000 3012.480000 ;
+ RECT 2717.290000 3017.440000 2718.090000 3017.920000 ;
+ RECT 2717.290000 3022.880000 2718.090000 3023.360000 ;
+ RECT 2717.290000 2995.680000 2718.090000 2996.160000 ;
+ RECT 2717.290000 3001.120000 2718.090000 3001.600000 ;
+ RECT 2717.290000 3006.560000 2718.090000 3007.040000 ;
+ RECT 2717.290000 2990.240000 2718.090000 2990.720000 ;
+ RECT 2717.290000 2984.800000 2718.090000 2985.280000 ;
+ RECT 2193.830000 3186.080000 2194.630000 3186.560000 ;
+ RECT 2193.830000 3175.200000 2194.630000 3175.680000 ;
+ RECT 2193.830000 3180.640000 2194.630000 3181.120000 ;
+ RECT 2193.830000 3158.880000 2194.630000 3159.360000 ;
+ RECT 2193.830000 3164.320000 2194.630000 3164.800000 ;
+ RECT 2193.830000 3169.760000 2194.630000 3170.240000 ;
+ RECT 2193.830000 3142.560000 2194.630000 3143.040000 ;
+ RECT 2193.830000 3148.000000 2194.630000 3148.480000 ;
+ RECT 2193.830000 3153.440000 2194.630000 3153.920000 ;
+ RECT 2193.830000 3126.240000 2194.630000 3126.720000 ;
+ RECT 2193.830000 3131.680000 2194.630000 3132.160000 ;
+ RECT 2193.830000 3137.120000 2194.630000 3137.600000 ;
+ RECT 2193.830000 3120.800000 2194.630000 3121.280000 ;
+ RECT 2193.830000 3115.360000 2194.630000 3115.840000 ;
+ RECT 2193.830000 3109.920000 2194.630000 3110.400000 ;
+ RECT 2193.830000 3093.600000 2194.630000 3094.080000 ;
+ RECT 2193.830000 3099.040000 2194.630000 3099.520000 ;
+ RECT 2193.830000 3104.480000 2194.630000 3104.960000 ;
+ RECT 2193.830000 3082.720000 2194.630000 3083.200000 ;
+ RECT 2193.830000 3088.160000 2194.630000 3088.640000 ;
+ RECT 2193.830000 3077.280000 2194.630000 3077.760000 ;
+ RECT 2193.830000 3060.960000 2194.630000 3061.440000 ;
+ RECT 2193.830000 3066.400000 2194.630000 3066.880000 ;
+ RECT 2193.830000 3071.840000 2194.630000 3072.320000 ;
+ RECT 2193.830000 3044.640000 2194.630000 3045.120000 ;
+ RECT 2193.830000 3050.080000 2194.630000 3050.560000 ;
+ RECT 2193.830000 3055.520000 2194.630000 3056.000000 ;
+ RECT 2193.830000 3033.760000 2194.630000 3034.240000 ;
+ RECT 2193.830000 3039.200000 2194.630000 3039.680000 ;
+ RECT 2193.830000 3028.320000 2194.630000 3028.800000 ;
+ RECT 2193.830000 3012.000000 2194.630000 3012.480000 ;
+ RECT 2193.830000 3017.440000 2194.630000 3017.920000 ;
+ RECT 2193.830000 3022.880000 2194.630000 3023.360000 ;
+ RECT 2193.830000 3006.560000 2194.630000 3007.040000 ;
+ RECT 2193.830000 2995.680000 2194.630000 2996.160000 ;
+ RECT 2193.830000 3001.120000 2194.630000 3001.600000 ;
+ RECT 2193.830000 2984.800000 2194.630000 2985.280000 ;
+ RECT 2193.830000 2990.240000 2194.630000 2990.720000 ;
+ RECT 2193.830000 3395.510000 2720.920000 3396.310000 ;
+ RECT 2193.830000 2982.790000 2720.920000 2983.590000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 2979.940000 2194.630000 2980.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2193.830000 3399.380000 2194.630000 3400.180000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 2979.940000 2718.090000 2980.740000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2717.290000 3399.380000 2718.090000 3400.180000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 2982.790000 2720.920000 2983.590000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2720.120000 3395.510000 2720.920000 3396.310000 ;
+ END
+# end of P/G pin shape extracted from block 'BlockRAM_1KB'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1347.060000 163.950000 1547.320000 ;
+ RECT 236.330000 1347.060000 237.330000 1547.320000 ;
+ RECT 167.080000 1349.910000 168.180000 1543.280000 ;
+ RECT 212.080000 1349.910000 213.180000 1543.280000 ;
+ LAYER met3 ;
+ RECT 236.330000 1536.880000 237.330000 1537.360000 ;
+ RECT 236.330000 1526.000000 237.330000 1526.480000 ;
+ RECT 236.330000 1531.440000 237.330000 1531.920000 ;
+ RECT 212.080000 1536.880000 213.180000 1537.360000 ;
+ RECT 212.080000 1531.440000 213.180000 1531.920000 ;
+ RECT 212.080000 1526.000000 213.180000 1526.480000 ;
+ RECT 236.330000 1515.120000 237.330000 1515.600000 ;
+ RECT 236.330000 1520.560000 237.330000 1521.040000 ;
+ RECT 236.330000 1498.800000 237.330000 1499.280000 ;
+ RECT 236.330000 1504.240000 237.330000 1504.720000 ;
+ RECT 236.330000 1509.680000 237.330000 1510.160000 ;
+ RECT 212.080000 1520.560000 213.180000 1521.040000 ;
+ RECT 212.080000 1515.120000 213.180000 1515.600000 ;
+ RECT 212.080000 1509.680000 213.180000 1510.160000 ;
+ RECT 212.080000 1504.240000 213.180000 1504.720000 ;
+ RECT 212.080000 1498.800000 213.180000 1499.280000 ;
+ RECT 236.330000 1487.920000 237.330000 1488.400000 ;
+ RECT 236.330000 1493.360000 237.330000 1493.840000 ;
+ RECT 236.330000 1477.040000 237.330000 1477.520000 ;
+ RECT 236.330000 1482.480000 237.330000 1482.960000 ;
+ RECT 212.080000 1477.040000 213.180000 1477.520000 ;
+ RECT 212.080000 1482.480000 213.180000 1482.960000 ;
+ RECT 212.080000 1487.920000 213.180000 1488.400000 ;
+ RECT 212.080000 1493.360000 213.180000 1493.840000 ;
+ RECT 236.330000 1460.720000 237.330000 1461.200000 ;
+ RECT 236.330000 1466.160000 237.330000 1466.640000 ;
+ RECT 236.330000 1471.600000 237.330000 1472.080000 ;
+ RECT 236.330000 1449.840000 237.330000 1450.320000 ;
+ RECT 236.330000 1455.280000 237.330000 1455.760000 ;
+ RECT 212.080000 1460.720000 213.180000 1461.200000 ;
+ RECT 212.080000 1455.280000 213.180000 1455.760000 ;
+ RECT 212.080000 1449.840000 213.180000 1450.320000 ;
+ RECT 212.080000 1466.160000 213.180000 1466.640000 ;
+ RECT 212.080000 1471.600000 213.180000 1472.080000 ;
+ RECT 167.080000 1536.880000 168.180000 1537.360000 ;
+ RECT 162.950000 1536.880000 163.950000 1537.360000 ;
+ RECT 162.950000 1526.000000 163.950000 1526.480000 ;
+ RECT 167.080000 1531.440000 168.180000 1531.920000 ;
+ RECT 167.080000 1526.000000 168.180000 1526.480000 ;
+ RECT 162.950000 1531.440000 163.950000 1531.920000 ;
+ RECT 162.950000 1515.120000 163.950000 1515.600000 ;
+ RECT 162.950000 1520.560000 163.950000 1521.040000 ;
+ RECT 167.080000 1520.560000 168.180000 1521.040000 ;
+ RECT 167.080000 1515.120000 168.180000 1515.600000 ;
+ RECT 162.950000 1498.800000 163.950000 1499.280000 ;
+ RECT 162.950000 1504.240000 163.950000 1504.720000 ;
+ RECT 167.080000 1504.240000 168.180000 1504.720000 ;
+ RECT 167.080000 1498.800000 168.180000 1499.280000 ;
+ RECT 167.080000 1509.680000 168.180000 1510.160000 ;
+ RECT 162.950000 1509.680000 163.950000 1510.160000 ;
+ RECT 162.950000 1487.920000 163.950000 1488.400000 ;
+ RECT 162.950000 1493.360000 163.950000 1493.840000 ;
+ RECT 167.080000 1487.920000 168.180000 1488.400000 ;
+ RECT 167.080000 1493.360000 168.180000 1493.840000 ;
+ RECT 162.950000 1477.040000 163.950000 1477.520000 ;
+ RECT 162.950000 1482.480000 163.950000 1482.960000 ;
+ RECT 167.080000 1477.040000 168.180000 1477.520000 ;
+ RECT 167.080000 1482.480000 168.180000 1482.960000 ;
+ RECT 167.080000 1471.600000 168.180000 1472.080000 ;
+ RECT 167.080000 1466.160000 168.180000 1466.640000 ;
+ RECT 162.950000 1471.600000 163.950000 1472.080000 ;
+ RECT 162.950000 1466.160000 163.950000 1466.640000 ;
+ RECT 167.080000 1460.720000 168.180000 1461.200000 ;
+ RECT 162.950000 1460.720000 163.950000 1461.200000 ;
+ RECT 162.950000 1449.840000 163.950000 1450.320000 ;
+ RECT 162.950000 1455.280000 163.950000 1455.760000 ;
+ RECT 167.080000 1455.280000 168.180000 1455.760000 ;
+ RECT 167.080000 1449.840000 168.180000 1450.320000 ;
+ RECT 236.330000 1438.960000 237.330000 1439.440000 ;
+ RECT 236.330000 1444.400000 237.330000 1444.880000 ;
+ RECT 236.330000 1422.640000 237.330000 1423.120000 ;
+ RECT 236.330000 1428.080000 237.330000 1428.560000 ;
+ RECT 236.330000 1433.520000 237.330000 1434.000000 ;
+ RECT 212.080000 1444.400000 213.180000 1444.880000 ;
+ RECT 212.080000 1438.960000 213.180000 1439.440000 ;
+ RECT 212.080000 1433.520000 213.180000 1434.000000 ;
+ RECT 212.080000 1428.080000 213.180000 1428.560000 ;
+ RECT 212.080000 1422.640000 213.180000 1423.120000 ;
+ RECT 236.330000 1411.760000 237.330000 1412.240000 ;
+ RECT 236.330000 1417.200000 237.330000 1417.680000 ;
+ RECT 236.330000 1400.880000 237.330000 1401.360000 ;
+ RECT 236.330000 1406.320000 237.330000 1406.800000 ;
+ RECT 212.080000 1417.200000 213.180000 1417.680000 ;
+ RECT 212.080000 1411.760000 213.180000 1412.240000 ;
+ RECT 212.080000 1406.320000 213.180000 1406.800000 ;
+ RECT 212.080000 1400.880000 213.180000 1401.360000 ;
+ RECT 236.330000 1390.000000 237.330000 1390.480000 ;
+ RECT 236.330000 1395.440000 237.330000 1395.920000 ;
+ RECT 236.330000 1373.680000 237.330000 1374.160000 ;
+ RECT 236.330000 1379.120000 237.330000 1379.600000 ;
+ RECT 236.330000 1384.560000 237.330000 1385.040000 ;
+ RECT 212.080000 1373.680000 213.180000 1374.160000 ;
+ RECT 212.080000 1379.120000 213.180000 1379.600000 ;
+ RECT 212.080000 1384.560000 213.180000 1385.040000 ;
+ RECT 212.080000 1390.000000 213.180000 1390.480000 ;
+ RECT 212.080000 1395.440000 213.180000 1395.920000 ;
+ RECT 236.330000 1362.800000 237.330000 1363.280000 ;
+ RECT 236.330000 1368.240000 237.330000 1368.720000 ;
+ RECT 236.330000 1351.920000 237.330000 1352.400000 ;
+ RECT 236.330000 1357.360000 237.330000 1357.840000 ;
+ RECT 212.080000 1362.800000 213.180000 1363.280000 ;
+ RECT 212.080000 1357.360000 213.180000 1357.840000 ;
+ RECT 212.080000 1351.920000 213.180000 1352.400000 ;
+ RECT 212.080000 1368.240000 213.180000 1368.720000 ;
+ RECT 162.950000 1438.960000 163.950000 1439.440000 ;
+ RECT 162.950000 1444.400000 163.950000 1444.880000 ;
+ RECT 167.080000 1444.400000 168.180000 1444.880000 ;
+ RECT 167.080000 1438.960000 168.180000 1439.440000 ;
+ RECT 167.080000 1433.520000 168.180000 1434.000000 ;
+ RECT 162.950000 1433.520000 163.950000 1434.000000 ;
+ RECT 167.080000 1422.640000 168.180000 1423.120000 ;
+ RECT 162.950000 1422.640000 163.950000 1423.120000 ;
+ RECT 162.950000 1428.080000 163.950000 1428.560000 ;
+ RECT 167.080000 1428.080000 168.180000 1428.560000 ;
+ RECT 162.950000 1411.760000 163.950000 1412.240000 ;
+ RECT 162.950000 1417.200000 163.950000 1417.680000 ;
+ RECT 167.080000 1417.200000 168.180000 1417.680000 ;
+ RECT 167.080000 1411.760000 168.180000 1412.240000 ;
+ RECT 162.950000 1400.880000 163.950000 1401.360000 ;
+ RECT 162.950000 1406.320000 163.950000 1406.800000 ;
+ RECT 167.080000 1406.320000 168.180000 1406.800000 ;
+ RECT 167.080000 1400.880000 168.180000 1401.360000 ;
+ RECT 162.950000 1390.000000 163.950000 1390.480000 ;
+ RECT 162.950000 1395.440000 163.950000 1395.920000 ;
+ RECT 167.080000 1390.000000 168.180000 1390.480000 ;
+ RECT 167.080000 1395.440000 168.180000 1395.920000 ;
+ RECT 162.950000 1373.680000 163.950000 1374.160000 ;
+ RECT 162.950000 1379.120000 163.950000 1379.600000 ;
+ RECT 167.080000 1373.680000 168.180000 1374.160000 ;
+ RECT 167.080000 1379.120000 168.180000 1379.600000 ;
+ RECT 167.080000 1384.560000 168.180000 1385.040000 ;
+ RECT 162.950000 1384.560000 163.950000 1385.040000 ;
+ RECT 162.950000 1362.800000 163.950000 1363.280000 ;
+ RECT 162.950000 1368.240000 163.950000 1368.720000 ;
+ RECT 167.080000 1362.800000 168.180000 1363.280000 ;
+ RECT 167.080000 1368.240000 168.180000 1368.720000 ;
+ RECT 167.080000 1351.920000 168.180000 1352.400000 ;
+ RECT 167.080000 1357.360000 168.180000 1357.840000 ;
+ RECT 162.950000 1357.360000 163.950000 1357.840000 ;
+ RECT 162.950000 1351.920000 163.950000 1352.400000 ;
+ RECT 160.120000 1542.280000 240.160000 1543.280000 ;
+ RECT 160.120000 1349.910000 240.160000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1347.060000 163.950000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1546.320000 163.950000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 1347.060000 237.330000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 1546.320000 237.330000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1349.910000 161.120000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1349.910000 240.160000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1542.280000 161.120000 1543.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1542.280000 240.160000 1543.280000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1146.800000 163.950000 1347.060000 ;
+ RECT 236.330000 1146.800000 237.330000 1347.060000 ;
+ RECT 167.080000 1149.650000 168.180000 1343.020000 ;
+ RECT 212.080000 1149.650000 213.180000 1343.020000 ;
+ LAYER met3 ;
+ RECT 236.330000 1336.620000 237.330000 1337.100000 ;
+ RECT 236.330000 1325.740000 237.330000 1326.220000 ;
+ RECT 236.330000 1331.180000 237.330000 1331.660000 ;
+ RECT 212.080000 1336.620000 213.180000 1337.100000 ;
+ RECT 212.080000 1331.180000 213.180000 1331.660000 ;
+ RECT 212.080000 1325.740000 213.180000 1326.220000 ;
+ RECT 236.330000 1314.860000 237.330000 1315.340000 ;
+ RECT 236.330000 1320.300000 237.330000 1320.780000 ;
+ RECT 236.330000 1298.540000 237.330000 1299.020000 ;
+ RECT 236.330000 1303.980000 237.330000 1304.460000 ;
+ RECT 236.330000 1309.420000 237.330000 1309.900000 ;
+ RECT 212.080000 1320.300000 213.180000 1320.780000 ;
+ RECT 212.080000 1314.860000 213.180000 1315.340000 ;
+ RECT 212.080000 1309.420000 213.180000 1309.900000 ;
+ RECT 212.080000 1303.980000 213.180000 1304.460000 ;
+ RECT 212.080000 1298.540000 213.180000 1299.020000 ;
+ RECT 236.330000 1287.660000 237.330000 1288.140000 ;
+ RECT 236.330000 1293.100000 237.330000 1293.580000 ;
+ RECT 236.330000 1276.780000 237.330000 1277.260000 ;
+ RECT 236.330000 1282.220000 237.330000 1282.700000 ;
+ RECT 212.080000 1276.780000 213.180000 1277.260000 ;
+ RECT 212.080000 1282.220000 213.180000 1282.700000 ;
+ RECT 212.080000 1287.660000 213.180000 1288.140000 ;
+ RECT 212.080000 1293.100000 213.180000 1293.580000 ;
+ RECT 236.330000 1260.460000 237.330000 1260.940000 ;
+ RECT 236.330000 1265.900000 237.330000 1266.380000 ;
+ RECT 236.330000 1271.340000 237.330000 1271.820000 ;
+ RECT 236.330000 1249.580000 237.330000 1250.060000 ;
+ RECT 236.330000 1255.020000 237.330000 1255.500000 ;
+ RECT 212.080000 1260.460000 213.180000 1260.940000 ;
+ RECT 212.080000 1255.020000 213.180000 1255.500000 ;
+ RECT 212.080000 1249.580000 213.180000 1250.060000 ;
+ RECT 212.080000 1265.900000 213.180000 1266.380000 ;
+ RECT 212.080000 1271.340000 213.180000 1271.820000 ;
+ RECT 167.080000 1336.620000 168.180000 1337.100000 ;
+ RECT 162.950000 1336.620000 163.950000 1337.100000 ;
+ RECT 162.950000 1325.740000 163.950000 1326.220000 ;
+ RECT 167.080000 1331.180000 168.180000 1331.660000 ;
+ RECT 167.080000 1325.740000 168.180000 1326.220000 ;
+ RECT 162.950000 1331.180000 163.950000 1331.660000 ;
+ RECT 162.950000 1314.860000 163.950000 1315.340000 ;
+ RECT 162.950000 1320.300000 163.950000 1320.780000 ;
+ RECT 167.080000 1320.300000 168.180000 1320.780000 ;
+ RECT 167.080000 1314.860000 168.180000 1315.340000 ;
+ RECT 162.950000 1298.540000 163.950000 1299.020000 ;
+ RECT 162.950000 1303.980000 163.950000 1304.460000 ;
+ RECT 167.080000 1303.980000 168.180000 1304.460000 ;
+ RECT 167.080000 1298.540000 168.180000 1299.020000 ;
+ RECT 167.080000 1309.420000 168.180000 1309.900000 ;
+ RECT 162.950000 1309.420000 163.950000 1309.900000 ;
+ RECT 162.950000 1287.660000 163.950000 1288.140000 ;
+ RECT 162.950000 1293.100000 163.950000 1293.580000 ;
+ RECT 167.080000 1287.660000 168.180000 1288.140000 ;
+ RECT 167.080000 1293.100000 168.180000 1293.580000 ;
+ RECT 162.950000 1276.780000 163.950000 1277.260000 ;
+ RECT 162.950000 1282.220000 163.950000 1282.700000 ;
+ RECT 167.080000 1276.780000 168.180000 1277.260000 ;
+ RECT 167.080000 1282.220000 168.180000 1282.700000 ;
+ RECT 167.080000 1271.340000 168.180000 1271.820000 ;
+ RECT 167.080000 1265.900000 168.180000 1266.380000 ;
+ RECT 162.950000 1271.340000 163.950000 1271.820000 ;
+ RECT 162.950000 1265.900000 163.950000 1266.380000 ;
+ RECT 167.080000 1260.460000 168.180000 1260.940000 ;
+ RECT 162.950000 1260.460000 163.950000 1260.940000 ;
+ RECT 162.950000 1249.580000 163.950000 1250.060000 ;
+ RECT 162.950000 1255.020000 163.950000 1255.500000 ;
+ RECT 167.080000 1255.020000 168.180000 1255.500000 ;
+ RECT 167.080000 1249.580000 168.180000 1250.060000 ;
+ RECT 236.330000 1238.700000 237.330000 1239.180000 ;
+ RECT 236.330000 1244.140000 237.330000 1244.620000 ;
+ RECT 236.330000 1222.380000 237.330000 1222.860000 ;
+ RECT 236.330000 1227.820000 237.330000 1228.300000 ;
+ RECT 236.330000 1233.260000 237.330000 1233.740000 ;
+ RECT 212.080000 1244.140000 213.180000 1244.620000 ;
+ RECT 212.080000 1238.700000 213.180000 1239.180000 ;
+ RECT 212.080000 1233.260000 213.180000 1233.740000 ;
+ RECT 212.080000 1227.820000 213.180000 1228.300000 ;
+ RECT 212.080000 1222.380000 213.180000 1222.860000 ;
+ RECT 236.330000 1211.500000 237.330000 1211.980000 ;
+ RECT 236.330000 1216.940000 237.330000 1217.420000 ;
+ RECT 236.330000 1200.620000 237.330000 1201.100000 ;
+ RECT 236.330000 1206.060000 237.330000 1206.540000 ;
+ RECT 212.080000 1216.940000 213.180000 1217.420000 ;
+ RECT 212.080000 1211.500000 213.180000 1211.980000 ;
+ RECT 212.080000 1206.060000 213.180000 1206.540000 ;
+ RECT 212.080000 1200.620000 213.180000 1201.100000 ;
+ RECT 236.330000 1189.740000 237.330000 1190.220000 ;
+ RECT 236.330000 1195.180000 237.330000 1195.660000 ;
+ RECT 236.330000 1173.420000 237.330000 1173.900000 ;
+ RECT 236.330000 1178.860000 237.330000 1179.340000 ;
+ RECT 236.330000 1184.300000 237.330000 1184.780000 ;
+ RECT 212.080000 1173.420000 213.180000 1173.900000 ;
+ RECT 212.080000 1178.860000 213.180000 1179.340000 ;
+ RECT 212.080000 1184.300000 213.180000 1184.780000 ;
+ RECT 212.080000 1189.740000 213.180000 1190.220000 ;
+ RECT 212.080000 1195.180000 213.180000 1195.660000 ;
+ RECT 236.330000 1162.540000 237.330000 1163.020000 ;
+ RECT 236.330000 1167.980000 237.330000 1168.460000 ;
+ RECT 236.330000 1151.660000 237.330000 1152.140000 ;
+ RECT 236.330000 1157.100000 237.330000 1157.580000 ;
+ RECT 212.080000 1162.540000 213.180000 1163.020000 ;
+ RECT 212.080000 1157.100000 213.180000 1157.580000 ;
+ RECT 212.080000 1151.660000 213.180000 1152.140000 ;
+ RECT 212.080000 1167.980000 213.180000 1168.460000 ;
+ RECT 162.950000 1238.700000 163.950000 1239.180000 ;
+ RECT 162.950000 1244.140000 163.950000 1244.620000 ;
+ RECT 167.080000 1244.140000 168.180000 1244.620000 ;
+ RECT 167.080000 1238.700000 168.180000 1239.180000 ;
+ RECT 167.080000 1233.260000 168.180000 1233.740000 ;
+ RECT 162.950000 1233.260000 163.950000 1233.740000 ;
+ RECT 167.080000 1222.380000 168.180000 1222.860000 ;
+ RECT 162.950000 1222.380000 163.950000 1222.860000 ;
+ RECT 162.950000 1227.820000 163.950000 1228.300000 ;
+ RECT 167.080000 1227.820000 168.180000 1228.300000 ;
+ RECT 162.950000 1211.500000 163.950000 1211.980000 ;
+ RECT 162.950000 1216.940000 163.950000 1217.420000 ;
+ RECT 167.080000 1216.940000 168.180000 1217.420000 ;
+ RECT 167.080000 1211.500000 168.180000 1211.980000 ;
+ RECT 162.950000 1200.620000 163.950000 1201.100000 ;
+ RECT 162.950000 1206.060000 163.950000 1206.540000 ;
+ RECT 167.080000 1206.060000 168.180000 1206.540000 ;
+ RECT 167.080000 1200.620000 168.180000 1201.100000 ;
+ RECT 162.950000 1189.740000 163.950000 1190.220000 ;
+ RECT 162.950000 1195.180000 163.950000 1195.660000 ;
+ RECT 167.080000 1189.740000 168.180000 1190.220000 ;
+ RECT 167.080000 1195.180000 168.180000 1195.660000 ;
+ RECT 162.950000 1173.420000 163.950000 1173.900000 ;
+ RECT 162.950000 1178.860000 163.950000 1179.340000 ;
+ RECT 167.080000 1173.420000 168.180000 1173.900000 ;
+ RECT 167.080000 1178.860000 168.180000 1179.340000 ;
+ RECT 167.080000 1184.300000 168.180000 1184.780000 ;
+ RECT 162.950000 1184.300000 163.950000 1184.780000 ;
+ RECT 162.950000 1162.540000 163.950000 1163.020000 ;
+ RECT 162.950000 1167.980000 163.950000 1168.460000 ;
+ RECT 167.080000 1162.540000 168.180000 1163.020000 ;
+ RECT 167.080000 1167.980000 168.180000 1168.460000 ;
+ RECT 167.080000 1151.660000 168.180000 1152.140000 ;
+ RECT 167.080000 1157.100000 168.180000 1157.580000 ;
+ RECT 162.950000 1157.100000 163.950000 1157.580000 ;
+ RECT 162.950000 1151.660000 163.950000 1152.140000 ;
+ RECT 160.120000 1342.020000 240.160000 1343.020000 ;
+ RECT 160.120000 1149.650000 240.160000 1150.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1146.800000 163.950000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1346.060000 163.950000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 1146.800000 237.330000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 1346.060000 237.330000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1149.650000 161.120000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1149.650000 240.160000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1342.020000 161.120000 1343.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1342.020000 240.160000 1343.020000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 946.540000 163.950000 1146.800000 ;
+ RECT 236.330000 946.540000 237.330000 1146.800000 ;
+ RECT 167.080000 949.390000 168.180000 1142.760000 ;
+ RECT 212.080000 949.390000 213.180000 1142.760000 ;
+ LAYER met3 ;
+ RECT 236.330000 1136.360000 237.330000 1136.840000 ;
+ RECT 236.330000 1125.480000 237.330000 1125.960000 ;
+ RECT 236.330000 1130.920000 237.330000 1131.400000 ;
+ RECT 212.080000 1136.360000 213.180000 1136.840000 ;
+ RECT 212.080000 1130.920000 213.180000 1131.400000 ;
+ RECT 212.080000 1125.480000 213.180000 1125.960000 ;
+ RECT 236.330000 1114.600000 237.330000 1115.080000 ;
+ RECT 236.330000 1120.040000 237.330000 1120.520000 ;
+ RECT 236.330000 1098.280000 237.330000 1098.760000 ;
+ RECT 236.330000 1103.720000 237.330000 1104.200000 ;
+ RECT 236.330000 1109.160000 237.330000 1109.640000 ;
+ RECT 212.080000 1120.040000 213.180000 1120.520000 ;
+ RECT 212.080000 1114.600000 213.180000 1115.080000 ;
+ RECT 212.080000 1109.160000 213.180000 1109.640000 ;
+ RECT 212.080000 1103.720000 213.180000 1104.200000 ;
+ RECT 212.080000 1098.280000 213.180000 1098.760000 ;
+ RECT 236.330000 1087.400000 237.330000 1087.880000 ;
+ RECT 236.330000 1092.840000 237.330000 1093.320000 ;
+ RECT 236.330000 1076.520000 237.330000 1077.000000 ;
+ RECT 236.330000 1081.960000 237.330000 1082.440000 ;
+ RECT 212.080000 1076.520000 213.180000 1077.000000 ;
+ RECT 212.080000 1081.960000 213.180000 1082.440000 ;
+ RECT 212.080000 1087.400000 213.180000 1087.880000 ;
+ RECT 212.080000 1092.840000 213.180000 1093.320000 ;
+ RECT 236.330000 1060.200000 237.330000 1060.680000 ;
+ RECT 236.330000 1065.640000 237.330000 1066.120000 ;
+ RECT 236.330000 1071.080000 237.330000 1071.560000 ;
+ RECT 236.330000 1049.320000 237.330000 1049.800000 ;
+ RECT 236.330000 1054.760000 237.330000 1055.240000 ;
+ RECT 212.080000 1060.200000 213.180000 1060.680000 ;
+ RECT 212.080000 1054.760000 213.180000 1055.240000 ;
+ RECT 212.080000 1049.320000 213.180000 1049.800000 ;
+ RECT 212.080000 1065.640000 213.180000 1066.120000 ;
+ RECT 212.080000 1071.080000 213.180000 1071.560000 ;
+ RECT 167.080000 1136.360000 168.180000 1136.840000 ;
+ RECT 162.950000 1136.360000 163.950000 1136.840000 ;
+ RECT 162.950000 1125.480000 163.950000 1125.960000 ;
+ RECT 167.080000 1130.920000 168.180000 1131.400000 ;
+ RECT 167.080000 1125.480000 168.180000 1125.960000 ;
+ RECT 162.950000 1130.920000 163.950000 1131.400000 ;
+ RECT 162.950000 1114.600000 163.950000 1115.080000 ;
+ RECT 162.950000 1120.040000 163.950000 1120.520000 ;
+ RECT 167.080000 1120.040000 168.180000 1120.520000 ;
+ RECT 167.080000 1114.600000 168.180000 1115.080000 ;
+ RECT 162.950000 1098.280000 163.950000 1098.760000 ;
+ RECT 162.950000 1103.720000 163.950000 1104.200000 ;
+ RECT 167.080000 1103.720000 168.180000 1104.200000 ;
+ RECT 167.080000 1098.280000 168.180000 1098.760000 ;
+ RECT 167.080000 1109.160000 168.180000 1109.640000 ;
+ RECT 162.950000 1109.160000 163.950000 1109.640000 ;
+ RECT 162.950000 1087.400000 163.950000 1087.880000 ;
+ RECT 162.950000 1092.840000 163.950000 1093.320000 ;
+ RECT 167.080000 1087.400000 168.180000 1087.880000 ;
+ RECT 167.080000 1092.840000 168.180000 1093.320000 ;
+ RECT 162.950000 1076.520000 163.950000 1077.000000 ;
+ RECT 162.950000 1081.960000 163.950000 1082.440000 ;
+ RECT 167.080000 1076.520000 168.180000 1077.000000 ;
+ RECT 167.080000 1081.960000 168.180000 1082.440000 ;
+ RECT 167.080000 1071.080000 168.180000 1071.560000 ;
+ RECT 167.080000 1065.640000 168.180000 1066.120000 ;
+ RECT 162.950000 1071.080000 163.950000 1071.560000 ;
+ RECT 162.950000 1065.640000 163.950000 1066.120000 ;
+ RECT 167.080000 1060.200000 168.180000 1060.680000 ;
+ RECT 162.950000 1060.200000 163.950000 1060.680000 ;
+ RECT 162.950000 1049.320000 163.950000 1049.800000 ;
+ RECT 162.950000 1054.760000 163.950000 1055.240000 ;
+ RECT 167.080000 1054.760000 168.180000 1055.240000 ;
+ RECT 167.080000 1049.320000 168.180000 1049.800000 ;
+ RECT 236.330000 1038.440000 237.330000 1038.920000 ;
+ RECT 236.330000 1043.880000 237.330000 1044.360000 ;
+ RECT 236.330000 1022.120000 237.330000 1022.600000 ;
+ RECT 236.330000 1027.560000 237.330000 1028.040000 ;
+ RECT 236.330000 1033.000000 237.330000 1033.480000 ;
+ RECT 212.080000 1043.880000 213.180000 1044.360000 ;
+ RECT 212.080000 1038.440000 213.180000 1038.920000 ;
+ RECT 212.080000 1033.000000 213.180000 1033.480000 ;
+ RECT 212.080000 1027.560000 213.180000 1028.040000 ;
+ RECT 212.080000 1022.120000 213.180000 1022.600000 ;
+ RECT 236.330000 1011.240000 237.330000 1011.720000 ;
+ RECT 236.330000 1016.680000 237.330000 1017.160000 ;
+ RECT 236.330000 1000.360000 237.330000 1000.840000 ;
+ RECT 236.330000 1005.800000 237.330000 1006.280000 ;
+ RECT 212.080000 1016.680000 213.180000 1017.160000 ;
+ RECT 212.080000 1011.240000 213.180000 1011.720000 ;
+ RECT 212.080000 1005.800000 213.180000 1006.280000 ;
+ RECT 212.080000 1000.360000 213.180000 1000.840000 ;
+ RECT 236.330000 989.480000 237.330000 989.960000 ;
+ RECT 236.330000 994.920000 237.330000 995.400000 ;
+ RECT 236.330000 973.160000 237.330000 973.640000 ;
+ RECT 236.330000 978.600000 237.330000 979.080000 ;
+ RECT 236.330000 984.040000 237.330000 984.520000 ;
+ RECT 212.080000 973.160000 213.180000 973.640000 ;
+ RECT 212.080000 978.600000 213.180000 979.080000 ;
+ RECT 212.080000 984.040000 213.180000 984.520000 ;
+ RECT 212.080000 989.480000 213.180000 989.960000 ;
+ RECT 212.080000 994.920000 213.180000 995.400000 ;
+ RECT 236.330000 962.280000 237.330000 962.760000 ;
+ RECT 236.330000 967.720000 237.330000 968.200000 ;
+ RECT 236.330000 951.400000 237.330000 951.880000 ;
+ RECT 236.330000 956.840000 237.330000 957.320000 ;
+ RECT 212.080000 962.280000 213.180000 962.760000 ;
+ RECT 212.080000 956.840000 213.180000 957.320000 ;
+ RECT 212.080000 951.400000 213.180000 951.880000 ;
+ RECT 212.080000 967.720000 213.180000 968.200000 ;
+ RECT 162.950000 1038.440000 163.950000 1038.920000 ;
+ RECT 162.950000 1043.880000 163.950000 1044.360000 ;
+ RECT 167.080000 1043.880000 168.180000 1044.360000 ;
+ RECT 167.080000 1038.440000 168.180000 1038.920000 ;
+ RECT 167.080000 1033.000000 168.180000 1033.480000 ;
+ RECT 162.950000 1033.000000 163.950000 1033.480000 ;
+ RECT 167.080000 1022.120000 168.180000 1022.600000 ;
+ RECT 162.950000 1022.120000 163.950000 1022.600000 ;
+ RECT 162.950000 1027.560000 163.950000 1028.040000 ;
+ RECT 167.080000 1027.560000 168.180000 1028.040000 ;
+ RECT 162.950000 1011.240000 163.950000 1011.720000 ;
+ RECT 162.950000 1016.680000 163.950000 1017.160000 ;
+ RECT 167.080000 1016.680000 168.180000 1017.160000 ;
+ RECT 167.080000 1011.240000 168.180000 1011.720000 ;
+ RECT 162.950000 1000.360000 163.950000 1000.840000 ;
+ RECT 162.950000 1005.800000 163.950000 1006.280000 ;
+ RECT 167.080000 1005.800000 168.180000 1006.280000 ;
+ RECT 167.080000 1000.360000 168.180000 1000.840000 ;
+ RECT 162.950000 989.480000 163.950000 989.960000 ;
+ RECT 162.950000 994.920000 163.950000 995.400000 ;
+ RECT 167.080000 989.480000 168.180000 989.960000 ;
+ RECT 167.080000 994.920000 168.180000 995.400000 ;
+ RECT 162.950000 973.160000 163.950000 973.640000 ;
+ RECT 162.950000 978.600000 163.950000 979.080000 ;
+ RECT 167.080000 973.160000 168.180000 973.640000 ;
+ RECT 167.080000 978.600000 168.180000 979.080000 ;
+ RECT 167.080000 984.040000 168.180000 984.520000 ;
+ RECT 162.950000 984.040000 163.950000 984.520000 ;
+ RECT 162.950000 962.280000 163.950000 962.760000 ;
+ RECT 162.950000 967.720000 163.950000 968.200000 ;
+ RECT 167.080000 962.280000 168.180000 962.760000 ;
+ RECT 167.080000 967.720000 168.180000 968.200000 ;
+ RECT 167.080000 951.400000 168.180000 951.880000 ;
+ RECT 167.080000 956.840000 168.180000 957.320000 ;
+ RECT 162.950000 956.840000 163.950000 957.320000 ;
+ RECT 162.950000 951.400000 163.950000 951.880000 ;
+ RECT 160.120000 1141.760000 240.160000 1142.760000 ;
+ RECT 160.120000 949.390000 240.160000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 946.540000 163.950000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1145.800000 163.950000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 946.540000 237.330000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 1145.800000 237.330000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 949.390000 161.120000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 949.390000 240.160000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1141.760000 161.120000 1142.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1141.760000 240.160000 1142.760000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 746.280000 163.950000 946.540000 ;
+ RECT 236.330000 746.280000 237.330000 946.540000 ;
+ RECT 167.080000 749.130000 168.180000 942.500000 ;
+ RECT 212.080000 749.130000 213.180000 942.500000 ;
+ LAYER met3 ;
+ RECT 236.330000 936.100000 237.330000 936.580000 ;
+ RECT 236.330000 925.220000 237.330000 925.700000 ;
+ RECT 236.330000 930.660000 237.330000 931.140000 ;
+ RECT 212.080000 936.100000 213.180000 936.580000 ;
+ RECT 212.080000 930.660000 213.180000 931.140000 ;
+ RECT 212.080000 925.220000 213.180000 925.700000 ;
+ RECT 236.330000 914.340000 237.330000 914.820000 ;
+ RECT 236.330000 919.780000 237.330000 920.260000 ;
+ RECT 236.330000 898.020000 237.330000 898.500000 ;
+ RECT 236.330000 903.460000 237.330000 903.940000 ;
+ RECT 236.330000 908.900000 237.330000 909.380000 ;
+ RECT 212.080000 919.780000 213.180000 920.260000 ;
+ RECT 212.080000 914.340000 213.180000 914.820000 ;
+ RECT 212.080000 908.900000 213.180000 909.380000 ;
+ RECT 212.080000 903.460000 213.180000 903.940000 ;
+ RECT 212.080000 898.020000 213.180000 898.500000 ;
+ RECT 236.330000 887.140000 237.330000 887.620000 ;
+ RECT 236.330000 892.580000 237.330000 893.060000 ;
+ RECT 236.330000 876.260000 237.330000 876.740000 ;
+ RECT 236.330000 881.700000 237.330000 882.180000 ;
+ RECT 212.080000 876.260000 213.180000 876.740000 ;
+ RECT 212.080000 881.700000 213.180000 882.180000 ;
+ RECT 212.080000 887.140000 213.180000 887.620000 ;
+ RECT 212.080000 892.580000 213.180000 893.060000 ;
+ RECT 236.330000 859.940000 237.330000 860.420000 ;
+ RECT 236.330000 865.380000 237.330000 865.860000 ;
+ RECT 236.330000 870.820000 237.330000 871.300000 ;
+ RECT 236.330000 849.060000 237.330000 849.540000 ;
+ RECT 236.330000 854.500000 237.330000 854.980000 ;
+ RECT 212.080000 859.940000 213.180000 860.420000 ;
+ RECT 212.080000 854.500000 213.180000 854.980000 ;
+ RECT 212.080000 849.060000 213.180000 849.540000 ;
+ RECT 212.080000 865.380000 213.180000 865.860000 ;
+ RECT 212.080000 870.820000 213.180000 871.300000 ;
+ RECT 167.080000 936.100000 168.180000 936.580000 ;
+ RECT 162.950000 936.100000 163.950000 936.580000 ;
+ RECT 162.950000 925.220000 163.950000 925.700000 ;
+ RECT 167.080000 930.660000 168.180000 931.140000 ;
+ RECT 167.080000 925.220000 168.180000 925.700000 ;
+ RECT 162.950000 930.660000 163.950000 931.140000 ;
+ RECT 162.950000 914.340000 163.950000 914.820000 ;
+ RECT 162.950000 919.780000 163.950000 920.260000 ;
+ RECT 167.080000 919.780000 168.180000 920.260000 ;
+ RECT 167.080000 914.340000 168.180000 914.820000 ;
+ RECT 162.950000 898.020000 163.950000 898.500000 ;
+ RECT 162.950000 903.460000 163.950000 903.940000 ;
+ RECT 167.080000 903.460000 168.180000 903.940000 ;
+ RECT 167.080000 898.020000 168.180000 898.500000 ;
+ RECT 167.080000 908.900000 168.180000 909.380000 ;
+ RECT 162.950000 908.900000 163.950000 909.380000 ;
+ RECT 162.950000 887.140000 163.950000 887.620000 ;
+ RECT 162.950000 892.580000 163.950000 893.060000 ;
+ RECT 167.080000 887.140000 168.180000 887.620000 ;
+ RECT 167.080000 892.580000 168.180000 893.060000 ;
+ RECT 162.950000 876.260000 163.950000 876.740000 ;
+ RECT 162.950000 881.700000 163.950000 882.180000 ;
+ RECT 167.080000 876.260000 168.180000 876.740000 ;
+ RECT 167.080000 881.700000 168.180000 882.180000 ;
+ RECT 167.080000 870.820000 168.180000 871.300000 ;
+ RECT 167.080000 865.380000 168.180000 865.860000 ;
+ RECT 162.950000 870.820000 163.950000 871.300000 ;
+ RECT 162.950000 865.380000 163.950000 865.860000 ;
+ RECT 167.080000 859.940000 168.180000 860.420000 ;
+ RECT 162.950000 859.940000 163.950000 860.420000 ;
+ RECT 162.950000 849.060000 163.950000 849.540000 ;
+ RECT 162.950000 854.500000 163.950000 854.980000 ;
+ RECT 167.080000 854.500000 168.180000 854.980000 ;
+ RECT 167.080000 849.060000 168.180000 849.540000 ;
+ RECT 236.330000 838.180000 237.330000 838.660000 ;
+ RECT 236.330000 843.620000 237.330000 844.100000 ;
+ RECT 236.330000 821.860000 237.330000 822.340000 ;
+ RECT 236.330000 827.300000 237.330000 827.780000 ;
+ RECT 236.330000 832.740000 237.330000 833.220000 ;
+ RECT 212.080000 843.620000 213.180000 844.100000 ;
+ RECT 212.080000 838.180000 213.180000 838.660000 ;
+ RECT 212.080000 832.740000 213.180000 833.220000 ;
+ RECT 212.080000 827.300000 213.180000 827.780000 ;
+ RECT 212.080000 821.860000 213.180000 822.340000 ;
+ RECT 236.330000 810.980000 237.330000 811.460000 ;
+ RECT 236.330000 816.420000 237.330000 816.900000 ;
+ RECT 236.330000 800.100000 237.330000 800.580000 ;
+ RECT 236.330000 805.540000 237.330000 806.020000 ;
+ RECT 212.080000 816.420000 213.180000 816.900000 ;
+ RECT 212.080000 810.980000 213.180000 811.460000 ;
+ RECT 212.080000 805.540000 213.180000 806.020000 ;
+ RECT 212.080000 800.100000 213.180000 800.580000 ;
+ RECT 236.330000 789.220000 237.330000 789.700000 ;
+ RECT 236.330000 794.660000 237.330000 795.140000 ;
+ RECT 236.330000 772.900000 237.330000 773.380000 ;
+ RECT 236.330000 778.340000 237.330000 778.820000 ;
+ RECT 236.330000 783.780000 237.330000 784.260000 ;
+ RECT 212.080000 772.900000 213.180000 773.380000 ;
+ RECT 212.080000 778.340000 213.180000 778.820000 ;
+ RECT 212.080000 783.780000 213.180000 784.260000 ;
+ RECT 212.080000 789.220000 213.180000 789.700000 ;
+ RECT 212.080000 794.660000 213.180000 795.140000 ;
+ RECT 236.330000 762.020000 237.330000 762.500000 ;
+ RECT 236.330000 767.460000 237.330000 767.940000 ;
+ RECT 236.330000 751.140000 237.330000 751.620000 ;
+ RECT 236.330000 756.580000 237.330000 757.060000 ;
+ RECT 212.080000 762.020000 213.180000 762.500000 ;
+ RECT 212.080000 756.580000 213.180000 757.060000 ;
+ RECT 212.080000 751.140000 213.180000 751.620000 ;
+ RECT 212.080000 767.460000 213.180000 767.940000 ;
+ RECT 162.950000 838.180000 163.950000 838.660000 ;
+ RECT 162.950000 843.620000 163.950000 844.100000 ;
+ RECT 167.080000 843.620000 168.180000 844.100000 ;
+ RECT 167.080000 838.180000 168.180000 838.660000 ;
+ RECT 167.080000 832.740000 168.180000 833.220000 ;
+ RECT 162.950000 832.740000 163.950000 833.220000 ;
+ RECT 167.080000 821.860000 168.180000 822.340000 ;
+ RECT 162.950000 821.860000 163.950000 822.340000 ;
+ RECT 162.950000 827.300000 163.950000 827.780000 ;
+ RECT 167.080000 827.300000 168.180000 827.780000 ;
+ RECT 162.950000 810.980000 163.950000 811.460000 ;
+ RECT 162.950000 816.420000 163.950000 816.900000 ;
+ RECT 167.080000 816.420000 168.180000 816.900000 ;
+ RECT 167.080000 810.980000 168.180000 811.460000 ;
+ RECT 162.950000 800.100000 163.950000 800.580000 ;
+ RECT 162.950000 805.540000 163.950000 806.020000 ;
+ RECT 167.080000 805.540000 168.180000 806.020000 ;
+ RECT 167.080000 800.100000 168.180000 800.580000 ;
+ RECT 162.950000 789.220000 163.950000 789.700000 ;
+ RECT 162.950000 794.660000 163.950000 795.140000 ;
+ RECT 167.080000 789.220000 168.180000 789.700000 ;
+ RECT 167.080000 794.660000 168.180000 795.140000 ;
+ RECT 162.950000 772.900000 163.950000 773.380000 ;
+ RECT 162.950000 778.340000 163.950000 778.820000 ;
+ RECT 167.080000 772.900000 168.180000 773.380000 ;
+ RECT 167.080000 778.340000 168.180000 778.820000 ;
+ RECT 167.080000 783.780000 168.180000 784.260000 ;
+ RECT 162.950000 783.780000 163.950000 784.260000 ;
+ RECT 162.950000 762.020000 163.950000 762.500000 ;
+ RECT 162.950000 767.460000 163.950000 767.940000 ;
+ RECT 167.080000 762.020000 168.180000 762.500000 ;
+ RECT 167.080000 767.460000 168.180000 767.940000 ;
+ RECT 167.080000 751.140000 168.180000 751.620000 ;
+ RECT 167.080000 756.580000 168.180000 757.060000 ;
+ RECT 162.950000 756.580000 163.950000 757.060000 ;
+ RECT 162.950000 751.140000 163.950000 751.620000 ;
+ RECT 160.120000 941.500000 240.160000 942.500000 ;
+ RECT 160.120000 749.130000 240.160000 750.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 746.280000 163.950000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 945.540000 163.950000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 746.280000 237.330000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 945.540000 237.330000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 749.130000 161.120000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 749.130000 240.160000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 941.500000 161.120000 942.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 941.500000 240.160000 942.500000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 546.020000 163.950000 746.280000 ;
+ RECT 236.330000 546.020000 237.330000 746.280000 ;
+ RECT 167.080000 548.870000 168.180000 742.240000 ;
+ RECT 212.080000 548.870000 213.180000 742.240000 ;
+ LAYER met3 ;
+ RECT 236.330000 735.840000 237.330000 736.320000 ;
+ RECT 236.330000 724.960000 237.330000 725.440000 ;
+ RECT 236.330000 730.400000 237.330000 730.880000 ;
+ RECT 212.080000 735.840000 213.180000 736.320000 ;
+ RECT 212.080000 730.400000 213.180000 730.880000 ;
+ RECT 212.080000 724.960000 213.180000 725.440000 ;
+ RECT 236.330000 714.080000 237.330000 714.560000 ;
+ RECT 236.330000 719.520000 237.330000 720.000000 ;
+ RECT 236.330000 697.760000 237.330000 698.240000 ;
+ RECT 236.330000 703.200000 237.330000 703.680000 ;
+ RECT 236.330000 708.640000 237.330000 709.120000 ;
+ RECT 212.080000 719.520000 213.180000 720.000000 ;
+ RECT 212.080000 714.080000 213.180000 714.560000 ;
+ RECT 212.080000 708.640000 213.180000 709.120000 ;
+ RECT 212.080000 703.200000 213.180000 703.680000 ;
+ RECT 212.080000 697.760000 213.180000 698.240000 ;
+ RECT 236.330000 686.880000 237.330000 687.360000 ;
+ RECT 236.330000 692.320000 237.330000 692.800000 ;
+ RECT 236.330000 676.000000 237.330000 676.480000 ;
+ RECT 236.330000 681.440000 237.330000 681.920000 ;
+ RECT 212.080000 676.000000 213.180000 676.480000 ;
+ RECT 212.080000 681.440000 213.180000 681.920000 ;
+ RECT 212.080000 686.880000 213.180000 687.360000 ;
+ RECT 212.080000 692.320000 213.180000 692.800000 ;
+ RECT 236.330000 659.680000 237.330000 660.160000 ;
+ RECT 236.330000 665.120000 237.330000 665.600000 ;
+ RECT 236.330000 670.560000 237.330000 671.040000 ;
+ RECT 236.330000 648.800000 237.330000 649.280000 ;
+ RECT 236.330000 654.240000 237.330000 654.720000 ;
+ RECT 212.080000 659.680000 213.180000 660.160000 ;
+ RECT 212.080000 654.240000 213.180000 654.720000 ;
+ RECT 212.080000 648.800000 213.180000 649.280000 ;
+ RECT 212.080000 665.120000 213.180000 665.600000 ;
+ RECT 212.080000 670.560000 213.180000 671.040000 ;
+ RECT 167.080000 735.840000 168.180000 736.320000 ;
+ RECT 162.950000 735.840000 163.950000 736.320000 ;
+ RECT 162.950000 724.960000 163.950000 725.440000 ;
+ RECT 167.080000 730.400000 168.180000 730.880000 ;
+ RECT 167.080000 724.960000 168.180000 725.440000 ;
+ RECT 162.950000 730.400000 163.950000 730.880000 ;
+ RECT 162.950000 714.080000 163.950000 714.560000 ;
+ RECT 162.950000 719.520000 163.950000 720.000000 ;
+ RECT 167.080000 719.520000 168.180000 720.000000 ;
+ RECT 167.080000 714.080000 168.180000 714.560000 ;
+ RECT 162.950000 697.760000 163.950000 698.240000 ;
+ RECT 162.950000 703.200000 163.950000 703.680000 ;
+ RECT 167.080000 703.200000 168.180000 703.680000 ;
+ RECT 167.080000 697.760000 168.180000 698.240000 ;
+ RECT 167.080000 708.640000 168.180000 709.120000 ;
+ RECT 162.950000 708.640000 163.950000 709.120000 ;
+ RECT 162.950000 686.880000 163.950000 687.360000 ;
+ RECT 162.950000 692.320000 163.950000 692.800000 ;
+ RECT 167.080000 686.880000 168.180000 687.360000 ;
+ RECT 167.080000 692.320000 168.180000 692.800000 ;
+ RECT 162.950000 676.000000 163.950000 676.480000 ;
+ RECT 162.950000 681.440000 163.950000 681.920000 ;
+ RECT 167.080000 676.000000 168.180000 676.480000 ;
+ RECT 167.080000 681.440000 168.180000 681.920000 ;
+ RECT 167.080000 670.560000 168.180000 671.040000 ;
+ RECT 167.080000 665.120000 168.180000 665.600000 ;
+ RECT 162.950000 670.560000 163.950000 671.040000 ;
+ RECT 162.950000 665.120000 163.950000 665.600000 ;
+ RECT 167.080000 659.680000 168.180000 660.160000 ;
+ RECT 162.950000 659.680000 163.950000 660.160000 ;
+ RECT 162.950000 648.800000 163.950000 649.280000 ;
+ RECT 162.950000 654.240000 163.950000 654.720000 ;
+ RECT 167.080000 654.240000 168.180000 654.720000 ;
+ RECT 167.080000 648.800000 168.180000 649.280000 ;
+ RECT 236.330000 637.920000 237.330000 638.400000 ;
+ RECT 236.330000 643.360000 237.330000 643.840000 ;
+ RECT 236.330000 621.600000 237.330000 622.080000 ;
+ RECT 236.330000 627.040000 237.330000 627.520000 ;
+ RECT 236.330000 632.480000 237.330000 632.960000 ;
+ RECT 212.080000 643.360000 213.180000 643.840000 ;
+ RECT 212.080000 637.920000 213.180000 638.400000 ;
+ RECT 212.080000 632.480000 213.180000 632.960000 ;
+ RECT 212.080000 627.040000 213.180000 627.520000 ;
+ RECT 212.080000 621.600000 213.180000 622.080000 ;
+ RECT 236.330000 610.720000 237.330000 611.200000 ;
+ RECT 236.330000 616.160000 237.330000 616.640000 ;
+ RECT 236.330000 599.840000 237.330000 600.320000 ;
+ RECT 236.330000 605.280000 237.330000 605.760000 ;
+ RECT 212.080000 616.160000 213.180000 616.640000 ;
+ RECT 212.080000 610.720000 213.180000 611.200000 ;
+ RECT 212.080000 605.280000 213.180000 605.760000 ;
+ RECT 212.080000 599.840000 213.180000 600.320000 ;
+ RECT 236.330000 588.960000 237.330000 589.440000 ;
+ RECT 236.330000 594.400000 237.330000 594.880000 ;
+ RECT 236.330000 572.640000 237.330000 573.120000 ;
+ RECT 236.330000 578.080000 237.330000 578.560000 ;
+ RECT 236.330000 583.520000 237.330000 584.000000 ;
+ RECT 212.080000 572.640000 213.180000 573.120000 ;
+ RECT 212.080000 578.080000 213.180000 578.560000 ;
+ RECT 212.080000 583.520000 213.180000 584.000000 ;
+ RECT 212.080000 588.960000 213.180000 589.440000 ;
+ RECT 212.080000 594.400000 213.180000 594.880000 ;
+ RECT 236.330000 561.760000 237.330000 562.240000 ;
+ RECT 236.330000 567.200000 237.330000 567.680000 ;
+ RECT 236.330000 550.880000 237.330000 551.360000 ;
+ RECT 236.330000 556.320000 237.330000 556.800000 ;
+ RECT 212.080000 561.760000 213.180000 562.240000 ;
+ RECT 212.080000 556.320000 213.180000 556.800000 ;
+ RECT 212.080000 550.880000 213.180000 551.360000 ;
+ RECT 212.080000 567.200000 213.180000 567.680000 ;
+ RECT 162.950000 637.920000 163.950000 638.400000 ;
+ RECT 162.950000 643.360000 163.950000 643.840000 ;
+ RECT 167.080000 643.360000 168.180000 643.840000 ;
+ RECT 167.080000 637.920000 168.180000 638.400000 ;
+ RECT 167.080000 632.480000 168.180000 632.960000 ;
+ RECT 162.950000 632.480000 163.950000 632.960000 ;
+ RECT 167.080000 621.600000 168.180000 622.080000 ;
+ RECT 162.950000 621.600000 163.950000 622.080000 ;
+ RECT 162.950000 627.040000 163.950000 627.520000 ;
+ RECT 167.080000 627.040000 168.180000 627.520000 ;
+ RECT 162.950000 610.720000 163.950000 611.200000 ;
+ RECT 162.950000 616.160000 163.950000 616.640000 ;
+ RECT 167.080000 616.160000 168.180000 616.640000 ;
+ RECT 167.080000 610.720000 168.180000 611.200000 ;
+ RECT 162.950000 599.840000 163.950000 600.320000 ;
+ RECT 162.950000 605.280000 163.950000 605.760000 ;
+ RECT 167.080000 605.280000 168.180000 605.760000 ;
+ RECT 167.080000 599.840000 168.180000 600.320000 ;
+ RECT 162.950000 588.960000 163.950000 589.440000 ;
+ RECT 162.950000 594.400000 163.950000 594.880000 ;
+ RECT 167.080000 588.960000 168.180000 589.440000 ;
+ RECT 167.080000 594.400000 168.180000 594.880000 ;
+ RECT 162.950000 572.640000 163.950000 573.120000 ;
+ RECT 162.950000 578.080000 163.950000 578.560000 ;
+ RECT 167.080000 572.640000 168.180000 573.120000 ;
+ RECT 167.080000 578.080000 168.180000 578.560000 ;
+ RECT 167.080000 583.520000 168.180000 584.000000 ;
+ RECT 162.950000 583.520000 163.950000 584.000000 ;
+ RECT 162.950000 561.760000 163.950000 562.240000 ;
+ RECT 162.950000 567.200000 163.950000 567.680000 ;
+ RECT 167.080000 561.760000 168.180000 562.240000 ;
+ RECT 167.080000 567.200000 168.180000 567.680000 ;
+ RECT 167.080000 550.880000 168.180000 551.360000 ;
+ RECT 167.080000 556.320000 168.180000 556.800000 ;
+ RECT 162.950000 556.320000 163.950000 556.800000 ;
+ RECT 162.950000 550.880000 163.950000 551.360000 ;
+ RECT 160.120000 741.240000 240.160000 742.240000 ;
+ RECT 160.120000 548.870000 240.160000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 546.020000 163.950000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 745.280000 163.950000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 546.020000 237.330000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 745.280000 237.330000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 548.870000 161.120000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 548.870000 240.160000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 741.240000 161.120000 742.240000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 741.240000 240.160000 742.240000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 345.760000 163.950000 546.020000 ;
+ RECT 236.330000 345.760000 237.330000 546.020000 ;
+ RECT 167.080000 348.610000 168.180000 541.980000 ;
+ RECT 212.080000 348.610000 213.180000 541.980000 ;
+ LAYER met3 ;
+ RECT 236.330000 535.580000 237.330000 536.060000 ;
+ RECT 236.330000 524.700000 237.330000 525.180000 ;
+ RECT 236.330000 530.140000 237.330000 530.620000 ;
+ RECT 212.080000 535.580000 213.180000 536.060000 ;
+ RECT 212.080000 530.140000 213.180000 530.620000 ;
+ RECT 212.080000 524.700000 213.180000 525.180000 ;
+ RECT 236.330000 513.820000 237.330000 514.300000 ;
+ RECT 236.330000 519.260000 237.330000 519.740000 ;
+ RECT 236.330000 497.500000 237.330000 497.980000 ;
+ RECT 236.330000 502.940000 237.330000 503.420000 ;
+ RECT 236.330000 508.380000 237.330000 508.860000 ;
+ RECT 212.080000 519.260000 213.180000 519.740000 ;
+ RECT 212.080000 513.820000 213.180000 514.300000 ;
+ RECT 212.080000 508.380000 213.180000 508.860000 ;
+ RECT 212.080000 502.940000 213.180000 503.420000 ;
+ RECT 212.080000 497.500000 213.180000 497.980000 ;
+ RECT 236.330000 486.620000 237.330000 487.100000 ;
+ RECT 236.330000 492.060000 237.330000 492.540000 ;
+ RECT 236.330000 475.740000 237.330000 476.220000 ;
+ RECT 236.330000 481.180000 237.330000 481.660000 ;
+ RECT 212.080000 475.740000 213.180000 476.220000 ;
+ RECT 212.080000 481.180000 213.180000 481.660000 ;
+ RECT 212.080000 486.620000 213.180000 487.100000 ;
+ RECT 212.080000 492.060000 213.180000 492.540000 ;
+ RECT 236.330000 459.420000 237.330000 459.900000 ;
+ RECT 236.330000 464.860000 237.330000 465.340000 ;
+ RECT 236.330000 470.300000 237.330000 470.780000 ;
+ RECT 236.330000 448.540000 237.330000 449.020000 ;
+ RECT 236.330000 453.980000 237.330000 454.460000 ;
+ RECT 212.080000 459.420000 213.180000 459.900000 ;
+ RECT 212.080000 453.980000 213.180000 454.460000 ;
+ RECT 212.080000 448.540000 213.180000 449.020000 ;
+ RECT 212.080000 464.860000 213.180000 465.340000 ;
+ RECT 212.080000 470.300000 213.180000 470.780000 ;
+ RECT 167.080000 535.580000 168.180000 536.060000 ;
+ RECT 162.950000 535.580000 163.950000 536.060000 ;
+ RECT 162.950000 524.700000 163.950000 525.180000 ;
+ RECT 167.080000 530.140000 168.180000 530.620000 ;
+ RECT 167.080000 524.700000 168.180000 525.180000 ;
+ RECT 162.950000 530.140000 163.950000 530.620000 ;
+ RECT 162.950000 513.820000 163.950000 514.300000 ;
+ RECT 162.950000 519.260000 163.950000 519.740000 ;
+ RECT 167.080000 519.260000 168.180000 519.740000 ;
+ RECT 167.080000 513.820000 168.180000 514.300000 ;
+ RECT 162.950000 497.500000 163.950000 497.980000 ;
+ RECT 162.950000 502.940000 163.950000 503.420000 ;
+ RECT 167.080000 502.940000 168.180000 503.420000 ;
+ RECT 167.080000 497.500000 168.180000 497.980000 ;
+ RECT 167.080000 508.380000 168.180000 508.860000 ;
+ RECT 162.950000 508.380000 163.950000 508.860000 ;
+ RECT 162.950000 486.620000 163.950000 487.100000 ;
+ RECT 162.950000 492.060000 163.950000 492.540000 ;
+ RECT 167.080000 486.620000 168.180000 487.100000 ;
+ RECT 167.080000 492.060000 168.180000 492.540000 ;
+ RECT 162.950000 475.740000 163.950000 476.220000 ;
+ RECT 162.950000 481.180000 163.950000 481.660000 ;
+ RECT 167.080000 475.740000 168.180000 476.220000 ;
+ RECT 167.080000 481.180000 168.180000 481.660000 ;
+ RECT 167.080000 470.300000 168.180000 470.780000 ;
+ RECT 167.080000 464.860000 168.180000 465.340000 ;
+ RECT 162.950000 470.300000 163.950000 470.780000 ;
+ RECT 162.950000 464.860000 163.950000 465.340000 ;
+ RECT 167.080000 459.420000 168.180000 459.900000 ;
+ RECT 162.950000 459.420000 163.950000 459.900000 ;
+ RECT 162.950000 448.540000 163.950000 449.020000 ;
+ RECT 162.950000 453.980000 163.950000 454.460000 ;
+ RECT 167.080000 453.980000 168.180000 454.460000 ;
+ RECT 167.080000 448.540000 168.180000 449.020000 ;
+ RECT 236.330000 437.660000 237.330000 438.140000 ;
+ RECT 236.330000 443.100000 237.330000 443.580000 ;
+ RECT 236.330000 421.340000 237.330000 421.820000 ;
+ RECT 236.330000 426.780000 237.330000 427.260000 ;
+ RECT 236.330000 432.220000 237.330000 432.700000 ;
+ RECT 212.080000 443.100000 213.180000 443.580000 ;
+ RECT 212.080000 437.660000 213.180000 438.140000 ;
+ RECT 212.080000 432.220000 213.180000 432.700000 ;
+ RECT 212.080000 426.780000 213.180000 427.260000 ;
+ RECT 212.080000 421.340000 213.180000 421.820000 ;
+ RECT 236.330000 410.460000 237.330000 410.940000 ;
+ RECT 236.330000 415.900000 237.330000 416.380000 ;
+ RECT 236.330000 399.580000 237.330000 400.060000 ;
+ RECT 236.330000 405.020000 237.330000 405.500000 ;
+ RECT 212.080000 415.900000 213.180000 416.380000 ;
+ RECT 212.080000 410.460000 213.180000 410.940000 ;
+ RECT 212.080000 405.020000 213.180000 405.500000 ;
+ RECT 212.080000 399.580000 213.180000 400.060000 ;
+ RECT 236.330000 388.700000 237.330000 389.180000 ;
+ RECT 236.330000 394.140000 237.330000 394.620000 ;
+ RECT 236.330000 372.380000 237.330000 372.860000 ;
+ RECT 236.330000 377.820000 237.330000 378.300000 ;
+ RECT 236.330000 383.260000 237.330000 383.740000 ;
+ RECT 212.080000 372.380000 213.180000 372.860000 ;
+ RECT 212.080000 377.820000 213.180000 378.300000 ;
+ RECT 212.080000 383.260000 213.180000 383.740000 ;
+ RECT 212.080000 388.700000 213.180000 389.180000 ;
+ RECT 212.080000 394.140000 213.180000 394.620000 ;
+ RECT 236.330000 361.500000 237.330000 361.980000 ;
+ RECT 236.330000 366.940000 237.330000 367.420000 ;
+ RECT 236.330000 350.620000 237.330000 351.100000 ;
+ RECT 236.330000 356.060000 237.330000 356.540000 ;
+ RECT 212.080000 361.500000 213.180000 361.980000 ;
+ RECT 212.080000 356.060000 213.180000 356.540000 ;
+ RECT 212.080000 350.620000 213.180000 351.100000 ;
+ RECT 212.080000 366.940000 213.180000 367.420000 ;
+ RECT 162.950000 437.660000 163.950000 438.140000 ;
+ RECT 162.950000 443.100000 163.950000 443.580000 ;
+ RECT 167.080000 443.100000 168.180000 443.580000 ;
+ RECT 167.080000 437.660000 168.180000 438.140000 ;
+ RECT 167.080000 432.220000 168.180000 432.700000 ;
+ RECT 162.950000 432.220000 163.950000 432.700000 ;
+ RECT 167.080000 421.340000 168.180000 421.820000 ;
+ RECT 162.950000 421.340000 163.950000 421.820000 ;
+ RECT 162.950000 426.780000 163.950000 427.260000 ;
+ RECT 167.080000 426.780000 168.180000 427.260000 ;
+ RECT 162.950000 410.460000 163.950000 410.940000 ;
+ RECT 162.950000 415.900000 163.950000 416.380000 ;
+ RECT 167.080000 415.900000 168.180000 416.380000 ;
+ RECT 167.080000 410.460000 168.180000 410.940000 ;
+ RECT 162.950000 399.580000 163.950000 400.060000 ;
+ RECT 162.950000 405.020000 163.950000 405.500000 ;
+ RECT 167.080000 405.020000 168.180000 405.500000 ;
+ RECT 167.080000 399.580000 168.180000 400.060000 ;
+ RECT 162.950000 388.700000 163.950000 389.180000 ;
+ RECT 162.950000 394.140000 163.950000 394.620000 ;
+ RECT 167.080000 388.700000 168.180000 389.180000 ;
+ RECT 167.080000 394.140000 168.180000 394.620000 ;
+ RECT 162.950000 372.380000 163.950000 372.860000 ;
+ RECT 162.950000 377.820000 163.950000 378.300000 ;
+ RECT 167.080000 372.380000 168.180000 372.860000 ;
+ RECT 167.080000 377.820000 168.180000 378.300000 ;
+ RECT 167.080000 383.260000 168.180000 383.740000 ;
+ RECT 162.950000 383.260000 163.950000 383.740000 ;
+ RECT 162.950000 361.500000 163.950000 361.980000 ;
+ RECT 162.950000 366.940000 163.950000 367.420000 ;
+ RECT 167.080000 361.500000 168.180000 361.980000 ;
+ RECT 167.080000 366.940000 168.180000 367.420000 ;
+ RECT 167.080000 350.620000 168.180000 351.100000 ;
+ RECT 167.080000 356.060000 168.180000 356.540000 ;
+ RECT 162.950000 356.060000 163.950000 356.540000 ;
+ RECT 162.950000 350.620000 163.950000 351.100000 ;
+ RECT 160.120000 540.980000 240.160000 541.980000 ;
+ RECT 160.120000 348.610000 240.160000 349.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 345.760000 163.950000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 545.020000 163.950000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 345.760000 237.330000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 545.020000 237.330000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 348.610000 161.120000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 348.610000 240.160000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 540.980000 161.120000 541.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 540.980000 240.160000 541.980000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 145.500000 163.950000 345.760000 ;
+ RECT 236.330000 145.500000 237.330000 345.760000 ;
+ RECT 167.080000 148.350000 168.180000 341.720000 ;
+ RECT 212.080000 148.350000 213.180000 341.720000 ;
+ LAYER met3 ;
+ RECT 236.330000 335.320000 237.330000 335.800000 ;
+ RECT 236.330000 324.440000 237.330000 324.920000 ;
+ RECT 236.330000 329.880000 237.330000 330.360000 ;
+ RECT 212.080000 335.320000 213.180000 335.800000 ;
+ RECT 212.080000 329.880000 213.180000 330.360000 ;
+ RECT 212.080000 324.440000 213.180000 324.920000 ;
+ RECT 236.330000 313.560000 237.330000 314.040000 ;
+ RECT 236.330000 319.000000 237.330000 319.480000 ;
+ RECT 236.330000 297.240000 237.330000 297.720000 ;
+ RECT 236.330000 302.680000 237.330000 303.160000 ;
+ RECT 236.330000 308.120000 237.330000 308.600000 ;
+ RECT 212.080000 319.000000 213.180000 319.480000 ;
+ RECT 212.080000 313.560000 213.180000 314.040000 ;
+ RECT 212.080000 308.120000 213.180000 308.600000 ;
+ RECT 212.080000 302.680000 213.180000 303.160000 ;
+ RECT 212.080000 297.240000 213.180000 297.720000 ;
+ RECT 236.330000 286.360000 237.330000 286.840000 ;
+ RECT 236.330000 291.800000 237.330000 292.280000 ;
+ RECT 236.330000 275.480000 237.330000 275.960000 ;
+ RECT 236.330000 280.920000 237.330000 281.400000 ;
+ RECT 212.080000 275.480000 213.180000 275.960000 ;
+ RECT 212.080000 280.920000 213.180000 281.400000 ;
+ RECT 212.080000 286.360000 213.180000 286.840000 ;
+ RECT 212.080000 291.800000 213.180000 292.280000 ;
+ RECT 236.330000 259.160000 237.330000 259.640000 ;
+ RECT 236.330000 264.600000 237.330000 265.080000 ;
+ RECT 236.330000 270.040000 237.330000 270.520000 ;
+ RECT 236.330000 248.280000 237.330000 248.760000 ;
+ RECT 236.330000 253.720000 237.330000 254.200000 ;
+ RECT 212.080000 259.160000 213.180000 259.640000 ;
+ RECT 212.080000 253.720000 213.180000 254.200000 ;
+ RECT 212.080000 248.280000 213.180000 248.760000 ;
+ RECT 212.080000 264.600000 213.180000 265.080000 ;
+ RECT 212.080000 270.040000 213.180000 270.520000 ;
+ RECT 167.080000 335.320000 168.180000 335.800000 ;
+ RECT 162.950000 335.320000 163.950000 335.800000 ;
+ RECT 162.950000 324.440000 163.950000 324.920000 ;
+ RECT 167.080000 329.880000 168.180000 330.360000 ;
+ RECT 167.080000 324.440000 168.180000 324.920000 ;
+ RECT 162.950000 329.880000 163.950000 330.360000 ;
+ RECT 162.950000 313.560000 163.950000 314.040000 ;
+ RECT 162.950000 319.000000 163.950000 319.480000 ;
+ RECT 167.080000 319.000000 168.180000 319.480000 ;
+ RECT 167.080000 313.560000 168.180000 314.040000 ;
+ RECT 162.950000 297.240000 163.950000 297.720000 ;
+ RECT 162.950000 302.680000 163.950000 303.160000 ;
+ RECT 167.080000 302.680000 168.180000 303.160000 ;
+ RECT 167.080000 297.240000 168.180000 297.720000 ;
+ RECT 167.080000 308.120000 168.180000 308.600000 ;
+ RECT 162.950000 308.120000 163.950000 308.600000 ;
+ RECT 162.950000 286.360000 163.950000 286.840000 ;
+ RECT 162.950000 291.800000 163.950000 292.280000 ;
+ RECT 167.080000 286.360000 168.180000 286.840000 ;
+ RECT 167.080000 291.800000 168.180000 292.280000 ;
+ RECT 162.950000 275.480000 163.950000 275.960000 ;
+ RECT 162.950000 280.920000 163.950000 281.400000 ;
+ RECT 167.080000 275.480000 168.180000 275.960000 ;
+ RECT 167.080000 280.920000 168.180000 281.400000 ;
+ RECT 167.080000 270.040000 168.180000 270.520000 ;
+ RECT 167.080000 264.600000 168.180000 265.080000 ;
+ RECT 162.950000 270.040000 163.950000 270.520000 ;
+ RECT 162.950000 264.600000 163.950000 265.080000 ;
+ RECT 167.080000 259.160000 168.180000 259.640000 ;
+ RECT 162.950000 259.160000 163.950000 259.640000 ;
+ RECT 162.950000 248.280000 163.950000 248.760000 ;
+ RECT 162.950000 253.720000 163.950000 254.200000 ;
+ RECT 167.080000 253.720000 168.180000 254.200000 ;
+ RECT 167.080000 248.280000 168.180000 248.760000 ;
+ RECT 236.330000 237.400000 237.330000 237.880000 ;
+ RECT 236.330000 242.840000 237.330000 243.320000 ;
+ RECT 236.330000 221.080000 237.330000 221.560000 ;
+ RECT 236.330000 226.520000 237.330000 227.000000 ;
+ RECT 236.330000 231.960000 237.330000 232.440000 ;
+ RECT 212.080000 242.840000 213.180000 243.320000 ;
+ RECT 212.080000 237.400000 213.180000 237.880000 ;
+ RECT 212.080000 231.960000 213.180000 232.440000 ;
+ RECT 212.080000 226.520000 213.180000 227.000000 ;
+ RECT 212.080000 221.080000 213.180000 221.560000 ;
+ RECT 236.330000 210.200000 237.330000 210.680000 ;
+ RECT 236.330000 215.640000 237.330000 216.120000 ;
+ RECT 236.330000 199.320000 237.330000 199.800000 ;
+ RECT 236.330000 204.760000 237.330000 205.240000 ;
+ RECT 212.080000 215.640000 213.180000 216.120000 ;
+ RECT 212.080000 210.200000 213.180000 210.680000 ;
+ RECT 212.080000 204.760000 213.180000 205.240000 ;
+ RECT 212.080000 199.320000 213.180000 199.800000 ;
+ RECT 236.330000 188.440000 237.330000 188.920000 ;
+ RECT 236.330000 193.880000 237.330000 194.360000 ;
+ RECT 236.330000 172.120000 237.330000 172.600000 ;
+ RECT 236.330000 177.560000 237.330000 178.040000 ;
+ RECT 236.330000 183.000000 237.330000 183.480000 ;
+ RECT 212.080000 172.120000 213.180000 172.600000 ;
+ RECT 212.080000 177.560000 213.180000 178.040000 ;
+ RECT 212.080000 183.000000 213.180000 183.480000 ;
+ RECT 212.080000 188.440000 213.180000 188.920000 ;
+ RECT 212.080000 193.880000 213.180000 194.360000 ;
+ RECT 236.330000 161.240000 237.330000 161.720000 ;
+ RECT 236.330000 166.680000 237.330000 167.160000 ;
+ RECT 236.330000 150.360000 237.330000 150.840000 ;
+ RECT 236.330000 155.800000 237.330000 156.280000 ;
+ RECT 212.080000 161.240000 213.180000 161.720000 ;
+ RECT 212.080000 155.800000 213.180000 156.280000 ;
+ RECT 212.080000 150.360000 213.180000 150.840000 ;
+ RECT 212.080000 166.680000 213.180000 167.160000 ;
+ RECT 162.950000 237.400000 163.950000 237.880000 ;
+ RECT 162.950000 242.840000 163.950000 243.320000 ;
+ RECT 167.080000 242.840000 168.180000 243.320000 ;
+ RECT 167.080000 237.400000 168.180000 237.880000 ;
+ RECT 167.080000 231.960000 168.180000 232.440000 ;
+ RECT 162.950000 231.960000 163.950000 232.440000 ;
+ RECT 167.080000 221.080000 168.180000 221.560000 ;
+ RECT 162.950000 221.080000 163.950000 221.560000 ;
+ RECT 162.950000 226.520000 163.950000 227.000000 ;
+ RECT 167.080000 226.520000 168.180000 227.000000 ;
+ RECT 162.950000 210.200000 163.950000 210.680000 ;
+ RECT 162.950000 215.640000 163.950000 216.120000 ;
+ RECT 167.080000 215.640000 168.180000 216.120000 ;
+ RECT 167.080000 210.200000 168.180000 210.680000 ;
+ RECT 162.950000 199.320000 163.950000 199.800000 ;
+ RECT 162.950000 204.760000 163.950000 205.240000 ;
+ RECT 167.080000 204.760000 168.180000 205.240000 ;
+ RECT 167.080000 199.320000 168.180000 199.800000 ;
+ RECT 162.950000 188.440000 163.950000 188.920000 ;
+ RECT 162.950000 193.880000 163.950000 194.360000 ;
+ RECT 167.080000 188.440000 168.180000 188.920000 ;
+ RECT 167.080000 193.880000 168.180000 194.360000 ;
+ RECT 162.950000 172.120000 163.950000 172.600000 ;
+ RECT 162.950000 177.560000 163.950000 178.040000 ;
+ RECT 167.080000 172.120000 168.180000 172.600000 ;
+ RECT 167.080000 177.560000 168.180000 178.040000 ;
+ RECT 167.080000 183.000000 168.180000 183.480000 ;
+ RECT 162.950000 183.000000 163.950000 183.480000 ;
+ RECT 162.950000 161.240000 163.950000 161.720000 ;
+ RECT 162.950000 166.680000 163.950000 167.160000 ;
+ RECT 167.080000 161.240000 168.180000 161.720000 ;
+ RECT 167.080000 166.680000 168.180000 167.160000 ;
+ RECT 167.080000 150.360000 168.180000 150.840000 ;
+ RECT 167.080000 155.800000 168.180000 156.280000 ;
+ RECT 162.950000 155.800000 163.950000 156.280000 ;
+ RECT 162.950000 150.360000 163.950000 150.840000 ;
+ RECT 160.120000 340.720000 240.160000 341.720000 ;
+ RECT 160.120000 148.350000 240.160000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 145.500000 163.950000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 344.760000 163.950000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 145.500000 237.330000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 344.760000 237.330000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 148.350000 161.120000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 148.350000 240.160000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 340.720000 161.120000 341.720000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 340.720000 240.160000 341.720000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 3149.400000 163.950000 3349.660000 ;
+ RECT 236.330000 3149.400000 237.330000 3349.660000 ;
+ RECT 167.080000 3152.250000 168.180000 3345.620000 ;
+ RECT 212.080000 3152.250000 213.180000 3345.620000 ;
+ LAYER met3 ;
+ RECT 236.330000 3339.220000 237.330000 3339.700000 ;
+ RECT 236.330000 3328.340000 237.330000 3328.820000 ;
+ RECT 236.330000 3333.780000 237.330000 3334.260000 ;
+ RECT 212.080000 3339.220000 213.180000 3339.700000 ;
+ RECT 212.080000 3333.780000 213.180000 3334.260000 ;
+ RECT 212.080000 3328.340000 213.180000 3328.820000 ;
+ RECT 236.330000 3317.460000 237.330000 3317.940000 ;
+ RECT 236.330000 3322.900000 237.330000 3323.380000 ;
+ RECT 236.330000 3301.140000 237.330000 3301.620000 ;
+ RECT 236.330000 3306.580000 237.330000 3307.060000 ;
+ RECT 236.330000 3312.020000 237.330000 3312.500000 ;
+ RECT 212.080000 3322.900000 213.180000 3323.380000 ;
+ RECT 212.080000 3317.460000 213.180000 3317.940000 ;
+ RECT 212.080000 3312.020000 213.180000 3312.500000 ;
+ RECT 212.080000 3306.580000 213.180000 3307.060000 ;
+ RECT 212.080000 3301.140000 213.180000 3301.620000 ;
+ RECT 236.330000 3290.260000 237.330000 3290.740000 ;
+ RECT 236.330000 3295.700000 237.330000 3296.180000 ;
+ RECT 236.330000 3279.380000 237.330000 3279.860000 ;
+ RECT 236.330000 3284.820000 237.330000 3285.300000 ;
+ RECT 212.080000 3279.380000 213.180000 3279.860000 ;
+ RECT 212.080000 3284.820000 213.180000 3285.300000 ;
+ RECT 212.080000 3290.260000 213.180000 3290.740000 ;
+ RECT 212.080000 3295.700000 213.180000 3296.180000 ;
+ RECT 236.330000 3263.060000 237.330000 3263.540000 ;
+ RECT 236.330000 3268.500000 237.330000 3268.980000 ;
+ RECT 236.330000 3273.940000 237.330000 3274.420000 ;
+ RECT 236.330000 3252.180000 237.330000 3252.660000 ;
+ RECT 236.330000 3257.620000 237.330000 3258.100000 ;
+ RECT 212.080000 3263.060000 213.180000 3263.540000 ;
+ RECT 212.080000 3257.620000 213.180000 3258.100000 ;
+ RECT 212.080000 3252.180000 213.180000 3252.660000 ;
+ RECT 212.080000 3268.500000 213.180000 3268.980000 ;
+ RECT 212.080000 3273.940000 213.180000 3274.420000 ;
+ RECT 167.080000 3339.220000 168.180000 3339.700000 ;
+ RECT 162.950000 3339.220000 163.950000 3339.700000 ;
+ RECT 162.950000 3328.340000 163.950000 3328.820000 ;
+ RECT 167.080000 3333.780000 168.180000 3334.260000 ;
+ RECT 167.080000 3328.340000 168.180000 3328.820000 ;
+ RECT 162.950000 3333.780000 163.950000 3334.260000 ;
+ RECT 162.950000 3317.460000 163.950000 3317.940000 ;
+ RECT 162.950000 3322.900000 163.950000 3323.380000 ;
+ RECT 167.080000 3322.900000 168.180000 3323.380000 ;
+ RECT 167.080000 3317.460000 168.180000 3317.940000 ;
+ RECT 162.950000 3301.140000 163.950000 3301.620000 ;
+ RECT 162.950000 3306.580000 163.950000 3307.060000 ;
+ RECT 167.080000 3306.580000 168.180000 3307.060000 ;
+ RECT 167.080000 3301.140000 168.180000 3301.620000 ;
+ RECT 167.080000 3312.020000 168.180000 3312.500000 ;
+ RECT 162.950000 3312.020000 163.950000 3312.500000 ;
+ RECT 162.950000 3290.260000 163.950000 3290.740000 ;
+ RECT 162.950000 3295.700000 163.950000 3296.180000 ;
+ RECT 167.080000 3290.260000 168.180000 3290.740000 ;
+ RECT 167.080000 3295.700000 168.180000 3296.180000 ;
+ RECT 162.950000 3279.380000 163.950000 3279.860000 ;
+ RECT 162.950000 3284.820000 163.950000 3285.300000 ;
+ RECT 167.080000 3279.380000 168.180000 3279.860000 ;
+ RECT 167.080000 3284.820000 168.180000 3285.300000 ;
+ RECT 167.080000 3273.940000 168.180000 3274.420000 ;
+ RECT 167.080000 3268.500000 168.180000 3268.980000 ;
+ RECT 162.950000 3273.940000 163.950000 3274.420000 ;
+ RECT 162.950000 3268.500000 163.950000 3268.980000 ;
+ RECT 167.080000 3263.060000 168.180000 3263.540000 ;
+ RECT 162.950000 3263.060000 163.950000 3263.540000 ;
+ RECT 162.950000 3252.180000 163.950000 3252.660000 ;
+ RECT 162.950000 3257.620000 163.950000 3258.100000 ;
+ RECT 167.080000 3257.620000 168.180000 3258.100000 ;
+ RECT 167.080000 3252.180000 168.180000 3252.660000 ;
+ RECT 236.330000 3241.300000 237.330000 3241.780000 ;
+ RECT 236.330000 3246.740000 237.330000 3247.220000 ;
+ RECT 236.330000 3224.980000 237.330000 3225.460000 ;
+ RECT 236.330000 3230.420000 237.330000 3230.900000 ;
+ RECT 236.330000 3235.860000 237.330000 3236.340000 ;
+ RECT 212.080000 3246.740000 213.180000 3247.220000 ;
+ RECT 212.080000 3241.300000 213.180000 3241.780000 ;
+ RECT 212.080000 3235.860000 213.180000 3236.340000 ;
+ RECT 212.080000 3230.420000 213.180000 3230.900000 ;
+ RECT 212.080000 3224.980000 213.180000 3225.460000 ;
+ RECT 236.330000 3214.100000 237.330000 3214.580000 ;
+ RECT 236.330000 3219.540000 237.330000 3220.020000 ;
+ RECT 236.330000 3203.220000 237.330000 3203.700000 ;
+ RECT 236.330000 3208.660000 237.330000 3209.140000 ;
+ RECT 212.080000 3219.540000 213.180000 3220.020000 ;
+ RECT 212.080000 3214.100000 213.180000 3214.580000 ;
+ RECT 212.080000 3208.660000 213.180000 3209.140000 ;
+ RECT 212.080000 3203.220000 213.180000 3203.700000 ;
+ RECT 236.330000 3192.340000 237.330000 3192.820000 ;
+ RECT 236.330000 3197.780000 237.330000 3198.260000 ;
+ RECT 236.330000 3176.020000 237.330000 3176.500000 ;
+ RECT 236.330000 3181.460000 237.330000 3181.940000 ;
+ RECT 236.330000 3186.900000 237.330000 3187.380000 ;
+ RECT 212.080000 3176.020000 213.180000 3176.500000 ;
+ RECT 212.080000 3181.460000 213.180000 3181.940000 ;
+ RECT 212.080000 3186.900000 213.180000 3187.380000 ;
+ RECT 212.080000 3192.340000 213.180000 3192.820000 ;
+ RECT 212.080000 3197.780000 213.180000 3198.260000 ;
+ RECT 236.330000 3165.140000 237.330000 3165.620000 ;
+ RECT 236.330000 3170.580000 237.330000 3171.060000 ;
+ RECT 236.330000 3154.260000 237.330000 3154.740000 ;
+ RECT 236.330000 3159.700000 237.330000 3160.180000 ;
+ RECT 212.080000 3165.140000 213.180000 3165.620000 ;
+ RECT 212.080000 3159.700000 213.180000 3160.180000 ;
+ RECT 212.080000 3154.260000 213.180000 3154.740000 ;
+ RECT 212.080000 3170.580000 213.180000 3171.060000 ;
+ RECT 162.950000 3241.300000 163.950000 3241.780000 ;
+ RECT 162.950000 3246.740000 163.950000 3247.220000 ;
+ RECT 167.080000 3246.740000 168.180000 3247.220000 ;
+ RECT 167.080000 3241.300000 168.180000 3241.780000 ;
+ RECT 167.080000 3235.860000 168.180000 3236.340000 ;
+ RECT 162.950000 3235.860000 163.950000 3236.340000 ;
+ RECT 167.080000 3224.980000 168.180000 3225.460000 ;
+ RECT 162.950000 3224.980000 163.950000 3225.460000 ;
+ RECT 162.950000 3230.420000 163.950000 3230.900000 ;
+ RECT 167.080000 3230.420000 168.180000 3230.900000 ;
+ RECT 162.950000 3214.100000 163.950000 3214.580000 ;
+ RECT 162.950000 3219.540000 163.950000 3220.020000 ;
+ RECT 167.080000 3219.540000 168.180000 3220.020000 ;
+ RECT 167.080000 3214.100000 168.180000 3214.580000 ;
+ RECT 162.950000 3203.220000 163.950000 3203.700000 ;
+ RECT 162.950000 3208.660000 163.950000 3209.140000 ;
+ RECT 167.080000 3208.660000 168.180000 3209.140000 ;
+ RECT 167.080000 3203.220000 168.180000 3203.700000 ;
+ RECT 162.950000 3192.340000 163.950000 3192.820000 ;
+ RECT 162.950000 3197.780000 163.950000 3198.260000 ;
+ RECT 167.080000 3192.340000 168.180000 3192.820000 ;
+ RECT 167.080000 3197.780000 168.180000 3198.260000 ;
+ RECT 162.950000 3176.020000 163.950000 3176.500000 ;
+ RECT 162.950000 3181.460000 163.950000 3181.940000 ;
+ RECT 167.080000 3176.020000 168.180000 3176.500000 ;
+ RECT 167.080000 3181.460000 168.180000 3181.940000 ;
+ RECT 167.080000 3186.900000 168.180000 3187.380000 ;
+ RECT 162.950000 3186.900000 163.950000 3187.380000 ;
+ RECT 162.950000 3165.140000 163.950000 3165.620000 ;
+ RECT 162.950000 3170.580000 163.950000 3171.060000 ;
+ RECT 167.080000 3165.140000 168.180000 3165.620000 ;
+ RECT 167.080000 3170.580000 168.180000 3171.060000 ;
+ RECT 167.080000 3154.260000 168.180000 3154.740000 ;
+ RECT 167.080000 3159.700000 168.180000 3160.180000 ;
+ RECT 162.950000 3159.700000 163.950000 3160.180000 ;
+ RECT 162.950000 3154.260000 163.950000 3154.740000 ;
+ RECT 160.120000 3344.620000 240.160000 3345.620000 ;
+ RECT 160.120000 3152.250000 240.160000 3153.250000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 3149.400000 163.950000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 3348.660000 163.950000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 3149.400000 237.330000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 3348.660000 237.330000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 3152.250000 161.120000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 3152.250000 240.160000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 3344.620000 161.120000 3345.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 3344.620000 240.160000 3345.620000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2949.140000 163.950000 3149.400000 ;
+ RECT 236.330000 2949.140000 237.330000 3149.400000 ;
+ RECT 167.080000 2951.990000 168.180000 3145.360000 ;
+ RECT 212.080000 2951.990000 213.180000 3145.360000 ;
+ LAYER met3 ;
+ RECT 236.330000 3138.960000 237.330000 3139.440000 ;
+ RECT 236.330000 3128.080000 237.330000 3128.560000 ;
+ RECT 236.330000 3133.520000 237.330000 3134.000000 ;
+ RECT 212.080000 3138.960000 213.180000 3139.440000 ;
+ RECT 212.080000 3133.520000 213.180000 3134.000000 ;
+ RECT 212.080000 3128.080000 213.180000 3128.560000 ;
+ RECT 236.330000 3117.200000 237.330000 3117.680000 ;
+ RECT 236.330000 3122.640000 237.330000 3123.120000 ;
+ RECT 236.330000 3100.880000 237.330000 3101.360000 ;
+ RECT 236.330000 3106.320000 237.330000 3106.800000 ;
+ RECT 236.330000 3111.760000 237.330000 3112.240000 ;
+ RECT 212.080000 3122.640000 213.180000 3123.120000 ;
+ RECT 212.080000 3117.200000 213.180000 3117.680000 ;
+ RECT 212.080000 3111.760000 213.180000 3112.240000 ;
+ RECT 212.080000 3106.320000 213.180000 3106.800000 ;
+ RECT 212.080000 3100.880000 213.180000 3101.360000 ;
+ RECT 236.330000 3090.000000 237.330000 3090.480000 ;
+ RECT 236.330000 3095.440000 237.330000 3095.920000 ;
+ RECT 236.330000 3079.120000 237.330000 3079.600000 ;
+ RECT 236.330000 3084.560000 237.330000 3085.040000 ;
+ RECT 212.080000 3079.120000 213.180000 3079.600000 ;
+ RECT 212.080000 3084.560000 213.180000 3085.040000 ;
+ RECT 212.080000 3090.000000 213.180000 3090.480000 ;
+ RECT 212.080000 3095.440000 213.180000 3095.920000 ;
+ RECT 236.330000 3062.800000 237.330000 3063.280000 ;
+ RECT 236.330000 3068.240000 237.330000 3068.720000 ;
+ RECT 236.330000 3073.680000 237.330000 3074.160000 ;
+ RECT 236.330000 3051.920000 237.330000 3052.400000 ;
+ RECT 236.330000 3057.360000 237.330000 3057.840000 ;
+ RECT 212.080000 3062.800000 213.180000 3063.280000 ;
+ RECT 212.080000 3057.360000 213.180000 3057.840000 ;
+ RECT 212.080000 3051.920000 213.180000 3052.400000 ;
+ RECT 212.080000 3068.240000 213.180000 3068.720000 ;
+ RECT 212.080000 3073.680000 213.180000 3074.160000 ;
+ RECT 167.080000 3138.960000 168.180000 3139.440000 ;
+ RECT 162.950000 3138.960000 163.950000 3139.440000 ;
+ RECT 162.950000 3128.080000 163.950000 3128.560000 ;
+ RECT 167.080000 3133.520000 168.180000 3134.000000 ;
+ RECT 167.080000 3128.080000 168.180000 3128.560000 ;
+ RECT 162.950000 3133.520000 163.950000 3134.000000 ;
+ RECT 162.950000 3117.200000 163.950000 3117.680000 ;
+ RECT 162.950000 3122.640000 163.950000 3123.120000 ;
+ RECT 167.080000 3122.640000 168.180000 3123.120000 ;
+ RECT 167.080000 3117.200000 168.180000 3117.680000 ;
+ RECT 162.950000 3100.880000 163.950000 3101.360000 ;
+ RECT 162.950000 3106.320000 163.950000 3106.800000 ;
+ RECT 167.080000 3106.320000 168.180000 3106.800000 ;
+ RECT 167.080000 3100.880000 168.180000 3101.360000 ;
+ RECT 167.080000 3111.760000 168.180000 3112.240000 ;
+ RECT 162.950000 3111.760000 163.950000 3112.240000 ;
+ RECT 162.950000 3090.000000 163.950000 3090.480000 ;
+ RECT 162.950000 3095.440000 163.950000 3095.920000 ;
+ RECT 167.080000 3090.000000 168.180000 3090.480000 ;
+ RECT 167.080000 3095.440000 168.180000 3095.920000 ;
+ RECT 162.950000 3079.120000 163.950000 3079.600000 ;
+ RECT 162.950000 3084.560000 163.950000 3085.040000 ;
+ RECT 167.080000 3079.120000 168.180000 3079.600000 ;
+ RECT 167.080000 3084.560000 168.180000 3085.040000 ;
+ RECT 167.080000 3073.680000 168.180000 3074.160000 ;
+ RECT 167.080000 3068.240000 168.180000 3068.720000 ;
+ RECT 162.950000 3073.680000 163.950000 3074.160000 ;
+ RECT 162.950000 3068.240000 163.950000 3068.720000 ;
+ RECT 167.080000 3062.800000 168.180000 3063.280000 ;
+ RECT 162.950000 3062.800000 163.950000 3063.280000 ;
+ RECT 162.950000 3051.920000 163.950000 3052.400000 ;
+ RECT 162.950000 3057.360000 163.950000 3057.840000 ;
+ RECT 167.080000 3057.360000 168.180000 3057.840000 ;
+ RECT 167.080000 3051.920000 168.180000 3052.400000 ;
+ RECT 236.330000 3041.040000 237.330000 3041.520000 ;
+ RECT 236.330000 3046.480000 237.330000 3046.960000 ;
+ RECT 236.330000 3024.720000 237.330000 3025.200000 ;
+ RECT 236.330000 3030.160000 237.330000 3030.640000 ;
+ RECT 236.330000 3035.600000 237.330000 3036.080000 ;
+ RECT 212.080000 3046.480000 213.180000 3046.960000 ;
+ RECT 212.080000 3041.040000 213.180000 3041.520000 ;
+ RECT 212.080000 3035.600000 213.180000 3036.080000 ;
+ RECT 212.080000 3030.160000 213.180000 3030.640000 ;
+ RECT 212.080000 3024.720000 213.180000 3025.200000 ;
+ RECT 236.330000 3013.840000 237.330000 3014.320000 ;
+ RECT 236.330000 3019.280000 237.330000 3019.760000 ;
+ RECT 236.330000 3002.960000 237.330000 3003.440000 ;
+ RECT 236.330000 3008.400000 237.330000 3008.880000 ;
+ RECT 212.080000 3019.280000 213.180000 3019.760000 ;
+ RECT 212.080000 3013.840000 213.180000 3014.320000 ;
+ RECT 212.080000 3008.400000 213.180000 3008.880000 ;
+ RECT 212.080000 3002.960000 213.180000 3003.440000 ;
+ RECT 236.330000 2992.080000 237.330000 2992.560000 ;
+ RECT 236.330000 2997.520000 237.330000 2998.000000 ;
+ RECT 236.330000 2975.760000 237.330000 2976.240000 ;
+ RECT 236.330000 2981.200000 237.330000 2981.680000 ;
+ RECT 236.330000 2986.640000 237.330000 2987.120000 ;
+ RECT 212.080000 2975.760000 213.180000 2976.240000 ;
+ RECT 212.080000 2981.200000 213.180000 2981.680000 ;
+ RECT 212.080000 2986.640000 213.180000 2987.120000 ;
+ RECT 212.080000 2992.080000 213.180000 2992.560000 ;
+ RECT 212.080000 2997.520000 213.180000 2998.000000 ;
+ RECT 236.330000 2964.880000 237.330000 2965.360000 ;
+ RECT 236.330000 2970.320000 237.330000 2970.800000 ;
+ RECT 236.330000 2954.000000 237.330000 2954.480000 ;
+ RECT 236.330000 2959.440000 237.330000 2959.920000 ;
+ RECT 212.080000 2964.880000 213.180000 2965.360000 ;
+ RECT 212.080000 2959.440000 213.180000 2959.920000 ;
+ RECT 212.080000 2954.000000 213.180000 2954.480000 ;
+ RECT 212.080000 2970.320000 213.180000 2970.800000 ;
+ RECT 162.950000 3041.040000 163.950000 3041.520000 ;
+ RECT 162.950000 3046.480000 163.950000 3046.960000 ;
+ RECT 167.080000 3046.480000 168.180000 3046.960000 ;
+ RECT 167.080000 3041.040000 168.180000 3041.520000 ;
+ RECT 167.080000 3035.600000 168.180000 3036.080000 ;
+ RECT 162.950000 3035.600000 163.950000 3036.080000 ;
+ RECT 167.080000 3024.720000 168.180000 3025.200000 ;
+ RECT 162.950000 3024.720000 163.950000 3025.200000 ;
+ RECT 162.950000 3030.160000 163.950000 3030.640000 ;
+ RECT 167.080000 3030.160000 168.180000 3030.640000 ;
+ RECT 162.950000 3013.840000 163.950000 3014.320000 ;
+ RECT 162.950000 3019.280000 163.950000 3019.760000 ;
+ RECT 167.080000 3019.280000 168.180000 3019.760000 ;
+ RECT 167.080000 3013.840000 168.180000 3014.320000 ;
+ RECT 162.950000 3002.960000 163.950000 3003.440000 ;
+ RECT 162.950000 3008.400000 163.950000 3008.880000 ;
+ RECT 167.080000 3008.400000 168.180000 3008.880000 ;
+ RECT 167.080000 3002.960000 168.180000 3003.440000 ;
+ RECT 162.950000 2992.080000 163.950000 2992.560000 ;
+ RECT 162.950000 2997.520000 163.950000 2998.000000 ;
+ RECT 167.080000 2992.080000 168.180000 2992.560000 ;
+ RECT 167.080000 2997.520000 168.180000 2998.000000 ;
+ RECT 162.950000 2975.760000 163.950000 2976.240000 ;
+ RECT 162.950000 2981.200000 163.950000 2981.680000 ;
+ RECT 167.080000 2975.760000 168.180000 2976.240000 ;
+ RECT 167.080000 2981.200000 168.180000 2981.680000 ;
+ RECT 167.080000 2986.640000 168.180000 2987.120000 ;
+ RECT 162.950000 2986.640000 163.950000 2987.120000 ;
+ RECT 162.950000 2964.880000 163.950000 2965.360000 ;
+ RECT 162.950000 2970.320000 163.950000 2970.800000 ;
+ RECT 167.080000 2964.880000 168.180000 2965.360000 ;
+ RECT 167.080000 2970.320000 168.180000 2970.800000 ;
+ RECT 167.080000 2954.000000 168.180000 2954.480000 ;
+ RECT 167.080000 2959.440000 168.180000 2959.920000 ;
+ RECT 162.950000 2959.440000 163.950000 2959.920000 ;
+ RECT 162.950000 2954.000000 163.950000 2954.480000 ;
+ RECT 160.120000 3144.360000 240.160000 3145.360000 ;
+ RECT 160.120000 2951.990000 240.160000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2949.140000 163.950000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 3148.400000 163.950000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 2949.140000 237.330000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 3148.400000 237.330000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2951.990000 161.120000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2951.990000 240.160000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 3144.360000 161.120000 3145.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 3144.360000 240.160000 3145.360000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2748.880000 163.950000 2949.140000 ;
+ RECT 236.330000 2748.880000 237.330000 2949.140000 ;
+ RECT 167.080000 2751.730000 168.180000 2945.100000 ;
+ RECT 212.080000 2751.730000 213.180000 2945.100000 ;
+ LAYER met3 ;
+ RECT 236.330000 2938.700000 237.330000 2939.180000 ;
+ RECT 236.330000 2927.820000 237.330000 2928.300000 ;
+ RECT 236.330000 2933.260000 237.330000 2933.740000 ;
+ RECT 212.080000 2938.700000 213.180000 2939.180000 ;
+ RECT 212.080000 2933.260000 213.180000 2933.740000 ;
+ RECT 212.080000 2927.820000 213.180000 2928.300000 ;
+ RECT 236.330000 2916.940000 237.330000 2917.420000 ;
+ RECT 236.330000 2922.380000 237.330000 2922.860000 ;
+ RECT 236.330000 2900.620000 237.330000 2901.100000 ;
+ RECT 236.330000 2906.060000 237.330000 2906.540000 ;
+ RECT 236.330000 2911.500000 237.330000 2911.980000 ;
+ RECT 212.080000 2922.380000 213.180000 2922.860000 ;
+ RECT 212.080000 2916.940000 213.180000 2917.420000 ;
+ RECT 212.080000 2911.500000 213.180000 2911.980000 ;
+ RECT 212.080000 2906.060000 213.180000 2906.540000 ;
+ RECT 212.080000 2900.620000 213.180000 2901.100000 ;
+ RECT 236.330000 2889.740000 237.330000 2890.220000 ;
+ RECT 236.330000 2895.180000 237.330000 2895.660000 ;
+ RECT 236.330000 2878.860000 237.330000 2879.340000 ;
+ RECT 236.330000 2884.300000 237.330000 2884.780000 ;
+ RECT 212.080000 2878.860000 213.180000 2879.340000 ;
+ RECT 212.080000 2884.300000 213.180000 2884.780000 ;
+ RECT 212.080000 2889.740000 213.180000 2890.220000 ;
+ RECT 212.080000 2895.180000 213.180000 2895.660000 ;
+ RECT 236.330000 2862.540000 237.330000 2863.020000 ;
+ RECT 236.330000 2867.980000 237.330000 2868.460000 ;
+ RECT 236.330000 2873.420000 237.330000 2873.900000 ;
+ RECT 236.330000 2851.660000 237.330000 2852.140000 ;
+ RECT 236.330000 2857.100000 237.330000 2857.580000 ;
+ RECT 212.080000 2862.540000 213.180000 2863.020000 ;
+ RECT 212.080000 2857.100000 213.180000 2857.580000 ;
+ RECT 212.080000 2851.660000 213.180000 2852.140000 ;
+ RECT 212.080000 2867.980000 213.180000 2868.460000 ;
+ RECT 212.080000 2873.420000 213.180000 2873.900000 ;
+ RECT 167.080000 2938.700000 168.180000 2939.180000 ;
+ RECT 162.950000 2938.700000 163.950000 2939.180000 ;
+ RECT 162.950000 2927.820000 163.950000 2928.300000 ;
+ RECT 167.080000 2933.260000 168.180000 2933.740000 ;
+ RECT 167.080000 2927.820000 168.180000 2928.300000 ;
+ RECT 162.950000 2933.260000 163.950000 2933.740000 ;
+ RECT 162.950000 2916.940000 163.950000 2917.420000 ;
+ RECT 162.950000 2922.380000 163.950000 2922.860000 ;
+ RECT 167.080000 2922.380000 168.180000 2922.860000 ;
+ RECT 167.080000 2916.940000 168.180000 2917.420000 ;
+ RECT 162.950000 2900.620000 163.950000 2901.100000 ;
+ RECT 162.950000 2906.060000 163.950000 2906.540000 ;
+ RECT 167.080000 2906.060000 168.180000 2906.540000 ;
+ RECT 167.080000 2900.620000 168.180000 2901.100000 ;
+ RECT 167.080000 2911.500000 168.180000 2911.980000 ;
+ RECT 162.950000 2911.500000 163.950000 2911.980000 ;
+ RECT 162.950000 2889.740000 163.950000 2890.220000 ;
+ RECT 162.950000 2895.180000 163.950000 2895.660000 ;
+ RECT 167.080000 2889.740000 168.180000 2890.220000 ;
+ RECT 167.080000 2895.180000 168.180000 2895.660000 ;
+ RECT 162.950000 2878.860000 163.950000 2879.340000 ;
+ RECT 162.950000 2884.300000 163.950000 2884.780000 ;
+ RECT 167.080000 2878.860000 168.180000 2879.340000 ;
+ RECT 167.080000 2884.300000 168.180000 2884.780000 ;
+ RECT 167.080000 2873.420000 168.180000 2873.900000 ;
+ RECT 167.080000 2867.980000 168.180000 2868.460000 ;
+ RECT 162.950000 2873.420000 163.950000 2873.900000 ;
+ RECT 162.950000 2867.980000 163.950000 2868.460000 ;
+ RECT 167.080000 2862.540000 168.180000 2863.020000 ;
+ RECT 162.950000 2862.540000 163.950000 2863.020000 ;
+ RECT 162.950000 2851.660000 163.950000 2852.140000 ;
+ RECT 162.950000 2857.100000 163.950000 2857.580000 ;
+ RECT 167.080000 2857.100000 168.180000 2857.580000 ;
+ RECT 167.080000 2851.660000 168.180000 2852.140000 ;
+ RECT 236.330000 2840.780000 237.330000 2841.260000 ;
+ RECT 236.330000 2846.220000 237.330000 2846.700000 ;
+ RECT 236.330000 2824.460000 237.330000 2824.940000 ;
+ RECT 236.330000 2829.900000 237.330000 2830.380000 ;
+ RECT 236.330000 2835.340000 237.330000 2835.820000 ;
+ RECT 212.080000 2846.220000 213.180000 2846.700000 ;
+ RECT 212.080000 2840.780000 213.180000 2841.260000 ;
+ RECT 212.080000 2835.340000 213.180000 2835.820000 ;
+ RECT 212.080000 2829.900000 213.180000 2830.380000 ;
+ RECT 212.080000 2824.460000 213.180000 2824.940000 ;
+ RECT 236.330000 2813.580000 237.330000 2814.060000 ;
+ RECT 236.330000 2819.020000 237.330000 2819.500000 ;
+ RECT 236.330000 2802.700000 237.330000 2803.180000 ;
+ RECT 236.330000 2808.140000 237.330000 2808.620000 ;
+ RECT 212.080000 2819.020000 213.180000 2819.500000 ;
+ RECT 212.080000 2813.580000 213.180000 2814.060000 ;
+ RECT 212.080000 2808.140000 213.180000 2808.620000 ;
+ RECT 212.080000 2802.700000 213.180000 2803.180000 ;
+ RECT 236.330000 2791.820000 237.330000 2792.300000 ;
+ RECT 236.330000 2797.260000 237.330000 2797.740000 ;
+ RECT 236.330000 2775.500000 237.330000 2775.980000 ;
+ RECT 236.330000 2780.940000 237.330000 2781.420000 ;
+ RECT 236.330000 2786.380000 237.330000 2786.860000 ;
+ RECT 212.080000 2775.500000 213.180000 2775.980000 ;
+ RECT 212.080000 2780.940000 213.180000 2781.420000 ;
+ RECT 212.080000 2786.380000 213.180000 2786.860000 ;
+ RECT 212.080000 2791.820000 213.180000 2792.300000 ;
+ RECT 212.080000 2797.260000 213.180000 2797.740000 ;
+ RECT 236.330000 2764.620000 237.330000 2765.100000 ;
+ RECT 236.330000 2770.060000 237.330000 2770.540000 ;
+ RECT 236.330000 2753.740000 237.330000 2754.220000 ;
+ RECT 236.330000 2759.180000 237.330000 2759.660000 ;
+ RECT 212.080000 2764.620000 213.180000 2765.100000 ;
+ RECT 212.080000 2759.180000 213.180000 2759.660000 ;
+ RECT 212.080000 2753.740000 213.180000 2754.220000 ;
+ RECT 212.080000 2770.060000 213.180000 2770.540000 ;
+ RECT 162.950000 2840.780000 163.950000 2841.260000 ;
+ RECT 162.950000 2846.220000 163.950000 2846.700000 ;
+ RECT 167.080000 2846.220000 168.180000 2846.700000 ;
+ RECT 167.080000 2840.780000 168.180000 2841.260000 ;
+ RECT 167.080000 2835.340000 168.180000 2835.820000 ;
+ RECT 162.950000 2835.340000 163.950000 2835.820000 ;
+ RECT 167.080000 2824.460000 168.180000 2824.940000 ;
+ RECT 162.950000 2824.460000 163.950000 2824.940000 ;
+ RECT 162.950000 2829.900000 163.950000 2830.380000 ;
+ RECT 167.080000 2829.900000 168.180000 2830.380000 ;
+ RECT 162.950000 2813.580000 163.950000 2814.060000 ;
+ RECT 162.950000 2819.020000 163.950000 2819.500000 ;
+ RECT 167.080000 2819.020000 168.180000 2819.500000 ;
+ RECT 167.080000 2813.580000 168.180000 2814.060000 ;
+ RECT 162.950000 2802.700000 163.950000 2803.180000 ;
+ RECT 162.950000 2808.140000 163.950000 2808.620000 ;
+ RECT 167.080000 2808.140000 168.180000 2808.620000 ;
+ RECT 167.080000 2802.700000 168.180000 2803.180000 ;
+ RECT 162.950000 2791.820000 163.950000 2792.300000 ;
+ RECT 162.950000 2797.260000 163.950000 2797.740000 ;
+ RECT 167.080000 2791.820000 168.180000 2792.300000 ;
+ RECT 167.080000 2797.260000 168.180000 2797.740000 ;
+ RECT 162.950000 2775.500000 163.950000 2775.980000 ;
+ RECT 162.950000 2780.940000 163.950000 2781.420000 ;
+ RECT 167.080000 2775.500000 168.180000 2775.980000 ;
+ RECT 167.080000 2780.940000 168.180000 2781.420000 ;
+ RECT 167.080000 2786.380000 168.180000 2786.860000 ;
+ RECT 162.950000 2786.380000 163.950000 2786.860000 ;
+ RECT 162.950000 2764.620000 163.950000 2765.100000 ;
+ RECT 162.950000 2770.060000 163.950000 2770.540000 ;
+ RECT 167.080000 2764.620000 168.180000 2765.100000 ;
+ RECT 167.080000 2770.060000 168.180000 2770.540000 ;
+ RECT 167.080000 2753.740000 168.180000 2754.220000 ;
+ RECT 167.080000 2759.180000 168.180000 2759.660000 ;
+ RECT 162.950000 2759.180000 163.950000 2759.660000 ;
+ RECT 162.950000 2753.740000 163.950000 2754.220000 ;
+ RECT 160.120000 2944.100000 240.160000 2945.100000 ;
+ RECT 160.120000 2751.730000 240.160000 2752.730000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2748.880000 163.950000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2948.140000 163.950000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 2748.880000 237.330000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 2948.140000 237.330000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2751.730000 161.120000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2751.730000 240.160000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2944.100000 161.120000 2945.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2944.100000 240.160000 2945.100000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2548.620000 163.950000 2748.880000 ;
+ RECT 236.330000 2548.620000 237.330000 2748.880000 ;
+ RECT 167.080000 2551.470000 168.180000 2744.840000 ;
+ RECT 212.080000 2551.470000 213.180000 2744.840000 ;
+ LAYER met3 ;
+ RECT 236.330000 2738.440000 237.330000 2738.920000 ;
+ RECT 236.330000 2727.560000 237.330000 2728.040000 ;
+ RECT 236.330000 2733.000000 237.330000 2733.480000 ;
+ RECT 212.080000 2738.440000 213.180000 2738.920000 ;
+ RECT 212.080000 2733.000000 213.180000 2733.480000 ;
+ RECT 212.080000 2727.560000 213.180000 2728.040000 ;
+ RECT 236.330000 2716.680000 237.330000 2717.160000 ;
+ RECT 236.330000 2722.120000 237.330000 2722.600000 ;
+ RECT 236.330000 2700.360000 237.330000 2700.840000 ;
+ RECT 236.330000 2705.800000 237.330000 2706.280000 ;
+ RECT 236.330000 2711.240000 237.330000 2711.720000 ;
+ RECT 212.080000 2722.120000 213.180000 2722.600000 ;
+ RECT 212.080000 2716.680000 213.180000 2717.160000 ;
+ RECT 212.080000 2711.240000 213.180000 2711.720000 ;
+ RECT 212.080000 2705.800000 213.180000 2706.280000 ;
+ RECT 212.080000 2700.360000 213.180000 2700.840000 ;
+ RECT 236.330000 2689.480000 237.330000 2689.960000 ;
+ RECT 236.330000 2694.920000 237.330000 2695.400000 ;
+ RECT 236.330000 2678.600000 237.330000 2679.080000 ;
+ RECT 236.330000 2684.040000 237.330000 2684.520000 ;
+ RECT 212.080000 2678.600000 213.180000 2679.080000 ;
+ RECT 212.080000 2684.040000 213.180000 2684.520000 ;
+ RECT 212.080000 2689.480000 213.180000 2689.960000 ;
+ RECT 212.080000 2694.920000 213.180000 2695.400000 ;
+ RECT 236.330000 2662.280000 237.330000 2662.760000 ;
+ RECT 236.330000 2667.720000 237.330000 2668.200000 ;
+ RECT 236.330000 2673.160000 237.330000 2673.640000 ;
+ RECT 236.330000 2651.400000 237.330000 2651.880000 ;
+ RECT 236.330000 2656.840000 237.330000 2657.320000 ;
+ RECT 212.080000 2662.280000 213.180000 2662.760000 ;
+ RECT 212.080000 2656.840000 213.180000 2657.320000 ;
+ RECT 212.080000 2651.400000 213.180000 2651.880000 ;
+ RECT 212.080000 2667.720000 213.180000 2668.200000 ;
+ RECT 212.080000 2673.160000 213.180000 2673.640000 ;
+ RECT 167.080000 2738.440000 168.180000 2738.920000 ;
+ RECT 162.950000 2738.440000 163.950000 2738.920000 ;
+ RECT 162.950000 2727.560000 163.950000 2728.040000 ;
+ RECT 167.080000 2733.000000 168.180000 2733.480000 ;
+ RECT 167.080000 2727.560000 168.180000 2728.040000 ;
+ RECT 162.950000 2733.000000 163.950000 2733.480000 ;
+ RECT 162.950000 2716.680000 163.950000 2717.160000 ;
+ RECT 162.950000 2722.120000 163.950000 2722.600000 ;
+ RECT 167.080000 2722.120000 168.180000 2722.600000 ;
+ RECT 167.080000 2716.680000 168.180000 2717.160000 ;
+ RECT 162.950000 2700.360000 163.950000 2700.840000 ;
+ RECT 162.950000 2705.800000 163.950000 2706.280000 ;
+ RECT 167.080000 2705.800000 168.180000 2706.280000 ;
+ RECT 167.080000 2700.360000 168.180000 2700.840000 ;
+ RECT 167.080000 2711.240000 168.180000 2711.720000 ;
+ RECT 162.950000 2711.240000 163.950000 2711.720000 ;
+ RECT 162.950000 2689.480000 163.950000 2689.960000 ;
+ RECT 162.950000 2694.920000 163.950000 2695.400000 ;
+ RECT 167.080000 2689.480000 168.180000 2689.960000 ;
+ RECT 167.080000 2694.920000 168.180000 2695.400000 ;
+ RECT 162.950000 2678.600000 163.950000 2679.080000 ;
+ RECT 162.950000 2684.040000 163.950000 2684.520000 ;
+ RECT 167.080000 2678.600000 168.180000 2679.080000 ;
+ RECT 167.080000 2684.040000 168.180000 2684.520000 ;
+ RECT 167.080000 2673.160000 168.180000 2673.640000 ;
+ RECT 167.080000 2667.720000 168.180000 2668.200000 ;
+ RECT 162.950000 2673.160000 163.950000 2673.640000 ;
+ RECT 162.950000 2667.720000 163.950000 2668.200000 ;
+ RECT 167.080000 2662.280000 168.180000 2662.760000 ;
+ RECT 162.950000 2662.280000 163.950000 2662.760000 ;
+ RECT 162.950000 2651.400000 163.950000 2651.880000 ;
+ RECT 162.950000 2656.840000 163.950000 2657.320000 ;
+ RECT 167.080000 2656.840000 168.180000 2657.320000 ;
+ RECT 167.080000 2651.400000 168.180000 2651.880000 ;
+ RECT 236.330000 2640.520000 237.330000 2641.000000 ;
+ RECT 236.330000 2645.960000 237.330000 2646.440000 ;
+ RECT 236.330000 2624.200000 237.330000 2624.680000 ;
+ RECT 236.330000 2629.640000 237.330000 2630.120000 ;
+ RECT 236.330000 2635.080000 237.330000 2635.560000 ;
+ RECT 212.080000 2645.960000 213.180000 2646.440000 ;
+ RECT 212.080000 2640.520000 213.180000 2641.000000 ;
+ RECT 212.080000 2635.080000 213.180000 2635.560000 ;
+ RECT 212.080000 2629.640000 213.180000 2630.120000 ;
+ RECT 212.080000 2624.200000 213.180000 2624.680000 ;
+ RECT 236.330000 2613.320000 237.330000 2613.800000 ;
+ RECT 236.330000 2618.760000 237.330000 2619.240000 ;
+ RECT 236.330000 2602.440000 237.330000 2602.920000 ;
+ RECT 236.330000 2607.880000 237.330000 2608.360000 ;
+ RECT 212.080000 2618.760000 213.180000 2619.240000 ;
+ RECT 212.080000 2613.320000 213.180000 2613.800000 ;
+ RECT 212.080000 2607.880000 213.180000 2608.360000 ;
+ RECT 212.080000 2602.440000 213.180000 2602.920000 ;
+ RECT 236.330000 2591.560000 237.330000 2592.040000 ;
+ RECT 236.330000 2597.000000 237.330000 2597.480000 ;
+ RECT 236.330000 2575.240000 237.330000 2575.720000 ;
+ RECT 236.330000 2580.680000 237.330000 2581.160000 ;
+ RECT 236.330000 2586.120000 237.330000 2586.600000 ;
+ RECT 212.080000 2575.240000 213.180000 2575.720000 ;
+ RECT 212.080000 2580.680000 213.180000 2581.160000 ;
+ RECT 212.080000 2586.120000 213.180000 2586.600000 ;
+ RECT 212.080000 2591.560000 213.180000 2592.040000 ;
+ RECT 212.080000 2597.000000 213.180000 2597.480000 ;
+ RECT 236.330000 2564.360000 237.330000 2564.840000 ;
+ RECT 236.330000 2569.800000 237.330000 2570.280000 ;
+ RECT 236.330000 2553.480000 237.330000 2553.960000 ;
+ RECT 236.330000 2558.920000 237.330000 2559.400000 ;
+ RECT 212.080000 2564.360000 213.180000 2564.840000 ;
+ RECT 212.080000 2558.920000 213.180000 2559.400000 ;
+ RECT 212.080000 2553.480000 213.180000 2553.960000 ;
+ RECT 212.080000 2569.800000 213.180000 2570.280000 ;
+ RECT 162.950000 2640.520000 163.950000 2641.000000 ;
+ RECT 162.950000 2645.960000 163.950000 2646.440000 ;
+ RECT 167.080000 2645.960000 168.180000 2646.440000 ;
+ RECT 167.080000 2640.520000 168.180000 2641.000000 ;
+ RECT 167.080000 2635.080000 168.180000 2635.560000 ;
+ RECT 162.950000 2635.080000 163.950000 2635.560000 ;
+ RECT 167.080000 2624.200000 168.180000 2624.680000 ;
+ RECT 162.950000 2624.200000 163.950000 2624.680000 ;
+ RECT 162.950000 2629.640000 163.950000 2630.120000 ;
+ RECT 167.080000 2629.640000 168.180000 2630.120000 ;
+ RECT 162.950000 2613.320000 163.950000 2613.800000 ;
+ RECT 162.950000 2618.760000 163.950000 2619.240000 ;
+ RECT 167.080000 2618.760000 168.180000 2619.240000 ;
+ RECT 167.080000 2613.320000 168.180000 2613.800000 ;
+ RECT 162.950000 2602.440000 163.950000 2602.920000 ;
+ RECT 162.950000 2607.880000 163.950000 2608.360000 ;
+ RECT 167.080000 2607.880000 168.180000 2608.360000 ;
+ RECT 167.080000 2602.440000 168.180000 2602.920000 ;
+ RECT 162.950000 2591.560000 163.950000 2592.040000 ;
+ RECT 162.950000 2597.000000 163.950000 2597.480000 ;
+ RECT 167.080000 2591.560000 168.180000 2592.040000 ;
+ RECT 167.080000 2597.000000 168.180000 2597.480000 ;
+ RECT 162.950000 2575.240000 163.950000 2575.720000 ;
+ RECT 162.950000 2580.680000 163.950000 2581.160000 ;
+ RECT 167.080000 2575.240000 168.180000 2575.720000 ;
+ RECT 167.080000 2580.680000 168.180000 2581.160000 ;
+ RECT 167.080000 2586.120000 168.180000 2586.600000 ;
+ RECT 162.950000 2586.120000 163.950000 2586.600000 ;
+ RECT 162.950000 2564.360000 163.950000 2564.840000 ;
+ RECT 162.950000 2569.800000 163.950000 2570.280000 ;
+ RECT 167.080000 2564.360000 168.180000 2564.840000 ;
+ RECT 167.080000 2569.800000 168.180000 2570.280000 ;
+ RECT 167.080000 2553.480000 168.180000 2553.960000 ;
+ RECT 167.080000 2558.920000 168.180000 2559.400000 ;
+ RECT 162.950000 2558.920000 163.950000 2559.400000 ;
+ RECT 162.950000 2553.480000 163.950000 2553.960000 ;
+ RECT 160.120000 2743.840000 240.160000 2744.840000 ;
+ RECT 160.120000 2551.470000 240.160000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2548.620000 163.950000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2747.880000 163.950000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 2548.620000 237.330000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 2747.880000 237.330000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2551.470000 161.120000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2551.470000 240.160000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2743.840000 161.120000 2744.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2743.840000 240.160000 2744.840000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2348.360000 163.950000 2548.620000 ;
+ RECT 236.330000 2348.360000 237.330000 2548.620000 ;
+ RECT 167.080000 2351.210000 168.180000 2544.580000 ;
+ RECT 212.080000 2351.210000 213.180000 2544.580000 ;
+ LAYER met3 ;
+ RECT 236.330000 2538.180000 237.330000 2538.660000 ;
+ RECT 236.330000 2527.300000 237.330000 2527.780000 ;
+ RECT 236.330000 2532.740000 237.330000 2533.220000 ;
+ RECT 212.080000 2538.180000 213.180000 2538.660000 ;
+ RECT 212.080000 2532.740000 213.180000 2533.220000 ;
+ RECT 212.080000 2527.300000 213.180000 2527.780000 ;
+ RECT 236.330000 2516.420000 237.330000 2516.900000 ;
+ RECT 236.330000 2521.860000 237.330000 2522.340000 ;
+ RECT 236.330000 2500.100000 237.330000 2500.580000 ;
+ RECT 236.330000 2505.540000 237.330000 2506.020000 ;
+ RECT 236.330000 2510.980000 237.330000 2511.460000 ;
+ RECT 212.080000 2521.860000 213.180000 2522.340000 ;
+ RECT 212.080000 2516.420000 213.180000 2516.900000 ;
+ RECT 212.080000 2510.980000 213.180000 2511.460000 ;
+ RECT 212.080000 2505.540000 213.180000 2506.020000 ;
+ RECT 212.080000 2500.100000 213.180000 2500.580000 ;
+ RECT 236.330000 2489.220000 237.330000 2489.700000 ;
+ RECT 236.330000 2494.660000 237.330000 2495.140000 ;
+ RECT 236.330000 2478.340000 237.330000 2478.820000 ;
+ RECT 236.330000 2483.780000 237.330000 2484.260000 ;
+ RECT 212.080000 2478.340000 213.180000 2478.820000 ;
+ RECT 212.080000 2483.780000 213.180000 2484.260000 ;
+ RECT 212.080000 2489.220000 213.180000 2489.700000 ;
+ RECT 212.080000 2494.660000 213.180000 2495.140000 ;
+ RECT 236.330000 2462.020000 237.330000 2462.500000 ;
+ RECT 236.330000 2467.460000 237.330000 2467.940000 ;
+ RECT 236.330000 2472.900000 237.330000 2473.380000 ;
+ RECT 236.330000 2451.140000 237.330000 2451.620000 ;
+ RECT 236.330000 2456.580000 237.330000 2457.060000 ;
+ RECT 212.080000 2462.020000 213.180000 2462.500000 ;
+ RECT 212.080000 2456.580000 213.180000 2457.060000 ;
+ RECT 212.080000 2451.140000 213.180000 2451.620000 ;
+ RECT 212.080000 2467.460000 213.180000 2467.940000 ;
+ RECT 212.080000 2472.900000 213.180000 2473.380000 ;
+ RECT 167.080000 2538.180000 168.180000 2538.660000 ;
+ RECT 162.950000 2538.180000 163.950000 2538.660000 ;
+ RECT 162.950000 2527.300000 163.950000 2527.780000 ;
+ RECT 167.080000 2532.740000 168.180000 2533.220000 ;
+ RECT 167.080000 2527.300000 168.180000 2527.780000 ;
+ RECT 162.950000 2532.740000 163.950000 2533.220000 ;
+ RECT 162.950000 2516.420000 163.950000 2516.900000 ;
+ RECT 162.950000 2521.860000 163.950000 2522.340000 ;
+ RECT 167.080000 2521.860000 168.180000 2522.340000 ;
+ RECT 167.080000 2516.420000 168.180000 2516.900000 ;
+ RECT 162.950000 2500.100000 163.950000 2500.580000 ;
+ RECT 162.950000 2505.540000 163.950000 2506.020000 ;
+ RECT 167.080000 2505.540000 168.180000 2506.020000 ;
+ RECT 167.080000 2500.100000 168.180000 2500.580000 ;
+ RECT 167.080000 2510.980000 168.180000 2511.460000 ;
+ RECT 162.950000 2510.980000 163.950000 2511.460000 ;
+ RECT 162.950000 2489.220000 163.950000 2489.700000 ;
+ RECT 162.950000 2494.660000 163.950000 2495.140000 ;
+ RECT 167.080000 2489.220000 168.180000 2489.700000 ;
+ RECT 167.080000 2494.660000 168.180000 2495.140000 ;
+ RECT 162.950000 2478.340000 163.950000 2478.820000 ;
+ RECT 162.950000 2483.780000 163.950000 2484.260000 ;
+ RECT 167.080000 2478.340000 168.180000 2478.820000 ;
+ RECT 167.080000 2483.780000 168.180000 2484.260000 ;
+ RECT 167.080000 2472.900000 168.180000 2473.380000 ;
+ RECT 167.080000 2467.460000 168.180000 2467.940000 ;
+ RECT 162.950000 2472.900000 163.950000 2473.380000 ;
+ RECT 162.950000 2467.460000 163.950000 2467.940000 ;
+ RECT 167.080000 2462.020000 168.180000 2462.500000 ;
+ RECT 162.950000 2462.020000 163.950000 2462.500000 ;
+ RECT 162.950000 2451.140000 163.950000 2451.620000 ;
+ RECT 162.950000 2456.580000 163.950000 2457.060000 ;
+ RECT 167.080000 2456.580000 168.180000 2457.060000 ;
+ RECT 167.080000 2451.140000 168.180000 2451.620000 ;
+ RECT 236.330000 2440.260000 237.330000 2440.740000 ;
+ RECT 236.330000 2445.700000 237.330000 2446.180000 ;
+ RECT 236.330000 2423.940000 237.330000 2424.420000 ;
+ RECT 236.330000 2429.380000 237.330000 2429.860000 ;
+ RECT 236.330000 2434.820000 237.330000 2435.300000 ;
+ RECT 212.080000 2445.700000 213.180000 2446.180000 ;
+ RECT 212.080000 2440.260000 213.180000 2440.740000 ;
+ RECT 212.080000 2434.820000 213.180000 2435.300000 ;
+ RECT 212.080000 2429.380000 213.180000 2429.860000 ;
+ RECT 212.080000 2423.940000 213.180000 2424.420000 ;
+ RECT 236.330000 2413.060000 237.330000 2413.540000 ;
+ RECT 236.330000 2418.500000 237.330000 2418.980000 ;
+ RECT 236.330000 2402.180000 237.330000 2402.660000 ;
+ RECT 236.330000 2407.620000 237.330000 2408.100000 ;
+ RECT 212.080000 2418.500000 213.180000 2418.980000 ;
+ RECT 212.080000 2413.060000 213.180000 2413.540000 ;
+ RECT 212.080000 2407.620000 213.180000 2408.100000 ;
+ RECT 212.080000 2402.180000 213.180000 2402.660000 ;
+ RECT 236.330000 2391.300000 237.330000 2391.780000 ;
+ RECT 236.330000 2396.740000 237.330000 2397.220000 ;
+ RECT 236.330000 2374.980000 237.330000 2375.460000 ;
+ RECT 236.330000 2380.420000 237.330000 2380.900000 ;
+ RECT 236.330000 2385.860000 237.330000 2386.340000 ;
+ RECT 212.080000 2374.980000 213.180000 2375.460000 ;
+ RECT 212.080000 2380.420000 213.180000 2380.900000 ;
+ RECT 212.080000 2385.860000 213.180000 2386.340000 ;
+ RECT 212.080000 2391.300000 213.180000 2391.780000 ;
+ RECT 212.080000 2396.740000 213.180000 2397.220000 ;
+ RECT 236.330000 2364.100000 237.330000 2364.580000 ;
+ RECT 236.330000 2369.540000 237.330000 2370.020000 ;
+ RECT 236.330000 2353.220000 237.330000 2353.700000 ;
+ RECT 236.330000 2358.660000 237.330000 2359.140000 ;
+ RECT 212.080000 2364.100000 213.180000 2364.580000 ;
+ RECT 212.080000 2358.660000 213.180000 2359.140000 ;
+ RECT 212.080000 2353.220000 213.180000 2353.700000 ;
+ RECT 212.080000 2369.540000 213.180000 2370.020000 ;
+ RECT 162.950000 2440.260000 163.950000 2440.740000 ;
+ RECT 162.950000 2445.700000 163.950000 2446.180000 ;
+ RECT 167.080000 2445.700000 168.180000 2446.180000 ;
+ RECT 167.080000 2440.260000 168.180000 2440.740000 ;
+ RECT 167.080000 2434.820000 168.180000 2435.300000 ;
+ RECT 162.950000 2434.820000 163.950000 2435.300000 ;
+ RECT 167.080000 2423.940000 168.180000 2424.420000 ;
+ RECT 162.950000 2423.940000 163.950000 2424.420000 ;
+ RECT 162.950000 2429.380000 163.950000 2429.860000 ;
+ RECT 167.080000 2429.380000 168.180000 2429.860000 ;
+ RECT 162.950000 2413.060000 163.950000 2413.540000 ;
+ RECT 162.950000 2418.500000 163.950000 2418.980000 ;
+ RECT 167.080000 2418.500000 168.180000 2418.980000 ;
+ RECT 167.080000 2413.060000 168.180000 2413.540000 ;
+ RECT 162.950000 2402.180000 163.950000 2402.660000 ;
+ RECT 162.950000 2407.620000 163.950000 2408.100000 ;
+ RECT 167.080000 2407.620000 168.180000 2408.100000 ;
+ RECT 167.080000 2402.180000 168.180000 2402.660000 ;
+ RECT 162.950000 2391.300000 163.950000 2391.780000 ;
+ RECT 162.950000 2396.740000 163.950000 2397.220000 ;
+ RECT 167.080000 2391.300000 168.180000 2391.780000 ;
+ RECT 167.080000 2396.740000 168.180000 2397.220000 ;
+ RECT 162.950000 2374.980000 163.950000 2375.460000 ;
+ RECT 162.950000 2380.420000 163.950000 2380.900000 ;
+ RECT 167.080000 2374.980000 168.180000 2375.460000 ;
+ RECT 167.080000 2380.420000 168.180000 2380.900000 ;
+ RECT 167.080000 2385.860000 168.180000 2386.340000 ;
+ RECT 162.950000 2385.860000 163.950000 2386.340000 ;
+ RECT 162.950000 2364.100000 163.950000 2364.580000 ;
+ RECT 162.950000 2369.540000 163.950000 2370.020000 ;
+ RECT 167.080000 2364.100000 168.180000 2364.580000 ;
+ RECT 167.080000 2369.540000 168.180000 2370.020000 ;
+ RECT 167.080000 2353.220000 168.180000 2353.700000 ;
+ RECT 167.080000 2358.660000 168.180000 2359.140000 ;
+ RECT 162.950000 2358.660000 163.950000 2359.140000 ;
+ RECT 162.950000 2353.220000 163.950000 2353.700000 ;
+ RECT 160.120000 2543.580000 240.160000 2544.580000 ;
+ RECT 160.120000 2351.210000 240.160000 2352.210000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2348.360000 163.950000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2547.620000 163.950000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 2348.360000 237.330000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 2547.620000 237.330000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2351.210000 161.120000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2351.210000 240.160000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2543.580000 161.120000 2544.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2543.580000 240.160000 2544.580000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2148.100000 163.950000 2348.360000 ;
+ RECT 236.330000 2148.100000 237.330000 2348.360000 ;
+ RECT 167.080000 2150.950000 168.180000 2344.320000 ;
+ RECT 212.080000 2150.950000 213.180000 2344.320000 ;
+ LAYER met3 ;
+ RECT 236.330000 2337.920000 237.330000 2338.400000 ;
+ RECT 236.330000 2327.040000 237.330000 2327.520000 ;
+ RECT 236.330000 2332.480000 237.330000 2332.960000 ;
+ RECT 212.080000 2337.920000 213.180000 2338.400000 ;
+ RECT 212.080000 2332.480000 213.180000 2332.960000 ;
+ RECT 212.080000 2327.040000 213.180000 2327.520000 ;
+ RECT 236.330000 2316.160000 237.330000 2316.640000 ;
+ RECT 236.330000 2321.600000 237.330000 2322.080000 ;
+ RECT 236.330000 2299.840000 237.330000 2300.320000 ;
+ RECT 236.330000 2305.280000 237.330000 2305.760000 ;
+ RECT 236.330000 2310.720000 237.330000 2311.200000 ;
+ RECT 212.080000 2321.600000 213.180000 2322.080000 ;
+ RECT 212.080000 2316.160000 213.180000 2316.640000 ;
+ RECT 212.080000 2310.720000 213.180000 2311.200000 ;
+ RECT 212.080000 2305.280000 213.180000 2305.760000 ;
+ RECT 212.080000 2299.840000 213.180000 2300.320000 ;
+ RECT 236.330000 2288.960000 237.330000 2289.440000 ;
+ RECT 236.330000 2294.400000 237.330000 2294.880000 ;
+ RECT 236.330000 2278.080000 237.330000 2278.560000 ;
+ RECT 236.330000 2283.520000 237.330000 2284.000000 ;
+ RECT 212.080000 2278.080000 213.180000 2278.560000 ;
+ RECT 212.080000 2283.520000 213.180000 2284.000000 ;
+ RECT 212.080000 2288.960000 213.180000 2289.440000 ;
+ RECT 212.080000 2294.400000 213.180000 2294.880000 ;
+ RECT 236.330000 2261.760000 237.330000 2262.240000 ;
+ RECT 236.330000 2267.200000 237.330000 2267.680000 ;
+ RECT 236.330000 2272.640000 237.330000 2273.120000 ;
+ RECT 236.330000 2250.880000 237.330000 2251.360000 ;
+ RECT 236.330000 2256.320000 237.330000 2256.800000 ;
+ RECT 212.080000 2261.760000 213.180000 2262.240000 ;
+ RECT 212.080000 2256.320000 213.180000 2256.800000 ;
+ RECT 212.080000 2250.880000 213.180000 2251.360000 ;
+ RECT 212.080000 2267.200000 213.180000 2267.680000 ;
+ RECT 212.080000 2272.640000 213.180000 2273.120000 ;
+ RECT 167.080000 2337.920000 168.180000 2338.400000 ;
+ RECT 162.950000 2337.920000 163.950000 2338.400000 ;
+ RECT 162.950000 2327.040000 163.950000 2327.520000 ;
+ RECT 167.080000 2332.480000 168.180000 2332.960000 ;
+ RECT 167.080000 2327.040000 168.180000 2327.520000 ;
+ RECT 162.950000 2332.480000 163.950000 2332.960000 ;
+ RECT 162.950000 2316.160000 163.950000 2316.640000 ;
+ RECT 162.950000 2321.600000 163.950000 2322.080000 ;
+ RECT 167.080000 2321.600000 168.180000 2322.080000 ;
+ RECT 167.080000 2316.160000 168.180000 2316.640000 ;
+ RECT 162.950000 2299.840000 163.950000 2300.320000 ;
+ RECT 162.950000 2305.280000 163.950000 2305.760000 ;
+ RECT 167.080000 2305.280000 168.180000 2305.760000 ;
+ RECT 167.080000 2299.840000 168.180000 2300.320000 ;
+ RECT 167.080000 2310.720000 168.180000 2311.200000 ;
+ RECT 162.950000 2310.720000 163.950000 2311.200000 ;
+ RECT 162.950000 2288.960000 163.950000 2289.440000 ;
+ RECT 162.950000 2294.400000 163.950000 2294.880000 ;
+ RECT 167.080000 2288.960000 168.180000 2289.440000 ;
+ RECT 167.080000 2294.400000 168.180000 2294.880000 ;
+ RECT 162.950000 2278.080000 163.950000 2278.560000 ;
+ RECT 162.950000 2283.520000 163.950000 2284.000000 ;
+ RECT 167.080000 2278.080000 168.180000 2278.560000 ;
+ RECT 167.080000 2283.520000 168.180000 2284.000000 ;
+ RECT 167.080000 2272.640000 168.180000 2273.120000 ;
+ RECT 167.080000 2267.200000 168.180000 2267.680000 ;
+ RECT 162.950000 2272.640000 163.950000 2273.120000 ;
+ RECT 162.950000 2267.200000 163.950000 2267.680000 ;
+ RECT 167.080000 2261.760000 168.180000 2262.240000 ;
+ RECT 162.950000 2261.760000 163.950000 2262.240000 ;
+ RECT 162.950000 2250.880000 163.950000 2251.360000 ;
+ RECT 162.950000 2256.320000 163.950000 2256.800000 ;
+ RECT 167.080000 2256.320000 168.180000 2256.800000 ;
+ RECT 167.080000 2250.880000 168.180000 2251.360000 ;
+ RECT 236.330000 2240.000000 237.330000 2240.480000 ;
+ RECT 236.330000 2245.440000 237.330000 2245.920000 ;
+ RECT 236.330000 2223.680000 237.330000 2224.160000 ;
+ RECT 236.330000 2229.120000 237.330000 2229.600000 ;
+ RECT 236.330000 2234.560000 237.330000 2235.040000 ;
+ RECT 212.080000 2245.440000 213.180000 2245.920000 ;
+ RECT 212.080000 2240.000000 213.180000 2240.480000 ;
+ RECT 212.080000 2234.560000 213.180000 2235.040000 ;
+ RECT 212.080000 2229.120000 213.180000 2229.600000 ;
+ RECT 212.080000 2223.680000 213.180000 2224.160000 ;
+ RECT 236.330000 2212.800000 237.330000 2213.280000 ;
+ RECT 236.330000 2218.240000 237.330000 2218.720000 ;
+ RECT 236.330000 2201.920000 237.330000 2202.400000 ;
+ RECT 236.330000 2207.360000 237.330000 2207.840000 ;
+ RECT 212.080000 2218.240000 213.180000 2218.720000 ;
+ RECT 212.080000 2212.800000 213.180000 2213.280000 ;
+ RECT 212.080000 2207.360000 213.180000 2207.840000 ;
+ RECT 212.080000 2201.920000 213.180000 2202.400000 ;
+ RECT 236.330000 2191.040000 237.330000 2191.520000 ;
+ RECT 236.330000 2196.480000 237.330000 2196.960000 ;
+ RECT 236.330000 2174.720000 237.330000 2175.200000 ;
+ RECT 236.330000 2180.160000 237.330000 2180.640000 ;
+ RECT 236.330000 2185.600000 237.330000 2186.080000 ;
+ RECT 212.080000 2174.720000 213.180000 2175.200000 ;
+ RECT 212.080000 2180.160000 213.180000 2180.640000 ;
+ RECT 212.080000 2185.600000 213.180000 2186.080000 ;
+ RECT 212.080000 2191.040000 213.180000 2191.520000 ;
+ RECT 212.080000 2196.480000 213.180000 2196.960000 ;
+ RECT 236.330000 2163.840000 237.330000 2164.320000 ;
+ RECT 236.330000 2169.280000 237.330000 2169.760000 ;
+ RECT 236.330000 2152.960000 237.330000 2153.440000 ;
+ RECT 236.330000 2158.400000 237.330000 2158.880000 ;
+ RECT 212.080000 2163.840000 213.180000 2164.320000 ;
+ RECT 212.080000 2158.400000 213.180000 2158.880000 ;
+ RECT 212.080000 2152.960000 213.180000 2153.440000 ;
+ RECT 212.080000 2169.280000 213.180000 2169.760000 ;
+ RECT 162.950000 2240.000000 163.950000 2240.480000 ;
+ RECT 162.950000 2245.440000 163.950000 2245.920000 ;
+ RECT 167.080000 2245.440000 168.180000 2245.920000 ;
+ RECT 167.080000 2240.000000 168.180000 2240.480000 ;
+ RECT 167.080000 2234.560000 168.180000 2235.040000 ;
+ RECT 162.950000 2234.560000 163.950000 2235.040000 ;
+ RECT 167.080000 2223.680000 168.180000 2224.160000 ;
+ RECT 162.950000 2223.680000 163.950000 2224.160000 ;
+ RECT 162.950000 2229.120000 163.950000 2229.600000 ;
+ RECT 167.080000 2229.120000 168.180000 2229.600000 ;
+ RECT 162.950000 2212.800000 163.950000 2213.280000 ;
+ RECT 162.950000 2218.240000 163.950000 2218.720000 ;
+ RECT 167.080000 2218.240000 168.180000 2218.720000 ;
+ RECT 167.080000 2212.800000 168.180000 2213.280000 ;
+ RECT 162.950000 2201.920000 163.950000 2202.400000 ;
+ RECT 162.950000 2207.360000 163.950000 2207.840000 ;
+ RECT 167.080000 2207.360000 168.180000 2207.840000 ;
+ RECT 167.080000 2201.920000 168.180000 2202.400000 ;
+ RECT 162.950000 2191.040000 163.950000 2191.520000 ;
+ RECT 162.950000 2196.480000 163.950000 2196.960000 ;
+ RECT 167.080000 2191.040000 168.180000 2191.520000 ;
+ RECT 167.080000 2196.480000 168.180000 2196.960000 ;
+ RECT 162.950000 2174.720000 163.950000 2175.200000 ;
+ RECT 162.950000 2180.160000 163.950000 2180.640000 ;
+ RECT 167.080000 2174.720000 168.180000 2175.200000 ;
+ RECT 167.080000 2180.160000 168.180000 2180.640000 ;
+ RECT 167.080000 2185.600000 168.180000 2186.080000 ;
+ RECT 162.950000 2185.600000 163.950000 2186.080000 ;
+ RECT 162.950000 2163.840000 163.950000 2164.320000 ;
+ RECT 162.950000 2169.280000 163.950000 2169.760000 ;
+ RECT 167.080000 2163.840000 168.180000 2164.320000 ;
+ RECT 167.080000 2169.280000 168.180000 2169.760000 ;
+ RECT 167.080000 2152.960000 168.180000 2153.440000 ;
+ RECT 167.080000 2158.400000 168.180000 2158.880000 ;
+ RECT 162.950000 2158.400000 163.950000 2158.880000 ;
+ RECT 162.950000 2152.960000 163.950000 2153.440000 ;
+ RECT 160.120000 2343.320000 240.160000 2344.320000 ;
+ RECT 160.120000 2150.950000 240.160000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2148.100000 163.950000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2347.360000 163.950000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 2148.100000 237.330000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 2347.360000 237.330000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2150.950000 161.120000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2150.950000 240.160000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2343.320000 161.120000 2344.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2343.320000 240.160000 2344.320000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1947.840000 163.950000 2148.100000 ;
+ RECT 236.330000 1947.840000 237.330000 2148.100000 ;
+ RECT 167.080000 1950.690000 168.180000 2144.060000 ;
+ RECT 212.080000 1950.690000 213.180000 2144.060000 ;
+ LAYER met3 ;
+ RECT 236.330000 2137.660000 237.330000 2138.140000 ;
+ RECT 236.330000 2126.780000 237.330000 2127.260000 ;
+ RECT 236.330000 2132.220000 237.330000 2132.700000 ;
+ RECT 212.080000 2137.660000 213.180000 2138.140000 ;
+ RECT 212.080000 2132.220000 213.180000 2132.700000 ;
+ RECT 212.080000 2126.780000 213.180000 2127.260000 ;
+ RECT 236.330000 2115.900000 237.330000 2116.380000 ;
+ RECT 236.330000 2121.340000 237.330000 2121.820000 ;
+ RECT 236.330000 2099.580000 237.330000 2100.060000 ;
+ RECT 236.330000 2105.020000 237.330000 2105.500000 ;
+ RECT 236.330000 2110.460000 237.330000 2110.940000 ;
+ RECT 212.080000 2121.340000 213.180000 2121.820000 ;
+ RECT 212.080000 2115.900000 213.180000 2116.380000 ;
+ RECT 212.080000 2110.460000 213.180000 2110.940000 ;
+ RECT 212.080000 2105.020000 213.180000 2105.500000 ;
+ RECT 212.080000 2099.580000 213.180000 2100.060000 ;
+ RECT 236.330000 2088.700000 237.330000 2089.180000 ;
+ RECT 236.330000 2094.140000 237.330000 2094.620000 ;
+ RECT 236.330000 2077.820000 237.330000 2078.300000 ;
+ RECT 236.330000 2083.260000 237.330000 2083.740000 ;
+ RECT 212.080000 2077.820000 213.180000 2078.300000 ;
+ RECT 212.080000 2083.260000 213.180000 2083.740000 ;
+ RECT 212.080000 2088.700000 213.180000 2089.180000 ;
+ RECT 212.080000 2094.140000 213.180000 2094.620000 ;
+ RECT 236.330000 2061.500000 237.330000 2061.980000 ;
+ RECT 236.330000 2066.940000 237.330000 2067.420000 ;
+ RECT 236.330000 2072.380000 237.330000 2072.860000 ;
+ RECT 236.330000 2050.620000 237.330000 2051.100000 ;
+ RECT 236.330000 2056.060000 237.330000 2056.540000 ;
+ RECT 212.080000 2061.500000 213.180000 2061.980000 ;
+ RECT 212.080000 2056.060000 213.180000 2056.540000 ;
+ RECT 212.080000 2050.620000 213.180000 2051.100000 ;
+ RECT 212.080000 2066.940000 213.180000 2067.420000 ;
+ RECT 212.080000 2072.380000 213.180000 2072.860000 ;
+ RECT 167.080000 2137.660000 168.180000 2138.140000 ;
+ RECT 162.950000 2137.660000 163.950000 2138.140000 ;
+ RECT 162.950000 2126.780000 163.950000 2127.260000 ;
+ RECT 167.080000 2132.220000 168.180000 2132.700000 ;
+ RECT 167.080000 2126.780000 168.180000 2127.260000 ;
+ RECT 162.950000 2132.220000 163.950000 2132.700000 ;
+ RECT 162.950000 2115.900000 163.950000 2116.380000 ;
+ RECT 162.950000 2121.340000 163.950000 2121.820000 ;
+ RECT 167.080000 2121.340000 168.180000 2121.820000 ;
+ RECT 167.080000 2115.900000 168.180000 2116.380000 ;
+ RECT 162.950000 2099.580000 163.950000 2100.060000 ;
+ RECT 162.950000 2105.020000 163.950000 2105.500000 ;
+ RECT 167.080000 2105.020000 168.180000 2105.500000 ;
+ RECT 167.080000 2099.580000 168.180000 2100.060000 ;
+ RECT 167.080000 2110.460000 168.180000 2110.940000 ;
+ RECT 162.950000 2110.460000 163.950000 2110.940000 ;
+ RECT 162.950000 2088.700000 163.950000 2089.180000 ;
+ RECT 162.950000 2094.140000 163.950000 2094.620000 ;
+ RECT 167.080000 2088.700000 168.180000 2089.180000 ;
+ RECT 167.080000 2094.140000 168.180000 2094.620000 ;
+ RECT 162.950000 2077.820000 163.950000 2078.300000 ;
+ RECT 162.950000 2083.260000 163.950000 2083.740000 ;
+ RECT 167.080000 2077.820000 168.180000 2078.300000 ;
+ RECT 167.080000 2083.260000 168.180000 2083.740000 ;
+ RECT 167.080000 2072.380000 168.180000 2072.860000 ;
+ RECT 167.080000 2066.940000 168.180000 2067.420000 ;
+ RECT 162.950000 2072.380000 163.950000 2072.860000 ;
+ RECT 162.950000 2066.940000 163.950000 2067.420000 ;
+ RECT 167.080000 2061.500000 168.180000 2061.980000 ;
+ RECT 162.950000 2061.500000 163.950000 2061.980000 ;
+ RECT 162.950000 2050.620000 163.950000 2051.100000 ;
+ RECT 162.950000 2056.060000 163.950000 2056.540000 ;
+ RECT 167.080000 2056.060000 168.180000 2056.540000 ;
+ RECT 167.080000 2050.620000 168.180000 2051.100000 ;
+ RECT 236.330000 2039.740000 237.330000 2040.220000 ;
+ RECT 236.330000 2045.180000 237.330000 2045.660000 ;
+ RECT 236.330000 2023.420000 237.330000 2023.900000 ;
+ RECT 236.330000 2028.860000 237.330000 2029.340000 ;
+ RECT 236.330000 2034.300000 237.330000 2034.780000 ;
+ RECT 212.080000 2045.180000 213.180000 2045.660000 ;
+ RECT 212.080000 2039.740000 213.180000 2040.220000 ;
+ RECT 212.080000 2034.300000 213.180000 2034.780000 ;
+ RECT 212.080000 2028.860000 213.180000 2029.340000 ;
+ RECT 212.080000 2023.420000 213.180000 2023.900000 ;
+ RECT 236.330000 2012.540000 237.330000 2013.020000 ;
+ RECT 236.330000 2017.980000 237.330000 2018.460000 ;
+ RECT 236.330000 2001.660000 237.330000 2002.140000 ;
+ RECT 236.330000 2007.100000 237.330000 2007.580000 ;
+ RECT 212.080000 2017.980000 213.180000 2018.460000 ;
+ RECT 212.080000 2012.540000 213.180000 2013.020000 ;
+ RECT 212.080000 2007.100000 213.180000 2007.580000 ;
+ RECT 212.080000 2001.660000 213.180000 2002.140000 ;
+ RECT 236.330000 1990.780000 237.330000 1991.260000 ;
+ RECT 236.330000 1996.220000 237.330000 1996.700000 ;
+ RECT 236.330000 1974.460000 237.330000 1974.940000 ;
+ RECT 236.330000 1979.900000 237.330000 1980.380000 ;
+ RECT 236.330000 1985.340000 237.330000 1985.820000 ;
+ RECT 212.080000 1974.460000 213.180000 1974.940000 ;
+ RECT 212.080000 1979.900000 213.180000 1980.380000 ;
+ RECT 212.080000 1985.340000 213.180000 1985.820000 ;
+ RECT 212.080000 1990.780000 213.180000 1991.260000 ;
+ RECT 212.080000 1996.220000 213.180000 1996.700000 ;
+ RECT 236.330000 1963.580000 237.330000 1964.060000 ;
+ RECT 236.330000 1969.020000 237.330000 1969.500000 ;
+ RECT 236.330000 1952.700000 237.330000 1953.180000 ;
+ RECT 236.330000 1958.140000 237.330000 1958.620000 ;
+ RECT 212.080000 1963.580000 213.180000 1964.060000 ;
+ RECT 212.080000 1958.140000 213.180000 1958.620000 ;
+ RECT 212.080000 1952.700000 213.180000 1953.180000 ;
+ RECT 212.080000 1969.020000 213.180000 1969.500000 ;
+ RECT 162.950000 2039.740000 163.950000 2040.220000 ;
+ RECT 162.950000 2045.180000 163.950000 2045.660000 ;
+ RECT 167.080000 2045.180000 168.180000 2045.660000 ;
+ RECT 167.080000 2039.740000 168.180000 2040.220000 ;
+ RECT 167.080000 2034.300000 168.180000 2034.780000 ;
+ RECT 162.950000 2034.300000 163.950000 2034.780000 ;
+ RECT 167.080000 2023.420000 168.180000 2023.900000 ;
+ RECT 162.950000 2023.420000 163.950000 2023.900000 ;
+ RECT 162.950000 2028.860000 163.950000 2029.340000 ;
+ RECT 167.080000 2028.860000 168.180000 2029.340000 ;
+ RECT 162.950000 2012.540000 163.950000 2013.020000 ;
+ RECT 162.950000 2017.980000 163.950000 2018.460000 ;
+ RECT 167.080000 2017.980000 168.180000 2018.460000 ;
+ RECT 167.080000 2012.540000 168.180000 2013.020000 ;
+ RECT 162.950000 2001.660000 163.950000 2002.140000 ;
+ RECT 162.950000 2007.100000 163.950000 2007.580000 ;
+ RECT 167.080000 2007.100000 168.180000 2007.580000 ;
+ RECT 167.080000 2001.660000 168.180000 2002.140000 ;
+ RECT 162.950000 1990.780000 163.950000 1991.260000 ;
+ RECT 162.950000 1996.220000 163.950000 1996.700000 ;
+ RECT 167.080000 1990.780000 168.180000 1991.260000 ;
+ RECT 167.080000 1996.220000 168.180000 1996.700000 ;
+ RECT 162.950000 1974.460000 163.950000 1974.940000 ;
+ RECT 162.950000 1979.900000 163.950000 1980.380000 ;
+ RECT 167.080000 1974.460000 168.180000 1974.940000 ;
+ RECT 167.080000 1979.900000 168.180000 1980.380000 ;
+ RECT 167.080000 1985.340000 168.180000 1985.820000 ;
+ RECT 162.950000 1985.340000 163.950000 1985.820000 ;
+ RECT 162.950000 1963.580000 163.950000 1964.060000 ;
+ RECT 162.950000 1969.020000 163.950000 1969.500000 ;
+ RECT 167.080000 1963.580000 168.180000 1964.060000 ;
+ RECT 167.080000 1969.020000 168.180000 1969.500000 ;
+ RECT 167.080000 1952.700000 168.180000 1953.180000 ;
+ RECT 167.080000 1958.140000 168.180000 1958.620000 ;
+ RECT 162.950000 1958.140000 163.950000 1958.620000 ;
+ RECT 162.950000 1952.700000 163.950000 1953.180000 ;
+ RECT 160.120000 2143.060000 240.160000 2144.060000 ;
+ RECT 160.120000 1950.690000 240.160000 1951.690000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1947.840000 163.950000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 2147.100000 163.950000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 1947.840000 237.330000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 2147.100000 237.330000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1950.690000 161.120000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1950.690000 240.160000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 2143.060000 161.120000 2144.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 2143.060000 240.160000 2144.060000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1747.580000 163.950000 1947.840000 ;
+ RECT 236.330000 1747.580000 237.330000 1947.840000 ;
+ RECT 167.080000 1750.430000 168.180000 1943.800000 ;
+ RECT 212.080000 1750.430000 213.180000 1943.800000 ;
+ LAYER met3 ;
+ RECT 236.330000 1937.400000 237.330000 1937.880000 ;
+ RECT 236.330000 1926.520000 237.330000 1927.000000 ;
+ RECT 236.330000 1931.960000 237.330000 1932.440000 ;
+ RECT 212.080000 1937.400000 213.180000 1937.880000 ;
+ RECT 212.080000 1931.960000 213.180000 1932.440000 ;
+ RECT 212.080000 1926.520000 213.180000 1927.000000 ;
+ RECT 236.330000 1915.640000 237.330000 1916.120000 ;
+ RECT 236.330000 1921.080000 237.330000 1921.560000 ;
+ RECT 236.330000 1899.320000 237.330000 1899.800000 ;
+ RECT 236.330000 1904.760000 237.330000 1905.240000 ;
+ RECT 236.330000 1910.200000 237.330000 1910.680000 ;
+ RECT 212.080000 1921.080000 213.180000 1921.560000 ;
+ RECT 212.080000 1915.640000 213.180000 1916.120000 ;
+ RECT 212.080000 1910.200000 213.180000 1910.680000 ;
+ RECT 212.080000 1904.760000 213.180000 1905.240000 ;
+ RECT 212.080000 1899.320000 213.180000 1899.800000 ;
+ RECT 236.330000 1888.440000 237.330000 1888.920000 ;
+ RECT 236.330000 1893.880000 237.330000 1894.360000 ;
+ RECT 236.330000 1877.560000 237.330000 1878.040000 ;
+ RECT 236.330000 1883.000000 237.330000 1883.480000 ;
+ RECT 212.080000 1877.560000 213.180000 1878.040000 ;
+ RECT 212.080000 1883.000000 213.180000 1883.480000 ;
+ RECT 212.080000 1888.440000 213.180000 1888.920000 ;
+ RECT 212.080000 1893.880000 213.180000 1894.360000 ;
+ RECT 236.330000 1861.240000 237.330000 1861.720000 ;
+ RECT 236.330000 1866.680000 237.330000 1867.160000 ;
+ RECT 236.330000 1872.120000 237.330000 1872.600000 ;
+ RECT 236.330000 1850.360000 237.330000 1850.840000 ;
+ RECT 236.330000 1855.800000 237.330000 1856.280000 ;
+ RECT 212.080000 1861.240000 213.180000 1861.720000 ;
+ RECT 212.080000 1855.800000 213.180000 1856.280000 ;
+ RECT 212.080000 1850.360000 213.180000 1850.840000 ;
+ RECT 212.080000 1866.680000 213.180000 1867.160000 ;
+ RECT 212.080000 1872.120000 213.180000 1872.600000 ;
+ RECT 167.080000 1937.400000 168.180000 1937.880000 ;
+ RECT 162.950000 1937.400000 163.950000 1937.880000 ;
+ RECT 162.950000 1926.520000 163.950000 1927.000000 ;
+ RECT 167.080000 1931.960000 168.180000 1932.440000 ;
+ RECT 167.080000 1926.520000 168.180000 1927.000000 ;
+ RECT 162.950000 1931.960000 163.950000 1932.440000 ;
+ RECT 162.950000 1915.640000 163.950000 1916.120000 ;
+ RECT 162.950000 1921.080000 163.950000 1921.560000 ;
+ RECT 167.080000 1921.080000 168.180000 1921.560000 ;
+ RECT 167.080000 1915.640000 168.180000 1916.120000 ;
+ RECT 162.950000 1899.320000 163.950000 1899.800000 ;
+ RECT 162.950000 1904.760000 163.950000 1905.240000 ;
+ RECT 167.080000 1904.760000 168.180000 1905.240000 ;
+ RECT 167.080000 1899.320000 168.180000 1899.800000 ;
+ RECT 167.080000 1910.200000 168.180000 1910.680000 ;
+ RECT 162.950000 1910.200000 163.950000 1910.680000 ;
+ RECT 162.950000 1888.440000 163.950000 1888.920000 ;
+ RECT 162.950000 1893.880000 163.950000 1894.360000 ;
+ RECT 167.080000 1888.440000 168.180000 1888.920000 ;
+ RECT 167.080000 1893.880000 168.180000 1894.360000 ;
+ RECT 162.950000 1877.560000 163.950000 1878.040000 ;
+ RECT 162.950000 1883.000000 163.950000 1883.480000 ;
+ RECT 167.080000 1877.560000 168.180000 1878.040000 ;
+ RECT 167.080000 1883.000000 168.180000 1883.480000 ;
+ RECT 167.080000 1872.120000 168.180000 1872.600000 ;
+ RECT 167.080000 1866.680000 168.180000 1867.160000 ;
+ RECT 162.950000 1872.120000 163.950000 1872.600000 ;
+ RECT 162.950000 1866.680000 163.950000 1867.160000 ;
+ RECT 167.080000 1861.240000 168.180000 1861.720000 ;
+ RECT 162.950000 1861.240000 163.950000 1861.720000 ;
+ RECT 162.950000 1850.360000 163.950000 1850.840000 ;
+ RECT 162.950000 1855.800000 163.950000 1856.280000 ;
+ RECT 167.080000 1855.800000 168.180000 1856.280000 ;
+ RECT 167.080000 1850.360000 168.180000 1850.840000 ;
+ RECT 236.330000 1839.480000 237.330000 1839.960000 ;
+ RECT 236.330000 1844.920000 237.330000 1845.400000 ;
+ RECT 236.330000 1823.160000 237.330000 1823.640000 ;
+ RECT 236.330000 1828.600000 237.330000 1829.080000 ;
+ RECT 236.330000 1834.040000 237.330000 1834.520000 ;
+ RECT 212.080000 1844.920000 213.180000 1845.400000 ;
+ RECT 212.080000 1839.480000 213.180000 1839.960000 ;
+ RECT 212.080000 1834.040000 213.180000 1834.520000 ;
+ RECT 212.080000 1828.600000 213.180000 1829.080000 ;
+ RECT 212.080000 1823.160000 213.180000 1823.640000 ;
+ RECT 236.330000 1812.280000 237.330000 1812.760000 ;
+ RECT 236.330000 1817.720000 237.330000 1818.200000 ;
+ RECT 236.330000 1801.400000 237.330000 1801.880000 ;
+ RECT 236.330000 1806.840000 237.330000 1807.320000 ;
+ RECT 212.080000 1817.720000 213.180000 1818.200000 ;
+ RECT 212.080000 1812.280000 213.180000 1812.760000 ;
+ RECT 212.080000 1806.840000 213.180000 1807.320000 ;
+ RECT 212.080000 1801.400000 213.180000 1801.880000 ;
+ RECT 236.330000 1790.520000 237.330000 1791.000000 ;
+ RECT 236.330000 1795.960000 237.330000 1796.440000 ;
+ RECT 236.330000 1774.200000 237.330000 1774.680000 ;
+ RECT 236.330000 1779.640000 237.330000 1780.120000 ;
+ RECT 236.330000 1785.080000 237.330000 1785.560000 ;
+ RECT 212.080000 1774.200000 213.180000 1774.680000 ;
+ RECT 212.080000 1779.640000 213.180000 1780.120000 ;
+ RECT 212.080000 1785.080000 213.180000 1785.560000 ;
+ RECT 212.080000 1790.520000 213.180000 1791.000000 ;
+ RECT 212.080000 1795.960000 213.180000 1796.440000 ;
+ RECT 236.330000 1763.320000 237.330000 1763.800000 ;
+ RECT 236.330000 1768.760000 237.330000 1769.240000 ;
+ RECT 236.330000 1752.440000 237.330000 1752.920000 ;
+ RECT 236.330000 1757.880000 237.330000 1758.360000 ;
+ RECT 212.080000 1763.320000 213.180000 1763.800000 ;
+ RECT 212.080000 1757.880000 213.180000 1758.360000 ;
+ RECT 212.080000 1752.440000 213.180000 1752.920000 ;
+ RECT 212.080000 1768.760000 213.180000 1769.240000 ;
+ RECT 162.950000 1839.480000 163.950000 1839.960000 ;
+ RECT 162.950000 1844.920000 163.950000 1845.400000 ;
+ RECT 167.080000 1844.920000 168.180000 1845.400000 ;
+ RECT 167.080000 1839.480000 168.180000 1839.960000 ;
+ RECT 167.080000 1834.040000 168.180000 1834.520000 ;
+ RECT 162.950000 1834.040000 163.950000 1834.520000 ;
+ RECT 167.080000 1823.160000 168.180000 1823.640000 ;
+ RECT 162.950000 1823.160000 163.950000 1823.640000 ;
+ RECT 162.950000 1828.600000 163.950000 1829.080000 ;
+ RECT 167.080000 1828.600000 168.180000 1829.080000 ;
+ RECT 162.950000 1812.280000 163.950000 1812.760000 ;
+ RECT 162.950000 1817.720000 163.950000 1818.200000 ;
+ RECT 167.080000 1817.720000 168.180000 1818.200000 ;
+ RECT 167.080000 1812.280000 168.180000 1812.760000 ;
+ RECT 162.950000 1801.400000 163.950000 1801.880000 ;
+ RECT 162.950000 1806.840000 163.950000 1807.320000 ;
+ RECT 167.080000 1806.840000 168.180000 1807.320000 ;
+ RECT 167.080000 1801.400000 168.180000 1801.880000 ;
+ RECT 162.950000 1790.520000 163.950000 1791.000000 ;
+ RECT 162.950000 1795.960000 163.950000 1796.440000 ;
+ RECT 167.080000 1790.520000 168.180000 1791.000000 ;
+ RECT 167.080000 1795.960000 168.180000 1796.440000 ;
+ RECT 162.950000 1774.200000 163.950000 1774.680000 ;
+ RECT 162.950000 1779.640000 163.950000 1780.120000 ;
+ RECT 167.080000 1774.200000 168.180000 1774.680000 ;
+ RECT 167.080000 1779.640000 168.180000 1780.120000 ;
+ RECT 167.080000 1785.080000 168.180000 1785.560000 ;
+ RECT 162.950000 1785.080000 163.950000 1785.560000 ;
+ RECT 162.950000 1763.320000 163.950000 1763.800000 ;
+ RECT 162.950000 1768.760000 163.950000 1769.240000 ;
+ RECT 167.080000 1763.320000 168.180000 1763.800000 ;
+ RECT 167.080000 1768.760000 168.180000 1769.240000 ;
+ RECT 167.080000 1752.440000 168.180000 1752.920000 ;
+ RECT 167.080000 1757.880000 168.180000 1758.360000 ;
+ RECT 162.950000 1757.880000 163.950000 1758.360000 ;
+ RECT 162.950000 1752.440000 163.950000 1752.920000 ;
+ RECT 160.120000 1942.800000 240.160000 1943.800000 ;
+ RECT 160.120000 1750.430000 240.160000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1747.580000 163.950000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1946.840000 163.950000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 1747.580000 237.330000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 1946.840000 237.330000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1750.430000 161.120000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1750.430000 240.160000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1942.800000 161.120000 1943.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1942.800000 240.160000 1943.800000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'W_IO'
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1547.320000 163.950000 1747.580000 ;
+ RECT 236.330000 1547.320000 237.330000 1747.580000 ;
+ RECT 167.080000 1550.170000 168.180000 1743.540000 ;
+ RECT 212.080000 1550.170000 213.180000 1743.540000 ;
+ LAYER met3 ;
+ RECT 236.330000 1737.140000 237.330000 1737.620000 ;
+ RECT 236.330000 1726.260000 237.330000 1726.740000 ;
+ RECT 236.330000 1731.700000 237.330000 1732.180000 ;
+ RECT 212.080000 1737.140000 213.180000 1737.620000 ;
+ RECT 212.080000 1731.700000 213.180000 1732.180000 ;
+ RECT 212.080000 1726.260000 213.180000 1726.740000 ;
+ RECT 236.330000 1715.380000 237.330000 1715.860000 ;
+ RECT 236.330000 1720.820000 237.330000 1721.300000 ;
+ RECT 236.330000 1699.060000 237.330000 1699.540000 ;
+ RECT 236.330000 1704.500000 237.330000 1704.980000 ;
+ RECT 236.330000 1709.940000 237.330000 1710.420000 ;
+ RECT 212.080000 1720.820000 213.180000 1721.300000 ;
+ RECT 212.080000 1715.380000 213.180000 1715.860000 ;
+ RECT 212.080000 1709.940000 213.180000 1710.420000 ;
+ RECT 212.080000 1704.500000 213.180000 1704.980000 ;
+ RECT 212.080000 1699.060000 213.180000 1699.540000 ;
+ RECT 236.330000 1688.180000 237.330000 1688.660000 ;
+ RECT 236.330000 1693.620000 237.330000 1694.100000 ;
+ RECT 236.330000 1677.300000 237.330000 1677.780000 ;
+ RECT 236.330000 1682.740000 237.330000 1683.220000 ;
+ RECT 212.080000 1677.300000 213.180000 1677.780000 ;
+ RECT 212.080000 1682.740000 213.180000 1683.220000 ;
+ RECT 212.080000 1688.180000 213.180000 1688.660000 ;
+ RECT 212.080000 1693.620000 213.180000 1694.100000 ;
+ RECT 236.330000 1660.980000 237.330000 1661.460000 ;
+ RECT 236.330000 1666.420000 237.330000 1666.900000 ;
+ RECT 236.330000 1671.860000 237.330000 1672.340000 ;
+ RECT 236.330000 1650.100000 237.330000 1650.580000 ;
+ RECT 236.330000 1655.540000 237.330000 1656.020000 ;
+ RECT 212.080000 1660.980000 213.180000 1661.460000 ;
+ RECT 212.080000 1655.540000 213.180000 1656.020000 ;
+ RECT 212.080000 1650.100000 213.180000 1650.580000 ;
+ RECT 212.080000 1666.420000 213.180000 1666.900000 ;
+ RECT 212.080000 1671.860000 213.180000 1672.340000 ;
+ RECT 167.080000 1737.140000 168.180000 1737.620000 ;
+ RECT 162.950000 1737.140000 163.950000 1737.620000 ;
+ RECT 162.950000 1726.260000 163.950000 1726.740000 ;
+ RECT 167.080000 1731.700000 168.180000 1732.180000 ;
+ RECT 167.080000 1726.260000 168.180000 1726.740000 ;
+ RECT 162.950000 1731.700000 163.950000 1732.180000 ;
+ RECT 162.950000 1715.380000 163.950000 1715.860000 ;
+ RECT 162.950000 1720.820000 163.950000 1721.300000 ;
+ RECT 167.080000 1720.820000 168.180000 1721.300000 ;
+ RECT 167.080000 1715.380000 168.180000 1715.860000 ;
+ RECT 162.950000 1699.060000 163.950000 1699.540000 ;
+ RECT 162.950000 1704.500000 163.950000 1704.980000 ;
+ RECT 167.080000 1704.500000 168.180000 1704.980000 ;
+ RECT 167.080000 1699.060000 168.180000 1699.540000 ;
+ RECT 167.080000 1709.940000 168.180000 1710.420000 ;
+ RECT 162.950000 1709.940000 163.950000 1710.420000 ;
+ RECT 162.950000 1688.180000 163.950000 1688.660000 ;
+ RECT 162.950000 1693.620000 163.950000 1694.100000 ;
+ RECT 167.080000 1688.180000 168.180000 1688.660000 ;
+ RECT 167.080000 1693.620000 168.180000 1694.100000 ;
+ RECT 162.950000 1677.300000 163.950000 1677.780000 ;
+ RECT 162.950000 1682.740000 163.950000 1683.220000 ;
+ RECT 167.080000 1677.300000 168.180000 1677.780000 ;
+ RECT 167.080000 1682.740000 168.180000 1683.220000 ;
+ RECT 167.080000 1671.860000 168.180000 1672.340000 ;
+ RECT 167.080000 1666.420000 168.180000 1666.900000 ;
+ RECT 162.950000 1671.860000 163.950000 1672.340000 ;
+ RECT 162.950000 1666.420000 163.950000 1666.900000 ;
+ RECT 167.080000 1660.980000 168.180000 1661.460000 ;
+ RECT 162.950000 1660.980000 163.950000 1661.460000 ;
+ RECT 162.950000 1650.100000 163.950000 1650.580000 ;
+ RECT 162.950000 1655.540000 163.950000 1656.020000 ;
+ RECT 167.080000 1655.540000 168.180000 1656.020000 ;
+ RECT 167.080000 1650.100000 168.180000 1650.580000 ;
+ RECT 236.330000 1639.220000 237.330000 1639.700000 ;
+ RECT 236.330000 1644.660000 237.330000 1645.140000 ;
+ RECT 236.330000 1622.900000 237.330000 1623.380000 ;
+ RECT 236.330000 1628.340000 237.330000 1628.820000 ;
+ RECT 236.330000 1633.780000 237.330000 1634.260000 ;
+ RECT 212.080000 1644.660000 213.180000 1645.140000 ;
+ RECT 212.080000 1639.220000 213.180000 1639.700000 ;
+ RECT 212.080000 1633.780000 213.180000 1634.260000 ;
+ RECT 212.080000 1628.340000 213.180000 1628.820000 ;
+ RECT 212.080000 1622.900000 213.180000 1623.380000 ;
+ RECT 236.330000 1612.020000 237.330000 1612.500000 ;
+ RECT 236.330000 1617.460000 237.330000 1617.940000 ;
+ RECT 236.330000 1601.140000 237.330000 1601.620000 ;
+ RECT 236.330000 1606.580000 237.330000 1607.060000 ;
+ RECT 212.080000 1617.460000 213.180000 1617.940000 ;
+ RECT 212.080000 1612.020000 213.180000 1612.500000 ;
+ RECT 212.080000 1606.580000 213.180000 1607.060000 ;
+ RECT 212.080000 1601.140000 213.180000 1601.620000 ;
+ RECT 236.330000 1590.260000 237.330000 1590.740000 ;
+ RECT 236.330000 1595.700000 237.330000 1596.180000 ;
+ RECT 236.330000 1573.940000 237.330000 1574.420000 ;
+ RECT 236.330000 1579.380000 237.330000 1579.860000 ;
+ RECT 236.330000 1584.820000 237.330000 1585.300000 ;
+ RECT 212.080000 1573.940000 213.180000 1574.420000 ;
+ RECT 212.080000 1579.380000 213.180000 1579.860000 ;
+ RECT 212.080000 1584.820000 213.180000 1585.300000 ;
+ RECT 212.080000 1590.260000 213.180000 1590.740000 ;
+ RECT 212.080000 1595.700000 213.180000 1596.180000 ;
+ RECT 236.330000 1563.060000 237.330000 1563.540000 ;
+ RECT 236.330000 1568.500000 237.330000 1568.980000 ;
+ RECT 236.330000 1552.180000 237.330000 1552.660000 ;
+ RECT 236.330000 1557.620000 237.330000 1558.100000 ;
+ RECT 212.080000 1563.060000 213.180000 1563.540000 ;
+ RECT 212.080000 1557.620000 213.180000 1558.100000 ;
+ RECT 212.080000 1552.180000 213.180000 1552.660000 ;
+ RECT 212.080000 1568.500000 213.180000 1568.980000 ;
+ RECT 162.950000 1639.220000 163.950000 1639.700000 ;
+ RECT 162.950000 1644.660000 163.950000 1645.140000 ;
+ RECT 167.080000 1644.660000 168.180000 1645.140000 ;
+ RECT 167.080000 1639.220000 168.180000 1639.700000 ;
+ RECT 167.080000 1633.780000 168.180000 1634.260000 ;
+ RECT 162.950000 1633.780000 163.950000 1634.260000 ;
+ RECT 167.080000 1622.900000 168.180000 1623.380000 ;
+ RECT 162.950000 1622.900000 163.950000 1623.380000 ;
+ RECT 162.950000 1628.340000 163.950000 1628.820000 ;
+ RECT 167.080000 1628.340000 168.180000 1628.820000 ;
+ RECT 162.950000 1612.020000 163.950000 1612.500000 ;
+ RECT 162.950000 1617.460000 163.950000 1617.940000 ;
+ RECT 167.080000 1617.460000 168.180000 1617.940000 ;
+ RECT 167.080000 1612.020000 168.180000 1612.500000 ;
+ RECT 162.950000 1601.140000 163.950000 1601.620000 ;
+ RECT 162.950000 1606.580000 163.950000 1607.060000 ;
+ RECT 167.080000 1606.580000 168.180000 1607.060000 ;
+ RECT 167.080000 1601.140000 168.180000 1601.620000 ;
+ RECT 162.950000 1590.260000 163.950000 1590.740000 ;
+ RECT 162.950000 1595.700000 163.950000 1596.180000 ;
+ RECT 167.080000 1590.260000 168.180000 1590.740000 ;
+ RECT 167.080000 1595.700000 168.180000 1596.180000 ;
+ RECT 162.950000 1573.940000 163.950000 1574.420000 ;
+ RECT 162.950000 1579.380000 163.950000 1579.860000 ;
+ RECT 167.080000 1573.940000 168.180000 1574.420000 ;
+ RECT 167.080000 1579.380000 168.180000 1579.860000 ;
+ RECT 167.080000 1584.820000 168.180000 1585.300000 ;
+ RECT 162.950000 1584.820000 163.950000 1585.300000 ;
+ RECT 162.950000 1563.060000 163.950000 1563.540000 ;
+ RECT 162.950000 1568.500000 163.950000 1568.980000 ;
+ RECT 167.080000 1563.060000 168.180000 1563.540000 ;
+ RECT 167.080000 1568.500000 168.180000 1568.980000 ;
+ RECT 167.080000 1552.180000 168.180000 1552.660000 ;
+ RECT 167.080000 1557.620000 168.180000 1558.100000 ;
+ RECT 162.950000 1557.620000 163.950000 1558.100000 ;
+ RECT 162.950000 1552.180000 163.950000 1552.660000 ;
+ RECT 160.120000 1742.540000 240.160000 1743.540000 ;
+ RECT 160.120000 1550.170000 240.160000 1551.170000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1547.320000 163.950000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 162.950000 1746.580000 163.950000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 1547.320000 237.330000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 236.330000 1746.580000 237.330000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1550.170000 161.120000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1550.170000 240.160000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 160.120000 1742.540000 161.120000 1743.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 239.160000 1742.540000 240.160000 1743.540000 ;
+ END
+# end of P/G pin shape extracted from block 'W_IO'
+
+
+# P/G pin shape extracted from block 'N_term_RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 3349.660000 2054.890000 3379.920000 ;
+ RECT 2157.170000 3349.660000 2158.170000 3379.920000 ;
+ RECT 2058.020000 3352.510000 2059.120000 3376.560000 ;
+ RECT 2103.020000 3352.510000 2104.120000 3376.560000 ;
+ RECT 2148.020000 3352.510000 2149.120000 3376.560000 ;
+ LAYER met3 ;
+ RECT 2157.170000 3365.400000 2158.170000 3365.880000 ;
+ RECT 2157.170000 3370.840000 2158.170000 3371.320000 ;
+ RECT 2148.020000 3365.400000 2149.120000 3365.880000 ;
+ RECT 2148.020000 3370.840000 2149.120000 3371.320000 ;
+ RECT 2103.020000 3370.840000 2104.120000 3371.320000 ;
+ RECT 2103.020000 3365.400000 2104.120000 3365.880000 ;
+ RECT 2053.890000 3365.400000 2054.890000 3365.880000 ;
+ RECT 2053.890000 3370.840000 2054.890000 3371.320000 ;
+ RECT 2058.020000 3365.400000 2059.120000 3365.880000 ;
+ RECT 2058.020000 3370.840000 2059.120000 3371.320000 ;
+ RECT 2157.170000 3354.520000 2158.170000 3355.000000 ;
+ RECT 2157.170000 3359.960000 2158.170000 3360.440000 ;
+ RECT 2148.020000 3354.520000 2149.120000 3355.000000 ;
+ RECT 2148.020000 3359.960000 2149.120000 3360.440000 ;
+ RECT 2103.020000 3359.960000 2104.120000 3360.440000 ;
+ RECT 2103.020000 3354.520000 2104.120000 3355.000000 ;
+ RECT 2053.890000 3359.960000 2054.890000 3360.440000 ;
+ RECT 2058.020000 3359.960000 2059.120000 3360.440000 ;
+ RECT 2053.890000 3354.520000 2054.890000 3355.000000 ;
+ RECT 2058.020000 3354.520000 2059.120000 3355.000000 ;
+ RECT 2051.060000 3375.560000 2161.000000 3376.560000 ;
+ RECT 2051.060000 3352.510000 2161.000000 3353.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 3349.660000 2054.890000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 3378.920000 2054.890000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 3349.660000 2158.170000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 3378.920000 2158.170000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 3352.510000 2052.060000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 3352.510000 2161.000000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 3375.560000 2052.060000 3376.560000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 3375.560000 2161.000000 3376.560000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1347.060000 2054.890000 1547.320000 ;
+ RECT 2157.170000 1347.060000 2158.170000 1547.320000 ;
+ RECT 2058.020000 1349.910000 2059.120000 1543.280000 ;
+ RECT 2103.020000 1349.910000 2104.120000 1543.280000 ;
+ RECT 2148.020000 1349.910000 2149.120000 1543.280000 ;
+ LAYER met3 ;
+ RECT 2157.170000 1526.000000 2158.170000 1526.480000 ;
+ RECT 2157.170000 1531.440000 2158.170000 1531.920000 ;
+ RECT 2157.170000 1536.880000 2158.170000 1537.360000 ;
+ RECT 2157.170000 1498.800000 2158.170000 1499.280000 ;
+ RECT 2157.170000 1504.240000 2158.170000 1504.720000 ;
+ RECT 2157.170000 1509.680000 2158.170000 1510.160000 ;
+ RECT 2157.170000 1515.120000 2158.170000 1515.600000 ;
+ RECT 2157.170000 1520.560000 2158.170000 1521.040000 ;
+ RECT 2148.020000 1526.000000 2149.120000 1526.480000 ;
+ RECT 2148.020000 1531.440000 2149.120000 1531.920000 ;
+ RECT 2148.020000 1536.880000 2149.120000 1537.360000 ;
+ RECT 2148.020000 1498.800000 2149.120000 1499.280000 ;
+ RECT 2148.020000 1504.240000 2149.120000 1504.720000 ;
+ RECT 2148.020000 1509.680000 2149.120000 1510.160000 ;
+ RECT 2148.020000 1515.120000 2149.120000 1515.600000 ;
+ RECT 2148.020000 1520.560000 2149.120000 1521.040000 ;
+ RECT 2157.170000 1477.040000 2158.170000 1477.520000 ;
+ RECT 2157.170000 1482.480000 2158.170000 1482.960000 ;
+ RECT 2157.170000 1487.920000 2158.170000 1488.400000 ;
+ RECT 2157.170000 1493.360000 2158.170000 1493.840000 ;
+ RECT 2157.170000 1449.840000 2158.170000 1450.320000 ;
+ RECT 2157.170000 1455.280000 2158.170000 1455.760000 ;
+ RECT 2157.170000 1460.720000 2158.170000 1461.200000 ;
+ RECT 2157.170000 1466.160000 2158.170000 1466.640000 ;
+ RECT 2157.170000 1471.600000 2158.170000 1472.080000 ;
+ RECT 2148.020000 1493.360000 2149.120000 1493.840000 ;
+ RECT 2148.020000 1487.920000 2149.120000 1488.400000 ;
+ RECT 2148.020000 1482.480000 2149.120000 1482.960000 ;
+ RECT 2148.020000 1477.040000 2149.120000 1477.520000 ;
+ RECT 2148.020000 1471.600000 2149.120000 1472.080000 ;
+ RECT 2148.020000 1466.160000 2149.120000 1466.640000 ;
+ RECT 2148.020000 1460.720000 2149.120000 1461.200000 ;
+ RECT 2148.020000 1449.840000 2149.120000 1450.320000 ;
+ RECT 2148.020000 1455.280000 2149.120000 1455.760000 ;
+ RECT 2103.020000 1536.880000 2104.120000 1537.360000 ;
+ RECT 2103.020000 1531.440000 2104.120000 1531.920000 ;
+ RECT 2103.020000 1526.000000 2104.120000 1526.480000 ;
+ RECT 2058.020000 1536.880000 2059.120000 1537.360000 ;
+ RECT 2058.020000 1531.440000 2059.120000 1531.920000 ;
+ RECT 2058.020000 1526.000000 2059.120000 1526.480000 ;
+ RECT 2103.020000 1515.120000 2104.120000 1515.600000 ;
+ RECT 2103.020000 1509.680000 2104.120000 1510.160000 ;
+ RECT 2103.020000 1504.240000 2104.120000 1504.720000 ;
+ RECT 2103.020000 1498.800000 2104.120000 1499.280000 ;
+ RECT 2103.020000 1520.560000 2104.120000 1521.040000 ;
+ RECT 2058.020000 1520.560000 2059.120000 1521.040000 ;
+ RECT 2058.020000 1515.120000 2059.120000 1515.600000 ;
+ RECT 2058.020000 1509.680000 2059.120000 1510.160000 ;
+ RECT 2058.020000 1504.240000 2059.120000 1504.720000 ;
+ RECT 2058.020000 1498.800000 2059.120000 1499.280000 ;
+ RECT 2053.890000 1526.000000 2054.890000 1526.480000 ;
+ RECT 2053.890000 1531.440000 2054.890000 1531.920000 ;
+ RECT 2053.890000 1536.880000 2054.890000 1537.360000 ;
+ RECT 2053.890000 1498.800000 2054.890000 1499.280000 ;
+ RECT 2053.890000 1504.240000 2054.890000 1504.720000 ;
+ RECT 2053.890000 1509.680000 2054.890000 1510.160000 ;
+ RECT 2053.890000 1515.120000 2054.890000 1515.600000 ;
+ RECT 2053.890000 1520.560000 2054.890000 1521.040000 ;
+ RECT 2103.020000 1493.360000 2104.120000 1493.840000 ;
+ RECT 2103.020000 1487.920000 2104.120000 1488.400000 ;
+ RECT 2103.020000 1482.480000 2104.120000 1482.960000 ;
+ RECT 2103.020000 1477.040000 2104.120000 1477.520000 ;
+ RECT 2058.020000 1493.360000 2059.120000 1493.840000 ;
+ RECT 2058.020000 1487.920000 2059.120000 1488.400000 ;
+ RECT 2058.020000 1482.480000 2059.120000 1482.960000 ;
+ RECT 2058.020000 1477.040000 2059.120000 1477.520000 ;
+ RECT 2103.020000 1471.600000 2104.120000 1472.080000 ;
+ RECT 2103.020000 1455.280000 2104.120000 1455.760000 ;
+ RECT 2103.020000 1449.840000 2104.120000 1450.320000 ;
+ RECT 2103.020000 1460.720000 2104.120000 1461.200000 ;
+ RECT 2103.020000 1466.160000 2104.120000 1466.640000 ;
+ RECT 2058.020000 1471.600000 2059.120000 1472.080000 ;
+ RECT 2058.020000 1455.280000 2059.120000 1455.760000 ;
+ RECT 2058.020000 1449.840000 2059.120000 1450.320000 ;
+ RECT 2058.020000 1460.720000 2059.120000 1461.200000 ;
+ RECT 2058.020000 1466.160000 2059.120000 1466.640000 ;
+ RECT 2053.890000 1477.040000 2054.890000 1477.520000 ;
+ RECT 2053.890000 1482.480000 2054.890000 1482.960000 ;
+ RECT 2053.890000 1487.920000 2054.890000 1488.400000 ;
+ RECT 2053.890000 1493.360000 2054.890000 1493.840000 ;
+ RECT 2053.890000 1449.840000 2054.890000 1450.320000 ;
+ RECT 2053.890000 1455.280000 2054.890000 1455.760000 ;
+ RECT 2053.890000 1460.720000 2054.890000 1461.200000 ;
+ RECT 2053.890000 1466.160000 2054.890000 1466.640000 ;
+ RECT 2053.890000 1471.600000 2054.890000 1472.080000 ;
+ RECT 2157.170000 1422.640000 2158.170000 1423.120000 ;
+ RECT 2157.170000 1428.080000 2158.170000 1428.560000 ;
+ RECT 2157.170000 1433.520000 2158.170000 1434.000000 ;
+ RECT 2157.170000 1438.960000 2158.170000 1439.440000 ;
+ RECT 2157.170000 1444.400000 2158.170000 1444.880000 ;
+ RECT 2157.170000 1400.880000 2158.170000 1401.360000 ;
+ RECT 2157.170000 1406.320000 2158.170000 1406.800000 ;
+ RECT 2157.170000 1411.760000 2158.170000 1412.240000 ;
+ RECT 2157.170000 1417.200000 2158.170000 1417.680000 ;
+ RECT 2148.020000 1422.640000 2149.120000 1423.120000 ;
+ RECT 2148.020000 1428.080000 2149.120000 1428.560000 ;
+ RECT 2148.020000 1433.520000 2149.120000 1434.000000 ;
+ RECT 2148.020000 1438.960000 2149.120000 1439.440000 ;
+ RECT 2148.020000 1444.400000 2149.120000 1444.880000 ;
+ RECT 2148.020000 1400.880000 2149.120000 1401.360000 ;
+ RECT 2148.020000 1406.320000 2149.120000 1406.800000 ;
+ RECT 2148.020000 1411.760000 2149.120000 1412.240000 ;
+ RECT 2148.020000 1417.200000 2149.120000 1417.680000 ;
+ RECT 2157.170000 1373.680000 2158.170000 1374.160000 ;
+ RECT 2157.170000 1379.120000 2158.170000 1379.600000 ;
+ RECT 2157.170000 1384.560000 2158.170000 1385.040000 ;
+ RECT 2157.170000 1390.000000 2158.170000 1390.480000 ;
+ RECT 2157.170000 1395.440000 2158.170000 1395.920000 ;
+ RECT 2157.170000 1351.920000 2158.170000 1352.400000 ;
+ RECT 2157.170000 1357.360000 2158.170000 1357.840000 ;
+ RECT 2157.170000 1362.800000 2158.170000 1363.280000 ;
+ RECT 2157.170000 1368.240000 2158.170000 1368.720000 ;
+ RECT 2148.020000 1395.440000 2149.120000 1395.920000 ;
+ RECT 2148.020000 1390.000000 2149.120000 1390.480000 ;
+ RECT 2148.020000 1384.560000 2149.120000 1385.040000 ;
+ RECT 2148.020000 1379.120000 2149.120000 1379.600000 ;
+ RECT 2148.020000 1373.680000 2149.120000 1374.160000 ;
+ RECT 2148.020000 1368.240000 2149.120000 1368.720000 ;
+ RECT 2148.020000 1362.800000 2149.120000 1363.280000 ;
+ RECT 2148.020000 1351.920000 2149.120000 1352.400000 ;
+ RECT 2148.020000 1357.360000 2149.120000 1357.840000 ;
+ RECT 2103.020000 1444.400000 2104.120000 1444.880000 ;
+ RECT 2103.020000 1438.960000 2104.120000 1439.440000 ;
+ RECT 2103.020000 1433.520000 2104.120000 1434.000000 ;
+ RECT 2103.020000 1422.640000 2104.120000 1423.120000 ;
+ RECT 2103.020000 1428.080000 2104.120000 1428.560000 ;
+ RECT 2058.020000 1444.400000 2059.120000 1444.880000 ;
+ RECT 2058.020000 1438.960000 2059.120000 1439.440000 ;
+ RECT 2058.020000 1433.520000 2059.120000 1434.000000 ;
+ RECT 2058.020000 1428.080000 2059.120000 1428.560000 ;
+ RECT 2058.020000 1422.640000 2059.120000 1423.120000 ;
+ RECT 2103.020000 1417.200000 2104.120000 1417.680000 ;
+ RECT 2103.020000 1411.760000 2104.120000 1412.240000 ;
+ RECT 2103.020000 1406.320000 2104.120000 1406.800000 ;
+ RECT 2103.020000 1400.880000 2104.120000 1401.360000 ;
+ RECT 2058.020000 1417.200000 2059.120000 1417.680000 ;
+ RECT 2058.020000 1411.760000 2059.120000 1412.240000 ;
+ RECT 2058.020000 1406.320000 2059.120000 1406.800000 ;
+ RECT 2058.020000 1400.880000 2059.120000 1401.360000 ;
+ RECT 2053.890000 1422.640000 2054.890000 1423.120000 ;
+ RECT 2053.890000 1428.080000 2054.890000 1428.560000 ;
+ RECT 2053.890000 1433.520000 2054.890000 1434.000000 ;
+ RECT 2053.890000 1438.960000 2054.890000 1439.440000 ;
+ RECT 2053.890000 1444.400000 2054.890000 1444.880000 ;
+ RECT 2053.890000 1400.880000 2054.890000 1401.360000 ;
+ RECT 2053.890000 1406.320000 2054.890000 1406.800000 ;
+ RECT 2053.890000 1411.760000 2054.890000 1412.240000 ;
+ RECT 2053.890000 1417.200000 2054.890000 1417.680000 ;
+ RECT 2103.020000 1395.440000 2104.120000 1395.920000 ;
+ RECT 2103.020000 1390.000000 2104.120000 1390.480000 ;
+ RECT 2103.020000 1384.560000 2104.120000 1385.040000 ;
+ RECT 2103.020000 1379.120000 2104.120000 1379.600000 ;
+ RECT 2103.020000 1373.680000 2104.120000 1374.160000 ;
+ RECT 2058.020000 1395.440000 2059.120000 1395.920000 ;
+ RECT 2058.020000 1390.000000 2059.120000 1390.480000 ;
+ RECT 2058.020000 1384.560000 2059.120000 1385.040000 ;
+ RECT 2058.020000 1379.120000 2059.120000 1379.600000 ;
+ RECT 2058.020000 1373.680000 2059.120000 1374.160000 ;
+ RECT 2103.020000 1357.360000 2104.120000 1357.840000 ;
+ RECT 2103.020000 1351.920000 2104.120000 1352.400000 ;
+ RECT 2103.020000 1362.800000 2104.120000 1363.280000 ;
+ RECT 2103.020000 1368.240000 2104.120000 1368.720000 ;
+ RECT 2058.020000 1357.360000 2059.120000 1357.840000 ;
+ RECT 2058.020000 1351.920000 2059.120000 1352.400000 ;
+ RECT 2058.020000 1362.800000 2059.120000 1363.280000 ;
+ RECT 2058.020000 1368.240000 2059.120000 1368.720000 ;
+ RECT 2053.890000 1373.680000 2054.890000 1374.160000 ;
+ RECT 2053.890000 1379.120000 2054.890000 1379.600000 ;
+ RECT 2053.890000 1384.560000 2054.890000 1385.040000 ;
+ RECT 2053.890000 1390.000000 2054.890000 1390.480000 ;
+ RECT 2053.890000 1395.440000 2054.890000 1395.920000 ;
+ RECT 2053.890000 1351.920000 2054.890000 1352.400000 ;
+ RECT 2053.890000 1357.360000 2054.890000 1357.840000 ;
+ RECT 2053.890000 1362.800000 2054.890000 1363.280000 ;
+ RECT 2053.890000 1368.240000 2054.890000 1368.720000 ;
+ RECT 2051.060000 1542.280000 2161.000000 1543.280000 ;
+ RECT 2051.060000 1349.910000 2161.000000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1347.060000 2054.890000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1546.320000 2054.890000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 1347.060000 2158.170000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 1546.320000 2158.170000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1349.910000 2052.060000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1349.910000 2161.000000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1542.280000 2052.060000 1543.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1542.280000 2161.000000 1543.280000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1146.800000 2054.890000 1347.060000 ;
+ RECT 2157.170000 1146.800000 2158.170000 1347.060000 ;
+ RECT 2058.020000 1149.650000 2059.120000 1343.020000 ;
+ RECT 2103.020000 1149.650000 2104.120000 1343.020000 ;
+ RECT 2148.020000 1149.650000 2149.120000 1343.020000 ;
+ LAYER met3 ;
+ RECT 2157.170000 1325.740000 2158.170000 1326.220000 ;
+ RECT 2157.170000 1331.180000 2158.170000 1331.660000 ;
+ RECT 2157.170000 1336.620000 2158.170000 1337.100000 ;
+ RECT 2157.170000 1298.540000 2158.170000 1299.020000 ;
+ RECT 2157.170000 1303.980000 2158.170000 1304.460000 ;
+ RECT 2157.170000 1309.420000 2158.170000 1309.900000 ;
+ RECT 2157.170000 1314.860000 2158.170000 1315.340000 ;
+ RECT 2157.170000 1320.300000 2158.170000 1320.780000 ;
+ RECT 2148.020000 1325.740000 2149.120000 1326.220000 ;
+ RECT 2148.020000 1331.180000 2149.120000 1331.660000 ;
+ RECT 2148.020000 1336.620000 2149.120000 1337.100000 ;
+ RECT 2148.020000 1298.540000 2149.120000 1299.020000 ;
+ RECT 2148.020000 1303.980000 2149.120000 1304.460000 ;
+ RECT 2148.020000 1309.420000 2149.120000 1309.900000 ;
+ RECT 2148.020000 1314.860000 2149.120000 1315.340000 ;
+ RECT 2148.020000 1320.300000 2149.120000 1320.780000 ;
+ RECT 2157.170000 1276.780000 2158.170000 1277.260000 ;
+ RECT 2157.170000 1282.220000 2158.170000 1282.700000 ;
+ RECT 2157.170000 1287.660000 2158.170000 1288.140000 ;
+ RECT 2157.170000 1293.100000 2158.170000 1293.580000 ;
+ RECT 2157.170000 1249.580000 2158.170000 1250.060000 ;
+ RECT 2157.170000 1255.020000 2158.170000 1255.500000 ;
+ RECT 2157.170000 1260.460000 2158.170000 1260.940000 ;
+ RECT 2157.170000 1265.900000 2158.170000 1266.380000 ;
+ RECT 2157.170000 1271.340000 2158.170000 1271.820000 ;
+ RECT 2148.020000 1293.100000 2149.120000 1293.580000 ;
+ RECT 2148.020000 1287.660000 2149.120000 1288.140000 ;
+ RECT 2148.020000 1282.220000 2149.120000 1282.700000 ;
+ RECT 2148.020000 1276.780000 2149.120000 1277.260000 ;
+ RECT 2148.020000 1271.340000 2149.120000 1271.820000 ;
+ RECT 2148.020000 1265.900000 2149.120000 1266.380000 ;
+ RECT 2148.020000 1260.460000 2149.120000 1260.940000 ;
+ RECT 2148.020000 1249.580000 2149.120000 1250.060000 ;
+ RECT 2148.020000 1255.020000 2149.120000 1255.500000 ;
+ RECT 2103.020000 1336.620000 2104.120000 1337.100000 ;
+ RECT 2103.020000 1331.180000 2104.120000 1331.660000 ;
+ RECT 2103.020000 1325.740000 2104.120000 1326.220000 ;
+ RECT 2058.020000 1336.620000 2059.120000 1337.100000 ;
+ RECT 2058.020000 1331.180000 2059.120000 1331.660000 ;
+ RECT 2058.020000 1325.740000 2059.120000 1326.220000 ;
+ RECT 2103.020000 1314.860000 2104.120000 1315.340000 ;
+ RECT 2103.020000 1309.420000 2104.120000 1309.900000 ;
+ RECT 2103.020000 1303.980000 2104.120000 1304.460000 ;
+ RECT 2103.020000 1298.540000 2104.120000 1299.020000 ;
+ RECT 2103.020000 1320.300000 2104.120000 1320.780000 ;
+ RECT 2058.020000 1320.300000 2059.120000 1320.780000 ;
+ RECT 2058.020000 1314.860000 2059.120000 1315.340000 ;
+ RECT 2058.020000 1309.420000 2059.120000 1309.900000 ;
+ RECT 2058.020000 1303.980000 2059.120000 1304.460000 ;
+ RECT 2058.020000 1298.540000 2059.120000 1299.020000 ;
+ RECT 2053.890000 1325.740000 2054.890000 1326.220000 ;
+ RECT 2053.890000 1331.180000 2054.890000 1331.660000 ;
+ RECT 2053.890000 1336.620000 2054.890000 1337.100000 ;
+ RECT 2053.890000 1298.540000 2054.890000 1299.020000 ;
+ RECT 2053.890000 1303.980000 2054.890000 1304.460000 ;
+ RECT 2053.890000 1309.420000 2054.890000 1309.900000 ;
+ RECT 2053.890000 1314.860000 2054.890000 1315.340000 ;
+ RECT 2053.890000 1320.300000 2054.890000 1320.780000 ;
+ RECT 2103.020000 1293.100000 2104.120000 1293.580000 ;
+ RECT 2103.020000 1287.660000 2104.120000 1288.140000 ;
+ RECT 2103.020000 1282.220000 2104.120000 1282.700000 ;
+ RECT 2103.020000 1276.780000 2104.120000 1277.260000 ;
+ RECT 2058.020000 1293.100000 2059.120000 1293.580000 ;
+ RECT 2058.020000 1287.660000 2059.120000 1288.140000 ;
+ RECT 2058.020000 1282.220000 2059.120000 1282.700000 ;
+ RECT 2058.020000 1276.780000 2059.120000 1277.260000 ;
+ RECT 2103.020000 1271.340000 2104.120000 1271.820000 ;
+ RECT 2103.020000 1255.020000 2104.120000 1255.500000 ;
+ RECT 2103.020000 1249.580000 2104.120000 1250.060000 ;
+ RECT 2103.020000 1260.460000 2104.120000 1260.940000 ;
+ RECT 2103.020000 1265.900000 2104.120000 1266.380000 ;
+ RECT 2058.020000 1271.340000 2059.120000 1271.820000 ;
+ RECT 2058.020000 1255.020000 2059.120000 1255.500000 ;
+ RECT 2058.020000 1249.580000 2059.120000 1250.060000 ;
+ RECT 2058.020000 1260.460000 2059.120000 1260.940000 ;
+ RECT 2058.020000 1265.900000 2059.120000 1266.380000 ;
+ RECT 2053.890000 1276.780000 2054.890000 1277.260000 ;
+ RECT 2053.890000 1282.220000 2054.890000 1282.700000 ;
+ RECT 2053.890000 1287.660000 2054.890000 1288.140000 ;
+ RECT 2053.890000 1293.100000 2054.890000 1293.580000 ;
+ RECT 2053.890000 1249.580000 2054.890000 1250.060000 ;
+ RECT 2053.890000 1255.020000 2054.890000 1255.500000 ;
+ RECT 2053.890000 1260.460000 2054.890000 1260.940000 ;
+ RECT 2053.890000 1265.900000 2054.890000 1266.380000 ;
+ RECT 2053.890000 1271.340000 2054.890000 1271.820000 ;
+ RECT 2157.170000 1222.380000 2158.170000 1222.860000 ;
+ RECT 2157.170000 1227.820000 2158.170000 1228.300000 ;
+ RECT 2157.170000 1233.260000 2158.170000 1233.740000 ;
+ RECT 2157.170000 1238.700000 2158.170000 1239.180000 ;
+ RECT 2157.170000 1244.140000 2158.170000 1244.620000 ;
+ RECT 2157.170000 1200.620000 2158.170000 1201.100000 ;
+ RECT 2157.170000 1206.060000 2158.170000 1206.540000 ;
+ RECT 2157.170000 1211.500000 2158.170000 1211.980000 ;
+ RECT 2157.170000 1216.940000 2158.170000 1217.420000 ;
+ RECT 2148.020000 1222.380000 2149.120000 1222.860000 ;
+ RECT 2148.020000 1227.820000 2149.120000 1228.300000 ;
+ RECT 2148.020000 1233.260000 2149.120000 1233.740000 ;
+ RECT 2148.020000 1238.700000 2149.120000 1239.180000 ;
+ RECT 2148.020000 1244.140000 2149.120000 1244.620000 ;
+ RECT 2148.020000 1200.620000 2149.120000 1201.100000 ;
+ RECT 2148.020000 1206.060000 2149.120000 1206.540000 ;
+ RECT 2148.020000 1211.500000 2149.120000 1211.980000 ;
+ RECT 2148.020000 1216.940000 2149.120000 1217.420000 ;
+ RECT 2157.170000 1173.420000 2158.170000 1173.900000 ;
+ RECT 2157.170000 1178.860000 2158.170000 1179.340000 ;
+ RECT 2157.170000 1184.300000 2158.170000 1184.780000 ;
+ RECT 2157.170000 1189.740000 2158.170000 1190.220000 ;
+ RECT 2157.170000 1195.180000 2158.170000 1195.660000 ;
+ RECT 2157.170000 1151.660000 2158.170000 1152.140000 ;
+ RECT 2157.170000 1157.100000 2158.170000 1157.580000 ;
+ RECT 2157.170000 1162.540000 2158.170000 1163.020000 ;
+ RECT 2157.170000 1167.980000 2158.170000 1168.460000 ;
+ RECT 2148.020000 1195.180000 2149.120000 1195.660000 ;
+ RECT 2148.020000 1189.740000 2149.120000 1190.220000 ;
+ RECT 2148.020000 1184.300000 2149.120000 1184.780000 ;
+ RECT 2148.020000 1178.860000 2149.120000 1179.340000 ;
+ RECT 2148.020000 1173.420000 2149.120000 1173.900000 ;
+ RECT 2148.020000 1167.980000 2149.120000 1168.460000 ;
+ RECT 2148.020000 1162.540000 2149.120000 1163.020000 ;
+ RECT 2148.020000 1151.660000 2149.120000 1152.140000 ;
+ RECT 2148.020000 1157.100000 2149.120000 1157.580000 ;
+ RECT 2103.020000 1244.140000 2104.120000 1244.620000 ;
+ RECT 2103.020000 1238.700000 2104.120000 1239.180000 ;
+ RECT 2103.020000 1233.260000 2104.120000 1233.740000 ;
+ RECT 2103.020000 1222.380000 2104.120000 1222.860000 ;
+ RECT 2103.020000 1227.820000 2104.120000 1228.300000 ;
+ RECT 2058.020000 1244.140000 2059.120000 1244.620000 ;
+ RECT 2058.020000 1238.700000 2059.120000 1239.180000 ;
+ RECT 2058.020000 1233.260000 2059.120000 1233.740000 ;
+ RECT 2058.020000 1227.820000 2059.120000 1228.300000 ;
+ RECT 2058.020000 1222.380000 2059.120000 1222.860000 ;
+ RECT 2103.020000 1216.940000 2104.120000 1217.420000 ;
+ RECT 2103.020000 1211.500000 2104.120000 1211.980000 ;
+ RECT 2103.020000 1206.060000 2104.120000 1206.540000 ;
+ RECT 2103.020000 1200.620000 2104.120000 1201.100000 ;
+ RECT 2058.020000 1216.940000 2059.120000 1217.420000 ;
+ RECT 2058.020000 1211.500000 2059.120000 1211.980000 ;
+ RECT 2058.020000 1206.060000 2059.120000 1206.540000 ;
+ RECT 2058.020000 1200.620000 2059.120000 1201.100000 ;
+ RECT 2053.890000 1222.380000 2054.890000 1222.860000 ;
+ RECT 2053.890000 1227.820000 2054.890000 1228.300000 ;
+ RECT 2053.890000 1233.260000 2054.890000 1233.740000 ;
+ RECT 2053.890000 1238.700000 2054.890000 1239.180000 ;
+ RECT 2053.890000 1244.140000 2054.890000 1244.620000 ;
+ RECT 2053.890000 1200.620000 2054.890000 1201.100000 ;
+ RECT 2053.890000 1206.060000 2054.890000 1206.540000 ;
+ RECT 2053.890000 1211.500000 2054.890000 1211.980000 ;
+ RECT 2053.890000 1216.940000 2054.890000 1217.420000 ;
+ RECT 2103.020000 1195.180000 2104.120000 1195.660000 ;
+ RECT 2103.020000 1189.740000 2104.120000 1190.220000 ;
+ RECT 2103.020000 1184.300000 2104.120000 1184.780000 ;
+ RECT 2103.020000 1178.860000 2104.120000 1179.340000 ;
+ RECT 2103.020000 1173.420000 2104.120000 1173.900000 ;
+ RECT 2058.020000 1195.180000 2059.120000 1195.660000 ;
+ RECT 2058.020000 1189.740000 2059.120000 1190.220000 ;
+ RECT 2058.020000 1184.300000 2059.120000 1184.780000 ;
+ RECT 2058.020000 1178.860000 2059.120000 1179.340000 ;
+ RECT 2058.020000 1173.420000 2059.120000 1173.900000 ;
+ RECT 2103.020000 1157.100000 2104.120000 1157.580000 ;
+ RECT 2103.020000 1151.660000 2104.120000 1152.140000 ;
+ RECT 2103.020000 1162.540000 2104.120000 1163.020000 ;
+ RECT 2103.020000 1167.980000 2104.120000 1168.460000 ;
+ RECT 2058.020000 1157.100000 2059.120000 1157.580000 ;
+ RECT 2058.020000 1151.660000 2059.120000 1152.140000 ;
+ RECT 2058.020000 1162.540000 2059.120000 1163.020000 ;
+ RECT 2058.020000 1167.980000 2059.120000 1168.460000 ;
+ RECT 2053.890000 1173.420000 2054.890000 1173.900000 ;
+ RECT 2053.890000 1178.860000 2054.890000 1179.340000 ;
+ RECT 2053.890000 1184.300000 2054.890000 1184.780000 ;
+ RECT 2053.890000 1189.740000 2054.890000 1190.220000 ;
+ RECT 2053.890000 1195.180000 2054.890000 1195.660000 ;
+ RECT 2053.890000 1151.660000 2054.890000 1152.140000 ;
+ RECT 2053.890000 1157.100000 2054.890000 1157.580000 ;
+ RECT 2053.890000 1162.540000 2054.890000 1163.020000 ;
+ RECT 2053.890000 1167.980000 2054.890000 1168.460000 ;
+ RECT 2051.060000 1342.020000 2161.000000 1343.020000 ;
+ RECT 2051.060000 1149.650000 2161.000000 1150.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1146.800000 2054.890000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1346.060000 2054.890000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 1146.800000 2158.170000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 1346.060000 2158.170000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1149.650000 2052.060000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1149.650000 2161.000000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1342.020000 2052.060000 1343.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1342.020000 2161.000000 1343.020000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 946.540000 2054.890000 1146.800000 ;
+ RECT 2157.170000 946.540000 2158.170000 1146.800000 ;
+ RECT 2058.020000 949.390000 2059.120000 1142.760000 ;
+ RECT 2103.020000 949.390000 2104.120000 1142.760000 ;
+ RECT 2148.020000 949.390000 2149.120000 1142.760000 ;
+ LAYER met3 ;
+ RECT 2157.170000 1125.480000 2158.170000 1125.960000 ;
+ RECT 2157.170000 1130.920000 2158.170000 1131.400000 ;
+ RECT 2157.170000 1136.360000 2158.170000 1136.840000 ;
+ RECT 2157.170000 1098.280000 2158.170000 1098.760000 ;
+ RECT 2157.170000 1103.720000 2158.170000 1104.200000 ;
+ RECT 2157.170000 1109.160000 2158.170000 1109.640000 ;
+ RECT 2157.170000 1114.600000 2158.170000 1115.080000 ;
+ RECT 2157.170000 1120.040000 2158.170000 1120.520000 ;
+ RECT 2148.020000 1125.480000 2149.120000 1125.960000 ;
+ RECT 2148.020000 1130.920000 2149.120000 1131.400000 ;
+ RECT 2148.020000 1136.360000 2149.120000 1136.840000 ;
+ RECT 2148.020000 1098.280000 2149.120000 1098.760000 ;
+ RECT 2148.020000 1103.720000 2149.120000 1104.200000 ;
+ RECT 2148.020000 1109.160000 2149.120000 1109.640000 ;
+ RECT 2148.020000 1114.600000 2149.120000 1115.080000 ;
+ RECT 2148.020000 1120.040000 2149.120000 1120.520000 ;
+ RECT 2157.170000 1076.520000 2158.170000 1077.000000 ;
+ RECT 2157.170000 1081.960000 2158.170000 1082.440000 ;
+ RECT 2157.170000 1087.400000 2158.170000 1087.880000 ;
+ RECT 2157.170000 1092.840000 2158.170000 1093.320000 ;
+ RECT 2157.170000 1049.320000 2158.170000 1049.800000 ;
+ RECT 2157.170000 1054.760000 2158.170000 1055.240000 ;
+ RECT 2157.170000 1060.200000 2158.170000 1060.680000 ;
+ RECT 2157.170000 1065.640000 2158.170000 1066.120000 ;
+ RECT 2157.170000 1071.080000 2158.170000 1071.560000 ;
+ RECT 2148.020000 1092.840000 2149.120000 1093.320000 ;
+ RECT 2148.020000 1087.400000 2149.120000 1087.880000 ;
+ RECT 2148.020000 1081.960000 2149.120000 1082.440000 ;
+ RECT 2148.020000 1076.520000 2149.120000 1077.000000 ;
+ RECT 2148.020000 1071.080000 2149.120000 1071.560000 ;
+ RECT 2148.020000 1065.640000 2149.120000 1066.120000 ;
+ RECT 2148.020000 1060.200000 2149.120000 1060.680000 ;
+ RECT 2148.020000 1049.320000 2149.120000 1049.800000 ;
+ RECT 2148.020000 1054.760000 2149.120000 1055.240000 ;
+ RECT 2103.020000 1136.360000 2104.120000 1136.840000 ;
+ RECT 2103.020000 1130.920000 2104.120000 1131.400000 ;
+ RECT 2103.020000 1125.480000 2104.120000 1125.960000 ;
+ RECT 2058.020000 1136.360000 2059.120000 1136.840000 ;
+ RECT 2058.020000 1130.920000 2059.120000 1131.400000 ;
+ RECT 2058.020000 1125.480000 2059.120000 1125.960000 ;
+ RECT 2103.020000 1114.600000 2104.120000 1115.080000 ;
+ RECT 2103.020000 1109.160000 2104.120000 1109.640000 ;
+ RECT 2103.020000 1103.720000 2104.120000 1104.200000 ;
+ RECT 2103.020000 1098.280000 2104.120000 1098.760000 ;
+ RECT 2103.020000 1120.040000 2104.120000 1120.520000 ;
+ RECT 2058.020000 1120.040000 2059.120000 1120.520000 ;
+ RECT 2058.020000 1114.600000 2059.120000 1115.080000 ;
+ RECT 2058.020000 1109.160000 2059.120000 1109.640000 ;
+ RECT 2058.020000 1103.720000 2059.120000 1104.200000 ;
+ RECT 2058.020000 1098.280000 2059.120000 1098.760000 ;
+ RECT 2053.890000 1125.480000 2054.890000 1125.960000 ;
+ RECT 2053.890000 1130.920000 2054.890000 1131.400000 ;
+ RECT 2053.890000 1136.360000 2054.890000 1136.840000 ;
+ RECT 2053.890000 1098.280000 2054.890000 1098.760000 ;
+ RECT 2053.890000 1103.720000 2054.890000 1104.200000 ;
+ RECT 2053.890000 1109.160000 2054.890000 1109.640000 ;
+ RECT 2053.890000 1114.600000 2054.890000 1115.080000 ;
+ RECT 2053.890000 1120.040000 2054.890000 1120.520000 ;
+ RECT 2103.020000 1092.840000 2104.120000 1093.320000 ;
+ RECT 2103.020000 1087.400000 2104.120000 1087.880000 ;
+ RECT 2103.020000 1081.960000 2104.120000 1082.440000 ;
+ RECT 2103.020000 1076.520000 2104.120000 1077.000000 ;
+ RECT 2058.020000 1092.840000 2059.120000 1093.320000 ;
+ RECT 2058.020000 1087.400000 2059.120000 1087.880000 ;
+ RECT 2058.020000 1081.960000 2059.120000 1082.440000 ;
+ RECT 2058.020000 1076.520000 2059.120000 1077.000000 ;
+ RECT 2103.020000 1071.080000 2104.120000 1071.560000 ;
+ RECT 2103.020000 1054.760000 2104.120000 1055.240000 ;
+ RECT 2103.020000 1049.320000 2104.120000 1049.800000 ;
+ RECT 2103.020000 1060.200000 2104.120000 1060.680000 ;
+ RECT 2103.020000 1065.640000 2104.120000 1066.120000 ;
+ RECT 2058.020000 1071.080000 2059.120000 1071.560000 ;
+ RECT 2058.020000 1054.760000 2059.120000 1055.240000 ;
+ RECT 2058.020000 1049.320000 2059.120000 1049.800000 ;
+ RECT 2058.020000 1060.200000 2059.120000 1060.680000 ;
+ RECT 2058.020000 1065.640000 2059.120000 1066.120000 ;
+ RECT 2053.890000 1076.520000 2054.890000 1077.000000 ;
+ RECT 2053.890000 1081.960000 2054.890000 1082.440000 ;
+ RECT 2053.890000 1087.400000 2054.890000 1087.880000 ;
+ RECT 2053.890000 1092.840000 2054.890000 1093.320000 ;
+ RECT 2053.890000 1049.320000 2054.890000 1049.800000 ;
+ RECT 2053.890000 1054.760000 2054.890000 1055.240000 ;
+ RECT 2053.890000 1060.200000 2054.890000 1060.680000 ;
+ RECT 2053.890000 1065.640000 2054.890000 1066.120000 ;
+ RECT 2053.890000 1071.080000 2054.890000 1071.560000 ;
+ RECT 2157.170000 1022.120000 2158.170000 1022.600000 ;
+ RECT 2157.170000 1027.560000 2158.170000 1028.040000 ;
+ RECT 2157.170000 1033.000000 2158.170000 1033.480000 ;
+ RECT 2157.170000 1038.440000 2158.170000 1038.920000 ;
+ RECT 2157.170000 1043.880000 2158.170000 1044.360000 ;
+ RECT 2157.170000 1000.360000 2158.170000 1000.840000 ;
+ RECT 2157.170000 1005.800000 2158.170000 1006.280000 ;
+ RECT 2157.170000 1011.240000 2158.170000 1011.720000 ;
+ RECT 2157.170000 1016.680000 2158.170000 1017.160000 ;
+ RECT 2148.020000 1022.120000 2149.120000 1022.600000 ;
+ RECT 2148.020000 1027.560000 2149.120000 1028.040000 ;
+ RECT 2148.020000 1033.000000 2149.120000 1033.480000 ;
+ RECT 2148.020000 1038.440000 2149.120000 1038.920000 ;
+ RECT 2148.020000 1043.880000 2149.120000 1044.360000 ;
+ RECT 2148.020000 1000.360000 2149.120000 1000.840000 ;
+ RECT 2148.020000 1005.800000 2149.120000 1006.280000 ;
+ RECT 2148.020000 1011.240000 2149.120000 1011.720000 ;
+ RECT 2148.020000 1016.680000 2149.120000 1017.160000 ;
+ RECT 2157.170000 973.160000 2158.170000 973.640000 ;
+ RECT 2157.170000 978.600000 2158.170000 979.080000 ;
+ RECT 2157.170000 984.040000 2158.170000 984.520000 ;
+ RECT 2157.170000 989.480000 2158.170000 989.960000 ;
+ RECT 2157.170000 994.920000 2158.170000 995.400000 ;
+ RECT 2157.170000 951.400000 2158.170000 951.880000 ;
+ RECT 2157.170000 956.840000 2158.170000 957.320000 ;
+ RECT 2157.170000 962.280000 2158.170000 962.760000 ;
+ RECT 2157.170000 967.720000 2158.170000 968.200000 ;
+ RECT 2148.020000 994.920000 2149.120000 995.400000 ;
+ RECT 2148.020000 989.480000 2149.120000 989.960000 ;
+ RECT 2148.020000 984.040000 2149.120000 984.520000 ;
+ RECT 2148.020000 978.600000 2149.120000 979.080000 ;
+ RECT 2148.020000 973.160000 2149.120000 973.640000 ;
+ RECT 2148.020000 967.720000 2149.120000 968.200000 ;
+ RECT 2148.020000 962.280000 2149.120000 962.760000 ;
+ RECT 2148.020000 951.400000 2149.120000 951.880000 ;
+ RECT 2148.020000 956.840000 2149.120000 957.320000 ;
+ RECT 2103.020000 1043.880000 2104.120000 1044.360000 ;
+ RECT 2103.020000 1038.440000 2104.120000 1038.920000 ;
+ RECT 2103.020000 1033.000000 2104.120000 1033.480000 ;
+ RECT 2103.020000 1022.120000 2104.120000 1022.600000 ;
+ RECT 2103.020000 1027.560000 2104.120000 1028.040000 ;
+ RECT 2058.020000 1043.880000 2059.120000 1044.360000 ;
+ RECT 2058.020000 1038.440000 2059.120000 1038.920000 ;
+ RECT 2058.020000 1033.000000 2059.120000 1033.480000 ;
+ RECT 2058.020000 1027.560000 2059.120000 1028.040000 ;
+ RECT 2058.020000 1022.120000 2059.120000 1022.600000 ;
+ RECT 2103.020000 1016.680000 2104.120000 1017.160000 ;
+ RECT 2103.020000 1011.240000 2104.120000 1011.720000 ;
+ RECT 2103.020000 1005.800000 2104.120000 1006.280000 ;
+ RECT 2103.020000 1000.360000 2104.120000 1000.840000 ;
+ RECT 2058.020000 1016.680000 2059.120000 1017.160000 ;
+ RECT 2058.020000 1011.240000 2059.120000 1011.720000 ;
+ RECT 2058.020000 1005.800000 2059.120000 1006.280000 ;
+ RECT 2058.020000 1000.360000 2059.120000 1000.840000 ;
+ RECT 2053.890000 1022.120000 2054.890000 1022.600000 ;
+ RECT 2053.890000 1027.560000 2054.890000 1028.040000 ;
+ RECT 2053.890000 1033.000000 2054.890000 1033.480000 ;
+ RECT 2053.890000 1038.440000 2054.890000 1038.920000 ;
+ RECT 2053.890000 1043.880000 2054.890000 1044.360000 ;
+ RECT 2053.890000 1000.360000 2054.890000 1000.840000 ;
+ RECT 2053.890000 1005.800000 2054.890000 1006.280000 ;
+ RECT 2053.890000 1011.240000 2054.890000 1011.720000 ;
+ RECT 2053.890000 1016.680000 2054.890000 1017.160000 ;
+ RECT 2103.020000 994.920000 2104.120000 995.400000 ;
+ RECT 2103.020000 989.480000 2104.120000 989.960000 ;
+ RECT 2103.020000 984.040000 2104.120000 984.520000 ;
+ RECT 2103.020000 978.600000 2104.120000 979.080000 ;
+ RECT 2103.020000 973.160000 2104.120000 973.640000 ;
+ RECT 2058.020000 994.920000 2059.120000 995.400000 ;
+ RECT 2058.020000 989.480000 2059.120000 989.960000 ;
+ RECT 2058.020000 984.040000 2059.120000 984.520000 ;
+ RECT 2058.020000 978.600000 2059.120000 979.080000 ;
+ RECT 2058.020000 973.160000 2059.120000 973.640000 ;
+ RECT 2103.020000 956.840000 2104.120000 957.320000 ;
+ RECT 2103.020000 951.400000 2104.120000 951.880000 ;
+ RECT 2103.020000 962.280000 2104.120000 962.760000 ;
+ RECT 2103.020000 967.720000 2104.120000 968.200000 ;
+ RECT 2058.020000 956.840000 2059.120000 957.320000 ;
+ RECT 2058.020000 951.400000 2059.120000 951.880000 ;
+ RECT 2058.020000 962.280000 2059.120000 962.760000 ;
+ RECT 2058.020000 967.720000 2059.120000 968.200000 ;
+ RECT 2053.890000 973.160000 2054.890000 973.640000 ;
+ RECT 2053.890000 978.600000 2054.890000 979.080000 ;
+ RECT 2053.890000 984.040000 2054.890000 984.520000 ;
+ RECT 2053.890000 989.480000 2054.890000 989.960000 ;
+ RECT 2053.890000 994.920000 2054.890000 995.400000 ;
+ RECT 2053.890000 951.400000 2054.890000 951.880000 ;
+ RECT 2053.890000 956.840000 2054.890000 957.320000 ;
+ RECT 2053.890000 962.280000 2054.890000 962.760000 ;
+ RECT 2053.890000 967.720000 2054.890000 968.200000 ;
+ RECT 2051.060000 1141.760000 2161.000000 1142.760000 ;
+ RECT 2051.060000 949.390000 2161.000000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 946.540000 2054.890000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1145.800000 2054.890000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 946.540000 2158.170000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 1145.800000 2158.170000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 949.390000 2052.060000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 949.390000 2161.000000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1141.760000 2052.060000 1142.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1141.760000 2161.000000 1142.760000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 746.280000 2054.890000 946.540000 ;
+ RECT 2157.170000 746.280000 2158.170000 946.540000 ;
+ RECT 2058.020000 749.130000 2059.120000 942.500000 ;
+ RECT 2103.020000 749.130000 2104.120000 942.500000 ;
+ RECT 2148.020000 749.130000 2149.120000 942.500000 ;
+ LAYER met3 ;
+ RECT 2157.170000 925.220000 2158.170000 925.700000 ;
+ RECT 2157.170000 930.660000 2158.170000 931.140000 ;
+ RECT 2157.170000 936.100000 2158.170000 936.580000 ;
+ RECT 2157.170000 898.020000 2158.170000 898.500000 ;
+ RECT 2157.170000 903.460000 2158.170000 903.940000 ;
+ RECT 2157.170000 908.900000 2158.170000 909.380000 ;
+ RECT 2157.170000 914.340000 2158.170000 914.820000 ;
+ RECT 2157.170000 919.780000 2158.170000 920.260000 ;
+ RECT 2148.020000 925.220000 2149.120000 925.700000 ;
+ RECT 2148.020000 930.660000 2149.120000 931.140000 ;
+ RECT 2148.020000 936.100000 2149.120000 936.580000 ;
+ RECT 2148.020000 898.020000 2149.120000 898.500000 ;
+ RECT 2148.020000 903.460000 2149.120000 903.940000 ;
+ RECT 2148.020000 908.900000 2149.120000 909.380000 ;
+ RECT 2148.020000 914.340000 2149.120000 914.820000 ;
+ RECT 2148.020000 919.780000 2149.120000 920.260000 ;
+ RECT 2157.170000 876.260000 2158.170000 876.740000 ;
+ RECT 2157.170000 881.700000 2158.170000 882.180000 ;
+ RECT 2157.170000 887.140000 2158.170000 887.620000 ;
+ RECT 2157.170000 892.580000 2158.170000 893.060000 ;
+ RECT 2157.170000 849.060000 2158.170000 849.540000 ;
+ RECT 2157.170000 854.500000 2158.170000 854.980000 ;
+ RECT 2157.170000 859.940000 2158.170000 860.420000 ;
+ RECT 2157.170000 865.380000 2158.170000 865.860000 ;
+ RECT 2157.170000 870.820000 2158.170000 871.300000 ;
+ RECT 2148.020000 892.580000 2149.120000 893.060000 ;
+ RECT 2148.020000 887.140000 2149.120000 887.620000 ;
+ RECT 2148.020000 881.700000 2149.120000 882.180000 ;
+ RECT 2148.020000 876.260000 2149.120000 876.740000 ;
+ RECT 2148.020000 870.820000 2149.120000 871.300000 ;
+ RECT 2148.020000 865.380000 2149.120000 865.860000 ;
+ RECT 2148.020000 859.940000 2149.120000 860.420000 ;
+ RECT 2148.020000 849.060000 2149.120000 849.540000 ;
+ RECT 2148.020000 854.500000 2149.120000 854.980000 ;
+ RECT 2103.020000 936.100000 2104.120000 936.580000 ;
+ RECT 2103.020000 930.660000 2104.120000 931.140000 ;
+ RECT 2103.020000 925.220000 2104.120000 925.700000 ;
+ RECT 2058.020000 936.100000 2059.120000 936.580000 ;
+ RECT 2058.020000 930.660000 2059.120000 931.140000 ;
+ RECT 2058.020000 925.220000 2059.120000 925.700000 ;
+ RECT 2103.020000 914.340000 2104.120000 914.820000 ;
+ RECT 2103.020000 908.900000 2104.120000 909.380000 ;
+ RECT 2103.020000 903.460000 2104.120000 903.940000 ;
+ RECT 2103.020000 898.020000 2104.120000 898.500000 ;
+ RECT 2103.020000 919.780000 2104.120000 920.260000 ;
+ RECT 2058.020000 919.780000 2059.120000 920.260000 ;
+ RECT 2058.020000 914.340000 2059.120000 914.820000 ;
+ RECT 2058.020000 908.900000 2059.120000 909.380000 ;
+ RECT 2058.020000 903.460000 2059.120000 903.940000 ;
+ RECT 2058.020000 898.020000 2059.120000 898.500000 ;
+ RECT 2053.890000 925.220000 2054.890000 925.700000 ;
+ RECT 2053.890000 930.660000 2054.890000 931.140000 ;
+ RECT 2053.890000 936.100000 2054.890000 936.580000 ;
+ RECT 2053.890000 898.020000 2054.890000 898.500000 ;
+ RECT 2053.890000 903.460000 2054.890000 903.940000 ;
+ RECT 2053.890000 908.900000 2054.890000 909.380000 ;
+ RECT 2053.890000 914.340000 2054.890000 914.820000 ;
+ RECT 2053.890000 919.780000 2054.890000 920.260000 ;
+ RECT 2103.020000 892.580000 2104.120000 893.060000 ;
+ RECT 2103.020000 887.140000 2104.120000 887.620000 ;
+ RECT 2103.020000 881.700000 2104.120000 882.180000 ;
+ RECT 2103.020000 876.260000 2104.120000 876.740000 ;
+ RECT 2058.020000 892.580000 2059.120000 893.060000 ;
+ RECT 2058.020000 887.140000 2059.120000 887.620000 ;
+ RECT 2058.020000 881.700000 2059.120000 882.180000 ;
+ RECT 2058.020000 876.260000 2059.120000 876.740000 ;
+ RECT 2103.020000 870.820000 2104.120000 871.300000 ;
+ RECT 2103.020000 854.500000 2104.120000 854.980000 ;
+ RECT 2103.020000 849.060000 2104.120000 849.540000 ;
+ RECT 2103.020000 859.940000 2104.120000 860.420000 ;
+ RECT 2103.020000 865.380000 2104.120000 865.860000 ;
+ RECT 2058.020000 870.820000 2059.120000 871.300000 ;
+ RECT 2058.020000 854.500000 2059.120000 854.980000 ;
+ RECT 2058.020000 849.060000 2059.120000 849.540000 ;
+ RECT 2058.020000 859.940000 2059.120000 860.420000 ;
+ RECT 2058.020000 865.380000 2059.120000 865.860000 ;
+ RECT 2053.890000 876.260000 2054.890000 876.740000 ;
+ RECT 2053.890000 881.700000 2054.890000 882.180000 ;
+ RECT 2053.890000 887.140000 2054.890000 887.620000 ;
+ RECT 2053.890000 892.580000 2054.890000 893.060000 ;
+ RECT 2053.890000 849.060000 2054.890000 849.540000 ;
+ RECT 2053.890000 854.500000 2054.890000 854.980000 ;
+ RECT 2053.890000 859.940000 2054.890000 860.420000 ;
+ RECT 2053.890000 865.380000 2054.890000 865.860000 ;
+ RECT 2053.890000 870.820000 2054.890000 871.300000 ;
+ RECT 2157.170000 821.860000 2158.170000 822.340000 ;
+ RECT 2157.170000 827.300000 2158.170000 827.780000 ;
+ RECT 2157.170000 832.740000 2158.170000 833.220000 ;
+ RECT 2157.170000 838.180000 2158.170000 838.660000 ;
+ RECT 2157.170000 843.620000 2158.170000 844.100000 ;
+ RECT 2157.170000 800.100000 2158.170000 800.580000 ;
+ RECT 2157.170000 805.540000 2158.170000 806.020000 ;
+ RECT 2157.170000 810.980000 2158.170000 811.460000 ;
+ RECT 2157.170000 816.420000 2158.170000 816.900000 ;
+ RECT 2148.020000 821.860000 2149.120000 822.340000 ;
+ RECT 2148.020000 827.300000 2149.120000 827.780000 ;
+ RECT 2148.020000 832.740000 2149.120000 833.220000 ;
+ RECT 2148.020000 838.180000 2149.120000 838.660000 ;
+ RECT 2148.020000 843.620000 2149.120000 844.100000 ;
+ RECT 2148.020000 800.100000 2149.120000 800.580000 ;
+ RECT 2148.020000 805.540000 2149.120000 806.020000 ;
+ RECT 2148.020000 810.980000 2149.120000 811.460000 ;
+ RECT 2148.020000 816.420000 2149.120000 816.900000 ;
+ RECT 2157.170000 772.900000 2158.170000 773.380000 ;
+ RECT 2157.170000 778.340000 2158.170000 778.820000 ;
+ RECT 2157.170000 783.780000 2158.170000 784.260000 ;
+ RECT 2157.170000 789.220000 2158.170000 789.700000 ;
+ RECT 2157.170000 794.660000 2158.170000 795.140000 ;
+ RECT 2157.170000 751.140000 2158.170000 751.620000 ;
+ RECT 2157.170000 756.580000 2158.170000 757.060000 ;
+ RECT 2157.170000 762.020000 2158.170000 762.500000 ;
+ RECT 2157.170000 767.460000 2158.170000 767.940000 ;
+ RECT 2148.020000 794.660000 2149.120000 795.140000 ;
+ RECT 2148.020000 789.220000 2149.120000 789.700000 ;
+ RECT 2148.020000 783.780000 2149.120000 784.260000 ;
+ RECT 2148.020000 778.340000 2149.120000 778.820000 ;
+ RECT 2148.020000 772.900000 2149.120000 773.380000 ;
+ RECT 2148.020000 767.460000 2149.120000 767.940000 ;
+ RECT 2148.020000 762.020000 2149.120000 762.500000 ;
+ RECT 2148.020000 751.140000 2149.120000 751.620000 ;
+ RECT 2148.020000 756.580000 2149.120000 757.060000 ;
+ RECT 2103.020000 843.620000 2104.120000 844.100000 ;
+ RECT 2103.020000 838.180000 2104.120000 838.660000 ;
+ RECT 2103.020000 832.740000 2104.120000 833.220000 ;
+ RECT 2103.020000 821.860000 2104.120000 822.340000 ;
+ RECT 2103.020000 827.300000 2104.120000 827.780000 ;
+ RECT 2058.020000 843.620000 2059.120000 844.100000 ;
+ RECT 2058.020000 838.180000 2059.120000 838.660000 ;
+ RECT 2058.020000 832.740000 2059.120000 833.220000 ;
+ RECT 2058.020000 827.300000 2059.120000 827.780000 ;
+ RECT 2058.020000 821.860000 2059.120000 822.340000 ;
+ RECT 2103.020000 816.420000 2104.120000 816.900000 ;
+ RECT 2103.020000 810.980000 2104.120000 811.460000 ;
+ RECT 2103.020000 805.540000 2104.120000 806.020000 ;
+ RECT 2103.020000 800.100000 2104.120000 800.580000 ;
+ RECT 2058.020000 816.420000 2059.120000 816.900000 ;
+ RECT 2058.020000 810.980000 2059.120000 811.460000 ;
+ RECT 2058.020000 805.540000 2059.120000 806.020000 ;
+ RECT 2058.020000 800.100000 2059.120000 800.580000 ;
+ RECT 2053.890000 821.860000 2054.890000 822.340000 ;
+ RECT 2053.890000 827.300000 2054.890000 827.780000 ;
+ RECT 2053.890000 832.740000 2054.890000 833.220000 ;
+ RECT 2053.890000 838.180000 2054.890000 838.660000 ;
+ RECT 2053.890000 843.620000 2054.890000 844.100000 ;
+ RECT 2053.890000 800.100000 2054.890000 800.580000 ;
+ RECT 2053.890000 805.540000 2054.890000 806.020000 ;
+ RECT 2053.890000 810.980000 2054.890000 811.460000 ;
+ RECT 2053.890000 816.420000 2054.890000 816.900000 ;
+ RECT 2103.020000 794.660000 2104.120000 795.140000 ;
+ RECT 2103.020000 789.220000 2104.120000 789.700000 ;
+ RECT 2103.020000 783.780000 2104.120000 784.260000 ;
+ RECT 2103.020000 778.340000 2104.120000 778.820000 ;
+ RECT 2103.020000 772.900000 2104.120000 773.380000 ;
+ RECT 2058.020000 794.660000 2059.120000 795.140000 ;
+ RECT 2058.020000 789.220000 2059.120000 789.700000 ;
+ RECT 2058.020000 783.780000 2059.120000 784.260000 ;
+ RECT 2058.020000 778.340000 2059.120000 778.820000 ;
+ RECT 2058.020000 772.900000 2059.120000 773.380000 ;
+ RECT 2103.020000 756.580000 2104.120000 757.060000 ;
+ RECT 2103.020000 751.140000 2104.120000 751.620000 ;
+ RECT 2103.020000 762.020000 2104.120000 762.500000 ;
+ RECT 2103.020000 767.460000 2104.120000 767.940000 ;
+ RECT 2058.020000 756.580000 2059.120000 757.060000 ;
+ RECT 2058.020000 751.140000 2059.120000 751.620000 ;
+ RECT 2058.020000 762.020000 2059.120000 762.500000 ;
+ RECT 2058.020000 767.460000 2059.120000 767.940000 ;
+ RECT 2053.890000 772.900000 2054.890000 773.380000 ;
+ RECT 2053.890000 778.340000 2054.890000 778.820000 ;
+ RECT 2053.890000 783.780000 2054.890000 784.260000 ;
+ RECT 2053.890000 789.220000 2054.890000 789.700000 ;
+ RECT 2053.890000 794.660000 2054.890000 795.140000 ;
+ RECT 2053.890000 751.140000 2054.890000 751.620000 ;
+ RECT 2053.890000 756.580000 2054.890000 757.060000 ;
+ RECT 2053.890000 762.020000 2054.890000 762.500000 ;
+ RECT 2053.890000 767.460000 2054.890000 767.940000 ;
+ RECT 2051.060000 941.500000 2161.000000 942.500000 ;
+ RECT 2051.060000 749.130000 2161.000000 750.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 746.280000 2054.890000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 945.540000 2054.890000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 746.280000 2158.170000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 945.540000 2158.170000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 749.130000 2052.060000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 749.130000 2161.000000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 941.500000 2052.060000 942.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 941.500000 2161.000000 942.500000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 546.020000 2054.890000 746.280000 ;
+ RECT 2157.170000 546.020000 2158.170000 746.280000 ;
+ RECT 2058.020000 548.870000 2059.120000 742.240000 ;
+ RECT 2103.020000 548.870000 2104.120000 742.240000 ;
+ RECT 2148.020000 548.870000 2149.120000 742.240000 ;
+ LAYER met3 ;
+ RECT 2157.170000 724.960000 2158.170000 725.440000 ;
+ RECT 2157.170000 730.400000 2158.170000 730.880000 ;
+ RECT 2157.170000 735.840000 2158.170000 736.320000 ;
+ RECT 2157.170000 697.760000 2158.170000 698.240000 ;
+ RECT 2157.170000 703.200000 2158.170000 703.680000 ;
+ RECT 2157.170000 708.640000 2158.170000 709.120000 ;
+ RECT 2157.170000 714.080000 2158.170000 714.560000 ;
+ RECT 2157.170000 719.520000 2158.170000 720.000000 ;
+ RECT 2148.020000 724.960000 2149.120000 725.440000 ;
+ RECT 2148.020000 730.400000 2149.120000 730.880000 ;
+ RECT 2148.020000 735.840000 2149.120000 736.320000 ;
+ RECT 2148.020000 697.760000 2149.120000 698.240000 ;
+ RECT 2148.020000 703.200000 2149.120000 703.680000 ;
+ RECT 2148.020000 708.640000 2149.120000 709.120000 ;
+ RECT 2148.020000 714.080000 2149.120000 714.560000 ;
+ RECT 2148.020000 719.520000 2149.120000 720.000000 ;
+ RECT 2157.170000 676.000000 2158.170000 676.480000 ;
+ RECT 2157.170000 681.440000 2158.170000 681.920000 ;
+ RECT 2157.170000 686.880000 2158.170000 687.360000 ;
+ RECT 2157.170000 692.320000 2158.170000 692.800000 ;
+ RECT 2157.170000 648.800000 2158.170000 649.280000 ;
+ RECT 2157.170000 654.240000 2158.170000 654.720000 ;
+ RECT 2157.170000 659.680000 2158.170000 660.160000 ;
+ RECT 2157.170000 665.120000 2158.170000 665.600000 ;
+ RECT 2157.170000 670.560000 2158.170000 671.040000 ;
+ RECT 2148.020000 692.320000 2149.120000 692.800000 ;
+ RECT 2148.020000 686.880000 2149.120000 687.360000 ;
+ RECT 2148.020000 681.440000 2149.120000 681.920000 ;
+ RECT 2148.020000 676.000000 2149.120000 676.480000 ;
+ RECT 2148.020000 670.560000 2149.120000 671.040000 ;
+ RECT 2148.020000 665.120000 2149.120000 665.600000 ;
+ RECT 2148.020000 659.680000 2149.120000 660.160000 ;
+ RECT 2148.020000 648.800000 2149.120000 649.280000 ;
+ RECT 2148.020000 654.240000 2149.120000 654.720000 ;
+ RECT 2103.020000 735.840000 2104.120000 736.320000 ;
+ RECT 2103.020000 730.400000 2104.120000 730.880000 ;
+ RECT 2103.020000 724.960000 2104.120000 725.440000 ;
+ RECT 2058.020000 735.840000 2059.120000 736.320000 ;
+ RECT 2058.020000 730.400000 2059.120000 730.880000 ;
+ RECT 2058.020000 724.960000 2059.120000 725.440000 ;
+ RECT 2103.020000 714.080000 2104.120000 714.560000 ;
+ RECT 2103.020000 708.640000 2104.120000 709.120000 ;
+ RECT 2103.020000 703.200000 2104.120000 703.680000 ;
+ RECT 2103.020000 697.760000 2104.120000 698.240000 ;
+ RECT 2103.020000 719.520000 2104.120000 720.000000 ;
+ RECT 2058.020000 719.520000 2059.120000 720.000000 ;
+ RECT 2058.020000 714.080000 2059.120000 714.560000 ;
+ RECT 2058.020000 708.640000 2059.120000 709.120000 ;
+ RECT 2058.020000 703.200000 2059.120000 703.680000 ;
+ RECT 2058.020000 697.760000 2059.120000 698.240000 ;
+ RECT 2053.890000 724.960000 2054.890000 725.440000 ;
+ RECT 2053.890000 730.400000 2054.890000 730.880000 ;
+ RECT 2053.890000 735.840000 2054.890000 736.320000 ;
+ RECT 2053.890000 697.760000 2054.890000 698.240000 ;
+ RECT 2053.890000 703.200000 2054.890000 703.680000 ;
+ RECT 2053.890000 708.640000 2054.890000 709.120000 ;
+ RECT 2053.890000 714.080000 2054.890000 714.560000 ;
+ RECT 2053.890000 719.520000 2054.890000 720.000000 ;
+ RECT 2103.020000 692.320000 2104.120000 692.800000 ;
+ RECT 2103.020000 686.880000 2104.120000 687.360000 ;
+ RECT 2103.020000 681.440000 2104.120000 681.920000 ;
+ RECT 2103.020000 676.000000 2104.120000 676.480000 ;
+ RECT 2058.020000 692.320000 2059.120000 692.800000 ;
+ RECT 2058.020000 686.880000 2059.120000 687.360000 ;
+ RECT 2058.020000 681.440000 2059.120000 681.920000 ;
+ RECT 2058.020000 676.000000 2059.120000 676.480000 ;
+ RECT 2103.020000 670.560000 2104.120000 671.040000 ;
+ RECT 2103.020000 654.240000 2104.120000 654.720000 ;
+ RECT 2103.020000 648.800000 2104.120000 649.280000 ;
+ RECT 2103.020000 659.680000 2104.120000 660.160000 ;
+ RECT 2103.020000 665.120000 2104.120000 665.600000 ;
+ RECT 2058.020000 670.560000 2059.120000 671.040000 ;
+ RECT 2058.020000 654.240000 2059.120000 654.720000 ;
+ RECT 2058.020000 648.800000 2059.120000 649.280000 ;
+ RECT 2058.020000 659.680000 2059.120000 660.160000 ;
+ RECT 2058.020000 665.120000 2059.120000 665.600000 ;
+ RECT 2053.890000 676.000000 2054.890000 676.480000 ;
+ RECT 2053.890000 681.440000 2054.890000 681.920000 ;
+ RECT 2053.890000 686.880000 2054.890000 687.360000 ;
+ RECT 2053.890000 692.320000 2054.890000 692.800000 ;
+ RECT 2053.890000 648.800000 2054.890000 649.280000 ;
+ RECT 2053.890000 654.240000 2054.890000 654.720000 ;
+ RECT 2053.890000 659.680000 2054.890000 660.160000 ;
+ RECT 2053.890000 665.120000 2054.890000 665.600000 ;
+ RECT 2053.890000 670.560000 2054.890000 671.040000 ;
+ RECT 2157.170000 621.600000 2158.170000 622.080000 ;
+ RECT 2157.170000 627.040000 2158.170000 627.520000 ;
+ RECT 2157.170000 632.480000 2158.170000 632.960000 ;
+ RECT 2157.170000 637.920000 2158.170000 638.400000 ;
+ RECT 2157.170000 643.360000 2158.170000 643.840000 ;
+ RECT 2157.170000 599.840000 2158.170000 600.320000 ;
+ RECT 2157.170000 605.280000 2158.170000 605.760000 ;
+ RECT 2157.170000 610.720000 2158.170000 611.200000 ;
+ RECT 2157.170000 616.160000 2158.170000 616.640000 ;
+ RECT 2148.020000 621.600000 2149.120000 622.080000 ;
+ RECT 2148.020000 627.040000 2149.120000 627.520000 ;
+ RECT 2148.020000 632.480000 2149.120000 632.960000 ;
+ RECT 2148.020000 637.920000 2149.120000 638.400000 ;
+ RECT 2148.020000 643.360000 2149.120000 643.840000 ;
+ RECT 2148.020000 599.840000 2149.120000 600.320000 ;
+ RECT 2148.020000 605.280000 2149.120000 605.760000 ;
+ RECT 2148.020000 610.720000 2149.120000 611.200000 ;
+ RECT 2148.020000 616.160000 2149.120000 616.640000 ;
+ RECT 2157.170000 572.640000 2158.170000 573.120000 ;
+ RECT 2157.170000 578.080000 2158.170000 578.560000 ;
+ RECT 2157.170000 583.520000 2158.170000 584.000000 ;
+ RECT 2157.170000 588.960000 2158.170000 589.440000 ;
+ RECT 2157.170000 594.400000 2158.170000 594.880000 ;
+ RECT 2157.170000 550.880000 2158.170000 551.360000 ;
+ RECT 2157.170000 556.320000 2158.170000 556.800000 ;
+ RECT 2157.170000 561.760000 2158.170000 562.240000 ;
+ RECT 2157.170000 567.200000 2158.170000 567.680000 ;
+ RECT 2148.020000 594.400000 2149.120000 594.880000 ;
+ RECT 2148.020000 588.960000 2149.120000 589.440000 ;
+ RECT 2148.020000 583.520000 2149.120000 584.000000 ;
+ RECT 2148.020000 578.080000 2149.120000 578.560000 ;
+ RECT 2148.020000 572.640000 2149.120000 573.120000 ;
+ RECT 2148.020000 567.200000 2149.120000 567.680000 ;
+ RECT 2148.020000 561.760000 2149.120000 562.240000 ;
+ RECT 2148.020000 550.880000 2149.120000 551.360000 ;
+ RECT 2148.020000 556.320000 2149.120000 556.800000 ;
+ RECT 2103.020000 643.360000 2104.120000 643.840000 ;
+ RECT 2103.020000 637.920000 2104.120000 638.400000 ;
+ RECT 2103.020000 632.480000 2104.120000 632.960000 ;
+ RECT 2103.020000 621.600000 2104.120000 622.080000 ;
+ RECT 2103.020000 627.040000 2104.120000 627.520000 ;
+ RECT 2058.020000 643.360000 2059.120000 643.840000 ;
+ RECT 2058.020000 637.920000 2059.120000 638.400000 ;
+ RECT 2058.020000 632.480000 2059.120000 632.960000 ;
+ RECT 2058.020000 627.040000 2059.120000 627.520000 ;
+ RECT 2058.020000 621.600000 2059.120000 622.080000 ;
+ RECT 2103.020000 616.160000 2104.120000 616.640000 ;
+ RECT 2103.020000 610.720000 2104.120000 611.200000 ;
+ RECT 2103.020000 605.280000 2104.120000 605.760000 ;
+ RECT 2103.020000 599.840000 2104.120000 600.320000 ;
+ RECT 2058.020000 616.160000 2059.120000 616.640000 ;
+ RECT 2058.020000 610.720000 2059.120000 611.200000 ;
+ RECT 2058.020000 605.280000 2059.120000 605.760000 ;
+ RECT 2058.020000 599.840000 2059.120000 600.320000 ;
+ RECT 2053.890000 621.600000 2054.890000 622.080000 ;
+ RECT 2053.890000 627.040000 2054.890000 627.520000 ;
+ RECT 2053.890000 632.480000 2054.890000 632.960000 ;
+ RECT 2053.890000 637.920000 2054.890000 638.400000 ;
+ RECT 2053.890000 643.360000 2054.890000 643.840000 ;
+ RECT 2053.890000 599.840000 2054.890000 600.320000 ;
+ RECT 2053.890000 605.280000 2054.890000 605.760000 ;
+ RECT 2053.890000 610.720000 2054.890000 611.200000 ;
+ RECT 2053.890000 616.160000 2054.890000 616.640000 ;
+ RECT 2103.020000 594.400000 2104.120000 594.880000 ;
+ RECT 2103.020000 588.960000 2104.120000 589.440000 ;
+ RECT 2103.020000 583.520000 2104.120000 584.000000 ;
+ RECT 2103.020000 578.080000 2104.120000 578.560000 ;
+ RECT 2103.020000 572.640000 2104.120000 573.120000 ;
+ RECT 2058.020000 594.400000 2059.120000 594.880000 ;
+ RECT 2058.020000 588.960000 2059.120000 589.440000 ;
+ RECT 2058.020000 583.520000 2059.120000 584.000000 ;
+ RECT 2058.020000 578.080000 2059.120000 578.560000 ;
+ RECT 2058.020000 572.640000 2059.120000 573.120000 ;
+ RECT 2103.020000 556.320000 2104.120000 556.800000 ;
+ RECT 2103.020000 550.880000 2104.120000 551.360000 ;
+ RECT 2103.020000 561.760000 2104.120000 562.240000 ;
+ RECT 2103.020000 567.200000 2104.120000 567.680000 ;
+ RECT 2058.020000 556.320000 2059.120000 556.800000 ;
+ RECT 2058.020000 550.880000 2059.120000 551.360000 ;
+ RECT 2058.020000 561.760000 2059.120000 562.240000 ;
+ RECT 2058.020000 567.200000 2059.120000 567.680000 ;
+ RECT 2053.890000 572.640000 2054.890000 573.120000 ;
+ RECT 2053.890000 578.080000 2054.890000 578.560000 ;
+ RECT 2053.890000 583.520000 2054.890000 584.000000 ;
+ RECT 2053.890000 588.960000 2054.890000 589.440000 ;
+ RECT 2053.890000 594.400000 2054.890000 594.880000 ;
+ RECT 2053.890000 550.880000 2054.890000 551.360000 ;
+ RECT 2053.890000 556.320000 2054.890000 556.800000 ;
+ RECT 2053.890000 561.760000 2054.890000 562.240000 ;
+ RECT 2053.890000 567.200000 2054.890000 567.680000 ;
+ RECT 2051.060000 741.240000 2161.000000 742.240000 ;
+ RECT 2051.060000 548.870000 2161.000000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 546.020000 2054.890000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 745.280000 2054.890000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 546.020000 2158.170000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 745.280000 2158.170000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 548.870000 2052.060000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 548.870000 2161.000000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 741.240000 2052.060000 742.240000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 741.240000 2161.000000 742.240000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 345.760000 2054.890000 546.020000 ;
+ RECT 2157.170000 345.760000 2158.170000 546.020000 ;
+ RECT 2058.020000 348.610000 2059.120000 541.980000 ;
+ RECT 2103.020000 348.610000 2104.120000 541.980000 ;
+ RECT 2148.020000 348.610000 2149.120000 541.980000 ;
+ LAYER met3 ;
+ RECT 2157.170000 524.700000 2158.170000 525.180000 ;
+ RECT 2157.170000 530.140000 2158.170000 530.620000 ;
+ RECT 2157.170000 535.580000 2158.170000 536.060000 ;
+ RECT 2157.170000 497.500000 2158.170000 497.980000 ;
+ RECT 2157.170000 502.940000 2158.170000 503.420000 ;
+ RECT 2157.170000 508.380000 2158.170000 508.860000 ;
+ RECT 2157.170000 513.820000 2158.170000 514.300000 ;
+ RECT 2157.170000 519.260000 2158.170000 519.740000 ;
+ RECT 2148.020000 524.700000 2149.120000 525.180000 ;
+ RECT 2148.020000 530.140000 2149.120000 530.620000 ;
+ RECT 2148.020000 535.580000 2149.120000 536.060000 ;
+ RECT 2148.020000 497.500000 2149.120000 497.980000 ;
+ RECT 2148.020000 502.940000 2149.120000 503.420000 ;
+ RECT 2148.020000 508.380000 2149.120000 508.860000 ;
+ RECT 2148.020000 513.820000 2149.120000 514.300000 ;
+ RECT 2148.020000 519.260000 2149.120000 519.740000 ;
+ RECT 2157.170000 475.740000 2158.170000 476.220000 ;
+ RECT 2157.170000 481.180000 2158.170000 481.660000 ;
+ RECT 2157.170000 486.620000 2158.170000 487.100000 ;
+ RECT 2157.170000 492.060000 2158.170000 492.540000 ;
+ RECT 2157.170000 448.540000 2158.170000 449.020000 ;
+ RECT 2157.170000 453.980000 2158.170000 454.460000 ;
+ RECT 2157.170000 459.420000 2158.170000 459.900000 ;
+ RECT 2157.170000 464.860000 2158.170000 465.340000 ;
+ RECT 2157.170000 470.300000 2158.170000 470.780000 ;
+ RECT 2148.020000 492.060000 2149.120000 492.540000 ;
+ RECT 2148.020000 486.620000 2149.120000 487.100000 ;
+ RECT 2148.020000 481.180000 2149.120000 481.660000 ;
+ RECT 2148.020000 475.740000 2149.120000 476.220000 ;
+ RECT 2148.020000 470.300000 2149.120000 470.780000 ;
+ RECT 2148.020000 464.860000 2149.120000 465.340000 ;
+ RECT 2148.020000 459.420000 2149.120000 459.900000 ;
+ RECT 2148.020000 448.540000 2149.120000 449.020000 ;
+ RECT 2148.020000 453.980000 2149.120000 454.460000 ;
+ RECT 2103.020000 535.580000 2104.120000 536.060000 ;
+ RECT 2103.020000 530.140000 2104.120000 530.620000 ;
+ RECT 2103.020000 524.700000 2104.120000 525.180000 ;
+ RECT 2058.020000 535.580000 2059.120000 536.060000 ;
+ RECT 2058.020000 530.140000 2059.120000 530.620000 ;
+ RECT 2058.020000 524.700000 2059.120000 525.180000 ;
+ RECT 2103.020000 513.820000 2104.120000 514.300000 ;
+ RECT 2103.020000 508.380000 2104.120000 508.860000 ;
+ RECT 2103.020000 502.940000 2104.120000 503.420000 ;
+ RECT 2103.020000 497.500000 2104.120000 497.980000 ;
+ RECT 2103.020000 519.260000 2104.120000 519.740000 ;
+ RECT 2058.020000 519.260000 2059.120000 519.740000 ;
+ RECT 2058.020000 513.820000 2059.120000 514.300000 ;
+ RECT 2058.020000 508.380000 2059.120000 508.860000 ;
+ RECT 2058.020000 502.940000 2059.120000 503.420000 ;
+ RECT 2058.020000 497.500000 2059.120000 497.980000 ;
+ RECT 2053.890000 524.700000 2054.890000 525.180000 ;
+ RECT 2053.890000 530.140000 2054.890000 530.620000 ;
+ RECT 2053.890000 535.580000 2054.890000 536.060000 ;
+ RECT 2053.890000 497.500000 2054.890000 497.980000 ;
+ RECT 2053.890000 502.940000 2054.890000 503.420000 ;
+ RECT 2053.890000 508.380000 2054.890000 508.860000 ;
+ RECT 2053.890000 513.820000 2054.890000 514.300000 ;
+ RECT 2053.890000 519.260000 2054.890000 519.740000 ;
+ RECT 2103.020000 492.060000 2104.120000 492.540000 ;
+ RECT 2103.020000 486.620000 2104.120000 487.100000 ;
+ RECT 2103.020000 481.180000 2104.120000 481.660000 ;
+ RECT 2103.020000 475.740000 2104.120000 476.220000 ;
+ RECT 2058.020000 492.060000 2059.120000 492.540000 ;
+ RECT 2058.020000 486.620000 2059.120000 487.100000 ;
+ RECT 2058.020000 481.180000 2059.120000 481.660000 ;
+ RECT 2058.020000 475.740000 2059.120000 476.220000 ;
+ RECT 2103.020000 470.300000 2104.120000 470.780000 ;
+ RECT 2103.020000 453.980000 2104.120000 454.460000 ;
+ RECT 2103.020000 448.540000 2104.120000 449.020000 ;
+ RECT 2103.020000 459.420000 2104.120000 459.900000 ;
+ RECT 2103.020000 464.860000 2104.120000 465.340000 ;
+ RECT 2058.020000 470.300000 2059.120000 470.780000 ;
+ RECT 2058.020000 453.980000 2059.120000 454.460000 ;
+ RECT 2058.020000 448.540000 2059.120000 449.020000 ;
+ RECT 2058.020000 459.420000 2059.120000 459.900000 ;
+ RECT 2058.020000 464.860000 2059.120000 465.340000 ;
+ RECT 2053.890000 475.740000 2054.890000 476.220000 ;
+ RECT 2053.890000 481.180000 2054.890000 481.660000 ;
+ RECT 2053.890000 486.620000 2054.890000 487.100000 ;
+ RECT 2053.890000 492.060000 2054.890000 492.540000 ;
+ RECT 2053.890000 448.540000 2054.890000 449.020000 ;
+ RECT 2053.890000 453.980000 2054.890000 454.460000 ;
+ RECT 2053.890000 459.420000 2054.890000 459.900000 ;
+ RECT 2053.890000 464.860000 2054.890000 465.340000 ;
+ RECT 2053.890000 470.300000 2054.890000 470.780000 ;
+ RECT 2157.170000 421.340000 2158.170000 421.820000 ;
+ RECT 2157.170000 426.780000 2158.170000 427.260000 ;
+ RECT 2157.170000 432.220000 2158.170000 432.700000 ;
+ RECT 2157.170000 437.660000 2158.170000 438.140000 ;
+ RECT 2157.170000 443.100000 2158.170000 443.580000 ;
+ RECT 2157.170000 399.580000 2158.170000 400.060000 ;
+ RECT 2157.170000 405.020000 2158.170000 405.500000 ;
+ RECT 2157.170000 410.460000 2158.170000 410.940000 ;
+ RECT 2157.170000 415.900000 2158.170000 416.380000 ;
+ RECT 2148.020000 421.340000 2149.120000 421.820000 ;
+ RECT 2148.020000 426.780000 2149.120000 427.260000 ;
+ RECT 2148.020000 432.220000 2149.120000 432.700000 ;
+ RECT 2148.020000 437.660000 2149.120000 438.140000 ;
+ RECT 2148.020000 443.100000 2149.120000 443.580000 ;
+ RECT 2148.020000 399.580000 2149.120000 400.060000 ;
+ RECT 2148.020000 405.020000 2149.120000 405.500000 ;
+ RECT 2148.020000 410.460000 2149.120000 410.940000 ;
+ RECT 2148.020000 415.900000 2149.120000 416.380000 ;
+ RECT 2157.170000 372.380000 2158.170000 372.860000 ;
+ RECT 2157.170000 377.820000 2158.170000 378.300000 ;
+ RECT 2157.170000 383.260000 2158.170000 383.740000 ;
+ RECT 2157.170000 388.700000 2158.170000 389.180000 ;
+ RECT 2157.170000 394.140000 2158.170000 394.620000 ;
+ RECT 2157.170000 350.620000 2158.170000 351.100000 ;
+ RECT 2157.170000 356.060000 2158.170000 356.540000 ;
+ RECT 2157.170000 361.500000 2158.170000 361.980000 ;
+ RECT 2157.170000 366.940000 2158.170000 367.420000 ;
+ RECT 2148.020000 394.140000 2149.120000 394.620000 ;
+ RECT 2148.020000 388.700000 2149.120000 389.180000 ;
+ RECT 2148.020000 383.260000 2149.120000 383.740000 ;
+ RECT 2148.020000 377.820000 2149.120000 378.300000 ;
+ RECT 2148.020000 372.380000 2149.120000 372.860000 ;
+ RECT 2148.020000 366.940000 2149.120000 367.420000 ;
+ RECT 2148.020000 361.500000 2149.120000 361.980000 ;
+ RECT 2148.020000 350.620000 2149.120000 351.100000 ;
+ RECT 2148.020000 356.060000 2149.120000 356.540000 ;
+ RECT 2103.020000 443.100000 2104.120000 443.580000 ;
+ RECT 2103.020000 437.660000 2104.120000 438.140000 ;
+ RECT 2103.020000 432.220000 2104.120000 432.700000 ;
+ RECT 2103.020000 421.340000 2104.120000 421.820000 ;
+ RECT 2103.020000 426.780000 2104.120000 427.260000 ;
+ RECT 2058.020000 443.100000 2059.120000 443.580000 ;
+ RECT 2058.020000 437.660000 2059.120000 438.140000 ;
+ RECT 2058.020000 432.220000 2059.120000 432.700000 ;
+ RECT 2058.020000 426.780000 2059.120000 427.260000 ;
+ RECT 2058.020000 421.340000 2059.120000 421.820000 ;
+ RECT 2103.020000 415.900000 2104.120000 416.380000 ;
+ RECT 2103.020000 410.460000 2104.120000 410.940000 ;
+ RECT 2103.020000 405.020000 2104.120000 405.500000 ;
+ RECT 2103.020000 399.580000 2104.120000 400.060000 ;
+ RECT 2058.020000 415.900000 2059.120000 416.380000 ;
+ RECT 2058.020000 410.460000 2059.120000 410.940000 ;
+ RECT 2058.020000 405.020000 2059.120000 405.500000 ;
+ RECT 2058.020000 399.580000 2059.120000 400.060000 ;
+ RECT 2053.890000 421.340000 2054.890000 421.820000 ;
+ RECT 2053.890000 426.780000 2054.890000 427.260000 ;
+ RECT 2053.890000 432.220000 2054.890000 432.700000 ;
+ RECT 2053.890000 437.660000 2054.890000 438.140000 ;
+ RECT 2053.890000 443.100000 2054.890000 443.580000 ;
+ RECT 2053.890000 399.580000 2054.890000 400.060000 ;
+ RECT 2053.890000 405.020000 2054.890000 405.500000 ;
+ RECT 2053.890000 410.460000 2054.890000 410.940000 ;
+ RECT 2053.890000 415.900000 2054.890000 416.380000 ;
+ RECT 2103.020000 394.140000 2104.120000 394.620000 ;
+ RECT 2103.020000 388.700000 2104.120000 389.180000 ;
+ RECT 2103.020000 383.260000 2104.120000 383.740000 ;
+ RECT 2103.020000 377.820000 2104.120000 378.300000 ;
+ RECT 2103.020000 372.380000 2104.120000 372.860000 ;
+ RECT 2058.020000 394.140000 2059.120000 394.620000 ;
+ RECT 2058.020000 388.700000 2059.120000 389.180000 ;
+ RECT 2058.020000 383.260000 2059.120000 383.740000 ;
+ RECT 2058.020000 377.820000 2059.120000 378.300000 ;
+ RECT 2058.020000 372.380000 2059.120000 372.860000 ;
+ RECT 2103.020000 356.060000 2104.120000 356.540000 ;
+ RECT 2103.020000 350.620000 2104.120000 351.100000 ;
+ RECT 2103.020000 361.500000 2104.120000 361.980000 ;
+ RECT 2103.020000 366.940000 2104.120000 367.420000 ;
+ RECT 2058.020000 356.060000 2059.120000 356.540000 ;
+ RECT 2058.020000 350.620000 2059.120000 351.100000 ;
+ RECT 2058.020000 361.500000 2059.120000 361.980000 ;
+ RECT 2058.020000 366.940000 2059.120000 367.420000 ;
+ RECT 2053.890000 372.380000 2054.890000 372.860000 ;
+ RECT 2053.890000 377.820000 2054.890000 378.300000 ;
+ RECT 2053.890000 383.260000 2054.890000 383.740000 ;
+ RECT 2053.890000 388.700000 2054.890000 389.180000 ;
+ RECT 2053.890000 394.140000 2054.890000 394.620000 ;
+ RECT 2053.890000 350.620000 2054.890000 351.100000 ;
+ RECT 2053.890000 356.060000 2054.890000 356.540000 ;
+ RECT 2053.890000 361.500000 2054.890000 361.980000 ;
+ RECT 2053.890000 366.940000 2054.890000 367.420000 ;
+ RECT 2051.060000 540.980000 2161.000000 541.980000 ;
+ RECT 2051.060000 348.610000 2161.000000 349.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 345.760000 2054.890000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 545.020000 2054.890000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 345.760000 2158.170000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 545.020000 2158.170000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 348.610000 2052.060000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 348.610000 2161.000000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 540.980000 2052.060000 541.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 540.980000 2161.000000 541.980000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 145.500000 2054.890000 345.760000 ;
+ RECT 2157.170000 145.500000 2158.170000 345.760000 ;
+ RECT 2058.020000 148.350000 2059.120000 341.720000 ;
+ RECT 2103.020000 148.350000 2104.120000 341.720000 ;
+ RECT 2148.020000 148.350000 2149.120000 341.720000 ;
+ LAYER met3 ;
+ RECT 2157.170000 324.440000 2158.170000 324.920000 ;
+ RECT 2157.170000 329.880000 2158.170000 330.360000 ;
+ RECT 2157.170000 335.320000 2158.170000 335.800000 ;
+ RECT 2157.170000 297.240000 2158.170000 297.720000 ;
+ RECT 2157.170000 302.680000 2158.170000 303.160000 ;
+ RECT 2157.170000 308.120000 2158.170000 308.600000 ;
+ RECT 2157.170000 313.560000 2158.170000 314.040000 ;
+ RECT 2157.170000 319.000000 2158.170000 319.480000 ;
+ RECT 2148.020000 324.440000 2149.120000 324.920000 ;
+ RECT 2148.020000 329.880000 2149.120000 330.360000 ;
+ RECT 2148.020000 335.320000 2149.120000 335.800000 ;
+ RECT 2148.020000 297.240000 2149.120000 297.720000 ;
+ RECT 2148.020000 302.680000 2149.120000 303.160000 ;
+ RECT 2148.020000 308.120000 2149.120000 308.600000 ;
+ RECT 2148.020000 313.560000 2149.120000 314.040000 ;
+ RECT 2148.020000 319.000000 2149.120000 319.480000 ;
+ RECT 2157.170000 275.480000 2158.170000 275.960000 ;
+ RECT 2157.170000 280.920000 2158.170000 281.400000 ;
+ RECT 2157.170000 286.360000 2158.170000 286.840000 ;
+ RECT 2157.170000 291.800000 2158.170000 292.280000 ;
+ RECT 2157.170000 248.280000 2158.170000 248.760000 ;
+ RECT 2157.170000 253.720000 2158.170000 254.200000 ;
+ RECT 2157.170000 259.160000 2158.170000 259.640000 ;
+ RECT 2157.170000 264.600000 2158.170000 265.080000 ;
+ RECT 2157.170000 270.040000 2158.170000 270.520000 ;
+ RECT 2148.020000 291.800000 2149.120000 292.280000 ;
+ RECT 2148.020000 286.360000 2149.120000 286.840000 ;
+ RECT 2148.020000 280.920000 2149.120000 281.400000 ;
+ RECT 2148.020000 275.480000 2149.120000 275.960000 ;
+ RECT 2148.020000 270.040000 2149.120000 270.520000 ;
+ RECT 2148.020000 264.600000 2149.120000 265.080000 ;
+ RECT 2148.020000 259.160000 2149.120000 259.640000 ;
+ RECT 2148.020000 248.280000 2149.120000 248.760000 ;
+ RECT 2148.020000 253.720000 2149.120000 254.200000 ;
+ RECT 2103.020000 335.320000 2104.120000 335.800000 ;
+ RECT 2103.020000 329.880000 2104.120000 330.360000 ;
+ RECT 2103.020000 324.440000 2104.120000 324.920000 ;
+ RECT 2058.020000 335.320000 2059.120000 335.800000 ;
+ RECT 2058.020000 329.880000 2059.120000 330.360000 ;
+ RECT 2058.020000 324.440000 2059.120000 324.920000 ;
+ RECT 2103.020000 313.560000 2104.120000 314.040000 ;
+ RECT 2103.020000 308.120000 2104.120000 308.600000 ;
+ RECT 2103.020000 302.680000 2104.120000 303.160000 ;
+ RECT 2103.020000 297.240000 2104.120000 297.720000 ;
+ RECT 2103.020000 319.000000 2104.120000 319.480000 ;
+ RECT 2058.020000 319.000000 2059.120000 319.480000 ;
+ RECT 2058.020000 313.560000 2059.120000 314.040000 ;
+ RECT 2058.020000 308.120000 2059.120000 308.600000 ;
+ RECT 2058.020000 302.680000 2059.120000 303.160000 ;
+ RECT 2058.020000 297.240000 2059.120000 297.720000 ;
+ RECT 2053.890000 324.440000 2054.890000 324.920000 ;
+ RECT 2053.890000 329.880000 2054.890000 330.360000 ;
+ RECT 2053.890000 335.320000 2054.890000 335.800000 ;
+ RECT 2053.890000 297.240000 2054.890000 297.720000 ;
+ RECT 2053.890000 302.680000 2054.890000 303.160000 ;
+ RECT 2053.890000 308.120000 2054.890000 308.600000 ;
+ RECT 2053.890000 313.560000 2054.890000 314.040000 ;
+ RECT 2053.890000 319.000000 2054.890000 319.480000 ;
+ RECT 2103.020000 291.800000 2104.120000 292.280000 ;
+ RECT 2103.020000 286.360000 2104.120000 286.840000 ;
+ RECT 2103.020000 280.920000 2104.120000 281.400000 ;
+ RECT 2103.020000 275.480000 2104.120000 275.960000 ;
+ RECT 2058.020000 291.800000 2059.120000 292.280000 ;
+ RECT 2058.020000 286.360000 2059.120000 286.840000 ;
+ RECT 2058.020000 280.920000 2059.120000 281.400000 ;
+ RECT 2058.020000 275.480000 2059.120000 275.960000 ;
+ RECT 2103.020000 270.040000 2104.120000 270.520000 ;
+ RECT 2103.020000 253.720000 2104.120000 254.200000 ;
+ RECT 2103.020000 248.280000 2104.120000 248.760000 ;
+ RECT 2103.020000 259.160000 2104.120000 259.640000 ;
+ RECT 2103.020000 264.600000 2104.120000 265.080000 ;
+ RECT 2058.020000 270.040000 2059.120000 270.520000 ;
+ RECT 2058.020000 253.720000 2059.120000 254.200000 ;
+ RECT 2058.020000 248.280000 2059.120000 248.760000 ;
+ RECT 2058.020000 259.160000 2059.120000 259.640000 ;
+ RECT 2058.020000 264.600000 2059.120000 265.080000 ;
+ RECT 2053.890000 275.480000 2054.890000 275.960000 ;
+ RECT 2053.890000 280.920000 2054.890000 281.400000 ;
+ RECT 2053.890000 286.360000 2054.890000 286.840000 ;
+ RECT 2053.890000 291.800000 2054.890000 292.280000 ;
+ RECT 2053.890000 248.280000 2054.890000 248.760000 ;
+ RECT 2053.890000 253.720000 2054.890000 254.200000 ;
+ RECT 2053.890000 259.160000 2054.890000 259.640000 ;
+ RECT 2053.890000 264.600000 2054.890000 265.080000 ;
+ RECT 2053.890000 270.040000 2054.890000 270.520000 ;
+ RECT 2157.170000 221.080000 2158.170000 221.560000 ;
+ RECT 2157.170000 226.520000 2158.170000 227.000000 ;
+ RECT 2157.170000 231.960000 2158.170000 232.440000 ;
+ RECT 2157.170000 237.400000 2158.170000 237.880000 ;
+ RECT 2157.170000 242.840000 2158.170000 243.320000 ;
+ RECT 2157.170000 199.320000 2158.170000 199.800000 ;
+ RECT 2157.170000 204.760000 2158.170000 205.240000 ;
+ RECT 2157.170000 210.200000 2158.170000 210.680000 ;
+ RECT 2157.170000 215.640000 2158.170000 216.120000 ;
+ RECT 2148.020000 221.080000 2149.120000 221.560000 ;
+ RECT 2148.020000 226.520000 2149.120000 227.000000 ;
+ RECT 2148.020000 231.960000 2149.120000 232.440000 ;
+ RECT 2148.020000 237.400000 2149.120000 237.880000 ;
+ RECT 2148.020000 242.840000 2149.120000 243.320000 ;
+ RECT 2148.020000 199.320000 2149.120000 199.800000 ;
+ RECT 2148.020000 204.760000 2149.120000 205.240000 ;
+ RECT 2148.020000 210.200000 2149.120000 210.680000 ;
+ RECT 2148.020000 215.640000 2149.120000 216.120000 ;
+ RECT 2157.170000 172.120000 2158.170000 172.600000 ;
+ RECT 2157.170000 177.560000 2158.170000 178.040000 ;
+ RECT 2157.170000 183.000000 2158.170000 183.480000 ;
+ RECT 2157.170000 188.440000 2158.170000 188.920000 ;
+ RECT 2157.170000 193.880000 2158.170000 194.360000 ;
+ RECT 2157.170000 150.360000 2158.170000 150.840000 ;
+ RECT 2157.170000 155.800000 2158.170000 156.280000 ;
+ RECT 2157.170000 161.240000 2158.170000 161.720000 ;
+ RECT 2157.170000 166.680000 2158.170000 167.160000 ;
+ RECT 2148.020000 193.880000 2149.120000 194.360000 ;
+ RECT 2148.020000 188.440000 2149.120000 188.920000 ;
+ RECT 2148.020000 183.000000 2149.120000 183.480000 ;
+ RECT 2148.020000 177.560000 2149.120000 178.040000 ;
+ RECT 2148.020000 172.120000 2149.120000 172.600000 ;
+ RECT 2148.020000 166.680000 2149.120000 167.160000 ;
+ RECT 2148.020000 161.240000 2149.120000 161.720000 ;
+ RECT 2148.020000 150.360000 2149.120000 150.840000 ;
+ RECT 2148.020000 155.800000 2149.120000 156.280000 ;
+ RECT 2103.020000 242.840000 2104.120000 243.320000 ;
+ RECT 2103.020000 237.400000 2104.120000 237.880000 ;
+ RECT 2103.020000 231.960000 2104.120000 232.440000 ;
+ RECT 2103.020000 221.080000 2104.120000 221.560000 ;
+ RECT 2103.020000 226.520000 2104.120000 227.000000 ;
+ RECT 2058.020000 242.840000 2059.120000 243.320000 ;
+ RECT 2058.020000 237.400000 2059.120000 237.880000 ;
+ RECT 2058.020000 231.960000 2059.120000 232.440000 ;
+ RECT 2058.020000 226.520000 2059.120000 227.000000 ;
+ RECT 2058.020000 221.080000 2059.120000 221.560000 ;
+ RECT 2103.020000 215.640000 2104.120000 216.120000 ;
+ RECT 2103.020000 210.200000 2104.120000 210.680000 ;
+ RECT 2103.020000 204.760000 2104.120000 205.240000 ;
+ RECT 2103.020000 199.320000 2104.120000 199.800000 ;
+ RECT 2058.020000 215.640000 2059.120000 216.120000 ;
+ RECT 2058.020000 210.200000 2059.120000 210.680000 ;
+ RECT 2058.020000 204.760000 2059.120000 205.240000 ;
+ RECT 2058.020000 199.320000 2059.120000 199.800000 ;
+ RECT 2053.890000 221.080000 2054.890000 221.560000 ;
+ RECT 2053.890000 226.520000 2054.890000 227.000000 ;
+ RECT 2053.890000 231.960000 2054.890000 232.440000 ;
+ RECT 2053.890000 237.400000 2054.890000 237.880000 ;
+ RECT 2053.890000 242.840000 2054.890000 243.320000 ;
+ RECT 2053.890000 199.320000 2054.890000 199.800000 ;
+ RECT 2053.890000 204.760000 2054.890000 205.240000 ;
+ RECT 2053.890000 210.200000 2054.890000 210.680000 ;
+ RECT 2053.890000 215.640000 2054.890000 216.120000 ;
+ RECT 2103.020000 193.880000 2104.120000 194.360000 ;
+ RECT 2103.020000 188.440000 2104.120000 188.920000 ;
+ RECT 2103.020000 183.000000 2104.120000 183.480000 ;
+ RECT 2103.020000 177.560000 2104.120000 178.040000 ;
+ RECT 2103.020000 172.120000 2104.120000 172.600000 ;
+ RECT 2058.020000 193.880000 2059.120000 194.360000 ;
+ RECT 2058.020000 188.440000 2059.120000 188.920000 ;
+ RECT 2058.020000 183.000000 2059.120000 183.480000 ;
+ RECT 2058.020000 177.560000 2059.120000 178.040000 ;
+ RECT 2058.020000 172.120000 2059.120000 172.600000 ;
+ RECT 2103.020000 155.800000 2104.120000 156.280000 ;
+ RECT 2103.020000 150.360000 2104.120000 150.840000 ;
+ RECT 2103.020000 161.240000 2104.120000 161.720000 ;
+ RECT 2103.020000 166.680000 2104.120000 167.160000 ;
+ RECT 2058.020000 155.800000 2059.120000 156.280000 ;
+ RECT 2058.020000 150.360000 2059.120000 150.840000 ;
+ RECT 2058.020000 161.240000 2059.120000 161.720000 ;
+ RECT 2058.020000 166.680000 2059.120000 167.160000 ;
+ RECT 2053.890000 172.120000 2054.890000 172.600000 ;
+ RECT 2053.890000 177.560000 2054.890000 178.040000 ;
+ RECT 2053.890000 183.000000 2054.890000 183.480000 ;
+ RECT 2053.890000 188.440000 2054.890000 188.920000 ;
+ RECT 2053.890000 193.880000 2054.890000 194.360000 ;
+ RECT 2053.890000 150.360000 2054.890000 150.840000 ;
+ RECT 2053.890000 155.800000 2054.890000 156.280000 ;
+ RECT 2053.890000 161.240000 2054.890000 161.720000 ;
+ RECT 2053.890000 166.680000 2054.890000 167.160000 ;
+ RECT 2051.060000 340.720000 2161.000000 341.720000 ;
+ RECT 2051.060000 148.350000 2161.000000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 145.500000 2054.890000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 344.760000 2054.890000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 145.500000 2158.170000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 344.760000 2158.170000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 148.350000 2052.060000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 148.350000 2161.000000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 340.720000 2052.060000 341.720000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 340.720000 2161.000000 341.720000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'S_term_RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 115.240000 2054.890000 145.500000 ;
+ RECT 2157.170000 115.240000 2158.170000 145.500000 ;
+ RECT 2058.020000 118.090000 2059.120000 142.140000 ;
+ RECT 2103.020000 118.090000 2104.120000 142.140000 ;
+ RECT 2148.020000 118.090000 2149.120000 142.140000 ;
+ LAYER met3 ;
+ RECT 2157.170000 130.980000 2158.170000 131.460000 ;
+ RECT 2157.170000 136.420000 2158.170000 136.900000 ;
+ RECT 2148.020000 130.980000 2149.120000 131.460000 ;
+ RECT 2148.020000 136.420000 2149.120000 136.900000 ;
+ RECT 2103.020000 136.420000 2104.120000 136.900000 ;
+ RECT 2103.020000 130.980000 2104.120000 131.460000 ;
+ RECT 2053.890000 130.980000 2054.890000 131.460000 ;
+ RECT 2053.890000 136.420000 2054.890000 136.900000 ;
+ RECT 2058.020000 130.980000 2059.120000 131.460000 ;
+ RECT 2058.020000 136.420000 2059.120000 136.900000 ;
+ RECT 2157.170000 120.100000 2158.170000 120.580000 ;
+ RECT 2157.170000 125.540000 2158.170000 126.020000 ;
+ RECT 2148.020000 120.100000 2149.120000 120.580000 ;
+ RECT 2148.020000 125.540000 2149.120000 126.020000 ;
+ RECT 2103.020000 125.540000 2104.120000 126.020000 ;
+ RECT 2103.020000 120.100000 2104.120000 120.580000 ;
+ RECT 2053.890000 125.540000 2054.890000 126.020000 ;
+ RECT 2058.020000 125.540000 2059.120000 126.020000 ;
+ RECT 2053.890000 120.100000 2054.890000 120.580000 ;
+ RECT 2058.020000 120.100000 2059.120000 120.580000 ;
+ RECT 2051.060000 141.140000 2161.000000 142.140000 ;
+ RECT 2051.060000 118.090000 2161.000000 119.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 115.240000 2054.890000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 144.500000 2054.890000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 115.240000 2158.170000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 144.500000 2158.170000 145.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 118.090000 2052.060000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 118.090000 2161.000000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 141.140000 2052.060000 142.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 141.140000 2161.000000 142.140000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 3149.400000 2054.890000 3349.660000 ;
+ RECT 2157.170000 3149.400000 2158.170000 3349.660000 ;
+ RECT 2058.020000 3152.250000 2059.120000 3345.620000 ;
+ RECT 2103.020000 3152.250000 2104.120000 3345.620000 ;
+ RECT 2148.020000 3152.250000 2149.120000 3345.620000 ;
+ LAYER met3 ;
+ RECT 2157.170000 3328.340000 2158.170000 3328.820000 ;
+ RECT 2157.170000 3333.780000 2158.170000 3334.260000 ;
+ RECT 2157.170000 3339.220000 2158.170000 3339.700000 ;
+ RECT 2157.170000 3301.140000 2158.170000 3301.620000 ;
+ RECT 2157.170000 3306.580000 2158.170000 3307.060000 ;
+ RECT 2157.170000 3312.020000 2158.170000 3312.500000 ;
+ RECT 2157.170000 3317.460000 2158.170000 3317.940000 ;
+ RECT 2157.170000 3322.900000 2158.170000 3323.380000 ;
+ RECT 2148.020000 3328.340000 2149.120000 3328.820000 ;
+ RECT 2148.020000 3333.780000 2149.120000 3334.260000 ;
+ RECT 2148.020000 3339.220000 2149.120000 3339.700000 ;
+ RECT 2148.020000 3301.140000 2149.120000 3301.620000 ;
+ RECT 2148.020000 3306.580000 2149.120000 3307.060000 ;
+ RECT 2148.020000 3312.020000 2149.120000 3312.500000 ;
+ RECT 2148.020000 3317.460000 2149.120000 3317.940000 ;
+ RECT 2148.020000 3322.900000 2149.120000 3323.380000 ;
+ RECT 2157.170000 3279.380000 2158.170000 3279.860000 ;
+ RECT 2157.170000 3284.820000 2158.170000 3285.300000 ;
+ RECT 2157.170000 3290.260000 2158.170000 3290.740000 ;
+ RECT 2157.170000 3295.700000 2158.170000 3296.180000 ;
+ RECT 2157.170000 3252.180000 2158.170000 3252.660000 ;
+ RECT 2157.170000 3257.620000 2158.170000 3258.100000 ;
+ RECT 2157.170000 3263.060000 2158.170000 3263.540000 ;
+ RECT 2157.170000 3268.500000 2158.170000 3268.980000 ;
+ RECT 2157.170000 3273.940000 2158.170000 3274.420000 ;
+ RECT 2148.020000 3295.700000 2149.120000 3296.180000 ;
+ RECT 2148.020000 3290.260000 2149.120000 3290.740000 ;
+ RECT 2148.020000 3284.820000 2149.120000 3285.300000 ;
+ RECT 2148.020000 3279.380000 2149.120000 3279.860000 ;
+ RECT 2148.020000 3273.940000 2149.120000 3274.420000 ;
+ RECT 2148.020000 3268.500000 2149.120000 3268.980000 ;
+ RECT 2148.020000 3263.060000 2149.120000 3263.540000 ;
+ RECT 2148.020000 3252.180000 2149.120000 3252.660000 ;
+ RECT 2148.020000 3257.620000 2149.120000 3258.100000 ;
+ RECT 2103.020000 3339.220000 2104.120000 3339.700000 ;
+ RECT 2103.020000 3333.780000 2104.120000 3334.260000 ;
+ RECT 2103.020000 3328.340000 2104.120000 3328.820000 ;
+ RECT 2058.020000 3339.220000 2059.120000 3339.700000 ;
+ RECT 2058.020000 3333.780000 2059.120000 3334.260000 ;
+ RECT 2058.020000 3328.340000 2059.120000 3328.820000 ;
+ RECT 2103.020000 3317.460000 2104.120000 3317.940000 ;
+ RECT 2103.020000 3312.020000 2104.120000 3312.500000 ;
+ RECT 2103.020000 3306.580000 2104.120000 3307.060000 ;
+ RECT 2103.020000 3301.140000 2104.120000 3301.620000 ;
+ RECT 2103.020000 3322.900000 2104.120000 3323.380000 ;
+ RECT 2058.020000 3322.900000 2059.120000 3323.380000 ;
+ RECT 2058.020000 3317.460000 2059.120000 3317.940000 ;
+ RECT 2058.020000 3312.020000 2059.120000 3312.500000 ;
+ RECT 2058.020000 3306.580000 2059.120000 3307.060000 ;
+ RECT 2058.020000 3301.140000 2059.120000 3301.620000 ;
+ RECT 2053.890000 3328.340000 2054.890000 3328.820000 ;
+ RECT 2053.890000 3333.780000 2054.890000 3334.260000 ;
+ RECT 2053.890000 3339.220000 2054.890000 3339.700000 ;
+ RECT 2053.890000 3301.140000 2054.890000 3301.620000 ;
+ RECT 2053.890000 3306.580000 2054.890000 3307.060000 ;
+ RECT 2053.890000 3312.020000 2054.890000 3312.500000 ;
+ RECT 2053.890000 3317.460000 2054.890000 3317.940000 ;
+ RECT 2053.890000 3322.900000 2054.890000 3323.380000 ;
+ RECT 2103.020000 3295.700000 2104.120000 3296.180000 ;
+ RECT 2103.020000 3290.260000 2104.120000 3290.740000 ;
+ RECT 2103.020000 3284.820000 2104.120000 3285.300000 ;
+ RECT 2103.020000 3279.380000 2104.120000 3279.860000 ;
+ RECT 2058.020000 3295.700000 2059.120000 3296.180000 ;
+ RECT 2058.020000 3290.260000 2059.120000 3290.740000 ;
+ RECT 2058.020000 3284.820000 2059.120000 3285.300000 ;
+ RECT 2058.020000 3279.380000 2059.120000 3279.860000 ;
+ RECT 2103.020000 3273.940000 2104.120000 3274.420000 ;
+ RECT 2103.020000 3257.620000 2104.120000 3258.100000 ;
+ RECT 2103.020000 3252.180000 2104.120000 3252.660000 ;
+ RECT 2103.020000 3263.060000 2104.120000 3263.540000 ;
+ RECT 2103.020000 3268.500000 2104.120000 3268.980000 ;
+ RECT 2058.020000 3273.940000 2059.120000 3274.420000 ;
+ RECT 2058.020000 3257.620000 2059.120000 3258.100000 ;
+ RECT 2058.020000 3252.180000 2059.120000 3252.660000 ;
+ RECT 2058.020000 3263.060000 2059.120000 3263.540000 ;
+ RECT 2058.020000 3268.500000 2059.120000 3268.980000 ;
+ RECT 2053.890000 3279.380000 2054.890000 3279.860000 ;
+ RECT 2053.890000 3284.820000 2054.890000 3285.300000 ;
+ RECT 2053.890000 3290.260000 2054.890000 3290.740000 ;
+ RECT 2053.890000 3295.700000 2054.890000 3296.180000 ;
+ RECT 2053.890000 3252.180000 2054.890000 3252.660000 ;
+ RECT 2053.890000 3257.620000 2054.890000 3258.100000 ;
+ RECT 2053.890000 3263.060000 2054.890000 3263.540000 ;
+ RECT 2053.890000 3268.500000 2054.890000 3268.980000 ;
+ RECT 2053.890000 3273.940000 2054.890000 3274.420000 ;
+ RECT 2157.170000 3224.980000 2158.170000 3225.460000 ;
+ RECT 2157.170000 3230.420000 2158.170000 3230.900000 ;
+ RECT 2157.170000 3235.860000 2158.170000 3236.340000 ;
+ RECT 2157.170000 3241.300000 2158.170000 3241.780000 ;
+ RECT 2157.170000 3246.740000 2158.170000 3247.220000 ;
+ RECT 2157.170000 3203.220000 2158.170000 3203.700000 ;
+ RECT 2157.170000 3208.660000 2158.170000 3209.140000 ;
+ RECT 2157.170000 3214.100000 2158.170000 3214.580000 ;
+ RECT 2157.170000 3219.540000 2158.170000 3220.020000 ;
+ RECT 2148.020000 3224.980000 2149.120000 3225.460000 ;
+ RECT 2148.020000 3230.420000 2149.120000 3230.900000 ;
+ RECT 2148.020000 3235.860000 2149.120000 3236.340000 ;
+ RECT 2148.020000 3241.300000 2149.120000 3241.780000 ;
+ RECT 2148.020000 3246.740000 2149.120000 3247.220000 ;
+ RECT 2148.020000 3203.220000 2149.120000 3203.700000 ;
+ RECT 2148.020000 3208.660000 2149.120000 3209.140000 ;
+ RECT 2148.020000 3214.100000 2149.120000 3214.580000 ;
+ RECT 2148.020000 3219.540000 2149.120000 3220.020000 ;
+ RECT 2157.170000 3176.020000 2158.170000 3176.500000 ;
+ RECT 2157.170000 3181.460000 2158.170000 3181.940000 ;
+ RECT 2157.170000 3186.900000 2158.170000 3187.380000 ;
+ RECT 2157.170000 3192.340000 2158.170000 3192.820000 ;
+ RECT 2157.170000 3197.780000 2158.170000 3198.260000 ;
+ RECT 2157.170000 3154.260000 2158.170000 3154.740000 ;
+ RECT 2157.170000 3159.700000 2158.170000 3160.180000 ;
+ RECT 2157.170000 3165.140000 2158.170000 3165.620000 ;
+ RECT 2157.170000 3170.580000 2158.170000 3171.060000 ;
+ RECT 2148.020000 3197.780000 2149.120000 3198.260000 ;
+ RECT 2148.020000 3192.340000 2149.120000 3192.820000 ;
+ RECT 2148.020000 3186.900000 2149.120000 3187.380000 ;
+ RECT 2148.020000 3181.460000 2149.120000 3181.940000 ;
+ RECT 2148.020000 3176.020000 2149.120000 3176.500000 ;
+ RECT 2148.020000 3170.580000 2149.120000 3171.060000 ;
+ RECT 2148.020000 3165.140000 2149.120000 3165.620000 ;
+ RECT 2148.020000 3154.260000 2149.120000 3154.740000 ;
+ RECT 2148.020000 3159.700000 2149.120000 3160.180000 ;
+ RECT 2103.020000 3246.740000 2104.120000 3247.220000 ;
+ RECT 2103.020000 3241.300000 2104.120000 3241.780000 ;
+ RECT 2103.020000 3235.860000 2104.120000 3236.340000 ;
+ RECT 2103.020000 3224.980000 2104.120000 3225.460000 ;
+ RECT 2103.020000 3230.420000 2104.120000 3230.900000 ;
+ RECT 2058.020000 3246.740000 2059.120000 3247.220000 ;
+ RECT 2058.020000 3241.300000 2059.120000 3241.780000 ;
+ RECT 2058.020000 3235.860000 2059.120000 3236.340000 ;
+ RECT 2058.020000 3230.420000 2059.120000 3230.900000 ;
+ RECT 2058.020000 3224.980000 2059.120000 3225.460000 ;
+ RECT 2103.020000 3219.540000 2104.120000 3220.020000 ;
+ RECT 2103.020000 3214.100000 2104.120000 3214.580000 ;
+ RECT 2103.020000 3208.660000 2104.120000 3209.140000 ;
+ RECT 2103.020000 3203.220000 2104.120000 3203.700000 ;
+ RECT 2058.020000 3219.540000 2059.120000 3220.020000 ;
+ RECT 2058.020000 3214.100000 2059.120000 3214.580000 ;
+ RECT 2058.020000 3208.660000 2059.120000 3209.140000 ;
+ RECT 2058.020000 3203.220000 2059.120000 3203.700000 ;
+ RECT 2053.890000 3224.980000 2054.890000 3225.460000 ;
+ RECT 2053.890000 3230.420000 2054.890000 3230.900000 ;
+ RECT 2053.890000 3235.860000 2054.890000 3236.340000 ;
+ RECT 2053.890000 3241.300000 2054.890000 3241.780000 ;
+ RECT 2053.890000 3246.740000 2054.890000 3247.220000 ;
+ RECT 2053.890000 3203.220000 2054.890000 3203.700000 ;
+ RECT 2053.890000 3208.660000 2054.890000 3209.140000 ;
+ RECT 2053.890000 3214.100000 2054.890000 3214.580000 ;
+ RECT 2053.890000 3219.540000 2054.890000 3220.020000 ;
+ RECT 2103.020000 3197.780000 2104.120000 3198.260000 ;
+ RECT 2103.020000 3192.340000 2104.120000 3192.820000 ;
+ RECT 2103.020000 3186.900000 2104.120000 3187.380000 ;
+ RECT 2103.020000 3181.460000 2104.120000 3181.940000 ;
+ RECT 2103.020000 3176.020000 2104.120000 3176.500000 ;
+ RECT 2058.020000 3197.780000 2059.120000 3198.260000 ;
+ RECT 2058.020000 3192.340000 2059.120000 3192.820000 ;
+ RECT 2058.020000 3186.900000 2059.120000 3187.380000 ;
+ RECT 2058.020000 3181.460000 2059.120000 3181.940000 ;
+ RECT 2058.020000 3176.020000 2059.120000 3176.500000 ;
+ RECT 2103.020000 3159.700000 2104.120000 3160.180000 ;
+ RECT 2103.020000 3154.260000 2104.120000 3154.740000 ;
+ RECT 2103.020000 3165.140000 2104.120000 3165.620000 ;
+ RECT 2103.020000 3170.580000 2104.120000 3171.060000 ;
+ RECT 2058.020000 3159.700000 2059.120000 3160.180000 ;
+ RECT 2058.020000 3154.260000 2059.120000 3154.740000 ;
+ RECT 2058.020000 3165.140000 2059.120000 3165.620000 ;
+ RECT 2058.020000 3170.580000 2059.120000 3171.060000 ;
+ RECT 2053.890000 3176.020000 2054.890000 3176.500000 ;
+ RECT 2053.890000 3181.460000 2054.890000 3181.940000 ;
+ RECT 2053.890000 3186.900000 2054.890000 3187.380000 ;
+ RECT 2053.890000 3192.340000 2054.890000 3192.820000 ;
+ RECT 2053.890000 3197.780000 2054.890000 3198.260000 ;
+ RECT 2053.890000 3154.260000 2054.890000 3154.740000 ;
+ RECT 2053.890000 3159.700000 2054.890000 3160.180000 ;
+ RECT 2053.890000 3165.140000 2054.890000 3165.620000 ;
+ RECT 2053.890000 3170.580000 2054.890000 3171.060000 ;
+ RECT 2051.060000 3344.620000 2161.000000 3345.620000 ;
+ RECT 2051.060000 3152.250000 2161.000000 3153.250000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 3149.400000 2054.890000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 3348.660000 2054.890000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 3149.400000 2158.170000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 3348.660000 2158.170000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 3152.250000 2052.060000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 3152.250000 2161.000000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 3344.620000 2052.060000 3345.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 3344.620000 2161.000000 3345.620000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2949.140000 2054.890000 3149.400000 ;
+ RECT 2157.170000 2949.140000 2158.170000 3149.400000 ;
+ RECT 2058.020000 2951.990000 2059.120000 3145.360000 ;
+ RECT 2103.020000 2951.990000 2104.120000 3145.360000 ;
+ RECT 2148.020000 2951.990000 2149.120000 3145.360000 ;
+ LAYER met3 ;
+ RECT 2157.170000 3128.080000 2158.170000 3128.560000 ;
+ RECT 2157.170000 3133.520000 2158.170000 3134.000000 ;
+ RECT 2157.170000 3138.960000 2158.170000 3139.440000 ;
+ RECT 2157.170000 3100.880000 2158.170000 3101.360000 ;
+ RECT 2157.170000 3106.320000 2158.170000 3106.800000 ;
+ RECT 2157.170000 3111.760000 2158.170000 3112.240000 ;
+ RECT 2157.170000 3117.200000 2158.170000 3117.680000 ;
+ RECT 2157.170000 3122.640000 2158.170000 3123.120000 ;
+ RECT 2148.020000 3128.080000 2149.120000 3128.560000 ;
+ RECT 2148.020000 3133.520000 2149.120000 3134.000000 ;
+ RECT 2148.020000 3138.960000 2149.120000 3139.440000 ;
+ RECT 2148.020000 3100.880000 2149.120000 3101.360000 ;
+ RECT 2148.020000 3106.320000 2149.120000 3106.800000 ;
+ RECT 2148.020000 3111.760000 2149.120000 3112.240000 ;
+ RECT 2148.020000 3117.200000 2149.120000 3117.680000 ;
+ RECT 2148.020000 3122.640000 2149.120000 3123.120000 ;
+ RECT 2157.170000 3079.120000 2158.170000 3079.600000 ;
+ RECT 2157.170000 3084.560000 2158.170000 3085.040000 ;
+ RECT 2157.170000 3090.000000 2158.170000 3090.480000 ;
+ RECT 2157.170000 3095.440000 2158.170000 3095.920000 ;
+ RECT 2157.170000 3051.920000 2158.170000 3052.400000 ;
+ RECT 2157.170000 3057.360000 2158.170000 3057.840000 ;
+ RECT 2157.170000 3062.800000 2158.170000 3063.280000 ;
+ RECT 2157.170000 3068.240000 2158.170000 3068.720000 ;
+ RECT 2157.170000 3073.680000 2158.170000 3074.160000 ;
+ RECT 2148.020000 3095.440000 2149.120000 3095.920000 ;
+ RECT 2148.020000 3090.000000 2149.120000 3090.480000 ;
+ RECT 2148.020000 3084.560000 2149.120000 3085.040000 ;
+ RECT 2148.020000 3079.120000 2149.120000 3079.600000 ;
+ RECT 2148.020000 3073.680000 2149.120000 3074.160000 ;
+ RECT 2148.020000 3068.240000 2149.120000 3068.720000 ;
+ RECT 2148.020000 3062.800000 2149.120000 3063.280000 ;
+ RECT 2148.020000 3051.920000 2149.120000 3052.400000 ;
+ RECT 2148.020000 3057.360000 2149.120000 3057.840000 ;
+ RECT 2103.020000 3138.960000 2104.120000 3139.440000 ;
+ RECT 2103.020000 3133.520000 2104.120000 3134.000000 ;
+ RECT 2103.020000 3128.080000 2104.120000 3128.560000 ;
+ RECT 2058.020000 3138.960000 2059.120000 3139.440000 ;
+ RECT 2058.020000 3133.520000 2059.120000 3134.000000 ;
+ RECT 2058.020000 3128.080000 2059.120000 3128.560000 ;
+ RECT 2103.020000 3117.200000 2104.120000 3117.680000 ;
+ RECT 2103.020000 3111.760000 2104.120000 3112.240000 ;
+ RECT 2103.020000 3106.320000 2104.120000 3106.800000 ;
+ RECT 2103.020000 3100.880000 2104.120000 3101.360000 ;
+ RECT 2103.020000 3122.640000 2104.120000 3123.120000 ;
+ RECT 2058.020000 3122.640000 2059.120000 3123.120000 ;
+ RECT 2058.020000 3117.200000 2059.120000 3117.680000 ;
+ RECT 2058.020000 3111.760000 2059.120000 3112.240000 ;
+ RECT 2058.020000 3106.320000 2059.120000 3106.800000 ;
+ RECT 2058.020000 3100.880000 2059.120000 3101.360000 ;
+ RECT 2053.890000 3128.080000 2054.890000 3128.560000 ;
+ RECT 2053.890000 3133.520000 2054.890000 3134.000000 ;
+ RECT 2053.890000 3138.960000 2054.890000 3139.440000 ;
+ RECT 2053.890000 3100.880000 2054.890000 3101.360000 ;
+ RECT 2053.890000 3106.320000 2054.890000 3106.800000 ;
+ RECT 2053.890000 3111.760000 2054.890000 3112.240000 ;
+ RECT 2053.890000 3117.200000 2054.890000 3117.680000 ;
+ RECT 2053.890000 3122.640000 2054.890000 3123.120000 ;
+ RECT 2103.020000 3095.440000 2104.120000 3095.920000 ;
+ RECT 2103.020000 3090.000000 2104.120000 3090.480000 ;
+ RECT 2103.020000 3084.560000 2104.120000 3085.040000 ;
+ RECT 2103.020000 3079.120000 2104.120000 3079.600000 ;
+ RECT 2058.020000 3095.440000 2059.120000 3095.920000 ;
+ RECT 2058.020000 3090.000000 2059.120000 3090.480000 ;
+ RECT 2058.020000 3084.560000 2059.120000 3085.040000 ;
+ RECT 2058.020000 3079.120000 2059.120000 3079.600000 ;
+ RECT 2103.020000 3073.680000 2104.120000 3074.160000 ;
+ RECT 2103.020000 3057.360000 2104.120000 3057.840000 ;
+ RECT 2103.020000 3051.920000 2104.120000 3052.400000 ;
+ RECT 2103.020000 3062.800000 2104.120000 3063.280000 ;
+ RECT 2103.020000 3068.240000 2104.120000 3068.720000 ;
+ RECT 2058.020000 3073.680000 2059.120000 3074.160000 ;
+ RECT 2058.020000 3057.360000 2059.120000 3057.840000 ;
+ RECT 2058.020000 3051.920000 2059.120000 3052.400000 ;
+ RECT 2058.020000 3062.800000 2059.120000 3063.280000 ;
+ RECT 2058.020000 3068.240000 2059.120000 3068.720000 ;
+ RECT 2053.890000 3079.120000 2054.890000 3079.600000 ;
+ RECT 2053.890000 3084.560000 2054.890000 3085.040000 ;
+ RECT 2053.890000 3090.000000 2054.890000 3090.480000 ;
+ RECT 2053.890000 3095.440000 2054.890000 3095.920000 ;
+ RECT 2053.890000 3051.920000 2054.890000 3052.400000 ;
+ RECT 2053.890000 3057.360000 2054.890000 3057.840000 ;
+ RECT 2053.890000 3062.800000 2054.890000 3063.280000 ;
+ RECT 2053.890000 3068.240000 2054.890000 3068.720000 ;
+ RECT 2053.890000 3073.680000 2054.890000 3074.160000 ;
+ RECT 2157.170000 3024.720000 2158.170000 3025.200000 ;
+ RECT 2157.170000 3030.160000 2158.170000 3030.640000 ;
+ RECT 2157.170000 3035.600000 2158.170000 3036.080000 ;
+ RECT 2157.170000 3041.040000 2158.170000 3041.520000 ;
+ RECT 2157.170000 3046.480000 2158.170000 3046.960000 ;
+ RECT 2157.170000 3002.960000 2158.170000 3003.440000 ;
+ RECT 2157.170000 3008.400000 2158.170000 3008.880000 ;
+ RECT 2157.170000 3013.840000 2158.170000 3014.320000 ;
+ RECT 2157.170000 3019.280000 2158.170000 3019.760000 ;
+ RECT 2148.020000 3024.720000 2149.120000 3025.200000 ;
+ RECT 2148.020000 3030.160000 2149.120000 3030.640000 ;
+ RECT 2148.020000 3035.600000 2149.120000 3036.080000 ;
+ RECT 2148.020000 3041.040000 2149.120000 3041.520000 ;
+ RECT 2148.020000 3046.480000 2149.120000 3046.960000 ;
+ RECT 2148.020000 3002.960000 2149.120000 3003.440000 ;
+ RECT 2148.020000 3008.400000 2149.120000 3008.880000 ;
+ RECT 2148.020000 3013.840000 2149.120000 3014.320000 ;
+ RECT 2148.020000 3019.280000 2149.120000 3019.760000 ;
+ RECT 2157.170000 2975.760000 2158.170000 2976.240000 ;
+ RECT 2157.170000 2981.200000 2158.170000 2981.680000 ;
+ RECT 2157.170000 2986.640000 2158.170000 2987.120000 ;
+ RECT 2157.170000 2992.080000 2158.170000 2992.560000 ;
+ RECT 2157.170000 2997.520000 2158.170000 2998.000000 ;
+ RECT 2157.170000 2954.000000 2158.170000 2954.480000 ;
+ RECT 2157.170000 2959.440000 2158.170000 2959.920000 ;
+ RECT 2157.170000 2964.880000 2158.170000 2965.360000 ;
+ RECT 2157.170000 2970.320000 2158.170000 2970.800000 ;
+ RECT 2148.020000 2997.520000 2149.120000 2998.000000 ;
+ RECT 2148.020000 2992.080000 2149.120000 2992.560000 ;
+ RECT 2148.020000 2986.640000 2149.120000 2987.120000 ;
+ RECT 2148.020000 2981.200000 2149.120000 2981.680000 ;
+ RECT 2148.020000 2975.760000 2149.120000 2976.240000 ;
+ RECT 2148.020000 2970.320000 2149.120000 2970.800000 ;
+ RECT 2148.020000 2964.880000 2149.120000 2965.360000 ;
+ RECT 2148.020000 2954.000000 2149.120000 2954.480000 ;
+ RECT 2148.020000 2959.440000 2149.120000 2959.920000 ;
+ RECT 2103.020000 3046.480000 2104.120000 3046.960000 ;
+ RECT 2103.020000 3041.040000 2104.120000 3041.520000 ;
+ RECT 2103.020000 3035.600000 2104.120000 3036.080000 ;
+ RECT 2103.020000 3024.720000 2104.120000 3025.200000 ;
+ RECT 2103.020000 3030.160000 2104.120000 3030.640000 ;
+ RECT 2058.020000 3046.480000 2059.120000 3046.960000 ;
+ RECT 2058.020000 3041.040000 2059.120000 3041.520000 ;
+ RECT 2058.020000 3035.600000 2059.120000 3036.080000 ;
+ RECT 2058.020000 3030.160000 2059.120000 3030.640000 ;
+ RECT 2058.020000 3024.720000 2059.120000 3025.200000 ;
+ RECT 2103.020000 3019.280000 2104.120000 3019.760000 ;
+ RECT 2103.020000 3013.840000 2104.120000 3014.320000 ;
+ RECT 2103.020000 3008.400000 2104.120000 3008.880000 ;
+ RECT 2103.020000 3002.960000 2104.120000 3003.440000 ;
+ RECT 2058.020000 3019.280000 2059.120000 3019.760000 ;
+ RECT 2058.020000 3013.840000 2059.120000 3014.320000 ;
+ RECT 2058.020000 3008.400000 2059.120000 3008.880000 ;
+ RECT 2058.020000 3002.960000 2059.120000 3003.440000 ;
+ RECT 2053.890000 3024.720000 2054.890000 3025.200000 ;
+ RECT 2053.890000 3030.160000 2054.890000 3030.640000 ;
+ RECT 2053.890000 3035.600000 2054.890000 3036.080000 ;
+ RECT 2053.890000 3041.040000 2054.890000 3041.520000 ;
+ RECT 2053.890000 3046.480000 2054.890000 3046.960000 ;
+ RECT 2053.890000 3002.960000 2054.890000 3003.440000 ;
+ RECT 2053.890000 3008.400000 2054.890000 3008.880000 ;
+ RECT 2053.890000 3013.840000 2054.890000 3014.320000 ;
+ RECT 2053.890000 3019.280000 2054.890000 3019.760000 ;
+ RECT 2103.020000 2997.520000 2104.120000 2998.000000 ;
+ RECT 2103.020000 2992.080000 2104.120000 2992.560000 ;
+ RECT 2103.020000 2986.640000 2104.120000 2987.120000 ;
+ RECT 2103.020000 2981.200000 2104.120000 2981.680000 ;
+ RECT 2103.020000 2975.760000 2104.120000 2976.240000 ;
+ RECT 2058.020000 2997.520000 2059.120000 2998.000000 ;
+ RECT 2058.020000 2992.080000 2059.120000 2992.560000 ;
+ RECT 2058.020000 2986.640000 2059.120000 2987.120000 ;
+ RECT 2058.020000 2981.200000 2059.120000 2981.680000 ;
+ RECT 2058.020000 2975.760000 2059.120000 2976.240000 ;
+ RECT 2103.020000 2959.440000 2104.120000 2959.920000 ;
+ RECT 2103.020000 2954.000000 2104.120000 2954.480000 ;
+ RECT 2103.020000 2964.880000 2104.120000 2965.360000 ;
+ RECT 2103.020000 2970.320000 2104.120000 2970.800000 ;
+ RECT 2058.020000 2959.440000 2059.120000 2959.920000 ;
+ RECT 2058.020000 2954.000000 2059.120000 2954.480000 ;
+ RECT 2058.020000 2964.880000 2059.120000 2965.360000 ;
+ RECT 2058.020000 2970.320000 2059.120000 2970.800000 ;
+ RECT 2053.890000 2975.760000 2054.890000 2976.240000 ;
+ RECT 2053.890000 2981.200000 2054.890000 2981.680000 ;
+ RECT 2053.890000 2986.640000 2054.890000 2987.120000 ;
+ RECT 2053.890000 2992.080000 2054.890000 2992.560000 ;
+ RECT 2053.890000 2997.520000 2054.890000 2998.000000 ;
+ RECT 2053.890000 2954.000000 2054.890000 2954.480000 ;
+ RECT 2053.890000 2959.440000 2054.890000 2959.920000 ;
+ RECT 2053.890000 2964.880000 2054.890000 2965.360000 ;
+ RECT 2053.890000 2970.320000 2054.890000 2970.800000 ;
+ RECT 2051.060000 3144.360000 2161.000000 3145.360000 ;
+ RECT 2051.060000 2951.990000 2161.000000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2949.140000 2054.890000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 3148.400000 2054.890000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 2949.140000 2158.170000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 3148.400000 2158.170000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2951.990000 2052.060000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2951.990000 2161.000000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 3144.360000 2052.060000 3145.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 3144.360000 2161.000000 3145.360000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2748.880000 2054.890000 2949.140000 ;
+ RECT 2157.170000 2748.880000 2158.170000 2949.140000 ;
+ RECT 2058.020000 2751.730000 2059.120000 2945.100000 ;
+ RECT 2103.020000 2751.730000 2104.120000 2945.100000 ;
+ RECT 2148.020000 2751.730000 2149.120000 2945.100000 ;
+ LAYER met3 ;
+ RECT 2157.170000 2927.820000 2158.170000 2928.300000 ;
+ RECT 2157.170000 2933.260000 2158.170000 2933.740000 ;
+ RECT 2157.170000 2938.700000 2158.170000 2939.180000 ;
+ RECT 2157.170000 2900.620000 2158.170000 2901.100000 ;
+ RECT 2157.170000 2906.060000 2158.170000 2906.540000 ;
+ RECT 2157.170000 2911.500000 2158.170000 2911.980000 ;
+ RECT 2157.170000 2916.940000 2158.170000 2917.420000 ;
+ RECT 2157.170000 2922.380000 2158.170000 2922.860000 ;
+ RECT 2148.020000 2927.820000 2149.120000 2928.300000 ;
+ RECT 2148.020000 2933.260000 2149.120000 2933.740000 ;
+ RECT 2148.020000 2938.700000 2149.120000 2939.180000 ;
+ RECT 2148.020000 2900.620000 2149.120000 2901.100000 ;
+ RECT 2148.020000 2906.060000 2149.120000 2906.540000 ;
+ RECT 2148.020000 2911.500000 2149.120000 2911.980000 ;
+ RECT 2148.020000 2916.940000 2149.120000 2917.420000 ;
+ RECT 2148.020000 2922.380000 2149.120000 2922.860000 ;
+ RECT 2157.170000 2878.860000 2158.170000 2879.340000 ;
+ RECT 2157.170000 2884.300000 2158.170000 2884.780000 ;
+ RECT 2157.170000 2889.740000 2158.170000 2890.220000 ;
+ RECT 2157.170000 2895.180000 2158.170000 2895.660000 ;
+ RECT 2157.170000 2851.660000 2158.170000 2852.140000 ;
+ RECT 2157.170000 2857.100000 2158.170000 2857.580000 ;
+ RECT 2157.170000 2862.540000 2158.170000 2863.020000 ;
+ RECT 2157.170000 2867.980000 2158.170000 2868.460000 ;
+ RECT 2157.170000 2873.420000 2158.170000 2873.900000 ;
+ RECT 2148.020000 2895.180000 2149.120000 2895.660000 ;
+ RECT 2148.020000 2889.740000 2149.120000 2890.220000 ;
+ RECT 2148.020000 2884.300000 2149.120000 2884.780000 ;
+ RECT 2148.020000 2878.860000 2149.120000 2879.340000 ;
+ RECT 2148.020000 2873.420000 2149.120000 2873.900000 ;
+ RECT 2148.020000 2867.980000 2149.120000 2868.460000 ;
+ RECT 2148.020000 2862.540000 2149.120000 2863.020000 ;
+ RECT 2148.020000 2851.660000 2149.120000 2852.140000 ;
+ RECT 2148.020000 2857.100000 2149.120000 2857.580000 ;
+ RECT 2103.020000 2938.700000 2104.120000 2939.180000 ;
+ RECT 2103.020000 2933.260000 2104.120000 2933.740000 ;
+ RECT 2103.020000 2927.820000 2104.120000 2928.300000 ;
+ RECT 2058.020000 2938.700000 2059.120000 2939.180000 ;
+ RECT 2058.020000 2933.260000 2059.120000 2933.740000 ;
+ RECT 2058.020000 2927.820000 2059.120000 2928.300000 ;
+ RECT 2103.020000 2916.940000 2104.120000 2917.420000 ;
+ RECT 2103.020000 2911.500000 2104.120000 2911.980000 ;
+ RECT 2103.020000 2906.060000 2104.120000 2906.540000 ;
+ RECT 2103.020000 2900.620000 2104.120000 2901.100000 ;
+ RECT 2103.020000 2922.380000 2104.120000 2922.860000 ;
+ RECT 2058.020000 2922.380000 2059.120000 2922.860000 ;
+ RECT 2058.020000 2916.940000 2059.120000 2917.420000 ;
+ RECT 2058.020000 2911.500000 2059.120000 2911.980000 ;
+ RECT 2058.020000 2906.060000 2059.120000 2906.540000 ;
+ RECT 2058.020000 2900.620000 2059.120000 2901.100000 ;
+ RECT 2053.890000 2927.820000 2054.890000 2928.300000 ;
+ RECT 2053.890000 2933.260000 2054.890000 2933.740000 ;
+ RECT 2053.890000 2938.700000 2054.890000 2939.180000 ;
+ RECT 2053.890000 2900.620000 2054.890000 2901.100000 ;
+ RECT 2053.890000 2906.060000 2054.890000 2906.540000 ;
+ RECT 2053.890000 2911.500000 2054.890000 2911.980000 ;
+ RECT 2053.890000 2916.940000 2054.890000 2917.420000 ;
+ RECT 2053.890000 2922.380000 2054.890000 2922.860000 ;
+ RECT 2103.020000 2895.180000 2104.120000 2895.660000 ;
+ RECT 2103.020000 2889.740000 2104.120000 2890.220000 ;
+ RECT 2103.020000 2884.300000 2104.120000 2884.780000 ;
+ RECT 2103.020000 2878.860000 2104.120000 2879.340000 ;
+ RECT 2058.020000 2895.180000 2059.120000 2895.660000 ;
+ RECT 2058.020000 2889.740000 2059.120000 2890.220000 ;
+ RECT 2058.020000 2884.300000 2059.120000 2884.780000 ;
+ RECT 2058.020000 2878.860000 2059.120000 2879.340000 ;
+ RECT 2103.020000 2873.420000 2104.120000 2873.900000 ;
+ RECT 2103.020000 2857.100000 2104.120000 2857.580000 ;
+ RECT 2103.020000 2851.660000 2104.120000 2852.140000 ;
+ RECT 2103.020000 2862.540000 2104.120000 2863.020000 ;
+ RECT 2103.020000 2867.980000 2104.120000 2868.460000 ;
+ RECT 2058.020000 2873.420000 2059.120000 2873.900000 ;
+ RECT 2058.020000 2857.100000 2059.120000 2857.580000 ;
+ RECT 2058.020000 2851.660000 2059.120000 2852.140000 ;
+ RECT 2058.020000 2862.540000 2059.120000 2863.020000 ;
+ RECT 2058.020000 2867.980000 2059.120000 2868.460000 ;
+ RECT 2053.890000 2878.860000 2054.890000 2879.340000 ;
+ RECT 2053.890000 2884.300000 2054.890000 2884.780000 ;
+ RECT 2053.890000 2889.740000 2054.890000 2890.220000 ;
+ RECT 2053.890000 2895.180000 2054.890000 2895.660000 ;
+ RECT 2053.890000 2851.660000 2054.890000 2852.140000 ;
+ RECT 2053.890000 2857.100000 2054.890000 2857.580000 ;
+ RECT 2053.890000 2862.540000 2054.890000 2863.020000 ;
+ RECT 2053.890000 2867.980000 2054.890000 2868.460000 ;
+ RECT 2053.890000 2873.420000 2054.890000 2873.900000 ;
+ RECT 2157.170000 2824.460000 2158.170000 2824.940000 ;
+ RECT 2157.170000 2829.900000 2158.170000 2830.380000 ;
+ RECT 2157.170000 2835.340000 2158.170000 2835.820000 ;
+ RECT 2157.170000 2840.780000 2158.170000 2841.260000 ;
+ RECT 2157.170000 2846.220000 2158.170000 2846.700000 ;
+ RECT 2157.170000 2802.700000 2158.170000 2803.180000 ;
+ RECT 2157.170000 2808.140000 2158.170000 2808.620000 ;
+ RECT 2157.170000 2813.580000 2158.170000 2814.060000 ;
+ RECT 2157.170000 2819.020000 2158.170000 2819.500000 ;
+ RECT 2148.020000 2824.460000 2149.120000 2824.940000 ;
+ RECT 2148.020000 2829.900000 2149.120000 2830.380000 ;
+ RECT 2148.020000 2835.340000 2149.120000 2835.820000 ;
+ RECT 2148.020000 2840.780000 2149.120000 2841.260000 ;
+ RECT 2148.020000 2846.220000 2149.120000 2846.700000 ;
+ RECT 2148.020000 2802.700000 2149.120000 2803.180000 ;
+ RECT 2148.020000 2808.140000 2149.120000 2808.620000 ;
+ RECT 2148.020000 2813.580000 2149.120000 2814.060000 ;
+ RECT 2148.020000 2819.020000 2149.120000 2819.500000 ;
+ RECT 2157.170000 2775.500000 2158.170000 2775.980000 ;
+ RECT 2157.170000 2780.940000 2158.170000 2781.420000 ;
+ RECT 2157.170000 2786.380000 2158.170000 2786.860000 ;
+ RECT 2157.170000 2791.820000 2158.170000 2792.300000 ;
+ RECT 2157.170000 2797.260000 2158.170000 2797.740000 ;
+ RECT 2157.170000 2753.740000 2158.170000 2754.220000 ;
+ RECT 2157.170000 2759.180000 2158.170000 2759.660000 ;
+ RECT 2157.170000 2764.620000 2158.170000 2765.100000 ;
+ RECT 2157.170000 2770.060000 2158.170000 2770.540000 ;
+ RECT 2148.020000 2797.260000 2149.120000 2797.740000 ;
+ RECT 2148.020000 2791.820000 2149.120000 2792.300000 ;
+ RECT 2148.020000 2786.380000 2149.120000 2786.860000 ;
+ RECT 2148.020000 2780.940000 2149.120000 2781.420000 ;
+ RECT 2148.020000 2775.500000 2149.120000 2775.980000 ;
+ RECT 2148.020000 2770.060000 2149.120000 2770.540000 ;
+ RECT 2148.020000 2764.620000 2149.120000 2765.100000 ;
+ RECT 2148.020000 2753.740000 2149.120000 2754.220000 ;
+ RECT 2148.020000 2759.180000 2149.120000 2759.660000 ;
+ RECT 2103.020000 2846.220000 2104.120000 2846.700000 ;
+ RECT 2103.020000 2840.780000 2104.120000 2841.260000 ;
+ RECT 2103.020000 2835.340000 2104.120000 2835.820000 ;
+ RECT 2103.020000 2824.460000 2104.120000 2824.940000 ;
+ RECT 2103.020000 2829.900000 2104.120000 2830.380000 ;
+ RECT 2058.020000 2846.220000 2059.120000 2846.700000 ;
+ RECT 2058.020000 2840.780000 2059.120000 2841.260000 ;
+ RECT 2058.020000 2835.340000 2059.120000 2835.820000 ;
+ RECT 2058.020000 2829.900000 2059.120000 2830.380000 ;
+ RECT 2058.020000 2824.460000 2059.120000 2824.940000 ;
+ RECT 2103.020000 2819.020000 2104.120000 2819.500000 ;
+ RECT 2103.020000 2813.580000 2104.120000 2814.060000 ;
+ RECT 2103.020000 2808.140000 2104.120000 2808.620000 ;
+ RECT 2103.020000 2802.700000 2104.120000 2803.180000 ;
+ RECT 2058.020000 2819.020000 2059.120000 2819.500000 ;
+ RECT 2058.020000 2813.580000 2059.120000 2814.060000 ;
+ RECT 2058.020000 2808.140000 2059.120000 2808.620000 ;
+ RECT 2058.020000 2802.700000 2059.120000 2803.180000 ;
+ RECT 2053.890000 2824.460000 2054.890000 2824.940000 ;
+ RECT 2053.890000 2829.900000 2054.890000 2830.380000 ;
+ RECT 2053.890000 2835.340000 2054.890000 2835.820000 ;
+ RECT 2053.890000 2840.780000 2054.890000 2841.260000 ;
+ RECT 2053.890000 2846.220000 2054.890000 2846.700000 ;
+ RECT 2053.890000 2802.700000 2054.890000 2803.180000 ;
+ RECT 2053.890000 2808.140000 2054.890000 2808.620000 ;
+ RECT 2053.890000 2813.580000 2054.890000 2814.060000 ;
+ RECT 2053.890000 2819.020000 2054.890000 2819.500000 ;
+ RECT 2103.020000 2797.260000 2104.120000 2797.740000 ;
+ RECT 2103.020000 2791.820000 2104.120000 2792.300000 ;
+ RECT 2103.020000 2786.380000 2104.120000 2786.860000 ;
+ RECT 2103.020000 2780.940000 2104.120000 2781.420000 ;
+ RECT 2103.020000 2775.500000 2104.120000 2775.980000 ;
+ RECT 2058.020000 2797.260000 2059.120000 2797.740000 ;
+ RECT 2058.020000 2791.820000 2059.120000 2792.300000 ;
+ RECT 2058.020000 2786.380000 2059.120000 2786.860000 ;
+ RECT 2058.020000 2780.940000 2059.120000 2781.420000 ;
+ RECT 2058.020000 2775.500000 2059.120000 2775.980000 ;
+ RECT 2103.020000 2759.180000 2104.120000 2759.660000 ;
+ RECT 2103.020000 2753.740000 2104.120000 2754.220000 ;
+ RECT 2103.020000 2764.620000 2104.120000 2765.100000 ;
+ RECT 2103.020000 2770.060000 2104.120000 2770.540000 ;
+ RECT 2058.020000 2759.180000 2059.120000 2759.660000 ;
+ RECT 2058.020000 2753.740000 2059.120000 2754.220000 ;
+ RECT 2058.020000 2764.620000 2059.120000 2765.100000 ;
+ RECT 2058.020000 2770.060000 2059.120000 2770.540000 ;
+ RECT 2053.890000 2775.500000 2054.890000 2775.980000 ;
+ RECT 2053.890000 2780.940000 2054.890000 2781.420000 ;
+ RECT 2053.890000 2786.380000 2054.890000 2786.860000 ;
+ RECT 2053.890000 2791.820000 2054.890000 2792.300000 ;
+ RECT 2053.890000 2797.260000 2054.890000 2797.740000 ;
+ RECT 2053.890000 2753.740000 2054.890000 2754.220000 ;
+ RECT 2053.890000 2759.180000 2054.890000 2759.660000 ;
+ RECT 2053.890000 2764.620000 2054.890000 2765.100000 ;
+ RECT 2053.890000 2770.060000 2054.890000 2770.540000 ;
+ RECT 2051.060000 2944.100000 2161.000000 2945.100000 ;
+ RECT 2051.060000 2751.730000 2161.000000 2752.730000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2748.880000 2054.890000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2948.140000 2054.890000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 2748.880000 2158.170000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 2948.140000 2158.170000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2751.730000 2052.060000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2751.730000 2161.000000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2944.100000 2052.060000 2945.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2944.100000 2161.000000 2945.100000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2548.620000 2054.890000 2748.880000 ;
+ RECT 2157.170000 2548.620000 2158.170000 2748.880000 ;
+ RECT 2058.020000 2551.470000 2059.120000 2744.840000 ;
+ RECT 2103.020000 2551.470000 2104.120000 2744.840000 ;
+ RECT 2148.020000 2551.470000 2149.120000 2744.840000 ;
+ LAYER met3 ;
+ RECT 2157.170000 2727.560000 2158.170000 2728.040000 ;
+ RECT 2157.170000 2733.000000 2158.170000 2733.480000 ;
+ RECT 2157.170000 2738.440000 2158.170000 2738.920000 ;
+ RECT 2157.170000 2700.360000 2158.170000 2700.840000 ;
+ RECT 2157.170000 2705.800000 2158.170000 2706.280000 ;
+ RECT 2157.170000 2711.240000 2158.170000 2711.720000 ;
+ RECT 2157.170000 2716.680000 2158.170000 2717.160000 ;
+ RECT 2157.170000 2722.120000 2158.170000 2722.600000 ;
+ RECT 2148.020000 2727.560000 2149.120000 2728.040000 ;
+ RECT 2148.020000 2733.000000 2149.120000 2733.480000 ;
+ RECT 2148.020000 2738.440000 2149.120000 2738.920000 ;
+ RECT 2148.020000 2700.360000 2149.120000 2700.840000 ;
+ RECT 2148.020000 2705.800000 2149.120000 2706.280000 ;
+ RECT 2148.020000 2711.240000 2149.120000 2711.720000 ;
+ RECT 2148.020000 2716.680000 2149.120000 2717.160000 ;
+ RECT 2148.020000 2722.120000 2149.120000 2722.600000 ;
+ RECT 2157.170000 2678.600000 2158.170000 2679.080000 ;
+ RECT 2157.170000 2684.040000 2158.170000 2684.520000 ;
+ RECT 2157.170000 2689.480000 2158.170000 2689.960000 ;
+ RECT 2157.170000 2694.920000 2158.170000 2695.400000 ;
+ RECT 2157.170000 2651.400000 2158.170000 2651.880000 ;
+ RECT 2157.170000 2656.840000 2158.170000 2657.320000 ;
+ RECT 2157.170000 2662.280000 2158.170000 2662.760000 ;
+ RECT 2157.170000 2667.720000 2158.170000 2668.200000 ;
+ RECT 2157.170000 2673.160000 2158.170000 2673.640000 ;
+ RECT 2148.020000 2694.920000 2149.120000 2695.400000 ;
+ RECT 2148.020000 2689.480000 2149.120000 2689.960000 ;
+ RECT 2148.020000 2684.040000 2149.120000 2684.520000 ;
+ RECT 2148.020000 2678.600000 2149.120000 2679.080000 ;
+ RECT 2148.020000 2673.160000 2149.120000 2673.640000 ;
+ RECT 2148.020000 2667.720000 2149.120000 2668.200000 ;
+ RECT 2148.020000 2662.280000 2149.120000 2662.760000 ;
+ RECT 2148.020000 2651.400000 2149.120000 2651.880000 ;
+ RECT 2148.020000 2656.840000 2149.120000 2657.320000 ;
+ RECT 2103.020000 2738.440000 2104.120000 2738.920000 ;
+ RECT 2103.020000 2733.000000 2104.120000 2733.480000 ;
+ RECT 2103.020000 2727.560000 2104.120000 2728.040000 ;
+ RECT 2058.020000 2738.440000 2059.120000 2738.920000 ;
+ RECT 2058.020000 2733.000000 2059.120000 2733.480000 ;
+ RECT 2058.020000 2727.560000 2059.120000 2728.040000 ;
+ RECT 2103.020000 2716.680000 2104.120000 2717.160000 ;
+ RECT 2103.020000 2711.240000 2104.120000 2711.720000 ;
+ RECT 2103.020000 2705.800000 2104.120000 2706.280000 ;
+ RECT 2103.020000 2700.360000 2104.120000 2700.840000 ;
+ RECT 2103.020000 2722.120000 2104.120000 2722.600000 ;
+ RECT 2058.020000 2722.120000 2059.120000 2722.600000 ;
+ RECT 2058.020000 2716.680000 2059.120000 2717.160000 ;
+ RECT 2058.020000 2711.240000 2059.120000 2711.720000 ;
+ RECT 2058.020000 2705.800000 2059.120000 2706.280000 ;
+ RECT 2058.020000 2700.360000 2059.120000 2700.840000 ;
+ RECT 2053.890000 2727.560000 2054.890000 2728.040000 ;
+ RECT 2053.890000 2733.000000 2054.890000 2733.480000 ;
+ RECT 2053.890000 2738.440000 2054.890000 2738.920000 ;
+ RECT 2053.890000 2700.360000 2054.890000 2700.840000 ;
+ RECT 2053.890000 2705.800000 2054.890000 2706.280000 ;
+ RECT 2053.890000 2711.240000 2054.890000 2711.720000 ;
+ RECT 2053.890000 2716.680000 2054.890000 2717.160000 ;
+ RECT 2053.890000 2722.120000 2054.890000 2722.600000 ;
+ RECT 2103.020000 2694.920000 2104.120000 2695.400000 ;
+ RECT 2103.020000 2689.480000 2104.120000 2689.960000 ;
+ RECT 2103.020000 2684.040000 2104.120000 2684.520000 ;
+ RECT 2103.020000 2678.600000 2104.120000 2679.080000 ;
+ RECT 2058.020000 2694.920000 2059.120000 2695.400000 ;
+ RECT 2058.020000 2689.480000 2059.120000 2689.960000 ;
+ RECT 2058.020000 2684.040000 2059.120000 2684.520000 ;
+ RECT 2058.020000 2678.600000 2059.120000 2679.080000 ;
+ RECT 2103.020000 2673.160000 2104.120000 2673.640000 ;
+ RECT 2103.020000 2656.840000 2104.120000 2657.320000 ;
+ RECT 2103.020000 2651.400000 2104.120000 2651.880000 ;
+ RECT 2103.020000 2662.280000 2104.120000 2662.760000 ;
+ RECT 2103.020000 2667.720000 2104.120000 2668.200000 ;
+ RECT 2058.020000 2673.160000 2059.120000 2673.640000 ;
+ RECT 2058.020000 2656.840000 2059.120000 2657.320000 ;
+ RECT 2058.020000 2651.400000 2059.120000 2651.880000 ;
+ RECT 2058.020000 2662.280000 2059.120000 2662.760000 ;
+ RECT 2058.020000 2667.720000 2059.120000 2668.200000 ;
+ RECT 2053.890000 2678.600000 2054.890000 2679.080000 ;
+ RECT 2053.890000 2684.040000 2054.890000 2684.520000 ;
+ RECT 2053.890000 2689.480000 2054.890000 2689.960000 ;
+ RECT 2053.890000 2694.920000 2054.890000 2695.400000 ;
+ RECT 2053.890000 2651.400000 2054.890000 2651.880000 ;
+ RECT 2053.890000 2656.840000 2054.890000 2657.320000 ;
+ RECT 2053.890000 2662.280000 2054.890000 2662.760000 ;
+ RECT 2053.890000 2667.720000 2054.890000 2668.200000 ;
+ RECT 2053.890000 2673.160000 2054.890000 2673.640000 ;
+ RECT 2157.170000 2624.200000 2158.170000 2624.680000 ;
+ RECT 2157.170000 2629.640000 2158.170000 2630.120000 ;
+ RECT 2157.170000 2635.080000 2158.170000 2635.560000 ;
+ RECT 2157.170000 2640.520000 2158.170000 2641.000000 ;
+ RECT 2157.170000 2645.960000 2158.170000 2646.440000 ;
+ RECT 2157.170000 2602.440000 2158.170000 2602.920000 ;
+ RECT 2157.170000 2607.880000 2158.170000 2608.360000 ;
+ RECT 2157.170000 2613.320000 2158.170000 2613.800000 ;
+ RECT 2157.170000 2618.760000 2158.170000 2619.240000 ;
+ RECT 2148.020000 2624.200000 2149.120000 2624.680000 ;
+ RECT 2148.020000 2629.640000 2149.120000 2630.120000 ;
+ RECT 2148.020000 2635.080000 2149.120000 2635.560000 ;
+ RECT 2148.020000 2640.520000 2149.120000 2641.000000 ;
+ RECT 2148.020000 2645.960000 2149.120000 2646.440000 ;
+ RECT 2148.020000 2602.440000 2149.120000 2602.920000 ;
+ RECT 2148.020000 2607.880000 2149.120000 2608.360000 ;
+ RECT 2148.020000 2613.320000 2149.120000 2613.800000 ;
+ RECT 2148.020000 2618.760000 2149.120000 2619.240000 ;
+ RECT 2157.170000 2575.240000 2158.170000 2575.720000 ;
+ RECT 2157.170000 2580.680000 2158.170000 2581.160000 ;
+ RECT 2157.170000 2586.120000 2158.170000 2586.600000 ;
+ RECT 2157.170000 2591.560000 2158.170000 2592.040000 ;
+ RECT 2157.170000 2597.000000 2158.170000 2597.480000 ;
+ RECT 2157.170000 2553.480000 2158.170000 2553.960000 ;
+ RECT 2157.170000 2558.920000 2158.170000 2559.400000 ;
+ RECT 2157.170000 2564.360000 2158.170000 2564.840000 ;
+ RECT 2157.170000 2569.800000 2158.170000 2570.280000 ;
+ RECT 2148.020000 2597.000000 2149.120000 2597.480000 ;
+ RECT 2148.020000 2591.560000 2149.120000 2592.040000 ;
+ RECT 2148.020000 2586.120000 2149.120000 2586.600000 ;
+ RECT 2148.020000 2580.680000 2149.120000 2581.160000 ;
+ RECT 2148.020000 2575.240000 2149.120000 2575.720000 ;
+ RECT 2148.020000 2569.800000 2149.120000 2570.280000 ;
+ RECT 2148.020000 2564.360000 2149.120000 2564.840000 ;
+ RECT 2148.020000 2553.480000 2149.120000 2553.960000 ;
+ RECT 2148.020000 2558.920000 2149.120000 2559.400000 ;
+ RECT 2103.020000 2645.960000 2104.120000 2646.440000 ;
+ RECT 2103.020000 2640.520000 2104.120000 2641.000000 ;
+ RECT 2103.020000 2635.080000 2104.120000 2635.560000 ;
+ RECT 2103.020000 2624.200000 2104.120000 2624.680000 ;
+ RECT 2103.020000 2629.640000 2104.120000 2630.120000 ;
+ RECT 2058.020000 2645.960000 2059.120000 2646.440000 ;
+ RECT 2058.020000 2640.520000 2059.120000 2641.000000 ;
+ RECT 2058.020000 2635.080000 2059.120000 2635.560000 ;
+ RECT 2058.020000 2629.640000 2059.120000 2630.120000 ;
+ RECT 2058.020000 2624.200000 2059.120000 2624.680000 ;
+ RECT 2103.020000 2618.760000 2104.120000 2619.240000 ;
+ RECT 2103.020000 2613.320000 2104.120000 2613.800000 ;
+ RECT 2103.020000 2607.880000 2104.120000 2608.360000 ;
+ RECT 2103.020000 2602.440000 2104.120000 2602.920000 ;
+ RECT 2058.020000 2618.760000 2059.120000 2619.240000 ;
+ RECT 2058.020000 2613.320000 2059.120000 2613.800000 ;
+ RECT 2058.020000 2607.880000 2059.120000 2608.360000 ;
+ RECT 2058.020000 2602.440000 2059.120000 2602.920000 ;
+ RECT 2053.890000 2624.200000 2054.890000 2624.680000 ;
+ RECT 2053.890000 2629.640000 2054.890000 2630.120000 ;
+ RECT 2053.890000 2635.080000 2054.890000 2635.560000 ;
+ RECT 2053.890000 2640.520000 2054.890000 2641.000000 ;
+ RECT 2053.890000 2645.960000 2054.890000 2646.440000 ;
+ RECT 2053.890000 2602.440000 2054.890000 2602.920000 ;
+ RECT 2053.890000 2607.880000 2054.890000 2608.360000 ;
+ RECT 2053.890000 2613.320000 2054.890000 2613.800000 ;
+ RECT 2053.890000 2618.760000 2054.890000 2619.240000 ;
+ RECT 2103.020000 2597.000000 2104.120000 2597.480000 ;
+ RECT 2103.020000 2591.560000 2104.120000 2592.040000 ;
+ RECT 2103.020000 2586.120000 2104.120000 2586.600000 ;
+ RECT 2103.020000 2580.680000 2104.120000 2581.160000 ;
+ RECT 2103.020000 2575.240000 2104.120000 2575.720000 ;
+ RECT 2058.020000 2597.000000 2059.120000 2597.480000 ;
+ RECT 2058.020000 2591.560000 2059.120000 2592.040000 ;
+ RECT 2058.020000 2586.120000 2059.120000 2586.600000 ;
+ RECT 2058.020000 2580.680000 2059.120000 2581.160000 ;
+ RECT 2058.020000 2575.240000 2059.120000 2575.720000 ;
+ RECT 2103.020000 2558.920000 2104.120000 2559.400000 ;
+ RECT 2103.020000 2553.480000 2104.120000 2553.960000 ;
+ RECT 2103.020000 2564.360000 2104.120000 2564.840000 ;
+ RECT 2103.020000 2569.800000 2104.120000 2570.280000 ;
+ RECT 2058.020000 2558.920000 2059.120000 2559.400000 ;
+ RECT 2058.020000 2553.480000 2059.120000 2553.960000 ;
+ RECT 2058.020000 2564.360000 2059.120000 2564.840000 ;
+ RECT 2058.020000 2569.800000 2059.120000 2570.280000 ;
+ RECT 2053.890000 2575.240000 2054.890000 2575.720000 ;
+ RECT 2053.890000 2580.680000 2054.890000 2581.160000 ;
+ RECT 2053.890000 2586.120000 2054.890000 2586.600000 ;
+ RECT 2053.890000 2591.560000 2054.890000 2592.040000 ;
+ RECT 2053.890000 2597.000000 2054.890000 2597.480000 ;
+ RECT 2053.890000 2553.480000 2054.890000 2553.960000 ;
+ RECT 2053.890000 2558.920000 2054.890000 2559.400000 ;
+ RECT 2053.890000 2564.360000 2054.890000 2564.840000 ;
+ RECT 2053.890000 2569.800000 2054.890000 2570.280000 ;
+ RECT 2051.060000 2743.840000 2161.000000 2744.840000 ;
+ RECT 2051.060000 2551.470000 2161.000000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2548.620000 2054.890000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2747.880000 2054.890000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 2548.620000 2158.170000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 2747.880000 2158.170000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2551.470000 2052.060000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2551.470000 2161.000000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2743.840000 2052.060000 2744.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2743.840000 2161.000000 2744.840000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2348.360000 2054.890000 2548.620000 ;
+ RECT 2157.170000 2348.360000 2158.170000 2548.620000 ;
+ RECT 2058.020000 2351.210000 2059.120000 2544.580000 ;
+ RECT 2103.020000 2351.210000 2104.120000 2544.580000 ;
+ RECT 2148.020000 2351.210000 2149.120000 2544.580000 ;
+ LAYER met3 ;
+ RECT 2157.170000 2527.300000 2158.170000 2527.780000 ;
+ RECT 2157.170000 2532.740000 2158.170000 2533.220000 ;
+ RECT 2157.170000 2538.180000 2158.170000 2538.660000 ;
+ RECT 2157.170000 2500.100000 2158.170000 2500.580000 ;
+ RECT 2157.170000 2505.540000 2158.170000 2506.020000 ;
+ RECT 2157.170000 2510.980000 2158.170000 2511.460000 ;
+ RECT 2157.170000 2516.420000 2158.170000 2516.900000 ;
+ RECT 2157.170000 2521.860000 2158.170000 2522.340000 ;
+ RECT 2148.020000 2527.300000 2149.120000 2527.780000 ;
+ RECT 2148.020000 2532.740000 2149.120000 2533.220000 ;
+ RECT 2148.020000 2538.180000 2149.120000 2538.660000 ;
+ RECT 2148.020000 2500.100000 2149.120000 2500.580000 ;
+ RECT 2148.020000 2505.540000 2149.120000 2506.020000 ;
+ RECT 2148.020000 2510.980000 2149.120000 2511.460000 ;
+ RECT 2148.020000 2516.420000 2149.120000 2516.900000 ;
+ RECT 2148.020000 2521.860000 2149.120000 2522.340000 ;
+ RECT 2157.170000 2478.340000 2158.170000 2478.820000 ;
+ RECT 2157.170000 2483.780000 2158.170000 2484.260000 ;
+ RECT 2157.170000 2489.220000 2158.170000 2489.700000 ;
+ RECT 2157.170000 2494.660000 2158.170000 2495.140000 ;
+ RECT 2157.170000 2451.140000 2158.170000 2451.620000 ;
+ RECT 2157.170000 2456.580000 2158.170000 2457.060000 ;
+ RECT 2157.170000 2462.020000 2158.170000 2462.500000 ;
+ RECT 2157.170000 2467.460000 2158.170000 2467.940000 ;
+ RECT 2157.170000 2472.900000 2158.170000 2473.380000 ;
+ RECT 2148.020000 2494.660000 2149.120000 2495.140000 ;
+ RECT 2148.020000 2489.220000 2149.120000 2489.700000 ;
+ RECT 2148.020000 2483.780000 2149.120000 2484.260000 ;
+ RECT 2148.020000 2478.340000 2149.120000 2478.820000 ;
+ RECT 2148.020000 2472.900000 2149.120000 2473.380000 ;
+ RECT 2148.020000 2467.460000 2149.120000 2467.940000 ;
+ RECT 2148.020000 2462.020000 2149.120000 2462.500000 ;
+ RECT 2148.020000 2451.140000 2149.120000 2451.620000 ;
+ RECT 2148.020000 2456.580000 2149.120000 2457.060000 ;
+ RECT 2103.020000 2538.180000 2104.120000 2538.660000 ;
+ RECT 2103.020000 2532.740000 2104.120000 2533.220000 ;
+ RECT 2103.020000 2527.300000 2104.120000 2527.780000 ;
+ RECT 2058.020000 2538.180000 2059.120000 2538.660000 ;
+ RECT 2058.020000 2532.740000 2059.120000 2533.220000 ;
+ RECT 2058.020000 2527.300000 2059.120000 2527.780000 ;
+ RECT 2103.020000 2516.420000 2104.120000 2516.900000 ;
+ RECT 2103.020000 2510.980000 2104.120000 2511.460000 ;
+ RECT 2103.020000 2505.540000 2104.120000 2506.020000 ;
+ RECT 2103.020000 2500.100000 2104.120000 2500.580000 ;
+ RECT 2103.020000 2521.860000 2104.120000 2522.340000 ;
+ RECT 2058.020000 2521.860000 2059.120000 2522.340000 ;
+ RECT 2058.020000 2516.420000 2059.120000 2516.900000 ;
+ RECT 2058.020000 2510.980000 2059.120000 2511.460000 ;
+ RECT 2058.020000 2505.540000 2059.120000 2506.020000 ;
+ RECT 2058.020000 2500.100000 2059.120000 2500.580000 ;
+ RECT 2053.890000 2527.300000 2054.890000 2527.780000 ;
+ RECT 2053.890000 2532.740000 2054.890000 2533.220000 ;
+ RECT 2053.890000 2538.180000 2054.890000 2538.660000 ;
+ RECT 2053.890000 2500.100000 2054.890000 2500.580000 ;
+ RECT 2053.890000 2505.540000 2054.890000 2506.020000 ;
+ RECT 2053.890000 2510.980000 2054.890000 2511.460000 ;
+ RECT 2053.890000 2516.420000 2054.890000 2516.900000 ;
+ RECT 2053.890000 2521.860000 2054.890000 2522.340000 ;
+ RECT 2103.020000 2494.660000 2104.120000 2495.140000 ;
+ RECT 2103.020000 2489.220000 2104.120000 2489.700000 ;
+ RECT 2103.020000 2483.780000 2104.120000 2484.260000 ;
+ RECT 2103.020000 2478.340000 2104.120000 2478.820000 ;
+ RECT 2058.020000 2494.660000 2059.120000 2495.140000 ;
+ RECT 2058.020000 2489.220000 2059.120000 2489.700000 ;
+ RECT 2058.020000 2483.780000 2059.120000 2484.260000 ;
+ RECT 2058.020000 2478.340000 2059.120000 2478.820000 ;
+ RECT 2103.020000 2472.900000 2104.120000 2473.380000 ;
+ RECT 2103.020000 2456.580000 2104.120000 2457.060000 ;
+ RECT 2103.020000 2451.140000 2104.120000 2451.620000 ;
+ RECT 2103.020000 2462.020000 2104.120000 2462.500000 ;
+ RECT 2103.020000 2467.460000 2104.120000 2467.940000 ;
+ RECT 2058.020000 2472.900000 2059.120000 2473.380000 ;
+ RECT 2058.020000 2456.580000 2059.120000 2457.060000 ;
+ RECT 2058.020000 2451.140000 2059.120000 2451.620000 ;
+ RECT 2058.020000 2462.020000 2059.120000 2462.500000 ;
+ RECT 2058.020000 2467.460000 2059.120000 2467.940000 ;
+ RECT 2053.890000 2478.340000 2054.890000 2478.820000 ;
+ RECT 2053.890000 2483.780000 2054.890000 2484.260000 ;
+ RECT 2053.890000 2489.220000 2054.890000 2489.700000 ;
+ RECT 2053.890000 2494.660000 2054.890000 2495.140000 ;
+ RECT 2053.890000 2451.140000 2054.890000 2451.620000 ;
+ RECT 2053.890000 2456.580000 2054.890000 2457.060000 ;
+ RECT 2053.890000 2462.020000 2054.890000 2462.500000 ;
+ RECT 2053.890000 2467.460000 2054.890000 2467.940000 ;
+ RECT 2053.890000 2472.900000 2054.890000 2473.380000 ;
+ RECT 2157.170000 2423.940000 2158.170000 2424.420000 ;
+ RECT 2157.170000 2429.380000 2158.170000 2429.860000 ;
+ RECT 2157.170000 2434.820000 2158.170000 2435.300000 ;
+ RECT 2157.170000 2440.260000 2158.170000 2440.740000 ;
+ RECT 2157.170000 2445.700000 2158.170000 2446.180000 ;
+ RECT 2157.170000 2402.180000 2158.170000 2402.660000 ;
+ RECT 2157.170000 2407.620000 2158.170000 2408.100000 ;
+ RECT 2157.170000 2413.060000 2158.170000 2413.540000 ;
+ RECT 2157.170000 2418.500000 2158.170000 2418.980000 ;
+ RECT 2148.020000 2423.940000 2149.120000 2424.420000 ;
+ RECT 2148.020000 2429.380000 2149.120000 2429.860000 ;
+ RECT 2148.020000 2434.820000 2149.120000 2435.300000 ;
+ RECT 2148.020000 2440.260000 2149.120000 2440.740000 ;
+ RECT 2148.020000 2445.700000 2149.120000 2446.180000 ;
+ RECT 2148.020000 2402.180000 2149.120000 2402.660000 ;
+ RECT 2148.020000 2407.620000 2149.120000 2408.100000 ;
+ RECT 2148.020000 2413.060000 2149.120000 2413.540000 ;
+ RECT 2148.020000 2418.500000 2149.120000 2418.980000 ;
+ RECT 2157.170000 2374.980000 2158.170000 2375.460000 ;
+ RECT 2157.170000 2380.420000 2158.170000 2380.900000 ;
+ RECT 2157.170000 2385.860000 2158.170000 2386.340000 ;
+ RECT 2157.170000 2391.300000 2158.170000 2391.780000 ;
+ RECT 2157.170000 2396.740000 2158.170000 2397.220000 ;
+ RECT 2157.170000 2353.220000 2158.170000 2353.700000 ;
+ RECT 2157.170000 2358.660000 2158.170000 2359.140000 ;
+ RECT 2157.170000 2364.100000 2158.170000 2364.580000 ;
+ RECT 2157.170000 2369.540000 2158.170000 2370.020000 ;
+ RECT 2148.020000 2396.740000 2149.120000 2397.220000 ;
+ RECT 2148.020000 2391.300000 2149.120000 2391.780000 ;
+ RECT 2148.020000 2385.860000 2149.120000 2386.340000 ;
+ RECT 2148.020000 2380.420000 2149.120000 2380.900000 ;
+ RECT 2148.020000 2374.980000 2149.120000 2375.460000 ;
+ RECT 2148.020000 2369.540000 2149.120000 2370.020000 ;
+ RECT 2148.020000 2364.100000 2149.120000 2364.580000 ;
+ RECT 2148.020000 2353.220000 2149.120000 2353.700000 ;
+ RECT 2148.020000 2358.660000 2149.120000 2359.140000 ;
+ RECT 2103.020000 2445.700000 2104.120000 2446.180000 ;
+ RECT 2103.020000 2440.260000 2104.120000 2440.740000 ;
+ RECT 2103.020000 2434.820000 2104.120000 2435.300000 ;
+ RECT 2103.020000 2423.940000 2104.120000 2424.420000 ;
+ RECT 2103.020000 2429.380000 2104.120000 2429.860000 ;
+ RECT 2058.020000 2445.700000 2059.120000 2446.180000 ;
+ RECT 2058.020000 2440.260000 2059.120000 2440.740000 ;
+ RECT 2058.020000 2434.820000 2059.120000 2435.300000 ;
+ RECT 2058.020000 2429.380000 2059.120000 2429.860000 ;
+ RECT 2058.020000 2423.940000 2059.120000 2424.420000 ;
+ RECT 2103.020000 2418.500000 2104.120000 2418.980000 ;
+ RECT 2103.020000 2413.060000 2104.120000 2413.540000 ;
+ RECT 2103.020000 2407.620000 2104.120000 2408.100000 ;
+ RECT 2103.020000 2402.180000 2104.120000 2402.660000 ;
+ RECT 2058.020000 2418.500000 2059.120000 2418.980000 ;
+ RECT 2058.020000 2413.060000 2059.120000 2413.540000 ;
+ RECT 2058.020000 2407.620000 2059.120000 2408.100000 ;
+ RECT 2058.020000 2402.180000 2059.120000 2402.660000 ;
+ RECT 2053.890000 2423.940000 2054.890000 2424.420000 ;
+ RECT 2053.890000 2429.380000 2054.890000 2429.860000 ;
+ RECT 2053.890000 2434.820000 2054.890000 2435.300000 ;
+ RECT 2053.890000 2440.260000 2054.890000 2440.740000 ;
+ RECT 2053.890000 2445.700000 2054.890000 2446.180000 ;
+ RECT 2053.890000 2402.180000 2054.890000 2402.660000 ;
+ RECT 2053.890000 2407.620000 2054.890000 2408.100000 ;
+ RECT 2053.890000 2413.060000 2054.890000 2413.540000 ;
+ RECT 2053.890000 2418.500000 2054.890000 2418.980000 ;
+ RECT 2103.020000 2396.740000 2104.120000 2397.220000 ;
+ RECT 2103.020000 2391.300000 2104.120000 2391.780000 ;
+ RECT 2103.020000 2385.860000 2104.120000 2386.340000 ;
+ RECT 2103.020000 2380.420000 2104.120000 2380.900000 ;
+ RECT 2103.020000 2374.980000 2104.120000 2375.460000 ;
+ RECT 2058.020000 2396.740000 2059.120000 2397.220000 ;
+ RECT 2058.020000 2391.300000 2059.120000 2391.780000 ;
+ RECT 2058.020000 2385.860000 2059.120000 2386.340000 ;
+ RECT 2058.020000 2380.420000 2059.120000 2380.900000 ;
+ RECT 2058.020000 2374.980000 2059.120000 2375.460000 ;
+ RECT 2103.020000 2358.660000 2104.120000 2359.140000 ;
+ RECT 2103.020000 2353.220000 2104.120000 2353.700000 ;
+ RECT 2103.020000 2364.100000 2104.120000 2364.580000 ;
+ RECT 2103.020000 2369.540000 2104.120000 2370.020000 ;
+ RECT 2058.020000 2358.660000 2059.120000 2359.140000 ;
+ RECT 2058.020000 2353.220000 2059.120000 2353.700000 ;
+ RECT 2058.020000 2364.100000 2059.120000 2364.580000 ;
+ RECT 2058.020000 2369.540000 2059.120000 2370.020000 ;
+ RECT 2053.890000 2374.980000 2054.890000 2375.460000 ;
+ RECT 2053.890000 2380.420000 2054.890000 2380.900000 ;
+ RECT 2053.890000 2385.860000 2054.890000 2386.340000 ;
+ RECT 2053.890000 2391.300000 2054.890000 2391.780000 ;
+ RECT 2053.890000 2396.740000 2054.890000 2397.220000 ;
+ RECT 2053.890000 2353.220000 2054.890000 2353.700000 ;
+ RECT 2053.890000 2358.660000 2054.890000 2359.140000 ;
+ RECT 2053.890000 2364.100000 2054.890000 2364.580000 ;
+ RECT 2053.890000 2369.540000 2054.890000 2370.020000 ;
+ RECT 2051.060000 2543.580000 2161.000000 2544.580000 ;
+ RECT 2051.060000 2351.210000 2161.000000 2352.210000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2348.360000 2054.890000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2547.620000 2054.890000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 2348.360000 2158.170000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 2547.620000 2158.170000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2351.210000 2052.060000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2351.210000 2161.000000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2543.580000 2052.060000 2544.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2543.580000 2161.000000 2544.580000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2148.100000 2054.890000 2348.360000 ;
+ RECT 2157.170000 2148.100000 2158.170000 2348.360000 ;
+ RECT 2058.020000 2150.950000 2059.120000 2344.320000 ;
+ RECT 2103.020000 2150.950000 2104.120000 2344.320000 ;
+ RECT 2148.020000 2150.950000 2149.120000 2344.320000 ;
+ LAYER met3 ;
+ RECT 2157.170000 2327.040000 2158.170000 2327.520000 ;
+ RECT 2157.170000 2332.480000 2158.170000 2332.960000 ;
+ RECT 2157.170000 2337.920000 2158.170000 2338.400000 ;
+ RECT 2157.170000 2299.840000 2158.170000 2300.320000 ;
+ RECT 2157.170000 2305.280000 2158.170000 2305.760000 ;
+ RECT 2157.170000 2310.720000 2158.170000 2311.200000 ;
+ RECT 2157.170000 2316.160000 2158.170000 2316.640000 ;
+ RECT 2157.170000 2321.600000 2158.170000 2322.080000 ;
+ RECT 2148.020000 2327.040000 2149.120000 2327.520000 ;
+ RECT 2148.020000 2332.480000 2149.120000 2332.960000 ;
+ RECT 2148.020000 2337.920000 2149.120000 2338.400000 ;
+ RECT 2148.020000 2299.840000 2149.120000 2300.320000 ;
+ RECT 2148.020000 2305.280000 2149.120000 2305.760000 ;
+ RECT 2148.020000 2310.720000 2149.120000 2311.200000 ;
+ RECT 2148.020000 2316.160000 2149.120000 2316.640000 ;
+ RECT 2148.020000 2321.600000 2149.120000 2322.080000 ;
+ RECT 2157.170000 2278.080000 2158.170000 2278.560000 ;
+ RECT 2157.170000 2283.520000 2158.170000 2284.000000 ;
+ RECT 2157.170000 2288.960000 2158.170000 2289.440000 ;
+ RECT 2157.170000 2294.400000 2158.170000 2294.880000 ;
+ RECT 2157.170000 2250.880000 2158.170000 2251.360000 ;
+ RECT 2157.170000 2256.320000 2158.170000 2256.800000 ;
+ RECT 2157.170000 2261.760000 2158.170000 2262.240000 ;
+ RECT 2157.170000 2267.200000 2158.170000 2267.680000 ;
+ RECT 2157.170000 2272.640000 2158.170000 2273.120000 ;
+ RECT 2148.020000 2294.400000 2149.120000 2294.880000 ;
+ RECT 2148.020000 2288.960000 2149.120000 2289.440000 ;
+ RECT 2148.020000 2283.520000 2149.120000 2284.000000 ;
+ RECT 2148.020000 2278.080000 2149.120000 2278.560000 ;
+ RECT 2148.020000 2272.640000 2149.120000 2273.120000 ;
+ RECT 2148.020000 2267.200000 2149.120000 2267.680000 ;
+ RECT 2148.020000 2261.760000 2149.120000 2262.240000 ;
+ RECT 2148.020000 2250.880000 2149.120000 2251.360000 ;
+ RECT 2148.020000 2256.320000 2149.120000 2256.800000 ;
+ RECT 2103.020000 2337.920000 2104.120000 2338.400000 ;
+ RECT 2103.020000 2332.480000 2104.120000 2332.960000 ;
+ RECT 2103.020000 2327.040000 2104.120000 2327.520000 ;
+ RECT 2058.020000 2337.920000 2059.120000 2338.400000 ;
+ RECT 2058.020000 2332.480000 2059.120000 2332.960000 ;
+ RECT 2058.020000 2327.040000 2059.120000 2327.520000 ;
+ RECT 2103.020000 2316.160000 2104.120000 2316.640000 ;
+ RECT 2103.020000 2310.720000 2104.120000 2311.200000 ;
+ RECT 2103.020000 2305.280000 2104.120000 2305.760000 ;
+ RECT 2103.020000 2299.840000 2104.120000 2300.320000 ;
+ RECT 2103.020000 2321.600000 2104.120000 2322.080000 ;
+ RECT 2058.020000 2321.600000 2059.120000 2322.080000 ;
+ RECT 2058.020000 2316.160000 2059.120000 2316.640000 ;
+ RECT 2058.020000 2310.720000 2059.120000 2311.200000 ;
+ RECT 2058.020000 2305.280000 2059.120000 2305.760000 ;
+ RECT 2058.020000 2299.840000 2059.120000 2300.320000 ;
+ RECT 2053.890000 2327.040000 2054.890000 2327.520000 ;
+ RECT 2053.890000 2332.480000 2054.890000 2332.960000 ;
+ RECT 2053.890000 2337.920000 2054.890000 2338.400000 ;
+ RECT 2053.890000 2299.840000 2054.890000 2300.320000 ;
+ RECT 2053.890000 2305.280000 2054.890000 2305.760000 ;
+ RECT 2053.890000 2310.720000 2054.890000 2311.200000 ;
+ RECT 2053.890000 2316.160000 2054.890000 2316.640000 ;
+ RECT 2053.890000 2321.600000 2054.890000 2322.080000 ;
+ RECT 2103.020000 2294.400000 2104.120000 2294.880000 ;
+ RECT 2103.020000 2288.960000 2104.120000 2289.440000 ;
+ RECT 2103.020000 2283.520000 2104.120000 2284.000000 ;
+ RECT 2103.020000 2278.080000 2104.120000 2278.560000 ;
+ RECT 2058.020000 2294.400000 2059.120000 2294.880000 ;
+ RECT 2058.020000 2288.960000 2059.120000 2289.440000 ;
+ RECT 2058.020000 2283.520000 2059.120000 2284.000000 ;
+ RECT 2058.020000 2278.080000 2059.120000 2278.560000 ;
+ RECT 2103.020000 2272.640000 2104.120000 2273.120000 ;
+ RECT 2103.020000 2256.320000 2104.120000 2256.800000 ;
+ RECT 2103.020000 2250.880000 2104.120000 2251.360000 ;
+ RECT 2103.020000 2261.760000 2104.120000 2262.240000 ;
+ RECT 2103.020000 2267.200000 2104.120000 2267.680000 ;
+ RECT 2058.020000 2272.640000 2059.120000 2273.120000 ;
+ RECT 2058.020000 2256.320000 2059.120000 2256.800000 ;
+ RECT 2058.020000 2250.880000 2059.120000 2251.360000 ;
+ RECT 2058.020000 2261.760000 2059.120000 2262.240000 ;
+ RECT 2058.020000 2267.200000 2059.120000 2267.680000 ;
+ RECT 2053.890000 2278.080000 2054.890000 2278.560000 ;
+ RECT 2053.890000 2283.520000 2054.890000 2284.000000 ;
+ RECT 2053.890000 2288.960000 2054.890000 2289.440000 ;
+ RECT 2053.890000 2294.400000 2054.890000 2294.880000 ;
+ RECT 2053.890000 2250.880000 2054.890000 2251.360000 ;
+ RECT 2053.890000 2256.320000 2054.890000 2256.800000 ;
+ RECT 2053.890000 2261.760000 2054.890000 2262.240000 ;
+ RECT 2053.890000 2267.200000 2054.890000 2267.680000 ;
+ RECT 2053.890000 2272.640000 2054.890000 2273.120000 ;
+ RECT 2157.170000 2223.680000 2158.170000 2224.160000 ;
+ RECT 2157.170000 2229.120000 2158.170000 2229.600000 ;
+ RECT 2157.170000 2234.560000 2158.170000 2235.040000 ;
+ RECT 2157.170000 2240.000000 2158.170000 2240.480000 ;
+ RECT 2157.170000 2245.440000 2158.170000 2245.920000 ;
+ RECT 2157.170000 2201.920000 2158.170000 2202.400000 ;
+ RECT 2157.170000 2207.360000 2158.170000 2207.840000 ;
+ RECT 2157.170000 2212.800000 2158.170000 2213.280000 ;
+ RECT 2157.170000 2218.240000 2158.170000 2218.720000 ;
+ RECT 2148.020000 2223.680000 2149.120000 2224.160000 ;
+ RECT 2148.020000 2229.120000 2149.120000 2229.600000 ;
+ RECT 2148.020000 2234.560000 2149.120000 2235.040000 ;
+ RECT 2148.020000 2240.000000 2149.120000 2240.480000 ;
+ RECT 2148.020000 2245.440000 2149.120000 2245.920000 ;
+ RECT 2148.020000 2201.920000 2149.120000 2202.400000 ;
+ RECT 2148.020000 2207.360000 2149.120000 2207.840000 ;
+ RECT 2148.020000 2212.800000 2149.120000 2213.280000 ;
+ RECT 2148.020000 2218.240000 2149.120000 2218.720000 ;
+ RECT 2157.170000 2174.720000 2158.170000 2175.200000 ;
+ RECT 2157.170000 2180.160000 2158.170000 2180.640000 ;
+ RECT 2157.170000 2185.600000 2158.170000 2186.080000 ;
+ RECT 2157.170000 2191.040000 2158.170000 2191.520000 ;
+ RECT 2157.170000 2196.480000 2158.170000 2196.960000 ;
+ RECT 2157.170000 2152.960000 2158.170000 2153.440000 ;
+ RECT 2157.170000 2158.400000 2158.170000 2158.880000 ;
+ RECT 2157.170000 2163.840000 2158.170000 2164.320000 ;
+ RECT 2157.170000 2169.280000 2158.170000 2169.760000 ;
+ RECT 2148.020000 2196.480000 2149.120000 2196.960000 ;
+ RECT 2148.020000 2191.040000 2149.120000 2191.520000 ;
+ RECT 2148.020000 2185.600000 2149.120000 2186.080000 ;
+ RECT 2148.020000 2180.160000 2149.120000 2180.640000 ;
+ RECT 2148.020000 2174.720000 2149.120000 2175.200000 ;
+ RECT 2148.020000 2169.280000 2149.120000 2169.760000 ;
+ RECT 2148.020000 2163.840000 2149.120000 2164.320000 ;
+ RECT 2148.020000 2152.960000 2149.120000 2153.440000 ;
+ RECT 2148.020000 2158.400000 2149.120000 2158.880000 ;
+ RECT 2103.020000 2245.440000 2104.120000 2245.920000 ;
+ RECT 2103.020000 2240.000000 2104.120000 2240.480000 ;
+ RECT 2103.020000 2234.560000 2104.120000 2235.040000 ;
+ RECT 2103.020000 2223.680000 2104.120000 2224.160000 ;
+ RECT 2103.020000 2229.120000 2104.120000 2229.600000 ;
+ RECT 2058.020000 2245.440000 2059.120000 2245.920000 ;
+ RECT 2058.020000 2240.000000 2059.120000 2240.480000 ;
+ RECT 2058.020000 2234.560000 2059.120000 2235.040000 ;
+ RECT 2058.020000 2229.120000 2059.120000 2229.600000 ;
+ RECT 2058.020000 2223.680000 2059.120000 2224.160000 ;
+ RECT 2103.020000 2218.240000 2104.120000 2218.720000 ;
+ RECT 2103.020000 2212.800000 2104.120000 2213.280000 ;
+ RECT 2103.020000 2207.360000 2104.120000 2207.840000 ;
+ RECT 2103.020000 2201.920000 2104.120000 2202.400000 ;
+ RECT 2058.020000 2218.240000 2059.120000 2218.720000 ;
+ RECT 2058.020000 2212.800000 2059.120000 2213.280000 ;
+ RECT 2058.020000 2207.360000 2059.120000 2207.840000 ;
+ RECT 2058.020000 2201.920000 2059.120000 2202.400000 ;
+ RECT 2053.890000 2223.680000 2054.890000 2224.160000 ;
+ RECT 2053.890000 2229.120000 2054.890000 2229.600000 ;
+ RECT 2053.890000 2234.560000 2054.890000 2235.040000 ;
+ RECT 2053.890000 2240.000000 2054.890000 2240.480000 ;
+ RECT 2053.890000 2245.440000 2054.890000 2245.920000 ;
+ RECT 2053.890000 2201.920000 2054.890000 2202.400000 ;
+ RECT 2053.890000 2207.360000 2054.890000 2207.840000 ;
+ RECT 2053.890000 2212.800000 2054.890000 2213.280000 ;
+ RECT 2053.890000 2218.240000 2054.890000 2218.720000 ;
+ RECT 2103.020000 2196.480000 2104.120000 2196.960000 ;
+ RECT 2103.020000 2191.040000 2104.120000 2191.520000 ;
+ RECT 2103.020000 2185.600000 2104.120000 2186.080000 ;
+ RECT 2103.020000 2180.160000 2104.120000 2180.640000 ;
+ RECT 2103.020000 2174.720000 2104.120000 2175.200000 ;
+ RECT 2058.020000 2196.480000 2059.120000 2196.960000 ;
+ RECT 2058.020000 2191.040000 2059.120000 2191.520000 ;
+ RECT 2058.020000 2185.600000 2059.120000 2186.080000 ;
+ RECT 2058.020000 2180.160000 2059.120000 2180.640000 ;
+ RECT 2058.020000 2174.720000 2059.120000 2175.200000 ;
+ RECT 2103.020000 2158.400000 2104.120000 2158.880000 ;
+ RECT 2103.020000 2152.960000 2104.120000 2153.440000 ;
+ RECT 2103.020000 2163.840000 2104.120000 2164.320000 ;
+ RECT 2103.020000 2169.280000 2104.120000 2169.760000 ;
+ RECT 2058.020000 2158.400000 2059.120000 2158.880000 ;
+ RECT 2058.020000 2152.960000 2059.120000 2153.440000 ;
+ RECT 2058.020000 2163.840000 2059.120000 2164.320000 ;
+ RECT 2058.020000 2169.280000 2059.120000 2169.760000 ;
+ RECT 2053.890000 2174.720000 2054.890000 2175.200000 ;
+ RECT 2053.890000 2180.160000 2054.890000 2180.640000 ;
+ RECT 2053.890000 2185.600000 2054.890000 2186.080000 ;
+ RECT 2053.890000 2191.040000 2054.890000 2191.520000 ;
+ RECT 2053.890000 2196.480000 2054.890000 2196.960000 ;
+ RECT 2053.890000 2152.960000 2054.890000 2153.440000 ;
+ RECT 2053.890000 2158.400000 2054.890000 2158.880000 ;
+ RECT 2053.890000 2163.840000 2054.890000 2164.320000 ;
+ RECT 2053.890000 2169.280000 2054.890000 2169.760000 ;
+ RECT 2051.060000 2343.320000 2161.000000 2344.320000 ;
+ RECT 2051.060000 2150.950000 2161.000000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2148.100000 2054.890000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2347.360000 2054.890000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 2148.100000 2158.170000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 2347.360000 2158.170000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2150.950000 2052.060000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2150.950000 2161.000000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2343.320000 2052.060000 2344.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2343.320000 2161.000000 2344.320000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1947.840000 2054.890000 2148.100000 ;
+ RECT 2157.170000 1947.840000 2158.170000 2148.100000 ;
+ RECT 2058.020000 1950.690000 2059.120000 2144.060000 ;
+ RECT 2103.020000 1950.690000 2104.120000 2144.060000 ;
+ RECT 2148.020000 1950.690000 2149.120000 2144.060000 ;
+ LAYER met3 ;
+ RECT 2157.170000 2126.780000 2158.170000 2127.260000 ;
+ RECT 2157.170000 2132.220000 2158.170000 2132.700000 ;
+ RECT 2157.170000 2137.660000 2158.170000 2138.140000 ;
+ RECT 2157.170000 2099.580000 2158.170000 2100.060000 ;
+ RECT 2157.170000 2105.020000 2158.170000 2105.500000 ;
+ RECT 2157.170000 2110.460000 2158.170000 2110.940000 ;
+ RECT 2157.170000 2115.900000 2158.170000 2116.380000 ;
+ RECT 2157.170000 2121.340000 2158.170000 2121.820000 ;
+ RECT 2148.020000 2126.780000 2149.120000 2127.260000 ;
+ RECT 2148.020000 2132.220000 2149.120000 2132.700000 ;
+ RECT 2148.020000 2137.660000 2149.120000 2138.140000 ;
+ RECT 2148.020000 2099.580000 2149.120000 2100.060000 ;
+ RECT 2148.020000 2105.020000 2149.120000 2105.500000 ;
+ RECT 2148.020000 2110.460000 2149.120000 2110.940000 ;
+ RECT 2148.020000 2115.900000 2149.120000 2116.380000 ;
+ RECT 2148.020000 2121.340000 2149.120000 2121.820000 ;
+ RECT 2157.170000 2077.820000 2158.170000 2078.300000 ;
+ RECT 2157.170000 2083.260000 2158.170000 2083.740000 ;
+ RECT 2157.170000 2088.700000 2158.170000 2089.180000 ;
+ RECT 2157.170000 2094.140000 2158.170000 2094.620000 ;
+ RECT 2157.170000 2050.620000 2158.170000 2051.100000 ;
+ RECT 2157.170000 2056.060000 2158.170000 2056.540000 ;
+ RECT 2157.170000 2061.500000 2158.170000 2061.980000 ;
+ RECT 2157.170000 2066.940000 2158.170000 2067.420000 ;
+ RECT 2157.170000 2072.380000 2158.170000 2072.860000 ;
+ RECT 2148.020000 2094.140000 2149.120000 2094.620000 ;
+ RECT 2148.020000 2088.700000 2149.120000 2089.180000 ;
+ RECT 2148.020000 2083.260000 2149.120000 2083.740000 ;
+ RECT 2148.020000 2077.820000 2149.120000 2078.300000 ;
+ RECT 2148.020000 2072.380000 2149.120000 2072.860000 ;
+ RECT 2148.020000 2066.940000 2149.120000 2067.420000 ;
+ RECT 2148.020000 2061.500000 2149.120000 2061.980000 ;
+ RECT 2148.020000 2050.620000 2149.120000 2051.100000 ;
+ RECT 2148.020000 2056.060000 2149.120000 2056.540000 ;
+ RECT 2103.020000 2137.660000 2104.120000 2138.140000 ;
+ RECT 2103.020000 2132.220000 2104.120000 2132.700000 ;
+ RECT 2103.020000 2126.780000 2104.120000 2127.260000 ;
+ RECT 2058.020000 2137.660000 2059.120000 2138.140000 ;
+ RECT 2058.020000 2132.220000 2059.120000 2132.700000 ;
+ RECT 2058.020000 2126.780000 2059.120000 2127.260000 ;
+ RECT 2103.020000 2115.900000 2104.120000 2116.380000 ;
+ RECT 2103.020000 2110.460000 2104.120000 2110.940000 ;
+ RECT 2103.020000 2105.020000 2104.120000 2105.500000 ;
+ RECT 2103.020000 2099.580000 2104.120000 2100.060000 ;
+ RECT 2103.020000 2121.340000 2104.120000 2121.820000 ;
+ RECT 2058.020000 2121.340000 2059.120000 2121.820000 ;
+ RECT 2058.020000 2115.900000 2059.120000 2116.380000 ;
+ RECT 2058.020000 2110.460000 2059.120000 2110.940000 ;
+ RECT 2058.020000 2105.020000 2059.120000 2105.500000 ;
+ RECT 2058.020000 2099.580000 2059.120000 2100.060000 ;
+ RECT 2053.890000 2126.780000 2054.890000 2127.260000 ;
+ RECT 2053.890000 2132.220000 2054.890000 2132.700000 ;
+ RECT 2053.890000 2137.660000 2054.890000 2138.140000 ;
+ RECT 2053.890000 2099.580000 2054.890000 2100.060000 ;
+ RECT 2053.890000 2105.020000 2054.890000 2105.500000 ;
+ RECT 2053.890000 2110.460000 2054.890000 2110.940000 ;
+ RECT 2053.890000 2115.900000 2054.890000 2116.380000 ;
+ RECT 2053.890000 2121.340000 2054.890000 2121.820000 ;
+ RECT 2103.020000 2094.140000 2104.120000 2094.620000 ;
+ RECT 2103.020000 2088.700000 2104.120000 2089.180000 ;
+ RECT 2103.020000 2083.260000 2104.120000 2083.740000 ;
+ RECT 2103.020000 2077.820000 2104.120000 2078.300000 ;
+ RECT 2058.020000 2094.140000 2059.120000 2094.620000 ;
+ RECT 2058.020000 2088.700000 2059.120000 2089.180000 ;
+ RECT 2058.020000 2083.260000 2059.120000 2083.740000 ;
+ RECT 2058.020000 2077.820000 2059.120000 2078.300000 ;
+ RECT 2103.020000 2072.380000 2104.120000 2072.860000 ;
+ RECT 2103.020000 2056.060000 2104.120000 2056.540000 ;
+ RECT 2103.020000 2050.620000 2104.120000 2051.100000 ;
+ RECT 2103.020000 2061.500000 2104.120000 2061.980000 ;
+ RECT 2103.020000 2066.940000 2104.120000 2067.420000 ;
+ RECT 2058.020000 2072.380000 2059.120000 2072.860000 ;
+ RECT 2058.020000 2056.060000 2059.120000 2056.540000 ;
+ RECT 2058.020000 2050.620000 2059.120000 2051.100000 ;
+ RECT 2058.020000 2061.500000 2059.120000 2061.980000 ;
+ RECT 2058.020000 2066.940000 2059.120000 2067.420000 ;
+ RECT 2053.890000 2077.820000 2054.890000 2078.300000 ;
+ RECT 2053.890000 2083.260000 2054.890000 2083.740000 ;
+ RECT 2053.890000 2088.700000 2054.890000 2089.180000 ;
+ RECT 2053.890000 2094.140000 2054.890000 2094.620000 ;
+ RECT 2053.890000 2050.620000 2054.890000 2051.100000 ;
+ RECT 2053.890000 2056.060000 2054.890000 2056.540000 ;
+ RECT 2053.890000 2061.500000 2054.890000 2061.980000 ;
+ RECT 2053.890000 2066.940000 2054.890000 2067.420000 ;
+ RECT 2053.890000 2072.380000 2054.890000 2072.860000 ;
+ RECT 2157.170000 2023.420000 2158.170000 2023.900000 ;
+ RECT 2157.170000 2028.860000 2158.170000 2029.340000 ;
+ RECT 2157.170000 2034.300000 2158.170000 2034.780000 ;
+ RECT 2157.170000 2039.740000 2158.170000 2040.220000 ;
+ RECT 2157.170000 2045.180000 2158.170000 2045.660000 ;
+ RECT 2157.170000 2001.660000 2158.170000 2002.140000 ;
+ RECT 2157.170000 2007.100000 2158.170000 2007.580000 ;
+ RECT 2157.170000 2012.540000 2158.170000 2013.020000 ;
+ RECT 2157.170000 2017.980000 2158.170000 2018.460000 ;
+ RECT 2148.020000 2023.420000 2149.120000 2023.900000 ;
+ RECT 2148.020000 2028.860000 2149.120000 2029.340000 ;
+ RECT 2148.020000 2034.300000 2149.120000 2034.780000 ;
+ RECT 2148.020000 2039.740000 2149.120000 2040.220000 ;
+ RECT 2148.020000 2045.180000 2149.120000 2045.660000 ;
+ RECT 2148.020000 2001.660000 2149.120000 2002.140000 ;
+ RECT 2148.020000 2007.100000 2149.120000 2007.580000 ;
+ RECT 2148.020000 2012.540000 2149.120000 2013.020000 ;
+ RECT 2148.020000 2017.980000 2149.120000 2018.460000 ;
+ RECT 2157.170000 1974.460000 2158.170000 1974.940000 ;
+ RECT 2157.170000 1979.900000 2158.170000 1980.380000 ;
+ RECT 2157.170000 1985.340000 2158.170000 1985.820000 ;
+ RECT 2157.170000 1990.780000 2158.170000 1991.260000 ;
+ RECT 2157.170000 1996.220000 2158.170000 1996.700000 ;
+ RECT 2157.170000 1952.700000 2158.170000 1953.180000 ;
+ RECT 2157.170000 1958.140000 2158.170000 1958.620000 ;
+ RECT 2157.170000 1963.580000 2158.170000 1964.060000 ;
+ RECT 2157.170000 1969.020000 2158.170000 1969.500000 ;
+ RECT 2148.020000 1996.220000 2149.120000 1996.700000 ;
+ RECT 2148.020000 1990.780000 2149.120000 1991.260000 ;
+ RECT 2148.020000 1985.340000 2149.120000 1985.820000 ;
+ RECT 2148.020000 1979.900000 2149.120000 1980.380000 ;
+ RECT 2148.020000 1974.460000 2149.120000 1974.940000 ;
+ RECT 2148.020000 1969.020000 2149.120000 1969.500000 ;
+ RECT 2148.020000 1963.580000 2149.120000 1964.060000 ;
+ RECT 2148.020000 1952.700000 2149.120000 1953.180000 ;
+ RECT 2148.020000 1958.140000 2149.120000 1958.620000 ;
+ RECT 2103.020000 2045.180000 2104.120000 2045.660000 ;
+ RECT 2103.020000 2039.740000 2104.120000 2040.220000 ;
+ RECT 2103.020000 2034.300000 2104.120000 2034.780000 ;
+ RECT 2103.020000 2023.420000 2104.120000 2023.900000 ;
+ RECT 2103.020000 2028.860000 2104.120000 2029.340000 ;
+ RECT 2058.020000 2045.180000 2059.120000 2045.660000 ;
+ RECT 2058.020000 2039.740000 2059.120000 2040.220000 ;
+ RECT 2058.020000 2034.300000 2059.120000 2034.780000 ;
+ RECT 2058.020000 2028.860000 2059.120000 2029.340000 ;
+ RECT 2058.020000 2023.420000 2059.120000 2023.900000 ;
+ RECT 2103.020000 2017.980000 2104.120000 2018.460000 ;
+ RECT 2103.020000 2012.540000 2104.120000 2013.020000 ;
+ RECT 2103.020000 2007.100000 2104.120000 2007.580000 ;
+ RECT 2103.020000 2001.660000 2104.120000 2002.140000 ;
+ RECT 2058.020000 2017.980000 2059.120000 2018.460000 ;
+ RECT 2058.020000 2012.540000 2059.120000 2013.020000 ;
+ RECT 2058.020000 2007.100000 2059.120000 2007.580000 ;
+ RECT 2058.020000 2001.660000 2059.120000 2002.140000 ;
+ RECT 2053.890000 2023.420000 2054.890000 2023.900000 ;
+ RECT 2053.890000 2028.860000 2054.890000 2029.340000 ;
+ RECT 2053.890000 2034.300000 2054.890000 2034.780000 ;
+ RECT 2053.890000 2039.740000 2054.890000 2040.220000 ;
+ RECT 2053.890000 2045.180000 2054.890000 2045.660000 ;
+ RECT 2053.890000 2001.660000 2054.890000 2002.140000 ;
+ RECT 2053.890000 2007.100000 2054.890000 2007.580000 ;
+ RECT 2053.890000 2012.540000 2054.890000 2013.020000 ;
+ RECT 2053.890000 2017.980000 2054.890000 2018.460000 ;
+ RECT 2103.020000 1996.220000 2104.120000 1996.700000 ;
+ RECT 2103.020000 1990.780000 2104.120000 1991.260000 ;
+ RECT 2103.020000 1985.340000 2104.120000 1985.820000 ;
+ RECT 2103.020000 1979.900000 2104.120000 1980.380000 ;
+ RECT 2103.020000 1974.460000 2104.120000 1974.940000 ;
+ RECT 2058.020000 1996.220000 2059.120000 1996.700000 ;
+ RECT 2058.020000 1990.780000 2059.120000 1991.260000 ;
+ RECT 2058.020000 1985.340000 2059.120000 1985.820000 ;
+ RECT 2058.020000 1979.900000 2059.120000 1980.380000 ;
+ RECT 2058.020000 1974.460000 2059.120000 1974.940000 ;
+ RECT 2103.020000 1958.140000 2104.120000 1958.620000 ;
+ RECT 2103.020000 1952.700000 2104.120000 1953.180000 ;
+ RECT 2103.020000 1963.580000 2104.120000 1964.060000 ;
+ RECT 2103.020000 1969.020000 2104.120000 1969.500000 ;
+ RECT 2058.020000 1958.140000 2059.120000 1958.620000 ;
+ RECT 2058.020000 1952.700000 2059.120000 1953.180000 ;
+ RECT 2058.020000 1963.580000 2059.120000 1964.060000 ;
+ RECT 2058.020000 1969.020000 2059.120000 1969.500000 ;
+ RECT 2053.890000 1974.460000 2054.890000 1974.940000 ;
+ RECT 2053.890000 1979.900000 2054.890000 1980.380000 ;
+ RECT 2053.890000 1985.340000 2054.890000 1985.820000 ;
+ RECT 2053.890000 1990.780000 2054.890000 1991.260000 ;
+ RECT 2053.890000 1996.220000 2054.890000 1996.700000 ;
+ RECT 2053.890000 1952.700000 2054.890000 1953.180000 ;
+ RECT 2053.890000 1958.140000 2054.890000 1958.620000 ;
+ RECT 2053.890000 1963.580000 2054.890000 1964.060000 ;
+ RECT 2053.890000 1969.020000 2054.890000 1969.500000 ;
+ RECT 2051.060000 2143.060000 2161.000000 2144.060000 ;
+ RECT 2051.060000 1950.690000 2161.000000 1951.690000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1947.840000 2054.890000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 2147.100000 2054.890000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 1947.840000 2158.170000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 2147.100000 2158.170000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1950.690000 2052.060000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1950.690000 2161.000000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 2143.060000 2052.060000 2144.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 2143.060000 2161.000000 2144.060000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1747.580000 2054.890000 1947.840000 ;
+ RECT 2157.170000 1747.580000 2158.170000 1947.840000 ;
+ RECT 2058.020000 1750.430000 2059.120000 1943.800000 ;
+ RECT 2103.020000 1750.430000 2104.120000 1943.800000 ;
+ RECT 2148.020000 1750.430000 2149.120000 1943.800000 ;
+ LAYER met3 ;
+ RECT 2157.170000 1926.520000 2158.170000 1927.000000 ;
+ RECT 2157.170000 1931.960000 2158.170000 1932.440000 ;
+ RECT 2157.170000 1937.400000 2158.170000 1937.880000 ;
+ RECT 2157.170000 1899.320000 2158.170000 1899.800000 ;
+ RECT 2157.170000 1904.760000 2158.170000 1905.240000 ;
+ RECT 2157.170000 1910.200000 2158.170000 1910.680000 ;
+ RECT 2157.170000 1915.640000 2158.170000 1916.120000 ;
+ RECT 2157.170000 1921.080000 2158.170000 1921.560000 ;
+ RECT 2148.020000 1926.520000 2149.120000 1927.000000 ;
+ RECT 2148.020000 1931.960000 2149.120000 1932.440000 ;
+ RECT 2148.020000 1937.400000 2149.120000 1937.880000 ;
+ RECT 2148.020000 1899.320000 2149.120000 1899.800000 ;
+ RECT 2148.020000 1904.760000 2149.120000 1905.240000 ;
+ RECT 2148.020000 1910.200000 2149.120000 1910.680000 ;
+ RECT 2148.020000 1915.640000 2149.120000 1916.120000 ;
+ RECT 2148.020000 1921.080000 2149.120000 1921.560000 ;
+ RECT 2157.170000 1877.560000 2158.170000 1878.040000 ;
+ RECT 2157.170000 1883.000000 2158.170000 1883.480000 ;
+ RECT 2157.170000 1888.440000 2158.170000 1888.920000 ;
+ RECT 2157.170000 1893.880000 2158.170000 1894.360000 ;
+ RECT 2157.170000 1850.360000 2158.170000 1850.840000 ;
+ RECT 2157.170000 1855.800000 2158.170000 1856.280000 ;
+ RECT 2157.170000 1861.240000 2158.170000 1861.720000 ;
+ RECT 2157.170000 1866.680000 2158.170000 1867.160000 ;
+ RECT 2157.170000 1872.120000 2158.170000 1872.600000 ;
+ RECT 2148.020000 1893.880000 2149.120000 1894.360000 ;
+ RECT 2148.020000 1888.440000 2149.120000 1888.920000 ;
+ RECT 2148.020000 1883.000000 2149.120000 1883.480000 ;
+ RECT 2148.020000 1877.560000 2149.120000 1878.040000 ;
+ RECT 2148.020000 1872.120000 2149.120000 1872.600000 ;
+ RECT 2148.020000 1866.680000 2149.120000 1867.160000 ;
+ RECT 2148.020000 1861.240000 2149.120000 1861.720000 ;
+ RECT 2148.020000 1850.360000 2149.120000 1850.840000 ;
+ RECT 2148.020000 1855.800000 2149.120000 1856.280000 ;
+ RECT 2103.020000 1937.400000 2104.120000 1937.880000 ;
+ RECT 2103.020000 1931.960000 2104.120000 1932.440000 ;
+ RECT 2103.020000 1926.520000 2104.120000 1927.000000 ;
+ RECT 2058.020000 1937.400000 2059.120000 1937.880000 ;
+ RECT 2058.020000 1931.960000 2059.120000 1932.440000 ;
+ RECT 2058.020000 1926.520000 2059.120000 1927.000000 ;
+ RECT 2103.020000 1915.640000 2104.120000 1916.120000 ;
+ RECT 2103.020000 1910.200000 2104.120000 1910.680000 ;
+ RECT 2103.020000 1904.760000 2104.120000 1905.240000 ;
+ RECT 2103.020000 1899.320000 2104.120000 1899.800000 ;
+ RECT 2103.020000 1921.080000 2104.120000 1921.560000 ;
+ RECT 2058.020000 1921.080000 2059.120000 1921.560000 ;
+ RECT 2058.020000 1915.640000 2059.120000 1916.120000 ;
+ RECT 2058.020000 1910.200000 2059.120000 1910.680000 ;
+ RECT 2058.020000 1904.760000 2059.120000 1905.240000 ;
+ RECT 2058.020000 1899.320000 2059.120000 1899.800000 ;
+ RECT 2053.890000 1926.520000 2054.890000 1927.000000 ;
+ RECT 2053.890000 1931.960000 2054.890000 1932.440000 ;
+ RECT 2053.890000 1937.400000 2054.890000 1937.880000 ;
+ RECT 2053.890000 1899.320000 2054.890000 1899.800000 ;
+ RECT 2053.890000 1904.760000 2054.890000 1905.240000 ;
+ RECT 2053.890000 1910.200000 2054.890000 1910.680000 ;
+ RECT 2053.890000 1915.640000 2054.890000 1916.120000 ;
+ RECT 2053.890000 1921.080000 2054.890000 1921.560000 ;
+ RECT 2103.020000 1893.880000 2104.120000 1894.360000 ;
+ RECT 2103.020000 1888.440000 2104.120000 1888.920000 ;
+ RECT 2103.020000 1883.000000 2104.120000 1883.480000 ;
+ RECT 2103.020000 1877.560000 2104.120000 1878.040000 ;
+ RECT 2058.020000 1893.880000 2059.120000 1894.360000 ;
+ RECT 2058.020000 1888.440000 2059.120000 1888.920000 ;
+ RECT 2058.020000 1883.000000 2059.120000 1883.480000 ;
+ RECT 2058.020000 1877.560000 2059.120000 1878.040000 ;
+ RECT 2103.020000 1872.120000 2104.120000 1872.600000 ;
+ RECT 2103.020000 1855.800000 2104.120000 1856.280000 ;
+ RECT 2103.020000 1850.360000 2104.120000 1850.840000 ;
+ RECT 2103.020000 1861.240000 2104.120000 1861.720000 ;
+ RECT 2103.020000 1866.680000 2104.120000 1867.160000 ;
+ RECT 2058.020000 1872.120000 2059.120000 1872.600000 ;
+ RECT 2058.020000 1855.800000 2059.120000 1856.280000 ;
+ RECT 2058.020000 1850.360000 2059.120000 1850.840000 ;
+ RECT 2058.020000 1861.240000 2059.120000 1861.720000 ;
+ RECT 2058.020000 1866.680000 2059.120000 1867.160000 ;
+ RECT 2053.890000 1877.560000 2054.890000 1878.040000 ;
+ RECT 2053.890000 1883.000000 2054.890000 1883.480000 ;
+ RECT 2053.890000 1888.440000 2054.890000 1888.920000 ;
+ RECT 2053.890000 1893.880000 2054.890000 1894.360000 ;
+ RECT 2053.890000 1850.360000 2054.890000 1850.840000 ;
+ RECT 2053.890000 1855.800000 2054.890000 1856.280000 ;
+ RECT 2053.890000 1861.240000 2054.890000 1861.720000 ;
+ RECT 2053.890000 1866.680000 2054.890000 1867.160000 ;
+ RECT 2053.890000 1872.120000 2054.890000 1872.600000 ;
+ RECT 2157.170000 1823.160000 2158.170000 1823.640000 ;
+ RECT 2157.170000 1828.600000 2158.170000 1829.080000 ;
+ RECT 2157.170000 1834.040000 2158.170000 1834.520000 ;
+ RECT 2157.170000 1839.480000 2158.170000 1839.960000 ;
+ RECT 2157.170000 1844.920000 2158.170000 1845.400000 ;
+ RECT 2157.170000 1801.400000 2158.170000 1801.880000 ;
+ RECT 2157.170000 1806.840000 2158.170000 1807.320000 ;
+ RECT 2157.170000 1812.280000 2158.170000 1812.760000 ;
+ RECT 2157.170000 1817.720000 2158.170000 1818.200000 ;
+ RECT 2148.020000 1823.160000 2149.120000 1823.640000 ;
+ RECT 2148.020000 1828.600000 2149.120000 1829.080000 ;
+ RECT 2148.020000 1834.040000 2149.120000 1834.520000 ;
+ RECT 2148.020000 1839.480000 2149.120000 1839.960000 ;
+ RECT 2148.020000 1844.920000 2149.120000 1845.400000 ;
+ RECT 2148.020000 1801.400000 2149.120000 1801.880000 ;
+ RECT 2148.020000 1806.840000 2149.120000 1807.320000 ;
+ RECT 2148.020000 1812.280000 2149.120000 1812.760000 ;
+ RECT 2148.020000 1817.720000 2149.120000 1818.200000 ;
+ RECT 2157.170000 1774.200000 2158.170000 1774.680000 ;
+ RECT 2157.170000 1779.640000 2158.170000 1780.120000 ;
+ RECT 2157.170000 1785.080000 2158.170000 1785.560000 ;
+ RECT 2157.170000 1790.520000 2158.170000 1791.000000 ;
+ RECT 2157.170000 1795.960000 2158.170000 1796.440000 ;
+ RECT 2157.170000 1752.440000 2158.170000 1752.920000 ;
+ RECT 2157.170000 1757.880000 2158.170000 1758.360000 ;
+ RECT 2157.170000 1763.320000 2158.170000 1763.800000 ;
+ RECT 2157.170000 1768.760000 2158.170000 1769.240000 ;
+ RECT 2148.020000 1795.960000 2149.120000 1796.440000 ;
+ RECT 2148.020000 1790.520000 2149.120000 1791.000000 ;
+ RECT 2148.020000 1785.080000 2149.120000 1785.560000 ;
+ RECT 2148.020000 1779.640000 2149.120000 1780.120000 ;
+ RECT 2148.020000 1774.200000 2149.120000 1774.680000 ;
+ RECT 2148.020000 1768.760000 2149.120000 1769.240000 ;
+ RECT 2148.020000 1763.320000 2149.120000 1763.800000 ;
+ RECT 2148.020000 1752.440000 2149.120000 1752.920000 ;
+ RECT 2148.020000 1757.880000 2149.120000 1758.360000 ;
+ RECT 2103.020000 1844.920000 2104.120000 1845.400000 ;
+ RECT 2103.020000 1839.480000 2104.120000 1839.960000 ;
+ RECT 2103.020000 1834.040000 2104.120000 1834.520000 ;
+ RECT 2103.020000 1823.160000 2104.120000 1823.640000 ;
+ RECT 2103.020000 1828.600000 2104.120000 1829.080000 ;
+ RECT 2058.020000 1844.920000 2059.120000 1845.400000 ;
+ RECT 2058.020000 1839.480000 2059.120000 1839.960000 ;
+ RECT 2058.020000 1834.040000 2059.120000 1834.520000 ;
+ RECT 2058.020000 1828.600000 2059.120000 1829.080000 ;
+ RECT 2058.020000 1823.160000 2059.120000 1823.640000 ;
+ RECT 2103.020000 1817.720000 2104.120000 1818.200000 ;
+ RECT 2103.020000 1812.280000 2104.120000 1812.760000 ;
+ RECT 2103.020000 1806.840000 2104.120000 1807.320000 ;
+ RECT 2103.020000 1801.400000 2104.120000 1801.880000 ;
+ RECT 2058.020000 1817.720000 2059.120000 1818.200000 ;
+ RECT 2058.020000 1812.280000 2059.120000 1812.760000 ;
+ RECT 2058.020000 1806.840000 2059.120000 1807.320000 ;
+ RECT 2058.020000 1801.400000 2059.120000 1801.880000 ;
+ RECT 2053.890000 1823.160000 2054.890000 1823.640000 ;
+ RECT 2053.890000 1828.600000 2054.890000 1829.080000 ;
+ RECT 2053.890000 1834.040000 2054.890000 1834.520000 ;
+ RECT 2053.890000 1839.480000 2054.890000 1839.960000 ;
+ RECT 2053.890000 1844.920000 2054.890000 1845.400000 ;
+ RECT 2053.890000 1801.400000 2054.890000 1801.880000 ;
+ RECT 2053.890000 1806.840000 2054.890000 1807.320000 ;
+ RECT 2053.890000 1812.280000 2054.890000 1812.760000 ;
+ RECT 2053.890000 1817.720000 2054.890000 1818.200000 ;
+ RECT 2103.020000 1795.960000 2104.120000 1796.440000 ;
+ RECT 2103.020000 1790.520000 2104.120000 1791.000000 ;
+ RECT 2103.020000 1785.080000 2104.120000 1785.560000 ;
+ RECT 2103.020000 1779.640000 2104.120000 1780.120000 ;
+ RECT 2103.020000 1774.200000 2104.120000 1774.680000 ;
+ RECT 2058.020000 1795.960000 2059.120000 1796.440000 ;
+ RECT 2058.020000 1790.520000 2059.120000 1791.000000 ;
+ RECT 2058.020000 1785.080000 2059.120000 1785.560000 ;
+ RECT 2058.020000 1779.640000 2059.120000 1780.120000 ;
+ RECT 2058.020000 1774.200000 2059.120000 1774.680000 ;
+ RECT 2103.020000 1757.880000 2104.120000 1758.360000 ;
+ RECT 2103.020000 1752.440000 2104.120000 1752.920000 ;
+ RECT 2103.020000 1763.320000 2104.120000 1763.800000 ;
+ RECT 2103.020000 1768.760000 2104.120000 1769.240000 ;
+ RECT 2058.020000 1757.880000 2059.120000 1758.360000 ;
+ RECT 2058.020000 1752.440000 2059.120000 1752.920000 ;
+ RECT 2058.020000 1763.320000 2059.120000 1763.800000 ;
+ RECT 2058.020000 1768.760000 2059.120000 1769.240000 ;
+ RECT 2053.890000 1774.200000 2054.890000 1774.680000 ;
+ RECT 2053.890000 1779.640000 2054.890000 1780.120000 ;
+ RECT 2053.890000 1785.080000 2054.890000 1785.560000 ;
+ RECT 2053.890000 1790.520000 2054.890000 1791.000000 ;
+ RECT 2053.890000 1795.960000 2054.890000 1796.440000 ;
+ RECT 2053.890000 1752.440000 2054.890000 1752.920000 ;
+ RECT 2053.890000 1757.880000 2054.890000 1758.360000 ;
+ RECT 2053.890000 1763.320000 2054.890000 1763.800000 ;
+ RECT 2053.890000 1768.760000 2054.890000 1769.240000 ;
+ RECT 2051.060000 1942.800000 2161.000000 1943.800000 ;
+ RECT 2051.060000 1750.430000 2161.000000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1747.580000 2054.890000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1946.840000 2054.890000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 1747.580000 2158.170000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 1946.840000 2158.170000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1750.430000 2052.060000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1750.430000 2161.000000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1942.800000 2052.060000 1943.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1942.800000 2161.000000 1943.800000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'RAM_IO'
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1547.320000 2054.890000 1747.580000 ;
+ RECT 2157.170000 1547.320000 2158.170000 1747.580000 ;
+ RECT 2058.020000 1550.170000 2059.120000 1743.540000 ;
+ RECT 2103.020000 1550.170000 2104.120000 1743.540000 ;
+ RECT 2148.020000 1550.170000 2149.120000 1743.540000 ;
+ LAYER met3 ;
+ RECT 2157.170000 1726.260000 2158.170000 1726.740000 ;
+ RECT 2157.170000 1731.700000 2158.170000 1732.180000 ;
+ RECT 2157.170000 1737.140000 2158.170000 1737.620000 ;
+ RECT 2157.170000 1699.060000 2158.170000 1699.540000 ;
+ RECT 2157.170000 1704.500000 2158.170000 1704.980000 ;
+ RECT 2157.170000 1709.940000 2158.170000 1710.420000 ;
+ RECT 2157.170000 1715.380000 2158.170000 1715.860000 ;
+ RECT 2157.170000 1720.820000 2158.170000 1721.300000 ;
+ RECT 2148.020000 1726.260000 2149.120000 1726.740000 ;
+ RECT 2148.020000 1731.700000 2149.120000 1732.180000 ;
+ RECT 2148.020000 1737.140000 2149.120000 1737.620000 ;
+ RECT 2148.020000 1699.060000 2149.120000 1699.540000 ;
+ RECT 2148.020000 1704.500000 2149.120000 1704.980000 ;
+ RECT 2148.020000 1709.940000 2149.120000 1710.420000 ;
+ RECT 2148.020000 1715.380000 2149.120000 1715.860000 ;
+ RECT 2148.020000 1720.820000 2149.120000 1721.300000 ;
+ RECT 2157.170000 1677.300000 2158.170000 1677.780000 ;
+ RECT 2157.170000 1682.740000 2158.170000 1683.220000 ;
+ RECT 2157.170000 1688.180000 2158.170000 1688.660000 ;
+ RECT 2157.170000 1693.620000 2158.170000 1694.100000 ;
+ RECT 2157.170000 1650.100000 2158.170000 1650.580000 ;
+ RECT 2157.170000 1655.540000 2158.170000 1656.020000 ;
+ RECT 2157.170000 1660.980000 2158.170000 1661.460000 ;
+ RECT 2157.170000 1666.420000 2158.170000 1666.900000 ;
+ RECT 2157.170000 1671.860000 2158.170000 1672.340000 ;
+ RECT 2148.020000 1693.620000 2149.120000 1694.100000 ;
+ RECT 2148.020000 1688.180000 2149.120000 1688.660000 ;
+ RECT 2148.020000 1682.740000 2149.120000 1683.220000 ;
+ RECT 2148.020000 1677.300000 2149.120000 1677.780000 ;
+ RECT 2148.020000 1671.860000 2149.120000 1672.340000 ;
+ RECT 2148.020000 1666.420000 2149.120000 1666.900000 ;
+ RECT 2148.020000 1660.980000 2149.120000 1661.460000 ;
+ RECT 2148.020000 1650.100000 2149.120000 1650.580000 ;
+ RECT 2148.020000 1655.540000 2149.120000 1656.020000 ;
+ RECT 2103.020000 1737.140000 2104.120000 1737.620000 ;
+ RECT 2103.020000 1731.700000 2104.120000 1732.180000 ;
+ RECT 2103.020000 1726.260000 2104.120000 1726.740000 ;
+ RECT 2058.020000 1737.140000 2059.120000 1737.620000 ;
+ RECT 2058.020000 1731.700000 2059.120000 1732.180000 ;
+ RECT 2058.020000 1726.260000 2059.120000 1726.740000 ;
+ RECT 2103.020000 1715.380000 2104.120000 1715.860000 ;
+ RECT 2103.020000 1709.940000 2104.120000 1710.420000 ;
+ RECT 2103.020000 1704.500000 2104.120000 1704.980000 ;
+ RECT 2103.020000 1699.060000 2104.120000 1699.540000 ;
+ RECT 2103.020000 1720.820000 2104.120000 1721.300000 ;
+ RECT 2058.020000 1720.820000 2059.120000 1721.300000 ;
+ RECT 2058.020000 1715.380000 2059.120000 1715.860000 ;
+ RECT 2058.020000 1709.940000 2059.120000 1710.420000 ;
+ RECT 2058.020000 1704.500000 2059.120000 1704.980000 ;
+ RECT 2058.020000 1699.060000 2059.120000 1699.540000 ;
+ RECT 2053.890000 1726.260000 2054.890000 1726.740000 ;
+ RECT 2053.890000 1731.700000 2054.890000 1732.180000 ;
+ RECT 2053.890000 1737.140000 2054.890000 1737.620000 ;
+ RECT 2053.890000 1699.060000 2054.890000 1699.540000 ;
+ RECT 2053.890000 1704.500000 2054.890000 1704.980000 ;
+ RECT 2053.890000 1709.940000 2054.890000 1710.420000 ;
+ RECT 2053.890000 1715.380000 2054.890000 1715.860000 ;
+ RECT 2053.890000 1720.820000 2054.890000 1721.300000 ;
+ RECT 2103.020000 1693.620000 2104.120000 1694.100000 ;
+ RECT 2103.020000 1688.180000 2104.120000 1688.660000 ;
+ RECT 2103.020000 1682.740000 2104.120000 1683.220000 ;
+ RECT 2103.020000 1677.300000 2104.120000 1677.780000 ;
+ RECT 2058.020000 1693.620000 2059.120000 1694.100000 ;
+ RECT 2058.020000 1688.180000 2059.120000 1688.660000 ;
+ RECT 2058.020000 1682.740000 2059.120000 1683.220000 ;
+ RECT 2058.020000 1677.300000 2059.120000 1677.780000 ;
+ RECT 2103.020000 1671.860000 2104.120000 1672.340000 ;
+ RECT 2103.020000 1655.540000 2104.120000 1656.020000 ;
+ RECT 2103.020000 1650.100000 2104.120000 1650.580000 ;
+ RECT 2103.020000 1660.980000 2104.120000 1661.460000 ;
+ RECT 2103.020000 1666.420000 2104.120000 1666.900000 ;
+ RECT 2058.020000 1671.860000 2059.120000 1672.340000 ;
+ RECT 2058.020000 1655.540000 2059.120000 1656.020000 ;
+ RECT 2058.020000 1650.100000 2059.120000 1650.580000 ;
+ RECT 2058.020000 1660.980000 2059.120000 1661.460000 ;
+ RECT 2058.020000 1666.420000 2059.120000 1666.900000 ;
+ RECT 2053.890000 1677.300000 2054.890000 1677.780000 ;
+ RECT 2053.890000 1682.740000 2054.890000 1683.220000 ;
+ RECT 2053.890000 1688.180000 2054.890000 1688.660000 ;
+ RECT 2053.890000 1693.620000 2054.890000 1694.100000 ;
+ RECT 2053.890000 1650.100000 2054.890000 1650.580000 ;
+ RECT 2053.890000 1655.540000 2054.890000 1656.020000 ;
+ RECT 2053.890000 1660.980000 2054.890000 1661.460000 ;
+ RECT 2053.890000 1666.420000 2054.890000 1666.900000 ;
+ RECT 2053.890000 1671.860000 2054.890000 1672.340000 ;
+ RECT 2157.170000 1622.900000 2158.170000 1623.380000 ;
+ RECT 2157.170000 1628.340000 2158.170000 1628.820000 ;
+ RECT 2157.170000 1633.780000 2158.170000 1634.260000 ;
+ RECT 2157.170000 1639.220000 2158.170000 1639.700000 ;
+ RECT 2157.170000 1644.660000 2158.170000 1645.140000 ;
+ RECT 2157.170000 1601.140000 2158.170000 1601.620000 ;
+ RECT 2157.170000 1606.580000 2158.170000 1607.060000 ;
+ RECT 2157.170000 1612.020000 2158.170000 1612.500000 ;
+ RECT 2157.170000 1617.460000 2158.170000 1617.940000 ;
+ RECT 2148.020000 1622.900000 2149.120000 1623.380000 ;
+ RECT 2148.020000 1628.340000 2149.120000 1628.820000 ;
+ RECT 2148.020000 1633.780000 2149.120000 1634.260000 ;
+ RECT 2148.020000 1639.220000 2149.120000 1639.700000 ;
+ RECT 2148.020000 1644.660000 2149.120000 1645.140000 ;
+ RECT 2148.020000 1601.140000 2149.120000 1601.620000 ;
+ RECT 2148.020000 1606.580000 2149.120000 1607.060000 ;
+ RECT 2148.020000 1612.020000 2149.120000 1612.500000 ;
+ RECT 2148.020000 1617.460000 2149.120000 1617.940000 ;
+ RECT 2157.170000 1573.940000 2158.170000 1574.420000 ;
+ RECT 2157.170000 1579.380000 2158.170000 1579.860000 ;
+ RECT 2157.170000 1584.820000 2158.170000 1585.300000 ;
+ RECT 2157.170000 1590.260000 2158.170000 1590.740000 ;
+ RECT 2157.170000 1595.700000 2158.170000 1596.180000 ;
+ RECT 2157.170000 1552.180000 2158.170000 1552.660000 ;
+ RECT 2157.170000 1557.620000 2158.170000 1558.100000 ;
+ RECT 2157.170000 1563.060000 2158.170000 1563.540000 ;
+ RECT 2157.170000 1568.500000 2158.170000 1568.980000 ;
+ RECT 2148.020000 1595.700000 2149.120000 1596.180000 ;
+ RECT 2148.020000 1590.260000 2149.120000 1590.740000 ;
+ RECT 2148.020000 1584.820000 2149.120000 1585.300000 ;
+ RECT 2148.020000 1579.380000 2149.120000 1579.860000 ;
+ RECT 2148.020000 1573.940000 2149.120000 1574.420000 ;
+ RECT 2148.020000 1568.500000 2149.120000 1568.980000 ;
+ RECT 2148.020000 1563.060000 2149.120000 1563.540000 ;
+ RECT 2148.020000 1552.180000 2149.120000 1552.660000 ;
+ RECT 2148.020000 1557.620000 2149.120000 1558.100000 ;
+ RECT 2103.020000 1644.660000 2104.120000 1645.140000 ;
+ RECT 2103.020000 1639.220000 2104.120000 1639.700000 ;
+ RECT 2103.020000 1633.780000 2104.120000 1634.260000 ;
+ RECT 2103.020000 1622.900000 2104.120000 1623.380000 ;
+ RECT 2103.020000 1628.340000 2104.120000 1628.820000 ;
+ RECT 2058.020000 1644.660000 2059.120000 1645.140000 ;
+ RECT 2058.020000 1639.220000 2059.120000 1639.700000 ;
+ RECT 2058.020000 1633.780000 2059.120000 1634.260000 ;
+ RECT 2058.020000 1628.340000 2059.120000 1628.820000 ;
+ RECT 2058.020000 1622.900000 2059.120000 1623.380000 ;
+ RECT 2103.020000 1617.460000 2104.120000 1617.940000 ;
+ RECT 2103.020000 1612.020000 2104.120000 1612.500000 ;
+ RECT 2103.020000 1606.580000 2104.120000 1607.060000 ;
+ RECT 2103.020000 1601.140000 2104.120000 1601.620000 ;
+ RECT 2058.020000 1617.460000 2059.120000 1617.940000 ;
+ RECT 2058.020000 1612.020000 2059.120000 1612.500000 ;
+ RECT 2058.020000 1606.580000 2059.120000 1607.060000 ;
+ RECT 2058.020000 1601.140000 2059.120000 1601.620000 ;
+ RECT 2053.890000 1622.900000 2054.890000 1623.380000 ;
+ RECT 2053.890000 1628.340000 2054.890000 1628.820000 ;
+ RECT 2053.890000 1633.780000 2054.890000 1634.260000 ;
+ RECT 2053.890000 1639.220000 2054.890000 1639.700000 ;
+ RECT 2053.890000 1644.660000 2054.890000 1645.140000 ;
+ RECT 2053.890000 1601.140000 2054.890000 1601.620000 ;
+ RECT 2053.890000 1606.580000 2054.890000 1607.060000 ;
+ RECT 2053.890000 1612.020000 2054.890000 1612.500000 ;
+ RECT 2053.890000 1617.460000 2054.890000 1617.940000 ;
+ RECT 2103.020000 1595.700000 2104.120000 1596.180000 ;
+ RECT 2103.020000 1590.260000 2104.120000 1590.740000 ;
+ RECT 2103.020000 1584.820000 2104.120000 1585.300000 ;
+ RECT 2103.020000 1579.380000 2104.120000 1579.860000 ;
+ RECT 2103.020000 1573.940000 2104.120000 1574.420000 ;
+ RECT 2058.020000 1595.700000 2059.120000 1596.180000 ;
+ RECT 2058.020000 1590.260000 2059.120000 1590.740000 ;
+ RECT 2058.020000 1584.820000 2059.120000 1585.300000 ;
+ RECT 2058.020000 1579.380000 2059.120000 1579.860000 ;
+ RECT 2058.020000 1573.940000 2059.120000 1574.420000 ;
+ RECT 2103.020000 1557.620000 2104.120000 1558.100000 ;
+ RECT 2103.020000 1552.180000 2104.120000 1552.660000 ;
+ RECT 2103.020000 1563.060000 2104.120000 1563.540000 ;
+ RECT 2103.020000 1568.500000 2104.120000 1568.980000 ;
+ RECT 2058.020000 1557.620000 2059.120000 1558.100000 ;
+ RECT 2058.020000 1552.180000 2059.120000 1552.660000 ;
+ RECT 2058.020000 1563.060000 2059.120000 1563.540000 ;
+ RECT 2058.020000 1568.500000 2059.120000 1568.980000 ;
+ RECT 2053.890000 1573.940000 2054.890000 1574.420000 ;
+ RECT 2053.890000 1579.380000 2054.890000 1579.860000 ;
+ RECT 2053.890000 1584.820000 2054.890000 1585.300000 ;
+ RECT 2053.890000 1590.260000 2054.890000 1590.740000 ;
+ RECT 2053.890000 1595.700000 2054.890000 1596.180000 ;
+ RECT 2053.890000 1552.180000 2054.890000 1552.660000 ;
+ RECT 2053.890000 1557.620000 2054.890000 1558.100000 ;
+ RECT 2053.890000 1563.060000 2054.890000 1563.540000 ;
+ RECT 2053.890000 1568.500000 2054.890000 1568.980000 ;
+ RECT 2051.060000 1742.540000 2161.000000 1743.540000 ;
+ RECT 2051.060000 1550.170000 2161.000000 1551.170000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1547.320000 2054.890000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2053.890000 1746.580000 2054.890000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 1547.320000 2158.170000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2157.170000 1746.580000 2158.170000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1550.170000 2052.060000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1550.170000 2161.000000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2051.060000 1742.540000 2052.060000 1743.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2160.000000 1742.540000 2161.000000 1743.540000 ;
+ END
+# end of P/G pin shape extracted from block 'RAM_IO'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 3349.660000 243.990000 3379.920000 ;
+ RECT 436.430000 3349.660000 437.430000 3379.920000 ;
+ RECT 247.120000 3352.510000 248.220000 3376.560000 ;
+ RECT 292.120000 3352.510000 293.220000 3376.560000 ;
+ RECT 337.120000 3352.510000 338.220000 3376.560000 ;
+ RECT 382.120000 3352.510000 383.220000 3376.560000 ;
+ RECT 427.120000 3352.510000 428.220000 3376.560000 ;
+ LAYER met3 ;
+ RECT 436.430000 3365.400000 437.430000 3365.880000 ;
+ RECT 436.430000 3370.840000 437.430000 3371.320000 ;
+ RECT 427.120000 3370.840000 428.220000 3371.320000 ;
+ RECT 427.120000 3365.400000 428.220000 3365.880000 ;
+ RECT 382.120000 3365.400000 383.220000 3365.880000 ;
+ RECT 382.120000 3370.840000 383.220000 3371.320000 ;
+ RECT 292.120000 3365.400000 293.220000 3365.880000 ;
+ RECT 337.120000 3365.400000 338.220000 3365.880000 ;
+ RECT 337.120000 3370.840000 338.220000 3371.320000 ;
+ RECT 292.120000 3370.840000 293.220000 3371.320000 ;
+ RECT 242.990000 3365.400000 243.990000 3365.880000 ;
+ RECT 247.120000 3365.400000 248.220000 3365.880000 ;
+ RECT 247.120000 3370.840000 248.220000 3371.320000 ;
+ RECT 242.990000 3370.840000 243.990000 3371.320000 ;
+ RECT 436.430000 3354.520000 437.430000 3355.000000 ;
+ RECT 436.430000 3359.960000 437.430000 3360.440000 ;
+ RECT 427.120000 3359.960000 428.220000 3360.440000 ;
+ RECT 427.120000 3354.520000 428.220000 3355.000000 ;
+ RECT 382.120000 3354.520000 383.220000 3355.000000 ;
+ RECT 382.120000 3359.960000 383.220000 3360.440000 ;
+ RECT 292.120000 3354.520000 293.220000 3355.000000 ;
+ RECT 337.120000 3354.520000 338.220000 3355.000000 ;
+ RECT 337.120000 3359.960000 338.220000 3360.440000 ;
+ RECT 292.120000 3359.960000 293.220000 3360.440000 ;
+ RECT 242.990000 3359.960000 243.990000 3360.440000 ;
+ RECT 247.120000 3359.960000 248.220000 3360.440000 ;
+ RECT 242.990000 3354.520000 243.990000 3355.000000 ;
+ RECT 247.120000 3354.520000 248.220000 3355.000000 ;
+ RECT 240.160000 3375.560000 440.260000 3376.560000 ;
+ RECT 240.160000 3352.510000 440.260000 3353.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 3349.660000 243.990000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 3378.920000 243.990000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 3349.660000 437.430000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 3378.920000 437.430000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 3352.510000 241.160000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 3352.510000 440.260000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 3375.560000 241.160000 3376.560000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 3375.560000 440.260000 3376.560000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 1349.910000 428.220000 1543.280000 ;
+ RECT 382.120000 1349.910000 383.220000 1543.280000 ;
+ RECT 436.430000 1347.060000 437.430000 1547.320000 ;
+ RECT 337.120000 1349.910000 338.220000 1543.280000 ;
+ RECT 292.120000 1349.910000 293.220000 1543.280000 ;
+ RECT 247.120000 1349.910000 248.220000 1543.280000 ;
+ RECT 242.990000 1347.060000 243.990000 1547.320000 ;
+ LAYER met3 ;
+ RECT 427.120000 1536.880000 428.220000 1537.360000 ;
+ RECT 436.430000 1536.880000 437.430000 1537.360000 ;
+ RECT 436.430000 1526.000000 437.430000 1526.480000 ;
+ RECT 436.430000 1531.440000 437.430000 1531.920000 ;
+ RECT 427.120000 1531.440000 428.220000 1531.920000 ;
+ RECT 427.120000 1526.000000 428.220000 1526.480000 ;
+ RECT 427.120000 1520.560000 428.220000 1521.040000 ;
+ RECT 427.120000 1515.120000 428.220000 1515.600000 ;
+ RECT 436.430000 1520.560000 437.430000 1521.040000 ;
+ RECT 436.430000 1515.120000 437.430000 1515.600000 ;
+ RECT 427.120000 1498.800000 428.220000 1499.280000 ;
+ RECT 427.120000 1504.240000 428.220000 1504.720000 ;
+ RECT 436.430000 1504.240000 437.430000 1504.720000 ;
+ RECT 436.430000 1498.800000 437.430000 1499.280000 ;
+ RECT 427.120000 1509.680000 428.220000 1510.160000 ;
+ RECT 436.430000 1509.680000 437.430000 1510.160000 ;
+ RECT 382.120000 1536.880000 383.220000 1537.360000 ;
+ RECT 382.120000 1531.440000 383.220000 1531.920000 ;
+ RECT 382.120000 1526.000000 383.220000 1526.480000 ;
+ RECT 382.120000 1520.560000 383.220000 1521.040000 ;
+ RECT 382.120000 1498.800000 383.220000 1499.280000 ;
+ RECT 382.120000 1504.240000 383.220000 1504.720000 ;
+ RECT 382.120000 1509.680000 383.220000 1510.160000 ;
+ RECT 382.120000 1515.120000 383.220000 1515.600000 ;
+ RECT 436.430000 1487.920000 437.430000 1488.400000 ;
+ RECT 436.430000 1493.360000 437.430000 1493.840000 ;
+ RECT 427.120000 1493.360000 428.220000 1493.840000 ;
+ RECT 427.120000 1487.920000 428.220000 1488.400000 ;
+ RECT 427.120000 1482.480000 428.220000 1482.960000 ;
+ RECT 427.120000 1477.040000 428.220000 1477.520000 ;
+ RECT 436.430000 1482.480000 437.430000 1482.960000 ;
+ RECT 436.430000 1477.040000 437.430000 1477.520000 ;
+ RECT 436.430000 1460.720000 437.430000 1461.200000 ;
+ RECT 436.430000 1466.160000 437.430000 1466.640000 ;
+ RECT 436.430000 1471.600000 437.430000 1472.080000 ;
+ RECT 427.120000 1466.160000 428.220000 1466.640000 ;
+ RECT 427.120000 1460.720000 428.220000 1461.200000 ;
+ RECT 427.120000 1471.600000 428.220000 1472.080000 ;
+ RECT 427.120000 1455.280000 428.220000 1455.760000 ;
+ RECT 427.120000 1449.840000 428.220000 1450.320000 ;
+ RECT 436.430000 1455.280000 437.430000 1455.760000 ;
+ RECT 436.430000 1449.840000 437.430000 1450.320000 ;
+ RECT 382.120000 1493.360000 383.220000 1493.840000 ;
+ RECT 382.120000 1487.920000 383.220000 1488.400000 ;
+ RECT 382.120000 1482.480000 383.220000 1482.960000 ;
+ RECT 382.120000 1477.040000 383.220000 1477.520000 ;
+ RECT 382.120000 1466.160000 383.220000 1466.640000 ;
+ RECT 382.120000 1460.720000 383.220000 1461.200000 ;
+ RECT 382.120000 1455.280000 383.220000 1455.760000 ;
+ RECT 382.120000 1449.840000 383.220000 1450.320000 ;
+ RECT 382.120000 1471.600000 383.220000 1472.080000 ;
+ RECT 337.120000 1536.880000 338.220000 1537.360000 ;
+ RECT 337.120000 1531.440000 338.220000 1531.920000 ;
+ RECT 337.120000 1526.000000 338.220000 1526.480000 ;
+ RECT 292.120000 1536.880000 293.220000 1537.360000 ;
+ RECT 292.120000 1531.440000 293.220000 1531.920000 ;
+ RECT 292.120000 1526.000000 293.220000 1526.480000 ;
+ RECT 337.120000 1509.680000 338.220000 1510.160000 ;
+ RECT 337.120000 1504.240000 338.220000 1504.720000 ;
+ RECT 337.120000 1498.800000 338.220000 1499.280000 ;
+ RECT 337.120000 1515.120000 338.220000 1515.600000 ;
+ RECT 337.120000 1520.560000 338.220000 1521.040000 ;
+ RECT 292.120000 1520.560000 293.220000 1521.040000 ;
+ RECT 292.120000 1509.680000 293.220000 1510.160000 ;
+ RECT 292.120000 1504.240000 293.220000 1504.720000 ;
+ RECT 292.120000 1498.800000 293.220000 1499.280000 ;
+ RECT 292.120000 1515.120000 293.220000 1515.600000 ;
+ RECT 247.120000 1536.880000 248.220000 1537.360000 ;
+ RECT 242.990000 1536.880000 243.990000 1537.360000 ;
+ RECT 242.990000 1531.440000 243.990000 1531.920000 ;
+ RECT 247.120000 1531.440000 248.220000 1531.920000 ;
+ RECT 247.120000 1526.000000 248.220000 1526.480000 ;
+ RECT 242.990000 1526.000000 243.990000 1526.480000 ;
+ RECT 247.120000 1520.560000 248.220000 1521.040000 ;
+ RECT 242.990000 1520.560000 243.990000 1521.040000 ;
+ RECT 247.120000 1515.120000 248.220000 1515.600000 ;
+ RECT 242.990000 1515.120000 243.990000 1515.600000 ;
+ RECT 247.120000 1504.240000 248.220000 1504.720000 ;
+ RECT 242.990000 1504.240000 243.990000 1504.720000 ;
+ RECT 247.120000 1498.800000 248.220000 1499.280000 ;
+ RECT 242.990000 1498.800000 243.990000 1499.280000 ;
+ RECT 247.120000 1509.680000 248.220000 1510.160000 ;
+ RECT 242.990000 1509.680000 243.990000 1510.160000 ;
+ RECT 337.120000 1493.360000 338.220000 1493.840000 ;
+ RECT 337.120000 1487.920000 338.220000 1488.400000 ;
+ RECT 337.120000 1482.480000 338.220000 1482.960000 ;
+ RECT 337.120000 1477.040000 338.220000 1477.520000 ;
+ RECT 292.120000 1493.360000 293.220000 1493.840000 ;
+ RECT 292.120000 1487.920000 293.220000 1488.400000 ;
+ RECT 292.120000 1482.480000 293.220000 1482.960000 ;
+ RECT 292.120000 1477.040000 293.220000 1477.520000 ;
+ RECT 337.120000 1466.160000 338.220000 1466.640000 ;
+ RECT 337.120000 1449.840000 338.220000 1450.320000 ;
+ RECT 337.120000 1455.280000 338.220000 1455.760000 ;
+ RECT 337.120000 1460.720000 338.220000 1461.200000 ;
+ RECT 337.120000 1471.600000 338.220000 1472.080000 ;
+ RECT 292.120000 1449.840000 293.220000 1450.320000 ;
+ RECT 292.120000 1455.280000 293.220000 1455.760000 ;
+ RECT 292.120000 1460.720000 293.220000 1461.200000 ;
+ RECT 292.120000 1466.160000 293.220000 1466.640000 ;
+ RECT 292.120000 1471.600000 293.220000 1472.080000 ;
+ RECT 247.120000 1493.360000 248.220000 1493.840000 ;
+ RECT 242.990000 1493.360000 243.990000 1493.840000 ;
+ RECT 247.120000 1487.920000 248.220000 1488.400000 ;
+ RECT 242.990000 1487.920000 243.990000 1488.400000 ;
+ RECT 247.120000 1482.480000 248.220000 1482.960000 ;
+ RECT 242.990000 1482.480000 243.990000 1482.960000 ;
+ RECT 247.120000 1477.040000 248.220000 1477.520000 ;
+ RECT 242.990000 1477.040000 243.990000 1477.520000 ;
+ RECT 247.120000 1471.600000 248.220000 1472.080000 ;
+ RECT 247.120000 1466.160000 248.220000 1466.640000 ;
+ RECT 242.990000 1471.600000 243.990000 1472.080000 ;
+ RECT 242.990000 1466.160000 243.990000 1466.640000 ;
+ RECT 247.120000 1460.720000 248.220000 1461.200000 ;
+ RECT 242.990000 1460.720000 243.990000 1461.200000 ;
+ RECT 247.120000 1455.280000 248.220000 1455.760000 ;
+ RECT 242.990000 1455.280000 243.990000 1455.760000 ;
+ RECT 247.120000 1449.840000 248.220000 1450.320000 ;
+ RECT 242.990000 1449.840000 243.990000 1450.320000 ;
+ RECT 427.120000 1444.400000 428.220000 1444.880000 ;
+ RECT 427.120000 1438.960000 428.220000 1439.440000 ;
+ RECT 436.430000 1444.400000 437.430000 1444.880000 ;
+ RECT 436.430000 1438.960000 437.430000 1439.440000 ;
+ RECT 436.430000 1422.640000 437.430000 1423.120000 ;
+ RECT 436.430000 1428.080000 437.430000 1428.560000 ;
+ RECT 436.430000 1433.520000 437.430000 1434.000000 ;
+ RECT 427.120000 1433.520000 428.220000 1434.000000 ;
+ RECT 427.120000 1428.080000 428.220000 1428.560000 ;
+ RECT 427.120000 1422.640000 428.220000 1423.120000 ;
+ RECT 427.120000 1411.760000 428.220000 1412.240000 ;
+ RECT 427.120000 1417.200000 428.220000 1417.680000 ;
+ RECT 436.430000 1417.200000 437.430000 1417.680000 ;
+ RECT 436.430000 1411.760000 437.430000 1412.240000 ;
+ RECT 436.430000 1400.880000 437.430000 1401.360000 ;
+ RECT 436.430000 1406.320000 437.430000 1406.800000 ;
+ RECT 427.120000 1400.880000 428.220000 1401.360000 ;
+ RECT 427.120000 1406.320000 428.220000 1406.800000 ;
+ RECT 382.120000 1444.400000 383.220000 1444.880000 ;
+ RECT 382.120000 1438.960000 383.220000 1439.440000 ;
+ RECT 382.120000 1433.520000 383.220000 1434.000000 ;
+ RECT 382.120000 1428.080000 383.220000 1428.560000 ;
+ RECT 382.120000 1422.640000 383.220000 1423.120000 ;
+ RECT 382.120000 1400.880000 383.220000 1401.360000 ;
+ RECT 382.120000 1406.320000 383.220000 1406.800000 ;
+ RECT 382.120000 1411.760000 383.220000 1412.240000 ;
+ RECT 382.120000 1417.200000 383.220000 1417.680000 ;
+ RECT 427.120000 1395.440000 428.220000 1395.920000 ;
+ RECT 427.120000 1390.000000 428.220000 1390.480000 ;
+ RECT 436.430000 1395.440000 437.430000 1395.920000 ;
+ RECT 436.430000 1390.000000 437.430000 1390.480000 ;
+ RECT 427.120000 1379.120000 428.220000 1379.600000 ;
+ RECT 427.120000 1373.680000 428.220000 1374.160000 ;
+ RECT 436.430000 1379.120000 437.430000 1379.600000 ;
+ RECT 436.430000 1373.680000 437.430000 1374.160000 ;
+ RECT 427.120000 1384.560000 428.220000 1385.040000 ;
+ RECT 436.430000 1384.560000 437.430000 1385.040000 ;
+ RECT 436.430000 1362.800000 437.430000 1363.280000 ;
+ RECT 436.430000 1368.240000 437.430000 1368.720000 ;
+ RECT 427.120000 1368.240000 428.220000 1368.720000 ;
+ RECT 427.120000 1362.800000 428.220000 1363.280000 ;
+ RECT 427.120000 1357.360000 428.220000 1357.840000 ;
+ RECT 427.120000 1351.920000 428.220000 1352.400000 ;
+ RECT 436.430000 1357.360000 437.430000 1357.840000 ;
+ RECT 436.430000 1351.920000 437.430000 1352.400000 ;
+ RECT 382.120000 1395.440000 383.220000 1395.920000 ;
+ RECT 382.120000 1390.000000 383.220000 1390.480000 ;
+ RECT 382.120000 1384.560000 383.220000 1385.040000 ;
+ RECT 382.120000 1379.120000 383.220000 1379.600000 ;
+ RECT 382.120000 1373.680000 383.220000 1374.160000 ;
+ RECT 382.120000 1368.240000 383.220000 1368.720000 ;
+ RECT 382.120000 1362.800000 383.220000 1363.280000 ;
+ RECT 382.120000 1357.360000 383.220000 1357.840000 ;
+ RECT 382.120000 1351.920000 383.220000 1352.400000 ;
+ RECT 337.120000 1444.400000 338.220000 1444.880000 ;
+ RECT 337.120000 1438.960000 338.220000 1439.440000 ;
+ RECT 337.120000 1433.520000 338.220000 1434.000000 ;
+ RECT 337.120000 1428.080000 338.220000 1428.560000 ;
+ RECT 337.120000 1422.640000 338.220000 1423.120000 ;
+ RECT 292.120000 1444.400000 293.220000 1444.880000 ;
+ RECT 292.120000 1438.960000 293.220000 1439.440000 ;
+ RECT 292.120000 1433.520000 293.220000 1434.000000 ;
+ RECT 292.120000 1428.080000 293.220000 1428.560000 ;
+ RECT 292.120000 1422.640000 293.220000 1423.120000 ;
+ RECT 337.120000 1417.200000 338.220000 1417.680000 ;
+ RECT 337.120000 1411.760000 338.220000 1412.240000 ;
+ RECT 337.120000 1406.320000 338.220000 1406.800000 ;
+ RECT 337.120000 1400.880000 338.220000 1401.360000 ;
+ RECT 292.120000 1411.760000 293.220000 1412.240000 ;
+ RECT 292.120000 1406.320000 293.220000 1406.800000 ;
+ RECT 292.120000 1400.880000 293.220000 1401.360000 ;
+ RECT 292.120000 1417.200000 293.220000 1417.680000 ;
+ RECT 247.120000 1444.400000 248.220000 1444.880000 ;
+ RECT 242.990000 1444.400000 243.990000 1444.880000 ;
+ RECT 247.120000 1438.960000 248.220000 1439.440000 ;
+ RECT 242.990000 1438.960000 243.990000 1439.440000 ;
+ RECT 247.120000 1433.520000 248.220000 1434.000000 ;
+ RECT 242.990000 1433.520000 243.990000 1434.000000 ;
+ RECT 247.120000 1422.640000 248.220000 1423.120000 ;
+ RECT 242.990000 1422.640000 243.990000 1423.120000 ;
+ RECT 242.990000 1428.080000 243.990000 1428.560000 ;
+ RECT 247.120000 1428.080000 248.220000 1428.560000 ;
+ RECT 247.120000 1417.200000 248.220000 1417.680000 ;
+ RECT 242.990000 1417.200000 243.990000 1417.680000 ;
+ RECT 247.120000 1411.760000 248.220000 1412.240000 ;
+ RECT 242.990000 1411.760000 243.990000 1412.240000 ;
+ RECT 247.120000 1406.320000 248.220000 1406.800000 ;
+ RECT 242.990000 1406.320000 243.990000 1406.800000 ;
+ RECT 247.120000 1400.880000 248.220000 1401.360000 ;
+ RECT 242.990000 1400.880000 243.990000 1401.360000 ;
+ RECT 337.120000 1395.440000 338.220000 1395.920000 ;
+ RECT 337.120000 1390.000000 338.220000 1390.480000 ;
+ RECT 337.120000 1384.560000 338.220000 1385.040000 ;
+ RECT 337.120000 1379.120000 338.220000 1379.600000 ;
+ RECT 337.120000 1373.680000 338.220000 1374.160000 ;
+ RECT 292.120000 1395.440000 293.220000 1395.920000 ;
+ RECT 292.120000 1390.000000 293.220000 1390.480000 ;
+ RECT 292.120000 1384.560000 293.220000 1385.040000 ;
+ RECT 292.120000 1379.120000 293.220000 1379.600000 ;
+ RECT 292.120000 1373.680000 293.220000 1374.160000 ;
+ RECT 337.120000 1351.920000 338.220000 1352.400000 ;
+ RECT 337.120000 1357.360000 338.220000 1357.840000 ;
+ RECT 337.120000 1362.800000 338.220000 1363.280000 ;
+ RECT 337.120000 1368.240000 338.220000 1368.720000 ;
+ RECT 292.120000 1351.920000 293.220000 1352.400000 ;
+ RECT 292.120000 1357.360000 293.220000 1357.840000 ;
+ RECT 292.120000 1362.800000 293.220000 1363.280000 ;
+ RECT 292.120000 1368.240000 293.220000 1368.720000 ;
+ RECT 247.120000 1395.440000 248.220000 1395.920000 ;
+ RECT 242.990000 1395.440000 243.990000 1395.920000 ;
+ RECT 247.120000 1390.000000 248.220000 1390.480000 ;
+ RECT 242.990000 1390.000000 243.990000 1390.480000 ;
+ RECT 247.120000 1379.120000 248.220000 1379.600000 ;
+ RECT 242.990000 1379.120000 243.990000 1379.600000 ;
+ RECT 247.120000 1373.680000 248.220000 1374.160000 ;
+ RECT 242.990000 1373.680000 243.990000 1374.160000 ;
+ RECT 247.120000 1384.560000 248.220000 1385.040000 ;
+ RECT 242.990000 1384.560000 243.990000 1385.040000 ;
+ RECT 247.120000 1368.240000 248.220000 1368.720000 ;
+ RECT 242.990000 1368.240000 243.990000 1368.720000 ;
+ RECT 247.120000 1362.800000 248.220000 1363.280000 ;
+ RECT 242.990000 1362.800000 243.990000 1363.280000 ;
+ RECT 247.120000 1357.360000 248.220000 1357.840000 ;
+ RECT 247.120000 1351.920000 248.220000 1352.400000 ;
+ RECT 242.990000 1357.360000 243.990000 1357.840000 ;
+ RECT 242.990000 1351.920000 243.990000 1352.400000 ;
+ RECT 240.160000 1542.280000 440.260000 1543.280000 ;
+ RECT 240.160000 1349.910000 440.260000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 1347.060000 243.990000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 1546.320000 243.990000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 1347.060000 437.430000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 1546.320000 437.430000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1349.910000 241.160000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1349.910000 440.260000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1542.280000 241.160000 1543.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1542.280000 440.260000 1543.280000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 1149.650000 428.220000 1343.020000 ;
+ RECT 382.120000 1149.650000 383.220000 1343.020000 ;
+ RECT 436.430000 1146.800000 437.430000 1347.060000 ;
+ RECT 337.120000 1149.650000 338.220000 1343.020000 ;
+ RECT 292.120000 1149.650000 293.220000 1343.020000 ;
+ RECT 247.120000 1149.650000 248.220000 1343.020000 ;
+ RECT 242.990000 1146.800000 243.990000 1347.060000 ;
+ LAYER met3 ;
+ RECT 427.120000 1336.620000 428.220000 1337.100000 ;
+ RECT 436.430000 1336.620000 437.430000 1337.100000 ;
+ RECT 436.430000 1325.740000 437.430000 1326.220000 ;
+ RECT 436.430000 1331.180000 437.430000 1331.660000 ;
+ RECT 427.120000 1331.180000 428.220000 1331.660000 ;
+ RECT 427.120000 1325.740000 428.220000 1326.220000 ;
+ RECT 427.120000 1320.300000 428.220000 1320.780000 ;
+ RECT 427.120000 1314.860000 428.220000 1315.340000 ;
+ RECT 436.430000 1320.300000 437.430000 1320.780000 ;
+ RECT 436.430000 1314.860000 437.430000 1315.340000 ;
+ RECT 427.120000 1298.540000 428.220000 1299.020000 ;
+ RECT 427.120000 1303.980000 428.220000 1304.460000 ;
+ RECT 436.430000 1303.980000 437.430000 1304.460000 ;
+ RECT 436.430000 1298.540000 437.430000 1299.020000 ;
+ RECT 427.120000 1309.420000 428.220000 1309.900000 ;
+ RECT 436.430000 1309.420000 437.430000 1309.900000 ;
+ RECT 382.120000 1336.620000 383.220000 1337.100000 ;
+ RECT 382.120000 1331.180000 383.220000 1331.660000 ;
+ RECT 382.120000 1325.740000 383.220000 1326.220000 ;
+ RECT 382.120000 1320.300000 383.220000 1320.780000 ;
+ RECT 382.120000 1298.540000 383.220000 1299.020000 ;
+ RECT 382.120000 1303.980000 383.220000 1304.460000 ;
+ RECT 382.120000 1309.420000 383.220000 1309.900000 ;
+ RECT 382.120000 1314.860000 383.220000 1315.340000 ;
+ RECT 436.430000 1287.660000 437.430000 1288.140000 ;
+ RECT 436.430000 1293.100000 437.430000 1293.580000 ;
+ RECT 427.120000 1293.100000 428.220000 1293.580000 ;
+ RECT 427.120000 1287.660000 428.220000 1288.140000 ;
+ RECT 427.120000 1282.220000 428.220000 1282.700000 ;
+ RECT 427.120000 1276.780000 428.220000 1277.260000 ;
+ RECT 436.430000 1282.220000 437.430000 1282.700000 ;
+ RECT 436.430000 1276.780000 437.430000 1277.260000 ;
+ RECT 436.430000 1260.460000 437.430000 1260.940000 ;
+ RECT 436.430000 1265.900000 437.430000 1266.380000 ;
+ RECT 436.430000 1271.340000 437.430000 1271.820000 ;
+ RECT 427.120000 1265.900000 428.220000 1266.380000 ;
+ RECT 427.120000 1260.460000 428.220000 1260.940000 ;
+ RECT 427.120000 1271.340000 428.220000 1271.820000 ;
+ RECT 427.120000 1255.020000 428.220000 1255.500000 ;
+ RECT 427.120000 1249.580000 428.220000 1250.060000 ;
+ RECT 436.430000 1255.020000 437.430000 1255.500000 ;
+ RECT 436.430000 1249.580000 437.430000 1250.060000 ;
+ RECT 382.120000 1293.100000 383.220000 1293.580000 ;
+ RECT 382.120000 1287.660000 383.220000 1288.140000 ;
+ RECT 382.120000 1282.220000 383.220000 1282.700000 ;
+ RECT 382.120000 1276.780000 383.220000 1277.260000 ;
+ RECT 382.120000 1265.900000 383.220000 1266.380000 ;
+ RECT 382.120000 1260.460000 383.220000 1260.940000 ;
+ RECT 382.120000 1255.020000 383.220000 1255.500000 ;
+ RECT 382.120000 1249.580000 383.220000 1250.060000 ;
+ RECT 382.120000 1271.340000 383.220000 1271.820000 ;
+ RECT 337.120000 1336.620000 338.220000 1337.100000 ;
+ RECT 337.120000 1331.180000 338.220000 1331.660000 ;
+ RECT 337.120000 1325.740000 338.220000 1326.220000 ;
+ RECT 292.120000 1336.620000 293.220000 1337.100000 ;
+ RECT 292.120000 1331.180000 293.220000 1331.660000 ;
+ RECT 292.120000 1325.740000 293.220000 1326.220000 ;
+ RECT 337.120000 1309.420000 338.220000 1309.900000 ;
+ RECT 337.120000 1303.980000 338.220000 1304.460000 ;
+ RECT 337.120000 1298.540000 338.220000 1299.020000 ;
+ RECT 337.120000 1314.860000 338.220000 1315.340000 ;
+ RECT 337.120000 1320.300000 338.220000 1320.780000 ;
+ RECT 292.120000 1320.300000 293.220000 1320.780000 ;
+ RECT 292.120000 1309.420000 293.220000 1309.900000 ;
+ RECT 292.120000 1303.980000 293.220000 1304.460000 ;
+ RECT 292.120000 1298.540000 293.220000 1299.020000 ;
+ RECT 292.120000 1314.860000 293.220000 1315.340000 ;
+ RECT 247.120000 1336.620000 248.220000 1337.100000 ;
+ RECT 242.990000 1336.620000 243.990000 1337.100000 ;
+ RECT 242.990000 1331.180000 243.990000 1331.660000 ;
+ RECT 247.120000 1331.180000 248.220000 1331.660000 ;
+ RECT 247.120000 1325.740000 248.220000 1326.220000 ;
+ RECT 242.990000 1325.740000 243.990000 1326.220000 ;
+ RECT 247.120000 1320.300000 248.220000 1320.780000 ;
+ RECT 242.990000 1320.300000 243.990000 1320.780000 ;
+ RECT 247.120000 1314.860000 248.220000 1315.340000 ;
+ RECT 242.990000 1314.860000 243.990000 1315.340000 ;
+ RECT 247.120000 1303.980000 248.220000 1304.460000 ;
+ RECT 242.990000 1303.980000 243.990000 1304.460000 ;
+ RECT 247.120000 1298.540000 248.220000 1299.020000 ;
+ RECT 242.990000 1298.540000 243.990000 1299.020000 ;
+ RECT 247.120000 1309.420000 248.220000 1309.900000 ;
+ RECT 242.990000 1309.420000 243.990000 1309.900000 ;
+ RECT 337.120000 1293.100000 338.220000 1293.580000 ;
+ RECT 337.120000 1287.660000 338.220000 1288.140000 ;
+ RECT 337.120000 1282.220000 338.220000 1282.700000 ;
+ RECT 337.120000 1276.780000 338.220000 1277.260000 ;
+ RECT 292.120000 1293.100000 293.220000 1293.580000 ;
+ RECT 292.120000 1287.660000 293.220000 1288.140000 ;
+ RECT 292.120000 1282.220000 293.220000 1282.700000 ;
+ RECT 292.120000 1276.780000 293.220000 1277.260000 ;
+ RECT 337.120000 1265.900000 338.220000 1266.380000 ;
+ RECT 337.120000 1249.580000 338.220000 1250.060000 ;
+ RECT 337.120000 1255.020000 338.220000 1255.500000 ;
+ RECT 337.120000 1260.460000 338.220000 1260.940000 ;
+ RECT 337.120000 1271.340000 338.220000 1271.820000 ;
+ RECT 292.120000 1249.580000 293.220000 1250.060000 ;
+ RECT 292.120000 1255.020000 293.220000 1255.500000 ;
+ RECT 292.120000 1260.460000 293.220000 1260.940000 ;
+ RECT 292.120000 1265.900000 293.220000 1266.380000 ;
+ RECT 292.120000 1271.340000 293.220000 1271.820000 ;
+ RECT 247.120000 1293.100000 248.220000 1293.580000 ;
+ RECT 242.990000 1293.100000 243.990000 1293.580000 ;
+ RECT 247.120000 1287.660000 248.220000 1288.140000 ;
+ RECT 242.990000 1287.660000 243.990000 1288.140000 ;
+ RECT 247.120000 1282.220000 248.220000 1282.700000 ;
+ RECT 242.990000 1282.220000 243.990000 1282.700000 ;
+ RECT 247.120000 1276.780000 248.220000 1277.260000 ;
+ RECT 242.990000 1276.780000 243.990000 1277.260000 ;
+ RECT 247.120000 1271.340000 248.220000 1271.820000 ;
+ RECT 247.120000 1265.900000 248.220000 1266.380000 ;
+ RECT 242.990000 1271.340000 243.990000 1271.820000 ;
+ RECT 242.990000 1265.900000 243.990000 1266.380000 ;
+ RECT 247.120000 1260.460000 248.220000 1260.940000 ;
+ RECT 242.990000 1260.460000 243.990000 1260.940000 ;
+ RECT 247.120000 1255.020000 248.220000 1255.500000 ;
+ RECT 242.990000 1255.020000 243.990000 1255.500000 ;
+ RECT 247.120000 1249.580000 248.220000 1250.060000 ;
+ RECT 242.990000 1249.580000 243.990000 1250.060000 ;
+ RECT 427.120000 1244.140000 428.220000 1244.620000 ;
+ RECT 427.120000 1238.700000 428.220000 1239.180000 ;
+ RECT 436.430000 1244.140000 437.430000 1244.620000 ;
+ RECT 436.430000 1238.700000 437.430000 1239.180000 ;
+ RECT 436.430000 1222.380000 437.430000 1222.860000 ;
+ RECT 436.430000 1227.820000 437.430000 1228.300000 ;
+ RECT 436.430000 1233.260000 437.430000 1233.740000 ;
+ RECT 427.120000 1233.260000 428.220000 1233.740000 ;
+ RECT 427.120000 1227.820000 428.220000 1228.300000 ;
+ RECT 427.120000 1222.380000 428.220000 1222.860000 ;
+ RECT 427.120000 1211.500000 428.220000 1211.980000 ;
+ RECT 427.120000 1216.940000 428.220000 1217.420000 ;
+ RECT 436.430000 1216.940000 437.430000 1217.420000 ;
+ RECT 436.430000 1211.500000 437.430000 1211.980000 ;
+ RECT 436.430000 1200.620000 437.430000 1201.100000 ;
+ RECT 436.430000 1206.060000 437.430000 1206.540000 ;
+ RECT 427.120000 1200.620000 428.220000 1201.100000 ;
+ RECT 427.120000 1206.060000 428.220000 1206.540000 ;
+ RECT 382.120000 1244.140000 383.220000 1244.620000 ;
+ RECT 382.120000 1238.700000 383.220000 1239.180000 ;
+ RECT 382.120000 1233.260000 383.220000 1233.740000 ;
+ RECT 382.120000 1227.820000 383.220000 1228.300000 ;
+ RECT 382.120000 1222.380000 383.220000 1222.860000 ;
+ RECT 382.120000 1200.620000 383.220000 1201.100000 ;
+ RECT 382.120000 1206.060000 383.220000 1206.540000 ;
+ RECT 382.120000 1211.500000 383.220000 1211.980000 ;
+ RECT 382.120000 1216.940000 383.220000 1217.420000 ;
+ RECT 427.120000 1195.180000 428.220000 1195.660000 ;
+ RECT 427.120000 1189.740000 428.220000 1190.220000 ;
+ RECT 436.430000 1195.180000 437.430000 1195.660000 ;
+ RECT 436.430000 1189.740000 437.430000 1190.220000 ;
+ RECT 427.120000 1178.860000 428.220000 1179.340000 ;
+ RECT 427.120000 1173.420000 428.220000 1173.900000 ;
+ RECT 436.430000 1178.860000 437.430000 1179.340000 ;
+ RECT 436.430000 1173.420000 437.430000 1173.900000 ;
+ RECT 427.120000 1184.300000 428.220000 1184.780000 ;
+ RECT 436.430000 1184.300000 437.430000 1184.780000 ;
+ RECT 436.430000 1162.540000 437.430000 1163.020000 ;
+ RECT 436.430000 1167.980000 437.430000 1168.460000 ;
+ RECT 427.120000 1167.980000 428.220000 1168.460000 ;
+ RECT 427.120000 1162.540000 428.220000 1163.020000 ;
+ RECT 427.120000 1157.100000 428.220000 1157.580000 ;
+ RECT 427.120000 1151.660000 428.220000 1152.140000 ;
+ RECT 436.430000 1157.100000 437.430000 1157.580000 ;
+ RECT 436.430000 1151.660000 437.430000 1152.140000 ;
+ RECT 382.120000 1195.180000 383.220000 1195.660000 ;
+ RECT 382.120000 1189.740000 383.220000 1190.220000 ;
+ RECT 382.120000 1184.300000 383.220000 1184.780000 ;
+ RECT 382.120000 1178.860000 383.220000 1179.340000 ;
+ RECT 382.120000 1173.420000 383.220000 1173.900000 ;
+ RECT 382.120000 1167.980000 383.220000 1168.460000 ;
+ RECT 382.120000 1162.540000 383.220000 1163.020000 ;
+ RECT 382.120000 1157.100000 383.220000 1157.580000 ;
+ RECT 382.120000 1151.660000 383.220000 1152.140000 ;
+ RECT 337.120000 1244.140000 338.220000 1244.620000 ;
+ RECT 337.120000 1238.700000 338.220000 1239.180000 ;
+ RECT 337.120000 1233.260000 338.220000 1233.740000 ;
+ RECT 337.120000 1227.820000 338.220000 1228.300000 ;
+ RECT 337.120000 1222.380000 338.220000 1222.860000 ;
+ RECT 292.120000 1244.140000 293.220000 1244.620000 ;
+ RECT 292.120000 1238.700000 293.220000 1239.180000 ;
+ RECT 292.120000 1233.260000 293.220000 1233.740000 ;
+ RECT 292.120000 1227.820000 293.220000 1228.300000 ;
+ RECT 292.120000 1222.380000 293.220000 1222.860000 ;
+ RECT 337.120000 1216.940000 338.220000 1217.420000 ;
+ RECT 337.120000 1211.500000 338.220000 1211.980000 ;
+ RECT 337.120000 1206.060000 338.220000 1206.540000 ;
+ RECT 337.120000 1200.620000 338.220000 1201.100000 ;
+ RECT 292.120000 1211.500000 293.220000 1211.980000 ;
+ RECT 292.120000 1206.060000 293.220000 1206.540000 ;
+ RECT 292.120000 1200.620000 293.220000 1201.100000 ;
+ RECT 292.120000 1216.940000 293.220000 1217.420000 ;
+ RECT 247.120000 1244.140000 248.220000 1244.620000 ;
+ RECT 242.990000 1244.140000 243.990000 1244.620000 ;
+ RECT 247.120000 1238.700000 248.220000 1239.180000 ;
+ RECT 242.990000 1238.700000 243.990000 1239.180000 ;
+ RECT 247.120000 1233.260000 248.220000 1233.740000 ;
+ RECT 242.990000 1233.260000 243.990000 1233.740000 ;
+ RECT 247.120000 1222.380000 248.220000 1222.860000 ;
+ RECT 242.990000 1222.380000 243.990000 1222.860000 ;
+ RECT 242.990000 1227.820000 243.990000 1228.300000 ;
+ RECT 247.120000 1227.820000 248.220000 1228.300000 ;
+ RECT 247.120000 1216.940000 248.220000 1217.420000 ;
+ RECT 242.990000 1216.940000 243.990000 1217.420000 ;
+ RECT 247.120000 1211.500000 248.220000 1211.980000 ;
+ RECT 242.990000 1211.500000 243.990000 1211.980000 ;
+ RECT 247.120000 1206.060000 248.220000 1206.540000 ;
+ RECT 242.990000 1206.060000 243.990000 1206.540000 ;
+ RECT 247.120000 1200.620000 248.220000 1201.100000 ;
+ RECT 242.990000 1200.620000 243.990000 1201.100000 ;
+ RECT 337.120000 1195.180000 338.220000 1195.660000 ;
+ RECT 337.120000 1189.740000 338.220000 1190.220000 ;
+ RECT 337.120000 1184.300000 338.220000 1184.780000 ;
+ RECT 337.120000 1178.860000 338.220000 1179.340000 ;
+ RECT 337.120000 1173.420000 338.220000 1173.900000 ;
+ RECT 292.120000 1195.180000 293.220000 1195.660000 ;
+ RECT 292.120000 1189.740000 293.220000 1190.220000 ;
+ RECT 292.120000 1184.300000 293.220000 1184.780000 ;
+ RECT 292.120000 1178.860000 293.220000 1179.340000 ;
+ RECT 292.120000 1173.420000 293.220000 1173.900000 ;
+ RECT 337.120000 1151.660000 338.220000 1152.140000 ;
+ RECT 337.120000 1157.100000 338.220000 1157.580000 ;
+ RECT 337.120000 1162.540000 338.220000 1163.020000 ;
+ RECT 337.120000 1167.980000 338.220000 1168.460000 ;
+ RECT 292.120000 1151.660000 293.220000 1152.140000 ;
+ RECT 292.120000 1157.100000 293.220000 1157.580000 ;
+ RECT 292.120000 1162.540000 293.220000 1163.020000 ;
+ RECT 292.120000 1167.980000 293.220000 1168.460000 ;
+ RECT 247.120000 1195.180000 248.220000 1195.660000 ;
+ RECT 242.990000 1195.180000 243.990000 1195.660000 ;
+ RECT 247.120000 1189.740000 248.220000 1190.220000 ;
+ RECT 242.990000 1189.740000 243.990000 1190.220000 ;
+ RECT 247.120000 1178.860000 248.220000 1179.340000 ;
+ RECT 242.990000 1178.860000 243.990000 1179.340000 ;
+ RECT 247.120000 1173.420000 248.220000 1173.900000 ;
+ RECT 242.990000 1173.420000 243.990000 1173.900000 ;
+ RECT 247.120000 1184.300000 248.220000 1184.780000 ;
+ RECT 242.990000 1184.300000 243.990000 1184.780000 ;
+ RECT 247.120000 1167.980000 248.220000 1168.460000 ;
+ RECT 242.990000 1167.980000 243.990000 1168.460000 ;
+ RECT 247.120000 1162.540000 248.220000 1163.020000 ;
+ RECT 242.990000 1162.540000 243.990000 1163.020000 ;
+ RECT 247.120000 1157.100000 248.220000 1157.580000 ;
+ RECT 247.120000 1151.660000 248.220000 1152.140000 ;
+ RECT 242.990000 1157.100000 243.990000 1157.580000 ;
+ RECT 242.990000 1151.660000 243.990000 1152.140000 ;
+ RECT 240.160000 1342.020000 440.260000 1343.020000 ;
+ RECT 240.160000 1149.650000 440.260000 1150.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 1146.800000 243.990000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 1346.060000 243.990000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 1146.800000 437.430000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 1346.060000 437.430000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1149.650000 241.160000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1149.650000 440.260000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1342.020000 241.160000 1343.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1342.020000 440.260000 1343.020000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 949.390000 428.220000 1142.760000 ;
+ RECT 382.120000 949.390000 383.220000 1142.760000 ;
+ RECT 436.430000 946.540000 437.430000 1146.800000 ;
+ RECT 337.120000 949.390000 338.220000 1142.760000 ;
+ RECT 292.120000 949.390000 293.220000 1142.760000 ;
+ RECT 247.120000 949.390000 248.220000 1142.760000 ;
+ RECT 242.990000 946.540000 243.990000 1146.800000 ;
+ LAYER met3 ;
+ RECT 427.120000 1136.360000 428.220000 1136.840000 ;
+ RECT 436.430000 1136.360000 437.430000 1136.840000 ;
+ RECT 436.430000 1125.480000 437.430000 1125.960000 ;
+ RECT 436.430000 1130.920000 437.430000 1131.400000 ;
+ RECT 427.120000 1130.920000 428.220000 1131.400000 ;
+ RECT 427.120000 1125.480000 428.220000 1125.960000 ;
+ RECT 427.120000 1120.040000 428.220000 1120.520000 ;
+ RECT 427.120000 1114.600000 428.220000 1115.080000 ;
+ RECT 436.430000 1120.040000 437.430000 1120.520000 ;
+ RECT 436.430000 1114.600000 437.430000 1115.080000 ;
+ RECT 427.120000 1098.280000 428.220000 1098.760000 ;
+ RECT 427.120000 1103.720000 428.220000 1104.200000 ;
+ RECT 436.430000 1103.720000 437.430000 1104.200000 ;
+ RECT 436.430000 1098.280000 437.430000 1098.760000 ;
+ RECT 427.120000 1109.160000 428.220000 1109.640000 ;
+ RECT 436.430000 1109.160000 437.430000 1109.640000 ;
+ RECT 382.120000 1136.360000 383.220000 1136.840000 ;
+ RECT 382.120000 1130.920000 383.220000 1131.400000 ;
+ RECT 382.120000 1125.480000 383.220000 1125.960000 ;
+ RECT 382.120000 1120.040000 383.220000 1120.520000 ;
+ RECT 382.120000 1098.280000 383.220000 1098.760000 ;
+ RECT 382.120000 1103.720000 383.220000 1104.200000 ;
+ RECT 382.120000 1109.160000 383.220000 1109.640000 ;
+ RECT 382.120000 1114.600000 383.220000 1115.080000 ;
+ RECT 436.430000 1087.400000 437.430000 1087.880000 ;
+ RECT 436.430000 1092.840000 437.430000 1093.320000 ;
+ RECT 427.120000 1092.840000 428.220000 1093.320000 ;
+ RECT 427.120000 1087.400000 428.220000 1087.880000 ;
+ RECT 427.120000 1081.960000 428.220000 1082.440000 ;
+ RECT 427.120000 1076.520000 428.220000 1077.000000 ;
+ RECT 436.430000 1081.960000 437.430000 1082.440000 ;
+ RECT 436.430000 1076.520000 437.430000 1077.000000 ;
+ RECT 436.430000 1060.200000 437.430000 1060.680000 ;
+ RECT 436.430000 1065.640000 437.430000 1066.120000 ;
+ RECT 436.430000 1071.080000 437.430000 1071.560000 ;
+ RECT 427.120000 1065.640000 428.220000 1066.120000 ;
+ RECT 427.120000 1060.200000 428.220000 1060.680000 ;
+ RECT 427.120000 1071.080000 428.220000 1071.560000 ;
+ RECT 427.120000 1054.760000 428.220000 1055.240000 ;
+ RECT 427.120000 1049.320000 428.220000 1049.800000 ;
+ RECT 436.430000 1054.760000 437.430000 1055.240000 ;
+ RECT 436.430000 1049.320000 437.430000 1049.800000 ;
+ RECT 382.120000 1092.840000 383.220000 1093.320000 ;
+ RECT 382.120000 1087.400000 383.220000 1087.880000 ;
+ RECT 382.120000 1081.960000 383.220000 1082.440000 ;
+ RECT 382.120000 1076.520000 383.220000 1077.000000 ;
+ RECT 382.120000 1065.640000 383.220000 1066.120000 ;
+ RECT 382.120000 1060.200000 383.220000 1060.680000 ;
+ RECT 382.120000 1054.760000 383.220000 1055.240000 ;
+ RECT 382.120000 1049.320000 383.220000 1049.800000 ;
+ RECT 382.120000 1071.080000 383.220000 1071.560000 ;
+ RECT 337.120000 1136.360000 338.220000 1136.840000 ;
+ RECT 337.120000 1130.920000 338.220000 1131.400000 ;
+ RECT 337.120000 1125.480000 338.220000 1125.960000 ;
+ RECT 292.120000 1136.360000 293.220000 1136.840000 ;
+ RECT 292.120000 1130.920000 293.220000 1131.400000 ;
+ RECT 292.120000 1125.480000 293.220000 1125.960000 ;
+ RECT 337.120000 1109.160000 338.220000 1109.640000 ;
+ RECT 337.120000 1103.720000 338.220000 1104.200000 ;
+ RECT 337.120000 1098.280000 338.220000 1098.760000 ;
+ RECT 337.120000 1114.600000 338.220000 1115.080000 ;
+ RECT 337.120000 1120.040000 338.220000 1120.520000 ;
+ RECT 292.120000 1120.040000 293.220000 1120.520000 ;
+ RECT 292.120000 1109.160000 293.220000 1109.640000 ;
+ RECT 292.120000 1103.720000 293.220000 1104.200000 ;
+ RECT 292.120000 1098.280000 293.220000 1098.760000 ;
+ RECT 292.120000 1114.600000 293.220000 1115.080000 ;
+ RECT 247.120000 1136.360000 248.220000 1136.840000 ;
+ RECT 242.990000 1136.360000 243.990000 1136.840000 ;
+ RECT 242.990000 1130.920000 243.990000 1131.400000 ;
+ RECT 247.120000 1130.920000 248.220000 1131.400000 ;
+ RECT 247.120000 1125.480000 248.220000 1125.960000 ;
+ RECT 242.990000 1125.480000 243.990000 1125.960000 ;
+ RECT 247.120000 1120.040000 248.220000 1120.520000 ;
+ RECT 242.990000 1120.040000 243.990000 1120.520000 ;
+ RECT 247.120000 1114.600000 248.220000 1115.080000 ;
+ RECT 242.990000 1114.600000 243.990000 1115.080000 ;
+ RECT 247.120000 1103.720000 248.220000 1104.200000 ;
+ RECT 242.990000 1103.720000 243.990000 1104.200000 ;
+ RECT 247.120000 1098.280000 248.220000 1098.760000 ;
+ RECT 242.990000 1098.280000 243.990000 1098.760000 ;
+ RECT 247.120000 1109.160000 248.220000 1109.640000 ;
+ RECT 242.990000 1109.160000 243.990000 1109.640000 ;
+ RECT 337.120000 1092.840000 338.220000 1093.320000 ;
+ RECT 337.120000 1087.400000 338.220000 1087.880000 ;
+ RECT 337.120000 1081.960000 338.220000 1082.440000 ;
+ RECT 337.120000 1076.520000 338.220000 1077.000000 ;
+ RECT 292.120000 1092.840000 293.220000 1093.320000 ;
+ RECT 292.120000 1087.400000 293.220000 1087.880000 ;
+ RECT 292.120000 1081.960000 293.220000 1082.440000 ;
+ RECT 292.120000 1076.520000 293.220000 1077.000000 ;
+ RECT 337.120000 1065.640000 338.220000 1066.120000 ;
+ RECT 337.120000 1049.320000 338.220000 1049.800000 ;
+ RECT 337.120000 1054.760000 338.220000 1055.240000 ;
+ RECT 337.120000 1060.200000 338.220000 1060.680000 ;
+ RECT 337.120000 1071.080000 338.220000 1071.560000 ;
+ RECT 292.120000 1049.320000 293.220000 1049.800000 ;
+ RECT 292.120000 1054.760000 293.220000 1055.240000 ;
+ RECT 292.120000 1060.200000 293.220000 1060.680000 ;
+ RECT 292.120000 1065.640000 293.220000 1066.120000 ;
+ RECT 292.120000 1071.080000 293.220000 1071.560000 ;
+ RECT 247.120000 1092.840000 248.220000 1093.320000 ;
+ RECT 242.990000 1092.840000 243.990000 1093.320000 ;
+ RECT 247.120000 1087.400000 248.220000 1087.880000 ;
+ RECT 242.990000 1087.400000 243.990000 1087.880000 ;
+ RECT 247.120000 1081.960000 248.220000 1082.440000 ;
+ RECT 242.990000 1081.960000 243.990000 1082.440000 ;
+ RECT 247.120000 1076.520000 248.220000 1077.000000 ;
+ RECT 242.990000 1076.520000 243.990000 1077.000000 ;
+ RECT 247.120000 1071.080000 248.220000 1071.560000 ;
+ RECT 247.120000 1065.640000 248.220000 1066.120000 ;
+ RECT 242.990000 1071.080000 243.990000 1071.560000 ;
+ RECT 242.990000 1065.640000 243.990000 1066.120000 ;
+ RECT 247.120000 1060.200000 248.220000 1060.680000 ;
+ RECT 242.990000 1060.200000 243.990000 1060.680000 ;
+ RECT 247.120000 1054.760000 248.220000 1055.240000 ;
+ RECT 242.990000 1054.760000 243.990000 1055.240000 ;
+ RECT 247.120000 1049.320000 248.220000 1049.800000 ;
+ RECT 242.990000 1049.320000 243.990000 1049.800000 ;
+ RECT 427.120000 1043.880000 428.220000 1044.360000 ;
+ RECT 427.120000 1038.440000 428.220000 1038.920000 ;
+ RECT 436.430000 1043.880000 437.430000 1044.360000 ;
+ RECT 436.430000 1038.440000 437.430000 1038.920000 ;
+ RECT 436.430000 1022.120000 437.430000 1022.600000 ;
+ RECT 436.430000 1027.560000 437.430000 1028.040000 ;
+ RECT 436.430000 1033.000000 437.430000 1033.480000 ;
+ RECT 427.120000 1033.000000 428.220000 1033.480000 ;
+ RECT 427.120000 1027.560000 428.220000 1028.040000 ;
+ RECT 427.120000 1022.120000 428.220000 1022.600000 ;
+ RECT 427.120000 1011.240000 428.220000 1011.720000 ;
+ RECT 427.120000 1016.680000 428.220000 1017.160000 ;
+ RECT 436.430000 1016.680000 437.430000 1017.160000 ;
+ RECT 436.430000 1011.240000 437.430000 1011.720000 ;
+ RECT 436.430000 1000.360000 437.430000 1000.840000 ;
+ RECT 436.430000 1005.800000 437.430000 1006.280000 ;
+ RECT 427.120000 1000.360000 428.220000 1000.840000 ;
+ RECT 427.120000 1005.800000 428.220000 1006.280000 ;
+ RECT 382.120000 1043.880000 383.220000 1044.360000 ;
+ RECT 382.120000 1038.440000 383.220000 1038.920000 ;
+ RECT 382.120000 1033.000000 383.220000 1033.480000 ;
+ RECT 382.120000 1027.560000 383.220000 1028.040000 ;
+ RECT 382.120000 1022.120000 383.220000 1022.600000 ;
+ RECT 382.120000 1000.360000 383.220000 1000.840000 ;
+ RECT 382.120000 1005.800000 383.220000 1006.280000 ;
+ RECT 382.120000 1011.240000 383.220000 1011.720000 ;
+ RECT 382.120000 1016.680000 383.220000 1017.160000 ;
+ RECT 427.120000 994.920000 428.220000 995.400000 ;
+ RECT 427.120000 989.480000 428.220000 989.960000 ;
+ RECT 436.430000 994.920000 437.430000 995.400000 ;
+ RECT 436.430000 989.480000 437.430000 989.960000 ;
+ RECT 427.120000 978.600000 428.220000 979.080000 ;
+ RECT 427.120000 973.160000 428.220000 973.640000 ;
+ RECT 436.430000 978.600000 437.430000 979.080000 ;
+ RECT 436.430000 973.160000 437.430000 973.640000 ;
+ RECT 427.120000 984.040000 428.220000 984.520000 ;
+ RECT 436.430000 984.040000 437.430000 984.520000 ;
+ RECT 436.430000 962.280000 437.430000 962.760000 ;
+ RECT 436.430000 967.720000 437.430000 968.200000 ;
+ RECT 427.120000 967.720000 428.220000 968.200000 ;
+ RECT 427.120000 962.280000 428.220000 962.760000 ;
+ RECT 427.120000 956.840000 428.220000 957.320000 ;
+ RECT 427.120000 951.400000 428.220000 951.880000 ;
+ RECT 436.430000 956.840000 437.430000 957.320000 ;
+ RECT 436.430000 951.400000 437.430000 951.880000 ;
+ RECT 382.120000 994.920000 383.220000 995.400000 ;
+ RECT 382.120000 989.480000 383.220000 989.960000 ;
+ RECT 382.120000 984.040000 383.220000 984.520000 ;
+ RECT 382.120000 978.600000 383.220000 979.080000 ;
+ RECT 382.120000 973.160000 383.220000 973.640000 ;
+ RECT 382.120000 967.720000 383.220000 968.200000 ;
+ RECT 382.120000 962.280000 383.220000 962.760000 ;
+ RECT 382.120000 956.840000 383.220000 957.320000 ;
+ RECT 382.120000 951.400000 383.220000 951.880000 ;
+ RECT 337.120000 1043.880000 338.220000 1044.360000 ;
+ RECT 337.120000 1038.440000 338.220000 1038.920000 ;
+ RECT 337.120000 1033.000000 338.220000 1033.480000 ;
+ RECT 337.120000 1027.560000 338.220000 1028.040000 ;
+ RECT 337.120000 1022.120000 338.220000 1022.600000 ;
+ RECT 292.120000 1043.880000 293.220000 1044.360000 ;
+ RECT 292.120000 1038.440000 293.220000 1038.920000 ;
+ RECT 292.120000 1033.000000 293.220000 1033.480000 ;
+ RECT 292.120000 1027.560000 293.220000 1028.040000 ;
+ RECT 292.120000 1022.120000 293.220000 1022.600000 ;
+ RECT 337.120000 1016.680000 338.220000 1017.160000 ;
+ RECT 337.120000 1011.240000 338.220000 1011.720000 ;
+ RECT 337.120000 1005.800000 338.220000 1006.280000 ;
+ RECT 337.120000 1000.360000 338.220000 1000.840000 ;
+ RECT 292.120000 1011.240000 293.220000 1011.720000 ;
+ RECT 292.120000 1005.800000 293.220000 1006.280000 ;
+ RECT 292.120000 1000.360000 293.220000 1000.840000 ;
+ RECT 292.120000 1016.680000 293.220000 1017.160000 ;
+ RECT 247.120000 1043.880000 248.220000 1044.360000 ;
+ RECT 242.990000 1043.880000 243.990000 1044.360000 ;
+ RECT 247.120000 1038.440000 248.220000 1038.920000 ;
+ RECT 242.990000 1038.440000 243.990000 1038.920000 ;
+ RECT 247.120000 1033.000000 248.220000 1033.480000 ;
+ RECT 242.990000 1033.000000 243.990000 1033.480000 ;
+ RECT 247.120000 1022.120000 248.220000 1022.600000 ;
+ RECT 242.990000 1022.120000 243.990000 1022.600000 ;
+ RECT 242.990000 1027.560000 243.990000 1028.040000 ;
+ RECT 247.120000 1027.560000 248.220000 1028.040000 ;
+ RECT 247.120000 1016.680000 248.220000 1017.160000 ;
+ RECT 242.990000 1016.680000 243.990000 1017.160000 ;
+ RECT 247.120000 1011.240000 248.220000 1011.720000 ;
+ RECT 242.990000 1011.240000 243.990000 1011.720000 ;
+ RECT 247.120000 1005.800000 248.220000 1006.280000 ;
+ RECT 242.990000 1005.800000 243.990000 1006.280000 ;
+ RECT 247.120000 1000.360000 248.220000 1000.840000 ;
+ RECT 242.990000 1000.360000 243.990000 1000.840000 ;
+ RECT 337.120000 994.920000 338.220000 995.400000 ;
+ RECT 337.120000 989.480000 338.220000 989.960000 ;
+ RECT 337.120000 984.040000 338.220000 984.520000 ;
+ RECT 337.120000 978.600000 338.220000 979.080000 ;
+ RECT 337.120000 973.160000 338.220000 973.640000 ;
+ RECT 292.120000 994.920000 293.220000 995.400000 ;
+ RECT 292.120000 989.480000 293.220000 989.960000 ;
+ RECT 292.120000 984.040000 293.220000 984.520000 ;
+ RECT 292.120000 978.600000 293.220000 979.080000 ;
+ RECT 292.120000 973.160000 293.220000 973.640000 ;
+ RECT 337.120000 951.400000 338.220000 951.880000 ;
+ RECT 337.120000 956.840000 338.220000 957.320000 ;
+ RECT 337.120000 962.280000 338.220000 962.760000 ;
+ RECT 337.120000 967.720000 338.220000 968.200000 ;
+ RECT 292.120000 951.400000 293.220000 951.880000 ;
+ RECT 292.120000 956.840000 293.220000 957.320000 ;
+ RECT 292.120000 962.280000 293.220000 962.760000 ;
+ RECT 292.120000 967.720000 293.220000 968.200000 ;
+ RECT 247.120000 994.920000 248.220000 995.400000 ;
+ RECT 242.990000 994.920000 243.990000 995.400000 ;
+ RECT 247.120000 989.480000 248.220000 989.960000 ;
+ RECT 242.990000 989.480000 243.990000 989.960000 ;
+ RECT 247.120000 978.600000 248.220000 979.080000 ;
+ RECT 242.990000 978.600000 243.990000 979.080000 ;
+ RECT 247.120000 973.160000 248.220000 973.640000 ;
+ RECT 242.990000 973.160000 243.990000 973.640000 ;
+ RECT 247.120000 984.040000 248.220000 984.520000 ;
+ RECT 242.990000 984.040000 243.990000 984.520000 ;
+ RECT 247.120000 967.720000 248.220000 968.200000 ;
+ RECT 242.990000 967.720000 243.990000 968.200000 ;
+ RECT 247.120000 962.280000 248.220000 962.760000 ;
+ RECT 242.990000 962.280000 243.990000 962.760000 ;
+ RECT 247.120000 956.840000 248.220000 957.320000 ;
+ RECT 247.120000 951.400000 248.220000 951.880000 ;
+ RECT 242.990000 956.840000 243.990000 957.320000 ;
+ RECT 242.990000 951.400000 243.990000 951.880000 ;
+ RECT 240.160000 1141.760000 440.260000 1142.760000 ;
+ RECT 240.160000 949.390000 440.260000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 946.540000 243.990000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 1145.800000 243.990000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 946.540000 437.430000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 1145.800000 437.430000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 949.390000 241.160000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 949.390000 440.260000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1141.760000 241.160000 1142.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1141.760000 440.260000 1142.760000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 749.130000 428.220000 942.500000 ;
+ RECT 382.120000 749.130000 383.220000 942.500000 ;
+ RECT 436.430000 746.280000 437.430000 946.540000 ;
+ RECT 337.120000 749.130000 338.220000 942.500000 ;
+ RECT 292.120000 749.130000 293.220000 942.500000 ;
+ RECT 247.120000 749.130000 248.220000 942.500000 ;
+ RECT 242.990000 746.280000 243.990000 946.540000 ;
+ LAYER met3 ;
+ RECT 427.120000 936.100000 428.220000 936.580000 ;
+ RECT 436.430000 936.100000 437.430000 936.580000 ;
+ RECT 436.430000 925.220000 437.430000 925.700000 ;
+ RECT 436.430000 930.660000 437.430000 931.140000 ;
+ RECT 427.120000 930.660000 428.220000 931.140000 ;
+ RECT 427.120000 925.220000 428.220000 925.700000 ;
+ RECT 427.120000 919.780000 428.220000 920.260000 ;
+ RECT 427.120000 914.340000 428.220000 914.820000 ;
+ RECT 436.430000 919.780000 437.430000 920.260000 ;
+ RECT 436.430000 914.340000 437.430000 914.820000 ;
+ RECT 427.120000 898.020000 428.220000 898.500000 ;
+ RECT 427.120000 903.460000 428.220000 903.940000 ;
+ RECT 436.430000 903.460000 437.430000 903.940000 ;
+ RECT 436.430000 898.020000 437.430000 898.500000 ;
+ RECT 427.120000 908.900000 428.220000 909.380000 ;
+ RECT 436.430000 908.900000 437.430000 909.380000 ;
+ RECT 382.120000 936.100000 383.220000 936.580000 ;
+ RECT 382.120000 930.660000 383.220000 931.140000 ;
+ RECT 382.120000 925.220000 383.220000 925.700000 ;
+ RECT 382.120000 919.780000 383.220000 920.260000 ;
+ RECT 382.120000 898.020000 383.220000 898.500000 ;
+ RECT 382.120000 903.460000 383.220000 903.940000 ;
+ RECT 382.120000 908.900000 383.220000 909.380000 ;
+ RECT 382.120000 914.340000 383.220000 914.820000 ;
+ RECT 436.430000 887.140000 437.430000 887.620000 ;
+ RECT 436.430000 892.580000 437.430000 893.060000 ;
+ RECT 427.120000 892.580000 428.220000 893.060000 ;
+ RECT 427.120000 887.140000 428.220000 887.620000 ;
+ RECT 427.120000 881.700000 428.220000 882.180000 ;
+ RECT 427.120000 876.260000 428.220000 876.740000 ;
+ RECT 436.430000 881.700000 437.430000 882.180000 ;
+ RECT 436.430000 876.260000 437.430000 876.740000 ;
+ RECT 436.430000 859.940000 437.430000 860.420000 ;
+ RECT 436.430000 865.380000 437.430000 865.860000 ;
+ RECT 436.430000 870.820000 437.430000 871.300000 ;
+ RECT 427.120000 865.380000 428.220000 865.860000 ;
+ RECT 427.120000 859.940000 428.220000 860.420000 ;
+ RECT 427.120000 870.820000 428.220000 871.300000 ;
+ RECT 427.120000 854.500000 428.220000 854.980000 ;
+ RECT 427.120000 849.060000 428.220000 849.540000 ;
+ RECT 436.430000 854.500000 437.430000 854.980000 ;
+ RECT 436.430000 849.060000 437.430000 849.540000 ;
+ RECT 382.120000 892.580000 383.220000 893.060000 ;
+ RECT 382.120000 887.140000 383.220000 887.620000 ;
+ RECT 382.120000 881.700000 383.220000 882.180000 ;
+ RECT 382.120000 876.260000 383.220000 876.740000 ;
+ RECT 382.120000 865.380000 383.220000 865.860000 ;
+ RECT 382.120000 859.940000 383.220000 860.420000 ;
+ RECT 382.120000 854.500000 383.220000 854.980000 ;
+ RECT 382.120000 849.060000 383.220000 849.540000 ;
+ RECT 382.120000 870.820000 383.220000 871.300000 ;
+ RECT 337.120000 936.100000 338.220000 936.580000 ;
+ RECT 337.120000 930.660000 338.220000 931.140000 ;
+ RECT 337.120000 925.220000 338.220000 925.700000 ;
+ RECT 292.120000 936.100000 293.220000 936.580000 ;
+ RECT 292.120000 930.660000 293.220000 931.140000 ;
+ RECT 292.120000 925.220000 293.220000 925.700000 ;
+ RECT 337.120000 908.900000 338.220000 909.380000 ;
+ RECT 337.120000 903.460000 338.220000 903.940000 ;
+ RECT 337.120000 898.020000 338.220000 898.500000 ;
+ RECT 337.120000 914.340000 338.220000 914.820000 ;
+ RECT 337.120000 919.780000 338.220000 920.260000 ;
+ RECT 292.120000 919.780000 293.220000 920.260000 ;
+ RECT 292.120000 908.900000 293.220000 909.380000 ;
+ RECT 292.120000 903.460000 293.220000 903.940000 ;
+ RECT 292.120000 898.020000 293.220000 898.500000 ;
+ RECT 292.120000 914.340000 293.220000 914.820000 ;
+ RECT 247.120000 936.100000 248.220000 936.580000 ;
+ RECT 242.990000 936.100000 243.990000 936.580000 ;
+ RECT 242.990000 930.660000 243.990000 931.140000 ;
+ RECT 247.120000 930.660000 248.220000 931.140000 ;
+ RECT 247.120000 925.220000 248.220000 925.700000 ;
+ RECT 242.990000 925.220000 243.990000 925.700000 ;
+ RECT 247.120000 919.780000 248.220000 920.260000 ;
+ RECT 242.990000 919.780000 243.990000 920.260000 ;
+ RECT 247.120000 914.340000 248.220000 914.820000 ;
+ RECT 242.990000 914.340000 243.990000 914.820000 ;
+ RECT 247.120000 903.460000 248.220000 903.940000 ;
+ RECT 242.990000 903.460000 243.990000 903.940000 ;
+ RECT 247.120000 898.020000 248.220000 898.500000 ;
+ RECT 242.990000 898.020000 243.990000 898.500000 ;
+ RECT 247.120000 908.900000 248.220000 909.380000 ;
+ RECT 242.990000 908.900000 243.990000 909.380000 ;
+ RECT 337.120000 892.580000 338.220000 893.060000 ;
+ RECT 337.120000 887.140000 338.220000 887.620000 ;
+ RECT 337.120000 881.700000 338.220000 882.180000 ;
+ RECT 337.120000 876.260000 338.220000 876.740000 ;
+ RECT 292.120000 892.580000 293.220000 893.060000 ;
+ RECT 292.120000 887.140000 293.220000 887.620000 ;
+ RECT 292.120000 881.700000 293.220000 882.180000 ;
+ RECT 292.120000 876.260000 293.220000 876.740000 ;
+ RECT 337.120000 865.380000 338.220000 865.860000 ;
+ RECT 337.120000 849.060000 338.220000 849.540000 ;
+ RECT 337.120000 854.500000 338.220000 854.980000 ;
+ RECT 337.120000 859.940000 338.220000 860.420000 ;
+ RECT 337.120000 870.820000 338.220000 871.300000 ;
+ RECT 292.120000 849.060000 293.220000 849.540000 ;
+ RECT 292.120000 854.500000 293.220000 854.980000 ;
+ RECT 292.120000 859.940000 293.220000 860.420000 ;
+ RECT 292.120000 865.380000 293.220000 865.860000 ;
+ RECT 292.120000 870.820000 293.220000 871.300000 ;
+ RECT 247.120000 892.580000 248.220000 893.060000 ;
+ RECT 242.990000 892.580000 243.990000 893.060000 ;
+ RECT 247.120000 887.140000 248.220000 887.620000 ;
+ RECT 242.990000 887.140000 243.990000 887.620000 ;
+ RECT 247.120000 881.700000 248.220000 882.180000 ;
+ RECT 242.990000 881.700000 243.990000 882.180000 ;
+ RECT 247.120000 876.260000 248.220000 876.740000 ;
+ RECT 242.990000 876.260000 243.990000 876.740000 ;
+ RECT 247.120000 870.820000 248.220000 871.300000 ;
+ RECT 247.120000 865.380000 248.220000 865.860000 ;
+ RECT 242.990000 870.820000 243.990000 871.300000 ;
+ RECT 242.990000 865.380000 243.990000 865.860000 ;
+ RECT 247.120000 859.940000 248.220000 860.420000 ;
+ RECT 242.990000 859.940000 243.990000 860.420000 ;
+ RECT 247.120000 854.500000 248.220000 854.980000 ;
+ RECT 242.990000 854.500000 243.990000 854.980000 ;
+ RECT 247.120000 849.060000 248.220000 849.540000 ;
+ RECT 242.990000 849.060000 243.990000 849.540000 ;
+ RECT 427.120000 843.620000 428.220000 844.100000 ;
+ RECT 427.120000 838.180000 428.220000 838.660000 ;
+ RECT 436.430000 843.620000 437.430000 844.100000 ;
+ RECT 436.430000 838.180000 437.430000 838.660000 ;
+ RECT 436.430000 821.860000 437.430000 822.340000 ;
+ RECT 436.430000 827.300000 437.430000 827.780000 ;
+ RECT 436.430000 832.740000 437.430000 833.220000 ;
+ RECT 427.120000 832.740000 428.220000 833.220000 ;
+ RECT 427.120000 827.300000 428.220000 827.780000 ;
+ RECT 427.120000 821.860000 428.220000 822.340000 ;
+ RECT 427.120000 810.980000 428.220000 811.460000 ;
+ RECT 427.120000 816.420000 428.220000 816.900000 ;
+ RECT 436.430000 816.420000 437.430000 816.900000 ;
+ RECT 436.430000 810.980000 437.430000 811.460000 ;
+ RECT 436.430000 800.100000 437.430000 800.580000 ;
+ RECT 436.430000 805.540000 437.430000 806.020000 ;
+ RECT 427.120000 800.100000 428.220000 800.580000 ;
+ RECT 427.120000 805.540000 428.220000 806.020000 ;
+ RECT 382.120000 843.620000 383.220000 844.100000 ;
+ RECT 382.120000 838.180000 383.220000 838.660000 ;
+ RECT 382.120000 832.740000 383.220000 833.220000 ;
+ RECT 382.120000 827.300000 383.220000 827.780000 ;
+ RECT 382.120000 821.860000 383.220000 822.340000 ;
+ RECT 382.120000 800.100000 383.220000 800.580000 ;
+ RECT 382.120000 805.540000 383.220000 806.020000 ;
+ RECT 382.120000 810.980000 383.220000 811.460000 ;
+ RECT 382.120000 816.420000 383.220000 816.900000 ;
+ RECT 427.120000 794.660000 428.220000 795.140000 ;
+ RECT 427.120000 789.220000 428.220000 789.700000 ;
+ RECT 436.430000 794.660000 437.430000 795.140000 ;
+ RECT 436.430000 789.220000 437.430000 789.700000 ;
+ RECT 427.120000 778.340000 428.220000 778.820000 ;
+ RECT 427.120000 772.900000 428.220000 773.380000 ;
+ RECT 436.430000 778.340000 437.430000 778.820000 ;
+ RECT 436.430000 772.900000 437.430000 773.380000 ;
+ RECT 427.120000 783.780000 428.220000 784.260000 ;
+ RECT 436.430000 783.780000 437.430000 784.260000 ;
+ RECT 436.430000 762.020000 437.430000 762.500000 ;
+ RECT 436.430000 767.460000 437.430000 767.940000 ;
+ RECT 427.120000 767.460000 428.220000 767.940000 ;
+ RECT 427.120000 762.020000 428.220000 762.500000 ;
+ RECT 427.120000 756.580000 428.220000 757.060000 ;
+ RECT 427.120000 751.140000 428.220000 751.620000 ;
+ RECT 436.430000 756.580000 437.430000 757.060000 ;
+ RECT 436.430000 751.140000 437.430000 751.620000 ;
+ RECT 382.120000 794.660000 383.220000 795.140000 ;
+ RECT 382.120000 789.220000 383.220000 789.700000 ;
+ RECT 382.120000 783.780000 383.220000 784.260000 ;
+ RECT 382.120000 778.340000 383.220000 778.820000 ;
+ RECT 382.120000 772.900000 383.220000 773.380000 ;
+ RECT 382.120000 767.460000 383.220000 767.940000 ;
+ RECT 382.120000 762.020000 383.220000 762.500000 ;
+ RECT 382.120000 756.580000 383.220000 757.060000 ;
+ RECT 382.120000 751.140000 383.220000 751.620000 ;
+ RECT 337.120000 843.620000 338.220000 844.100000 ;
+ RECT 337.120000 838.180000 338.220000 838.660000 ;
+ RECT 337.120000 832.740000 338.220000 833.220000 ;
+ RECT 337.120000 827.300000 338.220000 827.780000 ;
+ RECT 337.120000 821.860000 338.220000 822.340000 ;
+ RECT 292.120000 843.620000 293.220000 844.100000 ;
+ RECT 292.120000 838.180000 293.220000 838.660000 ;
+ RECT 292.120000 832.740000 293.220000 833.220000 ;
+ RECT 292.120000 827.300000 293.220000 827.780000 ;
+ RECT 292.120000 821.860000 293.220000 822.340000 ;
+ RECT 337.120000 816.420000 338.220000 816.900000 ;
+ RECT 337.120000 810.980000 338.220000 811.460000 ;
+ RECT 337.120000 805.540000 338.220000 806.020000 ;
+ RECT 337.120000 800.100000 338.220000 800.580000 ;
+ RECT 292.120000 810.980000 293.220000 811.460000 ;
+ RECT 292.120000 805.540000 293.220000 806.020000 ;
+ RECT 292.120000 800.100000 293.220000 800.580000 ;
+ RECT 292.120000 816.420000 293.220000 816.900000 ;
+ RECT 247.120000 843.620000 248.220000 844.100000 ;
+ RECT 242.990000 843.620000 243.990000 844.100000 ;
+ RECT 247.120000 838.180000 248.220000 838.660000 ;
+ RECT 242.990000 838.180000 243.990000 838.660000 ;
+ RECT 247.120000 832.740000 248.220000 833.220000 ;
+ RECT 242.990000 832.740000 243.990000 833.220000 ;
+ RECT 247.120000 821.860000 248.220000 822.340000 ;
+ RECT 242.990000 821.860000 243.990000 822.340000 ;
+ RECT 242.990000 827.300000 243.990000 827.780000 ;
+ RECT 247.120000 827.300000 248.220000 827.780000 ;
+ RECT 247.120000 816.420000 248.220000 816.900000 ;
+ RECT 242.990000 816.420000 243.990000 816.900000 ;
+ RECT 247.120000 810.980000 248.220000 811.460000 ;
+ RECT 242.990000 810.980000 243.990000 811.460000 ;
+ RECT 247.120000 805.540000 248.220000 806.020000 ;
+ RECT 242.990000 805.540000 243.990000 806.020000 ;
+ RECT 247.120000 800.100000 248.220000 800.580000 ;
+ RECT 242.990000 800.100000 243.990000 800.580000 ;
+ RECT 337.120000 794.660000 338.220000 795.140000 ;
+ RECT 337.120000 789.220000 338.220000 789.700000 ;
+ RECT 337.120000 783.780000 338.220000 784.260000 ;
+ RECT 337.120000 778.340000 338.220000 778.820000 ;
+ RECT 337.120000 772.900000 338.220000 773.380000 ;
+ RECT 292.120000 794.660000 293.220000 795.140000 ;
+ RECT 292.120000 789.220000 293.220000 789.700000 ;
+ RECT 292.120000 783.780000 293.220000 784.260000 ;
+ RECT 292.120000 778.340000 293.220000 778.820000 ;
+ RECT 292.120000 772.900000 293.220000 773.380000 ;
+ RECT 337.120000 751.140000 338.220000 751.620000 ;
+ RECT 337.120000 756.580000 338.220000 757.060000 ;
+ RECT 337.120000 762.020000 338.220000 762.500000 ;
+ RECT 337.120000 767.460000 338.220000 767.940000 ;
+ RECT 292.120000 751.140000 293.220000 751.620000 ;
+ RECT 292.120000 756.580000 293.220000 757.060000 ;
+ RECT 292.120000 762.020000 293.220000 762.500000 ;
+ RECT 292.120000 767.460000 293.220000 767.940000 ;
+ RECT 247.120000 794.660000 248.220000 795.140000 ;
+ RECT 242.990000 794.660000 243.990000 795.140000 ;
+ RECT 247.120000 789.220000 248.220000 789.700000 ;
+ RECT 242.990000 789.220000 243.990000 789.700000 ;
+ RECT 247.120000 778.340000 248.220000 778.820000 ;
+ RECT 242.990000 778.340000 243.990000 778.820000 ;
+ RECT 247.120000 772.900000 248.220000 773.380000 ;
+ RECT 242.990000 772.900000 243.990000 773.380000 ;
+ RECT 247.120000 783.780000 248.220000 784.260000 ;
+ RECT 242.990000 783.780000 243.990000 784.260000 ;
+ RECT 247.120000 767.460000 248.220000 767.940000 ;
+ RECT 242.990000 767.460000 243.990000 767.940000 ;
+ RECT 247.120000 762.020000 248.220000 762.500000 ;
+ RECT 242.990000 762.020000 243.990000 762.500000 ;
+ RECT 247.120000 756.580000 248.220000 757.060000 ;
+ RECT 247.120000 751.140000 248.220000 751.620000 ;
+ RECT 242.990000 756.580000 243.990000 757.060000 ;
+ RECT 242.990000 751.140000 243.990000 751.620000 ;
+ RECT 240.160000 941.500000 440.260000 942.500000 ;
+ RECT 240.160000 749.130000 440.260000 750.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 746.280000 243.990000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 945.540000 243.990000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 746.280000 437.430000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 945.540000 437.430000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 749.130000 241.160000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 749.130000 440.260000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 941.500000 241.160000 942.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 941.500000 440.260000 942.500000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 548.870000 428.220000 742.240000 ;
+ RECT 382.120000 548.870000 383.220000 742.240000 ;
+ RECT 436.430000 546.020000 437.430000 746.280000 ;
+ RECT 337.120000 548.870000 338.220000 742.240000 ;
+ RECT 292.120000 548.870000 293.220000 742.240000 ;
+ RECT 247.120000 548.870000 248.220000 742.240000 ;
+ RECT 242.990000 546.020000 243.990000 746.280000 ;
+ LAYER met3 ;
+ RECT 427.120000 735.840000 428.220000 736.320000 ;
+ RECT 436.430000 735.840000 437.430000 736.320000 ;
+ RECT 436.430000 724.960000 437.430000 725.440000 ;
+ RECT 436.430000 730.400000 437.430000 730.880000 ;
+ RECT 427.120000 730.400000 428.220000 730.880000 ;
+ RECT 427.120000 724.960000 428.220000 725.440000 ;
+ RECT 427.120000 719.520000 428.220000 720.000000 ;
+ RECT 427.120000 714.080000 428.220000 714.560000 ;
+ RECT 436.430000 719.520000 437.430000 720.000000 ;
+ RECT 436.430000 714.080000 437.430000 714.560000 ;
+ RECT 427.120000 697.760000 428.220000 698.240000 ;
+ RECT 427.120000 703.200000 428.220000 703.680000 ;
+ RECT 436.430000 703.200000 437.430000 703.680000 ;
+ RECT 436.430000 697.760000 437.430000 698.240000 ;
+ RECT 427.120000 708.640000 428.220000 709.120000 ;
+ RECT 436.430000 708.640000 437.430000 709.120000 ;
+ RECT 382.120000 735.840000 383.220000 736.320000 ;
+ RECT 382.120000 730.400000 383.220000 730.880000 ;
+ RECT 382.120000 724.960000 383.220000 725.440000 ;
+ RECT 382.120000 719.520000 383.220000 720.000000 ;
+ RECT 382.120000 697.760000 383.220000 698.240000 ;
+ RECT 382.120000 703.200000 383.220000 703.680000 ;
+ RECT 382.120000 708.640000 383.220000 709.120000 ;
+ RECT 382.120000 714.080000 383.220000 714.560000 ;
+ RECT 436.430000 686.880000 437.430000 687.360000 ;
+ RECT 436.430000 692.320000 437.430000 692.800000 ;
+ RECT 427.120000 692.320000 428.220000 692.800000 ;
+ RECT 427.120000 686.880000 428.220000 687.360000 ;
+ RECT 427.120000 681.440000 428.220000 681.920000 ;
+ RECT 427.120000 676.000000 428.220000 676.480000 ;
+ RECT 436.430000 681.440000 437.430000 681.920000 ;
+ RECT 436.430000 676.000000 437.430000 676.480000 ;
+ RECT 436.430000 659.680000 437.430000 660.160000 ;
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+ RECT 436.430000 670.560000 437.430000 671.040000 ;
+ RECT 427.120000 665.120000 428.220000 665.600000 ;
+ RECT 427.120000 659.680000 428.220000 660.160000 ;
+ RECT 427.120000 670.560000 428.220000 671.040000 ;
+ RECT 427.120000 654.240000 428.220000 654.720000 ;
+ RECT 427.120000 648.800000 428.220000 649.280000 ;
+ RECT 436.430000 654.240000 437.430000 654.720000 ;
+ RECT 436.430000 648.800000 437.430000 649.280000 ;
+ RECT 382.120000 692.320000 383.220000 692.800000 ;
+ RECT 382.120000 686.880000 383.220000 687.360000 ;
+ RECT 382.120000 681.440000 383.220000 681.920000 ;
+ RECT 382.120000 676.000000 383.220000 676.480000 ;
+ RECT 382.120000 665.120000 383.220000 665.600000 ;
+ RECT 382.120000 659.680000 383.220000 660.160000 ;
+ RECT 382.120000 654.240000 383.220000 654.720000 ;
+ RECT 382.120000 648.800000 383.220000 649.280000 ;
+ RECT 382.120000 670.560000 383.220000 671.040000 ;
+ RECT 337.120000 735.840000 338.220000 736.320000 ;
+ RECT 337.120000 730.400000 338.220000 730.880000 ;
+ RECT 337.120000 724.960000 338.220000 725.440000 ;
+ RECT 292.120000 735.840000 293.220000 736.320000 ;
+ RECT 292.120000 730.400000 293.220000 730.880000 ;
+ RECT 292.120000 724.960000 293.220000 725.440000 ;
+ RECT 337.120000 708.640000 338.220000 709.120000 ;
+ RECT 337.120000 703.200000 338.220000 703.680000 ;
+ RECT 337.120000 697.760000 338.220000 698.240000 ;
+ RECT 337.120000 714.080000 338.220000 714.560000 ;
+ RECT 337.120000 719.520000 338.220000 720.000000 ;
+ RECT 292.120000 719.520000 293.220000 720.000000 ;
+ RECT 292.120000 708.640000 293.220000 709.120000 ;
+ RECT 292.120000 703.200000 293.220000 703.680000 ;
+ RECT 292.120000 697.760000 293.220000 698.240000 ;
+ RECT 292.120000 714.080000 293.220000 714.560000 ;
+ RECT 247.120000 735.840000 248.220000 736.320000 ;
+ RECT 242.990000 735.840000 243.990000 736.320000 ;
+ RECT 242.990000 730.400000 243.990000 730.880000 ;
+ RECT 247.120000 730.400000 248.220000 730.880000 ;
+ RECT 247.120000 724.960000 248.220000 725.440000 ;
+ RECT 242.990000 724.960000 243.990000 725.440000 ;
+ RECT 247.120000 719.520000 248.220000 720.000000 ;
+ RECT 242.990000 719.520000 243.990000 720.000000 ;
+ RECT 247.120000 714.080000 248.220000 714.560000 ;
+ RECT 242.990000 714.080000 243.990000 714.560000 ;
+ RECT 247.120000 703.200000 248.220000 703.680000 ;
+ RECT 242.990000 703.200000 243.990000 703.680000 ;
+ RECT 247.120000 697.760000 248.220000 698.240000 ;
+ RECT 242.990000 697.760000 243.990000 698.240000 ;
+ RECT 247.120000 708.640000 248.220000 709.120000 ;
+ RECT 242.990000 708.640000 243.990000 709.120000 ;
+ RECT 337.120000 692.320000 338.220000 692.800000 ;
+ RECT 337.120000 686.880000 338.220000 687.360000 ;
+ RECT 337.120000 681.440000 338.220000 681.920000 ;
+ RECT 337.120000 676.000000 338.220000 676.480000 ;
+ RECT 292.120000 692.320000 293.220000 692.800000 ;
+ RECT 292.120000 686.880000 293.220000 687.360000 ;
+ RECT 292.120000 681.440000 293.220000 681.920000 ;
+ RECT 292.120000 676.000000 293.220000 676.480000 ;
+ RECT 337.120000 665.120000 338.220000 665.600000 ;
+ RECT 337.120000 648.800000 338.220000 649.280000 ;
+ RECT 337.120000 654.240000 338.220000 654.720000 ;
+ RECT 337.120000 659.680000 338.220000 660.160000 ;
+ RECT 337.120000 670.560000 338.220000 671.040000 ;
+ RECT 292.120000 648.800000 293.220000 649.280000 ;
+ RECT 292.120000 654.240000 293.220000 654.720000 ;
+ RECT 292.120000 659.680000 293.220000 660.160000 ;
+ RECT 292.120000 665.120000 293.220000 665.600000 ;
+ RECT 292.120000 670.560000 293.220000 671.040000 ;
+ RECT 247.120000 692.320000 248.220000 692.800000 ;
+ RECT 242.990000 692.320000 243.990000 692.800000 ;
+ RECT 247.120000 686.880000 248.220000 687.360000 ;
+ RECT 242.990000 686.880000 243.990000 687.360000 ;
+ RECT 247.120000 681.440000 248.220000 681.920000 ;
+ RECT 242.990000 681.440000 243.990000 681.920000 ;
+ RECT 247.120000 676.000000 248.220000 676.480000 ;
+ RECT 242.990000 676.000000 243.990000 676.480000 ;
+ RECT 247.120000 670.560000 248.220000 671.040000 ;
+ RECT 247.120000 665.120000 248.220000 665.600000 ;
+ RECT 242.990000 670.560000 243.990000 671.040000 ;
+ RECT 242.990000 665.120000 243.990000 665.600000 ;
+ RECT 247.120000 659.680000 248.220000 660.160000 ;
+ RECT 242.990000 659.680000 243.990000 660.160000 ;
+ RECT 247.120000 654.240000 248.220000 654.720000 ;
+ RECT 242.990000 654.240000 243.990000 654.720000 ;
+ RECT 247.120000 648.800000 248.220000 649.280000 ;
+ RECT 242.990000 648.800000 243.990000 649.280000 ;
+ RECT 427.120000 643.360000 428.220000 643.840000 ;
+ RECT 427.120000 637.920000 428.220000 638.400000 ;
+ RECT 436.430000 643.360000 437.430000 643.840000 ;
+ RECT 436.430000 637.920000 437.430000 638.400000 ;
+ RECT 436.430000 621.600000 437.430000 622.080000 ;
+ RECT 436.430000 627.040000 437.430000 627.520000 ;
+ RECT 436.430000 632.480000 437.430000 632.960000 ;
+ RECT 427.120000 632.480000 428.220000 632.960000 ;
+ RECT 427.120000 627.040000 428.220000 627.520000 ;
+ RECT 427.120000 621.600000 428.220000 622.080000 ;
+ RECT 427.120000 610.720000 428.220000 611.200000 ;
+ RECT 427.120000 616.160000 428.220000 616.640000 ;
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+ RECT 436.430000 610.720000 437.430000 611.200000 ;
+ RECT 436.430000 599.840000 437.430000 600.320000 ;
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+ RECT 427.120000 599.840000 428.220000 600.320000 ;
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+ RECT 382.120000 643.360000 383.220000 643.840000 ;
+ RECT 382.120000 637.920000 383.220000 638.400000 ;
+ RECT 382.120000 632.480000 383.220000 632.960000 ;
+ RECT 382.120000 627.040000 383.220000 627.520000 ;
+ RECT 382.120000 621.600000 383.220000 622.080000 ;
+ RECT 382.120000 599.840000 383.220000 600.320000 ;
+ RECT 382.120000 605.280000 383.220000 605.760000 ;
+ RECT 382.120000 610.720000 383.220000 611.200000 ;
+ RECT 382.120000 616.160000 383.220000 616.640000 ;
+ RECT 427.120000 594.400000 428.220000 594.880000 ;
+ RECT 427.120000 588.960000 428.220000 589.440000 ;
+ RECT 436.430000 594.400000 437.430000 594.880000 ;
+ RECT 436.430000 588.960000 437.430000 589.440000 ;
+ RECT 427.120000 578.080000 428.220000 578.560000 ;
+ RECT 427.120000 572.640000 428.220000 573.120000 ;
+ RECT 436.430000 578.080000 437.430000 578.560000 ;
+ RECT 436.430000 572.640000 437.430000 573.120000 ;
+ RECT 427.120000 583.520000 428.220000 584.000000 ;
+ RECT 436.430000 583.520000 437.430000 584.000000 ;
+ RECT 436.430000 561.760000 437.430000 562.240000 ;
+ RECT 436.430000 567.200000 437.430000 567.680000 ;
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+ RECT 427.120000 561.760000 428.220000 562.240000 ;
+ RECT 427.120000 556.320000 428.220000 556.800000 ;
+ RECT 427.120000 550.880000 428.220000 551.360000 ;
+ RECT 436.430000 556.320000 437.430000 556.800000 ;
+ RECT 436.430000 550.880000 437.430000 551.360000 ;
+ RECT 382.120000 594.400000 383.220000 594.880000 ;
+ RECT 382.120000 588.960000 383.220000 589.440000 ;
+ RECT 382.120000 583.520000 383.220000 584.000000 ;
+ RECT 382.120000 578.080000 383.220000 578.560000 ;
+ RECT 382.120000 572.640000 383.220000 573.120000 ;
+ RECT 382.120000 567.200000 383.220000 567.680000 ;
+ RECT 382.120000 561.760000 383.220000 562.240000 ;
+ RECT 382.120000 556.320000 383.220000 556.800000 ;
+ RECT 382.120000 550.880000 383.220000 551.360000 ;
+ RECT 337.120000 643.360000 338.220000 643.840000 ;
+ RECT 337.120000 637.920000 338.220000 638.400000 ;
+ RECT 337.120000 632.480000 338.220000 632.960000 ;
+ RECT 337.120000 627.040000 338.220000 627.520000 ;
+ RECT 337.120000 621.600000 338.220000 622.080000 ;
+ RECT 292.120000 643.360000 293.220000 643.840000 ;
+ RECT 292.120000 637.920000 293.220000 638.400000 ;
+ RECT 292.120000 632.480000 293.220000 632.960000 ;
+ RECT 292.120000 627.040000 293.220000 627.520000 ;
+ RECT 292.120000 621.600000 293.220000 622.080000 ;
+ RECT 337.120000 616.160000 338.220000 616.640000 ;
+ RECT 337.120000 610.720000 338.220000 611.200000 ;
+ RECT 337.120000 605.280000 338.220000 605.760000 ;
+ RECT 337.120000 599.840000 338.220000 600.320000 ;
+ RECT 292.120000 610.720000 293.220000 611.200000 ;
+ RECT 292.120000 605.280000 293.220000 605.760000 ;
+ RECT 292.120000 599.840000 293.220000 600.320000 ;
+ RECT 292.120000 616.160000 293.220000 616.640000 ;
+ RECT 247.120000 643.360000 248.220000 643.840000 ;
+ RECT 242.990000 643.360000 243.990000 643.840000 ;
+ RECT 247.120000 637.920000 248.220000 638.400000 ;
+ RECT 242.990000 637.920000 243.990000 638.400000 ;
+ RECT 247.120000 632.480000 248.220000 632.960000 ;
+ RECT 242.990000 632.480000 243.990000 632.960000 ;
+ RECT 247.120000 621.600000 248.220000 622.080000 ;
+ RECT 242.990000 621.600000 243.990000 622.080000 ;
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+ RECT 247.120000 627.040000 248.220000 627.520000 ;
+ RECT 247.120000 616.160000 248.220000 616.640000 ;
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+ RECT 247.120000 610.720000 248.220000 611.200000 ;
+ RECT 242.990000 610.720000 243.990000 611.200000 ;
+ RECT 247.120000 605.280000 248.220000 605.760000 ;
+ RECT 242.990000 605.280000 243.990000 605.760000 ;
+ RECT 247.120000 599.840000 248.220000 600.320000 ;
+ RECT 242.990000 599.840000 243.990000 600.320000 ;
+ RECT 337.120000 594.400000 338.220000 594.880000 ;
+ RECT 337.120000 588.960000 338.220000 589.440000 ;
+ RECT 337.120000 583.520000 338.220000 584.000000 ;
+ RECT 337.120000 578.080000 338.220000 578.560000 ;
+ RECT 337.120000 572.640000 338.220000 573.120000 ;
+ RECT 292.120000 594.400000 293.220000 594.880000 ;
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+ RECT 292.120000 583.520000 293.220000 584.000000 ;
+ RECT 292.120000 578.080000 293.220000 578.560000 ;
+ RECT 292.120000 572.640000 293.220000 573.120000 ;
+ RECT 337.120000 550.880000 338.220000 551.360000 ;
+ RECT 337.120000 556.320000 338.220000 556.800000 ;
+ RECT 337.120000 561.760000 338.220000 562.240000 ;
+ RECT 337.120000 567.200000 338.220000 567.680000 ;
+ RECT 292.120000 550.880000 293.220000 551.360000 ;
+ RECT 292.120000 556.320000 293.220000 556.800000 ;
+ RECT 292.120000 561.760000 293.220000 562.240000 ;
+ RECT 292.120000 567.200000 293.220000 567.680000 ;
+ RECT 247.120000 594.400000 248.220000 594.880000 ;
+ RECT 242.990000 594.400000 243.990000 594.880000 ;
+ RECT 247.120000 588.960000 248.220000 589.440000 ;
+ RECT 242.990000 588.960000 243.990000 589.440000 ;
+ RECT 247.120000 578.080000 248.220000 578.560000 ;
+ RECT 242.990000 578.080000 243.990000 578.560000 ;
+ RECT 247.120000 572.640000 248.220000 573.120000 ;
+ RECT 242.990000 572.640000 243.990000 573.120000 ;
+ RECT 247.120000 583.520000 248.220000 584.000000 ;
+ RECT 242.990000 583.520000 243.990000 584.000000 ;
+ RECT 247.120000 567.200000 248.220000 567.680000 ;
+ RECT 242.990000 567.200000 243.990000 567.680000 ;
+ RECT 247.120000 561.760000 248.220000 562.240000 ;
+ RECT 242.990000 561.760000 243.990000 562.240000 ;
+ RECT 247.120000 556.320000 248.220000 556.800000 ;
+ RECT 247.120000 550.880000 248.220000 551.360000 ;
+ RECT 242.990000 556.320000 243.990000 556.800000 ;
+ RECT 242.990000 550.880000 243.990000 551.360000 ;
+ RECT 240.160000 741.240000 440.260000 742.240000 ;
+ RECT 240.160000 548.870000 440.260000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 546.020000 243.990000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 745.280000 243.990000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 546.020000 437.430000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 745.280000 437.430000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 548.870000 241.160000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 548.870000 440.260000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 741.240000 241.160000 742.240000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 741.240000 440.260000 742.240000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 348.610000 428.220000 541.980000 ;
+ RECT 382.120000 348.610000 383.220000 541.980000 ;
+ RECT 436.430000 345.760000 437.430000 546.020000 ;
+ RECT 337.120000 348.610000 338.220000 541.980000 ;
+ RECT 292.120000 348.610000 293.220000 541.980000 ;
+ RECT 247.120000 348.610000 248.220000 541.980000 ;
+ RECT 242.990000 345.760000 243.990000 546.020000 ;
+ LAYER met3 ;
+ RECT 427.120000 535.580000 428.220000 536.060000 ;
+ RECT 436.430000 535.580000 437.430000 536.060000 ;
+ RECT 436.430000 524.700000 437.430000 525.180000 ;
+ RECT 436.430000 530.140000 437.430000 530.620000 ;
+ RECT 427.120000 530.140000 428.220000 530.620000 ;
+ RECT 427.120000 524.700000 428.220000 525.180000 ;
+ RECT 427.120000 519.260000 428.220000 519.740000 ;
+ RECT 427.120000 513.820000 428.220000 514.300000 ;
+ RECT 436.430000 519.260000 437.430000 519.740000 ;
+ RECT 436.430000 513.820000 437.430000 514.300000 ;
+ RECT 427.120000 497.500000 428.220000 497.980000 ;
+ RECT 427.120000 502.940000 428.220000 503.420000 ;
+ RECT 436.430000 502.940000 437.430000 503.420000 ;
+ RECT 436.430000 497.500000 437.430000 497.980000 ;
+ RECT 427.120000 508.380000 428.220000 508.860000 ;
+ RECT 436.430000 508.380000 437.430000 508.860000 ;
+ RECT 382.120000 535.580000 383.220000 536.060000 ;
+ RECT 382.120000 530.140000 383.220000 530.620000 ;
+ RECT 382.120000 524.700000 383.220000 525.180000 ;
+ RECT 382.120000 519.260000 383.220000 519.740000 ;
+ RECT 382.120000 497.500000 383.220000 497.980000 ;
+ RECT 382.120000 502.940000 383.220000 503.420000 ;
+ RECT 382.120000 508.380000 383.220000 508.860000 ;
+ RECT 382.120000 513.820000 383.220000 514.300000 ;
+ RECT 436.430000 486.620000 437.430000 487.100000 ;
+ RECT 436.430000 492.060000 437.430000 492.540000 ;
+ RECT 427.120000 492.060000 428.220000 492.540000 ;
+ RECT 427.120000 486.620000 428.220000 487.100000 ;
+ RECT 427.120000 481.180000 428.220000 481.660000 ;
+ RECT 427.120000 475.740000 428.220000 476.220000 ;
+ RECT 436.430000 481.180000 437.430000 481.660000 ;
+ RECT 436.430000 475.740000 437.430000 476.220000 ;
+ RECT 436.430000 459.420000 437.430000 459.900000 ;
+ RECT 436.430000 464.860000 437.430000 465.340000 ;
+ RECT 436.430000 470.300000 437.430000 470.780000 ;
+ RECT 427.120000 464.860000 428.220000 465.340000 ;
+ RECT 427.120000 459.420000 428.220000 459.900000 ;
+ RECT 427.120000 470.300000 428.220000 470.780000 ;
+ RECT 427.120000 453.980000 428.220000 454.460000 ;
+ RECT 427.120000 448.540000 428.220000 449.020000 ;
+ RECT 436.430000 453.980000 437.430000 454.460000 ;
+ RECT 436.430000 448.540000 437.430000 449.020000 ;
+ RECT 382.120000 492.060000 383.220000 492.540000 ;
+ RECT 382.120000 486.620000 383.220000 487.100000 ;
+ RECT 382.120000 481.180000 383.220000 481.660000 ;
+ RECT 382.120000 475.740000 383.220000 476.220000 ;
+ RECT 382.120000 464.860000 383.220000 465.340000 ;
+ RECT 382.120000 459.420000 383.220000 459.900000 ;
+ RECT 382.120000 453.980000 383.220000 454.460000 ;
+ RECT 382.120000 448.540000 383.220000 449.020000 ;
+ RECT 382.120000 470.300000 383.220000 470.780000 ;
+ RECT 337.120000 535.580000 338.220000 536.060000 ;
+ RECT 337.120000 530.140000 338.220000 530.620000 ;
+ RECT 337.120000 524.700000 338.220000 525.180000 ;
+ RECT 292.120000 535.580000 293.220000 536.060000 ;
+ RECT 292.120000 530.140000 293.220000 530.620000 ;
+ RECT 292.120000 524.700000 293.220000 525.180000 ;
+ RECT 337.120000 508.380000 338.220000 508.860000 ;
+ RECT 337.120000 502.940000 338.220000 503.420000 ;
+ RECT 337.120000 497.500000 338.220000 497.980000 ;
+ RECT 337.120000 513.820000 338.220000 514.300000 ;
+ RECT 337.120000 519.260000 338.220000 519.740000 ;
+ RECT 292.120000 519.260000 293.220000 519.740000 ;
+ RECT 292.120000 508.380000 293.220000 508.860000 ;
+ RECT 292.120000 502.940000 293.220000 503.420000 ;
+ RECT 292.120000 497.500000 293.220000 497.980000 ;
+ RECT 292.120000 513.820000 293.220000 514.300000 ;
+ RECT 247.120000 535.580000 248.220000 536.060000 ;
+ RECT 242.990000 535.580000 243.990000 536.060000 ;
+ RECT 242.990000 530.140000 243.990000 530.620000 ;
+ RECT 247.120000 530.140000 248.220000 530.620000 ;
+ RECT 247.120000 524.700000 248.220000 525.180000 ;
+ RECT 242.990000 524.700000 243.990000 525.180000 ;
+ RECT 247.120000 519.260000 248.220000 519.740000 ;
+ RECT 242.990000 519.260000 243.990000 519.740000 ;
+ RECT 247.120000 513.820000 248.220000 514.300000 ;
+ RECT 242.990000 513.820000 243.990000 514.300000 ;
+ RECT 247.120000 502.940000 248.220000 503.420000 ;
+ RECT 242.990000 502.940000 243.990000 503.420000 ;
+ RECT 247.120000 497.500000 248.220000 497.980000 ;
+ RECT 242.990000 497.500000 243.990000 497.980000 ;
+ RECT 247.120000 508.380000 248.220000 508.860000 ;
+ RECT 242.990000 508.380000 243.990000 508.860000 ;
+ RECT 337.120000 492.060000 338.220000 492.540000 ;
+ RECT 337.120000 486.620000 338.220000 487.100000 ;
+ RECT 337.120000 481.180000 338.220000 481.660000 ;
+ RECT 337.120000 475.740000 338.220000 476.220000 ;
+ RECT 292.120000 492.060000 293.220000 492.540000 ;
+ RECT 292.120000 486.620000 293.220000 487.100000 ;
+ RECT 292.120000 481.180000 293.220000 481.660000 ;
+ RECT 292.120000 475.740000 293.220000 476.220000 ;
+ RECT 337.120000 464.860000 338.220000 465.340000 ;
+ RECT 337.120000 448.540000 338.220000 449.020000 ;
+ RECT 337.120000 453.980000 338.220000 454.460000 ;
+ RECT 337.120000 459.420000 338.220000 459.900000 ;
+ RECT 337.120000 470.300000 338.220000 470.780000 ;
+ RECT 292.120000 448.540000 293.220000 449.020000 ;
+ RECT 292.120000 453.980000 293.220000 454.460000 ;
+ RECT 292.120000 459.420000 293.220000 459.900000 ;
+ RECT 292.120000 464.860000 293.220000 465.340000 ;
+ RECT 292.120000 470.300000 293.220000 470.780000 ;
+ RECT 247.120000 492.060000 248.220000 492.540000 ;
+ RECT 242.990000 492.060000 243.990000 492.540000 ;
+ RECT 247.120000 486.620000 248.220000 487.100000 ;
+ RECT 242.990000 486.620000 243.990000 487.100000 ;
+ RECT 247.120000 481.180000 248.220000 481.660000 ;
+ RECT 242.990000 481.180000 243.990000 481.660000 ;
+ RECT 247.120000 475.740000 248.220000 476.220000 ;
+ RECT 242.990000 475.740000 243.990000 476.220000 ;
+ RECT 247.120000 470.300000 248.220000 470.780000 ;
+ RECT 247.120000 464.860000 248.220000 465.340000 ;
+ RECT 242.990000 470.300000 243.990000 470.780000 ;
+ RECT 242.990000 464.860000 243.990000 465.340000 ;
+ RECT 247.120000 459.420000 248.220000 459.900000 ;
+ RECT 242.990000 459.420000 243.990000 459.900000 ;
+ RECT 247.120000 453.980000 248.220000 454.460000 ;
+ RECT 242.990000 453.980000 243.990000 454.460000 ;
+ RECT 247.120000 448.540000 248.220000 449.020000 ;
+ RECT 242.990000 448.540000 243.990000 449.020000 ;
+ RECT 427.120000 443.100000 428.220000 443.580000 ;
+ RECT 427.120000 437.660000 428.220000 438.140000 ;
+ RECT 436.430000 443.100000 437.430000 443.580000 ;
+ RECT 436.430000 437.660000 437.430000 438.140000 ;
+ RECT 436.430000 421.340000 437.430000 421.820000 ;
+ RECT 436.430000 426.780000 437.430000 427.260000 ;
+ RECT 436.430000 432.220000 437.430000 432.700000 ;
+ RECT 427.120000 432.220000 428.220000 432.700000 ;
+ RECT 427.120000 426.780000 428.220000 427.260000 ;
+ RECT 427.120000 421.340000 428.220000 421.820000 ;
+ RECT 427.120000 410.460000 428.220000 410.940000 ;
+ RECT 427.120000 415.900000 428.220000 416.380000 ;
+ RECT 436.430000 415.900000 437.430000 416.380000 ;
+ RECT 436.430000 410.460000 437.430000 410.940000 ;
+ RECT 436.430000 399.580000 437.430000 400.060000 ;
+ RECT 436.430000 405.020000 437.430000 405.500000 ;
+ RECT 427.120000 399.580000 428.220000 400.060000 ;
+ RECT 427.120000 405.020000 428.220000 405.500000 ;
+ RECT 382.120000 443.100000 383.220000 443.580000 ;
+ RECT 382.120000 437.660000 383.220000 438.140000 ;
+ RECT 382.120000 432.220000 383.220000 432.700000 ;
+ RECT 382.120000 426.780000 383.220000 427.260000 ;
+ RECT 382.120000 421.340000 383.220000 421.820000 ;
+ RECT 382.120000 399.580000 383.220000 400.060000 ;
+ RECT 382.120000 405.020000 383.220000 405.500000 ;
+ RECT 382.120000 410.460000 383.220000 410.940000 ;
+ RECT 382.120000 415.900000 383.220000 416.380000 ;
+ RECT 427.120000 394.140000 428.220000 394.620000 ;
+ RECT 427.120000 388.700000 428.220000 389.180000 ;
+ RECT 436.430000 394.140000 437.430000 394.620000 ;
+ RECT 436.430000 388.700000 437.430000 389.180000 ;
+ RECT 427.120000 377.820000 428.220000 378.300000 ;
+ RECT 427.120000 372.380000 428.220000 372.860000 ;
+ RECT 436.430000 377.820000 437.430000 378.300000 ;
+ RECT 436.430000 372.380000 437.430000 372.860000 ;
+ RECT 427.120000 383.260000 428.220000 383.740000 ;
+ RECT 436.430000 383.260000 437.430000 383.740000 ;
+ RECT 436.430000 361.500000 437.430000 361.980000 ;
+ RECT 436.430000 366.940000 437.430000 367.420000 ;
+ RECT 427.120000 366.940000 428.220000 367.420000 ;
+ RECT 427.120000 361.500000 428.220000 361.980000 ;
+ RECT 427.120000 356.060000 428.220000 356.540000 ;
+ RECT 427.120000 350.620000 428.220000 351.100000 ;
+ RECT 436.430000 356.060000 437.430000 356.540000 ;
+ RECT 436.430000 350.620000 437.430000 351.100000 ;
+ RECT 382.120000 394.140000 383.220000 394.620000 ;
+ RECT 382.120000 388.700000 383.220000 389.180000 ;
+ RECT 382.120000 383.260000 383.220000 383.740000 ;
+ RECT 382.120000 377.820000 383.220000 378.300000 ;
+ RECT 382.120000 372.380000 383.220000 372.860000 ;
+ RECT 382.120000 366.940000 383.220000 367.420000 ;
+ RECT 382.120000 361.500000 383.220000 361.980000 ;
+ RECT 382.120000 356.060000 383.220000 356.540000 ;
+ RECT 382.120000 350.620000 383.220000 351.100000 ;
+ RECT 337.120000 443.100000 338.220000 443.580000 ;
+ RECT 337.120000 437.660000 338.220000 438.140000 ;
+ RECT 337.120000 432.220000 338.220000 432.700000 ;
+ RECT 337.120000 426.780000 338.220000 427.260000 ;
+ RECT 337.120000 421.340000 338.220000 421.820000 ;
+ RECT 292.120000 443.100000 293.220000 443.580000 ;
+ RECT 292.120000 437.660000 293.220000 438.140000 ;
+ RECT 292.120000 432.220000 293.220000 432.700000 ;
+ RECT 292.120000 426.780000 293.220000 427.260000 ;
+ RECT 292.120000 421.340000 293.220000 421.820000 ;
+ RECT 337.120000 415.900000 338.220000 416.380000 ;
+ RECT 337.120000 410.460000 338.220000 410.940000 ;
+ RECT 337.120000 405.020000 338.220000 405.500000 ;
+ RECT 337.120000 399.580000 338.220000 400.060000 ;
+ RECT 292.120000 410.460000 293.220000 410.940000 ;
+ RECT 292.120000 405.020000 293.220000 405.500000 ;
+ RECT 292.120000 399.580000 293.220000 400.060000 ;
+ RECT 292.120000 415.900000 293.220000 416.380000 ;
+ RECT 247.120000 443.100000 248.220000 443.580000 ;
+ RECT 242.990000 443.100000 243.990000 443.580000 ;
+ RECT 247.120000 437.660000 248.220000 438.140000 ;
+ RECT 242.990000 437.660000 243.990000 438.140000 ;
+ RECT 247.120000 432.220000 248.220000 432.700000 ;
+ RECT 242.990000 432.220000 243.990000 432.700000 ;
+ RECT 247.120000 421.340000 248.220000 421.820000 ;
+ RECT 242.990000 421.340000 243.990000 421.820000 ;
+ RECT 242.990000 426.780000 243.990000 427.260000 ;
+ RECT 247.120000 426.780000 248.220000 427.260000 ;
+ RECT 247.120000 415.900000 248.220000 416.380000 ;
+ RECT 242.990000 415.900000 243.990000 416.380000 ;
+ RECT 247.120000 410.460000 248.220000 410.940000 ;
+ RECT 242.990000 410.460000 243.990000 410.940000 ;
+ RECT 247.120000 405.020000 248.220000 405.500000 ;
+ RECT 242.990000 405.020000 243.990000 405.500000 ;
+ RECT 247.120000 399.580000 248.220000 400.060000 ;
+ RECT 242.990000 399.580000 243.990000 400.060000 ;
+ RECT 337.120000 394.140000 338.220000 394.620000 ;
+ RECT 337.120000 388.700000 338.220000 389.180000 ;
+ RECT 337.120000 383.260000 338.220000 383.740000 ;
+ RECT 337.120000 377.820000 338.220000 378.300000 ;
+ RECT 337.120000 372.380000 338.220000 372.860000 ;
+ RECT 292.120000 394.140000 293.220000 394.620000 ;
+ RECT 292.120000 388.700000 293.220000 389.180000 ;
+ RECT 292.120000 383.260000 293.220000 383.740000 ;
+ RECT 292.120000 377.820000 293.220000 378.300000 ;
+ RECT 292.120000 372.380000 293.220000 372.860000 ;
+ RECT 337.120000 350.620000 338.220000 351.100000 ;
+ RECT 337.120000 356.060000 338.220000 356.540000 ;
+ RECT 337.120000 361.500000 338.220000 361.980000 ;
+ RECT 337.120000 366.940000 338.220000 367.420000 ;
+ RECT 292.120000 350.620000 293.220000 351.100000 ;
+ RECT 292.120000 356.060000 293.220000 356.540000 ;
+ RECT 292.120000 361.500000 293.220000 361.980000 ;
+ RECT 292.120000 366.940000 293.220000 367.420000 ;
+ RECT 247.120000 394.140000 248.220000 394.620000 ;
+ RECT 242.990000 394.140000 243.990000 394.620000 ;
+ RECT 247.120000 388.700000 248.220000 389.180000 ;
+ RECT 242.990000 388.700000 243.990000 389.180000 ;
+ RECT 247.120000 377.820000 248.220000 378.300000 ;
+ RECT 242.990000 377.820000 243.990000 378.300000 ;
+ RECT 247.120000 372.380000 248.220000 372.860000 ;
+ RECT 242.990000 372.380000 243.990000 372.860000 ;
+ RECT 247.120000 383.260000 248.220000 383.740000 ;
+ RECT 242.990000 383.260000 243.990000 383.740000 ;
+ RECT 247.120000 366.940000 248.220000 367.420000 ;
+ RECT 242.990000 366.940000 243.990000 367.420000 ;
+ RECT 247.120000 361.500000 248.220000 361.980000 ;
+ RECT 242.990000 361.500000 243.990000 361.980000 ;
+ RECT 247.120000 356.060000 248.220000 356.540000 ;
+ RECT 247.120000 350.620000 248.220000 351.100000 ;
+ RECT 242.990000 356.060000 243.990000 356.540000 ;
+ RECT 242.990000 350.620000 243.990000 351.100000 ;
+ RECT 240.160000 540.980000 440.260000 541.980000 ;
+ RECT 240.160000 348.610000 440.260000 349.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 345.760000 243.990000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 545.020000 243.990000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 345.760000 437.430000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 545.020000 437.430000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 348.610000 241.160000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 348.610000 440.260000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 540.980000 241.160000 541.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 540.980000 440.260000 541.980000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 148.350000 428.220000 341.720000 ;
+ RECT 382.120000 148.350000 383.220000 341.720000 ;
+ RECT 436.430000 145.500000 437.430000 345.760000 ;
+ RECT 337.120000 148.350000 338.220000 341.720000 ;
+ RECT 292.120000 148.350000 293.220000 341.720000 ;
+ RECT 247.120000 148.350000 248.220000 341.720000 ;
+ RECT 242.990000 145.500000 243.990000 345.760000 ;
+ LAYER met3 ;
+ RECT 427.120000 335.320000 428.220000 335.800000 ;
+ RECT 436.430000 335.320000 437.430000 335.800000 ;
+ RECT 436.430000 324.440000 437.430000 324.920000 ;
+ RECT 436.430000 329.880000 437.430000 330.360000 ;
+ RECT 427.120000 329.880000 428.220000 330.360000 ;
+ RECT 427.120000 324.440000 428.220000 324.920000 ;
+ RECT 427.120000 319.000000 428.220000 319.480000 ;
+ RECT 427.120000 313.560000 428.220000 314.040000 ;
+ RECT 436.430000 319.000000 437.430000 319.480000 ;
+ RECT 436.430000 313.560000 437.430000 314.040000 ;
+ RECT 427.120000 297.240000 428.220000 297.720000 ;
+ RECT 427.120000 302.680000 428.220000 303.160000 ;
+ RECT 436.430000 302.680000 437.430000 303.160000 ;
+ RECT 436.430000 297.240000 437.430000 297.720000 ;
+ RECT 427.120000 308.120000 428.220000 308.600000 ;
+ RECT 436.430000 308.120000 437.430000 308.600000 ;
+ RECT 382.120000 335.320000 383.220000 335.800000 ;
+ RECT 382.120000 329.880000 383.220000 330.360000 ;
+ RECT 382.120000 324.440000 383.220000 324.920000 ;
+ RECT 382.120000 319.000000 383.220000 319.480000 ;
+ RECT 382.120000 297.240000 383.220000 297.720000 ;
+ RECT 382.120000 302.680000 383.220000 303.160000 ;
+ RECT 382.120000 308.120000 383.220000 308.600000 ;
+ RECT 382.120000 313.560000 383.220000 314.040000 ;
+ RECT 436.430000 286.360000 437.430000 286.840000 ;
+ RECT 436.430000 291.800000 437.430000 292.280000 ;
+ RECT 427.120000 291.800000 428.220000 292.280000 ;
+ RECT 427.120000 286.360000 428.220000 286.840000 ;
+ RECT 427.120000 280.920000 428.220000 281.400000 ;
+ RECT 427.120000 275.480000 428.220000 275.960000 ;
+ RECT 436.430000 280.920000 437.430000 281.400000 ;
+ RECT 436.430000 275.480000 437.430000 275.960000 ;
+ RECT 436.430000 259.160000 437.430000 259.640000 ;
+ RECT 436.430000 264.600000 437.430000 265.080000 ;
+ RECT 436.430000 270.040000 437.430000 270.520000 ;
+ RECT 427.120000 264.600000 428.220000 265.080000 ;
+ RECT 427.120000 259.160000 428.220000 259.640000 ;
+ RECT 427.120000 270.040000 428.220000 270.520000 ;
+ RECT 427.120000 253.720000 428.220000 254.200000 ;
+ RECT 427.120000 248.280000 428.220000 248.760000 ;
+ RECT 436.430000 253.720000 437.430000 254.200000 ;
+ RECT 436.430000 248.280000 437.430000 248.760000 ;
+ RECT 382.120000 291.800000 383.220000 292.280000 ;
+ RECT 382.120000 286.360000 383.220000 286.840000 ;
+ RECT 382.120000 280.920000 383.220000 281.400000 ;
+ RECT 382.120000 275.480000 383.220000 275.960000 ;
+ RECT 382.120000 264.600000 383.220000 265.080000 ;
+ RECT 382.120000 259.160000 383.220000 259.640000 ;
+ RECT 382.120000 253.720000 383.220000 254.200000 ;
+ RECT 382.120000 248.280000 383.220000 248.760000 ;
+ RECT 382.120000 270.040000 383.220000 270.520000 ;
+ RECT 337.120000 335.320000 338.220000 335.800000 ;
+ RECT 337.120000 329.880000 338.220000 330.360000 ;
+ RECT 337.120000 324.440000 338.220000 324.920000 ;
+ RECT 292.120000 335.320000 293.220000 335.800000 ;
+ RECT 292.120000 329.880000 293.220000 330.360000 ;
+ RECT 292.120000 324.440000 293.220000 324.920000 ;
+ RECT 337.120000 308.120000 338.220000 308.600000 ;
+ RECT 337.120000 302.680000 338.220000 303.160000 ;
+ RECT 337.120000 297.240000 338.220000 297.720000 ;
+ RECT 337.120000 313.560000 338.220000 314.040000 ;
+ RECT 337.120000 319.000000 338.220000 319.480000 ;
+ RECT 292.120000 319.000000 293.220000 319.480000 ;
+ RECT 292.120000 308.120000 293.220000 308.600000 ;
+ RECT 292.120000 302.680000 293.220000 303.160000 ;
+ RECT 292.120000 297.240000 293.220000 297.720000 ;
+ RECT 292.120000 313.560000 293.220000 314.040000 ;
+ RECT 247.120000 335.320000 248.220000 335.800000 ;
+ RECT 242.990000 335.320000 243.990000 335.800000 ;
+ RECT 242.990000 329.880000 243.990000 330.360000 ;
+ RECT 247.120000 329.880000 248.220000 330.360000 ;
+ RECT 247.120000 324.440000 248.220000 324.920000 ;
+ RECT 242.990000 324.440000 243.990000 324.920000 ;
+ RECT 247.120000 319.000000 248.220000 319.480000 ;
+ RECT 242.990000 319.000000 243.990000 319.480000 ;
+ RECT 247.120000 313.560000 248.220000 314.040000 ;
+ RECT 242.990000 313.560000 243.990000 314.040000 ;
+ RECT 247.120000 302.680000 248.220000 303.160000 ;
+ RECT 242.990000 302.680000 243.990000 303.160000 ;
+ RECT 247.120000 297.240000 248.220000 297.720000 ;
+ RECT 242.990000 297.240000 243.990000 297.720000 ;
+ RECT 247.120000 308.120000 248.220000 308.600000 ;
+ RECT 242.990000 308.120000 243.990000 308.600000 ;
+ RECT 337.120000 291.800000 338.220000 292.280000 ;
+ RECT 337.120000 286.360000 338.220000 286.840000 ;
+ RECT 337.120000 280.920000 338.220000 281.400000 ;
+ RECT 337.120000 275.480000 338.220000 275.960000 ;
+ RECT 292.120000 291.800000 293.220000 292.280000 ;
+ RECT 292.120000 286.360000 293.220000 286.840000 ;
+ RECT 292.120000 280.920000 293.220000 281.400000 ;
+ RECT 292.120000 275.480000 293.220000 275.960000 ;
+ RECT 337.120000 264.600000 338.220000 265.080000 ;
+ RECT 337.120000 248.280000 338.220000 248.760000 ;
+ RECT 337.120000 253.720000 338.220000 254.200000 ;
+ RECT 337.120000 259.160000 338.220000 259.640000 ;
+ RECT 337.120000 270.040000 338.220000 270.520000 ;
+ RECT 292.120000 248.280000 293.220000 248.760000 ;
+ RECT 292.120000 253.720000 293.220000 254.200000 ;
+ RECT 292.120000 259.160000 293.220000 259.640000 ;
+ RECT 292.120000 264.600000 293.220000 265.080000 ;
+ RECT 292.120000 270.040000 293.220000 270.520000 ;
+ RECT 247.120000 291.800000 248.220000 292.280000 ;
+ RECT 242.990000 291.800000 243.990000 292.280000 ;
+ RECT 247.120000 286.360000 248.220000 286.840000 ;
+ RECT 242.990000 286.360000 243.990000 286.840000 ;
+ RECT 247.120000 280.920000 248.220000 281.400000 ;
+ RECT 242.990000 280.920000 243.990000 281.400000 ;
+ RECT 247.120000 275.480000 248.220000 275.960000 ;
+ RECT 242.990000 275.480000 243.990000 275.960000 ;
+ RECT 247.120000 270.040000 248.220000 270.520000 ;
+ RECT 247.120000 264.600000 248.220000 265.080000 ;
+ RECT 242.990000 270.040000 243.990000 270.520000 ;
+ RECT 242.990000 264.600000 243.990000 265.080000 ;
+ RECT 247.120000 259.160000 248.220000 259.640000 ;
+ RECT 242.990000 259.160000 243.990000 259.640000 ;
+ RECT 247.120000 253.720000 248.220000 254.200000 ;
+ RECT 242.990000 253.720000 243.990000 254.200000 ;
+ RECT 247.120000 248.280000 248.220000 248.760000 ;
+ RECT 242.990000 248.280000 243.990000 248.760000 ;
+ RECT 427.120000 242.840000 428.220000 243.320000 ;
+ RECT 427.120000 237.400000 428.220000 237.880000 ;
+ RECT 436.430000 242.840000 437.430000 243.320000 ;
+ RECT 436.430000 237.400000 437.430000 237.880000 ;
+ RECT 436.430000 221.080000 437.430000 221.560000 ;
+ RECT 436.430000 226.520000 437.430000 227.000000 ;
+ RECT 436.430000 231.960000 437.430000 232.440000 ;
+ RECT 427.120000 231.960000 428.220000 232.440000 ;
+ RECT 427.120000 226.520000 428.220000 227.000000 ;
+ RECT 427.120000 221.080000 428.220000 221.560000 ;
+ RECT 427.120000 210.200000 428.220000 210.680000 ;
+ RECT 427.120000 215.640000 428.220000 216.120000 ;
+ RECT 436.430000 215.640000 437.430000 216.120000 ;
+ RECT 436.430000 210.200000 437.430000 210.680000 ;
+ RECT 436.430000 199.320000 437.430000 199.800000 ;
+ RECT 436.430000 204.760000 437.430000 205.240000 ;
+ RECT 427.120000 199.320000 428.220000 199.800000 ;
+ RECT 427.120000 204.760000 428.220000 205.240000 ;
+ RECT 382.120000 242.840000 383.220000 243.320000 ;
+ RECT 382.120000 237.400000 383.220000 237.880000 ;
+ RECT 382.120000 231.960000 383.220000 232.440000 ;
+ RECT 382.120000 226.520000 383.220000 227.000000 ;
+ RECT 382.120000 221.080000 383.220000 221.560000 ;
+ RECT 382.120000 199.320000 383.220000 199.800000 ;
+ RECT 382.120000 204.760000 383.220000 205.240000 ;
+ RECT 382.120000 210.200000 383.220000 210.680000 ;
+ RECT 382.120000 215.640000 383.220000 216.120000 ;
+ RECT 427.120000 193.880000 428.220000 194.360000 ;
+ RECT 427.120000 188.440000 428.220000 188.920000 ;
+ RECT 436.430000 193.880000 437.430000 194.360000 ;
+ RECT 436.430000 188.440000 437.430000 188.920000 ;
+ RECT 427.120000 177.560000 428.220000 178.040000 ;
+ RECT 427.120000 172.120000 428.220000 172.600000 ;
+ RECT 436.430000 177.560000 437.430000 178.040000 ;
+ RECT 436.430000 172.120000 437.430000 172.600000 ;
+ RECT 427.120000 183.000000 428.220000 183.480000 ;
+ RECT 436.430000 183.000000 437.430000 183.480000 ;
+ RECT 436.430000 161.240000 437.430000 161.720000 ;
+ RECT 436.430000 166.680000 437.430000 167.160000 ;
+ RECT 427.120000 166.680000 428.220000 167.160000 ;
+ RECT 427.120000 161.240000 428.220000 161.720000 ;
+ RECT 427.120000 155.800000 428.220000 156.280000 ;
+ RECT 427.120000 150.360000 428.220000 150.840000 ;
+ RECT 436.430000 155.800000 437.430000 156.280000 ;
+ RECT 436.430000 150.360000 437.430000 150.840000 ;
+ RECT 382.120000 193.880000 383.220000 194.360000 ;
+ RECT 382.120000 188.440000 383.220000 188.920000 ;
+ RECT 382.120000 183.000000 383.220000 183.480000 ;
+ RECT 382.120000 177.560000 383.220000 178.040000 ;
+ RECT 382.120000 172.120000 383.220000 172.600000 ;
+ RECT 382.120000 166.680000 383.220000 167.160000 ;
+ RECT 382.120000 161.240000 383.220000 161.720000 ;
+ RECT 382.120000 155.800000 383.220000 156.280000 ;
+ RECT 382.120000 150.360000 383.220000 150.840000 ;
+ RECT 337.120000 242.840000 338.220000 243.320000 ;
+ RECT 337.120000 237.400000 338.220000 237.880000 ;
+ RECT 337.120000 231.960000 338.220000 232.440000 ;
+ RECT 337.120000 226.520000 338.220000 227.000000 ;
+ RECT 337.120000 221.080000 338.220000 221.560000 ;
+ RECT 292.120000 242.840000 293.220000 243.320000 ;
+ RECT 292.120000 237.400000 293.220000 237.880000 ;
+ RECT 292.120000 231.960000 293.220000 232.440000 ;
+ RECT 292.120000 226.520000 293.220000 227.000000 ;
+ RECT 292.120000 221.080000 293.220000 221.560000 ;
+ RECT 337.120000 215.640000 338.220000 216.120000 ;
+ RECT 337.120000 210.200000 338.220000 210.680000 ;
+ RECT 337.120000 204.760000 338.220000 205.240000 ;
+ RECT 337.120000 199.320000 338.220000 199.800000 ;
+ RECT 292.120000 210.200000 293.220000 210.680000 ;
+ RECT 292.120000 204.760000 293.220000 205.240000 ;
+ RECT 292.120000 199.320000 293.220000 199.800000 ;
+ RECT 292.120000 215.640000 293.220000 216.120000 ;
+ RECT 247.120000 242.840000 248.220000 243.320000 ;
+ RECT 242.990000 242.840000 243.990000 243.320000 ;
+ RECT 247.120000 237.400000 248.220000 237.880000 ;
+ RECT 242.990000 237.400000 243.990000 237.880000 ;
+ RECT 247.120000 231.960000 248.220000 232.440000 ;
+ RECT 242.990000 231.960000 243.990000 232.440000 ;
+ RECT 247.120000 221.080000 248.220000 221.560000 ;
+ RECT 242.990000 221.080000 243.990000 221.560000 ;
+ RECT 242.990000 226.520000 243.990000 227.000000 ;
+ RECT 247.120000 226.520000 248.220000 227.000000 ;
+ RECT 247.120000 215.640000 248.220000 216.120000 ;
+ RECT 242.990000 215.640000 243.990000 216.120000 ;
+ RECT 247.120000 210.200000 248.220000 210.680000 ;
+ RECT 242.990000 210.200000 243.990000 210.680000 ;
+ RECT 247.120000 204.760000 248.220000 205.240000 ;
+ RECT 242.990000 204.760000 243.990000 205.240000 ;
+ RECT 247.120000 199.320000 248.220000 199.800000 ;
+ RECT 242.990000 199.320000 243.990000 199.800000 ;
+ RECT 337.120000 193.880000 338.220000 194.360000 ;
+ RECT 337.120000 188.440000 338.220000 188.920000 ;
+ RECT 337.120000 183.000000 338.220000 183.480000 ;
+ RECT 337.120000 177.560000 338.220000 178.040000 ;
+ RECT 337.120000 172.120000 338.220000 172.600000 ;
+ RECT 292.120000 193.880000 293.220000 194.360000 ;
+ RECT 292.120000 188.440000 293.220000 188.920000 ;
+ RECT 292.120000 183.000000 293.220000 183.480000 ;
+ RECT 292.120000 177.560000 293.220000 178.040000 ;
+ RECT 292.120000 172.120000 293.220000 172.600000 ;
+ RECT 337.120000 150.360000 338.220000 150.840000 ;
+ RECT 337.120000 155.800000 338.220000 156.280000 ;
+ RECT 337.120000 161.240000 338.220000 161.720000 ;
+ RECT 337.120000 166.680000 338.220000 167.160000 ;
+ RECT 292.120000 150.360000 293.220000 150.840000 ;
+ RECT 292.120000 155.800000 293.220000 156.280000 ;
+ RECT 292.120000 161.240000 293.220000 161.720000 ;
+ RECT 292.120000 166.680000 293.220000 167.160000 ;
+ RECT 247.120000 193.880000 248.220000 194.360000 ;
+ RECT 242.990000 193.880000 243.990000 194.360000 ;
+ RECT 247.120000 188.440000 248.220000 188.920000 ;
+ RECT 242.990000 188.440000 243.990000 188.920000 ;
+ RECT 247.120000 177.560000 248.220000 178.040000 ;
+ RECT 242.990000 177.560000 243.990000 178.040000 ;
+ RECT 247.120000 172.120000 248.220000 172.600000 ;
+ RECT 242.990000 172.120000 243.990000 172.600000 ;
+ RECT 247.120000 183.000000 248.220000 183.480000 ;
+ RECT 242.990000 183.000000 243.990000 183.480000 ;
+ RECT 247.120000 166.680000 248.220000 167.160000 ;
+ RECT 242.990000 166.680000 243.990000 167.160000 ;
+ RECT 247.120000 161.240000 248.220000 161.720000 ;
+ RECT 242.990000 161.240000 243.990000 161.720000 ;
+ RECT 247.120000 155.800000 248.220000 156.280000 ;
+ RECT 247.120000 150.360000 248.220000 150.840000 ;
+ RECT 242.990000 155.800000 243.990000 156.280000 ;
+ RECT 242.990000 150.360000 243.990000 150.840000 ;
+ RECT 240.160000 340.720000 440.260000 341.720000 ;
+ RECT 240.160000 148.350000 440.260000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 145.500000 243.990000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 344.760000 243.990000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 145.500000 437.430000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 344.760000 437.430000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 148.350000 241.160000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 148.350000 440.260000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 340.720000 241.160000 341.720000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 340.720000 440.260000 341.720000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 115.240000 243.990000 145.500000 ;
+ RECT 436.430000 115.240000 437.430000 145.500000 ;
+ RECT 247.120000 118.090000 248.220000 142.140000 ;
+ RECT 292.120000 118.090000 293.220000 142.140000 ;
+ RECT 337.120000 118.090000 338.220000 142.140000 ;
+ RECT 382.120000 118.090000 383.220000 142.140000 ;
+ RECT 427.120000 118.090000 428.220000 142.140000 ;
+ LAYER met3 ;
+ RECT 436.430000 130.980000 437.430000 131.460000 ;
+ RECT 436.430000 136.420000 437.430000 136.900000 ;
+ RECT 427.120000 136.420000 428.220000 136.900000 ;
+ RECT 427.120000 130.980000 428.220000 131.460000 ;
+ RECT 382.120000 130.980000 383.220000 131.460000 ;
+ RECT 382.120000 136.420000 383.220000 136.900000 ;
+ RECT 292.120000 130.980000 293.220000 131.460000 ;
+ RECT 337.120000 130.980000 338.220000 131.460000 ;
+ RECT 337.120000 136.420000 338.220000 136.900000 ;
+ RECT 292.120000 136.420000 293.220000 136.900000 ;
+ RECT 242.990000 130.980000 243.990000 131.460000 ;
+ RECT 247.120000 130.980000 248.220000 131.460000 ;
+ RECT 247.120000 136.420000 248.220000 136.900000 ;
+ RECT 242.990000 136.420000 243.990000 136.900000 ;
+ RECT 436.430000 120.100000 437.430000 120.580000 ;
+ RECT 436.430000 125.540000 437.430000 126.020000 ;
+ RECT 427.120000 125.540000 428.220000 126.020000 ;
+ RECT 427.120000 120.100000 428.220000 120.580000 ;
+ RECT 382.120000 120.100000 383.220000 120.580000 ;
+ RECT 382.120000 125.540000 383.220000 126.020000 ;
+ RECT 292.120000 120.100000 293.220000 120.580000 ;
+ RECT 337.120000 120.100000 338.220000 120.580000 ;
+ RECT 337.120000 125.540000 338.220000 126.020000 ;
+ RECT 292.120000 125.540000 293.220000 126.020000 ;
+ RECT 242.990000 125.540000 243.990000 126.020000 ;
+ RECT 247.120000 125.540000 248.220000 126.020000 ;
+ RECT 242.990000 120.100000 243.990000 120.580000 ;
+ RECT 247.120000 120.100000 248.220000 120.580000 ;
+ RECT 240.160000 141.140000 440.260000 142.140000 ;
+ RECT 240.160000 118.090000 440.260000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 118.090000 241.160000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 118.090000 440.260000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 141.140000 241.160000 142.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 141.140000 440.260000 142.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 115.240000 243.990000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 144.500000 243.990000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 115.240000 437.430000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 144.500000 437.430000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 3152.250000 428.220000 3345.620000 ;
+ RECT 382.120000 3152.250000 383.220000 3345.620000 ;
+ RECT 436.430000 3149.400000 437.430000 3349.660000 ;
+ RECT 337.120000 3152.250000 338.220000 3345.620000 ;
+ RECT 292.120000 3152.250000 293.220000 3345.620000 ;
+ RECT 247.120000 3152.250000 248.220000 3345.620000 ;
+ RECT 242.990000 3149.400000 243.990000 3349.660000 ;
+ LAYER met3 ;
+ RECT 427.120000 3339.220000 428.220000 3339.700000 ;
+ RECT 436.430000 3339.220000 437.430000 3339.700000 ;
+ RECT 436.430000 3328.340000 437.430000 3328.820000 ;
+ RECT 436.430000 3333.780000 437.430000 3334.260000 ;
+ RECT 427.120000 3333.780000 428.220000 3334.260000 ;
+ RECT 427.120000 3328.340000 428.220000 3328.820000 ;
+ RECT 427.120000 3322.900000 428.220000 3323.380000 ;
+ RECT 427.120000 3317.460000 428.220000 3317.940000 ;
+ RECT 436.430000 3322.900000 437.430000 3323.380000 ;
+ RECT 436.430000 3317.460000 437.430000 3317.940000 ;
+ RECT 427.120000 3301.140000 428.220000 3301.620000 ;
+ RECT 427.120000 3306.580000 428.220000 3307.060000 ;
+ RECT 436.430000 3306.580000 437.430000 3307.060000 ;
+ RECT 436.430000 3301.140000 437.430000 3301.620000 ;
+ RECT 427.120000 3312.020000 428.220000 3312.500000 ;
+ RECT 436.430000 3312.020000 437.430000 3312.500000 ;
+ RECT 382.120000 3339.220000 383.220000 3339.700000 ;
+ RECT 382.120000 3333.780000 383.220000 3334.260000 ;
+ RECT 382.120000 3328.340000 383.220000 3328.820000 ;
+ RECT 382.120000 3322.900000 383.220000 3323.380000 ;
+ RECT 382.120000 3301.140000 383.220000 3301.620000 ;
+ RECT 382.120000 3306.580000 383.220000 3307.060000 ;
+ RECT 382.120000 3312.020000 383.220000 3312.500000 ;
+ RECT 382.120000 3317.460000 383.220000 3317.940000 ;
+ RECT 436.430000 3290.260000 437.430000 3290.740000 ;
+ RECT 436.430000 3295.700000 437.430000 3296.180000 ;
+ RECT 427.120000 3295.700000 428.220000 3296.180000 ;
+ RECT 427.120000 3290.260000 428.220000 3290.740000 ;
+ RECT 427.120000 3284.820000 428.220000 3285.300000 ;
+ RECT 427.120000 3279.380000 428.220000 3279.860000 ;
+ RECT 436.430000 3284.820000 437.430000 3285.300000 ;
+ RECT 436.430000 3279.380000 437.430000 3279.860000 ;
+ RECT 436.430000 3263.060000 437.430000 3263.540000 ;
+ RECT 436.430000 3268.500000 437.430000 3268.980000 ;
+ RECT 436.430000 3273.940000 437.430000 3274.420000 ;
+ RECT 427.120000 3268.500000 428.220000 3268.980000 ;
+ RECT 427.120000 3263.060000 428.220000 3263.540000 ;
+ RECT 427.120000 3273.940000 428.220000 3274.420000 ;
+ RECT 427.120000 3257.620000 428.220000 3258.100000 ;
+ RECT 427.120000 3252.180000 428.220000 3252.660000 ;
+ RECT 436.430000 3257.620000 437.430000 3258.100000 ;
+ RECT 436.430000 3252.180000 437.430000 3252.660000 ;
+ RECT 382.120000 3295.700000 383.220000 3296.180000 ;
+ RECT 382.120000 3290.260000 383.220000 3290.740000 ;
+ RECT 382.120000 3284.820000 383.220000 3285.300000 ;
+ RECT 382.120000 3279.380000 383.220000 3279.860000 ;
+ RECT 382.120000 3268.500000 383.220000 3268.980000 ;
+ RECT 382.120000 3263.060000 383.220000 3263.540000 ;
+ RECT 382.120000 3257.620000 383.220000 3258.100000 ;
+ RECT 382.120000 3252.180000 383.220000 3252.660000 ;
+ RECT 382.120000 3273.940000 383.220000 3274.420000 ;
+ RECT 337.120000 3339.220000 338.220000 3339.700000 ;
+ RECT 337.120000 3333.780000 338.220000 3334.260000 ;
+ RECT 337.120000 3328.340000 338.220000 3328.820000 ;
+ RECT 292.120000 3339.220000 293.220000 3339.700000 ;
+ RECT 292.120000 3333.780000 293.220000 3334.260000 ;
+ RECT 292.120000 3328.340000 293.220000 3328.820000 ;
+ RECT 337.120000 3312.020000 338.220000 3312.500000 ;
+ RECT 337.120000 3306.580000 338.220000 3307.060000 ;
+ RECT 337.120000 3301.140000 338.220000 3301.620000 ;
+ RECT 337.120000 3317.460000 338.220000 3317.940000 ;
+ RECT 337.120000 3322.900000 338.220000 3323.380000 ;
+ RECT 292.120000 3322.900000 293.220000 3323.380000 ;
+ RECT 292.120000 3312.020000 293.220000 3312.500000 ;
+ RECT 292.120000 3306.580000 293.220000 3307.060000 ;
+ RECT 292.120000 3301.140000 293.220000 3301.620000 ;
+ RECT 292.120000 3317.460000 293.220000 3317.940000 ;
+ RECT 247.120000 3339.220000 248.220000 3339.700000 ;
+ RECT 242.990000 3339.220000 243.990000 3339.700000 ;
+ RECT 242.990000 3333.780000 243.990000 3334.260000 ;
+ RECT 247.120000 3333.780000 248.220000 3334.260000 ;
+ RECT 247.120000 3328.340000 248.220000 3328.820000 ;
+ RECT 242.990000 3328.340000 243.990000 3328.820000 ;
+ RECT 247.120000 3322.900000 248.220000 3323.380000 ;
+ RECT 242.990000 3322.900000 243.990000 3323.380000 ;
+ RECT 247.120000 3317.460000 248.220000 3317.940000 ;
+ RECT 242.990000 3317.460000 243.990000 3317.940000 ;
+ RECT 247.120000 3306.580000 248.220000 3307.060000 ;
+ RECT 242.990000 3306.580000 243.990000 3307.060000 ;
+ RECT 247.120000 3301.140000 248.220000 3301.620000 ;
+ RECT 242.990000 3301.140000 243.990000 3301.620000 ;
+ RECT 247.120000 3312.020000 248.220000 3312.500000 ;
+ RECT 242.990000 3312.020000 243.990000 3312.500000 ;
+ RECT 337.120000 3295.700000 338.220000 3296.180000 ;
+ RECT 337.120000 3290.260000 338.220000 3290.740000 ;
+ RECT 337.120000 3284.820000 338.220000 3285.300000 ;
+ RECT 337.120000 3279.380000 338.220000 3279.860000 ;
+ RECT 292.120000 3295.700000 293.220000 3296.180000 ;
+ RECT 292.120000 3290.260000 293.220000 3290.740000 ;
+ RECT 292.120000 3284.820000 293.220000 3285.300000 ;
+ RECT 292.120000 3279.380000 293.220000 3279.860000 ;
+ RECT 337.120000 3268.500000 338.220000 3268.980000 ;
+ RECT 337.120000 3252.180000 338.220000 3252.660000 ;
+ RECT 337.120000 3257.620000 338.220000 3258.100000 ;
+ RECT 337.120000 3263.060000 338.220000 3263.540000 ;
+ RECT 337.120000 3273.940000 338.220000 3274.420000 ;
+ RECT 292.120000 3252.180000 293.220000 3252.660000 ;
+ RECT 292.120000 3257.620000 293.220000 3258.100000 ;
+ RECT 292.120000 3263.060000 293.220000 3263.540000 ;
+ RECT 292.120000 3268.500000 293.220000 3268.980000 ;
+ RECT 292.120000 3273.940000 293.220000 3274.420000 ;
+ RECT 247.120000 3295.700000 248.220000 3296.180000 ;
+ RECT 242.990000 3295.700000 243.990000 3296.180000 ;
+ RECT 247.120000 3290.260000 248.220000 3290.740000 ;
+ RECT 242.990000 3290.260000 243.990000 3290.740000 ;
+ RECT 247.120000 3284.820000 248.220000 3285.300000 ;
+ RECT 242.990000 3284.820000 243.990000 3285.300000 ;
+ RECT 247.120000 3279.380000 248.220000 3279.860000 ;
+ RECT 242.990000 3279.380000 243.990000 3279.860000 ;
+ RECT 247.120000 3273.940000 248.220000 3274.420000 ;
+ RECT 247.120000 3268.500000 248.220000 3268.980000 ;
+ RECT 242.990000 3273.940000 243.990000 3274.420000 ;
+ RECT 242.990000 3268.500000 243.990000 3268.980000 ;
+ RECT 247.120000 3263.060000 248.220000 3263.540000 ;
+ RECT 242.990000 3263.060000 243.990000 3263.540000 ;
+ RECT 247.120000 3257.620000 248.220000 3258.100000 ;
+ RECT 242.990000 3257.620000 243.990000 3258.100000 ;
+ RECT 247.120000 3252.180000 248.220000 3252.660000 ;
+ RECT 242.990000 3252.180000 243.990000 3252.660000 ;
+ RECT 427.120000 3246.740000 428.220000 3247.220000 ;
+ RECT 427.120000 3241.300000 428.220000 3241.780000 ;
+ RECT 436.430000 3246.740000 437.430000 3247.220000 ;
+ RECT 436.430000 3241.300000 437.430000 3241.780000 ;
+ RECT 436.430000 3224.980000 437.430000 3225.460000 ;
+ RECT 436.430000 3230.420000 437.430000 3230.900000 ;
+ RECT 436.430000 3235.860000 437.430000 3236.340000 ;
+ RECT 427.120000 3235.860000 428.220000 3236.340000 ;
+ RECT 427.120000 3230.420000 428.220000 3230.900000 ;
+ RECT 427.120000 3224.980000 428.220000 3225.460000 ;
+ RECT 427.120000 3214.100000 428.220000 3214.580000 ;
+ RECT 427.120000 3219.540000 428.220000 3220.020000 ;
+ RECT 436.430000 3219.540000 437.430000 3220.020000 ;
+ RECT 436.430000 3214.100000 437.430000 3214.580000 ;
+ RECT 436.430000 3203.220000 437.430000 3203.700000 ;
+ RECT 436.430000 3208.660000 437.430000 3209.140000 ;
+ RECT 427.120000 3203.220000 428.220000 3203.700000 ;
+ RECT 427.120000 3208.660000 428.220000 3209.140000 ;
+ RECT 382.120000 3246.740000 383.220000 3247.220000 ;
+ RECT 382.120000 3241.300000 383.220000 3241.780000 ;
+ RECT 382.120000 3235.860000 383.220000 3236.340000 ;
+ RECT 382.120000 3230.420000 383.220000 3230.900000 ;
+ RECT 382.120000 3224.980000 383.220000 3225.460000 ;
+ RECT 382.120000 3203.220000 383.220000 3203.700000 ;
+ RECT 382.120000 3208.660000 383.220000 3209.140000 ;
+ RECT 382.120000 3214.100000 383.220000 3214.580000 ;
+ RECT 382.120000 3219.540000 383.220000 3220.020000 ;
+ RECT 427.120000 3197.780000 428.220000 3198.260000 ;
+ RECT 427.120000 3192.340000 428.220000 3192.820000 ;
+ RECT 436.430000 3197.780000 437.430000 3198.260000 ;
+ RECT 436.430000 3192.340000 437.430000 3192.820000 ;
+ RECT 427.120000 3181.460000 428.220000 3181.940000 ;
+ RECT 427.120000 3176.020000 428.220000 3176.500000 ;
+ RECT 436.430000 3181.460000 437.430000 3181.940000 ;
+ RECT 436.430000 3176.020000 437.430000 3176.500000 ;
+ RECT 427.120000 3186.900000 428.220000 3187.380000 ;
+ RECT 436.430000 3186.900000 437.430000 3187.380000 ;
+ RECT 436.430000 3165.140000 437.430000 3165.620000 ;
+ RECT 436.430000 3170.580000 437.430000 3171.060000 ;
+ RECT 427.120000 3170.580000 428.220000 3171.060000 ;
+ RECT 427.120000 3165.140000 428.220000 3165.620000 ;
+ RECT 427.120000 3159.700000 428.220000 3160.180000 ;
+ RECT 427.120000 3154.260000 428.220000 3154.740000 ;
+ RECT 436.430000 3159.700000 437.430000 3160.180000 ;
+ RECT 436.430000 3154.260000 437.430000 3154.740000 ;
+ RECT 382.120000 3197.780000 383.220000 3198.260000 ;
+ RECT 382.120000 3192.340000 383.220000 3192.820000 ;
+ RECT 382.120000 3186.900000 383.220000 3187.380000 ;
+ RECT 382.120000 3181.460000 383.220000 3181.940000 ;
+ RECT 382.120000 3176.020000 383.220000 3176.500000 ;
+ RECT 382.120000 3170.580000 383.220000 3171.060000 ;
+ RECT 382.120000 3165.140000 383.220000 3165.620000 ;
+ RECT 382.120000 3159.700000 383.220000 3160.180000 ;
+ RECT 382.120000 3154.260000 383.220000 3154.740000 ;
+ RECT 337.120000 3246.740000 338.220000 3247.220000 ;
+ RECT 337.120000 3241.300000 338.220000 3241.780000 ;
+ RECT 337.120000 3235.860000 338.220000 3236.340000 ;
+ RECT 337.120000 3230.420000 338.220000 3230.900000 ;
+ RECT 337.120000 3224.980000 338.220000 3225.460000 ;
+ RECT 292.120000 3246.740000 293.220000 3247.220000 ;
+ RECT 292.120000 3241.300000 293.220000 3241.780000 ;
+ RECT 292.120000 3235.860000 293.220000 3236.340000 ;
+ RECT 292.120000 3230.420000 293.220000 3230.900000 ;
+ RECT 292.120000 3224.980000 293.220000 3225.460000 ;
+ RECT 337.120000 3219.540000 338.220000 3220.020000 ;
+ RECT 337.120000 3214.100000 338.220000 3214.580000 ;
+ RECT 337.120000 3208.660000 338.220000 3209.140000 ;
+ RECT 337.120000 3203.220000 338.220000 3203.700000 ;
+ RECT 292.120000 3214.100000 293.220000 3214.580000 ;
+ RECT 292.120000 3208.660000 293.220000 3209.140000 ;
+ RECT 292.120000 3203.220000 293.220000 3203.700000 ;
+ RECT 292.120000 3219.540000 293.220000 3220.020000 ;
+ RECT 247.120000 3246.740000 248.220000 3247.220000 ;
+ RECT 242.990000 3246.740000 243.990000 3247.220000 ;
+ RECT 247.120000 3241.300000 248.220000 3241.780000 ;
+ RECT 242.990000 3241.300000 243.990000 3241.780000 ;
+ RECT 247.120000 3235.860000 248.220000 3236.340000 ;
+ RECT 242.990000 3235.860000 243.990000 3236.340000 ;
+ RECT 247.120000 3224.980000 248.220000 3225.460000 ;
+ RECT 242.990000 3224.980000 243.990000 3225.460000 ;
+ RECT 242.990000 3230.420000 243.990000 3230.900000 ;
+ RECT 247.120000 3230.420000 248.220000 3230.900000 ;
+ RECT 247.120000 3219.540000 248.220000 3220.020000 ;
+ RECT 242.990000 3219.540000 243.990000 3220.020000 ;
+ RECT 247.120000 3214.100000 248.220000 3214.580000 ;
+ RECT 242.990000 3214.100000 243.990000 3214.580000 ;
+ RECT 247.120000 3208.660000 248.220000 3209.140000 ;
+ RECT 242.990000 3208.660000 243.990000 3209.140000 ;
+ RECT 247.120000 3203.220000 248.220000 3203.700000 ;
+ RECT 242.990000 3203.220000 243.990000 3203.700000 ;
+ RECT 337.120000 3197.780000 338.220000 3198.260000 ;
+ RECT 337.120000 3192.340000 338.220000 3192.820000 ;
+ RECT 337.120000 3186.900000 338.220000 3187.380000 ;
+ RECT 337.120000 3181.460000 338.220000 3181.940000 ;
+ RECT 337.120000 3176.020000 338.220000 3176.500000 ;
+ RECT 292.120000 3197.780000 293.220000 3198.260000 ;
+ RECT 292.120000 3192.340000 293.220000 3192.820000 ;
+ RECT 292.120000 3186.900000 293.220000 3187.380000 ;
+ RECT 292.120000 3181.460000 293.220000 3181.940000 ;
+ RECT 292.120000 3176.020000 293.220000 3176.500000 ;
+ RECT 337.120000 3154.260000 338.220000 3154.740000 ;
+ RECT 337.120000 3159.700000 338.220000 3160.180000 ;
+ RECT 337.120000 3165.140000 338.220000 3165.620000 ;
+ RECT 337.120000 3170.580000 338.220000 3171.060000 ;
+ RECT 292.120000 3154.260000 293.220000 3154.740000 ;
+ RECT 292.120000 3159.700000 293.220000 3160.180000 ;
+ RECT 292.120000 3165.140000 293.220000 3165.620000 ;
+ RECT 292.120000 3170.580000 293.220000 3171.060000 ;
+ RECT 247.120000 3197.780000 248.220000 3198.260000 ;
+ RECT 242.990000 3197.780000 243.990000 3198.260000 ;
+ RECT 247.120000 3192.340000 248.220000 3192.820000 ;
+ RECT 242.990000 3192.340000 243.990000 3192.820000 ;
+ RECT 247.120000 3181.460000 248.220000 3181.940000 ;
+ RECT 242.990000 3181.460000 243.990000 3181.940000 ;
+ RECT 247.120000 3176.020000 248.220000 3176.500000 ;
+ RECT 242.990000 3176.020000 243.990000 3176.500000 ;
+ RECT 247.120000 3186.900000 248.220000 3187.380000 ;
+ RECT 242.990000 3186.900000 243.990000 3187.380000 ;
+ RECT 247.120000 3170.580000 248.220000 3171.060000 ;
+ RECT 242.990000 3170.580000 243.990000 3171.060000 ;
+ RECT 247.120000 3165.140000 248.220000 3165.620000 ;
+ RECT 242.990000 3165.140000 243.990000 3165.620000 ;
+ RECT 247.120000 3159.700000 248.220000 3160.180000 ;
+ RECT 247.120000 3154.260000 248.220000 3154.740000 ;
+ RECT 242.990000 3159.700000 243.990000 3160.180000 ;
+ RECT 242.990000 3154.260000 243.990000 3154.740000 ;
+ RECT 240.160000 3344.620000 440.260000 3345.620000 ;
+ RECT 240.160000 3152.250000 440.260000 3153.250000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 3149.400000 243.990000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 3348.660000 243.990000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 3149.400000 437.430000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 3348.660000 437.430000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 3152.250000 241.160000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 3152.250000 440.260000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 3344.620000 241.160000 3345.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 3344.620000 440.260000 3345.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 2951.990000 428.220000 3145.360000 ;
+ RECT 382.120000 2951.990000 383.220000 3145.360000 ;
+ RECT 436.430000 2949.140000 437.430000 3149.400000 ;
+ RECT 337.120000 2951.990000 338.220000 3145.360000 ;
+ RECT 292.120000 2951.990000 293.220000 3145.360000 ;
+ RECT 247.120000 2951.990000 248.220000 3145.360000 ;
+ RECT 242.990000 2949.140000 243.990000 3149.400000 ;
+ LAYER met3 ;
+ RECT 427.120000 3138.960000 428.220000 3139.440000 ;
+ RECT 436.430000 3138.960000 437.430000 3139.440000 ;
+ RECT 436.430000 3128.080000 437.430000 3128.560000 ;
+ RECT 436.430000 3133.520000 437.430000 3134.000000 ;
+ RECT 427.120000 3133.520000 428.220000 3134.000000 ;
+ RECT 427.120000 3128.080000 428.220000 3128.560000 ;
+ RECT 427.120000 3122.640000 428.220000 3123.120000 ;
+ RECT 427.120000 3117.200000 428.220000 3117.680000 ;
+ RECT 436.430000 3122.640000 437.430000 3123.120000 ;
+ RECT 436.430000 3117.200000 437.430000 3117.680000 ;
+ RECT 427.120000 3100.880000 428.220000 3101.360000 ;
+ RECT 427.120000 3106.320000 428.220000 3106.800000 ;
+ RECT 436.430000 3106.320000 437.430000 3106.800000 ;
+ RECT 436.430000 3100.880000 437.430000 3101.360000 ;
+ RECT 427.120000 3111.760000 428.220000 3112.240000 ;
+ RECT 436.430000 3111.760000 437.430000 3112.240000 ;
+ RECT 382.120000 3138.960000 383.220000 3139.440000 ;
+ RECT 382.120000 3133.520000 383.220000 3134.000000 ;
+ RECT 382.120000 3128.080000 383.220000 3128.560000 ;
+ RECT 382.120000 3122.640000 383.220000 3123.120000 ;
+ RECT 382.120000 3100.880000 383.220000 3101.360000 ;
+ RECT 382.120000 3106.320000 383.220000 3106.800000 ;
+ RECT 382.120000 3111.760000 383.220000 3112.240000 ;
+ RECT 382.120000 3117.200000 383.220000 3117.680000 ;
+ RECT 436.430000 3090.000000 437.430000 3090.480000 ;
+ RECT 436.430000 3095.440000 437.430000 3095.920000 ;
+ RECT 427.120000 3095.440000 428.220000 3095.920000 ;
+ RECT 427.120000 3090.000000 428.220000 3090.480000 ;
+ RECT 427.120000 3084.560000 428.220000 3085.040000 ;
+ RECT 427.120000 3079.120000 428.220000 3079.600000 ;
+ RECT 436.430000 3084.560000 437.430000 3085.040000 ;
+ RECT 436.430000 3079.120000 437.430000 3079.600000 ;
+ RECT 436.430000 3062.800000 437.430000 3063.280000 ;
+ RECT 436.430000 3068.240000 437.430000 3068.720000 ;
+ RECT 436.430000 3073.680000 437.430000 3074.160000 ;
+ RECT 427.120000 3068.240000 428.220000 3068.720000 ;
+ RECT 427.120000 3062.800000 428.220000 3063.280000 ;
+ RECT 427.120000 3073.680000 428.220000 3074.160000 ;
+ RECT 427.120000 3057.360000 428.220000 3057.840000 ;
+ RECT 427.120000 3051.920000 428.220000 3052.400000 ;
+ RECT 436.430000 3057.360000 437.430000 3057.840000 ;
+ RECT 436.430000 3051.920000 437.430000 3052.400000 ;
+ RECT 382.120000 3095.440000 383.220000 3095.920000 ;
+ RECT 382.120000 3090.000000 383.220000 3090.480000 ;
+ RECT 382.120000 3084.560000 383.220000 3085.040000 ;
+ RECT 382.120000 3079.120000 383.220000 3079.600000 ;
+ RECT 382.120000 3068.240000 383.220000 3068.720000 ;
+ RECT 382.120000 3062.800000 383.220000 3063.280000 ;
+ RECT 382.120000 3057.360000 383.220000 3057.840000 ;
+ RECT 382.120000 3051.920000 383.220000 3052.400000 ;
+ RECT 382.120000 3073.680000 383.220000 3074.160000 ;
+ RECT 337.120000 3138.960000 338.220000 3139.440000 ;
+ RECT 337.120000 3133.520000 338.220000 3134.000000 ;
+ RECT 337.120000 3128.080000 338.220000 3128.560000 ;
+ RECT 292.120000 3138.960000 293.220000 3139.440000 ;
+ RECT 292.120000 3133.520000 293.220000 3134.000000 ;
+ RECT 292.120000 3128.080000 293.220000 3128.560000 ;
+ RECT 337.120000 3111.760000 338.220000 3112.240000 ;
+ RECT 337.120000 3106.320000 338.220000 3106.800000 ;
+ RECT 337.120000 3100.880000 338.220000 3101.360000 ;
+ RECT 337.120000 3117.200000 338.220000 3117.680000 ;
+ RECT 337.120000 3122.640000 338.220000 3123.120000 ;
+ RECT 292.120000 3122.640000 293.220000 3123.120000 ;
+ RECT 292.120000 3111.760000 293.220000 3112.240000 ;
+ RECT 292.120000 3106.320000 293.220000 3106.800000 ;
+ RECT 292.120000 3100.880000 293.220000 3101.360000 ;
+ RECT 292.120000 3117.200000 293.220000 3117.680000 ;
+ RECT 247.120000 3138.960000 248.220000 3139.440000 ;
+ RECT 242.990000 3138.960000 243.990000 3139.440000 ;
+ RECT 242.990000 3133.520000 243.990000 3134.000000 ;
+ RECT 247.120000 3133.520000 248.220000 3134.000000 ;
+ RECT 247.120000 3128.080000 248.220000 3128.560000 ;
+ RECT 242.990000 3128.080000 243.990000 3128.560000 ;
+ RECT 247.120000 3122.640000 248.220000 3123.120000 ;
+ RECT 242.990000 3122.640000 243.990000 3123.120000 ;
+ RECT 247.120000 3117.200000 248.220000 3117.680000 ;
+ RECT 242.990000 3117.200000 243.990000 3117.680000 ;
+ RECT 247.120000 3106.320000 248.220000 3106.800000 ;
+ RECT 242.990000 3106.320000 243.990000 3106.800000 ;
+ RECT 247.120000 3100.880000 248.220000 3101.360000 ;
+ RECT 242.990000 3100.880000 243.990000 3101.360000 ;
+ RECT 247.120000 3111.760000 248.220000 3112.240000 ;
+ RECT 242.990000 3111.760000 243.990000 3112.240000 ;
+ RECT 337.120000 3095.440000 338.220000 3095.920000 ;
+ RECT 337.120000 3090.000000 338.220000 3090.480000 ;
+ RECT 337.120000 3084.560000 338.220000 3085.040000 ;
+ RECT 337.120000 3079.120000 338.220000 3079.600000 ;
+ RECT 292.120000 3095.440000 293.220000 3095.920000 ;
+ RECT 292.120000 3090.000000 293.220000 3090.480000 ;
+ RECT 292.120000 3084.560000 293.220000 3085.040000 ;
+ RECT 292.120000 3079.120000 293.220000 3079.600000 ;
+ RECT 337.120000 3068.240000 338.220000 3068.720000 ;
+ RECT 337.120000 3051.920000 338.220000 3052.400000 ;
+ RECT 337.120000 3057.360000 338.220000 3057.840000 ;
+ RECT 337.120000 3062.800000 338.220000 3063.280000 ;
+ RECT 337.120000 3073.680000 338.220000 3074.160000 ;
+ RECT 292.120000 3051.920000 293.220000 3052.400000 ;
+ RECT 292.120000 3057.360000 293.220000 3057.840000 ;
+ RECT 292.120000 3062.800000 293.220000 3063.280000 ;
+ RECT 292.120000 3068.240000 293.220000 3068.720000 ;
+ RECT 292.120000 3073.680000 293.220000 3074.160000 ;
+ RECT 247.120000 3095.440000 248.220000 3095.920000 ;
+ RECT 242.990000 3095.440000 243.990000 3095.920000 ;
+ RECT 247.120000 3090.000000 248.220000 3090.480000 ;
+ RECT 242.990000 3090.000000 243.990000 3090.480000 ;
+ RECT 247.120000 3084.560000 248.220000 3085.040000 ;
+ RECT 242.990000 3084.560000 243.990000 3085.040000 ;
+ RECT 247.120000 3079.120000 248.220000 3079.600000 ;
+ RECT 242.990000 3079.120000 243.990000 3079.600000 ;
+ RECT 247.120000 3073.680000 248.220000 3074.160000 ;
+ RECT 247.120000 3068.240000 248.220000 3068.720000 ;
+ RECT 242.990000 3073.680000 243.990000 3074.160000 ;
+ RECT 242.990000 3068.240000 243.990000 3068.720000 ;
+ RECT 247.120000 3062.800000 248.220000 3063.280000 ;
+ RECT 242.990000 3062.800000 243.990000 3063.280000 ;
+ RECT 247.120000 3057.360000 248.220000 3057.840000 ;
+ RECT 242.990000 3057.360000 243.990000 3057.840000 ;
+ RECT 247.120000 3051.920000 248.220000 3052.400000 ;
+ RECT 242.990000 3051.920000 243.990000 3052.400000 ;
+ RECT 427.120000 3046.480000 428.220000 3046.960000 ;
+ RECT 427.120000 3041.040000 428.220000 3041.520000 ;
+ RECT 436.430000 3046.480000 437.430000 3046.960000 ;
+ RECT 436.430000 3041.040000 437.430000 3041.520000 ;
+ RECT 436.430000 3024.720000 437.430000 3025.200000 ;
+ RECT 436.430000 3030.160000 437.430000 3030.640000 ;
+ RECT 436.430000 3035.600000 437.430000 3036.080000 ;
+ RECT 427.120000 3035.600000 428.220000 3036.080000 ;
+ RECT 427.120000 3030.160000 428.220000 3030.640000 ;
+ RECT 427.120000 3024.720000 428.220000 3025.200000 ;
+ RECT 427.120000 3013.840000 428.220000 3014.320000 ;
+ RECT 427.120000 3019.280000 428.220000 3019.760000 ;
+ RECT 436.430000 3019.280000 437.430000 3019.760000 ;
+ RECT 436.430000 3013.840000 437.430000 3014.320000 ;
+ RECT 436.430000 3002.960000 437.430000 3003.440000 ;
+ RECT 436.430000 3008.400000 437.430000 3008.880000 ;
+ RECT 427.120000 3002.960000 428.220000 3003.440000 ;
+ RECT 427.120000 3008.400000 428.220000 3008.880000 ;
+ RECT 382.120000 3046.480000 383.220000 3046.960000 ;
+ RECT 382.120000 3041.040000 383.220000 3041.520000 ;
+ RECT 382.120000 3035.600000 383.220000 3036.080000 ;
+ RECT 382.120000 3030.160000 383.220000 3030.640000 ;
+ RECT 382.120000 3024.720000 383.220000 3025.200000 ;
+ RECT 382.120000 3002.960000 383.220000 3003.440000 ;
+ RECT 382.120000 3008.400000 383.220000 3008.880000 ;
+ RECT 382.120000 3013.840000 383.220000 3014.320000 ;
+ RECT 382.120000 3019.280000 383.220000 3019.760000 ;
+ RECT 427.120000 2997.520000 428.220000 2998.000000 ;
+ RECT 427.120000 2992.080000 428.220000 2992.560000 ;
+ RECT 436.430000 2997.520000 437.430000 2998.000000 ;
+ RECT 436.430000 2992.080000 437.430000 2992.560000 ;
+ RECT 427.120000 2981.200000 428.220000 2981.680000 ;
+ RECT 427.120000 2975.760000 428.220000 2976.240000 ;
+ RECT 436.430000 2981.200000 437.430000 2981.680000 ;
+ RECT 436.430000 2975.760000 437.430000 2976.240000 ;
+ RECT 427.120000 2986.640000 428.220000 2987.120000 ;
+ RECT 436.430000 2986.640000 437.430000 2987.120000 ;
+ RECT 436.430000 2964.880000 437.430000 2965.360000 ;
+ RECT 436.430000 2970.320000 437.430000 2970.800000 ;
+ RECT 427.120000 2970.320000 428.220000 2970.800000 ;
+ RECT 427.120000 2964.880000 428.220000 2965.360000 ;
+ RECT 427.120000 2959.440000 428.220000 2959.920000 ;
+ RECT 427.120000 2954.000000 428.220000 2954.480000 ;
+ RECT 436.430000 2959.440000 437.430000 2959.920000 ;
+ RECT 436.430000 2954.000000 437.430000 2954.480000 ;
+ RECT 382.120000 2997.520000 383.220000 2998.000000 ;
+ RECT 382.120000 2992.080000 383.220000 2992.560000 ;
+ RECT 382.120000 2986.640000 383.220000 2987.120000 ;
+ RECT 382.120000 2981.200000 383.220000 2981.680000 ;
+ RECT 382.120000 2975.760000 383.220000 2976.240000 ;
+ RECT 382.120000 2970.320000 383.220000 2970.800000 ;
+ RECT 382.120000 2964.880000 383.220000 2965.360000 ;
+ RECT 382.120000 2959.440000 383.220000 2959.920000 ;
+ RECT 382.120000 2954.000000 383.220000 2954.480000 ;
+ RECT 337.120000 3046.480000 338.220000 3046.960000 ;
+ RECT 337.120000 3041.040000 338.220000 3041.520000 ;
+ RECT 337.120000 3035.600000 338.220000 3036.080000 ;
+ RECT 337.120000 3030.160000 338.220000 3030.640000 ;
+ RECT 337.120000 3024.720000 338.220000 3025.200000 ;
+ RECT 292.120000 3046.480000 293.220000 3046.960000 ;
+ RECT 292.120000 3041.040000 293.220000 3041.520000 ;
+ RECT 292.120000 3035.600000 293.220000 3036.080000 ;
+ RECT 292.120000 3030.160000 293.220000 3030.640000 ;
+ RECT 292.120000 3024.720000 293.220000 3025.200000 ;
+ RECT 337.120000 3019.280000 338.220000 3019.760000 ;
+ RECT 337.120000 3013.840000 338.220000 3014.320000 ;
+ RECT 337.120000 3008.400000 338.220000 3008.880000 ;
+ RECT 337.120000 3002.960000 338.220000 3003.440000 ;
+ RECT 292.120000 3013.840000 293.220000 3014.320000 ;
+ RECT 292.120000 3008.400000 293.220000 3008.880000 ;
+ RECT 292.120000 3002.960000 293.220000 3003.440000 ;
+ RECT 292.120000 3019.280000 293.220000 3019.760000 ;
+ RECT 247.120000 3046.480000 248.220000 3046.960000 ;
+ RECT 242.990000 3046.480000 243.990000 3046.960000 ;
+ RECT 247.120000 3041.040000 248.220000 3041.520000 ;
+ RECT 242.990000 3041.040000 243.990000 3041.520000 ;
+ RECT 247.120000 3035.600000 248.220000 3036.080000 ;
+ RECT 242.990000 3035.600000 243.990000 3036.080000 ;
+ RECT 247.120000 3024.720000 248.220000 3025.200000 ;
+ RECT 242.990000 3024.720000 243.990000 3025.200000 ;
+ RECT 242.990000 3030.160000 243.990000 3030.640000 ;
+ RECT 247.120000 3030.160000 248.220000 3030.640000 ;
+ RECT 247.120000 3019.280000 248.220000 3019.760000 ;
+ RECT 242.990000 3019.280000 243.990000 3019.760000 ;
+ RECT 247.120000 3013.840000 248.220000 3014.320000 ;
+ RECT 242.990000 3013.840000 243.990000 3014.320000 ;
+ RECT 247.120000 3008.400000 248.220000 3008.880000 ;
+ RECT 242.990000 3008.400000 243.990000 3008.880000 ;
+ RECT 247.120000 3002.960000 248.220000 3003.440000 ;
+ RECT 242.990000 3002.960000 243.990000 3003.440000 ;
+ RECT 337.120000 2997.520000 338.220000 2998.000000 ;
+ RECT 337.120000 2992.080000 338.220000 2992.560000 ;
+ RECT 337.120000 2986.640000 338.220000 2987.120000 ;
+ RECT 337.120000 2981.200000 338.220000 2981.680000 ;
+ RECT 337.120000 2975.760000 338.220000 2976.240000 ;
+ RECT 292.120000 2997.520000 293.220000 2998.000000 ;
+ RECT 292.120000 2992.080000 293.220000 2992.560000 ;
+ RECT 292.120000 2986.640000 293.220000 2987.120000 ;
+ RECT 292.120000 2981.200000 293.220000 2981.680000 ;
+ RECT 292.120000 2975.760000 293.220000 2976.240000 ;
+ RECT 337.120000 2954.000000 338.220000 2954.480000 ;
+ RECT 337.120000 2959.440000 338.220000 2959.920000 ;
+ RECT 337.120000 2964.880000 338.220000 2965.360000 ;
+ RECT 337.120000 2970.320000 338.220000 2970.800000 ;
+ RECT 292.120000 2954.000000 293.220000 2954.480000 ;
+ RECT 292.120000 2959.440000 293.220000 2959.920000 ;
+ RECT 292.120000 2964.880000 293.220000 2965.360000 ;
+ RECT 292.120000 2970.320000 293.220000 2970.800000 ;
+ RECT 247.120000 2997.520000 248.220000 2998.000000 ;
+ RECT 242.990000 2997.520000 243.990000 2998.000000 ;
+ RECT 247.120000 2992.080000 248.220000 2992.560000 ;
+ RECT 242.990000 2992.080000 243.990000 2992.560000 ;
+ RECT 247.120000 2981.200000 248.220000 2981.680000 ;
+ RECT 242.990000 2981.200000 243.990000 2981.680000 ;
+ RECT 247.120000 2975.760000 248.220000 2976.240000 ;
+ RECT 242.990000 2975.760000 243.990000 2976.240000 ;
+ RECT 247.120000 2986.640000 248.220000 2987.120000 ;
+ RECT 242.990000 2986.640000 243.990000 2987.120000 ;
+ RECT 247.120000 2970.320000 248.220000 2970.800000 ;
+ RECT 242.990000 2970.320000 243.990000 2970.800000 ;
+ RECT 247.120000 2964.880000 248.220000 2965.360000 ;
+ RECT 242.990000 2964.880000 243.990000 2965.360000 ;
+ RECT 247.120000 2959.440000 248.220000 2959.920000 ;
+ RECT 247.120000 2954.000000 248.220000 2954.480000 ;
+ RECT 242.990000 2959.440000 243.990000 2959.920000 ;
+ RECT 242.990000 2954.000000 243.990000 2954.480000 ;
+ RECT 240.160000 3144.360000 440.260000 3145.360000 ;
+ RECT 240.160000 2951.990000 440.260000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 2949.140000 243.990000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 3148.400000 243.990000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 2949.140000 437.430000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 3148.400000 437.430000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2951.990000 241.160000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2951.990000 440.260000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 3144.360000 241.160000 3145.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 3144.360000 440.260000 3145.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 2751.730000 428.220000 2945.100000 ;
+ RECT 382.120000 2751.730000 383.220000 2945.100000 ;
+ RECT 436.430000 2748.880000 437.430000 2949.140000 ;
+ RECT 337.120000 2751.730000 338.220000 2945.100000 ;
+ RECT 292.120000 2751.730000 293.220000 2945.100000 ;
+ RECT 247.120000 2751.730000 248.220000 2945.100000 ;
+ RECT 242.990000 2748.880000 243.990000 2949.140000 ;
+ LAYER met3 ;
+ RECT 427.120000 2938.700000 428.220000 2939.180000 ;
+ RECT 436.430000 2938.700000 437.430000 2939.180000 ;
+ RECT 436.430000 2927.820000 437.430000 2928.300000 ;
+ RECT 436.430000 2933.260000 437.430000 2933.740000 ;
+ RECT 427.120000 2933.260000 428.220000 2933.740000 ;
+ RECT 427.120000 2927.820000 428.220000 2928.300000 ;
+ RECT 427.120000 2922.380000 428.220000 2922.860000 ;
+ RECT 427.120000 2916.940000 428.220000 2917.420000 ;
+ RECT 436.430000 2922.380000 437.430000 2922.860000 ;
+ RECT 436.430000 2916.940000 437.430000 2917.420000 ;
+ RECT 427.120000 2900.620000 428.220000 2901.100000 ;
+ RECT 427.120000 2906.060000 428.220000 2906.540000 ;
+ RECT 436.430000 2906.060000 437.430000 2906.540000 ;
+ RECT 436.430000 2900.620000 437.430000 2901.100000 ;
+ RECT 427.120000 2911.500000 428.220000 2911.980000 ;
+ RECT 436.430000 2911.500000 437.430000 2911.980000 ;
+ RECT 382.120000 2938.700000 383.220000 2939.180000 ;
+ RECT 382.120000 2933.260000 383.220000 2933.740000 ;
+ RECT 382.120000 2927.820000 383.220000 2928.300000 ;
+ RECT 382.120000 2922.380000 383.220000 2922.860000 ;
+ RECT 382.120000 2900.620000 383.220000 2901.100000 ;
+ RECT 382.120000 2906.060000 383.220000 2906.540000 ;
+ RECT 382.120000 2911.500000 383.220000 2911.980000 ;
+ RECT 382.120000 2916.940000 383.220000 2917.420000 ;
+ RECT 436.430000 2889.740000 437.430000 2890.220000 ;
+ RECT 436.430000 2895.180000 437.430000 2895.660000 ;
+ RECT 427.120000 2895.180000 428.220000 2895.660000 ;
+ RECT 427.120000 2889.740000 428.220000 2890.220000 ;
+ RECT 427.120000 2884.300000 428.220000 2884.780000 ;
+ RECT 427.120000 2878.860000 428.220000 2879.340000 ;
+ RECT 436.430000 2884.300000 437.430000 2884.780000 ;
+ RECT 436.430000 2878.860000 437.430000 2879.340000 ;
+ RECT 436.430000 2862.540000 437.430000 2863.020000 ;
+ RECT 436.430000 2867.980000 437.430000 2868.460000 ;
+ RECT 436.430000 2873.420000 437.430000 2873.900000 ;
+ RECT 427.120000 2867.980000 428.220000 2868.460000 ;
+ RECT 427.120000 2862.540000 428.220000 2863.020000 ;
+ RECT 427.120000 2873.420000 428.220000 2873.900000 ;
+ RECT 427.120000 2857.100000 428.220000 2857.580000 ;
+ RECT 427.120000 2851.660000 428.220000 2852.140000 ;
+ RECT 436.430000 2857.100000 437.430000 2857.580000 ;
+ RECT 436.430000 2851.660000 437.430000 2852.140000 ;
+ RECT 382.120000 2895.180000 383.220000 2895.660000 ;
+ RECT 382.120000 2889.740000 383.220000 2890.220000 ;
+ RECT 382.120000 2884.300000 383.220000 2884.780000 ;
+ RECT 382.120000 2878.860000 383.220000 2879.340000 ;
+ RECT 382.120000 2867.980000 383.220000 2868.460000 ;
+ RECT 382.120000 2862.540000 383.220000 2863.020000 ;
+ RECT 382.120000 2857.100000 383.220000 2857.580000 ;
+ RECT 382.120000 2851.660000 383.220000 2852.140000 ;
+ RECT 382.120000 2873.420000 383.220000 2873.900000 ;
+ RECT 337.120000 2938.700000 338.220000 2939.180000 ;
+ RECT 337.120000 2933.260000 338.220000 2933.740000 ;
+ RECT 337.120000 2927.820000 338.220000 2928.300000 ;
+ RECT 292.120000 2938.700000 293.220000 2939.180000 ;
+ RECT 292.120000 2933.260000 293.220000 2933.740000 ;
+ RECT 292.120000 2927.820000 293.220000 2928.300000 ;
+ RECT 337.120000 2911.500000 338.220000 2911.980000 ;
+ RECT 337.120000 2906.060000 338.220000 2906.540000 ;
+ RECT 337.120000 2900.620000 338.220000 2901.100000 ;
+ RECT 337.120000 2916.940000 338.220000 2917.420000 ;
+ RECT 337.120000 2922.380000 338.220000 2922.860000 ;
+ RECT 292.120000 2922.380000 293.220000 2922.860000 ;
+ RECT 292.120000 2911.500000 293.220000 2911.980000 ;
+ RECT 292.120000 2906.060000 293.220000 2906.540000 ;
+ RECT 292.120000 2900.620000 293.220000 2901.100000 ;
+ RECT 292.120000 2916.940000 293.220000 2917.420000 ;
+ RECT 247.120000 2938.700000 248.220000 2939.180000 ;
+ RECT 242.990000 2938.700000 243.990000 2939.180000 ;
+ RECT 242.990000 2933.260000 243.990000 2933.740000 ;
+ RECT 247.120000 2933.260000 248.220000 2933.740000 ;
+ RECT 247.120000 2927.820000 248.220000 2928.300000 ;
+ RECT 242.990000 2927.820000 243.990000 2928.300000 ;
+ RECT 247.120000 2922.380000 248.220000 2922.860000 ;
+ RECT 242.990000 2922.380000 243.990000 2922.860000 ;
+ RECT 247.120000 2916.940000 248.220000 2917.420000 ;
+ RECT 242.990000 2916.940000 243.990000 2917.420000 ;
+ RECT 247.120000 2906.060000 248.220000 2906.540000 ;
+ RECT 242.990000 2906.060000 243.990000 2906.540000 ;
+ RECT 247.120000 2900.620000 248.220000 2901.100000 ;
+ RECT 242.990000 2900.620000 243.990000 2901.100000 ;
+ RECT 247.120000 2911.500000 248.220000 2911.980000 ;
+ RECT 242.990000 2911.500000 243.990000 2911.980000 ;
+ RECT 337.120000 2895.180000 338.220000 2895.660000 ;
+ RECT 337.120000 2889.740000 338.220000 2890.220000 ;
+ RECT 337.120000 2884.300000 338.220000 2884.780000 ;
+ RECT 337.120000 2878.860000 338.220000 2879.340000 ;
+ RECT 292.120000 2895.180000 293.220000 2895.660000 ;
+ RECT 292.120000 2889.740000 293.220000 2890.220000 ;
+ RECT 292.120000 2884.300000 293.220000 2884.780000 ;
+ RECT 292.120000 2878.860000 293.220000 2879.340000 ;
+ RECT 337.120000 2867.980000 338.220000 2868.460000 ;
+ RECT 337.120000 2851.660000 338.220000 2852.140000 ;
+ RECT 337.120000 2857.100000 338.220000 2857.580000 ;
+ RECT 337.120000 2862.540000 338.220000 2863.020000 ;
+ RECT 337.120000 2873.420000 338.220000 2873.900000 ;
+ RECT 292.120000 2851.660000 293.220000 2852.140000 ;
+ RECT 292.120000 2857.100000 293.220000 2857.580000 ;
+ RECT 292.120000 2862.540000 293.220000 2863.020000 ;
+ RECT 292.120000 2867.980000 293.220000 2868.460000 ;
+ RECT 292.120000 2873.420000 293.220000 2873.900000 ;
+ RECT 247.120000 2895.180000 248.220000 2895.660000 ;
+ RECT 242.990000 2895.180000 243.990000 2895.660000 ;
+ RECT 247.120000 2889.740000 248.220000 2890.220000 ;
+ RECT 242.990000 2889.740000 243.990000 2890.220000 ;
+ RECT 247.120000 2884.300000 248.220000 2884.780000 ;
+ RECT 242.990000 2884.300000 243.990000 2884.780000 ;
+ RECT 247.120000 2878.860000 248.220000 2879.340000 ;
+ RECT 242.990000 2878.860000 243.990000 2879.340000 ;
+ RECT 247.120000 2873.420000 248.220000 2873.900000 ;
+ RECT 247.120000 2867.980000 248.220000 2868.460000 ;
+ RECT 242.990000 2873.420000 243.990000 2873.900000 ;
+ RECT 242.990000 2867.980000 243.990000 2868.460000 ;
+ RECT 247.120000 2862.540000 248.220000 2863.020000 ;
+ RECT 242.990000 2862.540000 243.990000 2863.020000 ;
+ RECT 247.120000 2857.100000 248.220000 2857.580000 ;
+ RECT 242.990000 2857.100000 243.990000 2857.580000 ;
+ RECT 247.120000 2851.660000 248.220000 2852.140000 ;
+ RECT 242.990000 2851.660000 243.990000 2852.140000 ;
+ RECT 427.120000 2846.220000 428.220000 2846.700000 ;
+ RECT 427.120000 2840.780000 428.220000 2841.260000 ;
+ RECT 436.430000 2846.220000 437.430000 2846.700000 ;
+ RECT 436.430000 2840.780000 437.430000 2841.260000 ;
+ RECT 436.430000 2824.460000 437.430000 2824.940000 ;
+ RECT 436.430000 2829.900000 437.430000 2830.380000 ;
+ RECT 436.430000 2835.340000 437.430000 2835.820000 ;
+ RECT 427.120000 2835.340000 428.220000 2835.820000 ;
+ RECT 427.120000 2829.900000 428.220000 2830.380000 ;
+ RECT 427.120000 2824.460000 428.220000 2824.940000 ;
+ RECT 427.120000 2813.580000 428.220000 2814.060000 ;
+ RECT 427.120000 2819.020000 428.220000 2819.500000 ;
+ RECT 436.430000 2819.020000 437.430000 2819.500000 ;
+ RECT 436.430000 2813.580000 437.430000 2814.060000 ;
+ RECT 436.430000 2802.700000 437.430000 2803.180000 ;
+ RECT 436.430000 2808.140000 437.430000 2808.620000 ;
+ RECT 427.120000 2802.700000 428.220000 2803.180000 ;
+ RECT 427.120000 2808.140000 428.220000 2808.620000 ;
+ RECT 382.120000 2846.220000 383.220000 2846.700000 ;
+ RECT 382.120000 2840.780000 383.220000 2841.260000 ;
+ RECT 382.120000 2835.340000 383.220000 2835.820000 ;
+ RECT 382.120000 2829.900000 383.220000 2830.380000 ;
+ RECT 382.120000 2824.460000 383.220000 2824.940000 ;
+ RECT 382.120000 2802.700000 383.220000 2803.180000 ;
+ RECT 382.120000 2808.140000 383.220000 2808.620000 ;
+ RECT 382.120000 2813.580000 383.220000 2814.060000 ;
+ RECT 382.120000 2819.020000 383.220000 2819.500000 ;
+ RECT 427.120000 2797.260000 428.220000 2797.740000 ;
+ RECT 427.120000 2791.820000 428.220000 2792.300000 ;
+ RECT 436.430000 2797.260000 437.430000 2797.740000 ;
+ RECT 436.430000 2791.820000 437.430000 2792.300000 ;
+ RECT 427.120000 2780.940000 428.220000 2781.420000 ;
+ RECT 427.120000 2775.500000 428.220000 2775.980000 ;
+ RECT 436.430000 2780.940000 437.430000 2781.420000 ;
+ RECT 436.430000 2775.500000 437.430000 2775.980000 ;
+ RECT 427.120000 2786.380000 428.220000 2786.860000 ;
+ RECT 436.430000 2786.380000 437.430000 2786.860000 ;
+ RECT 436.430000 2764.620000 437.430000 2765.100000 ;
+ RECT 436.430000 2770.060000 437.430000 2770.540000 ;
+ RECT 427.120000 2770.060000 428.220000 2770.540000 ;
+ RECT 427.120000 2764.620000 428.220000 2765.100000 ;
+ RECT 427.120000 2759.180000 428.220000 2759.660000 ;
+ RECT 427.120000 2753.740000 428.220000 2754.220000 ;
+ RECT 436.430000 2759.180000 437.430000 2759.660000 ;
+ RECT 436.430000 2753.740000 437.430000 2754.220000 ;
+ RECT 382.120000 2797.260000 383.220000 2797.740000 ;
+ RECT 382.120000 2791.820000 383.220000 2792.300000 ;
+ RECT 382.120000 2786.380000 383.220000 2786.860000 ;
+ RECT 382.120000 2780.940000 383.220000 2781.420000 ;
+ RECT 382.120000 2775.500000 383.220000 2775.980000 ;
+ RECT 382.120000 2770.060000 383.220000 2770.540000 ;
+ RECT 382.120000 2764.620000 383.220000 2765.100000 ;
+ RECT 382.120000 2759.180000 383.220000 2759.660000 ;
+ RECT 382.120000 2753.740000 383.220000 2754.220000 ;
+ RECT 337.120000 2846.220000 338.220000 2846.700000 ;
+ RECT 337.120000 2840.780000 338.220000 2841.260000 ;
+ RECT 337.120000 2835.340000 338.220000 2835.820000 ;
+ RECT 337.120000 2829.900000 338.220000 2830.380000 ;
+ RECT 337.120000 2824.460000 338.220000 2824.940000 ;
+ RECT 292.120000 2846.220000 293.220000 2846.700000 ;
+ RECT 292.120000 2840.780000 293.220000 2841.260000 ;
+ RECT 292.120000 2835.340000 293.220000 2835.820000 ;
+ RECT 292.120000 2829.900000 293.220000 2830.380000 ;
+ RECT 292.120000 2824.460000 293.220000 2824.940000 ;
+ RECT 337.120000 2819.020000 338.220000 2819.500000 ;
+ RECT 337.120000 2813.580000 338.220000 2814.060000 ;
+ RECT 337.120000 2808.140000 338.220000 2808.620000 ;
+ RECT 337.120000 2802.700000 338.220000 2803.180000 ;
+ RECT 292.120000 2813.580000 293.220000 2814.060000 ;
+ RECT 292.120000 2808.140000 293.220000 2808.620000 ;
+ RECT 292.120000 2802.700000 293.220000 2803.180000 ;
+ RECT 292.120000 2819.020000 293.220000 2819.500000 ;
+ RECT 247.120000 2846.220000 248.220000 2846.700000 ;
+ RECT 242.990000 2846.220000 243.990000 2846.700000 ;
+ RECT 247.120000 2840.780000 248.220000 2841.260000 ;
+ RECT 242.990000 2840.780000 243.990000 2841.260000 ;
+ RECT 247.120000 2835.340000 248.220000 2835.820000 ;
+ RECT 242.990000 2835.340000 243.990000 2835.820000 ;
+ RECT 247.120000 2824.460000 248.220000 2824.940000 ;
+ RECT 242.990000 2824.460000 243.990000 2824.940000 ;
+ RECT 242.990000 2829.900000 243.990000 2830.380000 ;
+ RECT 247.120000 2829.900000 248.220000 2830.380000 ;
+ RECT 247.120000 2819.020000 248.220000 2819.500000 ;
+ RECT 242.990000 2819.020000 243.990000 2819.500000 ;
+ RECT 247.120000 2813.580000 248.220000 2814.060000 ;
+ RECT 242.990000 2813.580000 243.990000 2814.060000 ;
+ RECT 247.120000 2808.140000 248.220000 2808.620000 ;
+ RECT 242.990000 2808.140000 243.990000 2808.620000 ;
+ RECT 247.120000 2802.700000 248.220000 2803.180000 ;
+ RECT 242.990000 2802.700000 243.990000 2803.180000 ;
+ RECT 337.120000 2797.260000 338.220000 2797.740000 ;
+ RECT 337.120000 2791.820000 338.220000 2792.300000 ;
+ RECT 337.120000 2786.380000 338.220000 2786.860000 ;
+ RECT 337.120000 2780.940000 338.220000 2781.420000 ;
+ RECT 337.120000 2775.500000 338.220000 2775.980000 ;
+ RECT 292.120000 2797.260000 293.220000 2797.740000 ;
+ RECT 292.120000 2791.820000 293.220000 2792.300000 ;
+ RECT 292.120000 2786.380000 293.220000 2786.860000 ;
+ RECT 292.120000 2780.940000 293.220000 2781.420000 ;
+ RECT 292.120000 2775.500000 293.220000 2775.980000 ;
+ RECT 337.120000 2753.740000 338.220000 2754.220000 ;
+ RECT 337.120000 2759.180000 338.220000 2759.660000 ;
+ RECT 337.120000 2764.620000 338.220000 2765.100000 ;
+ RECT 337.120000 2770.060000 338.220000 2770.540000 ;
+ RECT 292.120000 2753.740000 293.220000 2754.220000 ;
+ RECT 292.120000 2759.180000 293.220000 2759.660000 ;
+ RECT 292.120000 2764.620000 293.220000 2765.100000 ;
+ RECT 292.120000 2770.060000 293.220000 2770.540000 ;
+ RECT 247.120000 2797.260000 248.220000 2797.740000 ;
+ RECT 242.990000 2797.260000 243.990000 2797.740000 ;
+ RECT 247.120000 2791.820000 248.220000 2792.300000 ;
+ RECT 242.990000 2791.820000 243.990000 2792.300000 ;
+ RECT 247.120000 2780.940000 248.220000 2781.420000 ;
+ RECT 242.990000 2780.940000 243.990000 2781.420000 ;
+ RECT 247.120000 2775.500000 248.220000 2775.980000 ;
+ RECT 242.990000 2775.500000 243.990000 2775.980000 ;
+ RECT 247.120000 2786.380000 248.220000 2786.860000 ;
+ RECT 242.990000 2786.380000 243.990000 2786.860000 ;
+ RECT 247.120000 2770.060000 248.220000 2770.540000 ;
+ RECT 242.990000 2770.060000 243.990000 2770.540000 ;
+ RECT 247.120000 2764.620000 248.220000 2765.100000 ;
+ RECT 242.990000 2764.620000 243.990000 2765.100000 ;
+ RECT 247.120000 2759.180000 248.220000 2759.660000 ;
+ RECT 247.120000 2753.740000 248.220000 2754.220000 ;
+ RECT 242.990000 2759.180000 243.990000 2759.660000 ;
+ RECT 242.990000 2753.740000 243.990000 2754.220000 ;
+ RECT 240.160000 2944.100000 440.260000 2945.100000 ;
+ RECT 240.160000 2751.730000 440.260000 2752.730000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 2748.880000 243.990000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 2948.140000 243.990000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 2748.880000 437.430000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 2948.140000 437.430000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2751.730000 241.160000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2751.730000 440.260000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2944.100000 241.160000 2945.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2944.100000 440.260000 2945.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 2551.470000 428.220000 2744.840000 ;
+ RECT 382.120000 2551.470000 383.220000 2744.840000 ;
+ RECT 436.430000 2548.620000 437.430000 2748.880000 ;
+ RECT 337.120000 2551.470000 338.220000 2744.840000 ;
+ RECT 292.120000 2551.470000 293.220000 2744.840000 ;
+ RECT 247.120000 2551.470000 248.220000 2744.840000 ;
+ RECT 242.990000 2548.620000 243.990000 2748.880000 ;
+ LAYER met3 ;
+ RECT 427.120000 2738.440000 428.220000 2738.920000 ;
+ RECT 436.430000 2738.440000 437.430000 2738.920000 ;
+ RECT 436.430000 2727.560000 437.430000 2728.040000 ;
+ RECT 436.430000 2733.000000 437.430000 2733.480000 ;
+ RECT 427.120000 2733.000000 428.220000 2733.480000 ;
+ RECT 427.120000 2727.560000 428.220000 2728.040000 ;
+ RECT 427.120000 2722.120000 428.220000 2722.600000 ;
+ RECT 427.120000 2716.680000 428.220000 2717.160000 ;
+ RECT 436.430000 2722.120000 437.430000 2722.600000 ;
+ RECT 436.430000 2716.680000 437.430000 2717.160000 ;
+ RECT 427.120000 2700.360000 428.220000 2700.840000 ;
+ RECT 427.120000 2705.800000 428.220000 2706.280000 ;
+ RECT 436.430000 2705.800000 437.430000 2706.280000 ;
+ RECT 436.430000 2700.360000 437.430000 2700.840000 ;
+ RECT 427.120000 2711.240000 428.220000 2711.720000 ;
+ RECT 436.430000 2711.240000 437.430000 2711.720000 ;
+ RECT 382.120000 2738.440000 383.220000 2738.920000 ;
+ RECT 382.120000 2733.000000 383.220000 2733.480000 ;
+ RECT 382.120000 2727.560000 383.220000 2728.040000 ;
+ RECT 382.120000 2722.120000 383.220000 2722.600000 ;
+ RECT 382.120000 2700.360000 383.220000 2700.840000 ;
+ RECT 382.120000 2705.800000 383.220000 2706.280000 ;
+ RECT 382.120000 2711.240000 383.220000 2711.720000 ;
+ RECT 382.120000 2716.680000 383.220000 2717.160000 ;
+ RECT 436.430000 2689.480000 437.430000 2689.960000 ;
+ RECT 436.430000 2694.920000 437.430000 2695.400000 ;
+ RECT 427.120000 2694.920000 428.220000 2695.400000 ;
+ RECT 427.120000 2689.480000 428.220000 2689.960000 ;
+ RECT 427.120000 2684.040000 428.220000 2684.520000 ;
+ RECT 427.120000 2678.600000 428.220000 2679.080000 ;
+ RECT 436.430000 2684.040000 437.430000 2684.520000 ;
+ RECT 436.430000 2678.600000 437.430000 2679.080000 ;
+ RECT 436.430000 2662.280000 437.430000 2662.760000 ;
+ RECT 436.430000 2667.720000 437.430000 2668.200000 ;
+ RECT 436.430000 2673.160000 437.430000 2673.640000 ;
+ RECT 427.120000 2667.720000 428.220000 2668.200000 ;
+ RECT 427.120000 2662.280000 428.220000 2662.760000 ;
+ RECT 427.120000 2673.160000 428.220000 2673.640000 ;
+ RECT 427.120000 2656.840000 428.220000 2657.320000 ;
+ RECT 427.120000 2651.400000 428.220000 2651.880000 ;
+ RECT 436.430000 2656.840000 437.430000 2657.320000 ;
+ RECT 436.430000 2651.400000 437.430000 2651.880000 ;
+ RECT 382.120000 2694.920000 383.220000 2695.400000 ;
+ RECT 382.120000 2689.480000 383.220000 2689.960000 ;
+ RECT 382.120000 2684.040000 383.220000 2684.520000 ;
+ RECT 382.120000 2678.600000 383.220000 2679.080000 ;
+ RECT 382.120000 2667.720000 383.220000 2668.200000 ;
+ RECT 382.120000 2662.280000 383.220000 2662.760000 ;
+ RECT 382.120000 2656.840000 383.220000 2657.320000 ;
+ RECT 382.120000 2651.400000 383.220000 2651.880000 ;
+ RECT 382.120000 2673.160000 383.220000 2673.640000 ;
+ RECT 337.120000 2738.440000 338.220000 2738.920000 ;
+ RECT 337.120000 2733.000000 338.220000 2733.480000 ;
+ RECT 337.120000 2727.560000 338.220000 2728.040000 ;
+ RECT 292.120000 2738.440000 293.220000 2738.920000 ;
+ RECT 292.120000 2733.000000 293.220000 2733.480000 ;
+ RECT 292.120000 2727.560000 293.220000 2728.040000 ;
+ RECT 337.120000 2711.240000 338.220000 2711.720000 ;
+ RECT 337.120000 2705.800000 338.220000 2706.280000 ;
+ RECT 337.120000 2700.360000 338.220000 2700.840000 ;
+ RECT 337.120000 2716.680000 338.220000 2717.160000 ;
+ RECT 337.120000 2722.120000 338.220000 2722.600000 ;
+ RECT 292.120000 2722.120000 293.220000 2722.600000 ;
+ RECT 292.120000 2711.240000 293.220000 2711.720000 ;
+ RECT 292.120000 2705.800000 293.220000 2706.280000 ;
+ RECT 292.120000 2700.360000 293.220000 2700.840000 ;
+ RECT 292.120000 2716.680000 293.220000 2717.160000 ;
+ RECT 247.120000 2738.440000 248.220000 2738.920000 ;
+ RECT 242.990000 2738.440000 243.990000 2738.920000 ;
+ RECT 242.990000 2733.000000 243.990000 2733.480000 ;
+ RECT 247.120000 2733.000000 248.220000 2733.480000 ;
+ RECT 247.120000 2727.560000 248.220000 2728.040000 ;
+ RECT 242.990000 2727.560000 243.990000 2728.040000 ;
+ RECT 247.120000 2722.120000 248.220000 2722.600000 ;
+ RECT 242.990000 2722.120000 243.990000 2722.600000 ;
+ RECT 247.120000 2716.680000 248.220000 2717.160000 ;
+ RECT 242.990000 2716.680000 243.990000 2717.160000 ;
+ RECT 247.120000 2705.800000 248.220000 2706.280000 ;
+ RECT 242.990000 2705.800000 243.990000 2706.280000 ;
+ RECT 247.120000 2700.360000 248.220000 2700.840000 ;
+ RECT 242.990000 2700.360000 243.990000 2700.840000 ;
+ RECT 247.120000 2711.240000 248.220000 2711.720000 ;
+ RECT 242.990000 2711.240000 243.990000 2711.720000 ;
+ RECT 337.120000 2694.920000 338.220000 2695.400000 ;
+ RECT 337.120000 2689.480000 338.220000 2689.960000 ;
+ RECT 337.120000 2684.040000 338.220000 2684.520000 ;
+ RECT 337.120000 2678.600000 338.220000 2679.080000 ;
+ RECT 292.120000 2694.920000 293.220000 2695.400000 ;
+ RECT 292.120000 2689.480000 293.220000 2689.960000 ;
+ RECT 292.120000 2684.040000 293.220000 2684.520000 ;
+ RECT 292.120000 2678.600000 293.220000 2679.080000 ;
+ RECT 337.120000 2667.720000 338.220000 2668.200000 ;
+ RECT 337.120000 2651.400000 338.220000 2651.880000 ;
+ RECT 337.120000 2656.840000 338.220000 2657.320000 ;
+ RECT 337.120000 2662.280000 338.220000 2662.760000 ;
+ RECT 337.120000 2673.160000 338.220000 2673.640000 ;
+ RECT 292.120000 2651.400000 293.220000 2651.880000 ;
+ RECT 292.120000 2656.840000 293.220000 2657.320000 ;
+ RECT 292.120000 2662.280000 293.220000 2662.760000 ;
+ RECT 292.120000 2667.720000 293.220000 2668.200000 ;
+ RECT 292.120000 2673.160000 293.220000 2673.640000 ;
+ RECT 247.120000 2694.920000 248.220000 2695.400000 ;
+ RECT 242.990000 2694.920000 243.990000 2695.400000 ;
+ RECT 247.120000 2689.480000 248.220000 2689.960000 ;
+ RECT 242.990000 2689.480000 243.990000 2689.960000 ;
+ RECT 247.120000 2684.040000 248.220000 2684.520000 ;
+ RECT 242.990000 2684.040000 243.990000 2684.520000 ;
+ RECT 247.120000 2678.600000 248.220000 2679.080000 ;
+ RECT 242.990000 2678.600000 243.990000 2679.080000 ;
+ RECT 247.120000 2673.160000 248.220000 2673.640000 ;
+ RECT 247.120000 2667.720000 248.220000 2668.200000 ;
+ RECT 242.990000 2673.160000 243.990000 2673.640000 ;
+ RECT 242.990000 2667.720000 243.990000 2668.200000 ;
+ RECT 247.120000 2662.280000 248.220000 2662.760000 ;
+ RECT 242.990000 2662.280000 243.990000 2662.760000 ;
+ RECT 247.120000 2656.840000 248.220000 2657.320000 ;
+ RECT 242.990000 2656.840000 243.990000 2657.320000 ;
+ RECT 247.120000 2651.400000 248.220000 2651.880000 ;
+ RECT 242.990000 2651.400000 243.990000 2651.880000 ;
+ RECT 427.120000 2645.960000 428.220000 2646.440000 ;
+ RECT 427.120000 2640.520000 428.220000 2641.000000 ;
+ RECT 436.430000 2645.960000 437.430000 2646.440000 ;
+ RECT 436.430000 2640.520000 437.430000 2641.000000 ;
+ RECT 436.430000 2624.200000 437.430000 2624.680000 ;
+ RECT 436.430000 2629.640000 437.430000 2630.120000 ;
+ RECT 436.430000 2635.080000 437.430000 2635.560000 ;
+ RECT 427.120000 2635.080000 428.220000 2635.560000 ;
+ RECT 427.120000 2629.640000 428.220000 2630.120000 ;
+ RECT 427.120000 2624.200000 428.220000 2624.680000 ;
+ RECT 427.120000 2613.320000 428.220000 2613.800000 ;
+ RECT 427.120000 2618.760000 428.220000 2619.240000 ;
+ RECT 436.430000 2618.760000 437.430000 2619.240000 ;
+ RECT 436.430000 2613.320000 437.430000 2613.800000 ;
+ RECT 436.430000 2602.440000 437.430000 2602.920000 ;
+ RECT 436.430000 2607.880000 437.430000 2608.360000 ;
+ RECT 427.120000 2602.440000 428.220000 2602.920000 ;
+ RECT 427.120000 2607.880000 428.220000 2608.360000 ;
+ RECT 382.120000 2645.960000 383.220000 2646.440000 ;
+ RECT 382.120000 2640.520000 383.220000 2641.000000 ;
+ RECT 382.120000 2635.080000 383.220000 2635.560000 ;
+ RECT 382.120000 2629.640000 383.220000 2630.120000 ;
+ RECT 382.120000 2624.200000 383.220000 2624.680000 ;
+ RECT 382.120000 2602.440000 383.220000 2602.920000 ;
+ RECT 382.120000 2607.880000 383.220000 2608.360000 ;
+ RECT 382.120000 2613.320000 383.220000 2613.800000 ;
+ RECT 382.120000 2618.760000 383.220000 2619.240000 ;
+ RECT 427.120000 2597.000000 428.220000 2597.480000 ;
+ RECT 427.120000 2591.560000 428.220000 2592.040000 ;
+ RECT 436.430000 2597.000000 437.430000 2597.480000 ;
+ RECT 436.430000 2591.560000 437.430000 2592.040000 ;
+ RECT 427.120000 2580.680000 428.220000 2581.160000 ;
+ RECT 427.120000 2575.240000 428.220000 2575.720000 ;
+ RECT 436.430000 2580.680000 437.430000 2581.160000 ;
+ RECT 436.430000 2575.240000 437.430000 2575.720000 ;
+ RECT 427.120000 2586.120000 428.220000 2586.600000 ;
+ RECT 436.430000 2586.120000 437.430000 2586.600000 ;
+ RECT 436.430000 2564.360000 437.430000 2564.840000 ;
+ RECT 436.430000 2569.800000 437.430000 2570.280000 ;
+ RECT 427.120000 2569.800000 428.220000 2570.280000 ;
+ RECT 427.120000 2564.360000 428.220000 2564.840000 ;
+ RECT 427.120000 2558.920000 428.220000 2559.400000 ;
+ RECT 427.120000 2553.480000 428.220000 2553.960000 ;
+ RECT 436.430000 2558.920000 437.430000 2559.400000 ;
+ RECT 436.430000 2553.480000 437.430000 2553.960000 ;
+ RECT 382.120000 2597.000000 383.220000 2597.480000 ;
+ RECT 382.120000 2591.560000 383.220000 2592.040000 ;
+ RECT 382.120000 2586.120000 383.220000 2586.600000 ;
+ RECT 382.120000 2580.680000 383.220000 2581.160000 ;
+ RECT 382.120000 2575.240000 383.220000 2575.720000 ;
+ RECT 382.120000 2569.800000 383.220000 2570.280000 ;
+ RECT 382.120000 2564.360000 383.220000 2564.840000 ;
+ RECT 382.120000 2558.920000 383.220000 2559.400000 ;
+ RECT 382.120000 2553.480000 383.220000 2553.960000 ;
+ RECT 337.120000 2645.960000 338.220000 2646.440000 ;
+ RECT 337.120000 2640.520000 338.220000 2641.000000 ;
+ RECT 337.120000 2635.080000 338.220000 2635.560000 ;
+ RECT 337.120000 2629.640000 338.220000 2630.120000 ;
+ RECT 337.120000 2624.200000 338.220000 2624.680000 ;
+ RECT 292.120000 2645.960000 293.220000 2646.440000 ;
+ RECT 292.120000 2640.520000 293.220000 2641.000000 ;
+ RECT 292.120000 2635.080000 293.220000 2635.560000 ;
+ RECT 292.120000 2629.640000 293.220000 2630.120000 ;
+ RECT 292.120000 2624.200000 293.220000 2624.680000 ;
+ RECT 337.120000 2618.760000 338.220000 2619.240000 ;
+ RECT 337.120000 2613.320000 338.220000 2613.800000 ;
+ RECT 337.120000 2607.880000 338.220000 2608.360000 ;
+ RECT 337.120000 2602.440000 338.220000 2602.920000 ;
+ RECT 292.120000 2613.320000 293.220000 2613.800000 ;
+ RECT 292.120000 2607.880000 293.220000 2608.360000 ;
+ RECT 292.120000 2602.440000 293.220000 2602.920000 ;
+ RECT 292.120000 2618.760000 293.220000 2619.240000 ;
+ RECT 247.120000 2645.960000 248.220000 2646.440000 ;
+ RECT 242.990000 2645.960000 243.990000 2646.440000 ;
+ RECT 247.120000 2640.520000 248.220000 2641.000000 ;
+ RECT 242.990000 2640.520000 243.990000 2641.000000 ;
+ RECT 247.120000 2635.080000 248.220000 2635.560000 ;
+ RECT 242.990000 2635.080000 243.990000 2635.560000 ;
+ RECT 247.120000 2624.200000 248.220000 2624.680000 ;
+ RECT 242.990000 2624.200000 243.990000 2624.680000 ;
+ RECT 242.990000 2629.640000 243.990000 2630.120000 ;
+ RECT 247.120000 2629.640000 248.220000 2630.120000 ;
+ RECT 247.120000 2618.760000 248.220000 2619.240000 ;
+ RECT 242.990000 2618.760000 243.990000 2619.240000 ;
+ RECT 247.120000 2613.320000 248.220000 2613.800000 ;
+ RECT 242.990000 2613.320000 243.990000 2613.800000 ;
+ RECT 247.120000 2607.880000 248.220000 2608.360000 ;
+ RECT 242.990000 2607.880000 243.990000 2608.360000 ;
+ RECT 247.120000 2602.440000 248.220000 2602.920000 ;
+ RECT 242.990000 2602.440000 243.990000 2602.920000 ;
+ RECT 337.120000 2597.000000 338.220000 2597.480000 ;
+ RECT 337.120000 2591.560000 338.220000 2592.040000 ;
+ RECT 337.120000 2586.120000 338.220000 2586.600000 ;
+ RECT 337.120000 2580.680000 338.220000 2581.160000 ;
+ RECT 337.120000 2575.240000 338.220000 2575.720000 ;
+ RECT 292.120000 2597.000000 293.220000 2597.480000 ;
+ RECT 292.120000 2591.560000 293.220000 2592.040000 ;
+ RECT 292.120000 2586.120000 293.220000 2586.600000 ;
+ RECT 292.120000 2580.680000 293.220000 2581.160000 ;
+ RECT 292.120000 2575.240000 293.220000 2575.720000 ;
+ RECT 337.120000 2553.480000 338.220000 2553.960000 ;
+ RECT 337.120000 2558.920000 338.220000 2559.400000 ;
+ RECT 337.120000 2564.360000 338.220000 2564.840000 ;
+ RECT 337.120000 2569.800000 338.220000 2570.280000 ;
+ RECT 292.120000 2553.480000 293.220000 2553.960000 ;
+ RECT 292.120000 2558.920000 293.220000 2559.400000 ;
+ RECT 292.120000 2564.360000 293.220000 2564.840000 ;
+ RECT 292.120000 2569.800000 293.220000 2570.280000 ;
+ RECT 247.120000 2597.000000 248.220000 2597.480000 ;
+ RECT 242.990000 2597.000000 243.990000 2597.480000 ;
+ RECT 247.120000 2591.560000 248.220000 2592.040000 ;
+ RECT 242.990000 2591.560000 243.990000 2592.040000 ;
+ RECT 247.120000 2580.680000 248.220000 2581.160000 ;
+ RECT 242.990000 2580.680000 243.990000 2581.160000 ;
+ RECT 247.120000 2575.240000 248.220000 2575.720000 ;
+ RECT 242.990000 2575.240000 243.990000 2575.720000 ;
+ RECT 247.120000 2586.120000 248.220000 2586.600000 ;
+ RECT 242.990000 2586.120000 243.990000 2586.600000 ;
+ RECT 247.120000 2569.800000 248.220000 2570.280000 ;
+ RECT 242.990000 2569.800000 243.990000 2570.280000 ;
+ RECT 247.120000 2564.360000 248.220000 2564.840000 ;
+ RECT 242.990000 2564.360000 243.990000 2564.840000 ;
+ RECT 247.120000 2558.920000 248.220000 2559.400000 ;
+ RECT 247.120000 2553.480000 248.220000 2553.960000 ;
+ RECT 242.990000 2558.920000 243.990000 2559.400000 ;
+ RECT 242.990000 2553.480000 243.990000 2553.960000 ;
+ RECT 240.160000 2743.840000 440.260000 2744.840000 ;
+ RECT 240.160000 2551.470000 440.260000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 2548.620000 243.990000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 2747.880000 243.990000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 2548.620000 437.430000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 2747.880000 437.430000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2551.470000 241.160000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2551.470000 440.260000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2743.840000 241.160000 2744.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2743.840000 440.260000 2744.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 2351.210000 428.220000 2544.580000 ;
+ RECT 382.120000 2351.210000 383.220000 2544.580000 ;
+ RECT 436.430000 2348.360000 437.430000 2548.620000 ;
+ RECT 337.120000 2351.210000 338.220000 2544.580000 ;
+ RECT 292.120000 2351.210000 293.220000 2544.580000 ;
+ RECT 247.120000 2351.210000 248.220000 2544.580000 ;
+ RECT 242.990000 2348.360000 243.990000 2548.620000 ;
+ LAYER met3 ;
+ RECT 427.120000 2538.180000 428.220000 2538.660000 ;
+ RECT 436.430000 2538.180000 437.430000 2538.660000 ;
+ RECT 436.430000 2527.300000 437.430000 2527.780000 ;
+ RECT 436.430000 2532.740000 437.430000 2533.220000 ;
+ RECT 427.120000 2532.740000 428.220000 2533.220000 ;
+ RECT 427.120000 2527.300000 428.220000 2527.780000 ;
+ RECT 427.120000 2521.860000 428.220000 2522.340000 ;
+ RECT 427.120000 2516.420000 428.220000 2516.900000 ;
+ RECT 436.430000 2521.860000 437.430000 2522.340000 ;
+ RECT 436.430000 2516.420000 437.430000 2516.900000 ;
+ RECT 427.120000 2500.100000 428.220000 2500.580000 ;
+ RECT 427.120000 2505.540000 428.220000 2506.020000 ;
+ RECT 436.430000 2505.540000 437.430000 2506.020000 ;
+ RECT 436.430000 2500.100000 437.430000 2500.580000 ;
+ RECT 427.120000 2510.980000 428.220000 2511.460000 ;
+ RECT 436.430000 2510.980000 437.430000 2511.460000 ;
+ RECT 382.120000 2538.180000 383.220000 2538.660000 ;
+ RECT 382.120000 2532.740000 383.220000 2533.220000 ;
+ RECT 382.120000 2527.300000 383.220000 2527.780000 ;
+ RECT 382.120000 2521.860000 383.220000 2522.340000 ;
+ RECT 382.120000 2500.100000 383.220000 2500.580000 ;
+ RECT 382.120000 2505.540000 383.220000 2506.020000 ;
+ RECT 382.120000 2510.980000 383.220000 2511.460000 ;
+ RECT 382.120000 2516.420000 383.220000 2516.900000 ;
+ RECT 436.430000 2489.220000 437.430000 2489.700000 ;
+ RECT 436.430000 2494.660000 437.430000 2495.140000 ;
+ RECT 427.120000 2494.660000 428.220000 2495.140000 ;
+ RECT 427.120000 2489.220000 428.220000 2489.700000 ;
+ RECT 427.120000 2483.780000 428.220000 2484.260000 ;
+ RECT 427.120000 2478.340000 428.220000 2478.820000 ;
+ RECT 436.430000 2483.780000 437.430000 2484.260000 ;
+ RECT 436.430000 2478.340000 437.430000 2478.820000 ;
+ RECT 436.430000 2462.020000 437.430000 2462.500000 ;
+ RECT 436.430000 2467.460000 437.430000 2467.940000 ;
+ RECT 436.430000 2472.900000 437.430000 2473.380000 ;
+ RECT 427.120000 2467.460000 428.220000 2467.940000 ;
+ RECT 427.120000 2462.020000 428.220000 2462.500000 ;
+ RECT 427.120000 2472.900000 428.220000 2473.380000 ;
+ RECT 427.120000 2456.580000 428.220000 2457.060000 ;
+ RECT 427.120000 2451.140000 428.220000 2451.620000 ;
+ RECT 436.430000 2456.580000 437.430000 2457.060000 ;
+ RECT 436.430000 2451.140000 437.430000 2451.620000 ;
+ RECT 382.120000 2494.660000 383.220000 2495.140000 ;
+ RECT 382.120000 2489.220000 383.220000 2489.700000 ;
+ RECT 382.120000 2483.780000 383.220000 2484.260000 ;
+ RECT 382.120000 2478.340000 383.220000 2478.820000 ;
+ RECT 382.120000 2467.460000 383.220000 2467.940000 ;
+ RECT 382.120000 2462.020000 383.220000 2462.500000 ;
+ RECT 382.120000 2456.580000 383.220000 2457.060000 ;
+ RECT 382.120000 2451.140000 383.220000 2451.620000 ;
+ RECT 382.120000 2472.900000 383.220000 2473.380000 ;
+ RECT 337.120000 2538.180000 338.220000 2538.660000 ;
+ RECT 337.120000 2532.740000 338.220000 2533.220000 ;
+ RECT 337.120000 2527.300000 338.220000 2527.780000 ;
+ RECT 292.120000 2538.180000 293.220000 2538.660000 ;
+ RECT 292.120000 2532.740000 293.220000 2533.220000 ;
+ RECT 292.120000 2527.300000 293.220000 2527.780000 ;
+ RECT 337.120000 2510.980000 338.220000 2511.460000 ;
+ RECT 337.120000 2505.540000 338.220000 2506.020000 ;
+ RECT 337.120000 2500.100000 338.220000 2500.580000 ;
+ RECT 337.120000 2516.420000 338.220000 2516.900000 ;
+ RECT 337.120000 2521.860000 338.220000 2522.340000 ;
+ RECT 292.120000 2521.860000 293.220000 2522.340000 ;
+ RECT 292.120000 2510.980000 293.220000 2511.460000 ;
+ RECT 292.120000 2505.540000 293.220000 2506.020000 ;
+ RECT 292.120000 2500.100000 293.220000 2500.580000 ;
+ RECT 292.120000 2516.420000 293.220000 2516.900000 ;
+ RECT 247.120000 2538.180000 248.220000 2538.660000 ;
+ RECT 242.990000 2538.180000 243.990000 2538.660000 ;
+ RECT 242.990000 2532.740000 243.990000 2533.220000 ;
+ RECT 247.120000 2532.740000 248.220000 2533.220000 ;
+ RECT 247.120000 2527.300000 248.220000 2527.780000 ;
+ RECT 242.990000 2527.300000 243.990000 2527.780000 ;
+ RECT 247.120000 2521.860000 248.220000 2522.340000 ;
+ RECT 242.990000 2521.860000 243.990000 2522.340000 ;
+ RECT 247.120000 2516.420000 248.220000 2516.900000 ;
+ RECT 242.990000 2516.420000 243.990000 2516.900000 ;
+ RECT 247.120000 2505.540000 248.220000 2506.020000 ;
+ RECT 242.990000 2505.540000 243.990000 2506.020000 ;
+ RECT 247.120000 2500.100000 248.220000 2500.580000 ;
+ RECT 242.990000 2500.100000 243.990000 2500.580000 ;
+ RECT 247.120000 2510.980000 248.220000 2511.460000 ;
+ RECT 242.990000 2510.980000 243.990000 2511.460000 ;
+ RECT 337.120000 2494.660000 338.220000 2495.140000 ;
+ RECT 337.120000 2489.220000 338.220000 2489.700000 ;
+ RECT 337.120000 2483.780000 338.220000 2484.260000 ;
+ RECT 337.120000 2478.340000 338.220000 2478.820000 ;
+ RECT 292.120000 2494.660000 293.220000 2495.140000 ;
+ RECT 292.120000 2489.220000 293.220000 2489.700000 ;
+ RECT 292.120000 2483.780000 293.220000 2484.260000 ;
+ RECT 292.120000 2478.340000 293.220000 2478.820000 ;
+ RECT 337.120000 2467.460000 338.220000 2467.940000 ;
+ RECT 337.120000 2451.140000 338.220000 2451.620000 ;
+ RECT 337.120000 2456.580000 338.220000 2457.060000 ;
+ RECT 337.120000 2462.020000 338.220000 2462.500000 ;
+ RECT 337.120000 2472.900000 338.220000 2473.380000 ;
+ RECT 292.120000 2451.140000 293.220000 2451.620000 ;
+ RECT 292.120000 2456.580000 293.220000 2457.060000 ;
+ RECT 292.120000 2462.020000 293.220000 2462.500000 ;
+ RECT 292.120000 2467.460000 293.220000 2467.940000 ;
+ RECT 292.120000 2472.900000 293.220000 2473.380000 ;
+ RECT 247.120000 2494.660000 248.220000 2495.140000 ;
+ RECT 242.990000 2494.660000 243.990000 2495.140000 ;
+ RECT 247.120000 2489.220000 248.220000 2489.700000 ;
+ RECT 242.990000 2489.220000 243.990000 2489.700000 ;
+ RECT 247.120000 2483.780000 248.220000 2484.260000 ;
+ RECT 242.990000 2483.780000 243.990000 2484.260000 ;
+ RECT 247.120000 2478.340000 248.220000 2478.820000 ;
+ RECT 242.990000 2478.340000 243.990000 2478.820000 ;
+ RECT 247.120000 2472.900000 248.220000 2473.380000 ;
+ RECT 247.120000 2467.460000 248.220000 2467.940000 ;
+ RECT 242.990000 2472.900000 243.990000 2473.380000 ;
+ RECT 242.990000 2467.460000 243.990000 2467.940000 ;
+ RECT 247.120000 2462.020000 248.220000 2462.500000 ;
+ RECT 242.990000 2462.020000 243.990000 2462.500000 ;
+ RECT 247.120000 2456.580000 248.220000 2457.060000 ;
+ RECT 242.990000 2456.580000 243.990000 2457.060000 ;
+ RECT 247.120000 2451.140000 248.220000 2451.620000 ;
+ RECT 242.990000 2451.140000 243.990000 2451.620000 ;
+ RECT 427.120000 2445.700000 428.220000 2446.180000 ;
+ RECT 427.120000 2440.260000 428.220000 2440.740000 ;
+ RECT 436.430000 2445.700000 437.430000 2446.180000 ;
+ RECT 436.430000 2440.260000 437.430000 2440.740000 ;
+ RECT 436.430000 2423.940000 437.430000 2424.420000 ;
+ RECT 436.430000 2429.380000 437.430000 2429.860000 ;
+ RECT 436.430000 2434.820000 437.430000 2435.300000 ;
+ RECT 427.120000 2434.820000 428.220000 2435.300000 ;
+ RECT 427.120000 2429.380000 428.220000 2429.860000 ;
+ RECT 427.120000 2423.940000 428.220000 2424.420000 ;
+ RECT 427.120000 2413.060000 428.220000 2413.540000 ;
+ RECT 427.120000 2418.500000 428.220000 2418.980000 ;
+ RECT 436.430000 2418.500000 437.430000 2418.980000 ;
+ RECT 436.430000 2413.060000 437.430000 2413.540000 ;
+ RECT 436.430000 2402.180000 437.430000 2402.660000 ;
+ RECT 436.430000 2407.620000 437.430000 2408.100000 ;
+ RECT 427.120000 2402.180000 428.220000 2402.660000 ;
+ RECT 427.120000 2407.620000 428.220000 2408.100000 ;
+ RECT 382.120000 2445.700000 383.220000 2446.180000 ;
+ RECT 382.120000 2440.260000 383.220000 2440.740000 ;
+ RECT 382.120000 2434.820000 383.220000 2435.300000 ;
+ RECT 382.120000 2429.380000 383.220000 2429.860000 ;
+ RECT 382.120000 2423.940000 383.220000 2424.420000 ;
+ RECT 382.120000 2402.180000 383.220000 2402.660000 ;
+ RECT 382.120000 2407.620000 383.220000 2408.100000 ;
+ RECT 382.120000 2413.060000 383.220000 2413.540000 ;
+ RECT 382.120000 2418.500000 383.220000 2418.980000 ;
+ RECT 427.120000 2396.740000 428.220000 2397.220000 ;
+ RECT 427.120000 2391.300000 428.220000 2391.780000 ;
+ RECT 436.430000 2396.740000 437.430000 2397.220000 ;
+ RECT 436.430000 2391.300000 437.430000 2391.780000 ;
+ RECT 427.120000 2380.420000 428.220000 2380.900000 ;
+ RECT 427.120000 2374.980000 428.220000 2375.460000 ;
+ RECT 436.430000 2380.420000 437.430000 2380.900000 ;
+ RECT 436.430000 2374.980000 437.430000 2375.460000 ;
+ RECT 427.120000 2385.860000 428.220000 2386.340000 ;
+ RECT 436.430000 2385.860000 437.430000 2386.340000 ;
+ RECT 436.430000 2364.100000 437.430000 2364.580000 ;
+ RECT 436.430000 2369.540000 437.430000 2370.020000 ;
+ RECT 427.120000 2369.540000 428.220000 2370.020000 ;
+ RECT 427.120000 2364.100000 428.220000 2364.580000 ;
+ RECT 427.120000 2358.660000 428.220000 2359.140000 ;
+ RECT 427.120000 2353.220000 428.220000 2353.700000 ;
+ RECT 436.430000 2358.660000 437.430000 2359.140000 ;
+ RECT 436.430000 2353.220000 437.430000 2353.700000 ;
+ RECT 382.120000 2396.740000 383.220000 2397.220000 ;
+ RECT 382.120000 2391.300000 383.220000 2391.780000 ;
+ RECT 382.120000 2385.860000 383.220000 2386.340000 ;
+ RECT 382.120000 2380.420000 383.220000 2380.900000 ;
+ RECT 382.120000 2374.980000 383.220000 2375.460000 ;
+ RECT 382.120000 2369.540000 383.220000 2370.020000 ;
+ RECT 382.120000 2364.100000 383.220000 2364.580000 ;
+ RECT 382.120000 2358.660000 383.220000 2359.140000 ;
+ RECT 382.120000 2353.220000 383.220000 2353.700000 ;
+ RECT 337.120000 2445.700000 338.220000 2446.180000 ;
+ RECT 337.120000 2440.260000 338.220000 2440.740000 ;
+ RECT 337.120000 2434.820000 338.220000 2435.300000 ;
+ RECT 337.120000 2429.380000 338.220000 2429.860000 ;
+ RECT 337.120000 2423.940000 338.220000 2424.420000 ;
+ RECT 292.120000 2445.700000 293.220000 2446.180000 ;
+ RECT 292.120000 2440.260000 293.220000 2440.740000 ;
+ RECT 292.120000 2434.820000 293.220000 2435.300000 ;
+ RECT 292.120000 2429.380000 293.220000 2429.860000 ;
+ RECT 292.120000 2423.940000 293.220000 2424.420000 ;
+ RECT 337.120000 2418.500000 338.220000 2418.980000 ;
+ RECT 337.120000 2413.060000 338.220000 2413.540000 ;
+ RECT 337.120000 2407.620000 338.220000 2408.100000 ;
+ RECT 337.120000 2402.180000 338.220000 2402.660000 ;
+ RECT 292.120000 2413.060000 293.220000 2413.540000 ;
+ RECT 292.120000 2407.620000 293.220000 2408.100000 ;
+ RECT 292.120000 2402.180000 293.220000 2402.660000 ;
+ RECT 292.120000 2418.500000 293.220000 2418.980000 ;
+ RECT 247.120000 2445.700000 248.220000 2446.180000 ;
+ RECT 242.990000 2445.700000 243.990000 2446.180000 ;
+ RECT 247.120000 2440.260000 248.220000 2440.740000 ;
+ RECT 242.990000 2440.260000 243.990000 2440.740000 ;
+ RECT 247.120000 2434.820000 248.220000 2435.300000 ;
+ RECT 242.990000 2434.820000 243.990000 2435.300000 ;
+ RECT 247.120000 2423.940000 248.220000 2424.420000 ;
+ RECT 242.990000 2423.940000 243.990000 2424.420000 ;
+ RECT 242.990000 2429.380000 243.990000 2429.860000 ;
+ RECT 247.120000 2429.380000 248.220000 2429.860000 ;
+ RECT 247.120000 2418.500000 248.220000 2418.980000 ;
+ RECT 242.990000 2418.500000 243.990000 2418.980000 ;
+ RECT 247.120000 2413.060000 248.220000 2413.540000 ;
+ RECT 242.990000 2413.060000 243.990000 2413.540000 ;
+ RECT 247.120000 2407.620000 248.220000 2408.100000 ;
+ RECT 242.990000 2407.620000 243.990000 2408.100000 ;
+ RECT 247.120000 2402.180000 248.220000 2402.660000 ;
+ RECT 242.990000 2402.180000 243.990000 2402.660000 ;
+ RECT 337.120000 2396.740000 338.220000 2397.220000 ;
+ RECT 337.120000 2391.300000 338.220000 2391.780000 ;
+ RECT 337.120000 2385.860000 338.220000 2386.340000 ;
+ RECT 337.120000 2380.420000 338.220000 2380.900000 ;
+ RECT 337.120000 2374.980000 338.220000 2375.460000 ;
+ RECT 292.120000 2396.740000 293.220000 2397.220000 ;
+ RECT 292.120000 2391.300000 293.220000 2391.780000 ;
+ RECT 292.120000 2385.860000 293.220000 2386.340000 ;
+ RECT 292.120000 2380.420000 293.220000 2380.900000 ;
+ RECT 292.120000 2374.980000 293.220000 2375.460000 ;
+ RECT 337.120000 2353.220000 338.220000 2353.700000 ;
+ RECT 337.120000 2358.660000 338.220000 2359.140000 ;
+ RECT 337.120000 2364.100000 338.220000 2364.580000 ;
+ RECT 337.120000 2369.540000 338.220000 2370.020000 ;
+ RECT 292.120000 2353.220000 293.220000 2353.700000 ;
+ RECT 292.120000 2358.660000 293.220000 2359.140000 ;
+ RECT 292.120000 2364.100000 293.220000 2364.580000 ;
+ RECT 292.120000 2369.540000 293.220000 2370.020000 ;
+ RECT 247.120000 2396.740000 248.220000 2397.220000 ;
+ RECT 242.990000 2396.740000 243.990000 2397.220000 ;
+ RECT 247.120000 2391.300000 248.220000 2391.780000 ;
+ RECT 242.990000 2391.300000 243.990000 2391.780000 ;
+ RECT 247.120000 2380.420000 248.220000 2380.900000 ;
+ RECT 242.990000 2380.420000 243.990000 2380.900000 ;
+ RECT 247.120000 2374.980000 248.220000 2375.460000 ;
+ RECT 242.990000 2374.980000 243.990000 2375.460000 ;
+ RECT 247.120000 2385.860000 248.220000 2386.340000 ;
+ RECT 242.990000 2385.860000 243.990000 2386.340000 ;
+ RECT 247.120000 2369.540000 248.220000 2370.020000 ;
+ RECT 242.990000 2369.540000 243.990000 2370.020000 ;
+ RECT 247.120000 2364.100000 248.220000 2364.580000 ;
+ RECT 242.990000 2364.100000 243.990000 2364.580000 ;
+ RECT 247.120000 2358.660000 248.220000 2359.140000 ;
+ RECT 247.120000 2353.220000 248.220000 2353.700000 ;
+ RECT 242.990000 2358.660000 243.990000 2359.140000 ;
+ RECT 242.990000 2353.220000 243.990000 2353.700000 ;
+ RECT 240.160000 2543.580000 440.260000 2544.580000 ;
+ RECT 240.160000 2351.210000 440.260000 2352.210000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 2348.360000 243.990000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 2547.620000 243.990000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 2348.360000 437.430000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 2547.620000 437.430000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2351.210000 241.160000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2351.210000 440.260000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2543.580000 241.160000 2544.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2543.580000 440.260000 2544.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 2150.950000 428.220000 2344.320000 ;
+ RECT 382.120000 2150.950000 383.220000 2344.320000 ;
+ RECT 436.430000 2148.100000 437.430000 2348.360000 ;
+ RECT 337.120000 2150.950000 338.220000 2344.320000 ;
+ RECT 292.120000 2150.950000 293.220000 2344.320000 ;
+ RECT 247.120000 2150.950000 248.220000 2344.320000 ;
+ RECT 242.990000 2148.100000 243.990000 2348.360000 ;
+ LAYER met3 ;
+ RECT 427.120000 2337.920000 428.220000 2338.400000 ;
+ RECT 436.430000 2337.920000 437.430000 2338.400000 ;
+ RECT 436.430000 2327.040000 437.430000 2327.520000 ;
+ RECT 436.430000 2332.480000 437.430000 2332.960000 ;
+ RECT 427.120000 2332.480000 428.220000 2332.960000 ;
+ RECT 427.120000 2327.040000 428.220000 2327.520000 ;
+ RECT 427.120000 2321.600000 428.220000 2322.080000 ;
+ RECT 427.120000 2316.160000 428.220000 2316.640000 ;
+ RECT 436.430000 2321.600000 437.430000 2322.080000 ;
+ RECT 436.430000 2316.160000 437.430000 2316.640000 ;
+ RECT 427.120000 2299.840000 428.220000 2300.320000 ;
+ RECT 427.120000 2305.280000 428.220000 2305.760000 ;
+ RECT 436.430000 2305.280000 437.430000 2305.760000 ;
+ RECT 436.430000 2299.840000 437.430000 2300.320000 ;
+ RECT 427.120000 2310.720000 428.220000 2311.200000 ;
+ RECT 436.430000 2310.720000 437.430000 2311.200000 ;
+ RECT 382.120000 2337.920000 383.220000 2338.400000 ;
+ RECT 382.120000 2332.480000 383.220000 2332.960000 ;
+ RECT 382.120000 2327.040000 383.220000 2327.520000 ;
+ RECT 382.120000 2321.600000 383.220000 2322.080000 ;
+ RECT 382.120000 2299.840000 383.220000 2300.320000 ;
+ RECT 382.120000 2305.280000 383.220000 2305.760000 ;
+ RECT 382.120000 2310.720000 383.220000 2311.200000 ;
+ RECT 382.120000 2316.160000 383.220000 2316.640000 ;
+ RECT 436.430000 2288.960000 437.430000 2289.440000 ;
+ RECT 436.430000 2294.400000 437.430000 2294.880000 ;
+ RECT 427.120000 2294.400000 428.220000 2294.880000 ;
+ RECT 427.120000 2288.960000 428.220000 2289.440000 ;
+ RECT 427.120000 2283.520000 428.220000 2284.000000 ;
+ RECT 427.120000 2278.080000 428.220000 2278.560000 ;
+ RECT 436.430000 2283.520000 437.430000 2284.000000 ;
+ RECT 436.430000 2278.080000 437.430000 2278.560000 ;
+ RECT 436.430000 2261.760000 437.430000 2262.240000 ;
+ RECT 436.430000 2267.200000 437.430000 2267.680000 ;
+ RECT 436.430000 2272.640000 437.430000 2273.120000 ;
+ RECT 427.120000 2267.200000 428.220000 2267.680000 ;
+ RECT 427.120000 2261.760000 428.220000 2262.240000 ;
+ RECT 427.120000 2272.640000 428.220000 2273.120000 ;
+ RECT 427.120000 2256.320000 428.220000 2256.800000 ;
+ RECT 427.120000 2250.880000 428.220000 2251.360000 ;
+ RECT 436.430000 2256.320000 437.430000 2256.800000 ;
+ RECT 436.430000 2250.880000 437.430000 2251.360000 ;
+ RECT 382.120000 2294.400000 383.220000 2294.880000 ;
+ RECT 382.120000 2288.960000 383.220000 2289.440000 ;
+ RECT 382.120000 2283.520000 383.220000 2284.000000 ;
+ RECT 382.120000 2278.080000 383.220000 2278.560000 ;
+ RECT 382.120000 2267.200000 383.220000 2267.680000 ;
+ RECT 382.120000 2261.760000 383.220000 2262.240000 ;
+ RECT 382.120000 2256.320000 383.220000 2256.800000 ;
+ RECT 382.120000 2250.880000 383.220000 2251.360000 ;
+ RECT 382.120000 2272.640000 383.220000 2273.120000 ;
+ RECT 337.120000 2337.920000 338.220000 2338.400000 ;
+ RECT 337.120000 2332.480000 338.220000 2332.960000 ;
+ RECT 337.120000 2327.040000 338.220000 2327.520000 ;
+ RECT 292.120000 2337.920000 293.220000 2338.400000 ;
+ RECT 292.120000 2332.480000 293.220000 2332.960000 ;
+ RECT 292.120000 2327.040000 293.220000 2327.520000 ;
+ RECT 337.120000 2310.720000 338.220000 2311.200000 ;
+ RECT 337.120000 2305.280000 338.220000 2305.760000 ;
+ RECT 337.120000 2299.840000 338.220000 2300.320000 ;
+ RECT 337.120000 2316.160000 338.220000 2316.640000 ;
+ RECT 337.120000 2321.600000 338.220000 2322.080000 ;
+ RECT 292.120000 2321.600000 293.220000 2322.080000 ;
+ RECT 292.120000 2310.720000 293.220000 2311.200000 ;
+ RECT 292.120000 2305.280000 293.220000 2305.760000 ;
+ RECT 292.120000 2299.840000 293.220000 2300.320000 ;
+ RECT 292.120000 2316.160000 293.220000 2316.640000 ;
+ RECT 247.120000 2337.920000 248.220000 2338.400000 ;
+ RECT 242.990000 2337.920000 243.990000 2338.400000 ;
+ RECT 242.990000 2332.480000 243.990000 2332.960000 ;
+ RECT 247.120000 2332.480000 248.220000 2332.960000 ;
+ RECT 247.120000 2327.040000 248.220000 2327.520000 ;
+ RECT 242.990000 2327.040000 243.990000 2327.520000 ;
+ RECT 247.120000 2321.600000 248.220000 2322.080000 ;
+ RECT 242.990000 2321.600000 243.990000 2322.080000 ;
+ RECT 247.120000 2316.160000 248.220000 2316.640000 ;
+ RECT 242.990000 2316.160000 243.990000 2316.640000 ;
+ RECT 247.120000 2305.280000 248.220000 2305.760000 ;
+ RECT 242.990000 2305.280000 243.990000 2305.760000 ;
+ RECT 247.120000 2299.840000 248.220000 2300.320000 ;
+ RECT 242.990000 2299.840000 243.990000 2300.320000 ;
+ RECT 247.120000 2310.720000 248.220000 2311.200000 ;
+ RECT 242.990000 2310.720000 243.990000 2311.200000 ;
+ RECT 337.120000 2294.400000 338.220000 2294.880000 ;
+ RECT 337.120000 2288.960000 338.220000 2289.440000 ;
+ RECT 337.120000 2283.520000 338.220000 2284.000000 ;
+ RECT 337.120000 2278.080000 338.220000 2278.560000 ;
+ RECT 292.120000 2294.400000 293.220000 2294.880000 ;
+ RECT 292.120000 2288.960000 293.220000 2289.440000 ;
+ RECT 292.120000 2283.520000 293.220000 2284.000000 ;
+ RECT 292.120000 2278.080000 293.220000 2278.560000 ;
+ RECT 337.120000 2267.200000 338.220000 2267.680000 ;
+ RECT 337.120000 2250.880000 338.220000 2251.360000 ;
+ RECT 337.120000 2256.320000 338.220000 2256.800000 ;
+ RECT 337.120000 2261.760000 338.220000 2262.240000 ;
+ RECT 337.120000 2272.640000 338.220000 2273.120000 ;
+ RECT 292.120000 2250.880000 293.220000 2251.360000 ;
+ RECT 292.120000 2256.320000 293.220000 2256.800000 ;
+ RECT 292.120000 2261.760000 293.220000 2262.240000 ;
+ RECT 292.120000 2267.200000 293.220000 2267.680000 ;
+ RECT 292.120000 2272.640000 293.220000 2273.120000 ;
+ RECT 247.120000 2294.400000 248.220000 2294.880000 ;
+ RECT 242.990000 2294.400000 243.990000 2294.880000 ;
+ RECT 247.120000 2288.960000 248.220000 2289.440000 ;
+ RECT 242.990000 2288.960000 243.990000 2289.440000 ;
+ RECT 247.120000 2283.520000 248.220000 2284.000000 ;
+ RECT 242.990000 2283.520000 243.990000 2284.000000 ;
+ RECT 247.120000 2278.080000 248.220000 2278.560000 ;
+ RECT 242.990000 2278.080000 243.990000 2278.560000 ;
+ RECT 247.120000 2272.640000 248.220000 2273.120000 ;
+ RECT 247.120000 2267.200000 248.220000 2267.680000 ;
+ RECT 242.990000 2272.640000 243.990000 2273.120000 ;
+ RECT 242.990000 2267.200000 243.990000 2267.680000 ;
+ RECT 247.120000 2261.760000 248.220000 2262.240000 ;
+ RECT 242.990000 2261.760000 243.990000 2262.240000 ;
+ RECT 247.120000 2256.320000 248.220000 2256.800000 ;
+ RECT 242.990000 2256.320000 243.990000 2256.800000 ;
+ RECT 247.120000 2250.880000 248.220000 2251.360000 ;
+ RECT 242.990000 2250.880000 243.990000 2251.360000 ;
+ RECT 427.120000 2245.440000 428.220000 2245.920000 ;
+ RECT 427.120000 2240.000000 428.220000 2240.480000 ;
+ RECT 436.430000 2245.440000 437.430000 2245.920000 ;
+ RECT 436.430000 2240.000000 437.430000 2240.480000 ;
+ RECT 436.430000 2223.680000 437.430000 2224.160000 ;
+ RECT 436.430000 2229.120000 437.430000 2229.600000 ;
+ RECT 436.430000 2234.560000 437.430000 2235.040000 ;
+ RECT 427.120000 2234.560000 428.220000 2235.040000 ;
+ RECT 427.120000 2229.120000 428.220000 2229.600000 ;
+ RECT 427.120000 2223.680000 428.220000 2224.160000 ;
+ RECT 427.120000 2212.800000 428.220000 2213.280000 ;
+ RECT 427.120000 2218.240000 428.220000 2218.720000 ;
+ RECT 436.430000 2218.240000 437.430000 2218.720000 ;
+ RECT 436.430000 2212.800000 437.430000 2213.280000 ;
+ RECT 436.430000 2201.920000 437.430000 2202.400000 ;
+ RECT 436.430000 2207.360000 437.430000 2207.840000 ;
+ RECT 427.120000 2201.920000 428.220000 2202.400000 ;
+ RECT 427.120000 2207.360000 428.220000 2207.840000 ;
+ RECT 382.120000 2245.440000 383.220000 2245.920000 ;
+ RECT 382.120000 2240.000000 383.220000 2240.480000 ;
+ RECT 382.120000 2234.560000 383.220000 2235.040000 ;
+ RECT 382.120000 2229.120000 383.220000 2229.600000 ;
+ RECT 382.120000 2223.680000 383.220000 2224.160000 ;
+ RECT 382.120000 2201.920000 383.220000 2202.400000 ;
+ RECT 382.120000 2207.360000 383.220000 2207.840000 ;
+ RECT 382.120000 2212.800000 383.220000 2213.280000 ;
+ RECT 382.120000 2218.240000 383.220000 2218.720000 ;
+ RECT 427.120000 2196.480000 428.220000 2196.960000 ;
+ RECT 427.120000 2191.040000 428.220000 2191.520000 ;
+ RECT 436.430000 2196.480000 437.430000 2196.960000 ;
+ RECT 436.430000 2191.040000 437.430000 2191.520000 ;
+ RECT 427.120000 2180.160000 428.220000 2180.640000 ;
+ RECT 427.120000 2174.720000 428.220000 2175.200000 ;
+ RECT 436.430000 2180.160000 437.430000 2180.640000 ;
+ RECT 436.430000 2174.720000 437.430000 2175.200000 ;
+ RECT 427.120000 2185.600000 428.220000 2186.080000 ;
+ RECT 436.430000 2185.600000 437.430000 2186.080000 ;
+ RECT 436.430000 2163.840000 437.430000 2164.320000 ;
+ RECT 436.430000 2169.280000 437.430000 2169.760000 ;
+ RECT 427.120000 2169.280000 428.220000 2169.760000 ;
+ RECT 427.120000 2163.840000 428.220000 2164.320000 ;
+ RECT 427.120000 2158.400000 428.220000 2158.880000 ;
+ RECT 427.120000 2152.960000 428.220000 2153.440000 ;
+ RECT 436.430000 2158.400000 437.430000 2158.880000 ;
+ RECT 436.430000 2152.960000 437.430000 2153.440000 ;
+ RECT 382.120000 2196.480000 383.220000 2196.960000 ;
+ RECT 382.120000 2191.040000 383.220000 2191.520000 ;
+ RECT 382.120000 2185.600000 383.220000 2186.080000 ;
+ RECT 382.120000 2180.160000 383.220000 2180.640000 ;
+ RECT 382.120000 2174.720000 383.220000 2175.200000 ;
+ RECT 382.120000 2169.280000 383.220000 2169.760000 ;
+ RECT 382.120000 2163.840000 383.220000 2164.320000 ;
+ RECT 382.120000 2158.400000 383.220000 2158.880000 ;
+ RECT 382.120000 2152.960000 383.220000 2153.440000 ;
+ RECT 337.120000 2245.440000 338.220000 2245.920000 ;
+ RECT 337.120000 2240.000000 338.220000 2240.480000 ;
+ RECT 337.120000 2234.560000 338.220000 2235.040000 ;
+ RECT 337.120000 2229.120000 338.220000 2229.600000 ;
+ RECT 337.120000 2223.680000 338.220000 2224.160000 ;
+ RECT 292.120000 2245.440000 293.220000 2245.920000 ;
+ RECT 292.120000 2240.000000 293.220000 2240.480000 ;
+ RECT 292.120000 2234.560000 293.220000 2235.040000 ;
+ RECT 292.120000 2229.120000 293.220000 2229.600000 ;
+ RECT 292.120000 2223.680000 293.220000 2224.160000 ;
+ RECT 337.120000 2218.240000 338.220000 2218.720000 ;
+ RECT 337.120000 2212.800000 338.220000 2213.280000 ;
+ RECT 337.120000 2207.360000 338.220000 2207.840000 ;
+ RECT 337.120000 2201.920000 338.220000 2202.400000 ;
+ RECT 292.120000 2212.800000 293.220000 2213.280000 ;
+ RECT 292.120000 2207.360000 293.220000 2207.840000 ;
+ RECT 292.120000 2201.920000 293.220000 2202.400000 ;
+ RECT 292.120000 2218.240000 293.220000 2218.720000 ;
+ RECT 247.120000 2245.440000 248.220000 2245.920000 ;
+ RECT 242.990000 2245.440000 243.990000 2245.920000 ;
+ RECT 247.120000 2240.000000 248.220000 2240.480000 ;
+ RECT 242.990000 2240.000000 243.990000 2240.480000 ;
+ RECT 247.120000 2234.560000 248.220000 2235.040000 ;
+ RECT 242.990000 2234.560000 243.990000 2235.040000 ;
+ RECT 247.120000 2223.680000 248.220000 2224.160000 ;
+ RECT 242.990000 2223.680000 243.990000 2224.160000 ;
+ RECT 242.990000 2229.120000 243.990000 2229.600000 ;
+ RECT 247.120000 2229.120000 248.220000 2229.600000 ;
+ RECT 247.120000 2218.240000 248.220000 2218.720000 ;
+ RECT 242.990000 2218.240000 243.990000 2218.720000 ;
+ RECT 247.120000 2212.800000 248.220000 2213.280000 ;
+ RECT 242.990000 2212.800000 243.990000 2213.280000 ;
+ RECT 247.120000 2207.360000 248.220000 2207.840000 ;
+ RECT 242.990000 2207.360000 243.990000 2207.840000 ;
+ RECT 247.120000 2201.920000 248.220000 2202.400000 ;
+ RECT 242.990000 2201.920000 243.990000 2202.400000 ;
+ RECT 337.120000 2196.480000 338.220000 2196.960000 ;
+ RECT 337.120000 2191.040000 338.220000 2191.520000 ;
+ RECT 337.120000 2185.600000 338.220000 2186.080000 ;
+ RECT 337.120000 2180.160000 338.220000 2180.640000 ;
+ RECT 337.120000 2174.720000 338.220000 2175.200000 ;
+ RECT 292.120000 2196.480000 293.220000 2196.960000 ;
+ RECT 292.120000 2191.040000 293.220000 2191.520000 ;
+ RECT 292.120000 2185.600000 293.220000 2186.080000 ;
+ RECT 292.120000 2180.160000 293.220000 2180.640000 ;
+ RECT 292.120000 2174.720000 293.220000 2175.200000 ;
+ RECT 337.120000 2152.960000 338.220000 2153.440000 ;
+ RECT 337.120000 2158.400000 338.220000 2158.880000 ;
+ RECT 337.120000 2163.840000 338.220000 2164.320000 ;
+ RECT 337.120000 2169.280000 338.220000 2169.760000 ;
+ RECT 292.120000 2152.960000 293.220000 2153.440000 ;
+ RECT 292.120000 2158.400000 293.220000 2158.880000 ;
+ RECT 292.120000 2163.840000 293.220000 2164.320000 ;
+ RECT 292.120000 2169.280000 293.220000 2169.760000 ;
+ RECT 247.120000 2196.480000 248.220000 2196.960000 ;
+ RECT 242.990000 2196.480000 243.990000 2196.960000 ;
+ RECT 247.120000 2191.040000 248.220000 2191.520000 ;
+ RECT 242.990000 2191.040000 243.990000 2191.520000 ;
+ RECT 247.120000 2180.160000 248.220000 2180.640000 ;
+ RECT 242.990000 2180.160000 243.990000 2180.640000 ;
+ RECT 247.120000 2174.720000 248.220000 2175.200000 ;
+ RECT 242.990000 2174.720000 243.990000 2175.200000 ;
+ RECT 247.120000 2185.600000 248.220000 2186.080000 ;
+ RECT 242.990000 2185.600000 243.990000 2186.080000 ;
+ RECT 247.120000 2169.280000 248.220000 2169.760000 ;
+ RECT 242.990000 2169.280000 243.990000 2169.760000 ;
+ RECT 247.120000 2163.840000 248.220000 2164.320000 ;
+ RECT 242.990000 2163.840000 243.990000 2164.320000 ;
+ RECT 247.120000 2158.400000 248.220000 2158.880000 ;
+ RECT 247.120000 2152.960000 248.220000 2153.440000 ;
+ RECT 242.990000 2158.400000 243.990000 2158.880000 ;
+ RECT 242.990000 2152.960000 243.990000 2153.440000 ;
+ RECT 240.160000 2343.320000 440.260000 2344.320000 ;
+ RECT 240.160000 2150.950000 440.260000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 2148.100000 243.990000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 2347.360000 243.990000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 2148.100000 437.430000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 2347.360000 437.430000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2150.950000 241.160000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2150.950000 440.260000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2343.320000 241.160000 2344.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2343.320000 440.260000 2344.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 1950.690000 428.220000 2144.060000 ;
+ RECT 382.120000 1950.690000 383.220000 2144.060000 ;
+ RECT 436.430000 1947.840000 437.430000 2148.100000 ;
+ RECT 337.120000 1950.690000 338.220000 2144.060000 ;
+ RECT 292.120000 1950.690000 293.220000 2144.060000 ;
+ RECT 247.120000 1950.690000 248.220000 2144.060000 ;
+ RECT 242.990000 1947.840000 243.990000 2148.100000 ;
+ LAYER met3 ;
+ RECT 427.120000 2137.660000 428.220000 2138.140000 ;
+ RECT 436.430000 2137.660000 437.430000 2138.140000 ;
+ RECT 436.430000 2126.780000 437.430000 2127.260000 ;
+ RECT 436.430000 2132.220000 437.430000 2132.700000 ;
+ RECT 427.120000 2132.220000 428.220000 2132.700000 ;
+ RECT 427.120000 2126.780000 428.220000 2127.260000 ;
+ RECT 427.120000 2121.340000 428.220000 2121.820000 ;
+ RECT 427.120000 2115.900000 428.220000 2116.380000 ;
+ RECT 436.430000 2121.340000 437.430000 2121.820000 ;
+ RECT 436.430000 2115.900000 437.430000 2116.380000 ;
+ RECT 427.120000 2099.580000 428.220000 2100.060000 ;
+ RECT 427.120000 2105.020000 428.220000 2105.500000 ;
+ RECT 436.430000 2105.020000 437.430000 2105.500000 ;
+ RECT 436.430000 2099.580000 437.430000 2100.060000 ;
+ RECT 427.120000 2110.460000 428.220000 2110.940000 ;
+ RECT 436.430000 2110.460000 437.430000 2110.940000 ;
+ RECT 382.120000 2137.660000 383.220000 2138.140000 ;
+ RECT 382.120000 2132.220000 383.220000 2132.700000 ;
+ RECT 382.120000 2126.780000 383.220000 2127.260000 ;
+ RECT 382.120000 2121.340000 383.220000 2121.820000 ;
+ RECT 382.120000 2099.580000 383.220000 2100.060000 ;
+ RECT 382.120000 2105.020000 383.220000 2105.500000 ;
+ RECT 382.120000 2110.460000 383.220000 2110.940000 ;
+ RECT 382.120000 2115.900000 383.220000 2116.380000 ;
+ RECT 436.430000 2088.700000 437.430000 2089.180000 ;
+ RECT 436.430000 2094.140000 437.430000 2094.620000 ;
+ RECT 427.120000 2094.140000 428.220000 2094.620000 ;
+ RECT 427.120000 2088.700000 428.220000 2089.180000 ;
+ RECT 427.120000 2083.260000 428.220000 2083.740000 ;
+ RECT 427.120000 2077.820000 428.220000 2078.300000 ;
+ RECT 436.430000 2083.260000 437.430000 2083.740000 ;
+ RECT 436.430000 2077.820000 437.430000 2078.300000 ;
+ RECT 436.430000 2061.500000 437.430000 2061.980000 ;
+ RECT 436.430000 2066.940000 437.430000 2067.420000 ;
+ RECT 436.430000 2072.380000 437.430000 2072.860000 ;
+ RECT 427.120000 2066.940000 428.220000 2067.420000 ;
+ RECT 427.120000 2061.500000 428.220000 2061.980000 ;
+ RECT 427.120000 2072.380000 428.220000 2072.860000 ;
+ RECT 427.120000 2056.060000 428.220000 2056.540000 ;
+ RECT 427.120000 2050.620000 428.220000 2051.100000 ;
+ RECT 436.430000 2056.060000 437.430000 2056.540000 ;
+ RECT 436.430000 2050.620000 437.430000 2051.100000 ;
+ RECT 382.120000 2094.140000 383.220000 2094.620000 ;
+ RECT 382.120000 2088.700000 383.220000 2089.180000 ;
+ RECT 382.120000 2083.260000 383.220000 2083.740000 ;
+ RECT 382.120000 2077.820000 383.220000 2078.300000 ;
+ RECT 382.120000 2066.940000 383.220000 2067.420000 ;
+ RECT 382.120000 2061.500000 383.220000 2061.980000 ;
+ RECT 382.120000 2056.060000 383.220000 2056.540000 ;
+ RECT 382.120000 2050.620000 383.220000 2051.100000 ;
+ RECT 382.120000 2072.380000 383.220000 2072.860000 ;
+ RECT 337.120000 2137.660000 338.220000 2138.140000 ;
+ RECT 337.120000 2132.220000 338.220000 2132.700000 ;
+ RECT 337.120000 2126.780000 338.220000 2127.260000 ;
+ RECT 292.120000 2137.660000 293.220000 2138.140000 ;
+ RECT 292.120000 2132.220000 293.220000 2132.700000 ;
+ RECT 292.120000 2126.780000 293.220000 2127.260000 ;
+ RECT 337.120000 2110.460000 338.220000 2110.940000 ;
+ RECT 337.120000 2105.020000 338.220000 2105.500000 ;
+ RECT 337.120000 2099.580000 338.220000 2100.060000 ;
+ RECT 337.120000 2115.900000 338.220000 2116.380000 ;
+ RECT 337.120000 2121.340000 338.220000 2121.820000 ;
+ RECT 292.120000 2121.340000 293.220000 2121.820000 ;
+ RECT 292.120000 2110.460000 293.220000 2110.940000 ;
+ RECT 292.120000 2105.020000 293.220000 2105.500000 ;
+ RECT 292.120000 2099.580000 293.220000 2100.060000 ;
+ RECT 292.120000 2115.900000 293.220000 2116.380000 ;
+ RECT 247.120000 2137.660000 248.220000 2138.140000 ;
+ RECT 242.990000 2137.660000 243.990000 2138.140000 ;
+ RECT 242.990000 2132.220000 243.990000 2132.700000 ;
+ RECT 247.120000 2132.220000 248.220000 2132.700000 ;
+ RECT 247.120000 2126.780000 248.220000 2127.260000 ;
+ RECT 242.990000 2126.780000 243.990000 2127.260000 ;
+ RECT 247.120000 2121.340000 248.220000 2121.820000 ;
+ RECT 242.990000 2121.340000 243.990000 2121.820000 ;
+ RECT 247.120000 2115.900000 248.220000 2116.380000 ;
+ RECT 242.990000 2115.900000 243.990000 2116.380000 ;
+ RECT 247.120000 2105.020000 248.220000 2105.500000 ;
+ RECT 242.990000 2105.020000 243.990000 2105.500000 ;
+ RECT 247.120000 2099.580000 248.220000 2100.060000 ;
+ RECT 242.990000 2099.580000 243.990000 2100.060000 ;
+ RECT 247.120000 2110.460000 248.220000 2110.940000 ;
+ RECT 242.990000 2110.460000 243.990000 2110.940000 ;
+ RECT 337.120000 2094.140000 338.220000 2094.620000 ;
+ RECT 337.120000 2088.700000 338.220000 2089.180000 ;
+ RECT 337.120000 2083.260000 338.220000 2083.740000 ;
+ RECT 337.120000 2077.820000 338.220000 2078.300000 ;
+ RECT 292.120000 2094.140000 293.220000 2094.620000 ;
+ RECT 292.120000 2088.700000 293.220000 2089.180000 ;
+ RECT 292.120000 2083.260000 293.220000 2083.740000 ;
+ RECT 292.120000 2077.820000 293.220000 2078.300000 ;
+ RECT 337.120000 2066.940000 338.220000 2067.420000 ;
+ RECT 337.120000 2050.620000 338.220000 2051.100000 ;
+ RECT 337.120000 2056.060000 338.220000 2056.540000 ;
+ RECT 337.120000 2061.500000 338.220000 2061.980000 ;
+ RECT 337.120000 2072.380000 338.220000 2072.860000 ;
+ RECT 292.120000 2050.620000 293.220000 2051.100000 ;
+ RECT 292.120000 2056.060000 293.220000 2056.540000 ;
+ RECT 292.120000 2061.500000 293.220000 2061.980000 ;
+ RECT 292.120000 2066.940000 293.220000 2067.420000 ;
+ RECT 292.120000 2072.380000 293.220000 2072.860000 ;
+ RECT 247.120000 2094.140000 248.220000 2094.620000 ;
+ RECT 242.990000 2094.140000 243.990000 2094.620000 ;
+ RECT 247.120000 2088.700000 248.220000 2089.180000 ;
+ RECT 242.990000 2088.700000 243.990000 2089.180000 ;
+ RECT 247.120000 2083.260000 248.220000 2083.740000 ;
+ RECT 242.990000 2083.260000 243.990000 2083.740000 ;
+ RECT 247.120000 2077.820000 248.220000 2078.300000 ;
+ RECT 242.990000 2077.820000 243.990000 2078.300000 ;
+ RECT 247.120000 2072.380000 248.220000 2072.860000 ;
+ RECT 247.120000 2066.940000 248.220000 2067.420000 ;
+ RECT 242.990000 2072.380000 243.990000 2072.860000 ;
+ RECT 242.990000 2066.940000 243.990000 2067.420000 ;
+ RECT 247.120000 2061.500000 248.220000 2061.980000 ;
+ RECT 242.990000 2061.500000 243.990000 2061.980000 ;
+ RECT 247.120000 2056.060000 248.220000 2056.540000 ;
+ RECT 242.990000 2056.060000 243.990000 2056.540000 ;
+ RECT 247.120000 2050.620000 248.220000 2051.100000 ;
+ RECT 242.990000 2050.620000 243.990000 2051.100000 ;
+ RECT 427.120000 2045.180000 428.220000 2045.660000 ;
+ RECT 427.120000 2039.740000 428.220000 2040.220000 ;
+ RECT 436.430000 2045.180000 437.430000 2045.660000 ;
+ RECT 436.430000 2039.740000 437.430000 2040.220000 ;
+ RECT 436.430000 2023.420000 437.430000 2023.900000 ;
+ RECT 436.430000 2028.860000 437.430000 2029.340000 ;
+ RECT 436.430000 2034.300000 437.430000 2034.780000 ;
+ RECT 427.120000 2034.300000 428.220000 2034.780000 ;
+ RECT 427.120000 2028.860000 428.220000 2029.340000 ;
+ RECT 427.120000 2023.420000 428.220000 2023.900000 ;
+ RECT 427.120000 2012.540000 428.220000 2013.020000 ;
+ RECT 427.120000 2017.980000 428.220000 2018.460000 ;
+ RECT 436.430000 2017.980000 437.430000 2018.460000 ;
+ RECT 436.430000 2012.540000 437.430000 2013.020000 ;
+ RECT 436.430000 2001.660000 437.430000 2002.140000 ;
+ RECT 436.430000 2007.100000 437.430000 2007.580000 ;
+ RECT 427.120000 2001.660000 428.220000 2002.140000 ;
+ RECT 427.120000 2007.100000 428.220000 2007.580000 ;
+ RECT 382.120000 2045.180000 383.220000 2045.660000 ;
+ RECT 382.120000 2039.740000 383.220000 2040.220000 ;
+ RECT 382.120000 2034.300000 383.220000 2034.780000 ;
+ RECT 382.120000 2028.860000 383.220000 2029.340000 ;
+ RECT 382.120000 2023.420000 383.220000 2023.900000 ;
+ RECT 382.120000 2001.660000 383.220000 2002.140000 ;
+ RECT 382.120000 2007.100000 383.220000 2007.580000 ;
+ RECT 382.120000 2012.540000 383.220000 2013.020000 ;
+ RECT 382.120000 2017.980000 383.220000 2018.460000 ;
+ RECT 427.120000 1996.220000 428.220000 1996.700000 ;
+ RECT 427.120000 1990.780000 428.220000 1991.260000 ;
+ RECT 436.430000 1996.220000 437.430000 1996.700000 ;
+ RECT 436.430000 1990.780000 437.430000 1991.260000 ;
+ RECT 427.120000 1979.900000 428.220000 1980.380000 ;
+ RECT 427.120000 1974.460000 428.220000 1974.940000 ;
+ RECT 436.430000 1979.900000 437.430000 1980.380000 ;
+ RECT 436.430000 1974.460000 437.430000 1974.940000 ;
+ RECT 427.120000 1985.340000 428.220000 1985.820000 ;
+ RECT 436.430000 1985.340000 437.430000 1985.820000 ;
+ RECT 436.430000 1963.580000 437.430000 1964.060000 ;
+ RECT 436.430000 1969.020000 437.430000 1969.500000 ;
+ RECT 427.120000 1969.020000 428.220000 1969.500000 ;
+ RECT 427.120000 1963.580000 428.220000 1964.060000 ;
+ RECT 427.120000 1958.140000 428.220000 1958.620000 ;
+ RECT 427.120000 1952.700000 428.220000 1953.180000 ;
+ RECT 436.430000 1958.140000 437.430000 1958.620000 ;
+ RECT 436.430000 1952.700000 437.430000 1953.180000 ;
+ RECT 382.120000 1996.220000 383.220000 1996.700000 ;
+ RECT 382.120000 1990.780000 383.220000 1991.260000 ;
+ RECT 382.120000 1985.340000 383.220000 1985.820000 ;
+ RECT 382.120000 1979.900000 383.220000 1980.380000 ;
+ RECT 382.120000 1974.460000 383.220000 1974.940000 ;
+ RECT 382.120000 1969.020000 383.220000 1969.500000 ;
+ RECT 382.120000 1963.580000 383.220000 1964.060000 ;
+ RECT 382.120000 1958.140000 383.220000 1958.620000 ;
+ RECT 382.120000 1952.700000 383.220000 1953.180000 ;
+ RECT 337.120000 2045.180000 338.220000 2045.660000 ;
+ RECT 337.120000 2039.740000 338.220000 2040.220000 ;
+ RECT 337.120000 2034.300000 338.220000 2034.780000 ;
+ RECT 337.120000 2028.860000 338.220000 2029.340000 ;
+ RECT 337.120000 2023.420000 338.220000 2023.900000 ;
+ RECT 292.120000 2045.180000 293.220000 2045.660000 ;
+ RECT 292.120000 2039.740000 293.220000 2040.220000 ;
+ RECT 292.120000 2034.300000 293.220000 2034.780000 ;
+ RECT 292.120000 2028.860000 293.220000 2029.340000 ;
+ RECT 292.120000 2023.420000 293.220000 2023.900000 ;
+ RECT 337.120000 2017.980000 338.220000 2018.460000 ;
+ RECT 337.120000 2012.540000 338.220000 2013.020000 ;
+ RECT 337.120000 2007.100000 338.220000 2007.580000 ;
+ RECT 337.120000 2001.660000 338.220000 2002.140000 ;
+ RECT 292.120000 2012.540000 293.220000 2013.020000 ;
+ RECT 292.120000 2007.100000 293.220000 2007.580000 ;
+ RECT 292.120000 2001.660000 293.220000 2002.140000 ;
+ RECT 292.120000 2017.980000 293.220000 2018.460000 ;
+ RECT 247.120000 2045.180000 248.220000 2045.660000 ;
+ RECT 242.990000 2045.180000 243.990000 2045.660000 ;
+ RECT 247.120000 2039.740000 248.220000 2040.220000 ;
+ RECT 242.990000 2039.740000 243.990000 2040.220000 ;
+ RECT 247.120000 2034.300000 248.220000 2034.780000 ;
+ RECT 242.990000 2034.300000 243.990000 2034.780000 ;
+ RECT 247.120000 2023.420000 248.220000 2023.900000 ;
+ RECT 242.990000 2023.420000 243.990000 2023.900000 ;
+ RECT 242.990000 2028.860000 243.990000 2029.340000 ;
+ RECT 247.120000 2028.860000 248.220000 2029.340000 ;
+ RECT 247.120000 2017.980000 248.220000 2018.460000 ;
+ RECT 242.990000 2017.980000 243.990000 2018.460000 ;
+ RECT 247.120000 2012.540000 248.220000 2013.020000 ;
+ RECT 242.990000 2012.540000 243.990000 2013.020000 ;
+ RECT 247.120000 2007.100000 248.220000 2007.580000 ;
+ RECT 242.990000 2007.100000 243.990000 2007.580000 ;
+ RECT 247.120000 2001.660000 248.220000 2002.140000 ;
+ RECT 242.990000 2001.660000 243.990000 2002.140000 ;
+ RECT 337.120000 1996.220000 338.220000 1996.700000 ;
+ RECT 337.120000 1990.780000 338.220000 1991.260000 ;
+ RECT 337.120000 1985.340000 338.220000 1985.820000 ;
+ RECT 337.120000 1979.900000 338.220000 1980.380000 ;
+ RECT 337.120000 1974.460000 338.220000 1974.940000 ;
+ RECT 292.120000 1996.220000 293.220000 1996.700000 ;
+ RECT 292.120000 1990.780000 293.220000 1991.260000 ;
+ RECT 292.120000 1985.340000 293.220000 1985.820000 ;
+ RECT 292.120000 1979.900000 293.220000 1980.380000 ;
+ RECT 292.120000 1974.460000 293.220000 1974.940000 ;
+ RECT 337.120000 1952.700000 338.220000 1953.180000 ;
+ RECT 337.120000 1958.140000 338.220000 1958.620000 ;
+ RECT 337.120000 1963.580000 338.220000 1964.060000 ;
+ RECT 337.120000 1969.020000 338.220000 1969.500000 ;
+ RECT 292.120000 1952.700000 293.220000 1953.180000 ;
+ RECT 292.120000 1958.140000 293.220000 1958.620000 ;
+ RECT 292.120000 1963.580000 293.220000 1964.060000 ;
+ RECT 292.120000 1969.020000 293.220000 1969.500000 ;
+ RECT 247.120000 1996.220000 248.220000 1996.700000 ;
+ RECT 242.990000 1996.220000 243.990000 1996.700000 ;
+ RECT 247.120000 1990.780000 248.220000 1991.260000 ;
+ RECT 242.990000 1990.780000 243.990000 1991.260000 ;
+ RECT 247.120000 1979.900000 248.220000 1980.380000 ;
+ RECT 242.990000 1979.900000 243.990000 1980.380000 ;
+ RECT 247.120000 1974.460000 248.220000 1974.940000 ;
+ RECT 242.990000 1974.460000 243.990000 1974.940000 ;
+ RECT 247.120000 1985.340000 248.220000 1985.820000 ;
+ RECT 242.990000 1985.340000 243.990000 1985.820000 ;
+ RECT 247.120000 1969.020000 248.220000 1969.500000 ;
+ RECT 242.990000 1969.020000 243.990000 1969.500000 ;
+ RECT 247.120000 1963.580000 248.220000 1964.060000 ;
+ RECT 242.990000 1963.580000 243.990000 1964.060000 ;
+ RECT 247.120000 1958.140000 248.220000 1958.620000 ;
+ RECT 247.120000 1952.700000 248.220000 1953.180000 ;
+ RECT 242.990000 1958.140000 243.990000 1958.620000 ;
+ RECT 242.990000 1952.700000 243.990000 1953.180000 ;
+ RECT 240.160000 2143.060000 440.260000 2144.060000 ;
+ RECT 240.160000 1950.690000 440.260000 1951.690000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 1947.840000 243.990000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 2147.100000 243.990000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 1947.840000 437.430000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 2147.100000 437.430000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1950.690000 241.160000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1950.690000 440.260000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 2143.060000 241.160000 2144.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 2143.060000 440.260000 2144.060000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 1750.430000 428.220000 1943.800000 ;
+ RECT 382.120000 1750.430000 383.220000 1943.800000 ;
+ RECT 436.430000 1747.580000 437.430000 1947.840000 ;
+ RECT 337.120000 1750.430000 338.220000 1943.800000 ;
+ RECT 292.120000 1750.430000 293.220000 1943.800000 ;
+ RECT 247.120000 1750.430000 248.220000 1943.800000 ;
+ RECT 242.990000 1747.580000 243.990000 1947.840000 ;
+ LAYER met3 ;
+ RECT 427.120000 1937.400000 428.220000 1937.880000 ;
+ RECT 436.430000 1937.400000 437.430000 1937.880000 ;
+ RECT 436.430000 1926.520000 437.430000 1927.000000 ;
+ RECT 436.430000 1931.960000 437.430000 1932.440000 ;
+ RECT 427.120000 1931.960000 428.220000 1932.440000 ;
+ RECT 427.120000 1926.520000 428.220000 1927.000000 ;
+ RECT 427.120000 1921.080000 428.220000 1921.560000 ;
+ RECT 427.120000 1915.640000 428.220000 1916.120000 ;
+ RECT 436.430000 1921.080000 437.430000 1921.560000 ;
+ RECT 436.430000 1915.640000 437.430000 1916.120000 ;
+ RECT 427.120000 1899.320000 428.220000 1899.800000 ;
+ RECT 427.120000 1904.760000 428.220000 1905.240000 ;
+ RECT 436.430000 1904.760000 437.430000 1905.240000 ;
+ RECT 436.430000 1899.320000 437.430000 1899.800000 ;
+ RECT 427.120000 1910.200000 428.220000 1910.680000 ;
+ RECT 436.430000 1910.200000 437.430000 1910.680000 ;
+ RECT 382.120000 1937.400000 383.220000 1937.880000 ;
+ RECT 382.120000 1931.960000 383.220000 1932.440000 ;
+ RECT 382.120000 1926.520000 383.220000 1927.000000 ;
+ RECT 382.120000 1921.080000 383.220000 1921.560000 ;
+ RECT 382.120000 1899.320000 383.220000 1899.800000 ;
+ RECT 382.120000 1904.760000 383.220000 1905.240000 ;
+ RECT 382.120000 1910.200000 383.220000 1910.680000 ;
+ RECT 382.120000 1915.640000 383.220000 1916.120000 ;
+ RECT 436.430000 1888.440000 437.430000 1888.920000 ;
+ RECT 436.430000 1893.880000 437.430000 1894.360000 ;
+ RECT 427.120000 1893.880000 428.220000 1894.360000 ;
+ RECT 427.120000 1888.440000 428.220000 1888.920000 ;
+ RECT 427.120000 1883.000000 428.220000 1883.480000 ;
+ RECT 427.120000 1877.560000 428.220000 1878.040000 ;
+ RECT 436.430000 1883.000000 437.430000 1883.480000 ;
+ RECT 436.430000 1877.560000 437.430000 1878.040000 ;
+ RECT 436.430000 1861.240000 437.430000 1861.720000 ;
+ RECT 436.430000 1866.680000 437.430000 1867.160000 ;
+ RECT 436.430000 1872.120000 437.430000 1872.600000 ;
+ RECT 427.120000 1866.680000 428.220000 1867.160000 ;
+ RECT 427.120000 1861.240000 428.220000 1861.720000 ;
+ RECT 427.120000 1872.120000 428.220000 1872.600000 ;
+ RECT 427.120000 1855.800000 428.220000 1856.280000 ;
+ RECT 427.120000 1850.360000 428.220000 1850.840000 ;
+ RECT 436.430000 1855.800000 437.430000 1856.280000 ;
+ RECT 436.430000 1850.360000 437.430000 1850.840000 ;
+ RECT 382.120000 1893.880000 383.220000 1894.360000 ;
+ RECT 382.120000 1888.440000 383.220000 1888.920000 ;
+ RECT 382.120000 1883.000000 383.220000 1883.480000 ;
+ RECT 382.120000 1877.560000 383.220000 1878.040000 ;
+ RECT 382.120000 1866.680000 383.220000 1867.160000 ;
+ RECT 382.120000 1861.240000 383.220000 1861.720000 ;
+ RECT 382.120000 1855.800000 383.220000 1856.280000 ;
+ RECT 382.120000 1850.360000 383.220000 1850.840000 ;
+ RECT 382.120000 1872.120000 383.220000 1872.600000 ;
+ RECT 337.120000 1937.400000 338.220000 1937.880000 ;
+ RECT 337.120000 1931.960000 338.220000 1932.440000 ;
+ RECT 337.120000 1926.520000 338.220000 1927.000000 ;
+ RECT 292.120000 1937.400000 293.220000 1937.880000 ;
+ RECT 292.120000 1931.960000 293.220000 1932.440000 ;
+ RECT 292.120000 1926.520000 293.220000 1927.000000 ;
+ RECT 337.120000 1910.200000 338.220000 1910.680000 ;
+ RECT 337.120000 1904.760000 338.220000 1905.240000 ;
+ RECT 337.120000 1899.320000 338.220000 1899.800000 ;
+ RECT 337.120000 1915.640000 338.220000 1916.120000 ;
+ RECT 337.120000 1921.080000 338.220000 1921.560000 ;
+ RECT 292.120000 1921.080000 293.220000 1921.560000 ;
+ RECT 292.120000 1910.200000 293.220000 1910.680000 ;
+ RECT 292.120000 1904.760000 293.220000 1905.240000 ;
+ RECT 292.120000 1899.320000 293.220000 1899.800000 ;
+ RECT 292.120000 1915.640000 293.220000 1916.120000 ;
+ RECT 247.120000 1937.400000 248.220000 1937.880000 ;
+ RECT 242.990000 1937.400000 243.990000 1937.880000 ;
+ RECT 242.990000 1931.960000 243.990000 1932.440000 ;
+ RECT 247.120000 1931.960000 248.220000 1932.440000 ;
+ RECT 247.120000 1926.520000 248.220000 1927.000000 ;
+ RECT 242.990000 1926.520000 243.990000 1927.000000 ;
+ RECT 247.120000 1921.080000 248.220000 1921.560000 ;
+ RECT 242.990000 1921.080000 243.990000 1921.560000 ;
+ RECT 247.120000 1915.640000 248.220000 1916.120000 ;
+ RECT 242.990000 1915.640000 243.990000 1916.120000 ;
+ RECT 247.120000 1904.760000 248.220000 1905.240000 ;
+ RECT 242.990000 1904.760000 243.990000 1905.240000 ;
+ RECT 247.120000 1899.320000 248.220000 1899.800000 ;
+ RECT 242.990000 1899.320000 243.990000 1899.800000 ;
+ RECT 247.120000 1910.200000 248.220000 1910.680000 ;
+ RECT 242.990000 1910.200000 243.990000 1910.680000 ;
+ RECT 337.120000 1893.880000 338.220000 1894.360000 ;
+ RECT 337.120000 1888.440000 338.220000 1888.920000 ;
+ RECT 337.120000 1883.000000 338.220000 1883.480000 ;
+ RECT 337.120000 1877.560000 338.220000 1878.040000 ;
+ RECT 292.120000 1893.880000 293.220000 1894.360000 ;
+ RECT 292.120000 1888.440000 293.220000 1888.920000 ;
+ RECT 292.120000 1883.000000 293.220000 1883.480000 ;
+ RECT 292.120000 1877.560000 293.220000 1878.040000 ;
+ RECT 337.120000 1866.680000 338.220000 1867.160000 ;
+ RECT 337.120000 1850.360000 338.220000 1850.840000 ;
+ RECT 337.120000 1855.800000 338.220000 1856.280000 ;
+ RECT 337.120000 1861.240000 338.220000 1861.720000 ;
+ RECT 337.120000 1872.120000 338.220000 1872.600000 ;
+ RECT 292.120000 1850.360000 293.220000 1850.840000 ;
+ RECT 292.120000 1855.800000 293.220000 1856.280000 ;
+ RECT 292.120000 1861.240000 293.220000 1861.720000 ;
+ RECT 292.120000 1866.680000 293.220000 1867.160000 ;
+ RECT 292.120000 1872.120000 293.220000 1872.600000 ;
+ RECT 247.120000 1893.880000 248.220000 1894.360000 ;
+ RECT 242.990000 1893.880000 243.990000 1894.360000 ;
+ RECT 247.120000 1888.440000 248.220000 1888.920000 ;
+ RECT 242.990000 1888.440000 243.990000 1888.920000 ;
+ RECT 247.120000 1883.000000 248.220000 1883.480000 ;
+ RECT 242.990000 1883.000000 243.990000 1883.480000 ;
+ RECT 247.120000 1877.560000 248.220000 1878.040000 ;
+ RECT 242.990000 1877.560000 243.990000 1878.040000 ;
+ RECT 247.120000 1872.120000 248.220000 1872.600000 ;
+ RECT 247.120000 1866.680000 248.220000 1867.160000 ;
+ RECT 242.990000 1872.120000 243.990000 1872.600000 ;
+ RECT 242.990000 1866.680000 243.990000 1867.160000 ;
+ RECT 247.120000 1861.240000 248.220000 1861.720000 ;
+ RECT 242.990000 1861.240000 243.990000 1861.720000 ;
+ RECT 247.120000 1855.800000 248.220000 1856.280000 ;
+ RECT 242.990000 1855.800000 243.990000 1856.280000 ;
+ RECT 247.120000 1850.360000 248.220000 1850.840000 ;
+ RECT 242.990000 1850.360000 243.990000 1850.840000 ;
+ RECT 427.120000 1844.920000 428.220000 1845.400000 ;
+ RECT 427.120000 1839.480000 428.220000 1839.960000 ;
+ RECT 436.430000 1844.920000 437.430000 1845.400000 ;
+ RECT 436.430000 1839.480000 437.430000 1839.960000 ;
+ RECT 436.430000 1823.160000 437.430000 1823.640000 ;
+ RECT 436.430000 1828.600000 437.430000 1829.080000 ;
+ RECT 436.430000 1834.040000 437.430000 1834.520000 ;
+ RECT 427.120000 1834.040000 428.220000 1834.520000 ;
+ RECT 427.120000 1828.600000 428.220000 1829.080000 ;
+ RECT 427.120000 1823.160000 428.220000 1823.640000 ;
+ RECT 427.120000 1812.280000 428.220000 1812.760000 ;
+ RECT 427.120000 1817.720000 428.220000 1818.200000 ;
+ RECT 436.430000 1817.720000 437.430000 1818.200000 ;
+ RECT 436.430000 1812.280000 437.430000 1812.760000 ;
+ RECT 436.430000 1801.400000 437.430000 1801.880000 ;
+ RECT 436.430000 1806.840000 437.430000 1807.320000 ;
+ RECT 427.120000 1801.400000 428.220000 1801.880000 ;
+ RECT 427.120000 1806.840000 428.220000 1807.320000 ;
+ RECT 382.120000 1844.920000 383.220000 1845.400000 ;
+ RECT 382.120000 1839.480000 383.220000 1839.960000 ;
+ RECT 382.120000 1834.040000 383.220000 1834.520000 ;
+ RECT 382.120000 1828.600000 383.220000 1829.080000 ;
+ RECT 382.120000 1823.160000 383.220000 1823.640000 ;
+ RECT 382.120000 1801.400000 383.220000 1801.880000 ;
+ RECT 382.120000 1806.840000 383.220000 1807.320000 ;
+ RECT 382.120000 1812.280000 383.220000 1812.760000 ;
+ RECT 382.120000 1817.720000 383.220000 1818.200000 ;
+ RECT 427.120000 1795.960000 428.220000 1796.440000 ;
+ RECT 427.120000 1790.520000 428.220000 1791.000000 ;
+ RECT 436.430000 1795.960000 437.430000 1796.440000 ;
+ RECT 436.430000 1790.520000 437.430000 1791.000000 ;
+ RECT 427.120000 1779.640000 428.220000 1780.120000 ;
+ RECT 427.120000 1774.200000 428.220000 1774.680000 ;
+ RECT 436.430000 1779.640000 437.430000 1780.120000 ;
+ RECT 436.430000 1774.200000 437.430000 1774.680000 ;
+ RECT 427.120000 1785.080000 428.220000 1785.560000 ;
+ RECT 436.430000 1785.080000 437.430000 1785.560000 ;
+ RECT 436.430000 1763.320000 437.430000 1763.800000 ;
+ RECT 436.430000 1768.760000 437.430000 1769.240000 ;
+ RECT 427.120000 1768.760000 428.220000 1769.240000 ;
+ RECT 427.120000 1763.320000 428.220000 1763.800000 ;
+ RECT 427.120000 1757.880000 428.220000 1758.360000 ;
+ RECT 427.120000 1752.440000 428.220000 1752.920000 ;
+ RECT 436.430000 1757.880000 437.430000 1758.360000 ;
+ RECT 436.430000 1752.440000 437.430000 1752.920000 ;
+ RECT 382.120000 1795.960000 383.220000 1796.440000 ;
+ RECT 382.120000 1790.520000 383.220000 1791.000000 ;
+ RECT 382.120000 1785.080000 383.220000 1785.560000 ;
+ RECT 382.120000 1779.640000 383.220000 1780.120000 ;
+ RECT 382.120000 1774.200000 383.220000 1774.680000 ;
+ RECT 382.120000 1768.760000 383.220000 1769.240000 ;
+ RECT 382.120000 1763.320000 383.220000 1763.800000 ;
+ RECT 382.120000 1757.880000 383.220000 1758.360000 ;
+ RECT 382.120000 1752.440000 383.220000 1752.920000 ;
+ RECT 337.120000 1844.920000 338.220000 1845.400000 ;
+ RECT 337.120000 1839.480000 338.220000 1839.960000 ;
+ RECT 337.120000 1834.040000 338.220000 1834.520000 ;
+ RECT 337.120000 1828.600000 338.220000 1829.080000 ;
+ RECT 337.120000 1823.160000 338.220000 1823.640000 ;
+ RECT 292.120000 1844.920000 293.220000 1845.400000 ;
+ RECT 292.120000 1839.480000 293.220000 1839.960000 ;
+ RECT 292.120000 1834.040000 293.220000 1834.520000 ;
+ RECT 292.120000 1828.600000 293.220000 1829.080000 ;
+ RECT 292.120000 1823.160000 293.220000 1823.640000 ;
+ RECT 337.120000 1817.720000 338.220000 1818.200000 ;
+ RECT 337.120000 1812.280000 338.220000 1812.760000 ;
+ RECT 337.120000 1806.840000 338.220000 1807.320000 ;
+ RECT 337.120000 1801.400000 338.220000 1801.880000 ;
+ RECT 292.120000 1812.280000 293.220000 1812.760000 ;
+ RECT 292.120000 1806.840000 293.220000 1807.320000 ;
+ RECT 292.120000 1801.400000 293.220000 1801.880000 ;
+ RECT 292.120000 1817.720000 293.220000 1818.200000 ;
+ RECT 247.120000 1844.920000 248.220000 1845.400000 ;
+ RECT 242.990000 1844.920000 243.990000 1845.400000 ;
+ RECT 247.120000 1839.480000 248.220000 1839.960000 ;
+ RECT 242.990000 1839.480000 243.990000 1839.960000 ;
+ RECT 247.120000 1834.040000 248.220000 1834.520000 ;
+ RECT 242.990000 1834.040000 243.990000 1834.520000 ;
+ RECT 247.120000 1823.160000 248.220000 1823.640000 ;
+ RECT 242.990000 1823.160000 243.990000 1823.640000 ;
+ RECT 242.990000 1828.600000 243.990000 1829.080000 ;
+ RECT 247.120000 1828.600000 248.220000 1829.080000 ;
+ RECT 247.120000 1817.720000 248.220000 1818.200000 ;
+ RECT 242.990000 1817.720000 243.990000 1818.200000 ;
+ RECT 247.120000 1812.280000 248.220000 1812.760000 ;
+ RECT 242.990000 1812.280000 243.990000 1812.760000 ;
+ RECT 247.120000 1806.840000 248.220000 1807.320000 ;
+ RECT 242.990000 1806.840000 243.990000 1807.320000 ;
+ RECT 247.120000 1801.400000 248.220000 1801.880000 ;
+ RECT 242.990000 1801.400000 243.990000 1801.880000 ;
+ RECT 337.120000 1795.960000 338.220000 1796.440000 ;
+ RECT 337.120000 1790.520000 338.220000 1791.000000 ;
+ RECT 337.120000 1785.080000 338.220000 1785.560000 ;
+ RECT 337.120000 1779.640000 338.220000 1780.120000 ;
+ RECT 337.120000 1774.200000 338.220000 1774.680000 ;
+ RECT 292.120000 1795.960000 293.220000 1796.440000 ;
+ RECT 292.120000 1790.520000 293.220000 1791.000000 ;
+ RECT 292.120000 1785.080000 293.220000 1785.560000 ;
+ RECT 292.120000 1779.640000 293.220000 1780.120000 ;
+ RECT 292.120000 1774.200000 293.220000 1774.680000 ;
+ RECT 337.120000 1752.440000 338.220000 1752.920000 ;
+ RECT 337.120000 1757.880000 338.220000 1758.360000 ;
+ RECT 337.120000 1763.320000 338.220000 1763.800000 ;
+ RECT 337.120000 1768.760000 338.220000 1769.240000 ;
+ RECT 292.120000 1752.440000 293.220000 1752.920000 ;
+ RECT 292.120000 1757.880000 293.220000 1758.360000 ;
+ RECT 292.120000 1763.320000 293.220000 1763.800000 ;
+ RECT 292.120000 1768.760000 293.220000 1769.240000 ;
+ RECT 247.120000 1795.960000 248.220000 1796.440000 ;
+ RECT 242.990000 1795.960000 243.990000 1796.440000 ;
+ RECT 247.120000 1790.520000 248.220000 1791.000000 ;
+ RECT 242.990000 1790.520000 243.990000 1791.000000 ;
+ RECT 247.120000 1779.640000 248.220000 1780.120000 ;
+ RECT 242.990000 1779.640000 243.990000 1780.120000 ;
+ RECT 247.120000 1774.200000 248.220000 1774.680000 ;
+ RECT 242.990000 1774.200000 243.990000 1774.680000 ;
+ RECT 247.120000 1785.080000 248.220000 1785.560000 ;
+ RECT 242.990000 1785.080000 243.990000 1785.560000 ;
+ RECT 247.120000 1768.760000 248.220000 1769.240000 ;
+ RECT 242.990000 1768.760000 243.990000 1769.240000 ;
+ RECT 247.120000 1763.320000 248.220000 1763.800000 ;
+ RECT 242.990000 1763.320000 243.990000 1763.800000 ;
+ RECT 247.120000 1757.880000 248.220000 1758.360000 ;
+ RECT 247.120000 1752.440000 248.220000 1752.920000 ;
+ RECT 242.990000 1757.880000 243.990000 1758.360000 ;
+ RECT 242.990000 1752.440000 243.990000 1752.920000 ;
+ RECT 240.160000 1942.800000 440.260000 1943.800000 ;
+ RECT 240.160000 1750.430000 440.260000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 1747.580000 243.990000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 1946.840000 243.990000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 1747.580000 437.430000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 1946.840000 437.430000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1750.430000 241.160000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1750.430000 440.260000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1942.800000 241.160000 1943.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1942.800000 440.260000 1943.800000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 427.120000 1550.170000 428.220000 1743.540000 ;
+ RECT 382.120000 1550.170000 383.220000 1743.540000 ;
+ RECT 436.430000 1547.320000 437.430000 1747.580000 ;
+ RECT 337.120000 1550.170000 338.220000 1743.540000 ;
+ RECT 292.120000 1550.170000 293.220000 1743.540000 ;
+ RECT 247.120000 1550.170000 248.220000 1743.540000 ;
+ RECT 242.990000 1547.320000 243.990000 1747.580000 ;
+ LAYER met3 ;
+ RECT 427.120000 1737.140000 428.220000 1737.620000 ;
+ RECT 436.430000 1737.140000 437.430000 1737.620000 ;
+ RECT 436.430000 1726.260000 437.430000 1726.740000 ;
+ RECT 436.430000 1731.700000 437.430000 1732.180000 ;
+ RECT 427.120000 1731.700000 428.220000 1732.180000 ;
+ RECT 427.120000 1726.260000 428.220000 1726.740000 ;
+ RECT 427.120000 1720.820000 428.220000 1721.300000 ;
+ RECT 427.120000 1715.380000 428.220000 1715.860000 ;
+ RECT 436.430000 1720.820000 437.430000 1721.300000 ;
+ RECT 436.430000 1715.380000 437.430000 1715.860000 ;
+ RECT 427.120000 1699.060000 428.220000 1699.540000 ;
+ RECT 427.120000 1704.500000 428.220000 1704.980000 ;
+ RECT 436.430000 1704.500000 437.430000 1704.980000 ;
+ RECT 436.430000 1699.060000 437.430000 1699.540000 ;
+ RECT 427.120000 1709.940000 428.220000 1710.420000 ;
+ RECT 436.430000 1709.940000 437.430000 1710.420000 ;
+ RECT 382.120000 1737.140000 383.220000 1737.620000 ;
+ RECT 382.120000 1731.700000 383.220000 1732.180000 ;
+ RECT 382.120000 1726.260000 383.220000 1726.740000 ;
+ RECT 382.120000 1720.820000 383.220000 1721.300000 ;
+ RECT 382.120000 1699.060000 383.220000 1699.540000 ;
+ RECT 382.120000 1704.500000 383.220000 1704.980000 ;
+ RECT 382.120000 1709.940000 383.220000 1710.420000 ;
+ RECT 382.120000 1715.380000 383.220000 1715.860000 ;
+ RECT 436.430000 1688.180000 437.430000 1688.660000 ;
+ RECT 436.430000 1693.620000 437.430000 1694.100000 ;
+ RECT 427.120000 1693.620000 428.220000 1694.100000 ;
+ RECT 427.120000 1688.180000 428.220000 1688.660000 ;
+ RECT 427.120000 1682.740000 428.220000 1683.220000 ;
+ RECT 427.120000 1677.300000 428.220000 1677.780000 ;
+ RECT 436.430000 1682.740000 437.430000 1683.220000 ;
+ RECT 436.430000 1677.300000 437.430000 1677.780000 ;
+ RECT 436.430000 1660.980000 437.430000 1661.460000 ;
+ RECT 436.430000 1666.420000 437.430000 1666.900000 ;
+ RECT 436.430000 1671.860000 437.430000 1672.340000 ;
+ RECT 427.120000 1666.420000 428.220000 1666.900000 ;
+ RECT 427.120000 1660.980000 428.220000 1661.460000 ;
+ RECT 427.120000 1671.860000 428.220000 1672.340000 ;
+ RECT 427.120000 1655.540000 428.220000 1656.020000 ;
+ RECT 427.120000 1650.100000 428.220000 1650.580000 ;
+ RECT 436.430000 1655.540000 437.430000 1656.020000 ;
+ RECT 436.430000 1650.100000 437.430000 1650.580000 ;
+ RECT 382.120000 1693.620000 383.220000 1694.100000 ;
+ RECT 382.120000 1688.180000 383.220000 1688.660000 ;
+ RECT 382.120000 1682.740000 383.220000 1683.220000 ;
+ RECT 382.120000 1677.300000 383.220000 1677.780000 ;
+ RECT 382.120000 1666.420000 383.220000 1666.900000 ;
+ RECT 382.120000 1660.980000 383.220000 1661.460000 ;
+ RECT 382.120000 1655.540000 383.220000 1656.020000 ;
+ RECT 382.120000 1650.100000 383.220000 1650.580000 ;
+ RECT 382.120000 1671.860000 383.220000 1672.340000 ;
+ RECT 337.120000 1737.140000 338.220000 1737.620000 ;
+ RECT 337.120000 1731.700000 338.220000 1732.180000 ;
+ RECT 337.120000 1726.260000 338.220000 1726.740000 ;
+ RECT 292.120000 1737.140000 293.220000 1737.620000 ;
+ RECT 292.120000 1731.700000 293.220000 1732.180000 ;
+ RECT 292.120000 1726.260000 293.220000 1726.740000 ;
+ RECT 337.120000 1709.940000 338.220000 1710.420000 ;
+ RECT 337.120000 1704.500000 338.220000 1704.980000 ;
+ RECT 337.120000 1699.060000 338.220000 1699.540000 ;
+ RECT 337.120000 1715.380000 338.220000 1715.860000 ;
+ RECT 337.120000 1720.820000 338.220000 1721.300000 ;
+ RECT 292.120000 1720.820000 293.220000 1721.300000 ;
+ RECT 292.120000 1709.940000 293.220000 1710.420000 ;
+ RECT 292.120000 1704.500000 293.220000 1704.980000 ;
+ RECT 292.120000 1699.060000 293.220000 1699.540000 ;
+ RECT 292.120000 1715.380000 293.220000 1715.860000 ;
+ RECT 247.120000 1737.140000 248.220000 1737.620000 ;
+ RECT 242.990000 1737.140000 243.990000 1737.620000 ;
+ RECT 242.990000 1731.700000 243.990000 1732.180000 ;
+ RECT 247.120000 1731.700000 248.220000 1732.180000 ;
+ RECT 247.120000 1726.260000 248.220000 1726.740000 ;
+ RECT 242.990000 1726.260000 243.990000 1726.740000 ;
+ RECT 247.120000 1720.820000 248.220000 1721.300000 ;
+ RECT 242.990000 1720.820000 243.990000 1721.300000 ;
+ RECT 247.120000 1715.380000 248.220000 1715.860000 ;
+ RECT 242.990000 1715.380000 243.990000 1715.860000 ;
+ RECT 247.120000 1704.500000 248.220000 1704.980000 ;
+ RECT 242.990000 1704.500000 243.990000 1704.980000 ;
+ RECT 247.120000 1699.060000 248.220000 1699.540000 ;
+ RECT 242.990000 1699.060000 243.990000 1699.540000 ;
+ RECT 247.120000 1709.940000 248.220000 1710.420000 ;
+ RECT 242.990000 1709.940000 243.990000 1710.420000 ;
+ RECT 337.120000 1693.620000 338.220000 1694.100000 ;
+ RECT 337.120000 1688.180000 338.220000 1688.660000 ;
+ RECT 337.120000 1682.740000 338.220000 1683.220000 ;
+ RECT 337.120000 1677.300000 338.220000 1677.780000 ;
+ RECT 292.120000 1693.620000 293.220000 1694.100000 ;
+ RECT 292.120000 1688.180000 293.220000 1688.660000 ;
+ RECT 292.120000 1682.740000 293.220000 1683.220000 ;
+ RECT 292.120000 1677.300000 293.220000 1677.780000 ;
+ RECT 337.120000 1666.420000 338.220000 1666.900000 ;
+ RECT 337.120000 1650.100000 338.220000 1650.580000 ;
+ RECT 337.120000 1655.540000 338.220000 1656.020000 ;
+ RECT 337.120000 1660.980000 338.220000 1661.460000 ;
+ RECT 337.120000 1671.860000 338.220000 1672.340000 ;
+ RECT 292.120000 1650.100000 293.220000 1650.580000 ;
+ RECT 292.120000 1655.540000 293.220000 1656.020000 ;
+ RECT 292.120000 1660.980000 293.220000 1661.460000 ;
+ RECT 292.120000 1666.420000 293.220000 1666.900000 ;
+ RECT 292.120000 1671.860000 293.220000 1672.340000 ;
+ RECT 247.120000 1693.620000 248.220000 1694.100000 ;
+ RECT 242.990000 1693.620000 243.990000 1694.100000 ;
+ RECT 247.120000 1688.180000 248.220000 1688.660000 ;
+ RECT 242.990000 1688.180000 243.990000 1688.660000 ;
+ RECT 247.120000 1682.740000 248.220000 1683.220000 ;
+ RECT 242.990000 1682.740000 243.990000 1683.220000 ;
+ RECT 247.120000 1677.300000 248.220000 1677.780000 ;
+ RECT 242.990000 1677.300000 243.990000 1677.780000 ;
+ RECT 247.120000 1671.860000 248.220000 1672.340000 ;
+ RECT 247.120000 1666.420000 248.220000 1666.900000 ;
+ RECT 242.990000 1671.860000 243.990000 1672.340000 ;
+ RECT 242.990000 1666.420000 243.990000 1666.900000 ;
+ RECT 247.120000 1660.980000 248.220000 1661.460000 ;
+ RECT 242.990000 1660.980000 243.990000 1661.460000 ;
+ RECT 247.120000 1655.540000 248.220000 1656.020000 ;
+ RECT 242.990000 1655.540000 243.990000 1656.020000 ;
+ RECT 247.120000 1650.100000 248.220000 1650.580000 ;
+ RECT 242.990000 1650.100000 243.990000 1650.580000 ;
+ RECT 427.120000 1644.660000 428.220000 1645.140000 ;
+ RECT 427.120000 1639.220000 428.220000 1639.700000 ;
+ RECT 436.430000 1644.660000 437.430000 1645.140000 ;
+ RECT 436.430000 1639.220000 437.430000 1639.700000 ;
+ RECT 436.430000 1622.900000 437.430000 1623.380000 ;
+ RECT 436.430000 1628.340000 437.430000 1628.820000 ;
+ RECT 436.430000 1633.780000 437.430000 1634.260000 ;
+ RECT 427.120000 1633.780000 428.220000 1634.260000 ;
+ RECT 427.120000 1628.340000 428.220000 1628.820000 ;
+ RECT 427.120000 1622.900000 428.220000 1623.380000 ;
+ RECT 427.120000 1612.020000 428.220000 1612.500000 ;
+ RECT 427.120000 1617.460000 428.220000 1617.940000 ;
+ RECT 436.430000 1617.460000 437.430000 1617.940000 ;
+ RECT 436.430000 1612.020000 437.430000 1612.500000 ;
+ RECT 436.430000 1601.140000 437.430000 1601.620000 ;
+ RECT 436.430000 1606.580000 437.430000 1607.060000 ;
+ RECT 427.120000 1601.140000 428.220000 1601.620000 ;
+ RECT 427.120000 1606.580000 428.220000 1607.060000 ;
+ RECT 382.120000 1644.660000 383.220000 1645.140000 ;
+ RECT 382.120000 1639.220000 383.220000 1639.700000 ;
+ RECT 382.120000 1633.780000 383.220000 1634.260000 ;
+ RECT 382.120000 1628.340000 383.220000 1628.820000 ;
+ RECT 382.120000 1622.900000 383.220000 1623.380000 ;
+ RECT 382.120000 1601.140000 383.220000 1601.620000 ;
+ RECT 382.120000 1606.580000 383.220000 1607.060000 ;
+ RECT 382.120000 1612.020000 383.220000 1612.500000 ;
+ RECT 382.120000 1617.460000 383.220000 1617.940000 ;
+ RECT 427.120000 1595.700000 428.220000 1596.180000 ;
+ RECT 427.120000 1590.260000 428.220000 1590.740000 ;
+ RECT 436.430000 1595.700000 437.430000 1596.180000 ;
+ RECT 436.430000 1590.260000 437.430000 1590.740000 ;
+ RECT 427.120000 1579.380000 428.220000 1579.860000 ;
+ RECT 427.120000 1573.940000 428.220000 1574.420000 ;
+ RECT 436.430000 1579.380000 437.430000 1579.860000 ;
+ RECT 436.430000 1573.940000 437.430000 1574.420000 ;
+ RECT 427.120000 1584.820000 428.220000 1585.300000 ;
+ RECT 436.430000 1584.820000 437.430000 1585.300000 ;
+ RECT 436.430000 1563.060000 437.430000 1563.540000 ;
+ RECT 436.430000 1568.500000 437.430000 1568.980000 ;
+ RECT 427.120000 1568.500000 428.220000 1568.980000 ;
+ RECT 427.120000 1563.060000 428.220000 1563.540000 ;
+ RECT 427.120000 1557.620000 428.220000 1558.100000 ;
+ RECT 427.120000 1552.180000 428.220000 1552.660000 ;
+ RECT 436.430000 1557.620000 437.430000 1558.100000 ;
+ RECT 436.430000 1552.180000 437.430000 1552.660000 ;
+ RECT 382.120000 1595.700000 383.220000 1596.180000 ;
+ RECT 382.120000 1590.260000 383.220000 1590.740000 ;
+ RECT 382.120000 1584.820000 383.220000 1585.300000 ;
+ RECT 382.120000 1579.380000 383.220000 1579.860000 ;
+ RECT 382.120000 1573.940000 383.220000 1574.420000 ;
+ RECT 382.120000 1568.500000 383.220000 1568.980000 ;
+ RECT 382.120000 1563.060000 383.220000 1563.540000 ;
+ RECT 382.120000 1557.620000 383.220000 1558.100000 ;
+ RECT 382.120000 1552.180000 383.220000 1552.660000 ;
+ RECT 337.120000 1644.660000 338.220000 1645.140000 ;
+ RECT 337.120000 1639.220000 338.220000 1639.700000 ;
+ RECT 337.120000 1633.780000 338.220000 1634.260000 ;
+ RECT 337.120000 1628.340000 338.220000 1628.820000 ;
+ RECT 337.120000 1622.900000 338.220000 1623.380000 ;
+ RECT 292.120000 1644.660000 293.220000 1645.140000 ;
+ RECT 292.120000 1639.220000 293.220000 1639.700000 ;
+ RECT 292.120000 1633.780000 293.220000 1634.260000 ;
+ RECT 292.120000 1628.340000 293.220000 1628.820000 ;
+ RECT 292.120000 1622.900000 293.220000 1623.380000 ;
+ RECT 337.120000 1617.460000 338.220000 1617.940000 ;
+ RECT 337.120000 1612.020000 338.220000 1612.500000 ;
+ RECT 337.120000 1606.580000 338.220000 1607.060000 ;
+ RECT 337.120000 1601.140000 338.220000 1601.620000 ;
+ RECT 292.120000 1612.020000 293.220000 1612.500000 ;
+ RECT 292.120000 1606.580000 293.220000 1607.060000 ;
+ RECT 292.120000 1601.140000 293.220000 1601.620000 ;
+ RECT 292.120000 1617.460000 293.220000 1617.940000 ;
+ RECT 247.120000 1644.660000 248.220000 1645.140000 ;
+ RECT 242.990000 1644.660000 243.990000 1645.140000 ;
+ RECT 247.120000 1639.220000 248.220000 1639.700000 ;
+ RECT 242.990000 1639.220000 243.990000 1639.700000 ;
+ RECT 247.120000 1633.780000 248.220000 1634.260000 ;
+ RECT 242.990000 1633.780000 243.990000 1634.260000 ;
+ RECT 247.120000 1622.900000 248.220000 1623.380000 ;
+ RECT 242.990000 1622.900000 243.990000 1623.380000 ;
+ RECT 242.990000 1628.340000 243.990000 1628.820000 ;
+ RECT 247.120000 1628.340000 248.220000 1628.820000 ;
+ RECT 247.120000 1617.460000 248.220000 1617.940000 ;
+ RECT 242.990000 1617.460000 243.990000 1617.940000 ;
+ RECT 247.120000 1612.020000 248.220000 1612.500000 ;
+ RECT 242.990000 1612.020000 243.990000 1612.500000 ;
+ RECT 247.120000 1606.580000 248.220000 1607.060000 ;
+ RECT 242.990000 1606.580000 243.990000 1607.060000 ;
+ RECT 247.120000 1601.140000 248.220000 1601.620000 ;
+ RECT 242.990000 1601.140000 243.990000 1601.620000 ;
+ RECT 337.120000 1595.700000 338.220000 1596.180000 ;
+ RECT 337.120000 1590.260000 338.220000 1590.740000 ;
+ RECT 337.120000 1584.820000 338.220000 1585.300000 ;
+ RECT 337.120000 1579.380000 338.220000 1579.860000 ;
+ RECT 337.120000 1573.940000 338.220000 1574.420000 ;
+ RECT 292.120000 1595.700000 293.220000 1596.180000 ;
+ RECT 292.120000 1590.260000 293.220000 1590.740000 ;
+ RECT 292.120000 1584.820000 293.220000 1585.300000 ;
+ RECT 292.120000 1579.380000 293.220000 1579.860000 ;
+ RECT 292.120000 1573.940000 293.220000 1574.420000 ;
+ RECT 337.120000 1552.180000 338.220000 1552.660000 ;
+ RECT 337.120000 1557.620000 338.220000 1558.100000 ;
+ RECT 337.120000 1563.060000 338.220000 1563.540000 ;
+ RECT 337.120000 1568.500000 338.220000 1568.980000 ;
+ RECT 292.120000 1552.180000 293.220000 1552.660000 ;
+ RECT 292.120000 1557.620000 293.220000 1558.100000 ;
+ RECT 292.120000 1563.060000 293.220000 1563.540000 ;
+ RECT 292.120000 1568.500000 293.220000 1568.980000 ;
+ RECT 247.120000 1595.700000 248.220000 1596.180000 ;
+ RECT 242.990000 1595.700000 243.990000 1596.180000 ;
+ RECT 247.120000 1590.260000 248.220000 1590.740000 ;
+ RECT 242.990000 1590.260000 243.990000 1590.740000 ;
+ RECT 247.120000 1579.380000 248.220000 1579.860000 ;
+ RECT 242.990000 1579.380000 243.990000 1579.860000 ;
+ RECT 247.120000 1573.940000 248.220000 1574.420000 ;
+ RECT 242.990000 1573.940000 243.990000 1574.420000 ;
+ RECT 247.120000 1584.820000 248.220000 1585.300000 ;
+ RECT 242.990000 1584.820000 243.990000 1585.300000 ;
+ RECT 247.120000 1568.500000 248.220000 1568.980000 ;
+ RECT 242.990000 1568.500000 243.990000 1568.980000 ;
+ RECT 247.120000 1563.060000 248.220000 1563.540000 ;
+ RECT 242.990000 1563.060000 243.990000 1563.540000 ;
+ RECT 247.120000 1557.620000 248.220000 1558.100000 ;
+ RECT 247.120000 1552.180000 248.220000 1552.660000 ;
+ RECT 242.990000 1557.620000 243.990000 1558.100000 ;
+ RECT 242.990000 1552.180000 243.990000 1552.660000 ;
+ RECT 240.160000 1742.540000 440.260000 1743.540000 ;
+ RECT 240.160000 1550.170000 440.260000 1551.170000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 1547.320000 243.990000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 242.990000 1746.580000 243.990000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 1547.320000 437.430000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 436.430000 1746.580000 437.430000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1550.170000 241.160000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1550.170000 440.260000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 240.160000 1742.540000 241.160000 1743.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 439.260000 1742.540000 440.260000 1743.540000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 3349.660000 444.090000 3379.920000 ;
+ RECT 636.530000 3349.660000 637.530000 3379.920000 ;
+ RECT 447.220000 3352.510000 448.320000 3376.560000 ;
+ RECT 492.220000 3352.510000 493.320000 3376.560000 ;
+ RECT 537.220000 3352.510000 538.320000 3376.560000 ;
+ RECT 582.220000 3352.510000 583.320000 3376.560000 ;
+ RECT 627.220000 3352.510000 628.320000 3376.560000 ;
+ LAYER met3 ;
+ RECT 636.530000 3365.400000 637.530000 3365.880000 ;
+ RECT 636.530000 3370.840000 637.530000 3371.320000 ;
+ RECT 627.220000 3370.840000 628.320000 3371.320000 ;
+ RECT 627.220000 3365.400000 628.320000 3365.880000 ;
+ RECT 582.220000 3365.400000 583.320000 3365.880000 ;
+ RECT 582.220000 3370.840000 583.320000 3371.320000 ;
+ RECT 492.220000 3365.400000 493.320000 3365.880000 ;
+ RECT 537.220000 3365.400000 538.320000 3365.880000 ;
+ RECT 537.220000 3370.840000 538.320000 3371.320000 ;
+ RECT 492.220000 3370.840000 493.320000 3371.320000 ;
+ RECT 443.090000 3365.400000 444.090000 3365.880000 ;
+ RECT 447.220000 3365.400000 448.320000 3365.880000 ;
+ RECT 447.220000 3370.840000 448.320000 3371.320000 ;
+ RECT 443.090000 3370.840000 444.090000 3371.320000 ;
+ RECT 636.530000 3354.520000 637.530000 3355.000000 ;
+ RECT 636.530000 3359.960000 637.530000 3360.440000 ;
+ RECT 627.220000 3359.960000 628.320000 3360.440000 ;
+ RECT 627.220000 3354.520000 628.320000 3355.000000 ;
+ RECT 582.220000 3354.520000 583.320000 3355.000000 ;
+ RECT 582.220000 3359.960000 583.320000 3360.440000 ;
+ RECT 492.220000 3354.520000 493.320000 3355.000000 ;
+ RECT 537.220000 3354.520000 538.320000 3355.000000 ;
+ RECT 537.220000 3359.960000 538.320000 3360.440000 ;
+ RECT 492.220000 3359.960000 493.320000 3360.440000 ;
+ RECT 443.090000 3359.960000 444.090000 3360.440000 ;
+ RECT 447.220000 3359.960000 448.320000 3360.440000 ;
+ RECT 443.090000 3354.520000 444.090000 3355.000000 ;
+ RECT 447.220000 3354.520000 448.320000 3355.000000 ;
+ RECT 440.260000 3375.560000 640.360000 3376.560000 ;
+ RECT 440.260000 3352.510000 640.360000 3353.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 3349.660000 444.090000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 3378.920000 444.090000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 3349.660000 637.530000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 3378.920000 637.530000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 3352.510000 441.260000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 3352.510000 640.360000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 3375.560000 441.260000 3376.560000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 3375.560000 640.360000 3376.560000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 1349.910000 628.320000 1543.280000 ;
+ RECT 582.220000 1349.910000 583.320000 1543.280000 ;
+ RECT 636.530000 1347.060000 637.530000 1547.320000 ;
+ RECT 537.220000 1349.910000 538.320000 1543.280000 ;
+ RECT 492.220000 1349.910000 493.320000 1543.280000 ;
+ RECT 447.220000 1349.910000 448.320000 1543.280000 ;
+ RECT 443.090000 1347.060000 444.090000 1547.320000 ;
+ LAYER met3 ;
+ RECT 627.220000 1536.880000 628.320000 1537.360000 ;
+ RECT 636.530000 1536.880000 637.530000 1537.360000 ;
+ RECT 636.530000 1526.000000 637.530000 1526.480000 ;
+ RECT 636.530000 1531.440000 637.530000 1531.920000 ;
+ RECT 627.220000 1531.440000 628.320000 1531.920000 ;
+ RECT 627.220000 1526.000000 628.320000 1526.480000 ;
+ RECT 627.220000 1520.560000 628.320000 1521.040000 ;
+ RECT 627.220000 1515.120000 628.320000 1515.600000 ;
+ RECT 636.530000 1520.560000 637.530000 1521.040000 ;
+ RECT 636.530000 1515.120000 637.530000 1515.600000 ;
+ RECT 627.220000 1498.800000 628.320000 1499.280000 ;
+ RECT 627.220000 1504.240000 628.320000 1504.720000 ;
+ RECT 636.530000 1504.240000 637.530000 1504.720000 ;
+ RECT 636.530000 1498.800000 637.530000 1499.280000 ;
+ RECT 627.220000 1509.680000 628.320000 1510.160000 ;
+ RECT 636.530000 1509.680000 637.530000 1510.160000 ;
+ RECT 582.220000 1536.880000 583.320000 1537.360000 ;
+ RECT 582.220000 1531.440000 583.320000 1531.920000 ;
+ RECT 582.220000 1526.000000 583.320000 1526.480000 ;
+ RECT 582.220000 1520.560000 583.320000 1521.040000 ;
+ RECT 582.220000 1498.800000 583.320000 1499.280000 ;
+ RECT 582.220000 1504.240000 583.320000 1504.720000 ;
+ RECT 582.220000 1509.680000 583.320000 1510.160000 ;
+ RECT 582.220000 1515.120000 583.320000 1515.600000 ;
+ RECT 636.530000 1487.920000 637.530000 1488.400000 ;
+ RECT 636.530000 1493.360000 637.530000 1493.840000 ;
+ RECT 627.220000 1493.360000 628.320000 1493.840000 ;
+ RECT 627.220000 1487.920000 628.320000 1488.400000 ;
+ RECT 627.220000 1482.480000 628.320000 1482.960000 ;
+ RECT 627.220000 1477.040000 628.320000 1477.520000 ;
+ RECT 636.530000 1482.480000 637.530000 1482.960000 ;
+ RECT 636.530000 1477.040000 637.530000 1477.520000 ;
+ RECT 636.530000 1460.720000 637.530000 1461.200000 ;
+ RECT 636.530000 1466.160000 637.530000 1466.640000 ;
+ RECT 636.530000 1471.600000 637.530000 1472.080000 ;
+ RECT 627.220000 1466.160000 628.320000 1466.640000 ;
+ RECT 627.220000 1460.720000 628.320000 1461.200000 ;
+ RECT 627.220000 1471.600000 628.320000 1472.080000 ;
+ RECT 627.220000 1455.280000 628.320000 1455.760000 ;
+ RECT 627.220000 1449.840000 628.320000 1450.320000 ;
+ RECT 636.530000 1455.280000 637.530000 1455.760000 ;
+ RECT 636.530000 1449.840000 637.530000 1450.320000 ;
+ RECT 582.220000 1493.360000 583.320000 1493.840000 ;
+ RECT 582.220000 1487.920000 583.320000 1488.400000 ;
+ RECT 582.220000 1482.480000 583.320000 1482.960000 ;
+ RECT 582.220000 1477.040000 583.320000 1477.520000 ;
+ RECT 582.220000 1466.160000 583.320000 1466.640000 ;
+ RECT 582.220000 1460.720000 583.320000 1461.200000 ;
+ RECT 582.220000 1455.280000 583.320000 1455.760000 ;
+ RECT 582.220000 1449.840000 583.320000 1450.320000 ;
+ RECT 582.220000 1471.600000 583.320000 1472.080000 ;
+ RECT 537.220000 1536.880000 538.320000 1537.360000 ;
+ RECT 537.220000 1531.440000 538.320000 1531.920000 ;
+ RECT 537.220000 1526.000000 538.320000 1526.480000 ;
+ RECT 492.220000 1536.880000 493.320000 1537.360000 ;
+ RECT 492.220000 1531.440000 493.320000 1531.920000 ;
+ RECT 492.220000 1526.000000 493.320000 1526.480000 ;
+ RECT 537.220000 1509.680000 538.320000 1510.160000 ;
+ RECT 537.220000 1504.240000 538.320000 1504.720000 ;
+ RECT 537.220000 1498.800000 538.320000 1499.280000 ;
+ RECT 537.220000 1515.120000 538.320000 1515.600000 ;
+ RECT 537.220000 1520.560000 538.320000 1521.040000 ;
+ RECT 492.220000 1520.560000 493.320000 1521.040000 ;
+ RECT 492.220000 1509.680000 493.320000 1510.160000 ;
+ RECT 492.220000 1504.240000 493.320000 1504.720000 ;
+ RECT 492.220000 1498.800000 493.320000 1499.280000 ;
+ RECT 492.220000 1515.120000 493.320000 1515.600000 ;
+ RECT 447.220000 1536.880000 448.320000 1537.360000 ;
+ RECT 443.090000 1536.880000 444.090000 1537.360000 ;
+ RECT 443.090000 1531.440000 444.090000 1531.920000 ;
+ RECT 447.220000 1531.440000 448.320000 1531.920000 ;
+ RECT 447.220000 1526.000000 448.320000 1526.480000 ;
+ RECT 443.090000 1526.000000 444.090000 1526.480000 ;
+ RECT 447.220000 1520.560000 448.320000 1521.040000 ;
+ RECT 443.090000 1520.560000 444.090000 1521.040000 ;
+ RECT 447.220000 1515.120000 448.320000 1515.600000 ;
+ RECT 443.090000 1515.120000 444.090000 1515.600000 ;
+ RECT 447.220000 1504.240000 448.320000 1504.720000 ;
+ RECT 443.090000 1504.240000 444.090000 1504.720000 ;
+ RECT 447.220000 1498.800000 448.320000 1499.280000 ;
+ RECT 443.090000 1498.800000 444.090000 1499.280000 ;
+ RECT 447.220000 1509.680000 448.320000 1510.160000 ;
+ RECT 443.090000 1509.680000 444.090000 1510.160000 ;
+ RECT 537.220000 1493.360000 538.320000 1493.840000 ;
+ RECT 537.220000 1487.920000 538.320000 1488.400000 ;
+ RECT 537.220000 1482.480000 538.320000 1482.960000 ;
+ RECT 537.220000 1477.040000 538.320000 1477.520000 ;
+ RECT 492.220000 1493.360000 493.320000 1493.840000 ;
+ RECT 492.220000 1487.920000 493.320000 1488.400000 ;
+ RECT 492.220000 1482.480000 493.320000 1482.960000 ;
+ RECT 492.220000 1477.040000 493.320000 1477.520000 ;
+ RECT 537.220000 1466.160000 538.320000 1466.640000 ;
+ RECT 537.220000 1449.840000 538.320000 1450.320000 ;
+ RECT 537.220000 1455.280000 538.320000 1455.760000 ;
+ RECT 537.220000 1460.720000 538.320000 1461.200000 ;
+ RECT 537.220000 1471.600000 538.320000 1472.080000 ;
+ RECT 492.220000 1449.840000 493.320000 1450.320000 ;
+ RECT 492.220000 1455.280000 493.320000 1455.760000 ;
+ RECT 492.220000 1460.720000 493.320000 1461.200000 ;
+ RECT 492.220000 1466.160000 493.320000 1466.640000 ;
+ RECT 492.220000 1471.600000 493.320000 1472.080000 ;
+ RECT 447.220000 1493.360000 448.320000 1493.840000 ;
+ RECT 443.090000 1493.360000 444.090000 1493.840000 ;
+ RECT 447.220000 1487.920000 448.320000 1488.400000 ;
+ RECT 443.090000 1487.920000 444.090000 1488.400000 ;
+ RECT 447.220000 1482.480000 448.320000 1482.960000 ;
+ RECT 443.090000 1482.480000 444.090000 1482.960000 ;
+ RECT 447.220000 1477.040000 448.320000 1477.520000 ;
+ RECT 443.090000 1477.040000 444.090000 1477.520000 ;
+ RECT 447.220000 1471.600000 448.320000 1472.080000 ;
+ RECT 447.220000 1466.160000 448.320000 1466.640000 ;
+ RECT 443.090000 1471.600000 444.090000 1472.080000 ;
+ RECT 443.090000 1466.160000 444.090000 1466.640000 ;
+ RECT 447.220000 1460.720000 448.320000 1461.200000 ;
+ RECT 443.090000 1460.720000 444.090000 1461.200000 ;
+ RECT 447.220000 1455.280000 448.320000 1455.760000 ;
+ RECT 443.090000 1455.280000 444.090000 1455.760000 ;
+ RECT 447.220000 1449.840000 448.320000 1450.320000 ;
+ RECT 443.090000 1449.840000 444.090000 1450.320000 ;
+ RECT 627.220000 1444.400000 628.320000 1444.880000 ;
+ RECT 627.220000 1438.960000 628.320000 1439.440000 ;
+ RECT 636.530000 1444.400000 637.530000 1444.880000 ;
+ RECT 636.530000 1438.960000 637.530000 1439.440000 ;
+ RECT 636.530000 1422.640000 637.530000 1423.120000 ;
+ RECT 636.530000 1428.080000 637.530000 1428.560000 ;
+ RECT 636.530000 1433.520000 637.530000 1434.000000 ;
+ RECT 627.220000 1433.520000 628.320000 1434.000000 ;
+ RECT 627.220000 1428.080000 628.320000 1428.560000 ;
+ RECT 627.220000 1422.640000 628.320000 1423.120000 ;
+ RECT 627.220000 1411.760000 628.320000 1412.240000 ;
+ RECT 627.220000 1417.200000 628.320000 1417.680000 ;
+ RECT 636.530000 1417.200000 637.530000 1417.680000 ;
+ RECT 636.530000 1411.760000 637.530000 1412.240000 ;
+ RECT 636.530000 1400.880000 637.530000 1401.360000 ;
+ RECT 636.530000 1406.320000 637.530000 1406.800000 ;
+ RECT 627.220000 1400.880000 628.320000 1401.360000 ;
+ RECT 627.220000 1406.320000 628.320000 1406.800000 ;
+ RECT 582.220000 1444.400000 583.320000 1444.880000 ;
+ RECT 582.220000 1438.960000 583.320000 1439.440000 ;
+ RECT 582.220000 1433.520000 583.320000 1434.000000 ;
+ RECT 582.220000 1428.080000 583.320000 1428.560000 ;
+ RECT 582.220000 1422.640000 583.320000 1423.120000 ;
+ RECT 582.220000 1400.880000 583.320000 1401.360000 ;
+ RECT 582.220000 1406.320000 583.320000 1406.800000 ;
+ RECT 582.220000 1411.760000 583.320000 1412.240000 ;
+ RECT 582.220000 1417.200000 583.320000 1417.680000 ;
+ RECT 627.220000 1395.440000 628.320000 1395.920000 ;
+ RECT 627.220000 1390.000000 628.320000 1390.480000 ;
+ RECT 636.530000 1395.440000 637.530000 1395.920000 ;
+ RECT 636.530000 1390.000000 637.530000 1390.480000 ;
+ RECT 627.220000 1379.120000 628.320000 1379.600000 ;
+ RECT 627.220000 1373.680000 628.320000 1374.160000 ;
+ RECT 636.530000 1379.120000 637.530000 1379.600000 ;
+ RECT 636.530000 1373.680000 637.530000 1374.160000 ;
+ RECT 627.220000 1384.560000 628.320000 1385.040000 ;
+ RECT 636.530000 1384.560000 637.530000 1385.040000 ;
+ RECT 636.530000 1362.800000 637.530000 1363.280000 ;
+ RECT 636.530000 1368.240000 637.530000 1368.720000 ;
+ RECT 627.220000 1368.240000 628.320000 1368.720000 ;
+ RECT 627.220000 1362.800000 628.320000 1363.280000 ;
+ RECT 627.220000 1357.360000 628.320000 1357.840000 ;
+ RECT 627.220000 1351.920000 628.320000 1352.400000 ;
+ RECT 636.530000 1357.360000 637.530000 1357.840000 ;
+ RECT 636.530000 1351.920000 637.530000 1352.400000 ;
+ RECT 582.220000 1395.440000 583.320000 1395.920000 ;
+ RECT 582.220000 1390.000000 583.320000 1390.480000 ;
+ RECT 582.220000 1384.560000 583.320000 1385.040000 ;
+ RECT 582.220000 1379.120000 583.320000 1379.600000 ;
+ RECT 582.220000 1373.680000 583.320000 1374.160000 ;
+ RECT 582.220000 1368.240000 583.320000 1368.720000 ;
+ RECT 582.220000 1362.800000 583.320000 1363.280000 ;
+ RECT 582.220000 1357.360000 583.320000 1357.840000 ;
+ RECT 582.220000 1351.920000 583.320000 1352.400000 ;
+ RECT 537.220000 1444.400000 538.320000 1444.880000 ;
+ RECT 537.220000 1438.960000 538.320000 1439.440000 ;
+ RECT 537.220000 1433.520000 538.320000 1434.000000 ;
+ RECT 537.220000 1428.080000 538.320000 1428.560000 ;
+ RECT 537.220000 1422.640000 538.320000 1423.120000 ;
+ RECT 492.220000 1444.400000 493.320000 1444.880000 ;
+ RECT 492.220000 1438.960000 493.320000 1439.440000 ;
+ RECT 492.220000 1433.520000 493.320000 1434.000000 ;
+ RECT 492.220000 1428.080000 493.320000 1428.560000 ;
+ RECT 492.220000 1422.640000 493.320000 1423.120000 ;
+ RECT 537.220000 1417.200000 538.320000 1417.680000 ;
+ RECT 537.220000 1411.760000 538.320000 1412.240000 ;
+ RECT 537.220000 1406.320000 538.320000 1406.800000 ;
+ RECT 537.220000 1400.880000 538.320000 1401.360000 ;
+ RECT 492.220000 1411.760000 493.320000 1412.240000 ;
+ RECT 492.220000 1406.320000 493.320000 1406.800000 ;
+ RECT 492.220000 1400.880000 493.320000 1401.360000 ;
+ RECT 492.220000 1417.200000 493.320000 1417.680000 ;
+ RECT 447.220000 1444.400000 448.320000 1444.880000 ;
+ RECT 443.090000 1444.400000 444.090000 1444.880000 ;
+ RECT 447.220000 1438.960000 448.320000 1439.440000 ;
+ RECT 443.090000 1438.960000 444.090000 1439.440000 ;
+ RECT 447.220000 1433.520000 448.320000 1434.000000 ;
+ RECT 443.090000 1433.520000 444.090000 1434.000000 ;
+ RECT 447.220000 1422.640000 448.320000 1423.120000 ;
+ RECT 443.090000 1422.640000 444.090000 1423.120000 ;
+ RECT 443.090000 1428.080000 444.090000 1428.560000 ;
+ RECT 447.220000 1428.080000 448.320000 1428.560000 ;
+ RECT 447.220000 1417.200000 448.320000 1417.680000 ;
+ RECT 443.090000 1417.200000 444.090000 1417.680000 ;
+ RECT 447.220000 1411.760000 448.320000 1412.240000 ;
+ RECT 443.090000 1411.760000 444.090000 1412.240000 ;
+ RECT 447.220000 1406.320000 448.320000 1406.800000 ;
+ RECT 443.090000 1406.320000 444.090000 1406.800000 ;
+ RECT 447.220000 1400.880000 448.320000 1401.360000 ;
+ RECT 443.090000 1400.880000 444.090000 1401.360000 ;
+ RECT 537.220000 1395.440000 538.320000 1395.920000 ;
+ RECT 537.220000 1390.000000 538.320000 1390.480000 ;
+ RECT 537.220000 1384.560000 538.320000 1385.040000 ;
+ RECT 537.220000 1379.120000 538.320000 1379.600000 ;
+ RECT 537.220000 1373.680000 538.320000 1374.160000 ;
+ RECT 492.220000 1395.440000 493.320000 1395.920000 ;
+ RECT 492.220000 1390.000000 493.320000 1390.480000 ;
+ RECT 492.220000 1384.560000 493.320000 1385.040000 ;
+ RECT 492.220000 1379.120000 493.320000 1379.600000 ;
+ RECT 492.220000 1373.680000 493.320000 1374.160000 ;
+ RECT 537.220000 1351.920000 538.320000 1352.400000 ;
+ RECT 537.220000 1357.360000 538.320000 1357.840000 ;
+ RECT 537.220000 1362.800000 538.320000 1363.280000 ;
+ RECT 537.220000 1368.240000 538.320000 1368.720000 ;
+ RECT 492.220000 1351.920000 493.320000 1352.400000 ;
+ RECT 492.220000 1357.360000 493.320000 1357.840000 ;
+ RECT 492.220000 1362.800000 493.320000 1363.280000 ;
+ RECT 492.220000 1368.240000 493.320000 1368.720000 ;
+ RECT 447.220000 1395.440000 448.320000 1395.920000 ;
+ RECT 443.090000 1395.440000 444.090000 1395.920000 ;
+ RECT 447.220000 1390.000000 448.320000 1390.480000 ;
+ RECT 443.090000 1390.000000 444.090000 1390.480000 ;
+ RECT 447.220000 1379.120000 448.320000 1379.600000 ;
+ RECT 443.090000 1379.120000 444.090000 1379.600000 ;
+ RECT 447.220000 1373.680000 448.320000 1374.160000 ;
+ RECT 443.090000 1373.680000 444.090000 1374.160000 ;
+ RECT 447.220000 1384.560000 448.320000 1385.040000 ;
+ RECT 443.090000 1384.560000 444.090000 1385.040000 ;
+ RECT 447.220000 1368.240000 448.320000 1368.720000 ;
+ RECT 443.090000 1368.240000 444.090000 1368.720000 ;
+ RECT 447.220000 1362.800000 448.320000 1363.280000 ;
+ RECT 443.090000 1362.800000 444.090000 1363.280000 ;
+ RECT 447.220000 1357.360000 448.320000 1357.840000 ;
+ RECT 447.220000 1351.920000 448.320000 1352.400000 ;
+ RECT 443.090000 1357.360000 444.090000 1357.840000 ;
+ RECT 443.090000 1351.920000 444.090000 1352.400000 ;
+ RECT 440.260000 1542.280000 640.360000 1543.280000 ;
+ RECT 440.260000 1349.910000 640.360000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 1347.060000 444.090000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 1546.320000 444.090000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 1347.060000 637.530000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 1546.320000 637.530000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1349.910000 441.260000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1349.910000 640.360000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1542.280000 441.260000 1543.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1542.280000 640.360000 1543.280000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 1149.650000 628.320000 1343.020000 ;
+ RECT 582.220000 1149.650000 583.320000 1343.020000 ;
+ RECT 636.530000 1146.800000 637.530000 1347.060000 ;
+ RECT 537.220000 1149.650000 538.320000 1343.020000 ;
+ RECT 492.220000 1149.650000 493.320000 1343.020000 ;
+ RECT 447.220000 1149.650000 448.320000 1343.020000 ;
+ RECT 443.090000 1146.800000 444.090000 1347.060000 ;
+ LAYER met3 ;
+ RECT 627.220000 1336.620000 628.320000 1337.100000 ;
+ RECT 636.530000 1336.620000 637.530000 1337.100000 ;
+ RECT 636.530000 1325.740000 637.530000 1326.220000 ;
+ RECT 636.530000 1331.180000 637.530000 1331.660000 ;
+ RECT 627.220000 1331.180000 628.320000 1331.660000 ;
+ RECT 627.220000 1325.740000 628.320000 1326.220000 ;
+ RECT 627.220000 1320.300000 628.320000 1320.780000 ;
+ RECT 627.220000 1314.860000 628.320000 1315.340000 ;
+ RECT 636.530000 1320.300000 637.530000 1320.780000 ;
+ RECT 636.530000 1314.860000 637.530000 1315.340000 ;
+ RECT 627.220000 1298.540000 628.320000 1299.020000 ;
+ RECT 627.220000 1303.980000 628.320000 1304.460000 ;
+ RECT 636.530000 1303.980000 637.530000 1304.460000 ;
+ RECT 636.530000 1298.540000 637.530000 1299.020000 ;
+ RECT 627.220000 1309.420000 628.320000 1309.900000 ;
+ RECT 636.530000 1309.420000 637.530000 1309.900000 ;
+ RECT 582.220000 1336.620000 583.320000 1337.100000 ;
+ RECT 582.220000 1331.180000 583.320000 1331.660000 ;
+ RECT 582.220000 1325.740000 583.320000 1326.220000 ;
+ RECT 582.220000 1320.300000 583.320000 1320.780000 ;
+ RECT 582.220000 1298.540000 583.320000 1299.020000 ;
+ RECT 582.220000 1303.980000 583.320000 1304.460000 ;
+ RECT 582.220000 1309.420000 583.320000 1309.900000 ;
+ RECT 582.220000 1314.860000 583.320000 1315.340000 ;
+ RECT 636.530000 1287.660000 637.530000 1288.140000 ;
+ RECT 636.530000 1293.100000 637.530000 1293.580000 ;
+ RECT 627.220000 1293.100000 628.320000 1293.580000 ;
+ RECT 627.220000 1287.660000 628.320000 1288.140000 ;
+ RECT 627.220000 1282.220000 628.320000 1282.700000 ;
+ RECT 627.220000 1276.780000 628.320000 1277.260000 ;
+ RECT 636.530000 1282.220000 637.530000 1282.700000 ;
+ RECT 636.530000 1276.780000 637.530000 1277.260000 ;
+ RECT 636.530000 1260.460000 637.530000 1260.940000 ;
+ RECT 636.530000 1265.900000 637.530000 1266.380000 ;
+ RECT 636.530000 1271.340000 637.530000 1271.820000 ;
+ RECT 627.220000 1265.900000 628.320000 1266.380000 ;
+ RECT 627.220000 1260.460000 628.320000 1260.940000 ;
+ RECT 627.220000 1271.340000 628.320000 1271.820000 ;
+ RECT 627.220000 1255.020000 628.320000 1255.500000 ;
+ RECT 627.220000 1249.580000 628.320000 1250.060000 ;
+ RECT 636.530000 1255.020000 637.530000 1255.500000 ;
+ RECT 636.530000 1249.580000 637.530000 1250.060000 ;
+ RECT 582.220000 1293.100000 583.320000 1293.580000 ;
+ RECT 582.220000 1287.660000 583.320000 1288.140000 ;
+ RECT 582.220000 1282.220000 583.320000 1282.700000 ;
+ RECT 582.220000 1276.780000 583.320000 1277.260000 ;
+ RECT 582.220000 1265.900000 583.320000 1266.380000 ;
+ RECT 582.220000 1260.460000 583.320000 1260.940000 ;
+ RECT 582.220000 1255.020000 583.320000 1255.500000 ;
+ RECT 582.220000 1249.580000 583.320000 1250.060000 ;
+ RECT 582.220000 1271.340000 583.320000 1271.820000 ;
+ RECT 537.220000 1336.620000 538.320000 1337.100000 ;
+ RECT 537.220000 1331.180000 538.320000 1331.660000 ;
+ RECT 537.220000 1325.740000 538.320000 1326.220000 ;
+ RECT 492.220000 1336.620000 493.320000 1337.100000 ;
+ RECT 492.220000 1331.180000 493.320000 1331.660000 ;
+ RECT 492.220000 1325.740000 493.320000 1326.220000 ;
+ RECT 537.220000 1309.420000 538.320000 1309.900000 ;
+ RECT 537.220000 1303.980000 538.320000 1304.460000 ;
+ RECT 537.220000 1298.540000 538.320000 1299.020000 ;
+ RECT 537.220000 1314.860000 538.320000 1315.340000 ;
+ RECT 537.220000 1320.300000 538.320000 1320.780000 ;
+ RECT 492.220000 1320.300000 493.320000 1320.780000 ;
+ RECT 492.220000 1309.420000 493.320000 1309.900000 ;
+ RECT 492.220000 1303.980000 493.320000 1304.460000 ;
+ RECT 492.220000 1298.540000 493.320000 1299.020000 ;
+ RECT 492.220000 1314.860000 493.320000 1315.340000 ;
+ RECT 447.220000 1336.620000 448.320000 1337.100000 ;
+ RECT 443.090000 1336.620000 444.090000 1337.100000 ;
+ RECT 443.090000 1331.180000 444.090000 1331.660000 ;
+ RECT 447.220000 1331.180000 448.320000 1331.660000 ;
+ RECT 447.220000 1325.740000 448.320000 1326.220000 ;
+ RECT 443.090000 1325.740000 444.090000 1326.220000 ;
+ RECT 447.220000 1320.300000 448.320000 1320.780000 ;
+ RECT 443.090000 1320.300000 444.090000 1320.780000 ;
+ RECT 447.220000 1314.860000 448.320000 1315.340000 ;
+ RECT 443.090000 1314.860000 444.090000 1315.340000 ;
+ RECT 447.220000 1303.980000 448.320000 1304.460000 ;
+ RECT 443.090000 1303.980000 444.090000 1304.460000 ;
+ RECT 447.220000 1298.540000 448.320000 1299.020000 ;
+ RECT 443.090000 1298.540000 444.090000 1299.020000 ;
+ RECT 447.220000 1309.420000 448.320000 1309.900000 ;
+ RECT 443.090000 1309.420000 444.090000 1309.900000 ;
+ RECT 537.220000 1293.100000 538.320000 1293.580000 ;
+ RECT 537.220000 1287.660000 538.320000 1288.140000 ;
+ RECT 537.220000 1282.220000 538.320000 1282.700000 ;
+ RECT 537.220000 1276.780000 538.320000 1277.260000 ;
+ RECT 492.220000 1293.100000 493.320000 1293.580000 ;
+ RECT 492.220000 1287.660000 493.320000 1288.140000 ;
+ RECT 492.220000 1282.220000 493.320000 1282.700000 ;
+ RECT 492.220000 1276.780000 493.320000 1277.260000 ;
+ RECT 537.220000 1265.900000 538.320000 1266.380000 ;
+ RECT 537.220000 1249.580000 538.320000 1250.060000 ;
+ RECT 537.220000 1255.020000 538.320000 1255.500000 ;
+ RECT 537.220000 1260.460000 538.320000 1260.940000 ;
+ RECT 537.220000 1271.340000 538.320000 1271.820000 ;
+ RECT 492.220000 1249.580000 493.320000 1250.060000 ;
+ RECT 492.220000 1255.020000 493.320000 1255.500000 ;
+ RECT 492.220000 1260.460000 493.320000 1260.940000 ;
+ RECT 492.220000 1265.900000 493.320000 1266.380000 ;
+ RECT 492.220000 1271.340000 493.320000 1271.820000 ;
+ RECT 447.220000 1293.100000 448.320000 1293.580000 ;
+ RECT 443.090000 1293.100000 444.090000 1293.580000 ;
+ RECT 447.220000 1287.660000 448.320000 1288.140000 ;
+ RECT 443.090000 1287.660000 444.090000 1288.140000 ;
+ RECT 447.220000 1282.220000 448.320000 1282.700000 ;
+ RECT 443.090000 1282.220000 444.090000 1282.700000 ;
+ RECT 447.220000 1276.780000 448.320000 1277.260000 ;
+ RECT 443.090000 1276.780000 444.090000 1277.260000 ;
+ RECT 447.220000 1271.340000 448.320000 1271.820000 ;
+ RECT 447.220000 1265.900000 448.320000 1266.380000 ;
+ RECT 443.090000 1271.340000 444.090000 1271.820000 ;
+ RECT 443.090000 1265.900000 444.090000 1266.380000 ;
+ RECT 447.220000 1260.460000 448.320000 1260.940000 ;
+ RECT 443.090000 1260.460000 444.090000 1260.940000 ;
+ RECT 447.220000 1255.020000 448.320000 1255.500000 ;
+ RECT 443.090000 1255.020000 444.090000 1255.500000 ;
+ RECT 447.220000 1249.580000 448.320000 1250.060000 ;
+ RECT 443.090000 1249.580000 444.090000 1250.060000 ;
+ RECT 627.220000 1244.140000 628.320000 1244.620000 ;
+ RECT 627.220000 1238.700000 628.320000 1239.180000 ;
+ RECT 636.530000 1244.140000 637.530000 1244.620000 ;
+ RECT 636.530000 1238.700000 637.530000 1239.180000 ;
+ RECT 636.530000 1222.380000 637.530000 1222.860000 ;
+ RECT 636.530000 1227.820000 637.530000 1228.300000 ;
+ RECT 636.530000 1233.260000 637.530000 1233.740000 ;
+ RECT 627.220000 1233.260000 628.320000 1233.740000 ;
+ RECT 627.220000 1227.820000 628.320000 1228.300000 ;
+ RECT 627.220000 1222.380000 628.320000 1222.860000 ;
+ RECT 627.220000 1211.500000 628.320000 1211.980000 ;
+ RECT 627.220000 1216.940000 628.320000 1217.420000 ;
+ RECT 636.530000 1216.940000 637.530000 1217.420000 ;
+ RECT 636.530000 1211.500000 637.530000 1211.980000 ;
+ RECT 636.530000 1200.620000 637.530000 1201.100000 ;
+ RECT 636.530000 1206.060000 637.530000 1206.540000 ;
+ RECT 627.220000 1200.620000 628.320000 1201.100000 ;
+ RECT 627.220000 1206.060000 628.320000 1206.540000 ;
+ RECT 582.220000 1244.140000 583.320000 1244.620000 ;
+ RECT 582.220000 1238.700000 583.320000 1239.180000 ;
+ RECT 582.220000 1233.260000 583.320000 1233.740000 ;
+ RECT 582.220000 1227.820000 583.320000 1228.300000 ;
+ RECT 582.220000 1222.380000 583.320000 1222.860000 ;
+ RECT 582.220000 1200.620000 583.320000 1201.100000 ;
+ RECT 582.220000 1206.060000 583.320000 1206.540000 ;
+ RECT 582.220000 1211.500000 583.320000 1211.980000 ;
+ RECT 582.220000 1216.940000 583.320000 1217.420000 ;
+ RECT 627.220000 1195.180000 628.320000 1195.660000 ;
+ RECT 627.220000 1189.740000 628.320000 1190.220000 ;
+ RECT 636.530000 1195.180000 637.530000 1195.660000 ;
+ RECT 636.530000 1189.740000 637.530000 1190.220000 ;
+ RECT 627.220000 1178.860000 628.320000 1179.340000 ;
+ RECT 627.220000 1173.420000 628.320000 1173.900000 ;
+ RECT 636.530000 1178.860000 637.530000 1179.340000 ;
+ RECT 636.530000 1173.420000 637.530000 1173.900000 ;
+ RECT 627.220000 1184.300000 628.320000 1184.780000 ;
+ RECT 636.530000 1184.300000 637.530000 1184.780000 ;
+ RECT 636.530000 1162.540000 637.530000 1163.020000 ;
+ RECT 636.530000 1167.980000 637.530000 1168.460000 ;
+ RECT 627.220000 1167.980000 628.320000 1168.460000 ;
+ RECT 627.220000 1162.540000 628.320000 1163.020000 ;
+ RECT 627.220000 1157.100000 628.320000 1157.580000 ;
+ RECT 627.220000 1151.660000 628.320000 1152.140000 ;
+ RECT 636.530000 1157.100000 637.530000 1157.580000 ;
+ RECT 636.530000 1151.660000 637.530000 1152.140000 ;
+ RECT 582.220000 1195.180000 583.320000 1195.660000 ;
+ RECT 582.220000 1189.740000 583.320000 1190.220000 ;
+ RECT 582.220000 1184.300000 583.320000 1184.780000 ;
+ RECT 582.220000 1178.860000 583.320000 1179.340000 ;
+ RECT 582.220000 1173.420000 583.320000 1173.900000 ;
+ RECT 582.220000 1167.980000 583.320000 1168.460000 ;
+ RECT 582.220000 1162.540000 583.320000 1163.020000 ;
+ RECT 582.220000 1157.100000 583.320000 1157.580000 ;
+ RECT 582.220000 1151.660000 583.320000 1152.140000 ;
+ RECT 537.220000 1244.140000 538.320000 1244.620000 ;
+ RECT 537.220000 1238.700000 538.320000 1239.180000 ;
+ RECT 537.220000 1233.260000 538.320000 1233.740000 ;
+ RECT 537.220000 1227.820000 538.320000 1228.300000 ;
+ RECT 537.220000 1222.380000 538.320000 1222.860000 ;
+ RECT 492.220000 1244.140000 493.320000 1244.620000 ;
+ RECT 492.220000 1238.700000 493.320000 1239.180000 ;
+ RECT 492.220000 1233.260000 493.320000 1233.740000 ;
+ RECT 492.220000 1227.820000 493.320000 1228.300000 ;
+ RECT 492.220000 1222.380000 493.320000 1222.860000 ;
+ RECT 537.220000 1216.940000 538.320000 1217.420000 ;
+ RECT 537.220000 1211.500000 538.320000 1211.980000 ;
+ RECT 537.220000 1206.060000 538.320000 1206.540000 ;
+ RECT 537.220000 1200.620000 538.320000 1201.100000 ;
+ RECT 492.220000 1211.500000 493.320000 1211.980000 ;
+ RECT 492.220000 1206.060000 493.320000 1206.540000 ;
+ RECT 492.220000 1200.620000 493.320000 1201.100000 ;
+ RECT 492.220000 1216.940000 493.320000 1217.420000 ;
+ RECT 447.220000 1244.140000 448.320000 1244.620000 ;
+ RECT 443.090000 1244.140000 444.090000 1244.620000 ;
+ RECT 447.220000 1238.700000 448.320000 1239.180000 ;
+ RECT 443.090000 1238.700000 444.090000 1239.180000 ;
+ RECT 447.220000 1233.260000 448.320000 1233.740000 ;
+ RECT 443.090000 1233.260000 444.090000 1233.740000 ;
+ RECT 447.220000 1222.380000 448.320000 1222.860000 ;
+ RECT 443.090000 1222.380000 444.090000 1222.860000 ;
+ RECT 443.090000 1227.820000 444.090000 1228.300000 ;
+ RECT 447.220000 1227.820000 448.320000 1228.300000 ;
+ RECT 447.220000 1216.940000 448.320000 1217.420000 ;
+ RECT 443.090000 1216.940000 444.090000 1217.420000 ;
+ RECT 447.220000 1211.500000 448.320000 1211.980000 ;
+ RECT 443.090000 1211.500000 444.090000 1211.980000 ;
+ RECT 447.220000 1206.060000 448.320000 1206.540000 ;
+ RECT 443.090000 1206.060000 444.090000 1206.540000 ;
+ RECT 447.220000 1200.620000 448.320000 1201.100000 ;
+ RECT 443.090000 1200.620000 444.090000 1201.100000 ;
+ RECT 537.220000 1195.180000 538.320000 1195.660000 ;
+ RECT 537.220000 1189.740000 538.320000 1190.220000 ;
+ RECT 537.220000 1184.300000 538.320000 1184.780000 ;
+ RECT 537.220000 1178.860000 538.320000 1179.340000 ;
+ RECT 537.220000 1173.420000 538.320000 1173.900000 ;
+ RECT 492.220000 1195.180000 493.320000 1195.660000 ;
+ RECT 492.220000 1189.740000 493.320000 1190.220000 ;
+ RECT 492.220000 1184.300000 493.320000 1184.780000 ;
+ RECT 492.220000 1178.860000 493.320000 1179.340000 ;
+ RECT 492.220000 1173.420000 493.320000 1173.900000 ;
+ RECT 537.220000 1151.660000 538.320000 1152.140000 ;
+ RECT 537.220000 1157.100000 538.320000 1157.580000 ;
+ RECT 537.220000 1162.540000 538.320000 1163.020000 ;
+ RECT 537.220000 1167.980000 538.320000 1168.460000 ;
+ RECT 492.220000 1151.660000 493.320000 1152.140000 ;
+ RECT 492.220000 1157.100000 493.320000 1157.580000 ;
+ RECT 492.220000 1162.540000 493.320000 1163.020000 ;
+ RECT 492.220000 1167.980000 493.320000 1168.460000 ;
+ RECT 447.220000 1195.180000 448.320000 1195.660000 ;
+ RECT 443.090000 1195.180000 444.090000 1195.660000 ;
+ RECT 447.220000 1189.740000 448.320000 1190.220000 ;
+ RECT 443.090000 1189.740000 444.090000 1190.220000 ;
+ RECT 447.220000 1178.860000 448.320000 1179.340000 ;
+ RECT 443.090000 1178.860000 444.090000 1179.340000 ;
+ RECT 447.220000 1173.420000 448.320000 1173.900000 ;
+ RECT 443.090000 1173.420000 444.090000 1173.900000 ;
+ RECT 447.220000 1184.300000 448.320000 1184.780000 ;
+ RECT 443.090000 1184.300000 444.090000 1184.780000 ;
+ RECT 447.220000 1167.980000 448.320000 1168.460000 ;
+ RECT 443.090000 1167.980000 444.090000 1168.460000 ;
+ RECT 447.220000 1162.540000 448.320000 1163.020000 ;
+ RECT 443.090000 1162.540000 444.090000 1163.020000 ;
+ RECT 447.220000 1157.100000 448.320000 1157.580000 ;
+ RECT 447.220000 1151.660000 448.320000 1152.140000 ;
+ RECT 443.090000 1157.100000 444.090000 1157.580000 ;
+ RECT 443.090000 1151.660000 444.090000 1152.140000 ;
+ RECT 440.260000 1342.020000 640.360000 1343.020000 ;
+ RECT 440.260000 1149.650000 640.360000 1150.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 1146.800000 444.090000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 1346.060000 444.090000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 1146.800000 637.530000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 1346.060000 637.530000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1149.650000 441.260000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1149.650000 640.360000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1342.020000 441.260000 1343.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1342.020000 640.360000 1343.020000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 949.390000 628.320000 1142.760000 ;
+ RECT 582.220000 949.390000 583.320000 1142.760000 ;
+ RECT 636.530000 946.540000 637.530000 1146.800000 ;
+ RECT 537.220000 949.390000 538.320000 1142.760000 ;
+ RECT 492.220000 949.390000 493.320000 1142.760000 ;
+ RECT 447.220000 949.390000 448.320000 1142.760000 ;
+ RECT 443.090000 946.540000 444.090000 1146.800000 ;
+ LAYER met3 ;
+ RECT 627.220000 1136.360000 628.320000 1136.840000 ;
+ RECT 636.530000 1136.360000 637.530000 1136.840000 ;
+ RECT 636.530000 1125.480000 637.530000 1125.960000 ;
+ RECT 636.530000 1130.920000 637.530000 1131.400000 ;
+ RECT 627.220000 1130.920000 628.320000 1131.400000 ;
+ RECT 627.220000 1125.480000 628.320000 1125.960000 ;
+ RECT 627.220000 1120.040000 628.320000 1120.520000 ;
+ RECT 627.220000 1114.600000 628.320000 1115.080000 ;
+ RECT 636.530000 1120.040000 637.530000 1120.520000 ;
+ RECT 636.530000 1114.600000 637.530000 1115.080000 ;
+ RECT 627.220000 1098.280000 628.320000 1098.760000 ;
+ RECT 627.220000 1103.720000 628.320000 1104.200000 ;
+ RECT 636.530000 1103.720000 637.530000 1104.200000 ;
+ RECT 636.530000 1098.280000 637.530000 1098.760000 ;
+ RECT 627.220000 1109.160000 628.320000 1109.640000 ;
+ RECT 636.530000 1109.160000 637.530000 1109.640000 ;
+ RECT 582.220000 1136.360000 583.320000 1136.840000 ;
+ RECT 582.220000 1130.920000 583.320000 1131.400000 ;
+ RECT 582.220000 1125.480000 583.320000 1125.960000 ;
+ RECT 582.220000 1120.040000 583.320000 1120.520000 ;
+ RECT 582.220000 1098.280000 583.320000 1098.760000 ;
+ RECT 582.220000 1103.720000 583.320000 1104.200000 ;
+ RECT 582.220000 1109.160000 583.320000 1109.640000 ;
+ RECT 582.220000 1114.600000 583.320000 1115.080000 ;
+ RECT 636.530000 1087.400000 637.530000 1087.880000 ;
+ RECT 636.530000 1092.840000 637.530000 1093.320000 ;
+ RECT 627.220000 1092.840000 628.320000 1093.320000 ;
+ RECT 627.220000 1087.400000 628.320000 1087.880000 ;
+ RECT 627.220000 1081.960000 628.320000 1082.440000 ;
+ RECT 627.220000 1076.520000 628.320000 1077.000000 ;
+ RECT 636.530000 1081.960000 637.530000 1082.440000 ;
+ RECT 636.530000 1076.520000 637.530000 1077.000000 ;
+ RECT 636.530000 1060.200000 637.530000 1060.680000 ;
+ RECT 636.530000 1065.640000 637.530000 1066.120000 ;
+ RECT 636.530000 1071.080000 637.530000 1071.560000 ;
+ RECT 627.220000 1065.640000 628.320000 1066.120000 ;
+ RECT 627.220000 1060.200000 628.320000 1060.680000 ;
+ RECT 627.220000 1071.080000 628.320000 1071.560000 ;
+ RECT 627.220000 1054.760000 628.320000 1055.240000 ;
+ RECT 627.220000 1049.320000 628.320000 1049.800000 ;
+ RECT 636.530000 1054.760000 637.530000 1055.240000 ;
+ RECT 636.530000 1049.320000 637.530000 1049.800000 ;
+ RECT 582.220000 1092.840000 583.320000 1093.320000 ;
+ RECT 582.220000 1087.400000 583.320000 1087.880000 ;
+ RECT 582.220000 1081.960000 583.320000 1082.440000 ;
+ RECT 582.220000 1076.520000 583.320000 1077.000000 ;
+ RECT 582.220000 1065.640000 583.320000 1066.120000 ;
+ RECT 582.220000 1060.200000 583.320000 1060.680000 ;
+ RECT 582.220000 1054.760000 583.320000 1055.240000 ;
+ RECT 582.220000 1049.320000 583.320000 1049.800000 ;
+ RECT 582.220000 1071.080000 583.320000 1071.560000 ;
+ RECT 537.220000 1136.360000 538.320000 1136.840000 ;
+ RECT 537.220000 1130.920000 538.320000 1131.400000 ;
+ RECT 537.220000 1125.480000 538.320000 1125.960000 ;
+ RECT 492.220000 1136.360000 493.320000 1136.840000 ;
+ RECT 492.220000 1130.920000 493.320000 1131.400000 ;
+ RECT 492.220000 1125.480000 493.320000 1125.960000 ;
+ RECT 537.220000 1109.160000 538.320000 1109.640000 ;
+ RECT 537.220000 1103.720000 538.320000 1104.200000 ;
+ RECT 537.220000 1098.280000 538.320000 1098.760000 ;
+ RECT 537.220000 1114.600000 538.320000 1115.080000 ;
+ RECT 537.220000 1120.040000 538.320000 1120.520000 ;
+ RECT 492.220000 1120.040000 493.320000 1120.520000 ;
+ RECT 492.220000 1109.160000 493.320000 1109.640000 ;
+ RECT 492.220000 1103.720000 493.320000 1104.200000 ;
+ RECT 492.220000 1098.280000 493.320000 1098.760000 ;
+ RECT 492.220000 1114.600000 493.320000 1115.080000 ;
+ RECT 447.220000 1136.360000 448.320000 1136.840000 ;
+ RECT 443.090000 1136.360000 444.090000 1136.840000 ;
+ RECT 443.090000 1130.920000 444.090000 1131.400000 ;
+ RECT 447.220000 1130.920000 448.320000 1131.400000 ;
+ RECT 447.220000 1125.480000 448.320000 1125.960000 ;
+ RECT 443.090000 1125.480000 444.090000 1125.960000 ;
+ RECT 447.220000 1120.040000 448.320000 1120.520000 ;
+ RECT 443.090000 1120.040000 444.090000 1120.520000 ;
+ RECT 447.220000 1114.600000 448.320000 1115.080000 ;
+ RECT 443.090000 1114.600000 444.090000 1115.080000 ;
+ RECT 447.220000 1103.720000 448.320000 1104.200000 ;
+ RECT 443.090000 1103.720000 444.090000 1104.200000 ;
+ RECT 447.220000 1098.280000 448.320000 1098.760000 ;
+ RECT 443.090000 1098.280000 444.090000 1098.760000 ;
+ RECT 447.220000 1109.160000 448.320000 1109.640000 ;
+ RECT 443.090000 1109.160000 444.090000 1109.640000 ;
+ RECT 537.220000 1092.840000 538.320000 1093.320000 ;
+ RECT 537.220000 1087.400000 538.320000 1087.880000 ;
+ RECT 537.220000 1081.960000 538.320000 1082.440000 ;
+ RECT 537.220000 1076.520000 538.320000 1077.000000 ;
+ RECT 492.220000 1092.840000 493.320000 1093.320000 ;
+ RECT 492.220000 1087.400000 493.320000 1087.880000 ;
+ RECT 492.220000 1081.960000 493.320000 1082.440000 ;
+ RECT 492.220000 1076.520000 493.320000 1077.000000 ;
+ RECT 537.220000 1065.640000 538.320000 1066.120000 ;
+ RECT 537.220000 1049.320000 538.320000 1049.800000 ;
+ RECT 537.220000 1054.760000 538.320000 1055.240000 ;
+ RECT 537.220000 1060.200000 538.320000 1060.680000 ;
+ RECT 537.220000 1071.080000 538.320000 1071.560000 ;
+ RECT 492.220000 1049.320000 493.320000 1049.800000 ;
+ RECT 492.220000 1054.760000 493.320000 1055.240000 ;
+ RECT 492.220000 1060.200000 493.320000 1060.680000 ;
+ RECT 492.220000 1065.640000 493.320000 1066.120000 ;
+ RECT 492.220000 1071.080000 493.320000 1071.560000 ;
+ RECT 447.220000 1092.840000 448.320000 1093.320000 ;
+ RECT 443.090000 1092.840000 444.090000 1093.320000 ;
+ RECT 447.220000 1087.400000 448.320000 1087.880000 ;
+ RECT 443.090000 1087.400000 444.090000 1087.880000 ;
+ RECT 447.220000 1081.960000 448.320000 1082.440000 ;
+ RECT 443.090000 1081.960000 444.090000 1082.440000 ;
+ RECT 447.220000 1076.520000 448.320000 1077.000000 ;
+ RECT 443.090000 1076.520000 444.090000 1077.000000 ;
+ RECT 447.220000 1071.080000 448.320000 1071.560000 ;
+ RECT 447.220000 1065.640000 448.320000 1066.120000 ;
+ RECT 443.090000 1071.080000 444.090000 1071.560000 ;
+ RECT 443.090000 1065.640000 444.090000 1066.120000 ;
+ RECT 447.220000 1060.200000 448.320000 1060.680000 ;
+ RECT 443.090000 1060.200000 444.090000 1060.680000 ;
+ RECT 447.220000 1054.760000 448.320000 1055.240000 ;
+ RECT 443.090000 1054.760000 444.090000 1055.240000 ;
+ RECT 447.220000 1049.320000 448.320000 1049.800000 ;
+ RECT 443.090000 1049.320000 444.090000 1049.800000 ;
+ RECT 627.220000 1043.880000 628.320000 1044.360000 ;
+ RECT 627.220000 1038.440000 628.320000 1038.920000 ;
+ RECT 636.530000 1043.880000 637.530000 1044.360000 ;
+ RECT 636.530000 1038.440000 637.530000 1038.920000 ;
+ RECT 636.530000 1022.120000 637.530000 1022.600000 ;
+ RECT 636.530000 1027.560000 637.530000 1028.040000 ;
+ RECT 636.530000 1033.000000 637.530000 1033.480000 ;
+ RECT 627.220000 1033.000000 628.320000 1033.480000 ;
+ RECT 627.220000 1027.560000 628.320000 1028.040000 ;
+ RECT 627.220000 1022.120000 628.320000 1022.600000 ;
+ RECT 627.220000 1011.240000 628.320000 1011.720000 ;
+ RECT 627.220000 1016.680000 628.320000 1017.160000 ;
+ RECT 636.530000 1016.680000 637.530000 1017.160000 ;
+ RECT 636.530000 1011.240000 637.530000 1011.720000 ;
+ RECT 636.530000 1000.360000 637.530000 1000.840000 ;
+ RECT 636.530000 1005.800000 637.530000 1006.280000 ;
+ RECT 627.220000 1000.360000 628.320000 1000.840000 ;
+ RECT 627.220000 1005.800000 628.320000 1006.280000 ;
+ RECT 582.220000 1043.880000 583.320000 1044.360000 ;
+ RECT 582.220000 1038.440000 583.320000 1038.920000 ;
+ RECT 582.220000 1033.000000 583.320000 1033.480000 ;
+ RECT 582.220000 1027.560000 583.320000 1028.040000 ;
+ RECT 582.220000 1022.120000 583.320000 1022.600000 ;
+ RECT 582.220000 1000.360000 583.320000 1000.840000 ;
+ RECT 582.220000 1005.800000 583.320000 1006.280000 ;
+ RECT 582.220000 1011.240000 583.320000 1011.720000 ;
+ RECT 582.220000 1016.680000 583.320000 1017.160000 ;
+ RECT 627.220000 994.920000 628.320000 995.400000 ;
+ RECT 627.220000 989.480000 628.320000 989.960000 ;
+ RECT 636.530000 994.920000 637.530000 995.400000 ;
+ RECT 636.530000 989.480000 637.530000 989.960000 ;
+ RECT 627.220000 978.600000 628.320000 979.080000 ;
+ RECT 627.220000 973.160000 628.320000 973.640000 ;
+ RECT 636.530000 978.600000 637.530000 979.080000 ;
+ RECT 636.530000 973.160000 637.530000 973.640000 ;
+ RECT 627.220000 984.040000 628.320000 984.520000 ;
+ RECT 636.530000 984.040000 637.530000 984.520000 ;
+ RECT 636.530000 962.280000 637.530000 962.760000 ;
+ RECT 636.530000 967.720000 637.530000 968.200000 ;
+ RECT 627.220000 967.720000 628.320000 968.200000 ;
+ RECT 627.220000 962.280000 628.320000 962.760000 ;
+ RECT 627.220000 956.840000 628.320000 957.320000 ;
+ RECT 627.220000 951.400000 628.320000 951.880000 ;
+ RECT 636.530000 956.840000 637.530000 957.320000 ;
+ RECT 636.530000 951.400000 637.530000 951.880000 ;
+ RECT 582.220000 994.920000 583.320000 995.400000 ;
+ RECT 582.220000 989.480000 583.320000 989.960000 ;
+ RECT 582.220000 984.040000 583.320000 984.520000 ;
+ RECT 582.220000 978.600000 583.320000 979.080000 ;
+ RECT 582.220000 973.160000 583.320000 973.640000 ;
+ RECT 582.220000 967.720000 583.320000 968.200000 ;
+ RECT 582.220000 962.280000 583.320000 962.760000 ;
+ RECT 582.220000 956.840000 583.320000 957.320000 ;
+ RECT 582.220000 951.400000 583.320000 951.880000 ;
+ RECT 537.220000 1043.880000 538.320000 1044.360000 ;
+ RECT 537.220000 1038.440000 538.320000 1038.920000 ;
+ RECT 537.220000 1033.000000 538.320000 1033.480000 ;
+ RECT 537.220000 1027.560000 538.320000 1028.040000 ;
+ RECT 537.220000 1022.120000 538.320000 1022.600000 ;
+ RECT 492.220000 1043.880000 493.320000 1044.360000 ;
+ RECT 492.220000 1038.440000 493.320000 1038.920000 ;
+ RECT 492.220000 1033.000000 493.320000 1033.480000 ;
+ RECT 492.220000 1027.560000 493.320000 1028.040000 ;
+ RECT 492.220000 1022.120000 493.320000 1022.600000 ;
+ RECT 537.220000 1016.680000 538.320000 1017.160000 ;
+ RECT 537.220000 1011.240000 538.320000 1011.720000 ;
+ RECT 537.220000 1005.800000 538.320000 1006.280000 ;
+ RECT 537.220000 1000.360000 538.320000 1000.840000 ;
+ RECT 492.220000 1011.240000 493.320000 1011.720000 ;
+ RECT 492.220000 1005.800000 493.320000 1006.280000 ;
+ RECT 492.220000 1000.360000 493.320000 1000.840000 ;
+ RECT 492.220000 1016.680000 493.320000 1017.160000 ;
+ RECT 447.220000 1043.880000 448.320000 1044.360000 ;
+ RECT 443.090000 1043.880000 444.090000 1044.360000 ;
+ RECT 447.220000 1038.440000 448.320000 1038.920000 ;
+ RECT 443.090000 1038.440000 444.090000 1038.920000 ;
+ RECT 447.220000 1033.000000 448.320000 1033.480000 ;
+ RECT 443.090000 1033.000000 444.090000 1033.480000 ;
+ RECT 447.220000 1022.120000 448.320000 1022.600000 ;
+ RECT 443.090000 1022.120000 444.090000 1022.600000 ;
+ RECT 443.090000 1027.560000 444.090000 1028.040000 ;
+ RECT 447.220000 1027.560000 448.320000 1028.040000 ;
+ RECT 447.220000 1016.680000 448.320000 1017.160000 ;
+ RECT 443.090000 1016.680000 444.090000 1017.160000 ;
+ RECT 447.220000 1011.240000 448.320000 1011.720000 ;
+ RECT 443.090000 1011.240000 444.090000 1011.720000 ;
+ RECT 447.220000 1005.800000 448.320000 1006.280000 ;
+ RECT 443.090000 1005.800000 444.090000 1006.280000 ;
+ RECT 447.220000 1000.360000 448.320000 1000.840000 ;
+ RECT 443.090000 1000.360000 444.090000 1000.840000 ;
+ RECT 537.220000 994.920000 538.320000 995.400000 ;
+ RECT 537.220000 989.480000 538.320000 989.960000 ;
+ RECT 537.220000 984.040000 538.320000 984.520000 ;
+ RECT 537.220000 978.600000 538.320000 979.080000 ;
+ RECT 537.220000 973.160000 538.320000 973.640000 ;
+ RECT 492.220000 994.920000 493.320000 995.400000 ;
+ RECT 492.220000 989.480000 493.320000 989.960000 ;
+ RECT 492.220000 984.040000 493.320000 984.520000 ;
+ RECT 492.220000 978.600000 493.320000 979.080000 ;
+ RECT 492.220000 973.160000 493.320000 973.640000 ;
+ RECT 537.220000 951.400000 538.320000 951.880000 ;
+ RECT 537.220000 956.840000 538.320000 957.320000 ;
+ RECT 537.220000 962.280000 538.320000 962.760000 ;
+ RECT 537.220000 967.720000 538.320000 968.200000 ;
+ RECT 492.220000 951.400000 493.320000 951.880000 ;
+ RECT 492.220000 956.840000 493.320000 957.320000 ;
+ RECT 492.220000 962.280000 493.320000 962.760000 ;
+ RECT 492.220000 967.720000 493.320000 968.200000 ;
+ RECT 447.220000 994.920000 448.320000 995.400000 ;
+ RECT 443.090000 994.920000 444.090000 995.400000 ;
+ RECT 447.220000 989.480000 448.320000 989.960000 ;
+ RECT 443.090000 989.480000 444.090000 989.960000 ;
+ RECT 447.220000 978.600000 448.320000 979.080000 ;
+ RECT 443.090000 978.600000 444.090000 979.080000 ;
+ RECT 447.220000 973.160000 448.320000 973.640000 ;
+ RECT 443.090000 973.160000 444.090000 973.640000 ;
+ RECT 447.220000 984.040000 448.320000 984.520000 ;
+ RECT 443.090000 984.040000 444.090000 984.520000 ;
+ RECT 447.220000 967.720000 448.320000 968.200000 ;
+ RECT 443.090000 967.720000 444.090000 968.200000 ;
+ RECT 447.220000 962.280000 448.320000 962.760000 ;
+ RECT 443.090000 962.280000 444.090000 962.760000 ;
+ RECT 447.220000 956.840000 448.320000 957.320000 ;
+ RECT 447.220000 951.400000 448.320000 951.880000 ;
+ RECT 443.090000 956.840000 444.090000 957.320000 ;
+ RECT 443.090000 951.400000 444.090000 951.880000 ;
+ RECT 440.260000 1141.760000 640.360000 1142.760000 ;
+ RECT 440.260000 949.390000 640.360000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 946.540000 444.090000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 1145.800000 444.090000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 946.540000 637.530000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 1145.800000 637.530000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 949.390000 441.260000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 949.390000 640.360000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1141.760000 441.260000 1142.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1141.760000 640.360000 1142.760000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 749.130000 628.320000 942.500000 ;
+ RECT 582.220000 749.130000 583.320000 942.500000 ;
+ RECT 636.530000 746.280000 637.530000 946.540000 ;
+ RECT 537.220000 749.130000 538.320000 942.500000 ;
+ RECT 492.220000 749.130000 493.320000 942.500000 ;
+ RECT 447.220000 749.130000 448.320000 942.500000 ;
+ RECT 443.090000 746.280000 444.090000 946.540000 ;
+ LAYER met3 ;
+ RECT 627.220000 936.100000 628.320000 936.580000 ;
+ RECT 636.530000 936.100000 637.530000 936.580000 ;
+ RECT 636.530000 925.220000 637.530000 925.700000 ;
+ RECT 636.530000 930.660000 637.530000 931.140000 ;
+ RECT 627.220000 930.660000 628.320000 931.140000 ;
+ RECT 627.220000 925.220000 628.320000 925.700000 ;
+ RECT 627.220000 919.780000 628.320000 920.260000 ;
+ RECT 627.220000 914.340000 628.320000 914.820000 ;
+ RECT 636.530000 919.780000 637.530000 920.260000 ;
+ RECT 636.530000 914.340000 637.530000 914.820000 ;
+ RECT 627.220000 898.020000 628.320000 898.500000 ;
+ RECT 627.220000 903.460000 628.320000 903.940000 ;
+ RECT 636.530000 903.460000 637.530000 903.940000 ;
+ RECT 636.530000 898.020000 637.530000 898.500000 ;
+ RECT 627.220000 908.900000 628.320000 909.380000 ;
+ RECT 636.530000 908.900000 637.530000 909.380000 ;
+ RECT 582.220000 936.100000 583.320000 936.580000 ;
+ RECT 582.220000 930.660000 583.320000 931.140000 ;
+ RECT 582.220000 925.220000 583.320000 925.700000 ;
+ RECT 582.220000 919.780000 583.320000 920.260000 ;
+ RECT 582.220000 898.020000 583.320000 898.500000 ;
+ RECT 582.220000 903.460000 583.320000 903.940000 ;
+ RECT 582.220000 908.900000 583.320000 909.380000 ;
+ RECT 582.220000 914.340000 583.320000 914.820000 ;
+ RECT 636.530000 887.140000 637.530000 887.620000 ;
+ RECT 636.530000 892.580000 637.530000 893.060000 ;
+ RECT 627.220000 892.580000 628.320000 893.060000 ;
+ RECT 627.220000 887.140000 628.320000 887.620000 ;
+ RECT 627.220000 881.700000 628.320000 882.180000 ;
+ RECT 627.220000 876.260000 628.320000 876.740000 ;
+ RECT 636.530000 881.700000 637.530000 882.180000 ;
+ RECT 636.530000 876.260000 637.530000 876.740000 ;
+ RECT 636.530000 859.940000 637.530000 860.420000 ;
+ RECT 636.530000 865.380000 637.530000 865.860000 ;
+ RECT 636.530000 870.820000 637.530000 871.300000 ;
+ RECT 627.220000 865.380000 628.320000 865.860000 ;
+ RECT 627.220000 859.940000 628.320000 860.420000 ;
+ RECT 627.220000 870.820000 628.320000 871.300000 ;
+ RECT 627.220000 854.500000 628.320000 854.980000 ;
+ RECT 627.220000 849.060000 628.320000 849.540000 ;
+ RECT 636.530000 854.500000 637.530000 854.980000 ;
+ RECT 636.530000 849.060000 637.530000 849.540000 ;
+ RECT 582.220000 892.580000 583.320000 893.060000 ;
+ RECT 582.220000 887.140000 583.320000 887.620000 ;
+ RECT 582.220000 881.700000 583.320000 882.180000 ;
+ RECT 582.220000 876.260000 583.320000 876.740000 ;
+ RECT 582.220000 865.380000 583.320000 865.860000 ;
+ RECT 582.220000 859.940000 583.320000 860.420000 ;
+ RECT 582.220000 854.500000 583.320000 854.980000 ;
+ RECT 582.220000 849.060000 583.320000 849.540000 ;
+ RECT 582.220000 870.820000 583.320000 871.300000 ;
+ RECT 537.220000 936.100000 538.320000 936.580000 ;
+ RECT 537.220000 930.660000 538.320000 931.140000 ;
+ RECT 537.220000 925.220000 538.320000 925.700000 ;
+ RECT 492.220000 936.100000 493.320000 936.580000 ;
+ RECT 492.220000 930.660000 493.320000 931.140000 ;
+ RECT 492.220000 925.220000 493.320000 925.700000 ;
+ RECT 537.220000 908.900000 538.320000 909.380000 ;
+ RECT 537.220000 903.460000 538.320000 903.940000 ;
+ RECT 537.220000 898.020000 538.320000 898.500000 ;
+ RECT 537.220000 914.340000 538.320000 914.820000 ;
+ RECT 537.220000 919.780000 538.320000 920.260000 ;
+ RECT 492.220000 919.780000 493.320000 920.260000 ;
+ RECT 492.220000 908.900000 493.320000 909.380000 ;
+ RECT 492.220000 903.460000 493.320000 903.940000 ;
+ RECT 492.220000 898.020000 493.320000 898.500000 ;
+ RECT 492.220000 914.340000 493.320000 914.820000 ;
+ RECT 447.220000 936.100000 448.320000 936.580000 ;
+ RECT 443.090000 936.100000 444.090000 936.580000 ;
+ RECT 443.090000 930.660000 444.090000 931.140000 ;
+ RECT 447.220000 930.660000 448.320000 931.140000 ;
+ RECT 447.220000 925.220000 448.320000 925.700000 ;
+ RECT 443.090000 925.220000 444.090000 925.700000 ;
+ RECT 447.220000 919.780000 448.320000 920.260000 ;
+ RECT 443.090000 919.780000 444.090000 920.260000 ;
+ RECT 447.220000 914.340000 448.320000 914.820000 ;
+ RECT 443.090000 914.340000 444.090000 914.820000 ;
+ RECT 447.220000 903.460000 448.320000 903.940000 ;
+ RECT 443.090000 903.460000 444.090000 903.940000 ;
+ RECT 447.220000 898.020000 448.320000 898.500000 ;
+ RECT 443.090000 898.020000 444.090000 898.500000 ;
+ RECT 447.220000 908.900000 448.320000 909.380000 ;
+ RECT 443.090000 908.900000 444.090000 909.380000 ;
+ RECT 537.220000 892.580000 538.320000 893.060000 ;
+ RECT 537.220000 887.140000 538.320000 887.620000 ;
+ RECT 537.220000 881.700000 538.320000 882.180000 ;
+ RECT 537.220000 876.260000 538.320000 876.740000 ;
+ RECT 492.220000 892.580000 493.320000 893.060000 ;
+ RECT 492.220000 887.140000 493.320000 887.620000 ;
+ RECT 492.220000 881.700000 493.320000 882.180000 ;
+ RECT 492.220000 876.260000 493.320000 876.740000 ;
+ RECT 537.220000 865.380000 538.320000 865.860000 ;
+ RECT 537.220000 849.060000 538.320000 849.540000 ;
+ RECT 537.220000 854.500000 538.320000 854.980000 ;
+ RECT 537.220000 859.940000 538.320000 860.420000 ;
+ RECT 537.220000 870.820000 538.320000 871.300000 ;
+ RECT 492.220000 849.060000 493.320000 849.540000 ;
+ RECT 492.220000 854.500000 493.320000 854.980000 ;
+ RECT 492.220000 859.940000 493.320000 860.420000 ;
+ RECT 492.220000 865.380000 493.320000 865.860000 ;
+ RECT 492.220000 870.820000 493.320000 871.300000 ;
+ RECT 447.220000 892.580000 448.320000 893.060000 ;
+ RECT 443.090000 892.580000 444.090000 893.060000 ;
+ RECT 447.220000 887.140000 448.320000 887.620000 ;
+ RECT 443.090000 887.140000 444.090000 887.620000 ;
+ RECT 447.220000 881.700000 448.320000 882.180000 ;
+ RECT 443.090000 881.700000 444.090000 882.180000 ;
+ RECT 447.220000 876.260000 448.320000 876.740000 ;
+ RECT 443.090000 876.260000 444.090000 876.740000 ;
+ RECT 447.220000 870.820000 448.320000 871.300000 ;
+ RECT 447.220000 865.380000 448.320000 865.860000 ;
+ RECT 443.090000 870.820000 444.090000 871.300000 ;
+ RECT 443.090000 865.380000 444.090000 865.860000 ;
+ RECT 447.220000 859.940000 448.320000 860.420000 ;
+ RECT 443.090000 859.940000 444.090000 860.420000 ;
+ RECT 447.220000 854.500000 448.320000 854.980000 ;
+ RECT 443.090000 854.500000 444.090000 854.980000 ;
+ RECT 447.220000 849.060000 448.320000 849.540000 ;
+ RECT 443.090000 849.060000 444.090000 849.540000 ;
+ RECT 627.220000 843.620000 628.320000 844.100000 ;
+ RECT 627.220000 838.180000 628.320000 838.660000 ;
+ RECT 636.530000 843.620000 637.530000 844.100000 ;
+ RECT 636.530000 838.180000 637.530000 838.660000 ;
+ RECT 636.530000 821.860000 637.530000 822.340000 ;
+ RECT 636.530000 827.300000 637.530000 827.780000 ;
+ RECT 636.530000 832.740000 637.530000 833.220000 ;
+ RECT 627.220000 832.740000 628.320000 833.220000 ;
+ RECT 627.220000 827.300000 628.320000 827.780000 ;
+ RECT 627.220000 821.860000 628.320000 822.340000 ;
+ RECT 627.220000 810.980000 628.320000 811.460000 ;
+ RECT 627.220000 816.420000 628.320000 816.900000 ;
+ RECT 636.530000 816.420000 637.530000 816.900000 ;
+ RECT 636.530000 810.980000 637.530000 811.460000 ;
+ RECT 636.530000 800.100000 637.530000 800.580000 ;
+ RECT 636.530000 805.540000 637.530000 806.020000 ;
+ RECT 627.220000 800.100000 628.320000 800.580000 ;
+ RECT 627.220000 805.540000 628.320000 806.020000 ;
+ RECT 582.220000 843.620000 583.320000 844.100000 ;
+ RECT 582.220000 838.180000 583.320000 838.660000 ;
+ RECT 582.220000 832.740000 583.320000 833.220000 ;
+ RECT 582.220000 827.300000 583.320000 827.780000 ;
+ RECT 582.220000 821.860000 583.320000 822.340000 ;
+ RECT 582.220000 800.100000 583.320000 800.580000 ;
+ RECT 582.220000 805.540000 583.320000 806.020000 ;
+ RECT 582.220000 810.980000 583.320000 811.460000 ;
+ RECT 582.220000 816.420000 583.320000 816.900000 ;
+ RECT 627.220000 794.660000 628.320000 795.140000 ;
+ RECT 627.220000 789.220000 628.320000 789.700000 ;
+ RECT 636.530000 794.660000 637.530000 795.140000 ;
+ RECT 636.530000 789.220000 637.530000 789.700000 ;
+ RECT 627.220000 778.340000 628.320000 778.820000 ;
+ RECT 627.220000 772.900000 628.320000 773.380000 ;
+ RECT 636.530000 778.340000 637.530000 778.820000 ;
+ RECT 636.530000 772.900000 637.530000 773.380000 ;
+ RECT 627.220000 783.780000 628.320000 784.260000 ;
+ RECT 636.530000 783.780000 637.530000 784.260000 ;
+ RECT 636.530000 762.020000 637.530000 762.500000 ;
+ RECT 636.530000 767.460000 637.530000 767.940000 ;
+ RECT 627.220000 767.460000 628.320000 767.940000 ;
+ RECT 627.220000 762.020000 628.320000 762.500000 ;
+ RECT 627.220000 756.580000 628.320000 757.060000 ;
+ RECT 627.220000 751.140000 628.320000 751.620000 ;
+ RECT 636.530000 756.580000 637.530000 757.060000 ;
+ RECT 636.530000 751.140000 637.530000 751.620000 ;
+ RECT 582.220000 794.660000 583.320000 795.140000 ;
+ RECT 582.220000 789.220000 583.320000 789.700000 ;
+ RECT 582.220000 783.780000 583.320000 784.260000 ;
+ RECT 582.220000 778.340000 583.320000 778.820000 ;
+ RECT 582.220000 772.900000 583.320000 773.380000 ;
+ RECT 582.220000 767.460000 583.320000 767.940000 ;
+ RECT 582.220000 762.020000 583.320000 762.500000 ;
+ RECT 582.220000 756.580000 583.320000 757.060000 ;
+ RECT 582.220000 751.140000 583.320000 751.620000 ;
+ RECT 537.220000 843.620000 538.320000 844.100000 ;
+ RECT 537.220000 838.180000 538.320000 838.660000 ;
+ RECT 537.220000 832.740000 538.320000 833.220000 ;
+ RECT 537.220000 827.300000 538.320000 827.780000 ;
+ RECT 537.220000 821.860000 538.320000 822.340000 ;
+ RECT 492.220000 843.620000 493.320000 844.100000 ;
+ RECT 492.220000 838.180000 493.320000 838.660000 ;
+ RECT 492.220000 832.740000 493.320000 833.220000 ;
+ RECT 492.220000 827.300000 493.320000 827.780000 ;
+ RECT 492.220000 821.860000 493.320000 822.340000 ;
+ RECT 537.220000 816.420000 538.320000 816.900000 ;
+ RECT 537.220000 810.980000 538.320000 811.460000 ;
+ RECT 537.220000 805.540000 538.320000 806.020000 ;
+ RECT 537.220000 800.100000 538.320000 800.580000 ;
+ RECT 492.220000 810.980000 493.320000 811.460000 ;
+ RECT 492.220000 805.540000 493.320000 806.020000 ;
+ RECT 492.220000 800.100000 493.320000 800.580000 ;
+ RECT 492.220000 816.420000 493.320000 816.900000 ;
+ RECT 447.220000 843.620000 448.320000 844.100000 ;
+ RECT 443.090000 843.620000 444.090000 844.100000 ;
+ RECT 447.220000 838.180000 448.320000 838.660000 ;
+ RECT 443.090000 838.180000 444.090000 838.660000 ;
+ RECT 447.220000 832.740000 448.320000 833.220000 ;
+ RECT 443.090000 832.740000 444.090000 833.220000 ;
+ RECT 447.220000 821.860000 448.320000 822.340000 ;
+ RECT 443.090000 821.860000 444.090000 822.340000 ;
+ RECT 443.090000 827.300000 444.090000 827.780000 ;
+ RECT 447.220000 827.300000 448.320000 827.780000 ;
+ RECT 447.220000 816.420000 448.320000 816.900000 ;
+ RECT 443.090000 816.420000 444.090000 816.900000 ;
+ RECT 447.220000 810.980000 448.320000 811.460000 ;
+ RECT 443.090000 810.980000 444.090000 811.460000 ;
+ RECT 447.220000 805.540000 448.320000 806.020000 ;
+ RECT 443.090000 805.540000 444.090000 806.020000 ;
+ RECT 447.220000 800.100000 448.320000 800.580000 ;
+ RECT 443.090000 800.100000 444.090000 800.580000 ;
+ RECT 537.220000 794.660000 538.320000 795.140000 ;
+ RECT 537.220000 789.220000 538.320000 789.700000 ;
+ RECT 537.220000 783.780000 538.320000 784.260000 ;
+ RECT 537.220000 778.340000 538.320000 778.820000 ;
+ RECT 537.220000 772.900000 538.320000 773.380000 ;
+ RECT 492.220000 794.660000 493.320000 795.140000 ;
+ RECT 492.220000 789.220000 493.320000 789.700000 ;
+ RECT 492.220000 783.780000 493.320000 784.260000 ;
+ RECT 492.220000 778.340000 493.320000 778.820000 ;
+ RECT 492.220000 772.900000 493.320000 773.380000 ;
+ RECT 537.220000 751.140000 538.320000 751.620000 ;
+ RECT 537.220000 756.580000 538.320000 757.060000 ;
+ RECT 537.220000 762.020000 538.320000 762.500000 ;
+ RECT 537.220000 767.460000 538.320000 767.940000 ;
+ RECT 492.220000 751.140000 493.320000 751.620000 ;
+ RECT 492.220000 756.580000 493.320000 757.060000 ;
+ RECT 492.220000 762.020000 493.320000 762.500000 ;
+ RECT 492.220000 767.460000 493.320000 767.940000 ;
+ RECT 447.220000 794.660000 448.320000 795.140000 ;
+ RECT 443.090000 794.660000 444.090000 795.140000 ;
+ RECT 447.220000 789.220000 448.320000 789.700000 ;
+ RECT 443.090000 789.220000 444.090000 789.700000 ;
+ RECT 447.220000 778.340000 448.320000 778.820000 ;
+ RECT 443.090000 778.340000 444.090000 778.820000 ;
+ RECT 447.220000 772.900000 448.320000 773.380000 ;
+ RECT 443.090000 772.900000 444.090000 773.380000 ;
+ RECT 447.220000 783.780000 448.320000 784.260000 ;
+ RECT 443.090000 783.780000 444.090000 784.260000 ;
+ RECT 447.220000 767.460000 448.320000 767.940000 ;
+ RECT 443.090000 767.460000 444.090000 767.940000 ;
+ RECT 447.220000 762.020000 448.320000 762.500000 ;
+ RECT 443.090000 762.020000 444.090000 762.500000 ;
+ RECT 447.220000 756.580000 448.320000 757.060000 ;
+ RECT 447.220000 751.140000 448.320000 751.620000 ;
+ RECT 443.090000 756.580000 444.090000 757.060000 ;
+ RECT 443.090000 751.140000 444.090000 751.620000 ;
+ RECT 440.260000 941.500000 640.360000 942.500000 ;
+ RECT 440.260000 749.130000 640.360000 750.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 746.280000 444.090000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 945.540000 444.090000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 746.280000 637.530000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 945.540000 637.530000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 749.130000 441.260000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 749.130000 640.360000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 941.500000 441.260000 942.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 941.500000 640.360000 942.500000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 548.870000 628.320000 742.240000 ;
+ RECT 582.220000 548.870000 583.320000 742.240000 ;
+ RECT 636.530000 546.020000 637.530000 746.280000 ;
+ RECT 537.220000 548.870000 538.320000 742.240000 ;
+ RECT 492.220000 548.870000 493.320000 742.240000 ;
+ RECT 447.220000 548.870000 448.320000 742.240000 ;
+ RECT 443.090000 546.020000 444.090000 746.280000 ;
+ LAYER met3 ;
+ RECT 627.220000 735.840000 628.320000 736.320000 ;
+ RECT 636.530000 735.840000 637.530000 736.320000 ;
+ RECT 636.530000 724.960000 637.530000 725.440000 ;
+ RECT 636.530000 730.400000 637.530000 730.880000 ;
+ RECT 627.220000 730.400000 628.320000 730.880000 ;
+ RECT 627.220000 724.960000 628.320000 725.440000 ;
+ RECT 627.220000 719.520000 628.320000 720.000000 ;
+ RECT 627.220000 714.080000 628.320000 714.560000 ;
+ RECT 636.530000 719.520000 637.530000 720.000000 ;
+ RECT 636.530000 714.080000 637.530000 714.560000 ;
+ RECT 627.220000 697.760000 628.320000 698.240000 ;
+ RECT 627.220000 703.200000 628.320000 703.680000 ;
+ RECT 636.530000 703.200000 637.530000 703.680000 ;
+ RECT 636.530000 697.760000 637.530000 698.240000 ;
+ RECT 627.220000 708.640000 628.320000 709.120000 ;
+ RECT 636.530000 708.640000 637.530000 709.120000 ;
+ RECT 582.220000 735.840000 583.320000 736.320000 ;
+ RECT 582.220000 730.400000 583.320000 730.880000 ;
+ RECT 582.220000 724.960000 583.320000 725.440000 ;
+ RECT 582.220000 719.520000 583.320000 720.000000 ;
+ RECT 582.220000 697.760000 583.320000 698.240000 ;
+ RECT 582.220000 703.200000 583.320000 703.680000 ;
+ RECT 582.220000 708.640000 583.320000 709.120000 ;
+ RECT 582.220000 714.080000 583.320000 714.560000 ;
+ RECT 636.530000 686.880000 637.530000 687.360000 ;
+ RECT 636.530000 692.320000 637.530000 692.800000 ;
+ RECT 627.220000 692.320000 628.320000 692.800000 ;
+ RECT 627.220000 686.880000 628.320000 687.360000 ;
+ RECT 627.220000 681.440000 628.320000 681.920000 ;
+ RECT 627.220000 676.000000 628.320000 676.480000 ;
+ RECT 636.530000 681.440000 637.530000 681.920000 ;
+ RECT 636.530000 676.000000 637.530000 676.480000 ;
+ RECT 636.530000 659.680000 637.530000 660.160000 ;
+ RECT 636.530000 665.120000 637.530000 665.600000 ;
+ RECT 636.530000 670.560000 637.530000 671.040000 ;
+ RECT 627.220000 665.120000 628.320000 665.600000 ;
+ RECT 627.220000 659.680000 628.320000 660.160000 ;
+ RECT 627.220000 670.560000 628.320000 671.040000 ;
+ RECT 627.220000 654.240000 628.320000 654.720000 ;
+ RECT 627.220000 648.800000 628.320000 649.280000 ;
+ RECT 636.530000 654.240000 637.530000 654.720000 ;
+ RECT 636.530000 648.800000 637.530000 649.280000 ;
+ RECT 582.220000 692.320000 583.320000 692.800000 ;
+ RECT 582.220000 686.880000 583.320000 687.360000 ;
+ RECT 582.220000 681.440000 583.320000 681.920000 ;
+ RECT 582.220000 676.000000 583.320000 676.480000 ;
+ RECT 582.220000 665.120000 583.320000 665.600000 ;
+ RECT 582.220000 659.680000 583.320000 660.160000 ;
+ RECT 582.220000 654.240000 583.320000 654.720000 ;
+ RECT 582.220000 648.800000 583.320000 649.280000 ;
+ RECT 582.220000 670.560000 583.320000 671.040000 ;
+ RECT 537.220000 735.840000 538.320000 736.320000 ;
+ RECT 537.220000 730.400000 538.320000 730.880000 ;
+ RECT 537.220000 724.960000 538.320000 725.440000 ;
+ RECT 492.220000 735.840000 493.320000 736.320000 ;
+ RECT 492.220000 730.400000 493.320000 730.880000 ;
+ RECT 492.220000 724.960000 493.320000 725.440000 ;
+ RECT 537.220000 708.640000 538.320000 709.120000 ;
+ RECT 537.220000 703.200000 538.320000 703.680000 ;
+ RECT 537.220000 697.760000 538.320000 698.240000 ;
+ RECT 537.220000 714.080000 538.320000 714.560000 ;
+ RECT 537.220000 719.520000 538.320000 720.000000 ;
+ RECT 492.220000 719.520000 493.320000 720.000000 ;
+ RECT 492.220000 708.640000 493.320000 709.120000 ;
+ RECT 492.220000 703.200000 493.320000 703.680000 ;
+ RECT 492.220000 697.760000 493.320000 698.240000 ;
+ RECT 492.220000 714.080000 493.320000 714.560000 ;
+ RECT 447.220000 735.840000 448.320000 736.320000 ;
+ RECT 443.090000 735.840000 444.090000 736.320000 ;
+ RECT 443.090000 730.400000 444.090000 730.880000 ;
+ RECT 447.220000 730.400000 448.320000 730.880000 ;
+ RECT 447.220000 724.960000 448.320000 725.440000 ;
+ RECT 443.090000 724.960000 444.090000 725.440000 ;
+ RECT 447.220000 719.520000 448.320000 720.000000 ;
+ RECT 443.090000 719.520000 444.090000 720.000000 ;
+ RECT 447.220000 714.080000 448.320000 714.560000 ;
+ RECT 443.090000 714.080000 444.090000 714.560000 ;
+ RECT 447.220000 703.200000 448.320000 703.680000 ;
+ RECT 443.090000 703.200000 444.090000 703.680000 ;
+ RECT 447.220000 697.760000 448.320000 698.240000 ;
+ RECT 443.090000 697.760000 444.090000 698.240000 ;
+ RECT 447.220000 708.640000 448.320000 709.120000 ;
+ RECT 443.090000 708.640000 444.090000 709.120000 ;
+ RECT 537.220000 692.320000 538.320000 692.800000 ;
+ RECT 537.220000 686.880000 538.320000 687.360000 ;
+ RECT 537.220000 681.440000 538.320000 681.920000 ;
+ RECT 537.220000 676.000000 538.320000 676.480000 ;
+ RECT 492.220000 692.320000 493.320000 692.800000 ;
+ RECT 492.220000 686.880000 493.320000 687.360000 ;
+ RECT 492.220000 681.440000 493.320000 681.920000 ;
+ RECT 492.220000 676.000000 493.320000 676.480000 ;
+ RECT 537.220000 665.120000 538.320000 665.600000 ;
+ RECT 537.220000 648.800000 538.320000 649.280000 ;
+ RECT 537.220000 654.240000 538.320000 654.720000 ;
+ RECT 537.220000 659.680000 538.320000 660.160000 ;
+ RECT 537.220000 670.560000 538.320000 671.040000 ;
+ RECT 492.220000 648.800000 493.320000 649.280000 ;
+ RECT 492.220000 654.240000 493.320000 654.720000 ;
+ RECT 492.220000 659.680000 493.320000 660.160000 ;
+ RECT 492.220000 665.120000 493.320000 665.600000 ;
+ RECT 492.220000 670.560000 493.320000 671.040000 ;
+ RECT 447.220000 692.320000 448.320000 692.800000 ;
+ RECT 443.090000 692.320000 444.090000 692.800000 ;
+ RECT 447.220000 686.880000 448.320000 687.360000 ;
+ RECT 443.090000 686.880000 444.090000 687.360000 ;
+ RECT 447.220000 681.440000 448.320000 681.920000 ;
+ RECT 443.090000 681.440000 444.090000 681.920000 ;
+ RECT 447.220000 676.000000 448.320000 676.480000 ;
+ RECT 443.090000 676.000000 444.090000 676.480000 ;
+ RECT 447.220000 670.560000 448.320000 671.040000 ;
+ RECT 447.220000 665.120000 448.320000 665.600000 ;
+ RECT 443.090000 670.560000 444.090000 671.040000 ;
+ RECT 443.090000 665.120000 444.090000 665.600000 ;
+ RECT 447.220000 659.680000 448.320000 660.160000 ;
+ RECT 443.090000 659.680000 444.090000 660.160000 ;
+ RECT 447.220000 654.240000 448.320000 654.720000 ;
+ RECT 443.090000 654.240000 444.090000 654.720000 ;
+ RECT 447.220000 648.800000 448.320000 649.280000 ;
+ RECT 443.090000 648.800000 444.090000 649.280000 ;
+ RECT 627.220000 643.360000 628.320000 643.840000 ;
+ RECT 627.220000 637.920000 628.320000 638.400000 ;
+ RECT 636.530000 643.360000 637.530000 643.840000 ;
+ RECT 636.530000 637.920000 637.530000 638.400000 ;
+ RECT 636.530000 621.600000 637.530000 622.080000 ;
+ RECT 636.530000 627.040000 637.530000 627.520000 ;
+ RECT 636.530000 632.480000 637.530000 632.960000 ;
+ RECT 627.220000 632.480000 628.320000 632.960000 ;
+ RECT 627.220000 627.040000 628.320000 627.520000 ;
+ RECT 627.220000 621.600000 628.320000 622.080000 ;
+ RECT 627.220000 610.720000 628.320000 611.200000 ;
+ RECT 627.220000 616.160000 628.320000 616.640000 ;
+ RECT 636.530000 616.160000 637.530000 616.640000 ;
+ RECT 636.530000 610.720000 637.530000 611.200000 ;
+ RECT 636.530000 599.840000 637.530000 600.320000 ;
+ RECT 636.530000 605.280000 637.530000 605.760000 ;
+ RECT 627.220000 599.840000 628.320000 600.320000 ;
+ RECT 627.220000 605.280000 628.320000 605.760000 ;
+ RECT 582.220000 643.360000 583.320000 643.840000 ;
+ RECT 582.220000 637.920000 583.320000 638.400000 ;
+ RECT 582.220000 632.480000 583.320000 632.960000 ;
+ RECT 582.220000 627.040000 583.320000 627.520000 ;
+ RECT 582.220000 621.600000 583.320000 622.080000 ;
+ RECT 582.220000 599.840000 583.320000 600.320000 ;
+ RECT 582.220000 605.280000 583.320000 605.760000 ;
+ RECT 582.220000 610.720000 583.320000 611.200000 ;
+ RECT 582.220000 616.160000 583.320000 616.640000 ;
+ RECT 627.220000 594.400000 628.320000 594.880000 ;
+ RECT 627.220000 588.960000 628.320000 589.440000 ;
+ RECT 636.530000 594.400000 637.530000 594.880000 ;
+ RECT 636.530000 588.960000 637.530000 589.440000 ;
+ RECT 627.220000 578.080000 628.320000 578.560000 ;
+ RECT 627.220000 572.640000 628.320000 573.120000 ;
+ RECT 636.530000 578.080000 637.530000 578.560000 ;
+ RECT 636.530000 572.640000 637.530000 573.120000 ;
+ RECT 627.220000 583.520000 628.320000 584.000000 ;
+ RECT 636.530000 583.520000 637.530000 584.000000 ;
+ RECT 636.530000 561.760000 637.530000 562.240000 ;
+ RECT 636.530000 567.200000 637.530000 567.680000 ;
+ RECT 627.220000 567.200000 628.320000 567.680000 ;
+ RECT 627.220000 561.760000 628.320000 562.240000 ;
+ RECT 627.220000 556.320000 628.320000 556.800000 ;
+ RECT 627.220000 550.880000 628.320000 551.360000 ;
+ RECT 636.530000 556.320000 637.530000 556.800000 ;
+ RECT 636.530000 550.880000 637.530000 551.360000 ;
+ RECT 582.220000 594.400000 583.320000 594.880000 ;
+ RECT 582.220000 588.960000 583.320000 589.440000 ;
+ RECT 582.220000 583.520000 583.320000 584.000000 ;
+ RECT 582.220000 578.080000 583.320000 578.560000 ;
+ RECT 582.220000 572.640000 583.320000 573.120000 ;
+ RECT 582.220000 567.200000 583.320000 567.680000 ;
+ RECT 582.220000 561.760000 583.320000 562.240000 ;
+ RECT 582.220000 556.320000 583.320000 556.800000 ;
+ RECT 582.220000 550.880000 583.320000 551.360000 ;
+ RECT 537.220000 643.360000 538.320000 643.840000 ;
+ RECT 537.220000 637.920000 538.320000 638.400000 ;
+ RECT 537.220000 632.480000 538.320000 632.960000 ;
+ RECT 537.220000 627.040000 538.320000 627.520000 ;
+ RECT 537.220000 621.600000 538.320000 622.080000 ;
+ RECT 492.220000 643.360000 493.320000 643.840000 ;
+ RECT 492.220000 637.920000 493.320000 638.400000 ;
+ RECT 492.220000 632.480000 493.320000 632.960000 ;
+ RECT 492.220000 627.040000 493.320000 627.520000 ;
+ RECT 492.220000 621.600000 493.320000 622.080000 ;
+ RECT 537.220000 616.160000 538.320000 616.640000 ;
+ RECT 537.220000 610.720000 538.320000 611.200000 ;
+ RECT 537.220000 605.280000 538.320000 605.760000 ;
+ RECT 537.220000 599.840000 538.320000 600.320000 ;
+ RECT 492.220000 610.720000 493.320000 611.200000 ;
+ RECT 492.220000 605.280000 493.320000 605.760000 ;
+ RECT 492.220000 599.840000 493.320000 600.320000 ;
+ RECT 492.220000 616.160000 493.320000 616.640000 ;
+ RECT 447.220000 643.360000 448.320000 643.840000 ;
+ RECT 443.090000 643.360000 444.090000 643.840000 ;
+ RECT 447.220000 637.920000 448.320000 638.400000 ;
+ RECT 443.090000 637.920000 444.090000 638.400000 ;
+ RECT 447.220000 632.480000 448.320000 632.960000 ;
+ RECT 443.090000 632.480000 444.090000 632.960000 ;
+ RECT 447.220000 621.600000 448.320000 622.080000 ;
+ RECT 443.090000 621.600000 444.090000 622.080000 ;
+ RECT 443.090000 627.040000 444.090000 627.520000 ;
+ RECT 447.220000 627.040000 448.320000 627.520000 ;
+ RECT 447.220000 616.160000 448.320000 616.640000 ;
+ RECT 443.090000 616.160000 444.090000 616.640000 ;
+ RECT 447.220000 610.720000 448.320000 611.200000 ;
+ RECT 443.090000 610.720000 444.090000 611.200000 ;
+ RECT 447.220000 605.280000 448.320000 605.760000 ;
+ RECT 443.090000 605.280000 444.090000 605.760000 ;
+ RECT 447.220000 599.840000 448.320000 600.320000 ;
+ RECT 443.090000 599.840000 444.090000 600.320000 ;
+ RECT 537.220000 594.400000 538.320000 594.880000 ;
+ RECT 537.220000 588.960000 538.320000 589.440000 ;
+ RECT 537.220000 583.520000 538.320000 584.000000 ;
+ RECT 537.220000 578.080000 538.320000 578.560000 ;
+ RECT 537.220000 572.640000 538.320000 573.120000 ;
+ RECT 492.220000 594.400000 493.320000 594.880000 ;
+ RECT 492.220000 588.960000 493.320000 589.440000 ;
+ RECT 492.220000 583.520000 493.320000 584.000000 ;
+ RECT 492.220000 578.080000 493.320000 578.560000 ;
+ RECT 492.220000 572.640000 493.320000 573.120000 ;
+ RECT 537.220000 550.880000 538.320000 551.360000 ;
+ RECT 537.220000 556.320000 538.320000 556.800000 ;
+ RECT 537.220000 561.760000 538.320000 562.240000 ;
+ RECT 537.220000 567.200000 538.320000 567.680000 ;
+ RECT 492.220000 550.880000 493.320000 551.360000 ;
+ RECT 492.220000 556.320000 493.320000 556.800000 ;
+ RECT 492.220000 561.760000 493.320000 562.240000 ;
+ RECT 492.220000 567.200000 493.320000 567.680000 ;
+ RECT 447.220000 594.400000 448.320000 594.880000 ;
+ RECT 443.090000 594.400000 444.090000 594.880000 ;
+ RECT 447.220000 588.960000 448.320000 589.440000 ;
+ RECT 443.090000 588.960000 444.090000 589.440000 ;
+ RECT 447.220000 578.080000 448.320000 578.560000 ;
+ RECT 443.090000 578.080000 444.090000 578.560000 ;
+ RECT 447.220000 572.640000 448.320000 573.120000 ;
+ RECT 443.090000 572.640000 444.090000 573.120000 ;
+ RECT 447.220000 583.520000 448.320000 584.000000 ;
+ RECT 443.090000 583.520000 444.090000 584.000000 ;
+ RECT 447.220000 567.200000 448.320000 567.680000 ;
+ RECT 443.090000 567.200000 444.090000 567.680000 ;
+ RECT 447.220000 561.760000 448.320000 562.240000 ;
+ RECT 443.090000 561.760000 444.090000 562.240000 ;
+ RECT 447.220000 556.320000 448.320000 556.800000 ;
+ RECT 447.220000 550.880000 448.320000 551.360000 ;
+ RECT 443.090000 556.320000 444.090000 556.800000 ;
+ RECT 443.090000 550.880000 444.090000 551.360000 ;
+ RECT 440.260000 741.240000 640.360000 742.240000 ;
+ RECT 440.260000 548.870000 640.360000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 546.020000 444.090000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 745.280000 444.090000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 546.020000 637.530000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 745.280000 637.530000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 548.870000 441.260000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 548.870000 640.360000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 741.240000 441.260000 742.240000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 741.240000 640.360000 742.240000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 348.610000 628.320000 541.980000 ;
+ RECT 582.220000 348.610000 583.320000 541.980000 ;
+ RECT 636.530000 345.760000 637.530000 546.020000 ;
+ RECT 537.220000 348.610000 538.320000 541.980000 ;
+ RECT 492.220000 348.610000 493.320000 541.980000 ;
+ RECT 447.220000 348.610000 448.320000 541.980000 ;
+ RECT 443.090000 345.760000 444.090000 546.020000 ;
+ LAYER met3 ;
+ RECT 627.220000 535.580000 628.320000 536.060000 ;
+ RECT 636.530000 535.580000 637.530000 536.060000 ;
+ RECT 636.530000 524.700000 637.530000 525.180000 ;
+ RECT 636.530000 530.140000 637.530000 530.620000 ;
+ RECT 627.220000 530.140000 628.320000 530.620000 ;
+ RECT 627.220000 524.700000 628.320000 525.180000 ;
+ RECT 627.220000 519.260000 628.320000 519.740000 ;
+ RECT 627.220000 513.820000 628.320000 514.300000 ;
+ RECT 636.530000 519.260000 637.530000 519.740000 ;
+ RECT 636.530000 513.820000 637.530000 514.300000 ;
+ RECT 627.220000 497.500000 628.320000 497.980000 ;
+ RECT 627.220000 502.940000 628.320000 503.420000 ;
+ RECT 636.530000 502.940000 637.530000 503.420000 ;
+ RECT 636.530000 497.500000 637.530000 497.980000 ;
+ RECT 627.220000 508.380000 628.320000 508.860000 ;
+ RECT 636.530000 508.380000 637.530000 508.860000 ;
+ RECT 582.220000 535.580000 583.320000 536.060000 ;
+ RECT 582.220000 530.140000 583.320000 530.620000 ;
+ RECT 582.220000 524.700000 583.320000 525.180000 ;
+ RECT 582.220000 519.260000 583.320000 519.740000 ;
+ RECT 582.220000 497.500000 583.320000 497.980000 ;
+ RECT 582.220000 502.940000 583.320000 503.420000 ;
+ RECT 582.220000 508.380000 583.320000 508.860000 ;
+ RECT 582.220000 513.820000 583.320000 514.300000 ;
+ RECT 636.530000 486.620000 637.530000 487.100000 ;
+ RECT 636.530000 492.060000 637.530000 492.540000 ;
+ RECT 627.220000 492.060000 628.320000 492.540000 ;
+ RECT 627.220000 486.620000 628.320000 487.100000 ;
+ RECT 627.220000 481.180000 628.320000 481.660000 ;
+ RECT 627.220000 475.740000 628.320000 476.220000 ;
+ RECT 636.530000 481.180000 637.530000 481.660000 ;
+ RECT 636.530000 475.740000 637.530000 476.220000 ;
+ RECT 636.530000 459.420000 637.530000 459.900000 ;
+ RECT 636.530000 464.860000 637.530000 465.340000 ;
+ RECT 636.530000 470.300000 637.530000 470.780000 ;
+ RECT 627.220000 464.860000 628.320000 465.340000 ;
+ RECT 627.220000 459.420000 628.320000 459.900000 ;
+ RECT 627.220000 470.300000 628.320000 470.780000 ;
+ RECT 627.220000 453.980000 628.320000 454.460000 ;
+ RECT 627.220000 448.540000 628.320000 449.020000 ;
+ RECT 636.530000 453.980000 637.530000 454.460000 ;
+ RECT 636.530000 448.540000 637.530000 449.020000 ;
+ RECT 582.220000 492.060000 583.320000 492.540000 ;
+ RECT 582.220000 486.620000 583.320000 487.100000 ;
+ RECT 582.220000 481.180000 583.320000 481.660000 ;
+ RECT 582.220000 475.740000 583.320000 476.220000 ;
+ RECT 582.220000 464.860000 583.320000 465.340000 ;
+ RECT 582.220000 459.420000 583.320000 459.900000 ;
+ RECT 582.220000 453.980000 583.320000 454.460000 ;
+ RECT 582.220000 448.540000 583.320000 449.020000 ;
+ RECT 582.220000 470.300000 583.320000 470.780000 ;
+ RECT 537.220000 535.580000 538.320000 536.060000 ;
+ RECT 537.220000 530.140000 538.320000 530.620000 ;
+ RECT 537.220000 524.700000 538.320000 525.180000 ;
+ RECT 492.220000 535.580000 493.320000 536.060000 ;
+ RECT 492.220000 530.140000 493.320000 530.620000 ;
+ RECT 492.220000 524.700000 493.320000 525.180000 ;
+ RECT 537.220000 508.380000 538.320000 508.860000 ;
+ RECT 537.220000 502.940000 538.320000 503.420000 ;
+ RECT 537.220000 497.500000 538.320000 497.980000 ;
+ RECT 537.220000 513.820000 538.320000 514.300000 ;
+ RECT 537.220000 519.260000 538.320000 519.740000 ;
+ RECT 492.220000 519.260000 493.320000 519.740000 ;
+ RECT 492.220000 508.380000 493.320000 508.860000 ;
+ RECT 492.220000 502.940000 493.320000 503.420000 ;
+ RECT 492.220000 497.500000 493.320000 497.980000 ;
+ RECT 492.220000 513.820000 493.320000 514.300000 ;
+ RECT 447.220000 535.580000 448.320000 536.060000 ;
+ RECT 443.090000 535.580000 444.090000 536.060000 ;
+ RECT 443.090000 530.140000 444.090000 530.620000 ;
+ RECT 447.220000 530.140000 448.320000 530.620000 ;
+ RECT 447.220000 524.700000 448.320000 525.180000 ;
+ RECT 443.090000 524.700000 444.090000 525.180000 ;
+ RECT 447.220000 519.260000 448.320000 519.740000 ;
+ RECT 443.090000 519.260000 444.090000 519.740000 ;
+ RECT 447.220000 513.820000 448.320000 514.300000 ;
+ RECT 443.090000 513.820000 444.090000 514.300000 ;
+ RECT 447.220000 502.940000 448.320000 503.420000 ;
+ RECT 443.090000 502.940000 444.090000 503.420000 ;
+ RECT 447.220000 497.500000 448.320000 497.980000 ;
+ RECT 443.090000 497.500000 444.090000 497.980000 ;
+ RECT 447.220000 508.380000 448.320000 508.860000 ;
+ RECT 443.090000 508.380000 444.090000 508.860000 ;
+ RECT 537.220000 492.060000 538.320000 492.540000 ;
+ RECT 537.220000 486.620000 538.320000 487.100000 ;
+ RECT 537.220000 481.180000 538.320000 481.660000 ;
+ RECT 537.220000 475.740000 538.320000 476.220000 ;
+ RECT 492.220000 492.060000 493.320000 492.540000 ;
+ RECT 492.220000 486.620000 493.320000 487.100000 ;
+ RECT 492.220000 481.180000 493.320000 481.660000 ;
+ RECT 492.220000 475.740000 493.320000 476.220000 ;
+ RECT 537.220000 464.860000 538.320000 465.340000 ;
+ RECT 537.220000 448.540000 538.320000 449.020000 ;
+ RECT 537.220000 453.980000 538.320000 454.460000 ;
+ RECT 537.220000 459.420000 538.320000 459.900000 ;
+ RECT 537.220000 470.300000 538.320000 470.780000 ;
+ RECT 492.220000 448.540000 493.320000 449.020000 ;
+ RECT 492.220000 453.980000 493.320000 454.460000 ;
+ RECT 492.220000 459.420000 493.320000 459.900000 ;
+ RECT 492.220000 464.860000 493.320000 465.340000 ;
+ RECT 492.220000 470.300000 493.320000 470.780000 ;
+ RECT 447.220000 492.060000 448.320000 492.540000 ;
+ RECT 443.090000 492.060000 444.090000 492.540000 ;
+ RECT 447.220000 486.620000 448.320000 487.100000 ;
+ RECT 443.090000 486.620000 444.090000 487.100000 ;
+ RECT 447.220000 481.180000 448.320000 481.660000 ;
+ RECT 443.090000 481.180000 444.090000 481.660000 ;
+ RECT 447.220000 475.740000 448.320000 476.220000 ;
+ RECT 443.090000 475.740000 444.090000 476.220000 ;
+ RECT 447.220000 470.300000 448.320000 470.780000 ;
+ RECT 447.220000 464.860000 448.320000 465.340000 ;
+ RECT 443.090000 470.300000 444.090000 470.780000 ;
+ RECT 443.090000 464.860000 444.090000 465.340000 ;
+ RECT 447.220000 459.420000 448.320000 459.900000 ;
+ RECT 443.090000 459.420000 444.090000 459.900000 ;
+ RECT 447.220000 453.980000 448.320000 454.460000 ;
+ RECT 443.090000 453.980000 444.090000 454.460000 ;
+ RECT 447.220000 448.540000 448.320000 449.020000 ;
+ RECT 443.090000 448.540000 444.090000 449.020000 ;
+ RECT 627.220000 443.100000 628.320000 443.580000 ;
+ RECT 627.220000 437.660000 628.320000 438.140000 ;
+ RECT 636.530000 443.100000 637.530000 443.580000 ;
+ RECT 636.530000 437.660000 637.530000 438.140000 ;
+ RECT 636.530000 421.340000 637.530000 421.820000 ;
+ RECT 636.530000 426.780000 637.530000 427.260000 ;
+ RECT 636.530000 432.220000 637.530000 432.700000 ;
+ RECT 627.220000 432.220000 628.320000 432.700000 ;
+ RECT 627.220000 426.780000 628.320000 427.260000 ;
+ RECT 627.220000 421.340000 628.320000 421.820000 ;
+ RECT 627.220000 410.460000 628.320000 410.940000 ;
+ RECT 627.220000 415.900000 628.320000 416.380000 ;
+ RECT 636.530000 415.900000 637.530000 416.380000 ;
+ RECT 636.530000 410.460000 637.530000 410.940000 ;
+ RECT 636.530000 399.580000 637.530000 400.060000 ;
+ RECT 636.530000 405.020000 637.530000 405.500000 ;
+ RECT 627.220000 399.580000 628.320000 400.060000 ;
+ RECT 627.220000 405.020000 628.320000 405.500000 ;
+ RECT 582.220000 443.100000 583.320000 443.580000 ;
+ RECT 582.220000 437.660000 583.320000 438.140000 ;
+ RECT 582.220000 432.220000 583.320000 432.700000 ;
+ RECT 582.220000 426.780000 583.320000 427.260000 ;
+ RECT 582.220000 421.340000 583.320000 421.820000 ;
+ RECT 582.220000 399.580000 583.320000 400.060000 ;
+ RECT 582.220000 405.020000 583.320000 405.500000 ;
+ RECT 582.220000 410.460000 583.320000 410.940000 ;
+ RECT 582.220000 415.900000 583.320000 416.380000 ;
+ RECT 627.220000 394.140000 628.320000 394.620000 ;
+ RECT 627.220000 388.700000 628.320000 389.180000 ;
+ RECT 636.530000 394.140000 637.530000 394.620000 ;
+ RECT 636.530000 388.700000 637.530000 389.180000 ;
+ RECT 627.220000 377.820000 628.320000 378.300000 ;
+ RECT 627.220000 372.380000 628.320000 372.860000 ;
+ RECT 636.530000 377.820000 637.530000 378.300000 ;
+ RECT 636.530000 372.380000 637.530000 372.860000 ;
+ RECT 627.220000 383.260000 628.320000 383.740000 ;
+ RECT 636.530000 383.260000 637.530000 383.740000 ;
+ RECT 636.530000 361.500000 637.530000 361.980000 ;
+ RECT 636.530000 366.940000 637.530000 367.420000 ;
+ RECT 627.220000 366.940000 628.320000 367.420000 ;
+ RECT 627.220000 361.500000 628.320000 361.980000 ;
+ RECT 627.220000 356.060000 628.320000 356.540000 ;
+ RECT 627.220000 350.620000 628.320000 351.100000 ;
+ RECT 636.530000 356.060000 637.530000 356.540000 ;
+ RECT 636.530000 350.620000 637.530000 351.100000 ;
+ RECT 582.220000 394.140000 583.320000 394.620000 ;
+ RECT 582.220000 388.700000 583.320000 389.180000 ;
+ RECT 582.220000 383.260000 583.320000 383.740000 ;
+ RECT 582.220000 377.820000 583.320000 378.300000 ;
+ RECT 582.220000 372.380000 583.320000 372.860000 ;
+ RECT 582.220000 366.940000 583.320000 367.420000 ;
+ RECT 582.220000 361.500000 583.320000 361.980000 ;
+ RECT 582.220000 356.060000 583.320000 356.540000 ;
+ RECT 582.220000 350.620000 583.320000 351.100000 ;
+ RECT 537.220000 443.100000 538.320000 443.580000 ;
+ RECT 537.220000 437.660000 538.320000 438.140000 ;
+ RECT 537.220000 432.220000 538.320000 432.700000 ;
+ RECT 537.220000 426.780000 538.320000 427.260000 ;
+ RECT 537.220000 421.340000 538.320000 421.820000 ;
+ RECT 492.220000 443.100000 493.320000 443.580000 ;
+ RECT 492.220000 437.660000 493.320000 438.140000 ;
+ RECT 492.220000 432.220000 493.320000 432.700000 ;
+ RECT 492.220000 426.780000 493.320000 427.260000 ;
+ RECT 492.220000 421.340000 493.320000 421.820000 ;
+ RECT 537.220000 415.900000 538.320000 416.380000 ;
+ RECT 537.220000 410.460000 538.320000 410.940000 ;
+ RECT 537.220000 405.020000 538.320000 405.500000 ;
+ RECT 537.220000 399.580000 538.320000 400.060000 ;
+ RECT 492.220000 410.460000 493.320000 410.940000 ;
+ RECT 492.220000 405.020000 493.320000 405.500000 ;
+ RECT 492.220000 399.580000 493.320000 400.060000 ;
+ RECT 492.220000 415.900000 493.320000 416.380000 ;
+ RECT 447.220000 443.100000 448.320000 443.580000 ;
+ RECT 443.090000 443.100000 444.090000 443.580000 ;
+ RECT 447.220000 437.660000 448.320000 438.140000 ;
+ RECT 443.090000 437.660000 444.090000 438.140000 ;
+ RECT 447.220000 432.220000 448.320000 432.700000 ;
+ RECT 443.090000 432.220000 444.090000 432.700000 ;
+ RECT 447.220000 421.340000 448.320000 421.820000 ;
+ RECT 443.090000 421.340000 444.090000 421.820000 ;
+ RECT 443.090000 426.780000 444.090000 427.260000 ;
+ RECT 447.220000 426.780000 448.320000 427.260000 ;
+ RECT 447.220000 415.900000 448.320000 416.380000 ;
+ RECT 443.090000 415.900000 444.090000 416.380000 ;
+ RECT 447.220000 410.460000 448.320000 410.940000 ;
+ RECT 443.090000 410.460000 444.090000 410.940000 ;
+ RECT 447.220000 405.020000 448.320000 405.500000 ;
+ RECT 443.090000 405.020000 444.090000 405.500000 ;
+ RECT 447.220000 399.580000 448.320000 400.060000 ;
+ RECT 443.090000 399.580000 444.090000 400.060000 ;
+ RECT 537.220000 394.140000 538.320000 394.620000 ;
+ RECT 537.220000 388.700000 538.320000 389.180000 ;
+ RECT 537.220000 383.260000 538.320000 383.740000 ;
+ RECT 537.220000 377.820000 538.320000 378.300000 ;
+ RECT 537.220000 372.380000 538.320000 372.860000 ;
+ RECT 492.220000 394.140000 493.320000 394.620000 ;
+ RECT 492.220000 388.700000 493.320000 389.180000 ;
+ RECT 492.220000 383.260000 493.320000 383.740000 ;
+ RECT 492.220000 377.820000 493.320000 378.300000 ;
+ RECT 492.220000 372.380000 493.320000 372.860000 ;
+ RECT 537.220000 350.620000 538.320000 351.100000 ;
+ RECT 537.220000 356.060000 538.320000 356.540000 ;
+ RECT 537.220000 361.500000 538.320000 361.980000 ;
+ RECT 537.220000 366.940000 538.320000 367.420000 ;
+ RECT 492.220000 350.620000 493.320000 351.100000 ;
+ RECT 492.220000 356.060000 493.320000 356.540000 ;
+ RECT 492.220000 361.500000 493.320000 361.980000 ;
+ RECT 492.220000 366.940000 493.320000 367.420000 ;
+ RECT 447.220000 394.140000 448.320000 394.620000 ;
+ RECT 443.090000 394.140000 444.090000 394.620000 ;
+ RECT 447.220000 388.700000 448.320000 389.180000 ;
+ RECT 443.090000 388.700000 444.090000 389.180000 ;
+ RECT 447.220000 377.820000 448.320000 378.300000 ;
+ RECT 443.090000 377.820000 444.090000 378.300000 ;
+ RECT 447.220000 372.380000 448.320000 372.860000 ;
+ RECT 443.090000 372.380000 444.090000 372.860000 ;
+ RECT 447.220000 383.260000 448.320000 383.740000 ;
+ RECT 443.090000 383.260000 444.090000 383.740000 ;
+ RECT 447.220000 366.940000 448.320000 367.420000 ;
+ RECT 443.090000 366.940000 444.090000 367.420000 ;
+ RECT 447.220000 361.500000 448.320000 361.980000 ;
+ RECT 443.090000 361.500000 444.090000 361.980000 ;
+ RECT 447.220000 356.060000 448.320000 356.540000 ;
+ RECT 447.220000 350.620000 448.320000 351.100000 ;
+ RECT 443.090000 356.060000 444.090000 356.540000 ;
+ RECT 443.090000 350.620000 444.090000 351.100000 ;
+ RECT 440.260000 540.980000 640.360000 541.980000 ;
+ RECT 440.260000 348.610000 640.360000 349.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 345.760000 444.090000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 545.020000 444.090000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 345.760000 637.530000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 545.020000 637.530000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 348.610000 441.260000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 348.610000 640.360000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 540.980000 441.260000 541.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 540.980000 640.360000 541.980000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 148.350000 628.320000 341.720000 ;
+ RECT 582.220000 148.350000 583.320000 341.720000 ;
+ RECT 636.530000 145.500000 637.530000 345.760000 ;
+ RECT 537.220000 148.350000 538.320000 341.720000 ;
+ RECT 492.220000 148.350000 493.320000 341.720000 ;
+ RECT 447.220000 148.350000 448.320000 341.720000 ;
+ RECT 443.090000 145.500000 444.090000 345.760000 ;
+ LAYER met3 ;
+ RECT 627.220000 335.320000 628.320000 335.800000 ;
+ RECT 636.530000 335.320000 637.530000 335.800000 ;
+ RECT 636.530000 324.440000 637.530000 324.920000 ;
+ RECT 636.530000 329.880000 637.530000 330.360000 ;
+ RECT 627.220000 329.880000 628.320000 330.360000 ;
+ RECT 627.220000 324.440000 628.320000 324.920000 ;
+ RECT 627.220000 319.000000 628.320000 319.480000 ;
+ RECT 627.220000 313.560000 628.320000 314.040000 ;
+ RECT 636.530000 319.000000 637.530000 319.480000 ;
+ RECT 636.530000 313.560000 637.530000 314.040000 ;
+ RECT 627.220000 297.240000 628.320000 297.720000 ;
+ RECT 627.220000 302.680000 628.320000 303.160000 ;
+ RECT 636.530000 302.680000 637.530000 303.160000 ;
+ RECT 636.530000 297.240000 637.530000 297.720000 ;
+ RECT 627.220000 308.120000 628.320000 308.600000 ;
+ RECT 636.530000 308.120000 637.530000 308.600000 ;
+ RECT 582.220000 335.320000 583.320000 335.800000 ;
+ RECT 582.220000 329.880000 583.320000 330.360000 ;
+ RECT 582.220000 324.440000 583.320000 324.920000 ;
+ RECT 582.220000 319.000000 583.320000 319.480000 ;
+ RECT 582.220000 297.240000 583.320000 297.720000 ;
+ RECT 582.220000 302.680000 583.320000 303.160000 ;
+ RECT 582.220000 308.120000 583.320000 308.600000 ;
+ RECT 582.220000 313.560000 583.320000 314.040000 ;
+ RECT 636.530000 286.360000 637.530000 286.840000 ;
+ RECT 636.530000 291.800000 637.530000 292.280000 ;
+ RECT 627.220000 291.800000 628.320000 292.280000 ;
+ RECT 627.220000 286.360000 628.320000 286.840000 ;
+ RECT 627.220000 280.920000 628.320000 281.400000 ;
+ RECT 627.220000 275.480000 628.320000 275.960000 ;
+ RECT 636.530000 280.920000 637.530000 281.400000 ;
+ RECT 636.530000 275.480000 637.530000 275.960000 ;
+ RECT 636.530000 259.160000 637.530000 259.640000 ;
+ RECT 636.530000 264.600000 637.530000 265.080000 ;
+ RECT 636.530000 270.040000 637.530000 270.520000 ;
+ RECT 627.220000 264.600000 628.320000 265.080000 ;
+ RECT 627.220000 259.160000 628.320000 259.640000 ;
+ RECT 627.220000 270.040000 628.320000 270.520000 ;
+ RECT 627.220000 253.720000 628.320000 254.200000 ;
+ RECT 627.220000 248.280000 628.320000 248.760000 ;
+ RECT 636.530000 253.720000 637.530000 254.200000 ;
+ RECT 636.530000 248.280000 637.530000 248.760000 ;
+ RECT 582.220000 291.800000 583.320000 292.280000 ;
+ RECT 582.220000 286.360000 583.320000 286.840000 ;
+ RECT 582.220000 280.920000 583.320000 281.400000 ;
+ RECT 582.220000 275.480000 583.320000 275.960000 ;
+ RECT 582.220000 264.600000 583.320000 265.080000 ;
+ RECT 582.220000 259.160000 583.320000 259.640000 ;
+ RECT 582.220000 253.720000 583.320000 254.200000 ;
+ RECT 582.220000 248.280000 583.320000 248.760000 ;
+ RECT 582.220000 270.040000 583.320000 270.520000 ;
+ RECT 537.220000 335.320000 538.320000 335.800000 ;
+ RECT 537.220000 329.880000 538.320000 330.360000 ;
+ RECT 537.220000 324.440000 538.320000 324.920000 ;
+ RECT 492.220000 335.320000 493.320000 335.800000 ;
+ RECT 492.220000 329.880000 493.320000 330.360000 ;
+ RECT 492.220000 324.440000 493.320000 324.920000 ;
+ RECT 537.220000 308.120000 538.320000 308.600000 ;
+ RECT 537.220000 302.680000 538.320000 303.160000 ;
+ RECT 537.220000 297.240000 538.320000 297.720000 ;
+ RECT 537.220000 313.560000 538.320000 314.040000 ;
+ RECT 537.220000 319.000000 538.320000 319.480000 ;
+ RECT 492.220000 319.000000 493.320000 319.480000 ;
+ RECT 492.220000 308.120000 493.320000 308.600000 ;
+ RECT 492.220000 302.680000 493.320000 303.160000 ;
+ RECT 492.220000 297.240000 493.320000 297.720000 ;
+ RECT 492.220000 313.560000 493.320000 314.040000 ;
+ RECT 447.220000 335.320000 448.320000 335.800000 ;
+ RECT 443.090000 335.320000 444.090000 335.800000 ;
+ RECT 443.090000 329.880000 444.090000 330.360000 ;
+ RECT 447.220000 329.880000 448.320000 330.360000 ;
+ RECT 447.220000 324.440000 448.320000 324.920000 ;
+ RECT 443.090000 324.440000 444.090000 324.920000 ;
+ RECT 447.220000 319.000000 448.320000 319.480000 ;
+ RECT 443.090000 319.000000 444.090000 319.480000 ;
+ RECT 447.220000 313.560000 448.320000 314.040000 ;
+ RECT 443.090000 313.560000 444.090000 314.040000 ;
+ RECT 447.220000 302.680000 448.320000 303.160000 ;
+ RECT 443.090000 302.680000 444.090000 303.160000 ;
+ RECT 447.220000 297.240000 448.320000 297.720000 ;
+ RECT 443.090000 297.240000 444.090000 297.720000 ;
+ RECT 447.220000 308.120000 448.320000 308.600000 ;
+ RECT 443.090000 308.120000 444.090000 308.600000 ;
+ RECT 537.220000 291.800000 538.320000 292.280000 ;
+ RECT 537.220000 286.360000 538.320000 286.840000 ;
+ RECT 537.220000 280.920000 538.320000 281.400000 ;
+ RECT 537.220000 275.480000 538.320000 275.960000 ;
+ RECT 492.220000 291.800000 493.320000 292.280000 ;
+ RECT 492.220000 286.360000 493.320000 286.840000 ;
+ RECT 492.220000 280.920000 493.320000 281.400000 ;
+ RECT 492.220000 275.480000 493.320000 275.960000 ;
+ RECT 537.220000 264.600000 538.320000 265.080000 ;
+ RECT 537.220000 248.280000 538.320000 248.760000 ;
+ RECT 537.220000 253.720000 538.320000 254.200000 ;
+ RECT 537.220000 259.160000 538.320000 259.640000 ;
+ RECT 537.220000 270.040000 538.320000 270.520000 ;
+ RECT 492.220000 248.280000 493.320000 248.760000 ;
+ RECT 492.220000 253.720000 493.320000 254.200000 ;
+ RECT 492.220000 259.160000 493.320000 259.640000 ;
+ RECT 492.220000 264.600000 493.320000 265.080000 ;
+ RECT 492.220000 270.040000 493.320000 270.520000 ;
+ RECT 447.220000 291.800000 448.320000 292.280000 ;
+ RECT 443.090000 291.800000 444.090000 292.280000 ;
+ RECT 447.220000 286.360000 448.320000 286.840000 ;
+ RECT 443.090000 286.360000 444.090000 286.840000 ;
+ RECT 447.220000 280.920000 448.320000 281.400000 ;
+ RECT 443.090000 280.920000 444.090000 281.400000 ;
+ RECT 447.220000 275.480000 448.320000 275.960000 ;
+ RECT 443.090000 275.480000 444.090000 275.960000 ;
+ RECT 447.220000 270.040000 448.320000 270.520000 ;
+ RECT 447.220000 264.600000 448.320000 265.080000 ;
+ RECT 443.090000 270.040000 444.090000 270.520000 ;
+ RECT 443.090000 264.600000 444.090000 265.080000 ;
+ RECT 447.220000 259.160000 448.320000 259.640000 ;
+ RECT 443.090000 259.160000 444.090000 259.640000 ;
+ RECT 447.220000 253.720000 448.320000 254.200000 ;
+ RECT 443.090000 253.720000 444.090000 254.200000 ;
+ RECT 447.220000 248.280000 448.320000 248.760000 ;
+ RECT 443.090000 248.280000 444.090000 248.760000 ;
+ RECT 627.220000 242.840000 628.320000 243.320000 ;
+ RECT 627.220000 237.400000 628.320000 237.880000 ;
+ RECT 636.530000 242.840000 637.530000 243.320000 ;
+ RECT 636.530000 237.400000 637.530000 237.880000 ;
+ RECT 636.530000 221.080000 637.530000 221.560000 ;
+ RECT 636.530000 226.520000 637.530000 227.000000 ;
+ RECT 636.530000 231.960000 637.530000 232.440000 ;
+ RECT 627.220000 231.960000 628.320000 232.440000 ;
+ RECT 627.220000 226.520000 628.320000 227.000000 ;
+ RECT 627.220000 221.080000 628.320000 221.560000 ;
+ RECT 627.220000 210.200000 628.320000 210.680000 ;
+ RECT 627.220000 215.640000 628.320000 216.120000 ;
+ RECT 636.530000 215.640000 637.530000 216.120000 ;
+ RECT 636.530000 210.200000 637.530000 210.680000 ;
+ RECT 636.530000 199.320000 637.530000 199.800000 ;
+ RECT 636.530000 204.760000 637.530000 205.240000 ;
+ RECT 627.220000 199.320000 628.320000 199.800000 ;
+ RECT 627.220000 204.760000 628.320000 205.240000 ;
+ RECT 582.220000 242.840000 583.320000 243.320000 ;
+ RECT 582.220000 237.400000 583.320000 237.880000 ;
+ RECT 582.220000 231.960000 583.320000 232.440000 ;
+ RECT 582.220000 226.520000 583.320000 227.000000 ;
+ RECT 582.220000 221.080000 583.320000 221.560000 ;
+ RECT 582.220000 199.320000 583.320000 199.800000 ;
+ RECT 582.220000 204.760000 583.320000 205.240000 ;
+ RECT 582.220000 210.200000 583.320000 210.680000 ;
+ RECT 582.220000 215.640000 583.320000 216.120000 ;
+ RECT 627.220000 193.880000 628.320000 194.360000 ;
+ RECT 627.220000 188.440000 628.320000 188.920000 ;
+ RECT 636.530000 193.880000 637.530000 194.360000 ;
+ RECT 636.530000 188.440000 637.530000 188.920000 ;
+ RECT 627.220000 177.560000 628.320000 178.040000 ;
+ RECT 627.220000 172.120000 628.320000 172.600000 ;
+ RECT 636.530000 177.560000 637.530000 178.040000 ;
+ RECT 636.530000 172.120000 637.530000 172.600000 ;
+ RECT 627.220000 183.000000 628.320000 183.480000 ;
+ RECT 636.530000 183.000000 637.530000 183.480000 ;
+ RECT 636.530000 161.240000 637.530000 161.720000 ;
+ RECT 636.530000 166.680000 637.530000 167.160000 ;
+ RECT 627.220000 166.680000 628.320000 167.160000 ;
+ RECT 627.220000 161.240000 628.320000 161.720000 ;
+ RECT 627.220000 155.800000 628.320000 156.280000 ;
+ RECT 627.220000 150.360000 628.320000 150.840000 ;
+ RECT 636.530000 155.800000 637.530000 156.280000 ;
+ RECT 636.530000 150.360000 637.530000 150.840000 ;
+ RECT 582.220000 193.880000 583.320000 194.360000 ;
+ RECT 582.220000 188.440000 583.320000 188.920000 ;
+ RECT 582.220000 183.000000 583.320000 183.480000 ;
+ RECT 582.220000 177.560000 583.320000 178.040000 ;
+ RECT 582.220000 172.120000 583.320000 172.600000 ;
+ RECT 582.220000 166.680000 583.320000 167.160000 ;
+ RECT 582.220000 161.240000 583.320000 161.720000 ;
+ RECT 582.220000 155.800000 583.320000 156.280000 ;
+ RECT 582.220000 150.360000 583.320000 150.840000 ;
+ RECT 537.220000 242.840000 538.320000 243.320000 ;
+ RECT 537.220000 237.400000 538.320000 237.880000 ;
+ RECT 537.220000 231.960000 538.320000 232.440000 ;
+ RECT 537.220000 226.520000 538.320000 227.000000 ;
+ RECT 537.220000 221.080000 538.320000 221.560000 ;
+ RECT 492.220000 242.840000 493.320000 243.320000 ;
+ RECT 492.220000 237.400000 493.320000 237.880000 ;
+ RECT 492.220000 231.960000 493.320000 232.440000 ;
+ RECT 492.220000 226.520000 493.320000 227.000000 ;
+ RECT 492.220000 221.080000 493.320000 221.560000 ;
+ RECT 537.220000 215.640000 538.320000 216.120000 ;
+ RECT 537.220000 210.200000 538.320000 210.680000 ;
+ RECT 537.220000 204.760000 538.320000 205.240000 ;
+ RECT 537.220000 199.320000 538.320000 199.800000 ;
+ RECT 492.220000 210.200000 493.320000 210.680000 ;
+ RECT 492.220000 204.760000 493.320000 205.240000 ;
+ RECT 492.220000 199.320000 493.320000 199.800000 ;
+ RECT 492.220000 215.640000 493.320000 216.120000 ;
+ RECT 447.220000 242.840000 448.320000 243.320000 ;
+ RECT 443.090000 242.840000 444.090000 243.320000 ;
+ RECT 447.220000 237.400000 448.320000 237.880000 ;
+ RECT 443.090000 237.400000 444.090000 237.880000 ;
+ RECT 447.220000 231.960000 448.320000 232.440000 ;
+ RECT 443.090000 231.960000 444.090000 232.440000 ;
+ RECT 447.220000 221.080000 448.320000 221.560000 ;
+ RECT 443.090000 221.080000 444.090000 221.560000 ;
+ RECT 443.090000 226.520000 444.090000 227.000000 ;
+ RECT 447.220000 226.520000 448.320000 227.000000 ;
+ RECT 447.220000 215.640000 448.320000 216.120000 ;
+ RECT 443.090000 215.640000 444.090000 216.120000 ;
+ RECT 447.220000 210.200000 448.320000 210.680000 ;
+ RECT 443.090000 210.200000 444.090000 210.680000 ;
+ RECT 447.220000 204.760000 448.320000 205.240000 ;
+ RECT 443.090000 204.760000 444.090000 205.240000 ;
+ RECT 447.220000 199.320000 448.320000 199.800000 ;
+ RECT 443.090000 199.320000 444.090000 199.800000 ;
+ RECT 537.220000 193.880000 538.320000 194.360000 ;
+ RECT 537.220000 188.440000 538.320000 188.920000 ;
+ RECT 537.220000 183.000000 538.320000 183.480000 ;
+ RECT 537.220000 177.560000 538.320000 178.040000 ;
+ RECT 537.220000 172.120000 538.320000 172.600000 ;
+ RECT 492.220000 193.880000 493.320000 194.360000 ;
+ RECT 492.220000 188.440000 493.320000 188.920000 ;
+ RECT 492.220000 183.000000 493.320000 183.480000 ;
+ RECT 492.220000 177.560000 493.320000 178.040000 ;
+ RECT 492.220000 172.120000 493.320000 172.600000 ;
+ RECT 537.220000 150.360000 538.320000 150.840000 ;
+ RECT 537.220000 155.800000 538.320000 156.280000 ;
+ RECT 537.220000 161.240000 538.320000 161.720000 ;
+ RECT 537.220000 166.680000 538.320000 167.160000 ;
+ RECT 492.220000 150.360000 493.320000 150.840000 ;
+ RECT 492.220000 155.800000 493.320000 156.280000 ;
+ RECT 492.220000 161.240000 493.320000 161.720000 ;
+ RECT 492.220000 166.680000 493.320000 167.160000 ;
+ RECT 447.220000 193.880000 448.320000 194.360000 ;
+ RECT 443.090000 193.880000 444.090000 194.360000 ;
+ RECT 447.220000 188.440000 448.320000 188.920000 ;
+ RECT 443.090000 188.440000 444.090000 188.920000 ;
+ RECT 447.220000 177.560000 448.320000 178.040000 ;
+ RECT 443.090000 177.560000 444.090000 178.040000 ;
+ RECT 447.220000 172.120000 448.320000 172.600000 ;
+ RECT 443.090000 172.120000 444.090000 172.600000 ;
+ RECT 447.220000 183.000000 448.320000 183.480000 ;
+ RECT 443.090000 183.000000 444.090000 183.480000 ;
+ RECT 447.220000 166.680000 448.320000 167.160000 ;
+ RECT 443.090000 166.680000 444.090000 167.160000 ;
+ RECT 447.220000 161.240000 448.320000 161.720000 ;
+ RECT 443.090000 161.240000 444.090000 161.720000 ;
+ RECT 447.220000 155.800000 448.320000 156.280000 ;
+ RECT 447.220000 150.360000 448.320000 150.840000 ;
+ RECT 443.090000 155.800000 444.090000 156.280000 ;
+ RECT 443.090000 150.360000 444.090000 150.840000 ;
+ RECT 440.260000 340.720000 640.360000 341.720000 ;
+ RECT 440.260000 148.350000 640.360000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 145.500000 444.090000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 344.760000 444.090000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 145.500000 637.530000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 344.760000 637.530000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 148.350000 441.260000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 148.350000 640.360000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 340.720000 441.260000 341.720000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 340.720000 640.360000 341.720000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 115.240000 444.090000 145.500000 ;
+ RECT 636.530000 115.240000 637.530000 145.500000 ;
+ RECT 447.220000 118.090000 448.320000 142.140000 ;
+ RECT 492.220000 118.090000 493.320000 142.140000 ;
+ RECT 537.220000 118.090000 538.320000 142.140000 ;
+ RECT 582.220000 118.090000 583.320000 142.140000 ;
+ RECT 627.220000 118.090000 628.320000 142.140000 ;
+ LAYER met3 ;
+ RECT 636.530000 130.980000 637.530000 131.460000 ;
+ RECT 636.530000 136.420000 637.530000 136.900000 ;
+ RECT 627.220000 136.420000 628.320000 136.900000 ;
+ RECT 627.220000 130.980000 628.320000 131.460000 ;
+ RECT 582.220000 130.980000 583.320000 131.460000 ;
+ RECT 582.220000 136.420000 583.320000 136.900000 ;
+ RECT 492.220000 130.980000 493.320000 131.460000 ;
+ RECT 537.220000 130.980000 538.320000 131.460000 ;
+ RECT 537.220000 136.420000 538.320000 136.900000 ;
+ RECT 492.220000 136.420000 493.320000 136.900000 ;
+ RECT 443.090000 130.980000 444.090000 131.460000 ;
+ RECT 447.220000 130.980000 448.320000 131.460000 ;
+ RECT 447.220000 136.420000 448.320000 136.900000 ;
+ RECT 443.090000 136.420000 444.090000 136.900000 ;
+ RECT 636.530000 120.100000 637.530000 120.580000 ;
+ RECT 636.530000 125.540000 637.530000 126.020000 ;
+ RECT 627.220000 125.540000 628.320000 126.020000 ;
+ RECT 627.220000 120.100000 628.320000 120.580000 ;
+ RECT 582.220000 120.100000 583.320000 120.580000 ;
+ RECT 582.220000 125.540000 583.320000 126.020000 ;
+ RECT 492.220000 120.100000 493.320000 120.580000 ;
+ RECT 537.220000 120.100000 538.320000 120.580000 ;
+ RECT 537.220000 125.540000 538.320000 126.020000 ;
+ RECT 492.220000 125.540000 493.320000 126.020000 ;
+ RECT 443.090000 125.540000 444.090000 126.020000 ;
+ RECT 447.220000 125.540000 448.320000 126.020000 ;
+ RECT 443.090000 120.100000 444.090000 120.580000 ;
+ RECT 447.220000 120.100000 448.320000 120.580000 ;
+ RECT 440.260000 141.140000 640.360000 142.140000 ;
+ RECT 440.260000 118.090000 640.360000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 118.090000 441.260000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 118.090000 640.360000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 141.140000 441.260000 142.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 141.140000 640.360000 142.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 115.240000 444.090000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 144.500000 444.090000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 115.240000 637.530000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 144.500000 637.530000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 3152.250000 628.320000 3345.620000 ;
+ RECT 582.220000 3152.250000 583.320000 3345.620000 ;
+ RECT 636.530000 3149.400000 637.530000 3349.660000 ;
+ RECT 537.220000 3152.250000 538.320000 3345.620000 ;
+ RECT 492.220000 3152.250000 493.320000 3345.620000 ;
+ RECT 447.220000 3152.250000 448.320000 3345.620000 ;
+ RECT 443.090000 3149.400000 444.090000 3349.660000 ;
+ LAYER met3 ;
+ RECT 627.220000 3339.220000 628.320000 3339.700000 ;
+ RECT 636.530000 3339.220000 637.530000 3339.700000 ;
+ RECT 636.530000 3328.340000 637.530000 3328.820000 ;
+ RECT 636.530000 3333.780000 637.530000 3334.260000 ;
+ RECT 627.220000 3333.780000 628.320000 3334.260000 ;
+ RECT 627.220000 3328.340000 628.320000 3328.820000 ;
+ RECT 627.220000 3322.900000 628.320000 3323.380000 ;
+ RECT 627.220000 3317.460000 628.320000 3317.940000 ;
+ RECT 636.530000 3322.900000 637.530000 3323.380000 ;
+ RECT 636.530000 3317.460000 637.530000 3317.940000 ;
+ RECT 627.220000 3301.140000 628.320000 3301.620000 ;
+ RECT 627.220000 3306.580000 628.320000 3307.060000 ;
+ RECT 636.530000 3306.580000 637.530000 3307.060000 ;
+ RECT 636.530000 3301.140000 637.530000 3301.620000 ;
+ RECT 627.220000 3312.020000 628.320000 3312.500000 ;
+ RECT 636.530000 3312.020000 637.530000 3312.500000 ;
+ RECT 582.220000 3339.220000 583.320000 3339.700000 ;
+ RECT 582.220000 3333.780000 583.320000 3334.260000 ;
+ RECT 582.220000 3328.340000 583.320000 3328.820000 ;
+ RECT 582.220000 3322.900000 583.320000 3323.380000 ;
+ RECT 582.220000 3301.140000 583.320000 3301.620000 ;
+ RECT 582.220000 3306.580000 583.320000 3307.060000 ;
+ RECT 582.220000 3312.020000 583.320000 3312.500000 ;
+ RECT 582.220000 3317.460000 583.320000 3317.940000 ;
+ RECT 636.530000 3290.260000 637.530000 3290.740000 ;
+ RECT 636.530000 3295.700000 637.530000 3296.180000 ;
+ RECT 627.220000 3295.700000 628.320000 3296.180000 ;
+ RECT 627.220000 3290.260000 628.320000 3290.740000 ;
+ RECT 627.220000 3284.820000 628.320000 3285.300000 ;
+ RECT 627.220000 3279.380000 628.320000 3279.860000 ;
+ RECT 636.530000 3284.820000 637.530000 3285.300000 ;
+ RECT 636.530000 3279.380000 637.530000 3279.860000 ;
+ RECT 636.530000 3263.060000 637.530000 3263.540000 ;
+ RECT 636.530000 3268.500000 637.530000 3268.980000 ;
+ RECT 636.530000 3273.940000 637.530000 3274.420000 ;
+ RECT 627.220000 3268.500000 628.320000 3268.980000 ;
+ RECT 627.220000 3263.060000 628.320000 3263.540000 ;
+ RECT 627.220000 3273.940000 628.320000 3274.420000 ;
+ RECT 627.220000 3257.620000 628.320000 3258.100000 ;
+ RECT 627.220000 3252.180000 628.320000 3252.660000 ;
+ RECT 636.530000 3257.620000 637.530000 3258.100000 ;
+ RECT 636.530000 3252.180000 637.530000 3252.660000 ;
+ RECT 582.220000 3295.700000 583.320000 3296.180000 ;
+ RECT 582.220000 3290.260000 583.320000 3290.740000 ;
+ RECT 582.220000 3284.820000 583.320000 3285.300000 ;
+ RECT 582.220000 3279.380000 583.320000 3279.860000 ;
+ RECT 582.220000 3268.500000 583.320000 3268.980000 ;
+ RECT 582.220000 3263.060000 583.320000 3263.540000 ;
+ RECT 582.220000 3257.620000 583.320000 3258.100000 ;
+ RECT 582.220000 3252.180000 583.320000 3252.660000 ;
+ RECT 582.220000 3273.940000 583.320000 3274.420000 ;
+ RECT 537.220000 3339.220000 538.320000 3339.700000 ;
+ RECT 537.220000 3333.780000 538.320000 3334.260000 ;
+ RECT 537.220000 3328.340000 538.320000 3328.820000 ;
+ RECT 492.220000 3339.220000 493.320000 3339.700000 ;
+ RECT 492.220000 3333.780000 493.320000 3334.260000 ;
+ RECT 492.220000 3328.340000 493.320000 3328.820000 ;
+ RECT 537.220000 3312.020000 538.320000 3312.500000 ;
+ RECT 537.220000 3306.580000 538.320000 3307.060000 ;
+ RECT 537.220000 3301.140000 538.320000 3301.620000 ;
+ RECT 537.220000 3317.460000 538.320000 3317.940000 ;
+ RECT 537.220000 3322.900000 538.320000 3323.380000 ;
+ RECT 492.220000 3322.900000 493.320000 3323.380000 ;
+ RECT 492.220000 3312.020000 493.320000 3312.500000 ;
+ RECT 492.220000 3306.580000 493.320000 3307.060000 ;
+ RECT 492.220000 3301.140000 493.320000 3301.620000 ;
+ RECT 492.220000 3317.460000 493.320000 3317.940000 ;
+ RECT 447.220000 3339.220000 448.320000 3339.700000 ;
+ RECT 443.090000 3339.220000 444.090000 3339.700000 ;
+ RECT 443.090000 3333.780000 444.090000 3334.260000 ;
+ RECT 447.220000 3333.780000 448.320000 3334.260000 ;
+ RECT 447.220000 3328.340000 448.320000 3328.820000 ;
+ RECT 443.090000 3328.340000 444.090000 3328.820000 ;
+ RECT 447.220000 3322.900000 448.320000 3323.380000 ;
+ RECT 443.090000 3322.900000 444.090000 3323.380000 ;
+ RECT 447.220000 3317.460000 448.320000 3317.940000 ;
+ RECT 443.090000 3317.460000 444.090000 3317.940000 ;
+ RECT 447.220000 3306.580000 448.320000 3307.060000 ;
+ RECT 443.090000 3306.580000 444.090000 3307.060000 ;
+ RECT 447.220000 3301.140000 448.320000 3301.620000 ;
+ RECT 443.090000 3301.140000 444.090000 3301.620000 ;
+ RECT 447.220000 3312.020000 448.320000 3312.500000 ;
+ RECT 443.090000 3312.020000 444.090000 3312.500000 ;
+ RECT 537.220000 3295.700000 538.320000 3296.180000 ;
+ RECT 537.220000 3290.260000 538.320000 3290.740000 ;
+ RECT 537.220000 3284.820000 538.320000 3285.300000 ;
+ RECT 537.220000 3279.380000 538.320000 3279.860000 ;
+ RECT 492.220000 3295.700000 493.320000 3296.180000 ;
+ RECT 492.220000 3290.260000 493.320000 3290.740000 ;
+ RECT 492.220000 3284.820000 493.320000 3285.300000 ;
+ RECT 492.220000 3279.380000 493.320000 3279.860000 ;
+ RECT 537.220000 3268.500000 538.320000 3268.980000 ;
+ RECT 537.220000 3252.180000 538.320000 3252.660000 ;
+ RECT 537.220000 3257.620000 538.320000 3258.100000 ;
+ RECT 537.220000 3263.060000 538.320000 3263.540000 ;
+ RECT 537.220000 3273.940000 538.320000 3274.420000 ;
+ RECT 492.220000 3252.180000 493.320000 3252.660000 ;
+ RECT 492.220000 3257.620000 493.320000 3258.100000 ;
+ RECT 492.220000 3263.060000 493.320000 3263.540000 ;
+ RECT 492.220000 3268.500000 493.320000 3268.980000 ;
+ RECT 492.220000 3273.940000 493.320000 3274.420000 ;
+ RECT 447.220000 3295.700000 448.320000 3296.180000 ;
+ RECT 443.090000 3295.700000 444.090000 3296.180000 ;
+ RECT 447.220000 3290.260000 448.320000 3290.740000 ;
+ RECT 443.090000 3290.260000 444.090000 3290.740000 ;
+ RECT 447.220000 3284.820000 448.320000 3285.300000 ;
+ RECT 443.090000 3284.820000 444.090000 3285.300000 ;
+ RECT 447.220000 3279.380000 448.320000 3279.860000 ;
+ RECT 443.090000 3279.380000 444.090000 3279.860000 ;
+ RECT 447.220000 3273.940000 448.320000 3274.420000 ;
+ RECT 447.220000 3268.500000 448.320000 3268.980000 ;
+ RECT 443.090000 3273.940000 444.090000 3274.420000 ;
+ RECT 443.090000 3268.500000 444.090000 3268.980000 ;
+ RECT 447.220000 3263.060000 448.320000 3263.540000 ;
+ RECT 443.090000 3263.060000 444.090000 3263.540000 ;
+ RECT 447.220000 3257.620000 448.320000 3258.100000 ;
+ RECT 443.090000 3257.620000 444.090000 3258.100000 ;
+ RECT 447.220000 3252.180000 448.320000 3252.660000 ;
+ RECT 443.090000 3252.180000 444.090000 3252.660000 ;
+ RECT 627.220000 3246.740000 628.320000 3247.220000 ;
+ RECT 627.220000 3241.300000 628.320000 3241.780000 ;
+ RECT 636.530000 3246.740000 637.530000 3247.220000 ;
+ RECT 636.530000 3241.300000 637.530000 3241.780000 ;
+ RECT 636.530000 3224.980000 637.530000 3225.460000 ;
+ RECT 636.530000 3230.420000 637.530000 3230.900000 ;
+ RECT 636.530000 3235.860000 637.530000 3236.340000 ;
+ RECT 627.220000 3235.860000 628.320000 3236.340000 ;
+ RECT 627.220000 3230.420000 628.320000 3230.900000 ;
+ RECT 627.220000 3224.980000 628.320000 3225.460000 ;
+ RECT 627.220000 3214.100000 628.320000 3214.580000 ;
+ RECT 627.220000 3219.540000 628.320000 3220.020000 ;
+ RECT 636.530000 3219.540000 637.530000 3220.020000 ;
+ RECT 636.530000 3214.100000 637.530000 3214.580000 ;
+ RECT 636.530000 3203.220000 637.530000 3203.700000 ;
+ RECT 636.530000 3208.660000 637.530000 3209.140000 ;
+ RECT 627.220000 3203.220000 628.320000 3203.700000 ;
+ RECT 627.220000 3208.660000 628.320000 3209.140000 ;
+ RECT 582.220000 3246.740000 583.320000 3247.220000 ;
+ RECT 582.220000 3241.300000 583.320000 3241.780000 ;
+ RECT 582.220000 3235.860000 583.320000 3236.340000 ;
+ RECT 582.220000 3230.420000 583.320000 3230.900000 ;
+ RECT 582.220000 3224.980000 583.320000 3225.460000 ;
+ RECT 582.220000 3203.220000 583.320000 3203.700000 ;
+ RECT 582.220000 3208.660000 583.320000 3209.140000 ;
+ RECT 582.220000 3214.100000 583.320000 3214.580000 ;
+ RECT 582.220000 3219.540000 583.320000 3220.020000 ;
+ RECT 627.220000 3197.780000 628.320000 3198.260000 ;
+ RECT 627.220000 3192.340000 628.320000 3192.820000 ;
+ RECT 636.530000 3197.780000 637.530000 3198.260000 ;
+ RECT 636.530000 3192.340000 637.530000 3192.820000 ;
+ RECT 627.220000 3181.460000 628.320000 3181.940000 ;
+ RECT 627.220000 3176.020000 628.320000 3176.500000 ;
+ RECT 636.530000 3181.460000 637.530000 3181.940000 ;
+ RECT 636.530000 3176.020000 637.530000 3176.500000 ;
+ RECT 627.220000 3186.900000 628.320000 3187.380000 ;
+ RECT 636.530000 3186.900000 637.530000 3187.380000 ;
+ RECT 636.530000 3165.140000 637.530000 3165.620000 ;
+ RECT 636.530000 3170.580000 637.530000 3171.060000 ;
+ RECT 627.220000 3170.580000 628.320000 3171.060000 ;
+ RECT 627.220000 3165.140000 628.320000 3165.620000 ;
+ RECT 627.220000 3159.700000 628.320000 3160.180000 ;
+ RECT 627.220000 3154.260000 628.320000 3154.740000 ;
+ RECT 636.530000 3159.700000 637.530000 3160.180000 ;
+ RECT 636.530000 3154.260000 637.530000 3154.740000 ;
+ RECT 582.220000 3197.780000 583.320000 3198.260000 ;
+ RECT 582.220000 3192.340000 583.320000 3192.820000 ;
+ RECT 582.220000 3186.900000 583.320000 3187.380000 ;
+ RECT 582.220000 3181.460000 583.320000 3181.940000 ;
+ RECT 582.220000 3176.020000 583.320000 3176.500000 ;
+ RECT 582.220000 3170.580000 583.320000 3171.060000 ;
+ RECT 582.220000 3165.140000 583.320000 3165.620000 ;
+ RECT 582.220000 3159.700000 583.320000 3160.180000 ;
+ RECT 582.220000 3154.260000 583.320000 3154.740000 ;
+ RECT 537.220000 3246.740000 538.320000 3247.220000 ;
+ RECT 537.220000 3241.300000 538.320000 3241.780000 ;
+ RECT 537.220000 3235.860000 538.320000 3236.340000 ;
+ RECT 537.220000 3230.420000 538.320000 3230.900000 ;
+ RECT 537.220000 3224.980000 538.320000 3225.460000 ;
+ RECT 492.220000 3246.740000 493.320000 3247.220000 ;
+ RECT 492.220000 3241.300000 493.320000 3241.780000 ;
+ RECT 492.220000 3235.860000 493.320000 3236.340000 ;
+ RECT 492.220000 3230.420000 493.320000 3230.900000 ;
+ RECT 492.220000 3224.980000 493.320000 3225.460000 ;
+ RECT 537.220000 3219.540000 538.320000 3220.020000 ;
+ RECT 537.220000 3214.100000 538.320000 3214.580000 ;
+ RECT 537.220000 3208.660000 538.320000 3209.140000 ;
+ RECT 537.220000 3203.220000 538.320000 3203.700000 ;
+ RECT 492.220000 3214.100000 493.320000 3214.580000 ;
+ RECT 492.220000 3208.660000 493.320000 3209.140000 ;
+ RECT 492.220000 3203.220000 493.320000 3203.700000 ;
+ RECT 492.220000 3219.540000 493.320000 3220.020000 ;
+ RECT 447.220000 3246.740000 448.320000 3247.220000 ;
+ RECT 443.090000 3246.740000 444.090000 3247.220000 ;
+ RECT 447.220000 3241.300000 448.320000 3241.780000 ;
+ RECT 443.090000 3241.300000 444.090000 3241.780000 ;
+ RECT 447.220000 3235.860000 448.320000 3236.340000 ;
+ RECT 443.090000 3235.860000 444.090000 3236.340000 ;
+ RECT 447.220000 3224.980000 448.320000 3225.460000 ;
+ RECT 443.090000 3224.980000 444.090000 3225.460000 ;
+ RECT 443.090000 3230.420000 444.090000 3230.900000 ;
+ RECT 447.220000 3230.420000 448.320000 3230.900000 ;
+ RECT 447.220000 3219.540000 448.320000 3220.020000 ;
+ RECT 443.090000 3219.540000 444.090000 3220.020000 ;
+ RECT 447.220000 3214.100000 448.320000 3214.580000 ;
+ RECT 443.090000 3214.100000 444.090000 3214.580000 ;
+ RECT 447.220000 3208.660000 448.320000 3209.140000 ;
+ RECT 443.090000 3208.660000 444.090000 3209.140000 ;
+ RECT 447.220000 3203.220000 448.320000 3203.700000 ;
+ RECT 443.090000 3203.220000 444.090000 3203.700000 ;
+ RECT 537.220000 3197.780000 538.320000 3198.260000 ;
+ RECT 537.220000 3192.340000 538.320000 3192.820000 ;
+ RECT 537.220000 3186.900000 538.320000 3187.380000 ;
+ RECT 537.220000 3181.460000 538.320000 3181.940000 ;
+ RECT 537.220000 3176.020000 538.320000 3176.500000 ;
+ RECT 492.220000 3197.780000 493.320000 3198.260000 ;
+ RECT 492.220000 3192.340000 493.320000 3192.820000 ;
+ RECT 492.220000 3186.900000 493.320000 3187.380000 ;
+ RECT 492.220000 3181.460000 493.320000 3181.940000 ;
+ RECT 492.220000 3176.020000 493.320000 3176.500000 ;
+ RECT 537.220000 3154.260000 538.320000 3154.740000 ;
+ RECT 537.220000 3159.700000 538.320000 3160.180000 ;
+ RECT 537.220000 3165.140000 538.320000 3165.620000 ;
+ RECT 537.220000 3170.580000 538.320000 3171.060000 ;
+ RECT 492.220000 3154.260000 493.320000 3154.740000 ;
+ RECT 492.220000 3159.700000 493.320000 3160.180000 ;
+ RECT 492.220000 3165.140000 493.320000 3165.620000 ;
+ RECT 492.220000 3170.580000 493.320000 3171.060000 ;
+ RECT 447.220000 3197.780000 448.320000 3198.260000 ;
+ RECT 443.090000 3197.780000 444.090000 3198.260000 ;
+ RECT 447.220000 3192.340000 448.320000 3192.820000 ;
+ RECT 443.090000 3192.340000 444.090000 3192.820000 ;
+ RECT 447.220000 3181.460000 448.320000 3181.940000 ;
+ RECT 443.090000 3181.460000 444.090000 3181.940000 ;
+ RECT 447.220000 3176.020000 448.320000 3176.500000 ;
+ RECT 443.090000 3176.020000 444.090000 3176.500000 ;
+ RECT 447.220000 3186.900000 448.320000 3187.380000 ;
+ RECT 443.090000 3186.900000 444.090000 3187.380000 ;
+ RECT 447.220000 3170.580000 448.320000 3171.060000 ;
+ RECT 443.090000 3170.580000 444.090000 3171.060000 ;
+ RECT 447.220000 3165.140000 448.320000 3165.620000 ;
+ RECT 443.090000 3165.140000 444.090000 3165.620000 ;
+ RECT 447.220000 3159.700000 448.320000 3160.180000 ;
+ RECT 447.220000 3154.260000 448.320000 3154.740000 ;
+ RECT 443.090000 3159.700000 444.090000 3160.180000 ;
+ RECT 443.090000 3154.260000 444.090000 3154.740000 ;
+ RECT 440.260000 3344.620000 640.360000 3345.620000 ;
+ RECT 440.260000 3152.250000 640.360000 3153.250000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 3149.400000 444.090000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 3348.660000 444.090000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 3149.400000 637.530000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 3348.660000 637.530000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 3152.250000 441.260000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 3152.250000 640.360000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 3344.620000 441.260000 3345.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 3344.620000 640.360000 3345.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 2951.990000 628.320000 3145.360000 ;
+ RECT 582.220000 2951.990000 583.320000 3145.360000 ;
+ RECT 636.530000 2949.140000 637.530000 3149.400000 ;
+ RECT 537.220000 2951.990000 538.320000 3145.360000 ;
+ RECT 492.220000 2951.990000 493.320000 3145.360000 ;
+ RECT 447.220000 2951.990000 448.320000 3145.360000 ;
+ RECT 443.090000 2949.140000 444.090000 3149.400000 ;
+ LAYER met3 ;
+ RECT 627.220000 3138.960000 628.320000 3139.440000 ;
+ RECT 636.530000 3138.960000 637.530000 3139.440000 ;
+ RECT 636.530000 3128.080000 637.530000 3128.560000 ;
+ RECT 636.530000 3133.520000 637.530000 3134.000000 ;
+ RECT 627.220000 3133.520000 628.320000 3134.000000 ;
+ RECT 627.220000 3128.080000 628.320000 3128.560000 ;
+ RECT 627.220000 3122.640000 628.320000 3123.120000 ;
+ RECT 627.220000 3117.200000 628.320000 3117.680000 ;
+ RECT 636.530000 3122.640000 637.530000 3123.120000 ;
+ RECT 636.530000 3117.200000 637.530000 3117.680000 ;
+ RECT 627.220000 3100.880000 628.320000 3101.360000 ;
+ RECT 627.220000 3106.320000 628.320000 3106.800000 ;
+ RECT 636.530000 3106.320000 637.530000 3106.800000 ;
+ RECT 636.530000 3100.880000 637.530000 3101.360000 ;
+ RECT 627.220000 3111.760000 628.320000 3112.240000 ;
+ RECT 636.530000 3111.760000 637.530000 3112.240000 ;
+ RECT 582.220000 3138.960000 583.320000 3139.440000 ;
+ RECT 582.220000 3133.520000 583.320000 3134.000000 ;
+ RECT 582.220000 3128.080000 583.320000 3128.560000 ;
+ RECT 582.220000 3122.640000 583.320000 3123.120000 ;
+ RECT 582.220000 3100.880000 583.320000 3101.360000 ;
+ RECT 582.220000 3106.320000 583.320000 3106.800000 ;
+ RECT 582.220000 3111.760000 583.320000 3112.240000 ;
+ RECT 582.220000 3117.200000 583.320000 3117.680000 ;
+ RECT 636.530000 3090.000000 637.530000 3090.480000 ;
+ RECT 636.530000 3095.440000 637.530000 3095.920000 ;
+ RECT 627.220000 3095.440000 628.320000 3095.920000 ;
+ RECT 627.220000 3090.000000 628.320000 3090.480000 ;
+ RECT 627.220000 3084.560000 628.320000 3085.040000 ;
+ RECT 627.220000 3079.120000 628.320000 3079.600000 ;
+ RECT 636.530000 3084.560000 637.530000 3085.040000 ;
+ RECT 636.530000 3079.120000 637.530000 3079.600000 ;
+ RECT 636.530000 3062.800000 637.530000 3063.280000 ;
+ RECT 636.530000 3068.240000 637.530000 3068.720000 ;
+ RECT 636.530000 3073.680000 637.530000 3074.160000 ;
+ RECT 627.220000 3068.240000 628.320000 3068.720000 ;
+ RECT 627.220000 3062.800000 628.320000 3063.280000 ;
+ RECT 627.220000 3073.680000 628.320000 3074.160000 ;
+ RECT 627.220000 3057.360000 628.320000 3057.840000 ;
+ RECT 627.220000 3051.920000 628.320000 3052.400000 ;
+ RECT 636.530000 3057.360000 637.530000 3057.840000 ;
+ RECT 636.530000 3051.920000 637.530000 3052.400000 ;
+ RECT 582.220000 3095.440000 583.320000 3095.920000 ;
+ RECT 582.220000 3090.000000 583.320000 3090.480000 ;
+ RECT 582.220000 3084.560000 583.320000 3085.040000 ;
+ RECT 582.220000 3079.120000 583.320000 3079.600000 ;
+ RECT 582.220000 3068.240000 583.320000 3068.720000 ;
+ RECT 582.220000 3062.800000 583.320000 3063.280000 ;
+ RECT 582.220000 3057.360000 583.320000 3057.840000 ;
+ RECT 582.220000 3051.920000 583.320000 3052.400000 ;
+ RECT 582.220000 3073.680000 583.320000 3074.160000 ;
+ RECT 537.220000 3138.960000 538.320000 3139.440000 ;
+ RECT 537.220000 3133.520000 538.320000 3134.000000 ;
+ RECT 537.220000 3128.080000 538.320000 3128.560000 ;
+ RECT 492.220000 3138.960000 493.320000 3139.440000 ;
+ RECT 492.220000 3133.520000 493.320000 3134.000000 ;
+ RECT 492.220000 3128.080000 493.320000 3128.560000 ;
+ RECT 537.220000 3111.760000 538.320000 3112.240000 ;
+ RECT 537.220000 3106.320000 538.320000 3106.800000 ;
+ RECT 537.220000 3100.880000 538.320000 3101.360000 ;
+ RECT 537.220000 3117.200000 538.320000 3117.680000 ;
+ RECT 537.220000 3122.640000 538.320000 3123.120000 ;
+ RECT 492.220000 3122.640000 493.320000 3123.120000 ;
+ RECT 492.220000 3111.760000 493.320000 3112.240000 ;
+ RECT 492.220000 3106.320000 493.320000 3106.800000 ;
+ RECT 492.220000 3100.880000 493.320000 3101.360000 ;
+ RECT 492.220000 3117.200000 493.320000 3117.680000 ;
+ RECT 447.220000 3138.960000 448.320000 3139.440000 ;
+ RECT 443.090000 3138.960000 444.090000 3139.440000 ;
+ RECT 443.090000 3133.520000 444.090000 3134.000000 ;
+ RECT 447.220000 3133.520000 448.320000 3134.000000 ;
+ RECT 447.220000 3128.080000 448.320000 3128.560000 ;
+ RECT 443.090000 3128.080000 444.090000 3128.560000 ;
+ RECT 447.220000 3122.640000 448.320000 3123.120000 ;
+ RECT 443.090000 3122.640000 444.090000 3123.120000 ;
+ RECT 447.220000 3117.200000 448.320000 3117.680000 ;
+ RECT 443.090000 3117.200000 444.090000 3117.680000 ;
+ RECT 447.220000 3106.320000 448.320000 3106.800000 ;
+ RECT 443.090000 3106.320000 444.090000 3106.800000 ;
+ RECT 447.220000 3100.880000 448.320000 3101.360000 ;
+ RECT 443.090000 3100.880000 444.090000 3101.360000 ;
+ RECT 447.220000 3111.760000 448.320000 3112.240000 ;
+ RECT 443.090000 3111.760000 444.090000 3112.240000 ;
+ RECT 537.220000 3095.440000 538.320000 3095.920000 ;
+ RECT 537.220000 3090.000000 538.320000 3090.480000 ;
+ RECT 537.220000 3084.560000 538.320000 3085.040000 ;
+ RECT 537.220000 3079.120000 538.320000 3079.600000 ;
+ RECT 492.220000 3095.440000 493.320000 3095.920000 ;
+ RECT 492.220000 3090.000000 493.320000 3090.480000 ;
+ RECT 492.220000 3084.560000 493.320000 3085.040000 ;
+ RECT 492.220000 3079.120000 493.320000 3079.600000 ;
+ RECT 537.220000 3068.240000 538.320000 3068.720000 ;
+ RECT 537.220000 3051.920000 538.320000 3052.400000 ;
+ RECT 537.220000 3057.360000 538.320000 3057.840000 ;
+ RECT 537.220000 3062.800000 538.320000 3063.280000 ;
+ RECT 537.220000 3073.680000 538.320000 3074.160000 ;
+ RECT 492.220000 3051.920000 493.320000 3052.400000 ;
+ RECT 492.220000 3057.360000 493.320000 3057.840000 ;
+ RECT 492.220000 3062.800000 493.320000 3063.280000 ;
+ RECT 492.220000 3068.240000 493.320000 3068.720000 ;
+ RECT 492.220000 3073.680000 493.320000 3074.160000 ;
+ RECT 447.220000 3095.440000 448.320000 3095.920000 ;
+ RECT 443.090000 3095.440000 444.090000 3095.920000 ;
+ RECT 447.220000 3090.000000 448.320000 3090.480000 ;
+ RECT 443.090000 3090.000000 444.090000 3090.480000 ;
+ RECT 447.220000 3084.560000 448.320000 3085.040000 ;
+ RECT 443.090000 3084.560000 444.090000 3085.040000 ;
+ RECT 447.220000 3079.120000 448.320000 3079.600000 ;
+ RECT 443.090000 3079.120000 444.090000 3079.600000 ;
+ RECT 447.220000 3073.680000 448.320000 3074.160000 ;
+ RECT 447.220000 3068.240000 448.320000 3068.720000 ;
+ RECT 443.090000 3073.680000 444.090000 3074.160000 ;
+ RECT 443.090000 3068.240000 444.090000 3068.720000 ;
+ RECT 447.220000 3062.800000 448.320000 3063.280000 ;
+ RECT 443.090000 3062.800000 444.090000 3063.280000 ;
+ RECT 447.220000 3057.360000 448.320000 3057.840000 ;
+ RECT 443.090000 3057.360000 444.090000 3057.840000 ;
+ RECT 447.220000 3051.920000 448.320000 3052.400000 ;
+ RECT 443.090000 3051.920000 444.090000 3052.400000 ;
+ RECT 627.220000 3046.480000 628.320000 3046.960000 ;
+ RECT 627.220000 3041.040000 628.320000 3041.520000 ;
+ RECT 636.530000 3046.480000 637.530000 3046.960000 ;
+ RECT 636.530000 3041.040000 637.530000 3041.520000 ;
+ RECT 636.530000 3024.720000 637.530000 3025.200000 ;
+ RECT 636.530000 3030.160000 637.530000 3030.640000 ;
+ RECT 636.530000 3035.600000 637.530000 3036.080000 ;
+ RECT 627.220000 3035.600000 628.320000 3036.080000 ;
+ RECT 627.220000 3030.160000 628.320000 3030.640000 ;
+ RECT 627.220000 3024.720000 628.320000 3025.200000 ;
+ RECT 627.220000 3013.840000 628.320000 3014.320000 ;
+ RECT 627.220000 3019.280000 628.320000 3019.760000 ;
+ RECT 636.530000 3019.280000 637.530000 3019.760000 ;
+ RECT 636.530000 3013.840000 637.530000 3014.320000 ;
+ RECT 636.530000 3002.960000 637.530000 3003.440000 ;
+ RECT 636.530000 3008.400000 637.530000 3008.880000 ;
+ RECT 627.220000 3002.960000 628.320000 3003.440000 ;
+ RECT 627.220000 3008.400000 628.320000 3008.880000 ;
+ RECT 582.220000 3046.480000 583.320000 3046.960000 ;
+ RECT 582.220000 3041.040000 583.320000 3041.520000 ;
+ RECT 582.220000 3035.600000 583.320000 3036.080000 ;
+ RECT 582.220000 3030.160000 583.320000 3030.640000 ;
+ RECT 582.220000 3024.720000 583.320000 3025.200000 ;
+ RECT 582.220000 3002.960000 583.320000 3003.440000 ;
+ RECT 582.220000 3008.400000 583.320000 3008.880000 ;
+ RECT 582.220000 3013.840000 583.320000 3014.320000 ;
+ RECT 582.220000 3019.280000 583.320000 3019.760000 ;
+ RECT 627.220000 2997.520000 628.320000 2998.000000 ;
+ RECT 627.220000 2992.080000 628.320000 2992.560000 ;
+ RECT 636.530000 2997.520000 637.530000 2998.000000 ;
+ RECT 636.530000 2992.080000 637.530000 2992.560000 ;
+ RECT 627.220000 2981.200000 628.320000 2981.680000 ;
+ RECT 627.220000 2975.760000 628.320000 2976.240000 ;
+ RECT 636.530000 2981.200000 637.530000 2981.680000 ;
+ RECT 636.530000 2975.760000 637.530000 2976.240000 ;
+ RECT 627.220000 2986.640000 628.320000 2987.120000 ;
+ RECT 636.530000 2986.640000 637.530000 2987.120000 ;
+ RECT 636.530000 2964.880000 637.530000 2965.360000 ;
+ RECT 636.530000 2970.320000 637.530000 2970.800000 ;
+ RECT 627.220000 2970.320000 628.320000 2970.800000 ;
+ RECT 627.220000 2964.880000 628.320000 2965.360000 ;
+ RECT 627.220000 2959.440000 628.320000 2959.920000 ;
+ RECT 627.220000 2954.000000 628.320000 2954.480000 ;
+ RECT 636.530000 2959.440000 637.530000 2959.920000 ;
+ RECT 636.530000 2954.000000 637.530000 2954.480000 ;
+ RECT 582.220000 2997.520000 583.320000 2998.000000 ;
+ RECT 582.220000 2992.080000 583.320000 2992.560000 ;
+ RECT 582.220000 2986.640000 583.320000 2987.120000 ;
+ RECT 582.220000 2981.200000 583.320000 2981.680000 ;
+ RECT 582.220000 2975.760000 583.320000 2976.240000 ;
+ RECT 582.220000 2970.320000 583.320000 2970.800000 ;
+ RECT 582.220000 2964.880000 583.320000 2965.360000 ;
+ RECT 582.220000 2959.440000 583.320000 2959.920000 ;
+ RECT 582.220000 2954.000000 583.320000 2954.480000 ;
+ RECT 537.220000 3046.480000 538.320000 3046.960000 ;
+ RECT 537.220000 3041.040000 538.320000 3041.520000 ;
+ RECT 537.220000 3035.600000 538.320000 3036.080000 ;
+ RECT 537.220000 3030.160000 538.320000 3030.640000 ;
+ RECT 537.220000 3024.720000 538.320000 3025.200000 ;
+ RECT 492.220000 3046.480000 493.320000 3046.960000 ;
+ RECT 492.220000 3041.040000 493.320000 3041.520000 ;
+ RECT 492.220000 3035.600000 493.320000 3036.080000 ;
+ RECT 492.220000 3030.160000 493.320000 3030.640000 ;
+ RECT 492.220000 3024.720000 493.320000 3025.200000 ;
+ RECT 537.220000 3019.280000 538.320000 3019.760000 ;
+ RECT 537.220000 3013.840000 538.320000 3014.320000 ;
+ RECT 537.220000 3008.400000 538.320000 3008.880000 ;
+ RECT 537.220000 3002.960000 538.320000 3003.440000 ;
+ RECT 492.220000 3013.840000 493.320000 3014.320000 ;
+ RECT 492.220000 3008.400000 493.320000 3008.880000 ;
+ RECT 492.220000 3002.960000 493.320000 3003.440000 ;
+ RECT 492.220000 3019.280000 493.320000 3019.760000 ;
+ RECT 447.220000 3046.480000 448.320000 3046.960000 ;
+ RECT 443.090000 3046.480000 444.090000 3046.960000 ;
+ RECT 447.220000 3041.040000 448.320000 3041.520000 ;
+ RECT 443.090000 3041.040000 444.090000 3041.520000 ;
+ RECT 447.220000 3035.600000 448.320000 3036.080000 ;
+ RECT 443.090000 3035.600000 444.090000 3036.080000 ;
+ RECT 447.220000 3024.720000 448.320000 3025.200000 ;
+ RECT 443.090000 3024.720000 444.090000 3025.200000 ;
+ RECT 443.090000 3030.160000 444.090000 3030.640000 ;
+ RECT 447.220000 3030.160000 448.320000 3030.640000 ;
+ RECT 447.220000 3019.280000 448.320000 3019.760000 ;
+ RECT 443.090000 3019.280000 444.090000 3019.760000 ;
+ RECT 447.220000 3013.840000 448.320000 3014.320000 ;
+ RECT 443.090000 3013.840000 444.090000 3014.320000 ;
+ RECT 447.220000 3008.400000 448.320000 3008.880000 ;
+ RECT 443.090000 3008.400000 444.090000 3008.880000 ;
+ RECT 447.220000 3002.960000 448.320000 3003.440000 ;
+ RECT 443.090000 3002.960000 444.090000 3003.440000 ;
+ RECT 537.220000 2997.520000 538.320000 2998.000000 ;
+ RECT 537.220000 2992.080000 538.320000 2992.560000 ;
+ RECT 537.220000 2986.640000 538.320000 2987.120000 ;
+ RECT 537.220000 2981.200000 538.320000 2981.680000 ;
+ RECT 537.220000 2975.760000 538.320000 2976.240000 ;
+ RECT 492.220000 2997.520000 493.320000 2998.000000 ;
+ RECT 492.220000 2992.080000 493.320000 2992.560000 ;
+ RECT 492.220000 2986.640000 493.320000 2987.120000 ;
+ RECT 492.220000 2981.200000 493.320000 2981.680000 ;
+ RECT 492.220000 2975.760000 493.320000 2976.240000 ;
+ RECT 537.220000 2954.000000 538.320000 2954.480000 ;
+ RECT 537.220000 2959.440000 538.320000 2959.920000 ;
+ RECT 537.220000 2964.880000 538.320000 2965.360000 ;
+ RECT 537.220000 2970.320000 538.320000 2970.800000 ;
+ RECT 492.220000 2954.000000 493.320000 2954.480000 ;
+ RECT 492.220000 2959.440000 493.320000 2959.920000 ;
+ RECT 492.220000 2964.880000 493.320000 2965.360000 ;
+ RECT 492.220000 2970.320000 493.320000 2970.800000 ;
+ RECT 447.220000 2997.520000 448.320000 2998.000000 ;
+ RECT 443.090000 2997.520000 444.090000 2998.000000 ;
+ RECT 447.220000 2992.080000 448.320000 2992.560000 ;
+ RECT 443.090000 2992.080000 444.090000 2992.560000 ;
+ RECT 447.220000 2981.200000 448.320000 2981.680000 ;
+ RECT 443.090000 2981.200000 444.090000 2981.680000 ;
+ RECT 447.220000 2975.760000 448.320000 2976.240000 ;
+ RECT 443.090000 2975.760000 444.090000 2976.240000 ;
+ RECT 447.220000 2986.640000 448.320000 2987.120000 ;
+ RECT 443.090000 2986.640000 444.090000 2987.120000 ;
+ RECT 447.220000 2970.320000 448.320000 2970.800000 ;
+ RECT 443.090000 2970.320000 444.090000 2970.800000 ;
+ RECT 447.220000 2964.880000 448.320000 2965.360000 ;
+ RECT 443.090000 2964.880000 444.090000 2965.360000 ;
+ RECT 447.220000 2959.440000 448.320000 2959.920000 ;
+ RECT 447.220000 2954.000000 448.320000 2954.480000 ;
+ RECT 443.090000 2959.440000 444.090000 2959.920000 ;
+ RECT 443.090000 2954.000000 444.090000 2954.480000 ;
+ RECT 440.260000 3144.360000 640.360000 3145.360000 ;
+ RECT 440.260000 2951.990000 640.360000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 2949.140000 444.090000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 3148.400000 444.090000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 2949.140000 637.530000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 3148.400000 637.530000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2951.990000 441.260000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2951.990000 640.360000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 3144.360000 441.260000 3145.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 3144.360000 640.360000 3145.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 2751.730000 628.320000 2945.100000 ;
+ RECT 582.220000 2751.730000 583.320000 2945.100000 ;
+ RECT 636.530000 2748.880000 637.530000 2949.140000 ;
+ RECT 537.220000 2751.730000 538.320000 2945.100000 ;
+ RECT 492.220000 2751.730000 493.320000 2945.100000 ;
+ RECT 447.220000 2751.730000 448.320000 2945.100000 ;
+ RECT 443.090000 2748.880000 444.090000 2949.140000 ;
+ LAYER met3 ;
+ RECT 627.220000 2938.700000 628.320000 2939.180000 ;
+ RECT 636.530000 2938.700000 637.530000 2939.180000 ;
+ RECT 636.530000 2927.820000 637.530000 2928.300000 ;
+ RECT 636.530000 2933.260000 637.530000 2933.740000 ;
+ RECT 627.220000 2933.260000 628.320000 2933.740000 ;
+ RECT 627.220000 2927.820000 628.320000 2928.300000 ;
+ RECT 627.220000 2922.380000 628.320000 2922.860000 ;
+ RECT 627.220000 2916.940000 628.320000 2917.420000 ;
+ RECT 636.530000 2922.380000 637.530000 2922.860000 ;
+ RECT 636.530000 2916.940000 637.530000 2917.420000 ;
+ RECT 627.220000 2900.620000 628.320000 2901.100000 ;
+ RECT 627.220000 2906.060000 628.320000 2906.540000 ;
+ RECT 636.530000 2906.060000 637.530000 2906.540000 ;
+ RECT 636.530000 2900.620000 637.530000 2901.100000 ;
+ RECT 627.220000 2911.500000 628.320000 2911.980000 ;
+ RECT 636.530000 2911.500000 637.530000 2911.980000 ;
+ RECT 582.220000 2938.700000 583.320000 2939.180000 ;
+ RECT 582.220000 2933.260000 583.320000 2933.740000 ;
+ RECT 582.220000 2927.820000 583.320000 2928.300000 ;
+ RECT 582.220000 2922.380000 583.320000 2922.860000 ;
+ RECT 582.220000 2900.620000 583.320000 2901.100000 ;
+ RECT 582.220000 2906.060000 583.320000 2906.540000 ;
+ RECT 582.220000 2911.500000 583.320000 2911.980000 ;
+ RECT 582.220000 2916.940000 583.320000 2917.420000 ;
+ RECT 636.530000 2889.740000 637.530000 2890.220000 ;
+ RECT 636.530000 2895.180000 637.530000 2895.660000 ;
+ RECT 627.220000 2895.180000 628.320000 2895.660000 ;
+ RECT 627.220000 2889.740000 628.320000 2890.220000 ;
+ RECT 627.220000 2884.300000 628.320000 2884.780000 ;
+ RECT 627.220000 2878.860000 628.320000 2879.340000 ;
+ RECT 636.530000 2884.300000 637.530000 2884.780000 ;
+ RECT 636.530000 2878.860000 637.530000 2879.340000 ;
+ RECT 636.530000 2862.540000 637.530000 2863.020000 ;
+ RECT 636.530000 2867.980000 637.530000 2868.460000 ;
+ RECT 636.530000 2873.420000 637.530000 2873.900000 ;
+ RECT 627.220000 2867.980000 628.320000 2868.460000 ;
+ RECT 627.220000 2862.540000 628.320000 2863.020000 ;
+ RECT 627.220000 2873.420000 628.320000 2873.900000 ;
+ RECT 627.220000 2857.100000 628.320000 2857.580000 ;
+ RECT 627.220000 2851.660000 628.320000 2852.140000 ;
+ RECT 636.530000 2857.100000 637.530000 2857.580000 ;
+ RECT 636.530000 2851.660000 637.530000 2852.140000 ;
+ RECT 582.220000 2895.180000 583.320000 2895.660000 ;
+ RECT 582.220000 2889.740000 583.320000 2890.220000 ;
+ RECT 582.220000 2884.300000 583.320000 2884.780000 ;
+ RECT 582.220000 2878.860000 583.320000 2879.340000 ;
+ RECT 582.220000 2867.980000 583.320000 2868.460000 ;
+ RECT 582.220000 2862.540000 583.320000 2863.020000 ;
+ RECT 582.220000 2857.100000 583.320000 2857.580000 ;
+ RECT 582.220000 2851.660000 583.320000 2852.140000 ;
+ RECT 582.220000 2873.420000 583.320000 2873.900000 ;
+ RECT 537.220000 2938.700000 538.320000 2939.180000 ;
+ RECT 537.220000 2933.260000 538.320000 2933.740000 ;
+ RECT 537.220000 2927.820000 538.320000 2928.300000 ;
+ RECT 492.220000 2938.700000 493.320000 2939.180000 ;
+ RECT 492.220000 2933.260000 493.320000 2933.740000 ;
+ RECT 492.220000 2927.820000 493.320000 2928.300000 ;
+ RECT 537.220000 2911.500000 538.320000 2911.980000 ;
+ RECT 537.220000 2906.060000 538.320000 2906.540000 ;
+ RECT 537.220000 2900.620000 538.320000 2901.100000 ;
+ RECT 537.220000 2916.940000 538.320000 2917.420000 ;
+ RECT 537.220000 2922.380000 538.320000 2922.860000 ;
+ RECT 492.220000 2922.380000 493.320000 2922.860000 ;
+ RECT 492.220000 2911.500000 493.320000 2911.980000 ;
+ RECT 492.220000 2906.060000 493.320000 2906.540000 ;
+ RECT 492.220000 2900.620000 493.320000 2901.100000 ;
+ RECT 492.220000 2916.940000 493.320000 2917.420000 ;
+ RECT 447.220000 2938.700000 448.320000 2939.180000 ;
+ RECT 443.090000 2938.700000 444.090000 2939.180000 ;
+ RECT 443.090000 2933.260000 444.090000 2933.740000 ;
+ RECT 447.220000 2933.260000 448.320000 2933.740000 ;
+ RECT 447.220000 2927.820000 448.320000 2928.300000 ;
+ RECT 443.090000 2927.820000 444.090000 2928.300000 ;
+ RECT 447.220000 2922.380000 448.320000 2922.860000 ;
+ RECT 443.090000 2922.380000 444.090000 2922.860000 ;
+ RECT 447.220000 2916.940000 448.320000 2917.420000 ;
+ RECT 443.090000 2916.940000 444.090000 2917.420000 ;
+ RECT 447.220000 2906.060000 448.320000 2906.540000 ;
+ RECT 443.090000 2906.060000 444.090000 2906.540000 ;
+ RECT 447.220000 2900.620000 448.320000 2901.100000 ;
+ RECT 443.090000 2900.620000 444.090000 2901.100000 ;
+ RECT 447.220000 2911.500000 448.320000 2911.980000 ;
+ RECT 443.090000 2911.500000 444.090000 2911.980000 ;
+ RECT 537.220000 2895.180000 538.320000 2895.660000 ;
+ RECT 537.220000 2889.740000 538.320000 2890.220000 ;
+ RECT 537.220000 2884.300000 538.320000 2884.780000 ;
+ RECT 537.220000 2878.860000 538.320000 2879.340000 ;
+ RECT 492.220000 2895.180000 493.320000 2895.660000 ;
+ RECT 492.220000 2889.740000 493.320000 2890.220000 ;
+ RECT 492.220000 2884.300000 493.320000 2884.780000 ;
+ RECT 492.220000 2878.860000 493.320000 2879.340000 ;
+ RECT 537.220000 2867.980000 538.320000 2868.460000 ;
+ RECT 537.220000 2851.660000 538.320000 2852.140000 ;
+ RECT 537.220000 2857.100000 538.320000 2857.580000 ;
+ RECT 537.220000 2862.540000 538.320000 2863.020000 ;
+ RECT 537.220000 2873.420000 538.320000 2873.900000 ;
+ RECT 492.220000 2851.660000 493.320000 2852.140000 ;
+ RECT 492.220000 2857.100000 493.320000 2857.580000 ;
+ RECT 492.220000 2862.540000 493.320000 2863.020000 ;
+ RECT 492.220000 2867.980000 493.320000 2868.460000 ;
+ RECT 492.220000 2873.420000 493.320000 2873.900000 ;
+ RECT 447.220000 2895.180000 448.320000 2895.660000 ;
+ RECT 443.090000 2895.180000 444.090000 2895.660000 ;
+ RECT 447.220000 2889.740000 448.320000 2890.220000 ;
+ RECT 443.090000 2889.740000 444.090000 2890.220000 ;
+ RECT 447.220000 2884.300000 448.320000 2884.780000 ;
+ RECT 443.090000 2884.300000 444.090000 2884.780000 ;
+ RECT 447.220000 2878.860000 448.320000 2879.340000 ;
+ RECT 443.090000 2878.860000 444.090000 2879.340000 ;
+ RECT 447.220000 2873.420000 448.320000 2873.900000 ;
+ RECT 447.220000 2867.980000 448.320000 2868.460000 ;
+ RECT 443.090000 2873.420000 444.090000 2873.900000 ;
+ RECT 443.090000 2867.980000 444.090000 2868.460000 ;
+ RECT 447.220000 2862.540000 448.320000 2863.020000 ;
+ RECT 443.090000 2862.540000 444.090000 2863.020000 ;
+ RECT 447.220000 2857.100000 448.320000 2857.580000 ;
+ RECT 443.090000 2857.100000 444.090000 2857.580000 ;
+ RECT 447.220000 2851.660000 448.320000 2852.140000 ;
+ RECT 443.090000 2851.660000 444.090000 2852.140000 ;
+ RECT 627.220000 2846.220000 628.320000 2846.700000 ;
+ RECT 627.220000 2840.780000 628.320000 2841.260000 ;
+ RECT 636.530000 2846.220000 637.530000 2846.700000 ;
+ RECT 636.530000 2840.780000 637.530000 2841.260000 ;
+ RECT 636.530000 2824.460000 637.530000 2824.940000 ;
+ RECT 636.530000 2829.900000 637.530000 2830.380000 ;
+ RECT 636.530000 2835.340000 637.530000 2835.820000 ;
+ RECT 627.220000 2835.340000 628.320000 2835.820000 ;
+ RECT 627.220000 2829.900000 628.320000 2830.380000 ;
+ RECT 627.220000 2824.460000 628.320000 2824.940000 ;
+ RECT 627.220000 2813.580000 628.320000 2814.060000 ;
+ RECT 627.220000 2819.020000 628.320000 2819.500000 ;
+ RECT 636.530000 2819.020000 637.530000 2819.500000 ;
+ RECT 636.530000 2813.580000 637.530000 2814.060000 ;
+ RECT 636.530000 2802.700000 637.530000 2803.180000 ;
+ RECT 636.530000 2808.140000 637.530000 2808.620000 ;
+ RECT 627.220000 2802.700000 628.320000 2803.180000 ;
+ RECT 627.220000 2808.140000 628.320000 2808.620000 ;
+ RECT 582.220000 2846.220000 583.320000 2846.700000 ;
+ RECT 582.220000 2840.780000 583.320000 2841.260000 ;
+ RECT 582.220000 2835.340000 583.320000 2835.820000 ;
+ RECT 582.220000 2829.900000 583.320000 2830.380000 ;
+ RECT 582.220000 2824.460000 583.320000 2824.940000 ;
+ RECT 582.220000 2802.700000 583.320000 2803.180000 ;
+ RECT 582.220000 2808.140000 583.320000 2808.620000 ;
+ RECT 582.220000 2813.580000 583.320000 2814.060000 ;
+ RECT 582.220000 2819.020000 583.320000 2819.500000 ;
+ RECT 627.220000 2797.260000 628.320000 2797.740000 ;
+ RECT 627.220000 2791.820000 628.320000 2792.300000 ;
+ RECT 636.530000 2797.260000 637.530000 2797.740000 ;
+ RECT 636.530000 2791.820000 637.530000 2792.300000 ;
+ RECT 627.220000 2780.940000 628.320000 2781.420000 ;
+ RECT 627.220000 2775.500000 628.320000 2775.980000 ;
+ RECT 636.530000 2780.940000 637.530000 2781.420000 ;
+ RECT 636.530000 2775.500000 637.530000 2775.980000 ;
+ RECT 627.220000 2786.380000 628.320000 2786.860000 ;
+ RECT 636.530000 2786.380000 637.530000 2786.860000 ;
+ RECT 636.530000 2764.620000 637.530000 2765.100000 ;
+ RECT 636.530000 2770.060000 637.530000 2770.540000 ;
+ RECT 627.220000 2770.060000 628.320000 2770.540000 ;
+ RECT 627.220000 2764.620000 628.320000 2765.100000 ;
+ RECT 627.220000 2759.180000 628.320000 2759.660000 ;
+ RECT 627.220000 2753.740000 628.320000 2754.220000 ;
+ RECT 636.530000 2759.180000 637.530000 2759.660000 ;
+ RECT 636.530000 2753.740000 637.530000 2754.220000 ;
+ RECT 582.220000 2797.260000 583.320000 2797.740000 ;
+ RECT 582.220000 2791.820000 583.320000 2792.300000 ;
+ RECT 582.220000 2786.380000 583.320000 2786.860000 ;
+ RECT 582.220000 2780.940000 583.320000 2781.420000 ;
+ RECT 582.220000 2775.500000 583.320000 2775.980000 ;
+ RECT 582.220000 2770.060000 583.320000 2770.540000 ;
+ RECT 582.220000 2764.620000 583.320000 2765.100000 ;
+ RECT 582.220000 2759.180000 583.320000 2759.660000 ;
+ RECT 582.220000 2753.740000 583.320000 2754.220000 ;
+ RECT 537.220000 2846.220000 538.320000 2846.700000 ;
+ RECT 537.220000 2840.780000 538.320000 2841.260000 ;
+ RECT 537.220000 2835.340000 538.320000 2835.820000 ;
+ RECT 537.220000 2829.900000 538.320000 2830.380000 ;
+ RECT 537.220000 2824.460000 538.320000 2824.940000 ;
+ RECT 492.220000 2846.220000 493.320000 2846.700000 ;
+ RECT 492.220000 2840.780000 493.320000 2841.260000 ;
+ RECT 492.220000 2835.340000 493.320000 2835.820000 ;
+ RECT 492.220000 2829.900000 493.320000 2830.380000 ;
+ RECT 492.220000 2824.460000 493.320000 2824.940000 ;
+ RECT 537.220000 2819.020000 538.320000 2819.500000 ;
+ RECT 537.220000 2813.580000 538.320000 2814.060000 ;
+ RECT 537.220000 2808.140000 538.320000 2808.620000 ;
+ RECT 537.220000 2802.700000 538.320000 2803.180000 ;
+ RECT 492.220000 2813.580000 493.320000 2814.060000 ;
+ RECT 492.220000 2808.140000 493.320000 2808.620000 ;
+ RECT 492.220000 2802.700000 493.320000 2803.180000 ;
+ RECT 492.220000 2819.020000 493.320000 2819.500000 ;
+ RECT 447.220000 2846.220000 448.320000 2846.700000 ;
+ RECT 443.090000 2846.220000 444.090000 2846.700000 ;
+ RECT 447.220000 2840.780000 448.320000 2841.260000 ;
+ RECT 443.090000 2840.780000 444.090000 2841.260000 ;
+ RECT 447.220000 2835.340000 448.320000 2835.820000 ;
+ RECT 443.090000 2835.340000 444.090000 2835.820000 ;
+ RECT 447.220000 2824.460000 448.320000 2824.940000 ;
+ RECT 443.090000 2824.460000 444.090000 2824.940000 ;
+ RECT 443.090000 2829.900000 444.090000 2830.380000 ;
+ RECT 447.220000 2829.900000 448.320000 2830.380000 ;
+ RECT 447.220000 2819.020000 448.320000 2819.500000 ;
+ RECT 443.090000 2819.020000 444.090000 2819.500000 ;
+ RECT 447.220000 2813.580000 448.320000 2814.060000 ;
+ RECT 443.090000 2813.580000 444.090000 2814.060000 ;
+ RECT 447.220000 2808.140000 448.320000 2808.620000 ;
+ RECT 443.090000 2808.140000 444.090000 2808.620000 ;
+ RECT 447.220000 2802.700000 448.320000 2803.180000 ;
+ RECT 443.090000 2802.700000 444.090000 2803.180000 ;
+ RECT 537.220000 2797.260000 538.320000 2797.740000 ;
+ RECT 537.220000 2791.820000 538.320000 2792.300000 ;
+ RECT 537.220000 2786.380000 538.320000 2786.860000 ;
+ RECT 537.220000 2780.940000 538.320000 2781.420000 ;
+ RECT 537.220000 2775.500000 538.320000 2775.980000 ;
+ RECT 492.220000 2797.260000 493.320000 2797.740000 ;
+ RECT 492.220000 2791.820000 493.320000 2792.300000 ;
+ RECT 492.220000 2786.380000 493.320000 2786.860000 ;
+ RECT 492.220000 2780.940000 493.320000 2781.420000 ;
+ RECT 492.220000 2775.500000 493.320000 2775.980000 ;
+ RECT 537.220000 2753.740000 538.320000 2754.220000 ;
+ RECT 537.220000 2759.180000 538.320000 2759.660000 ;
+ RECT 537.220000 2764.620000 538.320000 2765.100000 ;
+ RECT 537.220000 2770.060000 538.320000 2770.540000 ;
+ RECT 492.220000 2753.740000 493.320000 2754.220000 ;
+ RECT 492.220000 2759.180000 493.320000 2759.660000 ;
+ RECT 492.220000 2764.620000 493.320000 2765.100000 ;
+ RECT 492.220000 2770.060000 493.320000 2770.540000 ;
+ RECT 447.220000 2797.260000 448.320000 2797.740000 ;
+ RECT 443.090000 2797.260000 444.090000 2797.740000 ;
+ RECT 447.220000 2791.820000 448.320000 2792.300000 ;
+ RECT 443.090000 2791.820000 444.090000 2792.300000 ;
+ RECT 447.220000 2780.940000 448.320000 2781.420000 ;
+ RECT 443.090000 2780.940000 444.090000 2781.420000 ;
+ RECT 447.220000 2775.500000 448.320000 2775.980000 ;
+ RECT 443.090000 2775.500000 444.090000 2775.980000 ;
+ RECT 447.220000 2786.380000 448.320000 2786.860000 ;
+ RECT 443.090000 2786.380000 444.090000 2786.860000 ;
+ RECT 447.220000 2770.060000 448.320000 2770.540000 ;
+ RECT 443.090000 2770.060000 444.090000 2770.540000 ;
+ RECT 447.220000 2764.620000 448.320000 2765.100000 ;
+ RECT 443.090000 2764.620000 444.090000 2765.100000 ;
+ RECT 447.220000 2759.180000 448.320000 2759.660000 ;
+ RECT 447.220000 2753.740000 448.320000 2754.220000 ;
+ RECT 443.090000 2759.180000 444.090000 2759.660000 ;
+ RECT 443.090000 2753.740000 444.090000 2754.220000 ;
+ RECT 440.260000 2944.100000 640.360000 2945.100000 ;
+ RECT 440.260000 2751.730000 640.360000 2752.730000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 2748.880000 444.090000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 2948.140000 444.090000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 2748.880000 637.530000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 2948.140000 637.530000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2751.730000 441.260000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2751.730000 640.360000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2944.100000 441.260000 2945.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2944.100000 640.360000 2945.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 2551.470000 628.320000 2744.840000 ;
+ RECT 582.220000 2551.470000 583.320000 2744.840000 ;
+ RECT 636.530000 2548.620000 637.530000 2748.880000 ;
+ RECT 537.220000 2551.470000 538.320000 2744.840000 ;
+ RECT 492.220000 2551.470000 493.320000 2744.840000 ;
+ RECT 447.220000 2551.470000 448.320000 2744.840000 ;
+ RECT 443.090000 2548.620000 444.090000 2748.880000 ;
+ LAYER met3 ;
+ RECT 627.220000 2738.440000 628.320000 2738.920000 ;
+ RECT 636.530000 2738.440000 637.530000 2738.920000 ;
+ RECT 636.530000 2727.560000 637.530000 2728.040000 ;
+ RECT 636.530000 2733.000000 637.530000 2733.480000 ;
+ RECT 627.220000 2733.000000 628.320000 2733.480000 ;
+ RECT 627.220000 2727.560000 628.320000 2728.040000 ;
+ RECT 627.220000 2722.120000 628.320000 2722.600000 ;
+ RECT 627.220000 2716.680000 628.320000 2717.160000 ;
+ RECT 636.530000 2722.120000 637.530000 2722.600000 ;
+ RECT 636.530000 2716.680000 637.530000 2717.160000 ;
+ RECT 627.220000 2700.360000 628.320000 2700.840000 ;
+ RECT 627.220000 2705.800000 628.320000 2706.280000 ;
+ RECT 636.530000 2705.800000 637.530000 2706.280000 ;
+ RECT 636.530000 2700.360000 637.530000 2700.840000 ;
+ RECT 627.220000 2711.240000 628.320000 2711.720000 ;
+ RECT 636.530000 2711.240000 637.530000 2711.720000 ;
+ RECT 582.220000 2738.440000 583.320000 2738.920000 ;
+ RECT 582.220000 2733.000000 583.320000 2733.480000 ;
+ RECT 582.220000 2727.560000 583.320000 2728.040000 ;
+ RECT 582.220000 2722.120000 583.320000 2722.600000 ;
+ RECT 582.220000 2700.360000 583.320000 2700.840000 ;
+ RECT 582.220000 2705.800000 583.320000 2706.280000 ;
+ RECT 582.220000 2711.240000 583.320000 2711.720000 ;
+ RECT 582.220000 2716.680000 583.320000 2717.160000 ;
+ RECT 636.530000 2689.480000 637.530000 2689.960000 ;
+ RECT 636.530000 2694.920000 637.530000 2695.400000 ;
+ RECT 627.220000 2694.920000 628.320000 2695.400000 ;
+ RECT 627.220000 2689.480000 628.320000 2689.960000 ;
+ RECT 627.220000 2684.040000 628.320000 2684.520000 ;
+ RECT 627.220000 2678.600000 628.320000 2679.080000 ;
+ RECT 636.530000 2684.040000 637.530000 2684.520000 ;
+ RECT 636.530000 2678.600000 637.530000 2679.080000 ;
+ RECT 636.530000 2662.280000 637.530000 2662.760000 ;
+ RECT 636.530000 2667.720000 637.530000 2668.200000 ;
+ RECT 636.530000 2673.160000 637.530000 2673.640000 ;
+ RECT 627.220000 2667.720000 628.320000 2668.200000 ;
+ RECT 627.220000 2662.280000 628.320000 2662.760000 ;
+ RECT 627.220000 2673.160000 628.320000 2673.640000 ;
+ RECT 627.220000 2656.840000 628.320000 2657.320000 ;
+ RECT 627.220000 2651.400000 628.320000 2651.880000 ;
+ RECT 636.530000 2656.840000 637.530000 2657.320000 ;
+ RECT 636.530000 2651.400000 637.530000 2651.880000 ;
+ RECT 582.220000 2694.920000 583.320000 2695.400000 ;
+ RECT 582.220000 2689.480000 583.320000 2689.960000 ;
+ RECT 582.220000 2684.040000 583.320000 2684.520000 ;
+ RECT 582.220000 2678.600000 583.320000 2679.080000 ;
+ RECT 582.220000 2667.720000 583.320000 2668.200000 ;
+ RECT 582.220000 2662.280000 583.320000 2662.760000 ;
+ RECT 582.220000 2656.840000 583.320000 2657.320000 ;
+ RECT 582.220000 2651.400000 583.320000 2651.880000 ;
+ RECT 582.220000 2673.160000 583.320000 2673.640000 ;
+ RECT 537.220000 2738.440000 538.320000 2738.920000 ;
+ RECT 537.220000 2733.000000 538.320000 2733.480000 ;
+ RECT 537.220000 2727.560000 538.320000 2728.040000 ;
+ RECT 492.220000 2738.440000 493.320000 2738.920000 ;
+ RECT 492.220000 2733.000000 493.320000 2733.480000 ;
+ RECT 492.220000 2727.560000 493.320000 2728.040000 ;
+ RECT 537.220000 2711.240000 538.320000 2711.720000 ;
+ RECT 537.220000 2705.800000 538.320000 2706.280000 ;
+ RECT 537.220000 2700.360000 538.320000 2700.840000 ;
+ RECT 537.220000 2716.680000 538.320000 2717.160000 ;
+ RECT 537.220000 2722.120000 538.320000 2722.600000 ;
+ RECT 492.220000 2722.120000 493.320000 2722.600000 ;
+ RECT 492.220000 2711.240000 493.320000 2711.720000 ;
+ RECT 492.220000 2705.800000 493.320000 2706.280000 ;
+ RECT 492.220000 2700.360000 493.320000 2700.840000 ;
+ RECT 492.220000 2716.680000 493.320000 2717.160000 ;
+ RECT 447.220000 2738.440000 448.320000 2738.920000 ;
+ RECT 443.090000 2738.440000 444.090000 2738.920000 ;
+ RECT 443.090000 2733.000000 444.090000 2733.480000 ;
+ RECT 447.220000 2733.000000 448.320000 2733.480000 ;
+ RECT 447.220000 2727.560000 448.320000 2728.040000 ;
+ RECT 443.090000 2727.560000 444.090000 2728.040000 ;
+ RECT 447.220000 2722.120000 448.320000 2722.600000 ;
+ RECT 443.090000 2722.120000 444.090000 2722.600000 ;
+ RECT 447.220000 2716.680000 448.320000 2717.160000 ;
+ RECT 443.090000 2716.680000 444.090000 2717.160000 ;
+ RECT 447.220000 2705.800000 448.320000 2706.280000 ;
+ RECT 443.090000 2705.800000 444.090000 2706.280000 ;
+ RECT 447.220000 2700.360000 448.320000 2700.840000 ;
+ RECT 443.090000 2700.360000 444.090000 2700.840000 ;
+ RECT 447.220000 2711.240000 448.320000 2711.720000 ;
+ RECT 443.090000 2711.240000 444.090000 2711.720000 ;
+ RECT 537.220000 2694.920000 538.320000 2695.400000 ;
+ RECT 537.220000 2689.480000 538.320000 2689.960000 ;
+ RECT 537.220000 2684.040000 538.320000 2684.520000 ;
+ RECT 537.220000 2678.600000 538.320000 2679.080000 ;
+ RECT 492.220000 2694.920000 493.320000 2695.400000 ;
+ RECT 492.220000 2689.480000 493.320000 2689.960000 ;
+ RECT 492.220000 2684.040000 493.320000 2684.520000 ;
+ RECT 492.220000 2678.600000 493.320000 2679.080000 ;
+ RECT 537.220000 2667.720000 538.320000 2668.200000 ;
+ RECT 537.220000 2651.400000 538.320000 2651.880000 ;
+ RECT 537.220000 2656.840000 538.320000 2657.320000 ;
+ RECT 537.220000 2662.280000 538.320000 2662.760000 ;
+ RECT 537.220000 2673.160000 538.320000 2673.640000 ;
+ RECT 492.220000 2651.400000 493.320000 2651.880000 ;
+ RECT 492.220000 2656.840000 493.320000 2657.320000 ;
+ RECT 492.220000 2662.280000 493.320000 2662.760000 ;
+ RECT 492.220000 2667.720000 493.320000 2668.200000 ;
+ RECT 492.220000 2673.160000 493.320000 2673.640000 ;
+ RECT 447.220000 2694.920000 448.320000 2695.400000 ;
+ RECT 443.090000 2694.920000 444.090000 2695.400000 ;
+ RECT 447.220000 2689.480000 448.320000 2689.960000 ;
+ RECT 443.090000 2689.480000 444.090000 2689.960000 ;
+ RECT 447.220000 2684.040000 448.320000 2684.520000 ;
+ RECT 443.090000 2684.040000 444.090000 2684.520000 ;
+ RECT 447.220000 2678.600000 448.320000 2679.080000 ;
+ RECT 443.090000 2678.600000 444.090000 2679.080000 ;
+ RECT 447.220000 2673.160000 448.320000 2673.640000 ;
+ RECT 447.220000 2667.720000 448.320000 2668.200000 ;
+ RECT 443.090000 2673.160000 444.090000 2673.640000 ;
+ RECT 443.090000 2667.720000 444.090000 2668.200000 ;
+ RECT 447.220000 2662.280000 448.320000 2662.760000 ;
+ RECT 443.090000 2662.280000 444.090000 2662.760000 ;
+ RECT 447.220000 2656.840000 448.320000 2657.320000 ;
+ RECT 443.090000 2656.840000 444.090000 2657.320000 ;
+ RECT 447.220000 2651.400000 448.320000 2651.880000 ;
+ RECT 443.090000 2651.400000 444.090000 2651.880000 ;
+ RECT 627.220000 2645.960000 628.320000 2646.440000 ;
+ RECT 627.220000 2640.520000 628.320000 2641.000000 ;
+ RECT 636.530000 2645.960000 637.530000 2646.440000 ;
+ RECT 636.530000 2640.520000 637.530000 2641.000000 ;
+ RECT 636.530000 2624.200000 637.530000 2624.680000 ;
+ RECT 636.530000 2629.640000 637.530000 2630.120000 ;
+ RECT 636.530000 2635.080000 637.530000 2635.560000 ;
+ RECT 627.220000 2635.080000 628.320000 2635.560000 ;
+ RECT 627.220000 2629.640000 628.320000 2630.120000 ;
+ RECT 627.220000 2624.200000 628.320000 2624.680000 ;
+ RECT 627.220000 2613.320000 628.320000 2613.800000 ;
+ RECT 627.220000 2618.760000 628.320000 2619.240000 ;
+ RECT 636.530000 2618.760000 637.530000 2619.240000 ;
+ RECT 636.530000 2613.320000 637.530000 2613.800000 ;
+ RECT 636.530000 2602.440000 637.530000 2602.920000 ;
+ RECT 636.530000 2607.880000 637.530000 2608.360000 ;
+ RECT 627.220000 2602.440000 628.320000 2602.920000 ;
+ RECT 627.220000 2607.880000 628.320000 2608.360000 ;
+ RECT 582.220000 2645.960000 583.320000 2646.440000 ;
+ RECT 582.220000 2640.520000 583.320000 2641.000000 ;
+ RECT 582.220000 2635.080000 583.320000 2635.560000 ;
+ RECT 582.220000 2629.640000 583.320000 2630.120000 ;
+ RECT 582.220000 2624.200000 583.320000 2624.680000 ;
+ RECT 582.220000 2602.440000 583.320000 2602.920000 ;
+ RECT 582.220000 2607.880000 583.320000 2608.360000 ;
+ RECT 582.220000 2613.320000 583.320000 2613.800000 ;
+ RECT 582.220000 2618.760000 583.320000 2619.240000 ;
+ RECT 627.220000 2597.000000 628.320000 2597.480000 ;
+ RECT 627.220000 2591.560000 628.320000 2592.040000 ;
+ RECT 636.530000 2597.000000 637.530000 2597.480000 ;
+ RECT 636.530000 2591.560000 637.530000 2592.040000 ;
+ RECT 627.220000 2580.680000 628.320000 2581.160000 ;
+ RECT 627.220000 2575.240000 628.320000 2575.720000 ;
+ RECT 636.530000 2580.680000 637.530000 2581.160000 ;
+ RECT 636.530000 2575.240000 637.530000 2575.720000 ;
+ RECT 627.220000 2586.120000 628.320000 2586.600000 ;
+ RECT 636.530000 2586.120000 637.530000 2586.600000 ;
+ RECT 636.530000 2564.360000 637.530000 2564.840000 ;
+ RECT 636.530000 2569.800000 637.530000 2570.280000 ;
+ RECT 627.220000 2569.800000 628.320000 2570.280000 ;
+ RECT 627.220000 2564.360000 628.320000 2564.840000 ;
+ RECT 627.220000 2558.920000 628.320000 2559.400000 ;
+ RECT 627.220000 2553.480000 628.320000 2553.960000 ;
+ RECT 636.530000 2558.920000 637.530000 2559.400000 ;
+ RECT 636.530000 2553.480000 637.530000 2553.960000 ;
+ RECT 582.220000 2597.000000 583.320000 2597.480000 ;
+ RECT 582.220000 2591.560000 583.320000 2592.040000 ;
+ RECT 582.220000 2586.120000 583.320000 2586.600000 ;
+ RECT 582.220000 2580.680000 583.320000 2581.160000 ;
+ RECT 582.220000 2575.240000 583.320000 2575.720000 ;
+ RECT 582.220000 2569.800000 583.320000 2570.280000 ;
+ RECT 582.220000 2564.360000 583.320000 2564.840000 ;
+ RECT 582.220000 2558.920000 583.320000 2559.400000 ;
+ RECT 582.220000 2553.480000 583.320000 2553.960000 ;
+ RECT 537.220000 2645.960000 538.320000 2646.440000 ;
+ RECT 537.220000 2640.520000 538.320000 2641.000000 ;
+ RECT 537.220000 2635.080000 538.320000 2635.560000 ;
+ RECT 537.220000 2629.640000 538.320000 2630.120000 ;
+ RECT 537.220000 2624.200000 538.320000 2624.680000 ;
+ RECT 492.220000 2645.960000 493.320000 2646.440000 ;
+ RECT 492.220000 2640.520000 493.320000 2641.000000 ;
+ RECT 492.220000 2635.080000 493.320000 2635.560000 ;
+ RECT 492.220000 2629.640000 493.320000 2630.120000 ;
+ RECT 492.220000 2624.200000 493.320000 2624.680000 ;
+ RECT 537.220000 2618.760000 538.320000 2619.240000 ;
+ RECT 537.220000 2613.320000 538.320000 2613.800000 ;
+ RECT 537.220000 2607.880000 538.320000 2608.360000 ;
+ RECT 537.220000 2602.440000 538.320000 2602.920000 ;
+ RECT 492.220000 2613.320000 493.320000 2613.800000 ;
+ RECT 492.220000 2607.880000 493.320000 2608.360000 ;
+ RECT 492.220000 2602.440000 493.320000 2602.920000 ;
+ RECT 492.220000 2618.760000 493.320000 2619.240000 ;
+ RECT 447.220000 2645.960000 448.320000 2646.440000 ;
+ RECT 443.090000 2645.960000 444.090000 2646.440000 ;
+ RECT 447.220000 2640.520000 448.320000 2641.000000 ;
+ RECT 443.090000 2640.520000 444.090000 2641.000000 ;
+ RECT 447.220000 2635.080000 448.320000 2635.560000 ;
+ RECT 443.090000 2635.080000 444.090000 2635.560000 ;
+ RECT 447.220000 2624.200000 448.320000 2624.680000 ;
+ RECT 443.090000 2624.200000 444.090000 2624.680000 ;
+ RECT 443.090000 2629.640000 444.090000 2630.120000 ;
+ RECT 447.220000 2629.640000 448.320000 2630.120000 ;
+ RECT 447.220000 2618.760000 448.320000 2619.240000 ;
+ RECT 443.090000 2618.760000 444.090000 2619.240000 ;
+ RECT 447.220000 2613.320000 448.320000 2613.800000 ;
+ RECT 443.090000 2613.320000 444.090000 2613.800000 ;
+ RECT 447.220000 2607.880000 448.320000 2608.360000 ;
+ RECT 443.090000 2607.880000 444.090000 2608.360000 ;
+ RECT 447.220000 2602.440000 448.320000 2602.920000 ;
+ RECT 443.090000 2602.440000 444.090000 2602.920000 ;
+ RECT 537.220000 2597.000000 538.320000 2597.480000 ;
+ RECT 537.220000 2591.560000 538.320000 2592.040000 ;
+ RECT 537.220000 2586.120000 538.320000 2586.600000 ;
+ RECT 537.220000 2580.680000 538.320000 2581.160000 ;
+ RECT 537.220000 2575.240000 538.320000 2575.720000 ;
+ RECT 492.220000 2597.000000 493.320000 2597.480000 ;
+ RECT 492.220000 2591.560000 493.320000 2592.040000 ;
+ RECT 492.220000 2586.120000 493.320000 2586.600000 ;
+ RECT 492.220000 2580.680000 493.320000 2581.160000 ;
+ RECT 492.220000 2575.240000 493.320000 2575.720000 ;
+ RECT 537.220000 2553.480000 538.320000 2553.960000 ;
+ RECT 537.220000 2558.920000 538.320000 2559.400000 ;
+ RECT 537.220000 2564.360000 538.320000 2564.840000 ;
+ RECT 537.220000 2569.800000 538.320000 2570.280000 ;
+ RECT 492.220000 2553.480000 493.320000 2553.960000 ;
+ RECT 492.220000 2558.920000 493.320000 2559.400000 ;
+ RECT 492.220000 2564.360000 493.320000 2564.840000 ;
+ RECT 492.220000 2569.800000 493.320000 2570.280000 ;
+ RECT 447.220000 2597.000000 448.320000 2597.480000 ;
+ RECT 443.090000 2597.000000 444.090000 2597.480000 ;
+ RECT 447.220000 2591.560000 448.320000 2592.040000 ;
+ RECT 443.090000 2591.560000 444.090000 2592.040000 ;
+ RECT 447.220000 2580.680000 448.320000 2581.160000 ;
+ RECT 443.090000 2580.680000 444.090000 2581.160000 ;
+ RECT 447.220000 2575.240000 448.320000 2575.720000 ;
+ RECT 443.090000 2575.240000 444.090000 2575.720000 ;
+ RECT 447.220000 2586.120000 448.320000 2586.600000 ;
+ RECT 443.090000 2586.120000 444.090000 2586.600000 ;
+ RECT 447.220000 2569.800000 448.320000 2570.280000 ;
+ RECT 443.090000 2569.800000 444.090000 2570.280000 ;
+ RECT 447.220000 2564.360000 448.320000 2564.840000 ;
+ RECT 443.090000 2564.360000 444.090000 2564.840000 ;
+ RECT 447.220000 2558.920000 448.320000 2559.400000 ;
+ RECT 447.220000 2553.480000 448.320000 2553.960000 ;
+ RECT 443.090000 2558.920000 444.090000 2559.400000 ;
+ RECT 443.090000 2553.480000 444.090000 2553.960000 ;
+ RECT 440.260000 2743.840000 640.360000 2744.840000 ;
+ RECT 440.260000 2551.470000 640.360000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 2548.620000 444.090000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 2747.880000 444.090000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 2548.620000 637.530000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 2747.880000 637.530000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2551.470000 441.260000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2551.470000 640.360000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2743.840000 441.260000 2744.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2743.840000 640.360000 2744.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 2351.210000 628.320000 2544.580000 ;
+ RECT 582.220000 2351.210000 583.320000 2544.580000 ;
+ RECT 636.530000 2348.360000 637.530000 2548.620000 ;
+ RECT 537.220000 2351.210000 538.320000 2544.580000 ;
+ RECT 492.220000 2351.210000 493.320000 2544.580000 ;
+ RECT 447.220000 2351.210000 448.320000 2544.580000 ;
+ RECT 443.090000 2348.360000 444.090000 2548.620000 ;
+ LAYER met3 ;
+ RECT 627.220000 2538.180000 628.320000 2538.660000 ;
+ RECT 636.530000 2538.180000 637.530000 2538.660000 ;
+ RECT 636.530000 2527.300000 637.530000 2527.780000 ;
+ RECT 636.530000 2532.740000 637.530000 2533.220000 ;
+ RECT 627.220000 2532.740000 628.320000 2533.220000 ;
+ RECT 627.220000 2527.300000 628.320000 2527.780000 ;
+ RECT 627.220000 2521.860000 628.320000 2522.340000 ;
+ RECT 627.220000 2516.420000 628.320000 2516.900000 ;
+ RECT 636.530000 2521.860000 637.530000 2522.340000 ;
+ RECT 636.530000 2516.420000 637.530000 2516.900000 ;
+ RECT 627.220000 2500.100000 628.320000 2500.580000 ;
+ RECT 627.220000 2505.540000 628.320000 2506.020000 ;
+ RECT 636.530000 2505.540000 637.530000 2506.020000 ;
+ RECT 636.530000 2500.100000 637.530000 2500.580000 ;
+ RECT 627.220000 2510.980000 628.320000 2511.460000 ;
+ RECT 636.530000 2510.980000 637.530000 2511.460000 ;
+ RECT 582.220000 2538.180000 583.320000 2538.660000 ;
+ RECT 582.220000 2532.740000 583.320000 2533.220000 ;
+ RECT 582.220000 2527.300000 583.320000 2527.780000 ;
+ RECT 582.220000 2521.860000 583.320000 2522.340000 ;
+ RECT 582.220000 2500.100000 583.320000 2500.580000 ;
+ RECT 582.220000 2505.540000 583.320000 2506.020000 ;
+ RECT 582.220000 2510.980000 583.320000 2511.460000 ;
+ RECT 582.220000 2516.420000 583.320000 2516.900000 ;
+ RECT 636.530000 2489.220000 637.530000 2489.700000 ;
+ RECT 636.530000 2494.660000 637.530000 2495.140000 ;
+ RECT 627.220000 2494.660000 628.320000 2495.140000 ;
+ RECT 627.220000 2489.220000 628.320000 2489.700000 ;
+ RECT 627.220000 2483.780000 628.320000 2484.260000 ;
+ RECT 627.220000 2478.340000 628.320000 2478.820000 ;
+ RECT 636.530000 2483.780000 637.530000 2484.260000 ;
+ RECT 636.530000 2478.340000 637.530000 2478.820000 ;
+ RECT 636.530000 2462.020000 637.530000 2462.500000 ;
+ RECT 636.530000 2467.460000 637.530000 2467.940000 ;
+ RECT 636.530000 2472.900000 637.530000 2473.380000 ;
+ RECT 627.220000 2467.460000 628.320000 2467.940000 ;
+ RECT 627.220000 2462.020000 628.320000 2462.500000 ;
+ RECT 627.220000 2472.900000 628.320000 2473.380000 ;
+ RECT 627.220000 2456.580000 628.320000 2457.060000 ;
+ RECT 627.220000 2451.140000 628.320000 2451.620000 ;
+ RECT 636.530000 2456.580000 637.530000 2457.060000 ;
+ RECT 636.530000 2451.140000 637.530000 2451.620000 ;
+ RECT 582.220000 2494.660000 583.320000 2495.140000 ;
+ RECT 582.220000 2489.220000 583.320000 2489.700000 ;
+ RECT 582.220000 2483.780000 583.320000 2484.260000 ;
+ RECT 582.220000 2478.340000 583.320000 2478.820000 ;
+ RECT 582.220000 2467.460000 583.320000 2467.940000 ;
+ RECT 582.220000 2462.020000 583.320000 2462.500000 ;
+ RECT 582.220000 2456.580000 583.320000 2457.060000 ;
+ RECT 582.220000 2451.140000 583.320000 2451.620000 ;
+ RECT 582.220000 2472.900000 583.320000 2473.380000 ;
+ RECT 537.220000 2538.180000 538.320000 2538.660000 ;
+ RECT 537.220000 2532.740000 538.320000 2533.220000 ;
+ RECT 537.220000 2527.300000 538.320000 2527.780000 ;
+ RECT 492.220000 2538.180000 493.320000 2538.660000 ;
+ RECT 492.220000 2532.740000 493.320000 2533.220000 ;
+ RECT 492.220000 2527.300000 493.320000 2527.780000 ;
+ RECT 537.220000 2510.980000 538.320000 2511.460000 ;
+ RECT 537.220000 2505.540000 538.320000 2506.020000 ;
+ RECT 537.220000 2500.100000 538.320000 2500.580000 ;
+ RECT 537.220000 2516.420000 538.320000 2516.900000 ;
+ RECT 537.220000 2521.860000 538.320000 2522.340000 ;
+ RECT 492.220000 2521.860000 493.320000 2522.340000 ;
+ RECT 492.220000 2510.980000 493.320000 2511.460000 ;
+ RECT 492.220000 2505.540000 493.320000 2506.020000 ;
+ RECT 492.220000 2500.100000 493.320000 2500.580000 ;
+ RECT 492.220000 2516.420000 493.320000 2516.900000 ;
+ RECT 447.220000 2538.180000 448.320000 2538.660000 ;
+ RECT 443.090000 2538.180000 444.090000 2538.660000 ;
+ RECT 443.090000 2532.740000 444.090000 2533.220000 ;
+ RECT 447.220000 2532.740000 448.320000 2533.220000 ;
+ RECT 447.220000 2527.300000 448.320000 2527.780000 ;
+ RECT 443.090000 2527.300000 444.090000 2527.780000 ;
+ RECT 447.220000 2521.860000 448.320000 2522.340000 ;
+ RECT 443.090000 2521.860000 444.090000 2522.340000 ;
+ RECT 447.220000 2516.420000 448.320000 2516.900000 ;
+ RECT 443.090000 2516.420000 444.090000 2516.900000 ;
+ RECT 447.220000 2505.540000 448.320000 2506.020000 ;
+ RECT 443.090000 2505.540000 444.090000 2506.020000 ;
+ RECT 447.220000 2500.100000 448.320000 2500.580000 ;
+ RECT 443.090000 2500.100000 444.090000 2500.580000 ;
+ RECT 447.220000 2510.980000 448.320000 2511.460000 ;
+ RECT 443.090000 2510.980000 444.090000 2511.460000 ;
+ RECT 537.220000 2494.660000 538.320000 2495.140000 ;
+ RECT 537.220000 2489.220000 538.320000 2489.700000 ;
+ RECT 537.220000 2483.780000 538.320000 2484.260000 ;
+ RECT 537.220000 2478.340000 538.320000 2478.820000 ;
+ RECT 492.220000 2494.660000 493.320000 2495.140000 ;
+ RECT 492.220000 2489.220000 493.320000 2489.700000 ;
+ RECT 492.220000 2483.780000 493.320000 2484.260000 ;
+ RECT 492.220000 2478.340000 493.320000 2478.820000 ;
+ RECT 537.220000 2467.460000 538.320000 2467.940000 ;
+ RECT 537.220000 2451.140000 538.320000 2451.620000 ;
+ RECT 537.220000 2456.580000 538.320000 2457.060000 ;
+ RECT 537.220000 2462.020000 538.320000 2462.500000 ;
+ RECT 537.220000 2472.900000 538.320000 2473.380000 ;
+ RECT 492.220000 2451.140000 493.320000 2451.620000 ;
+ RECT 492.220000 2456.580000 493.320000 2457.060000 ;
+ RECT 492.220000 2462.020000 493.320000 2462.500000 ;
+ RECT 492.220000 2467.460000 493.320000 2467.940000 ;
+ RECT 492.220000 2472.900000 493.320000 2473.380000 ;
+ RECT 447.220000 2494.660000 448.320000 2495.140000 ;
+ RECT 443.090000 2494.660000 444.090000 2495.140000 ;
+ RECT 447.220000 2489.220000 448.320000 2489.700000 ;
+ RECT 443.090000 2489.220000 444.090000 2489.700000 ;
+ RECT 447.220000 2483.780000 448.320000 2484.260000 ;
+ RECT 443.090000 2483.780000 444.090000 2484.260000 ;
+ RECT 447.220000 2478.340000 448.320000 2478.820000 ;
+ RECT 443.090000 2478.340000 444.090000 2478.820000 ;
+ RECT 447.220000 2472.900000 448.320000 2473.380000 ;
+ RECT 447.220000 2467.460000 448.320000 2467.940000 ;
+ RECT 443.090000 2472.900000 444.090000 2473.380000 ;
+ RECT 443.090000 2467.460000 444.090000 2467.940000 ;
+ RECT 447.220000 2462.020000 448.320000 2462.500000 ;
+ RECT 443.090000 2462.020000 444.090000 2462.500000 ;
+ RECT 447.220000 2456.580000 448.320000 2457.060000 ;
+ RECT 443.090000 2456.580000 444.090000 2457.060000 ;
+ RECT 447.220000 2451.140000 448.320000 2451.620000 ;
+ RECT 443.090000 2451.140000 444.090000 2451.620000 ;
+ RECT 627.220000 2445.700000 628.320000 2446.180000 ;
+ RECT 627.220000 2440.260000 628.320000 2440.740000 ;
+ RECT 636.530000 2445.700000 637.530000 2446.180000 ;
+ RECT 636.530000 2440.260000 637.530000 2440.740000 ;
+ RECT 636.530000 2423.940000 637.530000 2424.420000 ;
+ RECT 636.530000 2429.380000 637.530000 2429.860000 ;
+ RECT 636.530000 2434.820000 637.530000 2435.300000 ;
+ RECT 627.220000 2434.820000 628.320000 2435.300000 ;
+ RECT 627.220000 2429.380000 628.320000 2429.860000 ;
+ RECT 627.220000 2423.940000 628.320000 2424.420000 ;
+ RECT 627.220000 2413.060000 628.320000 2413.540000 ;
+ RECT 627.220000 2418.500000 628.320000 2418.980000 ;
+ RECT 636.530000 2418.500000 637.530000 2418.980000 ;
+ RECT 636.530000 2413.060000 637.530000 2413.540000 ;
+ RECT 636.530000 2402.180000 637.530000 2402.660000 ;
+ RECT 636.530000 2407.620000 637.530000 2408.100000 ;
+ RECT 627.220000 2402.180000 628.320000 2402.660000 ;
+ RECT 627.220000 2407.620000 628.320000 2408.100000 ;
+ RECT 582.220000 2445.700000 583.320000 2446.180000 ;
+ RECT 582.220000 2440.260000 583.320000 2440.740000 ;
+ RECT 582.220000 2434.820000 583.320000 2435.300000 ;
+ RECT 582.220000 2429.380000 583.320000 2429.860000 ;
+ RECT 582.220000 2423.940000 583.320000 2424.420000 ;
+ RECT 582.220000 2402.180000 583.320000 2402.660000 ;
+ RECT 582.220000 2407.620000 583.320000 2408.100000 ;
+ RECT 582.220000 2413.060000 583.320000 2413.540000 ;
+ RECT 582.220000 2418.500000 583.320000 2418.980000 ;
+ RECT 627.220000 2396.740000 628.320000 2397.220000 ;
+ RECT 627.220000 2391.300000 628.320000 2391.780000 ;
+ RECT 636.530000 2396.740000 637.530000 2397.220000 ;
+ RECT 636.530000 2391.300000 637.530000 2391.780000 ;
+ RECT 627.220000 2380.420000 628.320000 2380.900000 ;
+ RECT 627.220000 2374.980000 628.320000 2375.460000 ;
+ RECT 636.530000 2380.420000 637.530000 2380.900000 ;
+ RECT 636.530000 2374.980000 637.530000 2375.460000 ;
+ RECT 627.220000 2385.860000 628.320000 2386.340000 ;
+ RECT 636.530000 2385.860000 637.530000 2386.340000 ;
+ RECT 636.530000 2364.100000 637.530000 2364.580000 ;
+ RECT 636.530000 2369.540000 637.530000 2370.020000 ;
+ RECT 627.220000 2369.540000 628.320000 2370.020000 ;
+ RECT 627.220000 2364.100000 628.320000 2364.580000 ;
+ RECT 627.220000 2358.660000 628.320000 2359.140000 ;
+ RECT 627.220000 2353.220000 628.320000 2353.700000 ;
+ RECT 636.530000 2358.660000 637.530000 2359.140000 ;
+ RECT 636.530000 2353.220000 637.530000 2353.700000 ;
+ RECT 582.220000 2396.740000 583.320000 2397.220000 ;
+ RECT 582.220000 2391.300000 583.320000 2391.780000 ;
+ RECT 582.220000 2385.860000 583.320000 2386.340000 ;
+ RECT 582.220000 2380.420000 583.320000 2380.900000 ;
+ RECT 582.220000 2374.980000 583.320000 2375.460000 ;
+ RECT 582.220000 2369.540000 583.320000 2370.020000 ;
+ RECT 582.220000 2364.100000 583.320000 2364.580000 ;
+ RECT 582.220000 2358.660000 583.320000 2359.140000 ;
+ RECT 582.220000 2353.220000 583.320000 2353.700000 ;
+ RECT 537.220000 2445.700000 538.320000 2446.180000 ;
+ RECT 537.220000 2440.260000 538.320000 2440.740000 ;
+ RECT 537.220000 2434.820000 538.320000 2435.300000 ;
+ RECT 537.220000 2429.380000 538.320000 2429.860000 ;
+ RECT 537.220000 2423.940000 538.320000 2424.420000 ;
+ RECT 492.220000 2445.700000 493.320000 2446.180000 ;
+ RECT 492.220000 2440.260000 493.320000 2440.740000 ;
+ RECT 492.220000 2434.820000 493.320000 2435.300000 ;
+ RECT 492.220000 2429.380000 493.320000 2429.860000 ;
+ RECT 492.220000 2423.940000 493.320000 2424.420000 ;
+ RECT 537.220000 2418.500000 538.320000 2418.980000 ;
+ RECT 537.220000 2413.060000 538.320000 2413.540000 ;
+ RECT 537.220000 2407.620000 538.320000 2408.100000 ;
+ RECT 537.220000 2402.180000 538.320000 2402.660000 ;
+ RECT 492.220000 2413.060000 493.320000 2413.540000 ;
+ RECT 492.220000 2407.620000 493.320000 2408.100000 ;
+ RECT 492.220000 2402.180000 493.320000 2402.660000 ;
+ RECT 492.220000 2418.500000 493.320000 2418.980000 ;
+ RECT 447.220000 2445.700000 448.320000 2446.180000 ;
+ RECT 443.090000 2445.700000 444.090000 2446.180000 ;
+ RECT 447.220000 2440.260000 448.320000 2440.740000 ;
+ RECT 443.090000 2440.260000 444.090000 2440.740000 ;
+ RECT 447.220000 2434.820000 448.320000 2435.300000 ;
+ RECT 443.090000 2434.820000 444.090000 2435.300000 ;
+ RECT 447.220000 2423.940000 448.320000 2424.420000 ;
+ RECT 443.090000 2423.940000 444.090000 2424.420000 ;
+ RECT 443.090000 2429.380000 444.090000 2429.860000 ;
+ RECT 447.220000 2429.380000 448.320000 2429.860000 ;
+ RECT 447.220000 2418.500000 448.320000 2418.980000 ;
+ RECT 443.090000 2418.500000 444.090000 2418.980000 ;
+ RECT 447.220000 2413.060000 448.320000 2413.540000 ;
+ RECT 443.090000 2413.060000 444.090000 2413.540000 ;
+ RECT 447.220000 2407.620000 448.320000 2408.100000 ;
+ RECT 443.090000 2407.620000 444.090000 2408.100000 ;
+ RECT 447.220000 2402.180000 448.320000 2402.660000 ;
+ RECT 443.090000 2402.180000 444.090000 2402.660000 ;
+ RECT 537.220000 2396.740000 538.320000 2397.220000 ;
+ RECT 537.220000 2391.300000 538.320000 2391.780000 ;
+ RECT 537.220000 2385.860000 538.320000 2386.340000 ;
+ RECT 537.220000 2380.420000 538.320000 2380.900000 ;
+ RECT 537.220000 2374.980000 538.320000 2375.460000 ;
+ RECT 492.220000 2396.740000 493.320000 2397.220000 ;
+ RECT 492.220000 2391.300000 493.320000 2391.780000 ;
+ RECT 492.220000 2385.860000 493.320000 2386.340000 ;
+ RECT 492.220000 2380.420000 493.320000 2380.900000 ;
+ RECT 492.220000 2374.980000 493.320000 2375.460000 ;
+ RECT 537.220000 2353.220000 538.320000 2353.700000 ;
+ RECT 537.220000 2358.660000 538.320000 2359.140000 ;
+ RECT 537.220000 2364.100000 538.320000 2364.580000 ;
+ RECT 537.220000 2369.540000 538.320000 2370.020000 ;
+ RECT 492.220000 2353.220000 493.320000 2353.700000 ;
+ RECT 492.220000 2358.660000 493.320000 2359.140000 ;
+ RECT 492.220000 2364.100000 493.320000 2364.580000 ;
+ RECT 492.220000 2369.540000 493.320000 2370.020000 ;
+ RECT 447.220000 2396.740000 448.320000 2397.220000 ;
+ RECT 443.090000 2396.740000 444.090000 2397.220000 ;
+ RECT 447.220000 2391.300000 448.320000 2391.780000 ;
+ RECT 443.090000 2391.300000 444.090000 2391.780000 ;
+ RECT 447.220000 2380.420000 448.320000 2380.900000 ;
+ RECT 443.090000 2380.420000 444.090000 2380.900000 ;
+ RECT 447.220000 2374.980000 448.320000 2375.460000 ;
+ RECT 443.090000 2374.980000 444.090000 2375.460000 ;
+ RECT 447.220000 2385.860000 448.320000 2386.340000 ;
+ RECT 443.090000 2385.860000 444.090000 2386.340000 ;
+ RECT 447.220000 2369.540000 448.320000 2370.020000 ;
+ RECT 443.090000 2369.540000 444.090000 2370.020000 ;
+ RECT 447.220000 2364.100000 448.320000 2364.580000 ;
+ RECT 443.090000 2364.100000 444.090000 2364.580000 ;
+ RECT 447.220000 2358.660000 448.320000 2359.140000 ;
+ RECT 447.220000 2353.220000 448.320000 2353.700000 ;
+ RECT 443.090000 2358.660000 444.090000 2359.140000 ;
+ RECT 443.090000 2353.220000 444.090000 2353.700000 ;
+ RECT 440.260000 2543.580000 640.360000 2544.580000 ;
+ RECT 440.260000 2351.210000 640.360000 2352.210000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 2348.360000 444.090000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 2547.620000 444.090000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 2348.360000 637.530000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 2547.620000 637.530000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2351.210000 441.260000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2351.210000 640.360000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2543.580000 441.260000 2544.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2543.580000 640.360000 2544.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 2150.950000 628.320000 2344.320000 ;
+ RECT 582.220000 2150.950000 583.320000 2344.320000 ;
+ RECT 636.530000 2148.100000 637.530000 2348.360000 ;
+ RECT 537.220000 2150.950000 538.320000 2344.320000 ;
+ RECT 492.220000 2150.950000 493.320000 2344.320000 ;
+ RECT 447.220000 2150.950000 448.320000 2344.320000 ;
+ RECT 443.090000 2148.100000 444.090000 2348.360000 ;
+ LAYER met3 ;
+ RECT 627.220000 2337.920000 628.320000 2338.400000 ;
+ RECT 636.530000 2337.920000 637.530000 2338.400000 ;
+ RECT 636.530000 2327.040000 637.530000 2327.520000 ;
+ RECT 636.530000 2332.480000 637.530000 2332.960000 ;
+ RECT 627.220000 2332.480000 628.320000 2332.960000 ;
+ RECT 627.220000 2327.040000 628.320000 2327.520000 ;
+ RECT 627.220000 2321.600000 628.320000 2322.080000 ;
+ RECT 627.220000 2316.160000 628.320000 2316.640000 ;
+ RECT 636.530000 2321.600000 637.530000 2322.080000 ;
+ RECT 636.530000 2316.160000 637.530000 2316.640000 ;
+ RECT 627.220000 2299.840000 628.320000 2300.320000 ;
+ RECT 627.220000 2305.280000 628.320000 2305.760000 ;
+ RECT 636.530000 2305.280000 637.530000 2305.760000 ;
+ RECT 636.530000 2299.840000 637.530000 2300.320000 ;
+ RECT 627.220000 2310.720000 628.320000 2311.200000 ;
+ RECT 636.530000 2310.720000 637.530000 2311.200000 ;
+ RECT 582.220000 2337.920000 583.320000 2338.400000 ;
+ RECT 582.220000 2332.480000 583.320000 2332.960000 ;
+ RECT 582.220000 2327.040000 583.320000 2327.520000 ;
+ RECT 582.220000 2321.600000 583.320000 2322.080000 ;
+ RECT 582.220000 2299.840000 583.320000 2300.320000 ;
+ RECT 582.220000 2305.280000 583.320000 2305.760000 ;
+ RECT 582.220000 2310.720000 583.320000 2311.200000 ;
+ RECT 582.220000 2316.160000 583.320000 2316.640000 ;
+ RECT 636.530000 2288.960000 637.530000 2289.440000 ;
+ RECT 636.530000 2294.400000 637.530000 2294.880000 ;
+ RECT 627.220000 2294.400000 628.320000 2294.880000 ;
+ RECT 627.220000 2288.960000 628.320000 2289.440000 ;
+ RECT 627.220000 2283.520000 628.320000 2284.000000 ;
+ RECT 627.220000 2278.080000 628.320000 2278.560000 ;
+ RECT 636.530000 2283.520000 637.530000 2284.000000 ;
+ RECT 636.530000 2278.080000 637.530000 2278.560000 ;
+ RECT 636.530000 2261.760000 637.530000 2262.240000 ;
+ RECT 636.530000 2267.200000 637.530000 2267.680000 ;
+ RECT 636.530000 2272.640000 637.530000 2273.120000 ;
+ RECT 627.220000 2267.200000 628.320000 2267.680000 ;
+ RECT 627.220000 2261.760000 628.320000 2262.240000 ;
+ RECT 627.220000 2272.640000 628.320000 2273.120000 ;
+ RECT 627.220000 2256.320000 628.320000 2256.800000 ;
+ RECT 627.220000 2250.880000 628.320000 2251.360000 ;
+ RECT 636.530000 2256.320000 637.530000 2256.800000 ;
+ RECT 636.530000 2250.880000 637.530000 2251.360000 ;
+ RECT 582.220000 2294.400000 583.320000 2294.880000 ;
+ RECT 582.220000 2288.960000 583.320000 2289.440000 ;
+ RECT 582.220000 2283.520000 583.320000 2284.000000 ;
+ RECT 582.220000 2278.080000 583.320000 2278.560000 ;
+ RECT 582.220000 2267.200000 583.320000 2267.680000 ;
+ RECT 582.220000 2261.760000 583.320000 2262.240000 ;
+ RECT 582.220000 2256.320000 583.320000 2256.800000 ;
+ RECT 582.220000 2250.880000 583.320000 2251.360000 ;
+ RECT 582.220000 2272.640000 583.320000 2273.120000 ;
+ RECT 537.220000 2337.920000 538.320000 2338.400000 ;
+ RECT 537.220000 2332.480000 538.320000 2332.960000 ;
+ RECT 537.220000 2327.040000 538.320000 2327.520000 ;
+ RECT 492.220000 2337.920000 493.320000 2338.400000 ;
+ RECT 492.220000 2332.480000 493.320000 2332.960000 ;
+ RECT 492.220000 2327.040000 493.320000 2327.520000 ;
+ RECT 537.220000 2310.720000 538.320000 2311.200000 ;
+ RECT 537.220000 2305.280000 538.320000 2305.760000 ;
+ RECT 537.220000 2299.840000 538.320000 2300.320000 ;
+ RECT 537.220000 2316.160000 538.320000 2316.640000 ;
+ RECT 537.220000 2321.600000 538.320000 2322.080000 ;
+ RECT 492.220000 2321.600000 493.320000 2322.080000 ;
+ RECT 492.220000 2310.720000 493.320000 2311.200000 ;
+ RECT 492.220000 2305.280000 493.320000 2305.760000 ;
+ RECT 492.220000 2299.840000 493.320000 2300.320000 ;
+ RECT 492.220000 2316.160000 493.320000 2316.640000 ;
+ RECT 447.220000 2337.920000 448.320000 2338.400000 ;
+ RECT 443.090000 2337.920000 444.090000 2338.400000 ;
+ RECT 443.090000 2332.480000 444.090000 2332.960000 ;
+ RECT 447.220000 2332.480000 448.320000 2332.960000 ;
+ RECT 447.220000 2327.040000 448.320000 2327.520000 ;
+ RECT 443.090000 2327.040000 444.090000 2327.520000 ;
+ RECT 447.220000 2321.600000 448.320000 2322.080000 ;
+ RECT 443.090000 2321.600000 444.090000 2322.080000 ;
+ RECT 447.220000 2316.160000 448.320000 2316.640000 ;
+ RECT 443.090000 2316.160000 444.090000 2316.640000 ;
+ RECT 447.220000 2305.280000 448.320000 2305.760000 ;
+ RECT 443.090000 2305.280000 444.090000 2305.760000 ;
+ RECT 447.220000 2299.840000 448.320000 2300.320000 ;
+ RECT 443.090000 2299.840000 444.090000 2300.320000 ;
+ RECT 447.220000 2310.720000 448.320000 2311.200000 ;
+ RECT 443.090000 2310.720000 444.090000 2311.200000 ;
+ RECT 537.220000 2294.400000 538.320000 2294.880000 ;
+ RECT 537.220000 2288.960000 538.320000 2289.440000 ;
+ RECT 537.220000 2283.520000 538.320000 2284.000000 ;
+ RECT 537.220000 2278.080000 538.320000 2278.560000 ;
+ RECT 492.220000 2294.400000 493.320000 2294.880000 ;
+ RECT 492.220000 2288.960000 493.320000 2289.440000 ;
+ RECT 492.220000 2283.520000 493.320000 2284.000000 ;
+ RECT 492.220000 2278.080000 493.320000 2278.560000 ;
+ RECT 537.220000 2267.200000 538.320000 2267.680000 ;
+ RECT 537.220000 2250.880000 538.320000 2251.360000 ;
+ RECT 537.220000 2256.320000 538.320000 2256.800000 ;
+ RECT 537.220000 2261.760000 538.320000 2262.240000 ;
+ RECT 537.220000 2272.640000 538.320000 2273.120000 ;
+ RECT 492.220000 2250.880000 493.320000 2251.360000 ;
+ RECT 492.220000 2256.320000 493.320000 2256.800000 ;
+ RECT 492.220000 2261.760000 493.320000 2262.240000 ;
+ RECT 492.220000 2267.200000 493.320000 2267.680000 ;
+ RECT 492.220000 2272.640000 493.320000 2273.120000 ;
+ RECT 447.220000 2294.400000 448.320000 2294.880000 ;
+ RECT 443.090000 2294.400000 444.090000 2294.880000 ;
+ RECT 447.220000 2288.960000 448.320000 2289.440000 ;
+ RECT 443.090000 2288.960000 444.090000 2289.440000 ;
+ RECT 447.220000 2283.520000 448.320000 2284.000000 ;
+ RECT 443.090000 2283.520000 444.090000 2284.000000 ;
+ RECT 447.220000 2278.080000 448.320000 2278.560000 ;
+ RECT 443.090000 2278.080000 444.090000 2278.560000 ;
+ RECT 447.220000 2272.640000 448.320000 2273.120000 ;
+ RECT 447.220000 2267.200000 448.320000 2267.680000 ;
+ RECT 443.090000 2272.640000 444.090000 2273.120000 ;
+ RECT 443.090000 2267.200000 444.090000 2267.680000 ;
+ RECT 447.220000 2261.760000 448.320000 2262.240000 ;
+ RECT 443.090000 2261.760000 444.090000 2262.240000 ;
+ RECT 447.220000 2256.320000 448.320000 2256.800000 ;
+ RECT 443.090000 2256.320000 444.090000 2256.800000 ;
+ RECT 447.220000 2250.880000 448.320000 2251.360000 ;
+ RECT 443.090000 2250.880000 444.090000 2251.360000 ;
+ RECT 627.220000 2245.440000 628.320000 2245.920000 ;
+ RECT 627.220000 2240.000000 628.320000 2240.480000 ;
+ RECT 636.530000 2245.440000 637.530000 2245.920000 ;
+ RECT 636.530000 2240.000000 637.530000 2240.480000 ;
+ RECT 636.530000 2223.680000 637.530000 2224.160000 ;
+ RECT 636.530000 2229.120000 637.530000 2229.600000 ;
+ RECT 636.530000 2234.560000 637.530000 2235.040000 ;
+ RECT 627.220000 2234.560000 628.320000 2235.040000 ;
+ RECT 627.220000 2229.120000 628.320000 2229.600000 ;
+ RECT 627.220000 2223.680000 628.320000 2224.160000 ;
+ RECT 627.220000 2212.800000 628.320000 2213.280000 ;
+ RECT 627.220000 2218.240000 628.320000 2218.720000 ;
+ RECT 636.530000 2218.240000 637.530000 2218.720000 ;
+ RECT 636.530000 2212.800000 637.530000 2213.280000 ;
+ RECT 636.530000 2201.920000 637.530000 2202.400000 ;
+ RECT 636.530000 2207.360000 637.530000 2207.840000 ;
+ RECT 627.220000 2201.920000 628.320000 2202.400000 ;
+ RECT 627.220000 2207.360000 628.320000 2207.840000 ;
+ RECT 582.220000 2245.440000 583.320000 2245.920000 ;
+ RECT 582.220000 2240.000000 583.320000 2240.480000 ;
+ RECT 582.220000 2234.560000 583.320000 2235.040000 ;
+ RECT 582.220000 2229.120000 583.320000 2229.600000 ;
+ RECT 582.220000 2223.680000 583.320000 2224.160000 ;
+ RECT 582.220000 2201.920000 583.320000 2202.400000 ;
+ RECT 582.220000 2207.360000 583.320000 2207.840000 ;
+ RECT 582.220000 2212.800000 583.320000 2213.280000 ;
+ RECT 582.220000 2218.240000 583.320000 2218.720000 ;
+ RECT 627.220000 2196.480000 628.320000 2196.960000 ;
+ RECT 627.220000 2191.040000 628.320000 2191.520000 ;
+ RECT 636.530000 2196.480000 637.530000 2196.960000 ;
+ RECT 636.530000 2191.040000 637.530000 2191.520000 ;
+ RECT 627.220000 2180.160000 628.320000 2180.640000 ;
+ RECT 627.220000 2174.720000 628.320000 2175.200000 ;
+ RECT 636.530000 2180.160000 637.530000 2180.640000 ;
+ RECT 636.530000 2174.720000 637.530000 2175.200000 ;
+ RECT 627.220000 2185.600000 628.320000 2186.080000 ;
+ RECT 636.530000 2185.600000 637.530000 2186.080000 ;
+ RECT 636.530000 2163.840000 637.530000 2164.320000 ;
+ RECT 636.530000 2169.280000 637.530000 2169.760000 ;
+ RECT 627.220000 2169.280000 628.320000 2169.760000 ;
+ RECT 627.220000 2163.840000 628.320000 2164.320000 ;
+ RECT 627.220000 2158.400000 628.320000 2158.880000 ;
+ RECT 627.220000 2152.960000 628.320000 2153.440000 ;
+ RECT 636.530000 2158.400000 637.530000 2158.880000 ;
+ RECT 636.530000 2152.960000 637.530000 2153.440000 ;
+ RECT 582.220000 2196.480000 583.320000 2196.960000 ;
+ RECT 582.220000 2191.040000 583.320000 2191.520000 ;
+ RECT 582.220000 2185.600000 583.320000 2186.080000 ;
+ RECT 582.220000 2180.160000 583.320000 2180.640000 ;
+ RECT 582.220000 2174.720000 583.320000 2175.200000 ;
+ RECT 582.220000 2169.280000 583.320000 2169.760000 ;
+ RECT 582.220000 2163.840000 583.320000 2164.320000 ;
+ RECT 582.220000 2158.400000 583.320000 2158.880000 ;
+ RECT 582.220000 2152.960000 583.320000 2153.440000 ;
+ RECT 537.220000 2245.440000 538.320000 2245.920000 ;
+ RECT 537.220000 2240.000000 538.320000 2240.480000 ;
+ RECT 537.220000 2234.560000 538.320000 2235.040000 ;
+ RECT 537.220000 2229.120000 538.320000 2229.600000 ;
+ RECT 537.220000 2223.680000 538.320000 2224.160000 ;
+ RECT 492.220000 2245.440000 493.320000 2245.920000 ;
+ RECT 492.220000 2240.000000 493.320000 2240.480000 ;
+ RECT 492.220000 2234.560000 493.320000 2235.040000 ;
+ RECT 492.220000 2229.120000 493.320000 2229.600000 ;
+ RECT 492.220000 2223.680000 493.320000 2224.160000 ;
+ RECT 537.220000 2218.240000 538.320000 2218.720000 ;
+ RECT 537.220000 2212.800000 538.320000 2213.280000 ;
+ RECT 537.220000 2207.360000 538.320000 2207.840000 ;
+ RECT 537.220000 2201.920000 538.320000 2202.400000 ;
+ RECT 492.220000 2212.800000 493.320000 2213.280000 ;
+ RECT 492.220000 2207.360000 493.320000 2207.840000 ;
+ RECT 492.220000 2201.920000 493.320000 2202.400000 ;
+ RECT 492.220000 2218.240000 493.320000 2218.720000 ;
+ RECT 447.220000 2245.440000 448.320000 2245.920000 ;
+ RECT 443.090000 2245.440000 444.090000 2245.920000 ;
+ RECT 447.220000 2240.000000 448.320000 2240.480000 ;
+ RECT 443.090000 2240.000000 444.090000 2240.480000 ;
+ RECT 447.220000 2234.560000 448.320000 2235.040000 ;
+ RECT 443.090000 2234.560000 444.090000 2235.040000 ;
+ RECT 447.220000 2223.680000 448.320000 2224.160000 ;
+ RECT 443.090000 2223.680000 444.090000 2224.160000 ;
+ RECT 443.090000 2229.120000 444.090000 2229.600000 ;
+ RECT 447.220000 2229.120000 448.320000 2229.600000 ;
+ RECT 447.220000 2218.240000 448.320000 2218.720000 ;
+ RECT 443.090000 2218.240000 444.090000 2218.720000 ;
+ RECT 447.220000 2212.800000 448.320000 2213.280000 ;
+ RECT 443.090000 2212.800000 444.090000 2213.280000 ;
+ RECT 447.220000 2207.360000 448.320000 2207.840000 ;
+ RECT 443.090000 2207.360000 444.090000 2207.840000 ;
+ RECT 447.220000 2201.920000 448.320000 2202.400000 ;
+ RECT 443.090000 2201.920000 444.090000 2202.400000 ;
+ RECT 537.220000 2196.480000 538.320000 2196.960000 ;
+ RECT 537.220000 2191.040000 538.320000 2191.520000 ;
+ RECT 537.220000 2185.600000 538.320000 2186.080000 ;
+ RECT 537.220000 2180.160000 538.320000 2180.640000 ;
+ RECT 537.220000 2174.720000 538.320000 2175.200000 ;
+ RECT 492.220000 2196.480000 493.320000 2196.960000 ;
+ RECT 492.220000 2191.040000 493.320000 2191.520000 ;
+ RECT 492.220000 2185.600000 493.320000 2186.080000 ;
+ RECT 492.220000 2180.160000 493.320000 2180.640000 ;
+ RECT 492.220000 2174.720000 493.320000 2175.200000 ;
+ RECT 537.220000 2152.960000 538.320000 2153.440000 ;
+ RECT 537.220000 2158.400000 538.320000 2158.880000 ;
+ RECT 537.220000 2163.840000 538.320000 2164.320000 ;
+ RECT 537.220000 2169.280000 538.320000 2169.760000 ;
+ RECT 492.220000 2152.960000 493.320000 2153.440000 ;
+ RECT 492.220000 2158.400000 493.320000 2158.880000 ;
+ RECT 492.220000 2163.840000 493.320000 2164.320000 ;
+ RECT 492.220000 2169.280000 493.320000 2169.760000 ;
+ RECT 447.220000 2196.480000 448.320000 2196.960000 ;
+ RECT 443.090000 2196.480000 444.090000 2196.960000 ;
+ RECT 447.220000 2191.040000 448.320000 2191.520000 ;
+ RECT 443.090000 2191.040000 444.090000 2191.520000 ;
+ RECT 447.220000 2180.160000 448.320000 2180.640000 ;
+ RECT 443.090000 2180.160000 444.090000 2180.640000 ;
+ RECT 447.220000 2174.720000 448.320000 2175.200000 ;
+ RECT 443.090000 2174.720000 444.090000 2175.200000 ;
+ RECT 447.220000 2185.600000 448.320000 2186.080000 ;
+ RECT 443.090000 2185.600000 444.090000 2186.080000 ;
+ RECT 447.220000 2169.280000 448.320000 2169.760000 ;
+ RECT 443.090000 2169.280000 444.090000 2169.760000 ;
+ RECT 447.220000 2163.840000 448.320000 2164.320000 ;
+ RECT 443.090000 2163.840000 444.090000 2164.320000 ;
+ RECT 447.220000 2158.400000 448.320000 2158.880000 ;
+ RECT 447.220000 2152.960000 448.320000 2153.440000 ;
+ RECT 443.090000 2158.400000 444.090000 2158.880000 ;
+ RECT 443.090000 2152.960000 444.090000 2153.440000 ;
+ RECT 440.260000 2343.320000 640.360000 2344.320000 ;
+ RECT 440.260000 2150.950000 640.360000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 2148.100000 444.090000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 2347.360000 444.090000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 2148.100000 637.530000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 2347.360000 637.530000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2150.950000 441.260000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2150.950000 640.360000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2343.320000 441.260000 2344.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2343.320000 640.360000 2344.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 1950.690000 628.320000 2144.060000 ;
+ RECT 582.220000 1950.690000 583.320000 2144.060000 ;
+ RECT 636.530000 1947.840000 637.530000 2148.100000 ;
+ RECT 537.220000 1950.690000 538.320000 2144.060000 ;
+ RECT 492.220000 1950.690000 493.320000 2144.060000 ;
+ RECT 447.220000 1950.690000 448.320000 2144.060000 ;
+ RECT 443.090000 1947.840000 444.090000 2148.100000 ;
+ LAYER met3 ;
+ RECT 627.220000 2137.660000 628.320000 2138.140000 ;
+ RECT 636.530000 2137.660000 637.530000 2138.140000 ;
+ RECT 636.530000 2126.780000 637.530000 2127.260000 ;
+ RECT 636.530000 2132.220000 637.530000 2132.700000 ;
+ RECT 627.220000 2132.220000 628.320000 2132.700000 ;
+ RECT 627.220000 2126.780000 628.320000 2127.260000 ;
+ RECT 627.220000 2121.340000 628.320000 2121.820000 ;
+ RECT 627.220000 2115.900000 628.320000 2116.380000 ;
+ RECT 636.530000 2121.340000 637.530000 2121.820000 ;
+ RECT 636.530000 2115.900000 637.530000 2116.380000 ;
+ RECT 627.220000 2099.580000 628.320000 2100.060000 ;
+ RECT 627.220000 2105.020000 628.320000 2105.500000 ;
+ RECT 636.530000 2105.020000 637.530000 2105.500000 ;
+ RECT 636.530000 2099.580000 637.530000 2100.060000 ;
+ RECT 627.220000 2110.460000 628.320000 2110.940000 ;
+ RECT 636.530000 2110.460000 637.530000 2110.940000 ;
+ RECT 582.220000 2137.660000 583.320000 2138.140000 ;
+ RECT 582.220000 2132.220000 583.320000 2132.700000 ;
+ RECT 582.220000 2126.780000 583.320000 2127.260000 ;
+ RECT 582.220000 2121.340000 583.320000 2121.820000 ;
+ RECT 582.220000 2099.580000 583.320000 2100.060000 ;
+ RECT 582.220000 2105.020000 583.320000 2105.500000 ;
+ RECT 582.220000 2110.460000 583.320000 2110.940000 ;
+ RECT 582.220000 2115.900000 583.320000 2116.380000 ;
+ RECT 636.530000 2088.700000 637.530000 2089.180000 ;
+ RECT 636.530000 2094.140000 637.530000 2094.620000 ;
+ RECT 627.220000 2094.140000 628.320000 2094.620000 ;
+ RECT 627.220000 2088.700000 628.320000 2089.180000 ;
+ RECT 627.220000 2083.260000 628.320000 2083.740000 ;
+ RECT 627.220000 2077.820000 628.320000 2078.300000 ;
+ RECT 636.530000 2083.260000 637.530000 2083.740000 ;
+ RECT 636.530000 2077.820000 637.530000 2078.300000 ;
+ RECT 636.530000 2061.500000 637.530000 2061.980000 ;
+ RECT 636.530000 2066.940000 637.530000 2067.420000 ;
+ RECT 636.530000 2072.380000 637.530000 2072.860000 ;
+ RECT 627.220000 2066.940000 628.320000 2067.420000 ;
+ RECT 627.220000 2061.500000 628.320000 2061.980000 ;
+ RECT 627.220000 2072.380000 628.320000 2072.860000 ;
+ RECT 627.220000 2056.060000 628.320000 2056.540000 ;
+ RECT 627.220000 2050.620000 628.320000 2051.100000 ;
+ RECT 636.530000 2056.060000 637.530000 2056.540000 ;
+ RECT 636.530000 2050.620000 637.530000 2051.100000 ;
+ RECT 582.220000 2094.140000 583.320000 2094.620000 ;
+ RECT 582.220000 2088.700000 583.320000 2089.180000 ;
+ RECT 582.220000 2083.260000 583.320000 2083.740000 ;
+ RECT 582.220000 2077.820000 583.320000 2078.300000 ;
+ RECT 582.220000 2066.940000 583.320000 2067.420000 ;
+ RECT 582.220000 2061.500000 583.320000 2061.980000 ;
+ RECT 582.220000 2056.060000 583.320000 2056.540000 ;
+ RECT 582.220000 2050.620000 583.320000 2051.100000 ;
+ RECT 582.220000 2072.380000 583.320000 2072.860000 ;
+ RECT 537.220000 2137.660000 538.320000 2138.140000 ;
+ RECT 537.220000 2132.220000 538.320000 2132.700000 ;
+ RECT 537.220000 2126.780000 538.320000 2127.260000 ;
+ RECT 492.220000 2137.660000 493.320000 2138.140000 ;
+ RECT 492.220000 2132.220000 493.320000 2132.700000 ;
+ RECT 492.220000 2126.780000 493.320000 2127.260000 ;
+ RECT 537.220000 2110.460000 538.320000 2110.940000 ;
+ RECT 537.220000 2105.020000 538.320000 2105.500000 ;
+ RECT 537.220000 2099.580000 538.320000 2100.060000 ;
+ RECT 537.220000 2115.900000 538.320000 2116.380000 ;
+ RECT 537.220000 2121.340000 538.320000 2121.820000 ;
+ RECT 492.220000 2121.340000 493.320000 2121.820000 ;
+ RECT 492.220000 2110.460000 493.320000 2110.940000 ;
+ RECT 492.220000 2105.020000 493.320000 2105.500000 ;
+ RECT 492.220000 2099.580000 493.320000 2100.060000 ;
+ RECT 492.220000 2115.900000 493.320000 2116.380000 ;
+ RECT 447.220000 2137.660000 448.320000 2138.140000 ;
+ RECT 443.090000 2137.660000 444.090000 2138.140000 ;
+ RECT 443.090000 2132.220000 444.090000 2132.700000 ;
+ RECT 447.220000 2132.220000 448.320000 2132.700000 ;
+ RECT 447.220000 2126.780000 448.320000 2127.260000 ;
+ RECT 443.090000 2126.780000 444.090000 2127.260000 ;
+ RECT 447.220000 2121.340000 448.320000 2121.820000 ;
+ RECT 443.090000 2121.340000 444.090000 2121.820000 ;
+ RECT 447.220000 2115.900000 448.320000 2116.380000 ;
+ RECT 443.090000 2115.900000 444.090000 2116.380000 ;
+ RECT 447.220000 2105.020000 448.320000 2105.500000 ;
+ RECT 443.090000 2105.020000 444.090000 2105.500000 ;
+ RECT 447.220000 2099.580000 448.320000 2100.060000 ;
+ RECT 443.090000 2099.580000 444.090000 2100.060000 ;
+ RECT 447.220000 2110.460000 448.320000 2110.940000 ;
+ RECT 443.090000 2110.460000 444.090000 2110.940000 ;
+ RECT 537.220000 2094.140000 538.320000 2094.620000 ;
+ RECT 537.220000 2088.700000 538.320000 2089.180000 ;
+ RECT 537.220000 2083.260000 538.320000 2083.740000 ;
+ RECT 537.220000 2077.820000 538.320000 2078.300000 ;
+ RECT 492.220000 2094.140000 493.320000 2094.620000 ;
+ RECT 492.220000 2088.700000 493.320000 2089.180000 ;
+ RECT 492.220000 2083.260000 493.320000 2083.740000 ;
+ RECT 492.220000 2077.820000 493.320000 2078.300000 ;
+ RECT 537.220000 2066.940000 538.320000 2067.420000 ;
+ RECT 537.220000 2050.620000 538.320000 2051.100000 ;
+ RECT 537.220000 2056.060000 538.320000 2056.540000 ;
+ RECT 537.220000 2061.500000 538.320000 2061.980000 ;
+ RECT 537.220000 2072.380000 538.320000 2072.860000 ;
+ RECT 492.220000 2050.620000 493.320000 2051.100000 ;
+ RECT 492.220000 2056.060000 493.320000 2056.540000 ;
+ RECT 492.220000 2061.500000 493.320000 2061.980000 ;
+ RECT 492.220000 2066.940000 493.320000 2067.420000 ;
+ RECT 492.220000 2072.380000 493.320000 2072.860000 ;
+ RECT 447.220000 2094.140000 448.320000 2094.620000 ;
+ RECT 443.090000 2094.140000 444.090000 2094.620000 ;
+ RECT 447.220000 2088.700000 448.320000 2089.180000 ;
+ RECT 443.090000 2088.700000 444.090000 2089.180000 ;
+ RECT 447.220000 2083.260000 448.320000 2083.740000 ;
+ RECT 443.090000 2083.260000 444.090000 2083.740000 ;
+ RECT 447.220000 2077.820000 448.320000 2078.300000 ;
+ RECT 443.090000 2077.820000 444.090000 2078.300000 ;
+ RECT 447.220000 2072.380000 448.320000 2072.860000 ;
+ RECT 447.220000 2066.940000 448.320000 2067.420000 ;
+ RECT 443.090000 2072.380000 444.090000 2072.860000 ;
+ RECT 443.090000 2066.940000 444.090000 2067.420000 ;
+ RECT 447.220000 2061.500000 448.320000 2061.980000 ;
+ RECT 443.090000 2061.500000 444.090000 2061.980000 ;
+ RECT 447.220000 2056.060000 448.320000 2056.540000 ;
+ RECT 443.090000 2056.060000 444.090000 2056.540000 ;
+ RECT 447.220000 2050.620000 448.320000 2051.100000 ;
+ RECT 443.090000 2050.620000 444.090000 2051.100000 ;
+ RECT 627.220000 2045.180000 628.320000 2045.660000 ;
+ RECT 627.220000 2039.740000 628.320000 2040.220000 ;
+ RECT 636.530000 2045.180000 637.530000 2045.660000 ;
+ RECT 636.530000 2039.740000 637.530000 2040.220000 ;
+ RECT 636.530000 2023.420000 637.530000 2023.900000 ;
+ RECT 636.530000 2028.860000 637.530000 2029.340000 ;
+ RECT 636.530000 2034.300000 637.530000 2034.780000 ;
+ RECT 627.220000 2034.300000 628.320000 2034.780000 ;
+ RECT 627.220000 2028.860000 628.320000 2029.340000 ;
+ RECT 627.220000 2023.420000 628.320000 2023.900000 ;
+ RECT 627.220000 2012.540000 628.320000 2013.020000 ;
+ RECT 627.220000 2017.980000 628.320000 2018.460000 ;
+ RECT 636.530000 2017.980000 637.530000 2018.460000 ;
+ RECT 636.530000 2012.540000 637.530000 2013.020000 ;
+ RECT 636.530000 2001.660000 637.530000 2002.140000 ;
+ RECT 636.530000 2007.100000 637.530000 2007.580000 ;
+ RECT 627.220000 2001.660000 628.320000 2002.140000 ;
+ RECT 627.220000 2007.100000 628.320000 2007.580000 ;
+ RECT 582.220000 2045.180000 583.320000 2045.660000 ;
+ RECT 582.220000 2039.740000 583.320000 2040.220000 ;
+ RECT 582.220000 2034.300000 583.320000 2034.780000 ;
+ RECT 582.220000 2028.860000 583.320000 2029.340000 ;
+ RECT 582.220000 2023.420000 583.320000 2023.900000 ;
+ RECT 582.220000 2001.660000 583.320000 2002.140000 ;
+ RECT 582.220000 2007.100000 583.320000 2007.580000 ;
+ RECT 582.220000 2012.540000 583.320000 2013.020000 ;
+ RECT 582.220000 2017.980000 583.320000 2018.460000 ;
+ RECT 627.220000 1996.220000 628.320000 1996.700000 ;
+ RECT 627.220000 1990.780000 628.320000 1991.260000 ;
+ RECT 636.530000 1996.220000 637.530000 1996.700000 ;
+ RECT 636.530000 1990.780000 637.530000 1991.260000 ;
+ RECT 627.220000 1979.900000 628.320000 1980.380000 ;
+ RECT 627.220000 1974.460000 628.320000 1974.940000 ;
+ RECT 636.530000 1979.900000 637.530000 1980.380000 ;
+ RECT 636.530000 1974.460000 637.530000 1974.940000 ;
+ RECT 627.220000 1985.340000 628.320000 1985.820000 ;
+ RECT 636.530000 1985.340000 637.530000 1985.820000 ;
+ RECT 636.530000 1963.580000 637.530000 1964.060000 ;
+ RECT 636.530000 1969.020000 637.530000 1969.500000 ;
+ RECT 627.220000 1969.020000 628.320000 1969.500000 ;
+ RECT 627.220000 1963.580000 628.320000 1964.060000 ;
+ RECT 627.220000 1958.140000 628.320000 1958.620000 ;
+ RECT 627.220000 1952.700000 628.320000 1953.180000 ;
+ RECT 636.530000 1958.140000 637.530000 1958.620000 ;
+ RECT 636.530000 1952.700000 637.530000 1953.180000 ;
+ RECT 582.220000 1996.220000 583.320000 1996.700000 ;
+ RECT 582.220000 1990.780000 583.320000 1991.260000 ;
+ RECT 582.220000 1985.340000 583.320000 1985.820000 ;
+ RECT 582.220000 1979.900000 583.320000 1980.380000 ;
+ RECT 582.220000 1974.460000 583.320000 1974.940000 ;
+ RECT 582.220000 1969.020000 583.320000 1969.500000 ;
+ RECT 582.220000 1963.580000 583.320000 1964.060000 ;
+ RECT 582.220000 1958.140000 583.320000 1958.620000 ;
+ RECT 582.220000 1952.700000 583.320000 1953.180000 ;
+ RECT 537.220000 2045.180000 538.320000 2045.660000 ;
+ RECT 537.220000 2039.740000 538.320000 2040.220000 ;
+ RECT 537.220000 2034.300000 538.320000 2034.780000 ;
+ RECT 537.220000 2028.860000 538.320000 2029.340000 ;
+ RECT 537.220000 2023.420000 538.320000 2023.900000 ;
+ RECT 492.220000 2045.180000 493.320000 2045.660000 ;
+ RECT 492.220000 2039.740000 493.320000 2040.220000 ;
+ RECT 492.220000 2034.300000 493.320000 2034.780000 ;
+ RECT 492.220000 2028.860000 493.320000 2029.340000 ;
+ RECT 492.220000 2023.420000 493.320000 2023.900000 ;
+ RECT 537.220000 2017.980000 538.320000 2018.460000 ;
+ RECT 537.220000 2012.540000 538.320000 2013.020000 ;
+ RECT 537.220000 2007.100000 538.320000 2007.580000 ;
+ RECT 537.220000 2001.660000 538.320000 2002.140000 ;
+ RECT 492.220000 2012.540000 493.320000 2013.020000 ;
+ RECT 492.220000 2007.100000 493.320000 2007.580000 ;
+ RECT 492.220000 2001.660000 493.320000 2002.140000 ;
+ RECT 492.220000 2017.980000 493.320000 2018.460000 ;
+ RECT 447.220000 2045.180000 448.320000 2045.660000 ;
+ RECT 443.090000 2045.180000 444.090000 2045.660000 ;
+ RECT 447.220000 2039.740000 448.320000 2040.220000 ;
+ RECT 443.090000 2039.740000 444.090000 2040.220000 ;
+ RECT 447.220000 2034.300000 448.320000 2034.780000 ;
+ RECT 443.090000 2034.300000 444.090000 2034.780000 ;
+ RECT 447.220000 2023.420000 448.320000 2023.900000 ;
+ RECT 443.090000 2023.420000 444.090000 2023.900000 ;
+ RECT 443.090000 2028.860000 444.090000 2029.340000 ;
+ RECT 447.220000 2028.860000 448.320000 2029.340000 ;
+ RECT 447.220000 2017.980000 448.320000 2018.460000 ;
+ RECT 443.090000 2017.980000 444.090000 2018.460000 ;
+ RECT 447.220000 2012.540000 448.320000 2013.020000 ;
+ RECT 443.090000 2012.540000 444.090000 2013.020000 ;
+ RECT 447.220000 2007.100000 448.320000 2007.580000 ;
+ RECT 443.090000 2007.100000 444.090000 2007.580000 ;
+ RECT 447.220000 2001.660000 448.320000 2002.140000 ;
+ RECT 443.090000 2001.660000 444.090000 2002.140000 ;
+ RECT 537.220000 1996.220000 538.320000 1996.700000 ;
+ RECT 537.220000 1990.780000 538.320000 1991.260000 ;
+ RECT 537.220000 1985.340000 538.320000 1985.820000 ;
+ RECT 537.220000 1979.900000 538.320000 1980.380000 ;
+ RECT 537.220000 1974.460000 538.320000 1974.940000 ;
+ RECT 492.220000 1996.220000 493.320000 1996.700000 ;
+ RECT 492.220000 1990.780000 493.320000 1991.260000 ;
+ RECT 492.220000 1985.340000 493.320000 1985.820000 ;
+ RECT 492.220000 1979.900000 493.320000 1980.380000 ;
+ RECT 492.220000 1974.460000 493.320000 1974.940000 ;
+ RECT 537.220000 1952.700000 538.320000 1953.180000 ;
+ RECT 537.220000 1958.140000 538.320000 1958.620000 ;
+ RECT 537.220000 1963.580000 538.320000 1964.060000 ;
+ RECT 537.220000 1969.020000 538.320000 1969.500000 ;
+ RECT 492.220000 1952.700000 493.320000 1953.180000 ;
+ RECT 492.220000 1958.140000 493.320000 1958.620000 ;
+ RECT 492.220000 1963.580000 493.320000 1964.060000 ;
+ RECT 492.220000 1969.020000 493.320000 1969.500000 ;
+ RECT 447.220000 1996.220000 448.320000 1996.700000 ;
+ RECT 443.090000 1996.220000 444.090000 1996.700000 ;
+ RECT 447.220000 1990.780000 448.320000 1991.260000 ;
+ RECT 443.090000 1990.780000 444.090000 1991.260000 ;
+ RECT 447.220000 1979.900000 448.320000 1980.380000 ;
+ RECT 443.090000 1979.900000 444.090000 1980.380000 ;
+ RECT 447.220000 1974.460000 448.320000 1974.940000 ;
+ RECT 443.090000 1974.460000 444.090000 1974.940000 ;
+ RECT 447.220000 1985.340000 448.320000 1985.820000 ;
+ RECT 443.090000 1985.340000 444.090000 1985.820000 ;
+ RECT 447.220000 1969.020000 448.320000 1969.500000 ;
+ RECT 443.090000 1969.020000 444.090000 1969.500000 ;
+ RECT 447.220000 1963.580000 448.320000 1964.060000 ;
+ RECT 443.090000 1963.580000 444.090000 1964.060000 ;
+ RECT 447.220000 1958.140000 448.320000 1958.620000 ;
+ RECT 447.220000 1952.700000 448.320000 1953.180000 ;
+ RECT 443.090000 1958.140000 444.090000 1958.620000 ;
+ RECT 443.090000 1952.700000 444.090000 1953.180000 ;
+ RECT 440.260000 2143.060000 640.360000 2144.060000 ;
+ RECT 440.260000 1950.690000 640.360000 1951.690000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 1947.840000 444.090000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 2147.100000 444.090000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 1947.840000 637.530000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 2147.100000 637.530000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1950.690000 441.260000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1950.690000 640.360000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 2143.060000 441.260000 2144.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 2143.060000 640.360000 2144.060000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 1750.430000 628.320000 1943.800000 ;
+ RECT 582.220000 1750.430000 583.320000 1943.800000 ;
+ RECT 636.530000 1747.580000 637.530000 1947.840000 ;
+ RECT 537.220000 1750.430000 538.320000 1943.800000 ;
+ RECT 492.220000 1750.430000 493.320000 1943.800000 ;
+ RECT 447.220000 1750.430000 448.320000 1943.800000 ;
+ RECT 443.090000 1747.580000 444.090000 1947.840000 ;
+ LAYER met3 ;
+ RECT 627.220000 1937.400000 628.320000 1937.880000 ;
+ RECT 636.530000 1937.400000 637.530000 1937.880000 ;
+ RECT 636.530000 1926.520000 637.530000 1927.000000 ;
+ RECT 636.530000 1931.960000 637.530000 1932.440000 ;
+ RECT 627.220000 1931.960000 628.320000 1932.440000 ;
+ RECT 627.220000 1926.520000 628.320000 1927.000000 ;
+ RECT 627.220000 1921.080000 628.320000 1921.560000 ;
+ RECT 627.220000 1915.640000 628.320000 1916.120000 ;
+ RECT 636.530000 1921.080000 637.530000 1921.560000 ;
+ RECT 636.530000 1915.640000 637.530000 1916.120000 ;
+ RECT 627.220000 1899.320000 628.320000 1899.800000 ;
+ RECT 627.220000 1904.760000 628.320000 1905.240000 ;
+ RECT 636.530000 1904.760000 637.530000 1905.240000 ;
+ RECT 636.530000 1899.320000 637.530000 1899.800000 ;
+ RECT 627.220000 1910.200000 628.320000 1910.680000 ;
+ RECT 636.530000 1910.200000 637.530000 1910.680000 ;
+ RECT 582.220000 1937.400000 583.320000 1937.880000 ;
+ RECT 582.220000 1931.960000 583.320000 1932.440000 ;
+ RECT 582.220000 1926.520000 583.320000 1927.000000 ;
+ RECT 582.220000 1921.080000 583.320000 1921.560000 ;
+ RECT 582.220000 1899.320000 583.320000 1899.800000 ;
+ RECT 582.220000 1904.760000 583.320000 1905.240000 ;
+ RECT 582.220000 1910.200000 583.320000 1910.680000 ;
+ RECT 582.220000 1915.640000 583.320000 1916.120000 ;
+ RECT 636.530000 1888.440000 637.530000 1888.920000 ;
+ RECT 636.530000 1893.880000 637.530000 1894.360000 ;
+ RECT 627.220000 1893.880000 628.320000 1894.360000 ;
+ RECT 627.220000 1888.440000 628.320000 1888.920000 ;
+ RECT 627.220000 1883.000000 628.320000 1883.480000 ;
+ RECT 627.220000 1877.560000 628.320000 1878.040000 ;
+ RECT 636.530000 1883.000000 637.530000 1883.480000 ;
+ RECT 636.530000 1877.560000 637.530000 1878.040000 ;
+ RECT 636.530000 1861.240000 637.530000 1861.720000 ;
+ RECT 636.530000 1866.680000 637.530000 1867.160000 ;
+ RECT 636.530000 1872.120000 637.530000 1872.600000 ;
+ RECT 627.220000 1866.680000 628.320000 1867.160000 ;
+ RECT 627.220000 1861.240000 628.320000 1861.720000 ;
+ RECT 627.220000 1872.120000 628.320000 1872.600000 ;
+ RECT 627.220000 1855.800000 628.320000 1856.280000 ;
+ RECT 627.220000 1850.360000 628.320000 1850.840000 ;
+ RECT 636.530000 1855.800000 637.530000 1856.280000 ;
+ RECT 636.530000 1850.360000 637.530000 1850.840000 ;
+ RECT 582.220000 1893.880000 583.320000 1894.360000 ;
+ RECT 582.220000 1888.440000 583.320000 1888.920000 ;
+ RECT 582.220000 1883.000000 583.320000 1883.480000 ;
+ RECT 582.220000 1877.560000 583.320000 1878.040000 ;
+ RECT 582.220000 1866.680000 583.320000 1867.160000 ;
+ RECT 582.220000 1861.240000 583.320000 1861.720000 ;
+ RECT 582.220000 1855.800000 583.320000 1856.280000 ;
+ RECT 582.220000 1850.360000 583.320000 1850.840000 ;
+ RECT 582.220000 1872.120000 583.320000 1872.600000 ;
+ RECT 537.220000 1937.400000 538.320000 1937.880000 ;
+ RECT 537.220000 1931.960000 538.320000 1932.440000 ;
+ RECT 537.220000 1926.520000 538.320000 1927.000000 ;
+ RECT 492.220000 1937.400000 493.320000 1937.880000 ;
+ RECT 492.220000 1931.960000 493.320000 1932.440000 ;
+ RECT 492.220000 1926.520000 493.320000 1927.000000 ;
+ RECT 537.220000 1910.200000 538.320000 1910.680000 ;
+ RECT 537.220000 1904.760000 538.320000 1905.240000 ;
+ RECT 537.220000 1899.320000 538.320000 1899.800000 ;
+ RECT 537.220000 1915.640000 538.320000 1916.120000 ;
+ RECT 537.220000 1921.080000 538.320000 1921.560000 ;
+ RECT 492.220000 1921.080000 493.320000 1921.560000 ;
+ RECT 492.220000 1910.200000 493.320000 1910.680000 ;
+ RECT 492.220000 1904.760000 493.320000 1905.240000 ;
+ RECT 492.220000 1899.320000 493.320000 1899.800000 ;
+ RECT 492.220000 1915.640000 493.320000 1916.120000 ;
+ RECT 447.220000 1937.400000 448.320000 1937.880000 ;
+ RECT 443.090000 1937.400000 444.090000 1937.880000 ;
+ RECT 443.090000 1931.960000 444.090000 1932.440000 ;
+ RECT 447.220000 1931.960000 448.320000 1932.440000 ;
+ RECT 447.220000 1926.520000 448.320000 1927.000000 ;
+ RECT 443.090000 1926.520000 444.090000 1927.000000 ;
+ RECT 447.220000 1921.080000 448.320000 1921.560000 ;
+ RECT 443.090000 1921.080000 444.090000 1921.560000 ;
+ RECT 447.220000 1915.640000 448.320000 1916.120000 ;
+ RECT 443.090000 1915.640000 444.090000 1916.120000 ;
+ RECT 447.220000 1904.760000 448.320000 1905.240000 ;
+ RECT 443.090000 1904.760000 444.090000 1905.240000 ;
+ RECT 447.220000 1899.320000 448.320000 1899.800000 ;
+ RECT 443.090000 1899.320000 444.090000 1899.800000 ;
+ RECT 447.220000 1910.200000 448.320000 1910.680000 ;
+ RECT 443.090000 1910.200000 444.090000 1910.680000 ;
+ RECT 537.220000 1893.880000 538.320000 1894.360000 ;
+ RECT 537.220000 1888.440000 538.320000 1888.920000 ;
+ RECT 537.220000 1883.000000 538.320000 1883.480000 ;
+ RECT 537.220000 1877.560000 538.320000 1878.040000 ;
+ RECT 492.220000 1893.880000 493.320000 1894.360000 ;
+ RECT 492.220000 1888.440000 493.320000 1888.920000 ;
+ RECT 492.220000 1883.000000 493.320000 1883.480000 ;
+ RECT 492.220000 1877.560000 493.320000 1878.040000 ;
+ RECT 537.220000 1866.680000 538.320000 1867.160000 ;
+ RECT 537.220000 1850.360000 538.320000 1850.840000 ;
+ RECT 537.220000 1855.800000 538.320000 1856.280000 ;
+ RECT 537.220000 1861.240000 538.320000 1861.720000 ;
+ RECT 537.220000 1872.120000 538.320000 1872.600000 ;
+ RECT 492.220000 1850.360000 493.320000 1850.840000 ;
+ RECT 492.220000 1855.800000 493.320000 1856.280000 ;
+ RECT 492.220000 1861.240000 493.320000 1861.720000 ;
+ RECT 492.220000 1866.680000 493.320000 1867.160000 ;
+ RECT 492.220000 1872.120000 493.320000 1872.600000 ;
+ RECT 447.220000 1893.880000 448.320000 1894.360000 ;
+ RECT 443.090000 1893.880000 444.090000 1894.360000 ;
+ RECT 447.220000 1888.440000 448.320000 1888.920000 ;
+ RECT 443.090000 1888.440000 444.090000 1888.920000 ;
+ RECT 447.220000 1883.000000 448.320000 1883.480000 ;
+ RECT 443.090000 1883.000000 444.090000 1883.480000 ;
+ RECT 447.220000 1877.560000 448.320000 1878.040000 ;
+ RECT 443.090000 1877.560000 444.090000 1878.040000 ;
+ RECT 447.220000 1872.120000 448.320000 1872.600000 ;
+ RECT 447.220000 1866.680000 448.320000 1867.160000 ;
+ RECT 443.090000 1872.120000 444.090000 1872.600000 ;
+ RECT 443.090000 1866.680000 444.090000 1867.160000 ;
+ RECT 447.220000 1861.240000 448.320000 1861.720000 ;
+ RECT 443.090000 1861.240000 444.090000 1861.720000 ;
+ RECT 447.220000 1855.800000 448.320000 1856.280000 ;
+ RECT 443.090000 1855.800000 444.090000 1856.280000 ;
+ RECT 447.220000 1850.360000 448.320000 1850.840000 ;
+ RECT 443.090000 1850.360000 444.090000 1850.840000 ;
+ RECT 627.220000 1844.920000 628.320000 1845.400000 ;
+ RECT 627.220000 1839.480000 628.320000 1839.960000 ;
+ RECT 636.530000 1844.920000 637.530000 1845.400000 ;
+ RECT 636.530000 1839.480000 637.530000 1839.960000 ;
+ RECT 636.530000 1823.160000 637.530000 1823.640000 ;
+ RECT 636.530000 1828.600000 637.530000 1829.080000 ;
+ RECT 636.530000 1834.040000 637.530000 1834.520000 ;
+ RECT 627.220000 1834.040000 628.320000 1834.520000 ;
+ RECT 627.220000 1828.600000 628.320000 1829.080000 ;
+ RECT 627.220000 1823.160000 628.320000 1823.640000 ;
+ RECT 627.220000 1812.280000 628.320000 1812.760000 ;
+ RECT 627.220000 1817.720000 628.320000 1818.200000 ;
+ RECT 636.530000 1817.720000 637.530000 1818.200000 ;
+ RECT 636.530000 1812.280000 637.530000 1812.760000 ;
+ RECT 636.530000 1801.400000 637.530000 1801.880000 ;
+ RECT 636.530000 1806.840000 637.530000 1807.320000 ;
+ RECT 627.220000 1801.400000 628.320000 1801.880000 ;
+ RECT 627.220000 1806.840000 628.320000 1807.320000 ;
+ RECT 582.220000 1844.920000 583.320000 1845.400000 ;
+ RECT 582.220000 1839.480000 583.320000 1839.960000 ;
+ RECT 582.220000 1834.040000 583.320000 1834.520000 ;
+ RECT 582.220000 1828.600000 583.320000 1829.080000 ;
+ RECT 582.220000 1823.160000 583.320000 1823.640000 ;
+ RECT 582.220000 1801.400000 583.320000 1801.880000 ;
+ RECT 582.220000 1806.840000 583.320000 1807.320000 ;
+ RECT 582.220000 1812.280000 583.320000 1812.760000 ;
+ RECT 582.220000 1817.720000 583.320000 1818.200000 ;
+ RECT 627.220000 1795.960000 628.320000 1796.440000 ;
+ RECT 627.220000 1790.520000 628.320000 1791.000000 ;
+ RECT 636.530000 1795.960000 637.530000 1796.440000 ;
+ RECT 636.530000 1790.520000 637.530000 1791.000000 ;
+ RECT 627.220000 1779.640000 628.320000 1780.120000 ;
+ RECT 627.220000 1774.200000 628.320000 1774.680000 ;
+ RECT 636.530000 1779.640000 637.530000 1780.120000 ;
+ RECT 636.530000 1774.200000 637.530000 1774.680000 ;
+ RECT 627.220000 1785.080000 628.320000 1785.560000 ;
+ RECT 636.530000 1785.080000 637.530000 1785.560000 ;
+ RECT 636.530000 1763.320000 637.530000 1763.800000 ;
+ RECT 636.530000 1768.760000 637.530000 1769.240000 ;
+ RECT 627.220000 1768.760000 628.320000 1769.240000 ;
+ RECT 627.220000 1763.320000 628.320000 1763.800000 ;
+ RECT 627.220000 1757.880000 628.320000 1758.360000 ;
+ RECT 627.220000 1752.440000 628.320000 1752.920000 ;
+ RECT 636.530000 1757.880000 637.530000 1758.360000 ;
+ RECT 636.530000 1752.440000 637.530000 1752.920000 ;
+ RECT 582.220000 1795.960000 583.320000 1796.440000 ;
+ RECT 582.220000 1790.520000 583.320000 1791.000000 ;
+ RECT 582.220000 1785.080000 583.320000 1785.560000 ;
+ RECT 582.220000 1779.640000 583.320000 1780.120000 ;
+ RECT 582.220000 1774.200000 583.320000 1774.680000 ;
+ RECT 582.220000 1768.760000 583.320000 1769.240000 ;
+ RECT 582.220000 1763.320000 583.320000 1763.800000 ;
+ RECT 582.220000 1757.880000 583.320000 1758.360000 ;
+ RECT 582.220000 1752.440000 583.320000 1752.920000 ;
+ RECT 537.220000 1844.920000 538.320000 1845.400000 ;
+ RECT 537.220000 1839.480000 538.320000 1839.960000 ;
+ RECT 537.220000 1834.040000 538.320000 1834.520000 ;
+ RECT 537.220000 1828.600000 538.320000 1829.080000 ;
+ RECT 537.220000 1823.160000 538.320000 1823.640000 ;
+ RECT 492.220000 1844.920000 493.320000 1845.400000 ;
+ RECT 492.220000 1839.480000 493.320000 1839.960000 ;
+ RECT 492.220000 1834.040000 493.320000 1834.520000 ;
+ RECT 492.220000 1828.600000 493.320000 1829.080000 ;
+ RECT 492.220000 1823.160000 493.320000 1823.640000 ;
+ RECT 537.220000 1817.720000 538.320000 1818.200000 ;
+ RECT 537.220000 1812.280000 538.320000 1812.760000 ;
+ RECT 537.220000 1806.840000 538.320000 1807.320000 ;
+ RECT 537.220000 1801.400000 538.320000 1801.880000 ;
+ RECT 492.220000 1812.280000 493.320000 1812.760000 ;
+ RECT 492.220000 1806.840000 493.320000 1807.320000 ;
+ RECT 492.220000 1801.400000 493.320000 1801.880000 ;
+ RECT 492.220000 1817.720000 493.320000 1818.200000 ;
+ RECT 447.220000 1844.920000 448.320000 1845.400000 ;
+ RECT 443.090000 1844.920000 444.090000 1845.400000 ;
+ RECT 447.220000 1839.480000 448.320000 1839.960000 ;
+ RECT 443.090000 1839.480000 444.090000 1839.960000 ;
+ RECT 447.220000 1834.040000 448.320000 1834.520000 ;
+ RECT 443.090000 1834.040000 444.090000 1834.520000 ;
+ RECT 447.220000 1823.160000 448.320000 1823.640000 ;
+ RECT 443.090000 1823.160000 444.090000 1823.640000 ;
+ RECT 443.090000 1828.600000 444.090000 1829.080000 ;
+ RECT 447.220000 1828.600000 448.320000 1829.080000 ;
+ RECT 447.220000 1817.720000 448.320000 1818.200000 ;
+ RECT 443.090000 1817.720000 444.090000 1818.200000 ;
+ RECT 447.220000 1812.280000 448.320000 1812.760000 ;
+ RECT 443.090000 1812.280000 444.090000 1812.760000 ;
+ RECT 447.220000 1806.840000 448.320000 1807.320000 ;
+ RECT 443.090000 1806.840000 444.090000 1807.320000 ;
+ RECT 447.220000 1801.400000 448.320000 1801.880000 ;
+ RECT 443.090000 1801.400000 444.090000 1801.880000 ;
+ RECT 537.220000 1795.960000 538.320000 1796.440000 ;
+ RECT 537.220000 1790.520000 538.320000 1791.000000 ;
+ RECT 537.220000 1785.080000 538.320000 1785.560000 ;
+ RECT 537.220000 1779.640000 538.320000 1780.120000 ;
+ RECT 537.220000 1774.200000 538.320000 1774.680000 ;
+ RECT 492.220000 1795.960000 493.320000 1796.440000 ;
+ RECT 492.220000 1790.520000 493.320000 1791.000000 ;
+ RECT 492.220000 1785.080000 493.320000 1785.560000 ;
+ RECT 492.220000 1779.640000 493.320000 1780.120000 ;
+ RECT 492.220000 1774.200000 493.320000 1774.680000 ;
+ RECT 537.220000 1752.440000 538.320000 1752.920000 ;
+ RECT 537.220000 1757.880000 538.320000 1758.360000 ;
+ RECT 537.220000 1763.320000 538.320000 1763.800000 ;
+ RECT 537.220000 1768.760000 538.320000 1769.240000 ;
+ RECT 492.220000 1752.440000 493.320000 1752.920000 ;
+ RECT 492.220000 1757.880000 493.320000 1758.360000 ;
+ RECT 492.220000 1763.320000 493.320000 1763.800000 ;
+ RECT 492.220000 1768.760000 493.320000 1769.240000 ;
+ RECT 447.220000 1795.960000 448.320000 1796.440000 ;
+ RECT 443.090000 1795.960000 444.090000 1796.440000 ;
+ RECT 447.220000 1790.520000 448.320000 1791.000000 ;
+ RECT 443.090000 1790.520000 444.090000 1791.000000 ;
+ RECT 447.220000 1779.640000 448.320000 1780.120000 ;
+ RECT 443.090000 1779.640000 444.090000 1780.120000 ;
+ RECT 447.220000 1774.200000 448.320000 1774.680000 ;
+ RECT 443.090000 1774.200000 444.090000 1774.680000 ;
+ RECT 447.220000 1785.080000 448.320000 1785.560000 ;
+ RECT 443.090000 1785.080000 444.090000 1785.560000 ;
+ RECT 447.220000 1768.760000 448.320000 1769.240000 ;
+ RECT 443.090000 1768.760000 444.090000 1769.240000 ;
+ RECT 447.220000 1763.320000 448.320000 1763.800000 ;
+ RECT 443.090000 1763.320000 444.090000 1763.800000 ;
+ RECT 447.220000 1757.880000 448.320000 1758.360000 ;
+ RECT 447.220000 1752.440000 448.320000 1752.920000 ;
+ RECT 443.090000 1757.880000 444.090000 1758.360000 ;
+ RECT 443.090000 1752.440000 444.090000 1752.920000 ;
+ RECT 440.260000 1942.800000 640.360000 1943.800000 ;
+ RECT 440.260000 1750.430000 640.360000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 1747.580000 444.090000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 1946.840000 444.090000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 1747.580000 637.530000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 1946.840000 637.530000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1750.430000 441.260000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1750.430000 640.360000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1942.800000 441.260000 1943.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1942.800000 640.360000 1943.800000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 627.220000 1550.170000 628.320000 1743.540000 ;
+ RECT 582.220000 1550.170000 583.320000 1743.540000 ;
+ RECT 636.530000 1547.320000 637.530000 1747.580000 ;
+ RECT 537.220000 1550.170000 538.320000 1743.540000 ;
+ RECT 492.220000 1550.170000 493.320000 1743.540000 ;
+ RECT 447.220000 1550.170000 448.320000 1743.540000 ;
+ RECT 443.090000 1547.320000 444.090000 1747.580000 ;
+ LAYER met3 ;
+ RECT 627.220000 1737.140000 628.320000 1737.620000 ;
+ RECT 636.530000 1737.140000 637.530000 1737.620000 ;
+ RECT 636.530000 1726.260000 637.530000 1726.740000 ;
+ RECT 636.530000 1731.700000 637.530000 1732.180000 ;
+ RECT 627.220000 1731.700000 628.320000 1732.180000 ;
+ RECT 627.220000 1726.260000 628.320000 1726.740000 ;
+ RECT 627.220000 1720.820000 628.320000 1721.300000 ;
+ RECT 627.220000 1715.380000 628.320000 1715.860000 ;
+ RECT 636.530000 1720.820000 637.530000 1721.300000 ;
+ RECT 636.530000 1715.380000 637.530000 1715.860000 ;
+ RECT 627.220000 1699.060000 628.320000 1699.540000 ;
+ RECT 627.220000 1704.500000 628.320000 1704.980000 ;
+ RECT 636.530000 1704.500000 637.530000 1704.980000 ;
+ RECT 636.530000 1699.060000 637.530000 1699.540000 ;
+ RECT 627.220000 1709.940000 628.320000 1710.420000 ;
+ RECT 636.530000 1709.940000 637.530000 1710.420000 ;
+ RECT 582.220000 1737.140000 583.320000 1737.620000 ;
+ RECT 582.220000 1731.700000 583.320000 1732.180000 ;
+ RECT 582.220000 1726.260000 583.320000 1726.740000 ;
+ RECT 582.220000 1720.820000 583.320000 1721.300000 ;
+ RECT 582.220000 1699.060000 583.320000 1699.540000 ;
+ RECT 582.220000 1704.500000 583.320000 1704.980000 ;
+ RECT 582.220000 1709.940000 583.320000 1710.420000 ;
+ RECT 582.220000 1715.380000 583.320000 1715.860000 ;
+ RECT 636.530000 1688.180000 637.530000 1688.660000 ;
+ RECT 636.530000 1693.620000 637.530000 1694.100000 ;
+ RECT 627.220000 1693.620000 628.320000 1694.100000 ;
+ RECT 627.220000 1688.180000 628.320000 1688.660000 ;
+ RECT 627.220000 1682.740000 628.320000 1683.220000 ;
+ RECT 627.220000 1677.300000 628.320000 1677.780000 ;
+ RECT 636.530000 1682.740000 637.530000 1683.220000 ;
+ RECT 636.530000 1677.300000 637.530000 1677.780000 ;
+ RECT 636.530000 1660.980000 637.530000 1661.460000 ;
+ RECT 636.530000 1666.420000 637.530000 1666.900000 ;
+ RECT 636.530000 1671.860000 637.530000 1672.340000 ;
+ RECT 627.220000 1666.420000 628.320000 1666.900000 ;
+ RECT 627.220000 1660.980000 628.320000 1661.460000 ;
+ RECT 627.220000 1671.860000 628.320000 1672.340000 ;
+ RECT 627.220000 1655.540000 628.320000 1656.020000 ;
+ RECT 627.220000 1650.100000 628.320000 1650.580000 ;
+ RECT 636.530000 1655.540000 637.530000 1656.020000 ;
+ RECT 636.530000 1650.100000 637.530000 1650.580000 ;
+ RECT 582.220000 1693.620000 583.320000 1694.100000 ;
+ RECT 582.220000 1688.180000 583.320000 1688.660000 ;
+ RECT 582.220000 1682.740000 583.320000 1683.220000 ;
+ RECT 582.220000 1677.300000 583.320000 1677.780000 ;
+ RECT 582.220000 1666.420000 583.320000 1666.900000 ;
+ RECT 582.220000 1660.980000 583.320000 1661.460000 ;
+ RECT 582.220000 1655.540000 583.320000 1656.020000 ;
+ RECT 582.220000 1650.100000 583.320000 1650.580000 ;
+ RECT 582.220000 1671.860000 583.320000 1672.340000 ;
+ RECT 537.220000 1737.140000 538.320000 1737.620000 ;
+ RECT 537.220000 1731.700000 538.320000 1732.180000 ;
+ RECT 537.220000 1726.260000 538.320000 1726.740000 ;
+ RECT 492.220000 1737.140000 493.320000 1737.620000 ;
+ RECT 492.220000 1731.700000 493.320000 1732.180000 ;
+ RECT 492.220000 1726.260000 493.320000 1726.740000 ;
+ RECT 537.220000 1709.940000 538.320000 1710.420000 ;
+ RECT 537.220000 1704.500000 538.320000 1704.980000 ;
+ RECT 537.220000 1699.060000 538.320000 1699.540000 ;
+ RECT 537.220000 1715.380000 538.320000 1715.860000 ;
+ RECT 537.220000 1720.820000 538.320000 1721.300000 ;
+ RECT 492.220000 1720.820000 493.320000 1721.300000 ;
+ RECT 492.220000 1709.940000 493.320000 1710.420000 ;
+ RECT 492.220000 1704.500000 493.320000 1704.980000 ;
+ RECT 492.220000 1699.060000 493.320000 1699.540000 ;
+ RECT 492.220000 1715.380000 493.320000 1715.860000 ;
+ RECT 447.220000 1737.140000 448.320000 1737.620000 ;
+ RECT 443.090000 1737.140000 444.090000 1737.620000 ;
+ RECT 443.090000 1731.700000 444.090000 1732.180000 ;
+ RECT 447.220000 1731.700000 448.320000 1732.180000 ;
+ RECT 447.220000 1726.260000 448.320000 1726.740000 ;
+ RECT 443.090000 1726.260000 444.090000 1726.740000 ;
+ RECT 447.220000 1720.820000 448.320000 1721.300000 ;
+ RECT 443.090000 1720.820000 444.090000 1721.300000 ;
+ RECT 447.220000 1715.380000 448.320000 1715.860000 ;
+ RECT 443.090000 1715.380000 444.090000 1715.860000 ;
+ RECT 447.220000 1704.500000 448.320000 1704.980000 ;
+ RECT 443.090000 1704.500000 444.090000 1704.980000 ;
+ RECT 447.220000 1699.060000 448.320000 1699.540000 ;
+ RECT 443.090000 1699.060000 444.090000 1699.540000 ;
+ RECT 447.220000 1709.940000 448.320000 1710.420000 ;
+ RECT 443.090000 1709.940000 444.090000 1710.420000 ;
+ RECT 537.220000 1693.620000 538.320000 1694.100000 ;
+ RECT 537.220000 1688.180000 538.320000 1688.660000 ;
+ RECT 537.220000 1682.740000 538.320000 1683.220000 ;
+ RECT 537.220000 1677.300000 538.320000 1677.780000 ;
+ RECT 492.220000 1693.620000 493.320000 1694.100000 ;
+ RECT 492.220000 1688.180000 493.320000 1688.660000 ;
+ RECT 492.220000 1682.740000 493.320000 1683.220000 ;
+ RECT 492.220000 1677.300000 493.320000 1677.780000 ;
+ RECT 537.220000 1666.420000 538.320000 1666.900000 ;
+ RECT 537.220000 1650.100000 538.320000 1650.580000 ;
+ RECT 537.220000 1655.540000 538.320000 1656.020000 ;
+ RECT 537.220000 1660.980000 538.320000 1661.460000 ;
+ RECT 537.220000 1671.860000 538.320000 1672.340000 ;
+ RECT 492.220000 1650.100000 493.320000 1650.580000 ;
+ RECT 492.220000 1655.540000 493.320000 1656.020000 ;
+ RECT 492.220000 1660.980000 493.320000 1661.460000 ;
+ RECT 492.220000 1666.420000 493.320000 1666.900000 ;
+ RECT 492.220000 1671.860000 493.320000 1672.340000 ;
+ RECT 447.220000 1693.620000 448.320000 1694.100000 ;
+ RECT 443.090000 1693.620000 444.090000 1694.100000 ;
+ RECT 447.220000 1688.180000 448.320000 1688.660000 ;
+ RECT 443.090000 1688.180000 444.090000 1688.660000 ;
+ RECT 447.220000 1682.740000 448.320000 1683.220000 ;
+ RECT 443.090000 1682.740000 444.090000 1683.220000 ;
+ RECT 447.220000 1677.300000 448.320000 1677.780000 ;
+ RECT 443.090000 1677.300000 444.090000 1677.780000 ;
+ RECT 447.220000 1671.860000 448.320000 1672.340000 ;
+ RECT 447.220000 1666.420000 448.320000 1666.900000 ;
+ RECT 443.090000 1671.860000 444.090000 1672.340000 ;
+ RECT 443.090000 1666.420000 444.090000 1666.900000 ;
+ RECT 447.220000 1660.980000 448.320000 1661.460000 ;
+ RECT 443.090000 1660.980000 444.090000 1661.460000 ;
+ RECT 447.220000 1655.540000 448.320000 1656.020000 ;
+ RECT 443.090000 1655.540000 444.090000 1656.020000 ;
+ RECT 447.220000 1650.100000 448.320000 1650.580000 ;
+ RECT 443.090000 1650.100000 444.090000 1650.580000 ;
+ RECT 627.220000 1644.660000 628.320000 1645.140000 ;
+ RECT 627.220000 1639.220000 628.320000 1639.700000 ;
+ RECT 636.530000 1644.660000 637.530000 1645.140000 ;
+ RECT 636.530000 1639.220000 637.530000 1639.700000 ;
+ RECT 636.530000 1622.900000 637.530000 1623.380000 ;
+ RECT 636.530000 1628.340000 637.530000 1628.820000 ;
+ RECT 636.530000 1633.780000 637.530000 1634.260000 ;
+ RECT 627.220000 1633.780000 628.320000 1634.260000 ;
+ RECT 627.220000 1628.340000 628.320000 1628.820000 ;
+ RECT 627.220000 1622.900000 628.320000 1623.380000 ;
+ RECT 627.220000 1612.020000 628.320000 1612.500000 ;
+ RECT 627.220000 1617.460000 628.320000 1617.940000 ;
+ RECT 636.530000 1617.460000 637.530000 1617.940000 ;
+ RECT 636.530000 1612.020000 637.530000 1612.500000 ;
+ RECT 636.530000 1601.140000 637.530000 1601.620000 ;
+ RECT 636.530000 1606.580000 637.530000 1607.060000 ;
+ RECT 627.220000 1601.140000 628.320000 1601.620000 ;
+ RECT 627.220000 1606.580000 628.320000 1607.060000 ;
+ RECT 582.220000 1644.660000 583.320000 1645.140000 ;
+ RECT 582.220000 1639.220000 583.320000 1639.700000 ;
+ RECT 582.220000 1633.780000 583.320000 1634.260000 ;
+ RECT 582.220000 1628.340000 583.320000 1628.820000 ;
+ RECT 582.220000 1622.900000 583.320000 1623.380000 ;
+ RECT 582.220000 1601.140000 583.320000 1601.620000 ;
+ RECT 582.220000 1606.580000 583.320000 1607.060000 ;
+ RECT 582.220000 1612.020000 583.320000 1612.500000 ;
+ RECT 582.220000 1617.460000 583.320000 1617.940000 ;
+ RECT 627.220000 1595.700000 628.320000 1596.180000 ;
+ RECT 627.220000 1590.260000 628.320000 1590.740000 ;
+ RECT 636.530000 1595.700000 637.530000 1596.180000 ;
+ RECT 636.530000 1590.260000 637.530000 1590.740000 ;
+ RECT 627.220000 1579.380000 628.320000 1579.860000 ;
+ RECT 627.220000 1573.940000 628.320000 1574.420000 ;
+ RECT 636.530000 1579.380000 637.530000 1579.860000 ;
+ RECT 636.530000 1573.940000 637.530000 1574.420000 ;
+ RECT 627.220000 1584.820000 628.320000 1585.300000 ;
+ RECT 636.530000 1584.820000 637.530000 1585.300000 ;
+ RECT 636.530000 1563.060000 637.530000 1563.540000 ;
+ RECT 636.530000 1568.500000 637.530000 1568.980000 ;
+ RECT 627.220000 1568.500000 628.320000 1568.980000 ;
+ RECT 627.220000 1563.060000 628.320000 1563.540000 ;
+ RECT 627.220000 1557.620000 628.320000 1558.100000 ;
+ RECT 627.220000 1552.180000 628.320000 1552.660000 ;
+ RECT 636.530000 1557.620000 637.530000 1558.100000 ;
+ RECT 636.530000 1552.180000 637.530000 1552.660000 ;
+ RECT 582.220000 1595.700000 583.320000 1596.180000 ;
+ RECT 582.220000 1590.260000 583.320000 1590.740000 ;
+ RECT 582.220000 1584.820000 583.320000 1585.300000 ;
+ RECT 582.220000 1579.380000 583.320000 1579.860000 ;
+ RECT 582.220000 1573.940000 583.320000 1574.420000 ;
+ RECT 582.220000 1568.500000 583.320000 1568.980000 ;
+ RECT 582.220000 1563.060000 583.320000 1563.540000 ;
+ RECT 582.220000 1557.620000 583.320000 1558.100000 ;
+ RECT 582.220000 1552.180000 583.320000 1552.660000 ;
+ RECT 537.220000 1644.660000 538.320000 1645.140000 ;
+ RECT 537.220000 1639.220000 538.320000 1639.700000 ;
+ RECT 537.220000 1633.780000 538.320000 1634.260000 ;
+ RECT 537.220000 1628.340000 538.320000 1628.820000 ;
+ RECT 537.220000 1622.900000 538.320000 1623.380000 ;
+ RECT 492.220000 1644.660000 493.320000 1645.140000 ;
+ RECT 492.220000 1639.220000 493.320000 1639.700000 ;
+ RECT 492.220000 1633.780000 493.320000 1634.260000 ;
+ RECT 492.220000 1628.340000 493.320000 1628.820000 ;
+ RECT 492.220000 1622.900000 493.320000 1623.380000 ;
+ RECT 537.220000 1617.460000 538.320000 1617.940000 ;
+ RECT 537.220000 1612.020000 538.320000 1612.500000 ;
+ RECT 537.220000 1606.580000 538.320000 1607.060000 ;
+ RECT 537.220000 1601.140000 538.320000 1601.620000 ;
+ RECT 492.220000 1612.020000 493.320000 1612.500000 ;
+ RECT 492.220000 1606.580000 493.320000 1607.060000 ;
+ RECT 492.220000 1601.140000 493.320000 1601.620000 ;
+ RECT 492.220000 1617.460000 493.320000 1617.940000 ;
+ RECT 447.220000 1644.660000 448.320000 1645.140000 ;
+ RECT 443.090000 1644.660000 444.090000 1645.140000 ;
+ RECT 447.220000 1639.220000 448.320000 1639.700000 ;
+ RECT 443.090000 1639.220000 444.090000 1639.700000 ;
+ RECT 447.220000 1633.780000 448.320000 1634.260000 ;
+ RECT 443.090000 1633.780000 444.090000 1634.260000 ;
+ RECT 447.220000 1622.900000 448.320000 1623.380000 ;
+ RECT 443.090000 1622.900000 444.090000 1623.380000 ;
+ RECT 443.090000 1628.340000 444.090000 1628.820000 ;
+ RECT 447.220000 1628.340000 448.320000 1628.820000 ;
+ RECT 447.220000 1617.460000 448.320000 1617.940000 ;
+ RECT 443.090000 1617.460000 444.090000 1617.940000 ;
+ RECT 447.220000 1612.020000 448.320000 1612.500000 ;
+ RECT 443.090000 1612.020000 444.090000 1612.500000 ;
+ RECT 447.220000 1606.580000 448.320000 1607.060000 ;
+ RECT 443.090000 1606.580000 444.090000 1607.060000 ;
+ RECT 447.220000 1601.140000 448.320000 1601.620000 ;
+ RECT 443.090000 1601.140000 444.090000 1601.620000 ;
+ RECT 537.220000 1595.700000 538.320000 1596.180000 ;
+ RECT 537.220000 1590.260000 538.320000 1590.740000 ;
+ RECT 537.220000 1584.820000 538.320000 1585.300000 ;
+ RECT 537.220000 1579.380000 538.320000 1579.860000 ;
+ RECT 537.220000 1573.940000 538.320000 1574.420000 ;
+ RECT 492.220000 1595.700000 493.320000 1596.180000 ;
+ RECT 492.220000 1590.260000 493.320000 1590.740000 ;
+ RECT 492.220000 1584.820000 493.320000 1585.300000 ;
+ RECT 492.220000 1579.380000 493.320000 1579.860000 ;
+ RECT 492.220000 1573.940000 493.320000 1574.420000 ;
+ RECT 537.220000 1552.180000 538.320000 1552.660000 ;
+ RECT 537.220000 1557.620000 538.320000 1558.100000 ;
+ RECT 537.220000 1563.060000 538.320000 1563.540000 ;
+ RECT 537.220000 1568.500000 538.320000 1568.980000 ;
+ RECT 492.220000 1552.180000 493.320000 1552.660000 ;
+ RECT 492.220000 1557.620000 493.320000 1558.100000 ;
+ RECT 492.220000 1563.060000 493.320000 1563.540000 ;
+ RECT 492.220000 1568.500000 493.320000 1568.980000 ;
+ RECT 447.220000 1595.700000 448.320000 1596.180000 ;
+ RECT 443.090000 1595.700000 444.090000 1596.180000 ;
+ RECT 447.220000 1590.260000 448.320000 1590.740000 ;
+ RECT 443.090000 1590.260000 444.090000 1590.740000 ;
+ RECT 447.220000 1579.380000 448.320000 1579.860000 ;
+ RECT 443.090000 1579.380000 444.090000 1579.860000 ;
+ RECT 447.220000 1573.940000 448.320000 1574.420000 ;
+ RECT 443.090000 1573.940000 444.090000 1574.420000 ;
+ RECT 447.220000 1584.820000 448.320000 1585.300000 ;
+ RECT 443.090000 1584.820000 444.090000 1585.300000 ;
+ RECT 447.220000 1568.500000 448.320000 1568.980000 ;
+ RECT 443.090000 1568.500000 444.090000 1568.980000 ;
+ RECT 447.220000 1563.060000 448.320000 1563.540000 ;
+ RECT 443.090000 1563.060000 444.090000 1563.540000 ;
+ RECT 447.220000 1557.620000 448.320000 1558.100000 ;
+ RECT 447.220000 1552.180000 448.320000 1552.660000 ;
+ RECT 443.090000 1557.620000 444.090000 1558.100000 ;
+ RECT 443.090000 1552.180000 444.090000 1552.660000 ;
+ RECT 440.260000 1742.540000 640.360000 1743.540000 ;
+ RECT 440.260000 1550.170000 640.360000 1551.170000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 1547.320000 444.090000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 443.090000 1746.580000 444.090000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 1547.320000 637.530000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 636.530000 1746.580000 637.530000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1550.170000 441.260000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1550.170000 640.360000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 440.260000 1742.540000 441.260000 1743.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 639.360000 1742.540000 640.360000 1743.540000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single2'
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 3349.660000 644.190000 3379.920000 ;
+ RECT 836.630000 3349.660000 837.630000 3379.920000 ;
+ RECT 647.320000 3352.510000 648.420000 3376.560000 ;
+ RECT 692.320000 3352.510000 693.420000 3376.560000 ;
+ RECT 737.320000 3352.510000 738.420000 3376.560000 ;
+ RECT 782.320000 3352.510000 783.420000 3376.560000 ;
+ RECT 827.320000 3352.510000 828.420000 3376.560000 ;
+ LAYER met3 ;
+ RECT 836.630000 3365.400000 837.630000 3365.880000 ;
+ RECT 836.630000 3370.840000 837.630000 3371.320000 ;
+ RECT 827.320000 3370.840000 828.420000 3371.320000 ;
+ RECT 827.320000 3365.400000 828.420000 3365.880000 ;
+ RECT 782.320000 3365.400000 783.420000 3365.880000 ;
+ RECT 782.320000 3370.840000 783.420000 3371.320000 ;
+ RECT 692.320000 3365.400000 693.420000 3365.880000 ;
+ RECT 737.320000 3365.400000 738.420000 3365.880000 ;
+ RECT 737.320000 3370.840000 738.420000 3371.320000 ;
+ RECT 692.320000 3370.840000 693.420000 3371.320000 ;
+ RECT 643.190000 3365.400000 644.190000 3365.880000 ;
+ RECT 647.320000 3365.400000 648.420000 3365.880000 ;
+ RECT 647.320000 3370.840000 648.420000 3371.320000 ;
+ RECT 643.190000 3370.840000 644.190000 3371.320000 ;
+ RECT 836.630000 3354.520000 837.630000 3355.000000 ;
+ RECT 836.630000 3359.960000 837.630000 3360.440000 ;
+ RECT 827.320000 3359.960000 828.420000 3360.440000 ;
+ RECT 827.320000 3354.520000 828.420000 3355.000000 ;
+ RECT 782.320000 3354.520000 783.420000 3355.000000 ;
+ RECT 782.320000 3359.960000 783.420000 3360.440000 ;
+ RECT 692.320000 3354.520000 693.420000 3355.000000 ;
+ RECT 737.320000 3354.520000 738.420000 3355.000000 ;
+ RECT 737.320000 3359.960000 738.420000 3360.440000 ;
+ RECT 692.320000 3359.960000 693.420000 3360.440000 ;
+ RECT 643.190000 3359.960000 644.190000 3360.440000 ;
+ RECT 647.320000 3359.960000 648.420000 3360.440000 ;
+ RECT 643.190000 3354.520000 644.190000 3355.000000 ;
+ RECT 647.320000 3354.520000 648.420000 3355.000000 ;
+ RECT 640.360000 3375.560000 840.460000 3376.560000 ;
+ RECT 640.360000 3352.510000 840.460000 3353.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 3349.660000 644.190000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 3378.920000 644.190000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 3349.660000 837.630000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 3378.920000 837.630000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 3352.510000 641.360000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 3352.510000 840.460000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 3375.560000 641.360000 3376.560000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 3375.560000 840.460000 3376.560000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single2'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 1349.910000 828.420000 1543.280000 ;
+ RECT 782.320000 1349.910000 783.420000 1543.280000 ;
+ RECT 836.630000 1347.060000 837.630000 1547.320000 ;
+ RECT 737.320000 1349.910000 738.420000 1543.280000 ;
+ RECT 692.320000 1349.910000 693.420000 1543.280000 ;
+ RECT 647.320000 1349.910000 648.420000 1543.280000 ;
+ RECT 643.190000 1347.060000 644.190000 1547.320000 ;
+ LAYER met3 ;
+ RECT 827.320000 1536.880000 828.420000 1537.360000 ;
+ RECT 836.630000 1536.880000 837.630000 1537.360000 ;
+ RECT 836.630000 1526.000000 837.630000 1526.480000 ;
+ RECT 836.630000 1531.440000 837.630000 1531.920000 ;
+ RECT 827.320000 1531.440000 828.420000 1531.920000 ;
+ RECT 827.320000 1526.000000 828.420000 1526.480000 ;
+ RECT 827.320000 1520.560000 828.420000 1521.040000 ;
+ RECT 827.320000 1515.120000 828.420000 1515.600000 ;
+ RECT 836.630000 1520.560000 837.630000 1521.040000 ;
+ RECT 836.630000 1515.120000 837.630000 1515.600000 ;
+ RECT 827.320000 1498.800000 828.420000 1499.280000 ;
+ RECT 827.320000 1504.240000 828.420000 1504.720000 ;
+ RECT 836.630000 1504.240000 837.630000 1504.720000 ;
+ RECT 836.630000 1498.800000 837.630000 1499.280000 ;
+ RECT 827.320000 1509.680000 828.420000 1510.160000 ;
+ RECT 836.630000 1509.680000 837.630000 1510.160000 ;
+ RECT 782.320000 1536.880000 783.420000 1537.360000 ;
+ RECT 782.320000 1531.440000 783.420000 1531.920000 ;
+ RECT 782.320000 1526.000000 783.420000 1526.480000 ;
+ RECT 782.320000 1520.560000 783.420000 1521.040000 ;
+ RECT 782.320000 1498.800000 783.420000 1499.280000 ;
+ RECT 782.320000 1504.240000 783.420000 1504.720000 ;
+ RECT 782.320000 1509.680000 783.420000 1510.160000 ;
+ RECT 782.320000 1515.120000 783.420000 1515.600000 ;
+ RECT 836.630000 1487.920000 837.630000 1488.400000 ;
+ RECT 836.630000 1493.360000 837.630000 1493.840000 ;
+ RECT 827.320000 1493.360000 828.420000 1493.840000 ;
+ RECT 827.320000 1487.920000 828.420000 1488.400000 ;
+ RECT 827.320000 1482.480000 828.420000 1482.960000 ;
+ RECT 827.320000 1477.040000 828.420000 1477.520000 ;
+ RECT 836.630000 1482.480000 837.630000 1482.960000 ;
+ RECT 836.630000 1477.040000 837.630000 1477.520000 ;
+ RECT 836.630000 1460.720000 837.630000 1461.200000 ;
+ RECT 836.630000 1466.160000 837.630000 1466.640000 ;
+ RECT 836.630000 1471.600000 837.630000 1472.080000 ;
+ RECT 827.320000 1466.160000 828.420000 1466.640000 ;
+ RECT 827.320000 1460.720000 828.420000 1461.200000 ;
+ RECT 827.320000 1471.600000 828.420000 1472.080000 ;
+ RECT 827.320000 1455.280000 828.420000 1455.760000 ;
+ RECT 827.320000 1449.840000 828.420000 1450.320000 ;
+ RECT 836.630000 1455.280000 837.630000 1455.760000 ;
+ RECT 836.630000 1449.840000 837.630000 1450.320000 ;
+ RECT 782.320000 1493.360000 783.420000 1493.840000 ;
+ RECT 782.320000 1487.920000 783.420000 1488.400000 ;
+ RECT 782.320000 1482.480000 783.420000 1482.960000 ;
+ RECT 782.320000 1477.040000 783.420000 1477.520000 ;
+ RECT 782.320000 1466.160000 783.420000 1466.640000 ;
+ RECT 782.320000 1460.720000 783.420000 1461.200000 ;
+ RECT 782.320000 1455.280000 783.420000 1455.760000 ;
+ RECT 782.320000 1449.840000 783.420000 1450.320000 ;
+ RECT 782.320000 1471.600000 783.420000 1472.080000 ;
+ RECT 737.320000 1536.880000 738.420000 1537.360000 ;
+ RECT 737.320000 1531.440000 738.420000 1531.920000 ;
+ RECT 737.320000 1526.000000 738.420000 1526.480000 ;
+ RECT 692.320000 1536.880000 693.420000 1537.360000 ;
+ RECT 692.320000 1531.440000 693.420000 1531.920000 ;
+ RECT 692.320000 1526.000000 693.420000 1526.480000 ;
+ RECT 737.320000 1509.680000 738.420000 1510.160000 ;
+ RECT 737.320000 1504.240000 738.420000 1504.720000 ;
+ RECT 737.320000 1498.800000 738.420000 1499.280000 ;
+ RECT 737.320000 1515.120000 738.420000 1515.600000 ;
+ RECT 737.320000 1520.560000 738.420000 1521.040000 ;
+ RECT 692.320000 1520.560000 693.420000 1521.040000 ;
+ RECT 692.320000 1509.680000 693.420000 1510.160000 ;
+ RECT 692.320000 1504.240000 693.420000 1504.720000 ;
+ RECT 692.320000 1498.800000 693.420000 1499.280000 ;
+ RECT 692.320000 1515.120000 693.420000 1515.600000 ;
+ RECT 647.320000 1536.880000 648.420000 1537.360000 ;
+ RECT 643.190000 1536.880000 644.190000 1537.360000 ;
+ RECT 643.190000 1531.440000 644.190000 1531.920000 ;
+ RECT 647.320000 1531.440000 648.420000 1531.920000 ;
+ RECT 647.320000 1526.000000 648.420000 1526.480000 ;
+ RECT 643.190000 1526.000000 644.190000 1526.480000 ;
+ RECT 647.320000 1520.560000 648.420000 1521.040000 ;
+ RECT 643.190000 1520.560000 644.190000 1521.040000 ;
+ RECT 647.320000 1515.120000 648.420000 1515.600000 ;
+ RECT 643.190000 1515.120000 644.190000 1515.600000 ;
+ RECT 647.320000 1504.240000 648.420000 1504.720000 ;
+ RECT 643.190000 1504.240000 644.190000 1504.720000 ;
+ RECT 647.320000 1498.800000 648.420000 1499.280000 ;
+ RECT 643.190000 1498.800000 644.190000 1499.280000 ;
+ RECT 647.320000 1509.680000 648.420000 1510.160000 ;
+ RECT 643.190000 1509.680000 644.190000 1510.160000 ;
+ RECT 737.320000 1493.360000 738.420000 1493.840000 ;
+ RECT 737.320000 1487.920000 738.420000 1488.400000 ;
+ RECT 737.320000 1482.480000 738.420000 1482.960000 ;
+ RECT 737.320000 1477.040000 738.420000 1477.520000 ;
+ RECT 692.320000 1493.360000 693.420000 1493.840000 ;
+ RECT 692.320000 1487.920000 693.420000 1488.400000 ;
+ RECT 692.320000 1482.480000 693.420000 1482.960000 ;
+ RECT 692.320000 1477.040000 693.420000 1477.520000 ;
+ RECT 737.320000 1466.160000 738.420000 1466.640000 ;
+ RECT 737.320000 1449.840000 738.420000 1450.320000 ;
+ RECT 737.320000 1455.280000 738.420000 1455.760000 ;
+ RECT 737.320000 1460.720000 738.420000 1461.200000 ;
+ RECT 737.320000 1471.600000 738.420000 1472.080000 ;
+ RECT 692.320000 1449.840000 693.420000 1450.320000 ;
+ RECT 692.320000 1455.280000 693.420000 1455.760000 ;
+ RECT 692.320000 1460.720000 693.420000 1461.200000 ;
+ RECT 692.320000 1466.160000 693.420000 1466.640000 ;
+ RECT 692.320000 1471.600000 693.420000 1472.080000 ;
+ RECT 647.320000 1493.360000 648.420000 1493.840000 ;
+ RECT 643.190000 1493.360000 644.190000 1493.840000 ;
+ RECT 647.320000 1487.920000 648.420000 1488.400000 ;
+ RECT 643.190000 1487.920000 644.190000 1488.400000 ;
+ RECT 647.320000 1482.480000 648.420000 1482.960000 ;
+ RECT 643.190000 1482.480000 644.190000 1482.960000 ;
+ RECT 647.320000 1477.040000 648.420000 1477.520000 ;
+ RECT 643.190000 1477.040000 644.190000 1477.520000 ;
+ RECT 647.320000 1471.600000 648.420000 1472.080000 ;
+ RECT 647.320000 1466.160000 648.420000 1466.640000 ;
+ RECT 643.190000 1471.600000 644.190000 1472.080000 ;
+ RECT 643.190000 1466.160000 644.190000 1466.640000 ;
+ RECT 647.320000 1460.720000 648.420000 1461.200000 ;
+ RECT 643.190000 1460.720000 644.190000 1461.200000 ;
+ RECT 647.320000 1455.280000 648.420000 1455.760000 ;
+ RECT 643.190000 1455.280000 644.190000 1455.760000 ;
+ RECT 647.320000 1449.840000 648.420000 1450.320000 ;
+ RECT 643.190000 1449.840000 644.190000 1450.320000 ;
+ RECT 827.320000 1444.400000 828.420000 1444.880000 ;
+ RECT 827.320000 1438.960000 828.420000 1439.440000 ;
+ RECT 836.630000 1444.400000 837.630000 1444.880000 ;
+ RECT 836.630000 1438.960000 837.630000 1439.440000 ;
+ RECT 836.630000 1422.640000 837.630000 1423.120000 ;
+ RECT 836.630000 1428.080000 837.630000 1428.560000 ;
+ RECT 836.630000 1433.520000 837.630000 1434.000000 ;
+ RECT 827.320000 1433.520000 828.420000 1434.000000 ;
+ RECT 827.320000 1428.080000 828.420000 1428.560000 ;
+ RECT 827.320000 1422.640000 828.420000 1423.120000 ;
+ RECT 827.320000 1411.760000 828.420000 1412.240000 ;
+ RECT 827.320000 1417.200000 828.420000 1417.680000 ;
+ RECT 836.630000 1417.200000 837.630000 1417.680000 ;
+ RECT 836.630000 1411.760000 837.630000 1412.240000 ;
+ RECT 836.630000 1400.880000 837.630000 1401.360000 ;
+ RECT 836.630000 1406.320000 837.630000 1406.800000 ;
+ RECT 827.320000 1400.880000 828.420000 1401.360000 ;
+ RECT 827.320000 1406.320000 828.420000 1406.800000 ;
+ RECT 782.320000 1444.400000 783.420000 1444.880000 ;
+ RECT 782.320000 1438.960000 783.420000 1439.440000 ;
+ RECT 782.320000 1433.520000 783.420000 1434.000000 ;
+ RECT 782.320000 1428.080000 783.420000 1428.560000 ;
+ RECT 782.320000 1422.640000 783.420000 1423.120000 ;
+ RECT 782.320000 1400.880000 783.420000 1401.360000 ;
+ RECT 782.320000 1406.320000 783.420000 1406.800000 ;
+ RECT 782.320000 1411.760000 783.420000 1412.240000 ;
+ RECT 782.320000 1417.200000 783.420000 1417.680000 ;
+ RECT 827.320000 1395.440000 828.420000 1395.920000 ;
+ RECT 827.320000 1390.000000 828.420000 1390.480000 ;
+ RECT 836.630000 1395.440000 837.630000 1395.920000 ;
+ RECT 836.630000 1390.000000 837.630000 1390.480000 ;
+ RECT 827.320000 1379.120000 828.420000 1379.600000 ;
+ RECT 827.320000 1373.680000 828.420000 1374.160000 ;
+ RECT 836.630000 1379.120000 837.630000 1379.600000 ;
+ RECT 836.630000 1373.680000 837.630000 1374.160000 ;
+ RECT 827.320000 1384.560000 828.420000 1385.040000 ;
+ RECT 836.630000 1384.560000 837.630000 1385.040000 ;
+ RECT 836.630000 1362.800000 837.630000 1363.280000 ;
+ RECT 836.630000 1368.240000 837.630000 1368.720000 ;
+ RECT 827.320000 1368.240000 828.420000 1368.720000 ;
+ RECT 827.320000 1362.800000 828.420000 1363.280000 ;
+ RECT 827.320000 1357.360000 828.420000 1357.840000 ;
+ RECT 827.320000 1351.920000 828.420000 1352.400000 ;
+ RECT 836.630000 1357.360000 837.630000 1357.840000 ;
+ RECT 836.630000 1351.920000 837.630000 1352.400000 ;
+ RECT 782.320000 1395.440000 783.420000 1395.920000 ;
+ RECT 782.320000 1390.000000 783.420000 1390.480000 ;
+ RECT 782.320000 1384.560000 783.420000 1385.040000 ;
+ RECT 782.320000 1379.120000 783.420000 1379.600000 ;
+ RECT 782.320000 1373.680000 783.420000 1374.160000 ;
+ RECT 782.320000 1368.240000 783.420000 1368.720000 ;
+ RECT 782.320000 1362.800000 783.420000 1363.280000 ;
+ RECT 782.320000 1357.360000 783.420000 1357.840000 ;
+ RECT 782.320000 1351.920000 783.420000 1352.400000 ;
+ RECT 737.320000 1444.400000 738.420000 1444.880000 ;
+ RECT 737.320000 1438.960000 738.420000 1439.440000 ;
+ RECT 737.320000 1433.520000 738.420000 1434.000000 ;
+ RECT 737.320000 1428.080000 738.420000 1428.560000 ;
+ RECT 737.320000 1422.640000 738.420000 1423.120000 ;
+ RECT 692.320000 1444.400000 693.420000 1444.880000 ;
+ RECT 692.320000 1438.960000 693.420000 1439.440000 ;
+ RECT 692.320000 1433.520000 693.420000 1434.000000 ;
+ RECT 692.320000 1428.080000 693.420000 1428.560000 ;
+ RECT 692.320000 1422.640000 693.420000 1423.120000 ;
+ RECT 737.320000 1417.200000 738.420000 1417.680000 ;
+ RECT 737.320000 1411.760000 738.420000 1412.240000 ;
+ RECT 737.320000 1406.320000 738.420000 1406.800000 ;
+ RECT 737.320000 1400.880000 738.420000 1401.360000 ;
+ RECT 692.320000 1411.760000 693.420000 1412.240000 ;
+ RECT 692.320000 1406.320000 693.420000 1406.800000 ;
+ RECT 692.320000 1400.880000 693.420000 1401.360000 ;
+ RECT 692.320000 1417.200000 693.420000 1417.680000 ;
+ RECT 647.320000 1444.400000 648.420000 1444.880000 ;
+ RECT 643.190000 1444.400000 644.190000 1444.880000 ;
+ RECT 647.320000 1438.960000 648.420000 1439.440000 ;
+ RECT 643.190000 1438.960000 644.190000 1439.440000 ;
+ RECT 647.320000 1433.520000 648.420000 1434.000000 ;
+ RECT 643.190000 1433.520000 644.190000 1434.000000 ;
+ RECT 647.320000 1422.640000 648.420000 1423.120000 ;
+ RECT 643.190000 1422.640000 644.190000 1423.120000 ;
+ RECT 643.190000 1428.080000 644.190000 1428.560000 ;
+ RECT 647.320000 1428.080000 648.420000 1428.560000 ;
+ RECT 647.320000 1417.200000 648.420000 1417.680000 ;
+ RECT 643.190000 1417.200000 644.190000 1417.680000 ;
+ RECT 647.320000 1411.760000 648.420000 1412.240000 ;
+ RECT 643.190000 1411.760000 644.190000 1412.240000 ;
+ RECT 647.320000 1406.320000 648.420000 1406.800000 ;
+ RECT 643.190000 1406.320000 644.190000 1406.800000 ;
+ RECT 647.320000 1400.880000 648.420000 1401.360000 ;
+ RECT 643.190000 1400.880000 644.190000 1401.360000 ;
+ RECT 737.320000 1395.440000 738.420000 1395.920000 ;
+ RECT 737.320000 1390.000000 738.420000 1390.480000 ;
+ RECT 737.320000 1384.560000 738.420000 1385.040000 ;
+ RECT 737.320000 1379.120000 738.420000 1379.600000 ;
+ RECT 737.320000 1373.680000 738.420000 1374.160000 ;
+ RECT 692.320000 1395.440000 693.420000 1395.920000 ;
+ RECT 692.320000 1390.000000 693.420000 1390.480000 ;
+ RECT 692.320000 1384.560000 693.420000 1385.040000 ;
+ RECT 692.320000 1379.120000 693.420000 1379.600000 ;
+ RECT 692.320000 1373.680000 693.420000 1374.160000 ;
+ RECT 737.320000 1351.920000 738.420000 1352.400000 ;
+ RECT 737.320000 1357.360000 738.420000 1357.840000 ;
+ RECT 737.320000 1362.800000 738.420000 1363.280000 ;
+ RECT 737.320000 1368.240000 738.420000 1368.720000 ;
+ RECT 692.320000 1351.920000 693.420000 1352.400000 ;
+ RECT 692.320000 1357.360000 693.420000 1357.840000 ;
+ RECT 692.320000 1362.800000 693.420000 1363.280000 ;
+ RECT 692.320000 1368.240000 693.420000 1368.720000 ;
+ RECT 647.320000 1395.440000 648.420000 1395.920000 ;
+ RECT 643.190000 1395.440000 644.190000 1395.920000 ;
+ RECT 647.320000 1390.000000 648.420000 1390.480000 ;
+ RECT 643.190000 1390.000000 644.190000 1390.480000 ;
+ RECT 647.320000 1379.120000 648.420000 1379.600000 ;
+ RECT 643.190000 1379.120000 644.190000 1379.600000 ;
+ RECT 647.320000 1373.680000 648.420000 1374.160000 ;
+ RECT 643.190000 1373.680000 644.190000 1374.160000 ;
+ RECT 647.320000 1384.560000 648.420000 1385.040000 ;
+ RECT 643.190000 1384.560000 644.190000 1385.040000 ;
+ RECT 647.320000 1368.240000 648.420000 1368.720000 ;
+ RECT 643.190000 1368.240000 644.190000 1368.720000 ;
+ RECT 647.320000 1362.800000 648.420000 1363.280000 ;
+ RECT 643.190000 1362.800000 644.190000 1363.280000 ;
+ RECT 647.320000 1357.360000 648.420000 1357.840000 ;
+ RECT 647.320000 1351.920000 648.420000 1352.400000 ;
+ RECT 643.190000 1357.360000 644.190000 1357.840000 ;
+ RECT 643.190000 1351.920000 644.190000 1352.400000 ;
+ RECT 640.360000 1542.280000 840.460000 1543.280000 ;
+ RECT 640.360000 1349.910000 840.460000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 1347.060000 644.190000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 1546.320000 644.190000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 1347.060000 837.630000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 1546.320000 837.630000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1349.910000 641.360000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1349.910000 840.460000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1542.280000 641.360000 1543.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1542.280000 840.460000 1543.280000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 1149.650000 828.420000 1343.020000 ;
+ RECT 782.320000 1149.650000 783.420000 1343.020000 ;
+ RECT 836.630000 1146.800000 837.630000 1347.060000 ;
+ RECT 737.320000 1149.650000 738.420000 1343.020000 ;
+ RECT 692.320000 1149.650000 693.420000 1343.020000 ;
+ RECT 647.320000 1149.650000 648.420000 1343.020000 ;
+ RECT 643.190000 1146.800000 644.190000 1347.060000 ;
+ LAYER met3 ;
+ RECT 827.320000 1336.620000 828.420000 1337.100000 ;
+ RECT 836.630000 1336.620000 837.630000 1337.100000 ;
+ RECT 836.630000 1325.740000 837.630000 1326.220000 ;
+ RECT 836.630000 1331.180000 837.630000 1331.660000 ;
+ RECT 827.320000 1331.180000 828.420000 1331.660000 ;
+ RECT 827.320000 1325.740000 828.420000 1326.220000 ;
+ RECT 827.320000 1320.300000 828.420000 1320.780000 ;
+ RECT 827.320000 1314.860000 828.420000 1315.340000 ;
+ RECT 836.630000 1320.300000 837.630000 1320.780000 ;
+ RECT 836.630000 1314.860000 837.630000 1315.340000 ;
+ RECT 827.320000 1298.540000 828.420000 1299.020000 ;
+ RECT 827.320000 1303.980000 828.420000 1304.460000 ;
+ RECT 836.630000 1303.980000 837.630000 1304.460000 ;
+ RECT 836.630000 1298.540000 837.630000 1299.020000 ;
+ RECT 827.320000 1309.420000 828.420000 1309.900000 ;
+ RECT 836.630000 1309.420000 837.630000 1309.900000 ;
+ RECT 782.320000 1336.620000 783.420000 1337.100000 ;
+ RECT 782.320000 1331.180000 783.420000 1331.660000 ;
+ RECT 782.320000 1325.740000 783.420000 1326.220000 ;
+ RECT 782.320000 1320.300000 783.420000 1320.780000 ;
+ RECT 782.320000 1298.540000 783.420000 1299.020000 ;
+ RECT 782.320000 1303.980000 783.420000 1304.460000 ;
+ RECT 782.320000 1309.420000 783.420000 1309.900000 ;
+ RECT 782.320000 1314.860000 783.420000 1315.340000 ;
+ RECT 836.630000 1287.660000 837.630000 1288.140000 ;
+ RECT 836.630000 1293.100000 837.630000 1293.580000 ;
+ RECT 827.320000 1293.100000 828.420000 1293.580000 ;
+ RECT 827.320000 1287.660000 828.420000 1288.140000 ;
+ RECT 827.320000 1282.220000 828.420000 1282.700000 ;
+ RECT 827.320000 1276.780000 828.420000 1277.260000 ;
+ RECT 836.630000 1282.220000 837.630000 1282.700000 ;
+ RECT 836.630000 1276.780000 837.630000 1277.260000 ;
+ RECT 836.630000 1260.460000 837.630000 1260.940000 ;
+ RECT 836.630000 1265.900000 837.630000 1266.380000 ;
+ RECT 836.630000 1271.340000 837.630000 1271.820000 ;
+ RECT 827.320000 1265.900000 828.420000 1266.380000 ;
+ RECT 827.320000 1260.460000 828.420000 1260.940000 ;
+ RECT 827.320000 1271.340000 828.420000 1271.820000 ;
+ RECT 827.320000 1255.020000 828.420000 1255.500000 ;
+ RECT 827.320000 1249.580000 828.420000 1250.060000 ;
+ RECT 836.630000 1255.020000 837.630000 1255.500000 ;
+ RECT 836.630000 1249.580000 837.630000 1250.060000 ;
+ RECT 782.320000 1293.100000 783.420000 1293.580000 ;
+ RECT 782.320000 1287.660000 783.420000 1288.140000 ;
+ RECT 782.320000 1282.220000 783.420000 1282.700000 ;
+ RECT 782.320000 1276.780000 783.420000 1277.260000 ;
+ RECT 782.320000 1265.900000 783.420000 1266.380000 ;
+ RECT 782.320000 1260.460000 783.420000 1260.940000 ;
+ RECT 782.320000 1255.020000 783.420000 1255.500000 ;
+ RECT 782.320000 1249.580000 783.420000 1250.060000 ;
+ RECT 782.320000 1271.340000 783.420000 1271.820000 ;
+ RECT 737.320000 1336.620000 738.420000 1337.100000 ;
+ RECT 737.320000 1331.180000 738.420000 1331.660000 ;
+ RECT 737.320000 1325.740000 738.420000 1326.220000 ;
+ RECT 692.320000 1336.620000 693.420000 1337.100000 ;
+ RECT 692.320000 1331.180000 693.420000 1331.660000 ;
+ RECT 692.320000 1325.740000 693.420000 1326.220000 ;
+ RECT 737.320000 1309.420000 738.420000 1309.900000 ;
+ RECT 737.320000 1303.980000 738.420000 1304.460000 ;
+ RECT 737.320000 1298.540000 738.420000 1299.020000 ;
+ RECT 737.320000 1314.860000 738.420000 1315.340000 ;
+ RECT 737.320000 1320.300000 738.420000 1320.780000 ;
+ RECT 692.320000 1320.300000 693.420000 1320.780000 ;
+ RECT 692.320000 1309.420000 693.420000 1309.900000 ;
+ RECT 692.320000 1303.980000 693.420000 1304.460000 ;
+ RECT 692.320000 1298.540000 693.420000 1299.020000 ;
+ RECT 692.320000 1314.860000 693.420000 1315.340000 ;
+ RECT 647.320000 1336.620000 648.420000 1337.100000 ;
+ RECT 643.190000 1336.620000 644.190000 1337.100000 ;
+ RECT 643.190000 1331.180000 644.190000 1331.660000 ;
+ RECT 647.320000 1331.180000 648.420000 1331.660000 ;
+ RECT 647.320000 1325.740000 648.420000 1326.220000 ;
+ RECT 643.190000 1325.740000 644.190000 1326.220000 ;
+ RECT 647.320000 1320.300000 648.420000 1320.780000 ;
+ RECT 643.190000 1320.300000 644.190000 1320.780000 ;
+ RECT 647.320000 1314.860000 648.420000 1315.340000 ;
+ RECT 643.190000 1314.860000 644.190000 1315.340000 ;
+ RECT 647.320000 1303.980000 648.420000 1304.460000 ;
+ RECT 643.190000 1303.980000 644.190000 1304.460000 ;
+ RECT 647.320000 1298.540000 648.420000 1299.020000 ;
+ RECT 643.190000 1298.540000 644.190000 1299.020000 ;
+ RECT 647.320000 1309.420000 648.420000 1309.900000 ;
+ RECT 643.190000 1309.420000 644.190000 1309.900000 ;
+ RECT 737.320000 1293.100000 738.420000 1293.580000 ;
+ RECT 737.320000 1287.660000 738.420000 1288.140000 ;
+ RECT 737.320000 1282.220000 738.420000 1282.700000 ;
+ RECT 737.320000 1276.780000 738.420000 1277.260000 ;
+ RECT 692.320000 1293.100000 693.420000 1293.580000 ;
+ RECT 692.320000 1287.660000 693.420000 1288.140000 ;
+ RECT 692.320000 1282.220000 693.420000 1282.700000 ;
+ RECT 692.320000 1276.780000 693.420000 1277.260000 ;
+ RECT 737.320000 1265.900000 738.420000 1266.380000 ;
+ RECT 737.320000 1249.580000 738.420000 1250.060000 ;
+ RECT 737.320000 1255.020000 738.420000 1255.500000 ;
+ RECT 737.320000 1260.460000 738.420000 1260.940000 ;
+ RECT 737.320000 1271.340000 738.420000 1271.820000 ;
+ RECT 692.320000 1249.580000 693.420000 1250.060000 ;
+ RECT 692.320000 1255.020000 693.420000 1255.500000 ;
+ RECT 692.320000 1260.460000 693.420000 1260.940000 ;
+ RECT 692.320000 1265.900000 693.420000 1266.380000 ;
+ RECT 692.320000 1271.340000 693.420000 1271.820000 ;
+ RECT 647.320000 1293.100000 648.420000 1293.580000 ;
+ RECT 643.190000 1293.100000 644.190000 1293.580000 ;
+ RECT 647.320000 1287.660000 648.420000 1288.140000 ;
+ RECT 643.190000 1287.660000 644.190000 1288.140000 ;
+ RECT 647.320000 1282.220000 648.420000 1282.700000 ;
+ RECT 643.190000 1282.220000 644.190000 1282.700000 ;
+ RECT 647.320000 1276.780000 648.420000 1277.260000 ;
+ RECT 643.190000 1276.780000 644.190000 1277.260000 ;
+ RECT 647.320000 1271.340000 648.420000 1271.820000 ;
+ RECT 647.320000 1265.900000 648.420000 1266.380000 ;
+ RECT 643.190000 1271.340000 644.190000 1271.820000 ;
+ RECT 643.190000 1265.900000 644.190000 1266.380000 ;
+ RECT 647.320000 1260.460000 648.420000 1260.940000 ;
+ RECT 643.190000 1260.460000 644.190000 1260.940000 ;
+ RECT 647.320000 1255.020000 648.420000 1255.500000 ;
+ RECT 643.190000 1255.020000 644.190000 1255.500000 ;
+ RECT 647.320000 1249.580000 648.420000 1250.060000 ;
+ RECT 643.190000 1249.580000 644.190000 1250.060000 ;
+ RECT 827.320000 1244.140000 828.420000 1244.620000 ;
+ RECT 827.320000 1238.700000 828.420000 1239.180000 ;
+ RECT 836.630000 1244.140000 837.630000 1244.620000 ;
+ RECT 836.630000 1238.700000 837.630000 1239.180000 ;
+ RECT 836.630000 1222.380000 837.630000 1222.860000 ;
+ RECT 836.630000 1227.820000 837.630000 1228.300000 ;
+ RECT 836.630000 1233.260000 837.630000 1233.740000 ;
+ RECT 827.320000 1233.260000 828.420000 1233.740000 ;
+ RECT 827.320000 1227.820000 828.420000 1228.300000 ;
+ RECT 827.320000 1222.380000 828.420000 1222.860000 ;
+ RECT 827.320000 1211.500000 828.420000 1211.980000 ;
+ RECT 827.320000 1216.940000 828.420000 1217.420000 ;
+ RECT 836.630000 1216.940000 837.630000 1217.420000 ;
+ RECT 836.630000 1211.500000 837.630000 1211.980000 ;
+ RECT 836.630000 1200.620000 837.630000 1201.100000 ;
+ RECT 836.630000 1206.060000 837.630000 1206.540000 ;
+ RECT 827.320000 1200.620000 828.420000 1201.100000 ;
+ RECT 827.320000 1206.060000 828.420000 1206.540000 ;
+ RECT 782.320000 1244.140000 783.420000 1244.620000 ;
+ RECT 782.320000 1238.700000 783.420000 1239.180000 ;
+ RECT 782.320000 1233.260000 783.420000 1233.740000 ;
+ RECT 782.320000 1227.820000 783.420000 1228.300000 ;
+ RECT 782.320000 1222.380000 783.420000 1222.860000 ;
+ RECT 782.320000 1200.620000 783.420000 1201.100000 ;
+ RECT 782.320000 1206.060000 783.420000 1206.540000 ;
+ RECT 782.320000 1211.500000 783.420000 1211.980000 ;
+ RECT 782.320000 1216.940000 783.420000 1217.420000 ;
+ RECT 827.320000 1195.180000 828.420000 1195.660000 ;
+ RECT 827.320000 1189.740000 828.420000 1190.220000 ;
+ RECT 836.630000 1195.180000 837.630000 1195.660000 ;
+ RECT 836.630000 1189.740000 837.630000 1190.220000 ;
+ RECT 827.320000 1178.860000 828.420000 1179.340000 ;
+ RECT 827.320000 1173.420000 828.420000 1173.900000 ;
+ RECT 836.630000 1178.860000 837.630000 1179.340000 ;
+ RECT 836.630000 1173.420000 837.630000 1173.900000 ;
+ RECT 827.320000 1184.300000 828.420000 1184.780000 ;
+ RECT 836.630000 1184.300000 837.630000 1184.780000 ;
+ RECT 836.630000 1162.540000 837.630000 1163.020000 ;
+ RECT 836.630000 1167.980000 837.630000 1168.460000 ;
+ RECT 827.320000 1167.980000 828.420000 1168.460000 ;
+ RECT 827.320000 1162.540000 828.420000 1163.020000 ;
+ RECT 827.320000 1157.100000 828.420000 1157.580000 ;
+ RECT 827.320000 1151.660000 828.420000 1152.140000 ;
+ RECT 836.630000 1157.100000 837.630000 1157.580000 ;
+ RECT 836.630000 1151.660000 837.630000 1152.140000 ;
+ RECT 782.320000 1195.180000 783.420000 1195.660000 ;
+ RECT 782.320000 1189.740000 783.420000 1190.220000 ;
+ RECT 782.320000 1184.300000 783.420000 1184.780000 ;
+ RECT 782.320000 1178.860000 783.420000 1179.340000 ;
+ RECT 782.320000 1173.420000 783.420000 1173.900000 ;
+ RECT 782.320000 1167.980000 783.420000 1168.460000 ;
+ RECT 782.320000 1162.540000 783.420000 1163.020000 ;
+ RECT 782.320000 1157.100000 783.420000 1157.580000 ;
+ RECT 782.320000 1151.660000 783.420000 1152.140000 ;
+ RECT 737.320000 1244.140000 738.420000 1244.620000 ;
+ RECT 737.320000 1238.700000 738.420000 1239.180000 ;
+ RECT 737.320000 1233.260000 738.420000 1233.740000 ;
+ RECT 737.320000 1227.820000 738.420000 1228.300000 ;
+ RECT 737.320000 1222.380000 738.420000 1222.860000 ;
+ RECT 692.320000 1244.140000 693.420000 1244.620000 ;
+ RECT 692.320000 1238.700000 693.420000 1239.180000 ;
+ RECT 692.320000 1233.260000 693.420000 1233.740000 ;
+ RECT 692.320000 1227.820000 693.420000 1228.300000 ;
+ RECT 692.320000 1222.380000 693.420000 1222.860000 ;
+ RECT 737.320000 1216.940000 738.420000 1217.420000 ;
+ RECT 737.320000 1211.500000 738.420000 1211.980000 ;
+ RECT 737.320000 1206.060000 738.420000 1206.540000 ;
+ RECT 737.320000 1200.620000 738.420000 1201.100000 ;
+ RECT 692.320000 1211.500000 693.420000 1211.980000 ;
+ RECT 692.320000 1206.060000 693.420000 1206.540000 ;
+ RECT 692.320000 1200.620000 693.420000 1201.100000 ;
+ RECT 692.320000 1216.940000 693.420000 1217.420000 ;
+ RECT 647.320000 1244.140000 648.420000 1244.620000 ;
+ RECT 643.190000 1244.140000 644.190000 1244.620000 ;
+ RECT 647.320000 1238.700000 648.420000 1239.180000 ;
+ RECT 643.190000 1238.700000 644.190000 1239.180000 ;
+ RECT 647.320000 1233.260000 648.420000 1233.740000 ;
+ RECT 643.190000 1233.260000 644.190000 1233.740000 ;
+ RECT 647.320000 1222.380000 648.420000 1222.860000 ;
+ RECT 643.190000 1222.380000 644.190000 1222.860000 ;
+ RECT 643.190000 1227.820000 644.190000 1228.300000 ;
+ RECT 647.320000 1227.820000 648.420000 1228.300000 ;
+ RECT 647.320000 1216.940000 648.420000 1217.420000 ;
+ RECT 643.190000 1216.940000 644.190000 1217.420000 ;
+ RECT 647.320000 1211.500000 648.420000 1211.980000 ;
+ RECT 643.190000 1211.500000 644.190000 1211.980000 ;
+ RECT 647.320000 1206.060000 648.420000 1206.540000 ;
+ RECT 643.190000 1206.060000 644.190000 1206.540000 ;
+ RECT 647.320000 1200.620000 648.420000 1201.100000 ;
+ RECT 643.190000 1200.620000 644.190000 1201.100000 ;
+ RECT 737.320000 1195.180000 738.420000 1195.660000 ;
+ RECT 737.320000 1189.740000 738.420000 1190.220000 ;
+ RECT 737.320000 1184.300000 738.420000 1184.780000 ;
+ RECT 737.320000 1178.860000 738.420000 1179.340000 ;
+ RECT 737.320000 1173.420000 738.420000 1173.900000 ;
+ RECT 692.320000 1195.180000 693.420000 1195.660000 ;
+ RECT 692.320000 1189.740000 693.420000 1190.220000 ;
+ RECT 692.320000 1184.300000 693.420000 1184.780000 ;
+ RECT 692.320000 1178.860000 693.420000 1179.340000 ;
+ RECT 692.320000 1173.420000 693.420000 1173.900000 ;
+ RECT 737.320000 1151.660000 738.420000 1152.140000 ;
+ RECT 737.320000 1157.100000 738.420000 1157.580000 ;
+ RECT 737.320000 1162.540000 738.420000 1163.020000 ;
+ RECT 737.320000 1167.980000 738.420000 1168.460000 ;
+ RECT 692.320000 1151.660000 693.420000 1152.140000 ;
+ RECT 692.320000 1157.100000 693.420000 1157.580000 ;
+ RECT 692.320000 1162.540000 693.420000 1163.020000 ;
+ RECT 692.320000 1167.980000 693.420000 1168.460000 ;
+ RECT 647.320000 1195.180000 648.420000 1195.660000 ;
+ RECT 643.190000 1195.180000 644.190000 1195.660000 ;
+ RECT 647.320000 1189.740000 648.420000 1190.220000 ;
+ RECT 643.190000 1189.740000 644.190000 1190.220000 ;
+ RECT 647.320000 1178.860000 648.420000 1179.340000 ;
+ RECT 643.190000 1178.860000 644.190000 1179.340000 ;
+ RECT 647.320000 1173.420000 648.420000 1173.900000 ;
+ RECT 643.190000 1173.420000 644.190000 1173.900000 ;
+ RECT 647.320000 1184.300000 648.420000 1184.780000 ;
+ RECT 643.190000 1184.300000 644.190000 1184.780000 ;
+ RECT 647.320000 1167.980000 648.420000 1168.460000 ;
+ RECT 643.190000 1167.980000 644.190000 1168.460000 ;
+ RECT 647.320000 1162.540000 648.420000 1163.020000 ;
+ RECT 643.190000 1162.540000 644.190000 1163.020000 ;
+ RECT 647.320000 1157.100000 648.420000 1157.580000 ;
+ RECT 647.320000 1151.660000 648.420000 1152.140000 ;
+ RECT 643.190000 1157.100000 644.190000 1157.580000 ;
+ RECT 643.190000 1151.660000 644.190000 1152.140000 ;
+ RECT 640.360000 1342.020000 840.460000 1343.020000 ;
+ RECT 640.360000 1149.650000 840.460000 1150.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 1146.800000 644.190000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 1346.060000 644.190000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 1146.800000 837.630000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 1346.060000 837.630000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1149.650000 641.360000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1149.650000 840.460000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1342.020000 641.360000 1343.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1342.020000 840.460000 1343.020000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 949.390000 828.420000 1142.760000 ;
+ RECT 782.320000 949.390000 783.420000 1142.760000 ;
+ RECT 836.630000 946.540000 837.630000 1146.800000 ;
+ RECT 737.320000 949.390000 738.420000 1142.760000 ;
+ RECT 692.320000 949.390000 693.420000 1142.760000 ;
+ RECT 647.320000 949.390000 648.420000 1142.760000 ;
+ RECT 643.190000 946.540000 644.190000 1146.800000 ;
+ LAYER met3 ;
+ RECT 827.320000 1136.360000 828.420000 1136.840000 ;
+ RECT 836.630000 1136.360000 837.630000 1136.840000 ;
+ RECT 836.630000 1125.480000 837.630000 1125.960000 ;
+ RECT 836.630000 1130.920000 837.630000 1131.400000 ;
+ RECT 827.320000 1130.920000 828.420000 1131.400000 ;
+ RECT 827.320000 1125.480000 828.420000 1125.960000 ;
+ RECT 827.320000 1120.040000 828.420000 1120.520000 ;
+ RECT 827.320000 1114.600000 828.420000 1115.080000 ;
+ RECT 836.630000 1120.040000 837.630000 1120.520000 ;
+ RECT 836.630000 1114.600000 837.630000 1115.080000 ;
+ RECT 827.320000 1098.280000 828.420000 1098.760000 ;
+ RECT 827.320000 1103.720000 828.420000 1104.200000 ;
+ RECT 836.630000 1103.720000 837.630000 1104.200000 ;
+ RECT 836.630000 1098.280000 837.630000 1098.760000 ;
+ RECT 827.320000 1109.160000 828.420000 1109.640000 ;
+ RECT 836.630000 1109.160000 837.630000 1109.640000 ;
+ RECT 782.320000 1136.360000 783.420000 1136.840000 ;
+ RECT 782.320000 1130.920000 783.420000 1131.400000 ;
+ RECT 782.320000 1125.480000 783.420000 1125.960000 ;
+ RECT 782.320000 1120.040000 783.420000 1120.520000 ;
+ RECT 782.320000 1098.280000 783.420000 1098.760000 ;
+ RECT 782.320000 1103.720000 783.420000 1104.200000 ;
+ RECT 782.320000 1109.160000 783.420000 1109.640000 ;
+ RECT 782.320000 1114.600000 783.420000 1115.080000 ;
+ RECT 836.630000 1087.400000 837.630000 1087.880000 ;
+ RECT 836.630000 1092.840000 837.630000 1093.320000 ;
+ RECT 827.320000 1092.840000 828.420000 1093.320000 ;
+ RECT 827.320000 1087.400000 828.420000 1087.880000 ;
+ RECT 827.320000 1081.960000 828.420000 1082.440000 ;
+ RECT 827.320000 1076.520000 828.420000 1077.000000 ;
+ RECT 836.630000 1081.960000 837.630000 1082.440000 ;
+ RECT 836.630000 1076.520000 837.630000 1077.000000 ;
+ RECT 836.630000 1060.200000 837.630000 1060.680000 ;
+ RECT 836.630000 1065.640000 837.630000 1066.120000 ;
+ RECT 836.630000 1071.080000 837.630000 1071.560000 ;
+ RECT 827.320000 1065.640000 828.420000 1066.120000 ;
+ RECT 827.320000 1060.200000 828.420000 1060.680000 ;
+ RECT 827.320000 1071.080000 828.420000 1071.560000 ;
+ RECT 827.320000 1054.760000 828.420000 1055.240000 ;
+ RECT 827.320000 1049.320000 828.420000 1049.800000 ;
+ RECT 836.630000 1054.760000 837.630000 1055.240000 ;
+ RECT 836.630000 1049.320000 837.630000 1049.800000 ;
+ RECT 782.320000 1092.840000 783.420000 1093.320000 ;
+ RECT 782.320000 1087.400000 783.420000 1087.880000 ;
+ RECT 782.320000 1081.960000 783.420000 1082.440000 ;
+ RECT 782.320000 1076.520000 783.420000 1077.000000 ;
+ RECT 782.320000 1065.640000 783.420000 1066.120000 ;
+ RECT 782.320000 1060.200000 783.420000 1060.680000 ;
+ RECT 782.320000 1054.760000 783.420000 1055.240000 ;
+ RECT 782.320000 1049.320000 783.420000 1049.800000 ;
+ RECT 782.320000 1071.080000 783.420000 1071.560000 ;
+ RECT 737.320000 1136.360000 738.420000 1136.840000 ;
+ RECT 737.320000 1130.920000 738.420000 1131.400000 ;
+ RECT 737.320000 1125.480000 738.420000 1125.960000 ;
+ RECT 692.320000 1136.360000 693.420000 1136.840000 ;
+ RECT 692.320000 1130.920000 693.420000 1131.400000 ;
+ RECT 692.320000 1125.480000 693.420000 1125.960000 ;
+ RECT 737.320000 1109.160000 738.420000 1109.640000 ;
+ RECT 737.320000 1103.720000 738.420000 1104.200000 ;
+ RECT 737.320000 1098.280000 738.420000 1098.760000 ;
+ RECT 737.320000 1114.600000 738.420000 1115.080000 ;
+ RECT 737.320000 1120.040000 738.420000 1120.520000 ;
+ RECT 692.320000 1120.040000 693.420000 1120.520000 ;
+ RECT 692.320000 1109.160000 693.420000 1109.640000 ;
+ RECT 692.320000 1103.720000 693.420000 1104.200000 ;
+ RECT 692.320000 1098.280000 693.420000 1098.760000 ;
+ RECT 692.320000 1114.600000 693.420000 1115.080000 ;
+ RECT 647.320000 1136.360000 648.420000 1136.840000 ;
+ RECT 643.190000 1136.360000 644.190000 1136.840000 ;
+ RECT 643.190000 1130.920000 644.190000 1131.400000 ;
+ RECT 647.320000 1130.920000 648.420000 1131.400000 ;
+ RECT 647.320000 1125.480000 648.420000 1125.960000 ;
+ RECT 643.190000 1125.480000 644.190000 1125.960000 ;
+ RECT 647.320000 1120.040000 648.420000 1120.520000 ;
+ RECT 643.190000 1120.040000 644.190000 1120.520000 ;
+ RECT 647.320000 1114.600000 648.420000 1115.080000 ;
+ RECT 643.190000 1114.600000 644.190000 1115.080000 ;
+ RECT 647.320000 1103.720000 648.420000 1104.200000 ;
+ RECT 643.190000 1103.720000 644.190000 1104.200000 ;
+ RECT 647.320000 1098.280000 648.420000 1098.760000 ;
+ RECT 643.190000 1098.280000 644.190000 1098.760000 ;
+ RECT 647.320000 1109.160000 648.420000 1109.640000 ;
+ RECT 643.190000 1109.160000 644.190000 1109.640000 ;
+ RECT 737.320000 1092.840000 738.420000 1093.320000 ;
+ RECT 737.320000 1087.400000 738.420000 1087.880000 ;
+ RECT 737.320000 1081.960000 738.420000 1082.440000 ;
+ RECT 737.320000 1076.520000 738.420000 1077.000000 ;
+ RECT 692.320000 1092.840000 693.420000 1093.320000 ;
+ RECT 692.320000 1087.400000 693.420000 1087.880000 ;
+ RECT 692.320000 1081.960000 693.420000 1082.440000 ;
+ RECT 692.320000 1076.520000 693.420000 1077.000000 ;
+ RECT 737.320000 1065.640000 738.420000 1066.120000 ;
+ RECT 737.320000 1049.320000 738.420000 1049.800000 ;
+ RECT 737.320000 1054.760000 738.420000 1055.240000 ;
+ RECT 737.320000 1060.200000 738.420000 1060.680000 ;
+ RECT 737.320000 1071.080000 738.420000 1071.560000 ;
+ RECT 692.320000 1049.320000 693.420000 1049.800000 ;
+ RECT 692.320000 1054.760000 693.420000 1055.240000 ;
+ RECT 692.320000 1060.200000 693.420000 1060.680000 ;
+ RECT 692.320000 1065.640000 693.420000 1066.120000 ;
+ RECT 692.320000 1071.080000 693.420000 1071.560000 ;
+ RECT 647.320000 1092.840000 648.420000 1093.320000 ;
+ RECT 643.190000 1092.840000 644.190000 1093.320000 ;
+ RECT 647.320000 1087.400000 648.420000 1087.880000 ;
+ RECT 643.190000 1087.400000 644.190000 1087.880000 ;
+ RECT 647.320000 1081.960000 648.420000 1082.440000 ;
+ RECT 643.190000 1081.960000 644.190000 1082.440000 ;
+ RECT 647.320000 1076.520000 648.420000 1077.000000 ;
+ RECT 643.190000 1076.520000 644.190000 1077.000000 ;
+ RECT 647.320000 1071.080000 648.420000 1071.560000 ;
+ RECT 647.320000 1065.640000 648.420000 1066.120000 ;
+ RECT 643.190000 1071.080000 644.190000 1071.560000 ;
+ RECT 643.190000 1065.640000 644.190000 1066.120000 ;
+ RECT 647.320000 1060.200000 648.420000 1060.680000 ;
+ RECT 643.190000 1060.200000 644.190000 1060.680000 ;
+ RECT 647.320000 1054.760000 648.420000 1055.240000 ;
+ RECT 643.190000 1054.760000 644.190000 1055.240000 ;
+ RECT 647.320000 1049.320000 648.420000 1049.800000 ;
+ RECT 643.190000 1049.320000 644.190000 1049.800000 ;
+ RECT 827.320000 1043.880000 828.420000 1044.360000 ;
+ RECT 827.320000 1038.440000 828.420000 1038.920000 ;
+ RECT 836.630000 1043.880000 837.630000 1044.360000 ;
+ RECT 836.630000 1038.440000 837.630000 1038.920000 ;
+ RECT 836.630000 1022.120000 837.630000 1022.600000 ;
+ RECT 836.630000 1027.560000 837.630000 1028.040000 ;
+ RECT 836.630000 1033.000000 837.630000 1033.480000 ;
+ RECT 827.320000 1033.000000 828.420000 1033.480000 ;
+ RECT 827.320000 1027.560000 828.420000 1028.040000 ;
+ RECT 827.320000 1022.120000 828.420000 1022.600000 ;
+ RECT 827.320000 1011.240000 828.420000 1011.720000 ;
+ RECT 827.320000 1016.680000 828.420000 1017.160000 ;
+ RECT 836.630000 1016.680000 837.630000 1017.160000 ;
+ RECT 836.630000 1011.240000 837.630000 1011.720000 ;
+ RECT 836.630000 1000.360000 837.630000 1000.840000 ;
+ RECT 836.630000 1005.800000 837.630000 1006.280000 ;
+ RECT 827.320000 1000.360000 828.420000 1000.840000 ;
+ RECT 827.320000 1005.800000 828.420000 1006.280000 ;
+ RECT 782.320000 1043.880000 783.420000 1044.360000 ;
+ RECT 782.320000 1038.440000 783.420000 1038.920000 ;
+ RECT 782.320000 1033.000000 783.420000 1033.480000 ;
+ RECT 782.320000 1027.560000 783.420000 1028.040000 ;
+ RECT 782.320000 1022.120000 783.420000 1022.600000 ;
+ RECT 782.320000 1000.360000 783.420000 1000.840000 ;
+ RECT 782.320000 1005.800000 783.420000 1006.280000 ;
+ RECT 782.320000 1011.240000 783.420000 1011.720000 ;
+ RECT 782.320000 1016.680000 783.420000 1017.160000 ;
+ RECT 827.320000 994.920000 828.420000 995.400000 ;
+ RECT 827.320000 989.480000 828.420000 989.960000 ;
+ RECT 836.630000 994.920000 837.630000 995.400000 ;
+ RECT 836.630000 989.480000 837.630000 989.960000 ;
+ RECT 827.320000 978.600000 828.420000 979.080000 ;
+ RECT 827.320000 973.160000 828.420000 973.640000 ;
+ RECT 836.630000 978.600000 837.630000 979.080000 ;
+ RECT 836.630000 973.160000 837.630000 973.640000 ;
+ RECT 827.320000 984.040000 828.420000 984.520000 ;
+ RECT 836.630000 984.040000 837.630000 984.520000 ;
+ RECT 836.630000 962.280000 837.630000 962.760000 ;
+ RECT 836.630000 967.720000 837.630000 968.200000 ;
+ RECT 827.320000 967.720000 828.420000 968.200000 ;
+ RECT 827.320000 962.280000 828.420000 962.760000 ;
+ RECT 827.320000 956.840000 828.420000 957.320000 ;
+ RECT 827.320000 951.400000 828.420000 951.880000 ;
+ RECT 836.630000 956.840000 837.630000 957.320000 ;
+ RECT 836.630000 951.400000 837.630000 951.880000 ;
+ RECT 782.320000 994.920000 783.420000 995.400000 ;
+ RECT 782.320000 989.480000 783.420000 989.960000 ;
+ RECT 782.320000 984.040000 783.420000 984.520000 ;
+ RECT 782.320000 978.600000 783.420000 979.080000 ;
+ RECT 782.320000 973.160000 783.420000 973.640000 ;
+ RECT 782.320000 967.720000 783.420000 968.200000 ;
+ RECT 782.320000 962.280000 783.420000 962.760000 ;
+ RECT 782.320000 956.840000 783.420000 957.320000 ;
+ RECT 782.320000 951.400000 783.420000 951.880000 ;
+ RECT 737.320000 1043.880000 738.420000 1044.360000 ;
+ RECT 737.320000 1038.440000 738.420000 1038.920000 ;
+ RECT 737.320000 1033.000000 738.420000 1033.480000 ;
+ RECT 737.320000 1027.560000 738.420000 1028.040000 ;
+ RECT 737.320000 1022.120000 738.420000 1022.600000 ;
+ RECT 692.320000 1043.880000 693.420000 1044.360000 ;
+ RECT 692.320000 1038.440000 693.420000 1038.920000 ;
+ RECT 692.320000 1033.000000 693.420000 1033.480000 ;
+ RECT 692.320000 1027.560000 693.420000 1028.040000 ;
+ RECT 692.320000 1022.120000 693.420000 1022.600000 ;
+ RECT 737.320000 1016.680000 738.420000 1017.160000 ;
+ RECT 737.320000 1011.240000 738.420000 1011.720000 ;
+ RECT 737.320000 1005.800000 738.420000 1006.280000 ;
+ RECT 737.320000 1000.360000 738.420000 1000.840000 ;
+ RECT 692.320000 1011.240000 693.420000 1011.720000 ;
+ RECT 692.320000 1005.800000 693.420000 1006.280000 ;
+ RECT 692.320000 1000.360000 693.420000 1000.840000 ;
+ RECT 692.320000 1016.680000 693.420000 1017.160000 ;
+ RECT 647.320000 1043.880000 648.420000 1044.360000 ;
+ RECT 643.190000 1043.880000 644.190000 1044.360000 ;
+ RECT 647.320000 1038.440000 648.420000 1038.920000 ;
+ RECT 643.190000 1038.440000 644.190000 1038.920000 ;
+ RECT 647.320000 1033.000000 648.420000 1033.480000 ;
+ RECT 643.190000 1033.000000 644.190000 1033.480000 ;
+ RECT 647.320000 1022.120000 648.420000 1022.600000 ;
+ RECT 643.190000 1022.120000 644.190000 1022.600000 ;
+ RECT 643.190000 1027.560000 644.190000 1028.040000 ;
+ RECT 647.320000 1027.560000 648.420000 1028.040000 ;
+ RECT 647.320000 1016.680000 648.420000 1017.160000 ;
+ RECT 643.190000 1016.680000 644.190000 1017.160000 ;
+ RECT 647.320000 1011.240000 648.420000 1011.720000 ;
+ RECT 643.190000 1011.240000 644.190000 1011.720000 ;
+ RECT 647.320000 1005.800000 648.420000 1006.280000 ;
+ RECT 643.190000 1005.800000 644.190000 1006.280000 ;
+ RECT 647.320000 1000.360000 648.420000 1000.840000 ;
+ RECT 643.190000 1000.360000 644.190000 1000.840000 ;
+ RECT 737.320000 994.920000 738.420000 995.400000 ;
+ RECT 737.320000 989.480000 738.420000 989.960000 ;
+ RECT 737.320000 984.040000 738.420000 984.520000 ;
+ RECT 737.320000 978.600000 738.420000 979.080000 ;
+ RECT 737.320000 973.160000 738.420000 973.640000 ;
+ RECT 692.320000 994.920000 693.420000 995.400000 ;
+ RECT 692.320000 989.480000 693.420000 989.960000 ;
+ RECT 692.320000 984.040000 693.420000 984.520000 ;
+ RECT 692.320000 978.600000 693.420000 979.080000 ;
+ RECT 692.320000 973.160000 693.420000 973.640000 ;
+ RECT 737.320000 951.400000 738.420000 951.880000 ;
+ RECT 737.320000 956.840000 738.420000 957.320000 ;
+ RECT 737.320000 962.280000 738.420000 962.760000 ;
+ RECT 737.320000 967.720000 738.420000 968.200000 ;
+ RECT 692.320000 951.400000 693.420000 951.880000 ;
+ RECT 692.320000 956.840000 693.420000 957.320000 ;
+ RECT 692.320000 962.280000 693.420000 962.760000 ;
+ RECT 692.320000 967.720000 693.420000 968.200000 ;
+ RECT 647.320000 994.920000 648.420000 995.400000 ;
+ RECT 643.190000 994.920000 644.190000 995.400000 ;
+ RECT 647.320000 989.480000 648.420000 989.960000 ;
+ RECT 643.190000 989.480000 644.190000 989.960000 ;
+ RECT 647.320000 978.600000 648.420000 979.080000 ;
+ RECT 643.190000 978.600000 644.190000 979.080000 ;
+ RECT 647.320000 973.160000 648.420000 973.640000 ;
+ RECT 643.190000 973.160000 644.190000 973.640000 ;
+ RECT 647.320000 984.040000 648.420000 984.520000 ;
+ RECT 643.190000 984.040000 644.190000 984.520000 ;
+ RECT 647.320000 967.720000 648.420000 968.200000 ;
+ RECT 643.190000 967.720000 644.190000 968.200000 ;
+ RECT 647.320000 962.280000 648.420000 962.760000 ;
+ RECT 643.190000 962.280000 644.190000 962.760000 ;
+ RECT 647.320000 956.840000 648.420000 957.320000 ;
+ RECT 647.320000 951.400000 648.420000 951.880000 ;
+ RECT 643.190000 956.840000 644.190000 957.320000 ;
+ RECT 643.190000 951.400000 644.190000 951.880000 ;
+ RECT 640.360000 1141.760000 840.460000 1142.760000 ;
+ RECT 640.360000 949.390000 840.460000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 946.540000 644.190000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 1145.800000 644.190000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 946.540000 837.630000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 1145.800000 837.630000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 949.390000 641.360000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 949.390000 840.460000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1141.760000 641.360000 1142.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1141.760000 840.460000 1142.760000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 749.130000 828.420000 942.500000 ;
+ RECT 782.320000 749.130000 783.420000 942.500000 ;
+ RECT 836.630000 746.280000 837.630000 946.540000 ;
+ RECT 737.320000 749.130000 738.420000 942.500000 ;
+ RECT 692.320000 749.130000 693.420000 942.500000 ;
+ RECT 647.320000 749.130000 648.420000 942.500000 ;
+ RECT 643.190000 746.280000 644.190000 946.540000 ;
+ LAYER met3 ;
+ RECT 827.320000 936.100000 828.420000 936.580000 ;
+ RECT 836.630000 936.100000 837.630000 936.580000 ;
+ RECT 836.630000 925.220000 837.630000 925.700000 ;
+ RECT 836.630000 930.660000 837.630000 931.140000 ;
+ RECT 827.320000 930.660000 828.420000 931.140000 ;
+ RECT 827.320000 925.220000 828.420000 925.700000 ;
+ RECT 827.320000 919.780000 828.420000 920.260000 ;
+ RECT 827.320000 914.340000 828.420000 914.820000 ;
+ RECT 836.630000 919.780000 837.630000 920.260000 ;
+ RECT 836.630000 914.340000 837.630000 914.820000 ;
+ RECT 827.320000 898.020000 828.420000 898.500000 ;
+ RECT 827.320000 903.460000 828.420000 903.940000 ;
+ RECT 836.630000 903.460000 837.630000 903.940000 ;
+ RECT 836.630000 898.020000 837.630000 898.500000 ;
+ RECT 827.320000 908.900000 828.420000 909.380000 ;
+ RECT 836.630000 908.900000 837.630000 909.380000 ;
+ RECT 782.320000 936.100000 783.420000 936.580000 ;
+ RECT 782.320000 930.660000 783.420000 931.140000 ;
+ RECT 782.320000 925.220000 783.420000 925.700000 ;
+ RECT 782.320000 919.780000 783.420000 920.260000 ;
+ RECT 782.320000 898.020000 783.420000 898.500000 ;
+ RECT 782.320000 903.460000 783.420000 903.940000 ;
+ RECT 782.320000 908.900000 783.420000 909.380000 ;
+ RECT 782.320000 914.340000 783.420000 914.820000 ;
+ RECT 836.630000 887.140000 837.630000 887.620000 ;
+ RECT 836.630000 892.580000 837.630000 893.060000 ;
+ RECT 827.320000 892.580000 828.420000 893.060000 ;
+ RECT 827.320000 887.140000 828.420000 887.620000 ;
+ RECT 827.320000 881.700000 828.420000 882.180000 ;
+ RECT 827.320000 876.260000 828.420000 876.740000 ;
+ RECT 836.630000 881.700000 837.630000 882.180000 ;
+ RECT 836.630000 876.260000 837.630000 876.740000 ;
+ RECT 836.630000 859.940000 837.630000 860.420000 ;
+ RECT 836.630000 865.380000 837.630000 865.860000 ;
+ RECT 836.630000 870.820000 837.630000 871.300000 ;
+ RECT 827.320000 865.380000 828.420000 865.860000 ;
+ RECT 827.320000 859.940000 828.420000 860.420000 ;
+ RECT 827.320000 870.820000 828.420000 871.300000 ;
+ RECT 827.320000 854.500000 828.420000 854.980000 ;
+ RECT 827.320000 849.060000 828.420000 849.540000 ;
+ RECT 836.630000 854.500000 837.630000 854.980000 ;
+ RECT 836.630000 849.060000 837.630000 849.540000 ;
+ RECT 782.320000 892.580000 783.420000 893.060000 ;
+ RECT 782.320000 887.140000 783.420000 887.620000 ;
+ RECT 782.320000 881.700000 783.420000 882.180000 ;
+ RECT 782.320000 876.260000 783.420000 876.740000 ;
+ RECT 782.320000 865.380000 783.420000 865.860000 ;
+ RECT 782.320000 859.940000 783.420000 860.420000 ;
+ RECT 782.320000 854.500000 783.420000 854.980000 ;
+ RECT 782.320000 849.060000 783.420000 849.540000 ;
+ RECT 782.320000 870.820000 783.420000 871.300000 ;
+ RECT 737.320000 936.100000 738.420000 936.580000 ;
+ RECT 737.320000 930.660000 738.420000 931.140000 ;
+ RECT 737.320000 925.220000 738.420000 925.700000 ;
+ RECT 692.320000 936.100000 693.420000 936.580000 ;
+ RECT 692.320000 930.660000 693.420000 931.140000 ;
+ RECT 692.320000 925.220000 693.420000 925.700000 ;
+ RECT 737.320000 908.900000 738.420000 909.380000 ;
+ RECT 737.320000 903.460000 738.420000 903.940000 ;
+ RECT 737.320000 898.020000 738.420000 898.500000 ;
+ RECT 737.320000 914.340000 738.420000 914.820000 ;
+ RECT 737.320000 919.780000 738.420000 920.260000 ;
+ RECT 692.320000 919.780000 693.420000 920.260000 ;
+ RECT 692.320000 908.900000 693.420000 909.380000 ;
+ RECT 692.320000 903.460000 693.420000 903.940000 ;
+ RECT 692.320000 898.020000 693.420000 898.500000 ;
+ RECT 692.320000 914.340000 693.420000 914.820000 ;
+ RECT 647.320000 936.100000 648.420000 936.580000 ;
+ RECT 643.190000 936.100000 644.190000 936.580000 ;
+ RECT 643.190000 930.660000 644.190000 931.140000 ;
+ RECT 647.320000 930.660000 648.420000 931.140000 ;
+ RECT 647.320000 925.220000 648.420000 925.700000 ;
+ RECT 643.190000 925.220000 644.190000 925.700000 ;
+ RECT 647.320000 919.780000 648.420000 920.260000 ;
+ RECT 643.190000 919.780000 644.190000 920.260000 ;
+ RECT 647.320000 914.340000 648.420000 914.820000 ;
+ RECT 643.190000 914.340000 644.190000 914.820000 ;
+ RECT 647.320000 903.460000 648.420000 903.940000 ;
+ RECT 643.190000 903.460000 644.190000 903.940000 ;
+ RECT 647.320000 898.020000 648.420000 898.500000 ;
+ RECT 643.190000 898.020000 644.190000 898.500000 ;
+ RECT 647.320000 908.900000 648.420000 909.380000 ;
+ RECT 643.190000 908.900000 644.190000 909.380000 ;
+ RECT 737.320000 892.580000 738.420000 893.060000 ;
+ RECT 737.320000 887.140000 738.420000 887.620000 ;
+ RECT 737.320000 881.700000 738.420000 882.180000 ;
+ RECT 737.320000 876.260000 738.420000 876.740000 ;
+ RECT 692.320000 892.580000 693.420000 893.060000 ;
+ RECT 692.320000 887.140000 693.420000 887.620000 ;
+ RECT 692.320000 881.700000 693.420000 882.180000 ;
+ RECT 692.320000 876.260000 693.420000 876.740000 ;
+ RECT 737.320000 865.380000 738.420000 865.860000 ;
+ RECT 737.320000 849.060000 738.420000 849.540000 ;
+ RECT 737.320000 854.500000 738.420000 854.980000 ;
+ RECT 737.320000 859.940000 738.420000 860.420000 ;
+ RECT 737.320000 870.820000 738.420000 871.300000 ;
+ RECT 692.320000 849.060000 693.420000 849.540000 ;
+ RECT 692.320000 854.500000 693.420000 854.980000 ;
+ RECT 692.320000 859.940000 693.420000 860.420000 ;
+ RECT 692.320000 865.380000 693.420000 865.860000 ;
+ RECT 692.320000 870.820000 693.420000 871.300000 ;
+ RECT 647.320000 892.580000 648.420000 893.060000 ;
+ RECT 643.190000 892.580000 644.190000 893.060000 ;
+ RECT 647.320000 887.140000 648.420000 887.620000 ;
+ RECT 643.190000 887.140000 644.190000 887.620000 ;
+ RECT 647.320000 881.700000 648.420000 882.180000 ;
+ RECT 643.190000 881.700000 644.190000 882.180000 ;
+ RECT 647.320000 876.260000 648.420000 876.740000 ;
+ RECT 643.190000 876.260000 644.190000 876.740000 ;
+ RECT 647.320000 870.820000 648.420000 871.300000 ;
+ RECT 647.320000 865.380000 648.420000 865.860000 ;
+ RECT 643.190000 870.820000 644.190000 871.300000 ;
+ RECT 643.190000 865.380000 644.190000 865.860000 ;
+ RECT 647.320000 859.940000 648.420000 860.420000 ;
+ RECT 643.190000 859.940000 644.190000 860.420000 ;
+ RECT 647.320000 854.500000 648.420000 854.980000 ;
+ RECT 643.190000 854.500000 644.190000 854.980000 ;
+ RECT 647.320000 849.060000 648.420000 849.540000 ;
+ RECT 643.190000 849.060000 644.190000 849.540000 ;
+ RECT 827.320000 843.620000 828.420000 844.100000 ;
+ RECT 827.320000 838.180000 828.420000 838.660000 ;
+ RECT 836.630000 843.620000 837.630000 844.100000 ;
+ RECT 836.630000 838.180000 837.630000 838.660000 ;
+ RECT 836.630000 821.860000 837.630000 822.340000 ;
+ RECT 836.630000 827.300000 837.630000 827.780000 ;
+ RECT 836.630000 832.740000 837.630000 833.220000 ;
+ RECT 827.320000 832.740000 828.420000 833.220000 ;
+ RECT 827.320000 827.300000 828.420000 827.780000 ;
+ RECT 827.320000 821.860000 828.420000 822.340000 ;
+ RECT 827.320000 810.980000 828.420000 811.460000 ;
+ RECT 827.320000 816.420000 828.420000 816.900000 ;
+ RECT 836.630000 816.420000 837.630000 816.900000 ;
+ RECT 836.630000 810.980000 837.630000 811.460000 ;
+ RECT 836.630000 800.100000 837.630000 800.580000 ;
+ RECT 836.630000 805.540000 837.630000 806.020000 ;
+ RECT 827.320000 800.100000 828.420000 800.580000 ;
+ RECT 827.320000 805.540000 828.420000 806.020000 ;
+ RECT 782.320000 843.620000 783.420000 844.100000 ;
+ RECT 782.320000 838.180000 783.420000 838.660000 ;
+ RECT 782.320000 832.740000 783.420000 833.220000 ;
+ RECT 782.320000 827.300000 783.420000 827.780000 ;
+ RECT 782.320000 821.860000 783.420000 822.340000 ;
+ RECT 782.320000 800.100000 783.420000 800.580000 ;
+ RECT 782.320000 805.540000 783.420000 806.020000 ;
+ RECT 782.320000 810.980000 783.420000 811.460000 ;
+ RECT 782.320000 816.420000 783.420000 816.900000 ;
+ RECT 827.320000 794.660000 828.420000 795.140000 ;
+ RECT 827.320000 789.220000 828.420000 789.700000 ;
+ RECT 836.630000 794.660000 837.630000 795.140000 ;
+ RECT 836.630000 789.220000 837.630000 789.700000 ;
+ RECT 827.320000 778.340000 828.420000 778.820000 ;
+ RECT 827.320000 772.900000 828.420000 773.380000 ;
+ RECT 836.630000 778.340000 837.630000 778.820000 ;
+ RECT 836.630000 772.900000 837.630000 773.380000 ;
+ RECT 827.320000 783.780000 828.420000 784.260000 ;
+ RECT 836.630000 783.780000 837.630000 784.260000 ;
+ RECT 836.630000 762.020000 837.630000 762.500000 ;
+ RECT 836.630000 767.460000 837.630000 767.940000 ;
+ RECT 827.320000 767.460000 828.420000 767.940000 ;
+ RECT 827.320000 762.020000 828.420000 762.500000 ;
+ RECT 827.320000 756.580000 828.420000 757.060000 ;
+ RECT 827.320000 751.140000 828.420000 751.620000 ;
+ RECT 836.630000 756.580000 837.630000 757.060000 ;
+ RECT 836.630000 751.140000 837.630000 751.620000 ;
+ RECT 782.320000 794.660000 783.420000 795.140000 ;
+ RECT 782.320000 789.220000 783.420000 789.700000 ;
+ RECT 782.320000 783.780000 783.420000 784.260000 ;
+ RECT 782.320000 778.340000 783.420000 778.820000 ;
+ RECT 782.320000 772.900000 783.420000 773.380000 ;
+ RECT 782.320000 767.460000 783.420000 767.940000 ;
+ RECT 782.320000 762.020000 783.420000 762.500000 ;
+ RECT 782.320000 756.580000 783.420000 757.060000 ;
+ RECT 782.320000 751.140000 783.420000 751.620000 ;
+ RECT 737.320000 843.620000 738.420000 844.100000 ;
+ RECT 737.320000 838.180000 738.420000 838.660000 ;
+ RECT 737.320000 832.740000 738.420000 833.220000 ;
+ RECT 737.320000 827.300000 738.420000 827.780000 ;
+ RECT 737.320000 821.860000 738.420000 822.340000 ;
+ RECT 692.320000 843.620000 693.420000 844.100000 ;
+ RECT 692.320000 838.180000 693.420000 838.660000 ;
+ RECT 692.320000 832.740000 693.420000 833.220000 ;
+ RECT 692.320000 827.300000 693.420000 827.780000 ;
+ RECT 692.320000 821.860000 693.420000 822.340000 ;
+ RECT 737.320000 816.420000 738.420000 816.900000 ;
+ RECT 737.320000 810.980000 738.420000 811.460000 ;
+ RECT 737.320000 805.540000 738.420000 806.020000 ;
+ RECT 737.320000 800.100000 738.420000 800.580000 ;
+ RECT 692.320000 810.980000 693.420000 811.460000 ;
+ RECT 692.320000 805.540000 693.420000 806.020000 ;
+ RECT 692.320000 800.100000 693.420000 800.580000 ;
+ RECT 692.320000 816.420000 693.420000 816.900000 ;
+ RECT 647.320000 843.620000 648.420000 844.100000 ;
+ RECT 643.190000 843.620000 644.190000 844.100000 ;
+ RECT 647.320000 838.180000 648.420000 838.660000 ;
+ RECT 643.190000 838.180000 644.190000 838.660000 ;
+ RECT 647.320000 832.740000 648.420000 833.220000 ;
+ RECT 643.190000 832.740000 644.190000 833.220000 ;
+ RECT 647.320000 821.860000 648.420000 822.340000 ;
+ RECT 643.190000 821.860000 644.190000 822.340000 ;
+ RECT 643.190000 827.300000 644.190000 827.780000 ;
+ RECT 647.320000 827.300000 648.420000 827.780000 ;
+ RECT 647.320000 816.420000 648.420000 816.900000 ;
+ RECT 643.190000 816.420000 644.190000 816.900000 ;
+ RECT 647.320000 810.980000 648.420000 811.460000 ;
+ RECT 643.190000 810.980000 644.190000 811.460000 ;
+ RECT 647.320000 805.540000 648.420000 806.020000 ;
+ RECT 643.190000 805.540000 644.190000 806.020000 ;
+ RECT 647.320000 800.100000 648.420000 800.580000 ;
+ RECT 643.190000 800.100000 644.190000 800.580000 ;
+ RECT 737.320000 794.660000 738.420000 795.140000 ;
+ RECT 737.320000 789.220000 738.420000 789.700000 ;
+ RECT 737.320000 783.780000 738.420000 784.260000 ;
+ RECT 737.320000 778.340000 738.420000 778.820000 ;
+ RECT 737.320000 772.900000 738.420000 773.380000 ;
+ RECT 692.320000 794.660000 693.420000 795.140000 ;
+ RECT 692.320000 789.220000 693.420000 789.700000 ;
+ RECT 692.320000 783.780000 693.420000 784.260000 ;
+ RECT 692.320000 778.340000 693.420000 778.820000 ;
+ RECT 692.320000 772.900000 693.420000 773.380000 ;
+ RECT 737.320000 751.140000 738.420000 751.620000 ;
+ RECT 737.320000 756.580000 738.420000 757.060000 ;
+ RECT 737.320000 762.020000 738.420000 762.500000 ;
+ RECT 737.320000 767.460000 738.420000 767.940000 ;
+ RECT 692.320000 751.140000 693.420000 751.620000 ;
+ RECT 692.320000 756.580000 693.420000 757.060000 ;
+ RECT 692.320000 762.020000 693.420000 762.500000 ;
+ RECT 692.320000 767.460000 693.420000 767.940000 ;
+ RECT 647.320000 794.660000 648.420000 795.140000 ;
+ RECT 643.190000 794.660000 644.190000 795.140000 ;
+ RECT 647.320000 789.220000 648.420000 789.700000 ;
+ RECT 643.190000 789.220000 644.190000 789.700000 ;
+ RECT 647.320000 778.340000 648.420000 778.820000 ;
+ RECT 643.190000 778.340000 644.190000 778.820000 ;
+ RECT 647.320000 772.900000 648.420000 773.380000 ;
+ RECT 643.190000 772.900000 644.190000 773.380000 ;
+ RECT 647.320000 783.780000 648.420000 784.260000 ;
+ RECT 643.190000 783.780000 644.190000 784.260000 ;
+ RECT 647.320000 767.460000 648.420000 767.940000 ;
+ RECT 643.190000 767.460000 644.190000 767.940000 ;
+ RECT 647.320000 762.020000 648.420000 762.500000 ;
+ RECT 643.190000 762.020000 644.190000 762.500000 ;
+ RECT 647.320000 756.580000 648.420000 757.060000 ;
+ RECT 647.320000 751.140000 648.420000 751.620000 ;
+ RECT 643.190000 756.580000 644.190000 757.060000 ;
+ RECT 643.190000 751.140000 644.190000 751.620000 ;
+ RECT 640.360000 941.500000 840.460000 942.500000 ;
+ RECT 640.360000 749.130000 840.460000 750.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 746.280000 644.190000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 945.540000 644.190000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 746.280000 837.630000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 945.540000 837.630000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 749.130000 641.360000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 749.130000 840.460000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 941.500000 641.360000 942.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 941.500000 840.460000 942.500000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 548.870000 828.420000 742.240000 ;
+ RECT 782.320000 548.870000 783.420000 742.240000 ;
+ RECT 836.630000 546.020000 837.630000 746.280000 ;
+ RECT 737.320000 548.870000 738.420000 742.240000 ;
+ RECT 692.320000 548.870000 693.420000 742.240000 ;
+ RECT 647.320000 548.870000 648.420000 742.240000 ;
+ RECT 643.190000 546.020000 644.190000 746.280000 ;
+ LAYER met3 ;
+ RECT 827.320000 735.840000 828.420000 736.320000 ;
+ RECT 836.630000 735.840000 837.630000 736.320000 ;
+ RECT 836.630000 724.960000 837.630000 725.440000 ;
+ RECT 836.630000 730.400000 837.630000 730.880000 ;
+ RECT 827.320000 730.400000 828.420000 730.880000 ;
+ RECT 827.320000 724.960000 828.420000 725.440000 ;
+ RECT 827.320000 719.520000 828.420000 720.000000 ;
+ RECT 827.320000 714.080000 828.420000 714.560000 ;
+ RECT 836.630000 719.520000 837.630000 720.000000 ;
+ RECT 836.630000 714.080000 837.630000 714.560000 ;
+ RECT 827.320000 697.760000 828.420000 698.240000 ;
+ RECT 827.320000 703.200000 828.420000 703.680000 ;
+ RECT 836.630000 703.200000 837.630000 703.680000 ;
+ RECT 836.630000 697.760000 837.630000 698.240000 ;
+ RECT 827.320000 708.640000 828.420000 709.120000 ;
+ RECT 836.630000 708.640000 837.630000 709.120000 ;
+ RECT 782.320000 735.840000 783.420000 736.320000 ;
+ RECT 782.320000 730.400000 783.420000 730.880000 ;
+ RECT 782.320000 724.960000 783.420000 725.440000 ;
+ RECT 782.320000 719.520000 783.420000 720.000000 ;
+ RECT 782.320000 697.760000 783.420000 698.240000 ;
+ RECT 782.320000 703.200000 783.420000 703.680000 ;
+ RECT 782.320000 708.640000 783.420000 709.120000 ;
+ RECT 782.320000 714.080000 783.420000 714.560000 ;
+ RECT 836.630000 686.880000 837.630000 687.360000 ;
+ RECT 836.630000 692.320000 837.630000 692.800000 ;
+ RECT 827.320000 692.320000 828.420000 692.800000 ;
+ RECT 827.320000 686.880000 828.420000 687.360000 ;
+ RECT 827.320000 681.440000 828.420000 681.920000 ;
+ RECT 827.320000 676.000000 828.420000 676.480000 ;
+ RECT 836.630000 681.440000 837.630000 681.920000 ;
+ RECT 836.630000 676.000000 837.630000 676.480000 ;
+ RECT 836.630000 659.680000 837.630000 660.160000 ;
+ RECT 836.630000 665.120000 837.630000 665.600000 ;
+ RECT 836.630000 670.560000 837.630000 671.040000 ;
+ RECT 827.320000 665.120000 828.420000 665.600000 ;
+ RECT 827.320000 659.680000 828.420000 660.160000 ;
+ RECT 827.320000 670.560000 828.420000 671.040000 ;
+ RECT 827.320000 654.240000 828.420000 654.720000 ;
+ RECT 827.320000 648.800000 828.420000 649.280000 ;
+ RECT 836.630000 654.240000 837.630000 654.720000 ;
+ RECT 836.630000 648.800000 837.630000 649.280000 ;
+ RECT 782.320000 692.320000 783.420000 692.800000 ;
+ RECT 782.320000 686.880000 783.420000 687.360000 ;
+ RECT 782.320000 681.440000 783.420000 681.920000 ;
+ RECT 782.320000 676.000000 783.420000 676.480000 ;
+ RECT 782.320000 665.120000 783.420000 665.600000 ;
+ RECT 782.320000 659.680000 783.420000 660.160000 ;
+ RECT 782.320000 654.240000 783.420000 654.720000 ;
+ RECT 782.320000 648.800000 783.420000 649.280000 ;
+ RECT 782.320000 670.560000 783.420000 671.040000 ;
+ RECT 737.320000 735.840000 738.420000 736.320000 ;
+ RECT 737.320000 730.400000 738.420000 730.880000 ;
+ RECT 737.320000 724.960000 738.420000 725.440000 ;
+ RECT 692.320000 735.840000 693.420000 736.320000 ;
+ RECT 692.320000 730.400000 693.420000 730.880000 ;
+ RECT 692.320000 724.960000 693.420000 725.440000 ;
+ RECT 737.320000 708.640000 738.420000 709.120000 ;
+ RECT 737.320000 703.200000 738.420000 703.680000 ;
+ RECT 737.320000 697.760000 738.420000 698.240000 ;
+ RECT 737.320000 714.080000 738.420000 714.560000 ;
+ RECT 737.320000 719.520000 738.420000 720.000000 ;
+ RECT 692.320000 719.520000 693.420000 720.000000 ;
+ RECT 692.320000 708.640000 693.420000 709.120000 ;
+ RECT 692.320000 703.200000 693.420000 703.680000 ;
+ RECT 692.320000 697.760000 693.420000 698.240000 ;
+ RECT 692.320000 714.080000 693.420000 714.560000 ;
+ RECT 647.320000 735.840000 648.420000 736.320000 ;
+ RECT 643.190000 735.840000 644.190000 736.320000 ;
+ RECT 643.190000 730.400000 644.190000 730.880000 ;
+ RECT 647.320000 730.400000 648.420000 730.880000 ;
+ RECT 647.320000 724.960000 648.420000 725.440000 ;
+ RECT 643.190000 724.960000 644.190000 725.440000 ;
+ RECT 647.320000 719.520000 648.420000 720.000000 ;
+ RECT 643.190000 719.520000 644.190000 720.000000 ;
+ RECT 647.320000 714.080000 648.420000 714.560000 ;
+ RECT 643.190000 714.080000 644.190000 714.560000 ;
+ RECT 647.320000 703.200000 648.420000 703.680000 ;
+ RECT 643.190000 703.200000 644.190000 703.680000 ;
+ RECT 647.320000 697.760000 648.420000 698.240000 ;
+ RECT 643.190000 697.760000 644.190000 698.240000 ;
+ RECT 647.320000 708.640000 648.420000 709.120000 ;
+ RECT 643.190000 708.640000 644.190000 709.120000 ;
+ RECT 737.320000 692.320000 738.420000 692.800000 ;
+ RECT 737.320000 686.880000 738.420000 687.360000 ;
+ RECT 737.320000 681.440000 738.420000 681.920000 ;
+ RECT 737.320000 676.000000 738.420000 676.480000 ;
+ RECT 692.320000 692.320000 693.420000 692.800000 ;
+ RECT 692.320000 686.880000 693.420000 687.360000 ;
+ RECT 692.320000 681.440000 693.420000 681.920000 ;
+ RECT 692.320000 676.000000 693.420000 676.480000 ;
+ RECT 737.320000 665.120000 738.420000 665.600000 ;
+ RECT 737.320000 648.800000 738.420000 649.280000 ;
+ RECT 737.320000 654.240000 738.420000 654.720000 ;
+ RECT 737.320000 659.680000 738.420000 660.160000 ;
+ RECT 737.320000 670.560000 738.420000 671.040000 ;
+ RECT 692.320000 648.800000 693.420000 649.280000 ;
+ RECT 692.320000 654.240000 693.420000 654.720000 ;
+ RECT 692.320000 659.680000 693.420000 660.160000 ;
+ RECT 692.320000 665.120000 693.420000 665.600000 ;
+ RECT 692.320000 670.560000 693.420000 671.040000 ;
+ RECT 647.320000 692.320000 648.420000 692.800000 ;
+ RECT 643.190000 692.320000 644.190000 692.800000 ;
+ RECT 647.320000 686.880000 648.420000 687.360000 ;
+ RECT 643.190000 686.880000 644.190000 687.360000 ;
+ RECT 647.320000 681.440000 648.420000 681.920000 ;
+ RECT 643.190000 681.440000 644.190000 681.920000 ;
+ RECT 647.320000 676.000000 648.420000 676.480000 ;
+ RECT 643.190000 676.000000 644.190000 676.480000 ;
+ RECT 647.320000 670.560000 648.420000 671.040000 ;
+ RECT 647.320000 665.120000 648.420000 665.600000 ;
+ RECT 643.190000 670.560000 644.190000 671.040000 ;
+ RECT 643.190000 665.120000 644.190000 665.600000 ;
+ RECT 647.320000 659.680000 648.420000 660.160000 ;
+ RECT 643.190000 659.680000 644.190000 660.160000 ;
+ RECT 647.320000 654.240000 648.420000 654.720000 ;
+ RECT 643.190000 654.240000 644.190000 654.720000 ;
+ RECT 647.320000 648.800000 648.420000 649.280000 ;
+ RECT 643.190000 648.800000 644.190000 649.280000 ;
+ RECT 827.320000 643.360000 828.420000 643.840000 ;
+ RECT 827.320000 637.920000 828.420000 638.400000 ;
+ RECT 836.630000 643.360000 837.630000 643.840000 ;
+ RECT 836.630000 637.920000 837.630000 638.400000 ;
+ RECT 836.630000 621.600000 837.630000 622.080000 ;
+ RECT 836.630000 627.040000 837.630000 627.520000 ;
+ RECT 836.630000 632.480000 837.630000 632.960000 ;
+ RECT 827.320000 632.480000 828.420000 632.960000 ;
+ RECT 827.320000 627.040000 828.420000 627.520000 ;
+ RECT 827.320000 621.600000 828.420000 622.080000 ;
+ RECT 827.320000 610.720000 828.420000 611.200000 ;
+ RECT 827.320000 616.160000 828.420000 616.640000 ;
+ RECT 836.630000 616.160000 837.630000 616.640000 ;
+ RECT 836.630000 610.720000 837.630000 611.200000 ;
+ RECT 836.630000 599.840000 837.630000 600.320000 ;
+ RECT 836.630000 605.280000 837.630000 605.760000 ;
+ RECT 827.320000 599.840000 828.420000 600.320000 ;
+ RECT 827.320000 605.280000 828.420000 605.760000 ;
+ RECT 782.320000 643.360000 783.420000 643.840000 ;
+ RECT 782.320000 637.920000 783.420000 638.400000 ;
+ RECT 782.320000 632.480000 783.420000 632.960000 ;
+ RECT 782.320000 627.040000 783.420000 627.520000 ;
+ RECT 782.320000 621.600000 783.420000 622.080000 ;
+ RECT 782.320000 599.840000 783.420000 600.320000 ;
+ RECT 782.320000 605.280000 783.420000 605.760000 ;
+ RECT 782.320000 610.720000 783.420000 611.200000 ;
+ RECT 782.320000 616.160000 783.420000 616.640000 ;
+ RECT 827.320000 594.400000 828.420000 594.880000 ;
+ RECT 827.320000 588.960000 828.420000 589.440000 ;
+ RECT 836.630000 594.400000 837.630000 594.880000 ;
+ RECT 836.630000 588.960000 837.630000 589.440000 ;
+ RECT 827.320000 578.080000 828.420000 578.560000 ;
+ RECT 827.320000 572.640000 828.420000 573.120000 ;
+ RECT 836.630000 578.080000 837.630000 578.560000 ;
+ RECT 836.630000 572.640000 837.630000 573.120000 ;
+ RECT 827.320000 583.520000 828.420000 584.000000 ;
+ RECT 836.630000 583.520000 837.630000 584.000000 ;
+ RECT 836.630000 561.760000 837.630000 562.240000 ;
+ RECT 836.630000 567.200000 837.630000 567.680000 ;
+ RECT 827.320000 567.200000 828.420000 567.680000 ;
+ RECT 827.320000 561.760000 828.420000 562.240000 ;
+ RECT 827.320000 556.320000 828.420000 556.800000 ;
+ RECT 827.320000 550.880000 828.420000 551.360000 ;
+ RECT 836.630000 556.320000 837.630000 556.800000 ;
+ RECT 836.630000 550.880000 837.630000 551.360000 ;
+ RECT 782.320000 594.400000 783.420000 594.880000 ;
+ RECT 782.320000 588.960000 783.420000 589.440000 ;
+ RECT 782.320000 583.520000 783.420000 584.000000 ;
+ RECT 782.320000 578.080000 783.420000 578.560000 ;
+ RECT 782.320000 572.640000 783.420000 573.120000 ;
+ RECT 782.320000 567.200000 783.420000 567.680000 ;
+ RECT 782.320000 561.760000 783.420000 562.240000 ;
+ RECT 782.320000 556.320000 783.420000 556.800000 ;
+ RECT 782.320000 550.880000 783.420000 551.360000 ;
+ RECT 737.320000 643.360000 738.420000 643.840000 ;
+ RECT 737.320000 637.920000 738.420000 638.400000 ;
+ RECT 737.320000 632.480000 738.420000 632.960000 ;
+ RECT 737.320000 627.040000 738.420000 627.520000 ;
+ RECT 737.320000 621.600000 738.420000 622.080000 ;
+ RECT 692.320000 643.360000 693.420000 643.840000 ;
+ RECT 692.320000 637.920000 693.420000 638.400000 ;
+ RECT 692.320000 632.480000 693.420000 632.960000 ;
+ RECT 692.320000 627.040000 693.420000 627.520000 ;
+ RECT 692.320000 621.600000 693.420000 622.080000 ;
+ RECT 737.320000 616.160000 738.420000 616.640000 ;
+ RECT 737.320000 610.720000 738.420000 611.200000 ;
+ RECT 737.320000 605.280000 738.420000 605.760000 ;
+ RECT 737.320000 599.840000 738.420000 600.320000 ;
+ RECT 692.320000 610.720000 693.420000 611.200000 ;
+ RECT 692.320000 605.280000 693.420000 605.760000 ;
+ RECT 692.320000 599.840000 693.420000 600.320000 ;
+ RECT 692.320000 616.160000 693.420000 616.640000 ;
+ RECT 647.320000 643.360000 648.420000 643.840000 ;
+ RECT 643.190000 643.360000 644.190000 643.840000 ;
+ RECT 647.320000 637.920000 648.420000 638.400000 ;
+ RECT 643.190000 637.920000 644.190000 638.400000 ;
+ RECT 647.320000 632.480000 648.420000 632.960000 ;
+ RECT 643.190000 632.480000 644.190000 632.960000 ;
+ RECT 647.320000 621.600000 648.420000 622.080000 ;
+ RECT 643.190000 621.600000 644.190000 622.080000 ;
+ RECT 643.190000 627.040000 644.190000 627.520000 ;
+ RECT 647.320000 627.040000 648.420000 627.520000 ;
+ RECT 647.320000 616.160000 648.420000 616.640000 ;
+ RECT 643.190000 616.160000 644.190000 616.640000 ;
+ RECT 647.320000 610.720000 648.420000 611.200000 ;
+ RECT 643.190000 610.720000 644.190000 611.200000 ;
+ RECT 647.320000 605.280000 648.420000 605.760000 ;
+ RECT 643.190000 605.280000 644.190000 605.760000 ;
+ RECT 647.320000 599.840000 648.420000 600.320000 ;
+ RECT 643.190000 599.840000 644.190000 600.320000 ;
+ RECT 737.320000 594.400000 738.420000 594.880000 ;
+ RECT 737.320000 588.960000 738.420000 589.440000 ;
+ RECT 737.320000 583.520000 738.420000 584.000000 ;
+ RECT 737.320000 578.080000 738.420000 578.560000 ;
+ RECT 737.320000 572.640000 738.420000 573.120000 ;
+ RECT 692.320000 594.400000 693.420000 594.880000 ;
+ RECT 692.320000 588.960000 693.420000 589.440000 ;
+ RECT 692.320000 583.520000 693.420000 584.000000 ;
+ RECT 692.320000 578.080000 693.420000 578.560000 ;
+ RECT 692.320000 572.640000 693.420000 573.120000 ;
+ RECT 737.320000 550.880000 738.420000 551.360000 ;
+ RECT 737.320000 556.320000 738.420000 556.800000 ;
+ RECT 737.320000 561.760000 738.420000 562.240000 ;
+ RECT 737.320000 567.200000 738.420000 567.680000 ;
+ RECT 692.320000 550.880000 693.420000 551.360000 ;
+ RECT 692.320000 556.320000 693.420000 556.800000 ;
+ RECT 692.320000 561.760000 693.420000 562.240000 ;
+ RECT 692.320000 567.200000 693.420000 567.680000 ;
+ RECT 647.320000 594.400000 648.420000 594.880000 ;
+ RECT 643.190000 594.400000 644.190000 594.880000 ;
+ RECT 647.320000 588.960000 648.420000 589.440000 ;
+ RECT 643.190000 588.960000 644.190000 589.440000 ;
+ RECT 647.320000 578.080000 648.420000 578.560000 ;
+ RECT 643.190000 578.080000 644.190000 578.560000 ;
+ RECT 647.320000 572.640000 648.420000 573.120000 ;
+ RECT 643.190000 572.640000 644.190000 573.120000 ;
+ RECT 647.320000 583.520000 648.420000 584.000000 ;
+ RECT 643.190000 583.520000 644.190000 584.000000 ;
+ RECT 647.320000 567.200000 648.420000 567.680000 ;
+ RECT 643.190000 567.200000 644.190000 567.680000 ;
+ RECT 647.320000 561.760000 648.420000 562.240000 ;
+ RECT 643.190000 561.760000 644.190000 562.240000 ;
+ RECT 647.320000 556.320000 648.420000 556.800000 ;
+ RECT 647.320000 550.880000 648.420000 551.360000 ;
+ RECT 643.190000 556.320000 644.190000 556.800000 ;
+ RECT 643.190000 550.880000 644.190000 551.360000 ;
+ RECT 640.360000 741.240000 840.460000 742.240000 ;
+ RECT 640.360000 548.870000 840.460000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 546.020000 644.190000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 745.280000 644.190000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 546.020000 837.630000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 745.280000 837.630000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 548.870000 641.360000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 548.870000 840.460000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 741.240000 641.360000 742.240000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 741.240000 840.460000 742.240000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 348.610000 828.420000 541.980000 ;
+ RECT 782.320000 348.610000 783.420000 541.980000 ;
+ RECT 836.630000 345.760000 837.630000 546.020000 ;
+ RECT 737.320000 348.610000 738.420000 541.980000 ;
+ RECT 692.320000 348.610000 693.420000 541.980000 ;
+ RECT 647.320000 348.610000 648.420000 541.980000 ;
+ RECT 643.190000 345.760000 644.190000 546.020000 ;
+ LAYER met3 ;
+ RECT 827.320000 535.580000 828.420000 536.060000 ;
+ RECT 836.630000 535.580000 837.630000 536.060000 ;
+ RECT 836.630000 524.700000 837.630000 525.180000 ;
+ RECT 836.630000 530.140000 837.630000 530.620000 ;
+ RECT 827.320000 530.140000 828.420000 530.620000 ;
+ RECT 827.320000 524.700000 828.420000 525.180000 ;
+ RECT 827.320000 519.260000 828.420000 519.740000 ;
+ RECT 827.320000 513.820000 828.420000 514.300000 ;
+ RECT 836.630000 519.260000 837.630000 519.740000 ;
+ RECT 836.630000 513.820000 837.630000 514.300000 ;
+ RECT 827.320000 497.500000 828.420000 497.980000 ;
+ RECT 827.320000 502.940000 828.420000 503.420000 ;
+ RECT 836.630000 502.940000 837.630000 503.420000 ;
+ RECT 836.630000 497.500000 837.630000 497.980000 ;
+ RECT 827.320000 508.380000 828.420000 508.860000 ;
+ RECT 836.630000 508.380000 837.630000 508.860000 ;
+ RECT 782.320000 535.580000 783.420000 536.060000 ;
+ RECT 782.320000 530.140000 783.420000 530.620000 ;
+ RECT 782.320000 524.700000 783.420000 525.180000 ;
+ RECT 782.320000 519.260000 783.420000 519.740000 ;
+ RECT 782.320000 497.500000 783.420000 497.980000 ;
+ RECT 782.320000 502.940000 783.420000 503.420000 ;
+ RECT 782.320000 508.380000 783.420000 508.860000 ;
+ RECT 782.320000 513.820000 783.420000 514.300000 ;
+ RECT 836.630000 486.620000 837.630000 487.100000 ;
+ RECT 836.630000 492.060000 837.630000 492.540000 ;
+ RECT 827.320000 492.060000 828.420000 492.540000 ;
+ RECT 827.320000 486.620000 828.420000 487.100000 ;
+ RECT 827.320000 481.180000 828.420000 481.660000 ;
+ RECT 827.320000 475.740000 828.420000 476.220000 ;
+ RECT 836.630000 481.180000 837.630000 481.660000 ;
+ RECT 836.630000 475.740000 837.630000 476.220000 ;
+ RECT 836.630000 459.420000 837.630000 459.900000 ;
+ RECT 836.630000 464.860000 837.630000 465.340000 ;
+ RECT 836.630000 470.300000 837.630000 470.780000 ;
+ RECT 827.320000 464.860000 828.420000 465.340000 ;
+ RECT 827.320000 459.420000 828.420000 459.900000 ;
+ RECT 827.320000 470.300000 828.420000 470.780000 ;
+ RECT 827.320000 453.980000 828.420000 454.460000 ;
+ RECT 827.320000 448.540000 828.420000 449.020000 ;
+ RECT 836.630000 453.980000 837.630000 454.460000 ;
+ RECT 836.630000 448.540000 837.630000 449.020000 ;
+ RECT 782.320000 492.060000 783.420000 492.540000 ;
+ RECT 782.320000 486.620000 783.420000 487.100000 ;
+ RECT 782.320000 481.180000 783.420000 481.660000 ;
+ RECT 782.320000 475.740000 783.420000 476.220000 ;
+ RECT 782.320000 464.860000 783.420000 465.340000 ;
+ RECT 782.320000 459.420000 783.420000 459.900000 ;
+ RECT 782.320000 453.980000 783.420000 454.460000 ;
+ RECT 782.320000 448.540000 783.420000 449.020000 ;
+ RECT 782.320000 470.300000 783.420000 470.780000 ;
+ RECT 737.320000 535.580000 738.420000 536.060000 ;
+ RECT 737.320000 530.140000 738.420000 530.620000 ;
+ RECT 737.320000 524.700000 738.420000 525.180000 ;
+ RECT 692.320000 535.580000 693.420000 536.060000 ;
+ RECT 692.320000 530.140000 693.420000 530.620000 ;
+ RECT 692.320000 524.700000 693.420000 525.180000 ;
+ RECT 737.320000 508.380000 738.420000 508.860000 ;
+ RECT 737.320000 502.940000 738.420000 503.420000 ;
+ RECT 737.320000 497.500000 738.420000 497.980000 ;
+ RECT 737.320000 513.820000 738.420000 514.300000 ;
+ RECT 737.320000 519.260000 738.420000 519.740000 ;
+ RECT 692.320000 519.260000 693.420000 519.740000 ;
+ RECT 692.320000 508.380000 693.420000 508.860000 ;
+ RECT 692.320000 502.940000 693.420000 503.420000 ;
+ RECT 692.320000 497.500000 693.420000 497.980000 ;
+ RECT 692.320000 513.820000 693.420000 514.300000 ;
+ RECT 647.320000 535.580000 648.420000 536.060000 ;
+ RECT 643.190000 535.580000 644.190000 536.060000 ;
+ RECT 643.190000 530.140000 644.190000 530.620000 ;
+ RECT 647.320000 530.140000 648.420000 530.620000 ;
+ RECT 647.320000 524.700000 648.420000 525.180000 ;
+ RECT 643.190000 524.700000 644.190000 525.180000 ;
+ RECT 647.320000 519.260000 648.420000 519.740000 ;
+ RECT 643.190000 519.260000 644.190000 519.740000 ;
+ RECT 647.320000 513.820000 648.420000 514.300000 ;
+ RECT 643.190000 513.820000 644.190000 514.300000 ;
+ RECT 647.320000 502.940000 648.420000 503.420000 ;
+ RECT 643.190000 502.940000 644.190000 503.420000 ;
+ RECT 647.320000 497.500000 648.420000 497.980000 ;
+ RECT 643.190000 497.500000 644.190000 497.980000 ;
+ RECT 647.320000 508.380000 648.420000 508.860000 ;
+ RECT 643.190000 508.380000 644.190000 508.860000 ;
+ RECT 737.320000 492.060000 738.420000 492.540000 ;
+ RECT 737.320000 486.620000 738.420000 487.100000 ;
+ RECT 737.320000 481.180000 738.420000 481.660000 ;
+ RECT 737.320000 475.740000 738.420000 476.220000 ;
+ RECT 692.320000 492.060000 693.420000 492.540000 ;
+ RECT 692.320000 486.620000 693.420000 487.100000 ;
+ RECT 692.320000 481.180000 693.420000 481.660000 ;
+ RECT 692.320000 475.740000 693.420000 476.220000 ;
+ RECT 737.320000 464.860000 738.420000 465.340000 ;
+ RECT 737.320000 448.540000 738.420000 449.020000 ;
+ RECT 737.320000 453.980000 738.420000 454.460000 ;
+ RECT 737.320000 459.420000 738.420000 459.900000 ;
+ RECT 737.320000 470.300000 738.420000 470.780000 ;
+ RECT 692.320000 448.540000 693.420000 449.020000 ;
+ RECT 692.320000 453.980000 693.420000 454.460000 ;
+ RECT 692.320000 459.420000 693.420000 459.900000 ;
+ RECT 692.320000 464.860000 693.420000 465.340000 ;
+ RECT 692.320000 470.300000 693.420000 470.780000 ;
+ RECT 647.320000 492.060000 648.420000 492.540000 ;
+ RECT 643.190000 492.060000 644.190000 492.540000 ;
+ RECT 647.320000 486.620000 648.420000 487.100000 ;
+ RECT 643.190000 486.620000 644.190000 487.100000 ;
+ RECT 647.320000 481.180000 648.420000 481.660000 ;
+ RECT 643.190000 481.180000 644.190000 481.660000 ;
+ RECT 647.320000 475.740000 648.420000 476.220000 ;
+ RECT 643.190000 475.740000 644.190000 476.220000 ;
+ RECT 647.320000 470.300000 648.420000 470.780000 ;
+ RECT 647.320000 464.860000 648.420000 465.340000 ;
+ RECT 643.190000 470.300000 644.190000 470.780000 ;
+ RECT 643.190000 464.860000 644.190000 465.340000 ;
+ RECT 647.320000 459.420000 648.420000 459.900000 ;
+ RECT 643.190000 459.420000 644.190000 459.900000 ;
+ RECT 647.320000 453.980000 648.420000 454.460000 ;
+ RECT 643.190000 453.980000 644.190000 454.460000 ;
+ RECT 647.320000 448.540000 648.420000 449.020000 ;
+ RECT 643.190000 448.540000 644.190000 449.020000 ;
+ RECT 827.320000 443.100000 828.420000 443.580000 ;
+ RECT 827.320000 437.660000 828.420000 438.140000 ;
+ RECT 836.630000 443.100000 837.630000 443.580000 ;
+ RECT 836.630000 437.660000 837.630000 438.140000 ;
+ RECT 836.630000 421.340000 837.630000 421.820000 ;
+ RECT 836.630000 426.780000 837.630000 427.260000 ;
+ RECT 836.630000 432.220000 837.630000 432.700000 ;
+ RECT 827.320000 432.220000 828.420000 432.700000 ;
+ RECT 827.320000 426.780000 828.420000 427.260000 ;
+ RECT 827.320000 421.340000 828.420000 421.820000 ;
+ RECT 827.320000 410.460000 828.420000 410.940000 ;
+ RECT 827.320000 415.900000 828.420000 416.380000 ;
+ RECT 836.630000 415.900000 837.630000 416.380000 ;
+ RECT 836.630000 410.460000 837.630000 410.940000 ;
+ RECT 836.630000 399.580000 837.630000 400.060000 ;
+ RECT 836.630000 405.020000 837.630000 405.500000 ;
+ RECT 827.320000 399.580000 828.420000 400.060000 ;
+ RECT 827.320000 405.020000 828.420000 405.500000 ;
+ RECT 782.320000 443.100000 783.420000 443.580000 ;
+ RECT 782.320000 437.660000 783.420000 438.140000 ;
+ RECT 782.320000 432.220000 783.420000 432.700000 ;
+ RECT 782.320000 426.780000 783.420000 427.260000 ;
+ RECT 782.320000 421.340000 783.420000 421.820000 ;
+ RECT 782.320000 399.580000 783.420000 400.060000 ;
+ RECT 782.320000 405.020000 783.420000 405.500000 ;
+ RECT 782.320000 410.460000 783.420000 410.940000 ;
+ RECT 782.320000 415.900000 783.420000 416.380000 ;
+ RECT 827.320000 394.140000 828.420000 394.620000 ;
+ RECT 827.320000 388.700000 828.420000 389.180000 ;
+ RECT 836.630000 394.140000 837.630000 394.620000 ;
+ RECT 836.630000 388.700000 837.630000 389.180000 ;
+ RECT 827.320000 377.820000 828.420000 378.300000 ;
+ RECT 827.320000 372.380000 828.420000 372.860000 ;
+ RECT 836.630000 377.820000 837.630000 378.300000 ;
+ RECT 836.630000 372.380000 837.630000 372.860000 ;
+ RECT 827.320000 383.260000 828.420000 383.740000 ;
+ RECT 836.630000 383.260000 837.630000 383.740000 ;
+ RECT 836.630000 361.500000 837.630000 361.980000 ;
+ RECT 836.630000 366.940000 837.630000 367.420000 ;
+ RECT 827.320000 366.940000 828.420000 367.420000 ;
+ RECT 827.320000 361.500000 828.420000 361.980000 ;
+ RECT 827.320000 356.060000 828.420000 356.540000 ;
+ RECT 827.320000 350.620000 828.420000 351.100000 ;
+ RECT 836.630000 356.060000 837.630000 356.540000 ;
+ RECT 836.630000 350.620000 837.630000 351.100000 ;
+ RECT 782.320000 394.140000 783.420000 394.620000 ;
+ RECT 782.320000 388.700000 783.420000 389.180000 ;
+ RECT 782.320000 383.260000 783.420000 383.740000 ;
+ RECT 782.320000 377.820000 783.420000 378.300000 ;
+ RECT 782.320000 372.380000 783.420000 372.860000 ;
+ RECT 782.320000 366.940000 783.420000 367.420000 ;
+ RECT 782.320000 361.500000 783.420000 361.980000 ;
+ RECT 782.320000 356.060000 783.420000 356.540000 ;
+ RECT 782.320000 350.620000 783.420000 351.100000 ;
+ RECT 737.320000 443.100000 738.420000 443.580000 ;
+ RECT 737.320000 437.660000 738.420000 438.140000 ;
+ RECT 737.320000 432.220000 738.420000 432.700000 ;
+ RECT 737.320000 426.780000 738.420000 427.260000 ;
+ RECT 737.320000 421.340000 738.420000 421.820000 ;
+ RECT 692.320000 443.100000 693.420000 443.580000 ;
+ RECT 692.320000 437.660000 693.420000 438.140000 ;
+ RECT 692.320000 432.220000 693.420000 432.700000 ;
+ RECT 692.320000 426.780000 693.420000 427.260000 ;
+ RECT 692.320000 421.340000 693.420000 421.820000 ;
+ RECT 737.320000 415.900000 738.420000 416.380000 ;
+ RECT 737.320000 410.460000 738.420000 410.940000 ;
+ RECT 737.320000 405.020000 738.420000 405.500000 ;
+ RECT 737.320000 399.580000 738.420000 400.060000 ;
+ RECT 692.320000 410.460000 693.420000 410.940000 ;
+ RECT 692.320000 405.020000 693.420000 405.500000 ;
+ RECT 692.320000 399.580000 693.420000 400.060000 ;
+ RECT 692.320000 415.900000 693.420000 416.380000 ;
+ RECT 647.320000 443.100000 648.420000 443.580000 ;
+ RECT 643.190000 443.100000 644.190000 443.580000 ;
+ RECT 647.320000 437.660000 648.420000 438.140000 ;
+ RECT 643.190000 437.660000 644.190000 438.140000 ;
+ RECT 647.320000 432.220000 648.420000 432.700000 ;
+ RECT 643.190000 432.220000 644.190000 432.700000 ;
+ RECT 647.320000 421.340000 648.420000 421.820000 ;
+ RECT 643.190000 421.340000 644.190000 421.820000 ;
+ RECT 643.190000 426.780000 644.190000 427.260000 ;
+ RECT 647.320000 426.780000 648.420000 427.260000 ;
+ RECT 647.320000 415.900000 648.420000 416.380000 ;
+ RECT 643.190000 415.900000 644.190000 416.380000 ;
+ RECT 647.320000 410.460000 648.420000 410.940000 ;
+ RECT 643.190000 410.460000 644.190000 410.940000 ;
+ RECT 647.320000 405.020000 648.420000 405.500000 ;
+ RECT 643.190000 405.020000 644.190000 405.500000 ;
+ RECT 647.320000 399.580000 648.420000 400.060000 ;
+ RECT 643.190000 399.580000 644.190000 400.060000 ;
+ RECT 737.320000 394.140000 738.420000 394.620000 ;
+ RECT 737.320000 388.700000 738.420000 389.180000 ;
+ RECT 737.320000 383.260000 738.420000 383.740000 ;
+ RECT 737.320000 377.820000 738.420000 378.300000 ;
+ RECT 737.320000 372.380000 738.420000 372.860000 ;
+ RECT 692.320000 394.140000 693.420000 394.620000 ;
+ RECT 692.320000 388.700000 693.420000 389.180000 ;
+ RECT 692.320000 383.260000 693.420000 383.740000 ;
+ RECT 692.320000 377.820000 693.420000 378.300000 ;
+ RECT 692.320000 372.380000 693.420000 372.860000 ;
+ RECT 737.320000 350.620000 738.420000 351.100000 ;
+ RECT 737.320000 356.060000 738.420000 356.540000 ;
+ RECT 737.320000 361.500000 738.420000 361.980000 ;
+ RECT 737.320000 366.940000 738.420000 367.420000 ;
+ RECT 692.320000 350.620000 693.420000 351.100000 ;
+ RECT 692.320000 356.060000 693.420000 356.540000 ;
+ RECT 692.320000 361.500000 693.420000 361.980000 ;
+ RECT 692.320000 366.940000 693.420000 367.420000 ;
+ RECT 647.320000 394.140000 648.420000 394.620000 ;
+ RECT 643.190000 394.140000 644.190000 394.620000 ;
+ RECT 647.320000 388.700000 648.420000 389.180000 ;
+ RECT 643.190000 388.700000 644.190000 389.180000 ;
+ RECT 647.320000 377.820000 648.420000 378.300000 ;
+ RECT 643.190000 377.820000 644.190000 378.300000 ;
+ RECT 647.320000 372.380000 648.420000 372.860000 ;
+ RECT 643.190000 372.380000 644.190000 372.860000 ;
+ RECT 647.320000 383.260000 648.420000 383.740000 ;
+ RECT 643.190000 383.260000 644.190000 383.740000 ;
+ RECT 647.320000 366.940000 648.420000 367.420000 ;
+ RECT 643.190000 366.940000 644.190000 367.420000 ;
+ RECT 647.320000 361.500000 648.420000 361.980000 ;
+ RECT 643.190000 361.500000 644.190000 361.980000 ;
+ RECT 647.320000 356.060000 648.420000 356.540000 ;
+ RECT 647.320000 350.620000 648.420000 351.100000 ;
+ RECT 643.190000 356.060000 644.190000 356.540000 ;
+ RECT 643.190000 350.620000 644.190000 351.100000 ;
+ RECT 640.360000 540.980000 840.460000 541.980000 ;
+ RECT 640.360000 348.610000 840.460000 349.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 345.760000 644.190000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 545.020000 644.190000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 345.760000 837.630000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 545.020000 837.630000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 348.610000 641.360000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 348.610000 840.460000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 540.980000 641.360000 541.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 540.980000 840.460000 541.980000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 148.350000 828.420000 341.720000 ;
+ RECT 782.320000 148.350000 783.420000 341.720000 ;
+ RECT 836.630000 145.500000 837.630000 345.760000 ;
+ RECT 737.320000 148.350000 738.420000 341.720000 ;
+ RECT 692.320000 148.350000 693.420000 341.720000 ;
+ RECT 647.320000 148.350000 648.420000 341.720000 ;
+ RECT 643.190000 145.500000 644.190000 345.760000 ;
+ LAYER met3 ;
+ RECT 827.320000 335.320000 828.420000 335.800000 ;
+ RECT 836.630000 335.320000 837.630000 335.800000 ;
+ RECT 836.630000 324.440000 837.630000 324.920000 ;
+ RECT 836.630000 329.880000 837.630000 330.360000 ;
+ RECT 827.320000 329.880000 828.420000 330.360000 ;
+ RECT 827.320000 324.440000 828.420000 324.920000 ;
+ RECT 827.320000 319.000000 828.420000 319.480000 ;
+ RECT 827.320000 313.560000 828.420000 314.040000 ;
+ RECT 836.630000 319.000000 837.630000 319.480000 ;
+ RECT 836.630000 313.560000 837.630000 314.040000 ;
+ RECT 827.320000 297.240000 828.420000 297.720000 ;
+ RECT 827.320000 302.680000 828.420000 303.160000 ;
+ RECT 836.630000 302.680000 837.630000 303.160000 ;
+ RECT 836.630000 297.240000 837.630000 297.720000 ;
+ RECT 827.320000 308.120000 828.420000 308.600000 ;
+ RECT 836.630000 308.120000 837.630000 308.600000 ;
+ RECT 782.320000 335.320000 783.420000 335.800000 ;
+ RECT 782.320000 329.880000 783.420000 330.360000 ;
+ RECT 782.320000 324.440000 783.420000 324.920000 ;
+ RECT 782.320000 319.000000 783.420000 319.480000 ;
+ RECT 782.320000 297.240000 783.420000 297.720000 ;
+ RECT 782.320000 302.680000 783.420000 303.160000 ;
+ RECT 782.320000 308.120000 783.420000 308.600000 ;
+ RECT 782.320000 313.560000 783.420000 314.040000 ;
+ RECT 836.630000 286.360000 837.630000 286.840000 ;
+ RECT 836.630000 291.800000 837.630000 292.280000 ;
+ RECT 827.320000 291.800000 828.420000 292.280000 ;
+ RECT 827.320000 286.360000 828.420000 286.840000 ;
+ RECT 827.320000 280.920000 828.420000 281.400000 ;
+ RECT 827.320000 275.480000 828.420000 275.960000 ;
+ RECT 836.630000 280.920000 837.630000 281.400000 ;
+ RECT 836.630000 275.480000 837.630000 275.960000 ;
+ RECT 836.630000 259.160000 837.630000 259.640000 ;
+ RECT 836.630000 264.600000 837.630000 265.080000 ;
+ RECT 836.630000 270.040000 837.630000 270.520000 ;
+ RECT 827.320000 264.600000 828.420000 265.080000 ;
+ RECT 827.320000 259.160000 828.420000 259.640000 ;
+ RECT 827.320000 270.040000 828.420000 270.520000 ;
+ RECT 827.320000 253.720000 828.420000 254.200000 ;
+ RECT 827.320000 248.280000 828.420000 248.760000 ;
+ RECT 836.630000 253.720000 837.630000 254.200000 ;
+ RECT 836.630000 248.280000 837.630000 248.760000 ;
+ RECT 782.320000 291.800000 783.420000 292.280000 ;
+ RECT 782.320000 286.360000 783.420000 286.840000 ;
+ RECT 782.320000 280.920000 783.420000 281.400000 ;
+ RECT 782.320000 275.480000 783.420000 275.960000 ;
+ RECT 782.320000 264.600000 783.420000 265.080000 ;
+ RECT 782.320000 259.160000 783.420000 259.640000 ;
+ RECT 782.320000 253.720000 783.420000 254.200000 ;
+ RECT 782.320000 248.280000 783.420000 248.760000 ;
+ RECT 782.320000 270.040000 783.420000 270.520000 ;
+ RECT 737.320000 335.320000 738.420000 335.800000 ;
+ RECT 737.320000 329.880000 738.420000 330.360000 ;
+ RECT 737.320000 324.440000 738.420000 324.920000 ;
+ RECT 692.320000 335.320000 693.420000 335.800000 ;
+ RECT 692.320000 329.880000 693.420000 330.360000 ;
+ RECT 692.320000 324.440000 693.420000 324.920000 ;
+ RECT 737.320000 308.120000 738.420000 308.600000 ;
+ RECT 737.320000 302.680000 738.420000 303.160000 ;
+ RECT 737.320000 297.240000 738.420000 297.720000 ;
+ RECT 737.320000 313.560000 738.420000 314.040000 ;
+ RECT 737.320000 319.000000 738.420000 319.480000 ;
+ RECT 692.320000 319.000000 693.420000 319.480000 ;
+ RECT 692.320000 308.120000 693.420000 308.600000 ;
+ RECT 692.320000 302.680000 693.420000 303.160000 ;
+ RECT 692.320000 297.240000 693.420000 297.720000 ;
+ RECT 692.320000 313.560000 693.420000 314.040000 ;
+ RECT 647.320000 335.320000 648.420000 335.800000 ;
+ RECT 643.190000 335.320000 644.190000 335.800000 ;
+ RECT 643.190000 329.880000 644.190000 330.360000 ;
+ RECT 647.320000 329.880000 648.420000 330.360000 ;
+ RECT 647.320000 324.440000 648.420000 324.920000 ;
+ RECT 643.190000 324.440000 644.190000 324.920000 ;
+ RECT 647.320000 319.000000 648.420000 319.480000 ;
+ RECT 643.190000 319.000000 644.190000 319.480000 ;
+ RECT 647.320000 313.560000 648.420000 314.040000 ;
+ RECT 643.190000 313.560000 644.190000 314.040000 ;
+ RECT 647.320000 302.680000 648.420000 303.160000 ;
+ RECT 643.190000 302.680000 644.190000 303.160000 ;
+ RECT 647.320000 297.240000 648.420000 297.720000 ;
+ RECT 643.190000 297.240000 644.190000 297.720000 ;
+ RECT 647.320000 308.120000 648.420000 308.600000 ;
+ RECT 643.190000 308.120000 644.190000 308.600000 ;
+ RECT 737.320000 291.800000 738.420000 292.280000 ;
+ RECT 737.320000 286.360000 738.420000 286.840000 ;
+ RECT 737.320000 280.920000 738.420000 281.400000 ;
+ RECT 737.320000 275.480000 738.420000 275.960000 ;
+ RECT 692.320000 291.800000 693.420000 292.280000 ;
+ RECT 692.320000 286.360000 693.420000 286.840000 ;
+ RECT 692.320000 280.920000 693.420000 281.400000 ;
+ RECT 692.320000 275.480000 693.420000 275.960000 ;
+ RECT 737.320000 264.600000 738.420000 265.080000 ;
+ RECT 737.320000 248.280000 738.420000 248.760000 ;
+ RECT 737.320000 253.720000 738.420000 254.200000 ;
+ RECT 737.320000 259.160000 738.420000 259.640000 ;
+ RECT 737.320000 270.040000 738.420000 270.520000 ;
+ RECT 692.320000 248.280000 693.420000 248.760000 ;
+ RECT 692.320000 253.720000 693.420000 254.200000 ;
+ RECT 692.320000 259.160000 693.420000 259.640000 ;
+ RECT 692.320000 264.600000 693.420000 265.080000 ;
+ RECT 692.320000 270.040000 693.420000 270.520000 ;
+ RECT 647.320000 291.800000 648.420000 292.280000 ;
+ RECT 643.190000 291.800000 644.190000 292.280000 ;
+ RECT 647.320000 286.360000 648.420000 286.840000 ;
+ RECT 643.190000 286.360000 644.190000 286.840000 ;
+ RECT 647.320000 280.920000 648.420000 281.400000 ;
+ RECT 643.190000 280.920000 644.190000 281.400000 ;
+ RECT 647.320000 275.480000 648.420000 275.960000 ;
+ RECT 643.190000 275.480000 644.190000 275.960000 ;
+ RECT 647.320000 270.040000 648.420000 270.520000 ;
+ RECT 647.320000 264.600000 648.420000 265.080000 ;
+ RECT 643.190000 270.040000 644.190000 270.520000 ;
+ RECT 643.190000 264.600000 644.190000 265.080000 ;
+ RECT 647.320000 259.160000 648.420000 259.640000 ;
+ RECT 643.190000 259.160000 644.190000 259.640000 ;
+ RECT 647.320000 253.720000 648.420000 254.200000 ;
+ RECT 643.190000 253.720000 644.190000 254.200000 ;
+ RECT 647.320000 248.280000 648.420000 248.760000 ;
+ RECT 643.190000 248.280000 644.190000 248.760000 ;
+ RECT 827.320000 242.840000 828.420000 243.320000 ;
+ RECT 827.320000 237.400000 828.420000 237.880000 ;
+ RECT 836.630000 242.840000 837.630000 243.320000 ;
+ RECT 836.630000 237.400000 837.630000 237.880000 ;
+ RECT 836.630000 221.080000 837.630000 221.560000 ;
+ RECT 836.630000 226.520000 837.630000 227.000000 ;
+ RECT 836.630000 231.960000 837.630000 232.440000 ;
+ RECT 827.320000 231.960000 828.420000 232.440000 ;
+ RECT 827.320000 226.520000 828.420000 227.000000 ;
+ RECT 827.320000 221.080000 828.420000 221.560000 ;
+ RECT 827.320000 210.200000 828.420000 210.680000 ;
+ RECT 827.320000 215.640000 828.420000 216.120000 ;
+ RECT 836.630000 215.640000 837.630000 216.120000 ;
+ RECT 836.630000 210.200000 837.630000 210.680000 ;
+ RECT 836.630000 199.320000 837.630000 199.800000 ;
+ RECT 836.630000 204.760000 837.630000 205.240000 ;
+ RECT 827.320000 199.320000 828.420000 199.800000 ;
+ RECT 827.320000 204.760000 828.420000 205.240000 ;
+ RECT 782.320000 242.840000 783.420000 243.320000 ;
+ RECT 782.320000 237.400000 783.420000 237.880000 ;
+ RECT 782.320000 231.960000 783.420000 232.440000 ;
+ RECT 782.320000 226.520000 783.420000 227.000000 ;
+ RECT 782.320000 221.080000 783.420000 221.560000 ;
+ RECT 782.320000 199.320000 783.420000 199.800000 ;
+ RECT 782.320000 204.760000 783.420000 205.240000 ;
+ RECT 782.320000 210.200000 783.420000 210.680000 ;
+ RECT 782.320000 215.640000 783.420000 216.120000 ;
+ RECT 827.320000 193.880000 828.420000 194.360000 ;
+ RECT 827.320000 188.440000 828.420000 188.920000 ;
+ RECT 836.630000 193.880000 837.630000 194.360000 ;
+ RECT 836.630000 188.440000 837.630000 188.920000 ;
+ RECT 827.320000 177.560000 828.420000 178.040000 ;
+ RECT 827.320000 172.120000 828.420000 172.600000 ;
+ RECT 836.630000 177.560000 837.630000 178.040000 ;
+ RECT 836.630000 172.120000 837.630000 172.600000 ;
+ RECT 827.320000 183.000000 828.420000 183.480000 ;
+ RECT 836.630000 183.000000 837.630000 183.480000 ;
+ RECT 836.630000 161.240000 837.630000 161.720000 ;
+ RECT 836.630000 166.680000 837.630000 167.160000 ;
+ RECT 827.320000 166.680000 828.420000 167.160000 ;
+ RECT 827.320000 161.240000 828.420000 161.720000 ;
+ RECT 827.320000 155.800000 828.420000 156.280000 ;
+ RECT 827.320000 150.360000 828.420000 150.840000 ;
+ RECT 836.630000 155.800000 837.630000 156.280000 ;
+ RECT 836.630000 150.360000 837.630000 150.840000 ;
+ RECT 782.320000 193.880000 783.420000 194.360000 ;
+ RECT 782.320000 188.440000 783.420000 188.920000 ;
+ RECT 782.320000 183.000000 783.420000 183.480000 ;
+ RECT 782.320000 177.560000 783.420000 178.040000 ;
+ RECT 782.320000 172.120000 783.420000 172.600000 ;
+ RECT 782.320000 166.680000 783.420000 167.160000 ;
+ RECT 782.320000 161.240000 783.420000 161.720000 ;
+ RECT 782.320000 155.800000 783.420000 156.280000 ;
+ RECT 782.320000 150.360000 783.420000 150.840000 ;
+ RECT 737.320000 242.840000 738.420000 243.320000 ;
+ RECT 737.320000 237.400000 738.420000 237.880000 ;
+ RECT 737.320000 231.960000 738.420000 232.440000 ;
+ RECT 737.320000 226.520000 738.420000 227.000000 ;
+ RECT 737.320000 221.080000 738.420000 221.560000 ;
+ RECT 692.320000 242.840000 693.420000 243.320000 ;
+ RECT 692.320000 237.400000 693.420000 237.880000 ;
+ RECT 692.320000 231.960000 693.420000 232.440000 ;
+ RECT 692.320000 226.520000 693.420000 227.000000 ;
+ RECT 692.320000 221.080000 693.420000 221.560000 ;
+ RECT 737.320000 215.640000 738.420000 216.120000 ;
+ RECT 737.320000 210.200000 738.420000 210.680000 ;
+ RECT 737.320000 204.760000 738.420000 205.240000 ;
+ RECT 737.320000 199.320000 738.420000 199.800000 ;
+ RECT 692.320000 210.200000 693.420000 210.680000 ;
+ RECT 692.320000 204.760000 693.420000 205.240000 ;
+ RECT 692.320000 199.320000 693.420000 199.800000 ;
+ RECT 692.320000 215.640000 693.420000 216.120000 ;
+ RECT 647.320000 242.840000 648.420000 243.320000 ;
+ RECT 643.190000 242.840000 644.190000 243.320000 ;
+ RECT 647.320000 237.400000 648.420000 237.880000 ;
+ RECT 643.190000 237.400000 644.190000 237.880000 ;
+ RECT 647.320000 231.960000 648.420000 232.440000 ;
+ RECT 643.190000 231.960000 644.190000 232.440000 ;
+ RECT 647.320000 221.080000 648.420000 221.560000 ;
+ RECT 643.190000 221.080000 644.190000 221.560000 ;
+ RECT 643.190000 226.520000 644.190000 227.000000 ;
+ RECT 647.320000 226.520000 648.420000 227.000000 ;
+ RECT 647.320000 215.640000 648.420000 216.120000 ;
+ RECT 643.190000 215.640000 644.190000 216.120000 ;
+ RECT 647.320000 210.200000 648.420000 210.680000 ;
+ RECT 643.190000 210.200000 644.190000 210.680000 ;
+ RECT 647.320000 204.760000 648.420000 205.240000 ;
+ RECT 643.190000 204.760000 644.190000 205.240000 ;
+ RECT 647.320000 199.320000 648.420000 199.800000 ;
+ RECT 643.190000 199.320000 644.190000 199.800000 ;
+ RECT 737.320000 193.880000 738.420000 194.360000 ;
+ RECT 737.320000 188.440000 738.420000 188.920000 ;
+ RECT 737.320000 183.000000 738.420000 183.480000 ;
+ RECT 737.320000 177.560000 738.420000 178.040000 ;
+ RECT 737.320000 172.120000 738.420000 172.600000 ;
+ RECT 692.320000 193.880000 693.420000 194.360000 ;
+ RECT 692.320000 188.440000 693.420000 188.920000 ;
+ RECT 692.320000 183.000000 693.420000 183.480000 ;
+ RECT 692.320000 177.560000 693.420000 178.040000 ;
+ RECT 692.320000 172.120000 693.420000 172.600000 ;
+ RECT 737.320000 150.360000 738.420000 150.840000 ;
+ RECT 737.320000 155.800000 738.420000 156.280000 ;
+ RECT 737.320000 161.240000 738.420000 161.720000 ;
+ RECT 737.320000 166.680000 738.420000 167.160000 ;
+ RECT 692.320000 150.360000 693.420000 150.840000 ;
+ RECT 692.320000 155.800000 693.420000 156.280000 ;
+ RECT 692.320000 161.240000 693.420000 161.720000 ;
+ RECT 692.320000 166.680000 693.420000 167.160000 ;
+ RECT 647.320000 193.880000 648.420000 194.360000 ;
+ RECT 643.190000 193.880000 644.190000 194.360000 ;
+ RECT 647.320000 188.440000 648.420000 188.920000 ;
+ RECT 643.190000 188.440000 644.190000 188.920000 ;
+ RECT 647.320000 177.560000 648.420000 178.040000 ;
+ RECT 643.190000 177.560000 644.190000 178.040000 ;
+ RECT 647.320000 172.120000 648.420000 172.600000 ;
+ RECT 643.190000 172.120000 644.190000 172.600000 ;
+ RECT 647.320000 183.000000 648.420000 183.480000 ;
+ RECT 643.190000 183.000000 644.190000 183.480000 ;
+ RECT 647.320000 166.680000 648.420000 167.160000 ;
+ RECT 643.190000 166.680000 644.190000 167.160000 ;
+ RECT 647.320000 161.240000 648.420000 161.720000 ;
+ RECT 643.190000 161.240000 644.190000 161.720000 ;
+ RECT 647.320000 155.800000 648.420000 156.280000 ;
+ RECT 647.320000 150.360000 648.420000 150.840000 ;
+ RECT 643.190000 155.800000 644.190000 156.280000 ;
+ RECT 643.190000 150.360000 644.190000 150.840000 ;
+ RECT 640.360000 340.720000 840.460000 341.720000 ;
+ RECT 640.360000 148.350000 840.460000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 145.500000 644.190000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 344.760000 644.190000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 145.500000 837.630000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 344.760000 837.630000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 148.350000 641.360000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 148.350000 840.460000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 340.720000 641.360000 341.720000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 340.720000 840.460000 341.720000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'S_term_single2'
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 115.240000 644.190000 145.500000 ;
+ RECT 836.630000 115.240000 837.630000 145.500000 ;
+ RECT 647.320000 118.090000 648.420000 142.140000 ;
+ RECT 692.320000 118.090000 693.420000 142.140000 ;
+ RECT 737.320000 118.090000 738.420000 142.140000 ;
+ RECT 782.320000 118.090000 783.420000 142.140000 ;
+ RECT 827.320000 118.090000 828.420000 142.140000 ;
+ LAYER met3 ;
+ RECT 836.630000 130.980000 837.630000 131.460000 ;
+ RECT 836.630000 136.420000 837.630000 136.900000 ;
+ RECT 827.320000 136.420000 828.420000 136.900000 ;
+ RECT 827.320000 130.980000 828.420000 131.460000 ;
+ RECT 782.320000 130.980000 783.420000 131.460000 ;
+ RECT 782.320000 136.420000 783.420000 136.900000 ;
+ RECT 692.320000 130.980000 693.420000 131.460000 ;
+ RECT 737.320000 130.980000 738.420000 131.460000 ;
+ RECT 737.320000 136.420000 738.420000 136.900000 ;
+ RECT 692.320000 136.420000 693.420000 136.900000 ;
+ RECT 643.190000 130.980000 644.190000 131.460000 ;
+ RECT 647.320000 130.980000 648.420000 131.460000 ;
+ RECT 647.320000 136.420000 648.420000 136.900000 ;
+ RECT 643.190000 136.420000 644.190000 136.900000 ;
+ RECT 836.630000 120.100000 837.630000 120.580000 ;
+ RECT 836.630000 125.540000 837.630000 126.020000 ;
+ RECT 827.320000 125.540000 828.420000 126.020000 ;
+ RECT 827.320000 120.100000 828.420000 120.580000 ;
+ RECT 782.320000 120.100000 783.420000 120.580000 ;
+ RECT 782.320000 125.540000 783.420000 126.020000 ;
+ RECT 692.320000 120.100000 693.420000 120.580000 ;
+ RECT 737.320000 120.100000 738.420000 120.580000 ;
+ RECT 737.320000 125.540000 738.420000 126.020000 ;
+ RECT 692.320000 125.540000 693.420000 126.020000 ;
+ RECT 643.190000 125.540000 644.190000 126.020000 ;
+ RECT 647.320000 125.540000 648.420000 126.020000 ;
+ RECT 643.190000 120.100000 644.190000 120.580000 ;
+ RECT 647.320000 120.100000 648.420000 120.580000 ;
+ RECT 640.360000 141.140000 840.460000 142.140000 ;
+ RECT 640.360000 118.090000 840.460000 119.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 115.240000 644.190000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 144.500000 644.190000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 115.240000 837.630000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 144.500000 837.630000 145.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 118.090000 641.360000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 118.090000 840.460000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 141.140000 641.360000 142.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 141.140000 840.460000 142.140000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single2'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 3152.250000 828.420000 3345.620000 ;
+ RECT 782.320000 3152.250000 783.420000 3345.620000 ;
+ RECT 836.630000 3149.400000 837.630000 3349.660000 ;
+ RECT 737.320000 3152.250000 738.420000 3345.620000 ;
+ RECT 692.320000 3152.250000 693.420000 3345.620000 ;
+ RECT 647.320000 3152.250000 648.420000 3345.620000 ;
+ RECT 643.190000 3149.400000 644.190000 3349.660000 ;
+ LAYER met3 ;
+ RECT 827.320000 3339.220000 828.420000 3339.700000 ;
+ RECT 836.630000 3339.220000 837.630000 3339.700000 ;
+ RECT 836.630000 3328.340000 837.630000 3328.820000 ;
+ RECT 836.630000 3333.780000 837.630000 3334.260000 ;
+ RECT 827.320000 3333.780000 828.420000 3334.260000 ;
+ RECT 827.320000 3328.340000 828.420000 3328.820000 ;
+ RECT 827.320000 3322.900000 828.420000 3323.380000 ;
+ RECT 827.320000 3317.460000 828.420000 3317.940000 ;
+ RECT 836.630000 3322.900000 837.630000 3323.380000 ;
+ RECT 836.630000 3317.460000 837.630000 3317.940000 ;
+ RECT 827.320000 3301.140000 828.420000 3301.620000 ;
+ RECT 827.320000 3306.580000 828.420000 3307.060000 ;
+ RECT 836.630000 3306.580000 837.630000 3307.060000 ;
+ RECT 836.630000 3301.140000 837.630000 3301.620000 ;
+ RECT 827.320000 3312.020000 828.420000 3312.500000 ;
+ RECT 836.630000 3312.020000 837.630000 3312.500000 ;
+ RECT 782.320000 3339.220000 783.420000 3339.700000 ;
+ RECT 782.320000 3333.780000 783.420000 3334.260000 ;
+ RECT 782.320000 3328.340000 783.420000 3328.820000 ;
+ RECT 782.320000 3322.900000 783.420000 3323.380000 ;
+ RECT 782.320000 3301.140000 783.420000 3301.620000 ;
+ RECT 782.320000 3306.580000 783.420000 3307.060000 ;
+ RECT 782.320000 3312.020000 783.420000 3312.500000 ;
+ RECT 782.320000 3317.460000 783.420000 3317.940000 ;
+ RECT 836.630000 3290.260000 837.630000 3290.740000 ;
+ RECT 836.630000 3295.700000 837.630000 3296.180000 ;
+ RECT 827.320000 3295.700000 828.420000 3296.180000 ;
+ RECT 827.320000 3290.260000 828.420000 3290.740000 ;
+ RECT 827.320000 3284.820000 828.420000 3285.300000 ;
+ RECT 827.320000 3279.380000 828.420000 3279.860000 ;
+ RECT 836.630000 3284.820000 837.630000 3285.300000 ;
+ RECT 836.630000 3279.380000 837.630000 3279.860000 ;
+ RECT 836.630000 3263.060000 837.630000 3263.540000 ;
+ RECT 836.630000 3268.500000 837.630000 3268.980000 ;
+ RECT 836.630000 3273.940000 837.630000 3274.420000 ;
+ RECT 827.320000 3268.500000 828.420000 3268.980000 ;
+ RECT 827.320000 3263.060000 828.420000 3263.540000 ;
+ RECT 827.320000 3273.940000 828.420000 3274.420000 ;
+ RECT 827.320000 3257.620000 828.420000 3258.100000 ;
+ RECT 827.320000 3252.180000 828.420000 3252.660000 ;
+ RECT 836.630000 3257.620000 837.630000 3258.100000 ;
+ RECT 836.630000 3252.180000 837.630000 3252.660000 ;
+ RECT 782.320000 3295.700000 783.420000 3296.180000 ;
+ RECT 782.320000 3290.260000 783.420000 3290.740000 ;
+ RECT 782.320000 3284.820000 783.420000 3285.300000 ;
+ RECT 782.320000 3279.380000 783.420000 3279.860000 ;
+ RECT 782.320000 3268.500000 783.420000 3268.980000 ;
+ RECT 782.320000 3263.060000 783.420000 3263.540000 ;
+ RECT 782.320000 3257.620000 783.420000 3258.100000 ;
+ RECT 782.320000 3252.180000 783.420000 3252.660000 ;
+ RECT 782.320000 3273.940000 783.420000 3274.420000 ;
+ RECT 737.320000 3339.220000 738.420000 3339.700000 ;
+ RECT 737.320000 3333.780000 738.420000 3334.260000 ;
+ RECT 737.320000 3328.340000 738.420000 3328.820000 ;
+ RECT 692.320000 3339.220000 693.420000 3339.700000 ;
+ RECT 692.320000 3333.780000 693.420000 3334.260000 ;
+ RECT 692.320000 3328.340000 693.420000 3328.820000 ;
+ RECT 737.320000 3312.020000 738.420000 3312.500000 ;
+ RECT 737.320000 3306.580000 738.420000 3307.060000 ;
+ RECT 737.320000 3301.140000 738.420000 3301.620000 ;
+ RECT 737.320000 3317.460000 738.420000 3317.940000 ;
+ RECT 737.320000 3322.900000 738.420000 3323.380000 ;
+ RECT 692.320000 3322.900000 693.420000 3323.380000 ;
+ RECT 692.320000 3312.020000 693.420000 3312.500000 ;
+ RECT 692.320000 3306.580000 693.420000 3307.060000 ;
+ RECT 692.320000 3301.140000 693.420000 3301.620000 ;
+ RECT 692.320000 3317.460000 693.420000 3317.940000 ;
+ RECT 647.320000 3339.220000 648.420000 3339.700000 ;
+ RECT 643.190000 3339.220000 644.190000 3339.700000 ;
+ RECT 643.190000 3333.780000 644.190000 3334.260000 ;
+ RECT 647.320000 3333.780000 648.420000 3334.260000 ;
+ RECT 647.320000 3328.340000 648.420000 3328.820000 ;
+ RECT 643.190000 3328.340000 644.190000 3328.820000 ;
+ RECT 647.320000 3322.900000 648.420000 3323.380000 ;
+ RECT 643.190000 3322.900000 644.190000 3323.380000 ;
+ RECT 647.320000 3317.460000 648.420000 3317.940000 ;
+ RECT 643.190000 3317.460000 644.190000 3317.940000 ;
+ RECT 647.320000 3306.580000 648.420000 3307.060000 ;
+ RECT 643.190000 3306.580000 644.190000 3307.060000 ;
+ RECT 647.320000 3301.140000 648.420000 3301.620000 ;
+ RECT 643.190000 3301.140000 644.190000 3301.620000 ;
+ RECT 647.320000 3312.020000 648.420000 3312.500000 ;
+ RECT 643.190000 3312.020000 644.190000 3312.500000 ;
+ RECT 737.320000 3295.700000 738.420000 3296.180000 ;
+ RECT 737.320000 3290.260000 738.420000 3290.740000 ;
+ RECT 737.320000 3284.820000 738.420000 3285.300000 ;
+ RECT 737.320000 3279.380000 738.420000 3279.860000 ;
+ RECT 692.320000 3295.700000 693.420000 3296.180000 ;
+ RECT 692.320000 3290.260000 693.420000 3290.740000 ;
+ RECT 692.320000 3284.820000 693.420000 3285.300000 ;
+ RECT 692.320000 3279.380000 693.420000 3279.860000 ;
+ RECT 737.320000 3268.500000 738.420000 3268.980000 ;
+ RECT 737.320000 3252.180000 738.420000 3252.660000 ;
+ RECT 737.320000 3257.620000 738.420000 3258.100000 ;
+ RECT 737.320000 3263.060000 738.420000 3263.540000 ;
+ RECT 737.320000 3273.940000 738.420000 3274.420000 ;
+ RECT 692.320000 3252.180000 693.420000 3252.660000 ;
+ RECT 692.320000 3257.620000 693.420000 3258.100000 ;
+ RECT 692.320000 3263.060000 693.420000 3263.540000 ;
+ RECT 692.320000 3268.500000 693.420000 3268.980000 ;
+ RECT 692.320000 3273.940000 693.420000 3274.420000 ;
+ RECT 647.320000 3295.700000 648.420000 3296.180000 ;
+ RECT 643.190000 3295.700000 644.190000 3296.180000 ;
+ RECT 647.320000 3290.260000 648.420000 3290.740000 ;
+ RECT 643.190000 3290.260000 644.190000 3290.740000 ;
+ RECT 647.320000 3284.820000 648.420000 3285.300000 ;
+ RECT 643.190000 3284.820000 644.190000 3285.300000 ;
+ RECT 647.320000 3279.380000 648.420000 3279.860000 ;
+ RECT 643.190000 3279.380000 644.190000 3279.860000 ;
+ RECT 647.320000 3273.940000 648.420000 3274.420000 ;
+ RECT 647.320000 3268.500000 648.420000 3268.980000 ;
+ RECT 643.190000 3273.940000 644.190000 3274.420000 ;
+ RECT 643.190000 3268.500000 644.190000 3268.980000 ;
+ RECT 647.320000 3263.060000 648.420000 3263.540000 ;
+ RECT 643.190000 3263.060000 644.190000 3263.540000 ;
+ RECT 647.320000 3257.620000 648.420000 3258.100000 ;
+ RECT 643.190000 3257.620000 644.190000 3258.100000 ;
+ RECT 647.320000 3252.180000 648.420000 3252.660000 ;
+ RECT 643.190000 3252.180000 644.190000 3252.660000 ;
+ RECT 827.320000 3246.740000 828.420000 3247.220000 ;
+ RECT 827.320000 3241.300000 828.420000 3241.780000 ;
+ RECT 836.630000 3246.740000 837.630000 3247.220000 ;
+ RECT 836.630000 3241.300000 837.630000 3241.780000 ;
+ RECT 836.630000 3224.980000 837.630000 3225.460000 ;
+ RECT 836.630000 3230.420000 837.630000 3230.900000 ;
+ RECT 836.630000 3235.860000 837.630000 3236.340000 ;
+ RECT 827.320000 3235.860000 828.420000 3236.340000 ;
+ RECT 827.320000 3230.420000 828.420000 3230.900000 ;
+ RECT 827.320000 3224.980000 828.420000 3225.460000 ;
+ RECT 827.320000 3214.100000 828.420000 3214.580000 ;
+ RECT 827.320000 3219.540000 828.420000 3220.020000 ;
+ RECT 836.630000 3219.540000 837.630000 3220.020000 ;
+ RECT 836.630000 3214.100000 837.630000 3214.580000 ;
+ RECT 836.630000 3203.220000 837.630000 3203.700000 ;
+ RECT 836.630000 3208.660000 837.630000 3209.140000 ;
+ RECT 827.320000 3203.220000 828.420000 3203.700000 ;
+ RECT 827.320000 3208.660000 828.420000 3209.140000 ;
+ RECT 782.320000 3246.740000 783.420000 3247.220000 ;
+ RECT 782.320000 3241.300000 783.420000 3241.780000 ;
+ RECT 782.320000 3235.860000 783.420000 3236.340000 ;
+ RECT 782.320000 3230.420000 783.420000 3230.900000 ;
+ RECT 782.320000 3224.980000 783.420000 3225.460000 ;
+ RECT 782.320000 3203.220000 783.420000 3203.700000 ;
+ RECT 782.320000 3208.660000 783.420000 3209.140000 ;
+ RECT 782.320000 3214.100000 783.420000 3214.580000 ;
+ RECT 782.320000 3219.540000 783.420000 3220.020000 ;
+ RECT 827.320000 3197.780000 828.420000 3198.260000 ;
+ RECT 827.320000 3192.340000 828.420000 3192.820000 ;
+ RECT 836.630000 3197.780000 837.630000 3198.260000 ;
+ RECT 836.630000 3192.340000 837.630000 3192.820000 ;
+ RECT 827.320000 3181.460000 828.420000 3181.940000 ;
+ RECT 827.320000 3176.020000 828.420000 3176.500000 ;
+ RECT 836.630000 3181.460000 837.630000 3181.940000 ;
+ RECT 836.630000 3176.020000 837.630000 3176.500000 ;
+ RECT 827.320000 3186.900000 828.420000 3187.380000 ;
+ RECT 836.630000 3186.900000 837.630000 3187.380000 ;
+ RECT 836.630000 3165.140000 837.630000 3165.620000 ;
+ RECT 836.630000 3170.580000 837.630000 3171.060000 ;
+ RECT 827.320000 3170.580000 828.420000 3171.060000 ;
+ RECT 827.320000 3165.140000 828.420000 3165.620000 ;
+ RECT 827.320000 3159.700000 828.420000 3160.180000 ;
+ RECT 827.320000 3154.260000 828.420000 3154.740000 ;
+ RECT 836.630000 3159.700000 837.630000 3160.180000 ;
+ RECT 836.630000 3154.260000 837.630000 3154.740000 ;
+ RECT 782.320000 3197.780000 783.420000 3198.260000 ;
+ RECT 782.320000 3192.340000 783.420000 3192.820000 ;
+ RECT 782.320000 3186.900000 783.420000 3187.380000 ;
+ RECT 782.320000 3181.460000 783.420000 3181.940000 ;
+ RECT 782.320000 3176.020000 783.420000 3176.500000 ;
+ RECT 782.320000 3170.580000 783.420000 3171.060000 ;
+ RECT 782.320000 3165.140000 783.420000 3165.620000 ;
+ RECT 782.320000 3159.700000 783.420000 3160.180000 ;
+ RECT 782.320000 3154.260000 783.420000 3154.740000 ;
+ RECT 737.320000 3246.740000 738.420000 3247.220000 ;
+ RECT 737.320000 3241.300000 738.420000 3241.780000 ;
+ RECT 737.320000 3235.860000 738.420000 3236.340000 ;
+ RECT 737.320000 3230.420000 738.420000 3230.900000 ;
+ RECT 737.320000 3224.980000 738.420000 3225.460000 ;
+ RECT 692.320000 3246.740000 693.420000 3247.220000 ;
+ RECT 692.320000 3241.300000 693.420000 3241.780000 ;
+ RECT 692.320000 3235.860000 693.420000 3236.340000 ;
+ RECT 692.320000 3230.420000 693.420000 3230.900000 ;
+ RECT 692.320000 3224.980000 693.420000 3225.460000 ;
+ RECT 737.320000 3219.540000 738.420000 3220.020000 ;
+ RECT 737.320000 3214.100000 738.420000 3214.580000 ;
+ RECT 737.320000 3208.660000 738.420000 3209.140000 ;
+ RECT 737.320000 3203.220000 738.420000 3203.700000 ;
+ RECT 692.320000 3214.100000 693.420000 3214.580000 ;
+ RECT 692.320000 3208.660000 693.420000 3209.140000 ;
+ RECT 692.320000 3203.220000 693.420000 3203.700000 ;
+ RECT 692.320000 3219.540000 693.420000 3220.020000 ;
+ RECT 647.320000 3246.740000 648.420000 3247.220000 ;
+ RECT 643.190000 3246.740000 644.190000 3247.220000 ;
+ RECT 647.320000 3241.300000 648.420000 3241.780000 ;
+ RECT 643.190000 3241.300000 644.190000 3241.780000 ;
+ RECT 647.320000 3235.860000 648.420000 3236.340000 ;
+ RECT 643.190000 3235.860000 644.190000 3236.340000 ;
+ RECT 647.320000 3224.980000 648.420000 3225.460000 ;
+ RECT 643.190000 3224.980000 644.190000 3225.460000 ;
+ RECT 643.190000 3230.420000 644.190000 3230.900000 ;
+ RECT 647.320000 3230.420000 648.420000 3230.900000 ;
+ RECT 647.320000 3219.540000 648.420000 3220.020000 ;
+ RECT 643.190000 3219.540000 644.190000 3220.020000 ;
+ RECT 647.320000 3214.100000 648.420000 3214.580000 ;
+ RECT 643.190000 3214.100000 644.190000 3214.580000 ;
+ RECT 647.320000 3208.660000 648.420000 3209.140000 ;
+ RECT 643.190000 3208.660000 644.190000 3209.140000 ;
+ RECT 647.320000 3203.220000 648.420000 3203.700000 ;
+ RECT 643.190000 3203.220000 644.190000 3203.700000 ;
+ RECT 737.320000 3197.780000 738.420000 3198.260000 ;
+ RECT 737.320000 3192.340000 738.420000 3192.820000 ;
+ RECT 737.320000 3186.900000 738.420000 3187.380000 ;
+ RECT 737.320000 3181.460000 738.420000 3181.940000 ;
+ RECT 737.320000 3176.020000 738.420000 3176.500000 ;
+ RECT 692.320000 3197.780000 693.420000 3198.260000 ;
+ RECT 692.320000 3192.340000 693.420000 3192.820000 ;
+ RECT 692.320000 3186.900000 693.420000 3187.380000 ;
+ RECT 692.320000 3181.460000 693.420000 3181.940000 ;
+ RECT 692.320000 3176.020000 693.420000 3176.500000 ;
+ RECT 737.320000 3154.260000 738.420000 3154.740000 ;
+ RECT 737.320000 3159.700000 738.420000 3160.180000 ;
+ RECT 737.320000 3165.140000 738.420000 3165.620000 ;
+ RECT 737.320000 3170.580000 738.420000 3171.060000 ;
+ RECT 692.320000 3154.260000 693.420000 3154.740000 ;
+ RECT 692.320000 3159.700000 693.420000 3160.180000 ;
+ RECT 692.320000 3165.140000 693.420000 3165.620000 ;
+ RECT 692.320000 3170.580000 693.420000 3171.060000 ;
+ RECT 647.320000 3197.780000 648.420000 3198.260000 ;
+ RECT 643.190000 3197.780000 644.190000 3198.260000 ;
+ RECT 647.320000 3192.340000 648.420000 3192.820000 ;
+ RECT 643.190000 3192.340000 644.190000 3192.820000 ;
+ RECT 647.320000 3181.460000 648.420000 3181.940000 ;
+ RECT 643.190000 3181.460000 644.190000 3181.940000 ;
+ RECT 647.320000 3176.020000 648.420000 3176.500000 ;
+ RECT 643.190000 3176.020000 644.190000 3176.500000 ;
+ RECT 647.320000 3186.900000 648.420000 3187.380000 ;
+ RECT 643.190000 3186.900000 644.190000 3187.380000 ;
+ RECT 647.320000 3170.580000 648.420000 3171.060000 ;
+ RECT 643.190000 3170.580000 644.190000 3171.060000 ;
+ RECT 647.320000 3165.140000 648.420000 3165.620000 ;
+ RECT 643.190000 3165.140000 644.190000 3165.620000 ;
+ RECT 647.320000 3159.700000 648.420000 3160.180000 ;
+ RECT 647.320000 3154.260000 648.420000 3154.740000 ;
+ RECT 643.190000 3159.700000 644.190000 3160.180000 ;
+ RECT 643.190000 3154.260000 644.190000 3154.740000 ;
+ RECT 640.360000 3344.620000 840.460000 3345.620000 ;
+ RECT 640.360000 3152.250000 840.460000 3153.250000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 3149.400000 644.190000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 3348.660000 644.190000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 3149.400000 837.630000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 3348.660000 837.630000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 3152.250000 641.360000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 3152.250000 840.460000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 3344.620000 641.360000 3345.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 3344.620000 840.460000 3345.620000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 2951.990000 828.420000 3145.360000 ;
+ RECT 782.320000 2951.990000 783.420000 3145.360000 ;
+ RECT 836.630000 2949.140000 837.630000 3149.400000 ;
+ RECT 737.320000 2951.990000 738.420000 3145.360000 ;
+ RECT 692.320000 2951.990000 693.420000 3145.360000 ;
+ RECT 647.320000 2951.990000 648.420000 3145.360000 ;
+ RECT 643.190000 2949.140000 644.190000 3149.400000 ;
+ LAYER met3 ;
+ RECT 827.320000 3138.960000 828.420000 3139.440000 ;
+ RECT 836.630000 3138.960000 837.630000 3139.440000 ;
+ RECT 836.630000 3128.080000 837.630000 3128.560000 ;
+ RECT 836.630000 3133.520000 837.630000 3134.000000 ;
+ RECT 827.320000 3133.520000 828.420000 3134.000000 ;
+ RECT 827.320000 3128.080000 828.420000 3128.560000 ;
+ RECT 827.320000 3122.640000 828.420000 3123.120000 ;
+ RECT 827.320000 3117.200000 828.420000 3117.680000 ;
+ RECT 836.630000 3122.640000 837.630000 3123.120000 ;
+ RECT 836.630000 3117.200000 837.630000 3117.680000 ;
+ RECT 827.320000 3100.880000 828.420000 3101.360000 ;
+ RECT 827.320000 3106.320000 828.420000 3106.800000 ;
+ RECT 836.630000 3106.320000 837.630000 3106.800000 ;
+ RECT 836.630000 3100.880000 837.630000 3101.360000 ;
+ RECT 827.320000 3111.760000 828.420000 3112.240000 ;
+ RECT 836.630000 3111.760000 837.630000 3112.240000 ;
+ RECT 782.320000 3138.960000 783.420000 3139.440000 ;
+ RECT 782.320000 3133.520000 783.420000 3134.000000 ;
+ RECT 782.320000 3128.080000 783.420000 3128.560000 ;
+ RECT 782.320000 3122.640000 783.420000 3123.120000 ;
+ RECT 782.320000 3100.880000 783.420000 3101.360000 ;
+ RECT 782.320000 3106.320000 783.420000 3106.800000 ;
+ RECT 782.320000 3111.760000 783.420000 3112.240000 ;
+ RECT 782.320000 3117.200000 783.420000 3117.680000 ;
+ RECT 836.630000 3090.000000 837.630000 3090.480000 ;
+ RECT 836.630000 3095.440000 837.630000 3095.920000 ;
+ RECT 827.320000 3095.440000 828.420000 3095.920000 ;
+ RECT 827.320000 3090.000000 828.420000 3090.480000 ;
+ RECT 827.320000 3084.560000 828.420000 3085.040000 ;
+ RECT 827.320000 3079.120000 828.420000 3079.600000 ;
+ RECT 836.630000 3084.560000 837.630000 3085.040000 ;
+ RECT 836.630000 3079.120000 837.630000 3079.600000 ;
+ RECT 836.630000 3062.800000 837.630000 3063.280000 ;
+ RECT 836.630000 3068.240000 837.630000 3068.720000 ;
+ RECT 836.630000 3073.680000 837.630000 3074.160000 ;
+ RECT 827.320000 3068.240000 828.420000 3068.720000 ;
+ RECT 827.320000 3062.800000 828.420000 3063.280000 ;
+ RECT 827.320000 3073.680000 828.420000 3074.160000 ;
+ RECT 827.320000 3057.360000 828.420000 3057.840000 ;
+ RECT 827.320000 3051.920000 828.420000 3052.400000 ;
+ RECT 836.630000 3057.360000 837.630000 3057.840000 ;
+ RECT 836.630000 3051.920000 837.630000 3052.400000 ;
+ RECT 782.320000 3095.440000 783.420000 3095.920000 ;
+ RECT 782.320000 3090.000000 783.420000 3090.480000 ;
+ RECT 782.320000 3084.560000 783.420000 3085.040000 ;
+ RECT 782.320000 3079.120000 783.420000 3079.600000 ;
+ RECT 782.320000 3068.240000 783.420000 3068.720000 ;
+ RECT 782.320000 3062.800000 783.420000 3063.280000 ;
+ RECT 782.320000 3057.360000 783.420000 3057.840000 ;
+ RECT 782.320000 3051.920000 783.420000 3052.400000 ;
+ RECT 782.320000 3073.680000 783.420000 3074.160000 ;
+ RECT 737.320000 3138.960000 738.420000 3139.440000 ;
+ RECT 737.320000 3133.520000 738.420000 3134.000000 ;
+ RECT 737.320000 3128.080000 738.420000 3128.560000 ;
+ RECT 692.320000 3138.960000 693.420000 3139.440000 ;
+ RECT 692.320000 3133.520000 693.420000 3134.000000 ;
+ RECT 692.320000 3128.080000 693.420000 3128.560000 ;
+ RECT 737.320000 3111.760000 738.420000 3112.240000 ;
+ RECT 737.320000 3106.320000 738.420000 3106.800000 ;
+ RECT 737.320000 3100.880000 738.420000 3101.360000 ;
+ RECT 737.320000 3117.200000 738.420000 3117.680000 ;
+ RECT 737.320000 3122.640000 738.420000 3123.120000 ;
+ RECT 692.320000 3122.640000 693.420000 3123.120000 ;
+ RECT 692.320000 3111.760000 693.420000 3112.240000 ;
+ RECT 692.320000 3106.320000 693.420000 3106.800000 ;
+ RECT 692.320000 3100.880000 693.420000 3101.360000 ;
+ RECT 692.320000 3117.200000 693.420000 3117.680000 ;
+ RECT 647.320000 3138.960000 648.420000 3139.440000 ;
+ RECT 643.190000 3138.960000 644.190000 3139.440000 ;
+ RECT 643.190000 3133.520000 644.190000 3134.000000 ;
+ RECT 647.320000 3133.520000 648.420000 3134.000000 ;
+ RECT 647.320000 3128.080000 648.420000 3128.560000 ;
+ RECT 643.190000 3128.080000 644.190000 3128.560000 ;
+ RECT 647.320000 3122.640000 648.420000 3123.120000 ;
+ RECT 643.190000 3122.640000 644.190000 3123.120000 ;
+ RECT 647.320000 3117.200000 648.420000 3117.680000 ;
+ RECT 643.190000 3117.200000 644.190000 3117.680000 ;
+ RECT 647.320000 3106.320000 648.420000 3106.800000 ;
+ RECT 643.190000 3106.320000 644.190000 3106.800000 ;
+ RECT 647.320000 3100.880000 648.420000 3101.360000 ;
+ RECT 643.190000 3100.880000 644.190000 3101.360000 ;
+ RECT 647.320000 3111.760000 648.420000 3112.240000 ;
+ RECT 643.190000 3111.760000 644.190000 3112.240000 ;
+ RECT 737.320000 3095.440000 738.420000 3095.920000 ;
+ RECT 737.320000 3090.000000 738.420000 3090.480000 ;
+ RECT 737.320000 3084.560000 738.420000 3085.040000 ;
+ RECT 737.320000 3079.120000 738.420000 3079.600000 ;
+ RECT 692.320000 3095.440000 693.420000 3095.920000 ;
+ RECT 692.320000 3090.000000 693.420000 3090.480000 ;
+ RECT 692.320000 3084.560000 693.420000 3085.040000 ;
+ RECT 692.320000 3079.120000 693.420000 3079.600000 ;
+ RECT 737.320000 3068.240000 738.420000 3068.720000 ;
+ RECT 737.320000 3051.920000 738.420000 3052.400000 ;
+ RECT 737.320000 3057.360000 738.420000 3057.840000 ;
+ RECT 737.320000 3062.800000 738.420000 3063.280000 ;
+ RECT 737.320000 3073.680000 738.420000 3074.160000 ;
+ RECT 692.320000 3051.920000 693.420000 3052.400000 ;
+ RECT 692.320000 3057.360000 693.420000 3057.840000 ;
+ RECT 692.320000 3062.800000 693.420000 3063.280000 ;
+ RECT 692.320000 3068.240000 693.420000 3068.720000 ;
+ RECT 692.320000 3073.680000 693.420000 3074.160000 ;
+ RECT 647.320000 3095.440000 648.420000 3095.920000 ;
+ RECT 643.190000 3095.440000 644.190000 3095.920000 ;
+ RECT 647.320000 3090.000000 648.420000 3090.480000 ;
+ RECT 643.190000 3090.000000 644.190000 3090.480000 ;
+ RECT 647.320000 3084.560000 648.420000 3085.040000 ;
+ RECT 643.190000 3084.560000 644.190000 3085.040000 ;
+ RECT 647.320000 3079.120000 648.420000 3079.600000 ;
+ RECT 643.190000 3079.120000 644.190000 3079.600000 ;
+ RECT 647.320000 3073.680000 648.420000 3074.160000 ;
+ RECT 647.320000 3068.240000 648.420000 3068.720000 ;
+ RECT 643.190000 3073.680000 644.190000 3074.160000 ;
+ RECT 643.190000 3068.240000 644.190000 3068.720000 ;
+ RECT 647.320000 3062.800000 648.420000 3063.280000 ;
+ RECT 643.190000 3062.800000 644.190000 3063.280000 ;
+ RECT 647.320000 3057.360000 648.420000 3057.840000 ;
+ RECT 643.190000 3057.360000 644.190000 3057.840000 ;
+ RECT 647.320000 3051.920000 648.420000 3052.400000 ;
+ RECT 643.190000 3051.920000 644.190000 3052.400000 ;
+ RECT 827.320000 3046.480000 828.420000 3046.960000 ;
+ RECT 827.320000 3041.040000 828.420000 3041.520000 ;
+ RECT 836.630000 3046.480000 837.630000 3046.960000 ;
+ RECT 836.630000 3041.040000 837.630000 3041.520000 ;
+ RECT 836.630000 3024.720000 837.630000 3025.200000 ;
+ RECT 836.630000 3030.160000 837.630000 3030.640000 ;
+ RECT 836.630000 3035.600000 837.630000 3036.080000 ;
+ RECT 827.320000 3035.600000 828.420000 3036.080000 ;
+ RECT 827.320000 3030.160000 828.420000 3030.640000 ;
+ RECT 827.320000 3024.720000 828.420000 3025.200000 ;
+ RECT 827.320000 3013.840000 828.420000 3014.320000 ;
+ RECT 827.320000 3019.280000 828.420000 3019.760000 ;
+ RECT 836.630000 3019.280000 837.630000 3019.760000 ;
+ RECT 836.630000 3013.840000 837.630000 3014.320000 ;
+ RECT 836.630000 3002.960000 837.630000 3003.440000 ;
+ RECT 836.630000 3008.400000 837.630000 3008.880000 ;
+ RECT 827.320000 3002.960000 828.420000 3003.440000 ;
+ RECT 827.320000 3008.400000 828.420000 3008.880000 ;
+ RECT 782.320000 3046.480000 783.420000 3046.960000 ;
+ RECT 782.320000 3041.040000 783.420000 3041.520000 ;
+ RECT 782.320000 3035.600000 783.420000 3036.080000 ;
+ RECT 782.320000 3030.160000 783.420000 3030.640000 ;
+ RECT 782.320000 3024.720000 783.420000 3025.200000 ;
+ RECT 782.320000 3002.960000 783.420000 3003.440000 ;
+ RECT 782.320000 3008.400000 783.420000 3008.880000 ;
+ RECT 782.320000 3013.840000 783.420000 3014.320000 ;
+ RECT 782.320000 3019.280000 783.420000 3019.760000 ;
+ RECT 827.320000 2997.520000 828.420000 2998.000000 ;
+ RECT 827.320000 2992.080000 828.420000 2992.560000 ;
+ RECT 836.630000 2997.520000 837.630000 2998.000000 ;
+ RECT 836.630000 2992.080000 837.630000 2992.560000 ;
+ RECT 827.320000 2981.200000 828.420000 2981.680000 ;
+ RECT 827.320000 2975.760000 828.420000 2976.240000 ;
+ RECT 836.630000 2981.200000 837.630000 2981.680000 ;
+ RECT 836.630000 2975.760000 837.630000 2976.240000 ;
+ RECT 827.320000 2986.640000 828.420000 2987.120000 ;
+ RECT 836.630000 2986.640000 837.630000 2987.120000 ;
+ RECT 836.630000 2964.880000 837.630000 2965.360000 ;
+ RECT 836.630000 2970.320000 837.630000 2970.800000 ;
+ RECT 827.320000 2970.320000 828.420000 2970.800000 ;
+ RECT 827.320000 2964.880000 828.420000 2965.360000 ;
+ RECT 827.320000 2959.440000 828.420000 2959.920000 ;
+ RECT 827.320000 2954.000000 828.420000 2954.480000 ;
+ RECT 836.630000 2959.440000 837.630000 2959.920000 ;
+ RECT 836.630000 2954.000000 837.630000 2954.480000 ;
+ RECT 782.320000 2997.520000 783.420000 2998.000000 ;
+ RECT 782.320000 2992.080000 783.420000 2992.560000 ;
+ RECT 782.320000 2986.640000 783.420000 2987.120000 ;
+ RECT 782.320000 2981.200000 783.420000 2981.680000 ;
+ RECT 782.320000 2975.760000 783.420000 2976.240000 ;
+ RECT 782.320000 2970.320000 783.420000 2970.800000 ;
+ RECT 782.320000 2964.880000 783.420000 2965.360000 ;
+ RECT 782.320000 2959.440000 783.420000 2959.920000 ;
+ RECT 782.320000 2954.000000 783.420000 2954.480000 ;
+ RECT 737.320000 3046.480000 738.420000 3046.960000 ;
+ RECT 737.320000 3041.040000 738.420000 3041.520000 ;
+ RECT 737.320000 3035.600000 738.420000 3036.080000 ;
+ RECT 737.320000 3030.160000 738.420000 3030.640000 ;
+ RECT 737.320000 3024.720000 738.420000 3025.200000 ;
+ RECT 692.320000 3046.480000 693.420000 3046.960000 ;
+ RECT 692.320000 3041.040000 693.420000 3041.520000 ;
+ RECT 692.320000 3035.600000 693.420000 3036.080000 ;
+ RECT 692.320000 3030.160000 693.420000 3030.640000 ;
+ RECT 692.320000 3024.720000 693.420000 3025.200000 ;
+ RECT 737.320000 3019.280000 738.420000 3019.760000 ;
+ RECT 737.320000 3013.840000 738.420000 3014.320000 ;
+ RECT 737.320000 3008.400000 738.420000 3008.880000 ;
+ RECT 737.320000 3002.960000 738.420000 3003.440000 ;
+ RECT 692.320000 3013.840000 693.420000 3014.320000 ;
+ RECT 692.320000 3008.400000 693.420000 3008.880000 ;
+ RECT 692.320000 3002.960000 693.420000 3003.440000 ;
+ RECT 692.320000 3019.280000 693.420000 3019.760000 ;
+ RECT 647.320000 3046.480000 648.420000 3046.960000 ;
+ RECT 643.190000 3046.480000 644.190000 3046.960000 ;
+ RECT 647.320000 3041.040000 648.420000 3041.520000 ;
+ RECT 643.190000 3041.040000 644.190000 3041.520000 ;
+ RECT 647.320000 3035.600000 648.420000 3036.080000 ;
+ RECT 643.190000 3035.600000 644.190000 3036.080000 ;
+ RECT 647.320000 3024.720000 648.420000 3025.200000 ;
+ RECT 643.190000 3024.720000 644.190000 3025.200000 ;
+ RECT 643.190000 3030.160000 644.190000 3030.640000 ;
+ RECT 647.320000 3030.160000 648.420000 3030.640000 ;
+ RECT 647.320000 3019.280000 648.420000 3019.760000 ;
+ RECT 643.190000 3019.280000 644.190000 3019.760000 ;
+ RECT 647.320000 3013.840000 648.420000 3014.320000 ;
+ RECT 643.190000 3013.840000 644.190000 3014.320000 ;
+ RECT 647.320000 3008.400000 648.420000 3008.880000 ;
+ RECT 643.190000 3008.400000 644.190000 3008.880000 ;
+ RECT 647.320000 3002.960000 648.420000 3003.440000 ;
+ RECT 643.190000 3002.960000 644.190000 3003.440000 ;
+ RECT 737.320000 2997.520000 738.420000 2998.000000 ;
+ RECT 737.320000 2992.080000 738.420000 2992.560000 ;
+ RECT 737.320000 2986.640000 738.420000 2987.120000 ;
+ RECT 737.320000 2981.200000 738.420000 2981.680000 ;
+ RECT 737.320000 2975.760000 738.420000 2976.240000 ;
+ RECT 692.320000 2997.520000 693.420000 2998.000000 ;
+ RECT 692.320000 2992.080000 693.420000 2992.560000 ;
+ RECT 692.320000 2986.640000 693.420000 2987.120000 ;
+ RECT 692.320000 2981.200000 693.420000 2981.680000 ;
+ RECT 692.320000 2975.760000 693.420000 2976.240000 ;
+ RECT 737.320000 2954.000000 738.420000 2954.480000 ;
+ RECT 737.320000 2959.440000 738.420000 2959.920000 ;
+ RECT 737.320000 2964.880000 738.420000 2965.360000 ;
+ RECT 737.320000 2970.320000 738.420000 2970.800000 ;
+ RECT 692.320000 2954.000000 693.420000 2954.480000 ;
+ RECT 692.320000 2959.440000 693.420000 2959.920000 ;
+ RECT 692.320000 2964.880000 693.420000 2965.360000 ;
+ RECT 692.320000 2970.320000 693.420000 2970.800000 ;
+ RECT 647.320000 2997.520000 648.420000 2998.000000 ;
+ RECT 643.190000 2997.520000 644.190000 2998.000000 ;
+ RECT 647.320000 2992.080000 648.420000 2992.560000 ;
+ RECT 643.190000 2992.080000 644.190000 2992.560000 ;
+ RECT 647.320000 2981.200000 648.420000 2981.680000 ;
+ RECT 643.190000 2981.200000 644.190000 2981.680000 ;
+ RECT 647.320000 2975.760000 648.420000 2976.240000 ;
+ RECT 643.190000 2975.760000 644.190000 2976.240000 ;
+ RECT 647.320000 2986.640000 648.420000 2987.120000 ;
+ RECT 643.190000 2986.640000 644.190000 2987.120000 ;
+ RECT 647.320000 2970.320000 648.420000 2970.800000 ;
+ RECT 643.190000 2970.320000 644.190000 2970.800000 ;
+ RECT 647.320000 2964.880000 648.420000 2965.360000 ;
+ RECT 643.190000 2964.880000 644.190000 2965.360000 ;
+ RECT 647.320000 2959.440000 648.420000 2959.920000 ;
+ RECT 647.320000 2954.000000 648.420000 2954.480000 ;
+ RECT 643.190000 2959.440000 644.190000 2959.920000 ;
+ RECT 643.190000 2954.000000 644.190000 2954.480000 ;
+ RECT 640.360000 3144.360000 840.460000 3145.360000 ;
+ RECT 640.360000 2951.990000 840.460000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 2949.140000 644.190000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 3148.400000 644.190000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 2949.140000 837.630000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 3148.400000 837.630000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2951.990000 641.360000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2951.990000 840.460000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 3144.360000 641.360000 3145.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 3144.360000 840.460000 3145.360000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 2751.730000 828.420000 2945.100000 ;
+ RECT 782.320000 2751.730000 783.420000 2945.100000 ;
+ RECT 836.630000 2748.880000 837.630000 2949.140000 ;
+ RECT 737.320000 2751.730000 738.420000 2945.100000 ;
+ RECT 692.320000 2751.730000 693.420000 2945.100000 ;
+ RECT 647.320000 2751.730000 648.420000 2945.100000 ;
+ RECT 643.190000 2748.880000 644.190000 2949.140000 ;
+ LAYER met3 ;
+ RECT 827.320000 2938.700000 828.420000 2939.180000 ;
+ RECT 836.630000 2938.700000 837.630000 2939.180000 ;
+ RECT 836.630000 2927.820000 837.630000 2928.300000 ;
+ RECT 836.630000 2933.260000 837.630000 2933.740000 ;
+ RECT 827.320000 2933.260000 828.420000 2933.740000 ;
+ RECT 827.320000 2927.820000 828.420000 2928.300000 ;
+ RECT 827.320000 2922.380000 828.420000 2922.860000 ;
+ RECT 827.320000 2916.940000 828.420000 2917.420000 ;
+ RECT 836.630000 2922.380000 837.630000 2922.860000 ;
+ RECT 836.630000 2916.940000 837.630000 2917.420000 ;
+ RECT 827.320000 2900.620000 828.420000 2901.100000 ;
+ RECT 827.320000 2906.060000 828.420000 2906.540000 ;
+ RECT 836.630000 2906.060000 837.630000 2906.540000 ;
+ RECT 836.630000 2900.620000 837.630000 2901.100000 ;
+ RECT 827.320000 2911.500000 828.420000 2911.980000 ;
+ RECT 836.630000 2911.500000 837.630000 2911.980000 ;
+ RECT 782.320000 2938.700000 783.420000 2939.180000 ;
+ RECT 782.320000 2933.260000 783.420000 2933.740000 ;
+ RECT 782.320000 2927.820000 783.420000 2928.300000 ;
+ RECT 782.320000 2922.380000 783.420000 2922.860000 ;
+ RECT 782.320000 2900.620000 783.420000 2901.100000 ;
+ RECT 782.320000 2906.060000 783.420000 2906.540000 ;
+ RECT 782.320000 2911.500000 783.420000 2911.980000 ;
+ RECT 782.320000 2916.940000 783.420000 2917.420000 ;
+ RECT 836.630000 2889.740000 837.630000 2890.220000 ;
+ RECT 836.630000 2895.180000 837.630000 2895.660000 ;
+ RECT 827.320000 2895.180000 828.420000 2895.660000 ;
+ RECT 827.320000 2889.740000 828.420000 2890.220000 ;
+ RECT 827.320000 2884.300000 828.420000 2884.780000 ;
+ RECT 827.320000 2878.860000 828.420000 2879.340000 ;
+ RECT 836.630000 2884.300000 837.630000 2884.780000 ;
+ RECT 836.630000 2878.860000 837.630000 2879.340000 ;
+ RECT 836.630000 2862.540000 837.630000 2863.020000 ;
+ RECT 836.630000 2867.980000 837.630000 2868.460000 ;
+ RECT 836.630000 2873.420000 837.630000 2873.900000 ;
+ RECT 827.320000 2867.980000 828.420000 2868.460000 ;
+ RECT 827.320000 2862.540000 828.420000 2863.020000 ;
+ RECT 827.320000 2873.420000 828.420000 2873.900000 ;
+ RECT 827.320000 2857.100000 828.420000 2857.580000 ;
+ RECT 827.320000 2851.660000 828.420000 2852.140000 ;
+ RECT 836.630000 2857.100000 837.630000 2857.580000 ;
+ RECT 836.630000 2851.660000 837.630000 2852.140000 ;
+ RECT 782.320000 2895.180000 783.420000 2895.660000 ;
+ RECT 782.320000 2889.740000 783.420000 2890.220000 ;
+ RECT 782.320000 2884.300000 783.420000 2884.780000 ;
+ RECT 782.320000 2878.860000 783.420000 2879.340000 ;
+ RECT 782.320000 2867.980000 783.420000 2868.460000 ;
+ RECT 782.320000 2862.540000 783.420000 2863.020000 ;
+ RECT 782.320000 2857.100000 783.420000 2857.580000 ;
+ RECT 782.320000 2851.660000 783.420000 2852.140000 ;
+ RECT 782.320000 2873.420000 783.420000 2873.900000 ;
+ RECT 737.320000 2938.700000 738.420000 2939.180000 ;
+ RECT 737.320000 2933.260000 738.420000 2933.740000 ;
+ RECT 737.320000 2927.820000 738.420000 2928.300000 ;
+ RECT 692.320000 2938.700000 693.420000 2939.180000 ;
+ RECT 692.320000 2933.260000 693.420000 2933.740000 ;
+ RECT 692.320000 2927.820000 693.420000 2928.300000 ;
+ RECT 737.320000 2911.500000 738.420000 2911.980000 ;
+ RECT 737.320000 2906.060000 738.420000 2906.540000 ;
+ RECT 737.320000 2900.620000 738.420000 2901.100000 ;
+ RECT 737.320000 2916.940000 738.420000 2917.420000 ;
+ RECT 737.320000 2922.380000 738.420000 2922.860000 ;
+ RECT 692.320000 2922.380000 693.420000 2922.860000 ;
+ RECT 692.320000 2911.500000 693.420000 2911.980000 ;
+ RECT 692.320000 2906.060000 693.420000 2906.540000 ;
+ RECT 692.320000 2900.620000 693.420000 2901.100000 ;
+ RECT 692.320000 2916.940000 693.420000 2917.420000 ;
+ RECT 647.320000 2938.700000 648.420000 2939.180000 ;
+ RECT 643.190000 2938.700000 644.190000 2939.180000 ;
+ RECT 643.190000 2933.260000 644.190000 2933.740000 ;
+ RECT 647.320000 2933.260000 648.420000 2933.740000 ;
+ RECT 647.320000 2927.820000 648.420000 2928.300000 ;
+ RECT 643.190000 2927.820000 644.190000 2928.300000 ;
+ RECT 647.320000 2922.380000 648.420000 2922.860000 ;
+ RECT 643.190000 2922.380000 644.190000 2922.860000 ;
+ RECT 647.320000 2916.940000 648.420000 2917.420000 ;
+ RECT 643.190000 2916.940000 644.190000 2917.420000 ;
+ RECT 647.320000 2906.060000 648.420000 2906.540000 ;
+ RECT 643.190000 2906.060000 644.190000 2906.540000 ;
+ RECT 647.320000 2900.620000 648.420000 2901.100000 ;
+ RECT 643.190000 2900.620000 644.190000 2901.100000 ;
+ RECT 647.320000 2911.500000 648.420000 2911.980000 ;
+ RECT 643.190000 2911.500000 644.190000 2911.980000 ;
+ RECT 737.320000 2895.180000 738.420000 2895.660000 ;
+ RECT 737.320000 2889.740000 738.420000 2890.220000 ;
+ RECT 737.320000 2884.300000 738.420000 2884.780000 ;
+ RECT 737.320000 2878.860000 738.420000 2879.340000 ;
+ RECT 692.320000 2895.180000 693.420000 2895.660000 ;
+ RECT 692.320000 2889.740000 693.420000 2890.220000 ;
+ RECT 692.320000 2884.300000 693.420000 2884.780000 ;
+ RECT 692.320000 2878.860000 693.420000 2879.340000 ;
+ RECT 737.320000 2867.980000 738.420000 2868.460000 ;
+ RECT 737.320000 2851.660000 738.420000 2852.140000 ;
+ RECT 737.320000 2857.100000 738.420000 2857.580000 ;
+ RECT 737.320000 2862.540000 738.420000 2863.020000 ;
+ RECT 737.320000 2873.420000 738.420000 2873.900000 ;
+ RECT 692.320000 2851.660000 693.420000 2852.140000 ;
+ RECT 692.320000 2857.100000 693.420000 2857.580000 ;
+ RECT 692.320000 2862.540000 693.420000 2863.020000 ;
+ RECT 692.320000 2867.980000 693.420000 2868.460000 ;
+ RECT 692.320000 2873.420000 693.420000 2873.900000 ;
+ RECT 647.320000 2895.180000 648.420000 2895.660000 ;
+ RECT 643.190000 2895.180000 644.190000 2895.660000 ;
+ RECT 647.320000 2889.740000 648.420000 2890.220000 ;
+ RECT 643.190000 2889.740000 644.190000 2890.220000 ;
+ RECT 647.320000 2884.300000 648.420000 2884.780000 ;
+ RECT 643.190000 2884.300000 644.190000 2884.780000 ;
+ RECT 647.320000 2878.860000 648.420000 2879.340000 ;
+ RECT 643.190000 2878.860000 644.190000 2879.340000 ;
+ RECT 647.320000 2873.420000 648.420000 2873.900000 ;
+ RECT 647.320000 2867.980000 648.420000 2868.460000 ;
+ RECT 643.190000 2873.420000 644.190000 2873.900000 ;
+ RECT 643.190000 2867.980000 644.190000 2868.460000 ;
+ RECT 647.320000 2862.540000 648.420000 2863.020000 ;
+ RECT 643.190000 2862.540000 644.190000 2863.020000 ;
+ RECT 647.320000 2857.100000 648.420000 2857.580000 ;
+ RECT 643.190000 2857.100000 644.190000 2857.580000 ;
+ RECT 647.320000 2851.660000 648.420000 2852.140000 ;
+ RECT 643.190000 2851.660000 644.190000 2852.140000 ;
+ RECT 827.320000 2846.220000 828.420000 2846.700000 ;
+ RECT 827.320000 2840.780000 828.420000 2841.260000 ;
+ RECT 836.630000 2846.220000 837.630000 2846.700000 ;
+ RECT 836.630000 2840.780000 837.630000 2841.260000 ;
+ RECT 836.630000 2824.460000 837.630000 2824.940000 ;
+ RECT 836.630000 2829.900000 837.630000 2830.380000 ;
+ RECT 836.630000 2835.340000 837.630000 2835.820000 ;
+ RECT 827.320000 2835.340000 828.420000 2835.820000 ;
+ RECT 827.320000 2829.900000 828.420000 2830.380000 ;
+ RECT 827.320000 2824.460000 828.420000 2824.940000 ;
+ RECT 827.320000 2813.580000 828.420000 2814.060000 ;
+ RECT 827.320000 2819.020000 828.420000 2819.500000 ;
+ RECT 836.630000 2819.020000 837.630000 2819.500000 ;
+ RECT 836.630000 2813.580000 837.630000 2814.060000 ;
+ RECT 836.630000 2802.700000 837.630000 2803.180000 ;
+ RECT 836.630000 2808.140000 837.630000 2808.620000 ;
+ RECT 827.320000 2802.700000 828.420000 2803.180000 ;
+ RECT 827.320000 2808.140000 828.420000 2808.620000 ;
+ RECT 782.320000 2846.220000 783.420000 2846.700000 ;
+ RECT 782.320000 2840.780000 783.420000 2841.260000 ;
+ RECT 782.320000 2835.340000 783.420000 2835.820000 ;
+ RECT 782.320000 2829.900000 783.420000 2830.380000 ;
+ RECT 782.320000 2824.460000 783.420000 2824.940000 ;
+ RECT 782.320000 2802.700000 783.420000 2803.180000 ;
+ RECT 782.320000 2808.140000 783.420000 2808.620000 ;
+ RECT 782.320000 2813.580000 783.420000 2814.060000 ;
+ RECT 782.320000 2819.020000 783.420000 2819.500000 ;
+ RECT 827.320000 2797.260000 828.420000 2797.740000 ;
+ RECT 827.320000 2791.820000 828.420000 2792.300000 ;
+ RECT 836.630000 2797.260000 837.630000 2797.740000 ;
+ RECT 836.630000 2791.820000 837.630000 2792.300000 ;
+ RECT 827.320000 2780.940000 828.420000 2781.420000 ;
+ RECT 827.320000 2775.500000 828.420000 2775.980000 ;
+ RECT 836.630000 2780.940000 837.630000 2781.420000 ;
+ RECT 836.630000 2775.500000 837.630000 2775.980000 ;
+ RECT 827.320000 2786.380000 828.420000 2786.860000 ;
+ RECT 836.630000 2786.380000 837.630000 2786.860000 ;
+ RECT 836.630000 2764.620000 837.630000 2765.100000 ;
+ RECT 836.630000 2770.060000 837.630000 2770.540000 ;
+ RECT 827.320000 2770.060000 828.420000 2770.540000 ;
+ RECT 827.320000 2764.620000 828.420000 2765.100000 ;
+ RECT 827.320000 2759.180000 828.420000 2759.660000 ;
+ RECT 827.320000 2753.740000 828.420000 2754.220000 ;
+ RECT 836.630000 2759.180000 837.630000 2759.660000 ;
+ RECT 836.630000 2753.740000 837.630000 2754.220000 ;
+ RECT 782.320000 2797.260000 783.420000 2797.740000 ;
+ RECT 782.320000 2791.820000 783.420000 2792.300000 ;
+ RECT 782.320000 2786.380000 783.420000 2786.860000 ;
+ RECT 782.320000 2780.940000 783.420000 2781.420000 ;
+ RECT 782.320000 2775.500000 783.420000 2775.980000 ;
+ RECT 782.320000 2770.060000 783.420000 2770.540000 ;
+ RECT 782.320000 2764.620000 783.420000 2765.100000 ;
+ RECT 782.320000 2759.180000 783.420000 2759.660000 ;
+ RECT 782.320000 2753.740000 783.420000 2754.220000 ;
+ RECT 737.320000 2846.220000 738.420000 2846.700000 ;
+ RECT 737.320000 2840.780000 738.420000 2841.260000 ;
+ RECT 737.320000 2835.340000 738.420000 2835.820000 ;
+ RECT 737.320000 2829.900000 738.420000 2830.380000 ;
+ RECT 737.320000 2824.460000 738.420000 2824.940000 ;
+ RECT 692.320000 2846.220000 693.420000 2846.700000 ;
+ RECT 692.320000 2840.780000 693.420000 2841.260000 ;
+ RECT 692.320000 2835.340000 693.420000 2835.820000 ;
+ RECT 692.320000 2829.900000 693.420000 2830.380000 ;
+ RECT 692.320000 2824.460000 693.420000 2824.940000 ;
+ RECT 737.320000 2819.020000 738.420000 2819.500000 ;
+ RECT 737.320000 2813.580000 738.420000 2814.060000 ;
+ RECT 737.320000 2808.140000 738.420000 2808.620000 ;
+ RECT 737.320000 2802.700000 738.420000 2803.180000 ;
+ RECT 692.320000 2813.580000 693.420000 2814.060000 ;
+ RECT 692.320000 2808.140000 693.420000 2808.620000 ;
+ RECT 692.320000 2802.700000 693.420000 2803.180000 ;
+ RECT 692.320000 2819.020000 693.420000 2819.500000 ;
+ RECT 647.320000 2846.220000 648.420000 2846.700000 ;
+ RECT 643.190000 2846.220000 644.190000 2846.700000 ;
+ RECT 647.320000 2840.780000 648.420000 2841.260000 ;
+ RECT 643.190000 2840.780000 644.190000 2841.260000 ;
+ RECT 647.320000 2835.340000 648.420000 2835.820000 ;
+ RECT 643.190000 2835.340000 644.190000 2835.820000 ;
+ RECT 647.320000 2824.460000 648.420000 2824.940000 ;
+ RECT 643.190000 2824.460000 644.190000 2824.940000 ;
+ RECT 643.190000 2829.900000 644.190000 2830.380000 ;
+ RECT 647.320000 2829.900000 648.420000 2830.380000 ;
+ RECT 647.320000 2819.020000 648.420000 2819.500000 ;
+ RECT 643.190000 2819.020000 644.190000 2819.500000 ;
+ RECT 647.320000 2813.580000 648.420000 2814.060000 ;
+ RECT 643.190000 2813.580000 644.190000 2814.060000 ;
+ RECT 647.320000 2808.140000 648.420000 2808.620000 ;
+ RECT 643.190000 2808.140000 644.190000 2808.620000 ;
+ RECT 647.320000 2802.700000 648.420000 2803.180000 ;
+ RECT 643.190000 2802.700000 644.190000 2803.180000 ;
+ RECT 737.320000 2797.260000 738.420000 2797.740000 ;
+ RECT 737.320000 2791.820000 738.420000 2792.300000 ;
+ RECT 737.320000 2786.380000 738.420000 2786.860000 ;
+ RECT 737.320000 2780.940000 738.420000 2781.420000 ;
+ RECT 737.320000 2775.500000 738.420000 2775.980000 ;
+ RECT 692.320000 2797.260000 693.420000 2797.740000 ;
+ RECT 692.320000 2791.820000 693.420000 2792.300000 ;
+ RECT 692.320000 2786.380000 693.420000 2786.860000 ;
+ RECT 692.320000 2780.940000 693.420000 2781.420000 ;
+ RECT 692.320000 2775.500000 693.420000 2775.980000 ;
+ RECT 737.320000 2753.740000 738.420000 2754.220000 ;
+ RECT 737.320000 2759.180000 738.420000 2759.660000 ;
+ RECT 737.320000 2764.620000 738.420000 2765.100000 ;
+ RECT 737.320000 2770.060000 738.420000 2770.540000 ;
+ RECT 692.320000 2753.740000 693.420000 2754.220000 ;
+ RECT 692.320000 2759.180000 693.420000 2759.660000 ;
+ RECT 692.320000 2764.620000 693.420000 2765.100000 ;
+ RECT 692.320000 2770.060000 693.420000 2770.540000 ;
+ RECT 647.320000 2797.260000 648.420000 2797.740000 ;
+ RECT 643.190000 2797.260000 644.190000 2797.740000 ;
+ RECT 647.320000 2791.820000 648.420000 2792.300000 ;
+ RECT 643.190000 2791.820000 644.190000 2792.300000 ;
+ RECT 647.320000 2780.940000 648.420000 2781.420000 ;
+ RECT 643.190000 2780.940000 644.190000 2781.420000 ;
+ RECT 647.320000 2775.500000 648.420000 2775.980000 ;
+ RECT 643.190000 2775.500000 644.190000 2775.980000 ;
+ RECT 647.320000 2786.380000 648.420000 2786.860000 ;
+ RECT 643.190000 2786.380000 644.190000 2786.860000 ;
+ RECT 647.320000 2770.060000 648.420000 2770.540000 ;
+ RECT 643.190000 2770.060000 644.190000 2770.540000 ;
+ RECT 647.320000 2764.620000 648.420000 2765.100000 ;
+ RECT 643.190000 2764.620000 644.190000 2765.100000 ;
+ RECT 647.320000 2759.180000 648.420000 2759.660000 ;
+ RECT 647.320000 2753.740000 648.420000 2754.220000 ;
+ RECT 643.190000 2759.180000 644.190000 2759.660000 ;
+ RECT 643.190000 2753.740000 644.190000 2754.220000 ;
+ RECT 640.360000 2944.100000 840.460000 2945.100000 ;
+ RECT 640.360000 2751.730000 840.460000 2752.730000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 2748.880000 644.190000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 2948.140000 644.190000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 2748.880000 837.630000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 2948.140000 837.630000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2751.730000 641.360000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2751.730000 840.460000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2944.100000 641.360000 2945.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2944.100000 840.460000 2945.100000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 2551.470000 828.420000 2744.840000 ;
+ RECT 782.320000 2551.470000 783.420000 2744.840000 ;
+ RECT 836.630000 2548.620000 837.630000 2748.880000 ;
+ RECT 737.320000 2551.470000 738.420000 2744.840000 ;
+ RECT 692.320000 2551.470000 693.420000 2744.840000 ;
+ RECT 647.320000 2551.470000 648.420000 2744.840000 ;
+ RECT 643.190000 2548.620000 644.190000 2748.880000 ;
+ LAYER met3 ;
+ RECT 827.320000 2738.440000 828.420000 2738.920000 ;
+ RECT 836.630000 2738.440000 837.630000 2738.920000 ;
+ RECT 836.630000 2727.560000 837.630000 2728.040000 ;
+ RECT 836.630000 2733.000000 837.630000 2733.480000 ;
+ RECT 827.320000 2733.000000 828.420000 2733.480000 ;
+ RECT 827.320000 2727.560000 828.420000 2728.040000 ;
+ RECT 827.320000 2722.120000 828.420000 2722.600000 ;
+ RECT 827.320000 2716.680000 828.420000 2717.160000 ;
+ RECT 836.630000 2722.120000 837.630000 2722.600000 ;
+ RECT 836.630000 2716.680000 837.630000 2717.160000 ;
+ RECT 827.320000 2700.360000 828.420000 2700.840000 ;
+ RECT 827.320000 2705.800000 828.420000 2706.280000 ;
+ RECT 836.630000 2705.800000 837.630000 2706.280000 ;
+ RECT 836.630000 2700.360000 837.630000 2700.840000 ;
+ RECT 827.320000 2711.240000 828.420000 2711.720000 ;
+ RECT 836.630000 2711.240000 837.630000 2711.720000 ;
+ RECT 782.320000 2738.440000 783.420000 2738.920000 ;
+ RECT 782.320000 2733.000000 783.420000 2733.480000 ;
+ RECT 782.320000 2727.560000 783.420000 2728.040000 ;
+ RECT 782.320000 2722.120000 783.420000 2722.600000 ;
+ RECT 782.320000 2700.360000 783.420000 2700.840000 ;
+ RECT 782.320000 2705.800000 783.420000 2706.280000 ;
+ RECT 782.320000 2711.240000 783.420000 2711.720000 ;
+ RECT 782.320000 2716.680000 783.420000 2717.160000 ;
+ RECT 836.630000 2689.480000 837.630000 2689.960000 ;
+ RECT 836.630000 2694.920000 837.630000 2695.400000 ;
+ RECT 827.320000 2694.920000 828.420000 2695.400000 ;
+ RECT 827.320000 2689.480000 828.420000 2689.960000 ;
+ RECT 827.320000 2684.040000 828.420000 2684.520000 ;
+ RECT 827.320000 2678.600000 828.420000 2679.080000 ;
+ RECT 836.630000 2684.040000 837.630000 2684.520000 ;
+ RECT 836.630000 2678.600000 837.630000 2679.080000 ;
+ RECT 836.630000 2662.280000 837.630000 2662.760000 ;
+ RECT 836.630000 2667.720000 837.630000 2668.200000 ;
+ RECT 836.630000 2673.160000 837.630000 2673.640000 ;
+ RECT 827.320000 2667.720000 828.420000 2668.200000 ;
+ RECT 827.320000 2662.280000 828.420000 2662.760000 ;
+ RECT 827.320000 2673.160000 828.420000 2673.640000 ;
+ RECT 827.320000 2656.840000 828.420000 2657.320000 ;
+ RECT 827.320000 2651.400000 828.420000 2651.880000 ;
+ RECT 836.630000 2656.840000 837.630000 2657.320000 ;
+ RECT 836.630000 2651.400000 837.630000 2651.880000 ;
+ RECT 782.320000 2694.920000 783.420000 2695.400000 ;
+ RECT 782.320000 2689.480000 783.420000 2689.960000 ;
+ RECT 782.320000 2684.040000 783.420000 2684.520000 ;
+ RECT 782.320000 2678.600000 783.420000 2679.080000 ;
+ RECT 782.320000 2667.720000 783.420000 2668.200000 ;
+ RECT 782.320000 2662.280000 783.420000 2662.760000 ;
+ RECT 782.320000 2656.840000 783.420000 2657.320000 ;
+ RECT 782.320000 2651.400000 783.420000 2651.880000 ;
+ RECT 782.320000 2673.160000 783.420000 2673.640000 ;
+ RECT 737.320000 2738.440000 738.420000 2738.920000 ;
+ RECT 737.320000 2733.000000 738.420000 2733.480000 ;
+ RECT 737.320000 2727.560000 738.420000 2728.040000 ;
+ RECT 692.320000 2738.440000 693.420000 2738.920000 ;
+ RECT 692.320000 2733.000000 693.420000 2733.480000 ;
+ RECT 692.320000 2727.560000 693.420000 2728.040000 ;
+ RECT 737.320000 2711.240000 738.420000 2711.720000 ;
+ RECT 737.320000 2705.800000 738.420000 2706.280000 ;
+ RECT 737.320000 2700.360000 738.420000 2700.840000 ;
+ RECT 737.320000 2716.680000 738.420000 2717.160000 ;
+ RECT 737.320000 2722.120000 738.420000 2722.600000 ;
+ RECT 692.320000 2722.120000 693.420000 2722.600000 ;
+ RECT 692.320000 2711.240000 693.420000 2711.720000 ;
+ RECT 692.320000 2705.800000 693.420000 2706.280000 ;
+ RECT 692.320000 2700.360000 693.420000 2700.840000 ;
+ RECT 692.320000 2716.680000 693.420000 2717.160000 ;
+ RECT 647.320000 2738.440000 648.420000 2738.920000 ;
+ RECT 643.190000 2738.440000 644.190000 2738.920000 ;
+ RECT 643.190000 2733.000000 644.190000 2733.480000 ;
+ RECT 647.320000 2733.000000 648.420000 2733.480000 ;
+ RECT 647.320000 2727.560000 648.420000 2728.040000 ;
+ RECT 643.190000 2727.560000 644.190000 2728.040000 ;
+ RECT 647.320000 2722.120000 648.420000 2722.600000 ;
+ RECT 643.190000 2722.120000 644.190000 2722.600000 ;
+ RECT 647.320000 2716.680000 648.420000 2717.160000 ;
+ RECT 643.190000 2716.680000 644.190000 2717.160000 ;
+ RECT 647.320000 2705.800000 648.420000 2706.280000 ;
+ RECT 643.190000 2705.800000 644.190000 2706.280000 ;
+ RECT 647.320000 2700.360000 648.420000 2700.840000 ;
+ RECT 643.190000 2700.360000 644.190000 2700.840000 ;
+ RECT 647.320000 2711.240000 648.420000 2711.720000 ;
+ RECT 643.190000 2711.240000 644.190000 2711.720000 ;
+ RECT 737.320000 2694.920000 738.420000 2695.400000 ;
+ RECT 737.320000 2689.480000 738.420000 2689.960000 ;
+ RECT 737.320000 2684.040000 738.420000 2684.520000 ;
+ RECT 737.320000 2678.600000 738.420000 2679.080000 ;
+ RECT 692.320000 2694.920000 693.420000 2695.400000 ;
+ RECT 692.320000 2689.480000 693.420000 2689.960000 ;
+ RECT 692.320000 2684.040000 693.420000 2684.520000 ;
+ RECT 692.320000 2678.600000 693.420000 2679.080000 ;
+ RECT 737.320000 2667.720000 738.420000 2668.200000 ;
+ RECT 737.320000 2651.400000 738.420000 2651.880000 ;
+ RECT 737.320000 2656.840000 738.420000 2657.320000 ;
+ RECT 737.320000 2662.280000 738.420000 2662.760000 ;
+ RECT 737.320000 2673.160000 738.420000 2673.640000 ;
+ RECT 692.320000 2651.400000 693.420000 2651.880000 ;
+ RECT 692.320000 2656.840000 693.420000 2657.320000 ;
+ RECT 692.320000 2662.280000 693.420000 2662.760000 ;
+ RECT 692.320000 2667.720000 693.420000 2668.200000 ;
+ RECT 692.320000 2673.160000 693.420000 2673.640000 ;
+ RECT 647.320000 2694.920000 648.420000 2695.400000 ;
+ RECT 643.190000 2694.920000 644.190000 2695.400000 ;
+ RECT 647.320000 2689.480000 648.420000 2689.960000 ;
+ RECT 643.190000 2689.480000 644.190000 2689.960000 ;
+ RECT 647.320000 2684.040000 648.420000 2684.520000 ;
+ RECT 643.190000 2684.040000 644.190000 2684.520000 ;
+ RECT 647.320000 2678.600000 648.420000 2679.080000 ;
+ RECT 643.190000 2678.600000 644.190000 2679.080000 ;
+ RECT 647.320000 2673.160000 648.420000 2673.640000 ;
+ RECT 647.320000 2667.720000 648.420000 2668.200000 ;
+ RECT 643.190000 2673.160000 644.190000 2673.640000 ;
+ RECT 643.190000 2667.720000 644.190000 2668.200000 ;
+ RECT 647.320000 2662.280000 648.420000 2662.760000 ;
+ RECT 643.190000 2662.280000 644.190000 2662.760000 ;
+ RECT 647.320000 2656.840000 648.420000 2657.320000 ;
+ RECT 643.190000 2656.840000 644.190000 2657.320000 ;
+ RECT 647.320000 2651.400000 648.420000 2651.880000 ;
+ RECT 643.190000 2651.400000 644.190000 2651.880000 ;
+ RECT 827.320000 2645.960000 828.420000 2646.440000 ;
+ RECT 827.320000 2640.520000 828.420000 2641.000000 ;
+ RECT 836.630000 2645.960000 837.630000 2646.440000 ;
+ RECT 836.630000 2640.520000 837.630000 2641.000000 ;
+ RECT 836.630000 2624.200000 837.630000 2624.680000 ;
+ RECT 836.630000 2629.640000 837.630000 2630.120000 ;
+ RECT 836.630000 2635.080000 837.630000 2635.560000 ;
+ RECT 827.320000 2635.080000 828.420000 2635.560000 ;
+ RECT 827.320000 2629.640000 828.420000 2630.120000 ;
+ RECT 827.320000 2624.200000 828.420000 2624.680000 ;
+ RECT 827.320000 2613.320000 828.420000 2613.800000 ;
+ RECT 827.320000 2618.760000 828.420000 2619.240000 ;
+ RECT 836.630000 2618.760000 837.630000 2619.240000 ;
+ RECT 836.630000 2613.320000 837.630000 2613.800000 ;
+ RECT 836.630000 2602.440000 837.630000 2602.920000 ;
+ RECT 836.630000 2607.880000 837.630000 2608.360000 ;
+ RECT 827.320000 2602.440000 828.420000 2602.920000 ;
+ RECT 827.320000 2607.880000 828.420000 2608.360000 ;
+ RECT 782.320000 2645.960000 783.420000 2646.440000 ;
+ RECT 782.320000 2640.520000 783.420000 2641.000000 ;
+ RECT 782.320000 2635.080000 783.420000 2635.560000 ;
+ RECT 782.320000 2629.640000 783.420000 2630.120000 ;
+ RECT 782.320000 2624.200000 783.420000 2624.680000 ;
+ RECT 782.320000 2602.440000 783.420000 2602.920000 ;
+ RECT 782.320000 2607.880000 783.420000 2608.360000 ;
+ RECT 782.320000 2613.320000 783.420000 2613.800000 ;
+ RECT 782.320000 2618.760000 783.420000 2619.240000 ;
+ RECT 827.320000 2597.000000 828.420000 2597.480000 ;
+ RECT 827.320000 2591.560000 828.420000 2592.040000 ;
+ RECT 836.630000 2597.000000 837.630000 2597.480000 ;
+ RECT 836.630000 2591.560000 837.630000 2592.040000 ;
+ RECT 827.320000 2580.680000 828.420000 2581.160000 ;
+ RECT 827.320000 2575.240000 828.420000 2575.720000 ;
+ RECT 836.630000 2580.680000 837.630000 2581.160000 ;
+ RECT 836.630000 2575.240000 837.630000 2575.720000 ;
+ RECT 827.320000 2586.120000 828.420000 2586.600000 ;
+ RECT 836.630000 2586.120000 837.630000 2586.600000 ;
+ RECT 836.630000 2564.360000 837.630000 2564.840000 ;
+ RECT 836.630000 2569.800000 837.630000 2570.280000 ;
+ RECT 827.320000 2569.800000 828.420000 2570.280000 ;
+ RECT 827.320000 2564.360000 828.420000 2564.840000 ;
+ RECT 827.320000 2558.920000 828.420000 2559.400000 ;
+ RECT 827.320000 2553.480000 828.420000 2553.960000 ;
+ RECT 836.630000 2558.920000 837.630000 2559.400000 ;
+ RECT 836.630000 2553.480000 837.630000 2553.960000 ;
+ RECT 782.320000 2597.000000 783.420000 2597.480000 ;
+ RECT 782.320000 2591.560000 783.420000 2592.040000 ;
+ RECT 782.320000 2586.120000 783.420000 2586.600000 ;
+ RECT 782.320000 2580.680000 783.420000 2581.160000 ;
+ RECT 782.320000 2575.240000 783.420000 2575.720000 ;
+ RECT 782.320000 2569.800000 783.420000 2570.280000 ;
+ RECT 782.320000 2564.360000 783.420000 2564.840000 ;
+ RECT 782.320000 2558.920000 783.420000 2559.400000 ;
+ RECT 782.320000 2553.480000 783.420000 2553.960000 ;
+ RECT 737.320000 2645.960000 738.420000 2646.440000 ;
+ RECT 737.320000 2640.520000 738.420000 2641.000000 ;
+ RECT 737.320000 2635.080000 738.420000 2635.560000 ;
+ RECT 737.320000 2629.640000 738.420000 2630.120000 ;
+ RECT 737.320000 2624.200000 738.420000 2624.680000 ;
+ RECT 692.320000 2645.960000 693.420000 2646.440000 ;
+ RECT 692.320000 2640.520000 693.420000 2641.000000 ;
+ RECT 692.320000 2635.080000 693.420000 2635.560000 ;
+ RECT 692.320000 2629.640000 693.420000 2630.120000 ;
+ RECT 692.320000 2624.200000 693.420000 2624.680000 ;
+ RECT 737.320000 2618.760000 738.420000 2619.240000 ;
+ RECT 737.320000 2613.320000 738.420000 2613.800000 ;
+ RECT 737.320000 2607.880000 738.420000 2608.360000 ;
+ RECT 737.320000 2602.440000 738.420000 2602.920000 ;
+ RECT 692.320000 2613.320000 693.420000 2613.800000 ;
+ RECT 692.320000 2607.880000 693.420000 2608.360000 ;
+ RECT 692.320000 2602.440000 693.420000 2602.920000 ;
+ RECT 692.320000 2618.760000 693.420000 2619.240000 ;
+ RECT 647.320000 2645.960000 648.420000 2646.440000 ;
+ RECT 643.190000 2645.960000 644.190000 2646.440000 ;
+ RECT 647.320000 2640.520000 648.420000 2641.000000 ;
+ RECT 643.190000 2640.520000 644.190000 2641.000000 ;
+ RECT 647.320000 2635.080000 648.420000 2635.560000 ;
+ RECT 643.190000 2635.080000 644.190000 2635.560000 ;
+ RECT 647.320000 2624.200000 648.420000 2624.680000 ;
+ RECT 643.190000 2624.200000 644.190000 2624.680000 ;
+ RECT 643.190000 2629.640000 644.190000 2630.120000 ;
+ RECT 647.320000 2629.640000 648.420000 2630.120000 ;
+ RECT 647.320000 2618.760000 648.420000 2619.240000 ;
+ RECT 643.190000 2618.760000 644.190000 2619.240000 ;
+ RECT 647.320000 2613.320000 648.420000 2613.800000 ;
+ RECT 643.190000 2613.320000 644.190000 2613.800000 ;
+ RECT 647.320000 2607.880000 648.420000 2608.360000 ;
+ RECT 643.190000 2607.880000 644.190000 2608.360000 ;
+ RECT 647.320000 2602.440000 648.420000 2602.920000 ;
+ RECT 643.190000 2602.440000 644.190000 2602.920000 ;
+ RECT 737.320000 2597.000000 738.420000 2597.480000 ;
+ RECT 737.320000 2591.560000 738.420000 2592.040000 ;
+ RECT 737.320000 2586.120000 738.420000 2586.600000 ;
+ RECT 737.320000 2580.680000 738.420000 2581.160000 ;
+ RECT 737.320000 2575.240000 738.420000 2575.720000 ;
+ RECT 692.320000 2597.000000 693.420000 2597.480000 ;
+ RECT 692.320000 2591.560000 693.420000 2592.040000 ;
+ RECT 692.320000 2586.120000 693.420000 2586.600000 ;
+ RECT 692.320000 2580.680000 693.420000 2581.160000 ;
+ RECT 692.320000 2575.240000 693.420000 2575.720000 ;
+ RECT 737.320000 2553.480000 738.420000 2553.960000 ;
+ RECT 737.320000 2558.920000 738.420000 2559.400000 ;
+ RECT 737.320000 2564.360000 738.420000 2564.840000 ;
+ RECT 737.320000 2569.800000 738.420000 2570.280000 ;
+ RECT 692.320000 2553.480000 693.420000 2553.960000 ;
+ RECT 692.320000 2558.920000 693.420000 2559.400000 ;
+ RECT 692.320000 2564.360000 693.420000 2564.840000 ;
+ RECT 692.320000 2569.800000 693.420000 2570.280000 ;
+ RECT 647.320000 2597.000000 648.420000 2597.480000 ;
+ RECT 643.190000 2597.000000 644.190000 2597.480000 ;
+ RECT 647.320000 2591.560000 648.420000 2592.040000 ;
+ RECT 643.190000 2591.560000 644.190000 2592.040000 ;
+ RECT 647.320000 2580.680000 648.420000 2581.160000 ;
+ RECT 643.190000 2580.680000 644.190000 2581.160000 ;
+ RECT 647.320000 2575.240000 648.420000 2575.720000 ;
+ RECT 643.190000 2575.240000 644.190000 2575.720000 ;
+ RECT 647.320000 2586.120000 648.420000 2586.600000 ;
+ RECT 643.190000 2586.120000 644.190000 2586.600000 ;
+ RECT 647.320000 2569.800000 648.420000 2570.280000 ;
+ RECT 643.190000 2569.800000 644.190000 2570.280000 ;
+ RECT 647.320000 2564.360000 648.420000 2564.840000 ;
+ RECT 643.190000 2564.360000 644.190000 2564.840000 ;
+ RECT 647.320000 2558.920000 648.420000 2559.400000 ;
+ RECT 647.320000 2553.480000 648.420000 2553.960000 ;
+ RECT 643.190000 2558.920000 644.190000 2559.400000 ;
+ RECT 643.190000 2553.480000 644.190000 2553.960000 ;
+ RECT 640.360000 2743.840000 840.460000 2744.840000 ;
+ RECT 640.360000 2551.470000 840.460000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 2548.620000 644.190000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 2747.880000 644.190000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 2548.620000 837.630000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 2747.880000 837.630000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2551.470000 641.360000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2551.470000 840.460000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2743.840000 641.360000 2744.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2743.840000 840.460000 2744.840000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 2351.210000 828.420000 2544.580000 ;
+ RECT 782.320000 2351.210000 783.420000 2544.580000 ;
+ RECT 836.630000 2348.360000 837.630000 2548.620000 ;
+ RECT 737.320000 2351.210000 738.420000 2544.580000 ;
+ RECT 692.320000 2351.210000 693.420000 2544.580000 ;
+ RECT 647.320000 2351.210000 648.420000 2544.580000 ;
+ RECT 643.190000 2348.360000 644.190000 2548.620000 ;
+ LAYER met3 ;
+ RECT 827.320000 2538.180000 828.420000 2538.660000 ;
+ RECT 836.630000 2538.180000 837.630000 2538.660000 ;
+ RECT 836.630000 2527.300000 837.630000 2527.780000 ;
+ RECT 836.630000 2532.740000 837.630000 2533.220000 ;
+ RECT 827.320000 2532.740000 828.420000 2533.220000 ;
+ RECT 827.320000 2527.300000 828.420000 2527.780000 ;
+ RECT 827.320000 2521.860000 828.420000 2522.340000 ;
+ RECT 827.320000 2516.420000 828.420000 2516.900000 ;
+ RECT 836.630000 2521.860000 837.630000 2522.340000 ;
+ RECT 836.630000 2516.420000 837.630000 2516.900000 ;
+ RECT 827.320000 2500.100000 828.420000 2500.580000 ;
+ RECT 827.320000 2505.540000 828.420000 2506.020000 ;
+ RECT 836.630000 2505.540000 837.630000 2506.020000 ;
+ RECT 836.630000 2500.100000 837.630000 2500.580000 ;
+ RECT 827.320000 2510.980000 828.420000 2511.460000 ;
+ RECT 836.630000 2510.980000 837.630000 2511.460000 ;
+ RECT 782.320000 2538.180000 783.420000 2538.660000 ;
+ RECT 782.320000 2532.740000 783.420000 2533.220000 ;
+ RECT 782.320000 2527.300000 783.420000 2527.780000 ;
+ RECT 782.320000 2521.860000 783.420000 2522.340000 ;
+ RECT 782.320000 2500.100000 783.420000 2500.580000 ;
+ RECT 782.320000 2505.540000 783.420000 2506.020000 ;
+ RECT 782.320000 2510.980000 783.420000 2511.460000 ;
+ RECT 782.320000 2516.420000 783.420000 2516.900000 ;
+ RECT 836.630000 2489.220000 837.630000 2489.700000 ;
+ RECT 836.630000 2494.660000 837.630000 2495.140000 ;
+ RECT 827.320000 2494.660000 828.420000 2495.140000 ;
+ RECT 827.320000 2489.220000 828.420000 2489.700000 ;
+ RECT 827.320000 2483.780000 828.420000 2484.260000 ;
+ RECT 827.320000 2478.340000 828.420000 2478.820000 ;
+ RECT 836.630000 2483.780000 837.630000 2484.260000 ;
+ RECT 836.630000 2478.340000 837.630000 2478.820000 ;
+ RECT 836.630000 2462.020000 837.630000 2462.500000 ;
+ RECT 836.630000 2467.460000 837.630000 2467.940000 ;
+ RECT 836.630000 2472.900000 837.630000 2473.380000 ;
+ RECT 827.320000 2467.460000 828.420000 2467.940000 ;
+ RECT 827.320000 2462.020000 828.420000 2462.500000 ;
+ RECT 827.320000 2472.900000 828.420000 2473.380000 ;
+ RECT 827.320000 2456.580000 828.420000 2457.060000 ;
+ RECT 827.320000 2451.140000 828.420000 2451.620000 ;
+ RECT 836.630000 2456.580000 837.630000 2457.060000 ;
+ RECT 836.630000 2451.140000 837.630000 2451.620000 ;
+ RECT 782.320000 2494.660000 783.420000 2495.140000 ;
+ RECT 782.320000 2489.220000 783.420000 2489.700000 ;
+ RECT 782.320000 2483.780000 783.420000 2484.260000 ;
+ RECT 782.320000 2478.340000 783.420000 2478.820000 ;
+ RECT 782.320000 2467.460000 783.420000 2467.940000 ;
+ RECT 782.320000 2462.020000 783.420000 2462.500000 ;
+ RECT 782.320000 2456.580000 783.420000 2457.060000 ;
+ RECT 782.320000 2451.140000 783.420000 2451.620000 ;
+ RECT 782.320000 2472.900000 783.420000 2473.380000 ;
+ RECT 737.320000 2538.180000 738.420000 2538.660000 ;
+ RECT 737.320000 2532.740000 738.420000 2533.220000 ;
+ RECT 737.320000 2527.300000 738.420000 2527.780000 ;
+ RECT 692.320000 2538.180000 693.420000 2538.660000 ;
+ RECT 692.320000 2532.740000 693.420000 2533.220000 ;
+ RECT 692.320000 2527.300000 693.420000 2527.780000 ;
+ RECT 737.320000 2510.980000 738.420000 2511.460000 ;
+ RECT 737.320000 2505.540000 738.420000 2506.020000 ;
+ RECT 737.320000 2500.100000 738.420000 2500.580000 ;
+ RECT 737.320000 2516.420000 738.420000 2516.900000 ;
+ RECT 737.320000 2521.860000 738.420000 2522.340000 ;
+ RECT 692.320000 2521.860000 693.420000 2522.340000 ;
+ RECT 692.320000 2510.980000 693.420000 2511.460000 ;
+ RECT 692.320000 2505.540000 693.420000 2506.020000 ;
+ RECT 692.320000 2500.100000 693.420000 2500.580000 ;
+ RECT 692.320000 2516.420000 693.420000 2516.900000 ;
+ RECT 647.320000 2538.180000 648.420000 2538.660000 ;
+ RECT 643.190000 2538.180000 644.190000 2538.660000 ;
+ RECT 643.190000 2532.740000 644.190000 2533.220000 ;
+ RECT 647.320000 2532.740000 648.420000 2533.220000 ;
+ RECT 647.320000 2527.300000 648.420000 2527.780000 ;
+ RECT 643.190000 2527.300000 644.190000 2527.780000 ;
+ RECT 647.320000 2521.860000 648.420000 2522.340000 ;
+ RECT 643.190000 2521.860000 644.190000 2522.340000 ;
+ RECT 647.320000 2516.420000 648.420000 2516.900000 ;
+ RECT 643.190000 2516.420000 644.190000 2516.900000 ;
+ RECT 647.320000 2505.540000 648.420000 2506.020000 ;
+ RECT 643.190000 2505.540000 644.190000 2506.020000 ;
+ RECT 647.320000 2500.100000 648.420000 2500.580000 ;
+ RECT 643.190000 2500.100000 644.190000 2500.580000 ;
+ RECT 647.320000 2510.980000 648.420000 2511.460000 ;
+ RECT 643.190000 2510.980000 644.190000 2511.460000 ;
+ RECT 737.320000 2494.660000 738.420000 2495.140000 ;
+ RECT 737.320000 2489.220000 738.420000 2489.700000 ;
+ RECT 737.320000 2483.780000 738.420000 2484.260000 ;
+ RECT 737.320000 2478.340000 738.420000 2478.820000 ;
+ RECT 692.320000 2494.660000 693.420000 2495.140000 ;
+ RECT 692.320000 2489.220000 693.420000 2489.700000 ;
+ RECT 692.320000 2483.780000 693.420000 2484.260000 ;
+ RECT 692.320000 2478.340000 693.420000 2478.820000 ;
+ RECT 737.320000 2467.460000 738.420000 2467.940000 ;
+ RECT 737.320000 2451.140000 738.420000 2451.620000 ;
+ RECT 737.320000 2456.580000 738.420000 2457.060000 ;
+ RECT 737.320000 2462.020000 738.420000 2462.500000 ;
+ RECT 737.320000 2472.900000 738.420000 2473.380000 ;
+ RECT 692.320000 2451.140000 693.420000 2451.620000 ;
+ RECT 692.320000 2456.580000 693.420000 2457.060000 ;
+ RECT 692.320000 2462.020000 693.420000 2462.500000 ;
+ RECT 692.320000 2467.460000 693.420000 2467.940000 ;
+ RECT 692.320000 2472.900000 693.420000 2473.380000 ;
+ RECT 647.320000 2494.660000 648.420000 2495.140000 ;
+ RECT 643.190000 2494.660000 644.190000 2495.140000 ;
+ RECT 647.320000 2489.220000 648.420000 2489.700000 ;
+ RECT 643.190000 2489.220000 644.190000 2489.700000 ;
+ RECT 647.320000 2483.780000 648.420000 2484.260000 ;
+ RECT 643.190000 2483.780000 644.190000 2484.260000 ;
+ RECT 647.320000 2478.340000 648.420000 2478.820000 ;
+ RECT 643.190000 2478.340000 644.190000 2478.820000 ;
+ RECT 647.320000 2472.900000 648.420000 2473.380000 ;
+ RECT 647.320000 2467.460000 648.420000 2467.940000 ;
+ RECT 643.190000 2472.900000 644.190000 2473.380000 ;
+ RECT 643.190000 2467.460000 644.190000 2467.940000 ;
+ RECT 647.320000 2462.020000 648.420000 2462.500000 ;
+ RECT 643.190000 2462.020000 644.190000 2462.500000 ;
+ RECT 647.320000 2456.580000 648.420000 2457.060000 ;
+ RECT 643.190000 2456.580000 644.190000 2457.060000 ;
+ RECT 647.320000 2451.140000 648.420000 2451.620000 ;
+ RECT 643.190000 2451.140000 644.190000 2451.620000 ;
+ RECT 827.320000 2445.700000 828.420000 2446.180000 ;
+ RECT 827.320000 2440.260000 828.420000 2440.740000 ;
+ RECT 836.630000 2445.700000 837.630000 2446.180000 ;
+ RECT 836.630000 2440.260000 837.630000 2440.740000 ;
+ RECT 836.630000 2423.940000 837.630000 2424.420000 ;
+ RECT 836.630000 2429.380000 837.630000 2429.860000 ;
+ RECT 836.630000 2434.820000 837.630000 2435.300000 ;
+ RECT 827.320000 2434.820000 828.420000 2435.300000 ;
+ RECT 827.320000 2429.380000 828.420000 2429.860000 ;
+ RECT 827.320000 2423.940000 828.420000 2424.420000 ;
+ RECT 827.320000 2413.060000 828.420000 2413.540000 ;
+ RECT 827.320000 2418.500000 828.420000 2418.980000 ;
+ RECT 836.630000 2418.500000 837.630000 2418.980000 ;
+ RECT 836.630000 2413.060000 837.630000 2413.540000 ;
+ RECT 836.630000 2402.180000 837.630000 2402.660000 ;
+ RECT 836.630000 2407.620000 837.630000 2408.100000 ;
+ RECT 827.320000 2402.180000 828.420000 2402.660000 ;
+ RECT 827.320000 2407.620000 828.420000 2408.100000 ;
+ RECT 782.320000 2445.700000 783.420000 2446.180000 ;
+ RECT 782.320000 2440.260000 783.420000 2440.740000 ;
+ RECT 782.320000 2434.820000 783.420000 2435.300000 ;
+ RECT 782.320000 2429.380000 783.420000 2429.860000 ;
+ RECT 782.320000 2423.940000 783.420000 2424.420000 ;
+ RECT 782.320000 2402.180000 783.420000 2402.660000 ;
+ RECT 782.320000 2407.620000 783.420000 2408.100000 ;
+ RECT 782.320000 2413.060000 783.420000 2413.540000 ;
+ RECT 782.320000 2418.500000 783.420000 2418.980000 ;
+ RECT 827.320000 2396.740000 828.420000 2397.220000 ;
+ RECT 827.320000 2391.300000 828.420000 2391.780000 ;
+ RECT 836.630000 2396.740000 837.630000 2397.220000 ;
+ RECT 836.630000 2391.300000 837.630000 2391.780000 ;
+ RECT 827.320000 2380.420000 828.420000 2380.900000 ;
+ RECT 827.320000 2374.980000 828.420000 2375.460000 ;
+ RECT 836.630000 2380.420000 837.630000 2380.900000 ;
+ RECT 836.630000 2374.980000 837.630000 2375.460000 ;
+ RECT 827.320000 2385.860000 828.420000 2386.340000 ;
+ RECT 836.630000 2385.860000 837.630000 2386.340000 ;
+ RECT 836.630000 2364.100000 837.630000 2364.580000 ;
+ RECT 836.630000 2369.540000 837.630000 2370.020000 ;
+ RECT 827.320000 2369.540000 828.420000 2370.020000 ;
+ RECT 827.320000 2364.100000 828.420000 2364.580000 ;
+ RECT 827.320000 2358.660000 828.420000 2359.140000 ;
+ RECT 827.320000 2353.220000 828.420000 2353.700000 ;
+ RECT 836.630000 2358.660000 837.630000 2359.140000 ;
+ RECT 836.630000 2353.220000 837.630000 2353.700000 ;
+ RECT 782.320000 2396.740000 783.420000 2397.220000 ;
+ RECT 782.320000 2391.300000 783.420000 2391.780000 ;
+ RECT 782.320000 2385.860000 783.420000 2386.340000 ;
+ RECT 782.320000 2380.420000 783.420000 2380.900000 ;
+ RECT 782.320000 2374.980000 783.420000 2375.460000 ;
+ RECT 782.320000 2369.540000 783.420000 2370.020000 ;
+ RECT 782.320000 2364.100000 783.420000 2364.580000 ;
+ RECT 782.320000 2358.660000 783.420000 2359.140000 ;
+ RECT 782.320000 2353.220000 783.420000 2353.700000 ;
+ RECT 737.320000 2445.700000 738.420000 2446.180000 ;
+ RECT 737.320000 2440.260000 738.420000 2440.740000 ;
+ RECT 737.320000 2434.820000 738.420000 2435.300000 ;
+ RECT 737.320000 2429.380000 738.420000 2429.860000 ;
+ RECT 737.320000 2423.940000 738.420000 2424.420000 ;
+ RECT 692.320000 2445.700000 693.420000 2446.180000 ;
+ RECT 692.320000 2440.260000 693.420000 2440.740000 ;
+ RECT 692.320000 2434.820000 693.420000 2435.300000 ;
+ RECT 692.320000 2429.380000 693.420000 2429.860000 ;
+ RECT 692.320000 2423.940000 693.420000 2424.420000 ;
+ RECT 737.320000 2418.500000 738.420000 2418.980000 ;
+ RECT 737.320000 2413.060000 738.420000 2413.540000 ;
+ RECT 737.320000 2407.620000 738.420000 2408.100000 ;
+ RECT 737.320000 2402.180000 738.420000 2402.660000 ;
+ RECT 692.320000 2413.060000 693.420000 2413.540000 ;
+ RECT 692.320000 2407.620000 693.420000 2408.100000 ;
+ RECT 692.320000 2402.180000 693.420000 2402.660000 ;
+ RECT 692.320000 2418.500000 693.420000 2418.980000 ;
+ RECT 647.320000 2445.700000 648.420000 2446.180000 ;
+ RECT 643.190000 2445.700000 644.190000 2446.180000 ;
+ RECT 647.320000 2440.260000 648.420000 2440.740000 ;
+ RECT 643.190000 2440.260000 644.190000 2440.740000 ;
+ RECT 647.320000 2434.820000 648.420000 2435.300000 ;
+ RECT 643.190000 2434.820000 644.190000 2435.300000 ;
+ RECT 647.320000 2423.940000 648.420000 2424.420000 ;
+ RECT 643.190000 2423.940000 644.190000 2424.420000 ;
+ RECT 643.190000 2429.380000 644.190000 2429.860000 ;
+ RECT 647.320000 2429.380000 648.420000 2429.860000 ;
+ RECT 647.320000 2418.500000 648.420000 2418.980000 ;
+ RECT 643.190000 2418.500000 644.190000 2418.980000 ;
+ RECT 647.320000 2413.060000 648.420000 2413.540000 ;
+ RECT 643.190000 2413.060000 644.190000 2413.540000 ;
+ RECT 647.320000 2407.620000 648.420000 2408.100000 ;
+ RECT 643.190000 2407.620000 644.190000 2408.100000 ;
+ RECT 647.320000 2402.180000 648.420000 2402.660000 ;
+ RECT 643.190000 2402.180000 644.190000 2402.660000 ;
+ RECT 737.320000 2396.740000 738.420000 2397.220000 ;
+ RECT 737.320000 2391.300000 738.420000 2391.780000 ;
+ RECT 737.320000 2385.860000 738.420000 2386.340000 ;
+ RECT 737.320000 2380.420000 738.420000 2380.900000 ;
+ RECT 737.320000 2374.980000 738.420000 2375.460000 ;
+ RECT 692.320000 2396.740000 693.420000 2397.220000 ;
+ RECT 692.320000 2391.300000 693.420000 2391.780000 ;
+ RECT 692.320000 2385.860000 693.420000 2386.340000 ;
+ RECT 692.320000 2380.420000 693.420000 2380.900000 ;
+ RECT 692.320000 2374.980000 693.420000 2375.460000 ;
+ RECT 737.320000 2353.220000 738.420000 2353.700000 ;
+ RECT 737.320000 2358.660000 738.420000 2359.140000 ;
+ RECT 737.320000 2364.100000 738.420000 2364.580000 ;
+ RECT 737.320000 2369.540000 738.420000 2370.020000 ;
+ RECT 692.320000 2353.220000 693.420000 2353.700000 ;
+ RECT 692.320000 2358.660000 693.420000 2359.140000 ;
+ RECT 692.320000 2364.100000 693.420000 2364.580000 ;
+ RECT 692.320000 2369.540000 693.420000 2370.020000 ;
+ RECT 647.320000 2396.740000 648.420000 2397.220000 ;
+ RECT 643.190000 2396.740000 644.190000 2397.220000 ;
+ RECT 647.320000 2391.300000 648.420000 2391.780000 ;
+ RECT 643.190000 2391.300000 644.190000 2391.780000 ;
+ RECT 647.320000 2380.420000 648.420000 2380.900000 ;
+ RECT 643.190000 2380.420000 644.190000 2380.900000 ;
+ RECT 647.320000 2374.980000 648.420000 2375.460000 ;
+ RECT 643.190000 2374.980000 644.190000 2375.460000 ;
+ RECT 647.320000 2385.860000 648.420000 2386.340000 ;
+ RECT 643.190000 2385.860000 644.190000 2386.340000 ;
+ RECT 647.320000 2369.540000 648.420000 2370.020000 ;
+ RECT 643.190000 2369.540000 644.190000 2370.020000 ;
+ RECT 647.320000 2364.100000 648.420000 2364.580000 ;
+ RECT 643.190000 2364.100000 644.190000 2364.580000 ;
+ RECT 647.320000 2358.660000 648.420000 2359.140000 ;
+ RECT 647.320000 2353.220000 648.420000 2353.700000 ;
+ RECT 643.190000 2358.660000 644.190000 2359.140000 ;
+ RECT 643.190000 2353.220000 644.190000 2353.700000 ;
+ RECT 640.360000 2543.580000 840.460000 2544.580000 ;
+ RECT 640.360000 2351.210000 840.460000 2352.210000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 2348.360000 644.190000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 2547.620000 644.190000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 2348.360000 837.630000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 2547.620000 837.630000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2351.210000 641.360000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2351.210000 840.460000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2543.580000 641.360000 2544.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2543.580000 840.460000 2544.580000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 2150.950000 828.420000 2344.320000 ;
+ RECT 782.320000 2150.950000 783.420000 2344.320000 ;
+ RECT 836.630000 2148.100000 837.630000 2348.360000 ;
+ RECT 737.320000 2150.950000 738.420000 2344.320000 ;
+ RECT 692.320000 2150.950000 693.420000 2344.320000 ;
+ RECT 647.320000 2150.950000 648.420000 2344.320000 ;
+ RECT 643.190000 2148.100000 644.190000 2348.360000 ;
+ LAYER met3 ;
+ RECT 827.320000 2337.920000 828.420000 2338.400000 ;
+ RECT 836.630000 2337.920000 837.630000 2338.400000 ;
+ RECT 836.630000 2327.040000 837.630000 2327.520000 ;
+ RECT 836.630000 2332.480000 837.630000 2332.960000 ;
+ RECT 827.320000 2332.480000 828.420000 2332.960000 ;
+ RECT 827.320000 2327.040000 828.420000 2327.520000 ;
+ RECT 827.320000 2321.600000 828.420000 2322.080000 ;
+ RECT 827.320000 2316.160000 828.420000 2316.640000 ;
+ RECT 836.630000 2321.600000 837.630000 2322.080000 ;
+ RECT 836.630000 2316.160000 837.630000 2316.640000 ;
+ RECT 827.320000 2299.840000 828.420000 2300.320000 ;
+ RECT 827.320000 2305.280000 828.420000 2305.760000 ;
+ RECT 836.630000 2305.280000 837.630000 2305.760000 ;
+ RECT 836.630000 2299.840000 837.630000 2300.320000 ;
+ RECT 827.320000 2310.720000 828.420000 2311.200000 ;
+ RECT 836.630000 2310.720000 837.630000 2311.200000 ;
+ RECT 782.320000 2337.920000 783.420000 2338.400000 ;
+ RECT 782.320000 2332.480000 783.420000 2332.960000 ;
+ RECT 782.320000 2327.040000 783.420000 2327.520000 ;
+ RECT 782.320000 2321.600000 783.420000 2322.080000 ;
+ RECT 782.320000 2299.840000 783.420000 2300.320000 ;
+ RECT 782.320000 2305.280000 783.420000 2305.760000 ;
+ RECT 782.320000 2310.720000 783.420000 2311.200000 ;
+ RECT 782.320000 2316.160000 783.420000 2316.640000 ;
+ RECT 836.630000 2288.960000 837.630000 2289.440000 ;
+ RECT 836.630000 2294.400000 837.630000 2294.880000 ;
+ RECT 827.320000 2294.400000 828.420000 2294.880000 ;
+ RECT 827.320000 2288.960000 828.420000 2289.440000 ;
+ RECT 827.320000 2283.520000 828.420000 2284.000000 ;
+ RECT 827.320000 2278.080000 828.420000 2278.560000 ;
+ RECT 836.630000 2283.520000 837.630000 2284.000000 ;
+ RECT 836.630000 2278.080000 837.630000 2278.560000 ;
+ RECT 836.630000 2261.760000 837.630000 2262.240000 ;
+ RECT 836.630000 2267.200000 837.630000 2267.680000 ;
+ RECT 836.630000 2272.640000 837.630000 2273.120000 ;
+ RECT 827.320000 2267.200000 828.420000 2267.680000 ;
+ RECT 827.320000 2261.760000 828.420000 2262.240000 ;
+ RECT 827.320000 2272.640000 828.420000 2273.120000 ;
+ RECT 827.320000 2256.320000 828.420000 2256.800000 ;
+ RECT 827.320000 2250.880000 828.420000 2251.360000 ;
+ RECT 836.630000 2256.320000 837.630000 2256.800000 ;
+ RECT 836.630000 2250.880000 837.630000 2251.360000 ;
+ RECT 782.320000 2294.400000 783.420000 2294.880000 ;
+ RECT 782.320000 2288.960000 783.420000 2289.440000 ;
+ RECT 782.320000 2283.520000 783.420000 2284.000000 ;
+ RECT 782.320000 2278.080000 783.420000 2278.560000 ;
+ RECT 782.320000 2267.200000 783.420000 2267.680000 ;
+ RECT 782.320000 2261.760000 783.420000 2262.240000 ;
+ RECT 782.320000 2256.320000 783.420000 2256.800000 ;
+ RECT 782.320000 2250.880000 783.420000 2251.360000 ;
+ RECT 782.320000 2272.640000 783.420000 2273.120000 ;
+ RECT 737.320000 2337.920000 738.420000 2338.400000 ;
+ RECT 737.320000 2332.480000 738.420000 2332.960000 ;
+ RECT 737.320000 2327.040000 738.420000 2327.520000 ;
+ RECT 692.320000 2337.920000 693.420000 2338.400000 ;
+ RECT 692.320000 2332.480000 693.420000 2332.960000 ;
+ RECT 692.320000 2327.040000 693.420000 2327.520000 ;
+ RECT 737.320000 2310.720000 738.420000 2311.200000 ;
+ RECT 737.320000 2305.280000 738.420000 2305.760000 ;
+ RECT 737.320000 2299.840000 738.420000 2300.320000 ;
+ RECT 737.320000 2316.160000 738.420000 2316.640000 ;
+ RECT 737.320000 2321.600000 738.420000 2322.080000 ;
+ RECT 692.320000 2321.600000 693.420000 2322.080000 ;
+ RECT 692.320000 2310.720000 693.420000 2311.200000 ;
+ RECT 692.320000 2305.280000 693.420000 2305.760000 ;
+ RECT 692.320000 2299.840000 693.420000 2300.320000 ;
+ RECT 692.320000 2316.160000 693.420000 2316.640000 ;
+ RECT 647.320000 2337.920000 648.420000 2338.400000 ;
+ RECT 643.190000 2337.920000 644.190000 2338.400000 ;
+ RECT 643.190000 2332.480000 644.190000 2332.960000 ;
+ RECT 647.320000 2332.480000 648.420000 2332.960000 ;
+ RECT 647.320000 2327.040000 648.420000 2327.520000 ;
+ RECT 643.190000 2327.040000 644.190000 2327.520000 ;
+ RECT 647.320000 2321.600000 648.420000 2322.080000 ;
+ RECT 643.190000 2321.600000 644.190000 2322.080000 ;
+ RECT 647.320000 2316.160000 648.420000 2316.640000 ;
+ RECT 643.190000 2316.160000 644.190000 2316.640000 ;
+ RECT 647.320000 2305.280000 648.420000 2305.760000 ;
+ RECT 643.190000 2305.280000 644.190000 2305.760000 ;
+ RECT 647.320000 2299.840000 648.420000 2300.320000 ;
+ RECT 643.190000 2299.840000 644.190000 2300.320000 ;
+ RECT 647.320000 2310.720000 648.420000 2311.200000 ;
+ RECT 643.190000 2310.720000 644.190000 2311.200000 ;
+ RECT 737.320000 2294.400000 738.420000 2294.880000 ;
+ RECT 737.320000 2288.960000 738.420000 2289.440000 ;
+ RECT 737.320000 2283.520000 738.420000 2284.000000 ;
+ RECT 737.320000 2278.080000 738.420000 2278.560000 ;
+ RECT 692.320000 2294.400000 693.420000 2294.880000 ;
+ RECT 692.320000 2288.960000 693.420000 2289.440000 ;
+ RECT 692.320000 2283.520000 693.420000 2284.000000 ;
+ RECT 692.320000 2278.080000 693.420000 2278.560000 ;
+ RECT 737.320000 2267.200000 738.420000 2267.680000 ;
+ RECT 737.320000 2250.880000 738.420000 2251.360000 ;
+ RECT 737.320000 2256.320000 738.420000 2256.800000 ;
+ RECT 737.320000 2261.760000 738.420000 2262.240000 ;
+ RECT 737.320000 2272.640000 738.420000 2273.120000 ;
+ RECT 692.320000 2250.880000 693.420000 2251.360000 ;
+ RECT 692.320000 2256.320000 693.420000 2256.800000 ;
+ RECT 692.320000 2261.760000 693.420000 2262.240000 ;
+ RECT 692.320000 2267.200000 693.420000 2267.680000 ;
+ RECT 692.320000 2272.640000 693.420000 2273.120000 ;
+ RECT 647.320000 2294.400000 648.420000 2294.880000 ;
+ RECT 643.190000 2294.400000 644.190000 2294.880000 ;
+ RECT 647.320000 2288.960000 648.420000 2289.440000 ;
+ RECT 643.190000 2288.960000 644.190000 2289.440000 ;
+ RECT 647.320000 2283.520000 648.420000 2284.000000 ;
+ RECT 643.190000 2283.520000 644.190000 2284.000000 ;
+ RECT 647.320000 2278.080000 648.420000 2278.560000 ;
+ RECT 643.190000 2278.080000 644.190000 2278.560000 ;
+ RECT 647.320000 2272.640000 648.420000 2273.120000 ;
+ RECT 647.320000 2267.200000 648.420000 2267.680000 ;
+ RECT 643.190000 2272.640000 644.190000 2273.120000 ;
+ RECT 643.190000 2267.200000 644.190000 2267.680000 ;
+ RECT 647.320000 2261.760000 648.420000 2262.240000 ;
+ RECT 643.190000 2261.760000 644.190000 2262.240000 ;
+ RECT 647.320000 2256.320000 648.420000 2256.800000 ;
+ RECT 643.190000 2256.320000 644.190000 2256.800000 ;
+ RECT 647.320000 2250.880000 648.420000 2251.360000 ;
+ RECT 643.190000 2250.880000 644.190000 2251.360000 ;
+ RECT 827.320000 2245.440000 828.420000 2245.920000 ;
+ RECT 827.320000 2240.000000 828.420000 2240.480000 ;
+ RECT 836.630000 2245.440000 837.630000 2245.920000 ;
+ RECT 836.630000 2240.000000 837.630000 2240.480000 ;
+ RECT 836.630000 2223.680000 837.630000 2224.160000 ;
+ RECT 836.630000 2229.120000 837.630000 2229.600000 ;
+ RECT 836.630000 2234.560000 837.630000 2235.040000 ;
+ RECT 827.320000 2234.560000 828.420000 2235.040000 ;
+ RECT 827.320000 2229.120000 828.420000 2229.600000 ;
+ RECT 827.320000 2223.680000 828.420000 2224.160000 ;
+ RECT 827.320000 2212.800000 828.420000 2213.280000 ;
+ RECT 827.320000 2218.240000 828.420000 2218.720000 ;
+ RECT 836.630000 2218.240000 837.630000 2218.720000 ;
+ RECT 836.630000 2212.800000 837.630000 2213.280000 ;
+ RECT 836.630000 2201.920000 837.630000 2202.400000 ;
+ RECT 836.630000 2207.360000 837.630000 2207.840000 ;
+ RECT 827.320000 2201.920000 828.420000 2202.400000 ;
+ RECT 827.320000 2207.360000 828.420000 2207.840000 ;
+ RECT 782.320000 2245.440000 783.420000 2245.920000 ;
+ RECT 782.320000 2240.000000 783.420000 2240.480000 ;
+ RECT 782.320000 2234.560000 783.420000 2235.040000 ;
+ RECT 782.320000 2229.120000 783.420000 2229.600000 ;
+ RECT 782.320000 2223.680000 783.420000 2224.160000 ;
+ RECT 782.320000 2201.920000 783.420000 2202.400000 ;
+ RECT 782.320000 2207.360000 783.420000 2207.840000 ;
+ RECT 782.320000 2212.800000 783.420000 2213.280000 ;
+ RECT 782.320000 2218.240000 783.420000 2218.720000 ;
+ RECT 827.320000 2196.480000 828.420000 2196.960000 ;
+ RECT 827.320000 2191.040000 828.420000 2191.520000 ;
+ RECT 836.630000 2196.480000 837.630000 2196.960000 ;
+ RECT 836.630000 2191.040000 837.630000 2191.520000 ;
+ RECT 827.320000 2180.160000 828.420000 2180.640000 ;
+ RECT 827.320000 2174.720000 828.420000 2175.200000 ;
+ RECT 836.630000 2180.160000 837.630000 2180.640000 ;
+ RECT 836.630000 2174.720000 837.630000 2175.200000 ;
+ RECT 827.320000 2185.600000 828.420000 2186.080000 ;
+ RECT 836.630000 2185.600000 837.630000 2186.080000 ;
+ RECT 836.630000 2163.840000 837.630000 2164.320000 ;
+ RECT 836.630000 2169.280000 837.630000 2169.760000 ;
+ RECT 827.320000 2169.280000 828.420000 2169.760000 ;
+ RECT 827.320000 2163.840000 828.420000 2164.320000 ;
+ RECT 827.320000 2158.400000 828.420000 2158.880000 ;
+ RECT 827.320000 2152.960000 828.420000 2153.440000 ;
+ RECT 836.630000 2158.400000 837.630000 2158.880000 ;
+ RECT 836.630000 2152.960000 837.630000 2153.440000 ;
+ RECT 782.320000 2196.480000 783.420000 2196.960000 ;
+ RECT 782.320000 2191.040000 783.420000 2191.520000 ;
+ RECT 782.320000 2185.600000 783.420000 2186.080000 ;
+ RECT 782.320000 2180.160000 783.420000 2180.640000 ;
+ RECT 782.320000 2174.720000 783.420000 2175.200000 ;
+ RECT 782.320000 2169.280000 783.420000 2169.760000 ;
+ RECT 782.320000 2163.840000 783.420000 2164.320000 ;
+ RECT 782.320000 2158.400000 783.420000 2158.880000 ;
+ RECT 782.320000 2152.960000 783.420000 2153.440000 ;
+ RECT 737.320000 2245.440000 738.420000 2245.920000 ;
+ RECT 737.320000 2240.000000 738.420000 2240.480000 ;
+ RECT 737.320000 2234.560000 738.420000 2235.040000 ;
+ RECT 737.320000 2229.120000 738.420000 2229.600000 ;
+ RECT 737.320000 2223.680000 738.420000 2224.160000 ;
+ RECT 692.320000 2245.440000 693.420000 2245.920000 ;
+ RECT 692.320000 2240.000000 693.420000 2240.480000 ;
+ RECT 692.320000 2234.560000 693.420000 2235.040000 ;
+ RECT 692.320000 2229.120000 693.420000 2229.600000 ;
+ RECT 692.320000 2223.680000 693.420000 2224.160000 ;
+ RECT 737.320000 2218.240000 738.420000 2218.720000 ;
+ RECT 737.320000 2212.800000 738.420000 2213.280000 ;
+ RECT 737.320000 2207.360000 738.420000 2207.840000 ;
+ RECT 737.320000 2201.920000 738.420000 2202.400000 ;
+ RECT 692.320000 2212.800000 693.420000 2213.280000 ;
+ RECT 692.320000 2207.360000 693.420000 2207.840000 ;
+ RECT 692.320000 2201.920000 693.420000 2202.400000 ;
+ RECT 692.320000 2218.240000 693.420000 2218.720000 ;
+ RECT 647.320000 2245.440000 648.420000 2245.920000 ;
+ RECT 643.190000 2245.440000 644.190000 2245.920000 ;
+ RECT 647.320000 2240.000000 648.420000 2240.480000 ;
+ RECT 643.190000 2240.000000 644.190000 2240.480000 ;
+ RECT 647.320000 2234.560000 648.420000 2235.040000 ;
+ RECT 643.190000 2234.560000 644.190000 2235.040000 ;
+ RECT 647.320000 2223.680000 648.420000 2224.160000 ;
+ RECT 643.190000 2223.680000 644.190000 2224.160000 ;
+ RECT 643.190000 2229.120000 644.190000 2229.600000 ;
+ RECT 647.320000 2229.120000 648.420000 2229.600000 ;
+ RECT 647.320000 2218.240000 648.420000 2218.720000 ;
+ RECT 643.190000 2218.240000 644.190000 2218.720000 ;
+ RECT 647.320000 2212.800000 648.420000 2213.280000 ;
+ RECT 643.190000 2212.800000 644.190000 2213.280000 ;
+ RECT 647.320000 2207.360000 648.420000 2207.840000 ;
+ RECT 643.190000 2207.360000 644.190000 2207.840000 ;
+ RECT 647.320000 2201.920000 648.420000 2202.400000 ;
+ RECT 643.190000 2201.920000 644.190000 2202.400000 ;
+ RECT 737.320000 2196.480000 738.420000 2196.960000 ;
+ RECT 737.320000 2191.040000 738.420000 2191.520000 ;
+ RECT 737.320000 2185.600000 738.420000 2186.080000 ;
+ RECT 737.320000 2180.160000 738.420000 2180.640000 ;
+ RECT 737.320000 2174.720000 738.420000 2175.200000 ;
+ RECT 692.320000 2196.480000 693.420000 2196.960000 ;
+ RECT 692.320000 2191.040000 693.420000 2191.520000 ;
+ RECT 692.320000 2185.600000 693.420000 2186.080000 ;
+ RECT 692.320000 2180.160000 693.420000 2180.640000 ;
+ RECT 692.320000 2174.720000 693.420000 2175.200000 ;
+ RECT 737.320000 2152.960000 738.420000 2153.440000 ;
+ RECT 737.320000 2158.400000 738.420000 2158.880000 ;
+ RECT 737.320000 2163.840000 738.420000 2164.320000 ;
+ RECT 737.320000 2169.280000 738.420000 2169.760000 ;
+ RECT 692.320000 2152.960000 693.420000 2153.440000 ;
+ RECT 692.320000 2158.400000 693.420000 2158.880000 ;
+ RECT 692.320000 2163.840000 693.420000 2164.320000 ;
+ RECT 692.320000 2169.280000 693.420000 2169.760000 ;
+ RECT 647.320000 2196.480000 648.420000 2196.960000 ;
+ RECT 643.190000 2196.480000 644.190000 2196.960000 ;
+ RECT 647.320000 2191.040000 648.420000 2191.520000 ;
+ RECT 643.190000 2191.040000 644.190000 2191.520000 ;
+ RECT 647.320000 2180.160000 648.420000 2180.640000 ;
+ RECT 643.190000 2180.160000 644.190000 2180.640000 ;
+ RECT 647.320000 2174.720000 648.420000 2175.200000 ;
+ RECT 643.190000 2174.720000 644.190000 2175.200000 ;
+ RECT 647.320000 2185.600000 648.420000 2186.080000 ;
+ RECT 643.190000 2185.600000 644.190000 2186.080000 ;
+ RECT 647.320000 2169.280000 648.420000 2169.760000 ;
+ RECT 643.190000 2169.280000 644.190000 2169.760000 ;
+ RECT 647.320000 2163.840000 648.420000 2164.320000 ;
+ RECT 643.190000 2163.840000 644.190000 2164.320000 ;
+ RECT 647.320000 2158.400000 648.420000 2158.880000 ;
+ RECT 647.320000 2152.960000 648.420000 2153.440000 ;
+ RECT 643.190000 2158.400000 644.190000 2158.880000 ;
+ RECT 643.190000 2152.960000 644.190000 2153.440000 ;
+ RECT 640.360000 2343.320000 840.460000 2344.320000 ;
+ RECT 640.360000 2150.950000 840.460000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 2148.100000 644.190000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 2347.360000 644.190000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 2148.100000 837.630000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 2347.360000 837.630000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2150.950000 641.360000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2150.950000 840.460000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2343.320000 641.360000 2344.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2343.320000 840.460000 2344.320000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 1950.690000 828.420000 2144.060000 ;
+ RECT 782.320000 1950.690000 783.420000 2144.060000 ;
+ RECT 836.630000 1947.840000 837.630000 2148.100000 ;
+ RECT 737.320000 1950.690000 738.420000 2144.060000 ;
+ RECT 692.320000 1950.690000 693.420000 2144.060000 ;
+ RECT 647.320000 1950.690000 648.420000 2144.060000 ;
+ RECT 643.190000 1947.840000 644.190000 2148.100000 ;
+ LAYER met3 ;
+ RECT 827.320000 2137.660000 828.420000 2138.140000 ;
+ RECT 836.630000 2137.660000 837.630000 2138.140000 ;
+ RECT 836.630000 2126.780000 837.630000 2127.260000 ;
+ RECT 836.630000 2132.220000 837.630000 2132.700000 ;
+ RECT 827.320000 2132.220000 828.420000 2132.700000 ;
+ RECT 827.320000 2126.780000 828.420000 2127.260000 ;
+ RECT 827.320000 2121.340000 828.420000 2121.820000 ;
+ RECT 827.320000 2115.900000 828.420000 2116.380000 ;
+ RECT 836.630000 2121.340000 837.630000 2121.820000 ;
+ RECT 836.630000 2115.900000 837.630000 2116.380000 ;
+ RECT 827.320000 2099.580000 828.420000 2100.060000 ;
+ RECT 827.320000 2105.020000 828.420000 2105.500000 ;
+ RECT 836.630000 2105.020000 837.630000 2105.500000 ;
+ RECT 836.630000 2099.580000 837.630000 2100.060000 ;
+ RECT 827.320000 2110.460000 828.420000 2110.940000 ;
+ RECT 836.630000 2110.460000 837.630000 2110.940000 ;
+ RECT 782.320000 2137.660000 783.420000 2138.140000 ;
+ RECT 782.320000 2132.220000 783.420000 2132.700000 ;
+ RECT 782.320000 2126.780000 783.420000 2127.260000 ;
+ RECT 782.320000 2121.340000 783.420000 2121.820000 ;
+ RECT 782.320000 2099.580000 783.420000 2100.060000 ;
+ RECT 782.320000 2105.020000 783.420000 2105.500000 ;
+ RECT 782.320000 2110.460000 783.420000 2110.940000 ;
+ RECT 782.320000 2115.900000 783.420000 2116.380000 ;
+ RECT 836.630000 2088.700000 837.630000 2089.180000 ;
+ RECT 836.630000 2094.140000 837.630000 2094.620000 ;
+ RECT 827.320000 2094.140000 828.420000 2094.620000 ;
+ RECT 827.320000 2088.700000 828.420000 2089.180000 ;
+ RECT 827.320000 2083.260000 828.420000 2083.740000 ;
+ RECT 827.320000 2077.820000 828.420000 2078.300000 ;
+ RECT 836.630000 2083.260000 837.630000 2083.740000 ;
+ RECT 836.630000 2077.820000 837.630000 2078.300000 ;
+ RECT 836.630000 2061.500000 837.630000 2061.980000 ;
+ RECT 836.630000 2066.940000 837.630000 2067.420000 ;
+ RECT 836.630000 2072.380000 837.630000 2072.860000 ;
+ RECT 827.320000 2066.940000 828.420000 2067.420000 ;
+ RECT 827.320000 2061.500000 828.420000 2061.980000 ;
+ RECT 827.320000 2072.380000 828.420000 2072.860000 ;
+ RECT 827.320000 2056.060000 828.420000 2056.540000 ;
+ RECT 827.320000 2050.620000 828.420000 2051.100000 ;
+ RECT 836.630000 2056.060000 837.630000 2056.540000 ;
+ RECT 836.630000 2050.620000 837.630000 2051.100000 ;
+ RECT 782.320000 2094.140000 783.420000 2094.620000 ;
+ RECT 782.320000 2088.700000 783.420000 2089.180000 ;
+ RECT 782.320000 2083.260000 783.420000 2083.740000 ;
+ RECT 782.320000 2077.820000 783.420000 2078.300000 ;
+ RECT 782.320000 2066.940000 783.420000 2067.420000 ;
+ RECT 782.320000 2061.500000 783.420000 2061.980000 ;
+ RECT 782.320000 2056.060000 783.420000 2056.540000 ;
+ RECT 782.320000 2050.620000 783.420000 2051.100000 ;
+ RECT 782.320000 2072.380000 783.420000 2072.860000 ;
+ RECT 737.320000 2137.660000 738.420000 2138.140000 ;
+ RECT 737.320000 2132.220000 738.420000 2132.700000 ;
+ RECT 737.320000 2126.780000 738.420000 2127.260000 ;
+ RECT 692.320000 2137.660000 693.420000 2138.140000 ;
+ RECT 692.320000 2132.220000 693.420000 2132.700000 ;
+ RECT 692.320000 2126.780000 693.420000 2127.260000 ;
+ RECT 737.320000 2110.460000 738.420000 2110.940000 ;
+ RECT 737.320000 2105.020000 738.420000 2105.500000 ;
+ RECT 737.320000 2099.580000 738.420000 2100.060000 ;
+ RECT 737.320000 2115.900000 738.420000 2116.380000 ;
+ RECT 737.320000 2121.340000 738.420000 2121.820000 ;
+ RECT 692.320000 2121.340000 693.420000 2121.820000 ;
+ RECT 692.320000 2110.460000 693.420000 2110.940000 ;
+ RECT 692.320000 2105.020000 693.420000 2105.500000 ;
+ RECT 692.320000 2099.580000 693.420000 2100.060000 ;
+ RECT 692.320000 2115.900000 693.420000 2116.380000 ;
+ RECT 647.320000 2137.660000 648.420000 2138.140000 ;
+ RECT 643.190000 2137.660000 644.190000 2138.140000 ;
+ RECT 643.190000 2132.220000 644.190000 2132.700000 ;
+ RECT 647.320000 2132.220000 648.420000 2132.700000 ;
+ RECT 647.320000 2126.780000 648.420000 2127.260000 ;
+ RECT 643.190000 2126.780000 644.190000 2127.260000 ;
+ RECT 647.320000 2121.340000 648.420000 2121.820000 ;
+ RECT 643.190000 2121.340000 644.190000 2121.820000 ;
+ RECT 647.320000 2115.900000 648.420000 2116.380000 ;
+ RECT 643.190000 2115.900000 644.190000 2116.380000 ;
+ RECT 647.320000 2105.020000 648.420000 2105.500000 ;
+ RECT 643.190000 2105.020000 644.190000 2105.500000 ;
+ RECT 647.320000 2099.580000 648.420000 2100.060000 ;
+ RECT 643.190000 2099.580000 644.190000 2100.060000 ;
+ RECT 647.320000 2110.460000 648.420000 2110.940000 ;
+ RECT 643.190000 2110.460000 644.190000 2110.940000 ;
+ RECT 737.320000 2094.140000 738.420000 2094.620000 ;
+ RECT 737.320000 2088.700000 738.420000 2089.180000 ;
+ RECT 737.320000 2083.260000 738.420000 2083.740000 ;
+ RECT 737.320000 2077.820000 738.420000 2078.300000 ;
+ RECT 692.320000 2094.140000 693.420000 2094.620000 ;
+ RECT 692.320000 2088.700000 693.420000 2089.180000 ;
+ RECT 692.320000 2083.260000 693.420000 2083.740000 ;
+ RECT 692.320000 2077.820000 693.420000 2078.300000 ;
+ RECT 737.320000 2066.940000 738.420000 2067.420000 ;
+ RECT 737.320000 2050.620000 738.420000 2051.100000 ;
+ RECT 737.320000 2056.060000 738.420000 2056.540000 ;
+ RECT 737.320000 2061.500000 738.420000 2061.980000 ;
+ RECT 737.320000 2072.380000 738.420000 2072.860000 ;
+ RECT 692.320000 2050.620000 693.420000 2051.100000 ;
+ RECT 692.320000 2056.060000 693.420000 2056.540000 ;
+ RECT 692.320000 2061.500000 693.420000 2061.980000 ;
+ RECT 692.320000 2066.940000 693.420000 2067.420000 ;
+ RECT 692.320000 2072.380000 693.420000 2072.860000 ;
+ RECT 647.320000 2094.140000 648.420000 2094.620000 ;
+ RECT 643.190000 2094.140000 644.190000 2094.620000 ;
+ RECT 647.320000 2088.700000 648.420000 2089.180000 ;
+ RECT 643.190000 2088.700000 644.190000 2089.180000 ;
+ RECT 647.320000 2083.260000 648.420000 2083.740000 ;
+ RECT 643.190000 2083.260000 644.190000 2083.740000 ;
+ RECT 647.320000 2077.820000 648.420000 2078.300000 ;
+ RECT 643.190000 2077.820000 644.190000 2078.300000 ;
+ RECT 647.320000 2072.380000 648.420000 2072.860000 ;
+ RECT 647.320000 2066.940000 648.420000 2067.420000 ;
+ RECT 643.190000 2072.380000 644.190000 2072.860000 ;
+ RECT 643.190000 2066.940000 644.190000 2067.420000 ;
+ RECT 647.320000 2061.500000 648.420000 2061.980000 ;
+ RECT 643.190000 2061.500000 644.190000 2061.980000 ;
+ RECT 647.320000 2056.060000 648.420000 2056.540000 ;
+ RECT 643.190000 2056.060000 644.190000 2056.540000 ;
+ RECT 647.320000 2050.620000 648.420000 2051.100000 ;
+ RECT 643.190000 2050.620000 644.190000 2051.100000 ;
+ RECT 827.320000 2045.180000 828.420000 2045.660000 ;
+ RECT 827.320000 2039.740000 828.420000 2040.220000 ;
+ RECT 836.630000 2045.180000 837.630000 2045.660000 ;
+ RECT 836.630000 2039.740000 837.630000 2040.220000 ;
+ RECT 836.630000 2023.420000 837.630000 2023.900000 ;
+ RECT 836.630000 2028.860000 837.630000 2029.340000 ;
+ RECT 836.630000 2034.300000 837.630000 2034.780000 ;
+ RECT 827.320000 2034.300000 828.420000 2034.780000 ;
+ RECT 827.320000 2028.860000 828.420000 2029.340000 ;
+ RECT 827.320000 2023.420000 828.420000 2023.900000 ;
+ RECT 827.320000 2012.540000 828.420000 2013.020000 ;
+ RECT 827.320000 2017.980000 828.420000 2018.460000 ;
+ RECT 836.630000 2017.980000 837.630000 2018.460000 ;
+ RECT 836.630000 2012.540000 837.630000 2013.020000 ;
+ RECT 836.630000 2001.660000 837.630000 2002.140000 ;
+ RECT 836.630000 2007.100000 837.630000 2007.580000 ;
+ RECT 827.320000 2001.660000 828.420000 2002.140000 ;
+ RECT 827.320000 2007.100000 828.420000 2007.580000 ;
+ RECT 782.320000 2045.180000 783.420000 2045.660000 ;
+ RECT 782.320000 2039.740000 783.420000 2040.220000 ;
+ RECT 782.320000 2034.300000 783.420000 2034.780000 ;
+ RECT 782.320000 2028.860000 783.420000 2029.340000 ;
+ RECT 782.320000 2023.420000 783.420000 2023.900000 ;
+ RECT 782.320000 2001.660000 783.420000 2002.140000 ;
+ RECT 782.320000 2007.100000 783.420000 2007.580000 ;
+ RECT 782.320000 2012.540000 783.420000 2013.020000 ;
+ RECT 782.320000 2017.980000 783.420000 2018.460000 ;
+ RECT 827.320000 1996.220000 828.420000 1996.700000 ;
+ RECT 827.320000 1990.780000 828.420000 1991.260000 ;
+ RECT 836.630000 1996.220000 837.630000 1996.700000 ;
+ RECT 836.630000 1990.780000 837.630000 1991.260000 ;
+ RECT 827.320000 1979.900000 828.420000 1980.380000 ;
+ RECT 827.320000 1974.460000 828.420000 1974.940000 ;
+ RECT 836.630000 1979.900000 837.630000 1980.380000 ;
+ RECT 836.630000 1974.460000 837.630000 1974.940000 ;
+ RECT 827.320000 1985.340000 828.420000 1985.820000 ;
+ RECT 836.630000 1985.340000 837.630000 1985.820000 ;
+ RECT 836.630000 1963.580000 837.630000 1964.060000 ;
+ RECT 836.630000 1969.020000 837.630000 1969.500000 ;
+ RECT 827.320000 1969.020000 828.420000 1969.500000 ;
+ RECT 827.320000 1963.580000 828.420000 1964.060000 ;
+ RECT 827.320000 1958.140000 828.420000 1958.620000 ;
+ RECT 827.320000 1952.700000 828.420000 1953.180000 ;
+ RECT 836.630000 1958.140000 837.630000 1958.620000 ;
+ RECT 836.630000 1952.700000 837.630000 1953.180000 ;
+ RECT 782.320000 1996.220000 783.420000 1996.700000 ;
+ RECT 782.320000 1990.780000 783.420000 1991.260000 ;
+ RECT 782.320000 1985.340000 783.420000 1985.820000 ;
+ RECT 782.320000 1979.900000 783.420000 1980.380000 ;
+ RECT 782.320000 1974.460000 783.420000 1974.940000 ;
+ RECT 782.320000 1969.020000 783.420000 1969.500000 ;
+ RECT 782.320000 1963.580000 783.420000 1964.060000 ;
+ RECT 782.320000 1958.140000 783.420000 1958.620000 ;
+ RECT 782.320000 1952.700000 783.420000 1953.180000 ;
+ RECT 737.320000 2045.180000 738.420000 2045.660000 ;
+ RECT 737.320000 2039.740000 738.420000 2040.220000 ;
+ RECT 737.320000 2034.300000 738.420000 2034.780000 ;
+ RECT 737.320000 2028.860000 738.420000 2029.340000 ;
+ RECT 737.320000 2023.420000 738.420000 2023.900000 ;
+ RECT 692.320000 2045.180000 693.420000 2045.660000 ;
+ RECT 692.320000 2039.740000 693.420000 2040.220000 ;
+ RECT 692.320000 2034.300000 693.420000 2034.780000 ;
+ RECT 692.320000 2028.860000 693.420000 2029.340000 ;
+ RECT 692.320000 2023.420000 693.420000 2023.900000 ;
+ RECT 737.320000 2017.980000 738.420000 2018.460000 ;
+ RECT 737.320000 2012.540000 738.420000 2013.020000 ;
+ RECT 737.320000 2007.100000 738.420000 2007.580000 ;
+ RECT 737.320000 2001.660000 738.420000 2002.140000 ;
+ RECT 692.320000 2012.540000 693.420000 2013.020000 ;
+ RECT 692.320000 2007.100000 693.420000 2007.580000 ;
+ RECT 692.320000 2001.660000 693.420000 2002.140000 ;
+ RECT 692.320000 2017.980000 693.420000 2018.460000 ;
+ RECT 647.320000 2045.180000 648.420000 2045.660000 ;
+ RECT 643.190000 2045.180000 644.190000 2045.660000 ;
+ RECT 647.320000 2039.740000 648.420000 2040.220000 ;
+ RECT 643.190000 2039.740000 644.190000 2040.220000 ;
+ RECT 647.320000 2034.300000 648.420000 2034.780000 ;
+ RECT 643.190000 2034.300000 644.190000 2034.780000 ;
+ RECT 647.320000 2023.420000 648.420000 2023.900000 ;
+ RECT 643.190000 2023.420000 644.190000 2023.900000 ;
+ RECT 643.190000 2028.860000 644.190000 2029.340000 ;
+ RECT 647.320000 2028.860000 648.420000 2029.340000 ;
+ RECT 647.320000 2017.980000 648.420000 2018.460000 ;
+ RECT 643.190000 2017.980000 644.190000 2018.460000 ;
+ RECT 647.320000 2012.540000 648.420000 2013.020000 ;
+ RECT 643.190000 2012.540000 644.190000 2013.020000 ;
+ RECT 647.320000 2007.100000 648.420000 2007.580000 ;
+ RECT 643.190000 2007.100000 644.190000 2007.580000 ;
+ RECT 647.320000 2001.660000 648.420000 2002.140000 ;
+ RECT 643.190000 2001.660000 644.190000 2002.140000 ;
+ RECT 737.320000 1996.220000 738.420000 1996.700000 ;
+ RECT 737.320000 1990.780000 738.420000 1991.260000 ;
+ RECT 737.320000 1985.340000 738.420000 1985.820000 ;
+ RECT 737.320000 1979.900000 738.420000 1980.380000 ;
+ RECT 737.320000 1974.460000 738.420000 1974.940000 ;
+ RECT 692.320000 1996.220000 693.420000 1996.700000 ;
+ RECT 692.320000 1990.780000 693.420000 1991.260000 ;
+ RECT 692.320000 1985.340000 693.420000 1985.820000 ;
+ RECT 692.320000 1979.900000 693.420000 1980.380000 ;
+ RECT 692.320000 1974.460000 693.420000 1974.940000 ;
+ RECT 737.320000 1952.700000 738.420000 1953.180000 ;
+ RECT 737.320000 1958.140000 738.420000 1958.620000 ;
+ RECT 737.320000 1963.580000 738.420000 1964.060000 ;
+ RECT 737.320000 1969.020000 738.420000 1969.500000 ;
+ RECT 692.320000 1952.700000 693.420000 1953.180000 ;
+ RECT 692.320000 1958.140000 693.420000 1958.620000 ;
+ RECT 692.320000 1963.580000 693.420000 1964.060000 ;
+ RECT 692.320000 1969.020000 693.420000 1969.500000 ;
+ RECT 647.320000 1996.220000 648.420000 1996.700000 ;
+ RECT 643.190000 1996.220000 644.190000 1996.700000 ;
+ RECT 647.320000 1990.780000 648.420000 1991.260000 ;
+ RECT 643.190000 1990.780000 644.190000 1991.260000 ;
+ RECT 647.320000 1979.900000 648.420000 1980.380000 ;
+ RECT 643.190000 1979.900000 644.190000 1980.380000 ;
+ RECT 647.320000 1974.460000 648.420000 1974.940000 ;
+ RECT 643.190000 1974.460000 644.190000 1974.940000 ;
+ RECT 647.320000 1985.340000 648.420000 1985.820000 ;
+ RECT 643.190000 1985.340000 644.190000 1985.820000 ;
+ RECT 647.320000 1969.020000 648.420000 1969.500000 ;
+ RECT 643.190000 1969.020000 644.190000 1969.500000 ;
+ RECT 647.320000 1963.580000 648.420000 1964.060000 ;
+ RECT 643.190000 1963.580000 644.190000 1964.060000 ;
+ RECT 647.320000 1958.140000 648.420000 1958.620000 ;
+ RECT 647.320000 1952.700000 648.420000 1953.180000 ;
+ RECT 643.190000 1958.140000 644.190000 1958.620000 ;
+ RECT 643.190000 1952.700000 644.190000 1953.180000 ;
+ RECT 640.360000 2143.060000 840.460000 2144.060000 ;
+ RECT 640.360000 1950.690000 840.460000 1951.690000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 1947.840000 644.190000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 2147.100000 644.190000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 1947.840000 837.630000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 2147.100000 837.630000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1950.690000 641.360000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1950.690000 840.460000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 2143.060000 641.360000 2144.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 2143.060000 840.460000 2144.060000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 1750.430000 828.420000 1943.800000 ;
+ RECT 782.320000 1750.430000 783.420000 1943.800000 ;
+ RECT 836.630000 1747.580000 837.630000 1947.840000 ;
+ RECT 737.320000 1750.430000 738.420000 1943.800000 ;
+ RECT 692.320000 1750.430000 693.420000 1943.800000 ;
+ RECT 647.320000 1750.430000 648.420000 1943.800000 ;
+ RECT 643.190000 1747.580000 644.190000 1947.840000 ;
+ LAYER met3 ;
+ RECT 827.320000 1937.400000 828.420000 1937.880000 ;
+ RECT 836.630000 1937.400000 837.630000 1937.880000 ;
+ RECT 836.630000 1926.520000 837.630000 1927.000000 ;
+ RECT 836.630000 1931.960000 837.630000 1932.440000 ;
+ RECT 827.320000 1931.960000 828.420000 1932.440000 ;
+ RECT 827.320000 1926.520000 828.420000 1927.000000 ;
+ RECT 827.320000 1921.080000 828.420000 1921.560000 ;
+ RECT 827.320000 1915.640000 828.420000 1916.120000 ;
+ RECT 836.630000 1921.080000 837.630000 1921.560000 ;
+ RECT 836.630000 1915.640000 837.630000 1916.120000 ;
+ RECT 827.320000 1899.320000 828.420000 1899.800000 ;
+ RECT 827.320000 1904.760000 828.420000 1905.240000 ;
+ RECT 836.630000 1904.760000 837.630000 1905.240000 ;
+ RECT 836.630000 1899.320000 837.630000 1899.800000 ;
+ RECT 827.320000 1910.200000 828.420000 1910.680000 ;
+ RECT 836.630000 1910.200000 837.630000 1910.680000 ;
+ RECT 782.320000 1937.400000 783.420000 1937.880000 ;
+ RECT 782.320000 1931.960000 783.420000 1932.440000 ;
+ RECT 782.320000 1926.520000 783.420000 1927.000000 ;
+ RECT 782.320000 1921.080000 783.420000 1921.560000 ;
+ RECT 782.320000 1899.320000 783.420000 1899.800000 ;
+ RECT 782.320000 1904.760000 783.420000 1905.240000 ;
+ RECT 782.320000 1910.200000 783.420000 1910.680000 ;
+ RECT 782.320000 1915.640000 783.420000 1916.120000 ;
+ RECT 836.630000 1888.440000 837.630000 1888.920000 ;
+ RECT 836.630000 1893.880000 837.630000 1894.360000 ;
+ RECT 827.320000 1893.880000 828.420000 1894.360000 ;
+ RECT 827.320000 1888.440000 828.420000 1888.920000 ;
+ RECT 827.320000 1883.000000 828.420000 1883.480000 ;
+ RECT 827.320000 1877.560000 828.420000 1878.040000 ;
+ RECT 836.630000 1883.000000 837.630000 1883.480000 ;
+ RECT 836.630000 1877.560000 837.630000 1878.040000 ;
+ RECT 836.630000 1861.240000 837.630000 1861.720000 ;
+ RECT 836.630000 1866.680000 837.630000 1867.160000 ;
+ RECT 836.630000 1872.120000 837.630000 1872.600000 ;
+ RECT 827.320000 1866.680000 828.420000 1867.160000 ;
+ RECT 827.320000 1861.240000 828.420000 1861.720000 ;
+ RECT 827.320000 1872.120000 828.420000 1872.600000 ;
+ RECT 827.320000 1855.800000 828.420000 1856.280000 ;
+ RECT 827.320000 1850.360000 828.420000 1850.840000 ;
+ RECT 836.630000 1855.800000 837.630000 1856.280000 ;
+ RECT 836.630000 1850.360000 837.630000 1850.840000 ;
+ RECT 782.320000 1893.880000 783.420000 1894.360000 ;
+ RECT 782.320000 1888.440000 783.420000 1888.920000 ;
+ RECT 782.320000 1883.000000 783.420000 1883.480000 ;
+ RECT 782.320000 1877.560000 783.420000 1878.040000 ;
+ RECT 782.320000 1866.680000 783.420000 1867.160000 ;
+ RECT 782.320000 1861.240000 783.420000 1861.720000 ;
+ RECT 782.320000 1855.800000 783.420000 1856.280000 ;
+ RECT 782.320000 1850.360000 783.420000 1850.840000 ;
+ RECT 782.320000 1872.120000 783.420000 1872.600000 ;
+ RECT 737.320000 1937.400000 738.420000 1937.880000 ;
+ RECT 737.320000 1931.960000 738.420000 1932.440000 ;
+ RECT 737.320000 1926.520000 738.420000 1927.000000 ;
+ RECT 692.320000 1937.400000 693.420000 1937.880000 ;
+ RECT 692.320000 1931.960000 693.420000 1932.440000 ;
+ RECT 692.320000 1926.520000 693.420000 1927.000000 ;
+ RECT 737.320000 1910.200000 738.420000 1910.680000 ;
+ RECT 737.320000 1904.760000 738.420000 1905.240000 ;
+ RECT 737.320000 1899.320000 738.420000 1899.800000 ;
+ RECT 737.320000 1915.640000 738.420000 1916.120000 ;
+ RECT 737.320000 1921.080000 738.420000 1921.560000 ;
+ RECT 692.320000 1921.080000 693.420000 1921.560000 ;
+ RECT 692.320000 1910.200000 693.420000 1910.680000 ;
+ RECT 692.320000 1904.760000 693.420000 1905.240000 ;
+ RECT 692.320000 1899.320000 693.420000 1899.800000 ;
+ RECT 692.320000 1915.640000 693.420000 1916.120000 ;
+ RECT 647.320000 1937.400000 648.420000 1937.880000 ;
+ RECT 643.190000 1937.400000 644.190000 1937.880000 ;
+ RECT 643.190000 1931.960000 644.190000 1932.440000 ;
+ RECT 647.320000 1931.960000 648.420000 1932.440000 ;
+ RECT 647.320000 1926.520000 648.420000 1927.000000 ;
+ RECT 643.190000 1926.520000 644.190000 1927.000000 ;
+ RECT 647.320000 1921.080000 648.420000 1921.560000 ;
+ RECT 643.190000 1921.080000 644.190000 1921.560000 ;
+ RECT 647.320000 1915.640000 648.420000 1916.120000 ;
+ RECT 643.190000 1915.640000 644.190000 1916.120000 ;
+ RECT 647.320000 1904.760000 648.420000 1905.240000 ;
+ RECT 643.190000 1904.760000 644.190000 1905.240000 ;
+ RECT 647.320000 1899.320000 648.420000 1899.800000 ;
+ RECT 643.190000 1899.320000 644.190000 1899.800000 ;
+ RECT 647.320000 1910.200000 648.420000 1910.680000 ;
+ RECT 643.190000 1910.200000 644.190000 1910.680000 ;
+ RECT 737.320000 1893.880000 738.420000 1894.360000 ;
+ RECT 737.320000 1888.440000 738.420000 1888.920000 ;
+ RECT 737.320000 1883.000000 738.420000 1883.480000 ;
+ RECT 737.320000 1877.560000 738.420000 1878.040000 ;
+ RECT 692.320000 1893.880000 693.420000 1894.360000 ;
+ RECT 692.320000 1888.440000 693.420000 1888.920000 ;
+ RECT 692.320000 1883.000000 693.420000 1883.480000 ;
+ RECT 692.320000 1877.560000 693.420000 1878.040000 ;
+ RECT 737.320000 1866.680000 738.420000 1867.160000 ;
+ RECT 737.320000 1850.360000 738.420000 1850.840000 ;
+ RECT 737.320000 1855.800000 738.420000 1856.280000 ;
+ RECT 737.320000 1861.240000 738.420000 1861.720000 ;
+ RECT 737.320000 1872.120000 738.420000 1872.600000 ;
+ RECT 692.320000 1850.360000 693.420000 1850.840000 ;
+ RECT 692.320000 1855.800000 693.420000 1856.280000 ;
+ RECT 692.320000 1861.240000 693.420000 1861.720000 ;
+ RECT 692.320000 1866.680000 693.420000 1867.160000 ;
+ RECT 692.320000 1872.120000 693.420000 1872.600000 ;
+ RECT 647.320000 1893.880000 648.420000 1894.360000 ;
+ RECT 643.190000 1893.880000 644.190000 1894.360000 ;
+ RECT 647.320000 1888.440000 648.420000 1888.920000 ;
+ RECT 643.190000 1888.440000 644.190000 1888.920000 ;
+ RECT 647.320000 1883.000000 648.420000 1883.480000 ;
+ RECT 643.190000 1883.000000 644.190000 1883.480000 ;
+ RECT 647.320000 1877.560000 648.420000 1878.040000 ;
+ RECT 643.190000 1877.560000 644.190000 1878.040000 ;
+ RECT 647.320000 1872.120000 648.420000 1872.600000 ;
+ RECT 647.320000 1866.680000 648.420000 1867.160000 ;
+ RECT 643.190000 1872.120000 644.190000 1872.600000 ;
+ RECT 643.190000 1866.680000 644.190000 1867.160000 ;
+ RECT 647.320000 1861.240000 648.420000 1861.720000 ;
+ RECT 643.190000 1861.240000 644.190000 1861.720000 ;
+ RECT 647.320000 1855.800000 648.420000 1856.280000 ;
+ RECT 643.190000 1855.800000 644.190000 1856.280000 ;
+ RECT 647.320000 1850.360000 648.420000 1850.840000 ;
+ RECT 643.190000 1850.360000 644.190000 1850.840000 ;
+ RECT 827.320000 1844.920000 828.420000 1845.400000 ;
+ RECT 827.320000 1839.480000 828.420000 1839.960000 ;
+ RECT 836.630000 1844.920000 837.630000 1845.400000 ;
+ RECT 836.630000 1839.480000 837.630000 1839.960000 ;
+ RECT 836.630000 1823.160000 837.630000 1823.640000 ;
+ RECT 836.630000 1828.600000 837.630000 1829.080000 ;
+ RECT 836.630000 1834.040000 837.630000 1834.520000 ;
+ RECT 827.320000 1834.040000 828.420000 1834.520000 ;
+ RECT 827.320000 1828.600000 828.420000 1829.080000 ;
+ RECT 827.320000 1823.160000 828.420000 1823.640000 ;
+ RECT 827.320000 1812.280000 828.420000 1812.760000 ;
+ RECT 827.320000 1817.720000 828.420000 1818.200000 ;
+ RECT 836.630000 1817.720000 837.630000 1818.200000 ;
+ RECT 836.630000 1812.280000 837.630000 1812.760000 ;
+ RECT 836.630000 1801.400000 837.630000 1801.880000 ;
+ RECT 836.630000 1806.840000 837.630000 1807.320000 ;
+ RECT 827.320000 1801.400000 828.420000 1801.880000 ;
+ RECT 827.320000 1806.840000 828.420000 1807.320000 ;
+ RECT 782.320000 1844.920000 783.420000 1845.400000 ;
+ RECT 782.320000 1839.480000 783.420000 1839.960000 ;
+ RECT 782.320000 1834.040000 783.420000 1834.520000 ;
+ RECT 782.320000 1828.600000 783.420000 1829.080000 ;
+ RECT 782.320000 1823.160000 783.420000 1823.640000 ;
+ RECT 782.320000 1801.400000 783.420000 1801.880000 ;
+ RECT 782.320000 1806.840000 783.420000 1807.320000 ;
+ RECT 782.320000 1812.280000 783.420000 1812.760000 ;
+ RECT 782.320000 1817.720000 783.420000 1818.200000 ;
+ RECT 827.320000 1795.960000 828.420000 1796.440000 ;
+ RECT 827.320000 1790.520000 828.420000 1791.000000 ;
+ RECT 836.630000 1795.960000 837.630000 1796.440000 ;
+ RECT 836.630000 1790.520000 837.630000 1791.000000 ;
+ RECT 827.320000 1779.640000 828.420000 1780.120000 ;
+ RECT 827.320000 1774.200000 828.420000 1774.680000 ;
+ RECT 836.630000 1779.640000 837.630000 1780.120000 ;
+ RECT 836.630000 1774.200000 837.630000 1774.680000 ;
+ RECT 827.320000 1785.080000 828.420000 1785.560000 ;
+ RECT 836.630000 1785.080000 837.630000 1785.560000 ;
+ RECT 836.630000 1763.320000 837.630000 1763.800000 ;
+ RECT 836.630000 1768.760000 837.630000 1769.240000 ;
+ RECT 827.320000 1768.760000 828.420000 1769.240000 ;
+ RECT 827.320000 1763.320000 828.420000 1763.800000 ;
+ RECT 827.320000 1757.880000 828.420000 1758.360000 ;
+ RECT 827.320000 1752.440000 828.420000 1752.920000 ;
+ RECT 836.630000 1757.880000 837.630000 1758.360000 ;
+ RECT 836.630000 1752.440000 837.630000 1752.920000 ;
+ RECT 782.320000 1795.960000 783.420000 1796.440000 ;
+ RECT 782.320000 1790.520000 783.420000 1791.000000 ;
+ RECT 782.320000 1785.080000 783.420000 1785.560000 ;
+ RECT 782.320000 1779.640000 783.420000 1780.120000 ;
+ RECT 782.320000 1774.200000 783.420000 1774.680000 ;
+ RECT 782.320000 1768.760000 783.420000 1769.240000 ;
+ RECT 782.320000 1763.320000 783.420000 1763.800000 ;
+ RECT 782.320000 1757.880000 783.420000 1758.360000 ;
+ RECT 782.320000 1752.440000 783.420000 1752.920000 ;
+ RECT 737.320000 1844.920000 738.420000 1845.400000 ;
+ RECT 737.320000 1839.480000 738.420000 1839.960000 ;
+ RECT 737.320000 1834.040000 738.420000 1834.520000 ;
+ RECT 737.320000 1828.600000 738.420000 1829.080000 ;
+ RECT 737.320000 1823.160000 738.420000 1823.640000 ;
+ RECT 692.320000 1844.920000 693.420000 1845.400000 ;
+ RECT 692.320000 1839.480000 693.420000 1839.960000 ;
+ RECT 692.320000 1834.040000 693.420000 1834.520000 ;
+ RECT 692.320000 1828.600000 693.420000 1829.080000 ;
+ RECT 692.320000 1823.160000 693.420000 1823.640000 ;
+ RECT 737.320000 1817.720000 738.420000 1818.200000 ;
+ RECT 737.320000 1812.280000 738.420000 1812.760000 ;
+ RECT 737.320000 1806.840000 738.420000 1807.320000 ;
+ RECT 737.320000 1801.400000 738.420000 1801.880000 ;
+ RECT 692.320000 1812.280000 693.420000 1812.760000 ;
+ RECT 692.320000 1806.840000 693.420000 1807.320000 ;
+ RECT 692.320000 1801.400000 693.420000 1801.880000 ;
+ RECT 692.320000 1817.720000 693.420000 1818.200000 ;
+ RECT 647.320000 1844.920000 648.420000 1845.400000 ;
+ RECT 643.190000 1844.920000 644.190000 1845.400000 ;
+ RECT 647.320000 1839.480000 648.420000 1839.960000 ;
+ RECT 643.190000 1839.480000 644.190000 1839.960000 ;
+ RECT 647.320000 1834.040000 648.420000 1834.520000 ;
+ RECT 643.190000 1834.040000 644.190000 1834.520000 ;
+ RECT 647.320000 1823.160000 648.420000 1823.640000 ;
+ RECT 643.190000 1823.160000 644.190000 1823.640000 ;
+ RECT 643.190000 1828.600000 644.190000 1829.080000 ;
+ RECT 647.320000 1828.600000 648.420000 1829.080000 ;
+ RECT 647.320000 1817.720000 648.420000 1818.200000 ;
+ RECT 643.190000 1817.720000 644.190000 1818.200000 ;
+ RECT 647.320000 1812.280000 648.420000 1812.760000 ;
+ RECT 643.190000 1812.280000 644.190000 1812.760000 ;
+ RECT 647.320000 1806.840000 648.420000 1807.320000 ;
+ RECT 643.190000 1806.840000 644.190000 1807.320000 ;
+ RECT 647.320000 1801.400000 648.420000 1801.880000 ;
+ RECT 643.190000 1801.400000 644.190000 1801.880000 ;
+ RECT 737.320000 1795.960000 738.420000 1796.440000 ;
+ RECT 737.320000 1790.520000 738.420000 1791.000000 ;
+ RECT 737.320000 1785.080000 738.420000 1785.560000 ;
+ RECT 737.320000 1779.640000 738.420000 1780.120000 ;
+ RECT 737.320000 1774.200000 738.420000 1774.680000 ;
+ RECT 692.320000 1795.960000 693.420000 1796.440000 ;
+ RECT 692.320000 1790.520000 693.420000 1791.000000 ;
+ RECT 692.320000 1785.080000 693.420000 1785.560000 ;
+ RECT 692.320000 1779.640000 693.420000 1780.120000 ;
+ RECT 692.320000 1774.200000 693.420000 1774.680000 ;
+ RECT 737.320000 1752.440000 738.420000 1752.920000 ;
+ RECT 737.320000 1757.880000 738.420000 1758.360000 ;
+ RECT 737.320000 1763.320000 738.420000 1763.800000 ;
+ RECT 737.320000 1768.760000 738.420000 1769.240000 ;
+ RECT 692.320000 1752.440000 693.420000 1752.920000 ;
+ RECT 692.320000 1757.880000 693.420000 1758.360000 ;
+ RECT 692.320000 1763.320000 693.420000 1763.800000 ;
+ RECT 692.320000 1768.760000 693.420000 1769.240000 ;
+ RECT 647.320000 1795.960000 648.420000 1796.440000 ;
+ RECT 643.190000 1795.960000 644.190000 1796.440000 ;
+ RECT 647.320000 1790.520000 648.420000 1791.000000 ;
+ RECT 643.190000 1790.520000 644.190000 1791.000000 ;
+ RECT 647.320000 1779.640000 648.420000 1780.120000 ;
+ RECT 643.190000 1779.640000 644.190000 1780.120000 ;
+ RECT 647.320000 1774.200000 648.420000 1774.680000 ;
+ RECT 643.190000 1774.200000 644.190000 1774.680000 ;
+ RECT 647.320000 1785.080000 648.420000 1785.560000 ;
+ RECT 643.190000 1785.080000 644.190000 1785.560000 ;
+ RECT 647.320000 1768.760000 648.420000 1769.240000 ;
+ RECT 643.190000 1768.760000 644.190000 1769.240000 ;
+ RECT 647.320000 1763.320000 648.420000 1763.800000 ;
+ RECT 643.190000 1763.320000 644.190000 1763.800000 ;
+ RECT 647.320000 1757.880000 648.420000 1758.360000 ;
+ RECT 647.320000 1752.440000 648.420000 1752.920000 ;
+ RECT 643.190000 1757.880000 644.190000 1758.360000 ;
+ RECT 643.190000 1752.440000 644.190000 1752.920000 ;
+ RECT 640.360000 1942.800000 840.460000 1943.800000 ;
+ RECT 640.360000 1750.430000 840.460000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 1747.580000 644.190000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 1946.840000 644.190000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 1747.580000 837.630000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 1946.840000 837.630000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1750.430000 641.360000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1750.430000 840.460000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1942.800000 641.360000 1943.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1942.800000 840.460000 1943.800000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'RegFile'
+ PORT
+ LAYER met4 ;
+ RECT 827.320000 1550.170000 828.420000 1743.540000 ;
+ RECT 782.320000 1550.170000 783.420000 1743.540000 ;
+ RECT 836.630000 1547.320000 837.630000 1747.580000 ;
+ RECT 737.320000 1550.170000 738.420000 1743.540000 ;
+ RECT 692.320000 1550.170000 693.420000 1743.540000 ;
+ RECT 647.320000 1550.170000 648.420000 1743.540000 ;
+ RECT 643.190000 1547.320000 644.190000 1747.580000 ;
+ LAYER met3 ;
+ RECT 827.320000 1737.140000 828.420000 1737.620000 ;
+ RECT 836.630000 1737.140000 837.630000 1737.620000 ;
+ RECT 836.630000 1726.260000 837.630000 1726.740000 ;
+ RECT 836.630000 1731.700000 837.630000 1732.180000 ;
+ RECT 827.320000 1731.700000 828.420000 1732.180000 ;
+ RECT 827.320000 1726.260000 828.420000 1726.740000 ;
+ RECT 827.320000 1720.820000 828.420000 1721.300000 ;
+ RECT 827.320000 1715.380000 828.420000 1715.860000 ;
+ RECT 836.630000 1720.820000 837.630000 1721.300000 ;
+ RECT 836.630000 1715.380000 837.630000 1715.860000 ;
+ RECT 827.320000 1699.060000 828.420000 1699.540000 ;
+ RECT 827.320000 1704.500000 828.420000 1704.980000 ;
+ RECT 836.630000 1704.500000 837.630000 1704.980000 ;
+ RECT 836.630000 1699.060000 837.630000 1699.540000 ;
+ RECT 827.320000 1709.940000 828.420000 1710.420000 ;
+ RECT 836.630000 1709.940000 837.630000 1710.420000 ;
+ RECT 782.320000 1737.140000 783.420000 1737.620000 ;
+ RECT 782.320000 1731.700000 783.420000 1732.180000 ;
+ RECT 782.320000 1726.260000 783.420000 1726.740000 ;
+ RECT 782.320000 1720.820000 783.420000 1721.300000 ;
+ RECT 782.320000 1699.060000 783.420000 1699.540000 ;
+ RECT 782.320000 1704.500000 783.420000 1704.980000 ;
+ RECT 782.320000 1709.940000 783.420000 1710.420000 ;
+ RECT 782.320000 1715.380000 783.420000 1715.860000 ;
+ RECT 836.630000 1688.180000 837.630000 1688.660000 ;
+ RECT 836.630000 1693.620000 837.630000 1694.100000 ;
+ RECT 827.320000 1693.620000 828.420000 1694.100000 ;
+ RECT 827.320000 1688.180000 828.420000 1688.660000 ;
+ RECT 827.320000 1682.740000 828.420000 1683.220000 ;
+ RECT 827.320000 1677.300000 828.420000 1677.780000 ;
+ RECT 836.630000 1682.740000 837.630000 1683.220000 ;
+ RECT 836.630000 1677.300000 837.630000 1677.780000 ;
+ RECT 836.630000 1660.980000 837.630000 1661.460000 ;
+ RECT 836.630000 1666.420000 837.630000 1666.900000 ;
+ RECT 836.630000 1671.860000 837.630000 1672.340000 ;
+ RECT 827.320000 1666.420000 828.420000 1666.900000 ;
+ RECT 827.320000 1660.980000 828.420000 1661.460000 ;
+ RECT 827.320000 1671.860000 828.420000 1672.340000 ;
+ RECT 827.320000 1655.540000 828.420000 1656.020000 ;
+ RECT 827.320000 1650.100000 828.420000 1650.580000 ;
+ RECT 836.630000 1655.540000 837.630000 1656.020000 ;
+ RECT 836.630000 1650.100000 837.630000 1650.580000 ;
+ RECT 782.320000 1693.620000 783.420000 1694.100000 ;
+ RECT 782.320000 1688.180000 783.420000 1688.660000 ;
+ RECT 782.320000 1682.740000 783.420000 1683.220000 ;
+ RECT 782.320000 1677.300000 783.420000 1677.780000 ;
+ RECT 782.320000 1666.420000 783.420000 1666.900000 ;
+ RECT 782.320000 1660.980000 783.420000 1661.460000 ;
+ RECT 782.320000 1655.540000 783.420000 1656.020000 ;
+ RECT 782.320000 1650.100000 783.420000 1650.580000 ;
+ RECT 782.320000 1671.860000 783.420000 1672.340000 ;
+ RECT 737.320000 1737.140000 738.420000 1737.620000 ;
+ RECT 737.320000 1731.700000 738.420000 1732.180000 ;
+ RECT 737.320000 1726.260000 738.420000 1726.740000 ;
+ RECT 692.320000 1737.140000 693.420000 1737.620000 ;
+ RECT 692.320000 1731.700000 693.420000 1732.180000 ;
+ RECT 692.320000 1726.260000 693.420000 1726.740000 ;
+ RECT 737.320000 1709.940000 738.420000 1710.420000 ;
+ RECT 737.320000 1704.500000 738.420000 1704.980000 ;
+ RECT 737.320000 1699.060000 738.420000 1699.540000 ;
+ RECT 737.320000 1715.380000 738.420000 1715.860000 ;
+ RECT 737.320000 1720.820000 738.420000 1721.300000 ;
+ RECT 692.320000 1720.820000 693.420000 1721.300000 ;
+ RECT 692.320000 1709.940000 693.420000 1710.420000 ;
+ RECT 692.320000 1704.500000 693.420000 1704.980000 ;
+ RECT 692.320000 1699.060000 693.420000 1699.540000 ;
+ RECT 692.320000 1715.380000 693.420000 1715.860000 ;
+ RECT 647.320000 1737.140000 648.420000 1737.620000 ;
+ RECT 643.190000 1737.140000 644.190000 1737.620000 ;
+ RECT 643.190000 1731.700000 644.190000 1732.180000 ;
+ RECT 647.320000 1731.700000 648.420000 1732.180000 ;
+ RECT 647.320000 1726.260000 648.420000 1726.740000 ;
+ RECT 643.190000 1726.260000 644.190000 1726.740000 ;
+ RECT 647.320000 1720.820000 648.420000 1721.300000 ;
+ RECT 643.190000 1720.820000 644.190000 1721.300000 ;
+ RECT 647.320000 1715.380000 648.420000 1715.860000 ;
+ RECT 643.190000 1715.380000 644.190000 1715.860000 ;
+ RECT 647.320000 1704.500000 648.420000 1704.980000 ;
+ RECT 643.190000 1704.500000 644.190000 1704.980000 ;
+ RECT 647.320000 1699.060000 648.420000 1699.540000 ;
+ RECT 643.190000 1699.060000 644.190000 1699.540000 ;
+ RECT 647.320000 1709.940000 648.420000 1710.420000 ;
+ RECT 643.190000 1709.940000 644.190000 1710.420000 ;
+ RECT 737.320000 1693.620000 738.420000 1694.100000 ;
+ RECT 737.320000 1688.180000 738.420000 1688.660000 ;
+ RECT 737.320000 1682.740000 738.420000 1683.220000 ;
+ RECT 737.320000 1677.300000 738.420000 1677.780000 ;
+ RECT 692.320000 1693.620000 693.420000 1694.100000 ;
+ RECT 692.320000 1688.180000 693.420000 1688.660000 ;
+ RECT 692.320000 1682.740000 693.420000 1683.220000 ;
+ RECT 692.320000 1677.300000 693.420000 1677.780000 ;
+ RECT 737.320000 1666.420000 738.420000 1666.900000 ;
+ RECT 737.320000 1650.100000 738.420000 1650.580000 ;
+ RECT 737.320000 1655.540000 738.420000 1656.020000 ;
+ RECT 737.320000 1660.980000 738.420000 1661.460000 ;
+ RECT 737.320000 1671.860000 738.420000 1672.340000 ;
+ RECT 692.320000 1650.100000 693.420000 1650.580000 ;
+ RECT 692.320000 1655.540000 693.420000 1656.020000 ;
+ RECT 692.320000 1660.980000 693.420000 1661.460000 ;
+ RECT 692.320000 1666.420000 693.420000 1666.900000 ;
+ RECT 692.320000 1671.860000 693.420000 1672.340000 ;
+ RECT 647.320000 1693.620000 648.420000 1694.100000 ;
+ RECT 643.190000 1693.620000 644.190000 1694.100000 ;
+ RECT 647.320000 1688.180000 648.420000 1688.660000 ;
+ RECT 643.190000 1688.180000 644.190000 1688.660000 ;
+ RECT 647.320000 1682.740000 648.420000 1683.220000 ;
+ RECT 643.190000 1682.740000 644.190000 1683.220000 ;
+ RECT 647.320000 1677.300000 648.420000 1677.780000 ;
+ RECT 643.190000 1677.300000 644.190000 1677.780000 ;
+ RECT 647.320000 1671.860000 648.420000 1672.340000 ;
+ RECT 647.320000 1666.420000 648.420000 1666.900000 ;
+ RECT 643.190000 1671.860000 644.190000 1672.340000 ;
+ RECT 643.190000 1666.420000 644.190000 1666.900000 ;
+ RECT 647.320000 1660.980000 648.420000 1661.460000 ;
+ RECT 643.190000 1660.980000 644.190000 1661.460000 ;
+ RECT 647.320000 1655.540000 648.420000 1656.020000 ;
+ RECT 643.190000 1655.540000 644.190000 1656.020000 ;
+ RECT 647.320000 1650.100000 648.420000 1650.580000 ;
+ RECT 643.190000 1650.100000 644.190000 1650.580000 ;
+ RECT 827.320000 1644.660000 828.420000 1645.140000 ;
+ RECT 827.320000 1639.220000 828.420000 1639.700000 ;
+ RECT 836.630000 1644.660000 837.630000 1645.140000 ;
+ RECT 836.630000 1639.220000 837.630000 1639.700000 ;
+ RECT 836.630000 1622.900000 837.630000 1623.380000 ;
+ RECT 836.630000 1628.340000 837.630000 1628.820000 ;
+ RECT 836.630000 1633.780000 837.630000 1634.260000 ;
+ RECT 827.320000 1633.780000 828.420000 1634.260000 ;
+ RECT 827.320000 1628.340000 828.420000 1628.820000 ;
+ RECT 827.320000 1622.900000 828.420000 1623.380000 ;
+ RECT 827.320000 1612.020000 828.420000 1612.500000 ;
+ RECT 827.320000 1617.460000 828.420000 1617.940000 ;
+ RECT 836.630000 1617.460000 837.630000 1617.940000 ;
+ RECT 836.630000 1612.020000 837.630000 1612.500000 ;
+ RECT 836.630000 1601.140000 837.630000 1601.620000 ;
+ RECT 836.630000 1606.580000 837.630000 1607.060000 ;
+ RECT 827.320000 1601.140000 828.420000 1601.620000 ;
+ RECT 827.320000 1606.580000 828.420000 1607.060000 ;
+ RECT 782.320000 1644.660000 783.420000 1645.140000 ;
+ RECT 782.320000 1639.220000 783.420000 1639.700000 ;
+ RECT 782.320000 1633.780000 783.420000 1634.260000 ;
+ RECT 782.320000 1628.340000 783.420000 1628.820000 ;
+ RECT 782.320000 1622.900000 783.420000 1623.380000 ;
+ RECT 782.320000 1601.140000 783.420000 1601.620000 ;
+ RECT 782.320000 1606.580000 783.420000 1607.060000 ;
+ RECT 782.320000 1612.020000 783.420000 1612.500000 ;
+ RECT 782.320000 1617.460000 783.420000 1617.940000 ;
+ RECT 827.320000 1595.700000 828.420000 1596.180000 ;
+ RECT 827.320000 1590.260000 828.420000 1590.740000 ;
+ RECT 836.630000 1595.700000 837.630000 1596.180000 ;
+ RECT 836.630000 1590.260000 837.630000 1590.740000 ;
+ RECT 827.320000 1579.380000 828.420000 1579.860000 ;
+ RECT 827.320000 1573.940000 828.420000 1574.420000 ;
+ RECT 836.630000 1579.380000 837.630000 1579.860000 ;
+ RECT 836.630000 1573.940000 837.630000 1574.420000 ;
+ RECT 827.320000 1584.820000 828.420000 1585.300000 ;
+ RECT 836.630000 1584.820000 837.630000 1585.300000 ;
+ RECT 836.630000 1563.060000 837.630000 1563.540000 ;
+ RECT 836.630000 1568.500000 837.630000 1568.980000 ;
+ RECT 827.320000 1568.500000 828.420000 1568.980000 ;
+ RECT 827.320000 1563.060000 828.420000 1563.540000 ;
+ RECT 827.320000 1557.620000 828.420000 1558.100000 ;
+ RECT 827.320000 1552.180000 828.420000 1552.660000 ;
+ RECT 836.630000 1557.620000 837.630000 1558.100000 ;
+ RECT 836.630000 1552.180000 837.630000 1552.660000 ;
+ RECT 782.320000 1595.700000 783.420000 1596.180000 ;
+ RECT 782.320000 1590.260000 783.420000 1590.740000 ;
+ RECT 782.320000 1584.820000 783.420000 1585.300000 ;
+ RECT 782.320000 1579.380000 783.420000 1579.860000 ;
+ RECT 782.320000 1573.940000 783.420000 1574.420000 ;
+ RECT 782.320000 1568.500000 783.420000 1568.980000 ;
+ RECT 782.320000 1563.060000 783.420000 1563.540000 ;
+ RECT 782.320000 1557.620000 783.420000 1558.100000 ;
+ RECT 782.320000 1552.180000 783.420000 1552.660000 ;
+ RECT 737.320000 1644.660000 738.420000 1645.140000 ;
+ RECT 737.320000 1639.220000 738.420000 1639.700000 ;
+ RECT 737.320000 1633.780000 738.420000 1634.260000 ;
+ RECT 737.320000 1628.340000 738.420000 1628.820000 ;
+ RECT 737.320000 1622.900000 738.420000 1623.380000 ;
+ RECT 692.320000 1644.660000 693.420000 1645.140000 ;
+ RECT 692.320000 1639.220000 693.420000 1639.700000 ;
+ RECT 692.320000 1633.780000 693.420000 1634.260000 ;
+ RECT 692.320000 1628.340000 693.420000 1628.820000 ;
+ RECT 692.320000 1622.900000 693.420000 1623.380000 ;
+ RECT 737.320000 1617.460000 738.420000 1617.940000 ;
+ RECT 737.320000 1612.020000 738.420000 1612.500000 ;
+ RECT 737.320000 1606.580000 738.420000 1607.060000 ;
+ RECT 737.320000 1601.140000 738.420000 1601.620000 ;
+ RECT 692.320000 1612.020000 693.420000 1612.500000 ;
+ RECT 692.320000 1606.580000 693.420000 1607.060000 ;
+ RECT 692.320000 1601.140000 693.420000 1601.620000 ;
+ RECT 692.320000 1617.460000 693.420000 1617.940000 ;
+ RECT 647.320000 1644.660000 648.420000 1645.140000 ;
+ RECT 643.190000 1644.660000 644.190000 1645.140000 ;
+ RECT 647.320000 1639.220000 648.420000 1639.700000 ;
+ RECT 643.190000 1639.220000 644.190000 1639.700000 ;
+ RECT 647.320000 1633.780000 648.420000 1634.260000 ;
+ RECT 643.190000 1633.780000 644.190000 1634.260000 ;
+ RECT 647.320000 1622.900000 648.420000 1623.380000 ;
+ RECT 643.190000 1622.900000 644.190000 1623.380000 ;
+ RECT 643.190000 1628.340000 644.190000 1628.820000 ;
+ RECT 647.320000 1628.340000 648.420000 1628.820000 ;
+ RECT 647.320000 1617.460000 648.420000 1617.940000 ;
+ RECT 643.190000 1617.460000 644.190000 1617.940000 ;
+ RECT 647.320000 1612.020000 648.420000 1612.500000 ;
+ RECT 643.190000 1612.020000 644.190000 1612.500000 ;
+ RECT 647.320000 1606.580000 648.420000 1607.060000 ;
+ RECT 643.190000 1606.580000 644.190000 1607.060000 ;
+ RECT 647.320000 1601.140000 648.420000 1601.620000 ;
+ RECT 643.190000 1601.140000 644.190000 1601.620000 ;
+ RECT 737.320000 1595.700000 738.420000 1596.180000 ;
+ RECT 737.320000 1590.260000 738.420000 1590.740000 ;
+ RECT 737.320000 1584.820000 738.420000 1585.300000 ;
+ RECT 737.320000 1579.380000 738.420000 1579.860000 ;
+ RECT 737.320000 1573.940000 738.420000 1574.420000 ;
+ RECT 692.320000 1595.700000 693.420000 1596.180000 ;
+ RECT 692.320000 1590.260000 693.420000 1590.740000 ;
+ RECT 692.320000 1584.820000 693.420000 1585.300000 ;
+ RECT 692.320000 1579.380000 693.420000 1579.860000 ;
+ RECT 692.320000 1573.940000 693.420000 1574.420000 ;
+ RECT 737.320000 1552.180000 738.420000 1552.660000 ;
+ RECT 737.320000 1557.620000 738.420000 1558.100000 ;
+ RECT 737.320000 1563.060000 738.420000 1563.540000 ;
+ RECT 737.320000 1568.500000 738.420000 1568.980000 ;
+ RECT 692.320000 1552.180000 693.420000 1552.660000 ;
+ RECT 692.320000 1557.620000 693.420000 1558.100000 ;
+ RECT 692.320000 1563.060000 693.420000 1563.540000 ;
+ RECT 692.320000 1568.500000 693.420000 1568.980000 ;
+ RECT 647.320000 1595.700000 648.420000 1596.180000 ;
+ RECT 643.190000 1595.700000 644.190000 1596.180000 ;
+ RECT 647.320000 1590.260000 648.420000 1590.740000 ;
+ RECT 643.190000 1590.260000 644.190000 1590.740000 ;
+ RECT 647.320000 1579.380000 648.420000 1579.860000 ;
+ RECT 643.190000 1579.380000 644.190000 1579.860000 ;
+ RECT 647.320000 1573.940000 648.420000 1574.420000 ;
+ RECT 643.190000 1573.940000 644.190000 1574.420000 ;
+ RECT 647.320000 1584.820000 648.420000 1585.300000 ;
+ RECT 643.190000 1584.820000 644.190000 1585.300000 ;
+ RECT 647.320000 1568.500000 648.420000 1568.980000 ;
+ RECT 643.190000 1568.500000 644.190000 1568.980000 ;
+ RECT 647.320000 1563.060000 648.420000 1563.540000 ;
+ RECT 643.190000 1563.060000 644.190000 1563.540000 ;
+ RECT 647.320000 1557.620000 648.420000 1558.100000 ;
+ RECT 647.320000 1552.180000 648.420000 1552.660000 ;
+ RECT 643.190000 1557.620000 644.190000 1558.100000 ;
+ RECT 643.190000 1552.180000 644.190000 1552.660000 ;
+ RECT 640.360000 1742.540000 840.460000 1743.540000 ;
+ RECT 640.360000 1550.170000 840.460000 1551.170000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 1547.320000 644.190000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 643.190000 1746.580000 644.190000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 1547.320000 837.630000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 836.630000 1746.580000 837.630000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1550.170000 641.360000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1550.170000 840.460000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 640.360000 1742.540000 641.360000 1743.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 839.460000 1742.540000 840.460000 1743.540000 ;
+ END
+# end of P/G pin shape extracted from block 'RegFile'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 3349.660000 844.290000 3379.920000 ;
+ RECT 1036.730000 3349.660000 1037.730000 3379.920000 ;
+ RECT 847.420000 3352.510000 848.520000 3376.560000 ;
+ RECT 892.420000 3352.510000 893.520000 3376.560000 ;
+ RECT 937.420000 3352.510000 938.520000 3376.560000 ;
+ RECT 982.420000 3352.510000 983.520000 3376.560000 ;
+ RECT 1027.420000 3352.510000 1028.520000 3376.560000 ;
+ LAYER met3 ;
+ RECT 1036.730000 3365.400000 1037.730000 3365.880000 ;
+ RECT 1036.730000 3370.840000 1037.730000 3371.320000 ;
+ RECT 1027.420000 3370.840000 1028.520000 3371.320000 ;
+ RECT 1027.420000 3365.400000 1028.520000 3365.880000 ;
+ RECT 982.420000 3365.400000 983.520000 3365.880000 ;
+ RECT 982.420000 3370.840000 983.520000 3371.320000 ;
+ RECT 892.420000 3365.400000 893.520000 3365.880000 ;
+ RECT 937.420000 3365.400000 938.520000 3365.880000 ;
+ RECT 937.420000 3370.840000 938.520000 3371.320000 ;
+ RECT 892.420000 3370.840000 893.520000 3371.320000 ;
+ RECT 843.290000 3365.400000 844.290000 3365.880000 ;
+ RECT 847.420000 3365.400000 848.520000 3365.880000 ;
+ RECT 847.420000 3370.840000 848.520000 3371.320000 ;
+ RECT 843.290000 3370.840000 844.290000 3371.320000 ;
+ RECT 1036.730000 3354.520000 1037.730000 3355.000000 ;
+ RECT 1036.730000 3359.960000 1037.730000 3360.440000 ;
+ RECT 1027.420000 3359.960000 1028.520000 3360.440000 ;
+ RECT 1027.420000 3354.520000 1028.520000 3355.000000 ;
+ RECT 982.420000 3354.520000 983.520000 3355.000000 ;
+ RECT 982.420000 3359.960000 983.520000 3360.440000 ;
+ RECT 892.420000 3354.520000 893.520000 3355.000000 ;
+ RECT 937.420000 3354.520000 938.520000 3355.000000 ;
+ RECT 937.420000 3359.960000 938.520000 3360.440000 ;
+ RECT 892.420000 3359.960000 893.520000 3360.440000 ;
+ RECT 843.290000 3359.960000 844.290000 3360.440000 ;
+ RECT 847.420000 3359.960000 848.520000 3360.440000 ;
+ RECT 843.290000 3354.520000 844.290000 3355.000000 ;
+ RECT 847.420000 3354.520000 848.520000 3355.000000 ;
+ RECT 840.460000 3375.560000 1040.560000 3376.560000 ;
+ RECT 840.460000 3352.510000 1040.560000 3353.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 3349.660000 844.290000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 3378.920000 844.290000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 3349.660000 1037.730000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 3378.920000 1037.730000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 3352.510000 841.460000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 3352.510000 1040.560000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 3375.560000 841.460000 3376.560000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 3375.560000 1040.560000 3376.560000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 1349.910000 1028.520000 1543.280000 ;
+ RECT 982.420000 1349.910000 983.520000 1543.280000 ;
+ RECT 1036.730000 1347.060000 1037.730000 1547.320000 ;
+ RECT 937.420000 1349.910000 938.520000 1543.280000 ;
+ RECT 892.420000 1349.910000 893.520000 1543.280000 ;
+ RECT 847.420000 1349.910000 848.520000 1543.280000 ;
+ RECT 843.290000 1347.060000 844.290000 1547.320000 ;
+ LAYER met3 ;
+ RECT 1027.420000 1536.880000 1028.520000 1537.360000 ;
+ RECT 1036.730000 1536.880000 1037.730000 1537.360000 ;
+ RECT 1036.730000 1526.000000 1037.730000 1526.480000 ;
+ RECT 1036.730000 1531.440000 1037.730000 1531.920000 ;
+ RECT 1027.420000 1531.440000 1028.520000 1531.920000 ;
+ RECT 1027.420000 1526.000000 1028.520000 1526.480000 ;
+ RECT 1027.420000 1520.560000 1028.520000 1521.040000 ;
+ RECT 1027.420000 1515.120000 1028.520000 1515.600000 ;
+ RECT 1036.730000 1520.560000 1037.730000 1521.040000 ;
+ RECT 1036.730000 1515.120000 1037.730000 1515.600000 ;
+ RECT 1027.420000 1498.800000 1028.520000 1499.280000 ;
+ RECT 1027.420000 1504.240000 1028.520000 1504.720000 ;
+ RECT 1036.730000 1504.240000 1037.730000 1504.720000 ;
+ RECT 1036.730000 1498.800000 1037.730000 1499.280000 ;
+ RECT 1027.420000 1509.680000 1028.520000 1510.160000 ;
+ RECT 1036.730000 1509.680000 1037.730000 1510.160000 ;
+ RECT 982.420000 1536.880000 983.520000 1537.360000 ;
+ RECT 982.420000 1531.440000 983.520000 1531.920000 ;
+ RECT 982.420000 1526.000000 983.520000 1526.480000 ;
+ RECT 982.420000 1520.560000 983.520000 1521.040000 ;
+ RECT 982.420000 1498.800000 983.520000 1499.280000 ;
+ RECT 982.420000 1504.240000 983.520000 1504.720000 ;
+ RECT 982.420000 1509.680000 983.520000 1510.160000 ;
+ RECT 982.420000 1515.120000 983.520000 1515.600000 ;
+ RECT 1036.730000 1487.920000 1037.730000 1488.400000 ;
+ RECT 1036.730000 1493.360000 1037.730000 1493.840000 ;
+ RECT 1027.420000 1493.360000 1028.520000 1493.840000 ;
+ RECT 1027.420000 1487.920000 1028.520000 1488.400000 ;
+ RECT 1027.420000 1482.480000 1028.520000 1482.960000 ;
+ RECT 1027.420000 1477.040000 1028.520000 1477.520000 ;
+ RECT 1036.730000 1482.480000 1037.730000 1482.960000 ;
+ RECT 1036.730000 1477.040000 1037.730000 1477.520000 ;
+ RECT 1036.730000 1460.720000 1037.730000 1461.200000 ;
+ RECT 1036.730000 1466.160000 1037.730000 1466.640000 ;
+ RECT 1036.730000 1471.600000 1037.730000 1472.080000 ;
+ RECT 1027.420000 1466.160000 1028.520000 1466.640000 ;
+ RECT 1027.420000 1460.720000 1028.520000 1461.200000 ;
+ RECT 1027.420000 1471.600000 1028.520000 1472.080000 ;
+ RECT 1027.420000 1455.280000 1028.520000 1455.760000 ;
+ RECT 1027.420000 1449.840000 1028.520000 1450.320000 ;
+ RECT 1036.730000 1455.280000 1037.730000 1455.760000 ;
+ RECT 1036.730000 1449.840000 1037.730000 1450.320000 ;
+ RECT 982.420000 1493.360000 983.520000 1493.840000 ;
+ RECT 982.420000 1487.920000 983.520000 1488.400000 ;
+ RECT 982.420000 1482.480000 983.520000 1482.960000 ;
+ RECT 982.420000 1477.040000 983.520000 1477.520000 ;
+ RECT 982.420000 1466.160000 983.520000 1466.640000 ;
+ RECT 982.420000 1460.720000 983.520000 1461.200000 ;
+ RECT 982.420000 1455.280000 983.520000 1455.760000 ;
+ RECT 982.420000 1449.840000 983.520000 1450.320000 ;
+ RECT 982.420000 1471.600000 983.520000 1472.080000 ;
+ RECT 937.420000 1536.880000 938.520000 1537.360000 ;
+ RECT 937.420000 1531.440000 938.520000 1531.920000 ;
+ RECT 937.420000 1526.000000 938.520000 1526.480000 ;
+ RECT 892.420000 1536.880000 893.520000 1537.360000 ;
+ RECT 892.420000 1531.440000 893.520000 1531.920000 ;
+ RECT 892.420000 1526.000000 893.520000 1526.480000 ;
+ RECT 937.420000 1509.680000 938.520000 1510.160000 ;
+ RECT 937.420000 1504.240000 938.520000 1504.720000 ;
+ RECT 937.420000 1498.800000 938.520000 1499.280000 ;
+ RECT 937.420000 1515.120000 938.520000 1515.600000 ;
+ RECT 937.420000 1520.560000 938.520000 1521.040000 ;
+ RECT 892.420000 1520.560000 893.520000 1521.040000 ;
+ RECT 892.420000 1509.680000 893.520000 1510.160000 ;
+ RECT 892.420000 1504.240000 893.520000 1504.720000 ;
+ RECT 892.420000 1498.800000 893.520000 1499.280000 ;
+ RECT 892.420000 1515.120000 893.520000 1515.600000 ;
+ RECT 847.420000 1536.880000 848.520000 1537.360000 ;
+ RECT 843.290000 1536.880000 844.290000 1537.360000 ;
+ RECT 843.290000 1531.440000 844.290000 1531.920000 ;
+ RECT 847.420000 1531.440000 848.520000 1531.920000 ;
+ RECT 847.420000 1526.000000 848.520000 1526.480000 ;
+ RECT 843.290000 1526.000000 844.290000 1526.480000 ;
+ RECT 847.420000 1520.560000 848.520000 1521.040000 ;
+ RECT 843.290000 1520.560000 844.290000 1521.040000 ;
+ RECT 847.420000 1515.120000 848.520000 1515.600000 ;
+ RECT 843.290000 1515.120000 844.290000 1515.600000 ;
+ RECT 847.420000 1504.240000 848.520000 1504.720000 ;
+ RECT 843.290000 1504.240000 844.290000 1504.720000 ;
+ RECT 847.420000 1498.800000 848.520000 1499.280000 ;
+ RECT 843.290000 1498.800000 844.290000 1499.280000 ;
+ RECT 847.420000 1509.680000 848.520000 1510.160000 ;
+ RECT 843.290000 1509.680000 844.290000 1510.160000 ;
+ RECT 937.420000 1493.360000 938.520000 1493.840000 ;
+ RECT 937.420000 1487.920000 938.520000 1488.400000 ;
+ RECT 937.420000 1482.480000 938.520000 1482.960000 ;
+ RECT 937.420000 1477.040000 938.520000 1477.520000 ;
+ RECT 892.420000 1493.360000 893.520000 1493.840000 ;
+ RECT 892.420000 1487.920000 893.520000 1488.400000 ;
+ RECT 892.420000 1482.480000 893.520000 1482.960000 ;
+ RECT 892.420000 1477.040000 893.520000 1477.520000 ;
+ RECT 937.420000 1466.160000 938.520000 1466.640000 ;
+ RECT 937.420000 1449.840000 938.520000 1450.320000 ;
+ RECT 937.420000 1455.280000 938.520000 1455.760000 ;
+ RECT 937.420000 1460.720000 938.520000 1461.200000 ;
+ RECT 937.420000 1471.600000 938.520000 1472.080000 ;
+ RECT 892.420000 1449.840000 893.520000 1450.320000 ;
+ RECT 892.420000 1455.280000 893.520000 1455.760000 ;
+ RECT 892.420000 1460.720000 893.520000 1461.200000 ;
+ RECT 892.420000 1466.160000 893.520000 1466.640000 ;
+ RECT 892.420000 1471.600000 893.520000 1472.080000 ;
+ RECT 847.420000 1493.360000 848.520000 1493.840000 ;
+ RECT 843.290000 1493.360000 844.290000 1493.840000 ;
+ RECT 847.420000 1487.920000 848.520000 1488.400000 ;
+ RECT 843.290000 1487.920000 844.290000 1488.400000 ;
+ RECT 847.420000 1482.480000 848.520000 1482.960000 ;
+ RECT 843.290000 1482.480000 844.290000 1482.960000 ;
+ RECT 847.420000 1477.040000 848.520000 1477.520000 ;
+ RECT 843.290000 1477.040000 844.290000 1477.520000 ;
+ RECT 847.420000 1471.600000 848.520000 1472.080000 ;
+ RECT 847.420000 1466.160000 848.520000 1466.640000 ;
+ RECT 843.290000 1471.600000 844.290000 1472.080000 ;
+ RECT 843.290000 1466.160000 844.290000 1466.640000 ;
+ RECT 847.420000 1460.720000 848.520000 1461.200000 ;
+ RECT 843.290000 1460.720000 844.290000 1461.200000 ;
+ RECT 847.420000 1455.280000 848.520000 1455.760000 ;
+ RECT 843.290000 1455.280000 844.290000 1455.760000 ;
+ RECT 847.420000 1449.840000 848.520000 1450.320000 ;
+ RECT 843.290000 1449.840000 844.290000 1450.320000 ;
+ RECT 1027.420000 1444.400000 1028.520000 1444.880000 ;
+ RECT 1027.420000 1438.960000 1028.520000 1439.440000 ;
+ RECT 1036.730000 1444.400000 1037.730000 1444.880000 ;
+ RECT 1036.730000 1438.960000 1037.730000 1439.440000 ;
+ RECT 1036.730000 1422.640000 1037.730000 1423.120000 ;
+ RECT 1036.730000 1428.080000 1037.730000 1428.560000 ;
+ RECT 1036.730000 1433.520000 1037.730000 1434.000000 ;
+ RECT 1027.420000 1433.520000 1028.520000 1434.000000 ;
+ RECT 1027.420000 1428.080000 1028.520000 1428.560000 ;
+ RECT 1027.420000 1422.640000 1028.520000 1423.120000 ;
+ RECT 1027.420000 1411.760000 1028.520000 1412.240000 ;
+ RECT 1027.420000 1417.200000 1028.520000 1417.680000 ;
+ RECT 1036.730000 1417.200000 1037.730000 1417.680000 ;
+ RECT 1036.730000 1411.760000 1037.730000 1412.240000 ;
+ RECT 1036.730000 1400.880000 1037.730000 1401.360000 ;
+ RECT 1036.730000 1406.320000 1037.730000 1406.800000 ;
+ RECT 1027.420000 1400.880000 1028.520000 1401.360000 ;
+ RECT 1027.420000 1406.320000 1028.520000 1406.800000 ;
+ RECT 982.420000 1444.400000 983.520000 1444.880000 ;
+ RECT 982.420000 1438.960000 983.520000 1439.440000 ;
+ RECT 982.420000 1433.520000 983.520000 1434.000000 ;
+ RECT 982.420000 1428.080000 983.520000 1428.560000 ;
+ RECT 982.420000 1422.640000 983.520000 1423.120000 ;
+ RECT 982.420000 1400.880000 983.520000 1401.360000 ;
+ RECT 982.420000 1406.320000 983.520000 1406.800000 ;
+ RECT 982.420000 1411.760000 983.520000 1412.240000 ;
+ RECT 982.420000 1417.200000 983.520000 1417.680000 ;
+ RECT 1027.420000 1395.440000 1028.520000 1395.920000 ;
+ RECT 1027.420000 1390.000000 1028.520000 1390.480000 ;
+ RECT 1036.730000 1395.440000 1037.730000 1395.920000 ;
+ RECT 1036.730000 1390.000000 1037.730000 1390.480000 ;
+ RECT 1027.420000 1379.120000 1028.520000 1379.600000 ;
+ RECT 1027.420000 1373.680000 1028.520000 1374.160000 ;
+ RECT 1036.730000 1379.120000 1037.730000 1379.600000 ;
+ RECT 1036.730000 1373.680000 1037.730000 1374.160000 ;
+ RECT 1027.420000 1384.560000 1028.520000 1385.040000 ;
+ RECT 1036.730000 1384.560000 1037.730000 1385.040000 ;
+ RECT 1036.730000 1362.800000 1037.730000 1363.280000 ;
+ RECT 1036.730000 1368.240000 1037.730000 1368.720000 ;
+ RECT 1027.420000 1368.240000 1028.520000 1368.720000 ;
+ RECT 1027.420000 1362.800000 1028.520000 1363.280000 ;
+ RECT 1027.420000 1357.360000 1028.520000 1357.840000 ;
+ RECT 1027.420000 1351.920000 1028.520000 1352.400000 ;
+ RECT 1036.730000 1357.360000 1037.730000 1357.840000 ;
+ RECT 1036.730000 1351.920000 1037.730000 1352.400000 ;
+ RECT 982.420000 1395.440000 983.520000 1395.920000 ;
+ RECT 982.420000 1390.000000 983.520000 1390.480000 ;
+ RECT 982.420000 1384.560000 983.520000 1385.040000 ;
+ RECT 982.420000 1379.120000 983.520000 1379.600000 ;
+ RECT 982.420000 1373.680000 983.520000 1374.160000 ;
+ RECT 982.420000 1368.240000 983.520000 1368.720000 ;
+ RECT 982.420000 1362.800000 983.520000 1363.280000 ;
+ RECT 982.420000 1357.360000 983.520000 1357.840000 ;
+ RECT 982.420000 1351.920000 983.520000 1352.400000 ;
+ RECT 937.420000 1444.400000 938.520000 1444.880000 ;
+ RECT 937.420000 1438.960000 938.520000 1439.440000 ;
+ RECT 937.420000 1433.520000 938.520000 1434.000000 ;
+ RECT 937.420000 1428.080000 938.520000 1428.560000 ;
+ RECT 937.420000 1422.640000 938.520000 1423.120000 ;
+ RECT 892.420000 1444.400000 893.520000 1444.880000 ;
+ RECT 892.420000 1438.960000 893.520000 1439.440000 ;
+ RECT 892.420000 1433.520000 893.520000 1434.000000 ;
+ RECT 892.420000 1428.080000 893.520000 1428.560000 ;
+ RECT 892.420000 1422.640000 893.520000 1423.120000 ;
+ RECT 937.420000 1417.200000 938.520000 1417.680000 ;
+ RECT 937.420000 1411.760000 938.520000 1412.240000 ;
+ RECT 937.420000 1406.320000 938.520000 1406.800000 ;
+ RECT 937.420000 1400.880000 938.520000 1401.360000 ;
+ RECT 892.420000 1411.760000 893.520000 1412.240000 ;
+ RECT 892.420000 1406.320000 893.520000 1406.800000 ;
+ RECT 892.420000 1400.880000 893.520000 1401.360000 ;
+ RECT 892.420000 1417.200000 893.520000 1417.680000 ;
+ RECT 847.420000 1444.400000 848.520000 1444.880000 ;
+ RECT 843.290000 1444.400000 844.290000 1444.880000 ;
+ RECT 847.420000 1438.960000 848.520000 1439.440000 ;
+ RECT 843.290000 1438.960000 844.290000 1439.440000 ;
+ RECT 847.420000 1433.520000 848.520000 1434.000000 ;
+ RECT 843.290000 1433.520000 844.290000 1434.000000 ;
+ RECT 847.420000 1422.640000 848.520000 1423.120000 ;
+ RECT 843.290000 1422.640000 844.290000 1423.120000 ;
+ RECT 843.290000 1428.080000 844.290000 1428.560000 ;
+ RECT 847.420000 1428.080000 848.520000 1428.560000 ;
+ RECT 847.420000 1417.200000 848.520000 1417.680000 ;
+ RECT 843.290000 1417.200000 844.290000 1417.680000 ;
+ RECT 847.420000 1411.760000 848.520000 1412.240000 ;
+ RECT 843.290000 1411.760000 844.290000 1412.240000 ;
+ RECT 847.420000 1406.320000 848.520000 1406.800000 ;
+ RECT 843.290000 1406.320000 844.290000 1406.800000 ;
+ RECT 847.420000 1400.880000 848.520000 1401.360000 ;
+ RECT 843.290000 1400.880000 844.290000 1401.360000 ;
+ RECT 937.420000 1395.440000 938.520000 1395.920000 ;
+ RECT 937.420000 1390.000000 938.520000 1390.480000 ;
+ RECT 937.420000 1384.560000 938.520000 1385.040000 ;
+ RECT 937.420000 1379.120000 938.520000 1379.600000 ;
+ RECT 937.420000 1373.680000 938.520000 1374.160000 ;
+ RECT 892.420000 1395.440000 893.520000 1395.920000 ;
+ RECT 892.420000 1390.000000 893.520000 1390.480000 ;
+ RECT 892.420000 1384.560000 893.520000 1385.040000 ;
+ RECT 892.420000 1379.120000 893.520000 1379.600000 ;
+ RECT 892.420000 1373.680000 893.520000 1374.160000 ;
+ RECT 937.420000 1351.920000 938.520000 1352.400000 ;
+ RECT 937.420000 1357.360000 938.520000 1357.840000 ;
+ RECT 937.420000 1362.800000 938.520000 1363.280000 ;
+ RECT 937.420000 1368.240000 938.520000 1368.720000 ;
+ RECT 892.420000 1351.920000 893.520000 1352.400000 ;
+ RECT 892.420000 1357.360000 893.520000 1357.840000 ;
+ RECT 892.420000 1362.800000 893.520000 1363.280000 ;
+ RECT 892.420000 1368.240000 893.520000 1368.720000 ;
+ RECT 847.420000 1395.440000 848.520000 1395.920000 ;
+ RECT 843.290000 1395.440000 844.290000 1395.920000 ;
+ RECT 847.420000 1390.000000 848.520000 1390.480000 ;
+ RECT 843.290000 1390.000000 844.290000 1390.480000 ;
+ RECT 847.420000 1379.120000 848.520000 1379.600000 ;
+ RECT 843.290000 1379.120000 844.290000 1379.600000 ;
+ RECT 847.420000 1373.680000 848.520000 1374.160000 ;
+ RECT 843.290000 1373.680000 844.290000 1374.160000 ;
+ RECT 847.420000 1384.560000 848.520000 1385.040000 ;
+ RECT 843.290000 1384.560000 844.290000 1385.040000 ;
+ RECT 847.420000 1368.240000 848.520000 1368.720000 ;
+ RECT 843.290000 1368.240000 844.290000 1368.720000 ;
+ RECT 847.420000 1362.800000 848.520000 1363.280000 ;
+ RECT 843.290000 1362.800000 844.290000 1363.280000 ;
+ RECT 847.420000 1357.360000 848.520000 1357.840000 ;
+ RECT 847.420000 1351.920000 848.520000 1352.400000 ;
+ RECT 843.290000 1357.360000 844.290000 1357.840000 ;
+ RECT 843.290000 1351.920000 844.290000 1352.400000 ;
+ RECT 840.460000 1542.280000 1040.560000 1543.280000 ;
+ RECT 840.460000 1349.910000 1040.560000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 1347.060000 844.290000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 1546.320000 844.290000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 1347.060000 1037.730000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 1546.320000 1037.730000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1349.910000 841.460000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1349.910000 1040.560000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1542.280000 841.460000 1543.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1542.280000 1040.560000 1543.280000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 1149.650000 1028.520000 1343.020000 ;
+ RECT 982.420000 1149.650000 983.520000 1343.020000 ;
+ RECT 1036.730000 1146.800000 1037.730000 1347.060000 ;
+ RECT 937.420000 1149.650000 938.520000 1343.020000 ;
+ RECT 892.420000 1149.650000 893.520000 1343.020000 ;
+ RECT 847.420000 1149.650000 848.520000 1343.020000 ;
+ RECT 843.290000 1146.800000 844.290000 1347.060000 ;
+ LAYER met3 ;
+ RECT 1027.420000 1336.620000 1028.520000 1337.100000 ;
+ RECT 1036.730000 1336.620000 1037.730000 1337.100000 ;
+ RECT 1036.730000 1325.740000 1037.730000 1326.220000 ;
+ RECT 1036.730000 1331.180000 1037.730000 1331.660000 ;
+ RECT 1027.420000 1331.180000 1028.520000 1331.660000 ;
+ RECT 1027.420000 1325.740000 1028.520000 1326.220000 ;
+ RECT 1027.420000 1320.300000 1028.520000 1320.780000 ;
+ RECT 1027.420000 1314.860000 1028.520000 1315.340000 ;
+ RECT 1036.730000 1320.300000 1037.730000 1320.780000 ;
+ RECT 1036.730000 1314.860000 1037.730000 1315.340000 ;
+ RECT 1027.420000 1298.540000 1028.520000 1299.020000 ;
+ RECT 1027.420000 1303.980000 1028.520000 1304.460000 ;
+ RECT 1036.730000 1303.980000 1037.730000 1304.460000 ;
+ RECT 1036.730000 1298.540000 1037.730000 1299.020000 ;
+ RECT 1027.420000 1309.420000 1028.520000 1309.900000 ;
+ RECT 1036.730000 1309.420000 1037.730000 1309.900000 ;
+ RECT 982.420000 1336.620000 983.520000 1337.100000 ;
+ RECT 982.420000 1331.180000 983.520000 1331.660000 ;
+ RECT 982.420000 1325.740000 983.520000 1326.220000 ;
+ RECT 982.420000 1320.300000 983.520000 1320.780000 ;
+ RECT 982.420000 1298.540000 983.520000 1299.020000 ;
+ RECT 982.420000 1303.980000 983.520000 1304.460000 ;
+ RECT 982.420000 1309.420000 983.520000 1309.900000 ;
+ RECT 982.420000 1314.860000 983.520000 1315.340000 ;
+ RECT 1036.730000 1287.660000 1037.730000 1288.140000 ;
+ RECT 1036.730000 1293.100000 1037.730000 1293.580000 ;
+ RECT 1027.420000 1293.100000 1028.520000 1293.580000 ;
+ RECT 1027.420000 1287.660000 1028.520000 1288.140000 ;
+ RECT 1027.420000 1282.220000 1028.520000 1282.700000 ;
+ RECT 1027.420000 1276.780000 1028.520000 1277.260000 ;
+ RECT 1036.730000 1282.220000 1037.730000 1282.700000 ;
+ RECT 1036.730000 1276.780000 1037.730000 1277.260000 ;
+ RECT 1036.730000 1260.460000 1037.730000 1260.940000 ;
+ RECT 1036.730000 1265.900000 1037.730000 1266.380000 ;
+ RECT 1036.730000 1271.340000 1037.730000 1271.820000 ;
+ RECT 1027.420000 1265.900000 1028.520000 1266.380000 ;
+ RECT 1027.420000 1260.460000 1028.520000 1260.940000 ;
+ RECT 1027.420000 1271.340000 1028.520000 1271.820000 ;
+ RECT 1027.420000 1255.020000 1028.520000 1255.500000 ;
+ RECT 1027.420000 1249.580000 1028.520000 1250.060000 ;
+ RECT 1036.730000 1255.020000 1037.730000 1255.500000 ;
+ RECT 1036.730000 1249.580000 1037.730000 1250.060000 ;
+ RECT 982.420000 1293.100000 983.520000 1293.580000 ;
+ RECT 982.420000 1287.660000 983.520000 1288.140000 ;
+ RECT 982.420000 1282.220000 983.520000 1282.700000 ;
+ RECT 982.420000 1276.780000 983.520000 1277.260000 ;
+ RECT 982.420000 1265.900000 983.520000 1266.380000 ;
+ RECT 982.420000 1260.460000 983.520000 1260.940000 ;
+ RECT 982.420000 1255.020000 983.520000 1255.500000 ;
+ RECT 982.420000 1249.580000 983.520000 1250.060000 ;
+ RECT 982.420000 1271.340000 983.520000 1271.820000 ;
+ RECT 937.420000 1336.620000 938.520000 1337.100000 ;
+ RECT 937.420000 1331.180000 938.520000 1331.660000 ;
+ RECT 937.420000 1325.740000 938.520000 1326.220000 ;
+ RECT 892.420000 1336.620000 893.520000 1337.100000 ;
+ RECT 892.420000 1331.180000 893.520000 1331.660000 ;
+ RECT 892.420000 1325.740000 893.520000 1326.220000 ;
+ RECT 937.420000 1309.420000 938.520000 1309.900000 ;
+ RECT 937.420000 1303.980000 938.520000 1304.460000 ;
+ RECT 937.420000 1298.540000 938.520000 1299.020000 ;
+ RECT 937.420000 1314.860000 938.520000 1315.340000 ;
+ RECT 937.420000 1320.300000 938.520000 1320.780000 ;
+ RECT 892.420000 1320.300000 893.520000 1320.780000 ;
+ RECT 892.420000 1309.420000 893.520000 1309.900000 ;
+ RECT 892.420000 1303.980000 893.520000 1304.460000 ;
+ RECT 892.420000 1298.540000 893.520000 1299.020000 ;
+ RECT 892.420000 1314.860000 893.520000 1315.340000 ;
+ RECT 847.420000 1336.620000 848.520000 1337.100000 ;
+ RECT 843.290000 1336.620000 844.290000 1337.100000 ;
+ RECT 843.290000 1331.180000 844.290000 1331.660000 ;
+ RECT 847.420000 1331.180000 848.520000 1331.660000 ;
+ RECT 847.420000 1325.740000 848.520000 1326.220000 ;
+ RECT 843.290000 1325.740000 844.290000 1326.220000 ;
+ RECT 847.420000 1320.300000 848.520000 1320.780000 ;
+ RECT 843.290000 1320.300000 844.290000 1320.780000 ;
+ RECT 847.420000 1314.860000 848.520000 1315.340000 ;
+ RECT 843.290000 1314.860000 844.290000 1315.340000 ;
+ RECT 847.420000 1303.980000 848.520000 1304.460000 ;
+ RECT 843.290000 1303.980000 844.290000 1304.460000 ;
+ RECT 847.420000 1298.540000 848.520000 1299.020000 ;
+ RECT 843.290000 1298.540000 844.290000 1299.020000 ;
+ RECT 847.420000 1309.420000 848.520000 1309.900000 ;
+ RECT 843.290000 1309.420000 844.290000 1309.900000 ;
+ RECT 937.420000 1293.100000 938.520000 1293.580000 ;
+ RECT 937.420000 1287.660000 938.520000 1288.140000 ;
+ RECT 937.420000 1282.220000 938.520000 1282.700000 ;
+ RECT 937.420000 1276.780000 938.520000 1277.260000 ;
+ RECT 892.420000 1293.100000 893.520000 1293.580000 ;
+ RECT 892.420000 1287.660000 893.520000 1288.140000 ;
+ RECT 892.420000 1282.220000 893.520000 1282.700000 ;
+ RECT 892.420000 1276.780000 893.520000 1277.260000 ;
+ RECT 937.420000 1265.900000 938.520000 1266.380000 ;
+ RECT 937.420000 1249.580000 938.520000 1250.060000 ;
+ RECT 937.420000 1255.020000 938.520000 1255.500000 ;
+ RECT 937.420000 1260.460000 938.520000 1260.940000 ;
+ RECT 937.420000 1271.340000 938.520000 1271.820000 ;
+ RECT 892.420000 1249.580000 893.520000 1250.060000 ;
+ RECT 892.420000 1255.020000 893.520000 1255.500000 ;
+ RECT 892.420000 1260.460000 893.520000 1260.940000 ;
+ RECT 892.420000 1265.900000 893.520000 1266.380000 ;
+ RECT 892.420000 1271.340000 893.520000 1271.820000 ;
+ RECT 847.420000 1293.100000 848.520000 1293.580000 ;
+ RECT 843.290000 1293.100000 844.290000 1293.580000 ;
+ RECT 847.420000 1287.660000 848.520000 1288.140000 ;
+ RECT 843.290000 1287.660000 844.290000 1288.140000 ;
+ RECT 847.420000 1282.220000 848.520000 1282.700000 ;
+ RECT 843.290000 1282.220000 844.290000 1282.700000 ;
+ RECT 847.420000 1276.780000 848.520000 1277.260000 ;
+ RECT 843.290000 1276.780000 844.290000 1277.260000 ;
+ RECT 847.420000 1271.340000 848.520000 1271.820000 ;
+ RECT 847.420000 1265.900000 848.520000 1266.380000 ;
+ RECT 843.290000 1271.340000 844.290000 1271.820000 ;
+ RECT 843.290000 1265.900000 844.290000 1266.380000 ;
+ RECT 847.420000 1260.460000 848.520000 1260.940000 ;
+ RECT 843.290000 1260.460000 844.290000 1260.940000 ;
+ RECT 847.420000 1255.020000 848.520000 1255.500000 ;
+ RECT 843.290000 1255.020000 844.290000 1255.500000 ;
+ RECT 847.420000 1249.580000 848.520000 1250.060000 ;
+ RECT 843.290000 1249.580000 844.290000 1250.060000 ;
+ RECT 1027.420000 1244.140000 1028.520000 1244.620000 ;
+ RECT 1027.420000 1238.700000 1028.520000 1239.180000 ;
+ RECT 1036.730000 1244.140000 1037.730000 1244.620000 ;
+ RECT 1036.730000 1238.700000 1037.730000 1239.180000 ;
+ RECT 1036.730000 1222.380000 1037.730000 1222.860000 ;
+ RECT 1036.730000 1227.820000 1037.730000 1228.300000 ;
+ RECT 1036.730000 1233.260000 1037.730000 1233.740000 ;
+ RECT 1027.420000 1233.260000 1028.520000 1233.740000 ;
+ RECT 1027.420000 1227.820000 1028.520000 1228.300000 ;
+ RECT 1027.420000 1222.380000 1028.520000 1222.860000 ;
+ RECT 1027.420000 1211.500000 1028.520000 1211.980000 ;
+ RECT 1027.420000 1216.940000 1028.520000 1217.420000 ;
+ RECT 1036.730000 1216.940000 1037.730000 1217.420000 ;
+ RECT 1036.730000 1211.500000 1037.730000 1211.980000 ;
+ RECT 1036.730000 1200.620000 1037.730000 1201.100000 ;
+ RECT 1036.730000 1206.060000 1037.730000 1206.540000 ;
+ RECT 1027.420000 1200.620000 1028.520000 1201.100000 ;
+ RECT 1027.420000 1206.060000 1028.520000 1206.540000 ;
+ RECT 982.420000 1244.140000 983.520000 1244.620000 ;
+ RECT 982.420000 1238.700000 983.520000 1239.180000 ;
+ RECT 982.420000 1233.260000 983.520000 1233.740000 ;
+ RECT 982.420000 1227.820000 983.520000 1228.300000 ;
+ RECT 982.420000 1222.380000 983.520000 1222.860000 ;
+ RECT 982.420000 1200.620000 983.520000 1201.100000 ;
+ RECT 982.420000 1206.060000 983.520000 1206.540000 ;
+ RECT 982.420000 1211.500000 983.520000 1211.980000 ;
+ RECT 982.420000 1216.940000 983.520000 1217.420000 ;
+ RECT 1027.420000 1195.180000 1028.520000 1195.660000 ;
+ RECT 1027.420000 1189.740000 1028.520000 1190.220000 ;
+ RECT 1036.730000 1195.180000 1037.730000 1195.660000 ;
+ RECT 1036.730000 1189.740000 1037.730000 1190.220000 ;
+ RECT 1027.420000 1178.860000 1028.520000 1179.340000 ;
+ RECT 1027.420000 1173.420000 1028.520000 1173.900000 ;
+ RECT 1036.730000 1178.860000 1037.730000 1179.340000 ;
+ RECT 1036.730000 1173.420000 1037.730000 1173.900000 ;
+ RECT 1027.420000 1184.300000 1028.520000 1184.780000 ;
+ RECT 1036.730000 1184.300000 1037.730000 1184.780000 ;
+ RECT 1036.730000 1162.540000 1037.730000 1163.020000 ;
+ RECT 1036.730000 1167.980000 1037.730000 1168.460000 ;
+ RECT 1027.420000 1167.980000 1028.520000 1168.460000 ;
+ RECT 1027.420000 1162.540000 1028.520000 1163.020000 ;
+ RECT 1027.420000 1157.100000 1028.520000 1157.580000 ;
+ RECT 1027.420000 1151.660000 1028.520000 1152.140000 ;
+ RECT 1036.730000 1157.100000 1037.730000 1157.580000 ;
+ RECT 1036.730000 1151.660000 1037.730000 1152.140000 ;
+ RECT 982.420000 1195.180000 983.520000 1195.660000 ;
+ RECT 982.420000 1189.740000 983.520000 1190.220000 ;
+ RECT 982.420000 1184.300000 983.520000 1184.780000 ;
+ RECT 982.420000 1178.860000 983.520000 1179.340000 ;
+ RECT 982.420000 1173.420000 983.520000 1173.900000 ;
+ RECT 982.420000 1167.980000 983.520000 1168.460000 ;
+ RECT 982.420000 1162.540000 983.520000 1163.020000 ;
+ RECT 982.420000 1157.100000 983.520000 1157.580000 ;
+ RECT 982.420000 1151.660000 983.520000 1152.140000 ;
+ RECT 937.420000 1244.140000 938.520000 1244.620000 ;
+ RECT 937.420000 1238.700000 938.520000 1239.180000 ;
+ RECT 937.420000 1233.260000 938.520000 1233.740000 ;
+ RECT 937.420000 1227.820000 938.520000 1228.300000 ;
+ RECT 937.420000 1222.380000 938.520000 1222.860000 ;
+ RECT 892.420000 1244.140000 893.520000 1244.620000 ;
+ RECT 892.420000 1238.700000 893.520000 1239.180000 ;
+ RECT 892.420000 1233.260000 893.520000 1233.740000 ;
+ RECT 892.420000 1227.820000 893.520000 1228.300000 ;
+ RECT 892.420000 1222.380000 893.520000 1222.860000 ;
+ RECT 937.420000 1216.940000 938.520000 1217.420000 ;
+ RECT 937.420000 1211.500000 938.520000 1211.980000 ;
+ RECT 937.420000 1206.060000 938.520000 1206.540000 ;
+ RECT 937.420000 1200.620000 938.520000 1201.100000 ;
+ RECT 892.420000 1211.500000 893.520000 1211.980000 ;
+ RECT 892.420000 1206.060000 893.520000 1206.540000 ;
+ RECT 892.420000 1200.620000 893.520000 1201.100000 ;
+ RECT 892.420000 1216.940000 893.520000 1217.420000 ;
+ RECT 847.420000 1244.140000 848.520000 1244.620000 ;
+ RECT 843.290000 1244.140000 844.290000 1244.620000 ;
+ RECT 847.420000 1238.700000 848.520000 1239.180000 ;
+ RECT 843.290000 1238.700000 844.290000 1239.180000 ;
+ RECT 847.420000 1233.260000 848.520000 1233.740000 ;
+ RECT 843.290000 1233.260000 844.290000 1233.740000 ;
+ RECT 847.420000 1222.380000 848.520000 1222.860000 ;
+ RECT 843.290000 1222.380000 844.290000 1222.860000 ;
+ RECT 843.290000 1227.820000 844.290000 1228.300000 ;
+ RECT 847.420000 1227.820000 848.520000 1228.300000 ;
+ RECT 847.420000 1216.940000 848.520000 1217.420000 ;
+ RECT 843.290000 1216.940000 844.290000 1217.420000 ;
+ RECT 847.420000 1211.500000 848.520000 1211.980000 ;
+ RECT 843.290000 1211.500000 844.290000 1211.980000 ;
+ RECT 847.420000 1206.060000 848.520000 1206.540000 ;
+ RECT 843.290000 1206.060000 844.290000 1206.540000 ;
+ RECT 847.420000 1200.620000 848.520000 1201.100000 ;
+ RECT 843.290000 1200.620000 844.290000 1201.100000 ;
+ RECT 937.420000 1195.180000 938.520000 1195.660000 ;
+ RECT 937.420000 1189.740000 938.520000 1190.220000 ;
+ RECT 937.420000 1184.300000 938.520000 1184.780000 ;
+ RECT 937.420000 1178.860000 938.520000 1179.340000 ;
+ RECT 937.420000 1173.420000 938.520000 1173.900000 ;
+ RECT 892.420000 1195.180000 893.520000 1195.660000 ;
+ RECT 892.420000 1189.740000 893.520000 1190.220000 ;
+ RECT 892.420000 1184.300000 893.520000 1184.780000 ;
+ RECT 892.420000 1178.860000 893.520000 1179.340000 ;
+ RECT 892.420000 1173.420000 893.520000 1173.900000 ;
+ RECT 937.420000 1151.660000 938.520000 1152.140000 ;
+ RECT 937.420000 1157.100000 938.520000 1157.580000 ;
+ RECT 937.420000 1162.540000 938.520000 1163.020000 ;
+ RECT 937.420000 1167.980000 938.520000 1168.460000 ;
+ RECT 892.420000 1151.660000 893.520000 1152.140000 ;
+ RECT 892.420000 1157.100000 893.520000 1157.580000 ;
+ RECT 892.420000 1162.540000 893.520000 1163.020000 ;
+ RECT 892.420000 1167.980000 893.520000 1168.460000 ;
+ RECT 847.420000 1195.180000 848.520000 1195.660000 ;
+ RECT 843.290000 1195.180000 844.290000 1195.660000 ;
+ RECT 847.420000 1189.740000 848.520000 1190.220000 ;
+ RECT 843.290000 1189.740000 844.290000 1190.220000 ;
+ RECT 847.420000 1178.860000 848.520000 1179.340000 ;
+ RECT 843.290000 1178.860000 844.290000 1179.340000 ;
+ RECT 847.420000 1173.420000 848.520000 1173.900000 ;
+ RECT 843.290000 1173.420000 844.290000 1173.900000 ;
+ RECT 847.420000 1184.300000 848.520000 1184.780000 ;
+ RECT 843.290000 1184.300000 844.290000 1184.780000 ;
+ RECT 847.420000 1167.980000 848.520000 1168.460000 ;
+ RECT 843.290000 1167.980000 844.290000 1168.460000 ;
+ RECT 847.420000 1162.540000 848.520000 1163.020000 ;
+ RECT 843.290000 1162.540000 844.290000 1163.020000 ;
+ RECT 847.420000 1157.100000 848.520000 1157.580000 ;
+ RECT 847.420000 1151.660000 848.520000 1152.140000 ;
+ RECT 843.290000 1157.100000 844.290000 1157.580000 ;
+ RECT 843.290000 1151.660000 844.290000 1152.140000 ;
+ RECT 840.460000 1342.020000 1040.560000 1343.020000 ;
+ RECT 840.460000 1149.650000 1040.560000 1150.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 1146.800000 844.290000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 1346.060000 844.290000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 1146.800000 1037.730000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 1346.060000 1037.730000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1149.650000 841.460000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1149.650000 1040.560000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1342.020000 841.460000 1343.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1342.020000 1040.560000 1343.020000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 949.390000 1028.520000 1142.760000 ;
+ RECT 982.420000 949.390000 983.520000 1142.760000 ;
+ RECT 1036.730000 946.540000 1037.730000 1146.800000 ;
+ RECT 937.420000 949.390000 938.520000 1142.760000 ;
+ RECT 892.420000 949.390000 893.520000 1142.760000 ;
+ RECT 847.420000 949.390000 848.520000 1142.760000 ;
+ RECT 843.290000 946.540000 844.290000 1146.800000 ;
+ LAYER met3 ;
+ RECT 1027.420000 1136.360000 1028.520000 1136.840000 ;
+ RECT 1036.730000 1136.360000 1037.730000 1136.840000 ;
+ RECT 1036.730000 1125.480000 1037.730000 1125.960000 ;
+ RECT 1036.730000 1130.920000 1037.730000 1131.400000 ;
+ RECT 1027.420000 1130.920000 1028.520000 1131.400000 ;
+ RECT 1027.420000 1125.480000 1028.520000 1125.960000 ;
+ RECT 1027.420000 1120.040000 1028.520000 1120.520000 ;
+ RECT 1027.420000 1114.600000 1028.520000 1115.080000 ;
+ RECT 1036.730000 1120.040000 1037.730000 1120.520000 ;
+ RECT 1036.730000 1114.600000 1037.730000 1115.080000 ;
+ RECT 1027.420000 1098.280000 1028.520000 1098.760000 ;
+ RECT 1027.420000 1103.720000 1028.520000 1104.200000 ;
+ RECT 1036.730000 1103.720000 1037.730000 1104.200000 ;
+ RECT 1036.730000 1098.280000 1037.730000 1098.760000 ;
+ RECT 1027.420000 1109.160000 1028.520000 1109.640000 ;
+ RECT 1036.730000 1109.160000 1037.730000 1109.640000 ;
+ RECT 982.420000 1136.360000 983.520000 1136.840000 ;
+ RECT 982.420000 1130.920000 983.520000 1131.400000 ;
+ RECT 982.420000 1125.480000 983.520000 1125.960000 ;
+ RECT 982.420000 1120.040000 983.520000 1120.520000 ;
+ RECT 982.420000 1098.280000 983.520000 1098.760000 ;
+ RECT 982.420000 1103.720000 983.520000 1104.200000 ;
+ RECT 982.420000 1109.160000 983.520000 1109.640000 ;
+ RECT 982.420000 1114.600000 983.520000 1115.080000 ;
+ RECT 1036.730000 1087.400000 1037.730000 1087.880000 ;
+ RECT 1036.730000 1092.840000 1037.730000 1093.320000 ;
+ RECT 1027.420000 1092.840000 1028.520000 1093.320000 ;
+ RECT 1027.420000 1087.400000 1028.520000 1087.880000 ;
+ RECT 1027.420000 1081.960000 1028.520000 1082.440000 ;
+ RECT 1027.420000 1076.520000 1028.520000 1077.000000 ;
+ RECT 1036.730000 1081.960000 1037.730000 1082.440000 ;
+ RECT 1036.730000 1076.520000 1037.730000 1077.000000 ;
+ RECT 1036.730000 1060.200000 1037.730000 1060.680000 ;
+ RECT 1036.730000 1065.640000 1037.730000 1066.120000 ;
+ RECT 1036.730000 1071.080000 1037.730000 1071.560000 ;
+ RECT 1027.420000 1065.640000 1028.520000 1066.120000 ;
+ RECT 1027.420000 1060.200000 1028.520000 1060.680000 ;
+ RECT 1027.420000 1071.080000 1028.520000 1071.560000 ;
+ RECT 1027.420000 1054.760000 1028.520000 1055.240000 ;
+ RECT 1027.420000 1049.320000 1028.520000 1049.800000 ;
+ RECT 1036.730000 1054.760000 1037.730000 1055.240000 ;
+ RECT 1036.730000 1049.320000 1037.730000 1049.800000 ;
+ RECT 982.420000 1092.840000 983.520000 1093.320000 ;
+ RECT 982.420000 1087.400000 983.520000 1087.880000 ;
+ RECT 982.420000 1081.960000 983.520000 1082.440000 ;
+ RECT 982.420000 1076.520000 983.520000 1077.000000 ;
+ RECT 982.420000 1065.640000 983.520000 1066.120000 ;
+ RECT 982.420000 1060.200000 983.520000 1060.680000 ;
+ RECT 982.420000 1054.760000 983.520000 1055.240000 ;
+ RECT 982.420000 1049.320000 983.520000 1049.800000 ;
+ RECT 982.420000 1071.080000 983.520000 1071.560000 ;
+ RECT 937.420000 1136.360000 938.520000 1136.840000 ;
+ RECT 937.420000 1130.920000 938.520000 1131.400000 ;
+ RECT 937.420000 1125.480000 938.520000 1125.960000 ;
+ RECT 892.420000 1136.360000 893.520000 1136.840000 ;
+ RECT 892.420000 1130.920000 893.520000 1131.400000 ;
+ RECT 892.420000 1125.480000 893.520000 1125.960000 ;
+ RECT 937.420000 1109.160000 938.520000 1109.640000 ;
+ RECT 937.420000 1103.720000 938.520000 1104.200000 ;
+ RECT 937.420000 1098.280000 938.520000 1098.760000 ;
+ RECT 937.420000 1114.600000 938.520000 1115.080000 ;
+ RECT 937.420000 1120.040000 938.520000 1120.520000 ;
+ RECT 892.420000 1120.040000 893.520000 1120.520000 ;
+ RECT 892.420000 1109.160000 893.520000 1109.640000 ;
+ RECT 892.420000 1103.720000 893.520000 1104.200000 ;
+ RECT 892.420000 1098.280000 893.520000 1098.760000 ;
+ RECT 892.420000 1114.600000 893.520000 1115.080000 ;
+ RECT 847.420000 1136.360000 848.520000 1136.840000 ;
+ RECT 843.290000 1136.360000 844.290000 1136.840000 ;
+ RECT 843.290000 1130.920000 844.290000 1131.400000 ;
+ RECT 847.420000 1130.920000 848.520000 1131.400000 ;
+ RECT 847.420000 1125.480000 848.520000 1125.960000 ;
+ RECT 843.290000 1125.480000 844.290000 1125.960000 ;
+ RECT 847.420000 1120.040000 848.520000 1120.520000 ;
+ RECT 843.290000 1120.040000 844.290000 1120.520000 ;
+ RECT 847.420000 1114.600000 848.520000 1115.080000 ;
+ RECT 843.290000 1114.600000 844.290000 1115.080000 ;
+ RECT 847.420000 1103.720000 848.520000 1104.200000 ;
+ RECT 843.290000 1103.720000 844.290000 1104.200000 ;
+ RECT 847.420000 1098.280000 848.520000 1098.760000 ;
+ RECT 843.290000 1098.280000 844.290000 1098.760000 ;
+ RECT 847.420000 1109.160000 848.520000 1109.640000 ;
+ RECT 843.290000 1109.160000 844.290000 1109.640000 ;
+ RECT 937.420000 1092.840000 938.520000 1093.320000 ;
+ RECT 937.420000 1087.400000 938.520000 1087.880000 ;
+ RECT 937.420000 1081.960000 938.520000 1082.440000 ;
+ RECT 937.420000 1076.520000 938.520000 1077.000000 ;
+ RECT 892.420000 1092.840000 893.520000 1093.320000 ;
+ RECT 892.420000 1087.400000 893.520000 1087.880000 ;
+ RECT 892.420000 1081.960000 893.520000 1082.440000 ;
+ RECT 892.420000 1076.520000 893.520000 1077.000000 ;
+ RECT 937.420000 1065.640000 938.520000 1066.120000 ;
+ RECT 937.420000 1049.320000 938.520000 1049.800000 ;
+ RECT 937.420000 1054.760000 938.520000 1055.240000 ;
+ RECT 937.420000 1060.200000 938.520000 1060.680000 ;
+ RECT 937.420000 1071.080000 938.520000 1071.560000 ;
+ RECT 892.420000 1049.320000 893.520000 1049.800000 ;
+ RECT 892.420000 1054.760000 893.520000 1055.240000 ;
+ RECT 892.420000 1060.200000 893.520000 1060.680000 ;
+ RECT 892.420000 1065.640000 893.520000 1066.120000 ;
+ RECT 892.420000 1071.080000 893.520000 1071.560000 ;
+ RECT 847.420000 1092.840000 848.520000 1093.320000 ;
+ RECT 843.290000 1092.840000 844.290000 1093.320000 ;
+ RECT 847.420000 1087.400000 848.520000 1087.880000 ;
+ RECT 843.290000 1087.400000 844.290000 1087.880000 ;
+ RECT 847.420000 1081.960000 848.520000 1082.440000 ;
+ RECT 843.290000 1081.960000 844.290000 1082.440000 ;
+ RECT 847.420000 1076.520000 848.520000 1077.000000 ;
+ RECT 843.290000 1076.520000 844.290000 1077.000000 ;
+ RECT 847.420000 1071.080000 848.520000 1071.560000 ;
+ RECT 847.420000 1065.640000 848.520000 1066.120000 ;
+ RECT 843.290000 1071.080000 844.290000 1071.560000 ;
+ RECT 843.290000 1065.640000 844.290000 1066.120000 ;
+ RECT 847.420000 1060.200000 848.520000 1060.680000 ;
+ RECT 843.290000 1060.200000 844.290000 1060.680000 ;
+ RECT 847.420000 1054.760000 848.520000 1055.240000 ;
+ RECT 843.290000 1054.760000 844.290000 1055.240000 ;
+ RECT 847.420000 1049.320000 848.520000 1049.800000 ;
+ RECT 843.290000 1049.320000 844.290000 1049.800000 ;
+ RECT 1027.420000 1043.880000 1028.520000 1044.360000 ;
+ RECT 1027.420000 1038.440000 1028.520000 1038.920000 ;
+ RECT 1036.730000 1043.880000 1037.730000 1044.360000 ;
+ RECT 1036.730000 1038.440000 1037.730000 1038.920000 ;
+ RECT 1036.730000 1022.120000 1037.730000 1022.600000 ;
+ RECT 1036.730000 1027.560000 1037.730000 1028.040000 ;
+ RECT 1036.730000 1033.000000 1037.730000 1033.480000 ;
+ RECT 1027.420000 1033.000000 1028.520000 1033.480000 ;
+ RECT 1027.420000 1027.560000 1028.520000 1028.040000 ;
+ RECT 1027.420000 1022.120000 1028.520000 1022.600000 ;
+ RECT 1027.420000 1011.240000 1028.520000 1011.720000 ;
+ RECT 1027.420000 1016.680000 1028.520000 1017.160000 ;
+ RECT 1036.730000 1016.680000 1037.730000 1017.160000 ;
+ RECT 1036.730000 1011.240000 1037.730000 1011.720000 ;
+ RECT 1036.730000 1000.360000 1037.730000 1000.840000 ;
+ RECT 1036.730000 1005.800000 1037.730000 1006.280000 ;
+ RECT 1027.420000 1000.360000 1028.520000 1000.840000 ;
+ RECT 1027.420000 1005.800000 1028.520000 1006.280000 ;
+ RECT 982.420000 1043.880000 983.520000 1044.360000 ;
+ RECT 982.420000 1038.440000 983.520000 1038.920000 ;
+ RECT 982.420000 1033.000000 983.520000 1033.480000 ;
+ RECT 982.420000 1027.560000 983.520000 1028.040000 ;
+ RECT 982.420000 1022.120000 983.520000 1022.600000 ;
+ RECT 982.420000 1000.360000 983.520000 1000.840000 ;
+ RECT 982.420000 1005.800000 983.520000 1006.280000 ;
+ RECT 982.420000 1011.240000 983.520000 1011.720000 ;
+ RECT 982.420000 1016.680000 983.520000 1017.160000 ;
+ RECT 1027.420000 994.920000 1028.520000 995.400000 ;
+ RECT 1027.420000 989.480000 1028.520000 989.960000 ;
+ RECT 1036.730000 994.920000 1037.730000 995.400000 ;
+ RECT 1036.730000 989.480000 1037.730000 989.960000 ;
+ RECT 1027.420000 978.600000 1028.520000 979.080000 ;
+ RECT 1027.420000 973.160000 1028.520000 973.640000 ;
+ RECT 1036.730000 978.600000 1037.730000 979.080000 ;
+ RECT 1036.730000 973.160000 1037.730000 973.640000 ;
+ RECT 1027.420000 984.040000 1028.520000 984.520000 ;
+ RECT 1036.730000 984.040000 1037.730000 984.520000 ;
+ RECT 1036.730000 962.280000 1037.730000 962.760000 ;
+ RECT 1036.730000 967.720000 1037.730000 968.200000 ;
+ RECT 1027.420000 967.720000 1028.520000 968.200000 ;
+ RECT 1027.420000 962.280000 1028.520000 962.760000 ;
+ RECT 1027.420000 956.840000 1028.520000 957.320000 ;
+ RECT 1027.420000 951.400000 1028.520000 951.880000 ;
+ RECT 1036.730000 956.840000 1037.730000 957.320000 ;
+ RECT 1036.730000 951.400000 1037.730000 951.880000 ;
+ RECT 982.420000 994.920000 983.520000 995.400000 ;
+ RECT 982.420000 989.480000 983.520000 989.960000 ;
+ RECT 982.420000 984.040000 983.520000 984.520000 ;
+ RECT 982.420000 978.600000 983.520000 979.080000 ;
+ RECT 982.420000 973.160000 983.520000 973.640000 ;
+ RECT 982.420000 967.720000 983.520000 968.200000 ;
+ RECT 982.420000 962.280000 983.520000 962.760000 ;
+ RECT 982.420000 956.840000 983.520000 957.320000 ;
+ RECT 982.420000 951.400000 983.520000 951.880000 ;
+ RECT 937.420000 1043.880000 938.520000 1044.360000 ;
+ RECT 937.420000 1038.440000 938.520000 1038.920000 ;
+ RECT 937.420000 1033.000000 938.520000 1033.480000 ;
+ RECT 937.420000 1027.560000 938.520000 1028.040000 ;
+ RECT 937.420000 1022.120000 938.520000 1022.600000 ;
+ RECT 892.420000 1043.880000 893.520000 1044.360000 ;
+ RECT 892.420000 1038.440000 893.520000 1038.920000 ;
+ RECT 892.420000 1033.000000 893.520000 1033.480000 ;
+ RECT 892.420000 1027.560000 893.520000 1028.040000 ;
+ RECT 892.420000 1022.120000 893.520000 1022.600000 ;
+ RECT 937.420000 1016.680000 938.520000 1017.160000 ;
+ RECT 937.420000 1011.240000 938.520000 1011.720000 ;
+ RECT 937.420000 1005.800000 938.520000 1006.280000 ;
+ RECT 937.420000 1000.360000 938.520000 1000.840000 ;
+ RECT 892.420000 1011.240000 893.520000 1011.720000 ;
+ RECT 892.420000 1005.800000 893.520000 1006.280000 ;
+ RECT 892.420000 1000.360000 893.520000 1000.840000 ;
+ RECT 892.420000 1016.680000 893.520000 1017.160000 ;
+ RECT 847.420000 1043.880000 848.520000 1044.360000 ;
+ RECT 843.290000 1043.880000 844.290000 1044.360000 ;
+ RECT 847.420000 1038.440000 848.520000 1038.920000 ;
+ RECT 843.290000 1038.440000 844.290000 1038.920000 ;
+ RECT 847.420000 1033.000000 848.520000 1033.480000 ;
+ RECT 843.290000 1033.000000 844.290000 1033.480000 ;
+ RECT 847.420000 1022.120000 848.520000 1022.600000 ;
+ RECT 843.290000 1022.120000 844.290000 1022.600000 ;
+ RECT 843.290000 1027.560000 844.290000 1028.040000 ;
+ RECT 847.420000 1027.560000 848.520000 1028.040000 ;
+ RECT 847.420000 1016.680000 848.520000 1017.160000 ;
+ RECT 843.290000 1016.680000 844.290000 1017.160000 ;
+ RECT 847.420000 1011.240000 848.520000 1011.720000 ;
+ RECT 843.290000 1011.240000 844.290000 1011.720000 ;
+ RECT 847.420000 1005.800000 848.520000 1006.280000 ;
+ RECT 843.290000 1005.800000 844.290000 1006.280000 ;
+ RECT 847.420000 1000.360000 848.520000 1000.840000 ;
+ RECT 843.290000 1000.360000 844.290000 1000.840000 ;
+ RECT 937.420000 994.920000 938.520000 995.400000 ;
+ RECT 937.420000 989.480000 938.520000 989.960000 ;
+ RECT 937.420000 984.040000 938.520000 984.520000 ;
+ RECT 937.420000 978.600000 938.520000 979.080000 ;
+ RECT 937.420000 973.160000 938.520000 973.640000 ;
+ RECT 892.420000 994.920000 893.520000 995.400000 ;
+ RECT 892.420000 989.480000 893.520000 989.960000 ;
+ RECT 892.420000 984.040000 893.520000 984.520000 ;
+ RECT 892.420000 978.600000 893.520000 979.080000 ;
+ RECT 892.420000 973.160000 893.520000 973.640000 ;
+ RECT 937.420000 951.400000 938.520000 951.880000 ;
+ RECT 937.420000 956.840000 938.520000 957.320000 ;
+ RECT 937.420000 962.280000 938.520000 962.760000 ;
+ RECT 937.420000 967.720000 938.520000 968.200000 ;
+ RECT 892.420000 951.400000 893.520000 951.880000 ;
+ RECT 892.420000 956.840000 893.520000 957.320000 ;
+ RECT 892.420000 962.280000 893.520000 962.760000 ;
+ RECT 892.420000 967.720000 893.520000 968.200000 ;
+ RECT 847.420000 994.920000 848.520000 995.400000 ;
+ RECT 843.290000 994.920000 844.290000 995.400000 ;
+ RECT 847.420000 989.480000 848.520000 989.960000 ;
+ RECT 843.290000 989.480000 844.290000 989.960000 ;
+ RECT 847.420000 978.600000 848.520000 979.080000 ;
+ RECT 843.290000 978.600000 844.290000 979.080000 ;
+ RECT 847.420000 973.160000 848.520000 973.640000 ;
+ RECT 843.290000 973.160000 844.290000 973.640000 ;
+ RECT 847.420000 984.040000 848.520000 984.520000 ;
+ RECT 843.290000 984.040000 844.290000 984.520000 ;
+ RECT 847.420000 967.720000 848.520000 968.200000 ;
+ RECT 843.290000 967.720000 844.290000 968.200000 ;
+ RECT 847.420000 962.280000 848.520000 962.760000 ;
+ RECT 843.290000 962.280000 844.290000 962.760000 ;
+ RECT 847.420000 956.840000 848.520000 957.320000 ;
+ RECT 847.420000 951.400000 848.520000 951.880000 ;
+ RECT 843.290000 956.840000 844.290000 957.320000 ;
+ RECT 843.290000 951.400000 844.290000 951.880000 ;
+ RECT 840.460000 1141.760000 1040.560000 1142.760000 ;
+ RECT 840.460000 949.390000 1040.560000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 946.540000 844.290000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 1145.800000 844.290000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 946.540000 1037.730000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 1145.800000 1037.730000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 949.390000 841.460000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 949.390000 1040.560000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1141.760000 841.460000 1142.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1141.760000 1040.560000 1142.760000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 749.130000 1028.520000 942.500000 ;
+ RECT 982.420000 749.130000 983.520000 942.500000 ;
+ RECT 1036.730000 746.280000 1037.730000 946.540000 ;
+ RECT 937.420000 749.130000 938.520000 942.500000 ;
+ RECT 892.420000 749.130000 893.520000 942.500000 ;
+ RECT 847.420000 749.130000 848.520000 942.500000 ;
+ RECT 843.290000 746.280000 844.290000 946.540000 ;
+ LAYER met3 ;
+ RECT 1027.420000 936.100000 1028.520000 936.580000 ;
+ RECT 1036.730000 936.100000 1037.730000 936.580000 ;
+ RECT 1036.730000 925.220000 1037.730000 925.700000 ;
+ RECT 1036.730000 930.660000 1037.730000 931.140000 ;
+ RECT 1027.420000 930.660000 1028.520000 931.140000 ;
+ RECT 1027.420000 925.220000 1028.520000 925.700000 ;
+ RECT 1027.420000 919.780000 1028.520000 920.260000 ;
+ RECT 1027.420000 914.340000 1028.520000 914.820000 ;
+ RECT 1036.730000 919.780000 1037.730000 920.260000 ;
+ RECT 1036.730000 914.340000 1037.730000 914.820000 ;
+ RECT 1027.420000 898.020000 1028.520000 898.500000 ;
+ RECT 1027.420000 903.460000 1028.520000 903.940000 ;
+ RECT 1036.730000 903.460000 1037.730000 903.940000 ;
+ RECT 1036.730000 898.020000 1037.730000 898.500000 ;
+ RECT 1027.420000 908.900000 1028.520000 909.380000 ;
+ RECT 1036.730000 908.900000 1037.730000 909.380000 ;
+ RECT 982.420000 936.100000 983.520000 936.580000 ;
+ RECT 982.420000 930.660000 983.520000 931.140000 ;
+ RECT 982.420000 925.220000 983.520000 925.700000 ;
+ RECT 982.420000 919.780000 983.520000 920.260000 ;
+ RECT 982.420000 898.020000 983.520000 898.500000 ;
+ RECT 982.420000 903.460000 983.520000 903.940000 ;
+ RECT 982.420000 908.900000 983.520000 909.380000 ;
+ RECT 982.420000 914.340000 983.520000 914.820000 ;
+ RECT 1036.730000 887.140000 1037.730000 887.620000 ;
+ RECT 1036.730000 892.580000 1037.730000 893.060000 ;
+ RECT 1027.420000 892.580000 1028.520000 893.060000 ;
+ RECT 1027.420000 887.140000 1028.520000 887.620000 ;
+ RECT 1027.420000 881.700000 1028.520000 882.180000 ;
+ RECT 1027.420000 876.260000 1028.520000 876.740000 ;
+ RECT 1036.730000 881.700000 1037.730000 882.180000 ;
+ RECT 1036.730000 876.260000 1037.730000 876.740000 ;
+ RECT 1036.730000 859.940000 1037.730000 860.420000 ;
+ RECT 1036.730000 865.380000 1037.730000 865.860000 ;
+ RECT 1036.730000 870.820000 1037.730000 871.300000 ;
+ RECT 1027.420000 865.380000 1028.520000 865.860000 ;
+ RECT 1027.420000 859.940000 1028.520000 860.420000 ;
+ RECT 1027.420000 870.820000 1028.520000 871.300000 ;
+ RECT 1027.420000 854.500000 1028.520000 854.980000 ;
+ RECT 1027.420000 849.060000 1028.520000 849.540000 ;
+ RECT 1036.730000 854.500000 1037.730000 854.980000 ;
+ RECT 1036.730000 849.060000 1037.730000 849.540000 ;
+ RECT 982.420000 892.580000 983.520000 893.060000 ;
+ RECT 982.420000 887.140000 983.520000 887.620000 ;
+ RECT 982.420000 881.700000 983.520000 882.180000 ;
+ RECT 982.420000 876.260000 983.520000 876.740000 ;
+ RECT 982.420000 865.380000 983.520000 865.860000 ;
+ RECT 982.420000 859.940000 983.520000 860.420000 ;
+ RECT 982.420000 854.500000 983.520000 854.980000 ;
+ RECT 982.420000 849.060000 983.520000 849.540000 ;
+ RECT 982.420000 870.820000 983.520000 871.300000 ;
+ RECT 937.420000 936.100000 938.520000 936.580000 ;
+ RECT 937.420000 930.660000 938.520000 931.140000 ;
+ RECT 937.420000 925.220000 938.520000 925.700000 ;
+ RECT 892.420000 936.100000 893.520000 936.580000 ;
+ RECT 892.420000 930.660000 893.520000 931.140000 ;
+ RECT 892.420000 925.220000 893.520000 925.700000 ;
+ RECT 937.420000 908.900000 938.520000 909.380000 ;
+ RECT 937.420000 903.460000 938.520000 903.940000 ;
+ RECT 937.420000 898.020000 938.520000 898.500000 ;
+ RECT 937.420000 914.340000 938.520000 914.820000 ;
+ RECT 937.420000 919.780000 938.520000 920.260000 ;
+ RECT 892.420000 919.780000 893.520000 920.260000 ;
+ RECT 892.420000 908.900000 893.520000 909.380000 ;
+ RECT 892.420000 903.460000 893.520000 903.940000 ;
+ RECT 892.420000 898.020000 893.520000 898.500000 ;
+ RECT 892.420000 914.340000 893.520000 914.820000 ;
+ RECT 847.420000 936.100000 848.520000 936.580000 ;
+ RECT 843.290000 936.100000 844.290000 936.580000 ;
+ RECT 843.290000 930.660000 844.290000 931.140000 ;
+ RECT 847.420000 930.660000 848.520000 931.140000 ;
+ RECT 847.420000 925.220000 848.520000 925.700000 ;
+ RECT 843.290000 925.220000 844.290000 925.700000 ;
+ RECT 847.420000 919.780000 848.520000 920.260000 ;
+ RECT 843.290000 919.780000 844.290000 920.260000 ;
+ RECT 847.420000 914.340000 848.520000 914.820000 ;
+ RECT 843.290000 914.340000 844.290000 914.820000 ;
+ RECT 847.420000 903.460000 848.520000 903.940000 ;
+ RECT 843.290000 903.460000 844.290000 903.940000 ;
+ RECT 847.420000 898.020000 848.520000 898.500000 ;
+ RECT 843.290000 898.020000 844.290000 898.500000 ;
+ RECT 847.420000 908.900000 848.520000 909.380000 ;
+ RECT 843.290000 908.900000 844.290000 909.380000 ;
+ RECT 937.420000 892.580000 938.520000 893.060000 ;
+ RECT 937.420000 887.140000 938.520000 887.620000 ;
+ RECT 937.420000 881.700000 938.520000 882.180000 ;
+ RECT 937.420000 876.260000 938.520000 876.740000 ;
+ RECT 892.420000 892.580000 893.520000 893.060000 ;
+ RECT 892.420000 887.140000 893.520000 887.620000 ;
+ RECT 892.420000 881.700000 893.520000 882.180000 ;
+ RECT 892.420000 876.260000 893.520000 876.740000 ;
+ RECT 937.420000 865.380000 938.520000 865.860000 ;
+ RECT 937.420000 849.060000 938.520000 849.540000 ;
+ RECT 937.420000 854.500000 938.520000 854.980000 ;
+ RECT 937.420000 859.940000 938.520000 860.420000 ;
+ RECT 937.420000 870.820000 938.520000 871.300000 ;
+ RECT 892.420000 849.060000 893.520000 849.540000 ;
+ RECT 892.420000 854.500000 893.520000 854.980000 ;
+ RECT 892.420000 859.940000 893.520000 860.420000 ;
+ RECT 892.420000 865.380000 893.520000 865.860000 ;
+ RECT 892.420000 870.820000 893.520000 871.300000 ;
+ RECT 847.420000 892.580000 848.520000 893.060000 ;
+ RECT 843.290000 892.580000 844.290000 893.060000 ;
+ RECT 847.420000 887.140000 848.520000 887.620000 ;
+ RECT 843.290000 887.140000 844.290000 887.620000 ;
+ RECT 847.420000 881.700000 848.520000 882.180000 ;
+ RECT 843.290000 881.700000 844.290000 882.180000 ;
+ RECT 847.420000 876.260000 848.520000 876.740000 ;
+ RECT 843.290000 876.260000 844.290000 876.740000 ;
+ RECT 847.420000 870.820000 848.520000 871.300000 ;
+ RECT 847.420000 865.380000 848.520000 865.860000 ;
+ RECT 843.290000 870.820000 844.290000 871.300000 ;
+ RECT 843.290000 865.380000 844.290000 865.860000 ;
+ RECT 847.420000 859.940000 848.520000 860.420000 ;
+ RECT 843.290000 859.940000 844.290000 860.420000 ;
+ RECT 847.420000 854.500000 848.520000 854.980000 ;
+ RECT 843.290000 854.500000 844.290000 854.980000 ;
+ RECT 847.420000 849.060000 848.520000 849.540000 ;
+ RECT 843.290000 849.060000 844.290000 849.540000 ;
+ RECT 1027.420000 843.620000 1028.520000 844.100000 ;
+ RECT 1027.420000 838.180000 1028.520000 838.660000 ;
+ RECT 1036.730000 843.620000 1037.730000 844.100000 ;
+ RECT 1036.730000 838.180000 1037.730000 838.660000 ;
+ RECT 1036.730000 821.860000 1037.730000 822.340000 ;
+ RECT 1036.730000 827.300000 1037.730000 827.780000 ;
+ RECT 1036.730000 832.740000 1037.730000 833.220000 ;
+ RECT 1027.420000 832.740000 1028.520000 833.220000 ;
+ RECT 1027.420000 827.300000 1028.520000 827.780000 ;
+ RECT 1027.420000 821.860000 1028.520000 822.340000 ;
+ RECT 1027.420000 810.980000 1028.520000 811.460000 ;
+ RECT 1027.420000 816.420000 1028.520000 816.900000 ;
+ RECT 1036.730000 816.420000 1037.730000 816.900000 ;
+ RECT 1036.730000 810.980000 1037.730000 811.460000 ;
+ RECT 1036.730000 800.100000 1037.730000 800.580000 ;
+ RECT 1036.730000 805.540000 1037.730000 806.020000 ;
+ RECT 1027.420000 800.100000 1028.520000 800.580000 ;
+ RECT 1027.420000 805.540000 1028.520000 806.020000 ;
+ RECT 982.420000 843.620000 983.520000 844.100000 ;
+ RECT 982.420000 838.180000 983.520000 838.660000 ;
+ RECT 982.420000 832.740000 983.520000 833.220000 ;
+ RECT 982.420000 827.300000 983.520000 827.780000 ;
+ RECT 982.420000 821.860000 983.520000 822.340000 ;
+ RECT 982.420000 800.100000 983.520000 800.580000 ;
+ RECT 982.420000 805.540000 983.520000 806.020000 ;
+ RECT 982.420000 810.980000 983.520000 811.460000 ;
+ RECT 982.420000 816.420000 983.520000 816.900000 ;
+ RECT 1027.420000 794.660000 1028.520000 795.140000 ;
+ RECT 1027.420000 789.220000 1028.520000 789.700000 ;
+ RECT 1036.730000 794.660000 1037.730000 795.140000 ;
+ RECT 1036.730000 789.220000 1037.730000 789.700000 ;
+ RECT 1027.420000 778.340000 1028.520000 778.820000 ;
+ RECT 1027.420000 772.900000 1028.520000 773.380000 ;
+ RECT 1036.730000 778.340000 1037.730000 778.820000 ;
+ RECT 1036.730000 772.900000 1037.730000 773.380000 ;
+ RECT 1027.420000 783.780000 1028.520000 784.260000 ;
+ RECT 1036.730000 783.780000 1037.730000 784.260000 ;
+ RECT 1036.730000 762.020000 1037.730000 762.500000 ;
+ RECT 1036.730000 767.460000 1037.730000 767.940000 ;
+ RECT 1027.420000 767.460000 1028.520000 767.940000 ;
+ RECT 1027.420000 762.020000 1028.520000 762.500000 ;
+ RECT 1027.420000 756.580000 1028.520000 757.060000 ;
+ RECT 1027.420000 751.140000 1028.520000 751.620000 ;
+ RECT 1036.730000 756.580000 1037.730000 757.060000 ;
+ RECT 1036.730000 751.140000 1037.730000 751.620000 ;
+ RECT 982.420000 794.660000 983.520000 795.140000 ;
+ RECT 982.420000 789.220000 983.520000 789.700000 ;
+ RECT 982.420000 783.780000 983.520000 784.260000 ;
+ RECT 982.420000 778.340000 983.520000 778.820000 ;
+ RECT 982.420000 772.900000 983.520000 773.380000 ;
+ RECT 982.420000 767.460000 983.520000 767.940000 ;
+ RECT 982.420000 762.020000 983.520000 762.500000 ;
+ RECT 982.420000 756.580000 983.520000 757.060000 ;
+ RECT 982.420000 751.140000 983.520000 751.620000 ;
+ RECT 937.420000 843.620000 938.520000 844.100000 ;
+ RECT 937.420000 838.180000 938.520000 838.660000 ;
+ RECT 937.420000 832.740000 938.520000 833.220000 ;
+ RECT 937.420000 827.300000 938.520000 827.780000 ;
+ RECT 937.420000 821.860000 938.520000 822.340000 ;
+ RECT 892.420000 843.620000 893.520000 844.100000 ;
+ RECT 892.420000 838.180000 893.520000 838.660000 ;
+ RECT 892.420000 832.740000 893.520000 833.220000 ;
+ RECT 892.420000 827.300000 893.520000 827.780000 ;
+ RECT 892.420000 821.860000 893.520000 822.340000 ;
+ RECT 937.420000 816.420000 938.520000 816.900000 ;
+ RECT 937.420000 810.980000 938.520000 811.460000 ;
+ RECT 937.420000 805.540000 938.520000 806.020000 ;
+ RECT 937.420000 800.100000 938.520000 800.580000 ;
+ RECT 892.420000 810.980000 893.520000 811.460000 ;
+ RECT 892.420000 805.540000 893.520000 806.020000 ;
+ RECT 892.420000 800.100000 893.520000 800.580000 ;
+ RECT 892.420000 816.420000 893.520000 816.900000 ;
+ RECT 847.420000 843.620000 848.520000 844.100000 ;
+ RECT 843.290000 843.620000 844.290000 844.100000 ;
+ RECT 847.420000 838.180000 848.520000 838.660000 ;
+ RECT 843.290000 838.180000 844.290000 838.660000 ;
+ RECT 847.420000 832.740000 848.520000 833.220000 ;
+ RECT 843.290000 832.740000 844.290000 833.220000 ;
+ RECT 847.420000 821.860000 848.520000 822.340000 ;
+ RECT 843.290000 821.860000 844.290000 822.340000 ;
+ RECT 843.290000 827.300000 844.290000 827.780000 ;
+ RECT 847.420000 827.300000 848.520000 827.780000 ;
+ RECT 847.420000 816.420000 848.520000 816.900000 ;
+ RECT 843.290000 816.420000 844.290000 816.900000 ;
+ RECT 847.420000 810.980000 848.520000 811.460000 ;
+ RECT 843.290000 810.980000 844.290000 811.460000 ;
+ RECT 847.420000 805.540000 848.520000 806.020000 ;
+ RECT 843.290000 805.540000 844.290000 806.020000 ;
+ RECT 847.420000 800.100000 848.520000 800.580000 ;
+ RECT 843.290000 800.100000 844.290000 800.580000 ;
+ RECT 937.420000 794.660000 938.520000 795.140000 ;
+ RECT 937.420000 789.220000 938.520000 789.700000 ;
+ RECT 937.420000 783.780000 938.520000 784.260000 ;
+ RECT 937.420000 778.340000 938.520000 778.820000 ;
+ RECT 937.420000 772.900000 938.520000 773.380000 ;
+ RECT 892.420000 794.660000 893.520000 795.140000 ;
+ RECT 892.420000 789.220000 893.520000 789.700000 ;
+ RECT 892.420000 783.780000 893.520000 784.260000 ;
+ RECT 892.420000 778.340000 893.520000 778.820000 ;
+ RECT 892.420000 772.900000 893.520000 773.380000 ;
+ RECT 937.420000 751.140000 938.520000 751.620000 ;
+ RECT 937.420000 756.580000 938.520000 757.060000 ;
+ RECT 937.420000 762.020000 938.520000 762.500000 ;
+ RECT 937.420000 767.460000 938.520000 767.940000 ;
+ RECT 892.420000 751.140000 893.520000 751.620000 ;
+ RECT 892.420000 756.580000 893.520000 757.060000 ;
+ RECT 892.420000 762.020000 893.520000 762.500000 ;
+ RECT 892.420000 767.460000 893.520000 767.940000 ;
+ RECT 847.420000 794.660000 848.520000 795.140000 ;
+ RECT 843.290000 794.660000 844.290000 795.140000 ;
+ RECT 847.420000 789.220000 848.520000 789.700000 ;
+ RECT 843.290000 789.220000 844.290000 789.700000 ;
+ RECT 847.420000 778.340000 848.520000 778.820000 ;
+ RECT 843.290000 778.340000 844.290000 778.820000 ;
+ RECT 847.420000 772.900000 848.520000 773.380000 ;
+ RECT 843.290000 772.900000 844.290000 773.380000 ;
+ RECT 847.420000 783.780000 848.520000 784.260000 ;
+ RECT 843.290000 783.780000 844.290000 784.260000 ;
+ RECT 847.420000 767.460000 848.520000 767.940000 ;
+ RECT 843.290000 767.460000 844.290000 767.940000 ;
+ RECT 847.420000 762.020000 848.520000 762.500000 ;
+ RECT 843.290000 762.020000 844.290000 762.500000 ;
+ RECT 847.420000 756.580000 848.520000 757.060000 ;
+ RECT 847.420000 751.140000 848.520000 751.620000 ;
+ RECT 843.290000 756.580000 844.290000 757.060000 ;
+ RECT 843.290000 751.140000 844.290000 751.620000 ;
+ RECT 840.460000 941.500000 1040.560000 942.500000 ;
+ RECT 840.460000 749.130000 1040.560000 750.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 746.280000 844.290000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 945.540000 844.290000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 746.280000 1037.730000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 945.540000 1037.730000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 749.130000 841.460000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 749.130000 1040.560000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 941.500000 841.460000 942.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 941.500000 1040.560000 942.500000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 548.870000 1028.520000 742.240000 ;
+ RECT 982.420000 548.870000 983.520000 742.240000 ;
+ RECT 1036.730000 546.020000 1037.730000 746.280000 ;
+ RECT 937.420000 548.870000 938.520000 742.240000 ;
+ RECT 892.420000 548.870000 893.520000 742.240000 ;
+ RECT 847.420000 548.870000 848.520000 742.240000 ;
+ RECT 843.290000 546.020000 844.290000 746.280000 ;
+ LAYER met3 ;
+ RECT 1027.420000 735.840000 1028.520000 736.320000 ;
+ RECT 1036.730000 735.840000 1037.730000 736.320000 ;
+ RECT 1036.730000 724.960000 1037.730000 725.440000 ;
+ RECT 1036.730000 730.400000 1037.730000 730.880000 ;
+ RECT 1027.420000 730.400000 1028.520000 730.880000 ;
+ RECT 1027.420000 724.960000 1028.520000 725.440000 ;
+ RECT 1027.420000 719.520000 1028.520000 720.000000 ;
+ RECT 1027.420000 714.080000 1028.520000 714.560000 ;
+ RECT 1036.730000 719.520000 1037.730000 720.000000 ;
+ RECT 1036.730000 714.080000 1037.730000 714.560000 ;
+ RECT 1027.420000 697.760000 1028.520000 698.240000 ;
+ RECT 1027.420000 703.200000 1028.520000 703.680000 ;
+ RECT 1036.730000 703.200000 1037.730000 703.680000 ;
+ RECT 1036.730000 697.760000 1037.730000 698.240000 ;
+ RECT 1027.420000 708.640000 1028.520000 709.120000 ;
+ RECT 1036.730000 708.640000 1037.730000 709.120000 ;
+ RECT 982.420000 735.840000 983.520000 736.320000 ;
+ RECT 982.420000 730.400000 983.520000 730.880000 ;
+ RECT 982.420000 724.960000 983.520000 725.440000 ;
+ RECT 982.420000 719.520000 983.520000 720.000000 ;
+ RECT 982.420000 697.760000 983.520000 698.240000 ;
+ RECT 982.420000 703.200000 983.520000 703.680000 ;
+ RECT 982.420000 708.640000 983.520000 709.120000 ;
+ RECT 982.420000 714.080000 983.520000 714.560000 ;
+ RECT 1036.730000 686.880000 1037.730000 687.360000 ;
+ RECT 1036.730000 692.320000 1037.730000 692.800000 ;
+ RECT 1027.420000 692.320000 1028.520000 692.800000 ;
+ RECT 1027.420000 686.880000 1028.520000 687.360000 ;
+ RECT 1027.420000 681.440000 1028.520000 681.920000 ;
+ RECT 1027.420000 676.000000 1028.520000 676.480000 ;
+ RECT 1036.730000 681.440000 1037.730000 681.920000 ;
+ RECT 1036.730000 676.000000 1037.730000 676.480000 ;
+ RECT 1036.730000 659.680000 1037.730000 660.160000 ;
+ RECT 1036.730000 665.120000 1037.730000 665.600000 ;
+ RECT 1036.730000 670.560000 1037.730000 671.040000 ;
+ RECT 1027.420000 665.120000 1028.520000 665.600000 ;
+ RECT 1027.420000 659.680000 1028.520000 660.160000 ;
+ RECT 1027.420000 670.560000 1028.520000 671.040000 ;
+ RECT 1027.420000 654.240000 1028.520000 654.720000 ;
+ RECT 1027.420000 648.800000 1028.520000 649.280000 ;
+ RECT 1036.730000 654.240000 1037.730000 654.720000 ;
+ RECT 1036.730000 648.800000 1037.730000 649.280000 ;
+ RECT 982.420000 692.320000 983.520000 692.800000 ;
+ RECT 982.420000 686.880000 983.520000 687.360000 ;
+ RECT 982.420000 681.440000 983.520000 681.920000 ;
+ RECT 982.420000 676.000000 983.520000 676.480000 ;
+ RECT 982.420000 665.120000 983.520000 665.600000 ;
+ RECT 982.420000 659.680000 983.520000 660.160000 ;
+ RECT 982.420000 654.240000 983.520000 654.720000 ;
+ RECT 982.420000 648.800000 983.520000 649.280000 ;
+ RECT 982.420000 670.560000 983.520000 671.040000 ;
+ RECT 937.420000 735.840000 938.520000 736.320000 ;
+ RECT 937.420000 730.400000 938.520000 730.880000 ;
+ RECT 937.420000 724.960000 938.520000 725.440000 ;
+ RECT 892.420000 735.840000 893.520000 736.320000 ;
+ RECT 892.420000 730.400000 893.520000 730.880000 ;
+ RECT 892.420000 724.960000 893.520000 725.440000 ;
+ RECT 937.420000 708.640000 938.520000 709.120000 ;
+ RECT 937.420000 703.200000 938.520000 703.680000 ;
+ RECT 937.420000 697.760000 938.520000 698.240000 ;
+ RECT 937.420000 714.080000 938.520000 714.560000 ;
+ RECT 937.420000 719.520000 938.520000 720.000000 ;
+ RECT 892.420000 719.520000 893.520000 720.000000 ;
+ RECT 892.420000 708.640000 893.520000 709.120000 ;
+ RECT 892.420000 703.200000 893.520000 703.680000 ;
+ RECT 892.420000 697.760000 893.520000 698.240000 ;
+ RECT 892.420000 714.080000 893.520000 714.560000 ;
+ RECT 847.420000 735.840000 848.520000 736.320000 ;
+ RECT 843.290000 735.840000 844.290000 736.320000 ;
+ RECT 843.290000 730.400000 844.290000 730.880000 ;
+ RECT 847.420000 730.400000 848.520000 730.880000 ;
+ RECT 847.420000 724.960000 848.520000 725.440000 ;
+ RECT 843.290000 724.960000 844.290000 725.440000 ;
+ RECT 847.420000 719.520000 848.520000 720.000000 ;
+ RECT 843.290000 719.520000 844.290000 720.000000 ;
+ RECT 847.420000 714.080000 848.520000 714.560000 ;
+ RECT 843.290000 714.080000 844.290000 714.560000 ;
+ RECT 847.420000 703.200000 848.520000 703.680000 ;
+ RECT 843.290000 703.200000 844.290000 703.680000 ;
+ RECT 847.420000 697.760000 848.520000 698.240000 ;
+ RECT 843.290000 697.760000 844.290000 698.240000 ;
+ RECT 847.420000 708.640000 848.520000 709.120000 ;
+ RECT 843.290000 708.640000 844.290000 709.120000 ;
+ RECT 937.420000 692.320000 938.520000 692.800000 ;
+ RECT 937.420000 686.880000 938.520000 687.360000 ;
+ RECT 937.420000 681.440000 938.520000 681.920000 ;
+ RECT 937.420000 676.000000 938.520000 676.480000 ;
+ RECT 892.420000 692.320000 893.520000 692.800000 ;
+ RECT 892.420000 686.880000 893.520000 687.360000 ;
+ RECT 892.420000 681.440000 893.520000 681.920000 ;
+ RECT 892.420000 676.000000 893.520000 676.480000 ;
+ RECT 937.420000 665.120000 938.520000 665.600000 ;
+ RECT 937.420000 648.800000 938.520000 649.280000 ;
+ RECT 937.420000 654.240000 938.520000 654.720000 ;
+ RECT 937.420000 659.680000 938.520000 660.160000 ;
+ RECT 937.420000 670.560000 938.520000 671.040000 ;
+ RECT 892.420000 648.800000 893.520000 649.280000 ;
+ RECT 892.420000 654.240000 893.520000 654.720000 ;
+ RECT 892.420000 659.680000 893.520000 660.160000 ;
+ RECT 892.420000 665.120000 893.520000 665.600000 ;
+ RECT 892.420000 670.560000 893.520000 671.040000 ;
+ RECT 847.420000 692.320000 848.520000 692.800000 ;
+ RECT 843.290000 692.320000 844.290000 692.800000 ;
+ RECT 847.420000 686.880000 848.520000 687.360000 ;
+ RECT 843.290000 686.880000 844.290000 687.360000 ;
+ RECT 847.420000 681.440000 848.520000 681.920000 ;
+ RECT 843.290000 681.440000 844.290000 681.920000 ;
+ RECT 847.420000 676.000000 848.520000 676.480000 ;
+ RECT 843.290000 676.000000 844.290000 676.480000 ;
+ RECT 847.420000 670.560000 848.520000 671.040000 ;
+ RECT 847.420000 665.120000 848.520000 665.600000 ;
+ RECT 843.290000 670.560000 844.290000 671.040000 ;
+ RECT 843.290000 665.120000 844.290000 665.600000 ;
+ RECT 847.420000 659.680000 848.520000 660.160000 ;
+ RECT 843.290000 659.680000 844.290000 660.160000 ;
+ RECT 847.420000 654.240000 848.520000 654.720000 ;
+ RECT 843.290000 654.240000 844.290000 654.720000 ;
+ RECT 847.420000 648.800000 848.520000 649.280000 ;
+ RECT 843.290000 648.800000 844.290000 649.280000 ;
+ RECT 1027.420000 643.360000 1028.520000 643.840000 ;
+ RECT 1027.420000 637.920000 1028.520000 638.400000 ;
+ RECT 1036.730000 643.360000 1037.730000 643.840000 ;
+ RECT 1036.730000 637.920000 1037.730000 638.400000 ;
+ RECT 1036.730000 621.600000 1037.730000 622.080000 ;
+ RECT 1036.730000 627.040000 1037.730000 627.520000 ;
+ RECT 1036.730000 632.480000 1037.730000 632.960000 ;
+ RECT 1027.420000 632.480000 1028.520000 632.960000 ;
+ RECT 1027.420000 627.040000 1028.520000 627.520000 ;
+ RECT 1027.420000 621.600000 1028.520000 622.080000 ;
+ RECT 1027.420000 610.720000 1028.520000 611.200000 ;
+ RECT 1027.420000 616.160000 1028.520000 616.640000 ;
+ RECT 1036.730000 616.160000 1037.730000 616.640000 ;
+ RECT 1036.730000 610.720000 1037.730000 611.200000 ;
+ RECT 1036.730000 599.840000 1037.730000 600.320000 ;
+ RECT 1036.730000 605.280000 1037.730000 605.760000 ;
+ RECT 1027.420000 599.840000 1028.520000 600.320000 ;
+ RECT 1027.420000 605.280000 1028.520000 605.760000 ;
+ RECT 982.420000 643.360000 983.520000 643.840000 ;
+ RECT 982.420000 637.920000 983.520000 638.400000 ;
+ RECT 982.420000 632.480000 983.520000 632.960000 ;
+ RECT 982.420000 627.040000 983.520000 627.520000 ;
+ RECT 982.420000 621.600000 983.520000 622.080000 ;
+ RECT 982.420000 599.840000 983.520000 600.320000 ;
+ RECT 982.420000 605.280000 983.520000 605.760000 ;
+ RECT 982.420000 610.720000 983.520000 611.200000 ;
+ RECT 982.420000 616.160000 983.520000 616.640000 ;
+ RECT 1027.420000 594.400000 1028.520000 594.880000 ;
+ RECT 1027.420000 588.960000 1028.520000 589.440000 ;
+ RECT 1036.730000 594.400000 1037.730000 594.880000 ;
+ RECT 1036.730000 588.960000 1037.730000 589.440000 ;
+ RECT 1027.420000 578.080000 1028.520000 578.560000 ;
+ RECT 1027.420000 572.640000 1028.520000 573.120000 ;
+ RECT 1036.730000 578.080000 1037.730000 578.560000 ;
+ RECT 1036.730000 572.640000 1037.730000 573.120000 ;
+ RECT 1027.420000 583.520000 1028.520000 584.000000 ;
+ RECT 1036.730000 583.520000 1037.730000 584.000000 ;
+ RECT 1036.730000 561.760000 1037.730000 562.240000 ;
+ RECT 1036.730000 567.200000 1037.730000 567.680000 ;
+ RECT 1027.420000 567.200000 1028.520000 567.680000 ;
+ RECT 1027.420000 561.760000 1028.520000 562.240000 ;
+ RECT 1027.420000 556.320000 1028.520000 556.800000 ;
+ RECT 1027.420000 550.880000 1028.520000 551.360000 ;
+ RECT 1036.730000 556.320000 1037.730000 556.800000 ;
+ RECT 1036.730000 550.880000 1037.730000 551.360000 ;
+ RECT 982.420000 594.400000 983.520000 594.880000 ;
+ RECT 982.420000 588.960000 983.520000 589.440000 ;
+ RECT 982.420000 583.520000 983.520000 584.000000 ;
+ RECT 982.420000 578.080000 983.520000 578.560000 ;
+ RECT 982.420000 572.640000 983.520000 573.120000 ;
+ RECT 982.420000 567.200000 983.520000 567.680000 ;
+ RECT 982.420000 561.760000 983.520000 562.240000 ;
+ RECT 982.420000 556.320000 983.520000 556.800000 ;
+ RECT 982.420000 550.880000 983.520000 551.360000 ;
+ RECT 937.420000 643.360000 938.520000 643.840000 ;
+ RECT 937.420000 637.920000 938.520000 638.400000 ;
+ RECT 937.420000 632.480000 938.520000 632.960000 ;
+ RECT 937.420000 627.040000 938.520000 627.520000 ;
+ RECT 937.420000 621.600000 938.520000 622.080000 ;
+ RECT 892.420000 643.360000 893.520000 643.840000 ;
+ RECT 892.420000 637.920000 893.520000 638.400000 ;
+ RECT 892.420000 632.480000 893.520000 632.960000 ;
+ RECT 892.420000 627.040000 893.520000 627.520000 ;
+ RECT 892.420000 621.600000 893.520000 622.080000 ;
+ RECT 937.420000 616.160000 938.520000 616.640000 ;
+ RECT 937.420000 610.720000 938.520000 611.200000 ;
+ RECT 937.420000 605.280000 938.520000 605.760000 ;
+ RECT 937.420000 599.840000 938.520000 600.320000 ;
+ RECT 892.420000 610.720000 893.520000 611.200000 ;
+ RECT 892.420000 605.280000 893.520000 605.760000 ;
+ RECT 892.420000 599.840000 893.520000 600.320000 ;
+ RECT 892.420000 616.160000 893.520000 616.640000 ;
+ RECT 847.420000 643.360000 848.520000 643.840000 ;
+ RECT 843.290000 643.360000 844.290000 643.840000 ;
+ RECT 847.420000 637.920000 848.520000 638.400000 ;
+ RECT 843.290000 637.920000 844.290000 638.400000 ;
+ RECT 847.420000 632.480000 848.520000 632.960000 ;
+ RECT 843.290000 632.480000 844.290000 632.960000 ;
+ RECT 847.420000 621.600000 848.520000 622.080000 ;
+ RECT 843.290000 621.600000 844.290000 622.080000 ;
+ RECT 843.290000 627.040000 844.290000 627.520000 ;
+ RECT 847.420000 627.040000 848.520000 627.520000 ;
+ RECT 847.420000 616.160000 848.520000 616.640000 ;
+ RECT 843.290000 616.160000 844.290000 616.640000 ;
+ RECT 847.420000 610.720000 848.520000 611.200000 ;
+ RECT 843.290000 610.720000 844.290000 611.200000 ;
+ RECT 847.420000 605.280000 848.520000 605.760000 ;
+ RECT 843.290000 605.280000 844.290000 605.760000 ;
+ RECT 847.420000 599.840000 848.520000 600.320000 ;
+ RECT 843.290000 599.840000 844.290000 600.320000 ;
+ RECT 937.420000 594.400000 938.520000 594.880000 ;
+ RECT 937.420000 588.960000 938.520000 589.440000 ;
+ RECT 937.420000 583.520000 938.520000 584.000000 ;
+ RECT 937.420000 578.080000 938.520000 578.560000 ;
+ RECT 937.420000 572.640000 938.520000 573.120000 ;
+ RECT 892.420000 594.400000 893.520000 594.880000 ;
+ RECT 892.420000 588.960000 893.520000 589.440000 ;
+ RECT 892.420000 583.520000 893.520000 584.000000 ;
+ RECT 892.420000 578.080000 893.520000 578.560000 ;
+ RECT 892.420000 572.640000 893.520000 573.120000 ;
+ RECT 937.420000 550.880000 938.520000 551.360000 ;
+ RECT 937.420000 556.320000 938.520000 556.800000 ;
+ RECT 937.420000 561.760000 938.520000 562.240000 ;
+ RECT 937.420000 567.200000 938.520000 567.680000 ;
+ RECT 892.420000 550.880000 893.520000 551.360000 ;
+ RECT 892.420000 556.320000 893.520000 556.800000 ;
+ RECT 892.420000 561.760000 893.520000 562.240000 ;
+ RECT 892.420000 567.200000 893.520000 567.680000 ;
+ RECT 847.420000 594.400000 848.520000 594.880000 ;
+ RECT 843.290000 594.400000 844.290000 594.880000 ;
+ RECT 847.420000 588.960000 848.520000 589.440000 ;
+ RECT 843.290000 588.960000 844.290000 589.440000 ;
+ RECT 847.420000 578.080000 848.520000 578.560000 ;
+ RECT 843.290000 578.080000 844.290000 578.560000 ;
+ RECT 847.420000 572.640000 848.520000 573.120000 ;
+ RECT 843.290000 572.640000 844.290000 573.120000 ;
+ RECT 847.420000 583.520000 848.520000 584.000000 ;
+ RECT 843.290000 583.520000 844.290000 584.000000 ;
+ RECT 847.420000 567.200000 848.520000 567.680000 ;
+ RECT 843.290000 567.200000 844.290000 567.680000 ;
+ RECT 847.420000 561.760000 848.520000 562.240000 ;
+ RECT 843.290000 561.760000 844.290000 562.240000 ;
+ RECT 847.420000 556.320000 848.520000 556.800000 ;
+ RECT 847.420000 550.880000 848.520000 551.360000 ;
+ RECT 843.290000 556.320000 844.290000 556.800000 ;
+ RECT 843.290000 550.880000 844.290000 551.360000 ;
+ RECT 840.460000 741.240000 1040.560000 742.240000 ;
+ RECT 840.460000 548.870000 1040.560000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 546.020000 844.290000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 745.280000 844.290000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 546.020000 1037.730000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 745.280000 1037.730000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 548.870000 841.460000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 548.870000 1040.560000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 741.240000 841.460000 742.240000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 741.240000 1040.560000 742.240000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 348.610000 1028.520000 541.980000 ;
+ RECT 982.420000 348.610000 983.520000 541.980000 ;
+ RECT 1036.730000 345.760000 1037.730000 546.020000 ;
+ RECT 937.420000 348.610000 938.520000 541.980000 ;
+ RECT 892.420000 348.610000 893.520000 541.980000 ;
+ RECT 847.420000 348.610000 848.520000 541.980000 ;
+ RECT 843.290000 345.760000 844.290000 546.020000 ;
+ LAYER met3 ;
+ RECT 1027.420000 535.580000 1028.520000 536.060000 ;
+ RECT 1036.730000 535.580000 1037.730000 536.060000 ;
+ RECT 1036.730000 524.700000 1037.730000 525.180000 ;
+ RECT 1036.730000 530.140000 1037.730000 530.620000 ;
+ RECT 1027.420000 530.140000 1028.520000 530.620000 ;
+ RECT 1027.420000 524.700000 1028.520000 525.180000 ;
+ RECT 1027.420000 519.260000 1028.520000 519.740000 ;
+ RECT 1027.420000 513.820000 1028.520000 514.300000 ;
+ RECT 1036.730000 519.260000 1037.730000 519.740000 ;
+ RECT 1036.730000 513.820000 1037.730000 514.300000 ;
+ RECT 1027.420000 497.500000 1028.520000 497.980000 ;
+ RECT 1027.420000 502.940000 1028.520000 503.420000 ;
+ RECT 1036.730000 502.940000 1037.730000 503.420000 ;
+ RECT 1036.730000 497.500000 1037.730000 497.980000 ;
+ RECT 1027.420000 508.380000 1028.520000 508.860000 ;
+ RECT 1036.730000 508.380000 1037.730000 508.860000 ;
+ RECT 982.420000 535.580000 983.520000 536.060000 ;
+ RECT 982.420000 530.140000 983.520000 530.620000 ;
+ RECT 982.420000 524.700000 983.520000 525.180000 ;
+ RECT 982.420000 519.260000 983.520000 519.740000 ;
+ RECT 982.420000 497.500000 983.520000 497.980000 ;
+ RECT 982.420000 502.940000 983.520000 503.420000 ;
+ RECT 982.420000 508.380000 983.520000 508.860000 ;
+ RECT 982.420000 513.820000 983.520000 514.300000 ;
+ RECT 1036.730000 486.620000 1037.730000 487.100000 ;
+ RECT 1036.730000 492.060000 1037.730000 492.540000 ;
+ RECT 1027.420000 492.060000 1028.520000 492.540000 ;
+ RECT 1027.420000 486.620000 1028.520000 487.100000 ;
+ RECT 1027.420000 481.180000 1028.520000 481.660000 ;
+ RECT 1027.420000 475.740000 1028.520000 476.220000 ;
+ RECT 1036.730000 481.180000 1037.730000 481.660000 ;
+ RECT 1036.730000 475.740000 1037.730000 476.220000 ;
+ RECT 1036.730000 459.420000 1037.730000 459.900000 ;
+ RECT 1036.730000 464.860000 1037.730000 465.340000 ;
+ RECT 1036.730000 470.300000 1037.730000 470.780000 ;
+ RECT 1027.420000 464.860000 1028.520000 465.340000 ;
+ RECT 1027.420000 459.420000 1028.520000 459.900000 ;
+ RECT 1027.420000 470.300000 1028.520000 470.780000 ;
+ RECT 1027.420000 453.980000 1028.520000 454.460000 ;
+ RECT 1027.420000 448.540000 1028.520000 449.020000 ;
+ RECT 1036.730000 453.980000 1037.730000 454.460000 ;
+ RECT 1036.730000 448.540000 1037.730000 449.020000 ;
+ RECT 982.420000 492.060000 983.520000 492.540000 ;
+ RECT 982.420000 486.620000 983.520000 487.100000 ;
+ RECT 982.420000 481.180000 983.520000 481.660000 ;
+ RECT 982.420000 475.740000 983.520000 476.220000 ;
+ RECT 982.420000 464.860000 983.520000 465.340000 ;
+ RECT 982.420000 459.420000 983.520000 459.900000 ;
+ RECT 982.420000 453.980000 983.520000 454.460000 ;
+ RECT 982.420000 448.540000 983.520000 449.020000 ;
+ RECT 982.420000 470.300000 983.520000 470.780000 ;
+ RECT 937.420000 535.580000 938.520000 536.060000 ;
+ RECT 937.420000 530.140000 938.520000 530.620000 ;
+ RECT 937.420000 524.700000 938.520000 525.180000 ;
+ RECT 892.420000 535.580000 893.520000 536.060000 ;
+ RECT 892.420000 530.140000 893.520000 530.620000 ;
+ RECT 892.420000 524.700000 893.520000 525.180000 ;
+ RECT 937.420000 508.380000 938.520000 508.860000 ;
+ RECT 937.420000 502.940000 938.520000 503.420000 ;
+ RECT 937.420000 497.500000 938.520000 497.980000 ;
+ RECT 937.420000 513.820000 938.520000 514.300000 ;
+ RECT 937.420000 519.260000 938.520000 519.740000 ;
+ RECT 892.420000 519.260000 893.520000 519.740000 ;
+ RECT 892.420000 508.380000 893.520000 508.860000 ;
+ RECT 892.420000 502.940000 893.520000 503.420000 ;
+ RECT 892.420000 497.500000 893.520000 497.980000 ;
+ RECT 892.420000 513.820000 893.520000 514.300000 ;
+ RECT 847.420000 535.580000 848.520000 536.060000 ;
+ RECT 843.290000 535.580000 844.290000 536.060000 ;
+ RECT 843.290000 530.140000 844.290000 530.620000 ;
+ RECT 847.420000 530.140000 848.520000 530.620000 ;
+ RECT 847.420000 524.700000 848.520000 525.180000 ;
+ RECT 843.290000 524.700000 844.290000 525.180000 ;
+ RECT 847.420000 519.260000 848.520000 519.740000 ;
+ RECT 843.290000 519.260000 844.290000 519.740000 ;
+ RECT 847.420000 513.820000 848.520000 514.300000 ;
+ RECT 843.290000 513.820000 844.290000 514.300000 ;
+ RECT 847.420000 502.940000 848.520000 503.420000 ;
+ RECT 843.290000 502.940000 844.290000 503.420000 ;
+ RECT 847.420000 497.500000 848.520000 497.980000 ;
+ RECT 843.290000 497.500000 844.290000 497.980000 ;
+ RECT 847.420000 508.380000 848.520000 508.860000 ;
+ RECT 843.290000 508.380000 844.290000 508.860000 ;
+ RECT 937.420000 492.060000 938.520000 492.540000 ;
+ RECT 937.420000 486.620000 938.520000 487.100000 ;
+ RECT 937.420000 481.180000 938.520000 481.660000 ;
+ RECT 937.420000 475.740000 938.520000 476.220000 ;
+ RECT 892.420000 492.060000 893.520000 492.540000 ;
+ RECT 892.420000 486.620000 893.520000 487.100000 ;
+ RECT 892.420000 481.180000 893.520000 481.660000 ;
+ RECT 892.420000 475.740000 893.520000 476.220000 ;
+ RECT 937.420000 464.860000 938.520000 465.340000 ;
+ RECT 937.420000 448.540000 938.520000 449.020000 ;
+ RECT 937.420000 453.980000 938.520000 454.460000 ;
+ RECT 937.420000 459.420000 938.520000 459.900000 ;
+ RECT 937.420000 470.300000 938.520000 470.780000 ;
+ RECT 892.420000 448.540000 893.520000 449.020000 ;
+ RECT 892.420000 453.980000 893.520000 454.460000 ;
+ RECT 892.420000 459.420000 893.520000 459.900000 ;
+ RECT 892.420000 464.860000 893.520000 465.340000 ;
+ RECT 892.420000 470.300000 893.520000 470.780000 ;
+ RECT 847.420000 492.060000 848.520000 492.540000 ;
+ RECT 843.290000 492.060000 844.290000 492.540000 ;
+ RECT 847.420000 486.620000 848.520000 487.100000 ;
+ RECT 843.290000 486.620000 844.290000 487.100000 ;
+ RECT 847.420000 481.180000 848.520000 481.660000 ;
+ RECT 843.290000 481.180000 844.290000 481.660000 ;
+ RECT 847.420000 475.740000 848.520000 476.220000 ;
+ RECT 843.290000 475.740000 844.290000 476.220000 ;
+ RECT 847.420000 470.300000 848.520000 470.780000 ;
+ RECT 847.420000 464.860000 848.520000 465.340000 ;
+ RECT 843.290000 470.300000 844.290000 470.780000 ;
+ RECT 843.290000 464.860000 844.290000 465.340000 ;
+ RECT 847.420000 459.420000 848.520000 459.900000 ;
+ RECT 843.290000 459.420000 844.290000 459.900000 ;
+ RECT 847.420000 453.980000 848.520000 454.460000 ;
+ RECT 843.290000 453.980000 844.290000 454.460000 ;
+ RECT 847.420000 448.540000 848.520000 449.020000 ;
+ RECT 843.290000 448.540000 844.290000 449.020000 ;
+ RECT 1027.420000 443.100000 1028.520000 443.580000 ;
+ RECT 1027.420000 437.660000 1028.520000 438.140000 ;
+ RECT 1036.730000 443.100000 1037.730000 443.580000 ;
+ RECT 1036.730000 437.660000 1037.730000 438.140000 ;
+ RECT 1036.730000 421.340000 1037.730000 421.820000 ;
+ RECT 1036.730000 426.780000 1037.730000 427.260000 ;
+ RECT 1036.730000 432.220000 1037.730000 432.700000 ;
+ RECT 1027.420000 432.220000 1028.520000 432.700000 ;
+ RECT 1027.420000 426.780000 1028.520000 427.260000 ;
+ RECT 1027.420000 421.340000 1028.520000 421.820000 ;
+ RECT 1027.420000 410.460000 1028.520000 410.940000 ;
+ RECT 1027.420000 415.900000 1028.520000 416.380000 ;
+ RECT 1036.730000 415.900000 1037.730000 416.380000 ;
+ RECT 1036.730000 410.460000 1037.730000 410.940000 ;
+ RECT 1036.730000 399.580000 1037.730000 400.060000 ;
+ RECT 1036.730000 405.020000 1037.730000 405.500000 ;
+ RECT 1027.420000 399.580000 1028.520000 400.060000 ;
+ RECT 1027.420000 405.020000 1028.520000 405.500000 ;
+ RECT 982.420000 443.100000 983.520000 443.580000 ;
+ RECT 982.420000 437.660000 983.520000 438.140000 ;
+ RECT 982.420000 432.220000 983.520000 432.700000 ;
+ RECT 982.420000 426.780000 983.520000 427.260000 ;
+ RECT 982.420000 421.340000 983.520000 421.820000 ;
+ RECT 982.420000 399.580000 983.520000 400.060000 ;
+ RECT 982.420000 405.020000 983.520000 405.500000 ;
+ RECT 982.420000 410.460000 983.520000 410.940000 ;
+ RECT 982.420000 415.900000 983.520000 416.380000 ;
+ RECT 1027.420000 394.140000 1028.520000 394.620000 ;
+ RECT 1027.420000 388.700000 1028.520000 389.180000 ;
+ RECT 1036.730000 394.140000 1037.730000 394.620000 ;
+ RECT 1036.730000 388.700000 1037.730000 389.180000 ;
+ RECT 1027.420000 377.820000 1028.520000 378.300000 ;
+ RECT 1027.420000 372.380000 1028.520000 372.860000 ;
+ RECT 1036.730000 377.820000 1037.730000 378.300000 ;
+ RECT 1036.730000 372.380000 1037.730000 372.860000 ;
+ RECT 1027.420000 383.260000 1028.520000 383.740000 ;
+ RECT 1036.730000 383.260000 1037.730000 383.740000 ;
+ RECT 1036.730000 361.500000 1037.730000 361.980000 ;
+ RECT 1036.730000 366.940000 1037.730000 367.420000 ;
+ RECT 1027.420000 366.940000 1028.520000 367.420000 ;
+ RECT 1027.420000 361.500000 1028.520000 361.980000 ;
+ RECT 1027.420000 356.060000 1028.520000 356.540000 ;
+ RECT 1027.420000 350.620000 1028.520000 351.100000 ;
+ RECT 1036.730000 356.060000 1037.730000 356.540000 ;
+ RECT 1036.730000 350.620000 1037.730000 351.100000 ;
+ RECT 982.420000 394.140000 983.520000 394.620000 ;
+ RECT 982.420000 388.700000 983.520000 389.180000 ;
+ RECT 982.420000 383.260000 983.520000 383.740000 ;
+ RECT 982.420000 377.820000 983.520000 378.300000 ;
+ RECT 982.420000 372.380000 983.520000 372.860000 ;
+ RECT 982.420000 366.940000 983.520000 367.420000 ;
+ RECT 982.420000 361.500000 983.520000 361.980000 ;
+ RECT 982.420000 356.060000 983.520000 356.540000 ;
+ RECT 982.420000 350.620000 983.520000 351.100000 ;
+ RECT 937.420000 443.100000 938.520000 443.580000 ;
+ RECT 937.420000 437.660000 938.520000 438.140000 ;
+ RECT 937.420000 432.220000 938.520000 432.700000 ;
+ RECT 937.420000 426.780000 938.520000 427.260000 ;
+ RECT 937.420000 421.340000 938.520000 421.820000 ;
+ RECT 892.420000 443.100000 893.520000 443.580000 ;
+ RECT 892.420000 437.660000 893.520000 438.140000 ;
+ RECT 892.420000 432.220000 893.520000 432.700000 ;
+ RECT 892.420000 426.780000 893.520000 427.260000 ;
+ RECT 892.420000 421.340000 893.520000 421.820000 ;
+ RECT 937.420000 415.900000 938.520000 416.380000 ;
+ RECT 937.420000 410.460000 938.520000 410.940000 ;
+ RECT 937.420000 405.020000 938.520000 405.500000 ;
+ RECT 937.420000 399.580000 938.520000 400.060000 ;
+ RECT 892.420000 410.460000 893.520000 410.940000 ;
+ RECT 892.420000 405.020000 893.520000 405.500000 ;
+ RECT 892.420000 399.580000 893.520000 400.060000 ;
+ RECT 892.420000 415.900000 893.520000 416.380000 ;
+ RECT 847.420000 443.100000 848.520000 443.580000 ;
+ RECT 843.290000 443.100000 844.290000 443.580000 ;
+ RECT 847.420000 437.660000 848.520000 438.140000 ;
+ RECT 843.290000 437.660000 844.290000 438.140000 ;
+ RECT 847.420000 432.220000 848.520000 432.700000 ;
+ RECT 843.290000 432.220000 844.290000 432.700000 ;
+ RECT 847.420000 421.340000 848.520000 421.820000 ;
+ RECT 843.290000 421.340000 844.290000 421.820000 ;
+ RECT 843.290000 426.780000 844.290000 427.260000 ;
+ RECT 847.420000 426.780000 848.520000 427.260000 ;
+ RECT 847.420000 415.900000 848.520000 416.380000 ;
+ RECT 843.290000 415.900000 844.290000 416.380000 ;
+ RECT 847.420000 410.460000 848.520000 410.940000 ;
+ RECT 843.290000 410.460000 844.290000 410.940000 ;
+ RECT 847.420000 405.020000 848.520000 405.500000 ;
+ RECT 843.290000 405.020000 844.290000 405.500000 ;
+ RECT 847.420000 399.580000 848.520000 400.060000 ;
+ RECT 843.290000 399.580000 844.290000 400.060000 ;
+ RECT 937.420000 394.140000 938.520000 394.620000 ;
+ RECT 937.420000 388.700000 938.520000 389.180000 ;
+ RECT 937.420000 383.260000 938.520000 383.740000 ;
+ RECT 937.420000 377.820000 938.520000 378.300000 ;
+ RECT 937.420000 372.380000 938.520000 372.860000 ;
+ RECT 892.420000 394.140000 893.520000 394.620000 ;
+ RECT 892.420000 388.700000 893.520000 389.180000 ;
+ RECT 892.420000 383.260000 893.520000 383.740000 ;
+ RECT 892.420000 377.820000 893.520000 378.300000 ;
+ RECT 892.420000 372.380000 893.520000 372.860000 ;
+ RECT 937.420000 350.620000 938.520000 351.100000 ;
+ RECT 937.420000 356.060000 938.520000 356.540000 ;
+ RECT 937.420000 361.500000 938.520000 361.980000 ;
+ RECT 937.420000 366.940000 938.520000 367.420000 ;
+ RECT 892.420000 350.620000 893.520000 351.100000 ;
+ RECT 892.420000 356.060000 893.520000 356.540000 ;
+ RECT 892.420000 361.500000 893.520000 361.980000 ;
+ RECT 892.420000 366.940000 893.520000 367.420000 ;
+ RECT 847.420000 394.140000 848.520000 394.620000 ;
+ RECT 843.290000 394.140000 844.290000 394.620000 ;
+ RECT 847.420000 388.700000 848.520000 389.180000 ;
+ RECT 843.290000 388.700000 844.290000 389.180000 ;
+ RECT 847.420000 377.820000 848.520000 378.300000 ;
+ RECT 843.290000 377.820000 844.290000 378.300000 ;
+ RECT 847.420000 372.380000 848.520000 372.860000 ;
+ RECT 843.290000 372.380000 844.290000 372.860000 ;
+ RECT 847.420000 383.260000 848.520000 383.740000 ;
+ RECT 843.290000 383.260000 844.290000 383.740000 ;
+ RECT 847.420000 366.940000 848.520000 367.420000 ;
+ RECT 843.290000 366.940000 844.290000 367.420000 ;
+ RECT 847.420000 361.500000 848.520000 361.980000 ;
+ RECT 843.290000 361.500000 844.290000 361.980000 ;
+ RECT 847.420000 356.060000 848.520000 356.540000 ;
+ RECT 847.420000 350.620000 848.520000 351.100000 ;
+ RECT 843.290000 356.060000 844.290000 356.540000 ;
+ RECT 843.290000 350.620000 844.290000 351.100000 ;
+ RECT 840.460000 540.980000 1040.560000 541.980000 ;
+ RECT 840.460000 348.610000 1040.560000 349.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 345.760000 844.290000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 545.020000 844.290000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 345.760000 1037.730000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 545.020000 1037.730000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 348.610000 841.460000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 348.610000 1040.560000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 540.980000 841.460000 541.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 540.980000 1040.560000 541.980000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 148.350000 1028.520000 341.720000 ;
+ RECT 982.420000 148.350000 983.520000 341.720000 ;
+ RECT 1036.730000 145.500000 1037.730000 345.760000 ;
+ RECT 937.420000 148.350000 938.520000 341.720000 ;
+ RECT 892.420000 148.350000 893.520000 341.720000 ;
+ RECT 847.420000 148.350000 848.520000 341.720000 ;
+ RECT 843.290000 145.500000 844.290000 345.760000 ;
+ LAYER met3 ;
+ RECT 1027.420000 335.320000 1028.520000 335.800000 ;
+ RECT 1036.730000 335.320000 1037.730000 335.800000 ;
+ RECT 1036.730000 324.440000 1037.730000 324.920000 ;
+ RECT 1036.730000 329.880000 1037.730000 330.360000 ;
+ RECT 1027.420000 329.880000 1028.520000 330.360000 ;
+ RECT 1027.420000 324.440000 1028.520000 324.920000 ;
+ RECT 1027.420000 319.000000 1028.520000 319.480000 ;
+ RECT 1027.420000 313.560000 1028.520000 314.040000 ;
+ RECT 1036.730000 319.000000 1037.730000 319.480000 ;
+ RECT 1036.730000 313.560000 1037.730000 314.040000 ;
+ RECT 1027.420000 297.240000 1028.520000 297.720000 ;
+ RECT 1027.420000 302.680000 1028.520000 303.160000 ;
+ RECT 1036.730000 302.680000 1037.730000 303.160000 ;
+ RECT 1036.730000 297.240000 1037.730000 297.720000 ;
+ RECT 1027.420000 308.120000 1028.520000 308.600000 ;
+ RECT 1036.730000 308.120000 1037.730000 308.600000 ;
+ RECT 982.420000 335.320000 983.520000 335.800000 ;
+ RECT 982.420000 329.880000 983.520000 330.360000 ;
+ RECT 982.420000 324.440000 983.520000 324.920000 ;
+ RECT 982.420000 319.000000 983.520000 319.480000 ;
+ RECT 982.420000 297.240000 983.520000 297.720000 ;
+ RECT 982.420000 302.680000 983.520000 303.160000 ;
+ RECT 982.420000 308.120000 983.520000 308.600000 ;
+ RECT 982.420000 313.560000 983.520000 314.040000 ;
+ RECT 1036.730000 286.360000 1037.730000 286.840000 ;
+ RECT 1036.730000 291.800000 1037.730000 292.280000 ;
+ RECT 1027.420000 291.800000 1028.520000 292.280000 ;
+ RECT 1027.420000 286.360000 1028.520000 286.840000 ;
+ RECT 1027.420000 280.920000 1028.520000 281.400000 ;
+ RECT 1027.420000 275.480000 1028.520000 275.960000 ;
+ RECT 1036.730000 280.920000 1037.730000 281.400000 ;
+ RECT 1036.730000 275.480000 1037.730000 275.960000 ;
+ RECT 1036.730000 259.160000 1037.730000 259.640000 ;
+ RECT 1036.730000 264.600000 1037.730000 265.080000 ;
+ RECT 1036.730000 270.040000 1037.730000 270.520000 ;
+ RECT 1027.420000 264.600000 1028.520000 265.080000 ;
+ RECT 1027.420000 259.160000 1028.520000 259.640000 ;
+ RECT 1027.420000 270.040000 1028.520000 270.520000 ;
+ RECT 1027.420000 253.720000 1028.520000 254.200000 ;
+ RECT 1027.420000 248.280000 1028.520000 248.760000 ;
+ RECT 1036.730000 253.720000 1037.730000 254.200000 ;
+ RECT 1036.730000 248.280000 1037.730000 248.760000 ;
+ RECT 982.420000 291.800000 983.520000 292.280000 ;
+ RECT 982.420000 286.360000 983.520000 286.840000 ;
+ RECT 982.420000 280.920000 983.520000 281.400000 ;
+ RECT 982.420000 275.480000 983.520000 275.960000 ;
+ RECT 982.420000 264.600000 983.520000 265.080000 ;
+ RECT 982.420000 259.160000 983.520000 259.640000 ;
+ RECT 982.420000 253.720000 983.520000 254.200000 ;
+ RECT 982.420000 248.280000 983.520000 248.760000 ;
+ RECT 982.420000 270.040000 983.520000 270.520000 ;
+ RECT 937.420000 335.320000 938.520000 335.800000 ;
+ RECT 937.420000 329.880000 938.520000 330.360000 ;
+ RECT 937.420000 324.440000 938.520000 324.920000 ;
+ RECT 892.420000 335.320000 893.520000 335.800000 ;
+ RECT 892.420000 329.880000 893.520000 330.360000 ;
+ RECT 892.420000 324.440000 893.520000 324.920000 ;
+ RECT 937.420000 308.120000 938.520000 308.600000 ;
+ RECT 937.420000 302.680000 938.520000 303.160000 ;
+ RECT 937.420000 297.240000 938.520000 297.720000 ;
+ RECT 937.420000 313.560000 938.520000 314.040000 ;
+ RECT 937.420000 319.000000 938.520000 319.480000 ;
+ RECT 892.420000 319.000000 893.520000 319.480000 ;
+ RECT 892.420000 308.120000 893.520000 308.600000 ;
+ RECT 892.420000 302.680000 893.520000 303.160000 ;
+ RECT 892.420000 297.240000 893.520000 297.720000 ;
+ RECT 892.420000 313.560000 893.520000 314.040000 ;
+ RECT 847.420000 335.320000 848.520000 335.800000 ;
+ RECT 843.290000 335.320000 844.290000 335.800000 ;
+ RECT 843.290000 329.880000 844.290000 330.360000 ;
+ RECT 847.420000 329.880000 848.520000 330.360000 ;
+ RECT 847.420000 324.440000 848.520000 324.920000 ;
+ RECT 843.290000 324.440000 844.290000 324.920000 ;
+ RECT 847.420000 319.000000 848.520000 319.480000 ;
+ RECT 843.290000 319.000000 844.290000 319.480000 ;
+ RECT 847.420000 313.560000 848.520000 314.040000 ;
+ RECT 843.290000 313.560000 844.290000 314.040000 ;
+ RECT 847.420000 302.680000 848.520000 303.160000 ;
+ RECT 843.290000 302.680000 844.290000 303.160000 ;
+ RECT 847.420000 297.240000 848.520000 297.720000 ;
+ RECT 843.290000 297.240000 844.290000 297.720000 ;
+ RECT 847.420000 308.120000 848.520000 308.600000 ;
+ RECT 843.290000 308.120000 844.290000 308.600000 ;
+ RECT 937.420000 291.800000 938.520000 292.280000 ;
+ RECT 937.420000 286.360000 938.520000 286.840000 ;
+ RECT 937.420000 280.920000 938.520000 281.400000 ;
+ RECT 937.420000 275.480000 938.520000 275.960000 ;
+ RECT 892.420000 291.800000 893.520000 292.280000 ;
+ RECT 892.420000 286.360000 893.520000 286.840000 ;
+ RECT 892.420000 280.920000 893.520000 281.400000 ;
+ RECT 892.420000 275.480000 893.520000 275.960000 ;
+ RECT 937.420000 264.600000 938.520000 265.080000 ;
+ RECT 937.420000 248.280000 938.520000 248.760000 ;
+ RECT 937.420000 253.720000 938.520000 254.200000 ;
+ RECT 937.420000 259.160000 938.520000 259.640000 ;
+ RECT 937.420000 270.040000 938.520000 270.520000 ;
+ RECT 892.420000 248.280000 893.520000 248.760000 ;
+ RECT 892.420000 253.720000 893.520000 254.200000 ;
+ RECT 892.420000 259.160000 893.520000 259.640000 ;
+ RECT 892.420000 264.600000 893.520000 265.080000 ;
+ RECT 892.420000 270.040000 893.520000 270.520000 ;
+ RECT 847.420000 291.800000 848.520000 292.280000 ;
+ RECT 843.290000 291.800000 844.290000 292.280000 ;
+ RECT 847.420000 286.360000 848.520000 286.840000 ;
+ RECT 843.290000 286.360000 844.290000 286.840000 ;
+ RECT 847.420000 280.920000 848.520000 281.400000 ;
+ RECT 843.290000 280.920000 844.290000 281.400000 ;
+ RECT 847.420000 275.480000 848.520000 275.960000 ;
+ RECT 843.290000 275.480000 844.290000 275.960000 ;
+ RECT 847.420000 270.040000 848.520000 270.520000 ;
+ RECT 847.420000 264.600000 848.520000 265.080000 ;
+ RECT 843.290000 270.040000 844.290000 270.520000 ;
+ RECT 843.290000 264.600000 844.290000 265.080000 ;
+ RECT 847.420000 259.160000 848.520000 259.640000 ;
+ RECT 843.290000 259.160000 844.290000 259.640000 ;
+ RECT 847.420000 253.720000 848.520000 254.200000 ;
+ RECT 843.290000 253.720000 844.290000 254.200000 ;
+ RECT 847.420000 248.280000 848.520000 248.760000 ;
+ RECT 843.290000 248.280000 844.290000 248.760000 ;
+ RECT 1027.420000 242.840000 1028.520000 243.320000 ;
+ RECT 1027.420000 237.400000 1028.520000 237.880000 ;
+ RECT 1036.730000 242.840000 1037.730000 243.320000 ;
+ RECT 1036.730000 237.400000 1037.730000 237.880000 ;
+ RECT 1036.730000 221.080000 1037.730000 221.560000 ;
+ RECT 1036.730000 226.520000 1037.730000 227.000000 ;
+ RECT 1036.730000 231.960000 1037.730000 232.440000 ;
+ RECT 1027.420000 231.960000 1028.520000 232.440000 ;
+ RECT 1027.420000 226.520000 1028.520000 227.000000 ;
+ RECT 1027.420000 221.080000 1028.520000 221.560000 ;
+ RECT 1027.420000 210.200000 1028.520000 210.680000 ;
+ RECT 1027.420000 215.640000 1028.520000 216.120000 ;
+ RECT 1036.730000 215.640000 1037.730000 216.120000 ;
+ RECT 1036.730000 210.200000 1037.730000 210.680000 ;
+ RECT 1036.730000 199.320000 1037.730000 199.800000 ;
+ RECT 1036.730000 204.760000 1037.730000 205.240000 ;
+ RECT 1027.420000 199.320000 1028.520000 199.800000 ;
+ RECT 1027.420000 204.760000 1028.520000 205.240000 ;
+ RECT 982.420000 242.840000 983.520000 243.320000 ;
+ RECT 982.420000 237.400000 983.520000 237.880000 ;
+ RECT 982.420000 231.960000 983.520000 232.440000 ;
+ RECT 982.420000 226.520000 983.520000 227.000000 ;
+ RECT 982.420000 221.080000 983.520000 221.560000 ;
+ RECT 982.420000 199.320000 983.520000 199.800000 ;
+ RECT 982.420000 204.760000 983.520000 205.240000 ;
+ RECT 982.420000 210.200000 983.520000 210.680000 ;
+ RECT 982.420000 215.640000 983.520000 216.120000 ;
+ RECT 1027.420000 193.880000 1028.520000 194.360000 ;
+ RECT 1027.420000 188.440000 1028.520000 188.920000 ;
+ RECT 1036.730000 193.880000 1037.730000 194.360000 ;
+ RECT 1036.730000 188.440000 1037.730000 188.920000 ;
+ RECT 1027.420000 177.560000 1028.520000 178.040000 ;
+ RECT 1027.420000 172.120000 1028.520000 172.600000 ;
+ RECT 1036.730000 177.560000 1037.730000 178.040000 ;
+ RECT 1036.730000 172.120000 1037.730000 172.600000 ;
+ RECT 1027.420000 183.000000 1028.520000 183.480000 ;
+ RECT 1036.730000 183.000000 1037.730000 183.480000 ;
+ RECT 1036.730000 161.240000 1037.730000 161.720000 ;
+ RECT 1036.730000 166.680000 1037.730000 167.160000 ;
+ RECT 1027.420000 166.680000 1028.520000 167.160000 ;
+ RECT 1027.420000 161.240000 1028.520000 161.720000 ;
+ RECT 1027.420000 155.800000 1028.520000 156.280000 ;
+ RECT 1027.420000 150.360000 1028.520000 150.840000 ;
+ RECT 1036.730000 155.800000 1037.730000 156.280000 ;
+ RECT 1036.730000 150.360000 1037.730000 150.840000 ;
+ RECT 982.420000 193.880000 983.520000 194.360000 ;
+ RECT 982.420000 188.440000 983.520000 188.920000 ;
+ RECT 982.420000 183.000000 983.520000 183.480000 ;
+ RECT 982.420000 177.560000 983.520000 178.040000 ;
+ RECT 982.420000 172.120000 983.520000 172.600000 ;
+ RECT 982.420000 166.680000 983.520000 167.160000 ;
+ RECT 982.420000 161.240000 983.520000 161.720000 ;
+ RECT 982.420000 155.800000 983.520000 156.280000 ;
+ RECT 982.420000 150.360000 983.520000 150.840000 ;
+ RECT 937.420000 242.840000 938.520000 243.320000 ;
+ RECT 937.420000 237.400000 938.520000 237.880000 ;
+ RECT 937.420000 231.960000 938.520000 232.440000 ;
+ RECT 937.420000 226.520000 938.520000 227.000000 ;
+ RECT 937.420000 221.080000 938.520000 221.560000 ;
+ RECT 892.420000 242.840000 893.520000 243.320000 ;
+ RECT 892.420000 237.400000 893.520000 237.880000 ;
+ RECT 892.420000 231.960000 893.520000 232.440000 ;
+ RECT 892.420000 226.520000 893.520000 227.000000 ;
+ RECT 892.420000 221.080000 893.520000 221.560000 ;
+ RECT 937.420000 215.640000 938.520000 216.120000 ;
+ RECT 937.420000 210.200000 938.520000 210.680000 ;
+ RECT 937.420000 204.760000 938.520000 205.240000 ;
+ RECT 937.420000 199.320000 938.520000 199.800000 ;
+ RECT 892.420000 210.200000 893.520000 210.680000 ;
+ RECT 892.420000 204.760000 893.520000 205.240000 ;
+ RECT 892.420000 199.320000 893.520000 199.800000 ;
+ RECT 892.420000 215.640000 893.520000 216.120000 ;
+ RECT 847.420000 242.840000 848.520000 243.320000 ;
+ RECT 843.290000 242.840000 844.290000 243.320000 ;
+ RECT 847.420000 237.400000 848.520000 237.880000 ;
+ RECT 843.290000 237.400000 844.290000 237.880000 ;
+ RECT 847.420000 231.960000 848.520000 232.440000 ;
+ RECT 843.290000 231.960000 844.290000 232.440000 ;
+ RECT 847.420000 221.080000 848.520000 221.560000 ;
+ RECT 843.290000 221.080000 844.290000 221.560000 ;
+ RECT 843.290000 226.520000 844.290000 227.000000 ;
+ RECT 847.420000 226.520000 848.520000 227.000000 ;
+ RECT 847.420000 215.640000 848.520000 216.120000 ;
+ RECT 843.290000 215.640000 844.290000 216.120000 ;
+ RECT 847.420000 210.200000 848.520000 210.680000 ;
+ RECT 843.290000 210.200000 844.290000 210.680000 ;
+ RECT 847.420000 204.760000 848.520000 205.240000 ;
+ RECT 843.290000 204.760000 844.290000 205.240000 ;
+ RECT 847.420000 199.320000 848.520000 199.800000 ;
+ RECT 843.290000 199.320000 844.290000 199.800000 ;
+ RECT 937.420000 193.880000 938.520000 194.360000 ;
+ RECT 937.420000 188.440000 938.520000 188.920000 ;
+ RECT 937.420000 183.000000 938.520000 183.480000 ;
+ RECT 937.420000 177.560000 938.520000 178.040000 ;
+ RECT 937.420000 172.120000 938.520000 172.600000 ;
+ RECT 892.420000 193.880000 893.520000 194.360000 ;
+ RECT 892.420000 188.440000 893.520000 188.920000 ;
+ RECT 892.420000 183.000000 893.520000 183.480000 ;
+ RECT 892.420000 177.560000 893.520000 178.040000 ;
+ RECT 892.420000 172.120000 893.520000 172.600000 ;
+ RECT 937.420000 150.360000 938.520000 150.840000 ;
+ RECT 937.420000 155.800000 938.520000 156.280000 ;
+ RECT 937.420000 161.240000 938.520000 161.720000 ;
+ RECT 937.420000 166.680000 938.520000 167.160000 ;
+ RECT 892.420000 150.360000 893.520000 150.840000 ;
+ RECT 892.420000 155.800000 893.520000 156.280000 ;
+ RECT 892.420000 161.240000 893.520000 161.720000 ;
+ RECT 892.420000 166.680000 893.520000 167.160000 ;
+ RECT 847.420000 193.880000 848.520000 194.360000 ;
+ RECT 843.290000 193.880000 844.290000 194.360000 ;
+ RECT 847.420000 188.440000 848.520000 188.920000 ;
+ RECT 843.290000 188.440000 844.290000 188.920000 ;
+ RECT 847.420000 177.560000 848.520000 178.040000 ;
+ RECT 843.290000 177.560000 844.290000 178.040000 ;
+ RECT 847.420000 172.120000 848.520000 172.600000 ;
+ RECT 843.290000 172.120000 844.290000 172.600000 ;
+ RECT 847.420000 183.000000 848.520000 183.480000 ;
+ RECT 843.290000 183.000000 844.290000 183.480000 ;
+ RECT 847.420000 166.680000 848.520000 167.160000 ;
+ RECT 843.290000 166.680000 844.290000 167.160000 ;
+ RECT 847.420000 161.240000 848.520000 161.720000 ;
+ RECT 843.290000 161.240000 844.290000 161.720000 ;
+ RECT 847.420000 155.800000 848.520000 156.280000 ;
+ RECT 847.420000 150.360000 848.520000 150.840000 ;
+ RECT 843.290000 155.800000 844.290000 156.280000 ;
+ RECT 843.290000 150.360000 844.290000 150.840000 ;
+ RECT 840.460000 340.720000 1040.560000 341.720000 ;
+ RECT 840.460000 148.350000 1040.560000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 145.500000 844.290000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 344.760000 844.290000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 145.500000 1037.730000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 344.760000 1037.730000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 148.350000 841.460000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 148.350000 1040.560000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 340.720000 841.460000 341.720000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 340.720000 1040.560000 341.720000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 115.240000 844.290000 145.500000 ;
+ RECT 1036.730000 115.240000 1037.730000 145.500000 ;
+ RECT 847.420000 118.090000 848.520000 142.140000 ;
+ RECT 892.420000 118.090000 893.520000 142.140000 ;
+ RECT 937.420000 118.090000 938.520000 142.140000 ;
+ RECT 982.420000 118.090000 983.520000 142.140000 ;
+ RECT 1027.420000 118.090000 1028.520000 142.140000 ;
+ LAYER met3 ;
+ RECT 1036.730000 130.980000 1037.730000 131.460000 ;
+ RECT 1036.730000 136.420000 1037.730000 136.900000 ;
+ RECT 1027.420000 136.420000 1028.520000 136.900000 ;
+ RECT 1027.420000 130.980000 1028.520000 131.460000 ;
+ RECT 982.420000 130.980000 983.520000 131.460000 ;
+ RECT 982.420000 136.420000 983.520000 136.900000 ;
+ RECT 892.420000 130.980000 893.520000 131.460000 ;
+ RECT 937.420000 130.980000 938.520000 131.460000 ;
+ RECT 937.420000 136.420000 938.520000 136.900000 ;
+ RECT 892.420000 136.420000 893.520000 136.900000 ;
+ RECT 843.290000 130.980000 844.290000 131.460000 ;
+ RECT 847.420000 130.980000 848.520000 131.460000 ;
+ RECT 847.420000 136.420000 848.520000 136.900000 ;
+ RECT 843.290000 136.420000 844.290000 136.900000 ;
+ RECT 1036.730000 120.100000 1037.730000 120.580000 ;
+ RECT 1036.730000 125.540000 1037.730000 126.020000 ;
+ RECT 1027.420000 125.540000 1028.520000 126.020000 ;
+ RECT 1027.420000 120.100000 1028.520000 120.580000 ;
+ RECT 982.420000 120.100000 983.520000 120.580000 ;
+ RECT 982.420000 125.540000 983.520000 126.020000 ;
+ RECT 892.420000 120.100000 893.520000 120.580000 ;
+ RECT 937.420000 120.100000 938.520000 120.580000 ;
+ RECT 937.420000 125.540000 938.520000 126.020000 ;
+ RECT 892.420000 125.540000 893.520000 126.020000 ;
+ RECT 843.290000 125.540000 844.290000 126.020000 ;
+ RECT 847.420000 125.540000 848.520000 126.020000 ;
+ RECT 843.290000 120.100000 844.290000 120.580000 ;
+ RECT 847.420000 120.100000 848.520000 120.580000 ;
+ RECT 840.460000 141.140000 1040.560000 142.140000 ;
+ RECT 840.460000 118.090000 1040.560000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 118.090000 841.460000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 118.090000 1040.560000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 141.140000 841.460000 142.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 141.140000 1040.560000 142.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 115.240000 844.290000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 144.500000 844.290000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 115.240000 1037.730000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 144.500000 1037.730000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 3152.250000 1028.520000 3345.620000 ;
+ RECT 982.420000 3152.250000 983.520000 3345.620000 ;
+ RECT 1036.730000 3149.400000 1037.730000 3349.660000 ;
+ RECT 937.420000 3152.250000 938.520000 3345.620000 ;
+ RECT 892.420000 3152.250000 893.520000 3345.620000 ;
+ RECT 847.420000 3152.250000 848.520000 3345.620000 ;
+ RECT 843.290000 3149.400000 844.290000 3349.660000 ;
+ LAYER met3 ;
+ RECT 1027.420000 3339.220000 1028.520000 3339.700000 ;
+ RECT 1036.730000 3339.220000 1037.730000 3339.700000 ;
+ RECT 1036.730000 3328.340000 1037.730000 3328.820000 ;
+ RECT 1036.730000 3333.780000 1037.730000 3334.260000 ;
+ RECT 1027.420000 3333.780000 1028.520000 3334.260000 ;
+ RECT 1027.420000 3328.340000 1028.520000 3328.820000 ;
+ RECT 1027.420000 3322.900000 1028.520000 3323.380000 ;
+ RECT 1027.420000 3317.460000 1028.520000 3317.940000 ;
+ RECT 1036.730000 3322.900000 1037.730000 3323.380000 ;
+ RECT 1036.730000 3317.460000 1037.730000 3317.940000 ;
+ RECT 1027.420000 3301.140000 1028.520000 3301.620000 ;
+ RECT 1027.420000 3306.580000 1028.520000 3307.060000 ;
+ RECT 1036.730000 3306.580000 1037.730000 3307.060000 ;
+ RECT 1036.730000 3301.140000 1037.730000 3301.620000 ;
+ RECT 1027.420000 3312.020000 1028.520000 3312.500000 ;
+ RECT 1036.730000 3312.020000 1037.730000 3312.500000 ;
+ RECT 982.420000 3339.220000 983.520000 3339.700000 ;
+ RECT 982.420000 3333.780000 983.520000 3334.260000 ;
+ RECT 982.420000 3328.340000 983.520000 3328.820000 ;
+ RECT 982.420000 3322.900000 983.520000 3323.380000 ;
+ RECT 982.420000 3301.140000 983.520000 3301.620000 ;
+ RECT 982.420000 3306.580000 983.520000 3307.060000 ;
+ RECT 982.420000 3312.020000 983.520000 3312.500000 ;
+ RECT 982.420000 3317.460000 983.520000 3317.940000 ;
+ RECT 1036.730000 3290.260000 1037.730000 3290.740000 ;
+ RECT 1036.730000 3295.700000 1037.730000 3296.180000 ;
+ RECT 1027.420000 3295.700000 1028.520000 3296.180000 ;
+ RECT 1027.420000 3290.260000 1028.520000 3290.740000 ;
+ RECT 1027.420000 3284.820000 1028.520000 3285.300000 ;
+ RECT 1027.420000 3279.380000 1028.520000 3279.860000 ;
+ RECT 1036.730000 3284.820000 1037.730000 3285.300000 ;
+ RECT 1036.730000 3279.380000 1037.730000 3279.860000 ;
+ RECT 1036.730000 3263.060000 1037.730000 3263.540000 ;
+ RECT 1036.730000 3268.500000 1037.730000 3268.980000 ;
+ RECT 1036.730000 3273.940000 1037.730000 3274.420000 ;
+ RECT 1027.420000 3268.500000 1028.520000 3268.980000 ;
+ RECT 1027.420000 3263.060000 1028.520000 3263.540000 ;
+ RECT 1027.420000 3273.940000 1028.520000 3274.420000 ;
+ RECT 1027.420000 3257.620000 1028.520000 3258.100000 ;
+ RECT 1027.420000 3252.180000 1028.520000 3252.660000 ;
+ RECT 1036.730000 3257.620000 1037.730000 3258.100000 ;
+ RECT 1036.730000 3252.180000 1037.730000 3252.660000 ;
+ RECT 982.420000 3295.700000 983.520000 3296.180000 ;
+ RECT 982.420000 3290.260000 983.520000 3290.740000 ;
+ RECT 982.420000 3284.820000 983.520000 3285.300000 ;
+ RECT 982.420000 3279.380000 983.520000 3279.860000 ;
+ RECT 982.420000 3268.500000 983.520000 3268.980000 ;
+ RECT 982.420000 3263.060000 983.520000 3263.540000 ;
+ RECT 982.420000 3257.620000 983.520000 3258.100000 ;
+ RECT 982.420000 3252.180000 983.520000 3252.660000 ;
+ RECT 982.420000 3273.940000 983.520000 3274.420000 ;
+ RECT 937.420000 3339.220000 938.520000 3339.700000 ;
+ RECT 937.420000 3333.780000 938.520000 3334.260000 ;
+ RECT 937.420000 3328.340000 938.520000 3328.820000 ;
+ RECT 892.420000 3339.220000 893.520000 3339.700000 ;
+ RECT 892.420000 3333.780000 893.520000 3334.260000 ;
+ RECT 892.420000 3328.340000 893.520000 3328.820000 ;
+ RECT 937.420000 3312.020000 938.520000 3312.500000 ;
+ RECT 937.420000 3306.580000 938.520000 3307.060000 ;
+ RECT 937.420000 3301.140000 938.520000 3301.620000 ;
+ RECT 937.420000 3317.460000 938.520000 3317.940000 ;
+ RECT 937.420000 3322.900000 938.520000 3323.380000 ;
+ RECT 892.420000 3322.900000 893.520000 3323.380000 ;
+ RECT 892.420000 3312.020000 893.520000 3312.500000 ;
+ RECT 892.420000 3306.580000 893.520000 3307.060000 ;
+ RECT 892.420000 3301.140000 893.520000 3301.620000 ;
+ RECT 892.420000 3317.460000 893.520000 3317.940000 ;
+ RECT 847.420000 3339.220000 848.520000 3339.700000 ;
+ RECT 843.290000 3339.220000 844.290000 3339.700000 ;
+ RECT 843.290000 3333.780000 844.290000 3334.260000 ;
+ RECT 847.420000 3333.780000 848.520000 3334.260000 ;
+ RECT 847.420000 3328.340000 848.520000 3328.820000 ;
+ RECT 843.290000 3328.340000 844.290000 3328.820000 ;
+ RECT 847.420000 3322.900000 848.520000 3323.380000 ;
+ RECT 843.290000 3322.900000 844.290000 3323.380000 ;
+ RECT 847.420000 3317.460000 848.520000 3317.940000 ;
+ RECT 843.290000 3317.460000 844.290000 3317.940000 ;
+ RECT 847.420000 3306.580000 848.520000 3307.060000 ;
+ RECT 843.290000 3306.580000 844.290000 3307.060000 ;
+ RECT 847.420000 3301.140000 848.520000 3301.620000 ;
+ RECT 843.290000 3301.140000 844.290000 3301.620000 ;
+ RECT 847.420000 3312.020000 848.520000 3312.500000 ;
+ RECT 843.290000 3312.020000 844.290000 3312.500000 ;
+ RECT 937.420000 3295.700000 938.520000 3296.180000 ;
+ RECT 937.420000 3290.260000 938.520000 3290.740000 ;
+ RECT 937.420000 3284.820000 938.520000 3285.300000 ;
+ RECT 937.420000 3279.380000 938.520000 3279.860000 ;
+ RECT 892.420000 3295.700000 893.520000 3296.180000 ;
+ RECT 892.420000 3290.260000 893.520000 3290.740000 ;
+ RECT 892.420000 3284.820000 893.520000 3285.300000 ;
+ RECT 892.420000 3279.380000 893.520000 3279.860000 ;
+ RECT 937.420000 3268.500000 938.520000 3268.980000 ;
+ RECT 937.420000 3252.180000 938.520000 3252.660000 ;
+ RECT 937.420000 3257.620000 938.520000 3258.100000 ;
+ RECT 937.420000 3263.060000 938.520000 3263.540000 ;
+ RECT 937.420000 3273.940000 938.520000 3274.420000 ;
+ RECT 892.420000 3252.180000 893.520000 3252.660000 ;
+ RECT 892.420000 3257.620000 893.520000 3258.100000 ;
+ RECT 892.420000 3263.060000 893.520000 3263.540000 ;
+ RECT 892.420000 3268.500000 893.520000 3268.980000 ;
+ RECT 892.420000 3273.940000 893.520000 3274.420000 ;
+ RECT 847.420000 3295.700000 848.520000 3296.180000 ;
+ RECT 843.290000 3295.700000 844.290000 3296.180000 ;
+ RECT 847.420000 3290.260000 848.520000 3290.740000 ;
+ RECT 843.290000 3290.260000 844.290000 3290.740000 ;
+ RECT 847.420000 3284.820000 848.520000 3285.300000 ;
+ RECT 843.290000 3284.820000 844.290000 3285.300000 ;
+ RECT 847.420000 3279.380000 848.520000 3279.860000 ;
+ RECT 843.290000 3279.380000 844.290000 3279.860000 ;
+ RECT 847.420000 3273.940000 848.520000 3274.420000 ;
+ RECT 847.420000 3268.500000 848.520000 3268.980000 ;
+ RECT 843.290000 3273.940000 844.290000 3274.420000 ;
+ RECT 843.290000 3268.500000 844.290000 3268.980000 ;
+ RECT 847.420000 3263.060000 848.520000 3263.540000 ;
+ RECT 843.290000 3263.060000 844.290000 3263.540000 ;
+ RECT 847.420000 3257.620000 848.520000 3258.100000 ;
+ RECT 843.290000 3257.620000 844.290000 3258.100000 ;
+ RECT 847.420000 3252.180000 848.520000 3252.660000 ;
+ RECT 843.290000 3252.180000 844.290000 3252.660000 ;
+ RECT 1027.420000 3246.740000 1028.520000 3247.220000 ;
+ RECT 1027.420000 3241.300000 1028.520000 3241.780000 ;
+ RECT 1036.730000 3246.740000 1037.730000 3247.220000 ;
+ RECT 1036.730000 3241.300000 1037.730000 3241.780000 ;
+ RECT 1036.730000 3224.980000 1037.730000 3225.460000 ;
+ RECT 1036.730000 3230.420000 1037.730000 3230.900000 ;
+ RECT 1036.730000 3235.860000 1037.730000 3236.340000 ;
+ RECT 1027.420000 3235.860000 1028.520000 3236.340000 ;
+ RECT 1027.420000 3230.420000 1028.520000 3230.900000 ;
+ RECT 1027.420000 3224.980000 1028.520000 3225.460000 ;
+ RECT 1027.420000 3214.100000 1028.520000 3214.580000 ;
+ RECT 1027.420000 3219.540000 1028.520000 3220.020000 ;
+ RECT 1036.730000 3219.540000 1037.730000 3220.020000 ;
+ RECT 1036.730000 3214.100000 1037.730000 3214.580000 ;
+ RECT 1036.730000 3203.220000 1037.730000 3203.700000 ;
+ RECT 1036.730000 3208.660000 1037.730000 3209.140000 ;
+ RECT 1027.420000 3203.220000 1028.520000 3203.700000 ;
+ RECT 1027.420000 3208.660000 1028.520000 3209.140000 ;
+ RECT 982.420000 3246.740000 983.520000 3247.220000 ;
+ RECT 982.420000 3241.300000 983.520000 3241.780000 ;
+ RECT 982.420000 3235.860000 983.520000 3236.340000 ;
+ RECT 982.420000 3230.420000 983.520000 3230.900000 ;
+ RECT 982.420000 3224.980000 983.520000 3225.460000 ;
+ RECT 982.420000 3203.220000 983.520000 3203.700000 ;
+ RECT 982.420000 3208.660000 983.520000 3209.140000 ;
+ RECT 982.420000 3214.100000 983.520000 3214.580000 ;
+ RECT 982.420000 3219.540000 983.520000 3220.020000 ;
+ RECT 1027.420000 3197.780000 1028.520000 3198.260000 ;
+ RECT 1027.420000 3192.340000 1028.520000 3192.820000 ;
+ RECT 1036.730000 3197.780000 1037.730000 3198.260000 ;
+ RECT 1036.730000 3192.340000 1037.730000 3192.820000 ;
+ RECT 1027.420000 3181.460000 1028.520000 3181.940000 ;
+ RECT 1027.420000 3176.020000 1028.520000 3176.500000 ;
+ RECT 1036.730000 3181.460000 1037.730000 3181.940000 ;
+ RECT 1036.730000 3176.020000 1037.730000 3176.500000 ;
+ RECT 1027.420000 3186.900000 1028.520000 3187.380000 ;
+ RECT 1036.730000 3186.900000 1037.730000 3187.380000 ;
+ RECT 1036.730000 3165.140000 1037.730000 3165.620000 ;
+ RECT 1036.730000 3170.580000 1037.730000 3171.060000 ;
+ RECT 1027.420000 3170.580000 1028.520000 3171.060000 ;
+ RECT 1027.420000 3165.140000 1028.520000 3165.620000 ;
+ RECT 1027.420000 3159.700000 1028.520000 3160.180000 ;
+ RECT 1027.420000 3154.260000 1028.520000 3154.740000 ;
+ RECT 1036.730000 3159.700000 1037.730000 3160.180000 ;
+ RECT 1036.730000 3154.260000 1037.730000 3154.740000 ;
+ RECT 982.420000 3197.780000 983.520000 3198.260000 ;
+ RECT 982.420000 3192.340000 983.520000 3192.820000 ;
+ RECT 982.420000 3186.900000 983.520000 3187.380000 ;
+ RECT 982.420000 3181.460000 983.520000 3181.940000 ;
+ RECT 982.420000 3176.020000 983.520000 3176.500000 ;
+ RECT 982.420000 3170.580000 983.520000 3171.060000 ;
+ RECT 982.420000 3165.140000 983.520000 3165.620000 ;
+ RECT 982.420000 3159.700000 983.520000 3160.180000 ;
+ RECT 982.420000 3154.260000 983.520000 3154.740000 ;
+ RECT 937.420000 3246.740000 938.520000 3247.220000 ;
+ RECT 937.420000 3241.300000 938.520000 3241.780000 ;
+ RECT 937.420000 3235.860000 938.520000 3236.340000 ;
+ RECT 937.420000 3230.420000 938.520000 3230.900000 ;
+ RECT 937.420000 3224.980000 938.520000 3225.460000 ;
+ RECT 892.420000 3246.740000 893.520000 3247.220000 ;
+ RECT 892.420000 3241.300000 893.520000 3241.780000 ;
+ RECT 892.420000 3235.860000 893.520000 3236.340000 ;
+ RECT 892.420000 3230.420000 893.520000 3230.900000 ;
+ RECT 892.420000 3224.980000 893.520000 3225.460000 ;
+ RECT 937.420000 3219.540000 938.520000 3220.020000 ;
+ RECT 937.420000 3214.100000 938.520000 3214.580000 ;
+ RECT 937.420000 3208.660000 938.520000 3209.140000 ;
+ RECT 937.420000 3203.220000 938.520000 3203.700000 ;
+ RECT 892.420000 3214.100000 893.520000 3214.580000 ;
+ RECT 892.420000 3208.660000 893.520000 3209.140000 ;
+ RECT 892.420000 3203.220000 893.520000 3203.700000 ;
+ RECT 892.420000 3219.540000 893.520000 3220.020000 ;
+ RECT 847.420000 3246.740000 848.520000 3247.220000 ;
+ RECT 843.290000 3246.740000 844.290000 3247.220000 ;
+ RECT 847.420000 3241.300000 848.520000 3241.780000 ;
+ RECT 843.290000 3241.300000 844.290000 3241.780000 ;
+ RECT 847.420000 3235.860000 848.520000 3236.340000 ;
+ RECT 843.290000 3235.860000 844.290000 3236.340000 ;
+ RECT 847.420000 3224.980000 848.520000 3225.460000 ;
+ RECT 843.290000 3224.980000 844.290000 3225.460000 ;
+ RECT 843.290000 3230.420000 844.290000 3230.900000 ;
+ RECT 847.420000 3230.420000 848.520000 3230.900000 ;
+ RECT 847.420000 3219.540000 848.520000 3220.020000 ;
+ RECT 843.290000 3219.540000 844.290000 3220.020000 ;
+ RECT 847.420000 3214.100000 848.520000 3214.580000 ;
+ RECT 843.290000 3214.100000 844.290000 3214.580000 ;
+ RECT 847.420000 3208.660000 848.520000 3209.140000 ;
+ RECT 843.290000 3208.660000 844.290000 3209.140000 ;
+ RECT 847.420000 3203.220000 848.520000 3203.700000 ;
+ RECT 843.290000 3203.220000 844.290000 3203.700000 ;
+ RECT 937.420000 3197.780000 938.520000 3198.260000 ;
+ RECT 937.420000 3192.340000 938.520000 3192.820000 ;
+ RECT 937.420000 3186.900000 938.520000 3187.380000 ;
+ RECT 937.420000 3181.460000 938.520000 3181.940000 ;
+ RECT 937.420000 3176.020000 938.520000 3176.500000 ;
+ RECT 892.420000 3197.780000 893.520000 3198.260000 ;
+ RECT 892.420000 3192.340000 893.520000 3192.820000 ;
+ RECT 892.420000 3186.900000 893.520000 3187.380000 ;
+ RECT 892.420000 3181.460000 893.520000 3181.940000 ;
+ RECT 892.420000 3176.020000 893.520000 3176.500000 ;
+ RECT 937.420000 3154.260000 938.520000 3154.740000 ;
+ RECT 937.420000 3159.700000 938.520000 3160.180000 ;
+ RECT 937.420000 3165.140000 938.520000 3165.620000 ;
+ RECT 937.420000 3170.580000 938.520000 3171.060000 ;
+ RECT 892.420000 3154.260000 893.520000 3154.740000 ;
+ RECT 892.420000 3159.700000 893.520000 3160.180000 ;
+ RECT 892.420000 3165.140000 893.520000 3165.620000 ;
+ RECT 892.420000 3170.580000 893.520000 3171.060000 ;
+ RECT 847.420000 3197.780000 848.520000 3198.260000 ;
+ RECT 843.290000 3197.780000 844.290000 3198.260000 ;
+ RECT 847.420000 3192.340000 848.520000 3192.820000 ;
+ RECT 843.290000 3192.340000 844.290000 3192.820000 ;
+ RECT 847.420000 3181.460000 848.520000 3181.940000 ;
+ RECT 843.290000 3181.460000 844.290000 3181.940000 ;
+ RECT 847.420000 3176.020000 848.520000 3176.500000 ;
+ RECT 843.290000 3176.020000 844.290000 3176.500000 ;
+ RECT 847.420000 3186.900000 848.520000 3187.380000 ;
+ RECT 843.290000 3186.900000 844.290000 3187.380000 ;
+ RECT 847.420000 3170.580000 848.520000 3171.060000 ;
+ RECT 843.290000 3170.580000 844.290000 3171.060000 ;
+ RECT 847.420000 3165.140000 848.520000 3165.620000 ;
+ RECT 843.290000 3165.140000 844.290000 3165.620000 ;
+ RECT 847.420000 3159.700000 848.520000 3160.180000 ;
+ RECT 847.420000 3154.260000 848.520000 3154.740000 ;
+ RECT 843.290000 3159.700000 844.290000 3160.180000 ;
+ RECT 843.290000 3154.260000 844.290000 3154.740000 ;
+ RECT 840.460000 3344.620000 1040.560000 3345.620000 ;
+ RECT 840.460000 3152.250000 1040.560000 3153.250000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 3149.400000 844.290000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 3348.660000 844.290000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 3149.400000 1037.730000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 3348.660000 1037.730000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 3152.250000 841.460000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 3152.250000 1040.560000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 3344.620000 841.460000 3345.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 3344.620000 1040.560000 3345.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 2951.990000 1028.520000 3145.360000 ;
+ RECT 982.420000 2951.990000 983.520000 3145.360000 ;
+ RECT 1036.730000 2949.140000 1037.730000 3149.400000 ;
+ RECT 937.420000 2951.990000 938.520000 3145.360000 ;
+ RECT 892.420000 2951.990000 893.520000 3145.360000 ;
+ RECT 847.420000 2951.990000 848.520000 3145.360000 ;
+ RECT 843.290000 2949.140000 844.290000 3149.400000 ;
+ LAYER met3 ;
+ RECT 1027.420000 3138.960000 1028.520000 3139.440000 ;
+ RECT 1036.730000 3138.960000 1037.730000 3139.440000 ;
+ RECT 1036.730000 3128.080000 1037.730000 3128.560000 ;
+ RECT 1036.730000 3133.520000 1037.730000 3134.000000 ;
+ RECT 1027.420000 3133.520000 1028.520000 3134.000000 ;
+ RECT 1027.420000 3128.080000 1028.520000 3128.560000 ;
+ RECT 1027.420000 3122.640000 1028.520000 3123.120000 ;
+ RECT 1027.420000 3117.200000 1028.520000 3117.680000 ;
+ RECT 1036.730000 3122.640000 1037.730000 3123.120000 ;
+ RECT 1036.730000 3117.200000 1037.730000 3117.680000 ;
+ RECT 1027.420000 3100.880000 1028.520000 3101.360000 ;
+ RECT 1027.420000 3106.320000 1028.520000 3106.800000 ;
+ RECT 1036.730000 3106.320000 1037.730000 3106.800000 ;
+ RECT 1036.730000 3100.880000 1037.730000 3101.360000 ;
+ RECT 1027.420000 3111.760000 1028.520000 3112.240000 ;
+ RECT 1036.730000 3111.760000 1037.730000 3112.240000 ;
+ RECT 982.420000 3138.960000 983.520000 3139.440000 ;
+ RECT 982.420000 3133.520000 983.520000 3134.000000 ;
+ RECT 982.420000 3128.080000 983.520000 3128.560000 ;
+ RECT 982.420000 3122.640000 983.520000 3123.120000 ;
+ RECT 982.420000 3100.880000 983.520000 3101.360000 ;
+ RECT 982.420000 3106.320000 983.520000 3106.800000 ;
+ RECT 982.420000 3111.760000 983.520000 3112.240000 ;
+ RECT 982.420000 3117.200000 983.520000 3117.680000 ;
+ RECT 1036.730000 3090.000000 1037.730000 3090.480000 ;
+ RECT 1036.730000 3095.440000 1037.730000 3095.920000 ;
+ RECT 1027.420000 3095.440000 1028.520000 3095.920000 ;
+ RECT 1027.420000 3090.000000 1028.520000 3090.480000 ;
+ RECT 1027.420000 3084.560000 1028.520000 3085.040000 ;
+ RECT 1027.420000 3079.120000 1028.520000 3079.600000 ;
+ RECT 1036.730000 3084.560000 1037.730000 3085.040000 ;
+ RECT 1036.730000 3079.120000 1037.730000 3079.600000 ;
+ RECT 1036.730000 3062.800000 1037.730000 3063.280000 ;
+ RECT 1036.730000 3068.240000 1037.730000 3068.720000 ;
+ RECT 1036.730000 3073.680000 1037.730000 3074.160000 ;
+ RECT 1027.420000 3068.240000 1028.520000 3068.720000 ;
+ RECT 1027.420000 3062.800000 1028.520000 3063.280000 ;
+ RECT 1027.420000 3073.680000 1028.520000 3074.160000 ;
+ RECT 1027.420000 3057.360000 1028.520000 3057.840000 ;
+ RECT 1027.420000 3051.920000 1028.520000 3052.400000 ;
+ RECT 1036.730000 3057.360000 1037.730000 3057.840000 ;
+ RECT 1036.730000 3051.920000 1037.730000 3052.400000 ;
+ RECT 982.420000 3095.440000 983.520000 3095.920000 ;
+ RECT 982.420000 3090.000000 983.520000 3090.480000 ;
+ RECT 982.420000 3084.560000 983.520000 3085.040000 ;
+ RECT 982.420000 3079.120000 983.520000 3079.600000 ;
+ RECT 982.420000 3068.240000 983.520000 3068.720000 ;
+ RECT 982.420000 3062.800000 983.520000 3063.280000 ;
+ RECT 982.420000 3057.360000 983.520000 3057.840000 ;
+ RECT 982.420000 3051.920000 983.520000 3052.400000 ;
+ RECT 982.420000 3073.680000 983.520000 3074.160000 ;
+ RECT 937.420000 3138.960000 938.520000 3139.440000 ;
+ RECT 937.420000 3133.520000 938.520000 3134.000000 ;
+ RECT 937.420000 3128.080000 938.520000 3128.560000 ;
+ RECT 892.420000 3138.960000 893.520000 3139.440000 ;
+ RECT 892.420000 3133.520000 893.520000 3134.000000 ;
+ RECT 892.420000 3128.080000 893.520000 3128.560000 ;
+ RECT 937.420000 3111.760000 938.520000 3112.240000 ;
+ RECT 937.420000 3106.320000 938.520000 3106.800000 ;
+ RECT 937.420000 3100.880000 938.520000 3101.360000 ;
+ RECT 937.420000 3117.200000 938.520000 3117.680000 ;
+ RECT 937.420000 3122.640000 938.520000 3123.120000 ;
+ RECT 892.420000 3122.640000 893.520000 3123.120000 ;
+ RECT 892.420000 3111.760000 893.520000 3112.240000 ;
+ RECT 892.420000 3106.320000 893.520000 3106.800000 ;
+ RECT 892.420000 3100.880000 893.520000 3101.360000 ;
+ RECT 892.420000 3117.200000 893.520000 3117.680000 ;
+ RECT 847.420000 3138.960000 848.520000 3139.440000 ;
+ RECT 843.290000 3138.960000 844.290000 3139.440000 ;
+ RECT 843.290000 3133.520000 844.290000 3134.000000 ;
+ RECT 847.420000 3133.520000 848.520000 3134.000000 ;
+ RECT 847.420000 3128.080000 848.520000 3128.560000 ;
+ RECT 843.290000 3128.080000 844.290000 3128.560000 ;
+ RECT 847.420000 3122.640000 848.520000 3123.120000 ;
+ RECT 843.290000 3122.640000 844.290000 3123.120000 ;
+ RECT 847.420000 3117.200000 848.520000 3117.680000 ;
+ RECT 843.290000 3117.200000 844.290000 3117.680000 ;
+ RECT 847.420000 3106.320000 848.520000 3106.800000 ;
+ RECT 843.290000 3106.320000 844.290000 3106.800000 ;
+ RECT 847.420000 3100.880000 848.520000 3101.360000 ;
+ RECT 843.290000 3100.880000 844.290000 3101.360000 ;
+ RECT 847.420000 3111.760000 848.520000 3112.240000 ;
+ RECT 843.290000 3111.760000 844.290000 3112.240000 ;
+ RECT 937.420000 3095.440000 938.520000 3095.920000 ;
+ RECT 937.420000 3090.000000 938.520000 3090.480000 ;
+ RECT 937.420000 3084.560000 938.520000 3085.040000 ;
+ RECT 937.420000 3079.120000 938.520000 3079.600000 ;
+ RECT 892.420000 3095.440000 893.520000 3095.920000 ;
+ RECT 892.420000 3090.000000 893.520000 3090.480000 ;
+ RECT 892.420000 3084.560000 893.520000 3085.040000 ;
+ RECT 892.420000 3079.120000 893.520000 3079.600000 ;
+ RECT 937.420000 3068.240000 938.520000 3068.720000 ;
+ RECT 937.420000 3051.920000 938.520000 3052.400000 ;
+ RECT 937.420000 3057.360000 938.520000 3057.840000 ;
+ RECT 937.420000 3062.800000 938.520000 3063.280000 ;
+ RECT 937.420000 3073.680000 938.520000 3074.160000 ;
+ RECT 892.420000 3051.920000 893.520000 3052.400000 ;
+ RECT 892.420000 3057.360000 893.520000 3057.840000 ;
+ RECT 892.420000 3062.800000 893.520000 3063.280000 ;
+ RECT 892.420000 3068.240000 893.520000 3068.720000 ;
+ RECT 892.420000 3073.680000 893.520000 3074.160000 ;
+ RECT 847.420000 3095.440000 848.520000 3095.920000 ;
+ RECT 843.290000 3095.440000 844.290000 3095.920000 ;
+ RECT 847.420000 3090.000000 848.520000 3090.480000 ;
+ RECT 843.290000 3090.000000 844.290000 3090.480000 ;
+ RECT 847.420000 3084.560000 848.520000 3085.040000 ;
+ RECT 843.290000 3084.560000 844.290000 3085.040000 ;
+ RECT 847.420000 3079.120000 848.520000 3079.600000 ;
+ RECT 843.290000 3079.120000 844.290000 3079.600000 ;
+ RECT 847.420000 3073.680000 848.520000 3074.160000 ;
+ RECT 847.420000 3068.240000 848.520000 3068.720000 ;
+ RECT 843.290000 3073.680000 844.290000 3074.160000 ;
+ RECT 843.290000 3068.240000 844.290000 3068.720000 ;
+ RECT 847.420000 3062.800000 848.520000 3063.280000 ;
+ RECT 843.290000 3062.800000 844.290000 3063.280000 ;
+ RECT 847.420000 3057.360000 848.520000 3057.840000 ;
+ RECT 843.290000 3057.360000 844.290000 3057.840000 ;
+ RECT 847.420000 3051.920000 848.520000 3052.400000 ;
+ RECT 843.290000 3051.920000 844.290000 3052.400000 ;
+ RECT 1027.420000 3046.480000 1028.520000 3046.960000 ;
+ RECT 1027.420000 3041.040000 1028.520000 3041.520000 ;
+ RECT 1036.730000 3046.480000 1037.730000 3046.960000 ;
+ RECT 1036.730000 3041.040000 1037.730000 3041.520000 ;
+ RECT 1036.730000 3024.720000 1037.730000 3025.200000 ;
+ RECT 1036.730000 3030.160000 1037.730000 3030.640000 ;
+ RECT 1036.730000 3035.600000 1037.730000 3036.080000 ;
+ RECT 1027.420000 3035.600000 1028.520000 3036.080000 ;
+ RECT 1027.420000 3030.160000 1028.520000 3030.640000 ;
+ RECT 1027.420000 3024.720000 1028.520000 3025.200000 ;
+ RECT 1027.420000 3013.840000 1028.520000 3014.320000 ;
+ RECT 1027.420000 3019.280000 1028.520000 3019.760000 ;
+ RECT 1036.730000 3019.280000 1037.730000 3019.760000 ;
+ RECT 1036.730000 3013.840000 1037.730000 3014.320000 ;
+ RECT 1036.730000 3002.960000 1037.730000 3003.440000 ;
+ RECT 1036.730000 3008.400000 1037.730000 3008.880000 ;
+ RECT 1027.420000 3002.960000 1028.520000 3003.440000 ;
+ RECT 1027.420000 3008.400000 1028.520000 3008.880000 ;
+ RECT 982.420000 3046.480000 983.520000 3046.960000 ;
+ RECT 982.420000 3041.040000 983.520000 3041.520000 ;
+ RECT 982.420000 3035.600000 983.520000 3036.080000 ;
+ RECT 982.420000 3030.160000 983.520000 3030.640000 ;
+ RECT 982.420000 3024.720000 983.520000 3025.200000 ;
+ RECT 982.420000 3002.960000 983.520000 3003.440000 ;
+ RECT 982.420000 3008.400000 983.520000 3008.880000 ;
+ RECT 982.420000 3013.840000 983.520000 3014.320000 ;
+ RECT 982.420000 3019.280000 983.520000 3019.760000 ;
+ RECT 1027.420000 2997.520000 1028.520000 2998.000000 ;
+ RECT 1027.420000 2992.080000 1028.520000 2992.560000 ;
+ RECT 1036.730000 2997.520000 1037.730000 2998.000000 ;
+ RECT 1036.730000 2992.080000 1037.730000 2992.560000 ;
+ RECT 1027.420000 2981.200000 1028.520000 2981.680000 ;
+ RECT 1027.420000 2975.760000 1028.520000 2976.240000 ;
+ RECT 1036.730000 2981.200000 1037.730000 2981.680000 ;
+ RECT 1036.730000 2975.760000 1037.730000 2976.240000 ;
+ RECT 1027.420000 2986.640000 1028.520000 2987.120000 ;
+ RECT 1036.730000 2986.640000 1037.730000 2987.120000 ;
+ RECT 1036.730000 2964.880000 1037.730000 2965.360000 ;
+ RECT 1036.730000 2970.320000 1037.730000 2970.800000 ;
+ RECT 1027.420000 2970.320000 1028.520000 2970.800000 ;
+ RECT 1027.420000 2964.880000 1028.520000 2965.360000 ;
+ RECT 1027.420000 2959.440000 1028.520000 2959.920000 ;
+ RECT 1027.420000 2954.000000 1028.520000 2954.480000 ;
+ RECT 1036.730000 2959.440000 1037.730000 2959.920000 ;
+ RECT 1036.730000 2954.000000 1037.730000 2954.480000 ;
+ RECT 982.420000 2997.520000 983.520000 2998.000000 ;
+ RECT 982.420000 2992.080000 983.520000 2992.560000 ;
+ RECT 982.420000 2986.640000 983.520000 2987.120000 ;
+ RECT 982.420000 2981.200000 983.520000 2981.680000 ;
+ RECT 982.420000 2975.760000 983.520000 2976.240000 ;
+ RECT 982.420000 2970.320000 983.520000 2970.800000 ;
+ RECT 982.420000 2964.880000 983.520000 2965.360000 ;
+ RECT 982.420000 2959.440000 983.520000 2959.920000 ;
+ RECT 982.420000 2954.000000 983.520000 2954.480000 ;
+ RECT 937.420000 3046.480000 938.520000 3046.960000 ;
+ RECT 937.420000 3041.040000 938.520000 3041.520000 ;
+ RECT 937.420000 3035.600000 938.520000 3036.080000 ;
+ RECT 937.420000 3030.160000 938.520000 3030.640000 ;
+ RECT 937.420000 3024.720000 938.520000 3025.200000 ;
+ RECT 892.420000 3046.480000 893.520000 3046.960000 ;
+ RECT 892.420000 3041.040000 893.520000 3041.520000 ;
+ RECT 892.420000 3035.600000 893.520000 3036.080000 ;
+ RECT 892.420000 3030.160000 893.520000 3030.640000 ;
+ RECT 892.420000 3024.720000 893.520000 3025.200000 ;
+ RECT 937.420000 3019.280000 938.520000 3019.760000 ;
+ RECT 937.420000 3013.840000 938.520000 3014.320000 ;
+ RECT 937.420000 3008.400000 938.520000 3008.880000 ;
+ RECT 937.420000 3002.960000 938.520000 3003.440000 ;
+ RECT 892.420000 3013.840000 893.520000 3014.320000 ;
+ RECT 892.420000 3008.400000 893.520000 3008.880000 ;
+ RECT 892.420000 3002.960000 893.520000 3003.440000 ;
+ RECT 892.420000 3019.280000 893.520000 3019.760000 ;
+ RECT 847.420000 3046.480000 848.520000 3046.960000 ;
+ RECT 843.290000 3046.480000 844.290000 3046.960000 ;
+ RECT 847.420000 3041.040000 848.520000 3041.520000 ;
+ RECT 843.290000 3041.040000 844.290000 3041.520000 ;
+ RECT 847.420000 3035.600000 848.520000 3036.080000 ;
+ RECT 843.290000 3035.600000 844.290000 3036.080000 ;
+ RECT 847.420000 3024.720000 848.520000 3025.200000 ;
+ RECT 843.290000 3024.720000 844.290000 3025.200000 ;
+ RECT 843.290000 3030.160000 844.290000 3030.640000 ;
+ RECT 847.420000 3030.160000 848.520000 3030.640000 ;
+ RECT 847.420000 3019.280000 848.520000 3019.760000 ;
+ RECT 843.290000 3019.280000 844.290000 3019.760000 ;
+ RECT 847.420000 3013.840000 848.520000 3014.320000 ;
+ RECT 843.290000 3013.840000 844.290000 3014.320000 ;
+ RECT 847.420000 3008.400000 848.520000 3008.880000 ;
+ RECT 843.290000 3008.400000 844.290000 3008.880000 ;
+ RECT 847.420000 3002.960000 848.520000 3003.440000 ;
+ RECT 843.290000 3002.960000 844.290000 3003.440000 ;
+ RECT 937.420000 2997.520000 938.520000 2998.000000 ;
+ RECT 937.420000 2992.080000 938.520000 2992.560000 ;
+ RECT 937.420000 2986.640000 938.520000 2987.120000 ;
+ RECT 937.420000 2981.200000 938.520000 2981.680000 ;
+ RECT 937.420000 2975.760000 938.520000 2976.240000 ;
+ RECT 892.420000 2997.520000 893.520000 2998.000000 ;
+ RECT 892.420000 2992.080000 893.520000 2992.560000 ;
+ RECT 892.420000 2986.640000 893.520000 2987.120000 ;
+ RECT 892.420000 2981.200000 893.520000 2981.680000 ;
+ RECT 892.420000 2975.760000 893.520000 2976.240000 ;
+ RECT 937.420000 2954.000000 938.520000 2954.480000 ;
+ RECT 937.420000 2959.440000 938.520000 2959.920000 ;
+ RECT 937.420000 2964.880000 938.520000 2965.360000 ;
+ RECT 937.420000 2970.320000 938.520000 2970.800000 ;
+ RECT 892.420000 2954.000000 893.520000 2954.480000 ;
+ RECT 892.420000 2959.440000 893.520000 2959.920000 ;
+ RECT 892.420000 2964.880000 893.520000 2965.360000 ;
+ RECT 892.420000 2970.320000 893.520000 2970.800000 ;
+ RECT 847.420000 2997.520000 848.520000 2998.000000 ;
+ RECT 843.290000 2997.520000 844.290000 2998.000000 ;
+ RECT 847.420000 2992.080000 848.520000 2992.560000 ;
+ RECT 843.290000 2992.080000 844.290000 2992.560000 ;
+ RECT 847.420000 2981.200000 848.520000 2981.680000 ;
+ RECT 843.290000 2981.200000 844.290000 2981.680000 ;
+ RECT 847.420000 2975.760000 848.520000 2976.240000 ;
+ RECT 843.290000 2975.760000 844.290000 2976.240000 ;
+ RECT 847.420000 2986.640000 848.520000 2987.120000 ;
+ RECT 843.290000 2986.640000 844.290000 2987.120000 ;
+ RECT 847.420000 2970.320000 848.520000 2970.800000 ;
+ RECT 843.290000 2970.320000 844.290000 2970.800000 ;
+ RECT 847.420000 2964.880000 848.520000 2965.360000 ;
+ RECT 843.290000 2964.880000 844.290000 2965.360000 ;
+ RECT 847.420000 2959.440000 848.520000 2959.920000 ;
+ RECT 847.420000 2954.000000 848.520000 2954.480000 ;
+ RECT 843.290000 2959.440000 844.290000 2959.920000 ;
+ RECT 843.290000 2954.000000 844.290000 2954.480000 ;
+ RECT 840.460000 3144.360000 1040.560000 3145.360000 ;
+ RECT 840.460000 2951.990000 1040.560000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 2949.140000 844.290000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 3148.400000 844.290000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 2949.140000 1037.730000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 3148.400000 1037.730000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2951.990000 841.460000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2951.990000 1040.560000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 3144.360000 841.460000 3145.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 3144.360000 1040.560000 3145.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 2751.730000 1028.520000 2945.100000 ;
+ RECT 982.420000 2751.730000 983.520000 2945.100000 ;
+ RECT 1036.730000 2748.880000 1037.730000 2949.140000 ;
+ RECT 937.420000 2751.730000 938.520000 2945.100000 ;
+ RECT 892.420000 2751.730000 893.520000 2945.100000 ;
+ RECT 847.420000 2751.730000 848.520000 2945.100000 ;
+ RECT 843.290000 2748.880000 844.290000 2949.140000 ;
+ LAYER met3 ;
+ RECT 1027.420000 2938.700000 1028.520000 2939.180000 ;
+ RECT 1036.730000 2938.700000 1037.730000 2939.180000 ;
+ RECT 1036.730000 2927.820000 1037.730000 2928.300000 ;
+ RECT 1036.730000 2933.260000 1037.730000 2933.740000 ;
+ RECT 1027.420000 2933.260000 1028.520000 2933.740000 ;
+ RECT 1027.420000 2927.820000 1028.520000 2928.300000 ;
+ RECT 1027.420000 2922.380000 1028.520000 2922.860000 ;
+ RECT 1027.420000 2916.940000 1028.520000 2917.420000 ;
+ RECT 1036.730000 2922.380000 1037.730000 2922.860000 ;
+ RECT 1036.730000 2916.940000 1037.730000 2917.420000 ;
+ RECT 1027.420000 2900.620000 1028.520000 2901.100000 ;
+ RECT 1027.420000 2906.060000 1028.520000 2906.540000 ;
+ RECT 1036.730000 2906.060000 1037.730000 2906.540000 ;
+ RECT 1036.730000 2900.620000 1037.730000 2901.100000 ;
+ RECT 1027.420000 2911.500000 1028.520000 2911.980000 ;
+ RECT 1036.730000 2911.500000 1037.730000 2911.980000 ;
+ RECT 982.420000 2938.700000 983.520000 2939.180000 ;
+ RECT 982.420000 2933.260000 983.520000 2933.740000 ;
+ RECT 982.420000 2927.820000 983.520000 2928.300000 ;
+ RECT 982.420000 2922.380000 983.520000 2922.860000 ;
+ RECT 982.420000 2900.620000 983.520000 2901.100000 ;
+ RECT 982.420000 2906.060000 983.520000 2906.540000 ;
+ RECT 982.420000 2911.500000 983.520000 2911.980000 ;
+ RECT 982.420000 2916.940000 983.520000 2917.420000 ;
+ RECT 1036.730000 2889.740000 1037.730000 2890.220000 ;
+ RECT 1036.730000 2895.180000 1037.730000 2895.660000 ;
+ RECT 1027.420000 2895.180000 1028.520000 2895.660000 ;
+ RECT 1027.420000 2889.740000 1028.520000 2890.220000 ;
+ RECT 1027.420000 2884.300000 1028.520000 2884.780000 ;
+ RECT 1027.420000 2878.860000 1028.520000 2879.340000 ;
+ RECT 1036.730000 2884.300000 1037.730000 2884.780000 ;
+ RECT 1036.730000 2878.860000 1037.730000 2879.340000 ;
+ RECT 1036.730000 2862.540000 1037.730000 2863.020000 ;
+ RECT 1036.730000 2867.980000 1037.730000 2868.460000 ;
+ RECT 1036.730000 2873.420000 1037.730000 2873.900000 ;
+ RECT 1027.420000 2867.980000 1028.520000 2868.460000 ;
+ RECT 1027.420000 2862.540000 1028.520000 2863.020000 ;
+ RECT 1027.420000 2873.420000 1028.520000 2873.900000 ;
+ RECT 1027.420000 2857.100000 1028.520000 2857.580000 ;
+ RECT 1027.420000 2851.660000 1028.520000 2852.140000 ;
+ RECT 1036.730000 2857.100000 1037.730000 2857.580000 ;
+ RECT 1036.730000 2851.660000 1037.730000 2852.140000 ;
+ RECT 982.420000 2895.180000 983.520000 2895.660000 ;
+ RECT 982.420000 2889.740000 983.520000 2890.220000 ;
+ RECT 982.420000 2884.300000 983.520000 2884.780000 ;
+ RECT 982.420000 2878.860000 983.520000 2879.340000 ;
+ RECT 982.420000 2867.980000 983.520000 2868.460000 ;
+ RECT 982.420000 2862.540000 983.520000 2863.020000 ;
+ RECT 982.420000 2857.100000 983.520000 2857.580000 ;
+ RECT 982.420000 2851.660000 983.520000 2852.140000 ;
+ RECT 982.420000 2873.420000 983.520000 2873.900000 ;
+ RECT 937.420000 2938.700000 938.520000 2939.180000 ;
+ RECT 937.420000 2933.260000 938.520000 2933.740000 ;
+ RECT 937.420000 2927.820000 938.520000 2928.300000 ;
+ RECT 892.420000 2938.700000 893.520000 2939.180000 ;
+ RECT 892.420000 2933.260000 893.520000 2933.740000 ;
+ RECT 892.420000 2927.820000 893.520000 2928.300000 ;
+ RECT 937.420000 2911.500000 938.520000 2911.980000 ;
+ RECT 937.420000 2906.060000 938.520000 2906.540000 ;
+ RECT 937.420000 2900.620000 938.520000 2901.100000 ;
+ RECT 937.420000 2916.940000 938.520000 2917.420000 ;
+ RECT 937.420000 2922.380000 938.520000 2922.860000 ;
+ RECT 892.420000 2922.380000 893.520000 2922.860000 ;
+ RECT 892.420000 2911.500000 893.520000 2911.980000 ;
+ RECT 892.420000 2906.060000 893.520000 2906.540000 ;
+ RECT 892.420000 2900.620000 893.520000 2901.100000 ;
+ RECT 892.420000 2916.940000 893.520000 2917.420000 ;
+ RECT 847.420000 2938.700000 848.520000 2939.180000 ;
+ RECT 843.290000 2938.700000 844.290000 2939.180000 ;
+ RECT 843.290000 2933.260000 844.290000 2933.740000 ;
+ RECT 847.420000 2933.260000 848.520000 2933.740000 ;
+ RECT 847.420000 2927.820000 848.520000 2928.300000 ;
+ RECT 843.290000 2927.820000 844.290000 2928.300000 ;
+ RECT 847.420000 2922.380000 848.520000 2922.860000 ;
+ RECT 843.290000 2922.380000 844.290000 2922.860000 ;
+ RECT 847.420000 2916.940000 848.520000 2917.420000 ;
+ RECT 843.290000 2916.940000 844.290000 2917.420000 ;
+ RECT 847.420000 2906.060000 848.520000 2906.540000 ;
+ RECT 843.290000 2906.060000 844.290000 2906.540000 ;
+ RECT 847.420000 2900.620000 848.520000 2901.100000 ;
+ RECT 843.290000 2900.620000 844.290000 2901.100000 ;
+ RECT 847.420000 2911.500000 848.520000 2911.980000 ;
+ RECT 843.290000 2911.500000 844.290000 2911.980000 ;
+ RECT 937.420000 2895.180000 938.520000 2895.660000 ;
+ RECT 937.420000 2889.740000 938.520000 2890.220000 ;
+ RECT 937.420000 2884.300000 938.520000 2884.780000 ;
+ RECT 937.420000 2878.860000 938.520000 2879.340000 ;
+ RECT 892.420000 2895.180000 893.520000 2895.660000 ;
+ RECT 892.420000 2889.740000 893.520000 2890.220000 ;
+ RECT 892.420000 2884.300000 893.520000 2884.780000 ;
+ RECT 892.420000 2878.860000 893.520000 2879.340000 ;
+ RECT 937.420000 2867.980000 938.520000 2868.460000 ;
+ RECT 937.420000 2851.660000 938.520000 2852.140000 ;
+ RECT 937.420000 2857.100000 938.520000 2857.580000 ;
+ RECT 937.420000 2862.540000 938.520000 2863.020000 ;
+ RECT 937.420000 2873.420000 938.520000 2873.900000 ;
+ RECT 892.420000 2851.660000 893.520000 2852.140000 ;
+ RECT 892.420000 2857.100000 893.520000 2857.580000 ;
+ RECT 892.420000 2862.540000 893.520000 2863.020000 ;
+ RECT 892.420000 2867.980000 893.520000 2868.460000 ;
+ RECT 892.420000 2873.420000 893.520000 2873.900000 ;
+ RECT 847.420000 2895.180000 848.520000 2895.660000 ;
+ RECT 843.290000 2895.180000 844.290000 2895.660000 ;
+ RECT 847.420000 2889.740000 848.520000 2890.220000 ;
+ RECT 843.290000 2889.740000 844.290000 2890.220000 ;
+ RECT 847.420000 2884.300000 848.520000 2884.780000 ;
+ RECT 843.290000 2884.300000 844.290000 2884.780000 ;
+ RECT 847.420000 2878.860000 848.520000 2879.340000 ;
+ RECT 843.290000 2878.860000 844.290000 2879.340000 ;
+ RECT 847.420000 2873.420000 848.520000 2873.900000 ;
+ RECT 847.420000 2867.980000 848.520000 2868.460000 ;
+ RECT 843.290000 2873.420000 844.290000 2873.900000 ;
+ RECT 843.290000 2867.980000 844.290000 2868.460000 ;
+ RECT 847.420000 2862.540000 848.520000 2863.020000 ;
+ RECT 843.290000 2862.540000 844.290000 2863.020000 ;
+ RECT 847.420000 2857.100000 848.520000 2857.580000 ;
+ RECT 843.290000 2857.100000 844.290000 2857.580000 ;
+ RECT 847.420000 2851.660000 848.520000 2852.140000 ;
+ RECT 843.290000 2851.660000 844.290000 2852.140000 ;
+ RECT 1027.420000 2846.220000 1028.520000 2846.700000 ;
+ RECT 1027.420000 2840.780000 1028.520000 2841.260000 ;
+ RECT 1036.730000 2846.220000 1037.730000 2846.700000 ;
+ RECT 1036.730000 2840.780000 1037.730000 2841.260000 ;
+ RECT 1036.730000 2824.460000 1037.730000 2824.940000 ;
+ RECT 1036.730000 2829.900000 1037.730000 2830.380000 ;
+ RECT 1036.730000 2835.340000 1037.730000 2835.820000 ;
+ RECT 1027.420000 2835.340000 1028.520000 2835.820000 ;
+ RECT 1027.420000 2829.900000 1028.520000 2830.380000 ;
+ RECT 1027.420000 2824.460000 1028.520000 2824.940000 ;
+ RECT 1027.420000 2813.580000 1028.520000 2814.060000 ;
+ RECT 1027.420000 2819.020000 1028.520000 2819.500000 ;
+ RECT 1036.730000 2819.020000 1037.730000 2819.500000 ;
+ RECT 1036.730000 2813.580000 1037.730000 2814.060000 ;
+ RECT 1036.730000 2802.700000 1037.730000 2803.180000 ;
+ RECT 1036.730000 2808.140000 1037.730000 2808.620000 ;
+ RECT 1027.420000 2802.700000 1028.520000 2803.180000 ;
+ RECT 1027.420000 2808.140000 1028.520000 2808.620000 ;
+ RECT 982.420000 2846.220000 983.520000 2846.700000 ;
+ RECT 982.420000 2840.780000 983.520000 2841.260000 ;
+ RECT 982.420000 2835.340000 983.520000 2835.820000 ;
+ RECT 982.420000 2829.900000 983.520000 2830.380000 ;
+ RECT 982.420000 2824.460000 983.520000 2824.940000 ;
+ RECT 982.420000 2802.700000 983.520000 2803.180000 ;
+ RECT 982.420000 2808.140000 983.520000 2808.620000 ;
+ RECT 982.420000 2813.580000 983.520000 2814.060000 ;
+ RECT 982.420000 2819.020000 983.520000 2819.500000 ;
+ RECT 1027.420000 2797.260000 1028.520000 2797.740000 ;
+ RECT 1027.420000 2791.820000 1028.520000 2792.300000 ;
+ RECT 1036.730000 2797.260000 1037.730000 2797.740000 ;
+ RECT 1036.730000 2791.820000 1037.730000 2792.300000 ;
+ RECT 1027.420000 2780.940000 1028.520000 2781.420000 ;
+ RECT 1027.420000 2775.500000 1028.520000 2775.980000 ;
+ RECT 1036.730000 2780.940000 1037.730000 2781.420000 ;
+ RECT 1036.730000 2775.500000 1037.730000 2775.980000 ;
+ RECT 1027.420000 2786.380000 1028.520000 2786.860000 ;
+ RECT 1036.730000 2786.380000 1037.730000 2786.860000 ;
+ RECT 1036.730000 2764.620000 1037.730000 2765.100000 ;
+ RECT 1036.730000 2770.060000 1037.730000 2770.540000 ;
+ RECT 1027.420000 2770.060000 1028.520000 2770.540000 ;
+ RECT 1027.420000 2764.620000 1028.520000 2765.100000 ;
+ RECT 1027.420000 2759.180000 1028.520000 2759.660000 ;
+ RECT 1027.420000 2753.740000 1028.520000 2754.220000 ;
+ RECT 1036.730000 2759.180000 1037.730000 2759.660000 ;
+ RECT 1036.730000 2753.740000 1037.730000 2754.220000 ;
+ RECT 982.420000 2797.260000 983.520000 2797.740000 ;
+ RECT 982.420000 2791.820000 983.520000 2792.300000 ;
+ RECT 982.420000 2786.380000 983.520000 2786.860000 ;
+ RECT 982.420000 2780.940000 983.520000 2781.420000 ;
+ RECT 982.420000 2775.500000 983.520000 2775.980000 ;
+ RECT 982.420000 2770.060000 983.520000 2770.540000 ;
+ RECT 982.420000 2764.620000 983.520000 2765.100000 ;
+ RECT 982.420000 2759.180000 983.520000 2759.660000 ;
+ RECT 982.420000 2753.740000 983.520000 2754.220000 ;
+ RECT 937.420000 2846.220000 938.520000 2846.700000 ;
+ RECT 937.420000 2840.780000 938.520000 2841.260000 ;
+ RECT 937.420000 2835.340000 938.520000 2835.820000 ;
+ RECT 937.420000 2829.900000 938.520000 2830.380000 ;
+ RECT 937.420000 2824.460000 938.520000 2824.940000 ;
+ RECT 892.420000 2846.220000 893.520000 2846.700000 ;
+ RECT 892.420000 2840.780000 893.520000 2841.260000 ;
+ RECT 892.420000 2835.340000 893.520000 2835.820000 ;
+ RECT 892.420000 2829.900000 893.520000 2830.380000 ;
+ RECT 892.420000 2824.460000 893.520000 2824.940000 ;
+ RECT 937.420000 2819.020000 938.520000 2819.500000 ;
+ RECT 937.420000 2813.580000 938.520000 2814.060000 ;
+ RECT 937.420000 2808.140000 938.520000 2808.620000 ;
+ RECT 937.420000 2802.700000 938.520000 2803.180000 ;
+ RECT 892.420000 2813.580000 893.520000 2814.060000 ;
+ RECT 892.420000 2808.140000 893.520000 2808.620000 ;
+ RECT 892.420000 2802.700000 893.520000 2803.180000 ;
+ RECT 892.420000 2819.020000 893.520000 2819.500000 ;
+ RECT 847.420000 2846.220000 848.520000 2846.700000 ;
+ RECT 843.290000 2846.220000 844.290000 2846.700000 ;
+ RECT 847.420000 2840.780000 848.520000 2841.260000 ;
+ RECT 843.290000 2840.780000 844.290000 2841.260000 ;
+ RECT 847.420000 2835.340000 848.520000 2835.820000 ;
+ RECT 843.290000 2835.340000 844.290000 2835.820000 ;
+ RECT 847.420000 2824.460000 848.520000 2824.940000 ;
+ RECT 843.290000 2824.460000 844.290000 2824.940000 ;
+ RECT 843.290000 2829.900000 844.290000 2830.380000 ;
+ RECT 847.420000 2829.900000 848.520000 2830.380000 ;
+ RECT 847.420000 2819.020000 848.520000 2819.500000 ;
+ RECT 843.290000 2819.020000 844.290000 2819.500000 ;
+ RECT 847.420000 2813.580000 848.520000 2814.060000 ;
+ RECT 843.290000 2813.580000 844.290000 2814.060000 ;
+ RECT 847.420000 2808.140000 848.520000 2808.620000 ;
+ RECT 843.290000 2808.140000 844.290000 2808.620000 ;
+ RECT 847.420000 2802.700000 848.520000 2803.180000 ;
+ RECT 843.290000 2802.700000 844.290000 2803.180000 ;
+ RECT 937.420000 2797.260000 938.520000 2797.740000 ;
+ RECT 937.420000 2791.820000 938.520000 2792.300000 ;
+ RECT 937.420000 2786.380000 938.520000 2786.860000 ;
+ RECT 937.420000 2780.940000 938.520000 2781.420000 ;
+ RECT 937.420000 2775.500000 938.520000 2775.980000 ;
+ RECT 892.420000 2797.260000 893.520000 2797.740000 ;
+ RECT 892.420000 2791.820000 893.520000 2792.300000 ;
+ RECT 892.420000 2786.380000 893.520000 2786.860000 ;
+ RECT 892.420000 2780.940000 893.520000 2781.420000 ;
+ RECT 892.420000 2775.500000 893.520000 2775.980000 ;
+ RECT 937.420000 2753.740000 938.520000 2754.220000 ;
+ RECT 937.420000 2759.180000 938.520000 2759.660000 ;
+ RECT 937.420000 2764.620000 938.520000 2765.100000 ;
+ RECT 937.420000 2770.060000 938.520000 2770.540000 ;
+ RECT 892.420000 2753.740000 893.520000 2754.220000 ;
+ RECT 892.420000 2759.180000 893.520000 2759.660000 ;
+ RECT 892.420000 2764.620000 893.520000 2765.100000 ;
+ RECT 892.420000 2770.060000 893.520000 2770.540000 ;
+ RECT 847.420000 2797.260000 848.520000 2797.740000 ;
+ RECT 843.290000 2797.260000 844.290000 2797.740000 ;
+ RECT 847.420000 2791.820000 848.520000 2792.300000 ;
+ RECT 843.290000 2791.820000 844.290000 2792.300000 ;
+ RECT 847.420000 2780.940000 848.520000 2781.420000 ;
+ RECT 843.290000 2780.940000 844.290000 2781.420000 ;
+ RECT 847.420000 2775.500000 848.520000 2775.980000 ;
+ RECT 843.290000 2775.500000 844.290000 2775.980000 ;
+ RECT 847.420000 2786.380000 848.520000 2786.860000 ;
+ RECT 843.290000 2786.380000 844.290000 2786.860000 ;
+ RECT 847.420000 2770.060000 848.520000 2770.540000 ;
+ RECT 843.290000 2770.060000 844.290000 2770.540000 ;
+ RECT 847.420000 2764.620000 848.520000 2765.100000 ;
+ RECT 843.290000 2764.620000 844.290000 2765.100000 ;
+ RECT 847.420000 2759.180000 848.520000 2759.660000 ;
+ RECT 847.420000 2753.740000 848.520000 2754.220000 ;
+ RECT 843.290000 2759.180000 844.290000 2759.660000 ;
+ RECT 843.290000 2753.740000 844.290000 2754.220000 ;
+ RECT 840.460000 2944.100000 1040.560000 2945.100000 ;
+ RECT 840.460000 2751.730000 1040.560000 2752.730000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 2748.880000 844.290000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 2948.140000 844.290000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 2748.880000 1037.730000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 2948.140000 1037.730000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2751.730000 841.460000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2751.730000 1040.560000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2944.100000 841.460000 2945.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2944.100000 1040.560000 2945.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 2551.470000 1028.520000 2744.840000 ;
+ RECT 982.420000 2551.470000 983.520000 2744.840000 ;
+ RECT 1036.730000 2548.620000 1037.730000 2748.880000 ;
+ RECT 937.420000 2551.470000 938.520000 2744.840000 ;
+ RECT 892.420000 2551.470000 893.520000 2744.840000 ;
+ RECT 847.420000 2551.470000 848.520000 2744.840000 ;
+ RECT 843.290000 2548.620000 844.290000 2748.880000 ;
+ LAYER met3 ;
+ RECT 1027.420000 2738.440000 1028.520000 2738.920000 ;
+ RECT 1036.730000 2738.440000 1037.730000 2738.920000 ;
+ RECT 1036.730000 2727.560000 1037.730000 2728.040000 ;
+ RECT 1036.730000 2733.000000 1037.730000 2733.480000 ;
+ RECT 1027.420000 2733.000000 1028.520000 2733.480000 ;
+ RECT 1027.420000 2727.560000 1028.520000 2728.040000 ;
+ RECT 1027.420000 2722.120000 1028.520000 2722.600000 ;
+ RECT 1027.420000 2716.680000 1028.520000 2717.160000 ;
+ RECT 1036.730000 2722.120000 1037.730000 2722.600000 ;
+ RECT 1036.730000 2716.680000 1037.730000 2717.160000 ;
+ RECT 1027.420000 2700.360000 1028.520000 2700.840000 ;
+ RECT 1027.420000 2705.800000 1028.520000 2706.280000 ;
+ RECT 1036.730000 2705.800000 1037.730000 2706.280000 ;
+ RECT 1036.730000 2700.360000 1037.730000 2700.840000 ;
+ RECT 1027.420000 2711.240000 1028.520000 2711.720000 ;
+ RECT 1036.730000 2711.240000 1037.730000 2711.720000 ;
+ RECT 982.420000 2738.440000 983.520000 2738.920000 ;
+ RECT 982.420000 2733.000000 983.520000 2733.480000 ;
+ RECT 982.420000 2727.560000 983.520000 2728.040000 ;
+ RECT 982.420000 2722.120000 983.520000 2722.600000 ;
+ RECT 982.420000 2700.360000 983.520000 2700.840000 ;
+ RECT 982.420000 2705.800000 983.520000 2706.280000 ;
+ RECT 982.420000 2711.240000 983.520000 2711.720000 ;
+ RECT 982.420000 2716.680000 983.520000 2717.160000 ;
+ RECT 1036.730000 2689.480000 1037.730000 2689.960000 ;
+ RECT 1036.730000 2694.920000 1037.730000 2695.400000 ;
+ RECT 1027.420000 2694.920000 1028.520000 2695.400000 ;
+ RECT 1027.420000 2689.480000 1028.520000 2689.960000 ;
+ RECT 1027.420000 2684.040000 1028.520000 2684.520000 ;
+ RECT 1027.420000 2678.600000 1028.520000 2679.080000 ;
+ RECT 1036.730000 2684.040000 1037.730000 2684.520000 ;
+ RECT 1036.730000 2678.600000 1037.730000 2679.080000 ;
+ RECT 1036.730000 2662.280000 1037.730000 2662.760000 ;
+ RECT 1036.730000 2667.720000 1037.730000 2668.200000 ;
+ RECT 1036.730000 2673.160000 1037.730000 2673.640000 ;
+ RECT 1027.420000 2667.720000 1028.520000 2668.200000 ;
+ RECT 1027.420000 2662.280000 1028.520000 2662.760000 ;
+ RECT 1027.420000 2673.160000 1028.520000 2673.640000 ;
+ RECT 1027.420000 2656.840000 1028.520000 2657.320000 ;
+ RECT 1027.420000 2651.400000 1028.520000 2651.880000 ;
+ RECT 1036.730000 2656.840000 1037.730000 2657.320000 ;
+ RECT 1036.730000 2651.400000 1037.730000 2651.880000 ;
+ RECT 982.420000 2694.920000 983.520000 2695.400000 ;
+ RECT 982.420000 2689.480000 983.520000 2689.960000 ;
+ RECT 982.420000 2684.040000 983.520000 2684.520000 ;
+ RECT 982.420000 2678.600000 983.520000 2679.080000 ;
+ RECT 982.420000 2667.720000 983.520000 2668.200000 ;
+ RECT 982.420000 2662.280000 983.520000 2662.760000 ;
+ RECT 982.420000 2656.840000 983.520000 2657.320000 ;
+ RECT 982.420000 2651.400000 983.520000 2651.880000 ;
+ RECT 982.420000 2673.160000 983.520000 2673.640000 ;
+ RECT 937.420000 2738.440000 938.520000 2738.920000 ;
+ RECT 937.420000 2733.000000 938.520000 2733.480000 ;
+ RECT 937.420000 2727.560000 938.520000 2728.040000 ;
+ RECT 892.420000 2738.440000 893.520000 2738.920000 ;
+ RECT 892.420000 2733.000000 893.520000 2733.480000 ;
+ RECT 892.420000 2727.560000 893.520000 2728.040000 ;
+ RECT 937.420000 2711.240000 938.520000 2711.720000 ;
+ RECT 937.420000 2705.800000 938.520000 2706.280000 ;
+ RECT 937.420000 2700.360000 938.520000 2700.840000 ;
+ RECT 937.420000 2716.680000 938.520000 2717.160000 ;
+ RECT 937.420000 2722.120000 938.520000 2722.600000 ;
+ RECT 892.420000 2722.120000 893.520000 2722.600000 ;
+ RECT 892.420000 2711.240000 893.520000 2711.720000 ;
+ RECT 892.420000 2705.800000 893.520000 2706.280000 ;
+ RECT 892.420000 2700.360000 893.520000 2700.840000 ;
+ RECT 892.420000 2716.680000 893.520000 2717.160000 ;
+ RECT 847.420000 2738.440000 848.520000 2738.920000 ;
+ RECT 843.290000 2738.440000 844.290000 2738.920000 ;
+ RECT 843.290000 2733.000000 844.290000 2733.480000 ;
+ RECT 847.420000 2733.000000 848.520000 2733.480000 ;
+ RECT 847.420000 2727.560000 848.520000 2728.040000 ;
+ RECT 843.290000 2727.560000 844.290000 2728.040000 ;
+ RECT 847.420000 2722.120000 848.520000 2722.600000 ;
+ RECT 843.290000 2722.120000 844.290000 2722.600000 ;
+ RECT 847.420000 2716.680000 848.520000 2717.160000 ;
+ RECT 843.290000 2716.680000 844.290000 2717.160000 ;
+ RECT 847.420000 2705.800000 848.520000 2706.280000 ;
+ RECT 843.290000 2705.800000 844.290000 2706.280000 ;
+ RECT 847.420000 2700.360000 848.520000 2700.840000 ;
+ RECT 843.290000 2700.360000 844.290000 2700.840000 ;
+ RECT 847.420000 2711.240000 848.520000 2711.720000 ;
+ RECT 843.290000 2711.240000 844.290000 2711.720000 ;
+ RECT 937.420000 2694.920000 938.520000 2695.400000 ;
+ RECT 937.420000 2689.480000 938.520000 2689.960000 ;
+ RECT 937.420000 2684.040000 938.520000 2684.520000 ;
+ RECT 937.420000 2678.600000 938.520000 2679.080000 ;
+ RECT 892.420000 2694.920000 893.520000 2695.400000 ;
+ RECT 892.420000 2689.480000 893.520000 2689.960000 ;
+ RECT 892.420000 2684.040000 893.520000 2684.520000 ;
+ RECT 892.420000 2678.600000 893.520000 2679.080000 ;
+ RECT 937.420000 2667.720000 938.520000 2668.200000 ;
+ RECT 937.420000 2651.400000 938.520000 2651.880000 ;
+ RECT 937.420000 2656.840000 938.520000 2657.320000 ;
+ RECT 937.420000 2662.280000 938.520000 2662.760000 ;
+ RECT 937.420000 2673.160000 938.520000 2673.640000 ;
+ RECT 892.420000 2651.400000 893.520000 2651.880000 ;
+ RECT 892.420000 2656.840000 893.520000 2657.320000 ;
+ RECT 892.420000 2662.280000 893.520000 2662.760000 ;
+ RECT 892.420000 2667.720000 893.520000 2668.200000 ;
+ RECT 892.420000 2673.160000 893.520000 2673.640000 ;
+ RECT 847.420000 2694.920000 848.520000 2695.400000 ;
+ RECT 843.290000 2694.920000 844.290000 2695.400000 ;
+ RECT 847.420000 2689.480000 848.520000 2689.960000 ;
+ RECT 843.290000 2689.480000 844.290000 2689.960000 ;
+ RECT 847.420000 2684.040000 848.520000 2684.520000 ;
+ RECT 843.290000 2684.040000 844.290000 2684.520000 ;
+ RECT 847.420000 2678.600000 848.520000 2679.080000 ;
+ RECT 843.290000 2678.600000 844.290000 2679.080000 ;
+ RECT 847.420000 2673.160000 848.520000 2673.640000 ;
+ RECT 847.420000 2667.720000 848.520000 2668.200000 ;
+ RECT 843.290000 2673.160000 844.290000 2673.640000 ;
+ RECT 843.290000 2667.720000 844.290000 2668.200000 ;
+ RECT 847.420000 2662.280000 848.520000 2662.760000 ;
+ RECT 843.290000 2662.280000 844.290000 2662.760000 ;
+ RECT 847.420000 2656.840000 848.520000 2657.320000 ;
+ RECT 843.290000 2656.840000 844.290000 2657.320000 ;
+ RECT 847.420000 2651.400000 848.520000 2651.880000 ;
+ RECT 843.290000 2651.400000 844.290000 2651.880000 ;
+ RECT 1027.420000 2645.960000 1028.520000 2646.440000 ;
+ RECT 1027.420000 2640.520000 1028.520000 2641.000000 ;
+ RECT 1036.730000 2645.960000 1037.730000 2646.440000 ;
+ RECT 1036.730000 2640.520000 1037.730000 2641.000000 ;
+ RECT 1036.730000 2624.200000 1037.730000 2624.680000 ;
+ RECT 1036.730000 2629.640000 1037.730000 2630.120000 ;
+ RECT 1036.730000 2635.080000 1037.730000 2635.560000 ;
+ RECT 1027.420000 2635.080000 1028.520000 2635.560000 ;
+ RECT 1027.420000 2629.640000 1028.520000 2630.120000 ;
+ RECT 1027.420000 2624.200000 1028.520000 2624.680000 ;
+ RECT 1027.420000 2613.320000 1028.520000 2613.800000 ;
+ RECT 1027.420000 2618.760000 1028.520000 2619.240000 ;
+ RECT 1036.730000 2618.760000 1037.730000 2619.240000 ;
+ RECT 1036.730000 2613.320000 1037.730000 2613.800000 ;
+ RECT 1036.730000 2602.440000 1037.730000 2602.920000 ;
+ RECT 1036.730000 2607.880000 1037.730000 2608.360000 ;
+ RECT 1027.420000 2602.440000 1028.520000 2602.920000 ;
+ RECT 1027.420000 2607.880000 1028.520000 2608.360000 ;
+ RECT 982.420000 2645.960000 983.520000 2646.440000 ;
+ RECT 982.420000 2640.520000 983.520000 2641.000000 ;
+ RECT 982.420000 2635.080000 983.520000 2635.560000 ;
+ RECT 982.420000 2629.640000 983.520000 2630.120000 ;
+ RECT 982.420000 2624.200000 983.520000 2624.680000 ;
+ RECT 982.420000 2602.440000 983.520000 2602.920000 ;
+ RECT 982.420000 2607.880000 983.520000 2608.360000 ;
+ RECT 982.420000 2613.320000 983.520000 2613.800000 ;
+ RECT 982.420000 2618.760000 983.520000 2619.240000 ;
+ RECT 1027.420000 2597.000000 1028.520000 2597.480000 ;
+ RECT 1027.420000 2591.560000 1028.520000 2592.040000 ;
+ RECT 1036.730000 2597.000000 1037.730000 2597.480000 ;
+ RECT 1036.730000 2591.560000 1037.730000 2592.040000 ;
+ RECT 1027.420000 2580.680000 1028.520000 2581.160000 ;
+ RECT 1027.420000 2575.240000 1028.520000 2575.720000 ;
+ RECT 1036.730000 2580.680000 1037.730000 2581.160000 ;
+ RECT 1036.730000 2575.240000 1037.730000 2575.720000 ;
+ RECT 1027.420000 2586.120000 1028.520000 2586.600000 ;
+ RECT 1036.730000 2586.120000 1037.730000 2586.600000 ;
+ RECT 1036.730000 2564.360000 1037.730000 2564.840000 ;
+ RECT 1036.730000 2569.800000 1037.730000 2570.280000 ;
+ RECT 1027.420000 2569.800000 1028.520000 2570.280000 ;
+ RECT 1027.420000 2564.360000 1028.520000 2564.840000 ;
+ RECT 1027.420000 2558.920000 1028.520000 2559.400000 ;
+ RECT 1027.420000 2553.480000 1028.520000 2553.960000 ;
+ RECT 1036.730000 2558.920000 1037.730000 2559.400000 ;
+ RECT 1036.730000 2553.480000 1037.730000 2553.960000 ;
+ RECT 982.420000 2597.000000 983.520000 2597.480000 ;
+ RECT 982.420000 2591.560000 983.520000 2592.040000 ;
+ RECT 982.420000 2586.120000 983.520000 2586.600000 ;
+ RECT 982.420000 2580.680000 983.520000 2581.160000 ;
+ RECT 982.420000 2575.240000 983.520000 2575.720000 ;
+ RECT 982.420000 2569.800000 983.520000 2570.280000 ;
+ RECT 982.420000 2564.360000 983.520000 2564.840000 ;
+ RECT 982.420000 2558.920000 983.520000 2559.400000 ;
+ RECT 982.420000 2553.480000 983.520000 2553.960000 ;
+ RECT 937.420000 2645.960000 938.520000 2646.440000 ;
+ RECT 937.420000 2640.520000 938.520000 2641.000000 ;
+ RECT 937.420000 2635.080000 938.520000 2635.560000 ;
+ RECT 937.420000 2629.640000 938.520000 2630.120000 ;
+ RECT 937.420000 2624.200000 938.520000 2624.680000 ;
+ RECT 892.420000 2645.960000 893.520000 2646.440000 ;
+ RECT 892.420000 2640.520000 893.520000 2641.000000 ;
+ RECT 892.420000 2635.080000 893.520000 2635.560000 ;
+ RECT 892.420000 2629.640000 893.520000 2630.120000 ;
+ RECT 892.420000 2624.200000 893.520000 2624.680000 ;
+ RECT 937.420000 2618.760000 938.520000 2619.240000 ;
+ RECT 937.420000 2613.320000 938.520000 2613.800000 ;
+ RECT 937.420000 2607.880000 938.520000 2608.360000 ;
+ RECT 937.420000 2602.440000 938.520000 2602.920000 ;
+ RECT 892.420000 2613.320000 893.520000 2613.800000 ;
+ RECT 892.420000 2607.880000 893.520000 2608.360000 ;
+ RECT 892.420000 2602.440000 893.520000 2602.920000 ;
+ RECT 892.420000 2618.760000 893.520000 2619.240000 ;
+ RECT 847.420000 2645.960000 848.520000 2646.440000 ;
+ RECT 843.290000 2645.960000 844.290000 2646.440000 ;
+ RECT 847.420000 2640.520000 848.520000 2641.000000 ;
+ RECT 843.290000 2640.520000 844.290000 2641.000000 ;
+ RECT 847.420000 2635.080000 848.520000 2635.560000 ;
+ RECT 843.290000 2635.080000 844.290000 2635.560000 ;
+ RECT 847.420000 2624.200000 848.520000 2624.680000 ;
+ RECT 843.290000 2624.200000 844.290000 2624.680000 ;
+ RECT 843.290000 2629.640000 844.290000 2630.120000 ;
+ RECT 847.420000 2629.640000 848.520000 2630.120000 ;
+ RECT 847.420000 2618.760000 848.520000 2619.240000 ;
+ RECT 843.290000 2618.760000 844.290000 2619.240000 ;
+ RECT 847.420000 2613.320000 848.520000 2613.800000 ;
+ RECT 843.290000 2613.320000 844.290000 2613.800000 ;
+ RECT 847.420000 2607.880000 848.520000 2608.360000 ;
+ RECT 843.290000 2607.880000 844.290000 2608.360000 ;
+ RECT 847.420000 2602.440000 848.520000 2602.920000 ;
+ RECT 843.290000 2602.440000 844.290000 2602.920000 ;
+ RECT 937.420000 2597.000000 938.520000 2597.480000 ;
+ RECT 937.420000 2591.560000 938.520000 2592.040000 ;
+ RECT 937.420000 2586.120000 938.520000 2586.600000 ;
+ RECT 937.420000 2580.680000 938.520000 2581.160000 ;
+ RECT 937.420000 2575.240000 938.520000 2575.720000 ;
+ RECT 892.420000 2597.000000 893.520000 2597.480000 ;
+ RECT 892.420000 2591.560000 893.520000 2592.040000 ;
+ RECT 892.420000 2586.120000 893.520000 2586.600000 ;
+ RECT 892.420000 2580.680000 893.520000 2581.160000 ;
+ RECT 892.420000 2575.240000 893.520000 2575.720000 ;
+ RECT 937.420000 2553.480000 938.520000 2553.960000 ;
+ RECT 937.420000 2558.920000 938.520000 2559.400000 ;
+ RECT 937.420000 2564.360000 938.520000 2564.840000 ;
+ RECT 937.420000 2569.800000 938.520000 2570.280000 ;
+ RECT 892.420000 2553.480000 893.520000 2553.960000 ;
+ RECT 892.420000 2558.920000 893.520000 2559.400000 ;
+ RECT 892.420000 2564.360000 893.520000 2564.840000 ;
+ RECT 892.420000 2569.800000 893.520000 2570.280000 ;
+ RECT 847.420000 2597.000000 848.520000 2597.480000 ;
+ RECT 843.290000 2597.000000 844.290000 2597.480000 ;
+ RECT 847.420000 2591.560000 848.520000 2592.040000 ;
+ RECT 843.290000 2591.560000 844.290000 2592.040000 ;
+ RECT 847.420000 2580.680000 848.520000 2581.160000 ;
+ RECT 843.290000 2580.680000 844.290000 2581.160000 ;
+ RECT 847.420000 2575.240000 848.520000 2575.720000 ;
+ RECT 843.290000 2575.240000 844.290000 2575.720000 ;
+ RECT 847.420000 2586.120000 848.520000 2586.600000 ;
+ RECT 843.290000 2586.120000 844.290000 2586.600000 ;
+ RECT 847.420000 2569.800000 848.520000 2570.280000 ;
+ RECT 843.290000 2569.800000 844.290000 2570.280000 ;
+ RECT 847.420000 2564.360000 848.520000 2564.840000 ;
+ RECT 843.290000 2564.360000 844.290000 2564.840000 ;
+ RECT 847.420000 2558.920000 848.520000 2559.400000 ;
+ RECT 847.420000 2553.480000 848.520000 2553.960000 ;
+ RECT 843.290000 2558.920000 844.290000 2559.400000 ;
+ RECT 843.290000 2553.480000 844.290000 2553.960000 ;
+ RECT 840.460000 2743.840000 1040.560000 2744.840000 ;
+ RECT 840.460000 2551.470000 1040.560000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 2548.620000 844.290000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 2747.880000 844.290000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 2548.620000 1037.730000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 2747.880000 1037.730000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2551.470000 841.460000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2551.470000 1040.560000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2743.840000 841.460000 2744.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2743.840000 1040.560000 2744.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 2351.210000 1028.520000 2544.580000 ;
+ RECT 982.420000 2351.210000 983.520000 2544.580000 ;
+ RECT 1036.730000 2348.360000 1037.730000 2548.620000 ;
+ RECT 937.420000 2351.210000 938.520000 2544.580000 ;
+ RECT 892.420000 2351.210000 893.520000 2544.580000 ;
+ RECT 847.420000 2351.210000 848.520000 2544.580000 ;
+ RECT 843.290000 2348.360000 844.290000 2548.620000 ;
+ LAYER met3 ;
+ RECT 1027.420000 2538.180000 1028.520000 2538.660000 ;
+ RECT 1036.730000 2538.180000 1037.730000 2538.660000 ;
+ RECT 1036.730000 2527.300000 1037.730000 2527.780000 ;
+ RECT 1036.730000 2532.740000 1037.730000 2533.220000 ;
+ RECT 1027.420000 2532.740000 1028.520000 2533.220000 ;
+ RECT 1027.420000 2527.300000 1028.520000 2527.780000 ;
+ RECT 1027.420000 2521.860000 1028.520000 2522.340000 ;
+ RECT 1027.420000 2516.420000 1028.520000 2516.900000 ;
+ RECT 1036.730000 2521.860000 1037.730000 2522.340000 ;
+ RECT 1036.730000 2516.420000 1037.730000 2516.900000 ;
+ RECT 1027.420000 2500.100000 1028.520000 2500.580000 ;
+ RECT 1027.420000 2505.540000 1028.520000 2506.020000 ;
+ RECT 1036.730000 2505.540000 1037.730000 2506.020000 ;
+ RECT 1036.730000 2500.100000 1037.730000 2500.580000 ;
+ RECT 1027.420000 2510.980000 1028.520000 2511.460000 ;
+ RECT 1036.730000 2510.980000 1037.730000 2511.460000 ;
+ RECT 982.420000 2538.180000 983.520000 2538.660000 ;
+ RECT 982.420000 2532.740000 983.520000 2533.220000 ;
+ RECT 982.420000 2527.300000 983.520000 2527.780000 ;
+ RECT 982.420000 2521.860000 983.520000 2522.340000 ;
+ RECT 982.420000 2500.100000 983.520000 2500.580000 ;
+ RECT 982.420000 2505.540000 983.520000 2506.020000 ;
+ RECT 982.420000 2510.980000 983.520000 2511.460000 ;
+ RECT 982.420000 2516.420000 983.520000 2516.900000 ;
+ RECT 1036.730000 2489.220000 1037.730000 2489.700000 ;
+ RECT 1036.730000 2494.660000 1037.730000 2495.140000 ;
+ RECT 1027.420000 2494.660000 1028.520000 2495.140000 ;
+ RECT 1027.420000 2489.220000 1028.520000 2489.700000 ;
+ RECT 1027.420000 2483.780000 1028.520000 2484.260000 ;
+ RECT 1027.420000 2478.340000 1028.520000 2478.820000 ;
+ RECT 1036.730000 2483.780000 1037.730000 2484.260000 ;
+ RECT 1036.730000 2478.340000 1037.730000 2478.820000 ;
+ RECT 1036.730000 2462.020000 1037.730000 2462.500000 ;
+ RECT 1036.730000 2467.460000 1037.730000 2467.940000 ;
+ RECT 1036.730000 2472.900000 1037.730000 2473.380000 ;
+ RECT 1027.420000 2467.460000 1028.520000 2467.940000 ;
+ RECT 1027.420000 2462.020000 1028.520000 2462.500000 ;
+ RECT 1027.420000 2472.900000 1028.520000 2473.380000 ;
+ RECT 1027.420000 2456.580000 1028.520000 2457.060000 ;
+ RECT 1027.420000 2451.140000 1028.520000 2451.620000 ;
+ RECT 1036.730000 2456.580000 1037.730000 2457.060000 ;
+ RECT 1036.730000 2451.140000 1037.730000 2451.620000 ;
+ RECT 982.420000 2494.660000 983.520000 2495.140000 ;
+ RECT 982.420000 2489.220000 983.520000 2489.700000 ;
+ RECT 982.420000 2483.780000 983.520000 2484.260000 ;
+ RECT 982.420000 2478.340000 983.520000 2478.820000 ;
+ RECT 982.420000 2467.460000 983.520000 2467.940000 ;
+ RECT 982.420000 2462.020000 983.520000 2462.500000 ;
+ RECT 982.420000 2456.580000 983.520000 2457.060000 ;
+ RECT 982.420000 2451.140000 983.520000 2451.620000 ;
+ RECT 982.420000 2472.900000 983.520000 2473.380000 ;
+ RECT 937.420000 2538.180000 938.520000 2538.660000 ;
+ RECT 937.420000 2532.740000 938.520000 2533.220000 ;
+ RECT 937.420000 2527.300000 938.520000 2527.780000 ;
+ RECT 892.420000 2538.180000 893.520000 2538.660000 ;
+ RECT 892.420000 2532.740000 893.520000 2533.220000 ;
+ RECT 892.420000 2527.300000 893.520000 2527.780000 ;
+ RECT 937.420000 2510.980000 938.520000 2511.460000 ;
+ RECT 937.420000 2505.540000 938.520000 2506.020000 ;
+ RECT 937.420000 2500.100000 938.520000 2500.580000 ;
+ RECT 937.420000 2516.420000 938.520000 2516.900000 ;
+ RECT 937.420000 2521.860000 938.520000 2522.340000 ;
+ RECT 892.420000 2521.860000 893.520000 2522.340000 ;
+ RECT 892.420000 2510.980000 893.520000 2511.460000 ;
+ RECT 892.420000 2505.540000 893.520000 2506.020000 ;
+ RECT 892.420000 2500.100000 893.520000 2500.580000 ;
+ RECT 892.420000 2516.420000 893.520000 2516.900000 ;
+ RECT 847.420000 2538.180000 848.520000 2538.660000 ;
+ RECT 843.290000 2538.180000 844.290000 2538.660000 ;
+ RECT 843.290000 2532.740000 844.290000 2533.220000 ;
+ RECT 847.420000 2532.740000 848.520000 2533.220000 ;
+ RECT 847.420000 2527.300000 848.520000 2527.780000 ;
+ RECT 843.290000 2527.300000 844.290000 2527.780000 ;
+ RECT 847.420000 2521.860000 848.520000 2522.340000 ;
+ RECT 843.290000 2521.860000 844.290000 2522.340000 ;
+ RECT 847.420000 2516.420000 848.520000 2516.900000 ;
+ RECT 843.290000 2516.420000 844.290000 2516.900000 ;
+ RECT 847.420000 2505.540000 848.520000 2506.020000 ;
+ RECT 843.290000 2505.540000 844.290000 2506.020000 ;
+ RECT 847.420000 2500.100000 848.520000 2500.580000 ;
+ RECT 843.290000 2500.100000 844.290000 2500.580000 ;
+ RECT 847.420000 2510.980000 848.520000 2511.460000 ;
+ RECT 843.290000 2510.980000 844.290000 2511.460000 ;
+ RECT 937.420000 2494.660000 938.520000 2495.140000 ;
+ RECT 937.420000 2489.220000 938.520000 2489.700000 ;
+ RECT 937.420000 2483.780000 938.520000 2484.260000 ;
+ RECT 937.420000 2478.340000 938.520000 2478.820000 ;
+ RECT 892.420000 2494.660000 893.520000 2495.140000 ;
+ RECT 892.420000 2489.220000 893.520000 2489.700000 ;
+ RECT 892.420000 2483.780000 893.520000 2484.260000 ;
+ RECT 892.420000 2478.340000 893.520000 2478.820000 ;
+ RECT 937.420000 2467.460000 938.520000 2467.940000 ;
+ RECT 937.420000 2451.140000 938.520000 2451.620000 ;
+ RECT 937.420000 2456.580000 938.520000 2457.060000 ;
+ RECT 937.420000 2462.020000 938.520000 2462.500000 ;
+ RECT 937.420000 2472.900000 938.520000 2473.380000 ;
+ RECT 892.420000 2451.140000 893.520000 2451.620000 ;
+ RECT 892.420000 2456.580000 893.520000 2457.060000 ;
+ RECT 892.420000 2462.020000 893.520000 2462.500000 ;
+ RECT 892.420000 2467.460000 893.520000 2467.940000 ;
+ RECT 892.420000 2472.900000 893.520000 2473.380000 ;
+ RECT 847.420000 2494.660000 848.520000 2495.140000 ;
+ RECT 843.290000 2494.660000 844.290000 2495.140000 ;
+ RECT 847.420000 2489.220000 848.520000 2489.700000 ;
+ RECT 843.290000 2489.220000 844.290000 2489.700000 ;
+ RECT 847.420000 2483.780000 848.520000 2484.260000 ;
+ RECT 843.290000 2483.780000 844.290000 2484.260000 ;
+ RECT 847.420000 2478.340000 848.520000 2478.820000 ;
+ RECT 843.290000 2478.340000 844.290000 2478.820000 ;
+ RECT 847.420000 2472.900000 848.520000 2473.380000 ;
+ RECT 847.420000 2467.460000 848.520000 2467.940000 ;
+ RECT 843.290000 2472.900000 844.290000 2473.380000 ;
+ RECT 843.290000 2467.460000 844.290000 2467.940000 ;
+ RECT 847.420000 2462.020000 848.520000 2462.500000 ;
+ RECT 843.290000 2462.020000 844.290000 2462.500000 ;
+ RECT 847.420000 2456.580000 848.520000 2457.060000 ;
+ RECT 843.290000 2456.580000 844.290000 2457.060000 ;
+ RECT 847.420000 2451.140000 848.520000 2451.620000 ;
+ RECT 843.290000 2451.140000 844.290000 2451.620000 ;
+ RECT 1027.420000 2445.700000 1028.520000 2446.180000 ;
+ RECT 1027.420000 2440.260000 1028.520000 2440.740000 ;
+ RECT 1036.730000 2445.700000 1037.730000 2446.180000 ;
+ RECT 1036.730000 2440.260000 1037.730000 2440.740000 ;
+ RECT 1036.730000 2423.940000 1037.730000 2424.420000 ;
+ RECT 1036.730000 2429.380000 1037.730000 2429.860000 ;
+ RECT 1036.730000 2434.820000 1037.730000 2435.300000 ;
+ RECT 1027.420000 2434.820000 1028.520000 2435.300000 ;
+ RECT 1027.420000 2429.380000 1028.520000 2429.860000 ;
+ RECT 1027.420000 2423.940000 1028.520000 2424.420000 ;
+ RECT 1027.420000 2413.060000 1028.520000 2413.540000 ;
+ RECT 1027.420000 2418.500000 1028.520000 2418.980000 ;
+ RECT 1036.730000 2418.500000 1037.730000 2418.980000 ;
+ RECT 1036.730000 2413.060000 1037.730000 2413.540000 ;
+ RECT 1036.730000 2402.180000 1037.730000 2402.660000 ;
+ RECT 1036.730000 2407.620000 1037.730000 2408.100000 ;
+ RECT 1027.420000 2402.180000 1028.520000 2402.660000 ;
+ RECT 1027.420000 2407.620000 1028.520000 2408.100000 ;
+ RECT 982.420000 2445.700000 983.520000 2446.180000 ;
+ RECT 982.420000 2440.260000 983.520000 2440.740000 ;
+ RECT 982.420000 2434.820000 983.520000 2435.300000 ;
+ RECT 982.420000 2429.380000 983.520000 2429.860000 ;
+ RECT 982.420000 2423.940000 983.520000 2424.420000 ;
+ RECT 982.420000 2402.180000 983.520000 2402.660000 ;
+ RECT 982.420000 2407.620000 983.520000 2408.100000 ;
+ RECT 982.420000 2413.060000 983.520000 2413.540000 ;
+ RECT 982.420000 2418.500000 983.520000 2418.980000 ;
+ RECT 1027.420000 2396.740000 1028.520000 2397.220000 ;
+ RECT 1027.420000 2391.300000 1028.520000 2391.780000 ;
+ RECT 1036.730000 2396.740000 1037.730000 2397.220000 ;
+ RECT 1036.730000 2391.300000 1037.730000 2391.780000 ;
+ RECT 1027.420000 2380.420000 1028.520000 2380.900000 ;
+ RECT 1027.420000 2374.980000 1028.520000 2375.460000 ;
+ RECT 1036.730000 2380.420000 1037.730000 2380.900000 ;
+ RECT 1036.730000 2374.980000 1037.730000 2375.460000 ;
+ RECT 1027.420000 2385.860000 1028.520000 2386.340000 ;
+ RECT 1036.730000 2385.860000 1037.730000 2386.340000 ;
+ RECT 1036.730000 2364.100000 1037.730000 2364.580000 ;
+ RECT 1036.730000 2369.540000 1037.730000 2370.020000 ;
+ RECT 1027.420000 2369.540000 1028.520000 2370.020000 ;
+ RECT 1027.420000 2364.100000 1028.520000 2364.580000 ;
+ RECT 1027.420000 2358.660000 1028.520000 2359.140000 ;
+ RECT 1027.420000 2353.220000 1028.520000 2353.700000 ;
+ RECT 1036.730000 2358.660000 1037.730000 2359.140000 ;
+ RECT 1036.730000 2353.220000 1037.730000 2353.700000 ;
+ RECT 982.420000 2396.740000 983.520000 2397.220000 ;
+ RECT 982.420000 2391.300000 983.520000 2391.780000 ;
+ RECT 982.420000 2385.860000 983.520000 2386.340000 ;
+ RECT 982.420000 2380.420000 983.520000 2380.900000 ;
+ RECT 982.420000 2374.980000 983.520000 2375.460000 ;
+ RECT 982.420000 2369.540000 983.520000 2370.020000 ;
+ RECT 982.420000 2364.100000 983.520000 2364.580000 ;
+ RECT 982.420000 2358.660000 983.520000 2359.140000 ;
+ RECT 982.420000 2353.220000 983.520000 2353.700000 ;
+ RECT 937.420000 2445.700000 938.520000 2446.180000 ;
+ RECT 937.420000 2440.260000 938.520000 2440.740000 ;
+ RECT 937.420000 2434.820000 938.520000 2435.300000 ;
+ RECT 937.420000 2429.380000 938.520000 2429.860000 ;
+ RECT 937.420000 2423.940000 938.520000 2424.420000 ;
+ RECT 892.420000 2445.700000 893.520000 2446.180000 ;
+ RECT 892.420000 2440.260000 893.520000 2440.740000 ;
+ RECT 892.420000 2434.820000 893.520000 2435.300000 ;
+ RECT 892.420000 2429.380000 893.520000 2429.860000 ;
+ RECT 892.420000 2423.940000 893.520000 2424.420000 ;
+ RECT 937.420000 2418.500000 938.520000 2418.980000 ;
+ RECT 937.420000 2413.060000 938.520000 2413.540000 ;
+ RECT 937.420000 2407.620000 938.520000 2408.100000 ;
+ RECT 937.420000 2402.180000 938.520000 2402.660000 ;
+ RECT 892.420000 2413.060000 893.520000 2413.540000 ;
+ RECT 892.420000 2407.620000 893.520000 2408.100000 ;
+ RECT 892.420000 2402.180000 893.520000 2402.660000 ;
+ RECT 892.420000 2418.500000 893.520000 2418.980000 ;
+ RECT 847.420000 2445.700000 848.520000 2446.180000 ;
+ RECT 843.290000 2445.700000 844.290000 2446.180000 ;
+ RECT 847.420000 2440.260000 848.520000 2440.740000 ;
+ RECT 843.290000 2440.260000 844.290000 2440.740000 ;
+ RECT 847.420000 2434.820000 848.520000 2435.300000 ;
+ RECT 843.290000 2434.820000 844.290000 2435.300000 ;
+ RECT 847.420000 2423.940000 848.520000 2424.420000 ;
+ RECT 843.290000 2423.940000 844.290000 2424.420000 ;
+ RECT 843.290000 2429.380000 844.290000 2429.860000 ;
+ RECT 847.420000 2429.380000 848.520000 2429.860000 ;
+ RECT 847.420000 2418.500000 848.520000 2418.980000 ;
+ RECT 843.290000 2418.500000 844.290000 2418.980000 ;
+ RECT 847.420000 2413.060000 848.520000 2413.540000 ;
+ RECT 843.290000 2413.060000 844.290000 2413.540000 ;
+ RECT 847.420000 2407.620000 848.520000 2408.100000 ;
+ RECT 843.290000 2407.620000 844.290000 2408.100000 ;
+ RECT 847.420000 2402.180000 848.520000 2402.660000 ;
+ RECT 843.290000 2402.180000 844.290000 2402.660000 ;
+ RECT 937.420000 2396.740000 938.520000 2397.220000 ;
+ RECT 937.420000 2391.300000 938.520000 2391.780000 ;
+ RECT 937.420000 2385.860000 938.520000 2386.340000 ;
+ RECT 937.420000 2380.420000 938.520000 2380.900000 ;
+ RECT 937.420000 2374.980000 938.520000 2375.460000 ;
+ RECT 892.420000 2396.740000 893.520000 2397.220000 ;
+ RECT 892.420000 2391.300000 893.520000 2391.780000 ;
+ RECT 892.420000 2385.860000 893.520000 2386.340000 ;
+ RECT 892.420000 2380.420000 893.520000 2380.900000 ;
+ RECT 892.420000 2374.980000 893.520000 2375.460000 ;
+ RECT 937.420000 2353.220000 938.520000 2353.700000 ;
+ RECT 937.420000 2358.660000 938.520000 2359.140000 ;
+ RECT 937.420000 2364.100000 938.520000 2364.580000 ;
+ RECT 937.420000 2369.540000 938.520000 2370.020000 ;
+ RECT 892.420000 2353.220000 893.520000 2353.700000 ;
+ RECT 892.420000 2358.660000 893.520000 2359.140000 ;
+ RECT 892.420000 2364.100000 893.520000 2364.580000 ;
+ RECT 892.420000 2369.540000 893.520000 2370.020000 ;
+ RECT 847.420000 2396.740000 848.520000 2397.220000 ;
+ RECT 843.290000 2396.740000 844.290000 2397.220000 ;
+ RECT 847.420000 2391.300000 848.520000 2391.780000 ;
+ RECT 843.290000 2391.300000 844.290000 2391.780000 ;
+ RECT 847.420000 2380.420000 848.520000 2380.900000 ;
+ RECT 843.290000 2380.420000 844.290000 2380.900000 ;
+ RECT 847.420000 2374.980000 848.520000 2375.460000 ;
+ RECT 843.290000 2374.980000 844.290000 2375.460000 ;
+ RECT 847.420000 2385.860000 848.520000 2386.340000 ;
+ RECT 843.290000 2385.860000 844.290000 2386.340000 ;
+ RECT 847.420000 2369.540000 848.520000 2370.020000 ;
+ RECT 843.290000 2369.540000 844.290000 2370.020000 ;
+ RECT 847.420000 2364.100000 848.520000 2364.580000 ;
+ RECT 843.290000 2364.100000 844.290000 2364.580000 ;
+ RECT 847.420000 2358.660000 848.520000 2359.140000 ;
+ RECT 847.420000 2353.220000 848.520000 2353.700000 ;
+ RECT 843.290000 2358.660000 844.290000 2359.140000 ;
+ RECT 843.290000 2353.220000 844.290000 2353.700000 ;
+ RECT 840.460000 2543.580000 1040.560000 2544.580000 ;
+ RECT 840.460000 2351.210000 1040.560000 2352.210000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 2348.360000 844.290000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 2547.620000 844.290000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 2348.360000 1037.730000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 2547.620000 1037.730000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2351.210000 841.460000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2351.210000 1040.560000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2543.580000 841.460000 2544.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2543.580000 1040.560000 2544.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 2150.950000 1028.520000 2344.320000 ;
+ RECT 982.420000 2150.950000 983.520000 2344.320000 ;
+ RECT 1036.730000 2148.100000 1037.730000 2348.360000 ;
+ RECT 937.420000 2150.950000 938.520000 2344.320000 ;
+ RECT 892.420000 2150.950000 893.520000 2344.320000 ;
+ RECT 847.420000 2150.950000 848.520000 2344.320000 ;
+ RECT 843.290000 2148.100000 844.290000 2348.360000 ;
+ LAYER met3 ;
+ RECT 1027.420000 2337.920000 1028.520000 2338.400000 ;
+ RECT 1036.730000 2337.920000 1037.730000 2338.400000 ;
+ RECT 1036.730000 2327.040000 1037.730000 2327.520000 ;
+ RECT 1036.730000 2332.480000 1037.730000 2332.960000 ;
+ RECT 1027.420000 2332.480000 1028.520000 2332.960000 ;
+ RECT 1027.420000 2327.040000 1028.520000 2327.520000 ;
+ RECT 1027.420000 2321.600000 1028.520000 2322.080000 ;
+ RECT 1027.420000 2316.160000 1028.520000 2316.640000 ;
+ RECT 1036.730000 2321.600000 1037.730000 2322.080000 ;
+ RECT 1036.730000 2316.160000 1037.730000 2316.640000 ;
+ RECT 1027.420000 2299.840000 1028.520000 2300.320000 ;
+ RECT 1027.420000 2305.280000 1028.520000 2305.760000 ;
+ RECT 1036.730000 2305.280000 1037.730000 2305.760000 ;
+ RECT 1036.730000 2299.840000 1037.730000 2300.320000 ;
+ RECT 1027.420000 2310.720000 1028.520000 2311.200000 ;
+ RECT 1036.730000 2310.720000 1037.730000 2311.200000 ;
+ RECT 982.420000 2337.920000 983.520000 2338.400000 ;
+ RECT 982.420000 2332.480000 983.520000 2332.960000 ;
+ RECT 982.420000 2327.040000 983.520000 2327.520000 ;
+ RECT 982.420000 2321.600000 983.520000 2322.080000 ;
+ RECT 982.420000 2299.840000 983.520000 2300.320000 ;
+ RECT 982.420000 2305.280000 983.520000 2305.760000 ;
+ RECT 982.420000 2310.720000 983.520000 2311.200000 ;
+ RECT 982.420000 2316.160000 983.520000 2316.640000 ;
+ RECT 1036.730000 2288.960000 1037.730000 2289.440000 ;
+ RECT 1036.730000 2294.400000 1037.730000 2294.880000 ;
+ RECT 1027.420000 2294.400000 1028.520000 2294.880000 ;
+ RECT 1027.420000 2288.960000 1028.520000 2289.440000 ;
+ RECT 1027.420000 2283.520000 1028.520000 2284.000000 ;
+ RECT 1027.420000 2278.080000 1028.520000 2278.560000 ;
+ RECT 1036.730000 2283.520000 1037.730000 2284.000000 ;
+ RECT 1036.730000 2278.080000 1037.730000 2278.560000 ;
+ RECT 1036.730000 2261.760000 1037.730000 2262.240000 ;
+ RECT 1036.730000 2267.200000 1037.730000 2267.680000 ;
+ RECT 1036.730000 2272.640000 1037.730000 2273.120000 ;
+ RECT 1027.420000 2267.200000 1028.520000 2267.680000 ;
+ RECT 1027.420000 2261.760000 1028.520000 2262.240000 ;
+ RECT 1027.420000 2272.640000 1028.520000 2273.120000 ;
+ RECT 1027.420000 2256.320000 1028.520000 2256.800000 ;
+ RECT 1027.420000 2250.880000 1028.520000 2251.360000 ;
+ RECT 1036.730000 2256.320000 1037.730000 2256.800000 ;
+ RECT 1036.730000 2250.880000 1037.730000 2251.360000 ;
+ RECT 982.420000 2294.400000 983.520000 2294.880000 ;
+ RECT 982.420000 2288.960000 983.520000 2289.440000 ;
+ RECT 982.420000 2283.520000 983.520000 2284.000000 ;
+ RECT 982.420000 2278.080000 983.520000 2278.560000 ;
+ RECT 982.420000 2267.200000 983.520000 2267.680000 ;
+ RECT 982.420000 2261.760000 983.520000 2262.240000 ;
+ RECT 982.420000 2256.320000 983.520000 2256.800000 ;
+ RECT 982.420000 2250.880000 983.520000 2251.360000 ;
+ RECT 982.420000 2272.640000 983.520000 2273.120000 ;
+ RECT 937.420000 2337.920000 938.520000 2338.400000 ;
+ RECT 937.420000 2332.480000 938.520000 2332.960000 ;
+ RECT 937.420000 2327.040000 938.520000 2327.520000 ;
+ RECT 892.420000 2337.920000 893.520000 2338.400000 ;
+ RECT 892.420000 2332.480000 893.520000 2332.960000 ;
+ RECT 892.420000 2327.040000 893.520000 2327.520000 ;
+ RECT 937.420000 2310.720000 938.520000 2311.200000 ;
+ RECT 937.420000 2305.280000 938.520000 2305.760000 ;
+ RECT 937.420000 2299.840000 938.520000 2300.320000 ;
+ RECT 937.420000 2316.160000 938.520000 2316.640000 ;
+ RECT 937.420000 2321.600000 938.520000 2322.080000 ;
+ RECT 892.420000 2321.600000 893.520000 2322.080000 ;
+ RECT 892.420000 2310.720000 893.520000 2311.200000 ;
+ RECT 892.420000 2305.280000 893.520000 2305.760000 ;
+ RECT 892.420000 2299.840000 893.520000 2300.320000 ;
+ RECT 892.420000 2316.160000 893.520000 2316.640000 ;
+ RECT 847.420000 2337.920000 848.520000 2338.400000 ;
+ RECT 843.290000 2337.920000 844.290000 2338.400000 ;
+ RECT 843.290000 2332.480000 844.290000 2332.960000 ;
+ RECT 847.420000 2332.480000 848.520000 2332.960000 ;
+ RECT 847.420000 2327.040000 848.520000 2327.520000 ;
+ RECT 843.290000 2327.040000 844.290000 2327.520000 ;
+ RECT 847.420000 2321.600000 848.520000 2322.080000 ;
+ RECT 843.290000 2321.600000 844.290000 2322.080000 ;
+ RECT 847.420000 2316.160000 848.520000 2316.640000 ;
+ RECT 843.290000 2316.160000 844.290000 2316.640000 ;
+ RECT 847.420000 2305.280000 848.520000 2305.760000 ;
+ RECT 843.290000 2305.280000 844.290000 2305.760000 ;
+ RECT 847.420000 2299.840000 848.520000 2300.320000 ;
+ RECT 843.290000 2299.840000 844.290000 2300.320000 ;
+ RECT 847.420000 2310.720000 848.520000 2311.200000 ;
+ RECT 843.290000 2310.720000 844.290000 2311.200000 ;
+ RECT 937.420000 2294.400000 938.520000 2294.880000 ;
+ RECT 937.420000 2288.960000 938.520000 2289.440000 ;
+ RECT 937.420000 2283.520000 938.520000 2284.000000 ;
+ RECT 937.420000 2278.080000 938.520000 2278.560000 ;
+ RECT 892.420000 2294.400000 893.520000 2294.880000 ;
+ RECT 892.420000 2288.960000 893.520000 2289.440000 ;
+ RECT 892.420000 2283.520000 893.520000 2284.000000 ;
+ RECT 892.420000 2278.080000 893.520000 2278.560000 ;
+ RECT 937.420000 2267.200000 938.520000 2267.680000 ;
+ RECT 937.420000 2250.880000 938.520000 2251.360000 ;
+ RECT 937.420000 2256.320000 938.520000 2256.800000 ;
+ RECT 937.420000 2261.760000 938.520000 2262.240000 ;
+ RECT 937.420000 2272.640000 938.520000 2273.120000 ;
+ RECT 892.420000 2250.880000 893.520000 2251.360000 ;
+ RECT 892.420000 2256.320000 893.520000 2256.800000 ;
+ RECT 892.420000 2261.760000 893.520000 2262.240000 ;
+ RECT 892.420000 2267.200000 893.520000 2267.680000 ;
+ RECT 892.420000 2272.640000 893.520000 2273.120000 ;
+ RECT 847.420000 2294.400000 848.520000 2294.880000 ;
+ RECT 843.290000 2294.400000 844.290000 2294.880000 ;
+ RECT 847.420000 2288.960000 848.520000 2289.440000 ;
+ RECT 843.290000 2288.960000 844.290000 2289.440000 ;
+ RECT 847.420000 2283.520000 848.520000 2284.000000 ;
+ RECT 843.290000 2283.520000 844.290000 2284.000000 ;
+ RECT 847.420000 2278.080000 848.520000 2278.560000 ;
+ RECT 843.290000 2278.080000 844.290000 2278.560000 ;
+ RECT 847.420000 2272.640000 848.520000 2273.120000 ;
+ RECT 847.420000 2267.200000 848.520000 2267.680000 ;
+ RECT 843.290000 2272.640000 844.290000 2273.120000 ;
+ RECT 843.290000 2267.200000 844.290000 2267.680000 ;
+ RECT 847.420000 2261.760000 848.520000 2262.240000 ;
+ RECT 843.290000 2261.760000 844.290000 2262.240000 ;
+ RECT 847.420000 2256.320000 848.520000 2256.800000 ;
+ RECT 843.290000 2256.320000 844.290000 2256.800000 ;
+ RECT 847.420000 2250.880000 848.520000 2251.360000 ;
+ RECT 843.290000 2250.880000 844.290000 2251.360000 ;
+ RECT 1027.420000 2245.440000 1028.520000 2245.920000 ;
+ RECT 1027.420000 2240.000000 1028.520000 2240.480000 ;
+ RECT 1036.730000 2245.440000 1037.730000 2245.920000 ;
+ RECT 1036.730000 2240.000000 1037.730000 2240.480000 ;
+ RECT 1036.730000 2223.680000 1037.730000 2224.160000 ;
+ RECT 1036.730000 2229.120000 1037.730000 2229.600000 ;
+ RECT 1036.730000 2234.560000 1037.730000 2235.040000 ;
+ RECT 1027.420000 2234.560000 1028.520000 2235.040000 ;
+ RECT 1027.420000 2229.120000 1028.520000 2229.600000 ;
+ RECT 1027.420000 2223.680000 1028.520000 2224.160000 ;
+ RECT 1027.420000 2212.800000 1028.520000 2213.280000 ;
+ RECT 1027.420000 2218.240000 1028.520000 2218.720000 ;
+ RECT 1036.730000 2218.240000 1037.730000 2218.720000 ;
+ RECT 1036.730000 2212.800000 1037.730000 2213.280000 ;
+ RECT 1036.730000 2201.920000 1037.730000 2202.400000 ;
+ RECT 1036.730000 2207.360000 1037.730000 2207.840000 ;
+ RECT 1027.420000 2201.920000 1028.520000 2202.400000 ;
+ RECT 1027.420000 2207.360000 1028.520000 2207.840000 ;
+ RECT 982.420000 2245.440000 983.520000 2245.920000 ;
+ RECT 982.420000 2240.000000 983.520000 2240.480000 ;
+ RECT 982.420000 2234.560000 983.520000 2235.040000 ;
+ RECT 982.420000 2229.120000 983.520000 2229.600000 ;
+ RECT 982.420000 2223.680000 983.520000 2224.160000 ;
+ RECT 982.420000 2201.920000 983.520000 2202.400000 ;
+ RECT 982.420000 2207.360000 983.520000 2207.840000 ;
+ RECT 982.420000 2212.800000 983.520000 2213.280000 ;
+ RECT 982.420000 2218.240000 983.520000 2218.720000 ;
+ RECT 1027.420000 2196.480000 1028.520000 2196.960000 ;
+ RECT 1027.420000 2191.040000 1028.520000 2191.520000 ;
+ RECT 1036.730000 2196.480000 1037.730000 2196.960000 ;
+ RECT 1036.730000 2191.040000 1037.730000 2191.520000 ;
+ RECT 1027.420000 2180.160000 1028.520000 2180.640000 ;
+ RECT 1027.420000 2174.720000 1028.520000 2175.200000 ;
+ RECT 1036.730000 2180.160000 1037.730000 2180.640000 ;
+ RECT 1036.730000 2174.720000 1037.730000 2175.200000 ;
+ RECT 1027.420000 2185.600000 1028.520000 2186.080000 ;
+ RECT 1036.730000 2185.600000 1037.730000 2186.080000 ;
+ RECT 1036.730000 2163.840000 1037.730000 2164.320000 ;
+ RECT 1036.730000 2169.280000 1037.730000 2169.760000 ;
+ RECT 1027.420000 2169.280000 1028.520000 2169.760000 ;
+ RECT 1027.420000 2163.840000 1028.520000 2164.320000 ;
+ RECT 1027.420000 2158.400000 1028.520000 2158.880000 ;
+ RECT 1027.420000 2152.960000 1028.520000 2153.440000 ;
+ RECT 1036.730000 2158.400000 1037.730000 2158.880000 ;
+ RECT 1036.730000 2152.960000 1037.730000 2153.440000 ;
+ RECT 982.420000 2196.480000 983.520000 2196.960000 ;
+ RECT 982.420000 2191.040000 983.520000 2191.520000 ;
+ RECT 982.420000 2185.600000 983.520000 2186.080000 ;
+ RECT 982.420000 2180.160000 983.520000 2180.640000 ;
+ RECT 982.420000 2174.720000 983.520000 2175.200000 ;
+ RECT 982.420000 2169.280000 983.520000 2169.760000 ;
+ RECT 982.420000 2163.840000 983.520000 2164.320000 ;
+ RECT 982.420000 2158.400000 983.520000 2158.880000 ;
+ RECT 982.420000 2152.960000 983.520000 2153.440000 ;
+ RECT 937.420000 2245.440000 938.520000 2245.920000 ;
+ RECT 937.420000 2240.000000 938.520000 2240.480000 ;
+ RECT 937.420000 2234.560000 938.520000 2235.040000 ;
+ RECT 937.420000 2229.120000 938.520000 2229.600000 ;
+ RECT 937.420000 2223.680000 938.520000 2224.160000 ;
+ RECT 892.420000 2245.440000 893.520000 2245.920000 ;
+ RECT 892.420000 2240.000000 893.520000 2240.480000 ;
+ RECT 892.420000 2234.560000 893.520000 2235.040000 ;
+ RECT 892.420000 2229.120000 893.520000 2229.600000 ;
+ RECT 892.420000 2223.680000 893.520000 2224.160000 ;
+ RECT 937.420000 2218.240000 938.520000 2218.720000 ;
+ RECT 937.420000 2212.800000 938.520000 2213.280000 ;
+ RECT 937.420000 2207.360000 938.520000 2207.840000 ;
+ RECT 937.420000 2201.920000 938.520000 2202.400000 ;
+ RECT 892.420000 2212.800000 893.520000 2213.280000 ;
+ RECT 892.420000 2207.360000 893.520000 2207.840000 ;
+ RECT 892.420000 2201.920000 893.520000 2202.400000 ;
+ RECT 892.420000 2218.240000 893.520000 2218.720000 ;
+ RECT 847.420000 2245.440000 848.520000 2245.920000 ;
+ RECT 843.290000 2245.440000 844.290000 2245.920000 ;
+ RECT 847.420000 2240.000000 848.520000 2240.480000 ;
+ RECT 843.290000 2240.000000 844.290000 2240.480000 ;
+ RECT 847.420000 2234.560000 848.520000 2235.040000 ;
+ RECT 843.290000 2234.560000 844.290000 2235.040000 ;
+ RECT 847.420000 2223.680000 848.520000 2224.160000 ;
+ RECT 843.290000 2223.680000 844.290000 2224.160000 ;
+ RECT 843.290000 2229.120000 844.290000 2229.600000 ;
+ RECT 847.420000 2229.120000 848.520000 2229.600000 ;
+ RECT 847.420000 2218.240000 848.520000 2218.720000 ;
+ RECT 843.290000 2218.240000 844.290000 2218.720000 ;
+ RECT 847.420000 2212.800000 848.520000 2213.280000 ;
+ RECT 843.290000 2212.800000 844.290000 2213.280000 ;
+ RECT 847.420000 2207.360000 848.520000 2207.840000 ;
+ RECT 843.290000 2207.360000 844.290000 2207.840000 ;
+ RECT 847.420000 2201.920000 848.520000 2202.400000 ;
+ RECT 843.290000 2201.920000 844.290000 2202.400000 ;
+ RECT 937.420000 2196.480000 938.520000 2196.960000 ;
+ RECT 937.420000 2191.040000 938.520000 2191.520000 ;
+ RECT 937.420000 2185.600000 938.520000 2186.080000 ;
+ RECT 937.420000 2180.160000 938.520000 2180.640000 ;
+ RECT 937.420000 2174.720000 938.520000 2175.200000 ;
+ RECT 892.420000 2196.480000 893.520000 2196.960000 ;
+ RECT 892.420000 2191.040000 893.520000 2191.520000 ;
+ RECT 892.420000 2185.600000 893.520000 2186.080000 ;
+ RECT 892.420000 2180.160000 893.520000 2180.640000 ;
+ RECT 892.420000 2174.720000 893.520000 2175.200000 ;
+ RECT 937.420000 2152.960000 938.520000 2153.440000 ;
+ RECT 937.420000 2158.400000 938.520000 2158.880000 ;
+ RECT 937.420000 2163.840000 938.520000 2164.320000 ;
+ RECT 937.420000 2169.280000 938.520000 2169.760000 ;
+ RECT 892.420000 2152.960000 893.520000 2153.440000 ;
+ RECT 892.420000 2158.400000 893.520000 2158.880000 ;
+ RECT 892.420000 2163.840000 893.520000 2164.320000 ;
+ RECT 892.420000 2169.280000 893.520000 2169.760000 ;
+ RECT 847.420000 2196.480000 848.520000 2196.960000 ;
+ RECT 843.290000 2196.480000 844.290000 2196.960000 ;
+ RECT 847.420000 2191.040000 848.520000 2191.520000 ;
+ RECT 843.290000 2191.040000 844.290000 2191.520000 ;
+ RECT 847.420000 2180.160000 848.520000 2180.640000 ;
+ RECT 843.290000 2180.160000 844.290000 2180.640000 ;
+ RECT 847.420000 2174.720000 848.520000 2175.200000 ;
+ RECT 843.290000 2174.720000 844.290000 2175.200000 ;
+ RECT 847.420000 2185.600000 848.520000 2186.080000 ;
+ RECT 843.290000 2185.600000 844.290000 2186.080000 ;
+ RECT 847.420000 2169.280000 848.520000 2169.760000 ;
+ RECT 843.290000 2169.280000 844.290000 2169.760000 ;
+ RECT 847.420000 2163.840000 848.520000 2164.320000 ;
+ RECT 843.290000 2163.840000 844.290000 2164.320000 ;
+ RECT 847.420000 2158.400000 848.520000 2158.880000 ;
+ RECT 847.420000 2152.960000 848.520000 2153.440000 ;
+ RECT 843.290000 2158.400000 844.290000 2158.880000 ;
+ RECT 843.290000 2152.960000 844.290000 2153.440000 ;
+ RECT 840.460000 2343.320000 1040.560000 2344.320000 ;
+ RECT 840.460000 2150.950000 1040.560000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 2148.100000 844.290000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 2347.360000 844.290000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 2148.100000 1037.730000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 2347.360000 1037.730000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2150.950000 841.460000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2150.950000 1040.560000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2343.320000 841.460000 2344.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2343.320000 1040.560000 2344.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 1950.690000 1028.520000 2144.060000 ;
+ RECT 982.420000 1950.690000 983.520000 2144.060000 ;
+ RECT 1036.730000 1947.840000 1037.730000 2148.100000 ;
+ RECT 937.420000 1950.690000 938.520000 2144.060000 ;
+ RECT 892.420000 1950.690000 893.520000 2144.060000 ;
+ RECT 847.420000 1950.690000 848.520000 2144.060000 ;
+ RECT 843.290000 1947.840000 844.290000 2148.100000 ;
+ LAYER met3 ;
+ RECT 1027.420000 2137.660000 1028.520000 2138.140000 ;
+ RECT 1036.730000 2137.660000 1037.730000 2138.140000 ;
+ RECT 1036.730000 2126.780000 1037.730000 2127.260000 ;
+ RECT 1036.730000 2132.220000 1037.730000 2132.700000 ;
+ RECT 1027.420000 2132.220000 1028.520000 2132.700000 ;
+ RECT 1027.420000 2126.780000 1028.520000 2127.260000 ;
+ RECT 1027.420000 2121.340000 1028.520000 2121.820000 ;
+ RECT 1027.420000 2115.900000 1028.520000 2116.380000 ;
+ RECT 1036.730000 2121.340000 1037.730000 2121.820000 ;
+ RECT 1036.730000 2115.900000 1037.730000 2116.380000 ;
+ RECT 1027.420000 2099.580000 1028.520000 2100.060000 ;
+ RECT 1027.420000 2105.020000 1028.520000 2105.500000 ;
+ RECT 1036.730000 2105.020000 1037.730000 2105.500000 ;
+ RECT 1036.730000 2099.580000 1037.730000 2100.060000 ;
+ RECT 1027.420000 2110.460000 1028.520000 2110.940000 ;
+ RECT 1036.730000 2110.460000 1037.730000 2110.940000 ;
+ RECT 982.420000 2137.660000 983.520000 2138.140000 ;
+ RECT 982.420000 2132.220000 983.520000 2132.700000 ;
+ RECT 982.420000 2126.780000 983.520000 2127.260000 ;
+ RECT 982.420000 2121.340000 983.520000 2121.820000 ;
+ RECT 982.420000 2099.580000 983.520000 2100.060000 ;
+ RECT 982.420000 2105.020000 983.520000 2105.500000 ;
+ RECT 982.420000 2110.460000 983.520000 2110.940000 ;
+ RECT 982.420000 2115.900000 983.520000 2116.380000 ;
+ RECT 1036.730000 2088.700000 1037.730000 2089.180000 ;
+ RECT 1036.730000 2094.140000 1037.730000 2094.620000 ;
+ RECT 1027.420000 2094.140000 1028.520000 2094.620000 ;
+ RECT 1027.420000 2088.700000 1028.520000 2089.180000 ;
+ RECT 1027.420000 2083.260000 1028.520000 2083.740000 ;
+ RECT 1027.420000 2077.820000 1028.520000 2078.300000 ;
+ RECT 1036.730000 2083.260000 1037.730000 2083.740000 ;
+ RECT 1036.730000 2077.820000 1037.730000 2078.300000 ;
+ RECT 1036.730000 2061.500000 1037.730000 2061.980000 ;
+ RECT 1036.730000 2066.940000 1037.730000 2067.420000 ;
+ RECT 1036.730000 2072.380000 1037.730000 2072.860000 ;
+ RECT 1027.420000 2066.940000 1028.520000 2067.420000 ;
+ RECT 1027.420000 2061.500000 1028.520000 2061.980000 ;
+ RECT 1027.420000 2072.380000 1028.520000 2072.860000 ;
+ RECT 1027.420000 2056.060000 1028.520000 2056.540000 ;
+ RECT 1027.420000 2050.620000 1028.520000 2051.100000 ;
+ RECT 1036.730000 2056.060000 1037.730000 2056.540000 ;
+ RECT 1036.730000 2050.620000 1037.730000 2051.100000 ;
+ RECT 982.420000 2094.140000 983.520000 2094.620000 ;
+ RECT 982.420000 2088.700000 983.520000 2089.180000 ;
+ RECT 982.420000 2083.260000 983.520000 2083.740000 ;
+ RECT 982.420000 2077.820000 983.520000 2078.300000 ;
+ RECT 982.420000 2066.940000 983.520000 2067.420000 ;
+ RECT 982.420000 2061.500000 983.520000 2061.980000 ;
+ RECT 982.420000 2056.060000 983.520000 2056.540000 ;
+ RECT 982.420000 2050.620000 983.520000 2051.100000 ;
+ RECT 982.420000 2072.380000 983.520000 2072.860000 ;
+ RECT 937.420000 2137.660000 938.520000 2138.140000 ;
+ RECT 937.420000 2132.220000 938.520000 2132.700000 ;
+ RECT 937.420000 2126.780000 938.520000 2127.260000 ;
+ RECT 892.420000 2137.660000 893.520000 2138.140000 ;
+ RECT 892.420000 2132.220000 893.520000 2132.700000 ;
+ RECT 892.420000 2126.780000 893.520000 2127.260000 ;
+ RECT 937.420000 2110.460000 938.520000 2110.940000 ;
+ RECT 937.420000 2105.020000 938.520000 2105.500000 ;
+ RECT 937.420000 2099.580000 938.520000 2100.060000 ;
+ RECT 937.420000 2115.900000 938.520000 2116.380000 ;
+ RECT 937.420000 2121.340000 938.520000 2121.820000 ;
+ RECT 892.420000 2121.340000 893.520000 2121.820000 ;
+ RECT 892.420000 2110.460000 893.520000 2110.940000 ;
+ RECT 892.420000 2105.020000 893.520000 2105.500000 ;
+ RECT 892.420000 2099.580000 893.520000 2100.060000 ;
+ RECT 892.420000 2115.900000 893.520000 2116.380000 ;
+ RECT 847.420000 2137.660000 848.520000 2138.140000 ;
+ RECT 843.290000 2137.660000 844.290000 2138.140000 ;
+ RECT 843.290000 2132.220000 844.290000 2132.700000 ;
+ RECT 847.420000 2132.220000 848.520000 2132.700000 ;
+ RECT 847.420000 2126.780000 848.520000 2127.260000 ;
+ RECT 843.290000 2126.780000 844.290000 2127.260000 ;
+ RECT 847.420000 2121.340000 848.520000 2121.820000 ;
+ RECT 843.290000 2121.340000 844.290000 2121.820000 ;
+ RECT 847.420000 2115.900000 848.520000 2116.380000 ;
+ RECT 843.290000 2115.900000 844.290000 2116.380000 ;
+ RECT 847.420000 2105.020000 848.520000 2105.500000 ;
+ RECT 843.290000 2105.020000 844.290000 2105.500000 ;
+ RECT 847.420000 2099.580000 848.520000 2100.060000 ;
+ RECT 843.290000 2099.580000 844.290000 2100.060000 ;
+ RECT 847.420000 2110.460000 848.520000 2110.940000 ;
+ RECT 843.290000 2110.460000 844.290000 2110.940000 ;
+ RECT 937.420000 2094.140000 938.520000 2094.620000 ;
+ RECT 937.420000 2088.700000 938.520000 2089.180000 ;
+ RECT 937.420000 2083.260000 938.520000 2083.740000 ;
+ RECT 937.420000 2077.820000 938.520000 2078.300000 ;
+ RECT 892.420000 2094.140000 893.520000 2094.620000 ;
+ RECT 892.420000 2088.700000 893.520000 2089.180000 ;
+ RECT 892.420000 2083.260000 893.520000 2083.740000 ;
+ RECT 892.420000 2077.820000 893.520000 2078.300000 ;
+ RECT 937.420000 2066.940000 938.520000 2067.420000 ;
+ RECT 937.420000 2050.620000 938.520000 2051.100000 ;
+ RECT 937.420000 2056.060000 938.520000 2056.540000 ;
+ RECT 937.420000 2061.500000 938.520000 2061.980000 ;
+ RECT 937.420000 2072.380000 938.520000 2072.860000 ;
+ RECT 892.420000 2050.620000 893.520000 2051.100000 ;
+ RECT 892.420000 2056.060000 893.520000 2056.540000 ;
+ RECT 892.420000 2061.500000 893.520000 2061.980000 ;
+ RECT 892.420000 2066.940000 893.520000 2067.420000 ;
+ RECT 892.420000 2072.380000 893.520000 2072.860000 ;
+ RECT 847.420000 2094.140000 848.520000 2094.620000 ;
+ RECT 843.290000 2094.140000 844.290000 2094.620000 ;
+ RECT 847.420000 2088.700000 848.520000 2089.180000 ;
+ RECT 843.290000 2088.700000 844.290000 2089.180000 ;
+ RECT 847.420000 2083.260000 848.520000 2083.740000 ;
+ RECT 843.290000 2083.260000 844.290000 2083.740000 ;
+ RECT 847.420000 2077.820000 848.520000 2078.300000 ;
+ RECT 843.290000 2077.820000 844.290000 2078.300000 ;
+ RECT 847.420000 2072.380000 848.520000 2072.860000 ;
+ RECT 847.420000 2066.940000 848.520000 2067.420000 ;
+ RECT 843.290000 2072.380000 844.290000 2072.860000 ;
+ RECT 843.290000 2066.940000 844.290000 2067.420000 ;
+ RECT 847.420000 2061.500000 848.520000 2061.980000 ;
+ RECT 843.290000 2061.500000 844.290000 2061.980000 ;
+ RECT 847.420000 2056.060000 848.520000 2056.540000 ;
+ RECT 843.290000 2056.060000 844.290000 2056.540000 ;
+ RECT 847.420000 2050.620000 848.520000 2051.100000 ;
+ RECT 843.290000 2050.620000 844.290000 2051.100000 ;
+ RECT 1027.420000 2045.180000 1028.520000 2045.660000 ;
+ RECT 1027.420000 2039.740000 1028.520000 2040.220000 ;
+ RECT 1036.730000 2045.180000 1037.730000 2045.660000 ;
+ RECT 1036.730000 2039.740000 1037.730000 2040.220000 ;
+ RECT 1036.730000 2023.420000 1037.730000 2023.900000 ;
+ RECT 1036.730000 2028.860000 1037.730000 2029.340000 ;
+ RECT 1036.730000 2034.300000 1037.730000 2034.780000 ;
+ RECT 1027.420000 2034.300000 1028.520000 2034.780000 ;
+ RECT 1027.420000 2028.860000 1028.520000 2029.340000 ;
+ RECT 1027.420000 2023.420000 1028.520000 2023.900000 ;
+ RECT 1027.420000 2012.540000 1028.520000 2013.020000 ;
+ RECT 1027.420000 2017.980000 1028.520000 2018.460000 ;
+ RECT 1036.730000 2017.980000 1037.730000 2018.460000 ;
+ RECT 1036.730000 2012.540000 1037.730000 2013.020000 ;
+ RECT 1036.730000 2001.660000 1037.730000 2002.140000 ;
+ RECT 1036.730000 2007.100000 1037.730000 2007.580000 ;
+ RECT 1027.420000 2001.660000 1028.520000 2002.140000 ;
+ RECT 1027.420000 2007.100000 1028.520000 2007.580000 ;
+ RECT 982.420000 2045.180000 983.520000 2045.660000 ;
+ RECT 982.420000 2039.740000 983.520000 2040.220000 ;
+ RECT 982.420000 2034.300000 983.520000 2034.780000 ;
+ RECT 982.420000 2028.860000 983.520000 2029.340000 ;
+ RECT 982.420000 2023.420000 983.520000 2023.900000 ;
+ RECT 982.420000 2001.660000 983.520000 2002.140000 ;
+ RECT 982.420000 2007.100000 983.520000 2007.580000 ;
+ RECT 982.420000 2012.540000 983.520000 2013.020000 ;
+ RECT 982.420000 2017.980000 983.520000 2018.460000 ;
+ RECT 1027.420000 1996.220000 1028.520000 1996.700000 ;
+ RECT 1027.420000 1990.780000 1028.520000 1991.260000 ;
+ RECT 1036.730000 1996.220000 1037.730000 1996.700000 ;
+ RECT 1036.730000 1990.780000 1037.730000 1991.260000 ;
+ RECT 1027.420000 1979.900000 1028.520000 1980.380000 ;
+ RECT 1027.420000 1974.460000 1028.520000 1974.940000 ;
+ RECT 1036.730000 1979.900000 1037.730000 1980.380000 ;
+ RECT 1036.730000 1974.460000 1037.730000 1974.940000 ;
+ RECT 1027.420000 1985.340000 1028.520000 1985.820000 ;
+ RECT 1036.730000 1985.340000 1037.730000 1985.820000 ;
+ RECT 1036.730000 1963.580000 1037.730000 1964.060000 ;
+ RECT 1036.730000 1969.020000 1037.730000 1969.500000 ;
+ RECT 1027.420000 1969.020000 1028.520000 1969.500000 ;
+ RECT 1027.420000 1963.580000 1028.520000 1964.060000 ;
+ RECT 1027.420000 1958.140000 1028.520000 1958.620000 ;
+ RECT 1027.420000 1952.700000 1028.520000 1953.180000 ;
+ RECT 1036.730000 1958.140000 1037.730000 1958.620000 ;
+ RECT 1036.730000 1952.700000 1037.730000 1953.180000 ;
+ RECT 982.420000 1996.220000 983.520000 1996.700000 ;
+ RECT 982.420000 1990.780000 983.520000 1991.260000 ;
+ RECT 982.420000 1985.340000 983.520000 1985.820000 ;
+ RECT 982.420000 1979.900000 983.520000 1980.380000 ;
+ RECT 982.420000 1974.460000 983.520000 1974.940000 ;
+ RECT 982.420000 1969.020000 983.520000 1969.500000 ;
+ RECT 982.420000 1963.580000 983.520000 1964.060000 ;
+ RECT 982.420000 1958.140000 983.520000 1958.620000 ;
+ RECT 982.420000 1952.700000 983.520000 1953.180000 ;
+ RECT 937.420000 2045.180000 938.520000 2045.660000 ;
+ RECT 937.420000 2039.740000 938.520000 2040.220000 ;
+ RECT 937.420000 2034.300000 938.520000 2034.780000 ;
+ RECT 937.420000 2028.860000 938.520000 2029.340000 ;
+ RECT 937.420000 2023.420000 938.520000 2023.900000 ;
+ RECT 892.420000 2045.180000 893.520000 2045.660000 ;
+ RECT 892.420000 2039.740000 893.520000 2040.220000 ;
+ RECT 892.420000 2034.300000 893.520000 2034.780000 ;
+ RECT 892.420000 2028.860000 893.520000 2029.340000 ;
+ RECT 892.420000 2023.420000 893.520000 2023.900000 ;
+ RECT 937.420000 2017.980000 938.520000 2018.460000 ;
+ RECT 937.420000 2012.540000 938.520000 2013.020000 ;
+ RECT 937.420000 2007.100000 938.520000 2007.580000 ;
+ RECT 937.420000 2001.660000 938.520000 2002.140000 ;
+ RECT 892.420000 2012.540000 893.520000 2013.020000 ;
+ RECT 892.420000 2007.100000 893.520000 2007.580000 ;
+ RECT 892.420000 2001.660000 893.520000 2002.140000 ;
+ RECT 892.420000 2017.980000 893.520000 2018.460000 ;
+ RECT 847.420000 2045.180000 848.520000 2045.660000 ;
+ RECT 843.290000 2045.180000 844.290000 2045.660000 ;
+ RECT 847.420000 2039.740000 848.520000 2040.220000 ;
+ RECT 843.290000 2039.740000 844.290000 2040.220000 ;
+ RECT 847.420000 2034.300000 848.520000 2034.780000 ;
+ RECT 843.290000 2034.300000 844.290000 2034.780000 ;
+ RECT 847.420000 2023.420000 848.520000 2023.900000 ;
+ RECT 843.290000 2023.420000 844.290000 2023.900000 ;
+ RECT 843.290000 2028.860000 844.290000 2029.340000 ;
+ RECT 847.420000 2028.860000 848.520000 2029.340000 ;
+ RECT 847.420000 2017.980000 848.520000 2018.460000 ;
+ RECT 843.290000 2017.980000 844.290000 2018.460000 ;
+ RECT 847.420000 2012.540000 848.520000 2013.020000 ;
+ RECT 843.290000 2012.540000 844.290000 2013.020000 ;
+ RECT 847.420000 2007.100000 848.520000 2007.580000 ;
+ RECT 843.290000 2007.100000 844.290000 2007.580000 ;
+ RECT 847.420000 2001.660000 848.520000 2002.140000 ;
+ RECT 843.290000 2001.660000 844.290000 2002.140000 ;
+ RECT 937.420000 1996.220000 938.520000 1996.700000 ;
+ RECT 937.420000 1990.780000 938.520000 1991.260000 ;
+ RECT 937.420000 1985.340000 938.520000 1985.820000 ;
+ RECT 937.420000 1979.900000 938.520000 1980.380000 ;
+ RECT 937.420000 1974.460000 938.520000 1974.940000 ;
+ RECT 892.420000 1996.220000 893.520000 1996.700000 ;
+ RECT 892.420000 1990.780000 893.520000 1991.260000 ;
+ RECT 892.420000 1985.340000 893.520000 1985.820000 ;
+ RECT 892.420000 1979.900000 893.520000 1980.380000 ;
+ RECT 892.420000 1974.460000 893.520000 1974.940000 ;
+ RECT 937.420000 1952.700000 938.520000 1953.180000 ;
+ RECT 937.420000 1958.140000 938.520000 1958.620000 ;
+ RECT 937.420000 1963.580000 938.520000 1964.060000 ;
+ RECT 937.420000 1969.020000 938.520000 1969.500000 ;
+ RECT 892.420000 1952.700000 893.520000 1953.180000 ;
+ RECT 892.420000 1958.140000 893.520000 1958.620000 ;
+ RECT 892.420000 1963.580000 893.520000 1964.060000 ;
+ RECT 892.420000 1969.020000 893.520000 1969.500000 ;
+ RECT 847.420000 1996.220000 848.520000 1996.700000 ;
+ RECT 843.290000 1996.220000 844.290000 1996.700000 ;
+ RECT 847.420000 1990.780000 848.520000 1991.260000 ;
+ RECT 843.290000 1990.780000 844.290000 1991.260000 ;
+ RECT 847.420000 1979.900000 848.520000 1980.380000 ;
+ RECT 843.290000 1979.900000 844.290000 1980.380000 ;
+ RECT 847.420000 1974.460000 848.520000 1974.940000 ;
+ RECT 843.290000 1974.460000 844.290000 1974.940000 ;
+ RECT 847.420000 1985.340000 848.520000 1985.820000 ;
+ RECT 843.290000 1985.340000 844.290000 1985.820000 ;
+ RECT 847.420000 1969.020000 848.520000 1969.500000 ;
+ RECT 843.290000 1969.020000 844.290000 1969.500000 ;
+ RECT 847.420000 1963.580000 848.520000 1964.060000 ;
+ RECT 843.290000 1963.580000 844.290000 1964.060000 ;
+ RECT 847.420000 1958.140000 848.520000 1958.620000 ;
+ RECT 847.420000 1952.700000 848.520000 1953.180000 ;
+ RECT 843.290000 1958.140000 844.290000 1958.620000 ;
+ RECT 843.290000 1952.700000 844.290000 1953.180000 ;
+ RECT 840.460000 2143.060000 1040.560000 2144.060000 ;
+ RECT 840.460000 1950.690000 1040.560000 1951.690000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 1947.840000 844.290000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 2147.100000 844.290000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 1947.840000 1037.730000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 2147.100000 1037.730000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1950.690000 841.460000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1950.690000 1040.560000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 2143.060000 841.460000 2144.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 2143.060000 1040.560000 2144.060000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 1750.430000 1028.520000 1943.800000 ;
+ RECT 982.420000 1750.430000 983.520000 1943.800000 ;
+ RECT 1036.730000 1747.580000 1037.730000 1947.840000 ;
+ RECT 937.420000 1750.430000 938.520000 1943.800000 ;
+ RECT 892.420000 1750.430000 893.520000 1943.800000 ;
+ RECT 847.420000 1750.430000 848.520000 1943.800000 ;
+ RECT 843.290000 1747.580000 844.290000 1947.840000 ;
+ LAYER met3 ;
+ RECT 1027.420000 1937.400000 1028.520000 1937.880000 ;
+ RECT 1036.730000 1937.400000 1037.730000 1937.880000 ;
+ RECT 1036.730000 1926.520000 1037.730000 1927.000000 ;
+ RECT 1036.730000 1931.960000 1037.730000 1932.440000 ;
+ RECT 1027.420000 1931.960000 1028.520000 1932.440000 ;
+ RECT 1027.420000 1926.520000 1028.520000 1927.000000 ;
+ RECT 1027.420000 1921.080000 1028.520000 1921.560000 ;
+ RECT 1027.420000 1915.640000 1028.520000 1916.120000 ;
+ RECT 1036.730000 1921.080000 1037.730000 1921.560000 ;
+ RECT 1036.730000 1915.640000 1037.730000 1916.120000 ;
+ RECT 1027.420000 1899.320000 1028.520000 1899.800000 ;
+ RECT 1027.420000 1904.760000 1028.520000 1905.240000 ;
+ RECT 1036.730000 1904.760000 1037.730000 1905.240000 ;
+ RECT 1036.730000 1899.320000 1037.730000 1899.800000 ;
+ RECT 1027.420000 1910.200000 1028.520000 1910.680000 ;
+ RECT 1036.730000 1910.200000 1037.730000 1910.680000 ;
+ RECT 982.420000 1937.400000 983.520000 1937.880000 ;
+ RECT 982.420000 1931.960000 983.520000 1932.440000 ;
+ RECT 982.420000 1926.520000 983.520000 1927.000000 ;
+ RECT 982.420000 1921.080000 983.520000 1921.560000 ;
+ RECT 982.420000 1899.320000 983.520000 1899.800000 ;
+ RECT 982.420000 1904.760000 983.520000 1905.240000 ;
+ RECT 982.420000 1910.200000 983.520000 1910.680000 ;
+ RECT 982.420000 1915.640000 983.520000 1916.120000 ;
+ RECT 1036.730000 1888.440000 1037.730000 1888.920000 ;
+ RECT 1036.730000 1893.880000 1037.730000 1894.360000 ;
+ RECT 1027.420000 1893.880000 1028.520000 1894.360000 ;
+ RECT 1027.420000 1888.440000 1028.520000 1888.920000 ;
+ RECT 1027.420000 1883.000000 1028.520000 1883.480000 ;
+ RECT 1027.420000 1877.560000 1028.520000 1878.040000 ;
+ RECT 1036.730000 1883.000000 1037.730000 1883.480000 ;
+ RECT 1036.730000 1877.560000 1037.730000 1878.040000 ;
+ RECT 1036.730000 1861.240000 1037.730000 1861.720000 ;
+ RECT 1036.730000 1866.680000 1037.730000 1867.160000 ;
+ RECT 1036.730000 1872.120000 1037.730000 1872.600000 ;
+ RECT 1027.420000 1866.680000 1028.520000 1867.160000 ;
+ RECT 1027.420000 1861.240000 1028.520000 1861.720000 ;
+ RECT 1027.420000 1872.120000 1028.520000 1872.600000 ;
+ RECT 1027.420000 1855.800000 1028.520000 1856.280000 ;
+ RECT 1027.420000 1850.360000 1028.520000 1850.840000 ;
+ RECT 1036.730000 1855.800000 1037.730000 1856.280000 ;
+ RECT 1036.730000 1850.360000 1037.730000 1850.840000 ;
+ RECT 982.420000 1893.880000 983.520000 1894.360000 ;
+ RECT 982.420000 1888.440000 983.520000 1888.920000 ;
+ RECT 982.420000 1883.000000 983.520000 1883.480000 ;
+ RECT 982.420000 1877.560000 983.520000 1878.040000 ;
+ RECT 982.420000 1866.680000 983.520000 1867.160000 ;
+ RECT 982.420000 1861.240000 983.520000 1861.720000 ;
+ RECT 982.420000 1855.800000 983.520000 1856.280000 ;
+ RECT 982.420000 1850.360000 983.520000 1850.840000 ;
+ RECT 982.420000 1872.120000 983.520000 1872.600000 ;
+ RECT 937.420000 1937.400000 938.520000 1937.880000 ;
+ RECT 937.420000 1931.960000 938.520000 1932.440000 ;
+ RECT 937.420000 1926.520000 938.520000 1927.000000 ;
+ RECT 892.420000 1937.400000 893.520000 1937.880000 ;
+ RECT 892.420000 1931.960000 893.520000 1932.440000 ;
+ RECT 892.420000 1926.520000 893.520000 1927.000000 ;
+ RECT 937.420000 1910.200000 938.520000 1910.680000 ;
+ RECT 937.420000 1904.760000 938.520000 1905.240000 ;
+ RECT 937.420000 1899.320000 938.520000 1899.800000 ;
+ RECT 937.420000 1915.640000 938.520000 1916.120000 ;
+ RECT 937.420000 1921.080000 938.520000 1921.560000 ;
+ RECT 892.420000 1921.080000 893.520000 1921.560000 ;
+ RECT 892.420000 1910.200000 893.520000 1910.680000 ;
+ RECT 892.420000 1904.760000 893.520000 1905.240000 ;
+ RECT 892.420000 1899.320000 893.520000 1899.800000 ;
+ RECT 892.420000 1915.640000 893.520000 1916.120000 ;
+ RECT 847.420000 1937.400000 848.520000 1937.880000 ;
+ RECT 843.290000 1937.400000 844.290000 1937.880000 ;
+ RECT 843.290000 1931.960000 844.290000 1932.440000 ;
+ RECT 847.420000 1931.960000 848.520000 1932.440000 ;
+ RECT 847.420000 1926.520000 848.520000 1927.000000 ;
+ RECT 843.290000 1926.520000 844.290000 1927.000000 ;
+ RECT 847.420000 1921.080000 848.520000 1921.560000 ;
+ RECT 843.290000 1921.080000 844.290000 1921.560000 ;
+ RECT 847.420000 1915.640000 848.520000 1916.120000 ;
+ RECT 843.290000 1915.640000 844.290000 1916.120000 ;
+ RECT 847.420000 1904.760000 848.520000 1905.240000 ;
+ RECT 843.290000 1904.760000 844.290000 1905.240000 ;
+ RECT 847.420000 1899.320000 848.520000 1899.800000 ;
+ RECT 843.290000 1899.320000 844.290000 1899.800000 ;
+ RECT 847.420000 1910.200000 848.520000 1910.680000 ;
+ RECT 843.290000 1910.200000 844.290000 1910.680000 ;
+ RECT 937.420000 1893.880000 938.520000 1894.360000 ;
+ RECT 937.420000 1888.440000 938.520000 1888.920000 ;
+ RECT 937.420000 1883.000000 938.520000 1883.480000 ;
+ RECT 937.420000 1877.560000 938.520000 1878.040000 ;
+ RECT 892.420000 1893.880000 893.520000 1894.360000 ;
+ RECT 892.420000 1888.440000 893.520000 1888.920000 ;
+ RECT 892.420000 1883.000000 893.520000 1883.480000 ;
+ RECT 892.420000 1877.560000 893.520000 1878.040000 ;
+ RECT 937.420000 1866.680000 938.520000 1867.160000 ;
+ RECT 937.420000 1850.360000 938.520000 1850.840000 ;
+ RECT 937.420000 1855.800000 938.520000 1856.280000 ;
+ RECT 937.420000 1861.240000 938.520000 1861.720000 ;
+ RECT 937.420000 1872.120000 938.520000 1872.600000 ;
+ RECT 892.420000 1850.360000 893.520000 1850.840000 ;
+ RECT 892.420000 1855.800000 893.520000 1856.280000 ;
+ RECT 892.420000 1861.240000 893.520000 1861.720000 ;
+ RECT 892.420000 1866.680000 893.520000 1867.160000 ;
+ RECT 892.420000 1872.120000 893.520000 1872.600000 ;
+ RECT 847.420000 1893.880000 848.520000 1894.360000 ;
+ RECT 843.290000 1893.880000 844.290000 1894.360000 ;
+ RECT 847.420000 1888.440000 848.520000 1888.920000 ;
+ RECT 843.290000 1888.440000 844.290000 1888.920000 ;
+ RECT 847.420000 1883.000000 848.520000 1883.480000 ;
+ RECT 843.290000 1883.000000 844.290000 1883.480000 ;
+ RECT 847.420000 1877.560000 848.520000 1878.040000 ;
+ RECT 843.290000 1877.560000 844.290000 1878.040000 ;
+ RECT 847.420000 1872.120000 848.520000 1872.600000 ;
+ RECT 847.420000 1866.680000 848.520000 1867.160000 ;
+ RECT 843.290000 1872.120000 844.290000 1872.600000 ;
+ RECT 843.290000 1866.680000 844.290000 1867.160000 ;
+ RECT 847.420000 1861.240000 848.520000 1861.720000 ;
+ RECT 843.290000 1861.240000 844.290000 1861.720000 ;
+ RECT 847.420000 1855.800000 848.520000 1856.280000 ;
+ RECT 843.290000 1855.800000 844.290000 1856.280000 ;
+ RECT 847.420000 1850.360000 848.520000 1850.840000 ;
+ RECT 843.290000 1850.360000 844.290000 1850.840000 ;
+ RECT 1027.420000 1844.920000 1028.520000 1845.400000 ;
+ RECT 1027.420000 1839.480000 1028.520000 1839.960000 ;
+ RECT 1036.730000 1844.920000 1037.730000 1845.400000 ;
+ RECT 1036.730000 1839.480000 1037.730000 1839.960000 ;
+ RECT 1036.730000 1823.160000 1037.730000 1823.640000 ;
+ RECT 1036.730000 1828.600000 1037.730000 1829.080000 ;
+ RECT 1036.730000 1834.040000 1037.730000 1834.520000 ;
+ RECT 1027.420000 1834.040000 1028.520000 1834.520000 ;
+ RECT 1027.420000 1828.600000 1028.520000 1829.080000 ;
+ RECT 1027.420000 1823.160000 1028.520000 1823.640000 ;
+ RECT 1027.420000 1812.280000 1028.520000 1812.760000 ;
+ RECT 1027.420000 1817.720000 1028.520000 1818.200000 ;
+ RECT 1036.730000 1817.720000 1037.730000 1818.200000 ;
+ RECT 1036.730000 1812.280000 1037.730000 1812.760000 ;
+ RECT 1036.730000 1801.400000 1037.730000 1801.880000 ;
+ RECT 1036.730000 1806.840000 1037.730000 1807.320000 ;
+ RECT 1027.420000 1801.400000 1028.520000 1801.880000 ;
+ RECT 1027.420000 1806.840000 1028.520000 1807.320000 ;
+ RECT 982.420000 1844.920000 983.520000 1845.400000 ;
+ RECT 982.420000 1839.480000 983.520000 1839.960000 ;
+ RECT 982.420000 1834.040000 983.520000 1834.520000 ;
+ RECT 982.420000 1828.600000 983.520000 1829.080000 ;
+ RECT 982.420000 1823.160000 983.520000 1823.640000 ;
+ RECT 982.420000 1801.400000 983.520000 1801.880000 ;
+ RECT 982.420000 1806.840000 983.520000 1807.320000 ;
+ RECT 982.420000 1812.280000 983.520000 1812.760000 ;
+ RECT 982.420000 1817.720000 983.520000 1818.200000 ;
+ RECT 1027.420000 1795.960000 1028.520000 1796.440000 ;
+ RECT 1027.420000 1790.520000 1028.520000 1791.000000 ;
+ RECT 1036.730000 1795.960000 1037.730000 1796.440000 ;
+ RECT 1036.730000 1790.520000 1037.730000 1791.000000 ;
+ RECT 1027.420000 1779.640000 1028.520000 1780.120000 ;
+ RECT 1027.420000 1774.200000 1028.520000 1774.680000 ;
+ RECT 1036.730000 1779.640000 1037.730000 1780.120000 ;
+ RECT 1036.730000 1774.200000 1037.730000 1774.680000 ;
+ RECT 1027.420000 1785.080000 1028.520000 1785.560000 ;
+ RECT 1036.730000 1785.080000 1037.730000 1785.560000 ;
+ RECT 1036.730000 1763.320000 1037.730000 1763.800000 ;
+ RECT 1036.730000 1768.760000 1037.730000 1769.240000 ;
+ RECT 1027.420000 1768.760000 1028.520000 1769.240000 ;
+ RECT 1027.420000 1763.320000 1028.520000 1763.800000 ;
+ RECT 1027.420000 1757.880000 1028.520000 1758.360000 ;
+ RECT 1027.420000 1752.440000 1028.520000 1752.920000 ;
+ RECT 1036.730000 1757.880000 1037.730000 1758.360000 ;
+ RECT 1036.730000 1752.440000 1037.730000 1752.920000 ;
+ RECT 982.420000 1795.960000 983.520000 1796.440000 ;
+ RECT 982.420000 1790.520000 983.520000 1791.000000 ;
+ RECT 982.420000 1785.080000 983.520000 1785.560000 ;
+ RECT 982.420000 1779.640000 983.520000 1780.120000 ;
+ RECT 982.420000 1774.200000 983.520000 1774.680000 ;
+ RECT 982.420000 1768.760000 983.520000 1769.240000 ;
+ RECT 982.420000 1763.320000 983.520000 1763.800000 ;
+ RECT 982.420000 1757.880000 983.520000 1758.360000 ;
+ RECT 982.420000 1752.440000 983.520000 1752.920000 ;
+ RECT 937.420000 1844.920000 938.520000 1845.400000 ;
+ RECT 937.420000 1839.480000 938.520000 1839.960000 ;
+ RECT 937.420000 1834.040000 938.520000 1834.520000 ;
+ RECT 937.420000 1828.600000 938.520000 1829.080000 ;
+ RECT 937.420000 1823.160000 938.520000 1823.640000 ;
+ RECT 892.420000 1844.920000 893.520000 1845.400000 ;
+ RECT 892.420000 1839.480000 893.520000 1839.960000 ;
+ RECT 892.420000 1834.040000 893.520000 1834.520000 ;
+ RECT 892.420000 1828.600000 893.520000 1829.080000 ;
+ RECT 892.420000 1823.160000 893.520000 1823.640000 ;
+ RECT 937.420000 1817.720000 938.520000 1818.200000 ;
+ RECT 937.420000 1812.280000 938.520000 1812.760000 ;
+ RECT 937.420000 1806.840000 938.520000 1807.320000 ;
+ RECT 937.420000 1801.400000 938.520000 1801.880000 ;
+ RECT 892.420000 1812.280000 893.520000 1812.760000 ;
+ RECT 892.420000 1806.840000 893.520000 1807.320000 ;
+ RECT 892.420000 1801.400000 893.520000 1801.880000 ;
+ RECT 892.420000 1817.720000 893.520000 1818.200000 ;
+ RECT 847.420000 1844.920000 848.520000 1845.400000 ;
+ RECT 843.290000 1844.920000 844.290000 1845.400000 ;
+ RECT 847.420000 1839.480000 848.520000 1839.960000 ;
+ RECT 843.290000 1839.480000 844.290000 1839.960000 ;
+ RECT 847.420000 1834.040000 848.520000 1834.520000 ;
+ RECT 843.290000 1834.040000 844.290000 1834.520000 ;
+ RECT 847.420000 1823.160000 848.520000 1823.640000 ;
+ RECT 843.290000 1823.160000 844.290000 1823.640000 ;
+ RECT 843.290000 1828.600000 844.290000 1829.080000 ;
+ RECT 847.420000 1828.600000 848.520000 1829.080000 ;
+ RECT 847.420000 1817.720000 848.520000 1818.200000 ;
+ RECT 843.290000 1817.720000 844.290000 1818.200000 ;
+ RECT 847.420000 1812.280000 848.520000 1812.760000 ;
+ RECT 843.290000 1812.280000 844.290000 1812.760000 ;
+ RECT 847.420000 1806.840000 848.520000 1807.320000 ;
+ RECT 843.290000 1806.840000 844.290000 1807.320000 ;
+ RECT 847.420000 1801.400000 848.520000 1801.880000 ;
+ RECT 843.290000 1801.400000 844.290000 1801.880000 ;
+ RECT 937.420000 1795.960000 938.520000 1796.440000 ;
+ RECT 937.420000 1790.520000 938.520000 1791.000000 ;
+ RECT 937.420000 1785.080000 938.520000 1785.560000 ;
+ RECT 937.420000 1779.640000 938.520000 1780.120000 ;
+ RECT 937.420000 1774.200000 938.520000 1774.680000 ;
+ RECT 892.420000 1795.960000 893.520000 1796.440000 ;
+ RECT 892.420000 1790.520000 893.520000 1791.000000 ;
+ RECT 892.420000 1785.080000 893.520000 1785.560000 ;
+ RECT 892.420000 1779.640000 893.520000 1780.120000 ;
+ RECT 892.420000 1774.200000 893.520000 1774.680000 ;
+ RECT 937.420000 1752.440000 938.520000 1752.920000 ;
+ RECT 937.420000 1757.880000 938.520000 1758.360000 ;
+ RECT 937.420000 1763.320000 938.520000 1763.800000 ;
+ RECT 937.420000 1768.760000 938.520000 1769.240000 ;
+ RECT 892.420000 1752.440000 893.520000 1752.920000 ;
+ RECT 892.420000 1757.880000 893.520000 1758.360000 ;
+ RECT 892.420000 1763.320000 893.520000 1763.800000 ;
+ RECT 892.420000 1768.760000 893.520000 1769.240000 ;
+ RECT 847.420000 1795.960000 848.520000 1796.440000 ;
+ RECT 843.290000 1795.960000 844.290000 1796.440000 ;
+ RECT 847.420000 1790.520000 848.520000 1791.000000 ;
+ RECT 843.290000 1790.520000 844.290000 1791.000000 ;
+ RECT 847.420000 1779.640000 848.520000 1780.120000 ;
+ RECT 843.290000 1779.640000 844.290000 1780.120000 ;
+ RECT 847.420000 1774.200000 848.520000 1774.680000 ;
+ RECT 843.290000 1774.200000 844.290000 1774.680000 ;
+ RECT 847.420000 1785.080000 848.520000 1785.560000 ;
+ RECT 843.290000 1785.080000 844.290000 1785.560000 ;
+ RECT 847.420000 1768.760000 848.520000 1769.240000 ;
+ RECT 843.290000 1768.760000 844.290000 1769.240000 ;
+ RECT 847.420000 1763.320000 848.520000 1763.800000 ;
+ RECT 843.290000 1763.320000 844.290000 1763.800000 ;
+ RECT 847.420000 1757.880000 848.520000 1758.360000 ;
+ RECT 847.420000 1752.440000 848.520000 1752.920000 ;
+ RECT 843.290000 1757.880000 844.290000 1758.360000 ;
+ RECT 843.290000 1752.440000 844.290000 1752.920000 ;
+ RECT 840.460000 1942.800000 1040.560000 1943.800000 ;
+ RECT 840.460000 1750.430000 1040.560000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 1747.580000 844.290000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 1946.840000 844.290000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 1747.580000 1037.730000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 1946.840000 1037.730000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1750.430000 841.460000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1750.430000 1040.560000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1942.800000 841.460000 1943.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1942.800000 1040.560000 1943.800000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1027.420000 1550.170000 1028.520000 1743.540000 ;
+ RECT 982.420000 1550.170000 983.520000 1743.540000 ;
+ RECT 1036.730000 1547.320000 1037.730000 1747.580000 ;
+ RECT 937.420000 1550.170000 938.520000 1743.540000 ;
+ RECT 892.420000 1550.170000 893.520000 1743.540000 ;
+ RECT 847.420000 1550.170000 848.520000 1743.540000 ;
+ RECT 843.290000 1547.320000 844.290000 1747.580000 ;
+ LAYER met3 ;
+ RECT 1027.420000 1737.140000 1028.520000 1737.620000 ;
+ RECT 1036.730000 1737.140000 1037.730000 1737.620000 ;
+ RECT 1036.730000 1726.260000 1037.730000 1726.740000 ;
+ RECT 1036.730000 1731.700000 1037.730000 1732.180000 ;
+ RECT 1027.420000 1731.700000 1028.520000 1732.180000 ;
+ RECT 1027.420000 1726.260000 1028.520000 1726.740000 ;
+ RECT 1027.420000 1720.820000 1028.520000 1721.300000 ;
+ RECT 1027.420000 1715.380000 1028.520000 1715.860000 ;
+ RECT 1036.730000 1720.820000 1037.730000 1721.300000 ;
+ RECT 1036.730000 1715.380000 1037.730000 1715.860000 ;
+ RECT 1027.420000 1699.060000 1028.520000 1699.540000 ;
+ RECT 1027.420000 1704.500000 1028.520000 1704.980000 ;
+ RECT 1036.730000 1704.500000 1037.730000 1704.980000 ;
+ RECT 1036.730000 1699.060000 1037.730000 1699.540000 ;
+ RECT 1027.420000 1709.940000 1028.520000 1710.420000 ;
+ RECT 1036.730000 1709.940000 1037.730000 1710.420000 ;
+ RECT 982.420000 1737.140000 983.520000 1737.620000 ;
+ RECT 982.420000 1731.700000 983.520000 1732.180000 ;
+ RECT 982.420000 1726.260000 983.520000 1726.740000 ;
+ RECT 982.420000 1720.820000 983.520000 1721.300000 ;
+ RECT 982.420000 1699.060000 983.520000 1699.540000 ;
+ RECT 982.420000 1704.500000 983.520000 1704.980000 ;
+ RECT 982.420000 1709.940000 983.520000 1710.420000 ;
+ RECT 982.420000 1715.380000 983.520000 1715.860000 ;
+ RECT 1036.730000 1688.180000 1037.730000 1688.660000 ;
+ RECT 1036.730000 1693.620000 1037.730000 1694.100000 ;
+ RECT 1027.420000 1693.620000 1028.520000 1694.100000 ;
+ RECT 1027.420000 1688.180000 1028.520000 1688.660000 ;
+ RECT 1027.420000 1682.740000 1028.520000 1683.220000 ;
+ RECT 1027.420000 1677.300000 1028.520000 1677.780000 ;
+ RECT 1036.730000 1682.740000 1037.730000 1683.220000 ;
+ RECT 1036.730000 1677.300000 1037.730000 1677.780000 ;
+ RECT 1036.730000 1660.980000 1037.730000 1661.460000 ;
+ RECT 1036.730000 1666.420000 1037.730000 1666.900000 ;
+ RECT 1036.730000 1671.860000 1037.730000 1672.340000 ;
+ RECT 1027.420000 1666.420000 1028.520000 1666.900000 ;
+ RECT 1027.420000 1660.980000 1028.520000 1661.460000 ;
+ RECT 1027.420000 1671.860000 1028.520000 1672.340000 ;
+ RECT 1027.420000 1655.540000 1028.520000 1656.020000 ;
+ RECT 1027.420000 1650.100000 1028.520000 1650.580000 ;
+ RECT 1036.730000 1655.540000 1037.730000 1656.020000 ;
+ RECT 1036.730000 1650.100000 1037.730000 1650.580000 ;
+ RECT 982.420000 1693.620000 983.520000 1694.100000 ;
+ RECT 982.420000 1688.180000 983.520000 1688.660000 ;
+ RECT 982.420000 1682.740000 983.520000 1683.220000 ;
+ RECT 982.420000 1677.300000 983.520000 1677.780000 ;
+ RECT 982.420000 1666.420000 983.520000 1666.900000 ;
+ RECT 982.420000 1660.980000 983.520000 1661.460000 ;
+ RECT 982.420000 1655.540000 983.520000 1656.020000 ;
+ RECT 982.420000 1650.100000 983.520000 1650.580000 ;
+ RECT 982.420000 1671.860000 983.520000 1672.340000 ;
+ RECT 937.420000 1737.140000 938.520000 1737.620000 ;
+ RECT 937.420000 1731.700000 938.520000 1732.180000 ;
+ RECT 937.420000 1726.260000 938.520000 1726.740000 ;
+ RECT 892.420000 1737.140000 893.520000 1737.620000 ;
+ RECT 892.420000 1731.700000 893.520000 1732.180000 ;
+ RECT 892.420000 1726.260000 893.520000 1726.740000 ;
+ RECT 937.420000 1709.940000 938.520000 1710.420000 ;
+ RECT 937.420000 1704.500000 938.520000 1704.980000 ;
+ RECT 937.420000 1699.060000 938.520000 1699.540000 ;
+ RECT 937.420000 1715.380000 938.520000 1715.860000 ;
+ RECT 937.420000 1720.820000 938.520000 1721.300000 ;
+ RECT 892.420000 1720.820000 893.520000 1721.300000 ;
+ RECT 892.420000 1709.940000 893.520000 1710.420000 ;
+ RECT 892.420000 1704.500000 893.520000 1704.980000 ;
+ RECT 892.420000 1699.060000 893.520000 1699.540000 ;
+ RECT 892.420000 1715.380000 893.520000 1715.860000 ;
+ RECT 847.420000 1737.140000 848.520000 1737.620000 ;
+ RECT 843.290000 1737.140000 844.290000 1737.620000 ;
+ RECT 843.290000 1731.700000 844.290000 1732.180000 ;
+ RECT 847.420000 1731.700000 848.520000 1732.180000 ;
+ RECT 847.420000 1726.260000 848.520000 1726.740000 ;
+ RECT 843.290000 1726.260000 844.290000 1726.740000 ;
+ RECT 847.420000 1720.820000 848.520000 1721.300000 ;
+ RECT 843.290000 1720.820000 844.290000 1721.300000 ;
+ RECT 847.420000 1715.380000 848.520000 1715.860000 ;
+ RECT 843.290000 1715.380000 844.290000 1715.860000 ;
+ RECT 847.420000 1704.500000 848.520000 1704.980000 ;
+ RECT 843.290000 1704.500000 844.290000 1704.980000 ;
+ RECT 847.420000 1699.060000 848.520000 1699.540000 ;
+ RECT 843.290000 1699.060000 844.290000 1699.540000 ;
+ RECT 847.420000 1709.940000 848.520000 1710.420000 ;
+ RECT 843.290000 1709.940000 844.290000 1710.420000 ;
+ RECT 937.420000 1693.620000 938.520000 1694.100000 ;
+ RECT 937.420000 1688.180000 938.520000 1688.660000 ;
+ RECT 937.420000 1682.740000 938.520000 1683.220000 ;
+ RECT 937.420000 1677.300000 938.520000 1677.780000 ;
+ RECT 892.420000 1693.620000 893.520000 1694.100000 ;
+ RECT 892.420000 1688.180000 893.520000 1688.660000 ;
+ RECT 892.420000 1682.740000 893.520000 1683.220000 ;
+ RECT 892.420000 1677.300000 893.520000 1677.780000 ;
+ RECT 937.420000 1666.420000 938.520000 1666.900000 ;
+ RECT 937.420000 1650.100000 938.520000 1650.580000 ;
+ RECT 937.420000 1655.540000 938.520000 1656.020000 ;
+ RECT 937.420000 1660.980000 938.520000 1661.460000 ;
+ RECT 937.420000 1671.860000 938.520000 1672.340000 ;
+ RECT 892.420000 1650.100000 893.520000 1650.580000 ;
+ RECT 892.420000 1655.540000 893.520000 1656.020000 ;
+ RECT 892.420000 1660.980000 893.520000 1661.460000 ;
+ RECT 892.420000 1666.420000 893.520000 1666.900000 ;
+ RECT 892.420000 1671.860000 893.520000 1672.340000 ;
+ RECT 847.420000 1693.620000 848.520000 1694.100000 ;
+ RECT 843.290000 1693.620000 844.290000 1694.100000 ;
+ RECT 847.420000 1688.180000 848.520000 1688.660000 ;
+ RECT 843.290000 1688.180000 844.290000 1688.660000 ;
+ RECT 847.420000 1682.740000 848.520000 1683.220000 ;
+ RECT 843.290000 1682.740000 844.290000 1683.220000 ;
+ RECT 847.420000 1677.300000 848.520000 1677.780000 ;
+ RECT 843.290000 1677.300000 844.290000 1677.780000 ;
+ RECT 847.420000 1671.860000 848.520000 1672.340000 ;
+ RECT 847.420000 1666.420000 848.520000 1666.900000 ;
+ RECT 843.290000 1671.860000 844.290000 1672.340000 ;
+ RECT 843.290000 1666.420000 844.290000 1666.900000 ;
+ RECT 847.420000 1660.980000 848.520000 1661.460000 ;
+ RECT 843.290000 1660.980000 844.290000 1661.460000 ;
+ RECT 847.420000 1655.540000 848.520000 1656.020000 ;
+ RECT 843.290000 1655.540000 844.290000 1656.020000 ;
+ RECT 847.420000 1650.100000 848.520000 1650.580000 ;
+ RECT 843.290000 1650.100000 844.290000 1650.580000 ;
+ RECT 1027.420000 1644.660000 1028.520000 1645.140000 ;
+ RECT 1027.420000 1639.220000 1028.520000 1639.700000 ;
+ RECT 1036.730000 1644.660000 1037.730000 1645.140000 ;
+ RECT 1036.730000 1639.220000 1037.730000 1639.700000 ;
+ RECT 1036.730000 1622.900000 1037.730000 1623.380000 ;
+ RECT 1036.730000 1628.340000 1037.730000 1628.820000 ;
+ RECT 1036.730000 1633.780000 1037.730000 1634.260000 ;
+ RECT 1027.420000 1633.780000 1028.520000 1634.260000 ;
+ RECT 1027.420000 1628.340000 1028.520000 1628.820000 ;
+ RECT 1027.420000 1622.900000 1028.520000 1623.380000 ;
+ RECT 1027.420000 1612.020000 1028.520000 1612.500000 ;
+ RECT 1027.420000 1617.460000 1028.520000 1617.940000 ;
+ RECT 1036.730000 1617.460000 1037.730000 1617.940000 ;
+ RECT 1036.730000 1612.020000 1037.730000 1612.500000 ;
+ RECT 1036.730000 1601.140000 1037.730000 1601.620000 ;
+ RECT 1036.730000 1606.580000 1037.730000 1607.060000 ;
+ RECT 1027.420000 1601.140000 1028.520000 1601.620000 ;
+ RECT 1027.420000 1606.580000 1028.520000 1607.060000 ;
+ RECT 982.420000 1644.660000 983.520000 1645.140000 ;
+ RECT 982.420000 1639.220000 983.520000 1639.700000 ;
+ RECT 982.420000 1633.780000 983.520000 1634.260000 ;
+ RECT 982.420000 1628.340000 983.520000 1628.820000 ;
+ RECT 982.420000 1622.900000 983.520000 1623.380000 ;
+ RECT 982.420000 1601.140000 983.520000 1601.620000 ;
+ RECT 982.420000 1606.580000 983.520000 1607.060000 ;
+ RECT 982.420000 1612.020000 983.520000 1612.500000 ;
+ RECT 982.420000 1617.460000 983.520000 1617.940000 ;
+ RECT 1027.420000 1595.700000 1028.520000 1596.180000 ;
+ RECT 1027.420000 1590.260000 1028.520000 1590.740000 ;
+ RECT 1036.730000 1595.700000 1037.730000 1596.180000 ;
+ RECT 1036.730000 1590.260000 1037.730000 1590.740000 ;
+ RECT 1027.420000 1579.380000 1028.520000 1579.860000 ;
+ RECT 1027.420000 1573.940000 1028.520000 1574.420000 ;
+ RECT 1036.730000 1579.380000 1037.730000 1579.860000 ;
+ RECT 1036.730000 1573.940000 1037.730000 1574.420000 ;
+ RECT 1027.420000 1584.820000 1028.520000 1585.300000 ;
+ RECT 1036.730000 1584.820000 1037.730000 1585.300000 ;
+ RECT 1036.730000 1563.060000 1037.730000 1563.540000 ;
+ RECT 1036.730000 1568.500000 1037.730000 1568.980000 ;
+ RECT 1027.420000 1568.500000 1028.520000 1568.980000 ;
+ RECT 1027.420000 1563.060000 1028.520000 1563.540000 ;
+ RECT 1027.420000 1557.620000 1028.520000 1558.100000 ;
+ RECT 1027.420000 1552.180000 1028.520000 1552.660000 ;
+ RECT 1036.730000 1557.620000 1037.730000 1558.100000 ;
+ RECT 1036.730000 1552.180000 1037.730000 1552.660000 ;
+ RECT 982.420000 1595.700000 983.520000 1596.180000 ;
+ RECT 982.420000 1590.260000 983.520000 1590.740000 ;
+ RECT 982.420000 1584.820000 983.520000 1585.300000 ;
+ RECT 982.420000 1579.380000 983.520000 1579.860000 ;
+ RECT 982.420000 1573.940000 983.520000 1574.420000 ;
+ RECT 982.420000 1568.500000 983.520000 1568.980000 ;
+ RECT 982.420000 1563.060000 983.520000 1563.540000 ;
+ RECT 982.420000 1557.620000 983.520000 1558.100000 ;
+ RECT 982.420000 1552.180000 983.520000 1552.660000 ;
+ RECT 937.420000 1644.660000 938.520000 1645.140000 ;
+ RECT 937.420000 1639.220000 938.520000 1639.700000 ;
+ RECT 937.420000 1633.780000 938.520000 1634.260000 ;
+ RECT 937.420000 1628.340000 938.520000 1628.820000 ;
+ RECT 937.420000 1622.900000 938.520000 1623.380000 ;
+ RECT 892.420000 1644.660000 893.520000 1645.140000 ;
+ RECT 892.420000 1639.220000 893.520000 1639.700000 ;
+ RECT 892.420000 1633.780000 893.520000 1634.260000 ;
+ RECT 892.420000 1628.340000 893.520000 1628.820000 ;
+ RECT 892.420000 1622.900000 893.520000 1623.380000 ;
+ RECT 937.420000 1617.460000 938.520000 1617.940000 ;
+ RECT 937.420000 1612.020000 938.520000 1612.500000 ;
+ RECT 937.420000 1606.580000 938.520000 1607.060000 ;
+ RECT 937.420000 1601.140000 938.520000 1601.620000 ;
+ RECT 892.420000 1612.020000 893.520000 1612.500000 ;
+ RECT 892.420000 1606.580000 893.520000 1607.060000 ;
+ RECT 892.420000 1601.140000 893.520000 1601.620000 ;
+ RECT 892.420000 1617.460000 893.520000 1617.940000 ;
+ RECT 847.420000 1644.660000 848.520000 1645.140000 ;
+ RECT 843.290000 1644.660000 844.290000 1645.140000 ;
+ RECT 847.420000 1639.220000 848.520000 1639.700000 ;
+ RECT 843.290000 1639.220000 844.290000 1639.700000 ;
+ RECT 847.420000 1633.780000 848.520000 1634.260000 ;
+ RECT 843.290000 1633.780000 844.290000 1634.260000 ;
+ RECT 847.420000 1622.900000 848.520000 1623.380000 ;
+ RECT 843.290000 1622.900000 844.290000 1623.380000 ;
+ RECT 843.290000 1628.340000 844.290000 1628.820000 ;
+ RECT 847.420000 1628.340000 848.520000 1628.820000 ;
+ RECT 847.420000 1617.460000 848.520000 1617.940000 ;
+ RECT 843.290000 1617.460000 844.290000 1617.940000 ;
+ RECT 847.420000 1612.020000 848.520000 1612.500000 ;
+ RECT 843.290000 1612.020000 844.290000 1612.500000 ;
+ RECT 847.420000 1606.580000 848.520000 1607.060000 ;
+ RECT 843.290000 1606.580000 844.290000 1607.060000 ;
+ RECT 847.420000 1601.140000 848.520000 1601.620000 ;
+ RECT 843.290000 1601.140000 844.290000 1601.620000 ;
+ RECT 937.420000 1595.700000 938.520000 1596.180000 ;
+ RECT 937.420000 1590.260000 938.520000 1590.740000 ;
+ RECT 937.420000 1584.820000 938.520000 1585.300000 ;
+ RECT 937.420000 1579.380000 938.520000 1579.860000 ;
+ RECT 937.420000 1573.940000 938.520000 1574.420000 ;
+ RECT 892.420000 1595.700000 893.520000 1596.180000 ;
+ RECT 892.420000 1590.260000 893.520000 1590.740000 ;
+ RECT 892.420000 1584.820000 893.520000 1585.300000 ;
+ RECT 892.420000 1579.380000 893.520000 1579.860000 ;
+ RECT 892.420000 1573.940000 893.520000 1574.420000 ;
+ RECT 937.420000 1552.180000 938.520000 1552.660000 ;
+ RECT 937.420000 1557.620000 938.520000 1558.100000 ;
+ RECT 937.420000 1563.060000 938.520000 1563.540000 ;
+ RECT 937.420000 1568.500000 938.520000 1568.980000 ;
+ RECT 892.420000 1552.180000 893.520000 1552.660000 ;
+ RECT 892.420000 1557.620000 893.520000 1558.100000 ;
+ RECT 892.420000 1563.060000 893.520000 1563.540000 ;
+ RECT 892.420000 1568.500000 893.520000 1568.980000 ;
+ RECT 847.420000 1595.700000 848.520000 1596.180000 ;
+ RECT 843.290000 1595.700000 844.290000 1596.180000 ;
+ RECT 847.420000 1590.260000 848.520000 1590.740000 ;
+ RECT 843.290000 1590.260000 844.290000 1590.740000 ;
+ RECT 847.420000 1579.380000 848.520000 1579.860000 ;
+ RECT 843.290000 1579.380000 844.290000 1579.860000 ;
+ RECT 847.420000 1573.940000 848.520000 1574.420000 ;
+ RECT 843.290000 1573.940000 844.290000 1574.420000 ;
+ RECT 847.420000 1584.820000 848.520000 1585.300000 ;
+ RECT 843.290000 1584.820000 844.290000 1585.300000 ;
+ RECT 847.420000 1568.500000 848.520000 1568.980000 ;
+ RECT 843.290000 1568.500000 844.290000 1568.980000 ;
+ RECT 847.420000 1563.060000 848.520000 1563.540000 ;
+ RECT 843.290000 1563.060000 844.290000 1563.540000 ;
+ RECT 847.420000 1557.620000 848.520000 1558.100000 ;
+ RECT 847.420000 1552.180000 848.520000 1552.660000 ;
+ RECT 843.290000 1557.620000 844.290000 1558.100000 ;
+ RECT 843.290000 1552.180000 844.290000 1552.660000 ;
+ RECT 840.460000 1742.540000 1040.560000 1743.540000 ;
+ RECT 840.460000 1550.170000 1040.560000 1551.170000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 1547.320000 844.290000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 843.290000 1746.580000 844.290000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 1547.320000 1037.730000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1036.730000 1746.580000 1037.730000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1550.170000 841.460000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1550.170000 1040.560000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 840.460000 1742.540000 841.460000 1743.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1039.560000 1742.540000 1040.560000 1743.540000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 3349.660000 1044.390000 3379.920000 ;
+ RECT 1236.830000 3349.660000 1237.830000 3379.920000 ;
+ RECT 1047.520000 3352.510000 1048.620000 3376.560000 ;
+ RECT 1092.520000 3352.510000 1093.620000 3376.560000 ;
+ RECT 1137.520000 3352.510000 1138.620000 3376.560000 ;
+ RECT 1182.520000 3352.510000 1183.620000 3376.560000 ;
+ RECT 1227.520000 3352.510000 1228.620000 3376.560000 ;
+ LAYER met3 ;
+ RECT 1236.830000 3365.400000 1237.830000 3365.880000 ;
+ RECT 1236.830000 3370.840000 1237.830000 3371.320000 ;
+ RECT 1227.520000 3370.840000 1228.620000 3371.320000 ;
+ RECT 1227.520000 3365.400000 1228.620000 3365.880000 ;
+ RECT 1182.520000 3365.400000 1183.620000 3365.880000 ;
+ RECT 1182.520000 3370.840000 1183.620000 3371.320000 ;
+ RECT 1092.520000 3365.400000 1093.620000 3365.880000 ;
+ RECT 1137.520000 3365.400000 1138.620000 3365.880000 ;
+ RECT 1137.520000 3370.840000 1138.620000 3371.320000 ;
+ RECT 1092.520000 3370.840000 1093.620000 3371.320000 ;
+ RECT 1043.390000 3365.400000 1044.390000 3365.880000 ;
+ RECT 1047.520000 3365.400000 1048.620000 3365.880000 ;
+ RECT 1047.520000 3370.840000 1048.620000 3371.320000 ;
+ RECT 1043.390000 3370.840000 1044.390000 3371.320000 ;
+ RECT 1236.830000 3354.520000 1237.830000 3355.000000 ;
+ RECT 1236.830000 3359.960000 1237.830000 3360.440000 ;
+ RECT 1227.520000 3359.960000 1228.620000 3360.440000 ;
+ RECT 1227.520000 3354.520000 1228.620000 3355.000000 ;
+ RECT 1182.520000 3354.520000 1183.620000 3355.000000 ;
+ RECT 1182.520000 3359.960000 1183.620000 3360.440000 ;
+ RECT 1092.520000 3354.520000 1093.620000 3355.000000 ;
+ RECT 1137.520000 3354.520000 1138.620000 3355.000000 ;
+ RECT 1137.520000 3359.960000 1138.620000 3360.440000 ;
+ RECT 1092.520000 3359.960000 1093.620000 3360.440000 ;
+ RECT 1043.390000 3359.960000 1044.390000 3360.440000 ;
+ RECT 1047.520000 3359.960000 1048.620000 3360.440000 ;
+ RECT 1043.390000 3354.520000 1044.390000 3355.000000 ;
+ RECT 1047.520000 3354.520000 1048.620000 3355.000000 ;
+ RECT 1040.560000 3375.560000 1240.660000 3376.560000 ;
+ RECT 1040.560000 3352.510000 1240.660000 3353.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 3349.660000 1044.390000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 3378.920000 1044.390000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 3349.660000 1237.830000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 3378.920000 1237.830000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 3352.510000 1041.560000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 3352.510000 1240.660000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 3375.560000 1041.560000 3376.560000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 3375.560000 1240.660000 3376.560000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 1349.910000 1228.620000 1543.280000 ;
+ RECT 1182.520000 1349.910000 1183.620000 1543.280000 ;
+ RECT 1236.830000 1347.060000 1237.830000 1547.320000 ;
+ RECT 1137.520000 1349.910000 1138.620000 1543.280000 ;
+ RECT 1092.520000 1349.910000 1093.620000 1543.280000 ;
+ RECT 1047.520000 1349.910000 1048.620000 1543.280000 ;
+ RECT 1043.390000 1347.060000 1044.390000 1547.320000 ;
+ LAYER met3 ;
+ RECT 1227.520000 1536.880000 1228.620000 1537.360000 ;
+ RECT 1236.830000 1536.880000 1237.830000 1537.360000 ;
+ RECT 1236.830000 1526.000000 1237.830000 1526.480000 ;
+ RECT 1236.830000 1531.440000 1237.830000 1531.920000 ;
+ RECT 1227.520000 1531.440000 1228.620000 1531.920000 ;
+ RECT 1227.520000 1526.000000 1228.620000 1526.480000 ;
+ RECT 1227.520000 1520.560000 1228.620000 1521.040000 ;
+ RECT 1227.520000 1515.120000 1228.620000 1515.600000 ;
+ RECT 1236.830000 1520.560000 1237.830000 1521.040000 ;
+ RECT 1236.830000 1515.120000 1237.830000 1515.600000 ;
+ RECT 1227.520000 1498.800000 1228.620000 1499.280000 ;
+ RECT 1227.520000 1504.240000 1228.620000 1504.720000 ;
+ RECT 1236.830000 1504.240000 1237.830000 1504.720000 ;
+ RECT 1236.830000 1498.800000 1237.830000 1499.280000 ;
+ RECT 1227.520000 1509.680000 1228.620000 1510.160000 ;
+ RECT 1236.830000 1509.680000 1237.830000 1510.160000 ;
+ RECT 1182.520000 1536.880000 1183.620000 1537.360000 ;
+ RECT 1182.520000 1531.440000 1183.620000 1531.920000 ;
+ RECT 1182.520000 1526.000000 1183.620000 1526.480000 ;
+ RECT 1182.520000 1520.560000 1183.620000 1521.040000 ;
+ RECT 1182.520000 1498.800000 1183.620000 1499.280000 ;
+ RECT 1182.520000 1504.240000 1183.620000 1504.720000 ;
+ RECT 1182.520000 1509.680000 1183.620000 1510.160000 ;
+ RECT 1182.520000 1515.120000 1183.620000 1515.600000 ;
+ RECT 1236.830000 1487.920000 1237.830000 1488.400000 ;
+ RECT 1236.830000 1493.360000 1237.830000 1493.840000 ;
+ RECT 1227.520000 1493.360000 1228.620000 1493.840000 ;
+ RECT 1227.520000 1487.920000 1228.620000 1488.400000 ;
+ RECT 1227.520000 1482.480000 1228.620000 1482.960000 ;
+ RECT 1227.520000 1477.040000 1228.620000 1477.520000 ;
+ RECT 1236.830000 1482.480000 1237.830000 1482.960000 ;
+ RECT 1236.830000 1477.040000 1237.830000 1477.520000 ;
+ RECT 1236.830000 1460.720000 1237.830000 1461.200000 ;
+ RECT 1236.830000 1466.160000 1237.830000 1466.640000 ;
+ RECT 1236.830000 1471.600000 1237.830000 1472.080000 ;
+ RECT 1227.520000 1466.160000 1228.620000 1466.640000 ;
+ RECT 1227.520000 1460.720000 1228.620000 1461.200000 ;
+ RECT 1227.520000 1471.600000 1228.620000 1472.080000 ;
+ RECT 1227.520000 1455.280000 1228.620000 1455.760000 ;
+ RECT 1227.520000 1449.840000 1228.620000 1450.320000 ;
+ RECT 1236.830000 1455.280000 1237.830000 1455.760000 ;
+ RECT 1236.830000 1449.840000 1237.830000 1450.320000 ;
+ RECT 1182.520000 1493.360000 1183.620000 1493.840000 ;
+ RECT 1182.520000 1487.920000 1183.620000 1488.400000 ;
+ RECT 1182.520000 1482.480000 1183.620000 1482.960000 ;
+ RECT 1182.520000 1477.040000 1183.620000 1477.520000 ;
+ RECT 1182.520000 1466.160000 1183.620000 1466.640000 ;
+ RECT 1182.520000 1460.720000 1183.620000 1461.200000 ;
+ RECT 1182.520000 1455.280000 1183.620000 1455.760000 ;
+ RECT 1182.520000 1449.840000 1183.620000 1450.320000 ;
+ RECT 1182.520000 1471.600000 1183.620000 1472.080000 ;
+ RECT 1137.520000 1536.880000 1138.620000 1537.360000 ;
+ RECT 1137.520000 1531.440000 1138.620000 1531.920000 ;
+ RECT 1137.520000 1526.000000 1138.620000 1526.480000 ;
+ RECT 1092.520000 1536.880000 1093.620000 1537.360000 ;
+ RECT 1092.520000 1531.440000 1093.620000 1531.920000 ;
+ RECT 1092.520000 1526.000000 1093.620000 1526.480000 ;
+ RECT 1137.520000 1509.680000 1138.620000 1510.160000 ;
+ RECT 1137.520000 1504.240000 1138.620000 1504.720000 ;
+ RECT 1137.520000 1498.800000 1138.620000 1499.280000 ;
+ RECT 1137.520000 1515.120000 1138.620000 1515.600000 ;
+ RECT 1137.520000 1520.560000 1138.620000 1521.040000 ;
+ RECT 1092.520000 1520.560000 1093.620000 1521.040000 ;
+ RECT 1092.520000 1509.680000 1093.620000 1510.160000 ;
+ RECT 1092.520000 1504.240000 1093.620000 1504.720000 ;
+ RECT 1092.520000 1498.800000 1093.620000 1499.280000 ;
+ RECT 1092.520000 1515.120000 1093.620000 1515.600000 ;
+ RECT 1047.520000 1536.880000 1048.620000 1537.360000 ;
+ RECT 1043.390000 1536.880000 1044.390000 1537.360000 ;
+ RECT 1043.390000 1531.440000 1044.390000 1531.920000 ;
+ RECT 1047.520000 1531.440000 1048.620000 1531.920000 ;
+ RECT 1047.520000 1526.000000 1048.620000 1526.480000 ;
+ RECT 1043.390000 1526.000000 1044.390000 1526.480000 ;
+ RECT 1047.520000 1520.560000 1048.620000 1521.040000 ;
+ RECT 1043.390000 1520.560000 1044.390000 1521.040000 ;
+ RECT 1047.520000 1515.120000 1048.620000 1515.600000 ;
+ RECT 1043.390000 1515.120000 1044.390000 1515.600000 ;
+ RECT 1047.520000 1504.240000 1048.620000 1504.720000 ;
+ RECT 1043.390000 1504.240000 1044.390000 1504.720000 ;
+ RECT 1047.520000 1498.800000 1048.620000 1499.280000 ;
+ RECT 1043.390000 1498.800000 1044.390000 1499.280000 ;
+ RECT 1047.520000 1509.680000 1048.620000 1510.160000 ;
+ RECT 1043.390000 1509.680000 1044.390000 1510.160000 ;
+ RECT 1137.520000 1493.360000 1138.620000 1493.840000 ;
+ RECT 1137.520000 1487.920000 1138.620000 1488.400000 ;
+ RECT 1137.520000 1482.480000 1138.620000 1482.960000 ;
+ RECT 1137.520000 1477.040000 1138.620000 1477.520000 ;
+ RECT 1092.520000 1493.360000 1093.620000 1493.840000 ;
+ RECT 1092.520000 1487.920000 1093.620000 1488.400000 ;
+ RECT 1092.520000 1482.480000 1093.620000 1482.960000 ;
+ RECT 1092.520000 1477.040000 1093.620000 1477.520000 ;
+ RECT 1137.520000 1466.160000 1138.620000 1466.640000 ;
+ RECT 1137.520000 1449.840000 1138.620000 1450.320000 ;
+ RECT 1137.520000 1455.280000 1138.620000 1455.760000 ;
+ RECT 1137.520000 1460.720000 1138.620000 1461.200000 ;
+ RECT 1137.520000 1471.600000 1138.620000 1472.080000 ;
+ RECT 1092.520000 1449.840000 1093.620000 1450.320000 ;
+ RECT 1092.520000 1455.280000 1093.620000 1455.760000 ;
+ RECT 1092.520000 1460.720000 1093.620000 1461.200000 ;
+ RECT 1092.520000 1466.160000 1093.620000 1466.640000 ;
+ RECT 1092.520000 1471.600000 1093.620000 1472.080000 ;
+ RECT 1047.520000 1493.360000 1048.620000 1493.840000 ;
+ RECT 1043.390000 1493.360000 1044.390000 1493.840000 ;
+ RECT 1047.520000 1487.920000 1048.620000 1488.400000 ;
+ RECT 1043.390000 1487.920000 1044.390000 1488.400000 ;
+ RECT 1047.520000 1482.480000 1048.620000 1482.960000 ;
+ RECT 1043.390000 1482.480000 1044.390000 1482.960000 ;
+ RECT 1047.520000 1477.040000 1048.620000 1477.520000 ;
+ RECT 1043.390000 1477.040000 1044.390000 1477.520000 ;
+ RECT 1047.520000 1471.600000 1048.620000 1472.080000 ;
+ RECT 1047.520000 1466.160000 1048.620000 1466.640000 ;
+ RECT 1043.390000 1471.600000 1044.390000 1472.080000 ;
+ RECT 1043.390000 1466.160000 1044.390000 1466.640000 ;
+ RECT 1047.520000 1460.720000 1048.620000 1461.200000 ;
+ RECT 1043.390000 1460.720000 1044.390000 1461.200000 ;
+ RECT 1047.520000 1455.280000 1048.620000 1455.760000 ;
+ RECT 1043.390000 1455.280000 1044.390000 1455.760000 ;
+ RECT 1047.520000 1449.840000 1048.620000 1450.320000 ;
+ RECT 1043.390000 1449.840000 1044.390000 1450.320000 ;
+ RECT 1227.520000 1444.400000 1228.620000 1444.880000 ;
+ RECT 1227.520000 1438.960000 1228.620000 1439.440000 ;
+ RECT 1236.830000 1444.400000 1237.830000 1444.880000 ;
+ RECT 1236.830000 1438.960000 1237.830000 1439.440000 ;
+ RECT 1236.830000 1422.640000 1237.830000 1423.120000 ;
+ RECT 1236.830000 1428.080000 1237.830000 1428.560000 ;
+ RECT 1236.830000 1433.520000 1237.830000 1434.000000 ;
+ RECT 1227.520000 1433.520000 1228.620000 1434.000000 ;
+ RECT 1227.520000 1428.080000 1228.620000 1428.560000 ;
+ RECT 1227.520000 1422.640000 1228.620000 1423.120000 ;
+ RECT 1227.520000 1411.760000 1228.620000 1412.240000 ;
+ RECT 1227.520000 1417.200000 1228.620000 1417.680000 ;
+ RECT 1236.830000 1417.200000 1237.830000 1417.680000 ;
+ RECT 1236.830000 1411.760000 1237.830000 1412.240000 ;
+ RECT 1236.830000 1400.880000 1237.830000 1401.360000 ;
+ RECT 1236.830000 1406.320000 1237.830000 1406.800000 ;
+ RECT 1227.520000 1400.880000 1228.620000 1401.360000 ;
+ RECT 1227.520000 1406.320000 1228.620000 1406.800000 ;
+ RECT 1182.520000 1444.400000 1183.620000 1444.880000 ;
+ RECT 1182.520000 1438.960000 1183.620000 1439.440000 ;
+ RECT 1182.520000 1433.520000 1183.620000 1434.000000 ;
+ RECT 1182.520000 1428.080000 1183.620000 1428.560000 ;
+ RECT 1182.520000 1422.640000 1183.620000 1423.120000 ;
+ RECT 1182.520000 1400.880000 1183.620000 1401.360000 ;
+ RECT 1182.520000 1406.320000 1183.620000 1406.800000 ;
+ RECT 1182.520000 1411.760000 1183.620000 1412.240000 ;
+ RECT 1182.520000 1417.200000 1183.620000 1417.680000 ;
+ RECT 1227.520000 1395.440000 1228.620000 1395.920000 ;
+ RECT 1227.520000 1390.000000 1228.620000 1390.480000 ;
+ RECT 1236.830000 1395.440000 1237.830000 1395.920000 ;
+ RECT 1236.830000 1390.000000 1237.830000 1390.480000 ;
+ RECT 1227.520000 1379.120000 1228.620000 1379.600000 ;
+ RECT 1227.520000 1373.680000 1228.620000 1374.160000 ;
+ RECT 1236.830000 1379.120000 1237.830000 1379.600000 ;
+ RECT 1236.830000 1373.680000 1237.830000 1374.160000 ;
+ RECT 1227.520000 1384.560000 1228.620000 1385.040000 ;
+ RECT 1236.830000 1384.560000 1237.830000 1385.040000 ;
+ RECT 1236.830000 1362.800000 1237.830000 1363.280000 ;
+ RECT 1236.830000 1368.240000 1237.830000 1368.720000 ;
+ RECT 1227.520000 1368.240000 1228.620000 1368.720000 ;
+ RECT 1227.520000 1362.800000 1228.620000 1363.280000 ;
+ RECT 1227.520000 1357.360000 1228.620000 1357.840000 ;
+ RECT 1227.520000 1351.920000 1228.620000 1352.400000 ;
+ RECT 1236.830000 1357.360000 1237.830000 1357.840000 ;
+ RECT 1236.830000 1351.920000 1237.830000 1352.400000 ;
+ RECT 1182.520000 1395.440000 1183.620000 1395.920000 ;
+ RECT 1182.520000 1390.000000 1183.620000 1390.480000 ;
+ RECT 1182.520000 1384.560000 1183.620000 1385.040000 ;
+ RECT 1182.520000 1379.120000 1183.620000 1379.600000 ;
+ RECT 1182.520000 1373.680000 1183.620000 1374.160000 ;
+ RECT 1182.520000 1368.240000 1183.620000 1368.720000 ;
+ RECT 1182.520000 1362.800000 1183.620000 1363.280000 ;
+ RECT 1182.520000 1357.360000 1183.620000 1357.840000 ;
+ RECT 1182.520000 1351.920000 1183.620000 1352.400000 ;
+ RECT 1137.520000 1444.400000 1138.620000 1444.880000 ;
+ RECT 1137.520000 1438.960000 1138.620000 1439.440000 ;
+ RECT 1137.520000 1433.520000 1138.620000 1434.000000 ;
+ RECT 1137.520000 1428.080000 1138.620000 1428.560000 ;
+ RECT 1137.520000 1422.640000 1138.620000 1423.120000 ;
+ RECT 1092.520000 1444.400000 1093.620000 1444.880000 ;
+ RECT 1092.520000 1438.960000 1093.620000 1439.440000 ;
+ RECT 1092.520000 1433.520000 1093.620000 1434.000000 ;
+ RECT 1092.520000 1428.080000 1093.620000 1428.560000 ;
+ RECT 1092.520000 1422.640000 1093.620000 1423.120000 ;
+ RECT 1137.520000 1417.200000 1138.620000 1417.680000 ;
+ RECT 1137.520000 1411.760000 1138.620000 1412.240000 ;
+ RECT 1137.520000 1406.320000 1138.620000 1406.800000 ;
+ RECT 1137.520000 1400.880000 1138.620000 1401.360000 ;
+ RECT 1092.520000 1411.760000 1093.620000 1412.240000 ;
+ RECT 1092.520000 1406.320000 1093.620000 1406.800000 ;
+ RECT 1092.520000 1400.880000 1093.620000 1401.360000 ;
+ RECT 1092.520000 1417.200000 1093.620000 1417.680000 ;
+ RECT 1047.520000 1444.400000 1048.620000 1444.880000 ;
+ RECT 1043.390000 1444.400000 1044.390000 1444.880000 ;
+ RECT 1047.520000 1438.960000 1048.620000 1439.440000 ;
+ RECT 1043.390000 1438.960000 1044.390000 1439.440000 ;
+ RECT 1047.520000 1433.520000 1048.620000 1434.000000 ;
+ RECT 1043.390000 1433.520000 1044.390000 1434.000000 ;
+ RECT 1047.520000 1422.640000 1048.620000 1423.120000 ;
+ RECT 1043.390000 1422.640000 1044.390000 1423.120000 ;
+ RECT 1043.390000 1428.080000 1044.390000 1428.560000 ;
+ RECT 1047.520000 1428.080000 1048.620000 1428.560000 ;
+ RECT 1047.520000 1417.200000 1048.620000 1417.680000 ;
+ RECT 1043.390000 1417.200000 1044.390000 1417.680000 ;
+ RECT 1047.520000 1411.760000 1048.620000 1412.240000 ;
+ RECT 1043.390000 1411.760000 1044.390000 1412.240000 ;
+ RECT 1047.520000 1406.320000 1048.620000 1406.800000 ;
+ RECT 1043.390000 1406.320000 1044.390000 1406.800000 ;
+ RECT 1047.520000 1400.880000 1048.620000 1401.360000 ;
+ RECT 1043.390000 1400.880000 1044.390000 1401.360000 ;
+ RECT 1137.520000 1395.440000 1138.620000 1395.920000 ;
+ RECT 1137.520000 1390.000000 1138.620000 1390.480000 ;
+ RECT 1137.520000 1384.560000 1138.620000 1385.040000 ;
+ RECT 1137.520000 1379.120000 1138.620000 1379.600000 ;
+ RECT 1137.520000 1373.680000 1138.620000 1374.160000 ;
+ RECT 1092.520000 1395.440000 1093.620000 1395.920000 ;
+ RECT 1092.520000 1390.000000 1093.620000 1390.480000 ;
+ RECT 1092.520000 1384.560000 1093.620000 1385.040000 ;
+ RECT 1092.520000 1379.120000 1093.620000 1379.600000 ;
+ RECT 1092.520000 1373.680000 1093.620000 1374.160000 ;
+ RECT 1137.520000 1351.920000 1138.620000 1352.400000 ;
+ RECT 1137.520000 1357.360000 1138.620000 1357.840000 ;
+ RECT 1137.520000 1362.800000 1138.620000 1363.280000 ;
+ RECT 1137.520000 1368.240000 1138.620000 1368.720000 ;
+ RECT 1092.520000 1351.920000 1093.620000 1352.400000 ;
+ RECT 1092.520000 1357.360000 1093.620000 1357.840000 ;
+ RECT 1092.520000 1362.800000 1093.620000 1363.280000 ;
+ RECT 1092.520000 1368.240000 1093.620000 1368.720000 ;
+ RECT 1047.520000 1395.440000 1048.620000 1395.920000 ;
+ RECT 1043.390000 1395.440000 1044.390000 1395.920000 ;
+ RECT 1047.520000 1390.000000 1048.620000 1390.480000 ;
+ RECT 1043.390000 1390.000000 1044.390000 1390.480000 ;
+ RECT 1047.520000 1379.120000 1048.620000 1379.600000 ;
+ RECT 1043.390000 1379.120000 1044.390000 1379.600000 ;
+ RECT 1047.520000 1373.680000 1048.620000 1374.160000 ;
+ RECT 1043.390000 1373.680000 1044.390000 1374.160000 ;
+ RECT 1047.520000 1384.560000 1048.620000 1385.040000 ;
+ RECT 1043.390000 1384.560000 1044.390000 1385.040000 ;
+ RECT 1047.520000 1368.240000 1048.620000 1368.720000 ;
+ RECT 1043.390000 1368.240000 1044.390000 1368.720000 ;
+ RECT 1047.520000 1362.800000 1048.620000 1363.280000 ;
+ RECT 1043.390000 1362.800000 1044.390000 1363.280000 ;
+ RECT 1047.520000 1357.360000 1048.620000 1357.840000 ;
+ RECT 1047.520000 1351.920000 1048.620000 1352.400000 ;
+ RECT 1043.390000 1357.360000 1044.390000 1357.840000 ;
+ RECT 1043.390000 1351.920000 1044.390000 1352.400000 ;
+ RECT 1040.560000 1542.280000 1240.660000 1543.280000 ;
+ RECT 1040.560000 1349.910000 1240.660000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 1347.060000 1044.390000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 1546.320000 1044.390000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 1347.060000 1237.830000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 1546.320000 1237.830000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1349.910000 1041.560000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1349.910000 1240.660000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1542.280000 1041.560000 1543.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1542.280000 1240.660000 1543.280000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 1149.650000 1228.620000 1343.020000 ;
+ RECT 1182.520000 1149.650000 1183.620000 1343.020000 ;
+ RECT 1236.830000 1146.800000 1237.830000 1347.060000 ;
+ RECT 1137.520000 1149.650000 1138.620000 1343.020000 ;
+ RECT 1092.520000 1149.650000 1093.620000 1343.020000 ;
+ RECT 1047.520000 1149.650000 1048.620000 1343.020000 ;
+ RECT 1043.390000 1146.800000 1044.390000 1347.060000 ;
+ LAYER met3 ;
+ RECT 1227.520000 1336.620000 1228.620000 1337.100000 ;
+ RECT 1236.830000 1336.620000 1237.830000 1337.100000 ;
+ RECT 1236.830000 1325.740000 1237.830000 1326.220000 ;
+ RECT 1236.830000 1331.180000 1237.830000 1331.660000 ;
+ RECT 1227.520000 1331.180000 1228.620000 1331.660000 ;
+ RECT 1227.520000 1325.740000 1228.620000 1326.220000 ;
+ RECT 1227.520000 1320.300000 1228.620000 1320.780000 ;
+ RECT 1227.520000 1314.860000 1228.620000 1315.340000 ;
+ RECT 1236.830000 1320.300000 1237.830000 1320.780000 ;
+ RECT 1236.830000 1314.860000 1237.830000 1315.340000 ;
+ RECT 1227.520000 1298.540000 1228.620000 1299.020000 ;
+ RECT 1227.520000 1303.980000 1228.620000 1304.460000 ;
+ RECT 1236.830000 1303.980000 1237.830000 1304.460000 ;
+ RECT 1236.830000 1298.540000 1237.830000 1299.020000 ;
+ RECT 1227.520000 1309.420000 1228.620000 1309.900000 ;
+ RECT 1236.830000 1309.420000 1237.830000 1309.900000 ;
+ RECT 1182.520000 1336.620000 1183.620000 1337.100000 ;
+ RECT 1182.520000 1331.180000 1183.620000 1331.660000 ;
+ RECT 1182.520000 1325.740000 1183.620000 1326.220000 ;
+ RECT 1182.520000 1320.300000 1183.620000 1320.780000 ;
+ RECT 1182.520000 1298.540000 1183.620000 1299.020000 ;
+ RECT 1182.520000 1303.980000 1183.620000 1304.460000 ;
+ RECT 1182.520000 1309.420000 1183.620000 1309.900000 ;
+ RECT 1182.520000 1314.860000 1183.620000 1315.340000 ;
+ RECT 1236.830000 1287.660000 1237.830000 1288.140000 ;
+ RECT 1236.830000 1293.100000 1237.830000 1293.580000 ;
+ RECT 1227.520000 1293.100000 1228.620000 1293.580000 ;
+ RECT 1227.520000 1287.660000 1228.620000 1288.140000 ;
+ RECT 1227.520000 1282.220000 1228.620000 1282.700000 ;
+ RECT 1227.520000 1276.780000 1228.620000 1277.260000 ;
+ RECT 1236.830000 1282.220000 1237.830000 1282.700000 ;
+ RECT 1236.830000 1276.780000 1237.830000 1277.260000 ;
+ RECT 1236.830000 1260.460000 1237.830000 1260.940000 ;
+ RECT 1236.830000 1265.900000 1237.830000 1266.380000 ;
+ RECT 1236.830000 1271.340000 1237.830000 1271.820000 ;
+ RECT 1227.520000 1265.900000 1228.620000 1266.380000 ;
+ RECT 1227.520000 1260.460000 1228.620000 1260.940000 ;
+ RECT 1227.520000 1271.340000 1228.620000 1271.820000 ;
+ RECT 1227.520000 1255.020000 1228.620000 1255.500000 ;
+ RECT 1227.520000 1249.580000 1228.620000 1250.060000 ;
+ RECT 1236.830000 1255.020000 1237.830000 1255.500000 ;
+ RECT 1236.830000 1249.580000 1237.830000 1250.060000 ;
+ RECT 1182.520000 1293.100000 1183.620000 1293.580000 ;
+ RECT 1182.520000 1287.660000 1183.620000 1288.140000 ;
+ RECT 1182.520000 1282.220000 1183.620000 1282.700000 ;
+ RECT 1182.520000 1276.780000 1183.620000 1277.260000 ;
+ RECT 1182.520000 1265.900000 1183.620000 1266.380000 ;
+ RECT 1182.520000 1260.460000 1183.620000 1260.940000 ;
+ RECT 1182.520000 1255.020000 1183.620000 1255.500000 ;
+ RECT 1182.520000 1249.580000 1183.620000 1250.060000 ;
+ RECT 1182.520000 1271.340000 1183.620000 1271.820000 ;
+ RECT 1137.520000 1336.620000 1138.620000 1337.100000 ;
+ RECT 1137.520000 1331.180000 1138.620000 1331.660000 ;
+ RECT 1137.520000 1325.740000 1138.620000 1326.220000 ;
+ RECT 1092.520000 1336.620000 1093.620000 1337.100000 ;
+ RECT 1092.520000 1331.180000 1093.620000 1331.660000 ;
+ RECT 1092.520000 1325.740000 1093.620000 1326.220000 ;
+ RECT 1137.520000 1309.420000 1138.620000 1309.900000 ;
+ RECT 1137.520000 1303.980000 1138.620000 1304.460000 ;
+ RECT 1137.520000 1298.540000 1138.620000 1299.020000 ;
+ RECT 1137.520000 1314.860000 1138.620000 1315.340000 ;
+ RECT 1137.520000 1320.300000 1138.620000 1320.780000 ;
+ RECT 1092.520000 1320.300000 1093.620000 1320.780000 ;
+ RECT 1092.520000 1309.420000 1093.620000 1309.900000 ;
+ RECT 1092.520000 1303.980000 1093.620000 1304.460000 ;
+ RECT 1092.520000 1298.540000 1093.620000 1299.020000 ;
+ RECT 1092.520000 1314.860000 1093.620000 1315.340000 ;
+ RECT 1047.520000 1336.620000 1048.620000 1337.100000 ;
+ RECT 1043.390000 1336.620000 1044.390000 1337.100000 ;
+ RECT 1043.390000 1331.180000 1044.390000 1331.660000 ;
+ RECT 1047.520000 1331.180000 1048.620000 1331.660000 ;
+ RECT 1047.520000 1325.740000 1048.620000 1326.220000 ;
+ RECT 1043.390000 1325.740000 1044.390000 1326.220000 ;
+ RECT 1047.520000 1320.300000 1048.620000 1320.780000 ;
+ RECT 1043.390000 1320.300000 1044.390000 1320.780000 ;
+ RECT 1047.520000 1314.860000 1048.620000 1315.340000 ;
+ RECT 1043.390000 1314.860000 1044.390000 1315.340000 ;
+ RECT 1047.520000 1303.980000 1048.620000 1304.460000 ;
+ RECT 1043.390000 1303.980000 1044.390000 1304.460000 ;
+ RECT 1047.520000 1298.540000 1048.620000 1299.020000 ;
+ RECT 1043.390000 1298.540000 1044.390000 1299.020000 ;
+ RECT 1047.520000 1309.420000 1048.620000 1309.900000 ;
+ RECT 1043.390000 1309.420000 1044.390000 1309.900000 ;
+ RECT 1137.520000 1293.100000 1138.620000 1293.580000 ;
+ RECT 1137.520000 1287.660000 1138.620000 1288.140000 ;
+ RECT 1137.520000 1282.220000 1138.620000 1282.700000 ;
+ RECT 1137.520000 1276.780000 1138.620000 1277.260000 ;
+ RECT 1092.520000 1293.100000 1093.620000 1293.580000 ;
+ RECT 1092.520000 1287.660000 1093.620000 1288.140000 ;
+ RECT 1092.520000 1282.220000 1093.620000 1282.700000 ;
+ RECT 1092.520000 1276.780000 1093.620000 1277.260000 ;
+ RECT 1137.520000 1265.900000 1138.620000 1266.380000 ;
+ RECT 1137.520000 1249.580000 1138.620000 1250.060000 ;
+ RECT 1137.520000 1255.020000 1138.620000 1255.500000 ;
+ RECT 1137.520000 1260.460000 1138.620000 1260.940000 ;
+ RECT 1137.520000 1271.340000 1138.620000 1271.820000 ;
+ RECT 1092.520000 1249.580000 1093.620000 1250.060000 ;
+ RECT 1092.520000 1255.020000 1093.620000 1255.500000 ;
+ RECT 1092.520000 1260.460000 1093.620000 1260.940000 ;
+ RECT 1092.520000 1265.900000 1093.620000 1266.380000 ;
+ RECT 1092.520000 1271.340000 1093.620000 1271.820000 ;
+ RECT 1047.520000 1293.100000 1048.620000 1293.580000 ;
+ RECT 1043.390000 1293.100000 1044.390000 1293.580000 ;
+ RECT 1047.520000 1287.660000 1048.620000 1288.140000 ;
+ RECT 1043.390000 1287.660000 1044.390000 1288.140000 ;
+ RECT 1047.520000 1282.220000 1048.620000 1282.700000 ;
+ RECT 1043.390000 1282.220000 1044.390000 1282.700000 ;
+ RECT 1047.520000 1276.780000 1048.620000 1277.260000 ;
+ RECT 1043.390000 1276.780000 1044.390000 1277.260000 ;
+ RECT 1047.520000 1271.340000 1048.620000 1271.820000 ;
+ RECT 1047.520000 1265.900000 1048.620000 1266.380000 ;
+ RECT 1043.390000 1271.340000 1044.390000 1271.820000 ;
+ RECT 1043.390000 1265.900000 1044.390000 1266.380000 ;
+ RECT 1047.520000 1260.460000 1048.620000 1260.940000 ;
+ RECT 1043.390000 1260.460000 1044.390000 1260.940000 ;
+ RECT 1047.520000 1255.020000 1048.620000 1255.500000 ;
+ RECT 1043.390000 1255.020000 1044.390000 1255.500000 ;
+ RECT 1047.520000 1249.580000 1048.620000 1250.060000 ;
+ RECT 1043.390000 1249.580000 1044.390000 1250.060000 ;
+ RECT 1227.520000 1244.140000 1228.620000 1244.620000 ;
+ RECT 1227.520000 1238.700000 1228.620000 1239.180000 ;
+ RECT 1236.830000 1244.140000 1237.830000 1244.620000 ;
+ RECT 1236.830000 1238.700000 1237.830000 1239.180000 ;
+ RECT 1236.830000 1222.380000 1237.830000 1222.860000 ;
+ RECT 1236.830000 1227.820000 1237.830000 1228.300000 ;
+ RECT 1236.830000 1233.260000 1237.830000 1233.740000 ;
+ RECT 1227.520000 1233.260000 1228.620000 1233.740000 ;
+ RECT 1227.520000 1227.820000 1228.620000 1228.300000 ;
+ RECT 1227.520000 1222.380000 1228.620000 1222.860000 ;
+ RECT 1227.520000 1211.500000 1228.620000 1211.980000 ;
+ RECT 1227.520000 1216.940000 1228.620000 1217.420000 ;
+ RECT 1236.830000 1216.940000 1237.830000 1217.420000 ;
+ RECT 1236.830000 1211.500000 1237.830000 1211.980000 ;
+ RECT 1236.830000 1200.620000 1237.830000 1201.100000 ;
+ RECT 1236.830000 1206.060000 1237.830000 1206.540000 ;
+ RECT 1227.520000 1200.620000 1228.620000 1201.100000 ;
+ RECT 1227.520000 1206.060000 1228.620000 1206.540000 ;
+ RECT 1182.520000 1244.140000 1183.620000 1244.620000 ;
+ RECT 1182.520000 1238.700000 1183.620000 1239.180000 ;
+ RECT 1182.520000 1233.260000 1183.620000 1233.740000 ;
+ RECT 1182.520000 1227.820000 1183.620000 1228.300000 ;
+ RECT 1182.520000 1222.380000 1183.620000 1222.860000 ;
+ RECT 1182.520000 1200.620000 1183.620000 1201.100000 ;
+ RECT 1182.520000 1206.060000 1183.620000 1206.540000 ;
+ RECT 1182.520000 1211.500000 1183.620000 1211.980000 ;
+ RECT 1182.520000 1216.940000 1183.620000 1217.420000 ;
+ RECT 1227.520000 1195.180000 1228.620000 1195.660000 ;
+ RECT 1227.520000 1189.740000 1228.620000 1190.220000 ;
+ RECT 1236.830000 1195.180000 1237.830000 1195.660000 ;
+ RECT 1236.830000 1189.740000 1237.830000 1190.220000 ;
+ RECT 1227.520000 1178.860000 1228.620000 1179.340000 ;
+ RECT 1227.520000 1173.420000 1228.620000 1173.900000 ;
+ RECT 1236.830000 1178.860000 1237.830000 1179.340000 ;
+ RECT 1236.830000 1173.420000 1237.830000 1173.900000 ;
+ RECT 1227.520000 1184.300000 1228.620000 1184.780000 ;
+ RECT 1236.830000 1184.300000 1237.830000 1184.780000 ;
+ RECT 1236.830000 1162.540000 1237.830000 1163.020000 ;
+ RECT 1236.830000 1167.980000 1237.830000 1168.460000 ;
+ RECT 1227.520000 1167.980000 1228.620000 1168.460000 ;
+ RECT 1227.520000 1162.540000 1228.620000 1163.020000 ;
+ RECT 1227.520000 1157.100000 1228.620000 1157.580000 ;
+ RECT 1227.520000 1151.660000 1228.620000 1152.140000 ;
+ RECT 1236.830000 1157.100000 1237.830000 1157.580000 ;
+ RECT 1236.830000 1151.660000 1237.830000 1152.140000 ;
+ RECT 1182.520000 1195.180000 1183.620000 1195.660000 ;
+ RECT 1182.520000 1189.740000 1183.620000 1190.220000 ;
+ RECT 1182.520000 1184.300000 1183.620000 1184.780000 ;
+ RECT 1182.520000 1178.860000 1183.620000 1179.340000 ;
+ RECT 1182.520000 1173.420000 1183.620000 1173.900000 ;
+ RECT 1182.520000 1167.980000 1183.620000 1168.460000 ;
+ RECT 1182.520000 1162.540000 1183.620000 1163.020000 ;
+ RECT 1182.520000 1157.100000 1183.620000 1157.580000 ;
+ RECT 1182.520000 1151.660000 1183.620000 1152.140000 ;
+ RECT 1137.520000 1244.140000 1138.620000 1244.620000 ;
+ RECT 1137.520000 1238.700000 1138.620000 1239.180000 ;
+ RECT 1137.520000 1233.260000 1138.620000 1233.740000 ;
+ RECT 1137.520000 1227.820000 1138.620000 1228.300000 ;
+ RECT 1137.520000 1222.380000 1138.620000 1222.860000 ;
+ RECT 1092.520000 1244.140000 1093.620000 1244.620000 ;
+ RECT 1092.520000 1238.700000 1093.620000 1239.180000 ;
+ RECT 1092.520000 1233.260000 1093.620000 1233.740000 ;
+ RECT 1092.520000 1227.820000 1093.620000 1228.300000 ;
+ RECT 1092.520000 1222.380000 1093.620000 1222.860000 ;
+ RECT 1137.520000 1216.940000 1138.620000 1217.420000 ;
+ RECT 1137.520000 1211.500000 1138.620000 1211.980000 ;
+ RECT 1137.520000 1206.060000 1138.620000 1206.540000 ;
+ RECT 1137.520000 1200.620000 1138.620000 1201.100000 ;
+ RECT 1092.520000 1211.500000 1093.620000 1211.980000 ;
+ RECT 1092.520000 1206.060000 1093.620000 1206.540000 ;
+ RECT 1092.520000 1200.620000 1093.620000 1201.100000 ;
+ RECT 1092.520000 1216.940000 1093.620000 1217.420000 ;
+ RECT 1047.520000 1244.140000 1048.620000 1244.620000 ;
+ RECT 1043.390000 1244.140000 1044.390000 1244.620000 ;
+ RECT 1047.520000 1238.700000 1048.620000 1239.180000 ;
+ RECT 1043.390000 1238.700000 1044.390000 1239.180000 ;
+ RECT 1047.520000 1233.260000 1048.620000 1233.740000 ;
+ RECT 1043.390000 1233.260000 1044.390000 1233.740000 ;
+ RECT 1047.520000 1222.380000 1048.620000 1222.860000 ;
+ RECT 1043.390000 1222.380000 1044.390000 1222.860000 ;
+ RECT 1043.390000 1227.820000 1044.390000 1228.300000 ;
+ RECT 1047.520000 1227.820000 1048.620000 1228.300000 ;
+ RECT 1047.520000 1216.940000 1048.620000 1217.420000 ;
+ RECT 1043.390000 1216.940000 1044.390000 1217.420000 ;
+ RECT 1047.520000 1211.500000 1048.620000 1211.980000 ;
+ RECT 1043.390000 1211.500000 1044.390000 1211.980000 ;
+ RECT 1047.520000 1206.060000 1048.620000 1206.540000 ;
+ RECT 1043.390000 1206.060000 1044.390000 1206.540000 ;
+ RECT 1047.520000 1200.620000 1048.620000 1201.100000 ;
+ RECT 1043.390000 1200.620000 1044.390000 1201.100000 ;
+ RECT 1137.520000 1195.180000 1138.620000 1195.660000 ;
+ RECT 1137.520000 1189.740000 1138.620000 1190.220000 ;
+ RECT 1137.520000 1184.300000 1138.620000 1184.780000 ;
+ RECT 1137.520000 1178.860000 1138.620000 1179.340000 ;
+ RECT 1137.520000 1173.420000 1138.620000 1173.900000 ;
+ RECT 1092.520000 1195.180000 1093.620000 1195.660000 ;
+ RECT 1092.520000 1189.740000 1093.620000 1190.220000 ;
+ RECT 1092.520000 1184.300000 1093.620000 1184.780000 ;
+ RECT 1092.520000 1178.860000 1093.620000 1179.340000 ;
+ RECT 1092.520000 1173.420000 1093.620000 1173.900000 ;
+ RECT 1137.520000 1151.660000 1138.620000 1152.140000 ;
+ RECT 1137.520000 1157.100000 1138.620000 1157.580000 ;
+ RECT 1137.520000 1162.540000 1138.620000 1163.020000 ;
+ RECT 1137.520000 1167.980000 1138.620000 1168.460000 ;
+ RECT 1092.520000 1151.660000 1093.620000 1152.140000 ;
+ RECT 1092.520000 1157.100000 1093.620000 1157.580000 ;
+ RECT 1092.520000 1162.540000 1093.620000 1163.020000 ;
+ RECT 1092.520000 1167.980000 1093.620000 1168.460000 ;
+ RECT 1047.520000 1195.180000 1048.620000 1195.660000 ;
+ RECT 1043.390000 1195.180000 1044.390000 1195.660000 ;
+ RECT 1047.520000 1189.740000 1048.620000 1190.220000 ;
+ RECT 1043.390000 1189.740000 1044.390000 1190.220000 ;
+ RECT 1047.520000 1178.860000 1048.620000 1179.340000 ;
+ RECT 1043.390000 1178.860000 1044.390000 1179.340000 ;
+ RECT 1047.520000 1173.420000 1048.620000 1173.900000 ;
+ RECT 1043.390000 1173.420000 1044.390000 1173.900000 ;
+ RECT 1047.520000 1184.300000 1048.620000 1184.780000 ;
+ RECT 1043.390000 1184.300000 1044.390000 1184.780000 ;
+ RECT 1047.520000 1167.980000 1048.620000 1168.460000 ;
+ RECT 1043.390000 1167.980000 1044.390000 1168.460000 ;
+ RECT 1047.520000 1162.540000 1048.620000 1163.020000 ;
+ RECT 1043.390000 1162.540000 1044.390000 1163.020000 ;
+ RECT 1047.520000 1157.100000 1048.620000 1157.580000 ;
+ RECT 1047.520000 1151.660000 1048.620000 1152.140000 ;
+ RECT 1043.390000 1157.100000 1044.390000 1157.580000 ;
+ RECT 1043.390000 1151.660000 1044.390000 1152.140000 ;
+ RECT 1040.560000 1342.020000 1240.660000 1343.020000 ;
+ RECT 1040.560000 1149.650000 1240.660000 1150.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 1146.800000 1044.390000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 1346.060000 1044.390000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 1146.800000 1237.830000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 1346.060000 1237.830000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1149.650000 1041.560000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1149.650000 1240.660000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1342.020000 1041.560000 1343.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1342.020000 1240.660000 1343.020000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 949.390000 1228.620000 1142.760000 ;
+ RECT 1182.520000 949.390000 1183.620000 1142.760000 ;
+ RECT 1236.830000 946.540000 1237.830000 1146.800000 ;
+ RECT 1137.520000 949.390000 1138.620000 1142.760000 ;
+ RECT 1092.520000 949.390000 1093.620000 1142.760000 ;
+ RECT 1047.520000 949.390000 1048.620000 1142.760000 ;
+ RECT 1043.390000 946.540000 1044.390000 1146.800000 ;
+ LAYER met3 ;
+ RECT 1227.520000 1136.360000 1228.620000 1136.840000 ;
+ RECT 1236.830000 1136.360000 1237.830000 1136.840000 ;
+ RECT 1236.830000 1125.480000 1237.830000 1125.960000 ;
+ RECT 1236.830000 1130.920000 1237.830000 1131.400000 ;
+ RECT 1227.520000 1130.920000 1228.620000 1131.400000 ;
+ RECT 1227.520000 1125.480000 1228.620000 1125.960000 ;
+ RECT 1227.520000 1120.040000 1228.620000 1120.520000 ;
+ RECT 1227.520000 1114.600000 1228.620000 1115.080000 ;
+ RECT 1236.830000 1120.040000 1237.830000 1120.520000 ;
+ RECT 1236.830000 1114.600000 1237.830000 1115.080000 ;
+ RECT 1227.520000 1098.280000 1228.620000 1098.760000 ;
+ RECT 1227.520000 1103.720000 1228.620000 1104.200000 ;
+ RECT 1236.830000 1103.720000 1237.830000 1104.200000 ;
+ RECT 1236.830000 1098.280000 1237.830000 1098.760000 ;
+ RECT 1227.520000 1109.160000 1228.620000 1109.640000 ;
+ RECT 1236.830000 1109.160000 1237.830000 1109.640000 ;
+ RECT 1182.520000 1136.360000 1183.620000 1136.840000 ;
+ RECT 1182.520000 1130.920000 1183.620000 1131.400000 ;
+ RECT 1182.520000 1125.480000 1183.620000 1125.960000 ;
+ RECT 1182.520000 1120.040000 1183.620000 1120.520000 ;
+ RECT 1182.520000 1098.280000 1183.620000 1098.760000 ;
+ RECT 1182.520000 1103.720000 1183.620000 1104.200000 ;
+ RECT 1182.520000 1109.160000 1183.620000 1109.640000 ;
+ RECT 1182.520000 1114.600000 1183.620000 1115.080000 ;
+ RECT 1236.830000 1087.400000 1237.830000 1087.880000 ;
+ RECT 1236.830000 1092.840000 1237.830000 1093.320000 ;
+ RECT 1227.520000 1092.840000 1228.620000 1093.320000 ;
+ RECT 1227.520000 1087.400000 1228.620000 1087.880000 ;
+ RECT 1227.520000 1081.960000 1228.620000 1082.440000 ;
+ RECT 1227.520000 1076.520000 1228.620000 1077.000000 ;
+ RECT 1236.830000 1081.960000 1237.830000 1082.440000 ;
+ RECT 1236.830000 1076.520000 1237.830000 1077.000000 ;
+ RECT 1236.830000 1060.200000 1237.830000 1060.680000 ;
+ RECT 1236.830000 1065.640000 1237.830000 1066.120000 ;
+ RECT 1236.830000 1071.080000 1237.830000 1071.560000 ;
+ RECT 1227.520000 1065.640000 1228.620000 1066.120000 ;
+ RECT 1227.520000 1060.200000 1228.620000 1060.680000 ;
+ RECT 1227.520000 1071.080000 1228.620000 1071.560000 ;
+ RECT 1227.520000 1054.760000 1228.620000 1055.240000 ;
+ RECT 1227.520000 1049.320000 1228.620000 1049.800000 ;
+ RECT 1236.830000 1054.760000 1237.830000 1055.240000 ;
+ RECT 1236.830000 1049.320000 1237.830000 1049.800000 ;
+ RECT 1182.520000 1092.840000 1183.620000 1093.320000 ;
+ RECT 1182.520000 1087.400000 1183.620000 1087.880000 ;
+ RECT 1182.520000 1081.960000 1183.620000 1082.440000 ;
+ RECT 1182.520000 1076.520000 1183.620000 1077.000000 ;
+ RECT 1182.520000 1065.640000 1183.620000 1066.120000 ;
+ RECT 1182.520000 1060.200000 1183.620000 1060.680000 ;
+ RECT 1182.520000 1054.760000 1183.620000 1055.240000 ;
+ RECT 1182.520000 1049.320000 1183.620000 1049.800000 ;
+ RECT 1182.520000 1071.080000 1183.620000 1071.560000 ;
+ RECT 1137.520000 1136.360000 1138.620000 1136.840000 ;
+ RECT 1137.520000 1130.920000 1138.620000 1131.400000 ;
+ RECT 1137.520000 1125.480000 1138.620000 1125.960000 ;
+ RECT 1092.520000 1136.360000 1093.620000 1136.840000 ;
+ RECT 1092.520000 1130.920000 1093.620000 1131.400000 ;
+ RECT 1092.520000 1125.480000 1093.620000 1125.960000 ;
+ RECT 1137.520000 1109.160000 1138.620000 1109.640000 ;
+ RECT 1137.520000 1103.720000 1138.620000 1104.200000 ;
+ RECT 1137.520000 1098.280000 1138.620000 1098.760000 ;
+ RECT 1137.520000 1114.600000 1138.620000 1115.080000 ;
+ RECT 1137.520000 1120.040000 1138.620000 1120.520000 ;
+ RECT 1092.520000 1120.040000 1093.620000 1120.520000 ;
+ RECT 1092.520000 1109.160000 1093.620000 1109.640000 ;
+ RECT 1092.520000 1103.720000 1093.620000 1104.200000 ;
+ RECT 1092.520000 1098.280000 1093.620000 1098.760000 ;
+ RECT 1092.520000 1114.600000 1093.620000 1115.080000 ;
+ RECT 1047.520000 1136.360000 1048.620000 1136.840000 ;
+ RECT 1043.390000 1136.360000 1044.390000 1136.840000 ;
+ RECT 1043.390000 1130.920000 1044.390000 1131.400000 ;
+ RECT 1047.520000 1130.920000 1048.620000 1131.400000 ;
+ RECT 1047.520000 1125.480000 1048.620000 1125.960000 ;
+ RECT 1043.390000 1125.480000 1044.390000 1125.960000 ;
+ RECT 1047.520000 1120.040000 1048.620000 1120.520000 ;
+ RECT 1043.390000 1120.040000 1044.390000 1120.520000 ;
+ RECT 1047.520000 1114.600000 1048.620000 1115.080000 ;
+ RECT 1043.390000 1114.600000 1044.390000 1115.080000 ;
+ RECT 1047.520000 1103.720000 1048.620000 1104.200000 ;
+ RECT 1043.390000 1103.720000 1044.390000 1104.200000 ;
+ RECT 1047.520000 1098.280000 1048.620000 1098.760000 ;
+ RECT 1043.390000 1098.280000 1044.390000 1098.760000 ;
+ RECT 1047.520000 1109.160000 1048.620000 1109.640000 ;
+ RECT 1043.390000 1109.160000 1044.390000 1109.640000 ;
+ RECT 1137.520000 1092.840000 1138.620000 1093.320000 ;
+ RECT 1137.520000 1087.400000 1138.620000 1087.880000 ;
+ RECT 1137.520000 1081.960000 1138.620000 1082.440000 ;
+ RECT 1137.520000 1076.520000 1138.620000 1077.000000 ;
+ RECT 1092.520000 1092.840000 1093.620000 1093.320000 ;
+ RECT 1092.520000 1087.400000 1093.620000 1087.880000 ;
+ RECT 1092.520000 1081.960000 1093.620000 1082.440000 ;
+ RECT 1092.520000 1076.520000 1093.620000 1077.000000 ;
+ RECT 1137.520000 1065.640000 1138.620000 1066.120000 ;
+ RECT 1137.520000 1049.320000 1138.620000 1049.800000 ;
+ RECT 1137.520000 1054.760000 1138.620000 1055.240000 ;
+ RECT 1137.520000 1060.200000 1138.620000 1060.680000 ;
+ RECT 1137.520000 1071.080000 1138.620000 1071.560000 ;
+ RECT 1092.520000 1049.320000 1093.620000 1049.800000 ;
+ RECT 1092.520000 1054.760000 1093.620000 1055.240000 ;
+ RECT 1092.520000 1060.200000 1093.620000 1060.680000 ;
+ RECT 1092.520000 1065.640000 1093.620000 1066.120000 ;
+ RECT 1092.520000 1071.080000 1093.620000 1071.560000 ;
+ RECT 1047.520000 1092.840000 1048.620000 1093.320000 ;
+ RECT 1043.390000 1092.840000 1044.390000 1093.320000 ;
+ RECT 1047.520000 1087.400000 1048.620000 1087.880000 ;
+ RECT 1043.390000 1087.400000 1044.390000 1087.880000 ;
+ RECT 1047.520000 1081.960000 1048.620000 1082.440000 ;
+ RECT 1043.390000 1081.960000 1044.390000 1082.440000 ;
+ RECT 1047.520000 1076.520000 1048.620000 1077.000000 ;
+ RECT 1043.390000 1076.520000 1044.390000 1077.000000 ;
+ RECT 1047.520000 1071.080000 1048.620000 1071.560000 ;
+ RECT 1047.520000 1065.640000 1048.620000 1066.120000 ;
+ RECT 1043.390000 1071.080000 1044.390000 1071.560000 ;
+ RECT 1043.390000 1065.640000 1044.390000 1066.120000 ;
+ RECT 1047.520000 1060.200000 1048.620000 1060.680000 ;
+ RECT 1043.390000 1060.200000 1044.390000 1060.680000 ;
+ RECT 1047.520000 1054.760000 1048.620000 1055.240000 ;
+ RECT 1043.390000 1054.760000 1044.390000 1055.240000 ;
+ RECT 1047.520000 1049.320000 1048.620000 1049.800000 ;
+ RECT 1043.390000 1049.320000 1044.390000 1049.800000 ;
+ RECT 1227.520000 1043.880000 1228.620000 1044.360000 ;
+ RECT 1227.520000 1038.440000 1228.620000 1038.920000 ;
+ RECT 1236.830000 1043.880000 1237.830000 1044.360000 ;
+ RECT 1236.830000 1038.440000 1237.830000 1038.920000 ;
+ RECT 1236.830000 1022.120000 1237.830000 1022.600000 ;
+ RECT 1236.830000 1027.560000 1237.830000 1028.040000 ;
+ RECT 1236.830000 1033.000000 1237.830000 1033.480000 ;
+ RECT 1227.520000 1033.000000 1228.620000 1033.480000 ;
+ RECT 1227.520000 1027.560000 1228.620000 1028.040000 ;
+ RECT 1227.520000 1022.120000 1228.620000 1022.600000 ;
+ RECT 1227.520000 1011.240000 1228.620000 1011.720000 ;
+ RECT 1227.520000 1016.680000 1228.620000 1017.160000 ;
+ RECT 1236.830000 1016.680000 1237.830000 1017.160000 ;
+ RECT 1236.830000 1011.240000 1237.830000 1011.720000 ;
+ RECT 1236.830000 1000.360000 1237.830000 1000.840000 ;
+ RECT 1236.830000 1005.800000 1237.830000 1006.280000 ;
+ RECT 1227.520000 1000.360000 1228.620000 1000.840000 ;
+ RECT 1227.520000 1005.800000 1228.620000 1006.280000 ;
+ RECT 1182.520000 1043.880000 1183.620000 1044.360000 ;
+ RECT 1182.520000 1038.440000 1183.620000 1038.920000 ;
+ RECT 1182.520000 1033.000000 1183.620000 1033.480000 ;
+ RECT 1182.520000 1027.560000 1183.620000 1028.040000 ;
+ RECT 1182.520000 1022.120000 1183.620000 1022.600000 ;
+ RECT 1182.520000 1000.360000 1183.620000 1000.840000 ;
+ RECT 1182.520000 1005.800000 1183.620000 1006.280000 ;
+ RECT 1182.520000 1011.240000 1183.620000 1011.720000 ;
+ RECT 1182.520000 1016.680000 1183.620000 1017.160000 ;
+ RECT 1227.520000 994.920000 1228.620000 995.400000 ;
+ RECT 1227.520000 989.480000 1228.620000 989.960000 ;
+ RECT 1236.830000 994.920000 1237.830000 995.400000 ;
+ RECT 1236.830000 989.480000 1237.830000 989.960000 ;
+ RECT 1227.520000 978.600000 1228.620000 979.080000 ;
+ RECT 1227.520000 973.160000 1228.620000 973.640000 ;
+ RECT 1236.830000 978.600000 1237.830000 979.080000 ;
+ RECT 1236.830000 973.160000 1237.830000 973.640000 ;
+ RECT 1227.520000 984.040000 1228.620000 984.520000 ;
+ RECT 1236.830000 984.040000 1237.830000 984.520000 ;
+ RECT 1236.830000 962.280000 1237.830000 962.760000 ;
+ RECT 1236.830000 967.720000 1237.830000 968.200000 ;
+ RECT 1227.520000 967.720000 1228.620000 968.200000 ;
+ RECT 1227.520000 962.280000 1228.620000 962.760000 ;
+ RECT 1227.520000 956.840000 1228.620000 957.320000 ;
+ RECT 1227.520000 951.400000 1228.620000 951.880000 ;
+ RECT 1236.830000 956.840000 1237.830000 957.320000 ;
+ RECT 1236.830000 951.400000 1237.830000 951.880000 ;
+ RECT 1182.520000 994.920000 1183.620000 995.400000 ;
+ RECT 1182.520000 989.480000 1183.620000 989.960000 ;
+ RECT 1182.520000 984.040000 1183.620000 984.520000 ;
+ RECT 1182.520000 978.600000 1183.620000 979.080000 ;
+ RECT 1182.520000 973.160000 1183.620000 973.640000 ;
+ RECT 1182.520000 967.720000 1183.620000 968.200000 ;
+ RECT 1182.520000 962.280000 1183.620000 962.760000 ;
+ RECT 1182.520000 956.840000 1183.620000 957.320000 ;
+ RECT 1182.520000 951.400000 1183.620000 951.880000 ;
+ RECT 1137.520000 1043.880000 1138.620000 1044.360000 ;
+ RECT 1137.520000 1038.440000 1138.620000 1038.920000 ;
+ RECT 1137.520000 1033.000000 1138.620000 1033.480000 ;
+ RECT 1137.520000 1027.560000 1138.620000 1028.040000 ;
+ RECT 1137.520000 1022.120000 1138.620000 1022.600000 ;
+ RECT 1092.520000 1043.880000 1093.620000 1044.360000 ;
+ RECT 1092.520000 1038.440000 1093.620000 1038.920000 ;
+ RECT 1092.520000 1033.000000 1093.620000 1033.480000 ;
+ RECT 1092.520000 1027.560000 1093.620000 1028.040000 ;
+ RECT 1092.520000 1022.120000 1093.620000 1022.600000 ;
+ RECT 1137.520000 1016.680000 1138.620000 1017.160000 ;
+ RECT 1137.520000 1011.240000 1138.620000 1011.720000 ;
+ RECT 1137.520000 1005.800000 1138.620000 1006.280000 ;
+ RECT 1137.520000 1000.360000 1138.620000 1000.840000 ;
+ RECT 1092.520000 1011.240000 1093.620000 1011.720000 ;
+ RECT 1092.520000 1005.800000 1093.620000 1006.280000 ;
+ RECT 1092.520000 1000.360000 1093.620000 1000.840000 ;
+ RECT 1092.520000 1016.680000 1093.620000 1017.160000 ;
+ RECT 1047.520000 1043.880000 1048.620000 1044.360000 ;
+ RECT 1043.390000 1043.880000 1044.390000 1044.360000 ;
+ RECT 1047.520000 1038.440000 1048.620000 1038.920000 ;
+ RECT 1043.390000 1038.440000 1044.390000 1038.920000 ;
+ RECT 1047.520000 1033.000000 1048.620000 1033.480000 ;
+ RECT 1043.390000 1033.000000 1044.390000 1033.480000 ;
+ RECT 1047.520000 1022.120000 1048.620000 1022.600000 ;
+ RECT 1043.390000 1022.120000 1044.390000 1022.600000 ;
+ RECT 1043.390000 1027.560000 1044.390000 1028.040000 ;
+ RECT 1047.520000 1027.560000 1048.620000 1028.040000 ;
+ RECT 1047.520000 1016.680000 1048.620000 1017.160000 ;
+ RECT 1043.390000 1016.680000 1044.390000 1017.160000 ;
+ RECT 1047.520000 1011.240000 1048.620000 1011.720000 ;
+ RECT 1043.390000 1011.240000 1044.390000 1011.720000 ;
+ RECT 1047.520000 1005.800000 1048.620000 1006.280000 ;
+ RECT 1043.390000 1005.800000 1044.390000 1006.280000 ;
+ RECT 1047.520000 1000.360000 1048.620000 1000.840000 ;
+ RECT 1043.390000 1000.360000 1044.390000 1000.840000 ;
+ RECT 1137.520000 994.920000 1138.620000 995.400000 ;
+ RECT 1137.520000 989.480000 1138.620000 989.960000 ;
+ RECT 1137.520000 984.040000 1138.620000 984.520000 ;
+ RECT 1137.520000 978.600000 1138.620000 979.080000 ;
+ RECT 1137.520000 973.160000 1138.620000 973.640000 ;
+ RECT 1092.520000 994.920000 1093.620000 995.400000 ;
+ RECT 1092.520000 989.480000 1093.620000 989.960000 ;
+ RECT 1092.520000 984.040000 1093.620000 984.520000 ;
+ RECT 1092.520000 978.600000 1093.620000 979.080000 ;
+ RECT 1092.520000 973.160000 1093.620000 973.640000 ;
+ RECT 1137.520000 951.400000 1138.620000 951.880000 ;
+ RECT 1137.520000 956.840000 1138.620000 957.320000 ;
+ RECT 1137.520000 962.280000 1138.620000 962.760000 ;
+ RECT 1137.520000 967.720000 1138.620000 968.200000 ;
+ RECT 1092.520000 951.400000 1093.620000 951.880000 ;
+ RECT 1092.520000 956.840000 1093.620000 957.320000 ;
+ RECT 1092.520000 962.280000 1093.620000 962.760000 ;
+ RECT 1092.520000 967.720000 1093.620000 968.200000 ;
+ RECT 1047.520000 994.920000 1048.620000 995.400000 ;
+ RECT 1043.390000 994.920000 1044.390000 995.400000 ;
+ RECT 1047.520000 989.480000 1048.620000 989.960000 ;
+ RECT 1043.390000 989.480000 1044.390000 989.960000 ;
+ RECT 1047.520000 978.600000 1048.620000 979.080000 ;
+ RECT 1043.390000 978.600000 1044.390000 979.080000 ;
+ RECT 1047.520000 973.160000 1048.620000 973.640000 ;
+ RECT 1043.390000 973.160000 1044.390000 973.640000 ;
+ RECT 1047.520000 984.040000 1048.620000 984.520000 ;
+ RECT 1043.390000 984.040000 1044.390000 984.520000 ;
+ RECT 1047.520000 967.720000 1048.620000 968.200000 ;
+ RECT 1043.390000 967.720000 1044.390000 968.200000 ;
+ RECT 1047.520000 962.280000 1048.620000 962.760000 ;
+ RECT 1043.390000 962.280000 1044.390000 962.760000 ;
+ RECT 1047.520000 956.840000 1048.620000 957.320000 ;
+ RECT 1047.520000 951.400000 1048.620000 951.880000 ;
+ RECT 1043.390000 956.840000 1044.390000 957.320000 ;
+ RECT 1043.390000 951.400000 1044.390000 951.880000 ;
+ RECT 1040.560000 1141.760000 1240.660000 1142.760000 ;
+ RECT 1040.560000 949.390000 1240.660000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 946.540000 1044.390000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 1145.800000 1044.390000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 946.540000 1237.830000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 1145.800000 1237.830000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 949.390000 1041.560000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 949.390000 1240.660000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1141.760000 1041.560000 1142.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1141.760000 1240.660000 1142.760000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 749.130000 1228.620000 942.500000 ;
+ RECT 1182.520000 749.130000 1183.620000 942.500000 ;
+ RECT 1236.830000 746.280000 1237.830000 946.540000 ;
+ RECT 1137.520000 749.130000 1138.620000 942.500000 ;
+ RECT 1092.520000 749.130000 1093.620000 942.500000 ;
+ RECT 1047.520000 749.130000 1048.620000 942.500000 ;
+ RECT 1043.390000 746.280000 1044.390000 946.540000 ;
+ LAYER met3 ;
+ RECT 1227.520000 936.100000 1228.620000 936.580000 ;
+ RECT 1236.830000 936.100000 1237.830000 936.580000 ;
+ RECT 1236.830000 925.220000 1237.830000 925.700000 ;
+ RECT 1236.830000 930.660000 1237.830000 931.140000 ;
+ RECT 1227.520000 930.660000 1228.620000 931.140000 ;
+ RECT 1227.520000 925.220000 1228.620000 925.700000 ;
+ RECT 1227.520000 919.780000 1228.620000 920.260000 ;
+ RECT 1227.520000 914.340000 1228.620000 914.820000 ;
+ RECT 1236.830000 919.780000 1237.830000 920.260000 ;
+ RECT 1236.830000 914.340000 1237.830000 914.820000 ;
+ RECT 1227.520000 898.020000 1228.620000 898.500000 ;
+ RECT 1227.520000 903.460000 1228.620000 903.940000 ;
+ RECT 1236.830000 903.460000 1237.830000 903.940000 ;
+ RECT 1236.830000 898.020000 1237.830000 898.500000 ;
+ RECT 1227.520000 908.900000 1228.620000 909.380000 ;
+ RECT 1236.830000 908.900000 1237.830000 909.380000 ;
+ RECT 1182.520000 936.100000 1183.620000 936.580000 ;
+ RECT 1182.520000 930.660000 1183.620000 931.140000 ;
+ RECT 1182.520000 925.220000 1183.620000 925.700000 ;
+ RECT 1182.520000 919.780000 1183.620000 920.260000 ;
+ RECT 1182.520000 898.020000 1183.620000 898.500000 ;
+ RECT 1182.520000 903.460000 1183.620000 903.940000 ;
+ RECT 1182.520000 908.900000 1183.620000 909.380000 ;
+ RECT 1182.520000 914.340000 1183.620000 914.820000 ;
+ RECT 1236.830000 887.140000 1237.830000 887.620000 ;
+ RECT 1236.830000 892.580000 1237.830000 893.060000 ;
+ RECT 1227.520000 892.580000 1228.620000 893.060000 ;
+ RECT 1227.520000 887.140000 1228.620000 887.620000 ;
+ RECT 1227.520000 881.700000 1228.620000 882.180000 ;
+ RECT 1227.520000 876.260000 1228.620000 876.740000 ;
+ RECT 1236.830000 881.700000 1237.830000 882.180000 ;
+ RECT 1236.830000 876.260000 1237.830000 876.740000 ;
+ RECT 1236.830000 859.940000 1237.830000 860.420000 ;
+ RECT 1236.830000 865.380000 1237.830000 865.860000 ;
+ RECT 1236.830000 870.820000 1237.830000 871.300000 ;
+ RECT 1227.520000 865.380000 1228.620000 865.860000 ;
+ RECT 1227.520000 859.940000 1228.620000 860.420000 ;
+ RECT 1227.520000 870.820000 1228.620000 871.300000 ;
+ RECT 1227.520000 854.500000 1228.620000 854.980000 ;
+ RECT 1227.520000 849.060000 1228.620000 849.540000 ;
+ RECT 1236.830000 854.500000 1237.830000 854.980000 ;
+ RECT 1236.830000 849.060000 1237.830000 849.540000 ;
+ RECT 1182.520000 892.580000 1183.620000 893.060000 ;
+ RECT 1182.520000 887.140000 1183.620000 887.620000 ;
+ RECT 1182.520000 881.700000 1183.620000 882.180000 ;
+ RECT 1182.520000 876.260000 1183.620000 876.740000 ;
+ RECT 1182.520000 865.380000 1183.620000 865.860000 ;
+ RECT 1182.520000 859.940000 1183.620000 860.420000 ;
+ RECT 1182.520000 854.500000 1183.620000 854.980000 ;
+ RECT 1182.520000 849.060000 1183.620000 849.540000 ;
+ RECT 1182.520000 870.820000 1183.620000 871.300000 ;
+ RECT 1137.520000 936.100000 1138.620000 936.580000 ;
+ RECT 1137.520000 930.660000 1138.620000 931.140000 ;
+ RECT 1137.520000 925.220000 1138.620000 925.700000 ;
+ RECT 1092.520000 936.100000 1093.620000 936.580000 ;
+ RECT 1092.520000 930.660000 1093.620000 931.140000 ;
+ RECT 1092.520000 925.220000 1093.620000 925.700000 ;
+ RECT 1137.520000 908.900000 1138.620000 909.380000 ;
+ RECT 1137.520000 903.460000 1138.620000 903.940000 ;
+ RECT 1137.520000 898.020000 1138.620000 898.500000 ;
+ RECT 1137.520000 914.340000 1138.620000 914.820000 ;
+ RECT 1137.520000 919.780000 1138.620000 920.260000 ;
+ RECT 1092.520000 919.780000 1093.620000 920.260000 ;
+ RECT 1092.520000 908.900000 1093.620000 909.380000 ;
+ RECT 1092.520000 903.460000 1093.620000 903.940000 ;
+ RECT 1092.520000 898.020000 1093.620000 898.500000 ;
+ RECT 1092.520000 914.340000 1093.620000 914.820000 ;
+ RECT 1047.520000 936.100000 1048.620000 936.580000 ;
+ RECT 1043.390000 936.100000 1044.390000 936.580000 ;
+ RECT 1043.390000 930.660000 1044.390000 931.140000 ;
+ RECT 1047.520000 930.660000 1048.620000 931.140000 ;
+ RECT 1047.520000 925.220000 1048.620000 925.700000 ;
+ RECT 1043.390000 925.220000 1044.390000 925.700000 ;
+ RECT 1047.520000 919.780000 1048.620000 920.260000 ;
+ RECT 1043.390000 919.780000 1044.390000 920.260000 ;
+ RECT 1047.520000 914.340000 1048.620000 914.820000 ;
+ RECT 1043.390000 914.340000 1044.390000 914.820000 ;
+ RECT 1047.520000 903.460000 1048.620000 903.940000 ;
+ RECT 1043.390000 903.460000 1044.390000 903.940000 ;
+ RECT 1047.520000 898.020000 1048.620000 898.500000 ;
+ RECT 1043.390000 898.020000 1044.390000 898.500000 ;
+ RECT 1047.520000 908.900000 1048.620000 909.380000 ;
+ RECT 1043.390000 908.900000 1044.390000 909.380000 ;
+ RECT 1137.520000 892.580000 1138.620000 893.060000 ;
+ RECT 1137.520000 887.140000 1138.620000 887.620000 ;
+ RECT 1137.520000 881.700000 1138.620000 882.180000 ;
+ RECT 1137.520000 876.260000 1138.620000 876.740000 ;
+ RECT 1092.520000 892.580000 1093.620000 893.060000 ;
+ RECT 1092.520000 887.140000 1093.620000 887.620000 ;
+ RECT 1092.520000 881.700000 1093.620000 882.180000 ;
+ RECT 1092.520000 876.260000 1093.620000 876.740000 ;
+ RECT 1137.520000 865.380000 1138.620000 865.860000 ;
+ RECT 1137.520000 849.060000 1138.620000 849.540000 ;
+ RECT 1137.520000 854.500000 1138.620000 854.980000 ;
+ RECT 1137.520000 859.940000 1138.620000 860.420000 ;
+ RECT 1137.520000 870.820000 1138.620000 871.300000 ;
+ RECT 1092.520000 849.060000 1093.620000 849.540000 ;
+ RECT 1092.520000 854.500000 1093.620000 854.980000 ;
+ RECT 1092.520000 859.940000 1093.620000 860.420000 ;
+ RECT 1092.520000 865.380000 1093.620000 865.860000 ;
+ RECT 1092.520000 870.820000 1093.620000 871.300000 ;
+ RECT 1047.520000 892.580000 1048.620000 893.060000 ;
+ RECT 1043.390000 892.580000 1044.390000 893.060000 ;
+ RECT 1047.520000 887.140000 1048.620000 887.620000 ;
+ RECT 1043.390000 887.140000 1044.390000 887.620000 ;
+ RECT 1047.520000 881.700000 1048.620000 882.180000 ;
+ RECT 1043.390000 881.700000 1044.390000 882.180000 ;
+ RECT 1047.520000 876.260000 1048.620000 876.740000 ;
+ RECT 1043.390000 876.260000 1044.390000 876.740000 ;
+ RECT 1047.520000 870.820000 1048.620000 871.300000 ;
+ RECT 1047.520000 865.380000 1048.620000 865.860000 ;
+ RECT 1043.390000 870.820000 1044.390000 871.300000 ;
+ RECT 1043.390000 865.380000 1044.390000 865.860000 ;
+ RECT 1047.520000 859.940000 1048.620000 860.420000 ;
+ RECT 1043.390000 859.940000 1044.390000 860.420000 ;
+ RECT 1047.520000 854.500000 1048.620000 854.980000 ;
+ RECT 1043.390000 854.500000 1044.390000 854.980000 ;
+ RECT 1047.520000 849.060000 1048.620000 849.540000 ;
+ RECT 1043.390000 849.060000 1044.390000 849.540000 ;
+ RECT 1227.520000 843.620000 1228.620000 844.100000 ;
+ RECT 1227.520000 838.180000 1228.620000 838.660000 ;
+ RECT 1236.830000 843.620000 1237.830000 844.100000 ;
+ RECT 1236.830000 838.180000 1237.830000 838.660000 ;
+ RECT 1236.830000 821.860000 1237.830000 822.340000 ;
+ RECT 1236.830000 827.300000 1237.830000 827.780000 ;
+ RECT 1236.830000 832.740000 1237.830000 833.220000 ;
+ RECT 1227.520000 832.740000 1228.620000 833.220000 ;
+ RECT 1227.520000 827.300000 1228.620000 827.780000 ;
+ RECT 1227.520000 821.860000 1228.620000 822.340000 ;
+ RECT 1227.520000 810.980000 1228.620000 811.460000 ;
+ RECT 1227.520000 816.420000 1228.620000 816.900000 ;
+ RECT 1236.830000 816.420000 1237.830000 816.900000 ;
+ RECT 1236.830000 810.980000 1237.830000 811.460000 ;
+ RECT 1236.830000 800.100000 1237.830000 800.580000 ;
+ RECT 1236.830000 805.540000 1237.830000 806.020000 ;
+ RECT 1227.520000 800.100000 1228.620000 800.580000 ;
+ RECT 1227.520000 805.540000 1228.620000 806.020000 ;
+ RECT 1182.520000 843.620000 1183.620000 844.100000 ;
+ RECT 1182.520000 838.180000 1183.620000 838.660000 ;
+ RECT 1182.520000 832.740000 1183.620000 833.220000 ;
+ RECT 1182.520000 827.300000 1183.620000 827.780000 ;
+ RECT 1182.520000 821.860000 1183.620000 822.340000 ;
+ RECT 1182.520000 800.100000 1183.620000 800.580000 ;
+ RECT 1182.520000 805.540000 1183.620000 806.020000 ;
+ RECT 1182.520000 810.980000 1183.620000 811.460000 ;
+ RECT 1182.520000 816.420000 1183.620000 816.900000 ;
+ RECT 1227.520000 794.660000 1228.620000 795.140000 ;
+ RECT 1227.520000 789.220000 1228.620000 789.700000 ;
+ RECT 1236.830000 794.660000 1237.830000 795.140000 ;
+ RECT 1236.830000 789.220000 1237.830000 789.700000 ;
+ RECT 1227.520000 778.340000 1228.620000 778.820000 ;
+ RECT 1227.520000 772.900000 1228.620000 773.380000 ;
+ RECT 1236.830000 778.340000 1237.830000 778.820000 ;
+ RECT 1236.830000 772.900000 1237.830000 773.380000 ;
+ RECT 1227.520000 783.780000 1228.620000 784.260000 ;
+ RECT 1236.830000 783.780000 1237.830000 784.260000 ;
+ RECT 1236.830000 762.020000 1237.830000 762.500000 ;
+ RECT 1236.830000 767.460000 1237.830000 767.940000 ;
+ RECT 1227.520000 767.460000 1228.620000 767.940000 ;
+ RECT 1227.520000 762.020000 1228.620000 762.500000 ;
+ RECT 1227.520000 756.580000 1228.620000 757.060000 ;
+ RECT 1227.520000 751.140000 1228.620000 751.620000 ;
+ RECT 1236.830000 756.580000 1237.830000 757.060000 ;
+ RECT 1236.830000 751.140000 1237.830000 751.620000 ;
+ RECT 1182.520000 794.660000 1183.620000 795.140000 ;
+ RECT 1182.520000 789.220000 1183.620000 789.700000 ;
+ RECT 1182.520000 783.780000 1183.620000 784.260000 ;
+ RECT 1182.520000 778.340000 1183.620000 778.820000 ;
+ RECT 1182.520000 772.900000 1183.620000 773.380000 ;
+ RECT 1182.520000 767.460000 1183.620000 767.940000 ;
+ RECT 1182.520000 762.020000 1183.620000 762.500000 ;
+ RECT 1182.520000 756.580000 1183.620000 757.060000 ;
+ RECT 1182.520000 751.140000 1183.620000 751.620000 ;
+ RECT 1137.520000 843.620000 1138.620000 844.100000 ;
+ RECT 1137.520000 838.180000 1138.620000 838.660000 ;
+ RECT 1137.520000 832.740000 1138.620000 833.220000 ;
+ RECT 1137.520000 827.300000 1138.620000 827.780000 ;
+ RECT 1137.520000 821.860000 1138.620000 822.340000 ;
+ RECT 1092.520000 843.620000 1093.620000 844.100000 ;
+ RECT 1092.520000 838.180000 1093.620000 838.660000 ;
+ RECT 1092.520000 832.740000 1093.620000 833.220000 ;
+ RECT 1092.520000 827.300000 1093.620000 827.780000 ;
+ RECT 1092.520000 821.860000 1093.620000 822.340000 ;
+ RECT 1137.520000 816.420000 1138.620000 816.900000 ;
+ RECT 1137.520000 810.980000 1138.620000 811.460000 ;
+ RECT 1137.520000 805.540000 1138.620000 806.020000 ;
+ RECT 1137.520000 800.100000 1138.620000 800.580000 ;
+ RECT 1092.520000 810.980000 1093.620000 811.460000 ;
+ RECT 1092.520000 805.540000 1093.620000 806.020000 ;
+ RECT 1092.520000 800.100000 1093.620000 800.580000 ;
+ RECT 1092.520000 816.420000 1093.620000 816.900000 ;
+ RECT 1047.520000 843.620000 1048.620000 844.100000 ;
+ RECT 1043.390000 843.620000 1044.390000 844.100000 ;
+ RECT 1047.520000 838.180000 1048.620000 838.660000 ;
+ RECT 1043.390000 838.180000 1044.390000 838.660000 ;
+ RECT 1047.520000 832.740000 1048.620000 833.220000 ;
+ RECT 1043.390000 832.740000 1044.390000 833.220000 ;
+ RECT 1047.520000 821.860000 1048.620000 822.340000 ;
+ RECT 1043.390000 821.860000 1044.390000 822.340000 ;
+ RECT 1043.390000 827.300000 1044.390000 827.780000 ;
+ RECT 1047.520000 827.300000 1048.620000 827.780000 ;
+ RECT 1047.520000 816.420000 1048.620000 816.900000 ;
+ RECT 1043.390000 816.420000 1044.390000 816.900000 ;
+ RECT 1047.520000 810.980000 1048.620000 811.460000 ;
+ RECT 1043.390000 810.980000 1044.390000 811.460000 ;
+ RECT 1047.520000 805.540000 1048.620000 806.020000 ;
+ RECT 1043.390000 805.540000 1044.390000 806.020000 ;
+ RECT 1047.520000 800.100000 1048.620000 800.580000 ;
+ RECT 1043.390000 800.100000 1044.390000 800.580000 ;
+ RECT 1137.520000 794.660000 1138.620000 795.140000 ;
+ RECT 1137.520000 789.220000 1138.620000 789.700000 ;
+ RECT 1137.520000 783.780000 1138.620000 784.260000 ;
+ RECT 1137.520000 778.340000 1138.620000 778.820000 ;
+ RECT 1137.520000 772.900000 1138.620000 773.380000 ;
+ RECT 1092.520000 794.660000 1093.620000 795.140000 ;
+ RECT 1092.520000 789.220000 1093.620000 789.700000 ;
+ RECT 1092.520000 783.780000 1093.620000 784.260000 ;
+ RECT 1092.520000 778.340000 1093.620000 778.820000 ;
+ RECT 1092.520000 772.900000 1093.620000 773.380000 ;
+ RECT 1137.520000 751.140000 1138.620000 751.620000 ;
+ RECT 1137.520000 756.580000 1138.620000 757.060000 ;
+ RECT 1137.520000 762.020000 1138.620000 762.500000 ;
+ RECT 1137.520000 767.460000 1138.620000 767.940000 ;
+ RECT 1092.520000 751.140000 1093.620000 751.620000 ;
+ RECT 1092.520000 756.580000 1093.620000 757.060000 ;
+ RECT 1092.520000 762.020000 1093.620000 762.500000 ;
+ RECT 1092.520000 767.460000 1093.620000 767.940000 ;
+ RECT 1047.520000 794.660000 1048.620000 795.140000 ;
+ RECT 1043.390000 794.660000 1044.390000 795.140000 ;
+ RECT 1047.520000 789.220000 1048.620000 789.700000 ;
+ RECT 1043.390000 789.220000 1044.390000 789.700000 ;
+ RECT 1047.520000 778.340000 1048.620000 778.820000 ;
+ RECT 1043.390000 778.340000 1044.390000 778.820000 ;
+ RECT 1047.520000 772.900000 1048.620000 773.380000 ;
+ RECT 1043.390000 772.900000 1044.390000 773.380000 ;
+ RECT 1047.520000 783.780000 1048.620000 784.260000 ;
+ RECT 1043.390000 783.780000 1044.390000 784.260000 ;
+ RECT 1047.520000 767.460000 1048.620000 767.940000 ;
+ RECT 1043.390000 767.460000 1044.390000 767.940000 ;
+ RECT 1047.520000 762.020000 1048.620000 762.500000 ;
+ RECT 1043.390000 762.020000 1044.390000 762.500000 ;
+ RECT 1047.520000 756.580000 1048.620000 757.060000 ;
+ RECT 1047.520000 751.140000 1048.620000 751.620000 ;
+ RECT 1043.390000 756.580000 1044.390000 757.060000 ;
+ RECT 1043.390000 751.140000 1044.390000 751.620000 ;
+ RECT 1040.560000 941.500000 1240.660000 942.500000 ;
+ RECT 1040.560000 749.130000 1240.660000 750.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 746.280000 1044.390000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 945.540000 1044.390000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 746.280000 1237.830000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 945.540000 1237.830000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 749.130000 1041.560000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 749.130000 1240.660000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 941.500000 1041.560000 942.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 941.500000 1240.660000 942.500000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 548.870000 1228.620000 742.240000 ;
+ RECT 1182.520000 548.870000 1183.620000 742.240000 ;
+ RECT 1236.830000 546.020000 1237.830000 746.280000 ;
+ RECT 1137.520000 548.870000 1138.620000 742.240000 ;
+ RECT 1092.520000 548.870000 1093.620000 742.240000 ;
+ RECT 1047.520000 548.870000 1048.620000 742.240000 ;
+ RECT 1043.390000 546.020000 1044.390000 746.280000 ;
+ LAYER met3 ;
+ RECT 1227.520000 735.840000 1228.620000 736.320000 ;
+ RECT 1236.830000 735.840000 1237.830000 736.320000 ;
+ RECT 1236.830000 724.960000 1237.830000 725.440000 ;
+ RECT 1236.830000 730.400000 1237.830000 730.880000 ;
+ RECT 1227.520000 730.400000 1228.620000 730.880000 ;
+ RECT 1227.520000 724.960000 1228.620000 725.440000 ;
+ RECT 1227.520000 719.520000 1228.620000 720.000000 ;
+ RECT 1227.520000 714.080000 1228.620000 714.560000 ;
+ RECT 1236.830000 719.520000 1237.830000 720.000000 ;
+ RECT 1236.830000 714.080000 1237.830000 714.560000 ;
+ RECT 1227.520000 697.760000 1228.620000 698.240000 ;
+ RECT 1227.520000 703.200000 1228.620000 703.680000 ;
+ RECT 1236.830000 703.200000 1237.830000 703.680000 ;
+ RECT 1236.830000 697.760000 1237.830000 698.240000 ;
+ RECT 1227.520000 708.640000 1228.620000 709.120000 ;
+ RECT 1236.830000 708.640000 1237.830000 709.120000 ;
+ RECT 1182.520000 735.840000 1183.620000 736.320000 ;
+ RECT 1182.520000 730.400000 1183.620000 730.880000 ;
+ RECT 1182.520000 724.960000 1183.620000 725.440000 ;
+ RECT 1182.520000 719.520000 1183.620000 720.000000 ;
+ RECT 1182.520000 697.760000 1183.620000 698.240000 ;
+ RECT 1182.520000 703.200000 1183.620000 703.680000 ;
+ RECT 1182.520000 708.640000 1183.620000 709.120000 ;
+ RECT 1182.520000 714.080000 1183.620000 714.560000 ;
+ RECT 1236.830000 686.880000 1237.830000 687.360000 ;
+ RECT 1236.830000 692.320000 1237.830000 692.800000 ;
+ RECT 1227.520000 692.320000 1228.620000 692.800000 ;
+ RECT 1227.520000 686.880000 1228.620000 687.360000 ;
+ RECT 1227.520000 681.440000 1228.620000 681.920000 ;
+ RECT 1227.520000 676.000000 1228.620000 676.480000 ;
+ RECT 1236.830000 681.440000 1237.830000 681.920000 ;
+ RECT 1236.830000 676.000000 1237.830000 676.480000 ;
+ RECT 1236.830000 659.680000 1237.830000 660.160000 ;
+ RECT 1236.830000 665.120000 1237.830000 665.600000 ;
+ RECT 1236.830000 670.560000 1237.830000 671.040000 ;
+ RECT 1227.520000 665.120000 1228.620000 665.600000 ;
+ RECT 1227.520000 659.680000 1228.620000 660.160000 ;
+ RECT 1227.520000 670.560000 1228.620000 671.040000 ;
+ RECT 1227.520000 654.240000 1228.620000 654.720000 ;
+ RECT 1227.520000 648.800000 1228.620000 649.280000 ;
+ RECT 1236.830000 654.240000 1237.830000 654.720000 ;
+ RECT 1236.830000 648.800000 1237.830000 649.280000 ;
+ RECT 1182.520000 692.320000 1183.620000 692.800000 ;
+ RECT 1182.520000 686.880000 1183.620000 687.360000 ;
+ RECT 1182.520000 681.440000 1183.620000 681.920000 ;
+ RECT 1182.520000 676.000000 1183.620000 676.480000 ;
+ RECT 1182.520000 665.120000 1183.620000 665.600000 ;
+ RECT 1182.520000 659.680000 1183.620000 660.160000 ;
+ RECT 1182.520000 654.240000 1183.620000 654.720000 ;
+ RECT 1182.520000 648.800000 1183.620000 649.280000 ;
+ RECT 1182.520000 670.560000 1183.620000 671.040000 ;
+ RECT 1137.520000 735.840000 1138.620000 736.320000 ;
+ RECT 1137.520000 730.400000 1138.620000 730.880000 ;
+ RECT 1137.520000 724.960000 1138.620000 725.440000 ;
+ RECT 1092.520000 735.840000 1093.620000 736.320000 ;
+ RECT 1092.520000 730.400000 1093.620000 730.880000 ;
+ RECT 1092.520000 724.960000 1093.620000 725.440000 ;
+ RECT 1137.520000 708.640000 1138.620000 709.120000 ;
+ RECT 1137.520000 703.200000 1138.620000 703.680000 ;
+ RECT 1137.520000 697.760000 1138.620000 698.240000 ;
+ RECT 1137.520000 714.080000 1138.620000 714.560000 ;
+ RECT 1137.520000 719.520000 1138.620000 720.000000 ;
+ RECT 1092.520000 719.520000 1093.620000 720.000000 ;
+ RECT 1092.520000 708.640000 1093.620000 709.120000 ;
+ RECT 1092.520000 703.200000 1093.620000 703.680000 ;
+ RECT 1092.520000 697.760000 1093.620000 698.240000 ;
+ RECT 1092.520000 714.080000 1093.620000 714.560000 ;
+ RECT 1047.520000 735.840000 1048.620000 736.320000 ;
+ RECT 1043.390000 735.840000 1044.390000 736.320000 ;
+ RECT 1043.390000 730.400000 1044.390000 730.880000 ;
+ RECT 1047.520000 730.400000 1048.620000 730.880000 ;
+ RECT 1047.520000 724.960000 1048.620000 725.440000 ;
+ RECT 1043.390000 724.960000 1044.390000 725.440000 ;
+ RECT 1047.520000 719.520000 1048.620000 720.000000 ;
+ RECT 1043.390000 719.520000 1044.390000 720.000000 ;
+ RECT 1047.520000 714.080000 1048.620000 714.560000 ;
+ RECT 1043.390000 714.080000 1044.390000 714.560000 ;
+ RECT 1047.520000 703.200000 1048.620000 703.680000 ;
+ RECT 1043.390000 703.200000 1044.390000 703.680000 ;
+ RECT 1047.520000 697.760000 1048.620000 698.240000 ;
+ RECT 1043.390000 697.760000 1044.390000 698.240000 ;
+ RECT 1047.520000 708.640000 1048.620000 709.120000 ;
+ RECT 1043.390000 708.640000 1044.390000 709.120000 ;
+ RECT 1137.520000 692.320000 1138.620000 692.800000 ;
+ RECT 1137.520000 686.880000 1138.620000 687.360000 ;
+ RECT 1137.520000 681.440000 1138.620000 681.920000 ;
+ RECT 1137.520000 676.000000 1138.620000 676.480000 ;
+ RECT 1092.520000 692.320000 1093.620000 692.800000 ;
+ RECT 1092.520000 686.880000 1093.620000 687.360000 ;
+ RECT 1092.520000 681.440000 1093.620000 681.920000 ;
+ RECT 1092.520000 676.000000 1093.620000 676.480000 ;
+ RECT 1137.520000 665.120000 1138.620000 665.600000 ;
+ RECT 1137.520000 648.800000 1138.620000 649.280000 ;
+ RECT 1137.520000 654.240000 1138.620000 654.720000 ;
+ RECT 1137.520000 659.680000 1138.620000 660.160000 ;
+ RECT 1137.520000 670.560000 1138.620000 671.040000 ;
+ RECT 1092.520000 648.800000 1093.620000 649.280000 ;
+ RECT 1092.520000 654.240000 1093.620000 654.720000 ;
+ RECT 1092.520000 659.680000 1093.620000 660.160000 ;
+ RECT 1092.520000 665.120000 1093.620000 665.600000 ;
+ RECT 1092.520000 670.560000 1093.620000 671.040000 ;
+ RECT 1047.520000 692.320000 1048.620000 692.800000 ;
+ RECT 1043.390000 692.320000 1044.390000 692.800000 ;
+ RECT 1047.520000 686.880000 1048.620000 687.360000 ;
+ RECT 1043.390000 686.880000 1044.390000 687.360000 ;
+ RECT 1047.520000 681.440000 1048.620000 681.920000 ;
+ RECT 1043.390000 681.440000 1044.390000 681.920000 ;
+ RECT 1047.520000 676.000000 1048.620000 676.480000 ;
+ RECT 1043.390000 676.000000 1044.390000 676.480000 ;
+ RECT 1047.520000 670.560000 1048.620000 671.040000 ;
+ RECT 1047.520000 665.120000 1048.620000 665.600000 ;
+ RECT 1043.390000 670.560000 1044.390000 671.040000 ;
+ RECT 1043.390000 665.120000 1044.390000 665.600000 ;
+ RECT 1047.520000 659.680000 1048.620000 660.160000 ;
+ RECT 1043.390000 659.680000 1044.390000 660.160000 ;
+ RECT 1047.520000 654.240000 1048.620000 654.720000 ;
+ RECT 1043.390000 654.240000 1044.390000 654.720000 ;
+ RECT 1047.520000 648.800000 1048.620000 649.280000 ;
+ RECT 1043.390000 648.800000 1044.390000 649.280000 ;
+ RECT 1227.520000 643.360000 1228.620000 643.840000 ;
+ RECT 1227.520000 637.920000 1228.620000 638.400000 ;
+ RECT 1236.830000 643.360000 1237.830000 643.840000 ;
+ RECT 1236.830000 637.920000 1237.830000 638.400000 ;
+ RECT 1236.830000 621.600000 1237.830000 622.080000 ;
+ RECT 1236.830000 627.040000 1237.830000 627.520000 ;
+ RECT 1236.830000 632.480000 1237.830000 632.960000 ;
+ RECT 1227.520000 632.480000 1228.620000 632.960000 ;
+ RECT 1227.520000 627.040000 1228.620000 627.520000 ;
+ RECT 1227.520000 621.600000 1228.620000 622.080000 ;
+ RECT 1227.520000 610.720000 1228.620000 611.200000 ;
+ RECT 1227.520000 616.160000 1228.620000 616.640000 ;
+ RECT 1236.830000 616.160000 1237.830000 616.640000 ;
+ RECT 1236.830000 610.720000 1237.830000 611.200000 ;
+ RECT 1236.830000 599.840000 1237.830000 600.320000 ;
+ RECT 1236.830000 605.280000 1237.830000 605.760000 ;
+ RECT 1227.520000 599.840000 1228.620000 600.320000 ;
+ RECT 1227.520000 605.280000 1228.620000 605.760000 ;
+ RECT 1182.520000 643.360000 1183.620000 643.840000 ;
+ RECT 1182.520000 637.920000 1183.620000 638.400000 ;
+ RECT 1182.520000 632.480000 1183.620000 632.960000 ;
+ RECT 1182.520000 627.040000 1183.620000 627.520000 ;
+ RECT 1182.520000 621.600000 1183.620000 622.080000 ;
+ RECT 1182.520000 599.840000 1183.620000 600.320000 ;
+ RECT 1182.520000 605.280000 1183.620000 605.760000 ;
+ RECT 1182.520000 610.720000 1183.620000 611.200000 ;
+ RECT 1182.520000 616.160000 1183.620000 616.640000 ;
+ RECT 1227.520000 594.400000 1228.620000 594.880000 ;
+ RECT 1227.520000 588.960000 1228.620000 589.440000 ;
+ RECT 1236.830000 594.400000 1237.830000 594.880000 ;
+ RECT 1236.830000 588.960000 1237.830000 589.440000 ;
+ RECT 1227.520000 578.080000 1228.620000 578.560000 ;
+ RECT 1227.520000 572.640000 1228.620000 573.120000 ;
+ RECT 1236.830000 578.080000 1237.830000 578.560000 ;
+ RECT 1236.830000 572.640000 1237.830000 573.120000 ;
+ RECT 1227.520000 583.520000 1228.620000 584.000000 ;
+ RECT 1236.830000 583.520000 1237.830000 584.000000 ;
+ RECT 1236.830000 561.760000 1237.830000 562.240000 ;
+ RECT 1236.830000 567.200000 1237.830000 567.680000 ;
+ RECT 1227.520000 567.200000 1228.620000 567.680000 ;
+ RECT 1227.520000 561.760000 1228.620000 562.240000 ;
+ RECT 1227.520000 556.320000 1228.620000 556.800000 ;
+ RECT 1227.520000 550.880000 1228.620000 551.360000 ;
+ RECT 1236.830000 556.320000 1237.830000 556.800000 ;
+ RECT 1236.830000 550.880000 1237.830000 551.360000 ;
+ RECT 1182.520000 594.400000 1183.620000 594.880000 ;
+ RECT 1182.520000 588.960000 1183.620000 589.440000 ;
+ RECT 1182.520000 583.520000 1183.620000 584.000000 ;
+ RECT 1182.520000 578.080000 1183.620000 578.560000 ;
+ RECT 1182.520000 572.640000 1183.620000 573.120000 ;
+ RECT 1182.520000 567.200000 1183.620000 567.680000 ;
+ RECT 1182.520000 561.760000 1183.620000 562.240000 ;
+ RECT 1182.520000 556.320000 1183.620000 556.800000 ;
+ RECT 1182.520000 550.880000 1183.620000 551.360000 ;
+ RECT 1137.520000 643.360000 1138.620000 643.840000 ;
+ RECT 1137.520000 637.920000 1138.620000 638.400000 ;
+ RECT 1137.520000 632.480000 1138.620000 632.960000 ;
+ RECT 1137.520000 627.040000 1138.620000 627.520000 ;
+ RECT 1137.520000 621.600000 1138.620000 622.080000 ;
+ RECT 1092.520000 643.360000 1093.620000 643.840000 ;
+ RECT 1092.520000 637.920000 1093.620000 638.400000 ;
+ RECT 1092.520000 632.480000 1093.620000 632.960000 ;
+ RECT 1092.520000 627.040000 1093.620000 627.520000 ;
+ RECT 1092.520000 621.600000 1093.620000 622.080000 ;
+ RECT 1137.520000 616.160000 1138.620000 616.640000 ;
+ RECT 1137.520000 610.720000 1138.620000 611.200000 ;
+ RECT 1137.520000 605.280000 1138.620000 605.760000 ;
+ RECT 1137.520000 599.840000 1138.620000 600.320000 ;
+ RECT 1092.520000 610.720000 1093.620000 611.200000 ;
+ RECT 1092.520000 605.280000 1093.620000 605.760000 ;
+ RECT 1092.520000 599.840000 1093.620000 600.320000 ;
+ RECT 1092.520000 616.160000 1093.620000 616.640000 ;
+ RECT 1047.520000 643.360000 1048.620000 643.840000 ;
+ RECT 1043.390000 643.360000 1044.390000 643.840000 ;
+ RECT 1047.520000 637.920000 1048.620000 638.400000 ;
+ RECT 1043.390000 637.920000 1044.390000 638.400000 ;
+ RECT 1047.520000 632.480000 1048.620000 632.960000 ;
+ RECT 1043.390000 632.480000 1044.390000 632.960000 ;
+ RECT 1047.520000 621.600000 1048.620000 622.080000 ;
+ RECT 1043.390000 621.600000 1044.390000 622.080000 ;
+ RECT 1043.390000 627.040000 1044.390000 627.520000 ;
+ RECT 1047.520000 627.040000 1048.620000 627.520000 ;
+ RECT 1047.520000 616.160000 1048.620000 616.640000 ;
+ RECT 1043.390000 616.160000 1044.390000 616.640000 ;
+ RECT 1047.520000 610.720000 1048.620000 611.200000 ;
+ RECT 1043.390000 610.720000 1044.390000 611.200000 ;
+ RECT 1047.520000 605.280000 1048.620000 605.760000 ;
+ RECT 1043.390000 605.280000 1044.390000 605.760000 ;
+ RECT 1047.520000 599.840000 1048.620000 600.320000 ;
+ RECT 1043.390000 599.840000 1044.390000 600.320000 ;
+ RECT 1137.520000 594.400000 1138.620000 594.880000 ;
+ RECT 1137.520000 588.960000 1138.620000 589.440000 ;
+ RECT 1137.520000 583.520000 1138.620000 584.000000 ;
+ RECT 1137.520000 578.080000 1138.620000 578.560000 ;
+ RECT 1137.520000 572.640000 1138.620000 573.120000 ;
+ RECT 1092.520000 594.400000 1093.620000 594.880000 ;
+ RECT 1092.520000 588.960000 1093.620000 589.440000 ;
+ RECT 1092.520000 583.520000 1093.620000 584.000000 ;
+ RECT 1092.520000 578.080000 1093.620000 578.560000 ;
+ RECT 1092.520000 572.640000 1093.620000 573.120000 ;
+ RECT 1137.520000 550.880000 1138.620000 551.360000 ;
+ RECT 1137.520000 556.320000 1138.620000 556.800000 ;
+ RECT 1137.520000 561.760000 1138.620000 562.240000 ;
+ RECT 1137.520000 567.200000 1138.620000 567.680000 ;
+ RECT 1092.520000 550.880000 1093.620000 551.360000 ;
+ RECT 1092.520000 556.320000 1093.620000 556.800000 ;
+ RECT 1092.520000 561.760000 1093.620000 562.240000 ;
+ RECT 1092.520000 567.200000 1093.620000 567.680000 ;
+ RECT 1047.520000 594.400000 1048.620000 594.880000 ;
+ RECT 1043.390000 594.400000 1044.390000 594.880000 ;
+ RECT 1047.520000 588.960000 1048.620000 589.440000 ;
+ RECT 1043.390000 588.960000 1044.390000 589.440000 ;
+ RECT 1047.520000 578.080000 1048.620000 578.560000 ;
+ RECT 1043.390000 578.080000 1044.390000 578.560000 ;
+ RECT 1047.520000 572.640000 1048.620000 573.120000 ;
+ RECT 1043.390000 572.640000 1044.390000 573.120000 ;
+ RECT 1047.520000 583.520000 1048.620000 584.000000 ;
+ RECT 1043.390000 583.520000 1044.390000 584.000000 ;
+ RECT 1047.520000 567.200000 1048.620000 567.680000 ;
+ RECT 1043.390000 567.200000 1044.390000 567.680000 ;
+ RECT 1047.520000 561.760000 1048.620000 562.240000 ;
+ RECT 1043.390000 561.760000 1044.390000 562.240000 ;
+ RECT 1047.520000 556.320000 1048.620000 556.800000 ;
+ RECT 1047.520000 550.880000 1048.620000 551.360000 ;
+ RECT 1043.390000 556.320000 1044.390000 556.800000 ;
+ RECT 1043.390000 550.880000 1044.390000 551.360000 ;
+ RECT 1040.560000 741.240000 1240.660000 742.240000 ;
+ RECT 1040.560000 548.870000 1240.660000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 546.020000 1044.390000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 745.280000 1044.390000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 546.020000 1237.830000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 745.280000 1237.830000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 548.870000 1041.560000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 548.870000 1240.660000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 741.240000 1041.560000 742.240000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 741.240000 1240.660000 742.240000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 348.610000 1228.620000 541.980000 ;
+ RECT 1182.520000 348.610000 1183.620000 541.980000 ;
+ RECT 1236.830000 345.760000 1237.830000 546.020000 ;
+ RECT 1137.520000 348.610000 1138.620000 541.980000 ;
+ RECT 1092.520000 348.610000 1093.620000 541.980000 ;
+ RECT 1047.520000 348.610000 1048.620000 541.980000 ;
+ RECT 1043.390000 345.760000 1044.390000 546.020000 ;
+ LAYER met3 ;
+ RECT 1227.520000 535.580000 1228.620000 536.060000 ;
+ RECT 1236.830000 535.580000 1237.830000 536.060000 ;
+ RECT 1236.830000 524.700000 1237.830000 525.180000 ;
+ RECT 1236.830000 530.140000 1237.830000 530.620000 ;
+ RECT 1227.520000 530.140000 1228.620000 530.620000 ;
+ RECT 1227.520000 524.700000 1228.620000 525.180000 ;
+ RECT 1227.520000 519.260000 1228.620000 519.740000 ;
+ RECT 1227.520000 513.820000 1228.620000 514.300000 ;
+ RECT 1236.830000 519.260000 1237.830000 519.740000 ;
+ RECT 1236.830000 513.820000 1237.830000 514.300000 ;
+ RECT 1227.520000 497.500000 1228.620000 497.980000 ;
+ RECT 1227.520000 502.940000 1228.620000 503.420000 ;
+ RECT 1236.830000 502.940000 1237.830000 503.420000 ;
+ RECT 1236.830000 497.500000 1237.830000 497.980000 ;
+ RECT 1227.520000 508.380000 1228.620000 508.860000 ;
+ RECT 1236.830000 508.380000 1237.830000 508.860000 ;
+ RECT 1182.520000 535.580000 1183.620000 536.060000 ;
+ RECT 1182.520000 530.140000 1183.620000 530.620000 ;
+ RECT 1182.520000 524.700000 1183.620000 525.180000 ;
+ RECT 1182.520000 519.260000 1183.620000 519.740000 ;
+ RECT 1182.520000 497.500000 1183.620000 497.980000 ;
+ RECT 1182.520000 502.940000 1183.620000 503.420000 ;
+ RECT 1182.520000 508.380000 1183.620000 508.860000 ;
+ RECT 1182.520000 513.820000 1183.620000 514.300000 ;
+ RECT 1236.830000 486.620000 1237.830000 487.100000 ;
+ RECT 1236.830000 492.060000 1237.830000 492.540000 ;
+ RECT 1227.520000 492.060000 1228.620000 492.540000 ;
+ RECT 1227.520000 486.620000 1228.620000 487.100000 ;
+ RECT 1227.520000 481.180000 1228.620000 481.660000 ;
+ RECT 1227.520000 475.740000 1228.620000 476.220000 ;
+ RECT 1236.830000 481.180000 1237.830000 481.660000 ;
+ RECT 1236.830000 475.740000 1237.830000 476.220000 ;
+ RECT 1236.830000 459.420000 1237.830000 459.900000 ;
+ RECT 1236.830000 464.860000 1237.830000 465.340000 ;
+ RECT 1236.830000 470.300000 1237.830000 470.780000 ;
+ RECT 1227.520000 464.860000 1228.620000 465.340000 ;
+ RECT 1227.520000 459.420000 1228.620000 459.900000 ;
+ RECT 1227.520000 470.300000 1228.620000 470.780000 ;
+ RECT 1227.520000 453.980000 1228.620000 454.460000 ;
+ RECT 1227.520000 448.540000 1228.620000 449.020000 ;
+ RECT 1236.830000 453.980000 1237.830000 454.460000 ;
+ RECT 1236.830000 448.540000 1237.830000 449.020000 ;
+ RECT 1182.520000 492.060000 1183.620000 492.540000 ;
+ RECT 1182.520000 486.620000 1183.620000 487.100000 ;
+ RECT 1182.520000 481.180000 1183.620000 481.660000 ;
+ RECT 1182.520000 475.740000 1183.620000 476.220000 ;
+ RECT 1182.520000 464.860000 1183.620000 465.340000 ;
+ RECT 1182.520000 459.420000 1183.620000 459.900000 ;
+ RECT 1182.520000 453.980000 1183.620000 454.460000 ;
+ RECT 1182.520000 448.540000 1183.620000 449.020000 ;
+ RECT 1182.520000 470.300000 1183.620000 470.780000 ;
+ RECT 1137.520000 535.580000 1138.620000 536.060000 ;
+ RECT 1137.520000 530.140000 1138.620000 530.620000 ;
+ RECT 1137.520000 524.700000 1138.620000 525.180000 ;
+ RECT 1092.520000 535.580000 1093.620000 536.060000 ;
+ RECT 1092.520000 530.140000 1093.620000 530.620000 ;
+ RECT 1092.520000 524.700000 1093.620000 525.180000 ;
+ RECT 1137.520000 508.380000 1138.620000 508.860000 ;
+ RECT 1137.520000 502.940000 1138.620000 503.420000 ;
+ RECT 1137.520000 497.500000 1138.620000 497.980000 ;
+ RECT 1137.520000 513.820000 1138.620000 514.300000 ;
+ RECT 1137.520000 519.260000 1138.620000 519.740000 ;
+ RECT 1092.520000 519.260000 1093.620000 519.740000 ;
+ RECT 1092.520000 508.380000 1093.620000 508.860000 ;
+ RECT 1092.520000 502.940000 1093.620000 503.420000 ;
+ RECT 1092.520000 497.500000 1093.620000 497.980000 ;
+ RECT 1092.520000 513.820000 1093.620000 514.300000 ;
+ RECT 1047.520000 535.580000 1048.620000 536.060000 ;
+ RECT 1043.390000 535.580000 1044.390000 536.060000 ;
+ RECT 1043.390000 530.140000 1044.390000 530.620000 ;
+ RECT 1047.520000 530.140000 1048.620000 530.620000 ;
+ RECT 1047.520000 524.700000 1048.620000 525.180000 ;
+ RECT 1043.390000 524.700000 1044.390000 525.180000 ;
+ RECT 1047.520000 519.260000 1048.620000 519.740000 ;
+ RECT 1043.390000 519.260000 1044.390000 519.740000 ;
+ RECT 1047.520000 513.820000 1048.620000 514.300000 ;
+ RECT 1043.390000 513.820000 1044.390000 514.300000 ;
+ RECT 1047.520000 502.940000 1048.620000 503.420000 ;
+ RECT 1043.390000 502.940000 1044.390000 503.420000 ;
+ RECT 1047.520000 497.500000 1048.620000 497.980000 ;
+ RECT 1043.390000 497.500000 1044.390000 497.980000 ;
+ RECT 1047.520000 508.380000 1048.620000 508.860000 ;
+ RECT 1043.390000 508.380000 1044.390000 508.860000 ;
+ RECT 1137.520000 492.060000 1138.620000 492.540000 ;
+ RECT 1137.520000 486.620000 1138.620000 487.100000 ;
+ RECT 1137.520000 481.180000 1138.620000 481.660000 ;
+ RECT 1137.520000 475.740000 1138.620000 476.220000 ;
+ RECT 1092.520000 492.060000 1093.620000 492.540000 ;
+ RECT 1092.520000 486.620000 1093.620000 487.100000 ;
+ RECT 1092.520000 481.180000 1093.620000 481.660000 ;
+ RECT 1092.520000 475.740000 1093.620000 476.220000 ;
+ RECT 1137.520000 464.860000 1138.620000 465.340000 ;
+ RECT 1137.520000 448.540000 1138.620000 449.020000 ;
+ RECT 1137.520000 453.980000 1138.620000 454.460000 ;
+ RECT 1137.520000 459.420000 1138.620000 459.900000 ;
+ RECT 1137.520000 470.300000 1138.620000 470.780000 ;
+ RECT 1092.520000 448.540000 1093.620000 449.020000 ;
+ RECT 1092.520000 453.980000 1093.620000 454.460000 ;
+ RECT 1092.520000 459.420000 1093.620000 459.900000 ;
+ RECT 1092.520000 464.860000 1093.620000 465.340000 ;
+ RECT 1092.520000 470.300000 1093.620000 470.780000 ;
+ RECT 1047.520000 492.060000 1048.620000 492.540000 ;
+ RECT 1043.390000 492.060000 1044.390000 492.540000 ;
+ RECT 1047.520000 486.620000 1048.620000 487.100000 ;
+ RECT 1043.390000 486.620000 1044.390000 487.100000 ;
+ RECT 1047.520000 481.180000 1048.620000 481.660000 ;
+ RECT 1043.390000 481.180000 1044.390000 481.660000 ;
+ RECT 1047.520000 475.740000 1048.620000 476.220000 ;
+ RECT 1043.390000 475.740000 1044.390000 476.220000 ;
+ RECT 1047.520000 470.300000 1048.620000 470.780000 ;
+ RECT 1047.520000 464.860000 1048.620000 465.340000 ;
+ RECT 1043.390000 470.300000 1044.390000 470.780000 ;
+ RECT 1043.390000 464.860000 1044.390000 465.340000 ;
+ RECT 1047.520000 459.420000 1048.620000 459.900000 ;
+ RECT 1043.390000 459.420000 1044.390000 459.900000 ;
+ RECT 1047.520000 453.980000 1048.620000 454.460000 ;
+ RECT 1043.390000 453.980000 1044.390000 454.460000 ;
+ RECT 1047.520000 448.540000 1048.620000 449.020000 ;
+ RECT 1043.390000 448.540000 1044.390000 449.020000 ;
+ RECT 1227.520000 443.100000 1228.620000 443.580000 ;
+ RECT 1227.520000 437.660000 1228.620000 438.140000 ;
+ RECT 1236.830000 443.100000 1237.830000 443.580000 ;
+ RECT 1236.830000 437.660000 1237.830000 438.140000 ;
+ RECT 1236.830000 421.340000 1237.830000 421.820000 ;
+ RECT 1236.830000 426.780000 1237.830000 427.260000 ;
+ RECT 1236.830000 432.220000 1237.830000 432.700000 ;
+ RECT 1227.520000 432.220000 1228.620000 432.700000 ;
+ RECT 1227.520000 426.780000 1228.620000 427.260000 ;
+ RECT 1227.520000 421.340000 1228.620000 421.820000 ;
+ RECT 1227.520000 410.460000 1228.620000 410.940000 ;
+ RECT 1227.520000 415.900000 1228.620000 416.380000 ;
+ RECT 1236.830000 415.900000 1237.830000 416.380000 ;
+ RECT 1236.830000 410.460000 1237.830000 410.940000 ;
+ RECT 1236.830000 399.580000 1237.830000 400.060000 ;
+ RECT 1236.830000 405.020000 1237.830000 405.500000 ;
+ RECT 1227.520000 399.580000 1228.620000 400.060000 ;
+ RECT 1227.520000 405.020000 1228.620000 405.500000 ;
+ RECT 1182.520000 443.100000 1183.620000 443.580000 ;
+ RECT 1182.520000 437.660000 1183.620000 438.140000 ;
+ RECT 1182.520000 432.220000 1183.620000 432.700000 ;
+ RECT 1182.520000 426.780000 1183.620000 427.260000 ;
+ RECT 1182.520000 421.340000 1183.620000 421.820000 ;
+ RECT 1182.520000 399.580000 1183.620000 400.060000 ;
+ RECT 1182.520000 405.020000 1183.620000 405.500000 ;
+ RECT 1182.520000 410.460000 1183.620000 410.940000 ;
+ RECT 1182.520000 415.900000 1183.620000 416.380000 ;
+ RECT 1227.520000 394.140000 1228.620000 394.620000 ;
+ RECT 1227.520000 388.700000 1228.620000 389.180000 ;
+ RECT 1236.830000 394.140000 1237.830000 394.620000 ;
+ RECT 1236.830000 388.700000 1237.830000 389.180000 ;
+ RECT 1227.520000 377.820000 1228.620000 378.300000 ;
+ RECT 1227.520000 372.380000 1228.620000 372.860000 ;
+ RECT 1236.830000 377.820000 1237.830000 378.300000 ;
+ RECT 1236.830000 372.380000 1237.830000 372.860000 ;
+ RECT 1227.520000 383.260000 1228.620000 383.740000 ;
+ RECT 1236.830000 383.260000 1237.830000 383.740000 ;
+ RECT 1236.830000 361.500000 1237.830000 361.980000 ;
+ RECT 1236.830000 366.940000 1237.830000 367.420000 ;
+ RECT 1227.520000 366.940000 1228.620000 367.420000 ;
+ RECT 1227.520000 361.500000 1228.620000 361.980000 ;
+ RECT 1227.520000 356.060000 1228.620000 356.540000 ;
+ RECT 1227.520000 350.620000 1228.620000 351.100000 ;
+ RECT 1236.830000 356.060000 1237.830000 356.540000 ;
+ RECT 1236.830000 350.620000 1237.830000 351.100000 ;
+ RECT 1182.520000 394.140000 1183.620000 394.620000 ;
+ RECT 1182.520000 388.700000 1183.620000 389.180000 ;
+ RECT 1182.520000 383.260000 1183.620000 383.740000 ;
+ RECT 1182.520000 377.820000 1183.620000 378.300000 ;
+ RECT 1182.520000 372.380000 1183.620000 372.860000 ;
+ RECT 1182.520000 366.940000 1183.620000 367.420000 ;
+ RECT 1182.520000 361.500000 1183.620000 361.980000 ;
+ RECT 1182.520000 356.060000 1183.620000 356.540000 ;
+ RECT 1182.520000 350.620000 1183.620000 351.100000 ;
+ RECT 1137.520000 443.100000 1138.620000 443.580000 ;
+ RECT 1137.520000 437.660000 1138.620000 438.140000 ;
+ RECT 1137.520000 432.220000 1138.620000 432.700000 ;
+ RECT 1137.520000 426.780000 1138.620000 427.260000 ;
+ RECT 1137.520000 421.340000 1138.620000 421.820000 ;
+ RECT 1092.520000 443.100000 1093.620000 443.580000 ;
+ RECT 1092.520000 437.660000 1093.620000 438.140000 ;
+ RECT 1092.520000 432.220000 1093.620000 432.700000 ;
+ RECT 1092.520000 426.780000 1093.620000 427.260000 ;
+ RECT 1092.520000 421.340000 1093.620000 421.820000 ;
+ RECT 1137.520000 415.900000 1138.620000 416.380000 ;
+ RECT 1137.520000 410.460000 1138.620000 410.940000 ;
+ RECT 1137.520000 405.020000 1138.620000 405.500000 ;
+ RECT 1137.520000 399.580000 1138.620000 400.060000 ;
+ RECT 1092.520000 410.460000 1093.620000 410.940000 ;
+ RECT 1092.520000 405.020000 1093.620000 405.500000 ;
+ RECT 1092.520000 399.580000 1093.620000 400.060000 ;
+ RECT 1092.520000 415.900000 1093.620000 416.380000 ;
+ RECT 1047.520000 443.100000 1048.620000 443.580000 ;
+ RECT 1043.390000 443.100000 1044.390000 443.580000 ;
+ RECT 1047.520000 437.660000 1048.620000 438.140000 ;
+ RECT 1043.390000 437.660000 1044.390000 438.140000 ;
+ RECT 1047.520000 432.220000 1048.620000 432.700000 ;
+ RECT 1043.390000 432.220000 1044.390000 432.700000 ;
+ RECT 1047.520000 421.340000 1048.620000 421.820000 ;
+ RECT 1043.390000 421.340000 1044.390000 421.820000 ;
+ RECT 1043.390000 426.780000 1044.390000 427.260000 ;
+ RECT 1047.520000 426.780000 1048.620000 427.260000 ;
+ RECT 1047.520000 415.900000 1048.620000 416.380000 ;
+ RECT 1043.390000 415.900000 1044.390000 416.380000 ;
+ RECT 1047.520000 410.460000 1048.620000 410.940000 ;
+ RECT 1043.390000 410.460000 1044.390000 410.940000 ;
+ RECT 1047.520000 405.020000 1048.620000 405.500000 ;
+ RECT 1043.390000 405.020000 1044.390000 405.500000 ;
+ RECT 1047.520000 399.580000 1048.620000 400.060000 ;
+ RECT 1043.390000 399.580000 1044.390000 400.060000 ;
+ RECT 1137.520000 394.140000 1138.620000 394.620000 ;
+ RECT 1137.520000 388.700000 1138.620000 389.180000 ;
+ RECT 1137.520000 383.260000 1138.620000 383.740000 ;
+ RECT 1137.520000 377.820000 1138.620000 378.300000 ;
+ RECT 1137.520000 372.380000 1138.620000 372.860000 ;
+ RECT 1092.520000 394.140000 1093.620000 394.620000 ;
+ RECT 1092.520000 388.700000 1093.620000 389.180000 ;
+ RECT 1092.520000 383.260000 1093.620000 383.740000 ;
+ RECT 1092.520000 377.820000 1093.620000 378.300000 ;
+ RECT 1092.520000 372.380000 1093.620000 372.860000 ;
+ RECT 1137.520000 350.620000 1138.620000 351.100000 ;
+ RECT 1137.520000 356.060000 1138.620000 356.540000 ;
+ RECT 1137.520000 361.500000 1138.620000 361.980000 ;
+ RECT 1137.520000 366.940000 1138.620000 367.420000 ;
+ RECT 1092.520000 350.620000 1093.620000 351.100000 ;
+ RECT 1092.520000 356.060000 1093.620000 356.540000 ;
+ RECT 1092.520000 361.500000 1093.620000 361.980000 ;
+ RECT 1092.520000 366.940000 1093.620000 367.420000 ;
+ RECT 1047.520000 394.140000 1048.620000 394.620000 ;
+ RECT 1043.390000 394.140000 1044.390000 394.620000 ;
+ RECT 1047.520000 388.700000 1048.620000 389.180000 ;
+ RECT 1043.390000 388.700000 1044.390000 389.180000 ;
+ RECT 1047.520000 377.820000 1048.620000 378.300000 ;
+ RECT 1043.390000 377.820000 1044.390000 378.300000 ;
+ RECT 1047.520000 372.380000 1048.620000 372.860000 ;
+ RECT 1043.390000 372.380000 1044.390000 372.860000 ;
+ RECT 1047.520000 383.260000 1048.620000 383.740000 ;
+ RECT 1043.390000 383.260000 1044.390000 383.740000 ;
+ RECT 1047.520000 366.940000 1048.620000 367.420000 ;
+ RECT 1043.390000 366.940000 1044.390000 367.420000 ;
+ RECT 1047.520000 361.500000 1048.620000 361.980000 ;
+ RECT 1043.390000 361.500000 1044.390000 361.980000 ;
+ RECT 1047.520000 356.060000 1048.620000 356.540000 ;
+ RECT 1047.520000 350.620000 1048.620000 351.100000 ;
+ RECT 1043.390000 356.060000 1044.390000 356.540000 ;
+ RECT 1043.390000 350.620000 1044.390000 351.100000 ;
+ RECT 1040.560000 540.980000 1240.660000 541.980000 ;
+ RECT 1040.560000 348.610000 1240.660000 349.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 345.760000 1044.390000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 545.020000 1044.390000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 345.760000 1237.830000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 545.020000 1237.830000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 348.610000 1041.560000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 348.610000 1240.660000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 540.980000 1041.560000 541.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 540.980000 1240.660000 541.980000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 148.350000 1228.620000 341.720000 ;
+ RECT 1182.520000 148.350000 1183.620000 341.720000 ;
+ RECT 1236.830000 145.500000 1237.830000 345.760000 ;
+ RECT 1137.520000 148.350000 1138.620000 341.720000 ;
+ RECT 1092.520000 148.350000 1093.620000 341.720000 ;
+ RECT 1047.520000 148.350000 1048.620000 341.720000 ;
+ RECT 1043.390000 145.500000 1044.390000 345.760000 ;
+ LAYER met3 ;
+ RECT 1227.520000 335.320000 1228.620000 335.800000 ;
+ RECT 1236.830000 335.320000 1237.830000 335.800000 ;
+ RECT 1236.830000 324.440000 1237.830000 324.920000 ;
+ RECT 1236.830000 329.880000 1237.830000 330.360000 ;
+ RECT 1227.520000 329.880000 1228.620000 330.360000 ;
+ RECT 1227.520000 324.440000 1228.620000 324.920000 ;
+ RECT 1227.520000 319.000000 1228.620000 319.480000 ;
+ RECT 1227.520000 313.560000 1228.620000 314.040000 ;
+ RECT 1236.830000 319.000000 1237.830000 319.480000 ;
+ RECT 1236.830000 313.560000 1237.830000 314.040000 ;
+ RECT 1227.520000 297.240000 1228.620000 297.720000 ;
+ RECT 1227.520000 302.680000 1228.620000 303.160000 ;
+ RECT 1236.830000 302.680000 1237.830000 303.160000 ;
+ RECT 1236.830000 297.240000 1237.830000 297.720000 ;
+ RECT 1227.520000 308.120000 1228.620000 308.600000 ;
+ RECT 1236.830000 308.120000 1237.830000 308.600000 ;
+ RECT 1182.520000 335.320000 1183.620000 335.800000 ;
+ RECT 1182.520000 329.880000 1183.620000 330.360000 ;
+ RECT 1182.520000 324.440000 1183.620000 324.920000 ;
+ RECT 1182.520000 319.000000 1183.620000 319.480000 ;
+ RECT 1182.520000 297.240000 1183.620000 297.720000 ;
+ RECT 1182.520000 302.680000 1183.620000 303.160000 ;
+ RECT 1182.520000 308.120000 1183.620000 308.600000 ;
+ RECT 1182.520000 313.560000 1183.620000 314.040000 ;
+ RECT 1236.830000 286.360000 1237.830000 286.840000 ;
+ RECT 1236.830000 291.800000 1237.830000 292.280000 ;
+ RECT 1227.520000 291.800000 1228.620000 292.280000 ;
+ RECT 1227.520000 286.360000 1228.620000 286.840000 ;
+ RECT 1227.520000 280.920000 1228.620000 281.400000 ;
+ RECT 1227.520000 275.480000 1228.620000 275.960000 ;
+ RECT 1236.830000 280.920000 1237.830000 281.400000 ;
+ RECT 1236.830000 275.480000 1237.830000 275.960000 ;
+ RECT 1236.830000 259.160000 1237.830000 259.640000 ;
+ RECT 1236.830000 264.600000 1237.830000 265.080000 ;
+ RECT 1236.830000 270.040000 1237.830000 270.520000 ;
+ RECT 1227.520000 264.600000 1228.620000 265.080000 ;
+ RECT 1227.520000 259.160000 1228.620000 259.640000 ;
+ RECT 1227.520000 270.040000 1228.620000 270.520000 ;
+ RECT 1227.520000 253.720000 1228.620000 254.200000 ;
+ RECT 1227.520000 248.280000 1228.620000 248.760000 ;
+ RECT 1236.830000 253.720000 1237.830000 254.200000 ;
+ RECT 1236.830000 248.280000 1237.830000 248.760000 ;
+ RECT 1182.520000 291.800000 1183.620000 292.280000 ;
+ RECT 1182.520000 286.360000 1183.620000 286.840000 ;
+ RECT 1182.520000 280.920000 1183.620000 281.400000 ;
+ RECT 1182.520000 275.480000 1183.620000 275.960000 ;
+ RECT 1182.520000 264.600000 1183.620000 265.080000 ;
+ RECT 1182.520000 259.160000 1183.620000 259.640000 ;
+ RECT 1182.520000 253.720000 1183.620000 254.200000 ;
+ RECT 1182.520000 248.280000 1183.620000 248.760000 ;
+ RECT 1182.520000 270.040000 1183.620000 270.520000 ;
+ RECT 1137.520000 335.320000 1138.620000 335.800000 ;
+ RECT 1137.520000 329.880000 1138.620000 330.360000 ;
+ RECT 1137.520000 324.440000 1138.620000 324.920000 ;
+ RECT 1092.520000 335.320000 1093.620000 335.800000 ;
+ RECT 1092.520000 329.880000 1093.620000 330.360000 ;
+ RECT 1092.520000 324.440000 1093.620000 324.920000 ;
+ RECT 1137.520000 308.120000 1138.620000 308.600000 ;
+ RECT 1137.520000 302.680000 1138.620000 303.160000 ;
+ RECT 1137.520000 297.240000 1138.620000 297.720000 ;
+ RECT 1137.520000 313.560000 1138.620000 314.040000 ;
+ RECT 1137.520000 319.000000 1138.620000 319.480000 ;
+ RECT 1092.520000 319.000000 1093.620000 319.480000 ;
+ RECT 1092.520000 308.120000 1093.620000 308.600000 ;
+ RECT 1092.520000 302.680000 1093.620000 303.160000 ;
+ RECT 1092.520000 297.240000 1093.620000 297.720000 ;
+ RECT 1092.520000 313.560000 1093.620000 314.040000 ;
+ RECT 1047.520000 335.320000 1048.620000 335.800000 ;
+ RECT 1043.390000 335.320000 1044.390000 335.800000 ;
+ RECT 1043.390000 329.880000 1044.390000 330.360000 ;
+ RECT 1047.520000 329.880000 1048.620000 330.360000 ;
+ RECT 1047.520000 324.440000 1048.620000 324.920000 ;
+ RECT 1043.390000 324.440000 1044.390000 324.920000 ;
+ RECT 1047.520000 319.000000 1048.620000 319.480000 ;
+ RECT 1043.390000 319.000000 1044.390000 319.480000 ;
+ RECT 1047.520000 313.560000 1048.620000 314.040000 ;
+ RECT 1043.390000 313.560000 1044.390000 314.040000 ;
+ RECT 1047.520000 302.680000 1048.620000 303.160000 ;
+ RECT 1043.390000 302.680000 1044.390000 303.160000 ;
+ RECT 1047.520000 297.240000 1048.620000 297.720000 ;
+ RECT 1043.390000 297.240000 1044.390000 297.720000 ;
+ RECT 1047.520000 308.120000 1048.620000 308.600000 ;
+ RECT 1043.390000 308.120000 1044.390000 308.600000 ;
+ RECT 1137.520000 291.800000 1138.620000 292.280000 ;
+ RECT 1137.520000 286.360000 1138.620000 286.840000 ;
+ RECT 1137.520000 280.920000 1138.620000 281.400000 ;
+ RECT 1137.520000 275.480000 1138.620000 275.960000 ;
+ RECT 1092.520000 291.800000 1093.620000 292.280000 ;
+ RECT 1092.520000 286.360000 1093.620000 286.840000 ;
+ RECT 1092.520000 280.920000 1093.620000 281.400000 ;
+ RECT 1092.520000 275.480000 1093.620000 275.960000 ;
+ RECT 1137.520000 264.600000 1138.620000 265.080000 ;
+ RECT 1137.520000 248.280000 1138.620000 248.760000 ;
+ RECT 1137.520000 253.720000 1138.620000 254.200000 ;
+ RECT 1137.520000 259.160000 1138.620000 259.640000 ;
+ RECT 1137.520000 270.040000 1138.620000 270.520000 ;
+ RECT 1092.520000 248.280000 1093.620000 248.760000 ;
+ RECT 1092.520000 253.720000 1093.620000 254.200000 ;
+ RECT 1092.520000 259.160000 1093.620000 259.640000 ;
+ RECT 1092.520000 264.600000 1093.620000 265.080000 ;
+ RECT 1092.520000 270.040000 1093.620000 270.520000 ;
+ RECT 1047.520000 291.800000 1048.620000 292.280000 ;
+ RECT 1043.390000 291.800000 1044.390000 292.280000 ;
+ RECT 1047.520000 286.360000 1048.620000 286.840000 ;
+ RECT 1043.390000 286.360000 1044.390000 286.840000 ;
+ RECT 1047.520000 280.920000 1048.620000 281.400000 ;
+ RECT 1043.390000 280.920000 1044.390000 281.400000 ;
+ RECT 1047.520000 275.480000 1048.620000 275.960000 ;
+ RECT 1043.390000 275.480000 1044.390000 275.960000 ;
+ RECT 1047.520000 270.040000 1048.620000 270.520000 ;
+ RECT 1047.520000 264.600000 1048.620000 265.080000 ;
+ RECT 1043.390000 270.040000 1044.390000 270.520000 ;
+ RECT 1043.390000 264.600000 1044.390000 265.080000 ;
+ RECT 1047.520000 259.160000 1048.620000 259.640000 ;
+ RECT 1043.390000 259.160000 1044.390000 259.640000 ;
+ RECT 1047.520000 253.720000 1048.620000 254.200000 ;
+ RECT 1043.390000 253.720000 1044.390000 254.200000 ;
+ RECT 1047.520000 248.280000 1048.620000 248.760000 ;
+ RECT 1043.390000 248.280000 1044.390000 248.760000 ;
+ RECT 1227.520000 242.840000 1228.620000 243.320000 ;
+ RECT 1227.520000 237.400000 1228.620000 237.880000 ;
+ RECT 1236.830000 242.840000 1237.830000 243.320000 ;
+ RECT 1236.830000 237.400000 1237.830000 237.880000 ;
+ RECT 1236.830000 221.080000 1237.830000 221.560000 ;
+ RECT 1236.830000 226.520000 1237.830000 227.000000 ;
+ RECT 1236.830000 231.960000 1237.830000 232.440000 ;
+ RECT 1227.520000 231.960000 1228.620000 232.440000 ;
+ RECT 1227.520000 226.520000 1228.620000 227.000000 ;
+ RECT 1227.520000 221.080000 1228.620000 221.560000 ;
+ RECT 1227.520000 210.200000 1228.620000 210.680000 ;
+ RECT 1227.520000 215.640000 1228.620000 216.120000 ;
+ RECT 1236.830000 215.640000 1237.830000 216.120000 ;
+ RECT 1236.830000 210.200000 1237.830000 210.680000 ;
+ RECT 1236.830000 199.320000 1237.830000 199.800000 ;
+ RECT 1236.830000 204.760000 1237.830000 205.240000 ;
+ RECT 1227.520000 199.320000 1228.620000 199.800000 ;
+ RECT 1227.520000 204.760000 1228.620000 205.240000 ;
+ RECT 1182.520000 242.840000 1183.620000 243.320000 ;
+ RECT 1182.520000 237.400000 1183.620000 237.880000 ;
+ RECT 1182.520000 231.960000 1183.620000 232.440000 ;
+ RECT 1182.520000 226.520000 1183.620000 227.000000 ;
+ RECT 1182.520000 221.080000 1183.620000 221.560000 ;
+ RECT 1182.520000 199.320000 1183.620000 199.800000 ;
+ RECT 1182.520000 204.760000 1183.620000 205.240000 ;
+ RECT 1182.520000 210.200000 1183.620000 210.680000 ;
+ RECT 1182.520000 215.640000 1183.620000 216.120000 ;
+ RECT 1227.520000 193.880000 1228.620000 194.360000 ;
+ RECT 1227.520000 188.440000 1228.620000 188.920000 ;
+ RECT 1236.830000 193.880000 1237.830000 194.360000 ;
+ RECT 1236.830000 188.440000 1237.830000 188.920000 ;
+ RECT 1227.520000 177.560000 1228.620000 178.040000 ;
+ RECT 1227.520000 172.120000 1228.620000 172.600000 ;
+ RECT 1236.830000 177.560000 1237.830000 178.040000 ;
+ RECT 1236.830000 172.120000 1237.830000 172.600000 ;
+ RECT 1227.520000 183.000000 1228.620000 183.480000 ;
+ RECT 1236.830000 183.000000 1237.830000 183.480000 ;
+ RECT 1236.830000 161.240000 1237.830000 161.720000 ;
+ RECT 1236.830000 166.680000 1237.830000 167.160000 ;
+ RECT 1227.520000 166.680000 1228.620000 167.160000 ;
+ RECT 1227.520000 161.240000 1228.620000 161.720000 ;
+ RECT 1227.520000 155.800000 1228.620000 156.280000 ;
+ RECT 1227.520000 150.360000 1228.620000 150.840000 ;
+ RECT 1236.830000 155.800000 1237.830000 156.280000 ;
+ RECT 1236.830000 150.360000 1237.830000 150.840000 ;
+ RECT 1182.520000 193.880000 1183.620000 194.360000 ;
+ RECT 1182.520000 188.440000 1183.620000 188.920000 ;
+ RECT 1182.520000 183.000000 1183.620000 183.480000 ;
+ RECT 1182.520000 177.560000 1183.620000 178.040000 ;
+ RECT 1182.520000 172.120000 1183.620000 172.600000 ;
+ RECT 1182.520000 166.680000 1183.620000 167.160000 ;
+ RECT 1182.520000 161.240000 1183.620000 161.720000 ;
+ RECT 1182.520000 155.800000 1183.620000 156.280000 ;
+ RECT 1182.520000 150.360000 1183.620000 150.840000 ;
+ RECT 1137.520000 242.840000 1138.620000 243.320000 ;
+ RECT 1137.520000 237.400000 1138.620000 237.880000 ;
+ RECT 1137.520000 231.960000 1138.620000 232.440000 ;
+ RECT 1137.520000 226.520000 1138.620000 227.000000 ;
+ RECT 1137.520000 221.080000 1138.620000 221.560000 ;
+ RECT 1092.520000 242.840000 1093.620000 243.320000 ;
+ RECT 1092.520000 237.400000 1093.620000 237.880000 ;
+ RECT 1092.520000 231.960000 1093.620000 232.440000 ;
+ RECT 1092.520000 226.520000 1093.620000 227.000000 ;
+ RECT 1092.520000 221.080000 1093.620000 221.560000 ;
+ RECT 1137.520000 215.640000 1138.620000 216.120000 ;
+ RECT 1137.520000 210.200000 1138.620000 210.680000 ;
+ RECT 1137.520000 204.760000 1138.620000 205.240000 ;
+ RECT 1137.520000 199.320000 1138.620000 199.800000 ;
+ RECT 1092.520000 210.200000 1093.620000 210.680000 ;
+ RECT 1092.520000 204.760000 1093.620000 205.240000 ;
+ RECT 1092.520000 199.320000 1093.620000 199.800000 ;
+ RECT 1092.520000 215.640000 1093.620000 216.120000 ;
+ RECT 1047.520000 242.840000 1048.620000 243.320000 ;
+ RECT 1043.390000 242.840000 1044.390000 243.320000 ;
+ RECT 1047.520000 237.400000 1048.620000 237.880000 ;
+ RECT 1043.390000 237.400000 1044.390000 237.880000 ;
+ RECT 1047.520000 231.960000 1048.620000 232.440000 ;
+ RECT 1043.390000 231.960000 1044.390000 232.440000 ;
+ RECT 1047.520000 221.080000 1048.620000 221.560000 ;
+ RECT 1043.390000 221.080000 1044.390000 221.560000 ;
+ RECT 1043.390000 226.520000 1044.390000 227.000000 ;
+ RECT 1047.520000 226.520000 1048.620000 227.000000 ;
+ RECT 1047.520000 215.640000 1048.620000 216.120000 ;
+ RECT 1043.390000 215.640000 1044.390000 216.120000 ;
+ RECT 1047.520000 210.200000 1048.620000 210.680000 ;
+ RECT 1043.390000 210.200000 1044.390000 210.680000 ;
+ RECT 1047.520000 204.760000 1048.620000 205.240000 ;
+ RECT 1043.390000 204.760000 1044.390000 205.240000 ;
+ RECT 1047.520000 199.320000 1048.620000 199.800000 ;
+ RECT 1043.390000 199.320000 1044.390000 199.800000 ;
+ RECT 1137.520000 193.880000 1138.620000 194.360000 ;
+ RECT 1137.520000 188.440000 1138.620000 188.920000 ;
+ RECT 1137.520000 183.000000 1138.620000 183.480000 ;
+ RECT 1137.520000 177.560000 1138.620000 178.040000 ;
+ RECT 1137.520000 172.120000 1138.620000 172.600000 ;
+ RECT 1092.520000 193.880000 1093.620000 194.360000 ;
+ RECT 1092.520000 188.440000 1093.620000 188.920000 ;
+ RECT 1092.520000 183.000000 1093.620000 183.480000 ;
+ RECT 1092.520000 177.560000 1093.620000 178.040000 ;
+ RECT 1092.520000 172.120000 1093.620000 172.600000 ;
+ RECT 1137.520000 150.360000 1138.620000 150.840000 ;
+ RECT 1137.520000 155.800000 1138.620000 156.280000 ;
+ RECT 1137.520000 161.240000 1138.620000 161.720000 ;
+ RECT 1137.520000 166.680000 1138.620000 167.160000 ;
+ RECT 1092.520000 150.360000 1093.620000 150.840000 ;
+ RECT 1092.520000 155.800000 1093.620000 156.280000 ;
+ RECT 1092.520000 161.240000 1093.620000 161.720000 ;
+ RECT 1092.520000 166.680000 1093.620000 167.160000 ;
+ RECT 1047.520000 193.880000 1048.620000 194.360000 ;
+ RECT 1043.390000 193.880000 1044.390000 194.360000 ;
+ RECT 1047.520000 188.440000 1048.620000 188.920000 ;
+ RECT 1043.390000 188.440000 1044.390000 188.920000 ;
+ RECT 1047.520000 177.560000 1048.620000 178.040000 ;
+ RECT 1043.390000 177.560000 1044.390000 178.040000 ;
+ RECT 1047.520000 172.120000 1048.620000 172.600000 ;
+ RECT 1043.390000 172.120000 1044.390000 172.600000 ;
+ RECT 1047.520000 183.000000 1048.620000 183.480000 ;
+ RECT 1043.390000 183.000000 1044.390000 183.480000 ;
+ RECT 1047.520000 166.680000 1048.620000 167.160000 ;
+ RECT 1043.390000 166.680000 1044.390000 167.160000 ;
+ RECT 1047.520000 161.240000 1048.620000 161.720000 ;
+ RECT 1043.390000 161.240000 1044.390000 161.720000 ;
+ RECT 1047.520000 155.800000 1048.620000 156.280000 ;
+ RECT 1047.520000 150.360000 1048.620000 150.840000 ;
+ RECT 1043.390000 155.800000 1044.390000 156.280000 ;
+ RECT 1043.390000 150.360000 1044.390000 150.840000 ;
+ RECT 1040.560000 340.720000 1240.660000 341.720000 ;
+ RECT 1040.560000 148.350000 1240.660000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 145.500000 1044.390000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 344.760000 1044.390000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 145.500000 1237.830000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 344.760000 1237.830000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 148.350000 1041.560000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 148.350000 1240.660000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 340.720000 1041.560000 341.720000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 340.720000 1240.660000 341.720000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 115.240000 1044.390000 145.500000 ;
+ RECT 1236.830000 115.240000 1237.830000 145.500000 ;
+ RECT 1047.520000 118.090000 1048.620000 142.140000 ;
+ RECT 1092.520000 118.090000 1093.620000 142.140000 ;
+ RECT 1137.520000 118.090000 1138.620000 142.140000 ;
+ RECT 1182.520000 118.090000 1183.620000 142.140000 ;
+ RECT 1227.520000 118.090000 1228.620000 142.140000 ;
+ LAYER met3 ;
+ RECT 1236.830000 130.980000 1237.830000 131.460000 ;
+ RECT 1236.830000 136.420000 1237.830000 136.900000 ;
+ RECT 1227.520000 136.420000 1228.620000 136.900000 ;
+ RECT 1227.520000 130.980000 1228.620000 131.460000 ;
+ RECT 1182.520000 130.980000 1183.620000 131.460000 ;
+ RECT 1182.520000 136.420000 1183.620000 136.900000 ;
+ RECT 1092.520000 130.980000 1093.620000 131.460000 ;
+ RECT 1137.520000 130.980000 1138.620000 131.460000 ;
+ RECT 1137.520000 136.420000 1138.620000 136.900000 ;
+ RECT 1092.520000 136.420000 1093.620000 136.900000 ;
+ RECT 1043.390000 130.980000 1044.390000 131.460000 ;
+ RECT 1047.520000 130.980000 1048.620000 131.460000 ;
+ RECT 1047.520000 136.420000 1048.620000 136.900000 ;
+ RECT 1043.390000 136.420000 1044.390000 136.900000 ;
+ RECT 1236.830000 120.100000 1237.830000 120.580000 ;
+ RECT 1236.830000 125.540000 1237.830000 126.020000 ;
+ RECT 1227.520000 125.540000 1228.620000 126.020000 ;
+ RECT 1227.520000 120.100000 1228.620000 120.580000 ;
+ RECT 1182.520000 120.100000 1183.620000 120.580000 ;
+ RECT 1182.520000 125.540000 1183.620000 126.020000 ;
+ RECT 1092.520000 120.100000 1093.620000 120.580000 ;
+ RECT 1137.520000 120.100000 1138.620000 120.580000 ;
+ RECT 1137.520000 125.540000 1138.620000 126.020000 ;
+ RECT 1092.520000 125.540000 1093.620000 126.020000 ;
+ RECT 1043.390000 125.540000 1044.390000 126.020000 ;
+ RECT 1047.520000 125.540000 1048.620000 126.020000 ;
+ RECT 1043.390000 120.100000 1044.390000 120.580000 ;
+ RECT 1047.520000 120.100000 1048.620000 120.580000 ;
+ RECT 1040.560000 141.140000 1240.660000 142.140000 ;
+ RECT 1040.560000 118.090000 1240.660000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 118.090000 1041.560000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 118.090000 1240.660000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 141.140000 1041.560000 142.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 141.140000 1240.660000 142.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 115.240000 1044.390000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 144.500000 1044.390000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 115.240000 1237.830000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 144.500000 1237.830000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 3152.250000 1228.620000 3345.620000 ;
+ RECT 1182.520000 3152.250000 1183.620000 3345.620000 ;
+ RECT 1236.830000 3149.400000 1237.830000 3349.660000 ;
+ RECT 1137.520000 3152.250000 1138.620000 3345.620000 ;
+ RECT 1092.520000 3152.250000 1093.620000 3345.620000 ;
+ RECT 1047.520000 3152.250000 1048.620000 3345.620000 ;
+ RECT 1043.390000 3149.400000 1044.390000 3349.660000 ;
+ LAYER met3 ;
+ RECT 1227.520000 3339.220000 1228.620000 3339.700000 ;
+ RECT 1236.830000 3339.220000 1237.830000 3339.700000 ;
+ RECT 1236.830000 3328.340000 1237.830000 3328.820000 ;
+ RECT 1236.830000 3333.780000 1237.830000 3334.260000 ;
+ RECT 1227.520000 3333.780000 1228.620000 3334.260000 ;
+ RECT 1227.520000 3328.340000 1228.620000 3328.820000 ;
+ RECT 1227.520000 3322.900000 1228.620000 3323.380000 ;
+ RECT 1227.520000 3317.460000 1228.620000 3317.940000 ;
+ RECT 1236.830000 3322.900000 1237.830000 3323.380000 ;
+ RECT 1236.830000 3317.460000 1237.830000 3317.940000 ;
+ RECT 1227.520000 3301.140000 1228.620000 3301.620000 ;
+ RECT 1227.520000 3306.580000 1228.620000 3307.060000 ;
+ RECT 1236.830000 3306.580000 1237.830000 3307.060000 ;
+ RECT 1236.830000 3301.140000 1237.830000 3301.620000 ;
+ RECT 1227.520000 3312.020000 1228.620000 3312.500000 ;
+ RECT 1236.830000 3312.020000 1237.830000 3312.500000 ;
+ RECT 1182.520000 3339.220000 1183.620000 3339.700000 ;
+ RECT 1182.520000 3333.780000 1183.620000 3334.260000 ;
+ RECT 1182.520000 3328.340000 1183.620000 3328.820000 ;
+ RECT 1182.520000 3322.900000 1183.620000 3323.380000 ;
+ RECT 1182.520000 3301.140000 1183.620000 3301.620000 ;
+ RECT 1182.520000 3306.580000 1183.620000 3307.060000 ;
+ RECT 1182.520000 3312.020000 1183.620000 3312.500000 ;
+ RECT 1182.520000 3317.460000 1183.620000 3317.940000 ;
+ RECT 1236.830000 3290.260000 1237.830000 3290.740000 ;
+ RECT 1236.830000 3295.700000 1237.830000 3296.180000 ;
+ RECT 1227.520000 3295.700000 1228.620000 3296.180000 ;
+ RECT 1227.520000 3290.260000 1228.620000 3290.740000 ;
+ RECT 1227.520000 3284.820000 1228.620000 3285.300000 ;
+ RECT 1227.520000 3279.380000 1228.620000 3279.860000 ;
+ RECT 1236.830000 3284.820000 1237.830000 3285.300000 ;
+ RECT 1236.830000 3279.380000 1237.830000 3279.860000 ;
+ RECT 1236.830000 3263.060000 1237.830000 3263.540000 ;
+ RECT 1236.830000 3268.500000 1237.830000 3268.980000 ;
+ RECT 1236.830000 3273.940000 1237.830000 3274.420000 ;
+ RECT 1227.520000 3268.500000 1228.620000 3268.980000 ;
+ RECT 1227.520000 3263.060000 1228.620000 3263.540000 ;
+ RECT 1227.520000 3273.940000 1228.620000 3274.420000 ;
+ RECT 1227.520000 3257.620000 1228.620000 3258.100000 ;
+ RECT 1227.520000 3252.180000 1228.620000 3252.660000 ;
+ RECT 1236.830000 3257.620000 1237.830000 3258.100000 ;
+ RECT 1236.830000 3252.180000 1237.830000 3252.660000 ;
+ RECT 1182.520000 3295.700000 1183.620000 3296.180000 ;
+ RECT 1182.520000 3290.260000 1183.620000 3290.740000 ;
+ RECT 1182.520000 3284.820000 1183.620000 3285.300000 ;
+ RECT 1182.520000 3279.380000 1183.620000 3279.860000 ;
+ RECT 1182.520000 3268.500000 1183.620000 3268.980000 ;
+ RECT 1182.520000 3263.060000 1183.620000 3263.540000 ;
+ RECT 1182.520000 3257.620000 1183.620000 3258.100000 ;
+ RECT 1182.520000 3252.180000 1183.620000 3252.660000 ;
+ RECT 1182.520000 3273.940000 1183.620000 3274.420000 ;
+ RECT 1137.520000 3339.220000 1138.620000 3339.700000 ;
+ RECT 1137.520000 3333.780000 1138.620000 3334.260000 ;
+ RECT 1137.520000 3328.340000 1138.620000 3328.820000 ;
+ RECT 1092.520000 3339.220000 1093.620000 3339.700000 ;
+ RECT 1092.520000 3333.780000 1093.620000 3334.260000 ;
+ RECT 1092.520000 3328.340000 1093.620000 3328.820000 ;
+ RECT 1137.520000 3312.020000 1138.620000 3312.500000 ;
+ RECT 1137.520000 3306.580000 1138.620000 3307.060000 ;
+ RECT 1137.520000 3301.140000 1138.620000 3301.620000 ;
+ RECT 1137.520000 3317.460000 1138.620000 3317.940000 ;
+ RECT 1137.520000 3322.900000 1138.620000 3323.380000 ;
+ RECT 1092.520000 3322.900000 1093.620000 3323.380000 ;
+ RECT 1092.520000 3312.020000 1093.620000 3312.500000 ;
+ RECT 1092.520000 3306.580000 1093.620000 3307.060000 ;
+ RECT 1092.520000 3301.140000 1093.620000 3301.620000 ;
+ RECT 1092.520000 3317.460000 1093.620000 3317.940000 ;
+ RECT 1047.520000 3339.220000 1048.620000 3339.700000 ;
+ RECT 1043.390000 3339.220000 1044.390000 3339.700000 ;
+ RECT 1043.390000 3333.780000 1044.390000 3334.260000 ;
+ RECT 1047.520000 3333.780000 1048.620000 3334.260000 ;
+ RECT 1047.520000 3328.340000 1048.620000 3328.820000 ;
+ RECT 1043.390000 3328.340000 1044.390000 3328.820000 ;
+ RECT 1047.520000 3322.900000 1048.620000 3323.380000 ;
+ RECT 1043.390000 3322.900000 1044.390000 3323.380000 ;
+ RECT 1047.520000 3317.460000 1048.620000 3317.940000 ;
+ RECT 1043.390000 3317.460000 1044.390000 3317.940000 ;
+ RECT 1047.520000 3306.580000 1048.620000 3307.060000 ;
+ RECT 1043.390000 3306.580000 1044.390000 3307.060000 ;
+ RECT 1047.520000 3301.140000 1048.620000 3301.620000 ;
+ RECT 1043.390000 3301.140000 1044.390000 3301.620000 ;
+ RECT 1047.520000 3312.020000 1048.620000 3312.500000 ;
+ RECT 1043.390000 3312.020000 1044.390000 3312.500000 ;
+ RECT 1137.520000 3295.700000 1138.620000 3296.180000 ;
+ RECT 1137.520000 3290.260000 1138.620000 3290.740000 ;
+ RECT 1137.520000 3284.820000 1138.620000 3285.300000 ;
+ RECT 1137.520000 3279.380000 1138.620000 3279.860000 ;
+ RECT 1092.520000 3295.700000 1093.620000 3296.180000 ;
+ RECT 1092.520000 3290.260000 1093.620000 3290.740000 ;
+ RECT 1092.520000 3284.820000 1093.620000 3285.300000 ;
+ RECT 1092.520000 3279.380000 1093.620000 3279.860000 ;
+ RECT 1137.520000 3268.500000 1138.620000 3268.980000 ;
+ RECT 1137.520000 3252.180000 1138.620000 3252.660000 ;
+ RECT 1137.520000 3257.620000 1138.620000 3258.100000 ;
+ RECT 1137.520000 3263.060000 1138.620000 3263.540000 ;
+ RECT 1137.520000 3273.940000 1138.620000 3274.420000 ;
+ RECT 1092.520000 3252.180000 1093.620000 3252.660000 ;
+ RECT 1092.520000 3257.620000 1093.620000 3258.100000 ;
+ RECT 1092.520000 3263.060000 1093.620000 3263.540000 ;
+ RECT 1092.520000 3268.500000 1093.620000 3268.980000 ;
+ RECT 1092.520000 3273.940000 1093.620000 3274.420000 ;
+ RECT 1047.520000 3295.700000 1048.620000 3296.180000 ;
+ RECT 1043.390000 3295.700000 1044.390000 3296.180000 ;
+ RECT 1047.520000 3290.260000 1048.620000 3290.740000 ;
+ RECT 1043.390000 3290.260000 1044.390000 3290.740000 ;
+ RECT 1047.520000 3284.820000 1048.620000 3285.300000 ;
+ RECT 1043.390000 3284.820000 1044.390000 3285.300000 ;
+ RECT 1047.520000 3279.380000 1048.620000 3279.860000 ;
+ RECT 1043.390000 3279.380000 1044.390000 3279.860000 ;
+ RECT 1047.520000 3273.940000 1048.620000 3274.420000 ;
+ RECT 1047.520000 3268.500000 1048.620000 3268.980000 ;
+ RECT 1043.390000 3273.940000 1044.390000 3274.420000 ;
+ RECT 1043.390000 3268.500000 1044.390000 3268.980000 ;
+ RECT 1047.520000 3263.060000 1048.620000 3263.540000 ;
+ RECT 1043.390000 3263.060000 1044.390000 3263.540000 ;
+ RECT 1047.520000 3257.620000 1048.620000 3258.100000 ;
+ RECT 1043.390000 3257.620000 1044.390000 3258.100000 ;
+ RECT 1047.520000 3252.180000 1048.620000 3252.660000 ;
+ RECT 1043.390000 3252.180000 1044.390000 3252.660000 ;
+ RECT 1227.520000 3246.740000 1228.620000 3247.220000 ;
+ RECT 1227.520000 3241.300000 1228.620000 3241.780000 ;
+ RECT 1236.830000 3246.740000 1237.830000 3247.220000 ;
+ RECT 1236.830000 3241.300000 1237.830000 3241.780000 ;
+ RECT 1236.830000 3224.980000 1237.830000 3225.460000 ;
+ RECT 1236.830000 3230.420000 1237.830000 3230.900000 ;
+ RECT 1236.830000 3235.860000 1237.830000 3236.340000 ;
+ RECT 1227.520000 3235.860000 1228.620000 3236.340000 ;
+ RECT 1227.520000 3230.420000 1228.620000 3230.900000 ;
+ RECT 1227.520000 3224.980000 1228.620000 3225.460000 ;
+ RECT 1227.520000 3214.100000 1228.620000 3214.580000 ;
+ RECT 1227.520000 3219.540000 1228.620000 3220.020000 ;
+ RECT 1236.830000 3219.540000 1237.830000 3220.020000 ;
+ RECT 1236.830000 3214.100000 1237.830000 3214.580000 ;
+ RECT 1236.830000 3203.220000 1237.830000 3203.700000 ;
+ RECT 1236.830000 3208.660000 1237.830000 3209.140000 ;
+ RECT 1227.520000 3203.220000 1228.620000 3203.700000 ;
+ RECT 1227.520000 3208.660000 1228.620000 3209.140000 ;
+ RECT 1182.520000 3246.740000 1183.620000 3247.220000 ;
+ RECT 1182.520000 3241.300000 1183.620000 3241.780000 ;
+ RECT 1182.520000 3235.860000 1183.620000 3236.340000 ;
+ RECT 1182.520000 3230.420000 1183.620000 3230.900000 ;
+ RECT 1182.520000 3224.980000 1183.620000 3225.460000 ;
+ RECT 1182.520000 3203.220000 1183.620000 3203.700000 ;
+ RECT 1182.520000 3208.660000 1183.620000 3209.140000 ;
+ RECT 1182.520000 3214.100000 1183.620000 3214.580000 ;
+ RECT 1182.520000 3219.540000 1183.620000 3220.020000 ;
+ RECT 1227.520000 3197.780000 1228.620000 3198.260000 ;
+ RECT 1227.520000 3192.340000 1228.620000 3192.820000 ;
+ RECT 1236.830000 3197.780000 1237.830000 3198.260000 ;
+ RECT 1236.830000 3192.340000 1237.830000 3192.820000 ;
+ RECT 1227.520000 3181.460000 1228.620000 3181.940000 ;
+ RECT 1227.520000 3176.020000 1228.620000 3176.500000 ;
+ RECT 1236.830000 3181.460000 1237.830000 3181.940000 ;
+ RECT 1236.830000 3176.020000 1237.830000 3176.500000 ;
+ RECT 1227.520000 3186.900000 1228.620000 3187.380000 ;
+ RECT 1236.830000 3186.900000 1237.830000 3187.380000 ;
+ RECT 1236.830000 3165.140000 1237.830000 3165.620000 ;
+ RECT 1236.830000 3170.580000 1237.830000 3171.060000 ;
+ RECT 1227.520000 3170.580000 1228.620000 3171.060000 ;
+ RECT 1227.520000 3165.140000 1228.620000 3165.620000 ;
+ RECT 1227.520000 3159.700000 1228.620000 3160.180000 ;
+ RECT 1227.520000 3154.260000 1228.620000 3154.740000 ;
+ RECT 1236.830000 3159.700000 1237.830000 3160.180000 ;
+ RECT 1236.830000 3154.260000 1237.830000 3154.740000 ;
+ RECT 1182.520000 3197.780000 1183.620000 3198.260000 ;
+ RECT 1182.520000 3192.340000 1183.620000 3192.820000 ;
+ RECT 1182.520000 3186.900000 1183.620000 3187.380000 ;
+ RECT 1182.520000 3181.460000 1183.620000 3181.940000 ;
+ RECT 1182.520000 3176.020000 1183.620000 3176.500000 ;
+ RECT 1182.520000 3170.580000 1183.620000 3171.060000 ;
+ RECT 1182.520000 3165.140000 1183.620000 3165.620000 ;
+ RECT 1182.520000 3159.700000 1183.620000 3160.180000 ;
+ RECT 1182.520000 3154.260000 1183.620000 3154.740000 ;
+ RECT 1137.520000 3246.740000 1138.620000 3247.220000 ;
+ RECT 1137.520000 3241.300000 1138.620000 3241.780000 ;
+ RECT 1137.520000 3235.860000 1138.620000 3236.340000 ;
+ RECT 1137.520000 3230.420000 1138.620000 3230.900000 ;
+ RECT 1137.520000 3224.980000 1138.620000 3225.460000 ;
+ RECT 1092.520000 3246.740000 1093.620000 3247.220000 ;
+ RECT 1092.520000 3241.300000 1093.620000 3241.780000 ;
+ RECT 1092.520000 3235.860000 1093.620000 3236.340000 ;
+ RECT 1092.520000 3230.420000 1093.620000 3230.900000 ;
+ RECT 1092.520000 3224.980000 1093.620000 3225.460000 ;
+ RECT 1137.520000 3219.540000 1138.620000 3220.020000 ;
+ RECT 1137.520000 3214.100000 1138.620000 3214.580000 ;
+ RECT 1137.520000 3208.660000 1138.620000 3209.140000 ;
+ RECT 1137.520000 3203.220000 1138.620000 3203.700000 ;
+ RECT 1092.520000 3214.100000 1093.620000 3214.580000 ;
+ RECT 1092.520000 3208.660000 1093.620000 3209.140000 ;
+ RECT 1092.520000 3203.220000 1093.620000 3203.700000 ;
+ RECT 1092.520000 3219.540000 1093.620000 3220.020000 ;
+ RECT 1047.520000 3246.740000 1048.620000 3247.220000 ;
+ RECT 1043.390000 3246.740000 1044.390000 3247.220000 ;
+ RECT 1047.520000 3241.300000 1048.620000 3241.780000 ;
+ RECT 1043.390000 3241.300000 1044.390000 3241.780000 ;
+ RECT 1047.520000 3235.860000 1048.620000 3236.340000 ;
+ RECT 1043.390000 3235.860000 1044.390000 3236.340000 ;
+ RECT 1047.520000 3224.980000 1048.620000 3225.460000 ;
+ RECT 1043.390000 3224.980000 1044.390000 3225.460000 ;
+ RECT 1043.390000 3230.420000 1044.390000 3230.900000 ;
+ RECT 1047.520000 3230.420000 1048.620000 3230.900000 ;
+ RECT 1047.520000 3219.540000 1048.620000 3220.020000 ;
+ RECT 1043.390000 3219.540000 1044.390000 3220.020000 ;
+ RECT 1047.520000 3214.100000 1048.620000 3214.580000 ;
+ RECT 1043.390000 3214.100000 1044.390000 3214.580000 ;
+ RECT 1047.520000 3208.660000 1048.620000 3209.140000 ;
+ RECT 1043.390000 3208.660000 1044.390000 3209.140000 ;
+ RECT 1047.520000 3203.220000 1048.620000 3203.700000 ;
+ RECT 1043.390000 3203.220000 1044.390000 3203.700000 ;
+ RECT 1137.520000 3197.780000 1138.620000 3198.260000 ;
+ RECT 1137.520000 3192.340000 1138.620000 3192.820000 ;
+ RECT 1137.520000 3186.900000 1138.620000 3187.380000 ;
+ RECT 1137.520000 3181.460000 1138.620000 3181.940000 ;
+ RECT 1137.520000 3176.020000 1138.620000 3176.500000 ;
+ RECT 1092.520000 3197.780000 1093.620000 3198.260000 ;
+ RECT 1092.520000 3192.340000 1093.620000 3192.820000 ;
+ RECT 1092.520000 3186.900000 1093.620000 3187.380000 ;
+ RECT 1092.520000 3181.460000 1093.620000 3181.940000 ;
+ RECT 1092.520000 3176.020000 1093.620000 3176.500000 ;
+ RECT 1137.520000 3154.260000 1138.620000 3154.740000 ;
+ RECT 1137.520000 3159.700000 1138.620000 3160.180000 ;
+ RECT 1137.520000 3165.140000 1138.620000 3165.620000 ;
+ RECT 1137.520000 3170.580000 1138.620000 3171.060000 ;
+ RECT 1092.520000 3154.260000 1093.620000 3154.740000 ;
+ RECT 1092.520000 3159.700000 1093.620000 3160.180000 ;
+ RECT 1092.520000 3165.140000 1093.620000 3165.620000 ;
+ RECT 1092.520000 3170.580000 1093.620000 3171.060000 ;
+ RECT 1047.520000 3197.780000 1048.620000 3198.260000 ;
+ RECT 1043.390000 3197.780000 1044.390000 3198.260000 ;
+ RECT 1047.520000 3192.340000 1048.620000 3192.820000 ;
+ RECT 1043.390000 3192.340000 1044.390000 3192.820000 ;
+ RECT 1047.520000 3181.460000 1048.620000 3181.940000 ;
+ RECT 1043.390000 3181.460000 1044.390000 3181.940000 ;
+ RECT 1047.520000 3176.020000 1048.620000 3176.500000 ;
+ RECT 1043.390000 3176.020000 1044.390000 3176.500000 ;
+ RECT 1047.520000 3186.900000 1048.620000 3187.380000 ;
+ RECT 1043.390000 3186.900000 1044.390000 3187.380000 ;
+ RECT 1047.520000 3170.580000 1048.620000 3171.060000 ;
+ RECT 1043.390000 3170.580000 1044.390000 3171.060000 ;
+ RECT 1047.520000 3165.140000 1048.620000 3165.620000 ;
+ RECT 1043.390000 3165.140000 1044.390000 3165.620000 ;
+ RECT 1047.520000 3159.700000 1048.620000 3160.180000 ;
+ RECT 1047.520000 3154.260000 1048.620000 3154.740000 ;
+ RECT 1043.390000 3159.700000 1044.390000 3160.180000 ;
+ RECT 1043.390000 3154.260000 1044.390000 3154.740000 ;
+ RECT 1040.560000 3344.620000 1240.660000 3345.620000 ;
+ RECT 1040.560000 3152.250000 1240.660000 3153.250000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 3149.400000 1044.390000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 3348.660000 1044.390000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 3149.400000 1237.830000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 3348.660000 1237.830000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 3152.250000 1041.560000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 3152.250000 1240.660000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 3344.620000 1041.560000 3345.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 3344.620000 1240.660000 3345.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 2951.990000 1228.620000 3145.360000 ;
+ RECT 1182.520000 2951.990000 1183.620000 3145.360000 ;
+ RECT 1236.830000 2949.140000 1237.830000 3149.400000 ;
+ RECT 1137.520000 2951.990000 1138.620000 3145.360000 ;
+ RECT 1092.520000 2951.990000 1093.620000 3145.360000 ;
+ RECT 1047.520000 2951.990000 1048.620000 3145.360000 ;
+ RECT 1043.390000 2949.140000 1044.390000 3149.400000 ;
+ LAYER met3 ;
+ RECT 1227.520000 3138.960000 1228.620000 3139.440000 ;
+ RECT 1236.830000 3138.960000 1237.830000 3139.440000 ;
+ RECT 1236.830000 3128.080000 1237.830000 3128.560000 ;
+ RECT 1236.830000 3133.520000 1237.830000 3134.000000 ;
+ RECT 1227.520000 3133.520000 1228.620000 3134.000000 ;
+ RECT 1227.520000 3128.080000 1228.620000 3128.560000 ;
+ RECT 1227.520000 3122.640000 1228.620000 3123.120000 ;
+ RECT 1227.520000 3117.200000 1228.620000 3117.680000 ;
+ RECT 1236.830000 3122.640000 1237.830000 3123.120000 ;
+ RECT 1236.830000 3117.200000 1237.830000 3117.680000 ;
+ RECT 1227.520000 3100.880000 1228.620000 3101.360000 ;
+ RECT 1227.520000 3106.320000 1228.620000 3106.800000 ;
+ RECT 1236.830000 3106.320000 1237.830000 3106.800000 ;
+ RECT 1236.830000 3100.880000 1237.830000 3101.360000 ;
+ RECT 1227.520000 3111.760000 1228.620000 3112.240000 ;
+ RECT 1236.830000 3111.760000 1237.830000 3112.240000 ;
+ RECT 1182.520000 3138.960000 1183.620000 3139.440000 ;
+ RECT 1182.520000 3133.520000 1183.620000 3134.000000 ;
+ RECT 1182.520000 3128.080000 1183.620000 3128.560000 ;
+ RECT 1182.520000 3122.640000 1183.620000 3123.120000 ;
+ RECT 1182.520000 3100.880000 1183.620000 3101.360000 ;
+ RECT 1182.520000 3106.320000 1183.620000 3106.800000 ;
+ RECT 1182.520000 3111.760000 1183.620000 3112.240000 ;
+ RECT 1182.520000 3117.200000 1183.620000 3117.680000 ;
+ RECT 1236.830000 3090.000000 1237.830000 3090.480000 ;
+ RECT 1236.830000 3095.440000 1237.830000 3095.920000 ;
+ RECT 1227.520000 3095.440000 1228.620000 3095.920000 ;
+ RECT 1227.520000 3090.000000 1228.620000 3090.480000 ;
+ RECT 1227.520000 3084.560000 1228.620000 3085.040000 ;
+ RECT 1227.520000 3079.120000 1228.620000 3079.600000 ;
+ RECT 1236.830000 3084.560000 1237.830000 3085.040000 ;
+ RECT 1236.830000 3079.120000 1237.830000 3079.600000 ;
+ RECT 1236.830000 3062.800000 1237.830000 3063.280000 ;
+ RECT 1236.830000 3068.240000 1237.830000 3068.720000 ;
+ RECT 1236.830000 3073.680000 1237.830000 3074.160000 ;
+ RECT 1227.520000 3068.240000 1228.620000 3068.720000 ;
+ RECT 1227.520000 3062.800000 1228.620000 3063.280000 ;
+ RECT 1227.520000 3073.680000 1228.620000 3074.160000 ;
+ RECT 1227.520000 3057.360000 1228.620000 3057.840000 ;
+ RECT 1227.520000 3051.920000 1228.620000 3052.400000 ;
+ RECT 1236.830000 3057.360000 1237.830000 3057.840000 ;
+ RECT 1236.830000 3051.920000 1237.830000 3052.400000 ;
+ RECT 1182.520000 3095.440000 1183.620000 3095.920000 ;
+ RECT 1182.520000 3090.000000 1183.620000 3090.480000 ;
+ RECT 1182.520000 3084.560000 1183.620000 3085.040000 ;
+ RECT 1182.520000 3079.120000 1183.620000 3079.600000 ;
+ RECT 1182.520000 3068.240000 1183.620000 3068.720000 ;
+ RECT 1182.520000 3062.800000 1183.620000 3063.280000 ;
+ RECT 1182.520000 3057.360000 1183.620000 3057.840000 ;
+ RECT 1182.520000 3051.920000 1183.620000 3052.400000 ;
+ RECT 1182.520000 3073.680000 1183.620000 3074.160000 ;
+ RECT 1137.520000 3138.960000 1138.620000 3139.440000 ;
+ RECT 1137.520000 3133.520000 1138.620000 3134.000000 ;
+ RECT 1137.520000 3128.080000 1138.620000 3128.560000 ;
+ RECT 1092.520000 3138.960000 1093.620000 3139.440000 ;
+ RECT 1092.520000 3133.520000 1093.620000 3134.000000 ;
+ RECT 1092.520000 3128.080000 1093.620000 3128.560000 ;
+ RECT 1137.520000 3111.760000 1138.620000 3112.240000 ;
+ RECT 1137.520000 3106.320000 1138.620000 3106.800000 ;
+ RECT 1137.520000 3100.880000 1138.620000 3101.360000 ;
+ RECT 1137.520000 3117.200000 1138.620000 3117.680000 ;
+ RECT 1137.520000 3122.640000 1138.620000 3123.120000 ;
+ RECT 1092.520000 3122.640000 1093.620000 3123.120000 ;
+ RECT 1092.520000 3111.760000 1093.620000 3112.240000 ;
+ RECT 1092.520000 3106.320000 1093.620000 3106.800000 ;
+ RECT 1092.520000 3100.880000 1093.620000 3101.360000 ;
+ RECT 1092.520000 3117.200000 1093.620000 3117.680000 ;
+ RECT 1047.520000 3138.960000 1048.620000 3139.440000 ;
+ RECT 1043.390000 3138.960000 1044.390000 3139.440000 ;
+ RECT 1043.390000 3133.520000 1044.390000 3134.000000 ;
+ RECT 1047.520000 3133.520000 1048.620000 3134.000000 ;
+ RECT 1047.520000 3128.080000 1048.620000 3128.560000 ;
+ RECT 1043.390000 3128.080000 1044.390000 3128.560000 ;
+ RECT 1047.520000 3122.640000 1048.620000 3123.120000 ;
+ RECT 1043.390000 3122.640000 1044.390000 3123.120000 ;
+ RECT 1047.520000 3117.200000 1048.620000 3117.680000 ;
+ RECT 1043.390000 3117.200000 1044.390000 3117.680000 ;
+ RECT 1047.520000 3106.320000 1048.620000 3106.800000 ;
+ RECT 1043.390000 3106.320000 1044.390000 3106.800000 ;
+ RECT 1047.520000 3100.880000 1048.620000 3101.360000 ;
+ RECT 1043.390000 3100.880000 1044.390000 3101.360000 ;
+ RECT 1047.520000 3111.760000 1048.620000 3112.240000 ;
+ RECT 1043.390000 3111.760000 1044.390000 3112.240000 ;
+ RECT 1137.520000 3095.440000 1138.620000 3095.920000 ;
+ RECT 1137.520000 3090.000000 1138.620000 3090.480000 ;
+ RECT 1137.520000 3084.560000 1138.620000 3085.040000 ;
+ RECT 1137.520000 3079.120000 1138.620000 3079.600000 ;
+ RECT 1092.520000 3095.440000 1093.620000 3095.920000 ;
+ RECT 1092.520000 3090.000000 1093.620000 3090.480000 ;
+ RECT 1092.520000 3084.560000 1093.620000 3085.040000 ;
+ RECT 1092.520000 3079.120000 1093.620000 3079.600000 ;
+ RECT 1137.520000 3068.240000 1138.620000 3068.720000 ;
+ RECT 1137.520000 3051.920000 1138.620000 3052.400000 ;
+ RECT 1137.520000 3057.360000 1138.620000 3057.840000 ;
+ RECT 1137.520000 3062.800000 1138.620000 3063.280000 ;
+ RECT 1137.520000 3073.680000 1138.620000 3074.160000 ;
+ RECT 1092.520000 3051.920000 1093.620000 3052.400000 ;
+ RECT 1092.520000 3057.360000 1093.620000 3057.840000 ;
+ RECT 1092.520000 3062.800000 1093.620000 3063.280000 ;
+ RECT 1092.520000 3068.240000 1093.620000 3068.720000 ;
+ RECT 1092.520000 3073.680000 1093.620000 3074.160000 ;
+ RECT 1047.520000 3095.440000 1048.620000 3095.920000 ;
+ RECT 1043.390000 3095.440000 1044.390000 3095.920000 ;
+ RECT 1047.520000 3090.000000 1048.620000 3090.480000 ;
+ RECT 1043.390000 3090.000000 1044.390000 3090.480000 ;
+ RECT 1047.520000 3084.560000 1048.620000 3085.040000 ;
+ RECT 1043.390000 3084.560000 1044.390000 3085.040000 ;
+ RECT 1047.520000 3079.120000 1048.620000 3079.600000 ;
+ RECT 1043.390000 3079.120000 1044.390000 3079.600000 ;
+ RECT 1047.520000 3073.680000 1048.620000 3074.160000 ;
+ RECT 1047.520000 3068.240000 1048.620000 3068.720000 ;
+ RECT 1043.390000 3073.680000 1044.390000 3074.160000 ;
+ RECT 1043.390000 3068.240000 1044.390000 3068.720000 ;
+ RECT 1047.520000 3062.800000 1048.620000 3063.280000 ;
+ RECT 1043.390000 3062.800000 1044.390000 3063.280000 ;
+ RECT 1047.520000 3057.360000 1048.620000 3057.840000 ;
+ RECT 1043.390000 3057.360000 1044.390000 3057.840000 ;
+ RECT 1047.520000 3051.920000 1048.620000 3052.400000 ;
+ RECT 1043.390000 3051.920000 1044.390000 3052.400000 ;
+ RECT 1227.520000 3046.480000 1228.620000 3046.960000 ;
+ RECT 1227.520000 3041.040000 1228.620000 3041.520000 ;
+ RECT 1236.830000 3046.480000 1237.830000 3046.960000 ;
+ RECT 1236.830000 3041.040000 1237.830000 3041.520000 ;
+ RECT 1236.830000 3024.720000 1237.830000 3025.200000 ;
+ RECT 1236.830000 3030.160000 1237.830000 3030.640000 ;
+ RECT 1236.830000 3035.600000 1237.830000 3036.080000 ;
+ RECT 1227.520000 3035.600000 1228.620000 3036.080000 ;
+ RECT 1227.520000 3030.160000 1228.620000 3030.640000 ;
+ RECT 1227.520000 3024.720000 1228.620000 3025.200000 ;
+ RECT 1227.520000 3013.840000 1228.620000 3014.320000 ;
+ RECT 1227.520000 3019.280000 1228.620000 3019.760000 ;
+ RECT 1236.830000 3019.280000 1237.830000 3019.760000 ;
+ RECT 1236.830000 3013.840000 1237.830000 3014.320000 ;
+ RECT 1236.830000 3002.960000 1237.830000 3003.440000 ;
+ RECT 1236.830000 3008.400000 1237.830000 3008.880000 ;
+ RECT 1227.520000 3002.960000 1228.620000 3003.440000 ;
+ RECT 1227.520000 3008.400000 1228.620000 3008.880000 ;
+ RECT 1182.520000 3046.480000 1183.620000 3046.960000 ;
+ RECT 1182.520000 3041.040000 1183.620000 3041.520000 ;
+ RECT 1182.520000 3035.600000 1183.620000 3036.080000 ;
+ RECT 1182.520000 3030.160000 1183.620000 3030.640000 ;
+ RECT 1182.520000 3024.720000 1183.620000 3025.200000 ;
+ RECT 1182.520000 3002.960000 1183.620000 3003.440000 ;
+ RECT 1182.520000 3008.400000 1183.620000 3008.880000 ;
+ RECT 1182.520000 3013.840000 1183.620000 3014.320000 ;
+ RECT 1182.520000 3019.280000 1183.620000 3019.760000 ;
+ RECT 1227.520000 2997.520000 1228.620000 2998.000000 ;
+ RECT 1227.520000 2992.080000 1228.620000 2992.560000 ;
+ RECT 1236.830000 2997.520000 1237.830000 2998.000000 ;
+ RECT 1236.830000 2992.080000 1237.830000 2992.560000 ;
+ RECT 1227.520000 2981.200000 1228.620000 2981.680000 ;
+ RECT 1227.520000 2975.760000 1228.620000 2976.240000 ;
+ RECT 1236.830000 2981.200000 1237.830000 2981.680000 ;
+ RECT 1236.830000 2975.760000 1237.830000 2976.240000 ;
+ RECT 1227.520000 2986.640000 1228.620000 2987.120000 ;
+ RECT 1236.830000 2986.640000 1237.830000 2987.120000 ;
+ RECT 1236.830000 2964.880000 1237.830000 2965.360000 ;
+ RECT 1236.830000 2970.320000 1237.830000 2970.800000 ;
+ RECT 1227.520000 2970.320000 1228.620000 2970.800000 ;
+ RECT 1227.520000 2964.880000 1228.620000 2965.360000 ;
+ RECT 1227.520000 2959.440000 1228.620000 2959.920000 ;
+ RECT 1227.520000 2954.000000 1228.620000 2954.480000 ;
+ RECT 1236.830000 2959.440000 1237.830000 2959.920000 ;
+ RECT 1236.830000 2954.000000 1237.830000 2954.480000 ;
+ RECT 1182.520000 2997.520000 1183.620000 2998.000000 ;
+ RECT 1182.520000 2992.080000 1183.620000 2992.560000 ;
+ RECT 1182.520000 2986.640000 1183.620000 2987.120000 ;
+ RECT 1182.520000 2981.200000 1183.620000 2981.680000 ;
+ RECT 1182.520000 2975.760000 1183.620000 2976.240000 ;
+ RECT 1182.520000 2970.320000 1183.620000 2970.800000 ;
+ RECT 1182.520000 2964.880000 1183.620000 2965.360000 ;
+ RECT 1182.520000 2959.440000 1183.620000 2959.920000 ;
+ RECT 1182.520000 2954.000000 1183.620000 2954.480000 ;
+ RECT 1137.520000 3046.480000 1138.620000 3046.960000 ;
+ RECT 1137.520000 3041.040000 1138.620000 3041.520000 ;
+ RECT 1137.520000 3035.600000 1138.620000 3036.080000 ;
+ RECT 1137.520000 3030.160000 1138.620000 3030.640000 ;
+ RECT 1137.520000 3024.720000 1138.620000 3025.200000 ;
+ RECT 1092.520000 3046.480000 1093.620000 3046.960000 ;
+ RECT 1092.520000 3041.040000 1093.620000 3041.520000 ;
+ RECT 1092.520000 3035.600000 1093.620000 3036.080000 ;
+ RECT 1092.520000 3030.160000 1093.620000 3030.640000 ;
+ RECT 1092.520000 3024.720000 1093.620000 3025.200000 ;
+ RECT 1137.520000 3019.280000 1138.620000 3019.760000 ;
+ RECT 1137.520000 3013.840000 1138.620000 3014.320000 ;
+ RECT 1137.520000 3008.400000 1138.620000 3008.880000 ;
+ RECT 1137.520000 3002.960000 1138.620000 3003.440000 ;
+ RECT 1092.520000 3013.840000 1093.620000 3014.320000 ;
+ RECT 1092.520000 3008.400000 1093.620000 3008.880000 ;
+ RECT 1092.520000 3002.960000 1093.620000 3003.440000 ;
+ RECT 1092.520000 3019.280000 1093.620000 3019.760000 ;
+ RECT 1047.520000 3046.480000 1048.620000 3046.960000 ;
+ RECT 1043.390000 3046.480000 1044.390000 3046.960000 ;
+ RECT 1047.520000 3041.040000 1048.620000 3041.520000 ;
+ RECT 1043.390000 3041.040000 1044.390000 3041.520000 ;
+ RECT 1047.520000 3035.600000 1048.620000 3036.080000 ;
+ RECT 1043.390000 3035.600000 1044.390000 3036.080000 ;
+ RECT 1047.520000 3024.720000 1048.620000 3025.200000 ;
+ RECT 1043.390000 3024.720000 1044.390000 3025.200000 ;
+ RECT 1043.390000 3030.160000 1044.390000 3030.640000 ;
+ RECT 1047.520000 3030.160000 1048.620000 3030.640000 ;
+ RECT 1047.520000 3019.280000 1048.620000 3019.760000 ;
+ RECT 1043.390000 3019.280000 1044.390000 3019.760000 ;
+ RECT 1047.520000 3013.840000 1048.620000 3014.320000 ;
+ RECT 1043.390000 3013.840000 1044.390000 3014.320000 ;
+ RECT 1047.520000 3008.400000 1048.620000 3008.880000 ;
+ RECT 1043.390000 3008.400000 1044.390000 3008.880000 ;
+ RECT 1047.520000 3002.960000 1048.620000 3003.440000 ;
+ RECT 1043.390000 3002.960000 1044.390000 3003.440000 ;
+ RECT 1137.520000 2997.520000 1138.620000 2998.000000 ;
+ RECT 1137.520000 2992.080000 1138.620000 2992.560000 ;
+ RECT 1137.520000 2986.640000 1138.620000 2987.120000 ;
+ RECT 1137.520000 2981.200000 1138.620000 2981.680000 ;
+ RECT 1137.520000 2975.760000 1138.620000 2976.240000 ;
+ RECT 1092.520000 2997.520000 1093.620000 2998.000000 ;
+ RECT 1092.520000 2992.080000 1093.620000 2992.560000 ;
+ RECT 1092.520000 2986.640000 1093.620000 2987.120000 ;
+ RECT 1092.520000 2981.200000 1093.620000 2981.680000 ;
+ RECT 1092.520000 2975.760000 1093.620000 2976.240000 ;
+ RECT 1137.520000 2954.000000 1138.620000 2954.480000 ;
+ RECT 1137.520000 2959.440000 1138.620000 2959.920000 ;
+ RECT 1137.520000 2964.880000 1138.620000 2965.360000 ;
+ RECT 1137.520000 2970.320000 1138.620000 2970.800000 ;
+ RECT 1092.520000 2954.000000 1093.620000 2954.480000 ;
+ RECT 1092.520000 2959.440000 1093.620000 2959.920000 ;
+ RECT 1092.520000 2964.880000 1093.620000 2965.360000 ;
+ RECT 1092.520000 2970.320000 1093.620000 2970.800000 ;
+ RECT 1047.520000 2997.520000 1048.620000 2998.000000 ;
+ RECT 1043.390000 2997.520000 1044.390000 2998.000000 ;
+ RECT 1047.520000 2992.080000 1048.620000 2992.560000 ;
+ RECT 1043.390000 2992.080000 1044.390000 2992.560000 ;
+ RECT 1047.520000 2981.200000 1048.620000 2981.680000 ;
+ RECT 1043.390000 2981.200000 1044.390000 2981.680000 ;
+ RECT 1047.520000 2975.760000 1048.620000 2976.240000 ;
+ RECT 1043.390000 2975.760000 1044.390000 2976.240000 ;
+ RECT 1047.520000 2986.640000 1048.620000 2987.120000 ;
+ RECT 1043.390000 2986.640000 1044.390000 2987.120000 ;
+ RECT 1047.520000 2970.320000 1048.620000 2970.800000 ;
+ RECT 1043.390000 2970.320000 1044.390000 2970.800000 ;
+ RECT 1047.520000 2964.880000 1048.620000 2965.360000 ;
+ RECT 1043.390000 2964.880000 1044.390000 2965.360000 ;
+ RECT 1047.520000 2959.440000 1048.620000 2959.920000 ;
+ RECT 1047.520000 2954.000000 1048.620000 2954.480000 ;
+ RECT 1043.390000 2959.440000 1044.390000 2959.920000 ;
+ RECT 1043.390000 2954.000000 1044.390000 2954.480000 ;
+ RECT 1040.560000 3144.360000 1240.660000 3145.360000 ;
+ RECT 1040.560000 2951.990000 1240.660000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 2949.140000 1044.390000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 3148.400000 1044.390000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 2949.140000 1237.830000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 3148.400000 1237.830000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2951.990000 1041.560000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2951.990000 1240.660000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 3144.360000 1041.560000 3145.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 3144.360000 1240.660000 3145.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 2751.730000 1228.620000 2945.100000 ;
+ RECT 1182.520000 2751.730000 1183.620000 2945.100000 ;
+ RECT 1236.830000 2748.880000 1237.830000 2949.140000 ;
+ RECT 1137.520000 2751.730000 1138.620000 2945.100000 ;
+ RECT 1092.520000 2751.730000 1093.620000 2945.100000 ;
+ RECT 1047.520000 2751.730000 1048.620000 2945.100000 ;
+ RECT 1043.390000 2748.880000 1044.390000 2949.140000 ;
+ LAYER met3 ;
+ RECT 1227.520000 2938.700000 1228.620000 2939.180000 ;
+ RECT 1236.830000 2938.700000 1237.830000 2939.180000 ;
+ RECT 1236.830000 2927.820000 1237.830000 2928.300000 ;
+ RECT 1236.830000 2933.260000 1237.830000 2933.740000 ;
+ RECT 1227.520000 2933.260000 1228.620000 2933.740000 ;
+ RECT 1227.520000 2927.820000 1228.620000 2928.300000 ;
+ RECT 1227.520000 2922.380000 1228.620000 2922.860000 ;
+ RECT 1227.520000 2916.940000 1228.620000 2917.420000 ;
+ RECT 1236.830000 2922.380000 1237.830000 2922.860000 ;
+ RECT 1236.830000 2916.940000 1237.830000 2917.420000 ;
+ RECT 1227.520000 2900.620000 1228.620000 2901.100000 ;
+ RECT 1227.520000 2906.060000 1228.620000 2906.540000 ;
+ RECT 1236.830000 2906.060000 1237.830000 2906.540000 ;
+ RECT 1236.830000 2900.620000 1237.830000 2901.100000 ;
+ RECT 1227.520000 2911.500000 1228.620000 2911.980000 ;
+ RECT 1236.830000 2911.500000 1237.830000 2911.980000 ;
+ RECT 1182.520000 2938.700000 1183.620000 2939.180000 ;
+ RECT 1182.520000 2933.260000 1183.620000 2933.740000 ;
+ RECT 1182.520000 2927.820000 1183.620000 2928.300000 ;
+ RECT 1182.520000 2922.380000 1183.620000 2922.860000 ;
+ RECT 1182.520000 2900.620000 1183.620000 2901.100000 ;
+ RECT 1182.520000 2906.060000 1183.620000 2906.540000 ;
+ RECT 1182.520000 2911.500000 1183.620000 2911.980000 ;
+ RECT 1182.520000 2916.940000 1183.620000 2917.420000 ;
+ RECT 1236.830000 2889.740000 1237.830000 2890.220000 ;
+ RECT 1236.830000 2895.180000 1237.830000 2895.660000 ;
+ RECT 1227.520000 2895.180000 1228.620000 2895.660000 ;
+ RECT 1227.520000 2889.740000 1228.620000 2890.220000 ;
+ RECT 1227.520000 2884.300000 1228.620000 2884.780000 ;
+ RECT 1227.520000 2878.860000 1228.620000 2879.340000 ;
+ RECT 1236.830000 2884.300000 1237.830000 2884.780000 ;
+ RECT 1236.830000 2878.860000 1237.830000 2879.340000 ;
+ RECT 1236.830000 2862.540000 1237.830000 2863.020000 ;
+ RECT 1236.830000 2867.980000 1237.830000 2868.460000 ;
+ RECT 1236.830000 2873.420000 1237.830000 2873.900000 ;
+ RECT 1227.520000 2867.980000 1228.620000 2868.460000 ;
+ RECT 1227.520000 2862.540000 1228.620000 2863.020000 ;
+ RECT 1227.520000 2873.420000 1228.620000 2873.900000 ;
+ RECT 1227.520000 2857.100000 1228.620000 2857.580000 ;
+ RECT 1227.520000 2851.660000 1228.620000 2852.140000 ;
+ RECT 1236.830000 2857.100000 1237.830000 2857.580000 ;
+ RECT 1236.830000 2851.660000 1237.830000 2852.140000 ;
+ RECT 1182.520000 2895.180000 1183.620000 2895.660000 ;
+ RECT 1182.520000 2889.740000 1183.620000 2890.220000 ;
+ RECT 1182.520000 2884.300000 1183.620000 2884.780000 ;
+ RECT 1182.520000 2878.860000 1183.620000 2879.340000 ;
+ RECT 1182.520000 2867.980000 1183.620000 2868.460000 ;
+ RECT 1182.520000 2862.540000 1183.620000 2863.020000 ;
+ RECT 1182.520000 2857.100000 1183.620000 2857.580000 ;
+ RECT 1182.520000 2851.660000 1183.620000 2852.140000 ;
+ RECT 1182.520000 2873.420000 1183.620000 2873.900000 ;
+ RECT 1137.520000 2938.700000 1138.620000 2939.180000 ;
+ RECT 1137.520000 2933.260000 1138.620000 2933.740000 ;
+ RECT 1137.520000 2927.820000 1138.620000 2928.300000 ;
+ RECT 1092.520000 2938.700000 1093.620000 2939.180000 ;
+ RECT 1092.520000 2933.260000 1093.620000 2933.740000 ;
+ RECT 1092.520000 2927.820000 1093.620000 2928.300000 ;
+ RECT 1137.520000 2911.500000 1138.620000 2911.980000 ;
+ RECT 1137.520000 2906.060000 1138.620000 2906.540000 ;
+ RECT 1137.520000 2900.620000 1138.620000 2901.100000 ;
+ RECT 1137.520000 2916.940000 1138.620000 2917.420000 ;
+ RECT 1137.520000 2922.380000 1138.620000 2922.860000 ;
+ RECT 1092.520000 2922.380000 1093.620000 2922.860000 ;
+ RECT 1092.520000 2911.500000 1093.620000 2911.980000 ;
+ RECT 1092.520000 2906.060000 1093.620000 2906.540000 ;
+ RECT 1092.520000 2900.620000 1093.620000 2901.100000 ;
+ RECT 1092.520000 2916.940000 1093.620000 2917.420000 ;
+ RECT 1047.520000 2938.700000 1048.620000 2939.180000 ;
+ RECT 1043.390000 2938.700000 1044.390000 2939.180000 ;
+ RECT 1043.390000 2933.260000 1044.390000 2933.740000 ;
+ RECT 1047.520000 2933.260000 1048.620000 2933.740000 ;
+ RECT 1047.520000 2927.820000 1048.620000 2928.300000 ;
+ RECT 1043.390000 2927.820000 1044.390000 2928.300000 ;
+ RECT 1047.520000 2922.380000 1048.620000 2922.860000 ;
+ RECT 1043.390000 2922.380000 1044.390000 2922.860000 ;
+ RECT 1047.520000 2916.940000 1048.620000 2917.420000 ;
+ RECT 1043.390000 2916.940000 1044.390000 2917.420000 ;
+ RECT 1047.520000 2906.060000 1048.620000 2906.540000 ;
+ RECT 1043.390000 2906.060000 1044.390000 2906.540000 ;
+ RECT 1047.520000 2900.620000 1048.620000 2901.100000 ;
+ RECT 1043.390000 2900.620000 1044.390000 2901.100000 ;
+ RECT 1047.520000 2911.500000 1048.620000 2911.980000 ;
+ RECT 1043.390000 2911.500000 1044.390000 2911.980000 ;
+ RECT 1137.520000 2895.180000 1138.620000 2895.660000 ;
+ RECT 1137.520000 2889.740000 1138.620000 2890.220000 ;
+ RECT 1137.520000 2884.300000 1138.620000 2884.780000 ;
+ RECT 1137.520000 2878.860000 1138.620000 2879.340000 ;
+ RECT 1092.520000 2895.180000 1093.620000 2895.660000 ;
+ RECT 1092.520000 2889.740000 1093.620000 2890.220000 ;
+ RECT 1092.520000 2884.300000 1093.620000 2884.780000 ;
+ RECT 1092.520000 2878.860000 1093.620000 2879.340000 ;
+ RECT 1137.520000 2867.980000 1138.620000 2868.460000 ;
+ RECT 1137.520000 2851.660000 1138.620000 2852.140000 ;
+ RECT 1137.520000 2857.100000 1138.620000 2857.580000 ;
+ RECT 1137.520000 2862.540000 1138.620000 2863.020000 ;
+ RECT 1137.520000 2873.420000 1138.620000 2873.900000 ;
+ RECT 1092.520000 2851.660000 1093.620000 2852.140000 ;
+ RECT 1092.520000 2857.100000 1093.620000 2857.580000 ;
+ RECT 1092.520000 2862.540000 1093.620000 2863.020000 ;
+ RECT 1092.520000 2867.980000 1093.620000 2868.460000 ;
+ RECT 1092.520000 2873.420000 1093.620000 2873.900000 ;
+ RECT 1047.520000 2895.180000 1048.620000 2895.660000 ;
+ RECT 1043.390000 2895.180000 1044.390000 2895.660000 ;
+ RECT 1047.520000 2889.740000 1048.620000 2890.220000 ;
+ RECT 1043.390000 2889.740000 1044.390000 2890.220000 ;
+ RECT 1047.520000 2884.300000 1048.620000 2884.780000 ;
+ RECT 1043.390000 2884.300000 1044.390000 2884.780000 ;
+ RECT 1047.520000 2878.860000 1048.620000 2879.340000 ;
+ RECT 1043.390000 2878.860000 1044.390000 2879.340000 ;
+ RECT 1047.520000 2873.420000 1048.620000 2873.900000 ;
+ RECT 1047.520000 2867.980000 1048.620000 2868.460000 ;
+ RECT 1043.390000 2873.420000 1044.390000 2873.900000 ;
+ RECT 1043.390000 2867.980000 1044.390000 2868.460000 ;
+ RECT 1047.520000 2862.540000 1048.620000 2863.020000 ;
+ RECT 1043.390000 2862.540000 1044.390000 2863.020000 ;
+ RECT 1047.520000 2857.100000 1048.620000 2857.580000 ;
+ RECT 1043.390000 2857.100000 1044.390000 2857.580000 ;
+ RECT 1047.520000 2851.660000 1048.620000 2852.140000 ;
+ RECT 1043.390000 2851.660000 1044.390000 2852.140000 ;
+ RECT 1227.520000 2846.220000 1228.620000 2846.700000 ;
+ RECT 1227.520000 2840.780000 1228.620000 2841.260000 ;
+ RECT 1236.830000 2846.220000 1237.830000 2846.700000 ;
+ RECT 1236.830000 2840.780000 1237.830000 2841.260000 ;
+ RECT 1236.830000 2824.460000 1237.830000 2824.940000 ;
+ RECT 1236.830000 2829.900000 1237.830000 2830.380000 ;
+ RECT 1236.830000 2835.340000 1237.830000 2835.820000 ;
+ RECT 1227.520000 2835.340000 1228.620000 2835.820000 ;
+ RECT 1227.520000 2829.900000 1228.620000 2830.380000 ;
+ RECT 1227.520000 2824.460000 1228.620000 2824.940000 ;
+ RECT 1227.520000 2813.580000 1228.620000 2814.060000 ;
+ RECT 1227.520000 2819.020000 1228.620000 2819.500000 ;
+ RECT 1236.830000 2819.020000 1237.830000 2819.500000 ;
+ RECT 1236.830000 2813.580000 1237.830000 2814.060000 ;
+ RECT 1236.830000 2802.700000 1237.830000 2803.180000 ;
+ RECT 1236.830000 2808.140000 1237.830000 2808.620000 ;
+ RECT 1227.520000 2802.700000 1228.620000 2803.180000 ;
+ RECT 1227.520000 2808.140000 1228.620000 2808.620000 ;
+ RECT 1182.520000 2846.220000 1183.620000 2846.700000 ;
+ RECT 1182.520000 2840.780000 1183.620000 2841.260000 ;
+ RECT 1182.520000 2835.340000 1183.620000 2835.820000 ;
+ RECT 1182.520000 2829.900000 1183.620000 2830.380000 ;
+ RECT 1182.520000 2824.460000 1183.620000 2824.940000 ;
+ RECT 1182.520000 2802.700000 1183.620000 2803.180000 ;
+ RECT 1182.520000 2808.140000 1183.620000 2808.620000 ;
+ RECT 1182.520000 2813.580000 1183.620000 2814.060000 ;
+ RECT 1182.520000 2819.020000 1183.620000 2819.500000 ;
+ RECT 1227.520000 2797.260000 1228.620000 2797.740000 ;
+ RECT 1227.520000 2791.820000 1228.620000 2792.300000 ;
+ RECT 1236.830000 2797.260000 1237.830000 2797.740000 ;
+ RECT 1236.830000 2791.820000 1237.830000 2792.300000 ;
+ RECT 1227.520000 2780.940000 1228.620000 2781.420000 ;
+ RECT 1227.520000 2775.500000 1228.620000 2775.980000 ;
+ RECT 1236.830000 2780.940000 1237.830000 2781.420000 ;
+ RECT 1236.830000 2775.500000 1237.830000 2775.980000 ;
+ RECT 1227.520000 2786.380000 1228.620000 2786.860000 ;
+ RECT 1236.830000 2786.380000 1237.830000 2786.860000 ;
+ RECT 1236.830000 2764.620000 1237.830000 2765.100000 ;
+ RECT 1236.830000 2770.060000 1237.830000 2770.540000 ;
+ RECT 1227.520000 2770.060000 1228.620000 2770.540000 ;
+ RECT 1227.520000 2764.620000 1228.620000 2765.100000 ;
+ RECT 1227.520000 2759.180000 1228.620000 2759.660000 ;
+ RECT 1227.520000 2753.740000 1228.620000 2754.220000 ;
+ RECT 1236.830000 2759.180000 1237.830000 2759.660000 ;
+ RECT 1236.830000 2753.740000 1237.830000 2754.220000 ;
+ RECT 1182.520000 2797.260000 1183.620000 2797.740000 ;
+ RECT 1182.520000 2791.820000 1183.620000 2792.300000 ;
+ RECT 1182.520000 2786.380000 1183.620000 2786.860000 ;
+ RECT 1182.520000 2780.940000 1183.620000 2781.420000 ;
+ RECT 1182.520000 2775.500000 1183.620000 2775.980000 ;
+ RECT 1182.520000 2770.060000 1183.620000 2770.540000 ;
+ RECT 1182.520000 2764.620000 1183.620000 2765.100000 ;
+ RECT 1182.520000 2759.180000 1183.620000 2759.660000 ;
+ RECT 1182.520000 2753.740000 1183.620000 2754.220000 ;
+ RECT 1137.520000 2846.220000 1138.620000 2846.700000 ;
+ RECT 1137.520000 2840.780000 1138.620000 2841.260000 ;
+ RECT 1137.520000 2835.340000 1138.620000 2835.820000 ;
+ RECT 1137.520000 2829.900000 1138.620000 2830.380000 ;
+ RECT 1137.520000 2824.460000 1138.620000 2824.940000 ;
+ RECT 1092.520000 2846.220000 1093.620000 2846.700000 ;
+ RECT 1092.520000 2840.780000 1093.620000 2841.260000 ;
+ RECT 1092.520000 2835.340000 1093.620000 2835.820000 ;
+ RECT 1092.520000 2829.900000 1093.620000 2830.380000 ;
+ RECT 1092.520000 2824.460000 1093.620000 2824.940000 ;
+ RECT 1137.520000 2819.020000 1138.620000 2819.500000 ;
+ RECT 1137.520000 2813.580000 1138.620000 2814.060000 ;
+ RECT 1137.520000 2808.140000 1138.620000 2808.620000 ;
+ RECT 1137.520000 2802.700000 1138.620000 2803.180000 ;
+ RECT 1092.520000 2813.580000 1093.620000 2814.060000 ;
+ RECT 1092.520000 2808.140000 1093.620000 2808.620000 ;
+ RECT 1092.520000 2802.700000 1093.620000 2803.180000 ;
+ RECT 1092.520000 2819.020000 1093.620000 2819.500000 ;
+ RECT 1047.520000 2846.220000 1048.620000 2846.700000 ;
+ RECT 1043.390000 2846.220000 1044.390000 2846.700000 ;
+ RECT 1047.520000 2840.780000 1048.620000 2841.260000 ;
+ RECT 1043.390000 2840.780000 1044.390000 2841.260000 ;
+ RECT 1047.520000 2835.340000 1048.620000 2835.820000 ;
+ RECT 1043.390000 2835.340000 1044.390000 2835.820000 ;
+ RECT 1047.520000 2824.460000 1048.620000 2824.940000 ;
+ RECT 1043.390000 2824.460000 1044.390000 2824.940000 ;
+ RECT 1043.390000 2829.900000 1044.390000 2830.380000 ;
+ RECT 1047.520000 2829.900000 1048.620000 2830.380000 ;
+ RECT 1047.520000 2819.020000 1048.620000 2819.500000 ;
+ RECT 1043.390000 2819.020000 1044.390000 2819.500000 ;
+ RECT 1047.520000 2813.580000 1048.620000 2814.060000 ;
+ RECT 1043.390000 2813.580000 1044.390000 2814.060000 ;
+ RECT 1047.520000 2808.140000 1048.620000 2808.620000 ;
+ RECT 1043.390000 2808.140000 1044.390000 2808.620000 ;
+ RECT 1047.520000 2802.700000 1048.620000 2803.180000 ;
+ RECT 1043.390000 2802.700000 1044.390000 2803.180000 ;
+ RECT 1137.520000 2797.260000 1138.620000 2797.740000 ;
+ RECT 1137.520000 2791.820000 1138.620000 2792.300000 ;
+ RECT 1137.520000 2786.380000 1138.620000 2786.860000 ;
+ RECT 1137.520000 2780.940000 1138.620000 2781.420000 ;
+ RECT 1137.520000 2775.500000 1138.620000 2775.980000 ;
+ RECT 1092.520000 2797.260000 1093.620000 2797.740000 ;
+ RECT 1092.520000 2791.820000 1093.620000 2792.300000 ;
+ RECT 1092.520000 2786.380000 1093.620000 2786.860000 ;
+ RECT 1092.520000 2780.940000 1093.620000 2781.420000 ;
+ RECT 1092.520000 2775.500000 1093.620000 2775.980000 ;
+ RECT 1137.520000 2753.740000 1138.620000 2754.220000 ;
+ RECT 1137.520000 2759.180000 1138.620000 2759.660000 ;
+ RECT 1137.520000 2764.620000 1138.620000 2765.100000 ;
+ RECT 1137.520000 2770.060000 1138.620000 2770.540000 ;
+ RECT 1092.520000 2753.740000 1093.620000 2754.220000 ;
+ RECT 1092.520000 2759.180000 1093.620000 2759.660000 ;
+ RECT 1092.520000 2764.620000 1093.620000 2765.100000 ;
+ RECT 1092.520000 2770.060000 1093.620000 2770.540000 ;
+ RECT 1047.520000 2797.260000 1048.620000 2797.740000 ;
+ RECT 1043.390000 2797.260000 1044.390000 2797.740000 ;
+ RECT 1047.520000 2791.820000 1048.620000 2792.300000 ;
+ RECT 1043.390000 2791.820000 1044.390000 2792.300000 ;
+ RECT 1047.520000 2780.940000 1048.620000 2781.420000 ;
+ RECT 1043.390000 2780.940000 1044.390000 2781.420000 ;
+ RECT 1047.520000 2775.500000 1048.620000 2775.980000 ;
+ RECT 1043.390000 2775.500000 1044.390000 2775.980000 ;
+ RECT 1047.520000 2786.380000 1048.620000 2786.860000 ;
+ RECT 1043.390000 2786.380000 1044.390000 2786.860000 ;
+ RECT 1047.520000 2770.060000 1048.620000 2770.540000 ;
+ RECT 1043.390000 2770.060000 1044.390000 2770.540000 ;
+ RECT 1047.520000 2764.620000 1048.620000 2765.100000 ;
+ RECT 1043.390000 2764.620000 1044.390000 2765.100000 ;
+ RECT 1047.520000 2759.180000 1048.620000 2759.660000 ;
+ RECT 1047.520000 2753.740000 1048.620000 2754.220000 ;
+ RECT 1043.390000 2759.180000 1044.390000 2759.660000 ;
+ RECT 1043.390000 2753.740000 1044.390000 2754.220000 ;
+ RECT 1040.560000 2944.100000 1240.660000 2945.100000 ;
+ RECT 1040.560000 2751.730000 1240.660000 2752.730000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 2748.880000 1044.390000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 2948.140000 1044.390000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 2748.880000 1237.830000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 2948.140000 1237.830000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2751.730000 1041.560000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2751.730000 1240.660000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2944.100000 1041.560000 2945.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2944.100000 1240.660000 2945.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 2551.470000 1228.620000 2744.840000 ;
+ RECT 1182.520000 2551.470000 1183.620000 2744.840000 ;
+ RECT 1236.830000 2548.620000 1237.830000 2748.880000 ;
+ RECT 1137.520000 2551.470000 1138.620000 2744.840000 ;
+ RECT 1092.520000 2551.470000 1093.620000 2744.840000 ;
+ RECT 1047.520000 2551.470000 1048.620000 2744.840000 ;
+ RECT 1043.390000 2548.620000 1044.390000 2748.880000 ;
+ LAYER met3 ;
+ RECT 1227.520000 2738.440000 1228.620000 2738.920000 ;
+ RECT 1236.830000 2738.440000 1237.830000 2738.920000 ;
+ RECT 1236.830000 2727.560000 1237.830000 2728.040000 ;
+ RECT 1236.830000 2733.000000 1237.830000 2733.480000 ;
+ RECT 1227.520000 2733.000000 1228.620000 2733.480000 ;
+ RECT 1227.520000 2727.560000 1228.620000 2728.040000 ;
+ RECT 1227.520000 2722.120000 1228.620000 2722.600000 ;
+ RECT 1227.520000 2716.680000 1228.620000 2717.160000 ;
+ RECT 1236.830000 2722.120000 1237.830000 2722.600000 ;
+ RECT 1236.830000 2716.680000 1237.830000 2717.160000 ;
+ RECT 1227.520000 2700.360000 1228.620000 2700.840000 ;
+ RECT 1227.520000 2705.800000 1228.620000 2706.280000 ;
+ RECT 1236.830000 2705.800000 1237.830000 2706.280000 ;
+ RECT 1236.830000 2700.360000 1237.830000 2700.840000 ;
+ RECT 1227.520000 2711.240000 1228.620000 2711.720000 ;
+ RECT 1236.830000 2711.240000 1237.830000 2711.720000 ;
+ RECT 1182.520000 2738.440000 1183.620000 2738.920000 ;
+ RECT 1182.520000 2733.000000 1183.620000 2733.480000 ;
+ RECT 1182.520000 2727.560000 1183.620000 2728.040000 ;
+ RECT 1182.520000 2722.120000 1183.620000 2722.600000 ;
+ RECT 1182.520000 2700.360000 1183.620000 2700.840000 ;
+ RECT 1182.520000 2705.800000 1183.620000 2706.280000 ;
+ RECT 1182.520000 2711.240000 1183.620000 2711.720000 ;
+ RECT 1182.520000 2716.680000 1183.620000 2717.160000 ;
+ RECT 1236.830000 2689.480000 1237.830000 2689.960000 ;
+ RECT 1236.830000 2694.920000 1237.830000 2695.400000 ;
+ RECT 1227.520000 2694.920000 1228.620000 2695.400000 ;
+ RECT 1227.520000 2689.480000 1228.620000 2689.960000 ;
+ RECT 1227.520000 2684.040000 1228.620000 2684.520000 ;
+ RECT 1227.520000 2678.600000 1228.620000 2679.080000 ;
+ RECT 1236.830000 2684.040000 1237.830000 2684.520000 ;
+ RECT 1236.830000 2678.600000 1237.830000 2679.080000 ;
+ RECT 1236.830000 2662.280000 1237.830000 2662.760000 ;
+ RECT 1236.830000 2667.720000 1237.830000 2668.200000 ;
+ RECT 1236.830000 2673.160000 1237.830000 2673.640000 ;
+ RECT 1227.520000 2667.720000 1228.620000 2668.200000 ;
+ RECT 1227.520000 2662.280000 1228.620000 2662.760000 ;
+ RECT 1227.520000 2673.160000 1228.620000 2673.640000 ;
+ RECT 1227.520000 2656.840000 1228.620000 2657.320000 ;
+ RECT 1227.520000 2651.400000 1228.620000 2651.880000 ;
+ RECT 1236.830000 2656.840000 1237.830000 2657.320000 ;
+ RECT 1236.830000 2651.400000 1237.830000 2651.880000 ;
+ RECT 1182.520000 2694.920000 1183.620000 2695.400000 ;
+ RECT 1182.520000 2689.480000 1183.620000 2689.960000 ;
+ RECT 1182.520000 2684.040000 1183.620000 2684.520000 ;
+ RECT 1182.520000 2678.600000 1183.620000 2679.080000 ;
+ RECT 1182.520000 2667.720000 1183.620000 2668.200000 ;
+ RECT 1182.520000 2662.280000 1183.620000 2662.760000 ;
+ RECT 1182.520000 2656.840000 1183.620000 2657.320000 ;
+ RECT 1182.520000 2651.400000 1183.620000 2651.880000 ;
+ RECT 1182.520000 2673.160000 1183.620000 2673.640000 ;
+ RECT 1137.520000 2738.440000 1138.620000 2738.920000 ;
+ RECT 1137.520000 2733.000000 1138.620000 2733.480000 ;
+ RECT 1137.520000 2727.560000 1138.620000 2728.040000 ;
+ RECT 1092.520000 2738.440000 1093.620000 2738.920000 ;
+ RECT 1092.520000 2733.000000 1093.620000 2733.480000 ;
+ RECT 1092.520000 2727.560000 1093.620000 2728.040000 ;
+ RECT 1137.520000 2711.240000 1138.620000 2711.720000 ;
+ RECT 1137.520000 2705.800000 1138.620000 2706.280000 ;
+ RECT 1137.520000 2700.360000 1138.620000 2700.840000 ;
+ RECT 1137.520000 2716.680000 1138.620000 2717.160000 ;
+ RECT 1137.520000 2722.120000 1138.620000 2722.600000 ;
+ RECT 1092.520000 2722.120000 1093.620000 2722.600000 ;
+ RECT 1092.520000 2711.240000 1093.620000 2711.720000 ;
+ RECT 1092.520000 2705.800000 1093.620000 2706.280000 ;
+ RECT 1092.520000 2700.360000 1093.620000 2700.840000 ;
+ RECT 1092.520000 2716.680000 1093.620000 2717.160000 ;
+ RECT 1047.520000 2738.440000 1048.620000 2738.920000 ;
+ RECT 1043.390000 2738.440000 1044.390000 2738.920000 ;
+ RECT 1043.390000 2733.000000 1044.390000 2733.480000 ;
+ RECT 1047.520000 2733.000000 1048.620000 2733.480000 ;
+ RECT 1047.520000 2727.560000 1048.620000 2728.040000 ;
+ RECT 1043.390000 2727.560000 1044.390000 2728.040000 ;
+ RECT 1047.520000 2722.120000 1048.620000 2722.600000 ;
+ RECT 1043.390000 2722.120000 1044.390000 2722.600000 ;
+ RECT 1047.520000 2716.680000 1048.620000 2717.160000 ;
+ RECT 1043.390000 2716.680000 1044.390000 2717.160000 ;
+ RECT 1047.520000 2705.800000 1048.620000 2706.280000 ;
+ RECT 1043.390000 2705.800000 1044.390000 2706.280000 ;
+ RECT 1047.520000 2700.360000 1048.620000 2700.840000 ;
+ RECT 1043.390000 2700.360000 1044.390000 2700.840000 ;
+ RECT 1047.520000 2711.240000 1048.620000 2711.720000 ;
+ RECT 1043.390000 2711.240000 1044.390000 2711.720000 ;
+ RECT 1137.520000 2694.920000 1138.620000 2695.400000 ;
+ RECT 1137.520000 2689.480000 1138.620000 2689.960000 ;
+ RECT 1137.520000 2684.040000 1138.620000 2684.520000 ;
+ RECT 1137.520000 2678.600000 1138.620000 2679.080000 ;
+ RECT 1092.520000 2694.920000 1093.620000 2695.400000 ;
+ RECT 1092.520000 2689.480000 1093.620000 2689.960000 ;
+ RECT 1092.520000 2684.040000 1093.620000 2684.520000 ;
+ RECT 1092.520000 2678.600000 1093.620000 2679.080000 ;
+ RECT 1137.520000 2667.720000 1138.620000 2668.200000 ;
+ RECT 1137.520000 2651.400000 1138.620000 2651.880000 ;
+ RECT 1137.520000 2656.840000 1138.620000 2657.320000 ;
+ RECT 1137.520000 2662.280000 1138.620000 2662.760000 ;
+ RECT 1137.520000 2673.160000 1138.620000 2673.640000 ;
+ RECT 1092.520000 2651.400000 1093.620000 2651.880000 ;
+ RECT 1092.520000 2656.840000 1093.620000 2657.320000 ;
+ RECT 1092.520000 2662.280000 1093.620000 2662.760000 ;
+ RECT 1092.520000 2667.720000 1093.620000 2668.200000 ;
+ RECT 1092.520000 2673.160000 1093.620000 2673.640000 ;
+ RECT 1047.520000 2694.920000 1048.620000 2695.400000 ;
+ RECT 1043.390000 2694.920000 1044.390000 2695.400000 ;
+ RECT 1047.520000 2689.480000 1048.620000 2689.960000 ;
+ RECT 1043.390000 2689.480000 1044.390000 2689.960000 ;
+ RECT 1047.520000 2684.040000 1048.620000 2684.520000 ;
+ RECT 1043.390000 2684.040000 1044.390000 2684.520000 ;
+ RECT 1047.520000 2678.600000 1048.620000 2679.080000 ;
+ RECT 1043.390000 2678.600000 1044.390000 2679.080000 ;
+ RECT 1047.520000 2673.160000 1048.620000 2673.640000 ;
+ RECT 1047.520000 2667.720000 1048.620000 2668.200000 ;
+ RECT 1043.390000 2673.160000 1044.390000 2673.640000 ;
+ RECT 1043.390000 2667.720000 1044.390000 2668.200000 ;
+ RECT 1047.520000 2662.280000 1048.620000 2662.760000 ;
+ RECT 1043.390000 2662.280000 1044.390000 2662.760000 ;
+ RECT 1047.520000 2656.840000 1048.620000 2657.320000 ;
+ RECT 1043.390000 2656.840000 1044.390000 2657.320000 ;
+ RECT 1047.520000 2651.400000 1048.620000 2651.880000 ;
+ RECT 1043.390000 2651.400000 1044.390000 2651.880000 ;
+ RECT 1227.520000 2645.960000 1228.620000 2646.440000 ;
+ RECT 1227.520000 2640.520000 1228.620000 2641.000000 ;
+ RECT 1236.830000 2645.960000 1237.830000 2646.440000 ;
+ RECT 1236.830000 2640.520000 1237.830000 2641.000000 ;
+ RECT 1236.830000 2624.200000 1237.830000 2624.680000 ;
+ RECT 1236.830000 2629.640000 1237.830000 2630.120000 ;
+ RECT 1236.830000 2635.080000 1237.830000 2635.560000 ;
+ RECT 1227.520000 2635.080000 1228.620000 2635.560000 ;
+ RECT 1227.520000 2629.640000 1228.620000 2630.120000 ;
+ RECT 1227.520000 2624.200000 1228.620000 2624.680000 ;
+ RECT 1227.520000 2613.320000 1228.620000 2613.800000 ;
+ RECT 1227.520000 2618.760000 1228.620000 2619.240000 ;
+ RECT 1236.830000 2618.760000 1237.830000 2619.240000 ;
+ RECT 1236.830000 2613.320000 1237.830000 2613.800000 ;
+ RECT 1236.830000 2602.440000 1237.830000 2602.920000 ;
+ RECT 1236.830000 2607.880000 1237.830000 2608.360000 ;
+ RECT 1227.520000 2602.440000 1228.620000 2602.920000 ;
+ RECT 1227.520000 2607.880000 1228.620000 2608.360000 ;
+ RECT 1182.520000 2645.960000 1183.620000 2646.440000 ;
+ RECT 1182.520000 2640.520000 1183.620000 2641.000000 ;
+ RECT 1182.520000 2635.080000 1183.620000 2635.560000 ;
+ RECT 1182.520000 2629.640000 1183.620000 2630.120000 ;
+ RECT 1182.520000 2624.200000 1183.620000 2624.680000 ;
+ RECT 1182.520000 2602.440000 1183.620000 2602.920000 ;
+ RECT 1182.520000 2607.880000 1183.620000 2608.360000 ;
+ RECT 1182.520000 2613.320000 1183.620000 2613.800000 ;
+ RECT 1182.520000 2618.760000 1183.620000 2619.240000 ;
+ RECT 1227.520000 2597.000000 1228.620000 2597.480000 ;
+ RECT 1227.520000 2591.560000 1228.620000 2592.040000 ;
+ RECT 1236.830000 2597.000000 1237.830000 2597.480000 ;
+ RECT 1236.830000 2591.560000 1237.830000 2592.040000 ;
+ RECT 1227.520000 2580.680000 1228.620000 2581.160000 ;
+ RECT 1227.520000 2575.240000 1228.620000 2575.720000 ;
+ RECT 1236.830000 2580.680000 1237.830000 2581.160000 ;
+ RECT 1236.830000 2575.240000 1237.830000 2575.720000 ;
+ RECT 1227.520000 2586.120000 1228.620000 2586.600000 ;
+ RECT 1236.830000 2586.120000 1237.830000 2586.600000 ;
+ RECT 1236.830000 2564.360000 1237.830000 2564.840000 ;
+ RECT 1236.830000 2569.800000 1237.830000 2570.280000 ;
+ RECT 1227.520000 2569.800000 1228.620000 2570.280000 ;
+ RECT 1227.520000 2564.360000 1228.620000 2564.840000 ;
+ RECT 1227.520000 2558.920000 1228.620000 2559.400000 ;
+ RECT 1227.520000 2553.480000 1228.620000 2553.960000 ;
+ RECT 1236.830000 2558.920000 1237.830000 2559.400000 ;
+ RECT 1236.830000 2553.480000 1237.830000 2553.960000 ;
+ RECT 1182.520000 2597.000000 1183.620000 2597.480000 ;
+ RECT 1182.520000 2591.560000 1183.620000 2592.040000 ;
+ RECT 1182.520000 2586.120000 1183.620000 2586.600000 ;
+ RECT 1182.520000 2580.680000 1183.620000 2581.160000 ;
+ RECT 1182.520000 2575.240000 1183.620000 2575.720000 ;
+ RECT 1182.520000 2569.800000 1183.620000 2570.280000 ;
+ RECT 1182.520000 2564.360000 1183.620000 2564.840000 ;
+ RECT 1182.520000 2558.920000 1183.620000 2559.400000 ;
+ RECT 1182.520000 2553.480000 1183.620000 2553.960000 ;
+ RECT 1137.520000 2645.960000 1138.620000 2646.440000 ;
+ RECT 1137.520000 2640.520000 1138.620000 2641.000000 ;
+ RECT 1137.520000 2635.080000 1138.620000 2635.560000 ;
+ RECT 1137.520000 2629.640000 1138.620000 2630.120000 ;
+ RECT 1137.520000 2624.200000 1138.620000 2624.680000 ;
+ RECT 1092.520000 2645.960000 1093.620000 2646.440000 ;
+ RECT 1092.520000 2640.520000 1093.620000 2641.000000 ;
+ RECT 1092.520000 2635.080000 1093.620000 2635.560000 ;
+ RECT 1092.520000 2629.640000 1093.620000 2630.120000 ;
+ RECT 1092.520000 2624.200000 1093.620000 2624.680000 ;
+ RECT 1137.520000 2618.760000 1138.620000 2619.240000 ;
+ RECT 1137.520000 2613.320000 1138.620000 2613.800000 ;
+ RECT 1137.520000 2607.880000 1138.620000 2608.360000 ;
+ RECT 1137.520000 2602.440000 1138.620000 2602.920000 ;
+ RECT 1092.520000 2613.320000 1093.620000 2613.800000 ;
+ RECT 1092.520000 2607.880000 1093.620000 2608.360000 ;
+ RECT 1092.520000 2602.440000 1093.620000 2602.920000 ;
+ RECT 1092.520000 2618.760000 1093.620000 2619.240000 ;
+ RECT 1047.520000 2645.960000 1048.620000 2646.440000 ;
+ RECT 1043.390000 2645.960000 1044.390000 2646.440000 ;
+ RECT 1047.520000 2640.520000 1048.620000 2641.000000 ;
+ RECT 1043.390000 2640.520000 1044.390000 2641.000000 ;
+ RECT 1047.520000 2635.080000 1048.620000 2635.560000 ;
+ RECT 1043.390000 2635.080000 1044.390000 2635.560000 ;
+ RECT 1047.520000 2624.200000 1048.620000 2624.680000 ;
+ RECT 1043.390000 2624.200000 1044.390000 2624.680000 ;
+ RECT 1043.390000 2629.640000 1044.390000 2630.120000 ;
+ RECT 1047.520000 2629.640000 1048.620000 2630.120000 ;
+ RECT 1047.520000 2618.760000 1048.620000 2619.240000 ;
+ RECT 1043.390000 2618.760000 1044.390000 2619.240000 ;
+ RECT 1047.520000 2613.320000 1048.620000 2613.800000 ;
+ RECT 1043.390000 2613.320000 1044.390000 2613.800000 ;
+ RECT 1047.520000 2607.880000 1048.620000 2608.360000 ;
+ RECT 1043.390000 2607.880000 1044.390000 2608.360000 ;
+ RECT 1047.520000 2602.440000 1048.620000 2602.920000 ;
+ RECT 1043.390000 2602.440000 1044.390000 2602.920000 ;
+ RECT 1137.520000 2597.000000 1138.620000 2597.480000 ;
+ RECT 1137.520000 2591.560000 1138.620000 2592.040000 ;
+ RECT 1137.520000 2586.120000 1138.620000 2586.600000 ;
+ RECT 1137.520000 2580.680000 1138.620000 2581.160000 ;
+ RECT 1137.520000 2575.240000 1138.620000 2575.720000 ;
+ RECT 1092.520000 2597.000000 1093.620000 2597.480000 ;
+ RECT 1092.520000 2591.560000 1093.620000 2592.040000 ;
+ RECT 1092.520000 2586.120000 1093.620000 2586.600000 ;
+ RECT 1092.520000 2580.680000 1093.620000 2581.160000 ;
+ RECT 1092.520000 2575.240000 1093.620000 2575.720000 ;
+ RECT 1137.520000 2553.480000 1138.620000 2553.960000 ;
+ RECT 1137.520000 2558.920000 1138.620000 2559.400000 ;
+ RECT 1137.520000 2564.360000 1138.620000 2564.840000 ;
+ RECT 1137.520000 2569.800000 1138.620000 2570.280000 ;
+ RECT 1092.520000 2553.480000 1093.620000 2553.960000 ;
+ RECT 1092.520000 2558.920000 1093.620000 2559.400000 ;
+ RECT 1092.520000 2564.360000 1093.620000 2564.840000 ;
+ RECT 1092.520000 2569.800000 1093.620000 2570.280000 ;
+ RECT 1047.520000 2597.000000 1048.620000 2597.480000 ;
+ RECT 1043.390000 2597.000000 1044.390000 2597.480000 ;
+ RECT 1047.520000 2591.560000 1048.620000 2592.040000 ;
+ RECT 1043.390000 2591.560000 1044.390000 2592.040000 ;
+ RECT 1047.520000 2580.680000 1048.620000 2581.160000 ;
+ RECT 1043.390000 2580.680000 1044.390000 2581.160000 ;
+ RECT 1047.520000 2575.240000 1048.620000 2575.720000 ;
+ RECT 1043.390000 2575.240000 1044.390000 2575.720000 ;
+ RECT 1047.520000 2586.120000 1048.620000 2586.600000 ;
+ RECT 1043.390000 2586.120000 1044.390000 2586.600000 ;
+ RECT 1047.520000 2569.800000 1048.620000 2570.280000 ;
+ RECT 1043.390000 2569.800000 1044.390000 2570.280000 ;
+ RECT 1047.520000 2564.360000 1048.620000 2564.840000 ;
+ RECT 1043.390000 2564.360000 1044.390000 2564.840000 ;
+ RECT 1047.520000 2558.920000 1048.620000 2559.400000 ;
+ RECT 1047.520000 2553.480000 1048.620000 2553.960000 ;
+ RECT 1043.390000 2558.920000 1044.390000 2559.400000 ;
+ RECT 1043.390000 2553.480000 1044.390000 2553.960000 ;
+ RECT 1040.560000 2743.840000 1240.660000 2744.840000 ;
+ RECT 1040.560000 2551.470000 1240.660000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 2548.620000 1044.390000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 2747.880000 1044.390000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 2548.620000 1237.830000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 2747.880000 1237.830000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2551.470000 1041.560000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2551.470000 1240.660000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2743.840000 1041.560000 2744.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2743.840000 1240.660000 2744.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 2351.210000 1228.620000 2544.580000 ;
+ RECT 1182.520000 2351.210000 1183.620000 2544.580000 ;
+ RECT 1236.830000 2348.360000 1237.830000 2548.620000 ;
+ RECT 1137.520000 2351.210000 1138.620000 2544.580000 ;
+ RECT 1092.520000 2351.210000 1093.620000 2544.580000 ;
+ RECT 1047.520000 2351.210000 1048.620000 2544.580000 ;
+ RECT 1043.390000 2348.360000 1044.390000 2548.620000 ;
+ LAYER met3 ;
+ RECT 1227.520000 2538.180000 1228.620000 2538.660000 ;
+ RECT 1236.830000 2538.180000 1237.830000 2538.660000 ;
+ RECT 1236.830000 2527.300000 1237.830000 2527.780000 ;
+ RECT 1236.830000 2532.740000 1237.830000 2533.220000 ;
+ RECT 1227.520000 2532.740000 1228.620000 2533.220000 ;
+ RECT 1227.520000 2527.300000 1228.620000 2527.780000 ;
+ RECT 1227.520000 2521.860000 1228.620000 2522.340000 ;
+ RECT 1227.520000 2516.420000 1228.620000 2516.900000 ;
+ RECT 1236.830000 2521.860000 1237.830000 2522.340000 ;
+ RECT 1236.830000 2516.420000 1237.830000 2516.900000 ;
+ RECT 1227.520000 2500.100000 1228.620000 2500.580000 ;
+ RECT 1227.520000 2505.540000 1228.620000 2506.020000 ;
+ RECT 1236.830000 2505.540000 1237.830000 2506.020000 ;
+ RECT 1236.830000 2500.100000 1237.830000 2500.580000 ;
+ RECT 1227.520000 2510.980000 1228.620000 2511.460000 ;
+ RECT 1236.830000 2510.980000 1237.830000 2511.460000 ;
+ RECT 1182.520000 2538.180000 1183.620000 2538.660000 ;
+ RECT 1182.520000 2532.740000 1183.620000 2533.220000 ;
+ RECT 1182.520000 2527.300000 1183.620000 2527.780000 ;
+ RECT 1182.520000 2521.860000 1183.620000 2522.340000 ;
+ RECT 1182.520000 2500.100000 1183.620000 2500.580000 ;
+ RECT 1182.520000 2505.540000 1183.620000 2506.020000 ;
+ RECT 1182.520000 2510.980000 1183.620000 2511.460000 ;
+ RECT 1182.520000 2516.420000 1183.620000 2516.900000 ;
+ RECT 1236.830000 2489.220000 1237.830000 2489.700000 ;
+ RECT 1236.830000 2494.660000 1237.830000 2495.140000 ;
+ RECT 1227.520000 2494.660000 1228.620000 2495.140000 ;
+ RECT 1227.520000 2489.220000 1228.620000 2489.700000 ;
+ RECT 1227.520000 2483.780000 1228.620000 2484.260000 ;
+ RECT 1227.520000 2478.340000 1228.620000 2478.820000 ;
+ RECT 1236.830000 2483.780000 1237.830000 2484.260000 ;
+ RECT 1236.830000 2478.340000 1237.830000 2478.820000 ;
+ RECT 1236.830000 2462.020000 1237.830000 2462.500000 ;
+ RECT 1236.830000 2467.460000 1237.830000 2467.940000 ;
+ RECT 1236.830000 2472.900000 1237.830000 2473.380000 ;
+ RECT 1227.520000 2467.460000 1228.620000 2467.940000 ;
+ RECT 1227.520000 2462.020000 1228.620000 2462.500000 ;
+ RECT 1227.520000 2472.900000 1228.620000 2473.380000 ;
+ RECT 1227.520000 2456.580000 1228.620000 2457.060000 ;
+ RECT 1227.520000 2451.140000 1228.620000 2451.620000 ;
+ RECT 1236.830000 2456.580000 1237.830000 2457.060000 ;
+ RECT 1236.830000 2451.140000 1237.830000 2451.620000 ;
+ RECT 1182.520000 2494.660000 1183.620000 2495.140000 ;
+ RECT 1182.520000 2489.220000 1183.620000 2489.700000 ;
+ RECT 1182.520000 2483.780000 1183.620000 2484.260000 ;
+ RECT 1182.520000 2478.340000 1183.620000 2478.820000 ;
+ RECT 1182.520000 2467.460000 1183.620000 2467.940000 ;
+ RECT 1182.520000 2462.020000 1183.620000 2462.500000 ;
+ RECT 1182.520000 2456.580000 1183.620000 2457.060000 ;
+ RECT 1182.520000 2451.140000 1183.620000 2451.620000 ;
+ RECT 1182.520000 2472.900000 1183.620000 2473.380000 ;
+ RECT 1137.520000 2538.180000 1138.620000 2538.660000 ;
+ RECT 1137.520000 2532.740000 1138.620000 2533.220000 ;
+ RECT 1137.520000 2527.300000 1138.620000 2527.780000 ;
+ RECT 1092.520000 2538.180000 1093.620000 2538.660000 ;
+ RECT 1092.520000 2532.740000 1093.620000 2533.220000 ;
+ RECT 1092.520000 2527.300000 1093.620000 2527.780000 ;
+ RECT 1137.520000 2510.980000 1138.620000 2511.460000 ;
+ RECT 1137.520000 2505.540000 1138.620000 2506.020000 ;
+ RECT 1137.520000 2500.100000 1138.620000 2500.580000 ;
+ RECT 1137.520000 2516.420000 1138.620000 2516.900000 ;
+ RECT 1137.520000 2521.860000 1138.620000 2522.340000 ;
+ RECT 1092.520000 2521.860000 1093.620000 2522.340000 ;
+ RECT 1092.520000 2510.980000 1093.620000 2511.460000 ;
+ RECT 1092.520000 2505.540000 1093.620000 2506.020000 ;
+ RECT 1092.520000 2500.100000 1093.620000 2500.580000 ;
+ RECT 1092.520000 2516.420000 1093.620000 2516.900000 ;
+ RECT 1047.520000 2538.180000 1048.620000 2538.660000 ;
+ RECT 1043.390000 2538.180000 1044.390000 2538.660000 ;
+ RECT 1043.390000 2532.740000 1044.390000 2533.220000 ;
+ RECT 1047.520000 2532.740000 1048.620000 2533.220000 ;
+ RECT 1047.520000 2527.300000 1048.620000 2527.780000 ;
+ RECT 1043.390000 2527.300000 1044.390000 2527.780000 ;
+ RECT 1047.520000 2521.860000 1048.620000 2522.340000 ;
+ RECT 1043.390000 2521.860000 1044.390000 2522.340000 ;
+ RECT 1047.520000 2516.420000 1048.620000 2516.900000 ;
+ RECT 1043.390000 2516.420000 1044.390000 2516.900000 ;
+ RECT 1047.520000 2505.540000 1048.620000 2506.020000 ;
+ RECT 1043.390000 2505.540000 1044.390000 2506.020000 ;
+ RECT 1047.520000 2500.100000 1048.620000 2500.580000 ;
+ RECT 1043.390000 2500.100000 1044.390000 2500.580000 ;
+ RECT 1047.520000 2510.980000 1048.620000 2511.460000 ;
+ RECT 1043.390000 2510.980000 1044.390000 2511.460000 ;
+ RECT 1137.520000 2494.660000 1138.620000 2495.140000 ;
+ RECT 1137.520000 2489.220000 1138.620000 2489.700000 ;
+ RECT 1137.520000 2483.780000 1138.620000 2484.260000 ;
+ RECT 1137.520000 2478.340000 1138.620000 2478.820000 ;
+ RECT 1092.520000 2494.660000 1093.620000 2495.140000 ;
+ RECT 1092.520000 2489.220000 1093.620000 2489.700000 ;
+ RECT 1092.520000 2483.780000 1093.620000 2484.260000 ;
+ RECT 1092.520000 2478.340000 1093.620000 2478.820000 ;
+ RECT 1137.520000 2467.460000 1138.620000 2467.940000 ;
+ RECT 1137.520000 2451.140000 1138.620000 2451.620000 ;
+ RECT 1137.520000 2456.580000 1138.620000 2457.060000 ;
+ RECT 1137.520000 2462.020000 1138.620000 2462.500000 ;
+ RECT 1137.520000 2472.900000 1138.620000 2473.380000 ;
+ RECT 1092.520000 2451.140000 1093.620000 2451.620000 ;
+ RECT 1092.520000 2456.580000 1093.620000 2457.060000 ;
+ RECT 1092.520000 2462.020000 1093.620000 2462.500000 ;
+ RECT 1092.520000 2467.460000 1093.620000 2467.940000 ;
+ RECT 1092.520000 2472.900000 1093.620000 2473.380000 ;
+ RECT 1047.520000 2494.660000 1048.620000 2495.140000 ;
+ RECT 1043.390000 2494.660000 1044.390000 2495.140000 ;
+ RECT 1047.520000 2489.220000 1048.620000 2489.700000 ;
+ RECT 1043.390000 2489.220000 1044.390000 2489.700000 ;
+ RECT 1047.520000 2483.780000 1048.620000 2484.260000 ;
+ RECT 1043.390000 2483.780000 1044.390000 2484.260000 ;
+ RECT 1047.520000 2478.340000 1048.620000 2478.820000 ;
+ RECT 1043.390000 2478.340000 1044.390000 2478.820000 ;
+ RECT 1047.520000 2472.900000 1048.620000 2473.380000 ;
+ RECT 1047.520000 2467.460000 1048.620000 2467.940000 ;
+ RECT 1043.390000 2472.900000 1044.390000 2473.380000 ;
+ RECT 1043.390000 2467.460000 1044.390000 2467.940000 ;
+ RECT 1047.520000 2462.020000 1048.620000 2462.500000 ;
+ RECT 1043.390000 2462.020000 1044.390000 2462.500000 ;
+ RECT 1047.520000 2456.580000 1048.620000 2457.060000 ;
+ RECT 1043.390000 2456.580000 1044.390000 2457.060000 ;
+ RECT 1047.520000 2451.140000 1048.620000 2451.620000 ;
+ RECT 1043.390000 2451.140000 1044.390000 2451.620000 ;
+ RECT 1227.520000 2445.700000 1228.620000 2446.180000 ;
+ RECT 1227.520000 2440.260000 1228.620000 2440.740000 ;
+ RECT 1236.830000 2445.700000 1237.830000 2446.180000 ;
+ RECT 1236.830000 2440.260000 1237.830000 2440.740000 ;
+ RECT 1236.830000 2423.940000 1237.830000 2424.420000 ;
+ RECT 1236.830000 2429.380000 1237.830000 2429.860000 ;
+ RECT 1236.830000 2434.820000 1237.830000 2435.300000 ;
+ RECT 1227.520000 2434.820000 1228.620000 2435.300000 ;
+ RECT 1227.520000 2429.380000 1228.620000 2429.860000 ;
+ RECT 1227.520000 2423.940000 1228.620000 2424.420000 ;
+ RECT 1227.520000 2413.060000 1228.620000 2413.540000 ;
+ RECT 1227.520000 2418.500000 1228.620000 2418.980000 ;
+ RECT 1236.830000 2418.500000 1237.830000 2418.980000 ;
+ RECT 1236.830000 2413.060000 1237.830000 2413.540000 ;
+ RECT 1236.830000 2402.180000 1237.830000 2402.660000 ;
+ RECT 1236.830000 2407.620000 1237.830000 2408.100000 ;
+ RECT 1227.520000 2402.180000 1228.620000 2402.660000 ;
+ RECT 1227.520000 2407.620000 1228.620000 2408.100000 ;
+ RECT 1182.520000 2445.700000 1183.620000 2446.180000 ;
+ RECT 1182.520000 2440.260000 1183.620000 2440.740000 ;
+ RECT 1182.520000 2434.820000 1183.620000 2435.300000 ;
+ RECT 1182.520000 2429.380000 1183.620000 2429.860000 ;
+ RECT 1182.520000 2423.940000 1183.620000 2424.420000 ;
+ RECT 1182.520000 2402.180000 1183.620000 2402.660000 ;
+ RECT 1182.520000 2407.620000 1183.620000 2408.100000 ;
+ RECT 1182.520000 2413.060000 1183.620000 2413.540000 ;
+ RECT 1182.520000 2418.500000 1183.620000 2418.980000 ;
+ RECT 1227.520000 2396.740000 1228.620000 2397.220000 ;
+ RECT 1227.520000 2391.300000 1228.620000 2391.780000 ;
+ RECT 1236.830000 2396.740000 1237.830000 2397.220000 ;
+ RECT 1236.830000 2391.300000 1237.830000 2391.780000 ;
+ RECT 1227.520000 2380.420000 1228.620000 2380.900000 ;
+ RECT 1227.520000 2374.980000 1228.620000 2375.460000 ;
+ RECT 1236.830000 2380.420000 1237.830000 2380.900000 ;
+ RECT 1236.830000 2374.980000 1237.830000 2375.460000 ;
+ RECT 1227.520000 2385.860000 1228.620000 2386.340000 ;
+ RECT 1236.830000 2385.860000 1237.830000 2386.340000 ;
+ RECT 1236.830000 2364.100000 1237.830000 2364.580000 ;
+ RECT 1236.830000 2369.540000 1237.830000 2370.020000 ;
+ RECT 1227.520000 2369.540000 1228.620000 2370.020000 ;
+ RECT 1227.520000 2364.100000 1228.620000 2364.580000 ;
+ RECT 1227.520000 2358.660000 1228.620000 2359.140000 ;
+ RECT 1227.520000 2353.220000 1228.620000 2353.700000 ;
+ RECT 1236.830000 2358.660000 1237.830000 2359.140000 ;
+ RECT 1236.830000 2353.220000 1237.830000 2353.700000 ;
+ RECT 1182.520000 2396.740000 1183.620000 2397.220000 ;
+ RECT 1182.520000 2391.300000 1183.620000 2391.780000 ;
+ RECT 1182.520000 2385.860000 1183.620000 2386.340000 ;
+ RECT 1182.520000 2380.420000 1183.620000 2380.900000 ;
+ RECT 1182.520000 2374.980000 1183.620000 2375.460000 ;
+ RECT 1182.520000 2369.540000 1183.620000 2370.020000 ;
+ RECT 1182.520000 2364.100000 1183.620000 2364.580000 ;
+ RECT 1182.520000 2358.660000 1183.620000 2359.140000 ;
+ RECT 1182.520000 2353.220000 1183.620000 2353.700000 ;
+ RECT 1137.520000 2445.700000 1138.620000 2446.180000 ;
+ RECT 1137.520000 2440.260000 1138.620000 2440.740000 ;
+ RECT 1137.520000 2434.820000 1138.620000 2435.300000 ;
+ RECT 1137.520000 2429.380000 1138.620000 2429.860000 ;
+ RECT 1137.520000 2423.940000 1138.620000 2424.420000 ;
+ RECT 1092.520000 2445.700000 1093.620000 2446.180000 ;
+ RECT 1092.520000 2440.260000 1093.620000 2440.740000 ;
+ RECT 1092.520000 2434.820000 1093.620000 2435.300000 ;
+ RECT 1092.520000 2429.380000 1093.620000 2429.860000 ;
+ RECT 1092.520000 2423.940000 1093.620000 2424.420000 ;
+ RECT 1137.520000 2418.500000 1138.620000 2418.980000 ;
+ RECT 1137.520000 2413.060000 1138.620000 2413.540000 ;
+ RECT 1137.520000 2407.620000 1138.620000 2408.100000 ;
+ RECT 1137.520000 2402.180000 1138.620000 2402.660000 ;
+ RECT 1092.520000 2413.060000 1093.620000 2413.540000 ;
+ RECT 1092.520000 2407.620000 1093.620000 2408.100000 ;
+ RECT 1092.520000 2402.180000 1093.620000 2402.660000 ;
+ RECT 1092.520000 2418.500000 1093.620000 2418.980000 ;
+ RECT 1047.520000 2445.700000 1048.620000 2446.180000 ;
+ RECT 1043.390000 2445.700000 1044.390000 2446.180000 ;
+ RECT 1047.520000 2440.260000 1048.620000 2440.740000 ;
+ RECT 1043.390000 2440.260000 1044.390000 2440.740000 ;
+ RECT 1047.520000 2434.820000 1048.620000 2435.300000 ;
+ RECT 1043.390000 2434.820000 1044.390000 2435.300000 ;
+ RECT 1047.520000 2423.940000 1048.620000 2424.420000 ;
+ RECT 1043.390000 2423.940000 1044.390000 2424.420000 ;
+ RECT 1043.390000 2429.380000 1044.390000 2429.860000 ;
+ RECT 1047.520000 2429.380000 1048.620000 2429.860000 ;
+ RECT 1047.520000 2418.500000 1048.620000 2418.980000 ;
+ RECT 1043.390000 2418.500000 1044.390000 2418.980000 ;
+ RECT 1047.520000 2413.060000 1048.620000 2413.540000 ;
+ RECT 1043.390000 2413.060000 1044.390000 2413.540000 ;
+ RECT 1047.520000 2407.620000 1048.620000 2408.100000 ;
+ RECT 1043.390000 2407.620000 1044.390000 2408.100000 ;
+ RECT 1047.520000 2402.180000 1048.620000 2402.660000 ;
+ RECT 1043.390000 2402.180000 1044.390000 2402.660000 ;
+ RECT 1137.520000 2396.740000 1138.620000 2397.220000 ;
+ RECT 1137.520000 2391.300000 1138.620000 2391.780000 ;
+ RECT 1137.520000 2385.860000 1138.620000 2386.340000 ;
+ RECT 1137.520000 2380.420000 1138.620000 2380.900000 ;
+ RECT 1137.520000 2374.980000 1138.620000 2375.460000 ;
+ RECT 1092.520000 2396.740000 1093.620000 2397.220000 ;
+ RECT 1092.520000 2391.300000 1093.620000 2391.780000 ;
+ RECT 1092.520000 2385.860000 1093.620000 2386.340000 ;
+ RECT 1092.520000 2380.420000 1093.620000 2380.900000 ;
+ RECT 1092.520000 2374.980000 1093.620000 2375.460000 ;
+ RECT 1137.520000 2353.220000 1138.620000 2353.700000 ;
+ RECT 1137.520000 2358.660000 1138.620000 2359.140000 ;
+ RECT 1137.520000 2364.100000 1138.620000 2364.580000 ;
+ RECT 1137.520000 2369.540000 1138.620000 2370.020000 ;
+ RECT 1092.520000 2353.220000 1093.620000 2353.700000 ;
+ RECT 1092.520000 2358.660000 1093.620000 2359.140000 ;
+ RECT 1092.520000 2364.100000 1093.620000 2364.580000 ;
+ RECT 1092.520000 2369.540000 1093.620000 2370.020000 ;
+ RECT 1047.520000 2396.740000 1048.620000 2397.220000 ;
+ RECT 1043.390000 2396.740000 1044.390000 2397.220000 ;
+ RECT 1047.520000 2391.300000 1048.620000 2391.780000 ;
+ RECT 1043.390000 2391.300000 1044.390000 2391.780000 ;
+ RECT 1047.520000 2380.420000 1048.620000 2380.900000 ;
+ RECT 1043.390000 2380.420000 1044.390000 2380.900000 ;
+ RECT 1047.520000 2374.980000 1048.620000 2375.460000 ;
+ RECT 1043.390000 2374.980000 1044.390000 2375.460000 ;
+ RECT 1047.520000 2385.860000 1048.620000 2386.340000 ;
+ RECT 1043.390000 2385.860000 1044.390000 2386.340000 ;
+ RECT 1047.520000 2369.540000 1048.620000 2370.020000 ;
+ RECT 1043.390000 2369.540000 1044.390000 2370.020000 ;
+ RECT 1047.520000 2364.100000 1048.620000 2364.580000 ;
+ RECT 1043.390000 2364.100000 1044.390000 2364.580000 ;
+ RECT 1047.520000 2358.660000 1048.620000 2359.140000 ;
+ RECT 1047.520000 2353.220000 1048.620000 2353.700000 ;
+ RECT 1043.390000 2358.660000 1044.390000 2359.140000 ;
+ RECT 1043.390000 2353.220000 1044.390000 2353.700000 ;
+ RECT 1040.560000 2543.580000 1240.660000 2544.580000 ;
+ RECT 1040.560000 2351.210000 1240.660000 2352.210000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 2348.360000 1044.390000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 2547.620000 1044.390000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 2348.360000 1237.830000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 2547.620000 1237.830000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2351.210000 1041.560000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2351.210000 1240.660000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2543.580000 1041.560000 2544.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2543.580000 1240.660000 2544.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 2150.950000 1228.620000 2344.320000 ;
+ RECT 1182.520000 2150.950000 1183.620000 2344.320000 ;
+ RECT 1236.830000 2148.100000 1237.830000 2348.360000 ;
+ RECT 1137.520000 2150.950000 1138.620000 2344.320000 ;
+ RECT 1092.520000 2150.950000 1093.620000 2344.320000 ;
+ RECT 1047.520000 2150.950000 1048.620000 2344.320000 ;
+ RECT 1043.390000 2148.100000 1044.390000 2348.360000 ;
+ LAYER met3 ;
+ RECT 1227.520000 2337.920000 1228.620000 2338.400000 ;
+ RECT 1236.830000 2337.920000 1237.830000 2338.400000 ;
+ RECT 1236.830000 2327.040000 1237.830000 2327.520000 ;
+ RECT 1236.830000 2332.480000 1237.830000 2332.960000 ;
+ RECT 1227.520000 2332.480000 1228.620000 2332.960000 ;
+ RECT 1227.520000 2327.040000 1228.620000 2327.520000 ;
+ RECT 1227.520000 2321.600000 1228.620000 2322.080000 ;
+ RECT 1227.520000 2316.160000 1228.620000 2316.640000 ;
+ RECT 1236.830000 2321.600000 1237.830000 2322.080000 ;
+ RECT 1236.830000 2316.160000 1237.830000 2316.640000 ;
+ RECT 1227.520000 2299.840000 1228.620000 2300.320000 ;
+ RECT 1227.520000 2305.280000 1228.620000 2305.760000 ;
+ RECT 1236.830000 2305.280000 1237.830000 2305.760000 ;
+ RECT 1236.830000 2299.840000 1237.830000 2300.320000 ;
+ RECT 1227.520000 2310.720000 1228.620000 2311.200000 ;
+ RECT 1236.830000 2310.720000 1237.830000 2311.200000 ;
+ RECT 1182.520000 2337.920000 1183.620000 2338.400000 ;
+ RECT 1182.520000 2332.480000 1183.620000 2332.960000 ;
+ RECT 1182.520000 2327.040000 1183.620000 2327.520000 ;
+ RECT 1182.520000 2321.600000 1183.620000 2322.080000 ;
+ RECT 1182.520000 2299.840000 1183.620000 2300.320000 ;
+ RECT 1182.520000 2305.280000 1183.620000 2305.760000 ;
+ RECT 1182.520000 2310.720000 1183.620000 2311.200000 ;
+ RECT 1182.520000 2316.160000 1183.620000 2316.640000 ;
+ RECT 1236.830000 2288.960000 1237.830000 2289.440000 ;
+ RECT 1236.830000 2294.400000 1237.830000 2294.880000 ;
+ RECT 1227.520000 2294.400000 1228.620000 2294.880000 ;
+ RECT 1227.520000 2288.960000 1228.620000 2289.440000 ;
+ RECT 1227.520000 2283.520000 1228.620000 2284.000000 ;
+ RECT 1227.520000 2278.080000 1228.620000 2278.560000 ;
+ RECT 1236.830000 2283.520000 1237.830000 2284.000000 ;
+ RECT 1236.830000 2278.080000 1237.830000 2278.560000 ;
+ RECT 1236.830000 2261.760000 1237.830000 2262.240000 ;
+ RECT 1236.830000 2267.200000 1237.830000 2267.680000 ;
+ RECT 1236.830000 2272.640000 1237.830000 2273.120000 ;
+ RECT 1227.520000 2267.200000 1228.620000 2267.680000 ;
+ RECT 1227.520000 2261.760000 1228.620000 2262.240000 ;
+ RECT 1227.520000 2272.640000 1228.620000 2273.120000 ;
+ RECT 1227.520000 2256.320000 1228.620000 2256.800000 ;
+ RECT 1227.520000 2250.880000 1228.620000 2251.360000 ;
+ RECT 1236.830000 2256.320000 1237.830000 2256.800000 ;
+ RECT 1236.830000 2250.880000 1237.830000 2251.360000 ;
+ RECT 1182.520000 2294.400000 1183.620000 2294.880000 ;
+ RECT 1182.520000 2288.960000 1183.620000 2289.440000 ;
+ RECT 1182.520000 2283.520000 1183.620000 2284.000000 ;
+ RECT 1182.520000 2278.080000 1183.620000 2278.560000 ;
+ RECT 1182.520000 2267.200000 1183.620000 2267.680000 ;
+ RECT 1182.520000 2261.760000 1183.620000 2262.240000 ;
+ RECT 1182.520000 2256.320000 1183.620000 2256.800000 ;
+ RECT 1182.520000 2250.880000 1183.620000 2251.360000 ;
+ RECT 1182.520000 2272.640000 1183.620000 2273.120000 ;
+ RECT 1137.520000 2337.920000 1138.620000 2338.400000 ;
+ RECT 1137.520000 2332.480000 1138.620000 2332.960000 ;
+ RECT 1137.520000 2327.040000 1138.620000 2327.520000 ;
+ RECT 1092.520000 2337.920000 1093.620000 2338.400000 ;
+ RECT 1092.520000 2332.480000 1093.620000 2332.960000 ;
+ RECT 1092.520000 2327.040000 1093.620000 2327.520000 ;
+ RECT 1137.520000 2310.720000 1138.620000 2311.200000 ;
+ RECT 1137.520000 2305.280000 1138.620000 2305.760000 ;
+ RECT 1137.520000 2299.840000 1138.620000 2300.320000 ;
+ RECT 1137.520000 2316.160000 1138.620000 2316.640000 ;
+ RECT 1137.520000 2321.600000 1138.620000 2322.080000 ;
+ RECT 1092.520000 2321.600000 1093.620000 2322.080000 ;
+ RECT 1092.520000 2310.720000 1093.620000 2311.200000 ;
+ RECT 1092.520000 2305.280000 1093.620000 2305.760000 ;
+ RECT 1092.520000 2299.840000 1093.620000 2300.320000 ;
+ RECT 1092.520000 2316.160000 1093.620000 2316.640000 ;
+ RECT 1047.520000 2337.920000 1048.620000 2338.400000 ;
+ RECT 1043.390000 2337.920000 1044.390000 2338.400000 ;
+ RECT 1043.390000 2332.480000 1044.390000 2332.960000 ;
+ RECT 1047.520000 2332.480000 1048.620000 2332.960000 ;
+ RECT 1047.520000 2327.040000 1048.620000 2327.520000 ;
+ RECT 1043.390000 2327.040000 1044.390000 2327.520000 ;
+ RECT 1047.520000 2321.600000 1048.620000 2322.080000 ;
+ RECT 1043.390000 2321.600000 1044.390000 2322.080000 ;
+ RECT 1047.520000 2316.160000 1048.620000 2316.640000 ;
+ RECT 1043.390000 2316.160000 1044.390000 2316.640000 ;
+ RECT 1047.520000 2305.280000 1048.620000 2305.760000 ;
+ RECT 1043.390000 2305.280000 1044.390000 2305.760000 ;
+ RECT 1047.520000 2299.840000 1048.620000 2300.320000 ;
+ RECT 1043.390000 2299.840000 1044.390000 2300.320000 ;
+ RECT 1047.520000 2310.720000 1048.620000 2311.200000 ;
+ RECT 1043.390000 2310.720000 1044.390000 2311.200000 ;
+ RECT 1137.520000 2294.400000 1138.620000 2294.880000 ;
+ RECT 1137.520000 2288.960000 1138.620000 2289.440000 ;
+ RECT 1137.520000 2283.520000 1138.620000 2284.000000 ;
+ RECT 1137.520000 2278.080000 1138.620000 2278.560000 ;
+ RECT 1092.520000 2294.400000 1093.620000 2294.880000 ;
+ RECT 1092.520000 2288.960000 1093.620000 2289.440000 ;
+ RECT 1092.520000 2283.520000 1093.620000 2284.000000 ;
+ RECT 1092.520000 2278.080000 1093.620000 2278.560000 ;
+ RECT 1137.520000 2267.200000 1138.620000 2267.680000 ;
+ RECT 1137.520000 2250.880000 1138.620000 2251.360000 ;
+ RECT 1137.520000 2256.320000 1138.620000 2256.800000 ;
+ RECT 1137.520000 2261.760000 1138.620000 2262.240000 ;
+ RECT 1137.520000 2272.640000 1138.620000 2273.120000 ;
+ RECT 1092.520000 2250.880000 1093.620000 2251.360000 ;
+ RECT 1092.520000 2256.320000 1093.620000 2256.800000 ;
+ RECT 1092.520000 2261.760000 1093.620000 2262.240000 ;
+ RECT 1092.520000 2267.200000 1093.620000 2267.680000 ;
+ RECT 1092.520000 2272.640000 1093.620000 2273.120000 ;
+ RECT 1047.520000 2294.400000 1048.620000 2294.880000 ;
+ RECT 1043.390000 2294.400000 1044.390000 2294.880000 ;
+ RECT 1047.520000 2288.960000 1048.620000 2289.440000 ;
+ RECT 1043.390000 2288.960000 1044.390000 2289.440000 ;
+ RECT 1047.520000 2283.520000 1048.620000 2284.000000 ;
+ RECT 1043.390000 2283.520000 1044.390000 2284.000000 ;
+ RECT 1047.520000 2278.080000 1048.620000 2278.560000 ;
+ RECT 1043.390000 2278.080000 1044.390000 2278.560000 ;
+ RECT 1047.520000 2272.640000 1048.620000 2273.120000 ;
+ RECT 1047.520000 2267.200000 1048.620000 2267.680000 ;
+ RECT 1043.390000 2272.640000 1044.390000 2273.120000 ;
+ RECT 1043.390000 2267.200000 1044.390000 2267.680000 ;
+ RECT 1047.520000 2261.760000 1048.620000 2262.240000 ;
+ RECT 1043.390000 2261.760000 1044.390000 2262.240000 ;
+ RECT 1047.520000 2256.320000 1048.620000 2256.800000 ;
+ RECT 1043.390000 2256.320000 1044.390000 2256.800000 ;
+ RECT 1047.520000 2250.880000 1048.620000 2251.360000 ;
+ RECT 1043.390000 2250.880000 1044.390000 2251.360000 ;
+ RECT 1227.520000 2245.440000 1228.620000 2245.920000 ;
+ RECT 1227.520000 2240.000000 1228.620000 2240.480000 ;
+ RECT 1236.830000 2245.440000 1237.830000 2245.920000 ;
+ RECT 1236.830000 2240.000000 1237.830000 2240.480000 ;
+ RECT 1236.830000 2223.680000 1237.830000 2224.160000 ;
+ RECT 1236.830000 2229.120000 1237.830000 2229.600000 ;
+ RECT 1236.830000 2234.560000 1237.830000 2235.040000 ;
+ RECT 1227.520000 2234.560000 1228.620000 2235.040000 ;
+ RECT 1227.520000 2229.120000 1228.620000 2229.600000 ;
+ RECT 1227.520000 2223.680000 1228.620000 2224.160000 ;
+ RECT 1227.520000 2212.800000 1228.620000 2213.280000 ;
+ RECT 1227.520000 2218.240000 1228.620000 2218.720000 ;
+ RECT 1236.830000 2218.240000 1237.830000 2218.720000 ;
+ RECT 1236.830000 2212.800000 1237.830000 2213.280000 ;
+ RECT 1236.830000 2201.920000 1237.830000 2202.400000 ;
+ RECT 1236.830000 2207.360000 1237.830000 2207.840000 ;
+ RECT 1227.520000 2201.920000 1228.620000 2202.400000 ;
+ RECT 1227.520000 2207.360000 1228.620000 2207.840000 ;
+ RECT 1182.520000 2245.440000 1183.620000 2245.920000 ;
+ RECT 1182.520000 2240.000000 1183.620000 2240.480000 ;
+ RECT 1182.520000 2234.560000 1183.620000 2235.040000 ;
+ RECT 1182.520000 2229.120000 1183.620000 2229.600000 ;
+ RECT 1182.520000 2223.680000 1183.620000 2224.160000 ;
+ RECT 1182.520000 2201.920000 1183.620000 2202.400000 ;
+ RECT 1182.520000 2207.360000 1183.620000 2207.840000 ;
+ RECT 1182.520000 2212.800000 1183.620000 2213.280000 ;
+ RECT 1182.520000 2218.240000 1183.620000 2218.720000 ;
+ RECT 1227.520000 2196.480000 1228.620000 2196.960000 ;
+ RECT 1227.520000 2191.040000 1228.620000 2191.520000 ;
+ RECT 1236.830000 2196.480000 1237.830000 2196.960000 ;
+ RECT 1236.830000 2191.040000 1237.830000 2191.520000 ;
+ RECT 1227.520000 2180.160000 1228.620000 2180.640000 ;
+ RECT 1227.520000 2174.720000 1228.620000 2175.200000 ;
+ RECT 1236.830000 2180.160000 1237.830000 2180.640000 ;
+ RECT 1236.830000 2174.720000 1237.830000 2175.200000 ;
+ RECT 1227.520000 2185.600000 1228.620000 2186.080000 ;
+ RECT 1236.830000 2185.600000 1237.830000 2186.080000 ;
+ RECT 1236.830000 2163.840000 1237.830000 2164.320000 ;
+ RECT 1236.830000 2169.280000 1237.830000 2169.760000 ;
+ RECT 1227.520000 2169.280000 1228.620000 2169.760000 ;
+ RECT 1227.520000 2163.840000 1228.620000 2164.320000 ;
+ RECT 1227.520000 2158.400000 1228.620000 2158.880000 ;
+ RECT 1227.520000 2152.960000 1228.620000 2153.440000 ;
+ RECT 1236.830000 2158.400000 1237.830000 2158.880000 ;
+ RECT 1236.830000 2152.960000 1237.830000 2153.440000 ;
+ RECT 1182.520000 2196.480000 1183.620000 2196.960000 ;
+ RECT 1182.520000 2191.040000 1183.620000 2191.520000 ;
+ RECT 1182.520000 2185.600000 1183.620000 2186.080000 ;
+ RECT 1182.520000 2180.160000 1183.620000 2180.640000 ;
+ RECT 1182.520000 2174.720000 1183.620000 2175.200000 ;
+ RECT 1182.520000 2169.280000 1183.620000 2169.760000 ;
+ RECT 1182.520000 2163.840000 1183.620000 2164.320000 ;
+ RECT 1182.520000 2158.400000 1183.620000 2158.880000 ;
+ RECT 1182.520000 2152.960000 1183.620000 2153.440000 ;
+ RECT 1137.520000 2245.440000 1138.620000 2245.920000 ;
+ RECT 1137.520000 2240.000000 1138.620000 2240.480000 ;
+ RECT 1137.520000 2234.560000 1138.620000 2235.040000 ;
+ RECT 1137.520000 2229.120000 1138.620000 2229.600000 ;
+ RECT 1137.520000 2223.680000 1138.620000 2224.160000 ;
+ RECT 1092.520000 2245.440000 1093.620000 2245.920000 ;
+ RECT 1092.520000 2240.000000 1093.620000 2240.480000 ;
+ RECT 1092.520000 2234.560000 1093.620000 2235.040000 ;
+ RECT 1092.520000 2229.120000 1093.620000 2229.600000 ;
+ RECT 1092.520000 2223.680000 1093.620000 2224.160000 ;
+ RECT 1137.520000 2218.240000 1138.620000 2218.720000 ;
+ RECT 1137.520000 2212.800000 1138.620000 2213.280000 ;
+ RECT 1137.520000 2207.360000 1138.620000 2207.840000 ;
+ RECT 1137.520000 2201.920000 1138.620000 2202.400000 ;
+ RECT 1092.520000 2212.800000 1093.620000 2213.280000 ;
+ RECT 1092.520000 2207.360000 1093.620000 2207.840000 ;
+ RECT 1092.520000 2201.920000 1093.620000 2202.400000 ;
+ RECT 1092.520000 2218.240000 1093.620000 2218.720000 ;
+ RECT 1047.520000 2245.440000 1048.620000 2245.920000 ;
+ RECT 1043.390000 2245.440000 1044.390000 2245.920000 ;
+ RECT 1047.520000 2240.000000 1048.620000 2240.480000 ;
+ RECT 1043.390000 2240.000000 1044.390000 2240.480000 ;
+ RECT 1047.520000 2234.560000 1048.620000 2235.040000 ;
+ RECT 1043.390000 2234.560000 1044.390000 2235.040000 ;
+ RECT 1047.520000 2223.680000 1048.620000 2224.160000 ;
+ RECT 1043.390000 2223.680000 1044.390000 2224.160000 ;
+ RECT 1043.390000 2229.120000 1044.390000 2229.600000 ;
+ RECT 1047.520000 2229.120000 1048.620000 2229.600000 ;
+ RECT 1047.520000 2218.240000 1048.620000 2218.720000 ;
+ RECT 1043.390000 2218.240000 1044.390000 2218.720000 ;
+ RECT 1047.520000 2212.800000 1048.620000 2213.280000 ;
+ RECT 1043.390000 2212.800000 1044.390000 2213.280000 ;
+ RECT 1047.520000 2207.360000 1048.620000 2207.840000 ;
+ RECT 1043.390000 2207.360000 1044.390000 2207.840000 ;
+ RECT 1047.520000 2201.920000 1048.620000 2202.400000 ;
+ RECT 1043.390000 2201.920000 1044.390000 2202.400000 ;
+ RECT 1137.520000 2196.480000 1138.620000 2196.960000 ;
+ RECT 1137.520000 2191.040000 1138.620000 2191.520000 ;
+ RECT 1137.520000 2185.600000 1138.620000 2186.080000 ;
+ RECT 1137.520000 2180.160000 1138.620000 2180.640000 ;
+ RECT 1137.520000 2174.720000 1138.620000 2175.200000 ;
+ RECT 1092.520000 2196.480000 1093.620000 2196.960000 ;
+ RECT 1092.520000 2191.040000 1093.620000 2191.520000 ;
+ RECT 1092.520000 2185.600000 1093.620000 2186.080000 ;
+ RECT 1092.520000 2180.160000 1093.620000 2180.640000 ;
+ RECT 1092.520000 2174.720000 1093.620000 2175.200000 ;
+ RECT 1137.520000 2152.960000 1138.620000 2153.440000 ;
+ RECT 1137.520000 2158.400000 1138.620000 2158.880000 ;
+ RECT 1137.520000 2163.840000 1138.620000 2164.320000 ;
+ RECT 1137.520000 2169.280000 1138.620000 2169.760000 ;
+ RECT 1092.520000 2152.960000 1093.620000 2153.440000 ;
+ RECT 1092.520000 2158.400000 1093.620000 2158.880000 ;
+ RECT 1092.520000 2163.840000 1093.620000 2164.320000 ;
+ RECT 1092.520000 2169.280000 1093.620000 2169.760000 ;
+ RECT 1047.520000 2196.480000 1048.620000 2196.960000 ;
+ RECT 1043.390000 2196.480000 1044.390000 2196.960000 ;
+ RECT 1047.520000 2191.040000 1048.620000 2191.520000 ;
+ RECT 1043.390000 2191.040000 1044.390000 2191.520000 ;
+ RECT 1047.520000 2180.160000 1048.620000 2180.640000 ;
+ RECT 1043.390000 2180.160000 1044.390000 2180.640000 ;
+ RECT 1047.520000 2174.720000 1048.620000 2175.200000 ;
+ RECT 1043.390000 2174.720000 1044.390000 2175.200000 ;
+ RECT 1047.520000 2185.600000 1048.620000 2186.080000 ;
+ RECT 1043.390000 2185.600000 1044.390000 2186.080000 ;
+ RECT 1047.520000 2169.280000 1048.620000 2169.760000 ;
+ RECT 1043.390000 2169.280000 1044.390000 2169.760000 ;
+ RECT 1047.520000 2163.840000 1048.620000 2164.320000 ;
+ RECT 1043.390000 2163.840000 1044.390000 2164.320000 ;
+ RECT 1047.520000 2158.400000 1048.620000 2158.880000 ;
+ RECT 1047.520000 2152.960000 1048.620000 2153.440000 ;
+ RECT 1043.390000 2158.400000 1044.390000 2158.880000 ;
+ RECT 1043.390000 2152.960000 1044.390000 2153.440000 ;
+ RECT 1040.560000 2343.320000 1240.660000 2344.320000 ;
+ RECT 1040.560000 2150.950000 1240.660000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 2148.100000 1044.390000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 2347.360000 1044.390000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 2148.100000 1237.830000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 2347.360000 1237.830000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2150.950000 1041.560000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2150.950000 1240.660000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2343.320000 1041.560000 2344.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2343.320000 1240.660000 2344.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 1950.690000 1228.620000 2144.060000 ;
+ RECT 1182.520000 1950.690000 1183.620000 2144.060000 ;
+ RECT 1236.830000 1947.840000 1237.830000 2148.100000 ;
+ RECT 1137.520000 1950.690000 1138.620000 2144.060000 ;
+ RECT 1092.520000 1950.690000 1093.620000 2144.060000 ;
+ RECT 1047.520000 1950.690000 1048.620000 2144.060000 ;
+ RECT 1043.390000 1947.840000 1044.390000 2148.100000 ;
+ LAYER met3 ;
+ RECT 1227.520000 2137.660000 1228.620000 2138.140000 ;
+ RECT 1236.830000 2137.660000 1237.830000 2138.140000 ;
+ RECT 1236.830000 2126.780000 1237.830000 2127.260000 ;
+ RECT 1236.830000 2132.220000 1237.830000 2132.700000 ;
+ RECT 1227.520000 2132.220000 1228.620000 2132.700000 ;
+ RECT 1227.520000 2126.780000 1228.620000 2127.260000 ;
+ RECT 1227.520000 2121.340000 1228.620000 2121.820000 ;
+ RECT 1227.520000 2115.900000 1228.620000 2116.380000 ;
+ RECT 1236.830000 2121.340000 1237.830000 2121.820000 ;
+ RECT 1236.830000 2115.900000 1237.830000 2116.380000 ;
+ RECT 1227.520000 2099.580000 1228.620000 2100.060000 ;
+ RECT 1227.520000 2105.020000 1228.620000 2105.500000 ;
+ RECT 1236.830000 2105.020000 1237.830000 2105.500000 ;
+ RECT 1236.830000 2099.580000 1237.830000 2100.060000 ;
+ RECT 1227.520000 2110.460000 1228.620000 2110.940000 ;
+ RECT 1236.830000 2110.460000 1237.830000 2110.940000 ;
+ RECT 1182.520000 2137.660000 1183.620000 2138.140000 ;
+ RECT 1182.520000 2132.220000 1183.620000 2132.700000 ;
+ RECT 1182.520000 2126.780000 1183.620000 2127.260000 ;
+ RECT 1182.520000 2121.340000 1183.620000 2121.820000 ;
+ RECT 1182.520000 2099.580000 1183.620000 2100.060000 ;
+ RECT 1182.520000 2105.020000 1183.620000 2105.500000 ;
+ RECT 1182.520000 2110.460000 1183.620000 2110.940000 ;
+ RECT 1182.520000 2115.900000 1183.620000 2116.380000 ;
+ RECT 1236.830000 2088.700000 1237.830000 2089.180000 ;
+ RECT 1236.830000 2094.140000 1237.830000 2094.620000 ;
+ RECT 1227.520000 2094.140000 1228.620000 2094.620000 ;
+ RECT 1227.520000 2088.700000 1228.620000 2089.180000 ;
+ RECT 1227.520000 2083.260000 1228.620000 2083.740000 ;
+ RECT 1227.520000 2077.820000 1228.620000 2078.300000 ;
+ RECT 1236.830000 2083.260000 1237.830000 2083.740000 ;
+ RECT 1236.830000 2077.820000 1237.830000 2078.300000 ;
+ RECT 1236.830000 2061.500000 1237.830000 2061.980000 ;
+ RECT 1236.830000 2066.940000 1237.830000 2067.420000 ;
+ RECT 1236.830000 2072.380000 1237.830000 2072.860000 ;
+ RECT 1227.520000 2066.940000 1228.620000 2067.420000 ;
+ RECT 1227.520000 2061.500000 1228.620000 2061.980000 ;
+ RECT 1227.520000 2072.380000 1228.620000 2072.860000 ;
+ RECT 1227.520000 2056.060000 1228.620000 2056.540000 ;
+ RECT 1227.520000 2050.620000 1228.620000 2051.100000 ;
+ RECT 1236.830000 2056.060000 1237.830000 2056.540000 ;
+ RECT 1236.830000 2050.620000 1237.830000 2051.100000 ;
+ RECT 1182.520000 2094.140000 1183.620000 2094.620000 ;
+ RECT 1182.520000 2088.700000 1183.620000 2089.180000 ;
+ RECT 1182.520000 2083.260000 1183.620000 2083.740000 ;
+ RECT 1182.520000 2077.820000 1183.620000 2078.300000 ;
+ RECT 1182.520000 2066.940000 1183.620000 2067.420000 ;
+ RECT 1182.520000 2061.500000 1183.620000 2061.980000 ;
+ RECT 1182.520000 2056.060000 1183.620000 2056.540000 ;
+ RECT 1182.520000 2050.620000 1183.620000 2051.100000 ;
+ RECT 1182.520000 2072.380000 1183.620000 2072.860000 ;
+ RECT 1137.520000 2137.660000 1138.620000 2138.140000 ;
+ RECT 1137.520000 2132.220000 1138.620000 2132.700000 ;
+ RECT 1137.520000 2126.780000 1138.620000 2127.260000 ;
+ RECT 1092.520000 2137.660000 1093.620000 2138.140000 ;
+ RECT 1092.520000 2132.220000 1093.620000 2132.700000 ;
+ RECT 1092.520000 2126.780000 1093.620000 2127.260000 ;
+ RECT 1137.520000 2110.460000 1138.620000 2110.940000 ;
+ RECT 1137.520000 2105.020000 1138.620000 2105.500000 ;
+ RECT 1137.520000 2099.580000 1138.620000 2100.060000 ;
+ RECT 1137.520000 2115.900000 1138.620000 2116.380000 ;
+ RECT 1137.520000 2121.340000 1138.620000 2121.820000 ;
+ RECT 1092.520000 2121.340000 1093.620000 2121.820000 ;
+ RECT 1092.520000 2110.460000 1093.620000 2110.940000 ;
+ RECT 1092.520000 2105.020000 1093.620000 2105.500000 ;
+ RECT 1092.520000 2099.580000 1093.620000 2100.060000 ;
+ RECT 1092.520000 2115.900000 1093.620000 2116.380000 ;
+ RECT 1047.520000 2137.660000 1048.620000 2138.140000 ;
+ RECT 1043.390000 2137.660000 1044.390000 2138.140000 ;
+ RECT 1043.390000 2132.220000 1044.390000 2132.700000 ;
+ RECT 1047.520000 2132.220000 1048.620000 2132.700000 ;
+ RECT 1047.520000 2126.780000 1048.620000 2127.260000 ;
+ RECT 1043.390000 2126.780000 1044.390000 2127.260000 ;
+ RECT 1047.520000 2121.340000 1048.620000 2121.820000 ;
+ RECT 1043.390000 2121.340000 1044.390000 2121.820000 ;
+ RECT 1047.520000 2115.900000 1048.620000 2116.380000 ;
+ RECT 1043.390000 2115.900000 1044.390000 2116.380000 ;
+ RECT 1047.520000 2105.020000 1048.620000 2105.500000 ;
+ RECT 1043.390000 2105.020000 1044.390000 2105.500000 ;
+ RECT 1047.520000 2099.580000 1048.620000 2100.060000 ;
+ RECT 1043.390000 2099.580000 1044.390000 2100.060000 ;
+ RECT 1047.520000 2110.460000 1048.620000 2110.940000 ;
+ RECT 1043.390000 2110.460000 1044.390000 2110.940000 ;
+ RECT 1137.520000 2094.140000 1138.620000 2094.620000 ;
+ RECT 1137.520000 2088.700000 1138.620000 2089.180000 ;
+ RECT 1137.520000 2083.260000 1138.620000 2083.740000 ;
+ RECT 1137.520000 2077.820000 1138.620000 2078.300000 ;
+ RECT 1092.520000 2094.140000 1093.620000 2094.620000 ;
+ RECT 1092.520000 2088.700000 1093.620000 2089.180000 ;
+ RECT 1092.520000 2083.260000 1093.620000 2083.740000 ;
+ RECT 1092.520000 2077.820000 1093.620000 2078.300000 ;
+ RECT 1137.520000 2066.940000 1138.620000 2067.420000 ;
+ RECT 1137.520000 2050.620000 1138.620000 2051.100000 ;
+ RECT 1137.520000 2056.060000 1138.620000 2056.540000 ;
+ RECT 1137.520000 2061.500000 1138.620000 2061.980000 ;
+ RECT 1137.520000 2072.380000 1138.620000 2072.860000 ;
+ RECT 1092.520000 2050.620000 1093.620000 2051.100000 ;
+ RECT 1092.520000 2056.060000 1093.620000 2056.540000 ;
+ RECT 1092.520000 2061.500000 1093.620000 2061.980000 ;
+ RECT 1092.520000 2066.940000 1093.620000 2067.420000 ;
+ RECT 1092.520000 2072.380000 1093.620000 2072.860000 ;
+ RECT 1047.520000 2094.140000 1048.620000 2094.620000 ;
+ RECT 1043.390000 2094.140000 1044.390000 2094.620000 ;
+ RECT 1047.520000 2088.700000 1048.620000 2089.180000 ;
+ RECT 1043.390000 2088.700000 1044.390000 2089.180000 ;
+ RECT 1047.520000 2083.260000 1048.620000 2083.740000 ;
+ RECT 1043.390000 2083.260000 1044.390000 2083.740000 ;
+ RECT 1047.520000 2077.820000 1048.620000 2078.300000 ;
+ RECT 1043.390000 2077.820000 1044.390000 2078.300000 ;
+ RECT 1047.520000 2072.380000 1048.620000 2072.860000 ;
+ RECT 1047.520000 2066.940000 1048.620000 2067.420000 ;
+ RECT 1043.390000 2072.380000 1044.390000 2072.860000 ;
+ RECT 1043.390000 2066.940000 1044.390000 2067.420000 ;
+ RECT 1047.520000 2061.500000 1048.620000 2061.980000 ;
+ RECT 1043.390000 2061.500000 1044.390000 2061.980000 ;
+ RECT 1047.520000 2056.060000 1048.620000 2056.540000 ;
+ RECT 1043.390000 2056.060000 1044.390000 2056.540000 ;
+ RECT 1047.520000 2050.620000 1048.620000 2051.100000 ;
+ RECT 1043.390000 2050.620000 1044.390000 2051.100000 ;
+ RECT 1227.520000 2045.180000 1228.620000 2045.660000 ;
+ RECT 1227.520000 2039.740000 1228.620000 2040.220000 ;
+ RECT 1236.830000 2045.180000 1237.830000 2045.660000 ;
+ RECT 1236.830000 2039.740000 1237.830000 2040.220000 ;
+ RECT 1236.830000 2023.420000 1237.830000 2023.900000 ;
+ RECT 1236.830000 2028.860000 1237.830000 2029.340000 ;
+ RECT 1236.830000 2034.300000 1237.830000 2034.780000 ;
+ RECT 1227.520000 2034.300000 1228.620000 2034.780000 ;
+ RECT 1227.520000 2028.860000 1228.620000 2029.340000 ;
+ RECT 1227.520000 2023.420000 1228.620000 2023.900000 ;
+ RECT 1227.520000 2012.540000 1228.620000 2013.020000 ;
+ RECT 1227.520000 2017.980000 1228.620000 2018.460000 ;
+ RECT 1236.830000 2017.980000 1237.830000 2018.460000 ;
+ RECT 1236.830000 2012.540000 1237.830000 2013.020000 ;
+ RECT 1236.830000 2001.660000 1237.830000 2002.140000 ;
+ RECT 1236.830000 2007.100000 1237.830000 2007.580000 ;
+ RECT 1227.520000 2001.660000 1228.620000 2002.140000 ;
+ RECT 1227.520000 2007.100000 1228.620000 2007.580000 ;
+ RECT 1182.520000 2045.180000 1183.620000 2045.660000 ;
+ RECT 1182.520000 2039.740000 1183.620000 2040.220000 ;
+ RECT 1182.520000 2034.300000 1183.620000 2034.780000 ;
+ RECT 1182.520000 2028.860000 1183.620000 2029.340000 ;
+ RECT 1182.520000 2023.420000 1183.620000 2023.900000 ;
+ RECT 1182.520000 2001.660000 1183.620000 2002.140000 ;
+ RECT 1182.520000 2007.100000 1183.620000 2007.580000 ;
+ RECT 1182.520000 2012.540000 1183.620000 2013.020000 ;
+ RECT 1182.520000 2017.980000 1183.620000 2018.460000 ;
+ RECT 1227.520000 1996.220000 1228.620000 1996.700000 ;
+ RECT 1227.520000 1990.780000 1228.620000 1991.260000 ;
+ RECT 1236.830000 1996.220000 1237.830000 1996.700000 ;
+ RECT 1236.830000 1990.780000 1237.830000 1991.260000 ;
+ RECT 1227.520000 1979.900000 1228.620000 1980.380000 ;
+ RECT 1227.520000 1974.460000 1228.620000 1974.940000 ;
+ RECT 1236.830000 1979.900000 1237.830000 1980.380000 ;
+ RECT 1236.830000 1974.460000 1237.830000 1974.940000 ;
+ RECT 1227.520000 1985.340000 1228.620000 1985.820000 ;
+ RECT 1236.830000 1985.340000 1237.830000 1985.820000 ;
+ RECT 1236.830000 1963.580000 1237.830000 1964.060000 ;
+ RECT 1236.830000 1969.020000 1237.830000 1969.500000 ;
+ RECT 1227.520000 1969.020000 1228.620000 1969.500000 ;
+ RECT 1227.520000 1963.580000 1228.620000 1964.060000 ;
+ RECT 1227.520000 1958.140000 1228.620000 1958.620000 ;
+ RECT 1227.520000 1952.700000 1228.620000 1953.180000 ;
+ RECT 1236.830000 1958.140000 1237.830000 1958.620000 ;
+ RECT 1236.830000 1952.700000 1237.830000 1953.180000 ;
+ RECT 1182.520000 1996.220000 1183.620000 1996.700000 ;
+ RECT 1182.520000 1990.780000 1183.620000 1991.260000 ;
+ RECT 1182.520000 1985.340000 1183.620000 1985.820000 ;
+ RECT 1182.520000 1979.900000 1183.620000 1980.380000 ;
+ RECT 1182.520000 1974.460000 1183.620000 1974.940000 ;
+ RECT 1182.520000 1969.020000 1183.620000 1969.500000 ;
+ RECT 1182.520000 1963.580000 1183.620000 1964.060000 ;
+ RECT 1182.520000 1958.140000 1183.620000 1958.620000 ;
+ RECT 1182.520000 1952.700000 1183.620000 1953.180000 ;
+ RECT 1137.520000 2045.180000 1138.620000 2045.660000 ;
+ RECT 1137.520000 2039.740000 1138.620000 2040.220000 ;
+ RECT 1137.520000 2034.300000 1138.620000 2034.780000 ;
+ RECT 1137.520000 2028.860000 1138.620000 2029.340000 ;
+ RECT 1137.520000 2023.420000 1138.620000 2023.900000 ;
+ RECT 1092.520000 2045.180000 1093.620000 2045.660000 ;
+ RECT 1092.520000 2039.740000 1093.620000 2040.220000 ;
+ RECT 1092.520000 2034.300000 1093.620000 2034.780000 ;
+ RECT 1092.520000 2028.860000 1093.620000 2029.340000 ;
+ RECT 1092.520000 2023.420000 1093.620000 2023.900000 ;
+ RECT 1137.520000 2017.980000 1138.620000 2018.460000 ;
+ RECT 1137.520000 2012.540000 1138.620000 2013.020000 ;
+ RECT 1137.520000 2007.100000 1138.620000 2007.580000 ;
+ RECT 1137.520000 2001.660000 1138.620000 2002.140000 ;
+ RECT 1092.520000 2012.540000 1093.620000 2013.020000 ;
+ RECT 1092.520000 2007.100000 1093.620000 2007.580000 ;
+ RECT 1092.520000 2001.660000 1093.620000 2002.140000 ;
+ RECT 1092.520000 2017.980000 1093.620000 2018.460000 ;
+ RECT 1047.520000 2045.180000 1048.620000 2045.660000 ;
+ RECT 1043.390000 2045.180000 1044.390000 2045.660000 ;
+ RECT 1047.520000 2039.740000 1048.620000 2040.220000 ;
+ RECT 1043.390000 2039.740000 1044.390000 2040.220000 ;
+ RECT 1047.520000 2034.300000 1048.620000 2034.780000 ;
+ RECT 1043.390000 2034.300000 1044.390000 2034.780000 ;
+ RECT 1047.520000 2023.420000 1048.620000 2023.900000 ;
+ RECT 1043.390000 2023.420000 1044.390000 2023.900000 ;
+ RECT 1043.390000 2028.860000 1044.390000 2029.340000 ;
+ RECT 1047.520000 2028.860000 1048.620000 2029.340000 ;
+ RECT 1047.520000 2017.980000 1048.620000 2018.460000 ;
+ RECT 1043.390000 2017.980000 1044.390000 2018.460000 ;
+ RECT 1047.520000 2012.540000 1048.620000 2013.020000 ;
+ RECT 1043.390000 2012.540000 1044.390000 2013.020000 ;
+ RECT 1047.520000 2007.100000 1048.620000 2007.580000 ;
+ RECT 1043.390000 2007.100000 1044.390000 2007.580000 ;
+ RECT 1047.520000 2001.660000 1048.620000 2002.140000 ;
+ RECT 1043.390000 2001.660000 1044.390000 2002.140000 ;
+ RECT 1137.520000 1996.220000 1138.620000 1996.700000 ;
+ RECT 1137.520000 1990.780000 1138.620000 1991.260000 ;
+ RECT 1137.520000 1985.340000 1138.620000 1985.820000 ;
+ RECT 1137.520000 1979.900000 1138.620000 1980.380000 ;
+ RECT 1137.520000 1974.460000 1138.620000 1974.940000 ;
+ RECT 1092.520000 1996.220000 1093.620000 1996.700000 ;
+ RECT 1092.520000 1990.780000 1093.620000 1991.260000 ;
+ RECT 1092.520000 1985.340000 1093.620000 1985.820000 ;
+ RECT 1092.520000 1979.900000 1093.620000 1980.380000 ;
+ RECT 1092.520000 1974.460000 1093.620000 1974.940000 ;
+ RECT 1137.520000 1952.700000 1138.620000 1953.180000 ;
+ RECT 1137.520000 1958.140000 1138.620000 1958.620000 ;
+ RECT 1137.520000 1963.580000 1138.620000 1964.060000 ;
+ RECT 1137.520000 1969.020000 1138.620000 1969.500000 ;
+ RECT 1092.520000 1952.700000 1093.620000 1953.180000 ;
+ RECT 1092.520000 1958.140000 1093.620000 1958.620000 ;
+ RECT 1092.520000 1963.580000 1093.620000 1964.060000 ;
+ RECT 1092.520000 1969.020000 1093.620000 1969.500000 ;
+ RECT 1047.520000 1996.220000 1048.620000 1996.700000 ;
+ RECT 1043.390000 1996.220000 1044.390000 1996.700000 ;
+ RECT 1047.520000 1990.780000 1048.620000 1991.260000 ;
+ RECT 1043.390000 1990.780000 1044.390000 1991.260000 ;
+ RECT 1047.520000 1979.900000 1048.620000 1980.380000 ;
+ RECT 1043.390000 1979.900000 1044.390000 1980.380000 ;
+ RECT 1047.520000 1974.460000 1048.620000 1974.940000 ;
+ RECT 1043.390000 1974.460000 1044.390000 1974.940000 ;
+ RECT 1047.520000 1985.340000 1048.620000 1985.820000 ;
+ RECT 1043.390000 1985.340000 1044.390000 1985.820000 ;
+ RECT 1047.520000 1969.020000 1048.620000 1969.500000 ;
+ RECT 1043.390000 1969.020000 1044.390000 1969.500000 ;
+ RECT 1047.520000 1963.580000 1048.620000 1964.060000 ;
+ RECT 1043.390000 1963.580000 1044.390000 1964.060000 ;
+ RECT 1047.520000 1958.140000 1048.620000 1958.620000 ;
+ RECT 1047.520000 1952.700000 1048.620000 1953.180000 ;
+ RECT 1043.390000 1958.140000 1044.390000 1958.620000 ;
+ RECT 1043.390000 1952.700000 1044.390000 1953.180000 ;
+ RECT 1040.560000 2143.060000 1240.660000 2144.060000 ;
+ RECT 1040.560000 1950.690000 1240.660000 1951.690000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 1947.840000 1044.390000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 2147.100000 1044.390000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 1947.840000 1237.830000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 2147.100000 1237.830000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1950.690000 1041.560000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1950.690000 1240.660000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 2143.060000 1041.560000 2144.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 2143.060000 1240.660000 2144.060000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 1750.430000 1228.620000 1943.800000 ;
+ RECT 1182.520000 1750.430000 1183.620000 1943.800000 ;
+ RECT 1236.830000 1747.580000 1237.830000 1947.840000 ;
+ RECT 1137.520000 1750.430000 1138.620000 1943.800000 ;
+ RECT 1092.520000 1750.430000 1093.620000 1943.800000 ;
+ RECT 1047.520000 1750.430000 1048.620000 1943.800000 ;
+ RECT 1043.390000 1747.580000 1044.390000 1947.840000 ;
+ LAYER met3 ;
+ RECT 1227.520000 1937.400000 1228.620000 1937.880000 ;
+ RECT 1236.830000 1937.400000 1237.830000 1937.880000 ;
+ RECT 1236.830000 1926.520000 1237.830000 1927.000000 ;
+ RECT 1236.830000 1931.960000 1237.830000 1932.440000 ;
+ RECT 1227.520000 1931.960000 1228.620000 1932.440000 ;
+ RECT 1227.520000 1926.520000 1228.620000 1927.000000 ;
+ RECT 1227.520000 1921.080000 1228.620000 1921.560000 ;
+ RECT 1227.520000 1915.640000 1228.620000 1916.120000 ;
+ RECT 1236.830000 1921.080000 1237.830000 1921.560000 ;
+ RECT 1236.830000 1915.640000 1237.830000 1916.120000 ;
+ RECT 1227.520000 1899.320000 1228.620000 1899.800000 ;
+ RECT 1227.520000 1904.760000 1228.620000 1905.240000 ;
+ RECT 1236.830000 1904.760000 1237.830000 1905.240000 ;
+ RECT 1236.830000 1899.320000 1237.830000 1899.800000 ;
+ RECT 1227.520000 1910.200000 1228.620000 1910.680000 ;
+ RECT 1236.830000 1910.200000 1237.830000 1910.680000 ;
+ RECT 1182.520000 1937.400000 1183.620000 1937.880000 ;
+ RECT 1182.520000 1931.960000 1183.620000 1932.440000 ;
+ RECT 1182.520000 1926.520000 1183.620000 1927.000000 ;
+ RECT 1182.520000 1921.080000 1183.620000 1921.560000 ;
+ RECT 1182.520000 1899.320000 1183.620000 1899.800000 ;
+ RECT 1182.520000 1904.760000 1183.620000 1905.240000 ;
+ RECT 1182.520000 1910.200000 1183.620000 1910.680000 ;
+ RECT 1182.520000 1915.640000 1183.620000 1916.120000 ;
+ RECT 1236.830000 1888.440000 1237.830000 1888.920000 ;
+ RECT 1236.830000 1893.880000 1237.830000 1894.360000 ;
+ RECT 1227.520000 1893.880000 1228.620000 1894.360000 ;
+ RECT 1227.520000 1888.440000 1228.620000 1888.920000 ;
+ RECT 1227.520000 1883.000000 1228.620000 1883.480000 ;
+ RECT 1227.520000 1877.560000 1228.620000 1878.040000 ;
+ RECT 1236.830000 1883.000000 1237.830000 1883.480000 ;
+ RECT 1236.830000 1877.560000 1237.830000 1878.040000 ;
+ RECT 1236.830000 1861.240000 1237.830000 1861.720000 ;
+ RECT 1236.830000 1866.680000 1237.830000 1867.160000 ;
+ RECT 1236.830000 1872.120000 1237.830000 1872.600000 ;
+ RECT 1227.520000 1866.680000 1228.620000 1867.160000 ;
+ RECT 1227.520000 1861.240000 1228.620000 1861.720000 ;
+ RECT 1227.520000 1872.120000 1228.620000 1872.600000 ;
+ RECT 1227.520000 1855.800000 1228.620000 1856.280000 ;
+ RECT 1227.520000 1850.360000 1228.620000 1850.840000 ;
+ RECT 1236.830000 1855.800000 1237.830000 1856.280000 ;
+ RECT 1236.830000 1850.360000 1237.830000 1850.840000 ;
+ RECT 1182.520000 1893.880000 1183.620000 1894.360000 ;
+ RECT 1182.520000 1888.440000 1183.620000 1888.920000 ;
+ RECT 1182.520000 1883.000000 1183.620000 1883.480000 ;
+ RECT 1182.520000 1877.560000 1183.620000 1878.040000 ;
+ RECT 1182.520000 1866.680000 1183.620000 1867.160000 ;
+ RECT 1182.520000 1861.240000 1183.620000 1861.720000 ;
+ RECT 1182.520000 1855.800000 1183.620000 1856.280000 ;
+ RECT 1182.520000 1850.360000 1183.620000 1850.840000 ;
+ RECT 1182.520000 1872.120000 1183.620000 1872.600000 ;
+ RECT 1137.520000 1937.400000 1138.620000 1937.880000 ;
+ RECT 1137.520000 1931.960000 1138.620000 1932.440000 ;
+ RECT 1137.520000 1926.520000 1138.620000 1927.000000 ;
+ RECT 1092.520000 1937.400000 1093.620000 1937.880000 ;
+ RECT 1092.520000 1931.960000 1093.620000 1932.440000 ;
+ RECT 1092.520000 1926.520000 1093.620000 1927.000000 ;
+ RECT 1137.520000 1910.200000 1138.620000 1910.680000 ;
+ RECT 1137.520000 1904.760000 1138.620000 1905.240000 ;
+ RECT 1137.520000 1899.320000 1138.620000 1899.800000 ;
+ RECT 1137.520000 1915.640000 1138.620000 1916.120000 ;
+ RECT 1137.520000 1921.080000 1138.620000 1921.560000 ;
+ RECT 1092.520000 1921.080000 1093.620000 1921.560000 ;
+ RECT 1092.520000 1910.200000 1093.620000 1910.680000 ;
+ RECT 1092.520000 1904.760000 1093.620000 1905.240000 ;
+ RECT 1092.520000 1899.320000 1093.620000 1899.800000 ;
+ RECT 1092.520000 1915.640000 1093.620000 1916.120000 ;
+ RECT 1047.520000 1937.400000 1048.620000 1937.880000 ;
+ RECT 1043.390000 1937.400000 1044.390000 1937.880000 ;
+ RECT 1043.390000 1931.960000 1044.390000 1932.440000 ;
+ RECT 1047.520000 1931.960000 1048.620000 1932.440000 ;
+ RECT 1047.520000 1926.520000 1048.620000 1927.000000 ;
+ RECT 1043.390000 1926.520000 1044.390000 1927.000000 ;
+ RECT 1047.520000 1921.080000 1048.620000 1921.560000 ;
+ RECT 1043.390000 1921.080000 1044.390000 1921.560000 ;
+ RECT 1047.520000 1915.640000 1048.620000 1916.120000 ;
+ RECT 1043.390000 1915.640000 1044.390000 1916.120000 ;
+ RECT 1047.520000 1904.760000 1048.620000 1905.240000 ;
+ RECT 1043.390000 1904.760000 1044.390000 1905.240000 ;
+ RECT 1047.520000 1899.320000 1048.620000 1899.800000 ;
+ RECT 1043.390000 1899.320000 1044.390000 1899.800000 ;
+ RECT 1047.520000 1910.200000 1048.620000 1910.680000 ;
+ RECT 1043.390000 1910.200000 1044.390000 1910.680000 ;
+ RECT 1137.520000 1893.880000 1138.620000 1894.360000 ;
+ RECT 1137.520000 1888.440000 1138.620000 1888.920000 ;
+ RECT 1137.520000 1883.000000 1138.620000 1883.480000 ;
+ RECT 1137.520000 1877.560000 1138.620000 1878.040000 ;
+ RECT 1092.520000 1893.880000 1093.620000 1894.360000 ;
+ RECT 1092.520000 1888.440000 1093.620000 1888.920000 ;
+ RECT 1092.520000 1883.000000 1093.620000 1883.480000 ;
+ RECT 1092.520000 1877.560000 1093.620000 1878.040000 ;
+ RECT 1137.520000 1866.680000 1138.620000 1867.160000 ;
+ RECT 1137.520000 1850.360000 1138.620000 1850.840000 ;
+ RECT 1137.520000 1855.800000 1138.620000 1856.280000 ;
+ RECT 1137.520000 1861.240000 1138.620000 1861.720000 ;
+ RECT 1137.520000 1872.120000 1138.620000 1872.600000 ;
+ RECT 1092.520000 1850.360000 1093.620000 1850.840000 ;
+ RECT 1092.520000 1855.800000 1093.620000 1856.280000 ;
+ RECT 1092.520000 1861.240000 1093.620000 1861.720000 ;
+ RECT 1092.520000 1866.680000 1093.620000 1867.160000 ;
+ RECT 1092.520000 1872.120000 1093.620000 1872.600000 ;
+ RECT 1047.520000 1893.880000 1048.620000 1894.360000 ;
+ RECT 1043.390000 1893.880000 1044.390000 1894.360000 ;
+ RECT 1047.520000 1888.440000 1048.620000 1888.920000 ;
+ RECT 1043.390000 1888.440000 1044.390000 1888.920000 ;
+ RECT 1047.520000 1883.000000 1048.620000 1883.480000 ;
+ RECT 1043.390000 1883.000000 1044.390000 1883.480000 ;
+ RECT 1047.520000 1877.560000 1048.620000 1878.040000 ;
+ RECT 1043.390000 1877.560000 1044.390000 1878.040000 ;
+ RECT 1047.520000 1872.120000 1048.620000 1872.600000 ;
+ RECT 1047.520000 1866.680000 1048.620000 1867.160000 ;
+ RECT 1043.390000 1872.120000 1044.390000 1872.600000 ;
+ RECT 1043.390000 1866.680000 1044.390000 1867.160000 ;
+ RECT 1047.520000 1861.240000 1048.620000 1861.720000 ;
+ RECT 1043.390000 1861.240000 1044.390000 1861.720000 ;
+ RECT 1047.520000 1855.800000 1048.620000 1856.280000 ;
+ RECT 1043.390000 1855.800000 1044.390000 1856.280000 ;
+ RECT 1047.520000 1850.360000 1048.620000 1850.840000 ;
+ RECT 1043.390000 1850.360000 1044.390000 1850.840000 ;
+ RECT 1227.520000 1844.920000 1228.620000 1845.400000 ;
+ RECT 1227.520000 1839.480000 1228.620000 1839.960000 ;
+ RECT 1236.830000 1844.920000 1237.830000 1845.400000 ;
+ RECT 1236.830000 1839.480000 1237.830000 1839.960000 ;
+ RECT 1236.830000 1823.160000 1237.830000 1823.640000 ;
+ RECT 1236.830000 1828.600000 1237.830000 1829.080000 ;
+ RECT 1236.830000 1834.040000 1237.830000 1834.520000 ;
+ RECT 1227.520000 1834.040000 1228.620000 1834.520000 ;
+ RECT 1227.520000 1828.600000 1228.620000 1829.080000 ;
+ RECT 1227.520000 1823.160000 1228.620000 1823.640000 ;
+ RECT 1227.520000 1812.280000 1228.620000 1812.760000 ;
+ RECT 1227.520000 1817.720000 1228.620000 1818.200000 ;
+ RECT 1236.830000 1817.720000 1237.830000 1818.200000 ;
+ RECT 1236.830000 1812.280000 1237.830000 1812.760000 ;
+ RECT 1236.830000 1801.400000 1237.830000 1801.880000 ;
+ RECT 1236.830000 1806.840000 1237.830000 1807.320000 ;
+ RECT 1227.520000 1801.400000 1228.620000 1801.880000 ;
+ RECT 1227.520000 1806.840000 1228.620000 1807.320000 ;
+ RECT 1182.520000 1844.920000 1183.620000 1845.400000 ;
+ RECT 1182.520000 1839.480000 1183.620000 1839.960000 ;
+ RECT 1182.520000 1834.040000 1183.620000 1834.520000 ;
+ RECT 1182.520000 1828.600000 1183.620000 1829.080000 ;
+ RECT 1182.520000 1823.160000 1183.620000 1823.640000 ;
+ RECT 1182.520000 1801.400000 1183.620000 1801.880000 ;
+ RECT 1182.520000 1806.840000 1183.620000 1807.320000 ;
+ RECT 1182.520000 1812.280000 1183.620000 1812.760000 ;
+ RECT 1182.520000 1817.720000 1183.620000 1818.200000 ;
+ RECT 1227.520000 1795.960000 1228.620000 1796.440000 ;
+ RECT 1227.520000 1790.520000 1228.620000 1791.000000 ;
+ RECT 1236.830000 1795.960000 1237.830000 1796.440000 ;
+ RECT 1236.830000 1790.520000 1237.830000 1791.000000 ;
+ RECT 1227.520000 1779.640000 1228.620000 1780.120000 ;
+ RECT 1227.520000 1774.200000 1228.620000 1774.680000 ;
+ RECT 1236.830000 1779.640000 1237.830000 1780.120000 ;
+ RECT 1236.830000 1774.200000 1237.830000 1774.680000 ;
+ RECT 1227.520000 1785.080000 1228.620000 1785.560000 ;
+ RECT 1236.830000 1785.080000 1237.830000 1785.560000 ;
+ RECT 1236.830000 1763.320000 1237.830000 1763.800000 ;
+ RECT 1236.830000 1768.760000 1237.830000 1769.240000 ;
+ RECT 1227.520000 1768.760000 1228.620000 1769.240000 ;
+ RECT 1227.520000 1763.320000 1228.620000 1763.800000 ;
+ RECT 1227.520000 1757.880000 1228.620000 1758.360000 ;
+ RECT 1227.520000 1752.440000 1228.620000 1752.920000 ;
+ RECT 1236.830000 1757.880000 1237.830000 1758.360000 ;
+ RECT 1236.830000 1752.440000 1237.830000 1752.920000 ;
+ RECT 1182.520000 1795.960000 1183.620000 1796.440000 ;
+ RECT 1182.520000 1790.520000 1183.620000 1791.000000 ;
+ RECT 1182.520000 1785.080000 1183.620000 1785.560000 ;
+ RECT 1182.520000 1779.640000 1183.620000 1780.120000 ;
+ RECT 1182.520000 1774.200000 1183.620000 1774.680000 ;
+ RECT 1182.520000 1768.760000 1183.620000 1769.240000 ;
+ RECT 1182.520000 1763.320000 1183.620000 1763.800000 ;
+ RECT 1182.520000 1757.880000 1183.620000 1758.360000 ;
+ RECT 1182.520000 1752.440000 1183.620000 1752.920000 ;
+ RECT 1137.520000 1844.920000 1138.620000 1845.400000 ;
+ RECT 1137.520000 1839.480000 1138.620000 1839.960000 ;
+ RECT 1137.520000 1834.040000 1138.620000 1834.520000 ;
+ RECT 1137.520000 1828.600000 1138.620000 1829.080000 ;
+ RECT 1137.520000 1823.160000 1138.620000 1823.640000 ;
+ RECT 1092.520000 1844.920000 1093.620000 1845.400000 ;
+ RECT 1092.520000 1839.480000 1093.620000 1839.960000 ;
+ RECT 1092.520000 1834.040000 1093.620000 1834.520000 ;
+ RECT 1092.520000 1828.600000 1093.620000 1829.080000 ;
+ RECT 1092.520000 1823.160000 1093.620000 1823.640000 ;
+ RECT 1137.520000 1817.720000 1138.620000 1818.200000 ;
+ RECT 1137.520000 1812.280000 1138.620000 1812.760000 ;
+ RECT 1137.520000 1806.840000 1138.620000 1807.320000 ;
+ RECT 1137.520000 1801.400000 1138.620000 1801.880000 ;
+ RECT 1092.520000 1812.280000 1093.620000 1812.760000 ;
+ RECT 1092.520000 1806.840000 1093.620000 1807.320000 ;
+ RECT 1092.520000 1801.400000 1093.620000 1801.880000 ;
+ RECT 1092.520000 1817.720000 1093.620000 1818.200000 ;
+ RECT 1047.520000 1844.920000 1048.620000 1845.400000 ;
+ RECT 1043.390000 1844.920000 1044.390000 1845.400000 ;
+ RECT 1047.520000 1839.480000 1048.620000 1839.960000 ;
+ RECT 1043.390000 1839.480000 1044.390000 1839.960000 ;
+ RECT 1047.520000 1834.040000 1048.620000 1834.520000 ;
+ RECT 1043.390000 1834.040000 1044.390000 1834.520000 ;
+ RECT 1047.520000 1823.160000 1048.620000 1823.640000 ;
+ RECT 1043.390000 1823.160000 1044.390000 1823.640000 ;
+ RECT 1043.390000 1828.600000 1044.390000 1829.080000 ;
+ RECT 1047.520000 1828.600000 1048.620000 1829.080000 ;
+ RECT 1047.520000 1817.720000 1048.620000 1818.200000 ;
+ RECT 1043.390000 1817.720000 1044.390000 1818.200000 ;
+ RECT 1047.520000 1812.280000 1048.620000 1812.760000 ;
+ RECT 1043.390000 1812.280000 1044.390000 1812.760000 ;
+ RECT 1047.520000 1806.840000 1048.620000 1807.320000 ;
+ RECT 1043.390000 1806.840000 1044.390000 1807.320000 ;
+ RECT 1047.520000 1801.400000 1048.620000 1801.880000 ;
+ RECT 1043.390000 1801.400000 1044.390000 1801.880000 ;
+ RECT 1137.520000 1795.960000 1138.620000 1796.440000 ;
+ RECT 1137.520000 1790.520000 1138.620000 1791.000000 ;
+ RECT 1137.520000 1785.080000 1138.620000 1785.560000 ;
+ RECT 1137.520000 1779.640000 1138.620000 1780.120000 ;
+ RECT 1137.520000 1774.200000 1138.620000 1774.680000 ;
+ RECT 1092.520000 1795.960000 1093.620000 1796.440000 ;
+ RECT 1092.520000 1790.520000 1093.620000 1791.000000 ;
+ RECT 1092.520000 1785.080000 1093.620000 1785.560000 ;
+ RECT 1092.520000 1779.640000 1093.620000 1780.120000 ;
+ RECT 1092.520000 1774.200000 1093.620000 1774.680000 ;
+ RECT 1137.520000 1752.440000 1138.620000 1752.920000 ;
+ RECT 1137.520000 1757.880000 1138.620000 1758.360000 ;
+ RECT 1137.520000 1763.320000 1138.620000 1763.800000 ;
+ RECT 1137.520000 1768.760000 1138.620000 1769.240000 ;
+ RECT 1092.520000 1752.440000 1093.620000 1752.920000 ;
+ RECT 1092.520000 1757.880000 1093.620000 1758.360000 ;
+ RECT 1092.520000 1763.320000 1093.620000 1763.800000 ;
+ RECT 1092.520000 1768.760000 1093.620000 1769.240000 ;
+ RECT 1047.520000 1795.960000 1048.620000 1796.440000 ;
+ RECT 1043.390000 1795.960000 1044.390000 1796.440000 ;
+ RECT 1047.520000 1790.520000 1048.620000 1791.000000 ;
+ RECT 1043.390000 1790.520000 1044.390000 1791.000000 ;
+ RECT 1047.520000 1779.640000 1048.620000 1780.120000 ;
+ RECT 1043.390000 1779.640000 1044.390000 1780.120000 ;
+ RECT 1047.520000 1774.200000 1048.620000 1774.680000 ;
+ RECT 1043.390000 1774.200000 1044.390000 1774.680000 ;
+ RECT 1047.520000 1785.080000 1048.620000 1785.560000 ;
+ RECT 1043.390000 1785.080000 1044.390000 1785.560000 ;
+ RECT 1047.520000 1768.760000 1048.620000 1769.240000 ;
+ RECT 1043.390000 1768.760000 1044.390000 1769.240000 ;
+ RECT 1047.520000 1763.320000 1048.620000 1763.800000 ;
+ RECT 1043.390000 1763.320000 1044.390000 1763.800000 ;
+ RECT 1047.520000 1757.880000 1048.620000 1758.360000 ;
+ RECT 1047.520000 1752.440000 1048.620000 1752.920000 ;
+ RECT 1043.390000 1757.880000 1044.390000 1758.360000 ;
+ RECT 1043.390000 1752.440000 1044.390000 1752.920000 ;
+ RECT 1040.560000 1942.800000 1240.660000 1943.800000 ;
+ RECT 1040.560000 1750.430000 1240.660000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 1747.580000 1044.390000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 1946.840000 1044.390000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 1747.580000 1237.830000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 1946.840000 1237.830000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1750.430000 1041.560000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1750.430000 1240.660000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1942.800000 1041.560000 1943.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1942.800000 1240.660000 1943.800000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1227.520000 1550.170000 1228.620000 1743.540000 ;
+ RECT 1182.520000 1550.170000 1183.620000 1743.540000 ;
+ RECT 1236.830000 1547.320000 1237.830000 1747.580000 ;
+ RECT 1137.520000 1550.170000 1138.620000 1743.540000 ;
+ RECT 1092.520000 1550.170000 1093.620000 1743.540000 ;
+ RECT 1047.520000 1550.170000 1048.620000 1743.540000 ;
+ RECT 1043.390000 1547.320000 1044.390000 1747.580000 ;
+ LAYER met3 ;
+ RECT 1227.520000 1737.140000 1228.620000 1737.620000 ;
+ RECT 1236.830000 1737.140000 1237.830000 1737.620000 ;
+ RECT 1236.830000 1726.260000 1237.830000 1726.740000 ;
+ RECT 1236.830000 1731.700000 1237.830000 1732.180000 ;
+ RECT 1227.520000 1731.700000 1228.620000 1732.180000 ;
+ RECT 1227.520000 1726.260000 1228.620000 1726.740000 ;
+ RECT 1227.520000 1720.820000 1228.620000 1721.300000 ;
+ RECT 1227.520000 1715.380000 1228.620000 1715.860000 ;
+ RECT 1236.830000 1720.820000 1237.830000 1721.300000 ;
+ RECT 1236.830000 1715.380000 1237.830000 1715.860000 ;
+ RECT 1227.520000 1699.060000 1228.620000 1699.540000 ;
+ RECT 1227.520000 1704.500000 1228.620000 1704.980000 ;
+ RECT 1236.830000 1704.500000 1237.830000 1704.980000 ;
+ RECT 1236.830000 1699.060000 1237.830000 1699.540000 ;
+ RECT 1227.520000 1709.940000 1228.620000 1710.420000 ;
+ RECT 1236.830000 1709.940000 1237.830000 1710.420000 ;
+ RECT 1182.520000 1737.140000 1183.620000 1737.620000 ;
+ RECT 1182.520000 1731.700000 1183.620000 1732.180000 ;
+ RECT 1182.520000 1726.260000 1183.620000 1726.740000 ;
+ RECT 1182.520000 1720.820000 1183.620000 1721.300000 ;
+ RECT 1182.520000 1699.060000 1183.620000 1699.540000 ;
+ RECT 1182.520000 1704.500000 1183.620000 1704.980000 ;
+ RECT 1182.520000 1709.940000 1183.620000 1710.420000 ;
+ RECT 1182.520000 1715.380000 1183.620000 1715.860000 ;
+ RECT 1236.830000 1688.180000 1237.830000 1688.660000 ;
+ RECT 1236.830000 1693.620000 1237.830000 1694.100000 ;
+ RECT 1227.520000 1693.620000 1228.620000 1694.100000 ;
+ RECT 1227.520000 1688.180000 1228.620000 1688.660000 ;
+ RECT 1227.520000 1682.740000 1228.620000 1683.220000 ;
+ RECT 1227.520000 1677.300000 1228.620000 1677.780000 ;
+ RECT 1236.830000 1682.740000 1237.830000 1683.220000 ;
+ RECT 1236.830000 1677.300000 1237.830000 1677.780000 ;
+ RECT 1236.830000 1660.980000 1237.830000 1661.460000 ;
+ RECT 1236.830000 1666.420000 1237.830000 1666.900000 ;
+ RECT 1236.830000 1671.860000 1237.830000 1672.340000 ;
+ RECT 1227.520000 1666.420000 1228.620000 1666.900000 ;
+ RECT 1227.520000 1660.980000 1228.620000 1661.460000 ;
+ RECT 1227.520000 1671.860000 1228.620000 1672.340000 ;
+ RECT 1227.520000 1655.540000 1228.620000 1656.020000 ;
+ RECT 1227.520000 1650.100000 1228.620000 1650.580000 ;
+ RECT 1236.830000 1655.540000 1237.830000 1656.020000 ;
+ RECT 1236.830000 1650.100000 1237.830000 1650.580000 ;
+ RECT 1182.520000 1693.620000 1183.620000 1694.100000 ;
+ RECT 1182.520000 1688.180000 1183.620000 1688.660000 ;
+ RECT 1182.520000 1682.740000 1183.620000 1683.220000 ;
+ RECT 1182.520000 1677.300000 1183.620000 1677.780000 ;
+ RECT 1182.520000 1666.420000 1183.620000 1666.900000 ;
+ RECT 1182.520000 1660.980000 1183.620000 1661.460000 ;
+ RECT 1182.520000 1655.540000 1183.620000 1656.020000 ;
+ RECT 1182.520000 1650.100000 1183.620000 1650.580000 ;
+ RECT 1182.520000 1671.860000 1183.620000 1672.340000 ;
+ RECT 1137.520000 1737.140000 1138.620000 1737.620000 ;
+ RECT 1137.520000 1731.700000 1138.620000 1732.180000 ;
+ RECT 1137.520000 1726.260000 1138.620000 1726.740000 ;
+ RECT 1092.520000 1737.140000 1093.620000 1737.620000 ;
+ RECT 1092.520000 1731.700000 1093.620000 1732.180000 ;
+ RECT 1092.520000 1726.260000 1093.620000 1726.740000 ;
+ RECT 1137.520000 1709.940000 1138.620000 1710.420000 ;
+ RECT 1137.520000 1704.500000 1138.620000 1704.980000 ;
+ RECT 1137.520000 1699.060000 1138.620000 1699.540000 ;
+ RECT 1137.520000 1715.380000 1138.620000 1715.860000 ;
+ RECT 1137.520000 1720.820000 1138.620000 1721.300000 ;
+ RECT 1092.520000 1720.820000 1093.620000 1721.300000 ;
+ RECT 1092.520000 1709.940000 1093.620000 1710.420000 ;
+ RECT 1092.520000 1704.500000 1093.620000 1704.980000 ;
+ RECT 1092.520000 1699.060000 1093.620000 1699.540000 ;
+ RECT 1092.520000 1715.380000 1093.620000 1715.860000 ;
+ RECT 1047.520000 1737.140000 1048.620000 1737.620000 ;
+ RECT 1043.390000 1737.140000 1044.390000 1737.620000 ;
+ RECT 1043.390000 1731.700000 1044.390000 1732.180000 ;
+ RECT 1047.520000 1731.700000 1048.620000 1732.180000 ;
+ RECT 1047.520000 1726.260000 1048.620000 1726.740000 ;
+ RECT 1043.390000 1726.260000 1044.390000 1726.740000 ;
+ RECT 1047.520000 1720.820000 1048.620000 1721.300000 ;
+ RECT 1043.390000 1720.820000 1044.390000 1721.300000 ;
+ RECT 1047.520000 1715.380000 1048.620000 1715.860000 ;
+ RECT 1043.390000 1715.380000 1044.390000 1715.860000 ;
+ RECT 1047.520000 1704.500000 1048.620000 1704.980000 ;
+ RECT 1043.390000 1704.500000 1044.390000 1704.980000 ;
+ RECT 1047.520000 1699.060000 1048.620000 1699.540000 ;
+ RECT 1043.390000 1699.060000 1044.390000 1699.540000 ;
+ RECT 1047.520000 1709.940000 1048.620000 1710.420000 ;
+ RECT 1043.390000 1709.940000 1044.390000 1710.420000 ;
+ RECT 1137.520000 1693.620000 1138.620000 1694.100000 ;
+ RECT 1137.520000 1688.180000 1138.620000 1688.660000 ;
+ RECT 1137.520000 1682.740000 1138.620000 1683.220000 ;
+ RECT 1137.520000 1677.300000 1138.620000 1677.780000 ;
+ RECT 1092.520000 1693.620000 1093.620000 1694.100000 ;
+ RECT 1092.520000 1688.180000 1093.620000 1688.660000 ;
+ RECT 1092.520000 1682.740000 1093.620000 1683.220000 ;
+ RECT 1092.520000 1677.300000 1093.620000 1677.780000 ;
+ RECT 1137.520000 1666.420000 1138.620000 1666.900000 ;
+ RECT 1137.520000 1650.100000 1138.620000 1650.580000 ;
+ RECT 1137.520000 1655.540000 1138.620000 1656.020000 ;
+ RECT 1137.520000 1660.980000 1138.620000 1661.460000 ;
+ RECT 1137.520000 1671.860000 1138.620000 1672.340000 ;
+ RECT 1092.520000 1650.100000 1093.620000 1650.580000 ;
+ RECT 1092.520000 1655.540000 1093.620000 1656.020000 ;
+ RECT 1092.520000 1660.980000 1093.620000 1661.460000 ;
+ RECT 1092.520000 1666.420000 1093.620000 1666.900000 ;
+ RECT 1092.520000 1671.860000 1093.620000 1672.340000 ;
+ RECT 1047.520000 1693.620000 1048.620000 1694.100000 ;
+ RECT 1043.390000 1693.620000 1044.390000 1694.100000 ;
+ RECT 1047.520000 1688.180000 1048.620000 1688.660000 ;
+ RECT 1043.390000 1688.180000 1044.390000 1688.660000 ;
+ RECT 1047.520000 1682.740000 1048.620000 1683.220000 ;
+ RECT 1043.390000 1682.740000 1044.390000 1683.220000 ;
+ RECT 1047.520000 1677.300000 1048.620000 1677.780000 ;
+ RECT 1043.390000 1677.300000 1044.390000 1677.780000 ;
+ RECT 1047.520000 1671.860000 1048.620000 1672.340000 ;
+ RECT 1047.520000 1666.420000 1048.620000 1666.900000 ;
+ RECT 1043.390000 1671.860000 1044.390000 1672.340000 ;
+ RECT 1043.390000 1666.420000 1044.390000 1666.900000 ;
+ RECT 1047.520000 1660.980000 1048.620000 1661.460000 ;
+ RECT 1043.390000 1660.980000 1044.390000 1661.460000 ;
+ RECT 1047.520000 1655.540000 1048.620000 1656.020000 ;
+ RECT 1043.390000 1655.540000 1044.390000 1656.020000 ;
+ RECT 1047.520000 1650.100000 1048.620000 1650.580000 ;
+ RECT 1043.390000 1650.100000 1044.390000 1650.580000 ;
+ RECT 1227.520000 1644.660000 1228.620000 1645.140000 ;
+ RECT 1227.520000 1639.220000 1228.620000 1639.700000 ;
+ RECT 1236.830000 1644.660000 1237.830000 1645.140000 ;
+ RECT 1236.830000 1639.220000 1237.830000 1639.700000 ;
+ RECT 1236.830000 1622.900000 1237.830000 1623.380000 ;
+ RECT 1236.830000 1628.340000 1237.830000 1628.820000 ;
+ RECT 1236.830000 1633.780000 1237.830000 1634.260000 ;
+ RECT 1227.520000 1633.780000 1228.620000 1634.260000 ;
+ RECT 1227.520000 1628.340000 1228.620000 1628.820000 ;
+ RECT 1227.520000 1622.900000 1228.620000 1623.380000 ;
+ RECT 1227.520000 1612.020000 1228.620000 1612.500000 ;
+ RECT 1227.520000 1617.460000 1228.620000 1617.940000 ;
+ RECT 1236.830000 1617.460000 1237.830000 1617.940000 ;
+ RECT 1236.830000 1612.020000 1237.830000 1612.500000 ;
+ RECT 1236.830000 1601.140000 1237.830000 1601.620000 ;
+ RECT 1236.830000 1606.580000 1237.830000 1607.060000 ;
+ RECT 1227.520000 1601.140000 1228.620000 1601.620000 ;
+ RECT 1227.520000 1606.580000 1228.620000 1607.060000 ;
+ RECT 1182.520000 1644.660000 1183.620000 1645.140000 ;
+ RECT 1182.520000 1639.220000 1183.620000 1639.700000 ;
+ RECT 1182.520000 1633.780000 1183.620000 1634.260000 ;
+ RECT 1182.520000 1628.340000 1183.620000 1628.820000 ;
+ RECT 1182.520000 1622.900000 1183.620000 1623.380000 ;
+ RECT 1182.520000 1601.140000 1183.620000 1601.620000 ;
+ RECT 1182.520000 1606.580000 1183.620000 1607.060000 ;
+ RECT 1182.520000 1612.020000 1183.620000 1612.500000 ;
+ RECT 1182.520000 1617.460000 1183.620000 1617.940000 ;
+ RECT 1227.520000 1595.700000 1228.620000 1596.180000 ;
+ RECT 1227.520000 1590.260000 1228.620000 1590.740000 ;
+ RECT 1236.830000 1595.700000 1237.830000 1596.180000 ;
+ RECT 1236.830000 1590.260000 1237.830000 1590.740000 ;
+ RECT 1227.520000 1579.380000 1228.620000 1579.860000 ;
+ RECT 1227.520000 1573.940000 1228.620000 1574.420000 ;
+ RECT 1236.830000 1579.380000 1237.830000 1579.860000 ;
+ RECT 1236.830000 1573.940000 1237.830000 1574.420000 ;
+ RECT 1227.520000 1584.820000 1228.620000 1585.300000 ;
+ RECT 1236.830000 1584.820000 1237.830000 1585.300000 ;
+ RECT 1236.830000 1563.060000 1237.830000 1563.540000 ;
+ RECT 1236.830000 1568.500000 1237.830000 1568.980000 ;
+ RECT 1227.520000 1568.500000 1228.620000 1568.980000 ;
+ RECT 1227.520000 1563.060000 1228.620000 1563.540000 ;
+ RECT 1227.520000 1557.620000 1228.620000 1558.100000 ;
+ RECT 1227.520000 1552.180000 1228.620000 1552.660000 ;
+ RECT 1236.830000 1557.620000 1237.830000 1558.100000 ;
+ RECT 1236.830000 1552.180000 1237.830000 1552.660000 ;
+ RECT 1182.520000 1595.700000 1183.620000 1596.180000 ;
+ RECT 1182.520000 1590.260000 1183.620000 1590.740000 ;
+ RECT 1182.520000 1584.820000 1183.620000 1585.300000 ;
+ RECT 1182.520000 1579.380000 1183.620000 1579.860000 ;
+ RECT 1182.520000 1573.940000 1183.620000 1574.420000 ;
+ RECT 1182.520000 1568.500000 1183.620000 1568.980000 ;
+ RECT 1182.520000 1563.060000 1183.620000 1563.540000 ;
+ RECT 1182.520000 1557.620000 1183.620000 1558.100000 ;
+ RECT 1182.520000 1552.180000 1183.620000 1552.660000 ;
+ RECT 1137.520000 1644.660000 1138.620000 1645.140000 ;
+ RECT 1137.520000 1639.220000 1138.620000 1639.700000 ;
+ RECT 1137.520000 1633.780000 1138.620000 1634.260000 ;
+ RECT 1137.520000 1628.340000 1138.620000 1628.820000 ;
+ RECT 1137.520000 1622.900000 1138.620000 1623.380000 ;
+ RECT 1092.520000 1644.660000 1093.620000 1645.140000 ;
+ RECT 1092.520000 1639.220000 1093.620000 1639.700000 ;
+ RECT 1092.520000 1633.780000 1093.620000 1634.260000 ;
+ RECT 1092.520000 1628.340000 1093.620000 1628.820000 ;
+ RECT 1092.520000 1622.900000 1093.620000 1623.380000 ;
+ RECT 1137.520000 1617.460000 1138.620000 1617.940000 ;
+ RECT 1137.520000 1612.020000 1138.620000 1612.500000 ;
+ RECT 1137.520000 1606.580000 1138.620000 1607.060000 ;
+ RECT 1137.520000 1601.140000 1138.620000 1601.620000 ;
+ RECT 1092.520000 1612.020000 1093.620000 1612.500000 ;
+ RECT 1092.520000 1606.580000 1093.620000 1607.060000 ;
+ RECT 1092.520000 1601.140000 1093.620000 1601.620000 ;
+ RECT 1092.520000 1617.460000 1093.620000 1617.940000 ;
+ RECT 1047.520000 1644.660000 1048.620000 1645.140000 ;
+ RECT 1043.390000 1644.660000 1044.390000 1645.140000 ;
+ RECT 1047.520000 1639.220000 1048.620000 1639.700000 ;
+ RECT 1043.390000 1639.220000 1044.390000 1639.700000 ;
+ RECT 1047.520000 1633.780000 1048.620000 1634.260000 ;
+ RECT 1043.390000 1633.780000 1044.390000 1634.260000 ;
+ RECT 1047.520000 1622.900000 1048.620000 1623.380000 ;
+ RECT 1043.390000 1622.900000 1044.390000 1623.380000 ;
+ RECT 1043.390000 1628.340000 1044.390000 1628.820000 ;
+ RECT 1047.520000 1628.340000 1048.620000 1628.820000 ;
+ RECT 1047.520000 1617.460000 1048.620000 1617.940000 ;
+ RECT 1043.390000 1617.460000 1044.390000 1617.940000 ;
+ RECT 1047.520000 1612.020000 1048.620000 1612.500000 ;
+ RECT 1043.390000 1612.020000 1044.390000 1612.500000 ;
+ RECT 1047.520000 1606.580000 1048.620000 1607.060000 ;
+ RECT 1043.390000 1606.580000 1044.390000 1607.060000 ;
+ RECT 1047.520000 1601.140000 1048.620000 1601.620000 ;
+ RECT 1043.390000 1601.140000 1044.390000 1601.620000 ;
+ RECT 1137.520000 1595.700000 1138.620000 1596.180000 ;
+ RECT 1137.520000 1590.260000 1138.620000 1590.740000 ;
+ RECT 1137.520000 1584.820000 1138.620000 1585.300000 ;
+ RECT 1137.520000 1579.380000 1138.620000 1579.860000 ;
+ RECT 1137.520000 1573.940000 1138.620000 1574.420000 ;
+ RECT 1092.520000 1595.700000 1093.620000 1596.180000 ;
+ RECT 1092.520000 1590.260000 1093.620000 1590.740000 ;
+ RECT 1092.520000 1584.820000 1093.620000 1585.300000 ;
+ RECT 1092.520000 1579.380000 1093.620000 1579.860000 ;
+ RECT 1092.520000 1573.940000 1093.620000 1574.420000 ;
+ RECT 1137.520000 1552.180000 1138.620000 1552.660000 ;
+ RECT 1137.520000 1557.620000 1138.620000 1558.100000 ;
+ RECT 1137.520000 1563.060000 1138.620000 1563.540000 ;
+ RECT 1137.520000 1568.500000 1138.620000 1568.980000 ;
+ RECT 1092.520000 1552.180000 1093.620000 1552.660000 ;
+ RECT 1092.520000 1557.620000 1093.620000 1558.100000 ;
+ RECT 1092.520000 1563.060000 1093.620000 1563.540000 ;
+ RECT 1092.520000 1568.500000 1093.620000 1568.980000 ;
+ RECT 1047.520000 1595.700000 1048.620000 1596.180000 ;
+ RECT 1043.390000 1595.700000 1044.390000 1596.180000 ;
+ RECT 1047.520000 1590.260000 1048.620000 1590.740000 ;
+ RECT 1043.390000 1590.260000 1044.390000 1590.740000 ;
+ RECT 1047.520000 1579.380000 1048.620000 1579.860000 ;
+ RECT 1043.390000 1579.380000 1044.390000 1579.860000 ;
+ RECT 1047.520000 1573.940000 1048.620000 1574.420000 ;
+ RECT 1043.390000 1573.940000 1044.390000 1574.420000 ;
+ RECT 1047.520000 1584.820000 1048.620000 1585.300000 ;
+ RECT 1043.390000 1584.820000 1044.390000 1585.300000 ;
+ RECT 1047.520000 1568.500000 1048.620000 1568.980000 ;
+ RECT 1043.390000 1568.500000 1044.390000 1568.980000 ;
+ RECT 1047.520000 1563.060000 1048.620000 1563.540000 ;
+ RECT 1043.390000 1563.060000 1044.390000 1563.540000 ;
+ RECT 1047.520000 1557.620000 1048.620000 1558.100000 ;
+ RECT 1047.520000 1552.180000 1048.620000 1552.660000 ;
+ RECT 1043.390000 1557.620000 1044.390000 1558.100000 ;
+ RECT 1043.390000 1552.180000 1044.390000 1552.660000 ;
+ RECT 1040.560000 1742.540000 1240.660000 1743.540000 ;
+ RECT 1040.560000 1550.170000 1240.660000 1551.170000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 1547.320000 1044.390000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1043.390000 1746.580000 1044.390000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 1547.320000 1237.830000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1236.830000 1746.580000 1237.830000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1550.170000 1041.560000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1550.170000 1240.660000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1040.560000 1742.540000 1041.560000 1743.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1239.660000 1742.540000 1240.660000 1743.540000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 3349.660000 1244.490000 3379.920000 ;
+ RECT 1436.930000 3349.660000 1437.930000 3379.920000 ;
+ RECT 1247.620000 3352.510000 1248.720000 3376.560000 ;
+ RECT 1292.620000 3352.510000 1293.720000 3376.560000 ;
+ RECT 1337.620000 3352.510000 1338.720000 3376.560000 ;
+ RECT 1382.620000 3352.510000 1383.720000 3376.560000 ;
+ RECT 1427.620000 3352.510000 1428.720000 3376.560000 ;
+ LAYER met3 ;
+ RECT 1436.930000 3365.400000 1437.930000 3365.880000 ;
+ RECT 1436.930000 3370.840000 1437.930000 3371.320000 ;
+ RECT 1427.620000 3370.840000 1428.720000 3371.320000 ;
+ RECT 1427.620000 3365.400000 1428.720000 3365.880000 ;
+ RECT 1382.620000 3365.400000 1383.720000 3365.880000 ;
+ RECT 1382.620000 3370.840000 1383.720000 3371.320000 ;
+ RECT 1292.620000 3365.400000 1293.720000 3365.880000 ;
+ RECT 1337.620000 3365.400000 1338.720000 3365.880000 ;
+ RECT 1337.620000 3370.840000 1338.720000 3371.320000 ;
+ RECT 1292.620000 3370.840000 1293.720000 3371.320000 ;
+ RECT 1243.490000 3365.400000 1244.490000 3365.880000 ;
+ RECT 1247.620000 3365.400000 1248.720000 3365.880000 ;
+ RECT 1247.620000 3370.840000 1248.720000 3371.320000 ;
+ RECT 1243.490000 3370.840000 1244.490000 3371.320000 ;
+ RECT 1436.930000 3354.520000 1437.930000 3355.000000 ;
+ RECT 1436.930000 3359.960000 1437.930000 3360.440000 ;
+ RECT 1427.620000 3359.960000 1428.720000 3360.440000 ;
+ RECT 1427.620000 3354.520000 1428.720000 3355.000000 ;
+ RECT 1382.620000 3354.520000 1383.720000 3355.000000 ;
+ RECT 1382.620000 3359.960000 1383.720000 3360.440000 ;
+ RECT 1292.620000 3354.520000 1293.720000 3355.000000 ;
+ RECT 1337.620000 3354.520000 1338.720000 3355.000000 ;
+ RECT 1337.620000 3359.960000 1338.720000 3360.440000 ;
+ RECT 1292.620000 3359.960000 1293.720000 3360.440000 ;
+ RECT 1243.490000 3359.960000 1244.490000 3360.440000 ;
+ RECT 1247.620000 3359.960000 1248.720000 3360.440000 ;
+ RECT 1243.490000 3354.520000 1244.490000 3355.000000 ;
+ RECT 1247.620000 3354.520000 1248.720000 3355.000000 ;
+ RECT 1240.660000 3375.560000 1440.760000 3376.560000 ;
+ RECT 1240.660000 3352.510000 1440.760000 3353.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 3349.660000 1244.490000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 3378.920000 1244.490000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 3349.660000 1437.930000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 3378.920000 1437.930000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 3352.510000 1241.660000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 3352.510000 1440.760000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 3375.560000 1241.660000 3376.560000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 3375.560000 1440.760000 3376.560000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 1349.910000 1428.720000 1543.280000 ;
+ RECT 1382.620000 1349.910000 1383.720000 1543.280000 ;
+ RECT 1436.930000 1347.060000 1437.930000 1547.320000 ;
+ RECT 1337.620000 1349.910000 1338.720000 1543.280000 ;
+ RECT 1292.620000 1349.910000 1293.720000 1543.280000 ;
+ RECT 1247.620000 1349.910000 1248.720000 1543.280000 ;
+ RECT 1243.490000 1347.060000 1244.490000 1547.320000 ;
+ LAYER met3 ;
+ RECT 1427.620000 1536.880000 1428.720000 1537.360000 ;
+ RECT 1436.930000 1536.880000 1437.930000 1537.360000 ;
+ RECT 1436.930000 1526.000000 1437.930000 1526.480000 ;
+ RECT 1436.930000 1531.440000 1437.930000 1531.920000 ;
+ RECT 1427.620000 1531.440000 1428.720000 1531.920000 ;
+ RECT 1427.620000 1526.000000 1428.720000 1526.480000 ;
+ RECT 1427.620000 1520.560000 1428.720000 1521.040000 ;
+ RECT 1427.620000 1515.120000 1428.720000 1515.600000 ;
+ RECT 1436.930000 1520.560000 1437.930000 1521.040000 ;
+ RECT 1436.930000 1515.120000 1437.930000 1515.600000 ;
+ RECT 1427.620000 1498.800000 1428.720000 1499.280000 ;
+ RECT 1427.620000 1504.240000 1428.720000 1504.720000 ;
+ RECT 1436.930000 1504.240000 1437.930000 1504.720000 ;
+ RECT 1436.930000 1498.800000 1437.930000 1499.280000 ;
+ RECT 1427.620000 1509.680000 1428.720000 1510.160000 ;
+ RECT 1436.930000 1509.680000 1437.930000 1510.160000 ;
+ RECT 1382.620000 1536.880000 1383.720000 1537.360000 ;
+ RECT 1382.620000 1531.440000 1383.720000 1531.920000 ;
+ RECT 1382.620000 1526.000000 1383.720000 1526.480000 ;
+ RECT 1382.620000 1520.560000 1383.720000 1521.040000 ;
+ RECT 1382.620000 1498.800000 1383.720000 1499.280000 ;
+ RECT 1382.620000 1504.240000 1383.720000 1504.720000 ;
+ RECT 1382.620000 1509.680000 1383.720000 1510.160000 ;
+ RECT 1382.620000 1515.120000 1383.720000 1515.600000 ;
+ RECT 1436.930000 1487.920000 1437.930000 1488.400000 ;
+ RECT 1436.930000 1493.360000 1437.930000 1493.840000 ;
+ RECT 1427.620000 1493.360000 1428.720000 1493.840000 ;
+ RECT 1427.620000 1487.920000 1428.720000 1488.400000 ;
+ RECT 1427.620000 1482.480000 1428.720000 1482.960000 ;
+ RECT 1427.620000 1477.040000 1428.720000 1477.520000 ;
+ RECT 1436.930000 1482.480000 1437.930000 1482.960000 ;
+ RECT 1436.930000 1477.040000 1437.930000 1477.520000 ;
+ RECT 1436.930000 1460.720000 1437.930000 1461.200000 ;
+ RECT 1436.930000 1466.160000 1437.930000 1466.640000 ;
+ RECT 1436.930000 1471.600000 1437.930000 1472.080000 ;
+ RECT 1427.620000 1466.160000 1428.720000 1466.640000 ;
+ RECT 1427.620000 1460.720000 1428.720000 1461.200000 ;
+ RECT 1427.620000 1471.600000 1428.720000 1472.080000 ;
+ RECT 1427.620000 1455.280000 1428.720000 1455.760000 ;
+ RECT 1427.620000 1449.840000 1428.720000 1450.320000 ;
+ RECT 1436.930000 1455.280000 1437.930000 1455.760000 ;
+ RECT 1436.930000 1449.840000 1437.930000 1450.320000 ;
+ RECT 1382.620000 1493.360000 1383.720000 1493.840000 ;
+ RECT 1382.620000 1487.920000 1383.720000 1488.400000 ;
+ RECT 1382.620000 1482.480000 1383.720000 1482.960000 ;
+ RECT 1382.620000 1477.040000 1383.720000 1477.520000 ;
+ RECT 1382.620000 1466.160000 1383.720000 1466.640000 ;
+ RECT 1382.620000 1460.720000 1383.720000 1461.200000 ;
+ RECT 1382.620000 1455.280000 1383.720000 1455.760000 ;
+ RECT 1382.620000 1449.840000 1383.720000 1450.320000 ;
+ RECT 1382.620000 1471.600000 1383.720000 1472.080000 ;
+ RECT 1337.620000 1536.880000 1338.720000 1537.360000 ;
+ RECT 1337.620000 1531.440000 1338.720000 1531.920000 ;
+ RECT 1337.620000 1526.000000 1338.720000 1526.480000 ;
+ RECT 1292.620000 1536.880000 1293.720000 1537.360000 ;
+ RECT 1292.620000 1531.440000 1293.720000 1531.920000 ;
+ RECT 1292.620000 1526.000000 1293.720000 1526.480000 ;
+ RECT 1337.620000 1509.680000 1338.720000 1510.160000 ;
+ RECT 1337.620000 1504.240000 1338.720000 1504.720000 ;
+ RECT 1337.620000 1498.800000 1338.720000 1499.280000 ;
+ RECT 1337.620000 1515.120000 1338.720000 1515.600000 ;
+ RECT 1337.620000 1520.560000 1338.720000 1521.040000 ;
+ RECT 1292.620000 1520.560000 1293.720000 1521.040000 ;
+ RECT 1292.620000 1509.680000 1293.720000 1510.160000 ;
+ RECT 1292.620000 1504.240000 1293.720000 1504.720000 ;
+ RECT 1292.620000 1498.800000 1293.720000 1499.280000 ;
+ RECT 1292.620000 1515.120000 1293.720000 1515.600000 ;
+ RECT 1247.620000 1536.880000 1248.720000 1537.360000 ;
+ RECT 1243.490000 1536.880000 1244.490000 1537.360000 ;
+ RECT 1243.490000 1531.440000 1244.490000 1531.920000 ;
+ RECT 1247.620000 1531.440000 1248.720000 1531.920000 ;
+ RECT 1247.620000 1526.000000 1248.720000 1526.480000 ;
+ RECT 1243.490000 1526.000000 1244.490000 1526.480000 ;
+ RECT 1247.620000 1520.560000 1248.720000 1521.040000 ;
+ RECT 1243.490000 1520.560000 1244.490000 1521.040000 ;
+ RECT 1247.620000 1515.120000 1248.720000 1515.600000 ;
+ RECT 1243.490000 1515.120000 1244.490000 1515.600000 ;
+ RECT 1247.620000 1504.240000 1248.720000 1504.720000 ;
+ RECT 1243.490000 1504.240000 1244.490000 1504.720000 ;
+ RECT 1247.620000 1498.800000 1248.720000 1499.280000 ;
+ RECT 1243.490000 1498.800000 1244.490000 1499.280000 ;
+ RECT 1247.620000 1509.680000 1248.720000 1510.160000 ;
+ RECT 1243.490000 1509.680000 1244.490000 1510.160000 ;
+ RECT 1337.620000 1493.360000 1338.720000 1493.840000 ;
+ RECT 1337.620000 1487.920000 1338.720000 1488.400000 ;
+ RECT 1337.620000 1482.480000 1338.720000 1482.960000 ;
+ RECT 1337.620000 1477.040000 1338.720000 1477.520000 ;
+ RECT 1292.620000 1493.360000 1293.720000 1493.840000 ;
+ RECT 1292.620000 1487.920000 1293.720000 1488.400000 ;
+ RECT 1292.620000 1482.480000 1293.720000 1482.960000 ;
+ RECT 1292.620000 1477.040000 1293.720000 1477.520000 ;
+ RECT 1337.620000 1466.160000 1338.720000 1466.640000 ;
+ RECT 1337.620000 1449.840000 1338.720000 1450.320000 ;
+ RECT 1337.620000 1455.280000 1338.720000 1455.760000 ;
+ RECT 1337.620000 1460.720000 1338.720000 1461.200000 ;
+ RECT 1337.620000 1471.600000 1338.720000 1472.080000 ;
+ RECT 1292.620000 1449.840000 1293.720000 1450.320000 ;
+ RECT 1292.620000 1455.280000 1293.720000 1455.760000 ;
+ RECT 1292.620000 1460.720000 1293.720000 1461.200000 ;
+ RECT 1292.620000 1466.160000 1293.720000 1466.640000 ;
+ RECT 1292.620000 1471.600000 1293.720000 1472.080000 ;
+ RECT 1247.620000 1493.360000 1248.720000 1493.840000 ;
+ RECT 1243.490000 1493.360000 1244.490000 1493.840000 ;
+ RECT 1247.620000 1487.920000 1248.720000 1488.400000 ;
+ RECT 1243.490000 1487.920000 1244.490000 1488.400000 ;
+ RECT 1247.620000 1482.480000 1248.720000 1482.960000 ;
+ RECT 1243.490000 1482.480000 1244.490000 1482.960000 ;
+ RECT 1247.620000 1477.040000 1248.720000 1477.520000 ;
+ RECT 1243.490000 1477.040000 1244.490000 1477.520000 ;
+ RECT 1247.620000 1471.600000 1248.720000 1472.080000 ;
+ RECT 1247.620000 1466.160000 1248.720000 1466.640000 ;
+ RECT 1243.490000 1471.600000 1244.490000 1472.080000 ;
+ RECT 1243.490000 1466.160000 1244.490000 1466.640000 ;
+ RECT 1247.620000 1460.720000 1248.720000 1461.200000 ;
+ RECT 1243.490000 1460.720000 1244.490000 1461.200000 ;
+ RECT 1247.620000 1455.280000 1248.720000 1455.760000 ;
+ RECT 1243.490000 1455.280000 1244.490000 1455.760000 ;
+ RECT 1247.620000 1449.840000 1248.720000 1450.320000 ;
+ RECT 1243.490000 1449.840000 1244.490000 1450.320000 ;
+ RECT 1427.620000 1444.400000 1428.720000 1444.880000 ;
+ RECT 1427.620000 1438.960000 1428.720000 1439.440000 ;
+ RECT 1436.930000 1444.400000 1437.930000 1444.880000 ;
+ RECT 1436.930000 1438.960000 1437.930000 1439.440000 ;
+ RECT 1436.930000 1422.640000 1437.930000 1423.120000 ;
+ RECT 1436.930000 1428.080000 1437.930000 1428.560000 ;
+ RECT 1436.930000 1433.520000 1437.930000 1434.000000 ;
+ RECT 1427.620000 1433.520000 1428.720000 1434.000000 ;
+ RECT 1427.620000 1428.080000 1428.720000 1428.560000 ;
+ RECT 1427.620000 1422.640000 1428.720000 1423.120000 ;
+ RECT 1427.620000 1411.760000 1428.720000 1412.240000 ;
+ RECT 1427.620000 1417.200000 1428.720000 1417.680000 ;
+ RECT 1436.930000 1417.200000 1437.930000 1417.680000 ;
+ RECT 1436.930000 1411.760000 1437.930000 1412.240000 ;
+ RECT 1436.930000 1400.880000 1437.930000 1401.360000 ;
+ RECT 1436.930000 1406.320000 1437.930000 1406.800000 ;
+ RECT 1427.620000 1400.880000 1428.720000 1401.360000 ;
+ RECT 1427.620000 1406.320000 1428.720000 1406.800000 ;
+ RECT 1382.620000 1444.400000 1383.720000 1444.880000 ;
+ RECT 1382.620000 1438.960000 1383.720000 1439.440000 ;
+ RECT 1382.620000 1433.520000 1383.720000 1434.000000 ;
+ RECT 1382.620000 1428.080000 1383.720000 1428.560000 ;
+ RECT 1382.620000 1422.640000 1383.720000 1423.120000 ;
+ RECT 1382.620000 1400.880000 1383.720000 1401.360000 ;
+ RECT 1382.620000 1406.320000 1383.720000 1406.800000 ;
+ RECT 1382.620000 1411.760000 1383.720000 1412.240000 ;
+ RECT 1382.620000 1417.200000 1383.720000 1417.680000 ;
+ RECT 1427.620000 1395.440000 1428.720000 1395.920000 ;
+ RECT 1427.620000 1390.000000 1428.720000 1390.480000 ;
+ RECT 1436.930000 1395.440000 1437.930000 1395.920000 ;
+ RECT 1436.930000 1390.000000 1437.930000 1390.480000 ;
+ RECT 1427.620000 1379.120000 1428.720000 1379.600000 ;
+ RECT 1427.620000 1373.680000 1428.720000 1374.160000 ;
+ RECT 1436.930000 1379.120000 1437.930000 1379.600000 ;
+ RECT 1436.930000 1373.680000 1437.930000 1374.160000 ;
+ RECT 1427.620000 1384.560000 1428.720000 1385.040000 ;
+ RECT 1436.930000 1384.560000 1437.930000 1385.040000 ;
+ RECT 1436.930000 1362.800000 1437.930000 1363.280000 ;
+ RECT 1436.930000 1368.240000 1437.930000 1368.720000 ;
+ RECT 1427.620000 1368.240000 1428.720000 1368.720000 ;
+ RECT 1427.620000 1362.800000 1428.720000 1363.280000 ;
+ RECT 1427.620000 1357.360000 1428.720000 1357.840000 ;
+ RECT 1427.620000 1351.920000 1428.720000 1352.400000 ;
+ RECT 1436.930000 1357.360000 1437.930000 1357.840000 ;
+ RECT 1436.930000 1351.920000 1437.930000 1352.400000 ;
+ RECT 1382.620000 1395.440000 1383.720000 1395.920000 ;
+ RECT 1382.620000 1390.000000 1383.720000 1390.480000 ;
+ RECT 1382.620000 1384.560000 1383.720000 1385.040000 ;
+ RECT 1382.620000 1379.120000 1383.720000 1379.600000 ;
+ RECT 1382.620000 1373.680000 1383.720000 1374.160000 ;
+ RECT 1382.620000 1368.240000 1383.720000 1368.720000 ;
+ RECT 1382.620000 1362.800000 1383.720000 1363.280000 ;
+ RECT 1382.620000 1357.360000 1383.720000 1357.840000 ;
+ RECT 1382.620000 1351.920000 1383.720000 1352.400000 ;
+ RECT 1337.620000 1444.400000 1338.720000 1444.880000 ;
+ RECT 1337.620000 1438.960000 1338.720000 1439.440000 ;
+ RECT 1337.620000 1433.520000 1338.720000 1434.000000 ;
+ RECT 1337.620000 1428.080000 1338.720000 1428.560000 ;
+ RECT 1337.620000 1422.640000 1338.720000 1423.120000 ;
+ RECT 1292.620000 1444.400000 1293.720000 1444.880000 ;
+ RECT 1292.620000 1438.960000 1293.720000 1439.440000 ;
+ RECT 1292.620000 1433.520000 1293.720000 1434.000000 ;
+ RECT 1292.620000 1428.080000 1293.720000 1428.560000 ;
+ RECT 1292.620000 1422.640000 1293.720000 1423.120000 ;
+ RECT 1337.620000 1417.200000 1338.720000 1417.680000 ;
+ RECT 1337.620000 1411.760000 1338.720000 1412.240000 ;
+ RECT 1337.620000 1406.320000 1338.720000 1406.800000 ;
+ RECT 1337.620000 1400.880000 1338.720000 1401.360000 ;
+ RECT 1292.620000 1411.760000 1293.720000 1412.240000 ;
+ RECT 1292.620000 1406.320000 1293.720000 1406.800000 ;
+ RECT 1292.620000 1400.880000 1293.720000 1401.360000 ;
+ RECT 1292.620000 1417.200000 1293.720000 1417.680000 ;
+ RECT 1247.620000 1444.400000 1248.720000 1444.880000 ;
+ RECT 1243.490000 1444.400000 1244.490000 1444.880000 ;
+ RECT 1247.620000 1438.960000 1248.720000 1439.440000 ;
+ RECT 1243.490000 1438.960000 1244.490000 1439.440000 ;
+ RECT 1247.620000 1433.520000 1248.720000 1434.000000 ;
+ RECT 1243.490000 1433.520000 1244.490000 1434.000000 ;
+ RECT 1247.620000 1422.640000 1248.720000 1423.120000 ;
+ RECT 1243.490000 1422.640000 1244.490000 1423.120000 ;
+ RECT 1243.490000 1428.080000 1244.490000 1428.560000 ;
+ RECT 1247.620000 1428.080000 1248.720000 1428.560000 ;
+ RECT 1247.620000 1417.200000 1248.720000 1417.680000 ;
+ RECT 1243.490000 1417.200000 1244.490000 1417.680000 ;
+ RECT 1247.620000 1411.760000 1248.720000 1412.240000 ;
+ RECT 1243.490000 1411.760000 1244.490000 1412.240000 ;
+ RECT 1247.620000 1406.320000 1248.720000 1406.800000 ;
+ RECT 1243.490000 1406.320000 1244.490000 1406.800000 ;
+ RECT 1247.620000 1400.880000 1248.720000 1401.360000 ;
+ RECT 1243.490000 1400.880000 1244.490000 1401.360000 ;
+ RECT 1337.620000 1395.440000 1338.720000 1395.920000 ;
+ RECT 1337.620000 1390.000000 1338.720000 1390.480000 ;
+ RECT 1337.620000 1384.560000 1338.720000 1385.040000 ;
+ RECT 1337.620000 1379.120000 1338.720000 1379.600000 ;
+ RECT 1337.620000 1373.680000 1338.720000 1374.160000 ;
+ RECT 1292.620000 1395.440000 1293.720000 1395.920000 ;
+ RECT 1292.620000 1390.000000 1293.720000 1390.480000 ;
+ RECT 1292.620000 1384.560000 1293.720000 1385.040000 ;
+ RECT 1292.620000 1379.120000 1293.720000 1379.600000 ;
+ RECT 1292.620000 1373.680000 1293.720000 1374.160000 ;
+ RECT 1337.620000 1351.920000 1338.720000 1352.400000 ;
+ RECT 1337.620000 1357.360000 1338.720000 1357.840000 ;
+ RECT 1337.620000 1362.800000 1338.720000 1363.280000 ;
+ RECT 1337.620000 1368.240000 1338.720000 1368.720000 ;
+ RECT 1292.620000 1351.920000 1293.720000 1352.400000 ;
+ RECT 1292.620000 1357.360000 1293.720000 1357.840000 ;
+ RECT 1292.620000 1362.800000 1293.720000 1363.280000 ;
+ RECT 1292.620000 1368.240000 1293.720000 1368.720000 ;
+ RECT 1247.620000 1395.440000 1248.720000 1395.920000 ;
+ RECT 1243.490000 1395.440000 1244.490000 1395.920000 ;
+ RECT 1247.620000 1390.000000 1248.720000 1390.480000 ;
+ RECT 1243.490000 1390.000000 1244.490000 1390.480000 ;
+ RECT 1247.620000 1379.120000 1248.720000 1379.600000 ;
+ RECT 1243.490000 1379.120000 1244.490000 1379.600000 ;
+ RECT 1247.620000 1373.680000 1248.720000 1374.160000 ;
+ RECT 1243.490000 1373.680000 1244.490000 1374.160000 ;
+ RECT 1247.620000 1384.560000 1248.720000 1385.040000 ;
+ RECT 1243.490000 1384.560000 1244.490000 1385.040000 ;
+ RECT 1247.620000 1368.240000 1248.720000 1368.720000 ;
+ RECT 1243.490000 1368.240000 1244.490000 1368.720000 ;
+ RECT 1247.620000 1362.800000 1248.720000 1363.280000 ;
+ RECT 1243.490000 1362.800000 1244.490000 1363.280000 ;
+ RECT 1247.620000 1357.360000 1248.720000 1357.840000 ;
+ RECT 1247.620000 1351.920000 1248.720000 1352.400000 ;
+ RECT 1243.490000 1357.360000 1244.490000 1357.840000 ;
+ RECT 1243.490000 1351.920000 1244.490000 1352.400000 ;
+ RECT 1240.660000 1542.280000 1440.760000 1543.280000 ;
+ RECT 1240.660000 1349.910000 1440.760000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 1347.060000 1244.490000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 1546.320000 1244.490000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 1347.060000 1437.930000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 1546.320000 1437.930000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1349.910000 1241.660000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1349.910000 1440.760000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1542.280000 1241.660000 1543.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1542.280000 1440.760000 1543.280000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 1149.650000 1428.720000 1343.020000 ;
+ RECT 1382.620000 1149.650000 1383.720000 1343.020000 ;
+ RECT 1436.930000 1146.800000 1437.930000 1347.060000 ;
+ RECT 1337.620000 1149.650000 1338.720000 1343.020000 ;
+ RECT 1292.620000 1149.650000 1293.720000 1343.020000 ;
+ RECT 1247.620000 1149.650000 1248.720000 1343.020000 ;
+ RECT 1243.490000 1146.800000 1244.490000 1347.060000 ;
+ LAYER met3 ;
+ RECT 1427.620000 1336.620000 1428.720000 1337.100000 ;
+ RECT 1436.930000 1336.620000 1437.930000 1337.100000 ;
+ RECT 1436.930000 1325.740000 1437.930000 1326.220000 ;
+ RECT 1436.930000 1331.180000 1437.930000 1331.660000 ;
+ RECT 1427.620000 1331.180000 1428.720000 1331.660000 ;
+ RECT 1427.620000 1325.740000 1428.720000 1326.220000 ;
+ RECT 1427.620000 1320.300000 1428.720000 1320.780000 ;
+ RECT 1427.620000 1314.860000 1428.720000 1315.340000 ;
+ RECT 1436.930000 1320.300000 1437.930000 1320.780000 ;
+ RECT 1436.930000 1314.860000 1437.930000 1315.340000 ;
+ RECT 1427.620000 1298.540000 1428.720000 1299.020000 ;
+ RECT 1427.620000 1303.980000 1428.720000 1304.460000 ;
+ RECT 1436.930000 1303.980000 1437.930000 1304.460000 ;
+ RECT 1436.930000 1298.540000 1437.930000 1299.020000 ;
+ RECT 1427.620000 1309.420000 1428.720000 1309.900000 ;
+ RECT 1436.930000 1309.420000 1437.930000 1309.900000 ;
+ RECT 1382.620000 1336.620000 1383.720000 1337.100000 ;
+ RECT 1382.620000 1331.180000 1383.720000 1331.660000 ;
+ RECT 1382.620000 1325.740000 1383.720000 1326.220000 ;
+ RECT 1382.620000 1320.300000 1383.720000 1320.780000 ;
+ RECT 1382.620000 1298.540000 1383.720000 1299.020000 ;
+ RECT 1382.620000 1303.980000 1383.720000 1304.460000 ;
+ RECT 1382.620000 1309.420000 1383.720000 1309.900000 ;
+ RECT 1382.620000 1314.860000 1383.720000 1315.340000 ;
+ RECT 1436.930000 1287.660000 1437.930000 1288.140000 ;
+ RECT 1436.930000 1293.100000 1437.930000 1293.580000 ;
+ RECT 1427.620000 1293.100000 1428.720000 1293.580000 ;
+ RECT 1427.620000 1287.660000 1428.720000 1288.140000 ;
+ RECT 1427.620000 1282.220000 1428.720000 1282.700000 ;
+ RECT 1427.620000 1276.780000 1428.720000 1277.260000 ;
+ RECT 1436.930000 1282.220000 1437.930000 1282.700000 ;
+ RECT 1436.930000 1276.780000 1437.930000 1277.260000 ;
+ RECT 1436.930000 1260.460000 1437.930000 1260.940000 ;
+ RECT 1436.930000 1265.900000 1437.930000 1266.380000 ;
+ RECT 1436.930000 1271.340000 1437.930000 1271.820000 ;
+ RECT 1427.620000 1265.900000 1428.720000 1266.380000 ;
+ RECT 1427.620000 1260.460000 1428.720000 1260.940000 ;
+ RECT 1427.620000 1271.340000 1428.720000 1271.820000 ;
+ RECT 1427.620000 1255.020000 1428.720000 1255.500000 ;
+ RECT 1427.620000 1249.580000 1428.720000 1250.060000 ;
+ RECT 1436.930000 1255.020000 1437.930000 1255.500000 ;
+ RECT 1436.930000 1249.580000 1437.930000 1250.060000 ;
+ RECT 1382.620000 1293.100000 1383.720000 1293.580000 ;
+ RECT 1382.620000 1287.660000 1383.720000 1288.140000 ;
+ RECT 1382.620000 1282.220000 1383.720000 1282.700000 ;
+ RECT 1382.620000 1276.780000 1383.720000 1277.260000 ;
+ RECT 1382.620000 1265.900000 1383.720000 1266.380000 ;
+ RECT 1382.620000 1260.460000 1383.720000 1260.940000 ;
+ RECT 1382.620000 1255.020000 1383.720000 1255.500000 ;
+ RECT 1382.620000 1249.580000 1383.720000 1250.060000 ;
+ RECT 1382.620000 1271.340000 1383.720000 1271.820000 ;
+ RECT 1337.620000 1336.620000 1338.720000 1337.100000 ;
+ RECT 1337.620000 1331.180000 1338.720000 1331.660000 ;
+ RECT 1337.620000 1325.740000 1338.720000 1326.220000 ;
+ RECT 1292.620000 1336.620000 1293.720000 1337.100000 ;
+ RECT 1292.620000 1331.180000 1293.720000 1331.660000 ;
+ RECT 1292.620000 1325.740000 1293.720000 1326.220000 ;
+ RECT 1337.620000 1309.420000 1338.720000 1309.900000 ;
+ RECT 1337.620000 1303.980000 1338.720000 1304.460000 ;
+ RECT 1337.620000 1298.540000 1338.720000 1299.020000 ;
+ RECT 1337.620000 1314.860000 1338.720000 1315.340000 ;
+ RECT 1337.620000 1320.300000 1338.720000 1320.780000 ;
+ RECT 1292.620000 1320.300000 1293.720000 1320.780000 ;
+ RECT 1292.620000 1309.420000 1293.720000 1309.900000 ;
+ RECT 1292.620000 1303.980000 1293.720000 1304.460000 ;
+ RECT 1292.620000 1298.540000 1293.720000 1299.020000 ;
+ RECT 1292.620000 1314.860000 1293.720000 1315.340000 ;
+ RECT 1247.620000 1336.620000 1248.720000 1337.100000 ;
+ RECT 1243.490000 1336.620000 1244.490000 1337.100000 ;
+ RECT 1243.490000 1331.180000 1244.490000 1331.660000 ;
+ RECT 1247.620000 1331.180000 1248.720000 1331.660000 ;
+ RECT 1247.620000 1325.740000 1248.720000 1326.220000 ;
+ RECT 1243.490000 1325.740000 1244.490000 1326.220000 ;
+ RECT 1247.620000 1320.300000 1248.720000 1320.780000 ;
+ RECT 1243.490000 1320.300000 1244.490000 1320.780000 ;
+ RECT 1247.620000 1314.860000 1248.720000 1315.340000 ;
+ RECT 1243.490000 1314.860000 1244.490000 1315.340000 ;
+ RECT 1247.620000 1303.980000 1248.720000 1304.460000 ;
+ RECT 1243.490000 1303.980000 1244.490000 1304.460000 ;
+ RECT 1247.620000 1298.540000 1248.720000 1299.020000 ;
+ RECT 1243.490000 1298.540000 1244.490000 1299.020000 ;
+ RECT 1247.620000 1309.420000 1248.720000 1309.900000 ;
+ RECT 1243.490000 1309.420000 1244.490000 1309.900000 ;
+ RECT 1337.620000 1293.100000 1338.720000 1293.580000 ;
+ RECT 1337.620000 1287.660000 1338.720000 1288.140000 ;
+ RECT 1337.620000 1282.220000 1338.720000 1282.700000 ;
+ RECT 1337.620000 1276.780000 1338.720000 1277.260000 ;
+ RECT 1292.620000 1293.100000 1293.720000 1293.580000 ;
+ RECT 1292.620000 1287.660000 1293.720000 1288.140000 ;
+ RECT 1292.620000 1282.220000 1293.720000 1282.700000 ;
+ RECT 1292.620000 1276.780000 1293.720000 1277.260000 ;
+ RECT 1337.620000 1265.900000 1338.720000 1266.380000 ;
+ RECT 1337.620000 1249.580000 1338.720000 1250.060000 ;
+ RECT 1337.620000 1255.020000 1338.720000 1255.500000 ;
+ RECT 1337.620000 1260.460000 1338.720000 1260.940000 ;
+ RECT 1337.620000 1271.340000 1338.720000 1271.820000 ;
+ RECT 1292.620000 1249.580000 1293.720000 1250.060000 ;
+ RECT 1292.620000 1255.020000 1293.720000 1255.500000 ;
+ RECT 1292.620000 1260.460000 1293.720000 1260.940000 ;
+ RECT 1292.620000 1265.900000 1293.720000 1266.380000 ;
+ RECT 1292.620000 1271.340000 1293.720000 1271.820000 ;
+ RECT 1247.620000 1293.100000 1248.720000 1293.580000 ;
+ RECT 1243.490000 1293.100000 1244.490000 1293.580000 ;
+ RECT 1247.620000 1287.660000 1248.720000 1288.140000 ;
+ RECT 1243.490000 1287.660000 1244.490000 1288.140000 ;
+ RECT 1247.620000 1282.220000 1248.720000 1282.700000 ;
+ RECT 1243.490000 1282.220000 1244.490000 1282.700000 ;
+ RECT 1247.620000 1276.780000 1248.720000 1277.260000 ;
+ RECT 1243.490000 1276.780000 1244.490000 1277.260000 ;
+ RECT 1247.620000 1271.340000 1248.720000 1271.820000 ;
+ RECT 1247.620000 1265.900000 1248.720000 1266.380000 ;
+ RECT 1243.490000 1271.340000 1244.490000 1271.820000 ;
+ RECT 1243.490000 1265.900000 1244.490000 1266.380000 ;
+ RECT 1247.620000 1260.460000 1248.720000 1260.940000 ;
+ RECT 1243.490000 1260.460000 1244.490000 1260.940000 ;
+ RECT 1247.620000 1255.020000 1248.720000 1255.500000 ;
+ RECT 1243.490000 1255.020000 1244.490000 1255.500000 ;
+ RECT 1247.620000 1249.580000 1248.720000 1250.060000 ;
+ RECT 1243.490000 1249.580000 1244.490000 1250.060000 ;
+ RECT 1427.620000 1244.140000 1428.720000 1244.620000 ;
+ RECT 1427.620000 1238.700000 1428.720000 1239.180000 ;
+ RECT 1436.930000 1244.140000 1437.930000 1244.620000 ;
+ RECT 1436.930000 1238.700000 1437.930000 1239.180000 ;
+ RECT 1436.930000 1222.380000 1437.930000 1222.860000 ;
+ RECT 1436.930000 1227.820000 1437.930000 1228.300000 ;
+ RECT 1436.930000 1233.260000 1437.930000 1233.740000 ;
+ RECT 1427.620000 1233.260000 1428.720000 1233.740000 ;
+ RECT 1427.620000 1227.820000 1428.720000 1228.300000 ;
+ RECT 1427.620000 1222.380000 1428.720000 1222.860000 ;
+ RECT 1427.620000 1211.500000 1428.720000 1211.980000 ;
+ RECT 1427.620000 1216.940000 1428.720000 1217.420000 ;
+ RECT 1436.930000 1216.940000 1437.930000 1217.420000 ;
+ RECT 1436.930000 1211.500000 1437.930000 1211.980000 ;
+ RECT 1436.930000 1200.620000 1437.930000 1201.100000 ;
+ RECT 1436.930000 1206.060000 1437.930000 1206.540000 ;
+ RECT 1427.620000 1200.620000 1428.720000 1201.100000 ;
+ RECT 1427.620000 1206.060000 1428.720000 1206.540000 ;
+ RECT 1382.620000 1244.140000 1383.720000 1244.620000 ;
+ RECT 1382.620000 1238.700000 1383.720000 1239.180000 ;
+ RECT 1382.620000 1233.260000 1383.720000 1233.740000 ;
+ RECT 1382.620000 1227.820000 1383.720000 1228.300000 ;
+ RECT 1382.620000 1222.380000 1383.720000 1222.860000 ;
+ RECT 1382.620000 1200.620000 1383.720000 1201.100000 ;
+ RECT 1382.620000 1206.060000 1383.720000 1206.540000 ;
+ RECT 1382.620000 1211.500000 1383.720000 1211.980000 ;
+ RECT 1382.620000 1216.940000 1383.720000 1217.420000 ;
+ RECT 1427.620000 1195.180000 1428.720000 1195.660000 ;
+ RECT 1427.620000 1189.740000 1428.720000 1190.220000 ;
+ RECT 1436.930000 1195.180000 1437.930000 1195.660000 ;
+ RECT 1436.930000 1189.740000 1437.930000 1190.220000 ;
+ RECT 1427.620000 1178.860000 1428.720000 1179.340000 ;
+ RECT 1427.620000 1173.420000 1428.720000 1173.900000 ;
+ RECT 1436.930000 1178.860000 1437.930000 1179.340000 ;
+ RECT 1436.930000 1173.420000 1437.930000 1173.900000 ;
+ RECT 1427.620000 1184.300000 1428.720000 1184.780000 ;
+ RECT 1436.930000 1184.300000 1437.930000 1184.780000 ;
+ RECT 1436.930000 1162.540000 1437.930000 1163.020000 ;
+ RECT 1436.930000 1167.980000 1437.930000 1168.460000 ;
+ RECT 1427.620000 1167.980000 1428.720000 1168.460000 ;
+ RECT 1427.620000 1162.540000 1428.720000 1163.020000 ;
+ RECT 1427.620000 1157.100000 1428.720000 1157.580000 ;
+ RECT 1427.620000 1151.660000 1428.720000 1152.140000 ;
+ RECT 1436.930000 1157.100000 1437.930000 1157.580000 ;
+ RECT 1436.930000 1151.660000 1437.930000 1152.140000 ;
+ RECT 1382.620000 1195.180000 1383.720000 1195.660000 ;
+ RECT 1382.620000 1189.740000 1383.720000 1190.220000 ;
+ RECT 1382.620000 1184.300000 1383.720000 1184.780000 ;
+ RECT 1382.620000 1178.860000 1383.720000 1179.340000 ;
+ RECT 1382.620000 1173.420000 1383.720000 1173.900000 ;
+ RECT 1382.620000 1167.980000 1383.720000 1168.460000 ;
+ RECT 1382.620000 1162.540000 1383.720000 1163.020000 ;
+ RECT 1382.620000 1157.100000 1383.720000 1157.580000 ;
+ RECT 1382.620000 1151.660000 1383.720000 1152.140000 ;
+ RECT 1337.620000 1244.140000 1338.720000 1244.620000 ;
+ RECT 1337.620000 1238.700000 1338.720000 1239.180000 ;
+ RECT 1337.620000 1233.260000 1338.720000 1233.740000 ;
+ RECT 1337.620000 1227.820000 1338.720000 1228.300000 ;
+ RECT 1337.620000 1222.380000 1338.720000 1222.860000 ;
+ RECT 1292.620000 1244.140000 1293.720000 1244.620000 ;
+ RECT 1292.620000 1238.700000 1293.720000 1239.180000 ;
+ RECT 1292.620000 1233.260000 1293.720000 1233.740000 ;
+ RECT 1292.620000 1227.820000 1293.720000 1228.300000 ;
+ RECT 1292.620000 1222.380000 1293.720000 1222.860000 ;
+ RECT 1337.620000 1216.940000 1338.720000 1217.420000 ;
+ RECT 1337.620000 1211.500000 1338.720000 1211.980000 ;
+ RECT 1337.620000 1206.060000 1338.720000 1206.540000 ;
+ RECT 1337.620000 1200.620000 1338.720000 1201.100000 ;
+ RECT 1292.620000 1211.500000 1293.720000 1211.980000 ;
+ RECT 1292.620000 1206.060000 1293.720000 1206.540000 ;
+ RECT 1292.620000 1200.620000 1293.720000 1201.100000 ;
+ RECT 1292.620000 1216.940000 1293.720000 1217.420000 ;
+ RECT 1247.620000 1244.140000 1248.720000 1244.620000 ;
+ RECT 1243.490000 1244.140000 1244.490000 1244.620000 ;
+ RECT 1247.620000 1238.700000 1248.720000 1239.180000 ;
+ RECT 1243.490000 1238.700000 1244.490000 1239.180000 ;
+ RECT 1247.620000 1233.260000 1248.720000 1233.740000 ;
+ RECT 1243.490000 1233.260000 1244.490000 1233.740000 ;
+ RECT 1247.620000 1222.380000 1248.720000 1222.860000 ;
+ RECT 1243.490000 1222.380000 1244.490000 1222.860000 ;
+ RECT 1243.490000 1227.820000 1244.490000 1228.300000 ;
+ RECT 1247.620000 1227.820000 1248.720000 1228.300000 ;
+ RECT 1247.620000 1216.940000 1248.720000 1217.420000 ;
+ RECT 1243.490000 1216.940000 1244.490000 1217.420000 ;
+ RECT 1247.620000 1211.500000 1248.720000 1211.980000 ;
+ RECT 1243.490000 1211.500000 1244.490000 1211.980000 ;
+ RECT 1247.620000 1206.060000 1248.720000 1206.540000 ;
+ RECT 1243.490000 1206.060000 1244.490000 1206.540000 ;
+ RECT 1247.620000 1200.620000 1248.720000 1201.100000 ;
+ RECT 1243.490000 1200.620000 1244.490000 1201.100000 ;
+ RECT 1337.620000 1195.180000 1338.720000 1195.660000 ;
+ RECT 1337.620000 1189.740000 1338.720000 1190.220000 ;
+ RECT 1337.620000 1184.300000 1338.720000 1184.780000 ;
+ RECT 1337.620000 1178.860000 1338.720000 1179.340000 ;
+ RECT 1337.620000 1173.420000 1338.720000 1173.900000 ;
+ RECT 1292.620000 1195.180000 1293.720000 1195.660000 ;
+ RECT 1292.620000 1189.740000 1293.720000 1190.220000 ;
+ RECT 1292.620000 1184.300000 1293.720000 1184.780000 ;
+ RECT 1292.620000 1178.860000 1293.720000 1179.340000 ;
+ RECT 1292.620000 1173.420000 1293.720000 1173.900000 ;
+ RECT 1337.620000 1151.660000 1338.720000 1152.140000 ;
+ RECT 1337.620000 1157.100000 1338.720000 1157.580000 ;
+ RECT 1337.620000 1162.540000 1338.720000 1163.020000 ;
+ RECT 1337.620000 1167.980000 1338.720000 1168.460000 ;
+ RECT 1292.620000 1151.660000 1293.720000 1152.140000 ;
+ RECT 1292.620000 1157.100000 1293.720000 1157.580000 ;
+ RECT 1292.620000 1162.540000 1293.720000 1163.020000 ;
+ RECT 1292.620000 1167.980000 1293.720000 1168.460000 ;
+ RECT 1247.620000 1195.180000 1248.720000 1195.660000 ;
+ RECT 1243.490000 1195.180000 1244.490000 1195.660000 ;
+ RECT 1247.620000 1189.740000 1248.720000 1190.220000 ;
+ RECT 1243.490000 1189.740000 1244.490000 1190.220000 ;
+ RECT 1247.620000 1178.860000 1248.720000 1179.340000 ;
+ RECT 1243.490000 1178.860000 1244.490000 1179.340000 ;
+ RECT 1247.620000 1173.420000 1248.720000 1173.900000 ;
+ RECT 1243.490000 1173.420000 1244.490000 1173.900000 ;
+ RECT 1247.620000 1184.300000 1248.720000 1184.780000 ;
+ RECT 1243.490000 1184.300000 1244.490000 1184.780000 ;
+ RECT 1247.620000 1167.980000 1248.720000 1168.460000 ;
+ RECT 1243.490000 1167.980000 1244.490000 1168.460000 ;
+ RECT 1247.620000 1162.540000 1248.720000 1163.020000 ;
+ RECT 1243.490000 1162.540000 1244.490000 1163.020000 ;
+ RECT 1247.620000 1157.100000 1248.720000 1157.580000 ;
+ RECT 1247.620000 1151.660000 1248.720000 1152.140000 ;
+ RECT 1243.490000 1157.100000 1244.490000 1157.580000 ;
+ RECT 1243.490000 1151.660000 1244.490000 1152.140000 ;
+ RECT 1240.660000 1342.020000 1440.760000 1343.020000 ;
+ RECT 1240.660000 1149.650000 1440.760000 1150.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 1146.800000 1244.490000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 1346.060000 1244.490000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 1146.800000 1437.930000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 1346.060000 1437.930000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1149.650000 1241.660000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1149.650000 1440.760000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1342.020000 1241.660000 1343.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1342.020000 1440.760000 1343.020000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 949.390000 1428.720000 1142.760000 ;
+ RECT 1382.620000 949.390000 1383.720000 1142.760000 ;
+ RECT 1436.930000 946.540000 1437.930000 1146.800000 ;
+ RECT 1337.620000 949.390000 1338.720000 1142.760000 ;
+ RECT 1292.620000 949.390000 1293.720000 1142.760000 ;
+ RECT 1247.620000 949.390000 1248.720000 1142.760000 ;
+ RECT 1243.490000 946.540000 1244.490000 1146.800000 ;
+ LAYER met3 ;
+ RECT 1427.620000 1136.360000 1428.720000 1136.840000 ;
+ RECT 1436.930000 1136.360000 1437.930000 1136.840000 ;
+ RECT 1436.930000 1125.480000 1437.930000 1125.960000 ;
+ RECT 1436.930000 1130.920000 1437.930000 1131.400000 ;
+ RECT 1427.620000 1130.920000 1428.720000 1131.400000 ;
+ RECT 1427.620000 1125.480000 1428.720000 1125.960000 ;
+ RECT 1427.620000 1120.040000 1428.720000 1120.520000 ;
+ RECT 1427.620000 1114.600000 1428.720000 1115.080000 ;
+ RECT 1436.930000 1120.040000 1437.930000 1120.520000 ;
+ RECT 1436.930000 1114.600000 1437.930000 1115.080000 ;
+ RECT 1427.620000 1098.280000 1428.720000 1098.760000 ;
+ RECT 1427.620000 1103.720000 1428.720000 1104.200000 ;
+ RECT 1436.930000 1103.720000 1437.930000 1104.200000 ;
+ RECT 1436.930000 1098.280000 1437.930000 1098.760000 ;
+ RECT 1427.620000 1109.160000 1428.720000 1109.640000 ;
+ RECT 1436.930000 1109.160000 1437.930000 1109.640000 ;
+ RECT 1382.620000 1136.360000 1383.720000 1136.840000 ;
+ RECT 1382.620000 1130.920000 1383.720000 1131.400000 ;
+ RECT 1382.620000 1125.480000 1383.720000 1125.960000 ;
+ RECT 1382.620000 1120.040000 1383.720000 1120.520000 ;
+ RECT 1382.620000 1098.280000 1383.720000 1098.760000 ;
+ RECT 1382.620000 1103.720000 1383.720000 1104.200000 ;
+ RECT 1382.620000 1109.160000 1383.720000 1109.640000 ;
+ RECT 1382.620000 1114.600000 1383.720000 1115.080000 ;
+ RECT 1436.930000 1087.400000 1437.930000 1087.880000 ;
+ RECT 1436.930000 1092.840000 1437.930000 1093.320000 ;
+ RECT 1427.620000 1092.840000 1428.720000 1093.320000 ;
+ RECT 1427.620000 1087.400000 1428.720000 1087.880000 ;
+ RECT 1427.620000 1081.960000 1428.720000 1082.440000 ;
+ RECT 1427.620000 1076.520000 1428.720000 1077.000000 ;
+ RECT 1436.930000 1081.960000 1437.930000 1082.440000 ;
+ RECT 1436.930000 1076.520000 1437.930000 1077.000000 ;
+ RECT 1436.930000 1060.200000 1437.930000 1060.680000 ;
+ RECT 1436.930000 1065.640000 1437.930000 1066.120000 ;
+ RECT 1436.930000 1071.080000 1437.930000 1071.560000 ;
+ RECT 1427.620000 1065.640000 1428.720000 1066.120000 ;
+ RECT 1427.620000 1060.200000 1428.720000 1060.680000 ;
+ RECT 1427.620000 1071.080000 1428.720000 1071.560000 ;
+ RECT 1427.620000 1054.760000 1428.720000 1055.240000 ;
+ RECT 1427.620000 1049.320000 1428.720000 1049.800000 ;
+ RECT 1436.930000 1054.760000 1437.930000 1055.240000 ;
+ RECT 1436.930000 1049.320000 1437.930000 1049.800000 ;
+ RECT 1382.620000 1092.840000 1383.720000 1093.320000 ;
+ RECT 1382.620000 1087.400000 1383.720000 1087.880000 ;
+ RECT 1382.620000 1081.960000 1383.720000 1082.440000 ;
+ RECT 1382.620000 1076.520000 1383.720000 1077.000000 ;
+ RECT 1382.620000 1065.640000 1383.720000 1066.120000 ;
+ RECT 1382.620000 1060.200000 1383.720000 1060.680000 ;
+ RECT 1382.620000 1054.760000 1383.720000 1055.240000 ;
+ RECT 1382.620000 1049.320000 1383.720000 1049.800000 ;
+ RECT 1382.620000 1071.080000 1383.720000 1071.560000 ;
+ RECT 1337.620000 1136.360000 1338.720000 1136.840000 ;
+ RECT 1337.620000 1130.920000 1338.720000 1131.400000 ;
+ RECT 1337.620000 1125.480000 1338.720000 1125.960000 ;
+ RECT 1292.620000 1136.360000 1293.720000 1136.840000 ;
+ RECT 1292.620000 1130.920000 1293.720000 1131.400000 ;
+ RECT 1292.620000 1125.480000 1293.720000 1125.960000 ;
+ RECT 1337.620000 1109.160000 1338.720000 1109.640000 ;
+ RECT 1337.620000 1103.720000 1338.720000 1104.200000 ;
+ RECT 1337.620000 1098.280000 1338.720000 1098.760000 ;
+ RECT 1337.620000 1114.600000 1338.720000 1115.080000 ;
+ RECT 1337.620000 1120.040000 1338.720000 1120.520000 ;
+ RECT 1292.620000 1120.040000 1293.720000 1120.520000 ;
+ RECT 1292.620000 1109.160000 1293.720000 1109.640000 ;
+ RECT 1292.620000 1103.720000 1293.720000 1104.200000 ;
+ RECT 1292.620000 1098.280000 1293.720000 1098.760000 ;
+ RECT 1292.620000 1114.600000 1293.720000 1115.080000 ;
+ RECT 1247.620000 1136.360000 1248.720000 1136.840000 ;
+ RECT 1243.490000 1136.360000 1244.490000 1136.840000 ;
+ RECT 1243.490000 1130.920000 1244.490000 1131.400000 ;
+ RECT 1247.620000 1130.920000 1248.720000 1131.400000 ;
+ RECT 1247.620000 1125.480000 1248.720000 1125.960000 ;
+ RECT 1243.490000 1125.480000 1244.490000 1125.960000 ;
+ RECT 1247.620000 1120.040000 1248.720000 1120.520000 ;
+ RECT 1243.490000 1120.040000 1244.490000 1120.520000 ;
+ RECT 1247.620000 1114.600000 1248.720000 1115.080000 ;
+ RECT 1243.490000 1114.600000 1244.490000 1115.080000 ;
+ RECT 1247.620000 1103.720000 1248.720000 1104.200000 ;
+ RECT 1243.490000 1103.720000 1244.490000 1104.200000 ;
+ RECT 1247.620000 1098.280000 1248.720000 1098.760000 ;
+ RECT 1243.490000 1098.280000 1244.490000 1098.760000 ;
+ RECT 1247.620000 1109.160000 1248.720000 1109.640000 ;
+ RECT 1243.490000 1109.160000 1244.490000 1109.640000 ;
+ RECT 1337.620000 1092.840000 1338.720000 1093.320000 ;
+ RECT 1337.620000 1087.400000 1338.720000 1087.880000 ;
+ RECT 1337.620000 1081.960000 1338.720000 1082.440000 ;
+ RECT 1337.620000 1076.520000 1338.720000 1077.000000 ;
+ RECT 1292.620000 1092.840000 1293.720000 1093.320000 ;
+ RECT 1292.620000 1087.400000 1293.720000 1087.880000 ;
+ RECT 1292.620000 1081.960000 1293.720000 1082.440000 ;
+ RECT 1292.620000 1076.520000 1293.720000 1077.000000 ;
+ RECT 1337.620000 1065.640000 1338.720000 1066.120000 ;
+ RECT 1337.620000 1049.320000 1338.720000 1049.800000 ;
+ RECT 1337.620000 1054.760000 1338.720000 1055.240000 ;
+ RECT 1337.620000 1060.200000 1338.720000 1060.680000 ;
+ RECT 1337.620000 1071.080000 1338.720000 1071.560000 ;
+ RECT 1292.620000 1049.320000 1293.720000 1049.800000 ;
+ RECT 1292.620000 1054.760000 1293.720000 1055.240000 ;
+ RECT 1292.620000 1060.200000 1293.720000 1060.680000 ;
+ RECT 1292.620000 1065.640000 1293.720000 1066.120000 ;
+ RECT 1292.620000 1071.080000 1293.720000 1071.560000 ;
+ RECT 1247.620000 1092.840000 1248.720000 1093.320000 ;
+ RECT 1243.490000 1092.840000 1244.490000 1093.320000 ;
+ RECT 1247.620000 1087.400000 1248.720000 1087.880000 ;
+ RECT 1243.490000 1087.400000 1244.490000 1087.880000 ;
+ RECT 1247.620000 1081.960000 1248.720000 1082.440000 ;
+ RECT 1243.490000 1081.960000 1244.490000 1082.440000 ;
+ RECT 1247.620000 1076.520000 1248.720000 1077.000000 ;
+ RECT 1243.490000 1076.520000 1244.490000 1077.000000 ;
+ RECT 1247.620000 1071.080000 1248.720000 1071.560000 ;
+ RECT 1247.620000 1065.640000 1248.720000 1066.120000 ;
+ RECT 1243.490000 1071.080000 1244.490000 1071.560000 ;
+ RECT 1243.490000 1065.640000 1244.490000 1066.120000 ;
+ RECT 1247.620000 1060.200000 1248.720000 1060.680000 ;
+ RECT 1243.490000 1060.200000 1244.490000 1060.680000 ;
+ RECT 1247.620000 1054.760000 1248.720000 1055.240000 ;
+ RECT 1243.490000 1054.760000 1244.490000 1055.240000 ;
+ RECT 1247.620000 1049.320000 1248.720000 1049.800000 ;
+ RECT 1243.490000 1049.320000 1244.490000 1049.800000 ;
+ RECT 1427.620000 1043.880000 1428.720000 1044.360000 ;
+ RECT 1427.620000 1038.440000 1428.720000 1038.920000 ;
+ RECT 1436.930000 1043.880000 1437.930000 1044.360000 ;
+ RECT 1436.930000 1038.440000 1437.930000 1038.920000 ;
+ RECT 1436.930000 1022.120000 1437.930000 1022.600000 ;
+ RECT 1436.930000 1027.560000 1437.930000 1028.040000 ;
+ RECT 1436.930000 1033.000000 1437.930000 1033.480000 ;
+ RECT 1427.620000 1033.000000 1428.720000 1033.480000 ;
+ RECT 1427.620000 1027.560000 1428.720000 1028.040000 ;
+ RECT 1427.620000 1022.120000 1428.720000 1022.600000 ;
+ RECT 1427.620000 1011.240000 1428.720000 1011.720000 ;
+ RECT 1427.620000 1016.680000 1428.720000 1017.160000 ;
+ RECT 1436.930000 1016.680000 1437.930000 1017.160000 ;
+ RECT 1436.930000 1011.240000 1437.930000 1011.720000 ;
+ RECT 1436.930000 1000.360000 1437.930000 1000.840000 ;
+ RECT 1436.930000 1005.800000 1437.930000 1006.280000 ;
+ RECT 1427.620000 1000.360000 1428.720000 1000.840000 ;
+ RECT 1427.620000 1005.800000 1428.720000 1006.280000 ;
+ RECT 1382.620000 1043.880000 1383.720000 1044.360000 ;
+ RECT 1382.620000 1038.440000 1383.720000 1038.920000 ;
+ RECT 1382.620000 1033.000000 1383.720000 1033.480000 ;
+ RECT 1382.620000 1027.560000 1383.720000 1028.040000 ;
+ RECT 1382.620000 1022.120000 1383.720000 1022.600000 ;
+ RECT 1382.620000 1000.360000 1383.720000 1000.840000 ;
+ RECT 1382.620000 1005.800000 1383.720000 1006.280000 ;
+ RECT 1382.620000 1011.240000 1383.720000 1011.720000 ;
+ RECT 1382.620000 1016.680000 1383.720000 1017.160000 ;
+ RECT 1427.620000 994.920000 1428.720000 995.400000 ;
+ RECT 1427.620000 989.480000 1428.720000 989.960000 ;
+ RECT 1436.930000 994.920000 1437.930000 995.400000 ;
+ RECT 1436.930000 989.480000 1437.930000 989.960000 ;
+ RECT 1427.620000 978.600000 1428.720000 979.080000 ;
+ RECT 1427.620000 973.160000 1428.720000 973.640000 ;
+ RECT 1436.930000 978.600000 1437.930000 979.080000 ;
+ RECT 1436.930000 973.160000 1437.930000 973.640000 ;
+ RECT 1427.620000 984.040000 1428.720000 984.520000 ;
+ RECT 1436.930000 984.040000 1437.930000 984.520000 ;
+ RECT 1436.930000 962.280000 1437.930000 962.760000 ;
+ RECT 1436.930000 967.720000 1437.930000 968.200000 ;
+ RECT 1427.620000 967.720000 1428.720000 968.200000 ;
+ RECT 1427.620000 962.280000 1428.720000 962.760000 ;
+ RECT 1427.620000 956.840000 1428.720000 957.320000 ;
+ RECT 1427.620000 951.400000 1428.720000 951.880000 ;
+ RECT 1436.930000 956.840000 1437.930000 957.320000 ;
+ RECT 1436.930000 951.400000 1437.930000 951.880000 ;
+ RECT 1382.620000 994.920000 1383.720000 995.400000 ;
+ RECT 1382.620000 989.480000 1383.720000 989.960000 ;
+ RECT 1382.620000 984.040000 1383.720000 984.520000 ;
+ RECT 1382.620000 978.600000 1383.720000 979.080000 ;
+ RECT 1382.620000 973.160000 1383.720000 973.640000 ;
+ RECT 1382.620000 967.720000 1383.720000 968.200000 ;
+ RECT 1382.620000 962.280000 1383.720000 962.760000 ;
+ RECT 1382.620000 956.840000 1383.720000 957.320000 ;
+ RECT 1382.620000 951.400000 1383.720000 951.880000 ;
+ RECT 1337.620000 1043.880000 1338.720000 1044.360000 ;
+ RECT 1337.620000 1038.440000 1338.720000 1038.920000 ;
+ RECT 1337.620000 1033.000000 1338.720000 1033.480000 ;
+ RECT 1337.620000 1027.560000 1338.720000 1028.040000 ;
+ RECT 1337.620000 1022.120000 1338.720000 1022.600000 ;
+ RECT 1292.620000 1043.880000 1293.720000 1044.360000 ;
+ RECT 1292.620000 1038.440000 1293.720000 1038.920000 ;
+ RECT 1292.620000 1033.000000 1293.720000 1033.480000 ;
+ RECT 1292.620000 1027.560000 1293.720000 1028.040000 ;
+ RECT 1292.620000 1022.120000 1293.720000 1022.600000 ;
+ RECT 1337.620000 1016.680000 1338.720000 1017.160000 ;
+ RECT 1337.620000 1011.240000 1338.720000 1011.720000 ;
+ RECT 1337.620000 1005.800000 1338.720000 1006.280000 ;
+ RECT 1337.620000 1000.360000 1338.720000 1000.840000 ;
+ RECT 1292.620000 1011.240000 1293.720000 1011.720000 ;
+ RECT 1292.620000 1005.800000 1293.720000 1006.280000 ;
+ RECT 1292.620000 1000.360000 1293.720000 1000.840000 ;
+ RECT 1292.620000 1016.680000 1293.720000 1017.160000 ;
+ RECT 1247.620000 1043.880000 1248.720000 1044.360000 ;
+ RECT 1243.490000 1043.880000 1244.490000 1044.360000 ;
+ RECT 1247.620000 1038.440000 1248.720000 1038.920000 ;
+ RECT 1243.490000 1038.440000 1244.490000 1038.920000 ;
+ RECT 1247.620000 1033.000000 1248.720000 1033.480000 ;
+ RECT 1243.490000 1033.000000 1244.490000 1033.480000 ;
+ RECT 1247.620000 1022.120000 1248.720000 1022.600000 ;
+ RECT 1243.490000 1022.120000 1244.490000 1022.600000 ;
+ RECT 1243.490000 1027.560000 1244.490000 1028.040000 ;
+ RECT 1247.620000 1027.560000 1248.720000 1028.040000 ;
+ RECT 1247.620000 1016.680000 1248.720000 1017.160000 ;
+ RECT 1243.490000 1016.680000 1244.490000 1017.160000 ;
+ RECT 1247.620000 1011.240000 1248.720000 1011.720000 ;
+ RECT 1243.490000 1011.240000 1244.490000 1011.720000 ;
+ RECT 1247.620000 1005.800000 1248.720000 1006.280000 ;
+ RECT 1243.490000 1005.800000 1244.490000 1006.280000 ;
+ RECT 1247.620000 1000.360000 1248.720000 1000.840000 ;
+ RECT 1243.490000 1000.360000 1244.490000 1000.840000 ;
+ RECT 1337.620000 994.920000 1338.720000 995.400000 ;
+ RECT 1337.620000 989.480000 1338.720000 989.960000 ;
+ RECT 1337.620000 984.040000 1338.720000 984.520000 ;
+ RECT 1337.620000 978.600000 1338.720000 979.080000 ;
+ RECT 1337.620000 973.160000 1338.720000 973.640000 ;
+ RECT 1292.620000 994.920000 1293.720000 995.400000 ;
+ RECT 1292.620000 989.480000 1293.720000 989.960000 ;
+ RECT 1292.620000 984.040000 1293.720000 984.520000 ;
+ RECT 1292.620000 978.600000 1293.720000 979.080000 ;
+ RECT 1292.620000 973.160000 1293.720000 973.640000 ;
+ RECT 1337.620000 951.400000 1338.720000 951.880000 ;
+ RECT 1337.620000 956.840000 1338.720000 957.320000 ;
+ RECT 1337.620000 962.280000 1338.720000 962.760000 ;
+ RECT 1337.620000 967.720000 1338.720000 968.200000 ;
+ RECT 1292.620000 951.400000 1293.720000 951.880000 ;
+ RECT 1292.620000 956.840000 1293.720000 957.320000 ;
+ RECT 1292.620000 962.280000 1293.720000 962.760000 ;
+ RECT 1292.620000 967.720000 1293.720000 968.200000 ;
+ RECT 1247.620000 994.920000 1248.720000 995.400000 ;
+ RECT 1243.490000 994.920000 1244.490000 995.400000 ;
+ RECT 1247.620000 989.480000 1248.720000 989.960000 ;
+ RECT 1243.490000 989.480000 1244.490000 989.960000 ;
+ RECT 1247.620000 978.600000 1248.720000 979.080000 ;
+ RECT 1243.490000 978.600000 1244.490000 979.080000 ;
+ RECT 1247.620000 973.160000 1248.720000 973.640000 ;
+ RECT 1243.490000 973.160000 1244.490000 973.640000 ;
+ RECT 1247.620000 984.040000 1248.720000 984.520000 ;
+ RECT 1243.490000 984.040000 1244.490000 984.520000 ;
+ RECT 1247.620000 967.720000 1248.720000 968.200000 ;
+ RECT 1243.490000 967.720000 1244.490000 968.200000 ;
+ RECT 1247.620000 962.280000 1248.720000 962.760000 ;
+ RECT 1243.490000 962.280000 1244.490000 962.760000 ;
+ RECT 1247.620000 956.840000 1248.720000 957.320000 ;
+ RECT 1247.620000 951.400000 1248.720000 951.880000 ;
+ RECT 1243.490000 956.840000 1244.490000 957.320000 ;
+ RECT 1243.490000 951.400000 1244.490000 951.880000 ;
+ RECT 1240.660000 1141.760000 1440.760000 1142.760000 ;
+ RECT 1240.660000 949.390000 1440.760000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 946.540000 1244.490000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 1145.800000 1244.490000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 946.540000 1437.930000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 1145.800000 1437.930000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 949.390000 1241.660000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 949.390000 1440.760000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1141.760000 1241.660000 1142.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1141.760000 1440.760000 1142.760000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 749.130000 1428.720000 942.500000 ;
+ RECT 1382.620000 749.130000 1383.720000 942.500000 ;
+ RECT 1436.930000 746.280000 1437.930000 946.540000 ;
+ RECT 1337.620000 749.130000 1338.720000 942.500000 ;
+ RECT 1292.620000 749.130000 1293.720000 942.500000 ;
+ RECT 1247.620000 749.130000 1248.720000 942.500000 ;
+ RECT 1243.490000 746.280000 1244.490000 946.540000 ;
+ LAYER met3 ;
+ RECT 1427.620000 936.100000 1428.720000 936.580000 ;
+ RECT 1436.930000 936.100000 1437.930000 936.580000 ;
+ RECT 1436.930000 925.220000 1437.930000 925.700000 ;
+ RECT 1436.930000 930.660000 1437.930000 931.140000 ;
+ RECT 1427.620000 930.660000 1428.720000 931.140000 ;
+ RECT 1427.620000 925.220000 1428.720000 925.700000 ;
+ RECT 1427.620000 919.780000 1428.720000 920.260000 ;
+ RECT 1427.620000 914.340000 1428.720000 914.820000 ;
+ RECT 1436.930000 919.780000 1437.930000 920.260000 ;
+ RECT 1436.930000 914.340000 1437.930000 914.820000 ;
+ RECT 1427.620000 898.020000 1428.720000 898.500000 ;
+ RECT 1427.620000 903.460000 1428.720000 903.940000 ;
+ RECT 1436.930000 903.460000 1437.930000 903.940000 ;
+ RECT 1436.930000 898.020000 1437.930000 898.500000 ;
+ RECT 1427.620000 908.900000 1428.720000 909.380000 ;
+ RECT 1436.930000 908.900000 1437.930000 909.380000 ;
+ RECT 1382.620000 936.100000 1383.720000 936.580000 ;
+ RECT 1382.620000 930.660000 1383.720000 931.140000 ;
+ RECT 1382.620000 925.220000 1383.720000 925.700000 ;
+ RECT 1382.620000 919.780000 1383.720000 920.260000 ;
+ RECT 1382.620000 898.020000 1383.720000 898.500000 ;
+ RECT 1382.620000 903.460000 1383.720000 903.940000 ;
+ RECT 1382.620000 908.900000 1383.720000 909.380000 ;
+ RECT 1382.620000 914.340000 1383.720000 914.820000 ;
+ RECT 1436.930000 887.140000 1437.930000 887.620000 ;
+ RECT 1436.930000 892.580000 1437.930000 893.060000 ;
+ RECT 1427.620000 892.580000 1428.720000 893.060000 ;
+ RECT 1427.620000 887.140000 1428.720000 887.620000 ;
+ RECT 1427.620000 881.700000 1428.720000 882.180000 ;
+ RECT 1427.620000 876.260000 1428.720000 876.740000 ;
+ RECT 1436.930000 881.700000 1437.930000 882.180000 ;
+ RECT 1436.930000 876.260000 1437.930000 876.740000 ;
+ RECT 1436.930000 859.940000 1437.930000 860.420000 ;
+ RECT 1436.930000 865.380000 1437.930000 865.860000 ;
+ RECT 1436.930000 870.820000 1437.930000 871.300000 ;
+ RECT 1427.620000 865.380000 1428.720000 865.860000 ;
+ RECT 1427.620000 859.940000 1428.720000 860.420000 ;
+ RECT 1427.620000 870.820000 1428.720000 871.300000 ;
+ RECT 1427.620000 854.500000 1428.720000 854.980000 ;
+ RECT 1427.620000 849.060000 1428.720000 849.540000 ;
+ RECT 1436.930000 854.500000 1437.930000 854.980000 ;
+ RECT 1436.930000 849.060000 1437.930000 849.540000 ;
+ RECT 1382.620000 892.580000 1383.720000 893.060000 ;
+ RECT 1382.620000 887.140000 1383.720000 887.620000 ;
+ RECT 1382.620000 881.700000 1383.720000 882.180000 ;
+ RECT 1382.620000 876.260000 1383.720000 876.740000 ;
+ RECT 1382.620000 865.380000 1383.720000 865.860000 ;
+ RECT 1382.620000 859.940000 1383.720000 860.420000 ;
+ RECT 1382.620000 854.500000 1383.720000 854.980000 ;
+ RECT 1382.620000 849.060000 1383.720000 849.540000 ;
+ RECT 1382.620000 870.820000 1383.720000 871.300000 ;
+ RECT 1337.620000 936.100000 1338.720000 936.580000 ;
+ RECT 1337.620000 930.660000 1338.720000 931.140000 ;
+ RECT 1337.620000 925.220000 1338.720000 925.700000 ;
+ RECT 1292.620000 936.100000 1293.720000 936.580000 ;
+ RECT 1292.620000 930.660000 1293.720000 931.140000 ;
+ RECT 1292.620000 925.220000 1293.720000 925.700000 ;
+ RECT 1337.620000 908.900000 1338.720000 909.380000 ;
+ RECT 1337.620000 903.460000 1338.720000 903.940000 ;
+ RECT 1337.620000 898.020000 1338.720000 898.500000 ;
+ RECT 1337.620000 914.340000 1338.720000 914.820000 ;
+ RECT 1337.620000 919.780000 1338.720000 920.260000 ;
+ RECT 1292.620000 919.780000 1293.720000 920.260000 ;
+ RECT 1292.620000 908.900000 1293.720000 909.380000 ;
+ RECT 1292.620000 903.460000 1293.720000 903.940000 ;
+ RECT 1292.620000 898.020000 1293.720000 898.500000 ;
+ RECT 1292.620000 914.340000 1293.720000 914.820000 ;
+ RECT 1247.620000 936.100000 1248.720000 936.580000 ;
+ RECT 1243.490000 936.100000 1244.490000 936.580000 ;
+ RECT 1243.490000 930.660000 1244.490000 931.140000 ;
+ RECT 1247.620000 930.660000 1248.720000 931.140000 ;
+ RECT 1247.620000 925.220000 1248.720000 925.700000 ;
+ RECT 1243.490000 925.220000 1244.490000 925.700000 ;
+ RECT 1247.620000 919.780000 1248.720000 920.260000 ;
+ RECT 1243.490000 919.780000 1244.490000 920.260000 ;
+ RECT 1247.620000 914.340000 1248.720000 914.820000 ;
+ RECT 1243.490000 914.340000 1244.490000 914.820000 ;
+ RECT 1247.620000 903.460000 1248.720000 903.940000 ;
+ RECT 1243.490000 903.460000 1244.490000 903.940000 ;
+ RECT 1247.620000 898.020000 1248.720000 898.500000 ;
+ RECT 1243.490000 898.020000 1244.490000 898.500000 ;
+ RECT 1247.620000 908.900000 1248.720000 909.380000 ;
+ RECT 1243.490000 908.900000 1244.490000 909.380000 ;
+ RECT 1337.620000 892.580000 1338.720000 893.060000 ;
+ RECT 1337.620000 887.140000 1338.720000 887.620000 ;
+ RECT 1337.620000 881.700000 1338.720000 882.180000 ;
+ RECT 1337.620000 876.260000 1338.720000 876.740000 ;
+ RECT 1292.620000 892.580000 1293.720000 893.060000 ;
+ RECT 1292.620000 887.140000 1293.720000 887.620000 ;
+ RECT 1292.620000 881.700000 1293.720000 882.180000 ;
+ RECT 1292.620000 876.260000 1293.720000 876.740000 ;
+ RECT 1337.620000 865.380000 1338.720000 865.860000 ;
+ RECT 1337.620000 849.060000 1338.720000 849.540000 ;
+ RECT 1337.620000 854.500000 1338.720000 854.980000 ;
+ RECT 1337.620000 859.940000 1338.720000 860.420000 ;
+ RECT 1337.620000 870.820000 1338.720000 871.300000 ;
+ RECT 1292.620000 849.060000 1293.720000 849.540000 ;
+ RECT 1292.620000 854.500000 1293.720000 854.980000 ;
+ RECT 1292.620000 859.940000 1293.720000 860.420000 ;
+ RECT 1292.620000 865.380000 1293.720000 865.860000 ;
+ RECT 1292.620000 870.820000 1293.720000 871.300000 ;
+ RECT 1247.620000 892.580000 1248.720000 893.060000 ;
+ RECT 1243.490000 892.580000 1244.490000 893.060000 ;
+ RECT 1247.620000 887.140000 1248.720000 887.620000 ;
+ RECT 1243.490000 887.140000 1244.490000 887.620000 ;
+ RECT 1247.620000 881.700000 1248.720000 882.180000 ;
+ RECT 1243.490000 881.700000 1244.490000 882.180000 ;
+ RECT 1247.620000 876.260000 1248.720000 876.740000 ;
+ RECT 1243.490000 876.260000 1244.490000 876.740000 ;
+ RECT 1247.620000 870.820000 1248.720000 871.300000 ;
+ RECT 1247.620000 865.380000 1248.720000 865.860000 ;
+ RECT 1243.490000 870.820000 1244.490000 871.300000 ;
+ RECT 1243.490000 865.380000 1244.490000 865.860000 ;
+ RECT 1247.620000 859.940000 1248.720000 860.420000 ;
+ RECT 1243.490000 859.940000 1244.490000 860.420000 ;
+ RECT 1247.620000 854.500000 1248.720000 854.980000 ;
+ RECT 1243.490000 854.500000 1244.490000 854.980000 ;
+ RECT 1247.620000 849.060000 1248.720000 849.540000 ;
+ RECT 1243.490000 849.060000 1244.490000 849.540000 ;
+ RECT 1427.620000 843.620000 1428.720000 844.100000 ;
+ RECT 1427.620000 838.180000 1428.720000 838.660000 ;
+ RECT 1436.930000 843.620000 1437.930000 844.100000 ;
+ RECT 1436.930000 838.180000 1437.930000 838.660000 ;
+ RECT 1436.930000 821.860000 1437.930000 822.340000 ;
+ RECT 1436.930000 827.300000 1437.930000 827.780000 ;
+ RECT 1436.930000 832.740000 1437.930000 833.220000 ;
+ RECT 1427.620000 832.740000 1428.720000 833.220000 ;
+ RECT 1427.620000 827.300000 1428.720000 827.780000 ;
+ RECT 1427.620000 821.860000 1428.720000 822.340000 ;
+ RECT 1427.620000 810.980000 1428.720000 811.460000 ;
+ RECT 1427.620000 816.420000 1428.720000 816.900000 ;
+ RECT 1436.930000 816.420000 1437.930000 816.900000 ;
+ RECT 1436.930000 810.980000 1437.930000 811.460000 ;
+ RECT 1436.930000 800.100000 1437.930000 800.580000 ;
+ RECT 1436.930000 805.540000 1437.930000 806.020000 ;
+ RECT 1427.620000 800.100000 1428.720000 800.580000 ;
+ RECT 1427.620000 805.540000 1428.720000 806.020000 ;
+ RECT 1382.620000 843.620000 1383.720000 844.100000 ;
+ RECT 1382.620000 838.180000 1383.720000 838.660000 ;
+ RECT 1382.620000 832.740000 1383.720000 833.220000 ;
+ RECT 1382.620000 827.300000 1383.720000 827.780000 ;
+ RECT 1382.620000 821.860000 1383.720000 822.340000 ;
+ RECT 1382.620000 800.100000 1383.720000 800.580000 ;
+ RECT 1382.620000 805.540000 1383.720000 806.020000 ;
+ RECT 1382.620000 810.980000 1383.720000 811.460000 ;
+ RECT 1382.620000 816.420000 1383.720000 816.900000 ;
+ RECT 1427.620000 794.660000 1428.720000 795.140000 ;
+ RECT 1427.620000 789.220000 1428.720000 789.700000 ;
+ RECT 1436.930000 794.660000 1437.930000 795.140000 ;
+ RECT 1436.930000 789.220000 1437.930000 789.700000 ;
+ RECT 1427.620000 778.340000 1428.720000 778.820000 ;
+ RECT 1427.620000 772.900000 1428.720000 773.380000 ;
+ RECT 1436.930000 778.340000 1437.930000 778.820000 ;
+ RECT 1436.930000 772.900000 1437.930000 773.380000 ;
+ RECT 1427.620000 783.780000 1428.720000 784.260000 ;
+ RECT 1436.930000 783.780000 1437.930000 784.260000 ;
+ RECT 1436.930000 762.020000 1437.930000 762.500000 ;
+ RECT 1436.930000 767.460000 1437.930000 767.940000 ;
+ RECT 1427.620000 767.460000 1428.720000 767.940000 ;
+ RECT 1427.620000 762.020000 1428.720000 762.500000 ;
+ RECT 1427.620000 756.580000 1428.720000 757.060000 ;
+ RECT 1427.620000 751.140000 1428.720000 751.620000 ;
+ RECT 1436.930000 756.580000 1437.930000 757.060000 ;
+ RECT 1436.930000 751.140000 1437.930000 751.620000 ;
+ RECT 1382.620000 794.660000 1383.720000 795.140000 ;
+ RECT 1382.620000 789.220000 1383.720000 789.700000 ;
+ RECT 1382.620000 783.780000 1383.720000 784.260000 ;
+ RECT 1382.620000 778.340000 1383.720000 778.820000 ;
+ RECT 1382.620000 772.900000 1383.720000 773.380000 ;
+ RECT 1382.620000 767.460000 1383.720000 767.940000 ;
+ RECT 1382.620000 762.020000 1383.720000 762.500000 ;
+ RECT 1382.620000 756.580000 1383.720000 757.060000 ;
+ RECT 1382.620000 751.140000 1383.720000 751.620000 ;
+ RECT 1337.620000 843.620000 1338.720000 844.100000 ;
+ RECT 1337.620000 838.180000 1338.720000 838.660000 ;
+ RECT 1337.620000 832.740000 1338.720000 833.220000 ;
+ RECT 1337.620000 827.300000 1338.720000 827.780000 ;
+ RECT 1337.620000 821.860000 1338.720000 822.340000 ;
+ RECT 1292.620000 843.620000 1293.720000 844.100000 ;
+ RECT 1292.620000 838.180000 1293.720000 838.660000 ;
+ RECT 1292.620000 832.740000 1293.720000 833.220000 ;
+ RECT 1292.620000 827.300000 1293.720000 827.780000 ;
+ RECT 1292.620000 821.860000 1293.720000 822.340000 ;
+ RECT 1337.620000 816.420000 1338.720000 816.900000 ;
+ RECT 1337.620000 810.980000 1338.720000 811.460000 ;
+ RECT 1337.620000 805.540000 1338.720000 806.020000 ;
+ RECT 1337.620000 800.100000 1338.720000 800.580000 ;
+ RECT 1292.620000 810.980000 1293.720000 811.460000 ;
+ RECT 1292.620000 805.540000 1293.720000 806.020000 ;
+ RECT 1292.620000 800.100000 1293.720000 800.580000 ;
+ RECT 1292.620000 816.420000 1293.720000 816.900000 ;
+ RECT 1247.620000 843.620000 1248.720000 844.100000 ;
+ RECT 1243.490000 843.620000 1244.490000 844.100000 ;
+ RECT 1247.620000 838.180000 1248.720000 838.660000 ;
+ RECT 1243.490000 838.180000 1244.490000 838.660000 ;
+ RECT 1247.620000 832.740000 1248.720000 833.220000 ;
+ RECT 1243.490000 832.740000 1244.490000 833.220000 ;
+ RECT 1247.620000 821.860000 1248.720000 822.340000 ;
+ RECT 1243.490000 821.860000 1244.490000 822.340000 ;
+ RECT 1243.490000 827.300000 1244.490000 827.780000 ;
+ RECT 1247.620000 827.300000 1248.720000 827.780000 ;
+ RECT 1247.620000 816.420000 1248.720000 816.900000 ;
+ RECT 1243.490000 816.420000 1244.490000 816.900000 ;
+ RECT 1247.620000 810.980000 1248.720000 811.460000 ;
+ RECT 1243.490000 810.980000 1244.490000 811.460000 ;
+ RECT 1247.620000 805.540000 1248.720000 806.020000 ;
+ RECT 1243.490000 805.540000 1244.490000 806.020000 ;
+ RECT 1247.620000 800.100000 1248.720000 800.580000 ;
+ RECT 1243.490000 800.100000 1244.490000 800.580000 ;
+ RECT 1337.620000 794.660000 1338.720000 795.140000 ;
+ RECT 1337.620000 789.220000 1338.720000 789.700000 ;
+ RECT 1337.620000 783.780000 1338.720000 784.260000 ;
+ RECT 1337.620000 778.340000 1338.720000 778.820000 ;
+ RECT 1337.620000 772.900000 1338.720000 773.380000 ;
+ RECT 1292.620000 794.660000 1293.720000 795.140000 ;
+ RECT 1292.620000 789.220000 1293.720000 789.700000 ;
+ RECT 1292.620000 783.780000 1293.720000 784.260000 ;
+ RECT 1292.620000 778.340000 1293.720000 778.820000 ;
+ RECT 1292.620000 772.900000 1293.720000 773.380000 ;
+ RECT 1337.620000 751.140000 1338.720000 751.620000 ;
+ RECT 1337.620000 756.580000 1338.720000 757.060000 ;
+ RECT 1337.620000 762.020000 1338.720000 762.500000 ;
+ RECT 1337.620000 767.460000 1338.720000 767.940000 ;
+ RECT 1292.620000 751.140000 1293.720000 751.620000 ;
+ RECT 1292.620000 756.580000 1293.720000 757.060000 ;
+ RECT 1292.620000 762.020000 1293.720000 762.500000 ;
+ RECT 1292.620000 767.460000 1293.720000 767.940000 ;
+ RECT 1247.620000 794.660000 1248.720000 795.140000 ;
+ RECT 1243.490000 794.660000 1244.490000 795.140000 ;
+ RECT 1247.620000 789.220000 1248.720000 789.700000 ;
+ RECT 1243.490000 789.220000 1244.490000 789.700000 ;
+ RECT 1247.620000 778.340000 1248.720000 778.820000 ;
+ RECT 1243.490000 778.340000 1244.490000 778.820000 ;
+ RECT 1247.620000 772.900000 1248.720000 773.380000 ;
+ RECT 1243.490000 772.900000 1244.490000 773.380000 ;
+ RECT 1247.620000 783.780000 1248.720000 784.260000 ;
+ RECT 1243.490000 783.780000 1244.490000 784.260000 ;
+ RECT 1247.620000 767.460000 1248.720000 767.940000 ;
+ RECT 1243.490000 767.460000 1244.490000 767.940000 ;
+ RECT 1247.620000 762.020000 1248.720000 762.500000 ;
+ RECT 1243.490000 762.020000 1244.490000 762.500000 ;
+ RECT 1247.620000 756.580000 1248.720000 757.060000 ;
+ RECT 1247.620000 751.140000 1248.720000 751.620000 ;
+ RECT 1243.490000 756.580000 1244.490000 757.060000 ;
+ RECT 1243.490000 751.140000 1244.490000 751.620000 ;
+ RECT 1240.660000 941.500000 1440.760000 942.500000 ;
+ RECT 1240.660000 749.130000 1440.760000 750.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 746.280000 1244.490000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 945.540000 1244.490000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 746.280000 1437.930000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 945.540000 1437.930000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 749.130000 1241.660000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 749.130000 1440.760000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 941.500000 1241.660000 942.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 941.500000 1440.760000 942.500000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 548.870000 1428.720000 742.240000 ;
+ RECT 1382.620000 548.870000 1383.720000 742.240000 ;
+ RECT 1436.930000 546.020000 1437.930000 746.280000 ;
+ RECT 1337.620000 548.870000 1338.720000 742.240000 ;
+ RECT 1292.620000 548.870000 1293.720000 742.240000 ;
+ RECT 1247.620000 548.870000 1248.720000 742.240000 ;
+ RECT 1243.490000 546.020000 1244.490000 746.280000 ;
+ LAYER met3 ;
+ RECT 1427.620000 735.840000 1428.720000 736.320000 ;
+ RECT 1436.930000 735.840000 1437.930000 736.320000 ;
+ RECT 1436.930000 724.960000 1437.930000 725.440000 ;
+ RECT 1436.930000 730.400000 1437.930000 730.880000 ;
+ RECT 1427.620000 730.400000 1428.720000 730.880000 ;
+ RECT 1427.620000 724.960000 1428.720000 725.440000 ;
+ RECT 1427.620000 719.520000 1428.720000 720.000000 ;
+ RECT 1427.620000 714.080000 1428.720000 714.560000 ;
+ RECT 1436.930000 719.520000 1437.930000 720.000000 ;
+ RECT 1436.930000 714.080000 1437.930000 714.560000 ;
+ RECT 1427.620000 697.760000 1428.720000 698.240000 ;
+ RECT 1427.620000 703.200000 1428.720000 703.680000 ;
+ RECT 1436.930000 703.200000 1437.930000 703.680000 ;
+ RECT 1436.930000 697.760000 1437.930000 698.240000 ;
+ RECT 1427.620000 708.640000 1428.720000 709.120000 ;
+ RECT 1436.930000 708.640000 1437.930000 709.120000 ;
+ RECT 1382.620000 735.840000 1383.720000 736.320000 ;
+ RECT 1382.620000 730.400000 1383.720000 730.880000 ;
+ RECT 1382.620000 724.960000 1383.720000 725.440000 ;
+ RECT 1382.620000 719.520000 1383.720000 720.000000 ;
+ RECT 1382.620000 697.760000 1383.720000 698.240000 ;
+ RECT 1382.620000 703.200000 1383.720000 703.680000 ;
+ RECT 1382.620000 708.640000 1383.720000 709.120000 ;
+ RECT 1382.620000 714.080000 1383.720000 714.560000 ;
+ RECT 1436.930000 686.880000 1437.930000 687.360000 ;
+ RECT 1436.930000 692.320000 1437.930000 692.800000 ;
+ RECT 1427.620000 692.320000 1428.720000 692.800000 ;
+ RECT 1427.620000 686.880000 1428.720000 687.360000 ;
+ RECT 1427.620000 681.440000 1428.720000 681.920000 ;
+ RECT 1427.620000 676.000000 1428.720000 676.480000 ;
+ RECT 1436.930000 681.440000 1437.930000 681.920000 ;
+ RECT 1436.930000 676.000000 1437.930000 676.480000 ;
+ RECT 1436.930000 659.680000 1437.930000 660.160000 ;
+ RECT 1436.930000 665.120000 1437.930000 665.600000 ;
+ RECT 1436.930000 670.560000 1437.930000 671.040000 ;
+ RECT 1427.620000 665.120000 1428.720000 665.600000 ;
+ RECT 1427.620000 659.680000 1428.720000 660.160000 ;
+ RECT 1427.620000 670.560000 1428.720000 671.040000 ;
+ RECT 1427.620000 654.240000 1428.720000 654.720000 ;
+ RECT 1427.620000 648.800000 1428.720000 649.280000 ;
+ RECT 1436.930000 654.240000 1437.930000 654.720000 ;
+ RECT 1436.930000 648.800000 1437.930000 649.280000 ;
+ RECT 1382.620000 692.320000 1383.720000 692.800000 ;
+ RECT 1382.620000 686.880000 1383.720000 687.360000 ;
+ RECT 1382.620000 681.440000 1383.720000 681.920000 ;
+ RECT 1382.620000 676.000000 1383.720000 676.480000 ;
+ RECT 1382.620000 665.120000 1383.720000 665.600000 ;
+ RECT 1382.620000 659.680000 1383.720000 660.160000 ;
+ RECT 1382.620000 654.240000 1383.720000 654.720000 ;
+ RECT 1382.620000 648.800000 1383.720000 649.280000 ;
+ RECT 1382.620000 670.560000 1383.720000 671.040000 ;
+ RECT 1337.620000 735.840000 1338.720000 736.320000 ;
+ RECT 1337.620000 730.400000 1338.720000 730.880000 ;
+ RECT 1337.620000 724.960000 1338.720000 725.440000 ;
+ RECT 1292.620000 735.840000 1293.720000 736.320000 ;
+ RECT 1292.620000 730.400000 1293.720000 730.880000 ;
+ RECT 1292.620000 724.960000 1293.720000 725.440000 ;
+ RECT 1337.620000 708.640000 1338.720000 709.120000 ;
+ RECT 1337.620000 703.200000 1338.720000 703.680000 ;
+ RECT 1337.620000 697.760000 1338.720000 698.240000 ;
+ RECT 1337.620000 714.080000 1338.720000 714.560000 ;
+ RECT 1337.620000 719.520000 1338.720000 720.000000 ;
+ RECT 1292.620000 719.520000 1293.720000 720.000000 ;
+ RECT 1292.620000 708.640000 1293.720000 709.120000 ;
+ RECT 1292.620000 703.200000 1293.720000 703.680000 ;
+ RECT 1292.620000 697.760000 1293.720000 698.240000 ;
+ RECT 1292.620000 714.080000 1293.720000 714.560000 ;
+ RECT 1247.620000 735.840000 1248.720000 736.320000 ;
+ RECT 1243.490000 735.840000 1244.490000 736.320000 ;
+ RECT 1243.490000 730.400000 1244.490000 730.880000 ;
+ RECT 1247.620000 730.400000 1248.720000 730.880000 ;
+ RECT 1247.620000 724.960000 1248.720000 725.440000 ;
+ RECT 1243.490000 724.960000 1244.490000 725.440000 ;
+ RECT 1247.620000 719.520000 1248.720000 720.000000 ;
+ RECT 1243.490000 719.520000 1244.490000 720.000000 ;
+ RECT 1247.620000 714.080000 1248.720000 714.560000 ;
+ RECT 1243.490000 714.080000 1244.490000 714.560000 ;
+ RECT 1247.620000 703.200000 1248.720000 703.680000 ;
+ RECT 1243.490000 703.200000 1244.490000 703.680000 ;
+ RECT 1247.620000 697.760000 1248.720000 698.240000 ;
+ RECT 1243.490000 697.760000 1244.490000 698.240000 ;
+ RECT 1247.620000 708.640000 1248.720000 709.120000 ;
+ RECT 1243.490000 708.640000 1244.490000 709.120000 ;
+ RECT 1337.620000 692.320000 1338.720000 692.800000 ;
+ RECT 1337.620000 686.880000 1338.720000 687.360000 ;
+ RECT 1337.620000 681.440000 1338.720000 681.920000 ;
+ RECT 1337.620000 676.000000 1338.720000 676.480000 ;
+ RECT 1292.620000 692.320000 1293.720000 692.800000 ;
+ RECT 1292.620000 686.880000 1293.720000 687.360000 ;
+ RECT 1292.620000 681.440000 1293.720000 681.920000 ;
+ RECT 1292.620000 676.000000 1293.720000 676.480000 ;
+ RECT 1337.620000 665.120000 1338.720000 665.600000 ;
+ RECT 1337.620000 648.800000 1338.720000 649.280000 ;
+ RECT 1337.620000 654.240000 1338.720000 654.720000 ;
+ RECT 1337.620000 659.680000 1338.720000 660.160000 ;
+ RECT 1337.620000 670.560000 1338.720000 671.040000 ;
+ RECT 1292.620000 648.800000 1293.720000 649.280000 ;
+ RECT 1292.620000 654.240000 1293.720000 654.720000 ;
+ RECT 1292.620000 659.680000 1293.720000 660.160000 ;
+ RECT 1292.620000 665.120000 1293.720000 665.600000 ;
+ RECT 1292.620000 670.560000 1293.720000 671.040000 ;
+ RECT 1247.620000 692.320000 1248.720000 692.800000 ;
+ RECT 1243.490000 692.320000 1244.490000 692.800000 ;
+ RECT 1247.620000 686.880000 1248.720000 687.360000 ;
+ RECT 1243.490000 686.880000 1244.490000 687.360000 ;
+ RECT 1247.620000 681.440000 1248.720000 681.920000 ;
+ RECT 1243.490000 681.440000 1244.490000 681.920000 ;
+ RECT 1247.620000 676.000000 1248.720000 676.480000 ;
+ RECT 1243.490000 676.000000 1244.490000 676.480000 ;
+ RECT 1247.620000 670.560000 1248.720000 671.040000 ;
+ RECT 1247.620000 665.120000 1248.720000 665.600000 ;
+ RECT 1243.490000 670.560000 1244.490000 671.040000 ;
+ RECT 1243.490000 665.120000 1244.490000 665.600000 ;
+ RECT 1247.620000 659.680000 1248.720000 660.160000 ;
+ RECT 1243.490000 659.680000 1244.490000 660.160000 ;
+ RECT 1247.620000 654.240000 1248.720000 654.720000 ;
+ RECT 1243.490000 654.240000 1244.490000 654.720000 ;
+ RECT 1247.620000 648.800000 1248.720000 649.280000 ;
+ RECT 1243.490000 648.800000 1244.490000 649.280000 ;
+ RECT 1427.620000 643.360000 1428.720000 643.840000 ;
+ RECT 1427.620000 637.920000 1428.720000 638.400000 ;
+ RECT 1436.930000 643.360000 1437.930000 643.840000 ;
+ RECT 1436.930000 637.920000 1437.930000 638.400000 ;
+ RECT 1436.930000 621.600000 1437.930000 622.080000 ;
+ RECT 1436.930000 627.040000 1437.930000 627.520000 ;
+ RECT 1436.930000 632.480000 1437.930000 632.960000 ;
+ RECT 1427.620000 632.480000 1428.720000 632.960000 ;
+ RECT 1427.620000 627.040000 1428.720000 627.520000 ;
+ RECT 1427.620000 621.600000 1428.720000 622.080000 ;
+ RECT 1427.620000 610.720000 1428.720000 611.200000 ;
+ RECT 1427.620000 616.160000 1428.720000 616.640000 ;
+ RECT 1436.930000 616.160000 1437.930000 616.640000 ;
+ RECT 1436.930000 610.720000 1437.930000 611.200000 ;
+ RECT 1436.930000 599.840000 1437.930000 600.320000 ;
+ RECT 1436.930000 605.280000 1437.930000 605.760000 ;
+ RECT 1427.620000 599.840000 1428.720000 600.320000 ;
+ RECT 1427.620000 605.280000 1428.720000 605.760000 ;
+ RECT 1382.620000 643.360000 1383.720000 643.840000 ;
+ RECT 1382.620000 637.920000 1383.720000 638.400000 ;
+ RECT 1382.620000 632.480000 1383.720000 632.960000 ;
+ RECT 1382.620000 627.040000 1383.720000 627.520000 ;
+ RECT 1382.620000 621.600000 1383.720000 622.080000 ;
+ RECT 1382.620000 599.840000 1383.720000 600.320000 ;
+ RECT 1382.620000 605.280000 1383.720000 605.760000 ;
+ RECT 1382.620000 610.720000 1383.720000 611.200000 ;
+ RECT 1382.620000 616.160000 1383.720000 616.640000 ;
+ RECT 1427.620000 594.400000 1428.720000 594.880000 ;
+ RECT 1427.620000 588.960000 1428.720000 589.440000 ;
+ RECT 1436.930000 594.400000 1437.930000 594.880000 ;
+ RECT 1436.930000 588.960000 1437.930000 589.440000 ;
+ RECT 1427.620000 578.080000 1428.720000 578.560000 ;
+ RECT 1427.620000 572.640000 1428.720000 573.120000 ;
+ RECT 1436.930000 578.080000 1437.930000 578.560000 ;
+ RECT 1436.930000 572.640000 1437.930000 573.120000 ;
+ RECT 1427.620000 583.520000 1428.720000 584.000000 ;
+ RECT 1436.930000 583.520000 1437.930000 584.000000 ;
+ RECT 1436.930000 561.760000 1437.930000 562.240000 ;
+ RECT 1436.930000 567.200000 1437.930000 567.680000 ;
+ RECT 1427.620000 567.200000 1428.720000 567.680000 ;
+ RECT 1427.620000 561.760000 1428.720000 562.240000 ;
+ RECT 1427.620000 556.320000 1428.720000 556.800000 ;
+ RECT 1427.620000 550.880000 1428.720000 551.360000 ;
+ RECT 1436.930000 556.320000 1437.930000 556.800000 ;
+ RECT 1436.930000 550.880000 1437.930000 551.360000 ;
+ RECT 1382.620000 594.400000 1383.720000 594.880000 ;
+ RECT 1382.620000 588.960000 1383.720000 589.440000 ;
+ RECT 1382.620000 583.520000 1383.720000 584.000000 ;
+ RECT 1382.620000 578.080000 1383.720000 578.560000 ;
+ RECT 1382.620000 572.640000 1383.720000 573.120000 ;
+ RECT 1382.620000 567.200000 1383.720000 567.680000 ;
+ RECT 1382.620000 561.760000 1383.720000 562.240000 ;
+ RECT 1382.620000 556.320000 1383.720000 556.800000 ;
+ RECT 1382.620000 550.880000 1383.720000 551.360000 ;
+ RECT 1337.620000 643.360000 1338.720000 643.840000 ;
+ RECT 1337.620000 637.920000 1338.720000 638.400000 ;
+ RECT 1337.620000 632.480000 1338.720000 632.960000 ;
+ RECT 1337.620000 627.040000 1338.720000 627.520000 ;
+ RECT 1337.620000 621.600000 1338.720000 622.080000 ;
+ RECT 1292.620000 643.360000 1293.720000 643.840000 ;
+ RECT 1292.620000 637.920000 1293.720000 638.400000 ;
+ RECT 1292.620000 632.480000 1293.720000 632.960000 ;
+ RECT 1292.620000 627.040000 1293.720000 627.520000 ;
+ RECT 1292.620000 621.600000 1293.720000 622.080000 ;
+ RECT 1337.620000 616.160000 1338.720000 616.640000 ;
+ RECT 1337.620000 610.720000 1338.720000 611.200000 ;
+ RECT 1337.620000 605.280000 1338.720000 605.760000 ;
+ RECT 1337.620000 599.840000 1338.720000 600.320000 ;
+ RECT 1292.620000 610.720000 1293.720000 611.200000 ;
+ RECT 1292.620000 605.280000 1293.720000 605.760000 ;
+ RECT 1292.620000 599.840000 1293.720000 600.320000 ;
+ RECT 1292.620000 616.160000 1293.720000 616.640000 ;
+ RECT 1247.620000 643.360000 1248.720000 643.840000 ;
+ RECT 1243.490000 643.360000 1244.490000 643.840000 ;
+ RECT 1247.620000 637.920000 1248.720000 638.400000 ;
+ RECT 1243.490000 637.920000 1244.490000 638.400000 ;
+ RECT 1247.620000 632.480000 1248.720000 632.960000 ;
+ RECT 1243.490000 632.480000 1244.490000 632.960000 ;
+ RECT 1247.620000 621.600000 1248.720000 622.080000 ;
+ RECT 1243.490000 621.600000 1244.490000 622.080000 ;
+ RECT 1243.490000 627.040000 1244.490000 627.520000 ;
+ RECT 1247.620000 627.040000 1248.720000 627.520000 ;
+ RECT 1247.620000 616.160000 1248.720000 616.640000 ;
+ RECT 1243.490000 616.160000 1244.490000 616.640000 ;
+ RECT 1247.620000 610.720000 1248.720000 611.200000 ;
+ RECT 1243.490000 610.720000 1244.490000 611.200000 ;
+ RECT 1247.620000 605.280000 1248.720000 605.760000 ;
+ RECT 1243.490000 605.280000 1244.490000 605.760000 ;
+ RECT 1247.620000 599.840000 1248.720000 600.320000 ;
+ RECT 1243.490000 599.840000 1244.490000 600.320000 ;
+ RECT 1337.620000 594.400000 1338.720000 594.880000 ;
+ RECT 1337.620000 588.960000 1338.720000 589.440000 ;
+ RECT 1337.620000 583.520000 1338.720000 584.000000 ;
+ RECT 1337.620000 578.080000 1338.720000 578.560000 ;
+ RECT 1337.620000 572.640000 1338.720000 573.120000 ;
+ RECT 1292.620000 594.400000 1293.720000 594.880000 ;
+ RECT 1292.620000 588.960000 1293.720000 589.440000 ;
+ RECT 1292.620000 583.520000 1293.720000 584.000000 ;
+ RECT 1292.620000 578.080000 1293.720000 578.560000 ;
+ RECT 1292.620000 572.640000 1293.720000 573.120000 ;
+ RECT 1337.620000 550.880000 1338.720000 551.360000 ;
+ RECT 1337.620000 556.320000 1338.720000 556.800000 ;
+ RECT 1337.620000 561.760000 1338.720000 562.240000 ;
+ RECT 1337.620000 567.200000 1338.720000 567.680000 ;
+ RECT 1292.620000 550.880000 1293.720000 551.360000 ;
+ RECT 1292.620000 556.320000 1293.720000 556.800000 ;
+ RECT 1292.620000 561.760000 1293.720000 562.240000 ;
+ RECT 1292.620000 567.200000 1293.720000 567.680000 ;
+ RECT 1247.620000 594.400000 1248.720000 594.880000 ;
+ RECT 1243.490000 594.400000 1244.490000 594.880000 ;
+ RECT 1247.620000 588.960000 1248.720000 589.440000 ;
+ RECT 1243.490000 588.960000 1244.490000 589.440000 ;
+ RECT 1247.620000 578.080000 1248.720000 578.560000 ;
+ RECT 1243.490000 578.080000 1244.490000 578.560000 ;
+ RECT 1247.620000 572.640000 1248.720000 573.120000 ;
+ RECT 1243.490000 572.640000 1244.490000 573.120000 ;
+ RECT 1247.620000 583.520000 1248.720000 584.000000 ;
+ RECT 1243.490000 583.520000 1244.490000 584.000000 ;
+ RECT 1247.620000 567.200000 1248.720000 567.680000 ;
+ RECT 1243.490000 567.200000 1244.490000 567.680000 ;
+ RECT 1247.620000 561.760000 1248.720000 562.240000 ;
+ RECT 1243.490000 561.760000 1244.490000 562.240000 ;
+ RECT 1247.620000 556.320000 1248.720000 556.800000 ;
+ RECT 1247.620000 550.880000 1248.720000 551.360000 ;
+ RECT 1243.490000 556.320000 1244.490000 556.800000 ;
+ RECT 1243.490000 550.880000 1244.490000 551.360000 ;
+ RECT 1240.660000 741.240000 1440.760000 742.240000 ;
+ RECT 1240.660000 548.870000 1440.760000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 546.020000 1244.490000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 745.280000 1244.490000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 546.020000 1437.930000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 745.280000 1437.930000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 548.870000 1241.660000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 548.870000 1440.760000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 741.240000 1241.660000 742.240000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 741.240000 1440.760000 742.240000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 348.610000 1428.720000 541.980000 ;
+ RECT 1382.620000 348.610000 1383.720000 541.980000 ;
+ RECT 1436.930000 345.760000 1437.930000 546.020000 ;
+ RECT 1337.620000 348.610000 1338.720000 541.980000 ;
+ RECT 1292.620000 348.610000 1293.720000 541.980000 ;
+ RECT 1247.620000 348.610000 1248.720000 541.980000 ;
+ RECT 1243.490000 345.760000 1244.490000 546.020000 ;
+ LAYER met3 ;
+ RECT 1427.620000 535.580000 1428.720000 536.060000 ;
+ RECT 1436.930000 535.580000 1437.930000 536.060000 ;
+ RECT 1436.930000 524.700000 1437.930000 525.180000 ;
+ RECT 1436.930000 530.140000 1437.930000 530.620000 ;
+ RECT 1427.620000 530.140000 1428.720000 530.620000 ;
+ RECT 1427.620000 524.700000 1428.720000 525.180000 ;
+ RECT 1427.620000 519.260000 1428.720000 519.740000 ;
+ RECT 1427.620000 513.820000 1428.720000 514.300000 ;
+ RECT 1436.930000 519.260000 1437.930000 519.740000 ;
+ RECT 1436.930000 513.820000 1437.930000 514.300000 ;
+ RECT 1427.620000 497.500000 1428.720000 497.980000 ;
+ RECT 1427.620000 502.940000 1428.720000 503.420000 ;
+ RECT 1436.930000 502.940000 1437.930000 503.420000 ;
+ RECT 1436.930000 497.500000 1437.930000 497.980000 ;
+ RECT 1427.620000 508.380000 1428.720000 508.860000 ;
+ RECT 1436.930000 508.380000 1437.930000 508.860000 ;
+ RECT 1382.620000 535.580000 1383.720000 536.060000 ;
+ RECT 1382.620000 530.140000 1383.720000 530.620000 ;
+ RECT 1382.620000 524.700000 1383.720000 525.180000 ;
+ RECT 1382.620000 519.260000 1383.720000 519.740000 ;
+ RECT 1382.620000 497.500000 1383.720000 497.980000 ;
+ RECT 1382.620000 502.940000 1383.720000 503.420000 ;
+ RECT 1382.620000 508.380000 1383.720000 508.860000 ;
+ RECT 1382.620000 513.820000 1383.720000 514.300000 ;
+ RECT 1436.930000 486.620000 1437.930000 487.100000 ;
+ RECT 1436.930000 492.060000 1437.930000 492.540000 ;
+ RECT 1427.620000 492.060000 1428.720000 492.540000 ;
+ RECT 1427.620000 486.620000 1428.720000 487.100000 ;
+ RECT 1427.620000 481.180000 1428.720000 481.660000 ;
+ RECT 1427.620000 475.740000 1428.720000 476.220000 ;
+ RECT 1436.930000 481.180000 1437.930000 481.660000 ;
+ RECT 1436.930000 475.740000 1437.930000 476.220000 ;
+ RECT 1436.930000 459.420000 1437.930000 459.900000 ;
+ RECT 1436.930000 464.860000 1437.930000 465.340000 ;
+ RECT 1436.930000 470.300000 1437.930000 470.780000 ;
+ RECT 1427.620000 464.860000 1428.720000 465.340000 ;
+ RECT 1427.620000 459.420000 1428.720000 459.900000 ;
+ RECT 1427.620000 470.300000 1428.720000 470.780000 ;
+ RECT 1427.620000 453.980000 1428.720000 454.460000 ;
+ RECT 1427.620000 448.540000 1428.720000 449.020000 ;
+ RECT 1436.930000 453.980000 1437.930000 454.460000 ;
+ RECT 1436.930000 448.540000 1437.930000 449.020000 ;
+ RECT 1382.620000 492.060000 1383.720000 492.540000 ;
+ RECT 1382.620000 486.620000 1383.720000 487.100000 ;
+ RECT 1382.620000 481.180000 1383.720000 481.660000 ;
+ RECT 1382.620000 475.740000 1383.720000 476.220000 ;
+ RECT 1382.620000 464.860000 1383.720000 465.340000 ;
+ RECT 1382.620000 459.420000 1383.720000 459.900000 ;
+ RECT 1382.620000 453.980000 1383.720000 454.460000 ;
+ RECT 1382.620000 448.540000 1383.720000 449.020000 ;
+ RECT 1382.620000 470.300000 1383.720000 470.780000 ;
+ RECT 1337.620000 535.580000 1338.720000 536.060000 ;
+ RECT 1337.620000 530.140000 1338.720000 530.620000 ;
+ RECT 1337.620000 524.700000 1338.720000 525.180000 ;
+ RECT 1292.620000 535.580000 1293.720000 536.060000 ;
+ RECT 1292.620000 530.140000 1293.720000 530.620000 ;
+ RECT 1292.620000 524.700000 1293.720000 525.180000 ;
+ RECT 1337.620000 508.380000 1338.720000 508.860000 ;
+ RECT 1337.620000 502.940000 1338.720000 503.420000 ;
+ RECT 1337.620000 497.500000 1338.720000 497.980000 ;
+ RECT 1337.620000 513.820000 1338.720000 514.300000 ;
+ RECT 1337.620000 519.260000 1338.720000 519.740000 ;
+ RECT 1292.620000 519.260000 1293.720000 519.740000 ;
+ RECT 1292.620000 508.380000 1293.720000 508.860000 ;
+ RECT 1292.620000 502.940000 1293.720000 503.420000 ;
+ RECT 1292.620000 497.500000 1293.720000 497.980000 ;
+ RECT 1292.620000 513.820000 1293.720000 514.300000 ;
+ RECT 1247.620000 535.580000 1248.720000 536.060000 ;
+ RECT 1243.490000 535.580000 1244.490000 536.060000 ;
+ RECT 1243.490000 530.140000 1244.490000 530.620000 ;
+ RECT 1247.620000 530.140000 1248.720000 530.620000 ;
+ RECT 1247.620000 524.700000 1248.720000 525.180000 ;
+ RECT 1243.490000 524.700000 1244.490000 525.180000 ;
+ RECT 1247.620000 519.260000 1248.720000 519.740000 ;
+ RECT 1243.490000 519.260000 1244.490000 519.740000 ;
+ RECT 1247.620000 513.820000 1248.720000 514.300000 ;
+ RECT 1243.490000 513.820000 1244.490000 514.300000 ;
+ RECT 1247.620000 502.940000 1248.720000 503.420000 ;
+ RECT 1243.490000 502.940000 1244.490000 503.420000 ;
+ RECT 1247.620000 497.500000 1248.720000 497.980000 ;
+ RECT 1243.490000 497.500000 1244.490000 497.980000 ;
+ RECT 1247.620000 508.380000 1248.720000 508.860000 ;
+ RECT 1243.490000 508.380000 1244.490000 508.860000 ;
+ RECT 1337.620000 492.060000 1338.720000 492.540000 ;
+ RECT 1337.620000 486.620000 1338.720000 487.100000 ;
+ RECT 1337.620000 481.180000 1338.720000 481.660000 ;
+ RECT 1337.620000 475.740000 1338.720000 476.220000 ;
+ RECT 1292.620000 492.060000 1293.720000 492.540000 ;
+ RECT 1292.620000 486.620000 1293.720000 487.100000 ;
+ RECT 1292.620000 481.180000 1293.720000 481.660000 ;
+ RECT 1292.620000 475.740000 1293.720000 476.220000 ;
+ RECT 1337.620000 464.860000 1338.720000 465.340000 ;
+ RECT 1337.620000 448.540000 1338.720000 449.020000 ;
+ RECT 1337.620000 453.980000 1338.720000 454.460000 ;
+ RECT 1337.620000 459.420000 1338.720000 459.900000 ;
+ RECT 1337.620000 470.300000 1338.720000 470.780000 ;
+ RECT 1292.620000 448.540000 1293.720000 449.020000 ;
+ RECT 1292.620000 453.980000 1293.720000 454.460000 ;
+ RECT 1292.620000 459.420000 1293.720000 459.900000 ;
+ RECT 1292.620000 464.860000 1293.720000 465.340000 ;
+ RECT 1292.620000 470.300000 1293.720000 470.780000 ;
+ RECT 1247.620000 492.060000 1248.720000 492.540000 ;
+ RECT 1243.490000 492.060000 1244.490000 492.540000 ;
+ RECT 1247.620000 486.620000 1248.720000 487.100000 ;
+ RECT 1243.490000 486.620000 1244.490000 487.100000 ;
+ RECT 1247.620000 481.180000 1248.720000 481.660000 ;
+ RECT 1243.490000 481.180000 1244.490000 481.660000 ;
+ RECT 1247.620000 475.740000 1248.720000 476.220000 ;
+ RECT 1243.490000 475.740000 1244.490000 476.220000 ;
+ RECT 1247.620000 470.300000 1248.720000 470.780000 ;
+ RECT 1247.620000 464.860000 1248.720000 465.340000 ;
+ RECT 1243.490000 470.300000 1244.490000 470.780000 ;
+ RECT 1243.490000 464.860000 1244.490000 465.340000 ;
+ RECT 1247.620000 459.420000 1248.720000 459.900000 ;
+ RECT 1243.490000 459.420000 1244.490000 459.900000 ;
+ RECT 1247.620000 453.980000 1248.720000 454.460000 ;
+ RECT 1243.490000 453.980000 1244.490000 454.460000 ;
+ RECT 1247.620000 448.540000 1248.720000 449.020000 ;
+ RECT 1243.490000 448.540000 1244.490000 449.020000 ;
+ RECT 1427.620000 443.100000 1428.720000 443.580000 ;
+ RECT 1427.620000 437.660000 1428.720000 438.140000 ;
+ RECT 1436.930000 443.100000 1437.930000 443.580000 ;
+ RECT 1436.930000 437.660000 1437.930000 438.140000 ;
+ RECT 1436.930000 421.340000 1437.930000 421.820000 ;
+ RECT 1436.930000 426.780000 1437.930000 427.260000 ;
+ RECT 1436.930000 432.220000 1437.930000 432.700000 ;
+ RECT 1427.620000 432.220000 1428.720000 432.700000 ;
+ RECT 1427.620000 426.780000 1428.720000 427.260000 ;
+ RECT 1427.620000 421.340000 1428.720000 421.820000 ;
+ RECT 1427.620000 410.460000 1428.720000 410.940000 ;
+ RECT 1427.620000 415.900000 1428.720000 416.380000 ;
+ RECT 1436.930000 415.900000 1437.930000 416.380000 ;
+ RECT 1436.930000 410.460000 1437.930000 410.940000 ;
+ RECT 1436.930000 399.580000 1437.930000 400.060000 ;
+ RECT 1436.930000 405.020000 1437.930000 405.500000 ;
+ RECT 1427.620000 399.580000 1428.720000 400.060000 ;
+ RECT 1427.620000 405.020000 1428.720000 405.500000 ;
+ RECT 1382.620000 443.100000 1383.720000 443.580000 ;
+ RECT 1382.620000 437.660000 1383.720000 438.140000 ;
+ RECT 1382.620000 432.220000 1383.720000 432.700000 ;
+ RECT 1382.620000 426.780000 1383.720000 427.260000 ;
+ RECT 1382.620000 421.340000 1383.720000 421.820000 ;
+ RECT 1382.620000 399.580000 1383.720000 400.060000 ;
+ RECT 1382.620000 405.020000 1383.720000 405.500000 ;
+ RECT 1382.620000 410.460000 1383.720000 410.940000 ;
+ RECT 1382.620000 415.900000 1383.720000 416.380000 ;
+ RECT 1427.620000 394.140000 1428.720000 394.620000 ;
+ RECT 1427.620000 388.700000 1428.720000 389.180000 ;
+ RECT 1436.930000 394.140000 1437.930000 394.620000 ;
+ RECT 1436.930000 388.700000 1437.930000 389.180000 ;
+ RECT 1427.620000 377.820000 1428.720000 378.300000 ;
+ RECT 1427.620000 372.380000 1428.720000 372.860000 ;
+ RECT 1436.930000 377.820000 1437.930000 378.300000 ;
+ RECT 1436.930000 372.380000 1437.930000 372.860000 ;
+ RECT 1427.620000 383.260000 1428.720000 383.740000 ;
+ RECT 1436.930000 383.260000 1437.930000 383.740000 ;
+ RECT 1436.930000 361.500000 1437.930000 361.980000 ;
+ RECT 1436.930000 366.940000 1437.930000 367.420000 ;
+ RECT 1427.620000 366.940000 1428.720000 367.420000 ;
+ RECT 1427.620000 361.500000 1428.720000 361.980000 ;
+ RECT 1427.620000 356.060000 1428.720000 356.540000 ;
+ RECT 1427.620000 350.620000 1428.720000 351.100000 ;
+ RECT 1436.930000 356.060000 1437.930000 356.540000 ;
+ RECT 1436.930000 350.620000 1437.930000 351.100000 ;
+ RECT 1382.620000 394.140000 1383.720000 394.620000 ;
+ RECT 1382.620000 388.700000 1383.720000 389.180000 ;
+ RECT 1382.620000 383.260000 1383.720000 383.740000 ;
+ RECT 1382.620000 377.820000 1383.720000 378.300000 ;
+ RECT 1382.620000 372.380000 1383.720000 372.860000 ;
+ RECT 1382.620000 366.940000 1383.720000 367.420000 ;
+ RECT 1382.620000 361.500000 1383.720000 361.980000 ;
+ RECT 1382.620000 356.060000 1383.720000 356.540000 ;
+ RECT 1382.620000 350.620000 1383.720000 351.100000 ;
+ RECT 1337.620000 443.100000 1338.720000 443.580000 ;
+ RECT 1337.620000 437.660000 1338.720000 438.140000 ;
+ RECT 1337.620000 432.220000 1338.720000 432.700000 ;
+ RECT 1337.620000 426.780000 1338.720000 427.260000 ;
+ RECT 1337.620000 421.340000 1338.720000 421.820000 ;
+ RECT 1292.620000 443.100000 1293.720000 443.580000 ;
+ RECT 1292.620000 437.660000 1293.720000 438.140000 ;
+ RECT 1292.620000 432.220000 1293.720000 432.700000 ;
+ RECT 1292.620000 426.780000 1293.720000 427.260000 ;
+ RECT 1292.620000 421.340000 1293.720000 421.820000 ;
+ RECT 1337.620000 415.900000 1338.720000 416.380000 ;
+ RECT 1337.620000 410.460000 1338.720000 410.940000 ;
+ RECT 1337.620000 405.020000 1338.720000 405.500000 ;
+ RECT 1337.620000 399.580000 1338.720000 400.060000 ;
+ RECT 1292.620000 410.460000 1293.720000 410.940000 ;
+ RECT 1292.620000 405.020000 1293.720000 405.500000 ;
+ RECT 1292.620000 399.580000 1293.720000 400.060000 ;
+ RECT 1292.620000 415.900000 1293.720000 416.380000 ;
+ RECT 1247.620000 443.100000 1248.720000 443.580000 ;
+ RECT 1243.490000 443.100000 1244.490000 443.580000 ;
+ RECT 1247.620000 437.660000 1248.720000 438.140000 ;
+ RECT 1243.490000 437.660000 1244.490000 438.140000 ;
+ RECT 1247.620000 432.220000 1248.720000 432.700000 ;
+ RECT 1243.490000 432.220000 1244.490000 432.700000 ;
+ RECT 1247.620000 421.340000 1248.720000 421.820000 ;
+ RECT 1243.490000 421.340000 1244.490000 421.820000 ;
+ RECT 1243.490000 426.780000 1244.490000 427.260000 ;
+ RECT 1247.620000 426.780000 1248.720000 427.260000 ;
+ RECT 1247.620000 415.900000 1248.720000 416.380000 ;
+ RECT 1243.490000 415.900000 1244.490000 416.380000 ;
+ RECT 1247.620000 410.460000 1248.720000 410.940000 ;
+ RECT 1243.490000 410.460000 1244.490000 410.940000 ;
+ RECT 1247.620000 405.020000 1248.720000 405.500000 ;
+ RECT 1243.490000 405.020000 1244.490000 405.500000 ;
+ RECT 1247.620000 399.580000 1248.720000 400.060000 ;
+ RECT 1243.490000 399.580000 1244.490000 400.060000 ;
+ RECT 1337.620000 394.140000 1338.720000 394.620000 ;
+ RECT 1337.620000 388.700000 1338.720000 389.180000 ;
+ RECT 1337.620000 383.260000 1338.720000 383.740000 ;
+ RECT 1337.620000 377.820000 1338.720000 378.300000 ;
+ RECT 1337.620000 372.380000 1338.720000 372.860000 ;
+ RECT 1292.620000 394.140000 1293.720000 394.620000 ;
+ RECT 1292.620000 388.700000 1293.720000 389.180000 ;
+ RECT 1292.620000 383.260000 1293.720000 383.740000 ;
+ RECT 1292.620000 377.820000 1293.720000 378.300000 ;
+ RECT 1292.620000 372.380000 1293.720000 372.860000 ;
+ RECT 1337.620000 350.620000 1338.720000 351.100000 ;
+ RECT 1337.620000 356.060000 1338.720000 356.540000 ;
+ RECT 1337.620000 361.500000 1338.720000 361.980000 ;
+ RECT 1337.620000 366.940000 1338.720000 367.420000 ;
+ RECT 1292.620000 350.620000 1293.720000 351.100000 ;
+ RECT 1292.620000 356.060000 1293.720000 356.540000 ;
+ RECT 1292.620000 361.500000 1293.720000 361.980000 ;
+ RECT 1292.620000 366.940000 1293.720000 367.420000 ;
+ RECT 1247.620000 394.140000 1248.720000 394.620000 ;
+ RECT 1243.490000 394.140000 1244.490000 394.620000 ;
+ RECT 1247.620000 388.700000 1248.720000 389.180000 ;
+ RECT 1243.490000 388.700000 1244.490000 389.180000 ;
+ RECT 1247.620000 377.820000 1248.720000 378.300000 ;
+ RECT 1243.490000 377.820000 1244.490000 378.300000 ;
+ RECT 1247.620000 372.380000 1248.720000 372.860000 ;
+ RECT 1243.490000 372.380000 1244.490000 372.860000 ;
+ RECT 1247.620000 383.260000 1248.720000 383.740000 ;
+ RECT 1243.490000 383.260000 1244.490000 383.740000 ;
+ RECT 1247.620000 366.940000 1248.720000 367.420000 ;
+ RECT 1243.490000 366.940000 1244.490000 367.420000 ;
+ RECT 1247.620000 361.500000 1248.720000 361.980000 ;
+ RECT 1243.490000 361.500000 1244.490000 361.980000 ;
+ RECT 1247.620000 356.060000 1248.720000 356.540000 ;
+ RECT 1247.620000 350.620000 1248.720000 351.100000 ;
+ RECT 1243.490000 356.060000 1244.490000 356.540000 ;
+ RECT 1243.490000 350.620000 1244.490000 351.100000 ;
+ RECT 1240.660000 540.980000 1440.760000 541.980000 ;
+ RECT 1240.660000 348.610000 1440.760000 349.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 345.760000 1244.490000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 545.020000 1244.490000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 345.760000 1437.930000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 545.020000 1437.930000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 348.610000 1241.660000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 348.610000 1440.760000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 540.980000 1241.660000 541.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 540.980000 1440.760000 541.980000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 148.350000 1428.720000 341.720000 ;
+ RECT 1382.620000 148.350000 1383.720000 341.720000 ;
+ RECT 1436.930000 145.500000 1437.930000 345.760000 ;
+ RECT 1337.620000 148.350000 1338.720000 341.720000 ;
+ RECT 1292.620000 148.350000 1293.720000 341.720000 ;
+ RECT 1247.620000 148.350000 1248.720000 341.720000 ;
+ RECT 1243.490000 145.500000 1244.490000 345.760000 ;
+ LAYER met3 ;
+ RECT 1427.620000 335.320000 1428.720000 335.800000 ;
+ RECT 1436.930000 335.320000 1437.930000 335.800000 ;
+ RECT 1436.930000 324.440000 1437.930000 324.920000 ;
+ RECT 1436.930000 329.880000 1437.930000 330.360000 ;
+ RECT 1427.620000 329.880000 1428.720000 330.360000 ;
+ RECT 1427.620000 324.440000 1428.720000 324.920000 ;
+ RECT 1427.620000 319.000000 1428.720000 319.480000 ;
+ RECT 1427.620000 313.560000 1428.720000 314.040000 ;
+ RECT 1436.930000 319.000000 1437.930000 319.480000 ;
+ RECT 1436.930000 313.560000 1437.930000 314.040000 ;
+ RECT 1427.620000 297.240000 1428.720000 297.720000 ;
+ RECT 1427.620000 302.680000 1428.720000 303.160000 ;
+ RECT 1436.930000 302.680000 1437.930000 303.160000 ;
+ RECT 1436.930000 297.240000 1437.930000 297.720000 ;
+ RECT 1427.620000 308.120000 1428.720000 308.600000 ;
+ RECT 1436.930000 308.120000 1437.930000 308.600000 ;
+ RECT 1382.620000 335.320000 1383.720000 335.800000 ;
+ RECT 1382.620000 329.880000 1383.720000 330.360000 ;
+ RECT 1382.620000 324.440000 1383.720000 324.920000 ;
+ RECT 1382.620000 319.000000 1383.720000 319.480000 ;
+ RECT 1382.620000 297.240000 1383.720000 297.720000 ;
+ RECT 1382.620000 302.680000 1383.720000 303.160000 ;
+ RECT 1382.620000 308.120000 1383.720000 308.600000 ;
+ RECT 1382.620000 313.560000 1383.720000 314.040000 ;
+ RECT 1436.930000 286.360000 1437.930000 286.840000 ;
+ RECT 1436.930000 291.800000 1437.930000 292.280000 ;
+ RECT 1427.620000 291.800000 1428.720000 292.280000 ;
+ RECT 1427.620000 286.360000 1428.720000 286.840000 ;
+ RECT 1427.620000 280.920000 1428.720000 281.400000 ;
+ RECT 1427.620000 275.480000 1428.720000 275.960000 ;
+ RECT 1436.930000 280.920000 1437.930000 281.400000 ;
+ RECT 1436.930000 275.480000 1437.930000 275.960000 ;
+ RECT 1436.930000 259.160000 1437.930000 259.640000 ;
+ RECT 1436.930000 264.600000 1437.930000 265.080000 ;
+ RECT 1436.930000 270.040000 1437.930000 270.520000 ;
+ RECT 1427.620000 264.600000 1428.720000 265.080000 ;
+ RECT 1427.620000 259.160000 1428.720000 259.640000 ;
+ RECT 1427.620000 270.040000 1428.720000 270.520000 ;
+ RECT 1427.620000 253.720000 1428.720000 254.200000 ;
+ RECT 1427.620000 248.280000 1428.720000 248.760000 ;
+ RECT 1436.930000 253.720000 1437.930000 254.200000 ;
+ RECT 1436.930000 248.280000 1437.930000 248.760000 ;
+ RECT 1382.620000 291.800000 1383.720000 292.280000 ;
+ RECT 1382.620000 286.360000 1383.720000 286.840000 ;
+ RECT 1382.620000 280.920000 1383.720000 281.400000 ;
+ RECT 1382.620000 275.480000 1383.720000 275.960000 ;
+ RECT 1382.620000 264.600000 1383.720000 265.080000 ;
+ RECT 1382.620000 259.160000 1383.720000 259.640000 ;
+ RECT 1382.620000 253.720000 1383.720000 254.200000 ;
+ RECT 1382.620000 248.280000 1383.720000 248.760000 ;
+ RECT 1382.620000 270.040000 1383.720000 270.520000 ;
+ RECT 1337.620000 335.320000 1338.720000 335.800000 ;
+ RECT 1337.620000 329.880000 1338.720000 330.360000 ;
+ RECT 1337.620000 324.440000 1338.720000 324.920000 ;
+ RECT 1292.620000 335.320000 1293.720000 335.800000 ;
+ RECT 1292.620000 329.880000 1293.720000 330.360000 ;
+ RECT 1292.620000 324.440000 1293.720000 324.920000 ;
+ RECT 1337.620000 308.120000 1338.720000 308.600000 ;
+ RECT 1337.620000 302.680000 1338.720000 303.160000 ;
+ RECT 1337.620000 297.240000 1338.720000 297.720000 ;
+ RECT 1337.620000 313.560000 1338.720000 314.040000 ;
+ RECT 1337.620000 319.000000 1338.720000 319.480000 ;
+ RECT 1292.620000 319.000000 1293.720000 319.480000 ;
+ RECT 1292.620000 308.120000 1293.720000 308.600000 ;
+ RECT 1292.620000 302.680000 1293.720000 303.160000 ;
+ RECT 1292.620000 297.240000 1293.720000 297.720000 ;
+ RECT 1292.620000 313.560000 1293.720000 314.040000 ;
+ RECT 1247.620000 335.320000 1248.720000 335.800000 ;
+ RECT 1243.490000 335.320000 1244.490000 335.800000 ;
+ RECT 1243.490000 329.880000 1244.490000 330.360000 ;
+ RECT 1247.620000 329.880000 1248.720000 330.360000 ;
+ RECT 1247.620000 324.440000 1248.720000 324.920000 ;
+ RECT 1243.490000 324.440000 1244.490000 324.920000 ;
+ RECT 1247.620000 319.000000 1248.720000 319.480000 ;
+ RECT 1243.490000 319.000000 1244.490000 319.480000 ;
+ RECT 1247.620000 313.560000 1248.720000 314.040000 ;
+ RECT 1243.490000 313.560000 1244.490000 314.040000 ;
+ RECT 1247.620000 302.680000 1248.720000 303.160000 ;
+ RECT 1243.490000 302.680000 1244.490000 303.160000 ;
+ RECT 1247.620000 297.240000 1248.720000 297.720000 ;
+ RECT 1243.490000 297.240000 1244.490000 297.720000 ;
+ RECT 1247.620000 308.120000 1248.720000 308.600000 ;
+ RECT 1243.490000 308.120000 1244.490000 308.600000 ;
+ RECT 1337.620000 291.800000 1338.720000 292.280000 ;
+ RECT 1337.620000 286.360000 1338.720000 286.840000 ;
+ RECT 1337.620000 280.920000 1338.720000 281.400000 ;
+ RECT 1337.620000 275.480000 1338.720000 275.960000 ;
+ RECT 1292.620000 291.800000 1293.720000 292.280000 ;
+ RECT 1292.620000 286.360000 1293.720000 286.840000 ;
+ RECT 1292.620000 280.920000 1293.720000 281.400000 ;
+ RECT 1292.620000 275.480000 1293.720000 275.960000 ;
+ RECT 1337.620000 264.600000 1338.720000 265.080000 ;
+ RECT 1337.620000 248.280000 1338.720000 248.760000 ;
+ RECT 1337.620000 253.720000 1338.720000 254.200000 ;
+ RECT 1337.620000 259.160000 1338.720000 259.640000 ;
+ RECT 1337.620000 270.040000 1338.720000 270.520000 ;
+ RECT 1292.620000 248.280000 1293.720000 248.760000 ;
+ RECT 1292.620000 253.720000 1293.720000 254.200000 ;
+ RECT 1292.620000 259.160000 1293.720000 259.640000 ;
+ RECT 1292.620000 264.600000 1293.720000 265.080000 ;
+ RECT 1292.620000 270.040000 1293.720000 270.520000 ;
+ RECT 1247.620000 291.800000 1248.720000 292.280000 ;
+ RECT 1243.490000 291.800000 1244.490000 292.280000 ;
+ RECT 1247.620000 286.360000 1248.720000 286.840000 ;
+ RECT 1243.490000 286.360000 1244.490000 286.840000 ;
+ RECT 1247.620000 280.920000 1248.720000 281.400000 ;
+ RECT 1243.490000 280.920000 1244.490000 281.400000 ;
+ RECT 1247.620000 275.480000 1248.720000 275.960000 ;
+ RECT 1243.490000 275.480000 1244.490000 275.960000 ;
+ RECT 1247.620000 270.040000 1248.720000 270.520000 ;
+ RECT 1247.620000 264.600000 1248.720000 265.080000 ;
+ RECT 1243.490000 270.040000 1244.490000 270.520000 ;
+ RECT 1243.490000 264.600000 1244.490000 265.080000 ;
+ RECT 1247.620000 259.160000 1248.720000 259.640000 ;
+ RECT 1243.490000 259.160000 1244.490000 259.640000 ;
+ RECT 1247.620000 253.720000 1248.720000 254.200000 ;
+ RECT 1243.490000 253.720000 1244.490000 254.200000 ;
+ RECT 1247.620000 248.280000 1248.720000 248.760000 ;
+ RECT 1243.490000 248.280000 1244.490000 248.760000 ;
+ RECT 1427.620000 242.840000 1428.720000 243.320000 ;
+ RECT 1427.620000 237.400000 1428.720000 237.880000 ;
+ RECT 1436.930000 242.840000 1437.930000 243.320000 ;
+ RECT 1436.930000 237.400000 1437.930000 237.880000 ;
+ RECT 1436.930000 221.080000 1437.930000 221.560000 ;
+ RECT 1436.930000 226.520000 1437.930000 227.000000 ;
+ RECT 1436.930000 231.960000 1437.930000 232.440000 ;
+ RECT 1427.620000 231.960000 1428.720000 232.440000 ;
+ RECT 1427.620000 226.520000 1428.720000 227.000000 ;
+ RECT 1427.620000 221.080000 1428.720000 221.560000 ;
+ RECT 1427.620000 210.200000 1428.720000 210.680000 ;
+ RECT 1427.620000 215.640000 1428.720000 216.120000 ;
+ RECT 1436.930000 215.640000 1437.930000 216.120000 ;
+ RECT 1436.930000 210.200000 1437.930000 210.680000 ;
+ RECT 1436.930000 199.320000 1437.930000 199.800000 ;
+ RECT 1436.930000 204.760000 1437.930000 205.240000 ;
+ RECT 1427.620000 199.320000 1428.720000 199.800000 ;
+ RECT 1427.620000 204.760000 1428.720000 205.240000 ;
+ RECT 1382.620000 242.840000 1383.720000 243.320000 ;
+ RECT 1382.620000 237.400000 1383.720000 237.880000 ;
+ RECT 1382.620000 231.960000 1383.720000 232.440000 ;
+ RECT 1382.620000 226.520000 1383.720000 227.000000 ;
+ RECT 1382.620000 221.080000 1383.720000 221.560000 ;
+ RECT 1382.620000 199.320000 1383.720000 199.800000 ;
+ RECT 1382.620000 204.760000 1383.720000 205.240000 ;
+ RECT 1382.620000 210.200000 1383.720000 210.680000 ;
+ RECT 1382.620000 215.640000 1383.720000 216.120000 ;
+ RECT 1427.620000 193.880000 1428.720000 194.360000 ;
+ RECT 1427.620000 188.440000 1428.720000 188.920000 ;
+ RECT 1436.930000 193.880000 1437.930000 194.360000 ;
+ RECT 1436.930000 188.440000 1437.930000 188.920000 ;
+ RECT 1427.620000 177.560000 1428.720000 178.040000 ;
+ RECT 1427.620000 172.120000 1428.720000 172.600000 ;
+ RECT 1436.930000 177.560000 1437.930000 178.040000 ;
+ RECT 1436.930000 172.120000 1437.930000 172.600000 ;
+ RECT 1427.620000 183.000000 1428.720000 183.480000 ;
+ RECT 1436.930000 183.000000 1437.930000 183.480000 ;
+ RECT 1436.930000 161.240000 1437.930000 161.720000 ;
+ RECT 1436.930000 166.680000 1437.930000 167.160000 ;
+ RECT 1427.620000 166.680000 1428.720000 167.160000 ;
+ RECT 1427.620000 161.240000 1428.720000 161.720000 ;
+ RECT 1427.620000 155.800000 1428.720000 156.280000 ;
+ RECT 1427.620000 150.360000 1428.720000 150.840000 ;
+ RECT 1436.930000 155.800000 1437.930000 156.280000 ;
+ RECT 1436.930000 150.360000 1437.930000 150.840000 ;
+ RECT 1382.620000 193.880000 1383.720000 194.360000 ;
+ RECT 1382.620000 188.440000 1383.720000 188.920000 ;
+ RECT 1382.620000 183.000000 1383.720000 183.480000 ;
+ RECT 1382.620000 177.560000 1383.720000 178.040000 ;
+ RECT 1382.620000 172.120000 1383.720000 172.600000 ;
+ RECT 1382.620000 166.680000 1383.720000 167.160000 ;
+ RECT 1382.620000 161.240000 1383.720000 161.720000 ;
+ RECT 1382.620000 155.800000 1383.720000 156.280000 ;
+ RECT 1382.620000 150.360000 1383.720000 150.840000 ;
+ RECT 1337.620000 242.840000 1338.720000 243.320000 ;
+ RECT 1337.620000 237.400000 1338.720000 237.880000 ;
+ RECT 1337.620000 231.960000 1338.720000 232.440000 ;
+ RECT 1337.620000 226.520000 1338.720000 227.000000 ;
+ RECT 1337.620000 221.080000 1338.720000 221.560000 ;
+ RECT 1292.620000 242.840000 1293.720000 243.320000 ;
+ RECT 1292.620000 237.400000 1293.720000 237.880000 ;
+ RECT 1292.620000 231.960000 1293.720000 232.440000 ;
+ RECT 1292.620000 226.520000 1293.720000 227.000000 ;
+ RECT 1292.620000 221.080000 1293.720000 221.560000 ;
+ RECT 1337.620000 215.640000 1338.720000 216.120000 ;
+ RECT 1337.620000 210.200000 1338.720000 210.680000 ;
+ RECT 1337.620000 204.760000 1338.720000 205.240000 ;
+ RECT 1337.620000 199.320000 1338.720000 199.800000 ;
+ RECT 1292.620000 210.200000 1293.720000 210.680000 ;
+ RECT 1292.620000 204.760000 1293.720000 205.240000 ;
+ RECT 1292.620000 199.320000 1293.720000 199.800000 ;
+ RECT 1292.620000 215.640000 1293.720000 216.120000 ;
+ RECT 1247.620000 242.840000 1248.720000 243.320000 ;
+ RECT 1243.490000 242.840000 1244.490000 243.320000 ;
+ RECT 1247.620000 237.400000 1248.720000 237.880000 ;
+ RECT 1243.490000 237.400000 1244.490000 237.880000 ;
+ RECT 1247.620000 231.960000 1248.720000 232.440000 ;
+ RECT 1243.490000 231.960000 1244.490000 232.440000 ;
+ RECT 1247.620000 221.080000 1248.720000 221.560000 ;
+ RECT 1243.490000 221.080000 1244.490000 221.560000 ;
+ RECT 1243.490000 226.520000 1244.490000 227.000000 ;
+ RECT 1247.620000 226.520000 1248.720000 227.000000 ;
+ RECT 1247.620000 215.640000 1248.720000 216.120000 ;
+ RECT 1243.490000 215.640000 1244.490000 216.120000 ;
+ RECT 1247.620000 210.200000 1248.720000 210.680000 ;
+ RECT 1243.490000 210.200000 1244.490000 210.680000 ;
+ RECT 1247.620000 204.760000 1248.720000 205.240000 ;
+ RECT 1243.490000 204.760000 1244.490000 205.240000 ;
+ RECT 1247.620000 199.320000 1248.720000 199.800000 ;
+ RECT 1243.490000 199.320000 1244.490000 199.800000 ;
+ RECT 1337.620000 193.880000 1338.720000 194.360000 ;
+ RECT 1337.620000 188.440000 1338.720000 188.920000 ;
+ RECT 1337.620000 183.000000 1338.720000 183.480000 ;
+ RECT 1337.620000 177.560000 1338.720000 178.040000 ;
+ RECT 1337.620000 172.120000 1338.720000 172.600000 ;
+ RECT 1292.620000 193.880000 1293.720000 194.360000 ;
+ RECT 1292.620000 188.440000 1293.720000 188.920000 ;
+ RECT 1292.620000 183.000000 1293.720000 183.480000 ;
+ RECT 1292.620000 177.560000 1293.720000 178.040000 ;
+ RECT 1292.620000 172.120000 1293.720000 172.600000 ;
+ RECT 1337.620000 150.360000 1338.720000 150.840000 ;
+ RECT 1337.620000 155.800000 1338.720000 156.280000 ;
+ RECT 1337.620000 161.240000 1338.720000 161.720000 ;
+ RECT 1337.620000 166.680000 1338.720000 167.160000 ;
+ RECT 1292.620000 150.360000 1293.720000 150.840000 ;
+ RECT 1292.620000 155.800000 1293.720000 156.280000 ;
+ RECT 1292.620000 161.240000 1293.720000 161.720000 ;
+ RECT 1292.620000 166.680000 1293.720000 167.160000 ;
+ RECT 1247.620000 193.880000 1248.720000 194.360000 ;
+ RECT 1243.490000 193.880000 1244.490000 194.360000 ;
+ RECT 1247.620000 188.440000 1248.720000 188.920000 ;
+ RECT 1243.490000 188.440000 1244.490000 188.920000 ;
+ RECT 1247.620000 177.560000 1248.720000 178.040000 ;
+ RECT 1243.490000 177.560000 1244.490000 178.040000 ;
+ RECT 1247.620000 172.120000 1248.720000 172.600000 ;
+ RECT 1243.490000 172.120000 1244.490000 172.600000 ;
+ RECT 1247.620000 183.000000 1248.720000 183.480000 ;
+ RECT 1243.490000 183.000000 1244.490000 183.480000 ;
+ RECT 1247.620000 166.680000 1248.720000 167.160000 ;
+ RECT 1243.490000 166.680000 1244.490000 167.160000 ;
+ RECT 1247.620000 161.240000 1248.720000 161.720000 ;
+ RECT 1243.490000 161.240000 1244.490000 161.720000 ;
+ RECT 1247.620000 155.800000 1248.720000 156.280000 ;
+ RECT 1247.620000 150.360000 1248.720000 150.840000 ;
+ RECT 1243.490000 155.800000 1244.490000 156.280000 ;
+ RECT 1243.490000 150.360000 1244.490000 150.840000 ;
+ RECT 1240.660000 340.720000 1440.760000 341.720000 ;
+ RECT 1240.660000 148.350000 1440.760000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 145.500000 1244.490000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 344.760000 1244.490000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 145.500000 1437.930000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 344.760000 1437.930000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 148.350000 1241.660000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 148.350000 1440.760000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 340.720000 1241.660000 341.720000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 340.720000 1440.760000 341.720000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 115.240000 1244.490000 145.500000 ;
+ RECT 1436.930000 115.240000 1437.930000 145.500000 ;
+ RECT 1247.620000 118.090000 1248.720000 142.140000 ;
+ RECT 1292.620000 118.090000 1293.720000 142.140000 ;
+ RECT 1337.620000 118.090000 1338.720000 142.140000 ;
+ RECT 1382.620000 118.090000 1383.720000 142.140000 ;
+ RECT 1427.620000 118.090000 1428.720000 142.140000 ;
+ LAYER met3 ;
+ RECT 1436.930000 130.980000 1437.930000 131.460000 ;
+ RECT 1436.930000 136.420000 1437.930000 136.900000 ;
+ RECT 1427.620000 136.420000 1428.720000 136.900000 ;
+ RECT 1427.620000 130.980000 1428.720000 131.460000 ;
+ RECT 1382.620000 130.980000 1383.720000 131.460000 ;
+ RECT 1382.620000 136.420000 1383.720000 136.900000 ;
+ RECT 1292.620000 130.980000 1293.720000 131.460000 ;
+ RECT 1337.620000 130.980000 1338.720000 131.460000 ;
+ RECT 1337.620000 136.420000 1338.720000 136.900000 ;
+ RECT 1292.620000 136.420000 1293.720000 136.900000 ;
+ RECT 1243.490000 130.980000 1244.490000 131.460000 ;
+ RECT 1247.620000 130.980000 1248.720000 131.460000 ;
+ RECT 1247.620000 136.420000 1248.720000 136.900000 ;
+ RECT 1243.490000 136.420000 1244.490000 136.900000 ;
+ RECT 1436.930000 120.100000 1437.930000 120.580000 ;
+ RECT 1436.930000 125.540000 1437.930000 126.020000 ;
+ RECT 1427.620000 125.540000 1428.720000 126.020000 ;
+ RECT 1427.620000 120.100000 1428.720000 120.580000 ;
+ RECT 1382.620000 120.100000 1383.720000 120.580000 ;
+ RECT 1382.620000 125.540000 1383.720000 126.020000 ;
+ RECT 1292.620000 120.100000 1293.720000 120.580000 ;
+ RECT 1337.620000 120.100000 1338.720000 120.580000 ;
+ RECT 1337.620000 125.540000 1338.720000 126.020000 ;
+ RECT 1292.620000 125.540000 1293.720000 126.020000 ;
+ RECT 1243.490000 125.540000 1244.490000 126.020000 ;
+ RECT 1247.620000 125.540000 1248.720000 126.020000 ;
+ RECT 1243.490000 120.100000 1244.490000 120.580000 ;
+ RECT 1247.620000 120.100000 1248.720000 120.580000 ;
+ RECT 1240.660000 141.140000 1440.760000 142.140000 ;
+ RECT 1240.660000 118.090000 1440.760000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 118.090000 1241.660000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 118.090000 1440.760000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 141.140000 1241.660000 142.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 141.140000 1440.760000 142.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 115.240000 1244.490000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 144.500000 1244.490000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 115.240000 1437.930000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 144.500000 1437.930000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 3152.250000 1428.720000 3345.620000 ;
+ RECT 1382.620000 3152.250000 1383.720000 3345.620000 ;
+ RECT 1436.930000 3149.400000 1437.930000 3349.660000 ;
+ RECT 1337.620000 3152.250000 1338.720000 3345.620000 ;
+ RECT 1292.620000 3152.250000 1293.720000 3345.620000 ;
+ RECT 1247.620000 3152.250000 1248.720000 3345.620000 ;
+ RECT 1243.490000 3149.400000 1244.490000 3349.660000 ;
+ LAYER met3 ;
+ RECT 1427.620000 3339.220000 1428.720000 3339.700000 ;
+ RECT 1436.930000 3339.220000 1437.930000 3339.700000 ;
+ RECT 1436.930000 3328.340000 1437.930000 3328.820000 ;
+ RECT 1436.930000 3333.780000 1437.930000 3334.260000 ;
+ RECT 1427.620000 3333.780000 1428.720000 3334.260000 ;
+ RECT 1427.620000 3328.340000 1428.720000 3328.820000 ;
+ RECT 1427.620000 3322.900000 1428.720000 3323.380000 ;
+ RECT 1427.620000 3317.460000 1428.720000 3317.940000 ;
+ RECT 1436.930000 3322.900000 1437.930000 3323.380000 ;
+ RECT 1436.930000 3317.460000 1437.930000 3317.940000 ;
+ RECT 1427.620000 3301.140000 1428.720000 3301.620000 ;
+ RECT 1427.620000 3306.580000 1428.720000 3307.060000 ;
+ RECT 1436.930000 3306.580000 1437.930000 3307.060000 ;
+ RECT 1436.930000 3301.140000 1437.930000 3301.620000 ;
+ RECT 1427.620000 3312.020000 1428.720000 3312.500000 ;
+ RECT 1436.930000 3312.020000 1437.930000 3312.500000 ;
+ RECT 1382.620000 3339.220000 1383.720000 3339.700000 ;
+ RECT 1382.620000 3333.780000 1383.720000 3334.260000 ;
+ RECT 1382.620000 3328.340000 1383.720000 3328.820000 ;
+ RECT 1382.620000 3322.900000 1383.720000 3323.380000 ;
+ RECT 1382.620000 3301.140000 1383.720000 3301.620000 ;
+ RECT 1382.620000 3306.580000 1383.720000 3307.060000 ;
+ RECT 1382.620000 3312.020000 1383.720000 3312.500000 ;
+ RECT 1382.620000 3317.460000 1383.720000 3317.940000 ;
+ RECT 1436.930000 3290.260000 1437.930000 3290.740000 ;
+ RECT 1436.930000 3295.700000 1437.930000 3296.180000 ;
+ RECT 1427.620000 3295.700000 1428.720000 3296.180000 ;
+ RECT 1427.620000 3290.260000 1428.720000 3290.740000 ;
+ RECT 1427.620000 3284.820000 1428.720000 3285.300000 ;
+ RECT 1427.620000 3279.380000 1428.720000 3279.860000 ;
+ RECT 1436.930000 3284.820000 1437.930000 3285.300000 ;
+ RECT 1436.930000 3279.380000 1437.930000 3279.860000 ;
+ RECT 1436.930000 3263.060000 1437.930000 3263.540000 ;
+ RECT 1436.930000 3268.500000 1437.930000 3268.980000 ;
+ RECT 1436.930000 3273.940000 1437.930000 3274.420000 ;
+ RECT 1427.620000 3268.500000 1428.720000 3268.980000 ;
+ RECT 1427.620000 3263.060000 1428.720000 3263.540000 ;
+ RECT 1427.620000 3273.940000 1428.720000 3274.420000 ;
+ RECT 1427.620000 3257.620000 1428.720000 3258.100000 ;
+ RECT 1427.620000 3252.180000 1428.720000 3252.660000 ;
+ RECT 1436.930000 3257.620000 1437.930000 3258.100000 ;
+ RECT 1436.930000 3252.180000 1437.930000 3252.660000 ;
+ RECT 1382.620000 3295.700000 1383.720000 3296.180000 ;
+ RECT 1382.620000 3290.260000 1383.720000 3290.740000 ;
+ RECT 1382.620000 3284.820000 1383.720000 3285.300000 ;
+ RECT 1382.620000 3279.380000 1383.720000 3279.860000 ;
+ RECT 1382.620000 3268.500000 1383.720000 3268.980000 ;
+ RECT 1382.620000 3263.060000 1383.720000 3263.540000 ;
+ RECT 1382.620000 3257.620000 1383.720000 3258.100000 ;
+ RECT 1382.620000 3252.180000 1383.720000 3252.660000 ;
+ RECT 1382.620000 3273.940000 1383.720000 3274.420000 ;
+ RECT 1337.620000 3339.220000 1338.720000 3339.700000 ;
+ RECT 1337.620000 3333.780000 1338.720000 3334.260000 ;
+ RECT 1337.620000 3328.340000 1338.720000 3328.820000 ;
+ RECT 1292.620000 3339.220000 1293.720000 3339.700000 ;
+ RECT 1292.620000 3333.780000 1293.720000 3334.260000 ;
+ RECT 1292.620000 3328.340000 1293.720000 3328.820000 ;
+ RECT 1337.620000 3312.020000 1338.720000 3312.500000 ;
+ RECT 1337.620000 3306.580000 1338.720000 3307.060000 ;
+ RECT 1337.620000 3301.140000 1338.720000 3301.620000 ;
+ RECT 1337.620000 3317.460000 1338.720000 3317.940000 ;
+ RECT 1337.620000 3322.900000 1338.720000 3323.380000 ;
+ RECT 1292.620000 3322.900000 1293.720000 3323.380000 ;
+ RECT 1292.620000 3312.020000 1293.720000 3312.500000 ;
+ RECT 1292.620000 3306.580000 1293.720000 3307.060000 ;
+ RECT 1292.620000 3301.140000 1293.720000 3301.620000 ;
+ RECT 1292.620000 3317.460000 1293.720000 3317.940000 ;
+ RECT 1247.620000 3339.220000 1248.720000 3339.700000 ;
+ RECT 1243.490000 3339.220000 1244.490000 3339.700000 ;
+ RECT 1243.490000 3333.780000 1244.490000 3334.260000 ;
+ RECT 1247.620000 3333.780000 1248.720000 3334.260000 ;
+ RECT 1247.620000 3328.340000 1248.720000 3328.820000 ;
+ RECT 1243.490000 3328.340000 1244.490000 3328.820000 ;
+ RECT 1247.620000 3322.900000 1248.720000 3323.380000 ;
+ RECT 1243.490000 3322.900000 1244.490000 3323.380000 ;
+ RECT 1247.620000 3317.460000 1248.720000 3317.940000 ;
+ RECT 1243.490000 3317.460000 1244.490000 3317.940000 ;
+ RECT 1247.620000 3306.580000 1248.720000 3307.060000 ;
+ RECT 1243.490000 3306.580000 1244.490000 3307.060000 ;
+ RECT 1247.620000 3301.140000 1248.720000 3301.620000 ;
+ RECT 1243.490000 3301.140000 1244.490000 3301.620000 ;
+ RECT 1247.620000 3312.020000 1248.720000 3312.500000 ;
+ RECT 1243.490000 3312.020000 1244.490000 3312.500000 ;
+ RECT 1337.620000 3295.700000 1338.720000 3296.180000 ;
+ RECT 1337.620000 3290.260000 1338.720000 3290.740000 ;
+ RECT 1337.620000 3284.820000 1338.720000 3285.300000 ;
+ RECT 1337.620000 3279.380000 1338.720000 3279.860000 ;
+ RECT 1292.620000 3295.700000 1293.720000 3296.180000 ;
+ RECT 1292.620000 3290.260000 1293.720000 3290.740000 ;
+ RECT 1292.620000 3284.820000 1293.720000 3285.300000 ;
+ RECT 1292.620000 3279.380000 1293.720000 3279.860000 ;
+ RECT 1337.620000 3268.500000 1338.720000 3268.980000 ;
+ RECT 1337.620000 3252.180000 1338.720000 3252.660000 ;
+ RECT 1337.620000 3257.620000 1338.720000 3258.100000 ;
+ RECT 1337.620000 3263.060000 1338.720000 3263.540000 ;
+ RECT 1337.620000 3273.940000 1338.720000 3274.420000 ;
+ RECT 1292.620000 3252.180000 1293.720000 3252.660000 ;
+ RECT 1292.620000 3257.620000 1293.720000 3258.100000 ;
+ RECT 1292.620000 3263.060000 1293.720000 3263.540000 ;
+ RECT 1292.620000 3268.500000 1293.720000 3268.980000 ;
+ RECT 1292.620000 3273.940000 1293.720000 3274.420000 ;
+ RECT 1247.620000 3295.700000 1248.720000 3296.180000 ;
+ RECT 1243.490000 3295.700000 1244.490000 3296.180000 ;
+ RECT 1247.620000 3290.260000 1248.720000 3290.740000 ;
+ RECT 1243.490000 3290.260000 1244.490000 3290.740000 ;
+ RECT 1247.620000 3284.820000 1248.720000 3285.300000 ;
+ RECT 1243.490000 3284.820000 1244.490000 3285.300000 ;
+ RECT 1247.620000 3279.380000 1248.720000 3279.860000 ;
+ RECT 1243.490000 3279.380000 1244.490000 3279.860000 ;
+ RECT 1247.620000 3273.940000 1248.720000 3274.420000 ;
+ RECT 1247.620000 3268.500000 1248.720000 3268.980000 ;
+ RECT 1243.490000 3273.940000 1244.490000 3274.420000 ;
+ RECT 1243.490000 3268.500000 1244.490000 3268.980000 ;
+ RECT 1247.620000 3263.060000 1248.720000 3263.540000 ;
+ RECT 1243.490000 3263.060000 1244.490000 3263.540000 ;
+ RECT 1247.620000 3257.620000 1248.720000 3258.100000 ;
+ RECT 1243.490000 3257.620000 1244.490000 3258.100000 ;
+ RECT 1247.620000 3252.180000 1248.720000 3252.660000 ;
+ RECT 1243.490000 3252.180000 1244.490000 3252.660000 ;
+ RECT 1427.620000 3246.740000 1428.720000 3247.220000 ;
+ RECT 1427.620000 3241.300000 1428.720000 3241.780000 ;
+ RECT 1436.930000 3246.740000 1437.930000 3247.220000 ;
+ RECT 1436.930000 3241.300000 1437.930000 3241.780000 ;
+ RECT 1436.930000 3224.980000 1437.930000 3225.460000 ;
+ RECT 1436.930000 3230.420000 1437.930000 3230.900000 ;
+ RECT 1436.930000 3235.860000 1437.930000 3236.340000 ;
+ RECT 1427.620000 3235.860000 1428.720000 3236.340000 ;
+ RECT 1427.620000 3230.420000 1428.720000 3230.900000 ;
+ RECT 1427.620000 3224.980000 1428.720000 3225.460000 ;
+ RECT 1427.620000 3214.100000 1428.720000 3214.580000 ;
+ RECT 1427.620000 3219.540000 1428.720000 3220.020000 ;
+ RECT 1436.930000 3219.540000 1437.930000 3220.020000 ;
+ RECT 1436.930000 3214.100000 1437.930000 3214.580000 ;
+ RECT 1436.930000 3203.220000 1437.930000 3203.700000 ;
+ RECT 1436.930000 3208.660000 1437.930000 3209.140000 ;
+ RECT 1427.620000 3203.220000 1428.720000 3203.700000 ;
+ RECT 1427.620000 3208.660000 1428.720000 3209.140000 ;
+ RECT 1382.620000 3246.740000 1383.720000 3247.220000 ;
+ RECT 1382.620000 3241.300000 1383.720000 3241.780000 ;
+ RECT 1382.620000 3235.860000 1383.720000 3236.340000 ;
+ RECT 1382.620000 3230.420000 1383.720000 3230.900000 ;
+ RECT 1382.620000 3224.980000 1383.720000 3225.460000 ;
+ RECT 1382.620000 3203.220000 1383.720000 3203.700000 ;
+ RECT 1382.620000 3208.660000 1383.720000 3209.140000 ;
+ RECT 1382.620000 3214.100000 1383.720000 3214.580000 ;
+ RECT 1382.620000 3219.540000 1383.720000 3220.020000 ;
+ RECT 1427.620000 3197.780000 1428.720000 3198.260000 ;
+ RECT 1427.620000 3192.340000 1428.720000 3192.820000 ;
+ RECT 1436.930000 3197.780000 1437.930000 3198.260000 ;
+ RECT 1436.930000 3192.340000 1437.930000 3192.820000 ;
+ RECT 1427.620000 3181.460000 1428.720000 3181.940000 ;
+ RECT 1427.620000 3176.020000 1428.720000 3176.500000 ;
+ RECT 1436.930000 3181.460000 1437.930000 3181.940000 ;
+ RECT 1436.930000 3176.020000 1437.930000 3176.500000 ;
+ RECT 1427.620000 3186.900000 1428.720000 3187.380000 ;
+ RECT 1436.930000 3186.900000 1437.930000 3187.380000 ;
+ RECT 1436.930000 3165.140000 1437.930000 3165.620000 ;
+ RECT 1436.930000 3170.580000 1437.930000 3171.060000 ;
+ RECT 1427.620000 3170.580000 1428.720000 3171.060000 ;
+ RECT 1427.620000 3165.140000 1428.720000 3165.620000 ;
+ RECT 1427.620000 3159.700000 1428.720000 3160.180000 ;
+ RECT 1427.620000 3154.260000 1428.720000 3154.740000 ;
+ RECT 1436.930000 3159.700000 1437.930000 3160.180000 ;
+ RECT 1436.930000 3154.260000 1437.930000 3154.740000 ;
+ RECT 1382.620000 3197.780000 1383.720000 3198.260000 ;
+ RECT 1382.620000 3192.340000 1383.720000 3192.820000 ;
+ RECT 1382.620000 3186.900000 1383.720000 3187.380000 ;
+ RECT 1382.620000 3181.460000 1383.720000 3181.940000 ;
+ RECT 1382.620000 3176.020000 1383.720000 3176.500000 ;
+ RECT 1382.620000 3170.580000 1383.720000 3171.060000 ;
+ RECT 1382.620000 3165.140000 1383.720000 3165.620000 ;
+ RECT 1382.620000 3159.700000 1383.720000 3160.180000 ;
+ RECT 1382.620000 3154.260000 1383.720000 3154.740000 ;
+ RECT 1337.620000 3246.740000 1338.720000 3247.220000 ;
+ RECT 1337.620000 3241.300000 1338.720000 3241.780000 ;
+ RECT 1337.620000 3235.860000 1338.720000 3236.340000 ;
+ RECT 1337.620000 3230.420000 1338.720000 3230.900000 ;
+ RECT 1337.620000 3224.980000 1338.720000 3225.460000 ;
+ RECT 1292.620000 3246.740000 1293.720000 3247.220000 ;
+ RECT 1292.620000 3241.300000 1293.720000 3241.780000 ;
+ RECT 1292.620000 3235.860000 1293.720000 3236.340000 ;
+ RECT 1292.620000 3230.420000 1293.720000 3230.900000 ;
+ RECT 1292.620000 3224.980000 1293.720000 3225.460000 ;
+ RECT 1337.620000 3219.540000 1338.720000 3220.020000 ;
+ RECT 1337.620000 3214.100000 1338.720000 3214.580000 ;
+ RECT 1337.620000 3208.660000 1338.720000 3209.140000 ;
+ RECT 1337.620000 3203.220000 1338.720000 3203.700000 ;
+ RECT 1292.620000 3214.100000 1293.720000 3214.580000 ;
+ RECT 1292.620000 3208.660000 1293.720000 3209.140000 ;
+ RECT 1292.620000 3203.220000 1293.720000 3203.700000 ;
+ RECT 1292.620000 3219.540000 1293.720000 3220.020000 ;
+ RECT 1247.620000 3246.740000 1248.720000 3247.220000 ;
+ RECT 1243.490000 3246.740000 1244.490000 3247.220000 ;
+ RECT 1247.620000 3241.300000 1248.720000 3241.780000 ;
+ RECT 1243.490000 3241.300000 1244.490000 3241.780000 ;
+ RECT 1247.620000 3235.860000 1248.720000 3236.340000 ;
+ RECT 1243.490000 3235.860000 1244.490000 3236.340000 ;
+ RECT 1247.620000 3224.980000 1248.720000 3225.460000 ;
+ RECT 1243.490000 3224.980000 1244.490000 3225.460000 ;
+ RECT 1243.490000 3230.420000 1244.490000 3230.900000 ;
+ RECT 1247.620000 3230.420000 1248.720000 3230.900000 ;
+ RECT 1247.620000 3219.540000 1248.720000 3220.020000 ;
+ RECT 1243.490000 3219.540000 1244.490000 3220.020000 ;
+ RECT 1247.620000 3214.100000 1248.720000 3214.580000 ;
+ RECT 1243.490000 3214.100000 1244.490000 3214.580000 ;
+ RECT 1247.620000 3208.660000 1248.720000 3209.140000 ;
+ RECT 1243.490000 3208.660000 1244.490000 3209.140000 ;
+ RECT 1247.620000 3203.220000 1248.720000 3203.700000 ;
+ RECT 1243.490000 3203.220000 1244.490000 3203.700000 ;
+ RECT 1337.620000 3197.780000 1338.720000 3198.260000 ;
+ RECT 1337.620000 3192.340000 1338.720000 3192.820000 ;
+ RECT 1337.620000 3186.900000 1338.720000 3187.380000 ;
+ RECT 1337.620000 3181.460000 1338.720000 3181.940000 ;
+ RECT 1337.620000 3176.020000 1338.720000 3176.500000 ;
+ RECT 1292.620000 3197.780000 1293.720000 3198.260000 ;
+ RECT 1292.620000 3192.340000 1293.720000 3192.820000 ;
+ RECT 1292.620000 3186.900000 1293.720000 3187.380000 ;
+ RECT 1292.620000 3181.460000 1293.720000 3181.940000 ;
+ RECT 1292.620000 3176.020000 1293.720000 3176.500000 ;
+ RECT 1337.620000 3154.260000 1338.720000 3154.740000 ;
+ RECT 1337.620000 3159.700000 1338.720000 3160.180000 ;
+ RECT 1337.620000 3165.140000 1338.720000 3165.620000 ;
+ RECT 1337.620000 3170.580000 1338.720000 3171.060000 ;
+ RECT 1292.620000 3154.260000 1293.720000 3154.740000 ;
+ RECT 1292.620000 3159.700000 1293.720000 3160.180000 ;
+ RECT 1292.620000 3165.140000 1293.720000 3165.620000 ;
+ RECT 1292.620000 3170.580000 1293.720000 3171.060000 ;
+ RECT 1247.620000 3197.780000 1248.720000 3198.260000 ;
+ RECT 1243.490000 3197.780000 1244.490000 3198.260000 ;
+ RECT 1247.620000 3192.340000 1248.720000 3192.820000 ;
+ RECT 1243.490000 3192.340000 1244.490000 3192.820000 ;
+ RECT 1247.620000 3181.460000 1248.720000 3181.940000 ;
+ RECT 1243.490000 3181.460000 1244.490000 3181.940000 ;
+ RECT 1247.620000 3176.020000 1248.720000 3176.500000 ;
+ RECT 1243.490000 3176.020000 1244.490000 3176.500000 ;
+ RECT 1247.620000 3186.900000 1248.720000 3187.380000 ;
+ RECT 1243.490000 3186.900000 1244.490000 3187.380000 ;
+ RECT 1247.620000 3170.580000 1248.720000 3171.060000 ;
+ RECT 1243.490000 3170.580000 1244.490000 3171.060000 ;
+ RECT 1247.620000 3165.140000 1248.720000 3165.620000 ;
+ RECT 1243.490000 3165.140000 1244.490000 3165.620000 ;
+ RECT 1247.620000 3159.700000 1248.720000 3160.180000 ;
+ RECT 1247.620000 3154.260000 1248.720000 3154.740000 ;
+ RECT 1243.490000 3159.700000 1244.490000 3160.180000 ;
+ RECT 1243.490000 3154.260000 1244.490000 3154.740000 ;
+ RECT 1240.660000 3344.620000 1440.760000 3345.620000 ;
+ RECT 1240.660000 3152.250000 1440.760000 3153.250000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 3149.400000 1244.490000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 3348.660000 1244.490000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 3149.400000 1437.930000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 3348.660000 1437.930000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 3152.250000 1241.660000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 3152.250000 1440.760000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 3344.620000 1241.660000 3345.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 3344.620000 1440.760000 3345.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 2951.990000 1428.720000 3145.360000 ;
+ RECT 1382.620000 2951.990000 1383.720000 3145.360000 ;
+ RECT 1436.930000 2949.140000 1437.930000 3149.400000 ;
+ RECT 1337.620000 2951.990000 1338.720000 3145.360000 ;
+ RECT 1292.620000 2951.990000 1293.720000 3145.360000 ;
+ RECT 1247.620000 2951.990000 1248.720000 3145.360000 ;
+ RECT 1243.490000 2949.140000 1244.490000 3149.400000 ;
+ LAYER met3 ;
+ RECT 1427.620000 3138.960000 1428.720000 3139.440000 ;
+ RECT 1436.930000 3138.960000 1437.930000 3139.440000 ;
+ RECT 1436.930000 3128.080000 1437.930000 3128.560000 ;
+ RECT 1436.930000 3133.520000 1437.930000 3134.000000 ;
+ RECT 1427.620000 3133.520000 1428.720000 3134.000000 ;
+ RECT 1427.620000 3128.080000 1428.720000 3128.560000 ;
+ RECT 1427.620000 3122.640000 1428.720000 3123.120000 ;
+ RECT 1427.620000 3117.200000 1428.720000 3117.680000 ;
+ RECT 1436.930000 3122.640000 1437.930000 3123.120000 ;
+ RECT 1436.930000 3117.200000 1437.930000 3117.680000 ;
+ RECT 1427.620000 3100.880000 1428.720000 3101.360000 ;
+ RECT 1427.620000 3106.320000 1428.720000 3106.800000 ;
+ RECT 1436.930000 3106.320000 1437.930000 3106.800000 ;
+ RECT 1436.930000 3100.880000 1437.930000 3101.360000 ;
+ RECT 1427.620000 3111.760000 1428.720000 3112.240000 ;
+ RECT 1436.930000 3111.760000 1437.930000 3112.240000 ;
+ RECT 1382.620000 3138.960000 1383.720000 3139.440000 ;
+ RECT 1382.620000 3133.520000 1383.720000 3134.000000 ;
+ RECT 1382.620000 3128.080000 1383.720000 3128.560000 ;
+ RECT 1382.620000 3122.640000 1383.720000 3123.120000 ;
+ RECT 1382.620000 3100.880000 1383.720000 3101.360000 ;
+ RECT 1382.620000 3106.320000 1383.720000 3106.800000 ;
+ RECT 1382.620000 3111.760000 1383.720000 3112.240000 ;
+ RECT 1382.620000 3117.200000 1383.720000 3117.680000 ;
+ RECT 1436.930000 3090.000000 1437.930000 3090.480000 ;
+ RECT 1436.930000 3095.440000 1437.930000 3095.920000 ;
+ RECT 1427.620000 3095.440000 1428.720000 3095.920000 ;
+ RECT 1427.620000 3090.000000 1428.720000 3090.480000 ;
+ RECT 1427.620000 3084.560000 1428.720000 3085.040000 ;
+ RECT 1427.620000 3079.120000 1428.720000 3079.600000 ;
+ RECT 1436.930000 3084.560000 1437.930000 3085.040000 ;
+ RECT 1436.930000 3079.120000 1437.930000 3079.600000 ;
+ RECT 1436.930000 3062.800000 1437.930000 3063.280000 ;
+ RECT 1436.930000 3068.240000 1437.930000 3068.720000 ;
+ RECT 1436.930000 3073.680000 1437.930000 3074.160000 ;
+ RECT 1427.620000 3068.240000 1428.720000 3068.720000 ;
+ RECT 1427.620000 3062.800000 1428.720000 3063.280000 ;
+ RECT 1427.620000 3073.680000 1428.720000 3074.160000 ;
+ RECT 1427.620000 3057.360000 1428.720000 3057.840000 ;
+ RECT 1427.620000 3051.920000 1428.720000 3052.400000 ;
+ RECT 1436.930000 3057.360000 1437.930000 3057.840000 ;
+ RECT 1436.930000 3051.920000 1437.930000 3052.400000 ;
+ RECT 1382.620000 3095.440000 1383.720000 3095.920000 ;
+ RECT 1382.620000 3090.000000 1383.720000 3090.480000 ;
+ RECT 1382.620000 3084.560000 1383.720000 3085.040000 ;
+ RECT 1382.620000 3079.120000 1383.720000 3079.600000 ;
+ RECT 1382.620000 3068.240000 1383.720000 3068.720000 ;
+ RECT 1382.620000 3062.800000 1383.720000 3063.280000 ;
+ RECT 1382.620000 3057.360000 1383.720000 3057.840000 ;
+ RECT 1382.620000 3051.920000 1383.720000 3052.400000 ;
+ RECT 1382.620000 3073.680000 1383.720000 3074.160000 ;
+ RECT 1337.620000 3138.960000 1338.720000 3139.440000 ;
+ RECT 1337.620000 3133.520000 1338.720000 3134.000000 ;
+ RECT 1337.620000 3128.080000 1338.720000 3128.560000 ;
+ RECT 1292.620000 3138.960000 1293.720000 3139.440000 ;
+ RECT 1292.620000 3133.520000 1293.720000 3134.000000 ;
+ RECT 1292.620000 3128.080000 1293.720000 3128.560000 ;
+ RECT 1337.620000 3111.760000 1338.720000 3112.240000 ;
+ RECT 1337.620000 3106.320000 1338.720000 3106.800000 ;
+ RECT 1337.620000 3100.880000 1338.720000 3101.360000 ;
+ RECT 1337.620000 3117.200000 1338.720000 3117.680000 ;
+ RECT 1337.620000 3122.640000 1338.720000 3123.120000 ;
+ RECT 1292.620000 3122.640000 1293.720000 3123.120000 ;
+ RECT 1292.620000 3111.760000 1293.720000 3112.240000 ;
+ RECT 1292.620000 3106.320000 1293.720000 3106.800000 ;
+ RECT 1292.620000 3100.880000 1293.720000 3101.360000 ;
+ RECT 1292.620000 3117.200000 1293.720000 3117.680000 ;
+ RECT 1247.620000 3138.960000 1248.720000 3139.440000 ;
+ RECT 1243.490000 3138.960000 1244.490000 3139.440000 ;
+ RECT 1243.490000 3133.520000 1244.490000 3134.000000 ;
+ RECT 1247.620000 3133.520000 1248.720000 3134.000000 ;
+ RECT 1247.620000 3128.080000 1248.720000 3128.560000 ;
+ RECT 1243.490000 3128.080000 1244.490000 3128.560000 ;
+ RECT 1247.620000 3122.640000 1248.720000 3123.120000 ;
+ RECT 1243.490000 3122.640000 1244.490000 3123.120000 ;
+ RECT 1247.620000 3117.200000 1248.720000 3117.680000 ;
+ RECT 1243.490000 3117.200000 1244.490000 3117.680000 ;
+ RECT 1247.620000 3106.320000 1248.720000 3106.800000 ;
+ RECT 1243.490000 3106.320000 1244.490000 3106.800000 ;
+ RECT 1247.620000 3100.880000 1248.720000 3101.360000 ;
+ RECT 1243.490000 3100.880000 1244.490000 3101.360000 ;
+ RECT 1247.620000 3111.760000 1248.720000 3112.240000 ;
+ RECT 1243.490000 3111.760000 1244.490000 3112.240000 ;
+ RECT 1337.620000 3095.440000 1338.720000 3095.920000 ;
+ RECT 1337.620000 3090.000000 1338.720000 3090.480000 ;
+ RECT 1337.620000 3084.560000 1338.720000 3085.040000 ;
+ RECT 1337.620000 3079.120000 1338.720000 3079.600000 ;
+ RECT 1292.620000 3095.440000 1293.720000 3095.920000 ;
+ RECT 1292.620000 3090.000000 1293.720000 3090.480000 ;
+ RECT 1292.620000 3084.560000 1293.720000 3085.040000 ;
+ RECT 1292.620000 3079.120000 1293.720000 3079.600000 ;
+ RECT 1337.620000 3068.240000 1338.720000 3068.720000 ;
+ RECT 1337.620000 3051.920000 1338.720000 3052.400000 ;
+ RECT 1337.620000 3057.360000 1338.720000 3057.840000 ;
+ RECT 1337.620000 3062.800000 1338.720000 3063.280000 ;
+ RECT 1337.620000 3073.680000 1338.720000 3074.160000 ;
+ RECT 1292.620000 3051.920000 1293.720000 3052.400000 ;
+ RECT 1292.620000 3057.360000 1293.720000 3057.840000 ;
+ RECT 1292.620000 3062.800000 1293.720000 3063.280000 ;
+ RECT 1292.620000 3068.240000 1293.720000 3068.720000 ;
+ RECT 1292.620000 3073.680000 1293.720000 3074.160000 ;
+ RECT 1247.620000 3095.440000 1248.720000 3095.920000 ;
+ RECT 1243.490000 3095.440000 1244.490000 3095.920000 ;
+ RECT 1247.620000 3090.000000 1248.720000 3090.480000 ;
+ RECT 1243.490000 3090.000000 1244.490000 3090.480000 ;
+ RECT 1247.620000 3084.560000 1248.720000 3085.040000 ;
+ RECT 1243.490000 3084.560000 1244.490000 3085.040000 ;
+ RECT 1247.620000 3079.120000 1248.720000 3079.600000 ;
+ RECT 1243.490000 3079.120000 1244.490000 3079.600000 ;
+ RECT 1247.620000 3073.680000 1248.720000 3074.160000 ;
+ RECT 1247.620000 3068.240000 1248.720000 3068.720000 ;
+ RECT 1243.490000 3073.680000 1244.490000 3074.160000 ;
+ RECT 1243.490000 3068.240000 1244.490000 3068.720000 ;
+ RECT 1247.620000 3062.800000 1248.720000 3063.280000 ;
+ RECT 1243.490000 3062.800000 1244.490000 3063.280000 ;
+ RECT 1247.620000 3057.360000 1248.720000 3057.840000 ;
+ RECT 1243.490000 3057.360000 1244.490000 3057.840000 ;
+ RECT 1247.620000 3051.920000 1248.720000 3052.400000 ;
+ RECT 1243.490000 3051.920000 1244.490000 3052.400000 ;
+ RECT 1427.620000 3046.480000 1428.720000 3046.960000 ;
+ RECT 1427.620000 3041.040000 1428.720000 3041.520000 ;
+ RECT 1436.930000 3046.480000 1437.930000 3046.960000 ;
+ RECT 1436.930000 3041.040000 1437.930000 3041.520000 ;
+ RECT 1436.930000 3024.720000 1437.930000 3025.200000 ;
+ RECT 1436.930000 3030.160000 1437.930000 3030.640000 ;
+ RECT 1436.930000 3035.600000 1437.930000 3036.080000 ;
+ RECT 1427.620000 3035.600000 1428.720000 3036.080000 ;
+ RECT 1427.620000 3030.160000 1428.720000 3030.640000 ;
+ RECT 1427.620000 3024.720000 1428.720000 3025.200000 ;
+ RECT 1427.620000 3013.840000 1428.720000 3014.320000 ;
+ RECT 1427.620000 3019.280000 1428.720000 3019.760000 ;
+ RECT 1436.930000 3019.280000 1437.930000 3019.760000 ;
+ RECT 1436.930000 3013.840000 1437.930000 3014.320000 ;
+ RECT 1436.930000 3002.960000 1437.930000 3003.440000 ;
+ RECT 1436.930000 3008.400000 1437.930000 3008.880000 ;
+ RECT 1427.620000 3002.960000 1428.720000 3003.440000 ;
+ RECT 1427.620000 3008.400000 1428.720000 3008.880000 ;
+ RECT 1382.620000 3046.480000 1383.720000 3046.960000 ;
+ RECT 1382.620000 3041.040000 1383.720000 3041.520000 ;
+ RECT 1382.620000 3035.600000 1383.720000 3036.080000 ;
+ RECT 1382.620000 3030.160000 1383.720000 3030.640000 ;
+ RECT 1382.620000 3024.720000 1383.720000 3025.200000 ;
+ RECT 1382.620000 3002.960000 1383.720000 3003.440000 ;
+ RECT 1382.620000 3008.400000 1383.720000 3008.880000 ;
+ RECT 1382.620000 3013.840000 1383.720000 3014.320000 ;
+ RECT 1382.620000 3019.280000 1383.720000 3019.760000 ;
+ RECT 1427.620000 2997.520000 1428.720000 2998.000000 ;
+ RECT 1427.620000 2992.080000 1428.720000 2992.560000 ;
+ RECT 1436.930000 2997.520000 1437.930000 2998.000000 ;
+ RECT 1436.930000 2992.080000 1437.930000 2992.560000 ;
+ RECT 1427.620000 2981.200000 1428.720000 2981.680000 ;
+ RECT 1427.620000 2975.760000 1428.720000 2976.240000 ;
+ RECT 1436.930000 2981.200000 1437.930000 2981.680000 ;
+ RECT 1436.930000 2975.760000 1437.930000 2976.240000 ;
+ RECT 1427.620000 2986.640000 1428.720000 2987.120000 ;
+ RECT 1436.930000 2986.640000 1437.930000 2987.120000 ;
+ RECT 1436.930000 2964.880000 1437.930000 2965.360000 ;
+ RECT 1436.930000 2970.320000 1437.930000 2970.800000 ;
+ RECT 1427.620000 2970.320000 1428.720000 2970.800000 ;
+ RECT 1427.620000 2964.880000 1428.720000 2965.360000 ;
+ RECT 1427.620000 2959.440000 1428.720000 2959.920000 ;
+ RECT 1427.620000 2954.000000 1428.720000 2954.480000 ;
+ RECT 1436.930000 2959.440000 1437.930000 2959.920000 ;
+ RECT 1436.930000 2954.000000 1437.930000 2954.480000 ;
+ RECT 1382.620000 2997.520000 1383.720000 2998.000000 ;
+ RECT 1382.620000 2992.080000 1383.720000 2992.560000 ;
+ RECT 1382.620000 2986.640000 1383.720000 2987.120000 ;
+ RECT 1382.620000 2981.200000 1383.720000 2981.680000 ;
+ RECT 1382.620000 2975.760000 1383.720000 2976.240000 ;
+ RECT 1382.620000 2970.320000 1383.720000 2970.800000 ;
+ RECT 1382.620000 2964.880000 1383.720000 2965.360000 ;
+ RECT 1382.620000 2959.440000 1383.720000 2959.920000 ;
+ RECT 1382.620000 2954.000000 1383.720000 2954.480000 ;
+ RECT 1337.620000 3046.480000 1338.720000 3046.960000 ;
+ RECT 1337.620000 3041.040000 1338.720000 3041.520000 ;
+ RECT 1337.620000 3035.600000 1338.720000 3036.080000 ;
+ RECT 1337.620000 3030.160000 1338.720000 3030.640000 ;
+ RECT 1337.620000 3024.720000 1338.720000 3025.200000 ;
+ RECT 1292.620000 3046.480000 1293.720000 3046.960000 ;
+ RECT 1292.620000 3041.040000 1293.720000 3041.520000 ;
+ RECT 1292.620000 3035.600000 1293.720000 3036.080000 ;
+ RECT 1292.620000 3030.160000 1293.720000 3030.640000 ;
+ RECT 1292.620000 3024.720000 1293.720000 3025.200000 ;
+ RECT 1337.620000 3019.280000 1338.720000 3019.760000 ;
+ RECT 1337.620000 3013.840000 1338.720000 3014.320000 ;
+ RECT 1337.620000 3008.400000 1338.720000 3008.880000 ;
+ RECT 1337.620000 3002.960000 1338.720000 3003.440000 ;
+ RECT 1292.620000 3013.840000 1293.720000 3014.320000 ;
+ RECT 1292.620000 3008.400000 1293.720000 3008.880000 ;
+ RECT 1292.620000 3002.960000 1293.720000 3003.440000 ;
+ RECT 1292.620000 3019.280000 1293.720000 3019.760000 ;
+ RECT 1247.620000 3046.480000 1248.720000 3046.960000 ;
+ RECT 1243.490000 3046.480000 1244.490000 3046.960000 ;
+ RECT 1247.620000 3041.040000 1248.720000 3041.520000 ;
+ RECT 1243.490000 3041.040000 1244.490000 3041.520000 ;
+ RECT 1247.620000 3035.600000 1248.720000 3036.080000 ;
+ RECT 1243.490000 3035.600000 1244.490000 3036.080000 ;
+ RECT 1247.620000 3024.720000 1248.720000 3025.200000 ;
+ RECT 1243.490000 3024.720000 1244.490000 3025.200000 ;
+ RECT 1243.490000 3030.160000 1244.490000 3030.640000 ;
+ RECT 1247.620000 3030.160000 1248.720000 3030.640000 ;
+ RECT 1247.620000 3019.280000 1248.720000 3019.760000 ;
+ RECT 1243.490000 3019.280000 1244.490000 3019.760000 ;
+ RECT 1247.620000 3013.840000 1248.720000 3014.320000 ;
+ RECT 1243.490000 3013.840000 1244.490000 3014.320000 ;
+ RECT 1247.620000 3008.400000 1248.720000 3008.880000 ;
+ RECT 1243.490000 3008.400000 1244.490000 3008.880000 ;
+ RECT 1247.620000 3002.960000 1248.720000 3003.440000 ;
+ RECT 1243.490000 3002.960000 1244.490000 3003.440000 ;
+ RECT 1337.620000 2997.520000 1338.720000 2998.000000 ;
+ RECT 1337.620000 2992.080000 1338.720000 2992.560000 ;
+ RECT 1337.620000 2986.640000 1338.720000 2987.120000 ;
+ RECT 1337.620000 2981.200000 1338.720000 2981.680000 ;
+ RECT 1337.620000 2975.760000 1338.720000 2976.240000 ;
+ RECT 1292.620000 2997.520000 1293.720000 2998.000000 ;
+ RECT 1292.620000 2992.080000 1293.720000 2992.560000 ;
+ RECT 1292.620000 2986.640000 1293.720000 2987.120000 ;
+ RECT 1292.620000 2981.200000 1293.720000 2981.680000 ;
+ RECT 1292.620000 2975.760000 1293.720000 2976.240000 ;
+ RECT 1337.620000 2954.000000 1338.720000 2954.480000 ;
+ RECT 1337.620000 2959.440000 1338.720000 2959.920000 ;
+ RECT 1337.620000 2964.880000 1338.720000 2965.360000 ;
+ RECT 1337.620000 2970.320000 1338.720000 2970.800000 ;
+ RECT 1292.620000 2954.000000 1293.720000 2954.480000 ;
+ RECT 1292.620000 2959.440000 1293.720000 2959.920000 ;
+ RECT 1292.620000 2964.880000 1293.720000 2965.360000 ;
+ RECT 1292.620000 2970.320000 1293.720000 2970.800000 ;
+ RECT 1247.620000 2997.520000 1248.720000 2998.000000 ;
+ RECT 1243.490000 2997.520000 1244.490000 2998.000000 ;
+ RECT 1247.620000 2992.080000 1248.720000 2992.560000 ;
+ RECT 1243.490000 2992.080000 1244.490000 2992.560000 ;
+ RECT 1247.620000 2981.200000 1248.720000 2981.680000 ;
+ RECT 1243.490000 2981.200000 1244.490000 2981.680000 ;
+ RECT 1247.620000 2975.760000 1248.720000 2976.240000 ;
+ RECT 1243.490000 2975.760000 1244.490000 2976.240000 ;
+ RECT 1247.620000 2986.640000 1248.720000 2987.120000 ;
+ RECT 1243.490000 2986.640000 1244.490000 2987.120000 ;
+ RECT 1247.620000 2970.320000 1248.720000 2970.800000 ;
+ RECT 1243.490000 2970.320000 1244.490000 2970.800000 ;
+ RECT 1247.620000 2964.880000 1248.720000 2965.360000 ;
+ RECT 1243.490000 2964.880000 1244.490000 2965.360000 ;
+ RECT 1247.620000 2959.440000 1248.720000 2959.920000 ;
+ RECT 1247.620000 2954.000000 1248.720000 2954.480000 ;
+ RECT 1243.490000 2959.440000 1244.490000 2959.920000 ;
+ RECT 1243.490000 2954.000000 1244.490000 2954.480000 ;
+ RECT 1240.660000 3144.360000 1440.760000 3145.360000 ;
+ RECT 1240.660000 2951.990000 1440.760000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 2949.140000 1244.490000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 3148.400000 1244.490000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 2949.140000 1437.930000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 3148.400000 1437.930000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2951.990000 1241.660000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2951.990000 1440.760000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 3144.360000 1241.660000 3145.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 3144.360000 1440.760000 3145.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 2751.730000 1428.720000 2945.100000 ;
+ RECT 1382.620000 2751.730000 1383.720000 2945.100000 ;
+ RECT 1436.930000 2748.880000 1437.930000 2949.140000 ;
+ RECT 1337.620000 2751.730000 1338.720000 2945.100000 ;
+ RECT 1292.620000 2751.730000 1293.720000 2945.100000 ;
+ RECT 1247.620000 2751.730000 1248.720000 2945.100000 ;
+ RECT 1243.490000 2748.880000 1244.490000 2949.140000 ;
+ LAYER met3 ;
+ RECT 1427.620000 2938.700000 1428.720000 2939.180000 ;
+ RECT 1436.930000 2938.700000 1437.930000 2939.180000 ;
+ RECT 1436.930000 2927.820000 1437.930000 2928.300000 ;
+ RECT 1436.930000 2933.260000 1437.930000 2933.740000 ;
+ RECT 1427.620000 2933.260000 1428.720000 2933.740000 ;
+ RECT 1427.620000 2927.820000 1428.720000 2928.300000 ;
+ RECT 1427.620000 2922.380000 1428.720000 2922.860000 ;
+ RECT 1427.620000 2916.940000 1428.720000 2917.420000 ;
+ RECT 1436.930000 2922.380000 1437.930000 2922.860000 ;
+ RECT 1436.930000 2916.940000 1437.930000 2917.420000 ;
+ RECT 1427.620000 2900.620000 1428.720000 2901.100000 ;
+ RECT 1427.620000 2906.060000 1428.720000 2906.540000 ;
+ RECT 1436.930000 2906.060000 1437.930000 2906.540000 ;
+ RECT 1436.930000 2900.620000 1437.930000 2901.100000 ;
+ RECT 1427.620000 2911.500000 1428.720000 2911.980000 ;
+ RECT 1436.930000 2911.500000 1437.930000 2911.980000 ;
+ RECT 1382.620000 2938.700000 1383.720000 2939.180000 ;
+ RECT 1382.620000 2933.260000 1383.720000 2933.740000 ;
+ RECT 1382.620000 2927.820000 1383.720000 2928.300000 ;
+ RECT 1382.620000 2922.380000 1383.720000 2922.860000 ;
+ RECT 1382.620000 2900.620000 1383.720000 2901.100000 ;
+ RECT 1382.620000 2906.060000 1383.720000 2906.540000 ;
+ RECT 1382.620000 2911.500000 1383.720000 2911.980000 ;
+ RECT 1382.620000 2916.940000 1383.720000 2917.420000 ;
+ RECT 1436.930000 2889.740000 1437.930000 2890.220000 ;
+ RECT 1436.930000 2895.180000 1437.930000 2895.660000 ;
+ RECT 1427.620000 2895.180000 1428.720000 2895.660000 ;
+ RECT 1427.620000 2889.740000 1428.720000 2890.220000 ;
+ RECT 1427.620000 2884.300000 1428.720000 2884.780000 ;
+ RECT 1427.620000 2878.860000 1428.720000 2879.340000 ;
+ RECT 1436.930000 2884.300000 1437.930000 2884.780000 ;
+ RECT 1436.930000 2878.860000 1437.930000 2879.340000 ;
+ RECT 1436.930000 2862.540000 1437.930000 2863.020000 ;
+ RECT 1436.930000 2867.980000 1437.930000 2868.460000 ;
+ RECT 1436.930000 2873.420000 1437.930000 2873.900000 ;
+ RECT 1427.620000 2867.980000 1428.720000 2868.460000 ;
+ RECT 1427.620000 2862.540000 1428.720000 2863.020000 ;
+ RECT 1427.620000 2873.420000 1428.720000 2873.900000 ;
+ RECT 1427.620000 2857.100000 1428.720000 2857.580000 ;
+ RECT 1427.620000 2851.660000 1428.720000 2852.140000 ;
+ RECT 1436.930000 2857.100000 1437.930000 2857.580000 ;
+ RECT 1436.930000 2851.660000 1437.930000 2852.140000 ;
+ RECT 1382.620000 2895.180000 1383.720000 2895.660000 ;
+ RECT 1382.620000 2889.740000 1383.720000 2890.220000 ;
+ RECT 1382.620000 2884.300000 1383.720000 2884.780000 ;
+ RECT 1382.620000 2878.860000 1383.720000 2879.340000 ;
+ RECT 1382.620000 2867.980000 1383.720000 2868.460000 ;
+ RECT 1382.620000 2862.540000 1383.720000 2863.020000 ;
+ RECT 1382.620000 2857.100000 1383.720000 2857.580000 ;
+ RECT 1382.620000 2851.660000 1383.720000 2852.140000 ;
+ RECT 1382.620000 2873.420000 1383.720000 2873.900000 ;
+ RECT 1337.620000 2938.700000 1338.720000 2939.180000 ;
+ RECT 1337.620000 2933.260000 1338.720000 2933.740000 ;
+ RECT 1337.620000 2927.820000 1338.720000 2928.300000 ;
+ RECT 1292.620000 2938.700000 1293.720000 2939.180000 ;
+ RECT 1292.620000 2933.260000 1293.720000 2933.740000 ;
+ RECT 1292.620000 2927.820000 1293.720000 2928.300000 ;
+ RECT 1337.620000 2911.500000 1338.720000 2911.980000 ;
+ RECT 1337.620000 2906.060000 1338.720000 2906.540000 ;
+ RECT 1337.620000 2900.620000 1338.720000 2901.100000 ;
+ RECT 1337.620000 2916.940000 1338.720000 2917.420000 ;
+ RECT 1337.620000 2922.380000 1338.720000 2922.860000 ;
+ RECT 1292.620000 2922.380000 1293.720000 2922.860000 ;
+ RECT 1292.620000 2911.500000 1293.720000 2911.980000 ;
+ RECT 1292.620000 2906.060000 1293.720000 2906.540000 ;
+ RECT 1292.620000 2900.620000 1293.720000 2901.100000 ;
+ RECT 1292.620000 2916.940000 1293.720000 2917.420000 ;
+ RECT 1247.620000 2938.700000 1248.720000 2939.180000 ;
+ RECT 1243.490000 2938.700000 1244.490000 2939.180000 ;
+ RECT 1243.490000 2933.260000 1244.490000 2933.740000 ;
+ RECT 1247.620000 2933.260000 1248.720000 2933.740000 ;
+ RECT 1247.620000 2927.820000 1248.720000 2928.300000 ;
+ RECT 1243.490000 2927.820000 1244.490000 2928.300000 ;
+ RECT 1247.620000 2922.380000 1248.720000 2922.860000 ;
+ RECT 1243.490000 2922.380000 1244.490000 2922.860000 ;
+ RECT 1247.620000 2916.940000 1248.720000 2917.420000 ;
+ RECT 1243.490000 2916.940000 1244.490000 2917.420000 ;
+ RECT 1247.620000 2906.060000 1248.720000 2906.540000 ;
+ RECT 1243.490000 2906.060000 1244.490000 2906.540000 ;
+ RECT 1247.620000 2900.620000 1248.720000 2901.100000 ;
+ RECT 1243.490000 2900.620000 1244.490000 2901.100000 ;
+ RECT 1247.620000 2911.500000 1248.720000 2911.980000 ;
+ RECT 1243.490000 2911.500000 1244.490000 2911.980000 ;
+ RECT 1337.620000 2895.180000 1338.720000 2895.660000 ;
+ RECT 1337.620000 2889.740000 1338.720000 2890.220000 ;
+ RECT 1337.620000 2884.300000 1338.720000 2884.780000 ;
+ RECT 1337.620000 2878.860000 1338.720000 2879.340000 ;
+ RECT 1292.620000 2895.180000 1293.720000 2895.660000 ;
+ RECT 1292.620000 2889.740000 1293.720000 2890.220000 ;
+ RECT 1292.620000 2884.300000 1293.720000 2884.780000 ;
+ RECT 1292.620000 2878.860000 1293.720000 2879.340000 ;
+ RECT 1337.620000 2867.980000 1338.720000 2868.460000 ;
+ RECT 1337.620000 2851.660000 1338.720000 2852.140000 ;
+ RECT 1337.620000 2857.100000 1338.720000 2857.580000 ;
+ RECT 1337.620000 2862.540000 1338.720000 2863.020000 ;
+ RECT 1337.620000 2873.420000 1338.720000 2873.900000 ;
+ RECT 1292.620000 2851.660000 1293.720000 2852.140000 ;
+ RECT 1292.620000 2857.100000 1293.720000 2857.580000 ;
+ RECT 1292.620000 2862.540000 1293.720000 2863.020000 ;
+ RECT 1292.620000 2867.980000 1293.720000 2868.460000 ;
+ RECT 1292.620000 2873.420000 1293.720000 2873.900000 ;
+ RECT 1247.620000 2895.180000 1248.720000 2895.660000 ;
+ RECT 1243.490000 2895.180000 1244.490000 2895.660000 ;
+ RECT 1247.620000 2889.740000 1248.720000 2890.220000 ;
+ RECT 1243.490000 2889.740000 1244.490000 2890.220000 ;
+ RECT 1247.620000 2884.300000 1248.720000 2884.780000 ;
+ RECT 1243.490000 2884.300000 1244.490000 2884.780000 ;
+ RECT 1247.620000 2878.860000 1248.720000 2879.340000 ;
+ RECT 1243.490000 2878.860000 1244.490000 2879.340000 ;
+ RECT 1247.620000 2873.420000 1248.720000 2873.900000 ;
+ RECT 1247.620000 2867.980000 1248.720000 2868.460000 ;
+ RECT 1243.490000 2873.420000 1244.490000 2873.900000 ;
+ RECT 1243.490000 2867.980000 1244.490000 2868.460000 ;
+ RECT 1247.620000 2862.540000 1248.720000 2863.020000 ;
+ RECT 1243.490000 2862.540000 1244.490000 2863.020000 ;
+ RECT 1247.620000 2857.100000 1248.720000 2857.580000 ;
+ RECT 1243.490000 2857.100000 1244.490000 2857.580000 ;
+ RECT 1247.620000 2851.660000 1248.720000 2852.140000 ;
+ RECT 1243.490000 2851.660000 1244.490000 2852.140000 ;
+ RECT 1427.620000 2846.220000 1428.720000 2846.700000 ;
+ RECT 1427.620000 2840.780000 1428.720000 2841.260000 ;
+ RECT 1436.930000 2846.220000 1437.930000 2846.700000 ;
+ RECT 1436.930000 2840.780000 1437.930000 2841.260000 ;
+ RECT 1436.930000 2824.460000 1437.930000 2824.940000 ;
+ RECT 1436.930000 2829.900000 1437.930000 2830.380000 ;
+ RECT 1436.930000 2835.340000 1437.930000 2835.820000 ;
+ RECT 1427.620000 2835.340000 1428.720000 2835.820000 ;
+ RECT 1427.620000 2829.900000 1428.720000 2830.380000 ;
+ RECT 1427.620000 2824.460000 1428.720000 2824.940000 ;
+ RECT 1427.620000 2813.580000 1428.720000 2814.060000 ;
+ RECT 1427.620000 2819.020000 1428.720000 2819.500000 ;
+ RECT 1436.930000 2819.020000 1437.930000 2819.500000 ;
+ RECT 1436.930000 2813.580000 1437.930000 2814.060000 ;
+ RECT 1436.930000 2802.700000 1437.930000 2803.180000 ;
+ RECT 1436.930000 2808.140000 1437.930000 2808.620000 ;
+ RECT 1427.620000 2802.700000 1428.720000 2803.180000 ;
+ RECT 1427.620000 2808.140000 1428.720000 2808.620000 ;
+ RECT 1382.620000 2846.220000 1383.720000 2846.700000 ;
+ RECT 1382.620000 2840.780000 1383.720000 2841.260000 ;
+ RECT 1382.620000 2835.340000 1383.720000 2835.820000 ;
+ RECT 1382.620000 2829.900000 1383.720000 2830.380000 ;
+ RECT 1382.620000 2824.460000 1383.720000 2824.940000 ;
+ RECT 1382.620000 2802.700000 1383.720000 2803.180000 ;
+ RECT 1382.620000 2808.140000 1383.720000 2808.620000 ;
+ RECT 1382.620000 2813.580000 1383.720000 2814.060000 ;
+ RECT 1382.620000 2819.020000 1383.720000 2819.500000 ;
+ RECT 1427.620000 2797.260000 1428.720000 2797.740000 ;
+ RECT 1427.620000 2791.820000 1428.720000 2792.300000 ;
+ RECT 1436.930000 2797.260000 1437.930000 2797.740000 ;
+ RECT 1436.930000 2791.820000 1437.930000 2792.300000 ;
+ RECT 1427.620000 2780.940000 1428.720000 2781.420000 ;
+ RECT 1427.620000 2775.500000 1428.720000 2775.980000 ;
+ RECT 1436.930000 2780.940000 1437.930000 2781.420000 ;
+ RECT 1436.930000 2775.500000 1437.930000 2775.980000 ;
+ RECT 1427.620000 2786.380000 1428.720000 2786.860000 ;
+ RECT 1436.930000 2786.380000 1437.930000 2786.860000 ;
+ RECT 1436.930000 2764.620000 1437.930000 2765.100000 ;
+ RECT 1436.930000 2770.060000 1437.930000 2770.540000 ;
+ RECT 1427.620000 2770.060000 1428.720000 2770.540000 ;
+ RECT 1427.620000 2764.620000 1428.720000 2765.100000 ;
+ RECT 1427.620000 2759.180000 1428.720000 2759.660000 ;
+ RECT 1427.620000 2753.740000 1428.720000 2754.220000 ;
+ RECT 1436.930000 2759.180000 1437.930000 2759.660000 ;
+ RECT 1436.930000 2753.740000 1437.930000 2754.220000 ;
+ RECT 1382.620000 2797.260000 1383.720000 2797.740000 ;
+ RECT 1382.620000 2791.820000 1383.720000 2792.300000 ;
+ RECT 1382.620000 2786.380000 1383.720000 2786.860000 ;
+ RECT 1382.620000 2780.940000 1383.720000 2781.420000 ;
+ RECT 1382.620000 2775.500000 1383.720000 2775.980000 ;
+ RECT 1382.620000 2770.060000 1383.720000 2770.540000 ;
+ RECT 1382.620000 2764.620000 1383.720000 2765.100000 ;
+ RECT 1382.620000 2759.180000 1383.720000 2759.660000 ;
+ RECT 1382.620000 2753.740000 1383.720000 2754.220000 ;
+ RECT 1337.620000 2846.220000 1338.720000 2846.700000 ;
+ RECT 1337.620000 2840.780000 1338.720000 2841.260000 ;
+ RECT 1337.620000 2835.340000 1338.720000 2835.820000 ;
+ RECT 1337.620000 2829.900000 1338.720000 2830.380000 ;
+ RECT 1337.620000 2824.460000 1338.720000 2824.940000 ;
+ RECT 1292.620000 2846.220000 1293.720000 2846.700000 ;
+ RECT 1292.620000 2840.780000 1293.720000 2841.260000 ;
+ RECT 1292.620000 2835.340000 1293.720000 2835.820000 ;
+ RECT 1292.620000 2829.900000 1293.720000 2830.380000 ;
+ RECT 1292.620000 2824.460000 1293.720000 2824.940000 ;
+ RECT 1337.620000 2819.020000 1338.720000 2819.500000 ;
+ RECT 1337.620000 2813.580000 1338.720000 2814.060000 ;
+ RECT 1337.620000 2808.140000 1338.720000 2808.620000 ;
+ RECT 1337.620000 2802.700000 1338.720000 2803.180000 ;
+ RECT 1292.620000 2813.580000 1293.720000 2814.060000 ;
+ RECT 1292.620000 2808.140000 1293.720000 2808.620000 ;
+ RECT 1292.620000 2802.700000 1293.720000 2803.180000 ;
+ RECT 1292.620000 2819.020000 1293.720000 2819.500000 ;
+ RECT 1247.620000 2846.220000 1248.720000 2846.700000 ;
+ RECT 1243.490000 2846.220000 1244.490000 2846.700000 ;
+ RECT 1247.620000 2840.780000 1248.720000 2841.260000 ;
+ RECT 1243.490000 2840.780000 1244.490000 2841.260000 ;
+ RECT 1247.620000 2835.340000 1248.720000 2835.820000 ;
+ RECT 1243.490000 2835.340000 1244.490000 2835.820000 ;
+ RECT 1247.620000 2824.460000 1248.720000 2824.940000 ;
+ RECT 1243.490000 2824.460000 1244.490000 2824.940000 ;
+ RECT 1243.490000 2829.900000 1244.490000 2830.380000 ;
+ RECT 1247.620000 2829.900000 1248.720000 2830.380000 ;
+ RECT 1247.620000 2819.020000 1248.720000 2819.500000 ;
+ RECT 1243.490000 2819.020000 1244.490000 2819.500000 ;
+ RECT 1247.620000 2813.580000 1248.720000 2814.060000 ;
+ RECT 1243.490000 2813.580000 1244.490000 2814.060000 ;
+ RECT 1247.620000 2808.140000 1248.720000 2808.620000 ;
+ RECT 1243.490000 2808.140000 1244.490000 2808.620000 ;
+ RECT 1247.620000 2802.700000 1248.720000 2803.180000 ;
+ RECT 1243.490000 2802.700000 1244.490000 2803.180000 ;
+ RECT 1337.620000 2797.260000 1338.720000 2797.740000 ;
+ RECT 1337.620000 2791.820000 1338.720000 2792.300000 ;
+ RECT 1337.620000 2786.380000 1338.720000 2786.860000 ;
+ RECT 1337.620000 2780.940000 1338.720000 2781.420000 ;
+ RECT 1337.620000 2775.500000 1338.720000 2775.980000 ;
+ RECT 1292.620000 2797.260000 1293.720000 2797.740000 ;
+ RECT 1292.620000 2791.820000 1293.720000 2792.300000 ;
+ RECT 1292.620000 2786.380000 1293.720000 2786.860000 ;
+ RECT 1292.620000 2780.940000 1293.720000 2781.420000 ;
+ RECT 1292.620000 2775.500000 1293.720000 2775.980000 ;
+ RECT 1337.620000 2753.740000 1338.720000 2754.220000 ;
+ RECT 1337.620000 2759.180000 1338.720000 2759.660000 ;
+ RECT 1337.620000 2764.620000 1338.720000 2765.100000 ;
+ RECT 1337.620000 2770.060000 1338.720000 2770.540000 ;
+ RECT 1292.620000 2753.740000 1293.720000 2754.220000 ;
+ RECT 1292.620000 2759.180000 1293.720000 2759.660000 ;
+ RECT 1292.620000 2764.620000 1293.720000 2765.100000 ;
+ RECT 1292.620000 2770.060000 1293.720000 2770.540000 ;
+ RECT 1247.620000 2797.260000 1248.720000 2797.740000 ;
+ RECT 1243.490000 2797.260000 1244.490000 2797.740000 ;
+ RECT 1247.620000 2791.820000 1248.720000 2792.300000 ;
+ RECT 1243.490000 2791.820000 1244.490000 2792.300000 ;
+ RECT 1247.620000 2780.940000 1248.720000 2781.420000 ;
+ RECT 1243.490000 2780.940000 1244.490000 2781.420000 ;
+ RECT 1247.620000 2775.500000 1248.720000 2775.980000 ;
+ RECT 1243.490000 2775.500000 1244.490000 2775.980000 ;
+ RECT 1247.620000 2786.380000 1248.720000 2786.860000 ;
+ RECT 1243.490000 2786.380000 1244.490000 2786.860000 ;
+ RECT 1247.620000 2770.060000 1248.720000 2770.540000 ;
+ RECT 1243.490000 2770.060000 1244.490000 2770.540000 ;
+ RECT 1247.620000 2764.620000 1248.720000 2765.100000 ;
+ RECT 1243.490000 2764.620000 1244.490000 2765.100000 ;
+ RECT 1247.620000 2759.180000 1248.720000 2759.660000 ;
+ RECT 1247.620000 2753.740000 1248.720000 2754.220000 ;
+ RECT 1243.490000 2759.180000 1244.490000 2759.660000 ;
+ RECT 1243.490000 2753.740000 1244.490000 2754.220000 ;
+ RECT 1240.660000 2944.100000 1440.760000 2945.100000 ;
+ RECT 1240.660000 2751.730000 1440.760000 2752.730000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 2748.880000 1244.490000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 2948.140000 1244.490000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 2748.880000 1437.930000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 2948.140000 1437.930000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2751.730000 1241.660000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2751.730000 1440.760000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2944.100000 1241.660000 2945.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2944.100000 1440.760000 2945.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 2551.470000 1428.720000 2744.840000 ;
+ RECT 1382.620000 2551.470000 1383.720000 2744.840000 ;
+ RECT 1436.930000 2548.620000 1437.930000 2748.880000 ;
+ RECT 1337.620000 2551.470000 1338.720000 2744.840000 ;
+ RECT 1292.620000 2551.470000 1293.720000 2744.840000 ;
+ RECT 1247.620000 2551.470000 1248.720000 2744.840000 ;
+ RECT 1243.490000 2548.620000 1244.490000 2748.880000 ;
+ LAYER met3 ;
+ RECT 1427.620000 2738.440000 1428.720000 2738.920000 ;
+ RECT 1436.930000 2738.440000 1437.930000 2738.920000 ;
+ RECT 1436.930000 2727.560000 1437.930000 2728.040000 ;
+ RECT 1436.930000 2733.000000 1437.930000 2733.480000 ;
+ RECT 1427.620000 2733.000000 1428.720000 2733.480000 ;
+ RECT 1427.620000 2727.560000 1428.720000 2728.040000 ;
+ RECT 1427.620000 2722.120000 1428.720000 2722.600000 ;
+ RECT 1427.620000 2716.680000 1428.720000 2717.160000 ;
+ RECT 1436.930000 2722.120000 1437.930000 2722.600000 ;
+ RECT 1436.930000 2716.680000 1437.930000 2717.160000 ;
+ RECT 1427.620000 2700.360000 1428.720000 2700.840000 ;
+ RECT 1427.620000 2705.800000 1428.720000 2706.280000 ;
+ RECT 1436.930000 2705.800000 1437.930000 2706.280000 ;
+ RECT 1436.930000 2700.360000 1437.930000 2700.840000 ;
+ RECT 1427.620000 2711.240000 1428.720000 2711.720000 ;
+ RECT 1436.930000 2711.240000 1437.930000 2711.720000 ;
+ RECT 1382.620000 2738.440000 1383.720000 2738.920000 ;
+ RECT 1382.620000 2733.000000 1383.720000 2733.480000 ;
+ RECT 1382.620000 2727.560000 1383.720000 2728.040000 ;
+ RECT 1382.620000 2722.120000 1383.720000 2722.600000 ;
+ RECT 1382.620000 2700.360000 1383.720000 2700.840000 ;
+ RECT 1382.620000 2705.800000 1383.720000 2706.280000 ;
+ RECT 1382.620000 2711.240000 1383.720000 2711.720000 ;
+ RECT 1382.620000 2716.680000 1383.720000 2717.160000 ;
+ RECT 1436.930000 2689.480000 1437.930000 2689.960000 ;
+ RECT 1436.930000 2694.920000 1437.930000 2695.400000 ;
+ RECT 1427.620000 2694.920000 1428.720000 2695.400000 ;
+ RECT 1427.620000 2689.480000 1428.720000 2689.960000 ;
+ RECT 1427.620000 2684.040000 1428.720000 2684.520000 ;
+ RECT 1427.620000 2678.600000 1428.720000 2679.080000 ;
+ RECT 1436.930000 2684.040000 1437.930000 2684.520000 ;
+ RECT 1436.930000 2678.600000 1437.930000 2679.080000 ;
+ RECT 1436.930000 2662.280000 1437.930000 2662.760000 ;
+ RECT 1436.930000 2667.720000 1437.930000 2668.200000 ;
+ RECT 1436.930000 2673.160000 1437.930000 2673.640000 ;
+ RECT 1427.620000 2667.720000 1428.720000 2668.200000 ;
+ RECT 1427.620000 2662.280000 1428.720000 2662.760000 ;
+ RECT 1427.620000 2673.160000 1428.720000 2673.640000 ;
+ RECT 1427.620000 2656.840000 1428.720000 2657.320000 ;
+ RECT 1427.620000 2651.400000 1428.720000 2651.880000 ;
+ RECT 1436.930000 2656.840000 1437.930000 2657.320000 ;
+ RECT 1436.930000 2651.400000 1437.930000 2651.880000 ;
+ RECT 1382.620000 2694.920000 1383.720000 2695.400000 ;
+ RECT 1382.620000 2689.480000 1383.720000 2689.960000 ;
+ RECT 1382.620000 2684.040000 1383.720000 2684.520000 ;
+ RECT 1382.620000 2678.600000 1383.720000 2679.080000 ;
+ RECT 1382.620000 2667.720000 1383.720000 2668.200000 ;
+ RECT 1382.620000 2662.280000 1383.720000 2662.760000 ;
+ RECT 1382.620000 2656.840000 1383.720000 2657.320000 ;
+ RECT 1382.620000 2651.400000 1383.720000 2651.880000 ;
+ RECT 1382.620000 2673.160000 1383.720000 2673.640000 ;
+ RECT 1337.620000 2738.440000 1338.720000 2738.920000 ;
+ RECT 1337.620000 2733.000000 1338.720000 2733.480000 ;
+ RECT 1337.620000 2727.560000 1338.720000 2728.040000 ;
+ RECT 1292.620000 2738.440000 1293.720000 2738.920000 ;
+ RECT 1292.620000 2733.000000 1293.720000 2733.480000 ;
+ RECT 1292.620000 2727.560000 1293.720000 2728.040000 ;
+ RECT 1337.620000 2711.240000 1338.720000 2711.720000 ;
+ RECT 1337.620000 2705.800000 1338.720000 2706.280000 ;
+ RECT 1337.620000 2700.360000 1338.720000 2700.840000 ;
+ RECT 1337.620000 2716.680000 1338.720000 2717.160000 ;
+ RECT 1337.620000 2722.120000 1338.720000 2722.600000 ;
+ RECT 1292.620000 2722.120000 1293.720000 2722.600000 ;
+ RECT 1292.620000 2711.240000 1293.720000 2711.720000 ;
+ RECT 1292.620000 2705.800000 1293.720000 2706.280000 ;
+ RECT 1292.620000 2700.360000 1293.720000 2700.840000 ;
+ RECT 1292.620000 2716.680000 1293.720000 2717.160000 ;
+ RECT 1247.620000 2738.440000 1248.720000 2738.920000 ;
+ RECT 1243.490000 2738.440000 1244.490000 2738.920000 ;
+ RECT 1243.490000 2733.000000 1244.490000 2733.480000 ;
+ RECT 1247.620000 2733.000000 1248.720000 2733.480000 ;
+ RECT 1247.620000 2727.560000 1248.720000 2728.040000 ;
+ RECT 1243.490000 2727.560000 1244.490000 2728.040000 ;
+ RECT 1247.620000 2722.120000 1248.720000 2722.600000 ;
+ RECT 1243.490000 2722.120000 1244.490000 2722.600000 ;
+ RECT 1247.620000 2716.680000 1248.720000 2717.160000 ;
+ RECT 1243.490000 2716.680000 1244.490000 2717.160000 ;
+ RECT 1247.620000 2705.800000 1248.720000 2706.280000 ;
+ RECT 1243.490000 2705.800000 1244.490000 2706.280000 ;
+ RECT 1247.620000 2700.360000 1248.720000 2700.840000 ;
+ RECT 1243.490000 2700.360000 1244.490000 2700.840000 ;
+ RECT 1247.620000 2711.240000 1248.720000 2711.720000 ;
+ RECT 1243.490000 2711.240000 1244.490000 2711.720000 ;
+ RECT 1337.620000 2694.920000 1338.720000 2695.400000 ;
+ RECT 1337.620000 2689.480000 1338.720000 2689.960000 ;
+ RECT 1337.620000 2684.040000 1338.720000 2684.520000 ;
+ RECT 1337.620000 2678.600000 1338.720000 2679.080000 ;
+ RECT 1292.620000 2694.920000 1293.720000 2695.400000 ;
+ RECT 1292.620000 2689.480000 1293.720000 2689.960000 ;
+ RECT 1292.620000 2684.040000 1293.720000 2684.520000 ;
+ RECT 1292.620000 2678.600000 1293.720000 2679.080000 ;
+ RECT 1337.620000 2667.720000 1338.720000 2668.200000 ;
+ RECT 1337.620000 2651.400000 1338.720000 2651.880000 ;
+ RECT 1337.620000 2656.840000 1338.720000 2657.320000 ;
+ RECT 1337.620000 2662.280000 1338.720000 2662.760000 ;
+ RECT 1337.620000 2673.160000 1338.720000 2673.640000 ;
+ RECT 1292.620000 2651.400000 1293.720000 2651.880000 ;
+ RECT 1292.620000 2656.840000 1293.720000 2657.320000 ;
+ RECT 1292.620000 2662.280000 1293.720000 2662.760000 ;
+ RECT 1292.620000 2667.720000 1293.720000 2668.200000 ;
+ RECT 1292.620000 2673.160000 1293.720000 2673.640000 ;
+ RECT 1247.620000 2694.920000 1248.720000 2695.400000 ;
+ RECT 1243.490000 2694.920000 1244.490000 2695.400000 ;
+ RECT 1247.620000 2689.480000 1248.720000 2689.960000 ;
+ RECT 1243.490000 2689.480000 1244.490000 2689.960000 ;
+ RECT 1247.620000 2684.040000 1248.720000 2684.520000 ;
+ RECT 1243.490000 2684.040000 1244.490000 2684.520000 ;
+ RECT 1247.620000 2678.600000 1248.720000 2679.080000 ;
+ RECT 1243.490000 2678.600000 1244.490000 2679.080000 ;
+ RECT 1247.620000 2673.160000 1248.720000 2673.640000 ;
+ RECT 1247.620000 2667.720000 1248.720000 2668.200000 ;
+ RECT 1243.490000 2673.160000 1244.490000 2673.640000 ;
+ RECT 1243.490000 2667.720000 1244.490000 2668.200000 ;
+ RECT 1247.620000 2662.280000 1248.720000 2662.760000 ;
+ RECT 1243.490000 2662.280000 1244.490000 2662.760000 ;
+ RECT 1247.620000 2656.840000 1248.720000 2657.320000 ;
+ RECT 1243.490000 2656.840000 1244.490000 2657.320000 ;
+ RECT 1247.620000 2651.400000 1248.720000 2651.880000 ;
+ RECT 1243.490000 2651.400000 1244.490000 2651.880000 ;
+ RECT 1427.620000 2645.960000 1428.720000 2646.440000 ;
+ RECT 1427.620000 2640.520000 1428.720000 2641.000000 ;
+ RECT 1436.930000 2645.960000 1437.930000 2646.440000 ;
+ RECT 1436.930000 2640.520000 1437.930000 2641.000000 ;
+ RECT 1436.930000 2624.200000 1437.930000 2624.680000 ;
+ RECT 1436.930000 2629.640000 1437.930000 2630.120000 ;
+ RECT 1436.930000 2635.080000 1437.930000 2635.560000 ;
+ RECT 1427.620000 2635.080000 1428.720000 2635.560000 ;
+ RECT 1427.620000 2629.640000 1428.720000 2630.120000 ;
+ RECT 1427.620000 2624.200000 1428.720000 2624.680000 ;
+ RECT 1427.620000 2613.320000 1428.720000 2613.800000 ;
+ RECT 1427.620000 2618.760000 1428.720000 2619.240000 ;
+ RECT 1436.930000 2618.760000 1437.930000 2619.240000 ;
+ RECT 1436.930000 2613.320000 1437.930000 2613.800000 ;
+ RECT 1436.930000 2602.440000 1437.930000 2602.920000 ;
+ RECT 1436.930000 2607.880000 1437.930000 2608.360000 ;
+ RECT 1427.620000 2602.440000 1428.720000 2602.920000 ;
+ RECT 1427.620000 2607.880000 1428.720000 2608.360000 ;
+ RECT 1382.620000 2645.960000 1383.720000 2646.440000 ;
+ RECT 1382.620000 2640.520000 1383.720000 2641.000000 ;
+ RECT 1382.620000 2635.080000 1383.720000 2635.560000 ;
+ RECT 1382.620000 2629.640000 1383.720000 2630.120000 ;
+ RECT 1382.620000 2624.200000 1383.720000 2624.680000 ;
+ RECT 1382.620000 2602.440000 1383.720000 2602.920000 ;
+ RECT 1382.620000 2607.880000 1383.720000 2608.360000 ;
+ RECT 1382.620000 2613.320000 1383.720000 2613.800000 ;
+ RECT 1382.620000 2618.760000 1383.720000 2619.240000 ;
+ RECT 1427.620000 2597.000000 1428.720000 2597.480000 ;
+ RECT 1427.620000 2591.560000 1428.720000 2592.040000 ;
+ RECT 1436.930000 2597.000000 1437.930000 2597.480000 ;
+ RECT 1436.930000 2591.560000 1437.930000 2592.040000 ;
+ RECT 1427.620000 2580.680000 1428.720000 2581.160000 ;
+ RECT 1427.620000 2575.240000 1428.720000 2575.720000 ;
+ RECT 1436.930000 2580.680000 1437.930000 2581.160000 ;
+ RECT 1436.930000 2575.240000 1437.930000 2575.720000 ;
+ RECT 1427.620000 2586.120000 1428.720000 2586.600000 ;
+ RECT 1436.930000 2586.120000 1437.930000 2586.600000 ;
+ RECT 1436.930000 2564.360000 1437.930000 2564.840000 ;
+ RECT 1436.930000 2569.800000 1437.930000 2570.280000 ;
+ RECT 1427.620000 2569.800000 1428.720000 2570.280000 ;
+ RECT 1427.620000 2564.360000 1428.720000 2564.840000 ;
+ RECT 1427.620000 2558.920000 1428.720000 2559.400000 ;
+ RECT 1427.620000 2553.480000 1428.720000 2553.960000 ;
+ RECT 1436.930000 2558.920000 1437.930000 2559.400000 ;
+ RECT 1436.930000 2553.480000 1437.930000 2553.960000 ;
+ RECT 1382.620000 2597.000000 1383.720000 2597.480000 ;
+ RECT 1382.620000 2591.560000 1383.720000 2592.040000 ;
+ RECT 1382.620000 2586.120000 1383.720000 2586.600000 ;
+ RECT 1382.620000 2580.680000 1383.720000 2581.160000 ;
+ RECT 1382.620000 2575.240000 1383.720000 2575.720000 ;
+ RECT 1382.620000 2569.800000 1383.720000 2570.280000 ;
+ RECT 1382.620000 2564.360000 1383.720000 2564.840000 ;
+ RECT 1382.620000 2558.920000 1383.720000 2559.400000 ;
+ RECT 1382.620000 2553.480000 1383.720000 2553.960000 ;
+ RECT 1337.620000 2645.960000 1338.720000 2646.440000 ;
+ RECT 1337.620000 2640.520000 1338.720000 2641.000000 ;
+ RECT 1337.620000 2635.080000 1338.720000 2635.560000 ;
+ RECT 1337.620000 2629.640000 1338.720000 2630.120000 ;
+ RECT 1337.620000 2624.200000 1338.720000 2624.680000 ;
+ RECT 1292.620000 2645.960000 1293.720000 2646.440000 ;
+ RECT 1292.620000 2640.520000 1293.720000 2641.000000 ;
+ RECT 1292.620000 2635.080000 1293.720000 2635.560000 ;
+ RECT 1292.620000 2629.640000 1293.720000 2630.120000 ;
+ RECT 1292.620000 2624.200000 1293.720000 2624.680000 ;
+ RECT 1337.620000 2618.760000 1338.720000 2619.240000 ;
+ RECT 1337.620000 2613.320000 1338.720000 2613.800000 ;
+ RECT 1337.620000 2607.880000 1338.720000 2608.360000 ;
+ RECT 1337.620000 2602.440000 1338.720000 2602.920000 ;
+ RECT 1292.620000 2613.320000 1293.720000 2613.800000 ;
+ RECT 1292.620000 2607.880000 1293.720000 2608.360000 ;
+ RECT 1292.620000 2602.440000 1293.720000 2602.920000 ;
+ RECT 1292.620000 2618.760000 1293.720000 2619.240000 ;
+ RECT 1247.620000 2645.960000 1248.720000 2646.440000 ;
+ RECT 1243.490000 2645.960000 1244.490000 2646.440000 ;
+ RECT 1247.620000 2640.520000 1248.720000 2641.000000 ;
+ RECT 1243.490000 2640.520000 1244.490000 2641.000000 ;
+ RECT 1247.620000 2635.080000 1248.720000 2635.560000 ;
+ RECT 1243.490000 2635.080000 1244.490000 2635.560000 ;
+ RECT 1247.620000 2624.200000 1248.720000 2624.680000 ;
+ RECT 1243.490000 2624.200000 1244.490000 2624.680000 ;
+ RECT 1243.490000 2629.640000 1244.490000 2630.120000 ;
+ RECT 1247.620000 2629.640000 1248.720000 2630.120000 ;
+ RECT 1247.620000 2618.760000 1248.720000 2619.240000 ;
+ RECT 1243.490000 2618.760000 1244.490000 2619.240000 ;
+ RECT 1247.620000 2613.320000 1248.720000 2613.800000 ;
+ RECT 1243.490000 2613.320000 1244.490000 2613.800000 ;
+ RECT 1247.620000 2607.880000 1248.720000 2608.360000 ;
+ RECT 1243.490000 2607.880000 1244.490000 2608.360000 ;
+ RECT 1247.620000 2602.440000 1248.720000 2602.920000 ;
+ RECT 1243.490000 2602.440000 1244.490000 2602.920000 ;
+ RECT 1337.620000 2597.000000 1338.720000 2597.480000 ;
+ RECT 1337.620000 2591.560000 1338.720000 2592.040000 ;
+ RECT 1337.620000 2586.120000 1338.720000 2586.600000 ;
+ RECT 1337.620000 2580.680000 1338.720000 2581.160000 ;
+ RECT 1337.620000 2575.240000 1338.720000 2575.720000 ;
+ RECT 1292.620000 2597.000000 1293.720000 2597.480000 ;
+ RECT 1292.620000 2591.560000 1293.720000 2592.040000 ;
+ RECT 1292.620000 2586.120000 1293.720000 2586.600000 ;
+ RECT 1292.620000 2580.680000 1293.720000 2581.160000 ;
+ RECT 1292.620000 2575.240000 1293.720000 2575.720000 ;
+ RECT 1337.620000 2553.480000 1338.720000 2553.960000 ;
+ RECT 1337.620000 2558.920000 1338.720000 2559.400000 ;
+ RECT 1337.620000 2564.360000 1338.720000 2564.840000 ;
+ RECT 1337.620000 2569.800000 1338.720000 2570.280000 ;
+ RECT 1292.620000 2553.480000 1293.720000 2553.960000 ;
+ RECT 1292.620000 2558.920000 1293.720000 2559.400000 ;
+ RECT 1292.620000 2564.360000 1293.720000 2564.840000 ;
+ RECT 1292.620000 2569.800000 1293.720000 2570.280000 ;
+ RECT 1247.620000 2597.000000 1248.720000 2597.480000 ;
+ RECT 1243.490000 2597.000000 1244.490000 2597.480000 ;
+ RECT 1247.620000 2591.560000 1248.720000 2592.040000 ;
+ RECT 1243.490000 2591.560000 1244.490000 2592.040000 ;
+ RECT 1247.620000 2580.680000 1248.720000 2581.160000 ;
+ RECT 1243.490000 2580.680000 1244.490000 2581.160000 ;
+ RECT 1247.620000 2575.240000 1248.720000 2575.720000 ;
+ RECT 1243.490000 2575.240000 1244.490000 2575.720000 ;
+ RECT 1247.620000 2586.120000 1248.720000 2586.600000 ;
+ RECT 1243.490000 2586.120000 1244.490000 2586.600000 ;
+ RECT 1247.620000 2569.800000 1248.720000 2570.280000 ;
+ RECT 1243.490000 2569.800000 1244.490000 2570.280000 ;
+ RECT 1247.620000 2564.360000 1248.720000 2564.840000 ;
+ RECT 1243.490000 2564.360000 1244.490000 2564.840000 ;
+ RECT 1247.620000 2558.920000 1248.720000 2559.400000 ;
+ RECT 1247.620000 2553.480000 1248.720000 2553.960000 ;
+ RECT 1243.490000 2558.920000 1244.490000 2559.400000 ;
+ RECT 1243.490000 2553.480000 1244.490000 2553.960000 ;
+ RECT 1240.660000 2743.840000 1440.760000 2744.840000 ;
+ RECT 1240.660000 2551.470000 1440.760000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 2548.620000 1244.490000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 2747.880000 1244.490000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 2548.620000 1437.930000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 2747.880000 1437.930000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2551.470000 1241.660000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2551.470000 1440.760000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2743.840000 1241.660000 2744.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2743.840000 1440.760000 2744.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 2351.210000 1428.720000 2544.580000 ;
+ RECT 1382.620000 2351.210000 1383.720000 2544.580000 ;
+ RECT 1436.930000 2348.360000 1437.930000 2548.620000 ;
+ RECT 1337.620000 2351.210000 1338.720000 2544.580000 ;
+ RECT 1292.620000 2351.210000 1293.720000 2544.580000 ;
+ RECT 1247.620000 2351.210000 1248.720000 2544.580000 ;
+ RECT 1243.490000 2348.360000 1244.490000 2548.620000 ;
+ LAYER met3 ;
+ RECT 1427.620000 2538.180000 1428.720000 2538.660000 ;
+ RECT 1436.930000 2538.180000 1437.930000 2538.660000 ;
+ RECT 1436.930000 2527.300000 1437.930000 2527.780000 ;
+ RECT 1436.930000 2532.740000 1437.930000 2533.220000 ;
+ RECT 1427.620000 2532.740000 1428.720000 2533.220000 ;
+ RECT 1427.620000 2527.300000 1428.720000 2527.780000 ;
+ RECT 1427.620000 2521.860000 1428.720000 2522.340000 ;
+ RECT 1427.620000 2516.420000 1428.720000 2516.900000 ;
+ RECT 1436.930000 2521.860000 1437.930000 2522.340000 ;
+ RECT 1436.930000 2516.420000 1437.930000 2516.900000 ;
+ RECT 1427.620000 2500.100000 1428.720000 2500.580000 ;
+ RECT 1427.620000 2505.540000 1428.720000 2506.020000 ;
+ RECT 1436.930000 2505.540000 1437.930000 2506.020000 ;
+ RECT 1436.930000 2500.100000 1437.930000 2500.580000 ;
+ RECT 1427.620000 2510.980000 1428.720000 2511.460000 ;
+ RECT 1436.930000 2510.980000 1437.930000 2511.460000 ;
+ RECT 1382.620000 2538.180000 1383.720000 2538.660000 ;
+ RECT 1382.620000 2532.740000 1383.720000 2533.220000 ;
+ RECT 1382.620000 2527.300000 1383.720000 2527.780000 ;
+ RECT 1382.620000 2521.860000 1383.720000 2522.340000 ;
+ RECT 1382.620000 2500.100000 1383.720000 2500.580000 ;
+ RECT 1382.620000 2505.540000 1383.720000 2506.020000 ;
+ RECT 1382.620000 2510.980000 1383.720000 2511.460000 ;
+ RECT 1382.620000 2516.420000 1383.720000 2516.900000 ;
+ RECT 1436.930000 2489.220000 1437.930000 2489.700000 ;
+ RECT 1436.930000 2494.660000 1437.930000 2495.140000 ;
+ RECT 1427.620000 2494.660000 1428.720000 2495.140000 ;
+ RECT 1427.620000 2489.220000 1428.720000 2489.700000 ;
+ RECT 1427.620000 2483.780000 1428.720000 2484.260000 ;
+ RECT 1427.620000 2478.340000 1428.720000 2478.820000 ;
+ RECT 1436.930000 2483.780000 1437.930000 2484.260000 ;
+ RECT 1436.930000 2478.340000 1437.930000 2478.820000 ;
+ RECT 1436.930000 2462.020000 1437.930000 2462.500000 ;
+ RECT 1436.930000 2467.460000 1437.930000 2467.940000 ;
+ RECT 1436.930000 2472.900000 1437.930000 2473.380000 ;
+ RECT 1427.620000 2467.460000 1428.720000 2467.940000 ;
+ RECT 1427.620000 2462.020000 1428.720000 2462.500000 ;
+ RECT 1427.620000 2472.900000 1428.720000 2473.380000 ;
+ RECT 1427.620000 2456.580000 1428.720000 2457.060000 ;
+ RECT 1427.620000 2451.140000 1428.720000 2451.620000 ;
+ RECT 1436.930000 2456.580000 1437.930000 2457.060000 ;
+ RECT 1436.930000 2451.140000 1437.930000 2451.620000 ;
+ RECT 1382.620000 2494.660000 1383.720000 2495.140000 ;
+ RECT 1382.620000 2489.220000 1383.720000 2489.700000 ;
+ RECT 1382.620000 2483.780000 1383.720000 2484.260000 ;
+ RECT 1382.620000 2478.340000 1383.720000 2478.820000 ;
+ RECT 1382.620000 2467.460000 1383.720000 2467.940000 ;
+ RECT 1382.620000 2462.020000 1383.720000 2462.500000 ;
+ RECT 1382.620000 2456.580000 1383.720000 2457.060000 ;
+ RECT 1382.620000 2451.140000 1383.720000 2451.620000 ;
+ RECT 1382.620000 2472.900000 1383.720000 2473.380000 ;
+ RECT 1337.620000 2538.180000 1338.720000 2538.660000 ;
+ RECT 1337.620000 2532.740000 1338.720000 2533.220000 ;
+ RECT 1337.620000 2527.300000 1338.720000 2527.780000 ;
+ RECT 1292.620000 2538.180000 1293.720000 2538.660000 ;
+ RECT 1292.620000 2532.740000 1293.720000 2533.220000 ;
+ RECT 1292.620000 2527.300000 1293.720000 2527.780000 ;
+ RECT 1337.620000 2510.980000 1338.720000 2511.460000 ;
+ RECT 1337.620000 2505.540000 1338.720000 2506.020000 ;
+ RECT 1337.620000 2500.100000 1338.720000 2500.580000 ;
+ RECT 1337.620000 2516.420000 1338.720000 2516.900000 ;
+ RECT 1337.620000 2521.860000 1338.720000 2522.340000 ;
+ RECT 1292.620000 2521.860000 1293.720000 2522.340000 ;
+ RECT 1292.620000 2510.980000 1293.720000 2511.460000 ;
+ RECT 1292.620000 2505.540000 1293.720000 2506.020000 ;
+ RECT 1292.620000 2500.100000 1293.720000 2500.580000 ;
+ RECT 1292.620000 2516.420000 1293.720000 2516.900000 ;
+ RECT 1247.620000 2538.180000 1248.720000 2538.660000 ;
+ RECT 1243.490000 2538.180000 1244.490000 2538.660000 ;
+ RECT 1243.490000 2532.740000 1244.490000 2533.220000 ;
+ RECT 1247.620000 2532.740000 1248.720000 2533.220000 ;
+ RECT 1247.620000 2527.300000 1248.720000 2527.780000 ;
+ RECT 1243.490000 2527.300000 1244.490000 2527.780000 ;
+ RECT 1247.620000 2521.860000 1248.720000 2522.340000 ;
+ RECT 1243.490000 2521.860000 1244.490000 2522.340000 ;
+ RECT 1247.620000 2516.420000 1248.720000 2516.900000 ;
+ RECT 1243.490000 2516.420000 1244.490000 2516.900000 ;
+ RECT 1247.620000 2505.540000 1248.720000 2506.020000 ;
+ RECT 1243.490000 2505.540000 1244.490000 2506.020000 ;
+ RECT 1247.620000 2500.100000 1248.720000 2500.580000 ;
+ RECT 1243.490000 2500.100000 1244.490000 2500.580000 ;
+ RECT 1247.620000 2510.980000 1248.720000 2511.460000 ;
+ RECT 1243.490000 2510.980000 1244.490000 2511.460000 ;
+ RECT 1337.620000 2494.660000 1338.720000 2495.140000 ;
+ RECT 1337.620000 2489.220000 1338.720000 2489.700000 ;
+ RECT 1337.620000 2483.780000 1338.720000 2484.260000 ;
+ RECT 1337.620000 2478.340000 1338.720000 2478.820000 ;
+ RECT 1292.620000 2494.660000 1293.720000 2495.140000 ;
+ RECT 1292.620000 2489.220000 1293.720000 2489.700000 ;
+ RECT 1292.620000 2483.780000 1293.720000 2484.260000 ;
+ RECT 1292.620000 2478.340000 1293.720000 2478.820000 ;
+ RECT 1337.620000 2467.460000 1338.720000 2467.940000 ;
+ RECT 1337.620000 2451.140000 1338.720000 2451.620000 ;
+ RECT 1337.620000 2456.580000 1338.720000 2457.060000 ;
+ RECT 1337.620000 2462.020000 1338.720000 2462.500000 ;
+ RECT 1337.620000 2472.900000 1338.720000 2473.380000 ;
+ RECT 1292.620000 2451.140000 1293.720000 2451.620000 ;
+ RECT 1292.620000 2456.580000 1293.720000 2457.060000 ;
+ RECT 1292.620000 2462.020000 1293.720000 2462.500000 ;
+ RECT 1292.620000 2467.460000 1293.720000 2467.940000 ;
+ RECT 1292.620000 2472.900000 1293.720000 2473.380000 ;
+ RECT 1247.620000 2494.660000 1248.720000 2495.140000 ;
+ RECT 1243.490000 2494.660000 1244.490000 2495.140000 ;
+ RECT 1247.620000 2489.220000 1248.720000 2489.700000 ;
+ RECT 1243.490000 2489.220000 1244.490000 2489.700000 ;
+ RECT 1247.620000 2483.780000 1248.720000 2484.260000 ;
+ RECT 1243.490000 2483.780000 1244.490000 2484.260000 ;
+ RECT 1247.620000 2478.340000 1248.720000 2478.820000 ;
+ RECT 1243.490000 2478.340000 1244.490000 2478.820000 ;
+ RECT 1247.620000 2472.900000 1248.720000 2473.380000 ;
+ RECT 1247.620000 2467.460000 1248.720000 2467.940000 ;
+ RECT 1243.490000 2472.900000 1244.490000 2473.380000 ;
+ RECT 1243.490000 2467.460000 1244.490000 2467.940000 ;
+ RECT 1247.620000 2462.020000 1248.720000 2462.500000 ;
+ RECT 1243.490000 2462.020000 1244.490000 2462.500000 ;
+ RECT 1247.620000 2456.580000 1248.720000 2457.060000 ;
+ RECT 1243.490000 2456.580000 1244.490000 2457.060000 ;
+ RECT 1247.620000 2451.140000 1248.720000 2451.620000 ;
+ RECT 1243.490000 2451.140000 1244.490000 2451.620000 ;
+ RECT 1427.620000 2445.700000 1428.720000 2446.180000 ;
+ RECT 1427.620000 2440.260000 1428.720000 2440.740000 ;
+ RECT 1436.930000 2445.700000 1437.930000 2446.180000 ;
+ RECT 1436.930000 2440.260000 1437.930000 2440.740000 ;
+ RECT 1436.930000 2423.940000 1437.930000 2424.420000 ;
+ RECT 1436.930000 2429.380000 1437.930000 2429.860000 ;
+ RECT 1436.930000 2434.820000 1437.930000 2435.300000 ;
+ RECT 1427.620000 2434.820000 1428.720000 2435.300000 ;
+ RECT 1427.620000 2429.380000 1428.720000 2429.860000 ;
+ RECT 1427.620000 2423.940000 1428.720000 2424.420000 ;
+ RECT 1427.620000 2413.060000 1428.720000 2413.540000 ;
+ RECT 1427.620000 2418.500000 1428.720000 2418.980000 ;
+ RECT 1436.930000 2418.500000 1437.930000 2418.980000 ;
+ RECT 1436.930000 2413.060000 1437.930000 2413.540000 ;
+ RECT 1436.930000 2402.180000 1437.930000 2402.660000 ;
+ RECT 1436.930000 2407.620000 1437.930000 2408.100000 ;
+ RECT 1427.620000 2402.180000 1428.720000 2402.660000 ;
+ RECT 1427.620000 2407.620000 1428.720000 2408.100000 ;
+ RECT 1382.620000 2445.700000 1383.720000 2446.180000 ;
+ RECT 1382.620000 2440.260000 1383.720000 2440.740000 ;
+ RECT 1382.620000 2434.820000 1383.720000 2435.300000 ;
+ RECT 1382.620000 2429.380000 1383.720000 2429.860000 ;
+ RECT 1382.620000 2423.940000 1383.720000 2424.420000 ;
+ RECT 1382.620000 2402.180000 1383.720000 2402.660000 ;
+ RECT 1382.620000 2407.620000 1383.720000 2408.100000 ;
+ RECT 1382.620000 2413.060000 1383.720000 2413.540000 ;
+ RECT 1382.620000 2418.500000 1383.720000 2418.980000 ;
+ RECT 1427.620000 2396.740000 1428.720000 2397.220000 ;
+ RECT 1427.620000 2391.300000 1428.720000 2391.780000 ;
+ RECT 1436.930000 2396.740000 1437.930000 2397.220000 ;
+ RECT 1436.930000 2391.300000 1437.930000 2391.780000 ;
+ RECT 1427.620000 2380.420000 1428.720000 2380.900000 ;
+ RECT 1427.620000 2374.980000 1428.720000 2375.460000 ;
+ RECT 1436.930000 2380.420000 1437.930000 2380.900000 ;
+ RECT 1436.930000 2374.980000 1437.930000 2375.460000 ;
+ RECT 1427.620000 2385.860000 1428.720000 2386.340000 ;
+ RECT 1436.930000 2385.860000 1437.930000 2386.340000 ;
+ RECT 1436.930000 2364.100000 1437.930000 2364.580000 ;
+ RECT 1436.930000 2369.540000 1437.930000 2370.020000 ;
+ RECT 1427.620000 2369.540000 1428.720000 2370.020000 ;
+ RECT 1427.620000 2364.100000 1428.720000 2364.580000 ;
+ RECT 1427.620000 2358.660000 1428.720000 2359.140000 ;
+ RECT 1427.620000 2353.220000 1428.720000 2353.700000 ;
+ RECT 1436.930000 2358.660000 1437.930000 2359.140000 ;
+ RECT 1436.930000 2353.220000 1437.930000 2353.700000 ;
+ RECT 1382.620000 2396.740000 1383.720000 2397.220000 ;
+ RECT 1382.620000 2391.300000 1383.720000 2391.780000 ;
+ RECT 1382.620000 2385.860000 1383.720000 2386.340000 ;
+ RECT 1382.620000 2380.420000 1383.720000 2380.900000 ;
+ RECT 1382.620000 2374.980000 1383.720000 2375.460000 ;
+ RECT 1382.620000 2369.540000 1383.720000 2370.020000 ;
+ RECT 1382.620000 2364.100000 1383.720000 2364.580000 ;
+ RECT 1382.620000 2358.660000 1383.720000 2359.140000 ;
+ RECT 1382.620000 2353.220000 1383.720000 2353.700000 ;
+ RECT 1337.620000 2445.700000 1338.720000 2446.180000 ;
+ RECT 1337.620000 2440.260000 1338.720000 2440.740000 ;
+ RECT 1337.620000 2434.820000 1338.720000 2435.300000 ;
+ RECT 1337.620000 2429.380000 1338.720000 2429.860000 ;
+ RECT 1337.620000 2423.940000 1338.720000 2424.420000 ;
+ RECT 1292.620000 2445.700000 1293.720000 2446.180000 ;
+ RECT 1292.620000 2440.260000 1293.720000 2440.740000 ;
+ RECT 1292.620000 2434.820000 1293.720000 2435.300000 ;
+ RECT 1292.620000 2429.380000 1293.720000 2429.860000 ;
+ RECT 1292.620000 2423.940000 1293.720000 2424.420000 ;
+ RECT 1337.620000 2418.500000 1338.720000 2418.980000 ;
+ RECT 1337.620000 2413.060000 1338.720000 2413.540000 ;
+ RECT 1337.620000 2407.620000 1338.720000 2408.100000 ;
+ RECT 1337.620000 2402.180000 1338.720000 2402.660000 ;
+ RECT 1292.620000 2413.060000 1293.720000 2413.540000 ;
+ RECT 1292.620000 2407.620000 1293.720000 2408.100000 ;
+ RECT 1292.620000 2402.180000 1293.720000 2402.660000 ;
+ RECT 1292.620000 2418.500000 1293.720000 2418.980000 ;
+ RECT 1247.620000 2445.700000 1248.720000 2446.180000 ;
+ RECT 1243.490000 2445.700000 1244.490000 2446.180000 ;
+ RECT 1247.620000 2440.260000 1248.720000 2440.740000 ;
+ RECT 1243.490000 2440.260000 1244.490000 2440.740000 ;
+ RECT 1247.620000 2434.820000 1248.720000 2435.300000 ;
+ RECT 1243.490000 2434.820000 1244.490000 2435.300000 ;
+ RECT 1247.620000 2423.940000 1248.720000 2424.420000 ;
+ RECT 1243.490000 2423.940000 1244.490000 2424.420000 ;
+ RECT 1243.490000 2429.380000 1244.490000 2429.860000 ;
+ RECT 1247.620000 2429.380000 1248.720000 2429.860000 ;
+ RECT 1247.620000 2418.500000 1248.720000 2418.980000 ;
+ RECT 1243.490000 2418.500000 1244.490000 2418.980000 ;
+ RECT 1247.620000 2413.060000 1248.720000 2413.540000 ;
+ RECT 1243.490000 2413.060000 1244.490000 2413.540000 ;
+ RECT 1247.620000 2407.620000 1248.720000 2408.100000 ;
+ RECT 1243.490000 2407.620000 1244.490000 2408.100000 ;
+ RECT 1247.620000 2402.180000 1248.720000 2402.660000 ;
+ RECT 1243.490000 2402.180000 1244.490000 2402.660000 ;
+ RECT 1337.620000 2396.740000 1338.720000 2397.220000 ;
+ RECT 1337.620000 2391.300000 1338.720000 2391.780000 ;
+ RECT 1337.620000 2385.860000 1338.720000 2386.340000 ;
+ RECT 1337.620000 2380.420000 1338.720000 2380.900000 ;
+ RECT 1337.620000 2374.980000 1338.720000 2375.460000 ;
+ RECT 1292.620000 2396.740000 1293.720000 2397.220000 ;
+ RECT 1292.620000 2391.300000 1293.720000 2391.780000 ;
+ RECT 1292.620000 2385.860000 1293.720000 2386.340000 ;
+ RECT 1292.620000 2380.420000 1293.720000 2380.900000 ;
+ RECT 1292.620000 2374.980000 1293.720000 2375.460000 ;
+ RECT 1337.620000 2353.220000 1338.720000 2353.700000 ;
+ RECT 1337.620000 2358.660000 1338.720000 2359.140000 ;
+ RECT 1337.620000 2364.100000 1338.720000 2364.580000 ;
+ RECT 1337.620000 2369.540000 1338.720000 2370.020000 ;
+ RECT 1292.620000 2353.220000 1293.720000 2353.700000 ;
+ RECT 1292.620000 2358.660000 1293.720000 2359.140000 ;
+ RECT 1292.620000 2364.100000 1293.720000 2364.580000 ;
+ RECT 1292.620000 2369.540000 1293.720000 2370.020000 ;
+ RECT 1247.620000 2396.740000 1248.720000 2397.220000 ;
+ RECT 1243.490000 2396.740000 1244.490000 2397.220000 ;
+ RECT 1247.620000 2391.300000 1248.720000 2391.780000 ;
+ RECT 1243.490000 2391.300000 1244.490000 2391.780000 ;
+ RECT 1247.620000 2380.420000 1248.720000 2380.900000 ;
+ RECT 1243.490000 2380.420000 1244.490000 2380.900000 ;
+ RECT 1247.620000 2374.980000 1248.720000 2375.460000 ;
+ RECT 1243.490000 2374.980000 1244.490000 2375.460000 ;
+ RECT 1247.620000 2385.860000 1248.720000 2386.340000 ;
+ RECT 1243.490000 2385.860000 1244.490000 2386.340000 ;
+ RECT 1247.620000 2369.540000 1248.720000 2370.020000 ;
+ RECT 1243.490000 2369.540000 1244.490000 2370.020000 ;
+ RECT 1247.620000 2364.100000 1248.720000 2364.580000 ;
+ RECT 1243.490000 2364.100000 1244.490000 2364.580000 ;
+ RECT 1247.620000 2358.660000 1248.720000 2359.140000 ;
+ RECT 1247.620000 2353.220000 1248.720000 2353.700000 ;
+ RECT 1243.490000 2358.660000 1244.490000 2359.140000 ;
+ RECT 1243.490000 2353.220000 1244.490000 2353.700000 ;
+ RECT 1240.660000 2543.580000 1440.760000 2544.580000 ;
+ RECT 1240.660000 2351.210000 1440.760000 2352.210000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 2348.360000 1244.490000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 2547.620000 1244.490000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 2348.360000 1437.930000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 2547.620000 1437.930000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2351.210000 1241.660000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2351.210000 1440.760000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2543.580000 1241.660000 2544.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2543.580000 1440.760000 2544.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 2150.950000 1428.720000 2344.320000 ;
+ RECT 1382.620000 2150.950000 1383.720000 2344.320000 ;
+ RECT 1436.930000 2148.100000 1437.930000 2348.360000 ;
+ RECT 1337.620000 2150.950000 1338.720000 2344.320000 ;
+ RECT 1292.620000 2150.950000 1293.720000 2344.320000 ;
+ RECT 1247.620000 2150.950000 1248.720000 2344.320000 ;
+ RECT 1243.490000 2148.100000 1244.490000 2348.360000 ;
+ LAYER met3 ;
+ RECT 1427.620000 2337.920000 1428.720000 2338.400000 ;
+ RECT 1436.930000 2337.920000 1437.930000 2338.400000 ;
+ RECT 1436.930000 2327.040000 1437.930000 2327.520000 ;
+ RECT 1436.930000 2332.480000 1437.930000 2332.960000 ;
+ RECT 1427.620000 2332.480000 1428.720000 2332.960000 ;
+ RECT 1427.620000 2327.040000 1428.720000 2327.520000 ;
+ RECT 1427.620000 2321.600000 1428.720000 2322.080000 ;
+ RECT 1427.620000 2316.160000 1428.720000 2316.640000 ;
+ RECT 1436.930000 2321.600000 1437.930000 2322.080000 ;
+ RECT 1436.930000 2316.160000 1437.930000 2316.640000 ;
+ RECT 1427.620000 2299.840000 1428.720000 2300.320000 ;
+ RECT 1427.620000 2305.280000 1428.720000 2305.760000 ;
+ RECT 1436.930000 2305.280000 1437.930000 2305.760000 ;
+ RECT 1436.930000 2299.840000 1437.930000 2300.320000 ;
+ RECT 1427.620000 2310.720000 1428.720000 2311.200000 ;
+ RECT 1436.930000 2310.720000 1437.930000 2311.200000 ;
+ RECT 1382.620000 2337.920000 1383.720000 2338.400000 ;
+ RECT 1382.620000 2332.480000 1383.720000 2332.960000 ;
+ RECT 1382.620000 2327.040000 1383.720000 2327.520000 ;
+ RECT 1382.620000 2321.600000 1383.720000 2322.080000 ;
+ RECT 1382.620000 2299.840000 1383.720000 2300.320000 ;
+ RECT 1382.620000 2305.280000 1383.720000 2305.760000 ;
+ RECT 1382.620000 2310.720000 1383.720000 2311.200000 ;
+ RECT 1382.620000 2316.160000 1383.720000 2316.640000 ;
+ RECT 1436.930000 2288.960000 1437.930000 2289.440000 ;
+ RECT 1436.930000 2294.400000 1437.930000 2294.880000 ;
+ RECT 1427.620000 2294.400000 1428.720000 2294.880000 ;
+ RECT 1427.620000 2288.960000 1428.720000 2289.440000 ;
+ RECT 1427.620000 2283.520000 1428.720000 2284.000000 ;
+ RECT 1427.620000 2278.080000 1428.720000 2278.560000 ;
+ RECT 1436.930000 2283.520000 1437.930000 2284.000000 ;
+ RECT 1436.930000 2278.080000 1437.930000 2278.560000 ;
+ RECT 1436.930000 2261.760000 1437.930000 2262.240000 ;
+ RECT 1436.930000 2267.200000 1437.930000 2267.680000 ;
+ RECT 1436.930000 2272.640000 1437.930000 2273.120000 ;
+ RECT 1427.620000 2267.200000 1428.720000 2267.680000 ;
+ RECT 1427.620000 2261.760000 1428.720000 2262.240000 ;
+ RECT 1427.620000 2272.640000 1428.720000 2273.120000 ;
+ RECT 1427.620000 2256.320000 1428.720000 2256.800000 ;
+ RECT 1427.620000 2250.880000 1428.720000 2251.360000 ;
+ RECT 1436.930000 2256.320000 1437.930000 2256.800000 ;
+ RECT 1436.930000 2250.880000 1437.930000 2251.360000 ;
+ RECT 1382.620000 2294.400000 1383.720000 2294.880000 ;
+ RECT 1382.620000 2288.960000 1383.720000 2289.440000 ;
+ RECT 1382.620000 2283.520000 1383.720000 2284.000000 ;
+ RECT 1382.620000 2278.080000 1383.720000 2278.560000 ;
+ RECT 1382.620000 2267.200000 1383.720000 2267.680000 ;
+ RECT 1382.620000 2261.760000 1383.720000 2262.240000 ;
+ RECT 1382.620000 2256.320000 1383.720000 2256.800000 ;
+ RECT 1382.620000 2250.880000 1383.720000 2251.360000 ;
+ RECT 1382.620000 2272.640000 1383.720000 2273.120000 ;
+ RECT 1337.620000 2337.920000 1338.720000 2338.400000 ;
+ RECT 1337.620000 2332.480000 1338.720000 2332.960000 ;
+ RECT 1337.620000 2327.040000 1338.720000 2327.520000 ;
+ RECT 1292.620000 2337.920000 1293.720000 2338.400000 ;
+ RECT 1292.620000 2332.480000 1293.720000 2332.960000 ;
+ RECT 1292.620000 2327.040000 1293.720000 2327.520000 ;
+ RECT 1337.620000 2310.720000 1338.720000 2311.200000 ;
+ RECT 1337.620000 2305.280000 1338.720000 2305.760000 ;
+ RECT 1337.620000 2299.840000 1338.720000 2300.320000 ;
+ RECT 1337.620000 2316.160000 1338.720000 2316.640000 ;
+ RECT 1337.620000 2321.600000 1338.720000 2322.080000 ;
+ RECT 1292.620000 2321.600000 1293.720000 2322.080000 ;
+ RECT 1292.620000 2310.720000 1293.720000 2311.200000 ;
+ RECT 1292.620000 2305.280000 1293.720000 2305.760000 ;
+ RECT 1292.620000 2299.840000 1293.720000 2300.320000 ;
+ RECT 1292.620000 2316.160000 1293.720000 2316.640000 ;
+ RECT 1247.620000 2337.920000 1248.720000 2338.400000 ;
+ RECT 1243.490000 2337.920000 1244.490000 2338.400000 ;
+ RECT 1243.490000 2332.480000 1244.490000 2332.960000 ;
+ RECT 1247.620000 2332.480000 1248.720000 2332.960000 ;
+ RECT 1247.620000 2327.040000 1248.720000 2327.520000 ;
+ RECT 1243.490000 2327.040000 1244.490000 2327.520000 ;
+ RECT 1247.620000 2321.600000 1248.720000 2322.080000 ;
+ RECT 1243.490000 2321.600000 1244.490000 2322.080000 ;
+ RECT 1247.620000 2316.160000 1248.720000 2316.640000 ;
+ RECT 1243.490000 2316.160000 1244.490000 2316.640000 ;
+ RECT 1247.620000 2305.280000 1248.720000 2305.760000 ;
+ RECT 1243.490000 2305.280000 1244.490000 2305.760000 ;
+ RECT 1247.620000 2299.840000 1248.720000 2300.320000 ;
+ RECT 1243.490000 2299.840000 1244.490000 2300.320000 ;
+ RECT 1247.620000 2310.720000 1248.720000 2311.200000 ;
+ RECT 1243.490000 2310.720000 1244.490000 2311.200000 ;
+ RECT 1337.620000 2294.400000 1338.720000 2294.880000 ;
+ RECT 1337.620000 2288.960000 1338.720000 2289.440000 ;
+ RECT 1337.620000 2283.520000 1338.720000 2284.000000 ;
+ RECT 1337.620000 2278.080000 1338.720000 2278.560000 ;
+ RECT 1292.620000 2294.400000 1293.720000 2294.880000 ;
+ RECT 1292.620000 2288.960000 1293.720000 2289.440000 ;
+ RECT 1292.620000 2283.520000 1293.720000 2284.000000 ;
+ RECT 1292.620000 2278.080000 1293.720000 2278.560000 ;
+ RECT 1337.620000 2267.200000 1338.720000 2267.680000 ;
+ RECT 1337.620000 2250.880000 1338.720000 2251.360000 ;
+ RECT 1337.620000 2256.320000 1338.720000 2256.800000 ;
+ RECT 1337.620000 2261.760000 1338.720000 2262.240000 ;
+ RECT 1337.620000 2272.640000 1338.720000 2273.120000 ;
+ RECT 1292.620000 2250.880000 1293.720000 2251.360000 ;
+ RECT 1292.620000 2256.320000 1293.720000 2256.800000 ;
+ RECT 1292.620000 2261.760000 1293.720000 2262.240000 ;
+ RECT 1292.620000 2267.200000 1293.720000 2267.680000 ;
+ RECT 1292.620000 2272.640000 1293.720000 2273.120000 ;
+ RECT 1247.620000 2294.400000 1248.720000 2294.880000 ;
+ RECT 1243.490000 2294.400000 1244.490000 2294.880000 ;
+ RECT 1247.620000 2288.960000 1248.720000 2289.440000 ;
+ RECT 1243.490000 2288.960000 1244.490000 2289.440000 ;
+ RECT 1247.620000 2283.520000 1248.720000 2284.000000 ;
+ RECT 1243.490000 2283.520000 1244.490000 2284.000000 ;
+ RECT 1247.620000 2278.080000 1248.720000 2278.560000 ;
+ RECT 1243.490000 2278.080000 1244.490000 2278.560000 ;
+ RECT 1247.620000 2272.640000 1248.720000 2273.120000 ;
+ RECT 1247.620000 2267.200000 1248.720000 2267.680000 ;
+ RECT 1243.490000 2272.640000 1244.490000 2273.120000 ;
+ RECT 1243.490000 2267.200000 1244.490000 2267.680000 ;
+ RECT 1247.620000 2261.760000 1248.720000 2262.240000 ;
+ RECT 1243.490000 2261.760000 1244.490000 2262.240000 ;
+ RECT 1247.620000 2256.320000 1248.720000 2256.800000 ;
+ RECT 1243.490000 2256.320000 1244.490000 2256.800000 ;
+ RECT 1247.620000 2250.880000 1248.720000 2251.360000 ;
+ RECT 1243.490000 2250.880000 1244.490000 2251.360000 ;
+ RECT 1427.620000 2245.440000 1428.720000 2245.920000 ;
+ RECT 1427.620000 2240.000000 1428.720000 2240.480000 ;
+ RECT 1436.930000 2245.440000 1437.930000 2245.920000 ;
+ RECT 1436.930000 2240.000000 1437.930000 2240.480000 ;
+ RECT 1436.930000 2223.680000 1437.930000 2224.160000 ;
+ RECT 1436.930000 2229.120000 1437.930000 2229.600000 ;
+ RECT 1436.930000 2234.560000 1437.930000 2235.040000 ;
+ RECT 1427.620000 2234.560000 1428.720000 2235.040000 ;
+ RECT 1427.620000 2229.120000 1428.720000 2229.600000 ;
+ RECT 1427.620000 2223.680000 1428.720000 2224.160000 ;
+ RECT 1427.620000 2212.800000 1428.720000 2213.280000 ;
+ RECT 1427.620000 2218.240000 1428.720000 2218.720000 ;
+ RECT 1436.930000 2218.240000 1437.930000 2218.720000 ;
+ RECT 1436.930000 2212.800000 1437.930000 2213.280000 ;
+ RECT 1436.930000 2201.920000 1437.930000 2202.400000 ;
+ RECT 1436.930000 2207.360000 1437.930000 2207.840000 ;
+ RECT 1427.620000 2201.920000 1428.720000 2202.400000 ;
+ RECT 1427.620000 2207.360000 1428.720000 2207.840000 ;
+ RECT 1382.620000 2245.440000 1383.720000 2245.920000 ;
+ RECT 1382.620000 2240.000000 1383.720000 2240.480000 ;
+ RECT 1382.620000 2234.560000 1383.720000 2235.040000 ;
+ RECT 1382.620000 2229.120000 1383.720000 2229.600000 ;
+ RECT 1382.620000 2223.680000 1383.720000 2224.160000 ;
+ RECT 1382.620000 2201.920000 1383.720000 2202.400000 ;
+ RECT 1382.620000 2207.360000 1383.720000 2207.840000 ;
+ RECT 1382.620000 2212.800000 1383.720000 2213.280000 ;
+ RECT 1382.620000 2218.240000 1383.720000 2218.720000 ;
+ RECT 1427.620000 2196.480000 1428.720000 2196.960000 ;
+ RECT 1427.620000 2191.040000 1428.720000 2191.520000 ;
+ RECT 1436.930000 2196.480000 1437.930000 2196.960000 ;
+ RECT 1436.930000 2191.040000 1437.930000 2191.520000 ;
+ RECT 1427.620000 2180.160000 1428.720000 2180.640000 ;
+ RECT 1427.620000 2174.720000 1428.720000 2175.200000 ;
+ RECT 1436.930000 2180.160000 1437.930000 2180.640000 ;
+ RECT 1436.930000 2174.720000 1437.930000 2175.200000 ;
+ RECT 1427.620000 2185.600000 1428.720000 2186.080000 ;
+ RECT 1436.930000 2185.600000 1437.930000 2186.080000 ;
+ RECT 1436.930000 2163.840000 1437.930000 2164.320000 ;
+ RECT 1436.930000 2169.280000 1437.930000 2169.760000 ;
+ RECT 1427.620000 2169.280000 1428.720000 2169.760000 ;
+ RECT 1427.620000 2163.840000 1428.720000 2164.320000 ;
+ RECT 1427.620000 2158.400000 1428.720000 2158.880000 ;
+ RECT 1427.620000 2152.960000 1428.720000 2153.440000 ;
+ RECT 1436.930000 2158.400000 1437.930000 2158.880000 ;
+ RECT 1436.930000 2152.960000 1437.930000 2153.440000 ;
+ RECT 1382.620000 2196.480000 1383.720000 2196.960000 ;
+ RECT 1382.620000 2191.040000 1383.720000 2191.520000 ;
+ RECT 1382.620000 2185.600000 1383.720000 2186.080000 ;
+ RECT 1382.620000 2180.160000 1383.720000 2180.640000 ;
+ RECT 1382.620000 2174.720000 1383.720000 2175.200000 ;
+ RECT 1382.620000 2169.280000 1383.720000 2169.760000 ;
+ RECT 1382.620000 2163.840000 1383.720000 2164.320000 ;
+ RECT 1382.620000 2158.400000 1383.720000 2158.880000 ;
+ RECT 1382.620000 2152.960000 1383.720000 2153.440000 ;
+ RECT 1337.620000 2245.440000 1338.720000 2245.920000 ;
+ RECT 1337.620000 2240.000000 1338.720000 2240.480000 ;
+ RECT 1337.620000 2234.560000 1338.720000 2235.040000 ;
+ RECT 1337.620000 2229.120000 1338.720000 2229.600000 ;
+ RECT 1337.620000 2223.680000 1338.720000 2224.160000 ;
+ RECT 1292.620000 2245.440000 1293.720000 2245.920000 ;
+ RECT 1292.620000 2240.000000 1293.720000 2240.480000 ;
+ RECT 1292.620000 2234.560000 1293.720000 2235.040000 ;
+ RECT 1292.620000 2229.120000 1293.720000 2229.600000 ;
+ RECT 1292.620000 2223.680000 1293.720000 2224.160000 ;
+ RECT 1337.620000 2218.240000 1338.720000 2218.720000 ;
+ RECT 1337.620000 2212.800000 1338.720000 2213.280000 ;
+ RECT 1337.620000 2207.360000 1338.720000 2207.840000 ;
+ RECT 1337.620000 2201.920000 1338.720000 2202.400000 ;
+ RECT 1292.620000 2212.800000 1293.720000 2213.280000 ;
+ RECT 1292.620000 2207.360000 1293.720000 2207.840000 ;
+ RECT 1292.620000 2201.920000 1293.720000 2202.400000 ;
+ RECT 1292.620000 2218.240000 1293.720000 2218.720000 ;
+ RECT 1247.620000 2245.440000 1248.720000 2245.920000 ;
+ RECT 1243.490000 2245.440000 1244.490000 2245.920000 ;
+ RECT 1247.620000 2240.000000 1248.720000 2240.480000 ;
+ RECT 1243.490000 2240.000000 1244.490000 2240.480000 ;
+ RECT 1247.620000 2234.560000 1248.720000 2235.040000 ;
+ RECT 1243.490000 2234.560000 1244.490000 2235.040000 ;
+ RECT 1247.620000 2223.680000 1248.720000 2224.160000 ;
+ RECT 1243.490000 2223.680000 1244.490000 2224.160000 ;
+ RECT 1243.490000 2229.120000 1244.490000 2229.600000 ;
+ RECT 1247.620000 2229.120000 1248.720000 2229.600000 ;
+ RECT 1247.620000 2218.240000 1248.720000 2218.720000 ;
+ RECT 1243.490000 2218.240000 1244.490000 2218.720000 ;
+ RECT 1247.620000 2212.800000 1248.720000 2213.280000 ;
+ RECT 1243.490000 2212.800000 1244.490000 2213.280000 ;
+ RECT 1247.620000 2207.360000 1248.720000 2207.840000 ;
+ RECT 1243.490000 2207.360000 1244.490000 2207.840000 ;
+ RECT 1247.620000 2201.920000 1248.720000 2202.400000 ;
+ RECT 1243.490000 2201.920000 1244.490000 2202.400000 ;
+ RECT 1337.620000 2196.480000 1338.720000 2196.960000 ;
+ RECT 1337.620000 2191.040000 1338.720000 2191.520000 ;
+ RECT 1337.620000 2185.600000 1338.720000 2186.080000 ;
+ RECT 1337.620000 2180.160000 1338.720000 2180.640000 ;
+ RECT 1337.620000 2174.720000 1338.720000 2175.200000 ;
+ RECT 1292.620000 2196.480000 1293.720000 2196.960000 ;
+ RECT 1292.620000 2191.040000 1293.720000 2191.520000 ;
+ RECT 1292.620000 2185.600000 1293.720000 2186.080000 ;
+ RECT 1292.620000 2180.160000 1293.720000 2180.640000 ;
+ RECT 1292.620000 2174.720000 1293.720000 2175.200000 ;
+ RECT 1337.620000 2152.960000 1338.720000 2153.440000 ;
+ RECT 1337.620000 2158.400000 1338.720000 2158.880000 ;
+ RECT 1337.620000 2163.840000 1338.720000 2164.320000 ;
+ RECT 1337.620000 2169.280000 1338.720000 2169.760000 ;
+ RECT 1292.620000 2152.960000 1293.720000 2153.440000 ;
+ RECT 1292.620000 2158.400000 1293.720000 2158.880000 ;
+ RECT 1292.620000 2163.840000 1293.720000 2164.320000 ;
+ RECT 1292.620000 2169.280000 1293.720000 2169.760000 ;
+ RECT 1247.620000 2196.480000 1248.720000 2196.960000 ;
+ RECT 1243.490000 2196.480000 1244.490000 2196.960000 ;
+ RECT 1247.620000 2191.040000 1248.720000 2191.520000 ;
+ RECT 1243.490000 2191.040000 1244.490000 2191.520000 ;
+ RECT 1247.620000 2180.160000 1248.720000 2180.640000 ;
+ RECT 1243.490000 2180.160000 1244.490000 2180.640000 ;
+ RECT 1247.620000 2174.720000 1248.720000 2175.200000 ;
+ RECT 1243.490000 2174.720000 1244.490000 2175.200000 ;
+ RECT 1247.620000 2185.600000 1248.720000 2186.080000 ;
+ RECT 1243.490000 2185.600000 1244.490000 2186.080000 ;
+ RECT 1247.620000 2169.280000 1248.720000 2169.760000 ;
+ RECT 1243.490000 2169.280000 1244.490000 2169.760000 ;
+ RECT 1247.620000 2163.840000 1248.720000 2164.320000 ;
+ RECT 1243.490000 2163.840000 1244.490000 2164.320000 ;
+ RECT 1247.620000 2158.400000 1248.720000 2158.880000 ;
+ RECT 1247.620000 2152.960000 1248.720000 2153.440000 ;
+ RECT 1243.490000 2158.400000 1244.490000 2158.880000 ;
+ RECT 1243.490000 2152.960000 1244.490000 2153.440000 ;
+ RECT 1240.660000 2343.320000 1440.760000 2344.320000 ;
+ RECT 1240.660000 2150.950000 1440.760000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 2148.100000 1244.490000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 2347.360000 1244.490000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 2148.100000 1437.930000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 2347.360000 1437.930000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2150.950000 1241.660000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2150.950000 1440.760000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2343.320000 1241.660000 2344.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2343.320000 1440.760000 2344.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 1950.690000 1428.720000 2144.060000 ;
+ RECT 1382.620000 1950.690000 1383.720000 2144.060000 ;
+ RECT 1436.930000 1947.840000 1437.930000 2148.100000 ;
+ RECT 1337.620000 1950.690000 1338.720000 2144.060000 ;
+ RECT 1292.620000 1950.690000 1293.720000 2144.060000 ;
+ RECT 1247.620000 1950.690000 1248.720000 2144.060000 ;
+ RECT 1243.490000 1947.840000 1244.490000 2148.100000 ;
+ LAYER met3 ;
+ RECT 1427.620000 2137.660000 1428.720000 2138.140000 ;
+ RECT 1436.930000 2137.660000 1437.930000 2138.140000 ;
+ RECT 1436.930000 2126.780000 1437.930000 2127.260000 ;
+ RECT 1436.930000 2132.220000 1437.930000 2132.700000 ;
+ RECT 1427.620000 2132.220000 1428.720000 2132.700000 ;
+ RECT 1427.620000 2126.780000 1428.720000 2127.260000 ;
+ RECT 1427.620000 2121.340000 1428.720000 2121.820000 ;
+ RECT 1427.620000 2115.900000 1428.720000 2116.380000 ;
+ RECT 1436.930000 2121.340000 1437.930000 2121.820000 ;
+ RECT 1436.930000 2115.900000 1437.930000 2116.380000 ;
+ RECT 1427.620000 2099.580000 1428.720000 2100.060000 ;
+ RECT 1427.620000 2105.020000 1428.720000 2105.500000 ;
+ RECT 1436.930000 2105.020000 1437.930000 2105.500000 ;
+ RECT 1436.930000 2099.580000 1437.930000 2100.060000 ;
+ RECT 1427.620000 2110.460000 1428.720000 2110.940000 ;
+ RECT 1436.930000 2110.460000 1437.930000 2110.940000 ;
+ RECT 1382.620000 2137.660000 1383.720000 2138.140000 ;
+ RECT 1382.620000 2132.220000 1383.720000 2132.700000 ;
+ RECT 1382.620000 2126.780000 1383.720000 2127.260000 ;
+ RECT 1382.620000 2121.340000 1383.720000 2121.820000 ;
+ RECT 1382.620000 2099.580000 1383.720000 2100.060000 ;
+ RECT 1382.620000 2105.020000 1383.720000 2105.500000 ;
+ RECT 1382.620000 2110.460000 1383.720000 2110.940000 ;
+ RECT 1382.620000 2115.900000 1383.720000 2116.380000 ;
+ RECT 1436.930000 2088.700000 1437.930000 2089.180000 ;
+ RECT 1436.930000 2094.140000 1437.930000 2094.620000 ;
+ RECT 1427.620000 2094.140000 1428.720000 2094.620000 ;
+ RECT 1427.620000 2088.700000 1428.720000 2089.180000 ;
+ RECT 1427.620000 2083.260000 1428.720000 2083.740000 ;
+ RECT 1427.620000 2077.820000 1428.720000 2078.300000 ;
+ RECT 1436.930000 2083.260000 1437.930000 2083.740000 ;
+ RECT 1436.930000 2077.820000 1437.930000 2078.300000 ;
+ RECT 1436.930000 2061.500000 1437.930000 2061.980000 ;
+ RECT 1436.930000 2066.940000 1437.930000 2067.420000 ;
+ RECT 1436.930000 2072.380000 1437.930000 2072.860000 ;
+ RECT 1427.620000 2066.940000 1428.720000 2067.420000 ;
+ RECT 1427.620000 2061.500000 1428.720000 2061.980000 ;
+ RECT 1427.620000 2072.380000 1428.720000 2072.860000 ;
+ RECT 1427.620000 2056.060000 1428.720000 2056.540000 ;
+ RECT 1427.620000 2050.620000 1428.720000 2051.100000 ;
+ RECT 1436.930000 2056.060000 1437.930000 2056.540000 ;
+ RECT 1436.930000 2050.620000 1437.930000 2051.100000 ;
+ RECT 1382.620000 2094.140000 1383.720000 2094.620000 ;
+ RECT 1382.620000 2088.700000 1383.720000 2089.180000 ;
+ RECT 1382.620000 2083.260000 1383.720000 2083.740000 ;
+ RECT 1382.620000 2077.820000 1383.720000 2078.300000 ;
+ RECT 1382.620000 2066.940000 1383.720000 2067.420000 ;
+ RECT 1382.620000 2061.500000 1383.720000 2061.980000 ;
+ RECT 1382.620000 2056.060000 1383.720000 2056.540000 ;
+ RECT 1382.620000 2050.620000 1383.720000 2051.100000 ;
+ RECT 1382.620000 2072.380000 1383.720000 2072.860000 ;
+ RECT 1337.620000 2137.660000 1338.720000 2138.140000 ;
+ RECT 1337.620000 2132.220000 1338.720000 2132.700000 ;
+ RECT 1337.620000 2126.780000 1338.720000 2127.260000 ;
+ RECT 1292.620000 2137.660000 1293.720000 2138.140000 ;
+ RECT 1292.620000 2132.220000 1293.720000 2132.700000 ;
+ RECT 1292.620000 2126.780000 1293.720000 2127.260000 ;
+ RECT 1337.620000 2110.460000 1338.720000 2110.940000 ;
+ RECT 1337.620000 2105.020000 1338.720000 2105.500000 ;
+ RECT 1337.620000 2099.580000 1338.720000 2100.060000 ;
+ RECT 1337.620000 2115.900000 1338.720000 2116.380000 ;
+ RECT 1337.620000 2121.340000 1338.720000 2121.820000 ;
+ RECT 1292.620000 2121.340000 1293.720000 2121.820000 ;
+ RECT 1292.620000 2110.460000 1293.720000 2110.940000 ;
+ RECT 1292.620000 2105.020000 1293.720000 2105.500000 ;
+ RECT 1292.620000 2099.580000 1293.720000 2100.060000 ;
+ RECT 1292.620000 2115.900000 1293.720000 2116.380000 ;
+ RECT 1247.620000 2137.660000 1248.720000 2138.140000 ;
+ RECT 1243.490000 2137.660000 1244.490000 2138.140000 ;
+ RECT 1243.490000 2132.220000 1244.490000 2132.700000 ;
+ RECT 1247.620000 2132.220000 1248.720000 2132.700000 ;
+ RECT 1247.620000 2126.780000 1248.720000 2127.260000 ;
+ RECT 1243.490000 2126.780000 1244.490000 2127.260000 ;
+ RECT 1247.620000 2121.340000 1248.720000 2121.820000 ;
+ RECT 1243.490000 2121.340000 1244.490000 2121.820000 ;
+ RECT 1247.620000 2115.900000 1248.720000 2116.380000 ;
+ RECT 1243.490000 2115.900000 1244.490000 2116.380000 ;
+ RECT 1247.620000 2105.020000 1248.720000 2105.500000 ;
+ RECT 1243.490000 2105.020000 1244.490000 2105.500000 ;
+ RECT 1247.620000 2099.580000 1248.720000 2100.060000 ;
+ RECT 1243.490000 2099.580000 1244.490000 2100.060000 ;
+ RECT 1247.620000 2110.460000 1248.720000 2110.940000 ;
+ RECT 1243.490000 2110.460000 1244.490000 2110.940000 ;
+ RECT 1337.620000 2094.140000 1338.720000 2094.620000 ;
+ RECT 1337.620000 2088.700000 1338.720000 2089.180000 ;
+ RECT 1337.620000 2083.260000 1338.720000 2083.740000 ;
+ RECT 1337.620000 2077.820000 1338.720000 2078.300000 ;
+ RECT 1292.620000 2094.140000 1293.720000 2094.620000 ;
+ RECT 1292.620000 2088.700000 1293.720000 2089.180000 ;
+ RECT 1292.620000 2083.260000 1293.720000 2083.740000 ;
+ RECT 1292.620000 2077.820000 1293.720000 2078.300000 ;
+ RECT 1337.620000 2066.940000 1338.720000 2067.420000 ;
+ RECT 1337.620000 2050.620000 1338.720000 2051.100000 ;
+ RECT 1337.620000 2056.060000 1338.720000 2056.540000 ;
+ RECT 1337.620000 2061.500000 1338.720000 2061.980000 ;
+ RECT 1337.620000 2072.380000 1338.720000 2072.860000 ;
+ RECT 1292.620000 2050.620000 1293.720000 2051.100000 ;
+ RECT 1292.620000 2056.060000 1293.720000 2056.540000 ;
+ RECT 1292.620000 2061.500000 1293.720000 2061.980000 ;
+ RECT 1292.620000 2066.940000 1293.720000 2067.420000 ;
+ RECT 1292.620000 2072.380000 1293.720000 2072.860000 ;
+ RECT 1247.620000 2094.140000 1248.720000 2094.620000 ;
+ RECT 1243.490000 2094.140000 1244.490000 2094.620000 ;
+ RECT 1247.620000 2088.700000 1248.720000 2089.180000 ;
+ RECT 1243.490000 2088.700000 1244.490000 2089.180000 ;
+ RECT 1247.620000 2083.260000 1248.720000 2083.740000 ;
+ RECT 1243.490000 2083.260000 1244.490000 2083.740000 ;
+ RECT 1247.620000 2077.820000 1248.720000 2078.300000 ;
+ RECT 1243.490000 2077.820000 1244.490000 2078.300000 ;
+ RECT 1247.620000 2072.380000 1248.720000 2072.860000 ;
+ RECT 1247.620000 2066.940000 1248.720000 2067.420000 ;
+ RECT 1243.490000 2072.380000 1244.490000 2072.860000 ;
+ RECT 1243.490000 2066.940000 1244.490000 2067.420000 ;
+ RECT 1247.620000 2061.500000 1248.720000 2061.980000 ;
+ RECT 1243.490000 2061.500000 1244.490000 2061.980000 ;
+ RECT 1247.620000 2056.060000 1248.720000 2056.540000 ;
+ RECT 1243.490000 2056.060000 1244.490000 2056.540000 ;
+ RECT 1247.620000 2050.620000 1248.720000 2051.100000 ;
+ RECT 1243.490000 2050.620000 1244.490000 2051.100000 ;
+ RECT 1427.620000 2045.180000 1428.720000 2045.660000 ;
+ RECT 1427.620000 2039.740000 1428.720000 2040.220000 ;
+ RECT 1436.930000 2045.180000 1437.930000 2045.660000 ;
+ RECT 1436.930000 2039.740000 1437.930000 2040.220000 ;
+ RECT 1436.930000 2023.420000 1437.930000 2023.900000 ;
+ RECT 1436.930000 2028.860000 1437.930000 2029.340000 ;
+ RECT 1436.930000 2034.300000 1437.930000 2034.780000 ;
+ RECT 1427.620000 2034.300000 1428.720000 2034.780000 ;
+ RECT 1427.620000 2028.860000 1428.720000 2029.340000 ;
+ RECT 1427.620000 2023.420000 1428.720000 2023.900000 ;
+ RECT 1427.620000 2012.540000 1428.720000 2013.020000 ;
+ RECT 1427.620000 2017.980000 1428.720000 2018.460000 ;
+ RECT 1436.930000 2017.980000 1437.930000 2018.460000 ;
+ RECT 1436.930000 2012.540000 1437.930000 2013.020000 ;
+ RECT 1436.930000 2001.660000 1437.930000 2002.140000 ;
+ RECT 1436.930000 2007.100000 1437.930000 2007.580000 ;
+ RECT 1427.620000 2001.660000 1428.720000 2002.140000 ;
+ RECT 1427.620000 2007.100000 1428.720000 2007.580000 ;
+ RECT 1382.620000 2045.180000 1383.720000 2045.660000 ;
+ RECT 1382.620000 2039.740000 1383.720000 2040.220000 ;
+ RECT 1382.620000 2034.300000 1383.720000 2034.780000 ;
+ RECT 1382.620000 2028.860000 1383.720000 2029.340000 ;
+ RECT 1382.620000 2023.420000 1383.720000 2023.900000 ;
+ RECT 1382.620000 2001.660000 1383.720000 2002.140000 ;
+ RECT 1382.620000 2007.100000 1383.720000 2007.580000 ;
+ RECT 1382.620000 2012.540000 1383.720000 2013.020000 ;
+ RECT 1382.620000 2017.980000 1383.720000 2018.460000 ;
+ RECT 1427.620000 1996.220000 1428.720000 1996.700000 ;
+ RECT 1427.620000 1990.780000 1428.720000 1991.260000 ;
+ RECT 1436.930000 1996.220000 1437.930000 1996.700000 ;
+ RECT 1436.930000 1990.780000 1437.930000 1991.260000 ;
+ RECT 1427.620000 1979.900000 1428.720000 1980.380000 ;
+ RECT 1427.620000 1974.460000 1428.720000 1974.940000 ;
+ RECT 1436.930000 1979.900000 1437.930000 1980.380000 ;
+ RECT 1436.930000 1974.460000 1437.930000 1974.940000 ;
+ RECT 1427.620000 1985.340000 1428.720000 1985.820000 ;
+ RECT 1436.930000 1985.340000 1437.930000 1985.820000 ;
+ RECT 1436.930000 1963.580000 1437.930000 1964.060000 ;
+ RECT 1436.930000 1969.020000 1437.930000 1969.500000 ;
+ RECT 1427.620000 1969.020000 1428.720000 1969.500000 ;
+ RECT 1427.620000 1963.580000 1428.720000 1964.060000 ;
+ RECT 1427.620000 1958.140000 1428.720000 1958.620000 ;
+ RECT 1427.620000 1952.700000 1428.720000 1953.180000 ;
+ RECT 1436.930000 1958.140000 1437.930000 1958.620000 ;
+ RECT 1436.930000 1952.700000 1437.930000 1953.180000 ;
+ RECT 1382.620000 1996.220000 1383.720000 1996.700000 ;
+ RECT 1382.620000 1990.780000 1383.720000 1991.260000 ;
+ RECT 1382.620000 1985.340000 1383.720000 1985.820000 ;
+ RECT 1382.620000 1979.900000 1383.720000 1980.380000 ;
+ RECT 1382.620000 1974.460000 1383.720000 1974.940000 ;
+ RECT 1382.620000 1969.020000 1383.720000 1969.500000 ;
+ RECT 1382.620000 1963.580000 1383.720000 1964.060000 ;
+ RECT 1382.620000 1958.140000 1383.720000 1958.620000 ;
+ RECT 1382.620000 1952.700000 1383.720000 1953.180000 ;
+ RECT 1337.620000 2045.180000 1338.720000 2045.660000 ;
+ RECT 1337.620000 2039.740000 1338.720000 2040.220000 ;
+ RECT 1337.620000 2034.300000 1338.720000 2034.780000 ;
+ RECT 1337.620000 2028.860000 1338.720000 2029.340000 ;
+ RECT 1337.620000 2023.420000 1338.720000 2023.900000 ;
+ RECT 1292.620000 2045.180000 1293.720000 2045.660000 ;
+ RECT 1292.620000 2039.740000 1293.720000 2040.220000 ;
+ RECT 1292.620000 2034.300000 1293.720000 2034.780000 ;
+ RECT 1292.620000 2028.860000 1293.720000 2029.340000 ;
+ RECT 1292.620000 2023.420000 1293.720000 2023.900000 ;
+ RECT 1337.620000 2017.980000 1338.720000 2018.460000 ;
+ RECT 1337.620000 2012.540000 1338.720000 2013.020000 ;
+ RECT 1337.620000 2007.100000 1338.720000 2007.580000 ;
+ RECT 1337.620000 2001.660000 1338.720000 2002.140000 ;
+ RECT 1292.620000 2012.540000 1293.720000 2013.020000 ;
+ RECT 1292.620000 2007.100000 1293.720000 2007.580000 ;
+ RECT 1292.620000 2001.660000 1293.720000 2002.140000 ;
+ RECT 1292.620000 2017.980000 1293.720000 2018.460000 ;
+ RECT 1247.620000 2045.180000 1248.720000 2045.660000 ;
+ RECT 1243.490000 2045.180000 1244.490000 2045.660000 ;
+ RECT 1247.620000 2039.740000 1248.720000 2040.220000 ;
+ RECT 1243.490000 2039.740000 1244.490000 2040.220000 ;
+ RECT 1247.620000 2034.300000 1248.720000 2034.780000 ;
+ RECT 1243.490000 2034.300000 1244.490000 2034.780000 ;
+ RECT 1247.620000 2023.420000 1248.720000 2023.900000 ;
+ RECT 1243.490000 2023.420000 1244.490000 2023.900000 ;
+ RECT 1243.490000 2028.860000 1244.490000 2029.340000 ;
+ RECT 1247.620000 2028.860000 1248.720000 2029.340000 ;
+ RECT 1247.620000 2017.980000 1248.720000 2018.460000 ;
+ RECT 1243.490000 2017.980000 1244.490000 2018.460000 ;
+ RECT 1247.620000 2012.540000 1248.720000 2013.020000 ;
+ RECT 1243.490000 2012.540000 1244.490000 2013.020000 ;
+ RECT 1247.620000 2007.100000 1248.720000 2007.580000 ;
+ RECT 1243.490000 2007.100000 1244.490000 2007.580000 ;
+ RECT 1247.620000 2001.660000 1248.720000 2002.140000 ;
+ RECT 1243.490000 2001.660000 1244.490000 2002.140000 ;
+ RECT 1337.620000 1996.220000 1338.720000 1996.700000 ;
+ RECT 1337.620000 1990.780000 1338.720000 1991.260000 ;
+ RECT 1337.620000 1985.340000 1338.720000 1985.820000 ;
+ RECT 1337.620000 1979.900000 1338.720000 1980.380000 ;
+ RECT 1337.620000 1974.460000 1338.720000 1974.940000 ;
+ RECT 1292.620000 1996.220000 1293.720000 1996.700000 ;
+ RECT 1292.620000 1990.780000 1293.720000 1991.260000 ;
+ RECT 1292.620000 1985.340000 1293.720000 1985.820000 ;
+ RECT 1292.620000 1979.900000 1293.720000 1980.380000 ;
+ RECT 1292.620000 1974.460000 1293.720000 1974.940000 ;
+ RECT 1337.620000 1952.700000 1338.720000 1953.180000 ;
+ RECT 1337.620000 1958.140000 1338.720000 1958.620000 ;
+ RECT 1337.620000 1963.580000 1338.720000 1964.060000 ;
+ RECT 1337.620000 1969.020000 1338.720000 1969.500000 ;
+ RECT 1292.620000 1952.700000 1293.720000 1953.180000 ;
+ RECT 1292.620000 1958.140000 1293.720000 1958.620000 ;
+ RECT 1292.620000 1963.580000 1293.720000 1964.060000 ;
+ RECT 1292.620000 1969.020000 1293.720000 1969.500000 ;
+ RECT 1247.620000 1996.220000 1248.720000 1996.700000 ;
+ RECT 1243.490000 1996.220000 1244.490000 1996.700000 ;
+ RECT 1247.620000 1990.780000 1248.720000 1991.260000 ;
+ RECT 1243.490000 1990.780000 1244.490000 1991.260000 ;
+ RECT 1247.620000 1979.900000 1248.720000 1980.380000 ;
+ RECT 1243.490000 1979.900000 1244.490000 1980.380000 ;
+ RECT 1247.620000 1974.460000 1248.720000 1974.940000 ;
+ RECT 1243.490000 1974.460000 1244.490000 1974.940000 ;
+ RECT 1247.620000 1985.340000 1248.720000 1985.820000 ;
+ RECT 1243.490000 1985.340000 1244.490000 1985.820000 ;
+ RECT 1247.620000 1969.020000 1248.720000 1969.500000 ;
+ RECT 1243.490000 1969.020000 1244.490000 1969.500000 ;
+ RECT 1247.620000 1963.580000 1248.720000 1964.060000 ;
+ RECT 1243.490000 1963.580000 1244.490000 1964.060000 ;
+ RECT 1247.620000 1958.140000 1248.720000 1958.620000 ;
+ RECT 1247.620000 1952.700000 1248.720000 1953.180000 ;
+ RECT 1243.490000 1958.140000 1244.490000 1958.620000 ;
+ RECT 1243.490000 1952.700000 1244.490000 1953.180000 ;
+ RECT 1240.660000 2143.060000 1440.760000 2144.060000 ;
+ RECT 1240.660000 1950.690000 1440.760000 1951.690000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 1947.840000 1244.490000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 2147.100000 1244.490000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 1947.840000 1437.930000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 2147.100000 1437.930000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1950.690000 1241.660000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1950.690000 1440.760000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 2143.060000 1241.660000 2144.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 2143.060000 1440.760000 2144.060000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 1750.430000 1428.720000 1943.800000 ;
+ RECT 1382.620000 1750.430000 1383.720000 1943.800000 ;
+ RECT 1436.930000 1747.580000 1437.930000 1947.840000 ;
+ RECT 1337.620000 1750.430000 1338.720000 1943.800000 ;
+ RECT 1292.620000 1750.430000 1293.720000 1943.800000 ;
+ RECT 1247.620000 1750.430000 1248.720000 1943.800000 ;
+ RECT 1243.490000 1747.580000 1244.490000 1947.840000 ;
+ LAYER met3 ;
+ RECT 1427.620000 1937.400000 1428.720000 1937.880000 ;
+ RECT 1436.930000 1937.400000 1437.930000 1937.880000 ;
+ RECT 1436.930000 1926.520000 1437.930000 1927.000000 ;
+ RECT 1436.930000 1931.960000 1437.930000 1932.440000 ;
+ RECT 1427.620000 1931.960000 1428.720000 1932.440000 ;
+ RECT 1427.620000 1926.520000 1428.720000 1927.000000 ;
+ RECT 1427.620000 1921.080000 1428.720000 1921.560000 ;
+ RECT 1427.620000 1915.640000 1428.720000 1916.120000 ;
+ RECT 1436.930000 1921.080000 1437.930000 1921.560000 ;
+ RECT 1436.930000 1915.640000 1437.930000 1916.120000 ;
+ RECT 1427.620000 1899.320000 1428.720000 1899.800000 ;
+ RECT 1427.620000 1904.760000 1428.720000 1905.240000 ;
+ RECT 1436.930000 1904.760000 1437.930000 1905.240000 ;
+ RECT 1436.930000 1899.320000 1437.930000 1899.800000 ;
+ RECT 1427.620000 1910.200000 1428.720000 1910.680000 ;
+ RECT 1436.930000 1910.200000 1437.930000 1910.680000 ;
+ RECT 1382.620000 1937.400000 1383.720000 1937.880000 ;
+ RECT 1382.620000 1931.960000 1383.720000 1932.440000 ;
+ RECT 1382.620000 1926.520000 1383.720000 1927.000000 ;
+ RECT 1382.620000 1921.080000 1383.720000 1921.560000 ;
+ RECT 1382.620000 1899.320000 1383.720000 1899.800000 ;
+ RECT 1382.620000 1904.760000 1383.720000 1905.240000 ;
+ RECT 1382.620000 1910.200000 1383.720000 1910.680000 ;
+ RECT 1382.620000 1915.640000 1383.720000 1916.120000 ;
+ RECT 1436.930000 1888.440000 1437.930000 1888.920000 ;
+ RECT 1436.930000 1893.880000 1437.930000 1894.360000 ;
+ RECT 1427.620000 1893.880000 1428.720000 1894.360000 ;
+ RECT 1427.620000 1888.440000 1428.720000 1888.920000 ;
+ RECT 1427.620000 1883.000000 1428.720000 1883.480000 ;
+ RECT 1427.620000 1877.560000 1428.720000 1878.040000 ;
+ RECT 1436.930000 1883.000000 1437.930000 1883.480000 ;
+ RECT 1436.930000 1877.560000 1437.930000 1878.040000 ;
+ RECT 1436.930000 1861.240000 1437.930000 1861.720000 ;
+ RECT 1436.930000 1866.680000 1437.930000 1867.160000 ;
+ RECT 1436.930000 1872.120000 1437.930000 1872.600000 ;
+ RECT 1427.620000 1866.680000 1428.720000 1867.160000 ;
+ RECT 1427.620000 1861.240000 1428.720000 1861.720000 ;
+ RECT 1427.620000 1872.120000 1428.720000 1872.600000 ;
+ RECT 1427.620000 1855.800000 1428.720000 1856.280000 ;
+ RECT 1427.620000 1850.360000 1428.720000 1850.840000 ;
+ RECT 1436.930000 1855.800000 1437.930000 1856.280000 ;
+ RECT 1436.930000 1850.360000 1437.930000 1850.840000 ;
+ RECT 1382.620000 1893.880000 1383.720000 1894.360000 ;
+ RECT 1382.620000 1888.440000 1383.720000 1888.920000 ;
+ RECT 1382.620000 1883.000000 1383.720000 1883.480000 ;
+ RECT 1382.620000 1877.560000 1383.720000 1878.040000 ;
+ RECT 1382.620000 1866.680000 1383.720000 1867.160000 ;
+ RECT 1382.620000 1861.240000 1383.720000 1861.720000 ;
+ RECT 1382.620000 1855.800000 1383.720000 1856.280000 ;
+ RECT 1382.620000 1850.360000 1383.720000 1850.840000 ;
+ RECT 1382.620000 1872.120000 1383.720000 1872.600000 ;
+ RECT 1337.620000 1937.400000 1338.720000 1937.880000 ;
+ RECT 1337.620000 1931.960000 1338.720000 1932.440000 ;
+ RECT 1337.620000 1926.520000 1338.720000 1927.000000 ;
+ RECT 1292.620000 1937.400000 1293.720000 1937.880000 ;
+ RECT 1292.620000 1931.960000 1293.720000 1932.440000 ;
+ RECT 1292.620000 1926.520000 1293.720000 1927.000000 ;
+ RECT 1337.620000 1910.200000 1338.720000 1910.680000 ;
+ RECT 1337.620000 1904.760000 1338.720000 1905.240000 ;
+ RECT 1337.620000 1899.320000 1338.720000 1899.800000 ;
+ RECT 1337.620000 1915.640000 1338.720000 1916.120000 ;
+ RECT 1337.620000 1921.080000 1338.720000 1921.560000 ;
+ RECT 1292.620000 1921.080000 1293.720000 1921.560000 ;
+ RECT 1292.620000 1910.200000 1293.720000 1910.680000 ;
+ RECT 1292.620000 1904.760000 1293.720000 1905.240000 ;
+ RECT 1292.620000 1899.320000 1293.720000 1899.800000 ;
+ RECT 1292.620000 1915.640000 1293.720000 1916.120000 ;
+ RECT 1247.620000 1937.400000 1248.720000 1937.880000 ;
+ RECT 1243.490000 1937.400000 1244.490000 1937.880000 ;
+ RECT 1243.490000 1931.960000 1244.490000 1932.440000 ;
+ RECT 1247.620000 1931.960000 1248.720000 1932.440000 ;
+ RECT 1247.620000 1926.520000 1248.720000 1927.000000 ;
+ RECT 1243.490000 1926.520000 1244.490000 1927.000000 ;
+ RECT 1247.620000 1921.080000 1248.720000 1921.560000 ;
+ RECT 1243.490000 1921.080000 1244.490000 1921.560000 ;
+ RECT 1247.620000 1915.640000 1248.720000 1916.120000 ;
+ RECT 1243.490000 1915.640000 1244.490000 1916.120000 ;
+ RECT 1247.620000 1904.760000 1248.720000 1905.240000 ;
+ RECT 1243.490000 1904.760000 1244.490000 1905.240000 ;
+ RECT 1247.620000 1899.320000 1248.720000 1899.800000 ;
+ RECT 1243.490000 1899.320000 1244.490000 1899.800000 ;
+ RECT 1247.620000 1910.200000 1248.720000 1910.680000 ;
+ RECT 1243.490000 1910.200000 1244.490000 1910.680000 ;
+ RECT 1337.620000 1893.880000 1338.720000 1894.360000 ;
+ RECT 1337.620000 1888.440000 1338.720000 1888.920000 ;
+ RECT 1337.620000 1883.000000 1338.720000 1883.480000 ;
+ RECT 1337.620000 1877.560000 1338.720000 1878.040000 ;
+ RECT 1292.620000 1893.880000 1293.720000 1894.360000 ;
+ RECT 1292.620000 1888.440000 1293.720000 1888.920000 ;
+ RECT 1292.620000 1883.000000 1293.720000 1883.480000 ;
+ RECT 1292.620000 1877.560000 1293.720000 1878.040000 ;
+ RECT 1337.620000 1866.680000 1338.720000 1867.160000 ;
+ RECT 1337.620000 1850.360000 1338.720000 1850.840000 ;
+ RECT 1337.620000 1855.800000 1338.720000 1856.280000 ;
+ RECT 1337.620000 1861.240000 1338.720000 1861.720000 ;
+ RECT 1337.620000 1872.120000 1338.720000 1872.600000 ;
+ RECT 1292.620000 1850.360000 1293.720000 1850.840000 ;
+ RECT 1292.620000 1855.800000 1293.720000 1856.280000 ;
+ RECT 1292.620000 1861.240000 1293.720000 1861.720000 ;
+ RECT 1292.620000 1866.680000 1293.720000 1867.160000 ;
+ RECT 1292.620000 1872.120000 1293.720000 1872.600000 ;
+ RECT 1247.620000 1893.880000 1248.720000 1894.360000 ;
+ RECT 1243.490000 1893.880000 1244.490000 1894.360000 ;
+ RECT 1247.620000 1888.440000 1248.720000 1888.920000 ;
+ RECT 1243.490000 1888.440000 1244.490000 1888.920000 ;
+ RECT 1247.620000 1883.000000 1248.720000 1883.480000 ;
+ RECT 1243.490000 1883.000000 1244.490000 1883.480000 ;
+ RECT 1247.620000 1877.560000 1248.720000 1878.040000 ;
+ RECT 1243.490000 1877.560000 1244.490000 1878.040000 ;
+ RECT 1247.620000 1872.120000 1248.720000 1872.600000 ;
+ RECT 1247.620000 1866.680000 1248.720000 1867.160000 ;
+ RECT 1243.490000 1872.120000 1244.490000 1872.600000 ;
+ RECT 1243.490000 1866.680000 1244.490000 1867.160000 ;
+ RECT 1247.620000 1861.240000 1248.720000 1861.720000 ;
+ RECT 1243.490000 1861.240000 1244.490000 1861.720000 ;
+ RECT 1247.620000 1855.800000 1248.720000 1856.280000 ;
+ RECT 1243.490000 1855.800000 1244.490000 1856.280000 ;
+ RECT 1247.620000 1850.360000 1248.720000 1850.840000 ;
+ RECT 1243.490000 1850.360000 1244.490000 1850.840000 ;
+ RECT 1427.620000 1844.920000 1428.720000 1845.400000 ;
+ RECT 1427.620000 1839.480000 1428.720000 1839.960000 ;
+ RECT 1436.930000 1844.920000 1437.930000 1845.400000 ;
+ RECT 1436.930000 1839.480000 1437.930000 1839.960000 ;
+ RECT 1436.930000 1823.160000 1437.930000 1823.640000 ;
+ RECT 1436.930000 1828.600000 1437.930000 1829.080000 ;
+ RECT 1436.930000 1834.040000 1437.930000 1834.520000 ;
+ RECT 1427.620000 1834.040000 1428.720000 1834.520000 ;
+ RECT 1427.620000 1828.600000 1428.720000 1829.080000 ;
+ RECT 1427.620000 1823.160000 1428.720000 1823.640000 ;
+ RECT 1427.620000 1812.280000 1428.720000 1812.760000 ;
+ RECT 1427.620000 1817.720000 1428.720000 1818.200000 ;
+ RECT 1436.930000 1817.720000 1437.930000 1818.200000 ;
+ RECT 1436.930000 1812.280000 1437.930000 1812.760000 ;
+ RECT 1436.930000 1801.400000 1437.930000 1801.880000 ;
+ RECT 1436.930000 1806.840000 1437.930000 1807.320000 ;
+ RECT 1427.620000 1801.400000 1428.720000 1801.880000 ;
+ RECT 1427.620000 1806.840000 1428.720000 1807.320000 ;
+ RECT 1382.620000 1844.920000 1383.720000 1845.400000 ;
+ RECT 1382.620000 1839.480000 1383.720000 1839.960000 ;
+ RECT 1382.620000 1834.040000 1383.720000 1834.520000 ;
+ RECT 1382.620000 1828.600000 1383.720000 1829.080000 ;
+ RECT 1382.620000 1823.160000 1383.720000 1823.640000 ;
+ RECT 1382.620000 1801.400000 1383.720000 1801.880000 ;
+ RECT 1382.620000 1806.840000 1383.720000 1807.320000 ;
+ RECT 1382.620000 1812.280000 1383.720000 1812.760000 ;
+ RECT 1382.620000 1817.720000 1383.720000 1818.200000 ;
+ RECT 1427.620000 1795.960000 1428.720000 1796.440000 ;
+ RECT 1427.620000 1790.520000 1428.720000 1791.000000 ;
+ RECT 1436.930000 1795.960000 1437.930000 1796.440000 ;
+ RECT 1436.930000 1790.520000 1437.930000 1791.000000 ;
+ RECT 1427.620000 1779.640000 1428.720000 1780.120000 ;
+ RECT 1427.620000 1774.200000 1428.720000 1774.680000 ;
+ RECT 1436.930000 1779.640000 1437.930000 1780.120000 ;
+ RECT 1436.930000 1774.200000 1437.930000 1774.680000 ;
+ RECT 1427.620000 1785.080000 1428.720000 1785.560000 ;
+ RECT 1436.930000 1785.080000 1437.930000 1785.560000 ;
+ RECT 1436.930000 1763.320000 1437.930000 1763.800000 ;
+ RECT 1436.930000 1768.760000 1437.930000 1769.240000 ;
+ RECT 1427.620000 1768.760000 1428.720000 1769.240000 ;
+ RECT 1427.620000 1763.320000 1428.720000 1763.800000 ;
+ RECT 1427.620000 1757.880000 1428.720000 1758.360000 ;
+ RECT 1427.620000 1752.440000 1428.720000 1752.920000 ;
+ RECT 1436.930000 1757.880000 1437.930000 1758.360000 ;
+ RECT 1436.930000 1752.440000 1437.930000 1752.920000 ;
+ RECT 1382.620000 1795.960000 1383.720000 1796.440000 ;
+ RECT 1382.620000 1790.520000 1383.720000 1791.000000 ;
+ RECT 1382.620000 1785.080000 1383.720000 1785.560000 ;
+ RECT 1382.620000 1779.640000 1383.720000 1780.120000 ;
+ RECT 1382.620000 1774.200000 1383.720000 1774.680000 ;
+ RECT 1382.620000 1768.760000 1383.720000 1769.240000 ;
+ RECT 1382.620000 1763.320000 1383.720000 1763.800000 ;
+ RECT 1382.620000 1757.880000 1383.720000 1758.360000 ;
+ RECT 1382.620000 1752.440000 1383.720000 1752.920000 ;
+ RECT 1337.620000 1844.920000 1338.720000 1845.400000 ;
+ RECT 1337.620000 1839.480000 1338.720000 1839.960000 ;
+ RECT 1337.620000 1834.040000 1338.720000 1834.520000 ;
+ RECT 1337.620000 1828.600000 1338.720000 1829.080000 ;
+ RECT 1337.620000 1823.160000 1338.720000 1823.640000 ;
+ RECT 1292.620000 1844.920000 1293.720000 1845.400000 ;
+ RECT 1292.620000 1839.480000 1293.720000 1839.960000 ;
+ RECT 1292.620000 1834.040000 1293.720000 1834.520000 ;
+ RECT 1292.620000 1828.600000 1293.720000 1829.080000 ;
+ RECT 1292.620000 1823.160000 1293.720000 1823.640000 ;
+ RECT 1337.620000 1817.720000 1338.720000 1818.200000 ;
+ RECT 1337.620000 1812.280000 1338.720000 1812.760000 ;
+ RECT 1337.620000 1806.840000 1338.720000 1807.320000 ;
+ RECT 1337.620000 1801.400000 1338.720000 1801.880000 ;
+ RECT 1292.620000 1812.280000 1293.720000 1812.760000 ;
+ RECT 1292.620000 1806.840000 1293.720000 1807.320000 ;
+ RECT 1292.620000 1801.400000 1293.720000 1801.880000 ;
+ RECT 1292.620000 1817.720000 1293.720000 1818.200000 ;
+ RECT 1247.620000 1844.920000 1248.720000 1845.400000 ;
+ RECT 1243.490000 1844.920000 1244.490000 1845.400000 ;
+ RECT 1247.620000 1839.480000 1248.720000 1839.960000 ;
+ RECT 1243.490000 1839.480000 1244.490000 1839.960000 ;
+ RECT 1247.620000 1834.040000 1248.720000 1834.520000 ;
+ RECT 1243.490000 1834.040000 1244.490000 1834.520000 ;
+ RECT 1247.620000 1823.160000 1248.720000 1823.640000 ;
+ RECT 1243.490000 1823.160000 1244.490000 1823.640000 ;
+ RECT 1243.490000 1828.600000 1244.490000 1829.080000 ;
+ RECT 1247.620000 1828.600000 1248.720000 1829.080000 ;
+ RECT 1247.620000 1817.720000 1248.720000 1818.200000 ;
+ RECT 1243.490000 1817.720000 1244.490000 1818.200000 ;
+ RECT 1247.620000 1812.280000 1248.720000 1812.760000 ;
+ RECT 1243.490000 1812.280000 1244.490000 1812.760000 ;
+ RECT 1247.620000 1806.840000 1248.720000 1807.320000 ;
+ RECT 1243.490000 1806.840000 1244.490000 1807.320000 ;
+ RECT 1247.620000 1801.400000 1248.720000 1801.880000 ;
+ RECT 1243.490000 1801.400000 1244.490000 1801.880000 ;
+ RECT 1337.620000 1795.960000 1338.720000 1796.440000 ;
+ RECT 1337.620000 1790.520000 1338.720000 1791.000000 ;
+ RECT 1337.620000 1785.080000 1338.720000 1785.560000 ;
+ RECT 1337.620000 1779.640000 1338.720000 1780.120000 ;
+ RECT 1337.620000 1774.200000 1338.720000 1774.680000 ;
+ RECT 1292.620000 1795.960000 1293.720000 1796.440000 ;
+ RECT 1292.620000 1790.520000 1293.720000 1791.000000 ;
+ RECT 1292.620000 1785.080000 1293.720000 1785.560000 ;
+ RECT 1292.620000 1779.640000 1293.720000 1780.120000 ;
+ RECT 1292.620000 1774.200000 1293.720000 1774.680000 ;
+ RECT 1337.620000 1752.440000 1338.720000 1752.920000 ;
+ RECT 1337.620000 1757.880000 1338.720000 1758.360000 ;
+ RECT 1337.620000 1763.320000 1338.720000 1763.800000 ;
+ RECT 1337.620000 1768.760000 1338.720000 1769.240000 ;
+ RECT 1292.620000 1752.440000 1293.720000 1752.920000 ;
+ RECT 1292.620000 1757.880000 1293.720000 1758.360000 ;
+ RECT 1292.620000 1763.320000 1293.720000 1763.800000 ;
+ RECT 1292.620000 1768.760000 1293.720000 1769.240000 ;
+ RECT 1247.620000 1795.960000 1248.720000 1796.440000 ;
+ RECT 1243.490000 1795.960000 1244.490000 1796.440000 ;
+ RECT 1247.620000 1790.520000 1248.720000 1791.000000 ;
+ RECT 1243.490000 1790.520000 1244.490000 1791.000000 ;
+ RECT 1247.620000 1779.640000 1248.720000 1780.120000 ;
+ RECT 1243.490000 1779.640000 1244.490000 1780.120000 ;
+ RECT 1247.620000 1774.200000 1248.720000 1774.680000 ;
+ RECT 1243.490000 1774.200000 1244.490000 1774.680000 ;
+ RECT 1247.620000 1785.080000 1248.720000 1785.560000 ;
+ RECT 1243.490000 1785.080000 1244.490000 1785.560000 ;
+ RECT 1247.620000 1768.760000 1248.720000 1769.240000 ;
+ RECT 1243.490000 1768.760000 1244.490000 1769.240000 ;
+ RECT 1247.620000 1763.320000 1248.720000 1763.800000 ;
+ RECT 1243.490000 1763.320000 1244.490000 1763.800000 ;
+ RECT 1247.620000 1757.880000 1248.720000 1758.360000 ;
+ RECT 1247.620000 1752.440000 1248.720000 1752.920000 ;
+ RECT 1243.490000 1757.880000 1244.490000 1758.360000 ;
+ RECT 1243.490000 1752.440000 1244.490000 1752.920000 ;
+ RECT 1240.660000 1942.800000 1440.760000 1943.800000 ;
+ RECT 1240.660000 1750.430000 1440.760000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 1747.580000 1244.490000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 1946.840000 1244.490000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 1747.580000 1437.930000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 1946.840000 1437.930000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1750.430000 1241.660000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1750.430000 1440.760000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1942.800000 1241.660000 1943.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1942.800000 1440.760000 1943.800000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1427.620000 1550.170000 1428.720000 1743.540000 ;
+ RECT 1382.620000 1550.170000 1383.720000 1743.540000 ;
+ RECT 1436.930000 1547.320000 1437.930000 1747.580000 ;
+ RECT 1337.620000 1550.170000 1338.720000 1743.540000 ;
+ RECT 1292.620000 1550.170000 1293.720000 1743.540000 ;
+ RECT 1247.620000 1550.170000 1248.720000 1743.540000 ;
+ RECT 1243.490000 1547.320000 1244.490000 1747.580000 ;
+ LAYER met3 ;
+ RECT 1427.620000 1737.140000 1428.720000 1737.620000 ;
+ RECT 1436.930000 1737.140000 1437.930000 1737.620000 ;
+ RECT 1436.930000 1726.260000 1437.930000 1726.740000 ;
+ RECT 1436.930000 1731.700000 1437.930000 1732.180000 ;
+ RECT 1427.620000 1731.700000 1428.720000 1732.180000 ;
+ RECT 1427.620000 1726.260000 1428.720000 1726.740000 ;
+ RECT 1427.620000 1720.820000 1428.720000 1721.300000 ;
+ RECT 1427.620000 1715.380000 1428.720000 1715.860000 ;
+ RECT 1436.930000 1720.820000 1437.930000 1721.300000 ;
+ RECT 1436.930000 1715.380000 1437.930000 1715.860000 ;
+ RECT 1427.620000 1699.060000 1428.720000 1699.540000 ;
+ RECT 1427.620000 1704.500000 1428.720000 1704.980000 ;
+ RECT 1436.930000 1704.500000 1437.930000 1704.980000 ;
+ RECT 1436.930000 1699.060000 1437.930000 1699.540000 ;
+ RECT 1427.620000 1709.940000 1428.720000 1710.420000 ;
+ RECT 1436.930000 1709.940000 1437.930000 1710.420000 ;
+ RECT 1382.620000 1737.140000 1383.720000 1737.620000 ;
+ RECT 1382.620000 1731.700000 1383.720000 1732.180000 ;
+ RECT 1382.620000 1726.260000 1383.720000 1726.740000 ;
+ RECT 1382.620000 1720.820000 1383.720000 1721.300000 ;
+ RECT 1382.620000 1699.060000 1383.720000 1699.540000 ;
+ RECT 1382.620000 1704.500000 1383.720000 1704.980000 ;
+ RECT 1382.620000 1709.940000 1383.720000 1710.420000 ;
+ RECT 1382.620000 1715.380000 1383.720000 1715.860000 ;
+ RECT 1436.930000 1688.180000 1437.930000 1688.660000 ;
+ RECT 1436.930000 1693.620000 1437.930000 1694.100000 ;
+ RECT 1427.620000 1693.620000 1428.720000 1694.100000 ;
+ RECT 1427.620000 1688.180000 1428.720000 1688.660000 ;
+ RECT 1427.620000 1682.740000 1428.720000 1683.220000 ;
+ RECT 1427.620000 1677.300000 1428.720000 1677.780000 ;
+ RECT 1436.930000 1682.740000 1437.930000 1683.220000 ;
+ RECT 1436.930000 1677.300000 1437.930000 1677.780000 ;
+ RECT 1436.930000 1660.980000 1437.930000 1661.460000 ;
+ RECT 1436.930000 1666.420000 1437.930000 1666.900000 ;
+ RECT 1436.930000 1671.860000 1437.930000 1672.340000 ;
+ RECT 1427.620000 1666.420000 1428.720000 1666.900000 ;
+ RECT 1427.620000 1660.980000 1428.720000 1661.460000 ;
+ RECT 1427.620000 1671.860000 1428.720000 1672.340000 ;
+ RECT 1427.620000 1655.540000 1428.720000 1656.020000 ;
+ RECT 1427.620000 1650.100000 1428.720000 1650.580000 ;
+ RECT 1436.930000 1655.540000 1437.930000 1656.020000 ;
+ RECT 1436.930000 1650.100000 1437.930000 1650.580000 ;
+ RECT 1382.620000 1693.620000 1383.720000 1694.100000 ;
+ RECT 1382.620000 1688.180000 1383.720000 1688.660000 ;
+ RECT 1382.620000 1682.740000 1383.720000 1683.220000 ;
+ RECT 1382.620000 1677.300000 1383.720000 1677.780000 ;
+ RECT 1382.620000 1666.420000 1383.720000 1666.900000 ;
+ RECT 1382.620000 1660.980000 1383.720000 1661.460000 ;
+ RECT 1382.620000 1655.540000 1383.720000 1656.020000 ;
+ RECT 1382.620000 1650.100000 1383.720000 1650.580000 ;
+ RECT 1382.620000 1671.860000 1383.720000 1672.340000 ;
+ RECT 1337.620000 1737.140000 1338.720000 1737.620000 ;
+ RECT 1337.620000 1731.700000 1338.720000 1732.180000 ;
+ RECT 1337.620000 1726.260000 1338.720000 1726.740000 ;
+ RECT 1292.620000 1737.140000 1293.720000 1737.620000 ;
+ RECT 1292.620000 1731.700000 1293.720000 1732.180000 ;
+ RECT 1292.620000 1726.260000 1293.720000 1726.740000 ;
+ RECT 1337.620000 1709.940000 1338.720000 1710.420000 ;
+ RECT 1337.620000 1704.500000 1338.720000 1704.980000 ;
+ RECT 1337.620000 1699.060000 1338.720000 1699.540000 ;
+ RECT 1337.620000 1715.380000 1338.720000 1715.860000 ;
+ RECT 1337.620000 1720.820000 1338.720000 1721.300000 ;
+ RECT 1292.620000 1720.820000 1293.720000 1721.300000 ;
+ RECT 1292.620000 1709.940000 1293.720000 1710.420000 ;
+ RECT 1292.620000 1704.500000 1293.720000 1704.980000 ;
+ RECT 1292.620000 1699.060000 1293.720000 1699.540000 ;
+ RECT 1292.620000 1715.380000 1293.720000 1715.860000 ;
+ RECT 1247.620000 1737.140000 1248.720000 1737.620000 ;
+ RECT 1243.490000 1737.140000 1244.490000 1737.620000 ;
+ RECT 1243.490000 1731.700000 1244.490000 1732.180000 ;
+ RECT 1247.620000 1731.700000 1248.720000 1732.180000 ;
+ RECT 1247.620000 1726.260000 1248.720000 1726.740000 ;
+ RECT 1243.490000 1726.260000 1244.490000 1726.740000 ;
+ RECT 1247.620000 1720.820000 1248.720000 1721.300000 ;
+ RECT 1243.490000 1720.820000 1244.490000 1721.300000 ;
+ RECT 1247.620000 1715.380000 1248.720000 1715.860000 ;
+ RECT 1243.490000 1715.380000 1244.490000 1715.860000 ;
+ RECT 1247.620000 1704.500000 1248.720000 1704.980000 ;
+ RECT 1243.490000 1704.500000 1244.490000 1704.980000 ;
+ RECT 1247.620000 1699.060000 1248.720000 1699.540000 ;
+ RECT 1243.490000 1699.060000 1244.490000 1699.540000 ;
+ RECT 1247.620000 1709.940000 1248.720000 1710.420000 ;
+ RECT 1243.490000 1709.940000 1244.490000 1710.420000 ;
+ RECT 1337.620000 1693.620000 1338.720000 1694.100000 ;
+ RECT 1337.620000 1688.180000 1338.720000 1688.660000 ;
+ RECT 1337.620000 1682.740000 1338.720000 1683.220000 ;
+ RECT 1337.620000 1677.300000 1338.720000 1677.780000 ;
+ RECT 1292.620000 1693.620000 1293.720000 1694.100000 ;
+ RECT 1292.620000 1688.180000 1293.720000 1688.660000 ;
+ RECT 1292.620000 1682.740000 1293.720000 1683.220000 ;
+ RECT 1292.620000 1677.300000 1293.720000 1677.780000 ;
+ RECT 1337.620000 1666.420000 1338.720000 1666.900000 ;
+ RECT 1337.620000 1650.100000 1338.720000 1650.580000 ;
+ RECT 1337.620000 1655.540000 1338.720000 1656.020000 ;
+ RECT 1337.620000 1660.980000 1338.720000 1661.460000 ;
+ RECT 1337.620000 1671.860000 1338.720000 1672.340000 ;
+ RECT 1292.620000 1650.100000 1293.720000 1650.580000 ;
+ RECT 1292.620000 1655.540000 1293.720000 1656.020000 ;
+ RECT 1292.620000 1660.980000 1293.720000 1661.460000 ;
+ RECT 1292.620000 1666.420000 1293.720000 1666.900000 ;
+ RECT 1292.620000 1671.860000 1293.720000 1672.340000 ;
+ RECT 1247.620000 1693.620000 1248.720000 1694.100000 ;
+ RECT 1243.490000 1693.620000 1244.490000 1694.100000 ;
+ RECT 1247.620000 1688.180000 1248.720000 1688.660000 ;
+ RECT 1243.490000 1688.180000 1244.490000 1688.660000 ;
+ RECT 1247.620000 1682.740000 1248.720000 1683.220000 ;
+ RECT 1243.490000 1682.740000 1244.490000 1683.220000 ;
+ RECT 1247.620000 1677.300000 1248.720000 1677.780000 ;
+ RECT 1243.490000 1677.300000 1244.490000 1677.780000 ;
+ RECT 1247.620000 1671.860000 1248.720000 1672.340000 ;
+ RECT 1247.620000 1666.420000 1248.720000 1666.900000 ;
+ RECT 1243.490000 1671.860000 1244.490000 1672.340000 ;
+ RECT 1243.490000 1666.420000 1244.490000 1666.900000 ;
+ RECT 1247.620000 1660.980000 1248.720000 1661.460000 ;
+ RECT 1243.490000 1660.980000 1244.490000 1661.460000 ;
+ RECT 1247.620000 1655.540000 1248.720000 1656.020000 ;
+ RECT 1243.490000 1655.540000 1244.490000 1656.020000 ;
+ RECT 1247.620000 1650.100000 1248.720000 1650.580000 ;
+ RECT 1243.490000 1650.100000 1244.490000 1650.580000 ;
+ RECT 1427.620000 1644.660000 1428.720000 1645.140000 ;
+ RECT 1427.620000 1639.220000 1428.720000 1639.700000 ;
+ RECT 1436.930000 1644.660000 1437.930000 1645.140000 ;
+ RECT 1436.930000 1639.220000 1437.930000 1639.700000 ;
+ RECT 1436.930000 1622.900000 1437.930000 1623.380000 ;
+ RECT 1436.930000 1628.340000 1437.930000 1628.820000 ;
+ RECT 1436.930000 1633.780000 1437.930000 1634.260000 ;
+ RECT 1427.620000 1633.780000 1428.720000 1634.260000 ;
+ RECT 1427.620000 1628.340000 1428.720000 1628.820000 ;
+ RECT 1427.620000 1622.900000 1428.720000 1623.380000 ;
+ RECT 1427.620000 1612.020000 1428.720000 1612.500000 ;
+ RECT 1427.620000 1617.460000 1428.720000 1617.940000 ;
+ RECT 1436.930000 1617.460000 1437.930000 1617.940000 ;
+ RECT 1436.930000 1612.020000 1437.930000 1612.500000 ;
+ RECT 1436.930000 1601.140000 1437.930000 1601.620000 ;
+ RECT 1436.930000 1606.580000 1437.930000 1607.060000 ;
+ RECT 1427.620000 1601.140000 1428.720000 1601.620000 ;
+ RECT 1427.620000 1606.580000 1428.720000 1607.060000 ;
+ RECT 1382.620000 1644.660000 1383.720000 1645.140000 ;
+ RECT 1382.620000 1639.220000 1383.720000 1639.700000 ;
+ RECT 1382.620000 1633.780000 1383.720000 1634.260000 ;
+ RECT 1382.620000 1628.340000 1383.720000 1628.820000 ;
+ RECT 1382.620000 1622.900000 1383.720000 1623.380000 ;
+ RECT 1382.620000 1601.140000 1383.720000 1601.620000 ;
+ RECT 1382.620000 1606.580000 1383.720000 1607.060000 ;
+ RECT 1382.620000 1612.020000 1383.720000 1612.500000 ;
+ RECT 1382.620000 1617.460000 1383.720000 1617.940000 ;
+ RECT 1427.620000 1595.700000 1428.720000 1596.180000 ;
+ RECT 1427.620000 1590.260000 1428.720000 1590.740000 ;
+ RECT 1436.930000 1595.700000 1437.930000 1596.180000 ;
+ RECT 1436.930000 1590.260000 1437.930000 1590.740000 ;
+ RECT 1427.620000 1579.380000 1428.720000 1579.860000 ;
+ RECT 1427.620000 1573.940000 1428.720000 1574.420000 ;
+ RECT 1436.930000 1579.380000 1437.930000 1579.860000 ;
+ RECT 1436.930000 1573.940000 1437.930000 1574.420000 ;
+ RECT 1427.620000 1584.820000 1428.720000 1585.300000 ;
+ RECT 1436.930000 1584.820000 1437.930000 1585.300000 ;
+ RECT 1436.930000 1563.060000 1437.930000 1563.540000 ;
+ RECT 1436.930000 1568.500000 1437.930000 1568.980000 ;
+ RECT 1427.620000 1568.500000 1428.720000 1568.980000 ;
+ RECT 1427.620000 1563.060000 1428.720000 1563.540000 ;
+ RECT 1427.620000 1557.620000 1428.720000 1558.100000 ;
+ RECT 1427.620000 1552.180000 1428.720000 1552.660000 ;
+ RECT 1436.930000 1557.620000 1437.930000 1558.100000 ;
+ RECT 1436.930000 1552.180000 1437.930000 1552.660000 ;
+ RECT 1382.620000 1595.700000 1383.720000 1596.180000 ;
+ RECT 1382.620000 1590.260000 1383.720000 1590.740000 ;
+ RECT 1382.620000 1584.820000 1383.720000 1585.300000 ;
+ RECT 1382.620000 1579.380000 1383.720000 1579.860000 ;
+ RECT 1382.620000 1573.940000 1383.720000 1574.420000 ;
+ RECT 1382.620000 1568.500000 1383.720000 1568.980000 ;
+ RECT 1382.620000 1563.060000 1383.720000 1563.540000 ;
+ RECT 1382.620000 1557.620000 1383.720000 1558.100000 ;
+ RECT 1382.620000 1552.180000 1383.720000 1552.660000 ;
+ RECT 1337.620000 1644.660000 1338.720000 1645.140000 ;
+ RECT 1337.620000 1639.220000 1338.720000 1639.700000 ;
+ RECT 1337.620000 1633.780000 1338.720000 1634.260000 ;
+ RECT 1337.620000 1628.340000 1338.720000 1628.820000 ;
+ RECT 1337.620000 1622.900000 1338.720000 1623.380000 ;
+ RECT 1292.620000 1644.660000 1293.720000 1645.140000 ;
+ RECT 1292.620000 1639.220000 1293.720000 1639.700000 ;
+ RECT 1292.620000 1633.780000 1293.720000 1634.260000 ;
+ RECT 1292.620000 1628.340000 1293.720000 1628.820000 ;
+ RECT 1292.620000 1622.900000 1293.720000 1623.380000 ;
+ RECT 1337.620000 1617.460000 1338.720000 1617.940000 ;
+ RECT 1337.620000 1612.020000 1338.720000 1612.500000 ;
+ RECT 1337.620000 1606.580000 1338.720000 1607.060000 ;
+ RECT 1337.620000 1601.140000 1338.720000 1601.620000 ;
+ RECT 1292.620000 1612.020000 1293.720000 1612.500000 ;
+ RECT 1292.620000 1606.580000 1293.720000 1607.060000 ;
+ RECT 1292.620000 1601.140000 1293.720000 1601.620000 ;
+ RECT 1292.620000 1617.460000 1293.720000 1617.940000 ;
+ RECT 1247.620000 1644.660000 1248.720000 1645.140000 ;
+ RECT 1243.490000 1644.660000 1244.490000 1645.140000 ;
+ RECT 1247.620000 1639.220000 1248.720000 1639.700000 ;
+ RECT 1243.490000 1639.220000 1244.490000 1639.700000 ;
+ RECT 1247.620000 1633.780000 1248.720000 1634.260000 ;
+ RECT 1243.490000 1633.780000 1244.490000 1634.260000 ;
+ RECT 1247.620000 1622.900000 1248.720000 1623.380000 ;
+ RECT 1243.490000 1622.900000 1244.490000 1623.380000 ;
+ RECT 1243.490000 1628.340000 1244.490000 1628.820000 ;
+ RECT 1247.620000 1628.340000 1248.720000 1628.820000 ;
+ RECT 1247.620000 1617.460000 1248.720000 1617.940000 ;
+ RECT 1243.490000 1617.460000 1244.490000 1617.940000 ;
+ RECT 1247.620000 1612.020000 1248.720000 1612.500000 ;
+ RECT 1243.490000 1612.020000 1244.490000 1612.500000 ;
+ RECT 1247.620000 1606.580000 1248.720000 1607.060000 ;
+ RECT 1243.490000 1606.580000 1244.490000 1607.060000 ;
+ RECT 1247.620000 1601.140000 1248.720000 1601.620000 ;
+ RECT 1243.490000 1601.140000 1244.490000 1601.620000 ;
+ RECT 1337.620000 1595.700000 1338.720000 1596.180000 ;
+ RECT 1337.620000 1590.260000 1338.720000 1590.740000 ;
+ RECT 1337.620000 1584.820000 1338.720000 1585.300000 ;
+ RECT 1337.620000 1579.380000 1338.720000 1579.860000 ;
+ RECT 1337.620000 1573.940000 1338.720000 1574.420000 ;
+ RECT 1292.620000 1595.700000 1293.720000 1596.180000 ;
+ RECT 1292.620000 1590.260000 1293.720000 1590.740000 ;
+ RECT 1292.620000 1584.820000 1293.720000 1585.300000 ;
+ RECT 1292.620000 1579.380000 1293.720000 1579.860000 ;
+ RECT 1292.620000 1573.940000 1293.720000 1574.420000 ;
+ RECT 1337.620000 1552.180000 1338.720000 1552.660000 ;
+ RECT 1337.620000 1557.620000 1338.720000 1558.100000 ;
+ RECT 1337.620000 1563.060000 1338.720000 1563.540000 ;
+ RECT 1337.620000 1568.500000 1338.720000 1568.980000 ;
+ RECT 1292.620000 1552.180000 1293.720000 1552.660000 ;
+ RECT 1292.620000 1557.620000 1293.720000 1558.100000 ;
+ RECT 1292.620000 1563.060000 1293.720000 1563.540000 ;
+ RECT 1292.620000 1568.500000 1293.720000 1568.980000 ;
+ RECT 1247.620000 1595.700000 1248.720000 1596.180000 ;
+ RECT 1243.490000 1595.700000 1244.490000 1596.180000 ;
+ RECT 1247.620000 1590.260000 1248.720000 1590.740000 ;
+ RECT 1243.490000 1590.260000 1244.490000 1590.740000 ;
+ RECT 1247.620000 1579.380000 1248.720000 1579.860000 ;
+ RECT 1243.490000 1579.380000 1244.490000 1579.860000 ;
+ RECT 1247.620000 1573.940000 1248.720000 1574.420000 ;
+ RECT 1243.490000 1573.940000 1244.490000 1574.420000 ;
+ RECT 1247.620000 1584.820000 1248.720000 1585.300000 ;
+ RECT 1243.490000 1584.820000 1244.490000 1585.300000 ;
+ RECT 1247.620000 1568.500000 1248.720000 1568.980000 ;
+ RECT 1243.490000 1568.500000 1244.490000 1568.980000 ;
+ RECT 1247.620000 1563.060000 1248.720000 1563.540000 ;
+ RECT 1243.490000 1563.060000 1244.490000 1563.540000 ;
+ RECT 1247.620000 1557.620000 1248.720000 1558.100000 ;
+ RECT 1247.620000 1552.180000 1248.720000 1552.660000 ;
+ RECT 1243.490000 1557.620000 1244.490000 1558.100000 ;
+ RECT 1243.490000 1552.180000 1244.490000 1552.660000 ;
+ RECT 1240.660000 1742.540000 1440.760000 1743.540000 ;
+ RECT 1240.660000 1550.170000 1440.760000 1551.170000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 1547.320000 1244.490000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1243.490000 1746.580000 1244.490000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 1547.320000 1437.930000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1436.930000 1746.580000 1437.930000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1550.170000 1241.660000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1550.170000 1440.760000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1240.660000 1742.540000 1241.660000 1743.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1439.760000 1742.540000 1440.760000 1743.540000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 3349.660000 1449.590000 3379.920000 ;
+ RECT 1642.030000 3349.660000 1643.030000 3379.920000 ;
+ RECT 1452.720000 3352.510000 1453.820000 3376.560000 ;
+ RECT 1497.720000 3352.510000 1498.820000 3376.560000 ;
+ RECT 1542.720000 3352.510000 1543.820000 3376.560000 ;
+ RECT 1587.720000 3352.510000 1588.820000 3376.560000 ;
+ RECT 1632.720000 3352.510000 1633.820000 3376.560000 ;
+ LAYER met3 ;
+ RECT 1642.030000 3365.400000 1643.030000 3365.880000 ;
+ RECT 1642.030000 3370.840000 1643.030000 3371.320000 ;
+ RECT 1632.720000 3370.840000 1633.820000 3371.320000 ;
+ RECT 1632.720000 3365.400000 1633.820000 3365.880000 ;
+ RECT 1587.720000 3365.400000 1588.820000 3365.880000 ;
+ RECT 1587.720000 3370.840000 1588.820000 3371.320000 ;
+ RECT 1497.720000 3365.400000 1498.820000 3365.880000 ;
+ RECT 1542.720000 3365.400000 1543.820000 3365.880000 ;
+ RECT 1542.720000 3370.840000 1543.820000 3371.320000 ;
+ RECT 1497.720000 3370.840000 1498.820000 3371.320000 ;
+ RECT 1448.590000 3365.400000 1449.590000 3365.880000 ;
+ RECT 1452.720000 3365.400000 1453.820000 3365.880000 ;
+ RECT 1452.720000 3370.840000 1453.820000 3371.320000 ;
+ RECT 1448.590000 3370.840000 1449.590000 3371.320000 ;
+ RECT 1642.030000 3354.520000 1643.030000 3355.000000 ;
+ RECT 1642.030000 3359.960000 1643.030000 3360.440000 ;
+ RECT 1632.720000 3359.960000 1633.820000 3360.440000 ;
+ RECT 1632.720000 3354.520000 1633.820000 3355.000000 ;
+ RECT 1587.720000 3354.520000 1588.820000 3355.000000 ;
+ RECT 1587.720000 3359.960000 1588.820000 3360.440000 ;
+ RECT 1497.720000 3354.520000 1498.820000 3355.000000 ;
+ RECT 1542.720000 3354.520000 1543.820000 3355.000000 ;
+ RECT 1542.720000 3359.960000 1543.820000 3360.440000 ;
+ RECT 1497.720000 3359.960000 1498.820000 3360.440000 ;
+ RECT 1448.590000 3359.960000 1449.590000 3360.440000 ;
+ RECT 1452.720000 3359.960000 1453.820000 3360.440000 ;
+ RECT 1448.590000 3354.520000 1449.590000 3355.000000 ;
+ RECT 1452.720000 3354.520000 1453.820000 3355.000000 ;
+ RECT 1445.760000 3375.560000 1645.860000 3376.560000 ;
+ RECT 1445.760000 3352.510000 1645.860000 3353.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 3349.660000 1449.590000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 3378.920000 1449.590000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 3349.660000 1643.030000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 3378.920000 1643.030000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 3352.510000 1446.760000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 3352.510000 1645.860000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 3375.560000 1446.760000 3376.560000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 3375.560000 1645.860000 3376.560000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 946.540000 1449.590000 1347.060000 ;
+ RECT 1642.030000 946.540000 1643.030000 1347.060000 ;
+ RECT 1452.720000 949.390000 1453.820000 1343.530000 ;
+ RECT 1497.720000 949.390000 1498.820000 1343.530000 ;
+ RECT 1542.720000 949.390000 1543.820000 1343.530000 ;
+ RECT 1587.720000 949.390000 1588.820000 1343.530000 ;
+ RECT 1632.720000 949.390000 1633.820000 1343.530000 ;
+ LAYER met3 ;
+ RECT 1632.720000 1337.640000 1633.820000 1338.120000 ;
+ RECT 1642.030000 1337.640000 1643.030000 1338.120000 ;
+ RECT 1642.030000 1332.200000 1643.030000 1332.680000 ;
+ RECT 1632.720000 1332.200000 1633.820000 1332.680000 ;
+ RECT 1632.720000 1326.760000 1633.820000 1327.240000 ;
+ RECT 1642.030000 1326.760000 1643.030000 1327.240000 ;
+ RECT 1642.030000 1310.440000 1643.030000 1310.920000 ;
+ RECT 1642.030000 1315.880000 1643.030000 1316.360000 ;
+ RECT 1642.030000 1321.320000 1643.030000 1321.800000 ;
+ RECT 1632.720000 1321.320000 1633.820000 1321.800000 ;
+ RECT 1632.720000 1310.440000 1633.820000 1310.920000 ;
+ RECT 1632.720000 1315.880000 1633.820000 1316.360000 ;
+ RECT 1632.720000 1299.560000 1633.820000 1300.040000 ;
+ RECT 1632.720000 1305.000000 1633.820000 1305.480000 ;
+ RECT 1642.030000 1305.000000 1643.030000 1305.480000 ;
+ RECT 1642.030000 1299.560000 1643.030000 1300.040000 ;
+ RECT 1587.720000 1337.640000 1588.820000 1338.120000 ;
+ RECT 1587.720000 1332.200000 1588.820000 1332.680000 ;
+ RECT 1587.720000 1326.760000 1588.820000 1327.240000 ;
+ RECT 1587.720000 1321.320000 1588.820000 1321.800000 ;
+ RECT 1587.720000 1299.560000 1588.820000 1300.040000 ;
+ RECT 1587.720000 1305.000000 1588.820000 1305.480000 ;
+ RECT 1587.720000 1310.440000 1588.820000 1310.920000 ;
+ RECT 1587.720000 1315.880000 1588.820000 1316.360000 ;
+ RECT 1632.720000 1294.120000 1633.820000 1294.600000 ;
+ RECT 1632.720000 1288.680000 1633.820000 1289.160000 ;
+ RECT 1642.030000 1294.120000 1643.030000 1294.600000 ;
+ RECT 1642.030000 1288.680000 1643.030000 1289.160000 ;
+ RECT 1642.030000 1272.360000 1643.030000 1272.840000 ;
+ RECT 1642.030000 1277.800000 1643.030000 1278.280000 ;
+ RECT 1642.030000 1283.240000 1643.030000 1283.720000 ;
+ RECT 1632.720000 1283.240000 1633.820000 1283.720000 ;
+ RECT 1632.720000 1277.800000 1633.820000 1278.280000 ;
+ RECT 1632.720000 1272.360000 1633.820000 1272.840000 ;
+ RECT 1632.720000 1261.480000 1633.820000 1261.960000 ;
+ RECT 1632.720000 1266.920000 1633.820000 1267.400000 ;
+ RECT 1642.030000 1266.920000 1643.030000 1267.400000 ;
+ RECT 1642.030000 1261.480000 1643.030000 1261.960000 ;
+ RECT 1642.030000 1250.600000 1643.030000 1251.080000 ;
+ RECT 1642.030000 1256.040000 1643.030000 1256.520000 ;
+ RECT 1632.720000 1250.600000 1633.820000 1251.080000 ;
+ RECT 1632.720000 1256.040000 1633.820000 1256.520000 ;
+ RECT 1587.720000 1294.120000 1588.820000 1294.600000 ;
+ RECT 1587.720000 1288.680000 1588.820000 1289.160000 ;
+ RECT 1587.720000 1283.240000 1588.820000 1283.720000 ;
+ RECT 1587.720000 1277.800000 1588.820000 1278.280000 ;
+ RECT 1587.720000 1272.360000 1588.820000 1272.840000 ;
+ RECT 1587.720000 1250.600000 1588.820000 1251.080000 ;
+ RECT 1587.720000 1256.040000 1588.820000 1256.520000 ;
+ RECT 1587.720000 1261.480000 1588.820000 1261.960000 ;
+ RECT 1587.720000 1266.920000 1588.820000 1267.400000 ;
+ RECT 1632.720000 1245.160000 1633.820000 1245.640000 ;
+ RECT 1632.720000 1239.720000 1633.820000 1240.200000 ;
+ RECT 1642.030000 1245.160000 1643.030000 1245.640000 ;
+ RECT 1642.030000 1239.720000 1643.030000 1240.200000 ;
+ RECT 1632.720000 1228.840000 1633.820000 1229.320000 ;
+ RECT 1632.720000 1223.400000 1633.820000 1223.880000 ;
+ RECT 1642.030000 1228.840000 1643.030000 1229.320000 ;
+ RECT 1642.030000 1223.400000 1643.030000 1223.880000 ;
+ RECT 1632.720000 1234.280000 1633.820000 1234.760000 ;
+ RECT 1642.030000 1234.280000 1643.030000 1234.760000 ;
+ RECT 1642.030000 1212.520000 1643.030000 1213.000000 ;
+ RECT 1642.030000 1217.960000 1643.030000 1218.440000 ;
+ RECT 1632.720000 1212.520000 1633.820000 1213.000000 ;
+ RECT 1632.720000 1217.960000 1633.820000 1218.440000 ;
+ RECT 1632.720000 1201.640000 1633.820000 1202.120000 ;
+ RECT 1632.720000 1207.080000 1633.820000 1207.560000 ;
+ RECT 1642.030000 1207.080000 1643.030000 1207.560000 ;
+ RECT 1642.030000 1201.640000 1643.030000 1202.120000 ;
+ RECT 1587.720000 1245.160000 1588.820000 1245.640000 ;
+ RECT 1587.720000 1239.720000 1588.820000 1240.200000 ;
+ RECT 1587.720000 1234.280000 1588.820000 1234.760000 ;
+ RECT 1587.720000 1228.840000 1588.820000 1229.320000 ;
+ RECT 1587.720000 1223.400000 1588.820000 1223.880000 ;
+ RECT 1587.720000 1201.640000 1588.820000 1202.120000 ;
+ RECT 1587.720000 1207.080000 1588.820000 1207.560000 ;
+ RECT 1587.720000 1212.520000 1588.820000 1213.000000 ;
+ RECT 1587.720000 1217.960000 1588.820000 1218.440000 ;
+ RECT 1642.030000 1185.320000 1643.030000 1185.800000 ;
+ RECT 1642.030000 1190.760000 1643.030000 1191.240000 ;
+ RECT 1642.030000 1196.200000 1643.030000 1196.680000 ;
+ RECT 1632.720000 1196.200000 1633.820000 1196.680000 ;
+ RECT 1632.720000 1190.760000 1633.820000 1191.240000 ;
+ RECT 1632.720000 1185.320000 1633.820000 1185.800000 ;
+ RECT 1632.720000 1179.880000 1633.820000 1180.360000 ;
+ RECT 1632.720000 1174.440000 1633.820000 1174.920000 ;
+ RECT 1642.030000 1179.880000 1643.030000 1180.360000 ;
+ RECT 1642.030000 1174.440000 1643.030000 1174.920000 ;
+ RECT 1632.720000 1163.560000 1633.820000 1164.040000 ;
+ RECT 1632.720000 1169.000000 1633.820000 1169.480000 ;
+ RECT 1642.030000 1169.000000 1643.030000 1169.480000 ;
+ RECT 1642.030000 1163.560000 1643.030000 1164.040000 ;
+ RECT 1642.030000 1147.240000 1643.030000 1147.720000 ;
+ RECT 1642.030000 1152.680000 1643.030000 1153.160000 ;
+ RECT 1642.030000 1158.120000 1643.030000 1158.600000 ;
+ RECT 1632.720000 1158.120000 1633.820000 1158.600000 ;
+ RECT 1632.720000 1152.680000 1633.820000 1153.160000 ;
+ RECT 1632.720000 1147.240000 1633.820000 1147.720000 ;
+ RECT 1587.720000 1196.200000 1588.820000 1196.680000 ;
+ RECT 1587.720000 1190.760000 1588.820000 1191.240000 ;
+ RECT 1587.720000 1185.320000 1588.820000 1185.800000 ;
+ RECT 1587.720000 1179.880000 1588.820000 1180.360000 ;
+ RECT 1587.720000 1174.440000 1588.820000 1174.920000 ;
+ RECT 1587.720000 1163.560000 1588.820000 1164.040000 ;
+ RECT 1587.720000 1158.120000 1588.820000 1158.600000 ;
+ RECT 1587.720000 1152.680000 1588.820000 1153.160000 ;
+ RECT 1587.720000 1147.240000 1588.820000 1147.720000 ;
+ RECT 1587.720000 1169.000000 1588.820000 1169.480000 ;
+ RECT 1542.720000 1337.640000 1543.820000 1338.120000 ;
+ RECT 1542.720000 1332.200000 1543.820000 1332.680000 ;
+ RECT 1542.720000 1326.760000 1543.820000 1327.240000 ;
+ RECT 1497.720000 1337.640000 1498.820000 1338.120000 ;
+ RECT 1497.720000 1332.200000 1498.820000 1332.680000 ;
+ RECT 1497.720000 1326.760000 1498.820000 1327.240000 ;
+ RECT 1542.720000 1310.440000 1543.820000 1310.920000 ;
+ RECT 1542.720000 1305.000000 1543.820000 1305.480000 ;
+ RECT 1542.720000 1299.560000 1543.820000 1300.040000 ;
+ RECT 1542.720000 1315.880000 1543.820000 1316.360000 ;
+ RECT 1542.720000 1321.320000 1543.820000 1321.800000 ;
+ RECT 1497.720000 1321.320000 1498.820000 1321.800000 ;
+ RECT 1497.720000 1310.440000 1498.820000 1310.920000 ;
+ RECT 1497.720000 1305.000000 1498.820000 1305.480000 ;
+ RECT 1497.720000 1299.560000 1498.820000 1300.040000 ;
+ RECT 1497.720000 1315.880000 1498.820000 1316.360000 ;
+ RECT 1452.720000 1337.640000 1453.820000 1338.120000 ;
+ RECT 1448.590000 1337.640000 1449.590000 1338.120000 ;
+ RECT 1448.590000 1332.200000 1449.590000 1332.680000 ;
+ RECT 1452.720000 1332.200000 1453.820000 1332.680000 ;
+ RECT 1452.720000 1326.760000 1453.820000 1327.240000 ;
+ RECT 1448.590000 1326.760000 1449.590000 1327.240000 ;
+ RECT 1452.720000 1321.320000 1453.820000 1321.800000 ;
+ RECT 1452.720000 1315.880000 1453.820000 1316.360000 ;
+ RECT 1448.590000 1321.320000 1449.590000 1321.800000 ;
+ RECT 1448.590000 1315.880000 1449.590000 1316.360000 ;
+ RECT 1452.720000 1310.440000 1453.820000 1310.920000 ;
+ RECT 1448.590000 1310.440000 1449.590000 1310.920000 ;
+ RECT 1452.720000 1305.000000 1453.820000 1305.480000 ;
+ RECT 1448.590000 1305.000000 1449.590000 1305.480000 ;
+ RECT 1452.720000 1299.560000 1453.820000 1300.040000 ;
+ RECT 1448.590000 1299.560000 1449.590000 1300.040000 ;
+ RECT 1542.720000 1294.120000 1543.820000 1294.600000 ;
+ RECT 1542.720000 1288.680000 1543.820000 1289.160000 ;
+ RECT 1542.720000 1283.240000 1543.820000 1283.720000 ;
+ RECT 1542.720000 1277.800000 1543.820000 1278.280000 ;
+ RECT 1542.720000 1272.360000 1543.820000 1272.840000 ;
+ RECT 1497.720000 1294.120000 1498.820000 1294.600000 ;
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+ RECT 1497.720000 1283.240000 1498.820000 1283.720000 ;
+ RECT 1497.720000 1277.800000 1498.820000 1278.280000 ;
+ RECT 1497.720000 1272.360000 1498.820000 1272.840000 ;
+ RECT 1542.720000 1266.920000 1543.820000 1267.400000 ;
+ RECT 1542.720000 1261.480000 1543.820000 1261.960000 ;
+ RECT 1542.720000 1256.040000 1543.820000 1256.520000 ;
+ RECT 1542.720000 1250.600000 1543.820000 1251.080000 ;
+ RECT 1497.720000 1261.480000 1498.820000 1261.960000 ;
+ RECT 1497.720000 1256.040000 1498.820000 1256.520000 ;
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+ RECT 1497.720000 1266.920000 1498.820000 1267.400000 ;
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+ RECT 1448.590000 1294.120000 1449.590000 1294.600000 ;
+ RECT 1452.720000 1288.680000 1453.820000 1289.160000 ;
+ RECT 1448.590000 1288.680000 1449.590000 1289.160000 ;
+ RECT 1452.720000 1283.240000 1453.820000 1283.720000 ;
+ RECT 1448.590000 1283.240000 1449.590000 1283.720000 ;
+ RECT 1452.720000 1272.360000 1453.820000 1272.840000 ;
+ RECT 1448.590000 1272.360000 1449.590000 1272.840000 ;
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+ RECT 1452.720000 1277.800000 1453.820000 1278.280000 ;
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+ RECT 1448.590000 1266.920000 1449.590000 1267.400000 ;
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+ RECT 1448.590000 1261.480000 1449.590000 1261.960000 ;
+ RECT 1452.720000 1256.040000 1453.820000 1256.520000 ;
+ RECT 1448.590000 1256.040000 1449.590000 1256.520000 ;
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+ RECT 1448.590000 1250.600000 1449.590000 1251.080000 ;
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+ RECT 1497.720000 1245.160000 1498.820000 1245.640000 ;
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+ RECT 1448.590000 1245.160000 1449.590000 1245.640000 ;
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+ RECT 1448.590000 1239.720000 1449.590000 1240.200000 ;
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+ RECT 1448.590000 1228.840000 1449.590000 1229.320000 ;
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+ RECT 1448.590000 1223.400000 1449.590000 1223.880000 ;
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+ RECT 1448.590000 1234.280000 1449.590000 1234.760000 ;
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+ RECT 1448.590000 1217.960000 1449.590000 1218.440000 ;
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+ RECT 1542.720000 1011.240000 1543.820000 1011.720000 ;
+ RECT 1542.720000 1005.800000 1543.820000 1006.280000 ;
+ RECT 1542.720000 1000.360000 1543.820000 1000.840000 ;
+ RECT 1497.720000 1011.240000 1498.820000 1011.720000 ;
+ RECT 1497.720000 1005.800000 1498.820000 1006.280000 ;
+ RECT 1497.720000 1000.360000 1498.820000 1000.840000 ;
+ RECT 1497.720000 1016.680000 1498.820000 1017.160000 ;
+ RECT 1452.720000 1043.880000 1453.820000 1044.360000 ;
+ RECT 1448.590000 1043.880000 1449.590000 1044.360000 ;
+ RECT 1452.720000 1038.440000 1453.820000 1038.920000 ;
+ RECT 1448.590000 1038.440000 1449.590000 1038.920000 ;
+ RECT 1452.720000 1033.000000 1453.820000 1033.480000 ;
+ RECT 1448.590000 1033.000000 1449.590000 1033.480000 ;
+ RECT 1452.720000 1022.120000 1453.820000 1022.600000 ;
+ RECT 1448.590000 1022.120000 1449.590000 1022.600000 ;
+ RECT 1448.590000 1027.560000 1449.590000 1028.040000 ;
+ RECT 1452.720000 1027.560000 1453.820000 1028.040000 ;
+ RECT 1452.720000 1016.680000 1453.820000 1017.160000 ;
+ RECT 1448.590000 1016.680000 1449.590000 1017.160000 ;
+ RECT 1452.720000 1011.240000 1453.820000 1011.720000 ;
+ RECT 1448.590000 1011.240000 1449.590000 1011.720000 ;
+ RECT 1452.720000 1005.800000 1453.820000 1006.280000 ;
+ RECT 1448.590000 1005.800000 1449.590000 1006.280000 ;
+ RECT 1452.720000 1000.360000 1453.820000 1000.840000 ;
+ RECT 1448.590000 1000.360000 1449.590000 1000.840000 ;
+ RECT 1542.720000 994.920000 1543.820000 995.400000 ;
+ RECT 1542.720000 989.480000 1543.820000 989.960000 ;
+ RECT 1542.720000 984.040000 1543.820000 984.520000 ;
+ RECT 1542.720000 978.600000 1543.820000 979.080000 ;
+ RECT 1542.720000 973.160000 1543.820000 973.640000 ;
+ RECT 1497.720000 994.920000 1498.820000 995.400000 ;
+ RECT 1497.720000 989.480000 1498.820000 989.960000 ;
+ RECT 1497.720000 984.040000 1498.820000 984.520000 ;
+ RECT 1497.720000 978.600000 1498.820000 979.080000 ;
+ RECT 1497.720000 973.160000 1498.820000 973.640000 ;
+ RECT 1542.720000 951.400000 1543.820000 951.880000 ;
+ RECT 1542.720000 956.840000 1543.820000 957.320000 ;
+ RECT 1542.720000 962.280000 1543.820000 962.760000 ;
+ RECT 1542.720000 967.720000 1543.820000 968.200000 ;
+ RECT 1497.720000 951.400000 1498.820000 951.880000 ;
+ RECT 1497.720000 956.840000 1498.820000 957.320000 ;
+ RECT 1497.720000 962.280000 1498.820000 962.760000 ;
+ RECT 1497.720000 967.720000 1498.820000 968.200000 ;
+ RECT 1452.720000 994.920000 1453.820000 995.400000 ;
+ RECT 1448.590000 994.920000 1449.590000 995.400000 ;
+ RECT 1452.720000 989.480000 1453.820000 989.960000 ;
+ RECT 1448.590000 989.480000 1449.590000 989.960000 ;
+ RECT 1452.720000 978.600000 1453.820000 979.080000 ;
+ RECT 1448.590000 978.600000 1449.590000 979.080000 ;
+ RECT 1452.720000 973.160000 1453.820000 973.640000 ;
+ RECT 1448.590000 973.160000 1449.590000 973.640000 ;
+ RECT 1452.720000 984.040000 1453.820000 984.520000 ;
+ RECT 1448.590000 984.040000 1449.590000 984.520000 ;
+ RECT 1452.720000 967.720000 1453.820000 968.200000 ;
+ RECT 1448.590000 967.720000 1449.590000 968.200000 ;
+ RECT 1452.720000 962.280000 1453.820000 962.760000 ;
+ RECT 1448.590000 962.280000 1449.590000 962.760000 ;
+ RECT 1452.720000 956.840000 1453.820000 957.320000 ;
+ RECT 1452.720000 951.400000 1453.820000 951.880000 ;
+ RECT 1448.590000 956.840000 1449.590000 957.320000 ;
+ RECT 1448.590000 951.400000 1449.590000 951.880000 ;
+ RECT 1445.760000 1342.530000 1645.860000 1343.530000 ;
+ RECT 1445.760000 949.390000 1645.860000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 946.540000 1449.590000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 1346.060000 1449.590000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 946.540000 1643.030000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 1346.060000 1643.030000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 949.390000 1446.760000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 949.390000 1645.860000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 1342.530000 1446.760000 1343.530000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 1342.530000 1645.860000 1343.530000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 546.020000 1449.590000 946.540000 ;
+ RECT 1642.030000 546.020000 1643.030000 946.540000 ;
+ RECT 1452.720000 548.870000 1453.820000 943.010000 ;
+ RECT 1497.720000 548.870000 1498.820000 943.010000 ;
+ RECT 1542.720000 548.870000 1543.820000 943.010000 ;
+ RECT 1587.720000 548.870000 1588.820000 943.010000 ;
+ RECT 1632.720000 548.870000 1633.820000 943.010000 ;
+ LAYER met3 ;
+ RECT 1632.720000 937.120000 1633.820000 937.600000 ;
+ RECT 1642.030000 937.120000 1643.030000 937.600000 ;
+ RECT 1642.030000 931.680000 1643.030000 932.160000 ;
+ RECT 1632.720000 931.680000 1633.820000 932.160000 ;
+ RECT 1632.720000 926.240000 1633.820000 926.720000 ;
+ RECT 1642.030000 926.240000 1643.030000 926.720000 ;
+ RECT 1642.030000 909.920000 1643.030000 910.400000 ;
+ RECT 1642.030000 915.360000 1643.030000 915.840000 ;
+ RECT 1642.030000 920.800000 1643.030000 921.280000 ;
+ RECT 1632.720000 920.800000 1633.820000 921.280000 ;
+ RECT 1632.720000 909.920000 1633.820000 910.400000 ;
+ RECT 1632.720000 915.360000 1633.820000 915.840000 ;
+ RECT 1632.720000 899.040000 1633.820000 899.520000 ;
+ RECT 1632.720000 904.480000 1633.820000 904.960000 ;
+ RECT 1642.030000 904.480000 1643.030000 904.960000 ;
+ RECT 1642.030000 899.040000 1643.030000 899.520000 ;
+ RECT 1587.720000 937.120000 1588.820000 937.600000 ;
+ RECT 1587.720000 931.680000 1588.820000 932.160000 ;
+ RECT 1587.720000 926.240000 1588.820000 926.720000 ;
+ RECT 1587.720000 920.800000 1588.820000 921.280000 ;
+ RECT 1587.720000 899.040000 1588.820000 899.520000 ;
+ RECT 1587.720000 904.480000 1588.820000 904.960000 ;
+ RECT 1587.720000 909.920000 1588.820000 910.400000 ;
+ RECT 1587.720000 915.360000 1588.820000 915.840000 ;
+ RECT 1632.720000 893.600000 1633.820000 894.080000 ;
+ RECT 1632.720000 888.160000 1633.820000 888.640000 ;
+ RECT 1642.030000 893.600000 1643.030000 894.080000 ;
+ RECT 1642.030000 888.160000 1643.030000 888.640000 ;
+ RECT 1642.030000 871.840000 1643.030000 872.320000 ;
+ RECT 1642.030000 877.280000 1643.030000 877.760000 ;
+ RECT 1642.030000 882.720000 1643.030000 883.200000 ;
+ RECT 1632.720000 882.720000 1633.820000 883.200000 ;
+ RECT 1632.720000 877.280000 1633.820000 877.760000 ;
+ RECT 1632.720000 871.840000 1633.820000 872.320000 ;
+ RECT 1632.720000 860.960000 1633.820000 861.440000 ;
+ RECT 1632.720000 866.400000 1633.820000 866.880000 ;
+ RECT 1642.030000 866.400000 1643.030000 866.880000 ;
+ RECT 1642.030000 860.960000 1643.030000 861.440000 ;
+ RECT 1642.030000 850.080000 1643.030000 850.560000 ;
+ RECT 1642.030000 855.520000 1643.030000 856.000000 ;
+ RECT 1632.720000 850.080000 1633.820000 850.560000 ;
+ RECT 1632.720000 855.520000 1633.820000 856.000000 ;
+ RECT 1587.720000 893.600000 1588.820000 894.080000 ;
+ RECT 1587.720000 888.160000 1588.820000 888.640000 ;
+ RECT 1587.720000 882.720000 1588.820000 883.200000 ;
+ RECT 1587.720000 877.280000 1588.820000 877.760000 ;
+ RECT 1587.720000 871.840000 1588.820000 872.320000 ;
+ RECT 1587.720000 850.080000 1588.820000 850.560000 ;
+ RECT 1587.720000 855.520000 1588.820000 856.000000 ;
+ RECT 1587.720000 860.960000 1588.820000 861.440000 ;
+ RECT 1587.720000 866.400000 1588.820000 866.880000 ;
+ RECT 1632.720000 844.640000 1633.820000 845.120000 ;
+ RECT 1632.720000 839.200000 1633.820000 839.680000 ;
+ RECT 1642.030000 844.640000 1643.030000 845.120000 ;
+ RECT 1642.030000 839.200000 1643.030000 839.680000 ;
+ RECT 1632.720000 828.320000 1633.820000 828.800000 ;
+ RECT 1632.720000 822.880000 1633.820000 823.360000 ;
+ RECT 1642.030000 828.320000 1643.030000 828.800000 ;
+ RECT 1642.030000 822.880000 1643.030000 823.360000 ;
+ RECT 1632.720000 833.760000 1633.820000 834.240000 ;
+ RECT 1642.030000 833.760000 1643.030000 834.240000 ;
+ RECT 1642.030000 812.000000 1643.030000 812.480000 ;
+ RECT 1642.030000 817.440000 1643.030000 817.920000 ;
+ RECT 1632.720000 812.000000 1633.820000 812.480000 ;
+ RECT 1632.720000 817.440000 1633.820000 817.920000 ;
+ RECT 1632.720000 801.120000 1633.820000 801.600000 ;
+ RECT 1632.720000 806.560000 1633.820000 807.040000 ;
+ RECT 1642.030000 806.560000 1643.030000 807.040000 ;
+ RECT 1642.030000 801.120000 1643.030000 801.600000 ;
+ RECT 1587.720000 844.640000 1588.820000 845.120000 ;
+ RECT 1587.720000 839.200000 1588.820000 839.680000 ;
+ RECT 1587.720000 833.760000 1588.820000 834.240000 ;
+ RECT 1587.720000 828.320000 1588.820000 828.800000 ;
+ RECT 1587.720000 822.880000 1588.820000 823.360000 ;
+ RECT 1587.720000 801.120000 1588.820000 801.600000 ;
+ RECT 1587.720000 806.560000 1588.820000 807.040000 ;
+ RECT 1587.720000 812.000000 1588.820000 812.480000 ;
+ RECT 1587.720000 817.440000 1588.820000 817.920000 ;
+ RECT 1642.030000 784.800000 1643.030000 785.280000 ;
+ RECT 1642.030000 790.240000 1643.030000 790.720000 ;
+ RECT 1642.030000 795.680000 1643.030000 796.160000 ;
+ RECT 1632.720000 795.680000 1633.820000 796.160000 ;
+ RECT 1632.720000 790.240000 1633.820000 790.720000 ;
+ RECT 1632.720000 784.800000 1633.820000 785.280000 ;
+ RECT 1632.720000 779.360000 1633.820000 779.840000 ;
+ RECT 1632.720000 773.920000 1633.820000 774.400000 ;
+ RECT 1642.030000 779.360000 1643.030000 779.840000 ;
+ RECT 1642.030000 773.920000 1643.030000 774.400000 ;
+ RECT 1632.720000 763.040000 1633.820000 763.520000 ;
+ RECT 1632.720000 768.480000 1633.820000 768.960000 ;
+ RECT 1642.030000 768.480000 1643.030000 768.960000 ;
+ RECT 1642.030000 763.040000 1643.030000 763.520000 ;
+ RECT 1642.030000 746.720000 1643.030000 747.200000 ;
+ RECT 1642.030000 752.160000 1643.030000 752.640000 ;
+ RECT 1642.030000 757.600000 1643.030000 758.080000 ;
+ RECT 1632.720000 757.600000 1633.820000 758.080000 ;
+ RECT 1632.720000 752.160000 1633.820000 752.640000 ;
+ RECT 1632.720000 746.720000 1633.820000 747.200000 ;
+ RECT 1587.720000 795.680000 1588.820000 796.160000 ;
+ RECT 1587.720000 790.240000 1588.820000 790.720000 ;
+ RECT 1587.720000 784.800000 1588.820000 785.280000 ;
+ RECT 1587.720000 779.360000 1588.820000 779.840000 ;
+ RECT 1587.720000 773.920000 1588.820000 774.400000 ;
+ RECT 1587.720000 763.040000 1588.820000 763.520000 ;
+ RECT 1587.720000 757.600000 1588.820000 758.080000 ;
+ RECT 1587.720000 752.160000 1588.820000 752.640000 ;
+ RECT 1587.720000 746.720000 1588.820000 747.200000 ;
+ RECT 1587.720000 768.480000 1588.820000 768.960000 ;
+ RECT 1542.720000 937.120000 1543.820000 937.600000 ;
+ RECT 1542.720000 931.680000 1543.820000 932.160000 ;
+ RECT 1542.720000 926.240000 1543.820000 926.720000 ;
+ RECT 1497.720000 937.120000 1498.820000 937.600000 ;
+ RECT 1497.720000 931.680000 1498.820000 932.160000 ;
+ RECT 1497.720000 926.240000 1498.820000 926.720000 ;
+ RECT 1542.720000 909.920000 1543.820000 910.400000 ;
+ RECT 1542.720000 904.480000 1543.820000 904.960000 ;
+ RECT 1542.720000 899.040000 1543.820000 899.520000 ;
+ RECT 1542.720000 915.360000 1543.820000 915.840000 ;
+ RECT 1542.720000 920.800000 1543.820000 921.280000 ;
+ RECT 1497.720000 920.800000 1498.820000 921.280000 ;
+ RECT 1497.720000 909.920000 1498.820000 910.400000 ;
+ RECT 1497.720000 904.480000 1498.820000 904.960000 ;
+ RECT 1497.720000 899.040000 1498.820000 899.520000 ;
+ RECT 1497.720000 915.360000 1498.820000 915.840000 ;
+ RECT 1452.720000 937.120000 1453.820000 937.600000 ;
+ RECT 1448.590000 937.120000 1449.590000 937.600000 ;
+ RECT 1448.590000 931.680000 1449.590000 932.160000 ;
+ RECT 1452.720000 931.680000 1453.820000 932.160000 ;
+ RECT 1452.720000 926.240000 1453.820000 926.720000 ;
+ RECT 1448.590000 926.240000 1449.590000 926.720000 ;
+ RECT 1452.720000 920.800000 1453.820000 921.280000 ;
+ RECT 1452.720000 915.360000 1453.820000 915.840000 ;
+ RECT 1448.590000 920.800000 1449.590000 921.280000 ;
+ RECT 1448.590000 915.360000 1449.590000 915.840000 ;
+ RECT 1452.720000 909.920000 1453.820000 910.400000 ;
+ RECT 1448.590000 909.920000 1449.590000 910.400000 ;
+ RECT 1452.720000 904.480000 1453.820000 904.960000 ;
+ RECT 1448.590000 904.480000 1449.590000 904.960000 ;
+ RECT 1452.720000 899.040000 1453.820000 899.520000 ;
+ RECT 1448.590000 899.040000 1449.590000 899.520000 ;
+ RECT 1542.720000 893.600000 1543.820000 894.080000 ;
+ RECT 1542.720000 888.160000 1543.820000 888.640000 ;
+ RECT 1542.720000 882.720000 1543.820000 883.200000 ;
+ RECT 1542.720000 877.280000 1543.820000 877.760000 ;
+ RECT 1542.720000 871.840000 1543.820000 872.320000 ;
+ RECT 1497.720000 893.600000 1498.820000 894.080000 ;
+ RECT 1497.720000 888.160000 1498.820000 888.640000 ;
+ RECT 1497.720000 882.720000 1498.820000 883.200000 ;
+ RECT 1497.720000 877.280000 1498.820000 877.760000 ;
+ RECT 1497.720000 871.840000 1498.820000 872.320000 ;
+ RECT 1542.720000 866.400000 1543.820000 866.880000 ;
+ RECT 1542.720000 860.960000 1543.820000 861.440000 ;
+ RECT 1542.720000 855.520000 1543.820000 856.000000 ;
+ RECT 1542.720000 850.080000 1543.820000 850.560000 ;
+ RECT 1497.720000 860.960000 1498.820000 861.440000 ;
+ RECT 1497.720000 855.520000 1498.820000 856.000000 ;
+ RECT 1497.720000 850.080000 1498.820000 850.560000 ;
+ RECT 1497.720000 866.400000 1498.820000 866.880000 ;
+ RECT 1452.720000 893.600000 1453.820000 894.080000 ;
+ RECT 1448.590000 893.600000 1449.590000 894.080000 ;
+ RECT 1452.720000 888.160000 1453.820000 888.640000 ;
+ RECT 1448.590000 888.160000 1449.590000 888.640000 ;
+ RECT 1452.720000 882.720000 1453.820000 883.200000 ;
+ RECT 1448.590000 882.720000 1449.590000 883.200000 ;
+ RECT 1452.720000 871.840000 1453.820000 872.320000 ;
+ RECT 1448.590000 871.840000 1449.590000 872.320000 ;
+ RECT 1448.590000 877.280000 1449.590000 877.760000 ;
+ RECT 1452.720000 877.280000 1453.820000 877.760000 ;
+ RECT 1452.720000 866.400000 1453.820000 866.880000 ;
+ RECT 1448.590000 866.400000 1449.590000 866.880000 ;
+ RECT 1452.720000 860.960000 1453.820000 861.440000 ;
+ RECT 1448.590000 860.960000 1449.590000 861.440000 ;
+ RECT 1452.720000 855.520000 1453.820000 856.000000 ;
+ RECT 1448.590000 855.520000 1449.590000 856.000000 ;
+ RECT 1452.720000 850.080000 1453.820000 850.560000 ;
+ RECT 1448.590000 850.080000 1449.590000 850.560000 ;
+ RECT 1542.720000 844.640000 1543.820000 845.120000 ;
+ RECT 1542.720000 839.200000 1543.820000 839.680000 ;
+ RECT 1542.720000 833.760000 1543.820000 834.240000 ;
+ RECT 1542.720000 828.320000 1543.820000 828.800000 ;
+ RECT 1542.720000 822.880000 1543.820000 823.360000 ;
+ RECT 1497.720000 844.640000 1498.820000 845.120000 ;
+ RECT 1497.720000 839.200000 1498.820000 839.680000 ;
+ RECT 1497.720000 833.760000 1498.820000 834.240000 ;
+ RECT 1497.720000 828.320000 1498.820000 828.800000 ;
+ RECT 1497.720000 822.880000 1498.820000 823.360000 ;
+ RECT 1542.720000 817.440000 1543.820000 817.920000 ;
+ RECT 1542.720000 812.000000 1543.820000 812.480000 ;
+ RECT 1542.720000 806.560000 1543.820000 807.040000 ;
+ RECT 1542.720000 801.120000 1543.820000 801.600000 ;
+ RECT 1497.720000 812.000000 1498.820000 812.480000 ;
+ RECT 1497.720000 806.560000 1498.820000 807.040000 ;
+ RECT 1497.720000 801.120000 1498.820000 801.600000 ;
+ RECT 1497.720000 817.440000 1498.820000 817.920000 ;
+ RECT 1452.720000 844.640000 1453.820000 845.120000 ;
+ RECT 1448.590000 844.640000 1449.590000 845.120000 ;
+ RECT 1452.720000 839.200000 1453.820000 839.680000 ;
+ RECT 1448.590000 839.200000 1449.590000 839.680000 ;
+ RECT 1452.720000 828.320000 1453.820000 828.800000 ;
+ RECT 1448.590000 828.320000 1449.590000 828.800000 ;
+ RECT 1452.720000 822.880000 1453.820000 823.360000 ;
+ RECT 1448.590000 822.880000 1449.590000 823.360000 ;
+ RECT 1452.720000 833.760000 1453.820000 834.240000 ;
+ RECT 1448.590000 833.760000 1449.590000 834.240000 ;
+ RECT 1452.720000 817.440000 1453.820000 817.920000 ;
+ RECT 1448.590000 817.440000 1449.590000 817.920000 ;
+ RECT 1452.720000 812.000000 1453.820000 812.480000 ;
+ RECT 1448.590000 812.000000 1449.590000 812.480000 ;
+ RECT 1452.720000 806.560000 1453.820000 807.040000 ;
+ RECT 1448.590000 806.560000 1449.590000 807.040000 ;
+ RECT 1452.720000 801.120000 1453.820000 801.600000 ;
+ RECT 1448.590000 801.120000 1449.590000 801.600000 ;
+ RECT 1542.720000 795.680000 1543.820000 796.160000 ;
+ RECT 1542.720000 790.240000 1543.820000 790.720000 ;
+ RECT 1542.720000 784.800000 1543.820000 785.280000 ;
+ RECT 1542.720000 779.360000 1543.820000 779.840000 ;
+ RECT 1542.720000 773.920000 1543.820000 774.400000 ;
+ RECT 1497.720000 795.680000 1498.820000 796.160000 ;
+ RECT 1497.720000 790.240000 1498.820000 790.720000 ;
+ RECT 1497.720000 784.800000 1498.820000 785.280000 ;
+ RECT 1497.720000 779.360000 1498.820000 779.840000 ;
+ RECT 1497.720000 773.920000 1498.820000 774.400000 ;
+ RECT 1542.720000 763.040000 1543.820000 763.520000 ;
+ RECT 1542.720000 746.720000 1543.820000 747.200000 ;
+ RECT 1542.720000 752.160000 1543.820000 752.640000 ;
+ RECT 1542.720000 757.600000 1543.820000 758.080000 ;
+ RECT 1542.720000 768.480000 1543.820000 768.960000 ;
+ RECT 1497.720000 746.720000 1498.820000 747.200000 ;
+ RECT 1497.720000 752.160000 1498.820000 752.640000 ;
+ RECT 1497.720000 757.600000 1498.820000 758.080000 ;
+ RECT 1497.720000 763.040000 1498.820000 763.520000 ;
+ RECT 1497.720000 768.480000 1498.820000 768.960000 ;
+ RECT 1452.720000 795.680000 1453.820000 796.160000 ;
+ RECT 1452.720000 790.240000 1453.820000 790.720000 ;
+ RECT 1448.590000 795.680000 1449.590000 796.160000 ;
+ RECT 1448.590000 790.240000 1449.590000 790.720000 ;
+ RECT 1452.720000 784.800000 1453.820000 785.280000 ;
+ RECT 1448.590000 784.800000 1449.590000 785.280000 ;
+ RECT 1452.720000 779.360000 1453.820000 779.840000 ;
+ RECT 1448.590000 779.360000 1449.590000 779.840000 ;
+ RECT 1452.720000 773.920000 1453.820000 774.400000 ;
+ RECT 1448.590000 773.920000 1449.590000 774.400000 ;
+ RECT 1452.720000 768.480000 1453.820000 768.960000 ;
+ RECT 1448.590000 768.480000 1449.590000 768.960000 ;
+ RECT 1452.720000 763.040000 1453.820000 763.520000 ;
+ RECT 1448.590000 763.040000 1449.590000 763.520000 ;
+ RECT 1452.720000 757.600000 1453.820000 758.080000 ;
+ RECT 1448.590000 757.600000 1449.590000 758.080000 ;
+ RECT 1452.720000 746.720000 1453.820000 747.200000 ;
+ RECT 1448.590000 746.720000 1449.590000 747.200000 ;
+ RECT 1448.590000 752.160000 1449.590000 752.640000 ;
+ RECT 1452.720000 752.160000 1453.820000 752.640000 ;
+ RECT 1632.720000 741.280000 1633.820000 741.760000 ;
+ RECT 1632.720000 735.840000 1633.820000 736.320000 ;
+ RECT 1642.030000 741.280000 1643.030000 741.760000 ;
+ RECT 1642.030000 735.840000 1643.030000 736.320000 ;
+ RECT 1642.030000 724.960000 1643.030000 725.440000 ;
+ RECT 1642.030000 730.400000 1643.030000 730.880000 ;
+ RECT 1632.720000 730.400000 1633.820000 730.880000 ;
+ RECT 1632.720000 724.960000 1633.820000 725.440000 ;
+ RECT 1632.720000 714.080000 1633.820000 714.560000 ;
+ RECT 1632.720000 719.520000 1633.820000 720.000000 ;
+ RECT 1642.030000 719.520000 1643.030000 720.000000 ;
+ RECT 1642.030000 714.080000 1643.030000 714.560000 ;
+ RECT 1632.720000 697.760000 1633.820000 698.240000 ;
+ RECT 1632.720000 703.200000 1633.820000 703.680000 ;
+ RECT 1642.030000 703.200000 1643.030000 703.680000 ;
+ RECT 1642.030000 697.760000 1643.030000 698.240000 ;
+ RECT 1632.720000 708.640000 1633.820000 709.120000 ;
+ RECT 1642.030000 708.640000 1643.030000 709.120000 ;
+ RECT 1587.720000 741.280000 1588.820000 741.760000 ;
+ RECT 1587.720000 735.840000 1588.820000 736.320000 ;
+ RECT 1587.720000 730.400000 1588.820000 730.880000 ;
+ RECT 1587.720000 724.960000 1588.820000 725.440000 ;
+ RECT 1587.720000 697.760000 1588.820000 698.240000 ;
+ RECT 1587.720000 703.200000 1588.820000 703.680000 ;
+ RECT 1587.720000 708.640000 1588.820000 709.120000 ;
+ RECT 1587.720000 714.080000 1588.820000 714.560000 ;
+ RECT 1587.720000 719.520000 1588.820000 720.000000 ;
+ RECT 1642.030000 686.880000 1643.030000 687.360000 ;
+ RECT 1642.030000 692.320000 1643.030000 692.800000 ;
+ RECT 1632.720000 692.320000 1633.820000 692.800000 ;
+ RECT 1632.720000 686.880000 1633.820000 687.360000 ;
+ RECT 1632.720000 681.440000 1633.820000 681.920000 ;
+ RECT 1632.720000 676.000000 1633.820000 676.480000 ;
+ RECT 1642.030000 681.440000 1643.030000 681.920000 ;
+ RECT 1642.030000 676.000000 1643.030000 676.480000 ;
+ RECT 1642.030000 659.680000 1643.030000 660.160000 ;
+ RECT 1642.030000 665.120000 1643.030000 665.600000 ;
+ RECT 1642.030000 670.560000 1643.030000 671.040000 ;
+ RECT 1632.720000 659.680000 1633.820000 660.160000 ;
+ RECT 1632.720000 665.120000 1633.820000 665.600000 ;
+ RECT 1632.720000 670.560000 1633.820000 671.040000 ;
+ RECT 1632.720000 648.800000 1633.820000 649.280000 ;
+ RECT 1632.720000 654.240000 1633.820000 654.720000 ;
+ RECT 1642.030000 654.240000 1643.030000 654.720000 ;
+ RECT 1642.030000 648.800000 1643.030000 649.280000 ;
+ RECT 1587.720000 692.320000 1588.820000 692.800000 ;
+ RECT 1587.720000 686.880000 1588.820000 687.360000 ;
+ RECT 1587.720000 681.440000 1588.820000 681.920000 ;
+ RECT 1587.720000 676.000000 1588.820000 676.480000 ;
+ RECT 1587.720000 648.800000 1588.820000 649.280000 ;
+ RECT 1587.720000 654.240000 1588.820000 654.720000 ;
+ RECT 1587.720000 659.680000 1588.820000 660.160000 ;
+ RECT 1587.720000 665.120000 1588.820000 665.600000 ;
+ RECT 1587.720000 670.560000 1588.820000 671.040000 ;
+ RECT 1632.720000 643.360000 1633.820000 643.840000 ;
+ RECT 1632.720000 637.920000 1633.820000 638.400000 ;
+ RECT 1642.030000 643.360000 1643.030000 643.840000 ;
+ RECT 1642.030000 637.920000 1643.030000 638.400000 ;
+ RECT 1642.030000 621.600000 1643.030000 622.080000 ;
+ RECT 1642.030000 627.040000 1643.030000 627.520000 ;
+ RECT 1642.030000 632.480000 1643.030000 632.960000 ;
+ RECT 1632.720000 632.480000 1633.820000 632.960000 ;
+ RECT 1632.720000 627.040000 1633.820000 627.520000 ;
+ RECT 1632.720000 621.600000 1633.820000 622.080000 ;
+ RECT 1632.720000 610.720000 1633.820000 611.200000 ;
+ RECT 1632.720000 616.160000 1633.820000 616.640000 ;
+ RECT 1642.030000 616.160000 1643.030000 616.640000 ;
+ RECT 1642.030000 610.720000 1643.030000 611.200000 ;
+ RECT 1642.030000 599.840000 1643.030000 600.320000 ;
+ RECT 1642.030000 605.280000 1643.030000 605.760000 ;
+ RECT 1632.720000 599.840000 1633.820000 600.320000 ;
+ RECT 1632.720000 605.280000 1633.820000 605.760000 ;
+ RECT 1587.720000 643.360000 1588.820000 643.840000 ;
+ RECT 1587.720000 637.920000 1588.820000 638.400000 ;
+ RECT 1587.720000 632.480000 1588.820000 632.960000 ;
+ RECT 1587.720000 627.040000 1588.820000 627.520000 ;
+ RECT 1587.720000 621.600000 1588.820000 622.080000 ;
+ RECT 1587.720000 599.840000 1588.820000 600.320000 ;
+ RECT 1587.720000 605.280000 1588.820000 605.760000 ;
+ RECT 1587.720000 610.720000 1588.820000 611.200000 ;
+ RECT 1587.720000 616.160000 1588.820000 616.640000 ;
+ RECT 1632.720000 594.400000 1633.820000 594.880000 ;
+ RECT 1632.720000 588.960000 1633.820000 589.440000 ;
+ RECT 1642.030000 594.400000 1643.030000 594.880000 ;
+ RECT 1642.030000 588.960000 1643.030000 589.440000 ;
+ RECT 1632.720000 578.080000 1633.820000 578.560000 ;
+ RECT 1632.720000 572.640000 1633.820000 573.120000 ;
+ RECT 1642.030000 578.080000 1643.030000 578.560000 ;
+ RECT 1642.030000 572.640000 1643.030000 573.120000 ;
+ RECT 1632.720000 583.520000 1633.820000 584.000000 ;
+ RECT 1642.030000 583.520000 1643.030000 584.000000 ;
+ RECT 1642.030000 561.760000 1643.030000 562.240000 ;
+ RECT 1642.030000 567.200000 1643.030000 567.680000 ;
+ RECT 1632.720000 567.200000 1633.820000 567.680000 ;
+ RECT 1632.720000 561.760000 1633.820000 562.240000 ;
+ RECT 1632.720000 556.320000 1633.820000 556.800000 ;
+ RECT 1632.720000 550.880000 1633.820000 551.360000 ;
+ RECT 1642.030000 556.320000 1643.030000 556.800000 ;
+ RECT 1642.030000 550.880000 1643.030000 551.360000 ;
+ RECT 1587.720000 594.400000 1588.820000 594.880000 ;
+ RECT 1587.720000 588.960000 1588.820000 589.440000 ;
+ RECT 1587.720000 583.520000 1588.820000 584.000000 ;
+ RECT 1587.720000 578.080000 1588.820000 578.560000 ;
+ RECT 1587.720000 572.640000 1588.820000 573.120000 ;
+ RECT 1587.720000 567.200000 1588.820000 567.680000 ;
+ RECT 1587.720000 561.760000 1588.820000 562.240000 ;
+ RECT 1587.720000 556.320000 1588.820000 556.800000 ;
+ RECT 1587.720000 550.880000 1588.820000 551.360000 ;
+ RECT 1542.720000 741.280000 1543.820000 741.760000 ;
+ RECT 1542.720000 735.840000 1543.820000 736.320000 ;
+ RECT 1542.720000 730.400000 1543.820000 730.880000 ;
+ RECT 1542.720000 724.960000 1543.820000 725.440000 ;
+ RECT 1497.720000 741.280000 1498.820000 741.760000 ;
+ RECT 1497.720000 735.840000 1498.820000 736.320000 ;
+ RECT 1497.720000 730.400000 1498.820000 730.880000 ;
+ RECT 1497.720000 724.960000 1498.820000 725.440000 ;
+ RECT 1542.720000 714.080000 1543.820000 714.560000 ;
+ RECT 1542.720000 708.640000 1543.820000 709.120000 ;
+ RECT 1542.720000 703.200000 1543.820000 703.680000 ;
+ RECT 1542.720000 697.760000 1543.820000 698.240000 ;
+ RECT 1542.720000 719.520000 1543.820000 720.000000 ;
+ RECT 1497.720000 708.640000 1498.820000 709.120000 ;
+ RECT 1497.720000 703.200000 1498.820000 703.680000 ;
+ RECT 1497.720000 697.760000 1498.820000 698.240000 ;
+ RECT 1497.720000 714.080000 1498.820000 714.560000 ;
+ RECT 1497.720000 719.520000 1498.820000 720.000000 ;
+ RECT 1452.720000 741.280000 1453.820000 741.760000 ;
+ RECT 1448.590000 741.280000 1449.590000 741.760000 ;
+ RECT 1452.720000 735.840000 1453.820000 736.320000 ;
+ RECT 1448.590000 735.840000 1449.590000 736.320000 ;
+ RECT 1452.720000 730.400000 1453.820000 730.880000 ;
+ RECT 1448.590000 730.400000 1449.590000 730.880000 ;
+ RECT 1452.720000 724.960000 1453.820000 725.440000 ;
+ RECT 1448.590000 724.960000 1449.590000 725.440000 ;
+ RECT 1452.720000 719.520000 1453.820000 720.000000 ;
+ RECT 1448.590000 719.520000 1449.590000 720.000000 ;
+ RECT 1452.720000 714.080000 1453.820000 714.560000 ;
+ RECT 1448.590000 714.080000 1449.590000 714.560000 ;
+ RECT 1452.720000 703.200000 1453.820000 703.680000 ;
+ RECT 1448.590000 703.200000 1449.590000 703.680000 ;
+ RECT 1452.720000 697.760000 1453.820000 698.240000 ;
+ RECT 1448.590000 697.760000 1449.590000 698.240000 ;
+ RECT 1452.720000 708.640000 1453.820000 709.120000 ;
+ RECT 1448.590000 708.640000 1449.590000 709.120000 ;
+ RECT 1542.720000 692.320000 1543.820000 692.800000 ;
+ RECT 1542.720000 686.880000 1543.820000 687.360000 ;
+ RECT 1542.720000 681.440000 1543.820000 681.920000 ;
+ RECT 1542.720000 676.000000 1543.820000 676.480000 ;
+ RECT 1497.720000 692.320000 1498.820000 692.800000 ;
+ RECT 1497.720000 686.880000 1498.820000 687.360000 ;
+ RECT 1497.720000 681.440000 1498.820000 681.920000 ;
+ RECT 1497.720000 676.000000 1498.820000 676.480000 ;
+ RECT 1542.720000 665.120000 1543.820000 665.600000 ;
+ RECT 1542.720000 659.680000 1543.820000 660.160000 ;
+ RECT 1542.720000 654.240000 1543.820000 654.720000 ;
+ RECT 1542.720000 648.800000 1543.820000 649.280000 ;
+ RECT 1542.720000 670.560000 1543.820000 671.040000 ;
+ RECT 1497.720000 659.680000 1498.820000 660.160000 ;
+ RECT 1497.720000 654.240000 1498.820000 654.720000 ;
+ RECT 1497.720000 648.800000 1498.820000 649.280000 ;
+ RECT 1497.720000 665.120000 1498.820000 665.600000 ;
+ RECT 1497.720000 670.560000 1498.820000 671.040000 ;
+ RECT 1452.720000 692.320000 1453.820000 692.800000 ;
+ RECT 1448.590000 692.320000 1449.590000 692.800000 ;
+ RECT 1452.720000 686.880000 1453.820000 687.360000 ;
+ RECT 1448.590000 686.880000 1449.590000 687.360000 ;
+ RECT 1452.720000 681.440000 1453.820000 681.920000 ;
+ RECT 1448.590000 681.440000 1449.590000 681.920000 ;
+ RECT 1452.720000 676.000000 1453.820000 676.480000 ;
+ RECT 1448.590000 676.000000 1449.590000 676.480000 ;
+ RECT 1452.720000 670.560000 1453.820000 671.040000 ;
+ RECT 1452.720000 665.120000 1453.820000 665.600000 ;
+ RECT 1448.590000 670.560000 1449.590000 671.040000 ;
+ RECT 1448.590000 665.120000 1449.590000 665.600000 ;
+ RECT 1452.720000 659.680000 1453.820000 660.160000 ;
+ RECT 1448.590000 659.680000 1449.590000 660.160000 ;
+ RECT 1452.720000 654.240000 1453.820000 654.720000 ;
+ RECT 1448.590000 654.240000 1449.590000 654.720000 ;
+ RECT 1452.720000 648.800000 1453.820000 649.280000 ;
+ RECT 1448.590000 648.800000 1449.590000 649.280000 ;
+ RECT 1542.720000 643.360000 1543.820000 643.840000 ;
+ RECT 1542.720000 637.920000 1543.820000 638.400000 ;
+ RECT 1542.720000 632.480000 1543.820000 632.960000 ;
+ RECT 1542.720000 627.040000 1543.820000 627.520000 ;
+ RECT 1542.720000 621.600000 1543.820000 622.080000 ;
+ RECT 1497.720000 643.360000 1498.820000 643.840000 ;
+ RECT 1497.720000 637.920000 1498.820000 638.400000 ;
+ RECT 1497.720000 632.480000 1498.820000 632.960000 ;
+ RECT 1497.720000 627.040000 1498.820000 627.520000 ;
+ RECT 1497.720000 621.600000 1498.820000 622.080000 ;
+ RECT 1542.720000 616.160000 1543.820000 616.640000 ;
+ RECT 1542.720000 610.720000 1543.820000 611.200000 ;
+ RECT 1542.720000 605.280000 1543.820000 605.760000 ;
+ RECT 1542.720000 599.840000 1543.820000 600.320000 ;
+ RECT 1497.720000 610.720000 1498.820000 611.200000 ;
+ RECT 1497.720000 605.280000 1498.820000 605.760000 ;
+ RECT 1497.720000 599.840000 1498.820000 600.320000 ;
+ RECT 1497.720000 616.160000 1498.820000 616.640000 ;
+ RECT 1452.720000 643.360000 1453.820000 643.840000 ;
+ RECT 1448.590000 643.360000 1449.590000 643.840000 ;
+ RECT 1452.720000 637.920000 1453.820000 638.400000 ;
+ RECT 1448.590000 637.920000 1449.590000 638.400000 ;
+ RECT 1452.720000 632.480000 1453.820000 632.960000 ;
+ RECT 1448.590000 632.480000 1449.590000 632.960000 ;
+ RECT 1452.720000 621.600000 1453.820000 622.080000 ;
+ RECT 1448.590000 621.600000 1449.590000 622.080000 ;
+ RECT 1448.590000 627.040000 1449.590000 627.520000 ;
+ RECT 1452.720000 627.040000 1453.820000 627.520000 ;
+ RECT 1452.720000 616.160000 1453.820000 616.640000 ;
+ RECT 1448.590000 616.160000 1449.590000 616.640000 ;
+ RECT 1452.720000 610.720000 1453.820000 611.200000 ;
+ RECT 1448.590000 610.720000 1449.590000 611.200000 ;
+ RECT 1452.720000 605.280000 1453.820000 605.760000 ;
+ RECT 1448.590000 605.280000 1449.590000 605.760000 ;
+ RECT 1452.720000 599.840000 1453.820000 600.320000 ;
+ RECT 1448.590000 599.840000 1449.590000 600.320000 ;
+ RECT 1542.720000 594.400000 1543.820000 594.880000 ;
+ RECT 1542.720000 588.960000 1543.820000 589.440000 ;
+ RECT 1542.720000 583.520000 1543.820000 584.000000 ;
+ RECT 1542.720000 578.080000 1543.820000 578.560000 ;
+ RECT 1542.720000 572.640000 1543.820000 573.120000 ;
+ RECT 1497.720000 594.400000 1498.820000 594.880000 ;
+ RECT 1497.720000 588.960000 1498.820000 589.440000 ;
+ RECT 1497.720000 583.520000 1498.820000 584.000000 ;
+ RECT 1497.720000 578.080000 1498.820000 578.560000 ;
+ RECT 1497.720000 572.640000 1498.820000 573.120000 ;
+ RECT 1542.720000 550.880000 1543.820000 551.360000 ;
+ RECT 1542.720000 556.320000 1543.820000 556.800000 ;
+ RECT 1542.720000 561.760000 1543.820000 562.240000 ;
+ RECT 1542.720000 567.200000 1543.820000 567.680000 ;
+ RECT 1497.720000 550.880000 1498.820000 551.360000 ;
+ RECT 1497.720000 556.320000 1498.820000 556.800000 ;
+ RECT 1497.720000 561.760000 1498.820000 562.240000 ;
+ RECT 1497.720000 567.200000 1498.820000 567.680000 ;
+ RECT 1452.720000 594.400000 1453.820000 594.880000 ;
+ RECT 1448.590000 594.400000 1449.590000 594.880000 ;
+ RECT 1452.720000 588.960000 1453.820000 589.440000 ;
+ RECT 1448.590000 588.960000 1449.590000 589.440000 ;
+ RECT 1452.720000 578.080000 1453.820000 578.560000 ;
+ RECT 1448.590000 578.080000 1449.590000 578.560000 ;
+ RECT 1452.720000 572.640000 1453.820000 573.120000 ;
+ RECT 1448.590000 572.640000 1449.590000 573.120000 ;
+ RECT 1452.720000 583.520000 1453.820000 584.000000 ;
+ RECT 1448.590000 583.520000 1449.590000 584.000000 ;
+ RECT 1452.720000 567.200000 1453.820000 567.680000 ;
+ RECT 1448.590000 567.200000 1449.590000 567.680000 ;
+ RECT 1452.720000 561.760000 1453.820000 562.240000 ;
+ RECT 1448.590000 561.760000 1449.590000 562.240000 ;
+ RECT 1452.720000 556.320000 1453.820000 556.800000 ;
+ RECT 1452.720000 550.880000 1453.820000 551.360000 ;
+ RECT 1448.590000 556.320000 1449.590000 556.800000 ;
+ RECT 1448.590000 550.880000 1449.590000 551.360000 ;
+ RECT 1445.760000 942.010000 1645.860000 943.010000 ;
+ RECT 1445.760000 548.870000 1645.860000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 546.020000 1449.590000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 945.540000 1449.590000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 546.020000 1643.030000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 945.540000 1643.030000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 548.870000 1446.760000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 548.870000 1645.860000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 942.010000 1446.760000 943.010000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 942.010000 1645.860000 943.010000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 145.500000 1449.590000 546.020000 ;
+ RECT 1642.030000 145.500000 1643.030000 546.020000 ;
+ RECT 1452.720000 148.350000 1453.820000 542.490000 ;
+ RECT 1497.720000 148.350000 1498.820000 542.490000 ;
+ RECT 1542.720000 148.350000 1543.820000 542.490000 ;
+ RECT 1587.720000 148.350000 1588.820000 542.490000 ;
+ RECT 1632.720000 148.350000 1633.820000 542.490000 ;
+ LAYER met3 ;
+ RECT 1632.720000 536.600000 1633.820000 537.080000 ;
+ RECT 1642.030000 536.600000 1643.030000 537.080000 ;
+ RECT 1642.030000 531.160000 1643.030000 531.640000 ;
+ RECT 1632.720000 531.160000 1633.820000 531.640000 ;
+ RECT 1632.720000 525.720000 1633.820000 526.200000 ;
+ RECT 1642.030000 525.720000 1643.030000 526.200000 ;
+ RECT 1642.030000 509.400000 1643.030000 509.880000 ;
+ RECT 1642.030000 514.840000 1643.030000 515.320000 ;
+ RECT 1642.030000 520.280000 1643.030000 520.760000 ;
+ RECT 1632.720000 520.280000 1633.820000 520.760000 ;
+ RECT 1632.720000 509.400000 1633.820000 509.880000 ;
+ RECT 1632.720000 514.840000 1633.820000 515.320000 ;
+ RECT 1632.720000 498.520000 1633.820000 499.000000 ;
+ RECT 1632.720000 503.960000 1633.820000 504.440000 ;
+ RECT 1642.030000 503.960000 1643.030000 504.440000 ;
+ RECT 1642.030000 498.520000 1643.030000 499.000000 ;
+ RECT 1587.720000 536.600000 1588.820000 537.080000 ;
+ RECT 1587.720000 531.160000 1588.820000 531.640000 ;
+ RECT 1587.720000 525.720000 1588.820000 526.200000 ;
+ RECT 1587.720000 520.280000 1588.820000 520.760000 ;
+ RECT 1587.720000 498.520000 1588.820000 499.000000 ;
+ RECT 1587.720000 503.960000 1588.820000 504.440000 ;
+ RECT 1587.720000 509.400000 1588.820000 509.880000 ;
+ RECT 1587.720000 514.840000 1588.820000 515.320000 ;
+ RECT 1632.720000 493.080000 1633.820000 493.560000 ;
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+ RECT 1542.720000 324.440000 1543.820000 324.920000 ;
+ RECT 1497.720000 340.760000 1498.820000 341.240000 ;
+ RECT 1497.720000 335.320000 1498.820000 335.800000 ;
+ RECT 1497.720000 329.880000 1498.820000 330.360000 ;
+ RECT 1497.720000 324.440000 1498.820000 324.920000 ;
+ RECT 1542.720000 313.560000 1543.820000 314.040000 ;
+ RECT 1542.720000 308.120000 1543.820000 308.600000 ;
+ RECT 1542.720000 302.680000 1543.820000 303.160000 ;
+ RECT 1542.720000 297.240000 1543.820000 297.720000 ;
+ RECT 1542.720000 319.000000 1543.820000 319.480000 ;
+ RECT 1497.720000 308.120000 1498.820000 308.600000 ;
+ RECT 1497.720000 302.680000 1498.820000 303.160000 ;
+ RECT 1497.720000 297.240000 1498.820000 297.720000 ;
+ RECT 1497.720000 313.560000 1498.820000 314.040000 ;
+ RECT 1497.720000 319.000000 1498.820000 319.480000 ;
+ RECT 1452.720000 340.760000 1453.820000 341.240000 ;
+ RECT 1448.590000 340.760000 1449.590000 341.240000 ;
+ RECT 1452.720000 335.320000 1453.820000 335.800000 ;
+ RECT 1448.590000 335.320000 1449.590000 335.800000 ;
+ RECT 1452.720000 329.880000 1453.820000 330.360000 ;
+ RECT 1448.590000 329.880000 1449.590000 330.360000 ;
+ RECT 1452.720000 324.440000 1453.820000 324.920000 ;
+ RECT 1448.590000 324.440000 1449.590000 324.920000 ;
+ RECT 1452.720000 319.000000 1453.820000 319.480000 ;
+ RECT 1448.590000 319.000000 1449.590000 319.480000 ;
+ RECT 1452.720000 313.560000 1453.820000 314.040000 ;
+ RECT 1448.590000 313.560000 1449.590000 314.040000 ;
+ RECT 1452.720000 302.680000 1453.820000 303.160000 ;
+ RECT 1448.590000 302.680000 1449.590000 303.160000 ;
+ RECT 1452.720000 297.240000 1453.820000 297.720000 ;
+ RECT 1448.590000 297.240000 1449.590000 297.720000 ;
+ RECT 1452.720000 308.120000 1453.820000 308.600000 ;
+ RECT 1448.590000 308.120000 1449.590000 308.600000 ;
+ RECT 1542.720000 291.800000 1543.820000 292.280000 ;
+ RECT 1542.720000 286.360000 1543.820000 286.840000 ;
+ RECT 1542.720000 280.920000 1543.820000 281.400000 ;
+ RECT 1542.720000 275.480000 1543.820000 275.960000 ;
+ RECT 1497.720000 291.800000 1498.820000 292.280000 ;
+ RECT 1497.720000 286.360000 1498.820000 286.840000 ;
+ RECT 1497.720000 280.920000 1498.820000 281.400000 ;
+ RECT 1497.720000 275.480000 1498.820000 275.960000 ;
+ RECT 1542.720000 264.600000 1543.820000 265.080000 ;
+ RECT 1542.720000 259.160000 1543.820000 259.640000 ;
+ RECT 1542.720000 253.720000 1543.820000 254.200000 ;
+ RECT 1542.720000 248.280000 1543.820000 248.760000 ;
+ RECT 1542.720000 270.040000 1543.820000 270.520000 ;
+ RECT 1497.720000 259.160000 1498.820000 259.640000 ;
+ RECT 1497.720000 253.720000 1498.820000 254.200000 ;
+ RECT 1497.720000 248.280000 1498.820000 248.760000 ;
+ RECT 1497.720000 264.600000 1498.820000 265.080000 ;
+ RECT 1497.720000 270.040000 1498.820000 270.520000 ;
+ RECT 1452.720000 291.800000 1453.820000 292.280000 ;
+ RECT 1448.590000 291.800000 1449.590000 292.280000 ;
+ RECT 1452.720000 286.360000 1453.820000 286.840000 ;
+ RECT 1448.590000 286.360000 1449.590000 286.840000 ;
+ RECT 1452.720000 280.920000 1453.820000 281.400000 ;
+ RECT 1448.590000 280.920000 1449.590000 281.400000 ;
+ RECT 1452.720000 275.480000 1453.820000 275.960000 ;
+ RECT 1448.590000 275.480000 1449.590000 275.960000 ;
+ RECT 1452.720000 270.040000 1453.820000 270.520000 ;
+ RECT 1452.720000 264.600000 1453.820000 265.080000 ;
+ RECT 1448.590000 270.040000 1449.590000 270.520000 ;
+ RECT 1448.590000 264.600000 1449.590000 265.080000 ;
+ RECT 1452.720000 259.160000 1453.820000 259.640000 ;
+ RECT 1448.590000 259.160000 1449.590000 259.640000 ;
+ RECT 1452.720000 253.720000 1453.820000 254.200000 ;
+ RECT 1448.590000 253.720000 1449.590000 254.200000 ;
+ RECT 1452.720000 248.280000 1453.820000 248.760000 ;
+ RECT 1448.590000 248.280000 1449.590000 248.760000 ;
+ RECT 1542.720000 242.840000 1543.820000 243.320000 ;
+ RECT 1542.720000 237.400000 1543.820000 237.880000 ;
+ RECT 1542.720000 231.960000 1543.820000 232.440000 ;
+ RECT 1542.720000 226.520000 1543.820000 227.000000 ;
+ RECT 1542.720000 221.080000 1543.820000 221.560000 ;
+ RECT 1497.720000 242.840000 1498.820000 243.320000 ;
+ RECT 1497.720000 237.400000 1498.820000 237.880000 ;
+ RECT 1497.720000 231.960000 1498.820000 232.440000 ;
+ RECT 1497.720000 226.520000 1498.820000 227.000000 ;
+ RECT 1497.720000 221.080000 1498.820000 221.560000 ;
+ RECT 1542.720000 215.640000 1543.820000 216.120000 ;
+ RECT 1542.720000 210.200000 1543.820000 210.680000 ;
+ RECT 1542.720000 204.760000 1543.820000 205.240000 ;
+ RECT 1542.720000 199.320000 1543.820000 199.800000 ;
+ RECT 1497.720000 210.200000 1498.820000 210.680000 ;
+ RECT 1497.720000 204.760000 1498.820000 205.240000 ;
+ RECT 1497.720000 199.320000 1498.820000 199.800000 ;
+ RECT 1497.720000 215.640000 1498.820000 216.120000 ;
+ RECT 1452.720000 242.840000 1453.820000 243.320000 ;
+ RECT 1448.590000 242.840000 1449.590000 243.320000 ;
+ RECT 1452.720000 237.400000 1453.820000 237.880000 ;
+ RECT 1448.590000 237.400000 1449.590000 237.880000 ;
+ RECT 1452.720000 231.960000 1453.820000 232.440000 ;
+ RECT 1448.590000 231.960000 1449.590000 232.440000 ;
+ RECT 1452.720000 221.080000 1453.820000 221.560000 ;
+ RECT 1448.590000 221.080000 1449.590000 221.560000 ;
+ RECT 1448.590000 226.520000 1449.590000 227.000000 ;
+ RECT 1452.720000 226.520000 1453.820000 227.000000 ;
+ RECT 1452.720000 215.640000 1453.820000 216.120000 ;
+ RECT 1448.590000 215.640000 1449.590000 216.120000 ;
+ RECT 1452.720000 210.200000 1453.820000 210.680000 ;
+ RECT 1448.590000 210.200000 1449.590000 210.680000 ;
+ RECT 1452.720000 204.760000 1453.820000 205.240000 ;
+ RECT 1448.590000 204.760000 1449.590000 205.240000 ;
+ RECT 1452.720000 199.320000 1453.820000 199.800000 ;
+ RECT 1448.590000 199.320000 1449.590000 199.800000 ;
+ RECT 1542.720000 193.880000 1543.820000 194.360000 ;
+ RECT 1542.720000 188.440000 1543.820000 188.920000 ;
+ RECT 1542.720000 183.000000 1543.820000 183.480000 ;
+ RECT 1542.720000 177.560000 1543.820000 178.040000 ;
+ RECT 1542.720000 172.120000 1543.820000 172.600000 ;
+ RECT 1497.720000 193.880000 1498.820000 194.360000 ;
+ RECT 1497.720000 188.440000 1498.820000 188.920000 ;
+ RECT 1497.720000 183.000000 1498.820000 183.480000 ;
+ RECT 1497.720000 177.560000 1498.820000 178.040000 ;
+ RECT 1497.720000 172.120000 1498.820000 172.600000 ;
+ RECT 1542.720000 150.360000 1543.820000 150.840000 ;
+ RECT 1542.720000 155.800000 1543.820000 156.280000 ;
+ RECT 1542.720000 161.240000 1543.820000 161.720000 ;
+ RECT 1542.720000 166.680000 1543.820000 167.160000 ;
+ RECT 1497.720000 150.360000 1498.820000 150.840000 ;
+ RECT 1497.720000 155.800000 1498.820000 156.280000 ;
+ RECT 1497.720000 161.240000 1498.820000 161.720000 ;
+ RECT 1497.720000 166.680000 1498.820000 167.160000 ;
+ RECT 1452.720000 193.880000 1453.820000 194.360000 ;
+ RECT 1448.590000 193.880000 1449.590000 194.360000 ;
+ RECT 1452.720000 188.440000 1453.820000 188.920000 ;
+ RECT 1448.590000 188.440000 1449.590000 188.920000 ;
+ RECT 1452.720000 177.560000 1453.820000 178.040000 ;
+ RECT 1448.590000 177.560000 1449.590000 178.040000 ;
+ RECT 1452.720000 172.120000 1453.820000 172.600000 ;
+ RECT 1448.590000 172.120000 1449.590000 172.600000 ;
+ RECT 1452.720000 183.000000 1453.820000 183.480000 ;
+ RECT 1448.590000 183.000000 1449.590000 183.480000 ;
+ RECT 1452.720000 166.680000 1453.820000 167.160000 ;
+ RECT 1448.590000 166.680000 1449.590000 167.160000 ;
+ RECT 1452.720000 161.240000 1453.820000 161.720000 ;
+ RECT 1448.590000 161.240000 1449.590000 161.720000 ;
+ RECT 1452.720000 155.800000 1453.820000 156.280000 ;
+ RECT 1452.720000 150.360000 1453.820000 150.840000 ;
+ RECT 1448.590000 155.800000 1449.590000 156.280000 ;
+ RECT 1448.590000 150.360000 1449.590000 150.840000 ;
+ RECT 1445.760000 541.490000 1645.860000 542.490000 ;
+ RECT 1445.760000 148.350000 1645.860000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 145.500000 1449.590000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 545.020000 1449.590000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 145.500000 1643.030000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 545.020000 1643.030000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 148.350000 1446.760000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 148.350000 1645.860000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 541.490000 1446.760000 542.490000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 541.490000 1645.860000 542.490000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'S_term_DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 115.240000 1449.590000 145.500000 ;
+ RECT 1642.030000 115.240000 1643.030000 145.500000 ;
+ RECT 1452.720000 118.090000 1453.820000 142.140000 ;
+ RECT 1497.720000 118.090000 1498.820000 142.140000 ;
+ RECT 1542.720000 118.090000 1543.820000 142.140000 ;
+ RECT 1587.720000 118.090000 1588.820000 142.140000 ;
+ RECT 1632.720000 118.090000 1633.820000 142.140000 ;
+ LAYER met3 ;
+ RECT 1642.030000 130.980000 1643.030000 131.460000 ;
+ RECT 1642.030000 136.420000 1643.030000 136.900000 ;
+ RECT 1632.720000 136.420000 1633.820000 136.900000 ;
+ RECT 1632.720000 130.980000 1633.820000 131.460000 ;
+ RECT 1587.720000 130.980000 1588.820000 131.460000 ;
+ RECT 1587.720000 136.420000 1588.820000 136.900000 ;
+ RECT 1497.720000 130.980000 1498.820000 131.460000 ;
+ RECT 1542.720000 130.980000 1543.820000 131.460000 ;
+ RECT 1542.720000 136.420000 1543.820000 136.900000 ;
+ RECT 1497.720000 136.420000 1498.820000 136.900000 ;
+ RECT 1448.590000 130.980000 1449.590000 131.460000 ;
+ RECT 1452.720000 130.980000 1453.820000 131.460000 ;
+ RECT 1452.720000 136.420000 1453.820000 136.900000 ;
+ RECT 1448.590000 136.420000 1449.590000 136.900000 ;
+ RECT 1642.030000 120.100000 1643.030000 120.580000 ;
+ RECT 1642.030000 125.540000 1643.030000 126.020000 ;
+ RECT 1632.720000 125.540000 1633.820000 126.020000 ;
+ RECT 1632.720000 120.100000 1633.820000 120.580000 ;
+ RECT 1587.720000 120.100000 1588.820000 120.580000 ;
+ RECT 1587.720000 125.540000 1588.820000 126.020000 ;
+ RECT 1497.720000 120.100000 1498.820000 120.580000 ;
+ RECT 1542.720000 120.100000 1543.820000 120.580000 ;
+ RECT 1542.720000 125.540000 1543.820000 126.020000 ;
+ RECT 1497.720000 125.540000 1498.820000 126.020000 ;
+ RECT 1448.590000 125.540000 1449.590000 126.020000 ;
+ RECT 1452.720000 125.540000 1453.820000 126.020000 ;
+ RECT 1448.590000 120.100000 1449.590000 120.580000 ;
+ RECT 1452.720000 120.100000 1453.820000 120.580000 ;
+ RECT 1445.760000 141.140000 1645.860000 142.140000 ;
+ RECT 1445.760000 118.090000 1645.860000 119.090000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 115.240000 1449.590000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 144.500000 1449.590000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 115.240000 1643.030000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 144.500000 1643.030000 145.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 118.090000 1446.760000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 118.090000 1645.860000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 141.140000 1446.760000 142.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 141.140000 1645.860000 142.140000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 2949.140000 1449.590000 3349.660000 ;
+ RECT 1642.030000 2949.140000 1643.030000 3349.660000 ;
+ RECT 1452.720000 2951.990000 1453.820000 3346.130000 ;
+ RECT 1497.720000 2951.990000 1498.820000 3346.130000 ;
+ RECT 1542.720000 2951.990000 1543.820000 3346.130000 ;
+ RECT 1587.720000 2951.990000 1588.820000 3346.130000 ;
+ RECT 1632.720000 2951.990000 1633.820000 3346.130000 ;
+ LAYER met3 ;
+ RECT 1632.720000 3340.240000 1633.820000 3340.720000 ;
+ RECT 1642.030000 3340.240000 1643.030000 3340.720000 ;
+ RECT 1642.030000 3334.800000 1643.030000 3335.280000 ;
+ RECT 1632.720000 3334.800000 1633.820000 3335.280000 ;
+ RECT 1632.720000 3329.360000 1633.820000 3329.840000 ;
+ RECT 1642.030000 3329.360000 1643.030000 3329.840000 ;
+ RECT 1642.030000 3313.040000 1643.030000 3313.520000 ;
+ RECT 1642.030000 3318.480000 1643.030000 3318.960000 ;
+ RECT 1642.030000 3323.920000 1643.030000 3324.400000 ;
+ RECT 1632.720000 3323.920000 1633.820000 3324.400000 ;
+ RECT 1632.720000 3313.040000 1633.820000 3313.520000 ;
+ RECT 1632.720000 3318.480000 1633.820000 3318.960000 ;
+ RECT 1632.720000 3302.160000 1633.820000 3302.640000 ;
+ RECT 1632.720000 3307.600000 1633.820000 3308.080000 ;
+ RECT 1642.030000 3307.600000 1643.030000 3308.080000 ;
+ RECT 1642.030000 3302.160000 1643.030000 3302.640000 ;
+ RECT 1587.720000 3340.240000 1588.820000 3340.720000 ;
+ RECT 1587.720000 3334.800000 1588.820000 3335.280000 ;
+ RECT 1587.720000 3329.360000 1588.820000 3329.840000 ;
+ RECT 1587.720000 3323.920000 1588.820000 3324.400000 ;
+ RECT 1587.720000 3302.160000 1588.820000 3302.640000 ;
+ RECT 1587.720000 3307.600000 1588.820000 3308.080000 ;
+ RECT 1587.720000 3313.040000 1588.820000 3313.520000 ;
+ RECT 1587.720000 3318.480000 1588.820000 3318.960000 ;
+ RECT 1632.720000 3296.720000 1633.820000 3297.200000 ;
+ RECT 1632.720000 3291.280000 1633.820000 3291.760000 ;
+ RECT 1642.030000 3296.720000 1643.030000 3297.200000 ;
+ RECT 1642.030000 3291.280000 1643.030000 3291.760000 ;
+ RECT 1642.030000 3274.960000 1643.030000 3275.440000 ;
+ RECT 1642.030000 3280.400000 1643.030000 3280.880000 ;
+ RECT 1642.030000 3285.840000 1643.030000 3286.320000 ;
+ RECT 1632.720000 3285.840000 1633.820000 3286.320000 ;
+ RECT 1632.720000 3280.400000 1633.820000 3280.880000 ;
+ RECT 1632.720000 3274.960000 1633.820000 3275.440000 ;
+ RECT 1632.720000 3264.080000 1633.820000 3264.560000 ;
+ RECT 1632.720000 3269.520000 1633.820000 3270.000000 ;
+ RECT 1642.030000 3269.520000 1643.030000 3270.000000 ;
+ RECT 1642.030000 3264.080000 1643.030000 3264.560000 ;
+ RECT 1642.030000 3253.200000 1643.030000 3253.680000 ;
+ RECT 1642.030000 3258.640000 1643.030000 3259.120000 ;
+ RECT 1632.720000 3253.200000 1633.820000 3253.680000 ;
+ RECT 1632.720000 3258.640000 1633.820000 3259.120000 ;
+ RECT 1587.720000 3296.720000 1588.820000 3297.200000 ;
+ RECT 1587.720000 3291.280000 1588.820000 3291.760000 ;
+ RECT 1587.720000 3285.840000 1588.820000 3286.320000 ;
+ RECT 1587.720000 3280.400000 1588.820000 3280.880000 ;
+ RECT 1587.720000 3274.960000 1588.820000 3275.440000 ;
+ RECT 1587.720000 3253.200000 1588.820000 3253.680000 ;
+ RECT 1587.720000 3258.640000 1588.820000 3259.120000 ;
+ RECT 1587.720000 3264.080000 1588.820000 3264.560000 ;
+ RECT 1587.720000 3269.520000 1588.820000 3270.000000 ;
+ RECT 1632.720000 3247.760000 1633.820000 3248.240000 ;
+ RECT 1632.720000 3242.320000 1633.820000 3242.800000 ;
+ RECT 1642.030000 3247.760000 1643.030000 3248.240000 ;
+ RECT 1642.030000 3242.320000 1643.030000 3242.800000 ;
+ RECT 1632.720000 3231.440000 1633.820000 3231.920000 ;
+ RECT 1632.720000 3226.000000 1633.820000 3226.480000 ;
+ RECT 1642.030000 3231.440000 1643.030000 3231.920000 ;
+ RECT 1642.030000 3226.000000 1643.030000 3226.480000 ;
+ RECT 1632.720000 3236.880000 1633.820000 3237.360000 ;
+ RECT 1642.030000 3236.880000 1643.030000 3237.360000 ;
+ RECT 1642.030000 3215.120000 1643.030000 3215.600000 ;
+ RECT 1642.030000 3220.560000 1643.030000 3221.040000 ;
+ RECT 1632.720000 3215.120000 1633.820000 3215.600000 ;
+ RECT 1632.720000 3220.560000 1633.820000 3221.040000 ;
+ RECT 1632.720000 3204.240000 1633.820000 3204.720000 ;
+ RECT 1632.720000 3209.680000 1633.820000 3210.160000 ;
+ RECT 1642.030000 3209.680000 1643.030000 3210.160000 ;
+ RECT 1642.030000 3204.240000 1643.030000 3204.720000 ;
+ RECT 1587.720000 3247.760000 1588.820000 3248.240000 ;
+ RECT 1587.720000 3242.320000 1588.820000 3242.800000 ;
+ RECT 1587.720000 3236.880000 1588.820000 3237.360000 ;
+ RECT 1587.720000 3231.440000 1588.820000 3231.920000 ;
+ RECT 1587.720000 3226.000000 1588.820000 3226.480000 ;
+ RECT 1587.720000 3204.240000 1588.820000 3204.720000 ;
+ RECT 1587.720000 3209.680000 1588.820000 3210.160000 ;
+ RECT 1587.720000 3215.120000 1588.820000 3215.600000 ;
+ RECT 1587.720000 3220.560000 1588.820000 3221.040000 ;
+ RECT 1642.030000 3187.920000 1643.030000 3188.400000 ;
+ RECT 1642.030000 3193.360000 1643.030000 3193.840000 ;
+ RECT 1642.030000 3198.800000 1643.030000 3199.280000 ;
+ RECT 1632.720000 3198.800000 1633.820000 3199.280000 ;
+ RECT 1632.720000 3193.360000 1633.820000 3193.840000 ;
+ RECT 1632.720000 3187.920000 1633.820000 3188.400000 ;
+ RECT 1632.720000 3182.480000 1633.820000 3182.960000 ;
+ RECT 1632.720000 3177.040000 1633.820000 3177.520000 ;
+ RECT 1642.030000 3182.480000 1643.030000 3182.960000 ;
+ RECT 1642.030000 3177.040000 1643.030000 3177.520000 ;
+ RECT 1632.720000 3166.160000 1633.820000 3166.640000 ;
+ RECT 1632.720000 3171.600000 1633.820000 3172.080000 ;
+ RECT 1642.030000 3171.600000 1643.030000 3172.080000 ;
+ RECT 1642.030000 3166.160000 1643.030000 3166.640000 ;
+ RECT 1642.030000 3149.840000 1643.030000 3150.320000 ;
+ RECT 1642.030000 3155.280000 1643.030000 3155.760000 ;
+ RECT 1642.030000 3160.720000 1643.030000 3161.200000 ;
+ RECT 1632.720000 3160.720000 1633.820000 3161.200000 ;
+ RECT 1632.720000 3155.280000 1633.820000 3155.760000 ;
+ RECT 1632.720000 3149.840000 1633.820000 3150.320000 ;
+ RECT 1587.720000 3198.800000 1588.820000 3199.280000 ;
+ RECT 1587.720000 3193.360000 1588.820000 3193.840000 ;
+ RECT 1587.720000 3187.920000 1588.820000 3188.400000 ;
+ RECT 1587.720000 3182.480000 1588.820000 3182.960000 ;
+ RECT 1587.720000 3177.040000 1588.820000 3177.520000 ;
+ RECT 1587.720000 3166.160000 1588.820000 3166.640000 ;
+ RECT 1587.720000 3160.720000 1588.820000 3161.200000 ;
+ RECT 1587.720000 3155.280000 1588.820000 3155.760000 ;
+ RECT 1587.720000 3149.840000 1588.820000 3150.320000 ;
+ RECT 1587.720000 3171.600000 1588.820000 3172.080000 ;
+ RECT 1542.720000 3340.240000 1543.820000 3340.720000 ;
+ RECT 1542.720000 3334.800000 1543.820000 3335.280000 ;
+ RECT 1542.720000 3329.360000 1543.820000 3329.840000 ;
+ RECT 1497.720000 3340.240000 1498.820000 3340.720000 ;
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+ RECT 1448.590000 3073.680000 1449.590000 3074.160000 ;
+ RECT 1448.590000 3068.240000 1449.590000 3068.720000 ;
+ RECT 1452.720000 3062.800000 1453.820000 3063.280000 ;
+ RECT 1448.590000 3062.800000 1449.590000 3063.280000 ;
+ RECT 1452.720000 3057.360000 1453.820000 3057.840000 ;
+ RECT 1448.590000 3057.360000 1449.590000 3057.840000 ;
+ RECT 1452.720000 3051.920000 1453.820000 3052.400000 ;
+ RECT 1448.590000 3051.920000 1449.590000 3052.400000 ;
+ RECT 1542.720000 3046.480000 1543.820000 3046.960000 ;
+ RECT 1542.720000 3041.040000 1543.820000 3041.520000 ;
+ RECT 1542.720000 3035.600000 1543.820000 3036.080000 ;
+ RECT 1542.720000 3030.160000 1543.820000 3030.640000 ;
+ RECT 1542.720000 3024.720000 1543.820000 3025.200000 ;
+ RECT 1497.720000 3046.480000 1498.820000 3046.960000 ;
+ RECT 1497.720000 3041.040000 1498.820000 3041.520000 ;
+ RECT 1497.720000 3035.600000 1498.820000 3036.080000 ;
+ RECT 1497.720000 3030.160000 1498.820000 3030.640000 ;
+ RECT 1497.720000 3024.720000 1498.820000 3025.200000 ;
+ RECT 1542.720000 3019.280000 1543.820000 3019.760000 ;
+ RECT 1542.720000 3013.840000 1543.820000 3014.320000 ;
+ RECT 1542.720000 3008.400000 1543.820000 3008.880000 ;
+ RECT 1542.720000 3002.960000 1543.820000 3003.440000 ;
+ RECT 1497.720000 3013.840000 1498.820000 3014.320000 ;
+ RECT 1497.720000 3008.400000 1498.820000 3008.880000 ;
+ RECT 1497.720000 3002.960000 1498.820000 3003.440000 ;
+ RECT 1497.720000 3019.280000 1498.820000 3019.760000 ;
+ RECT 1452.720000 3046.480000 1453.820000 3046.960000 ;
+ RECT 1448.590000 3046.480000 1449.590000 3046.960000 ;
+ RECT 1452.720000 3041.040000 1453.820000 3041.520000 ;
+ RECT 1448.590000 3041.040000 1449.590000 3041.520000 ;
+ RECT 1452.720000 3035.600000 1453.820000 3036.080000 ;
+ RECT 1448.590000 3035.600000 1449.590000 3036.080000 ;
+ RECT 1452.720000 3024.720000 1453.820000 3025.200000 ;
+ RECT 1448.590000 3024.720000 1449.590000 3025.200000 ;
+ RECT 1448.590000 3030.160000 1449.590000 3030.640000 ;
+ RECT 1452.720000 3030.160000 1453.820000 3030.640000 ;
+ RECT 1452.720000 3019.280000 1453.820000 3019.760000 ;
+ RECT 1448.590000 3019.280000 1449.590000 3019.760000 ;
+ RECT 1452.720000 3013.840000 1453.820000 3014.320000 ;
+ RECT 1448.590000 3013.840000 1449.590000 3014.320000 ;
+ RECT 1452.720000 3008.400000 1453.820000 3008.880000 ;
+ RECT 1448.590000 3008.400000 1449.590000 3008.880000 ;
+ RECT 1452.720000 3002.960000 1453.820000 3003.440000 ;
+ RECT 1448.590000 3002.960000 1449.590000 3003.440000 ;
+ RECT 1542.720000 2997.520000 1543.820000 2998.000000 ;
+ RECT 1542.720000 2992.080000 1543.820000 2992.560000 ;
+ RECT 1542.720000 2986.640000 1543.820000 2987.120000 ;
+ RECT 1542.720000 2981.200000 1543.820000 2981.680000 ;
+ RECT 1542.720000 2975.760000 1543.820000 2976.240000 ;
+ RECT 1497.720000 2997.520000 1498.820000 2998.000000 ;
+ RECT 1497.720000 2992.080000 1498.820000 2992.560000 ;
+ RECT 1497.720000 2986.640000 1498.820000 2987.120000 ;
+ RECT 1497.720000 2981.200000 1498.820000 2981.680000 ;
+ RECT 1497.720000 2975.760000 1498.820000 2976.240000 ;
+ RECT 1542.720000 2954.000000 1543.820000 2954.480000 ;
+ RECT 1542.720000 2959.440000 1543.820000 2959.920000 ;
+ RECT 1542.720000 2964.880000 1543.820000 2965.360000 ;
+ RECT 1542.720000 2970.320000 1543.820000 2970.800000 ;
+ RECT 1497.720000 2954.000000 1498.820000 2954.480000 ;
+ RECT 1497.720000 2959.440000 1498.820000 2959.920000 ;
+ RECT 1497.720000 2964.880000 1498.820000 2965.360000 ;
+ RECT 1497.720000 2970.320000 1498.820000 2970.800000 ;
+ RECT 1452.720000 2997.520000 1453.820000 2998.000000 ;
+ RECT 1448.590000 2997.520000 1449.590000 2998.000000 ;
+ RECT 1452.720000 2992.080000 1453.820000 2992.560000 ;
+ RECT 1448.590000 2992.080000 1449.590000 2992.560000 ;
+ RECT 1452.720000 2981.200000 1453.820000 2981.680000 ;
+ RECT 1448.590000 2981.200000 1449.590000 2981.680000 ;
+ RECT 1452.720000 2975.760000 1453.820000 2976.240000 ;
+ RECT 1448.590000 2975.760000 1449.590000 2976.240000 ;
+ RECT 1452.720000 2986.640000 1453.820000 2987.120000 ;
+ RECT 1448.590000 2986.640000 1449.590000 2987.120000 ;
+ RECT 1452.720000 2970.320000 1453.820000 2970.800000 ;
+ RECT 1448.590000 2970.320000 1449.590000 2970.800000 ;
+ RECT 1452.720000 2964.880000 1453.820000 2965.360000 ;
+ RECT 1448.590000 2964.880000 1449.590000 2965.360000 ;
+ RECT 1452.720000 2959.440000 1453.820000 2959.920000 ;
+ RECT 1452.720000 2954.000000 1453.820000 2954.480000 ;
+ RECT 1448.590000 2959.440000 1449.590000 2959.920000 ;
+ RECT 1448.590000 2954.000000 1449.590000 2954.480000 ;
+ RECT 1445.760000 3345.130000 1645.860000 3346.130000 ;
+ RECT 1445.760000 2951.990000 1645.860000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 2949.140000 1449.590000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 3348.660000 1449.590000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 2949.140000 1643.030000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 3348.660000 1643.030000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2951.990000 1446.760000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2951.990000 1645.860000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 3345.130000 1446.760000 3346.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 3345.130000 1645.860000 3346.130000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 2548.620000 1449.590000 2949.140000 ;
+ RECT 1642.030000 2548.620000 1643.030000 2949.140000 ;
+ RECT 1452.720000 2551.470000 1453.820000 2945.610000 ;
+ RECT 1497.720000 2551.470000 1498.820000 2945.610000 ;
+ RECT 1542.720000 2551.470000 1543.820000 2945.610000 ;
+ RECT 1587.720000 2551.470000 1588.820000 2945.610000 ;
+ RECT 1632.720000 2551.470000 1633.820000 2945.610000 ;
+ LAYER met3 ;
+ RECT 1632.720000 2939.720000 1633.820000 2940.200000 ;
+ RECT 1642.030000 2939.720000 1643.030000 2940.200000 ;
+ RECT 1642.030000 2934.280000 1643.030000 2934.760000 ;
+ RECT 1632.720000 2934.280000 1633.820000 2934.760000 ;
+ RECT 1632.720000 2928.840000 1633.820000 2929.320000 ;
+ RECT 1642.030000 2928.840000 1643.030000 2929.320000 ;
+ RECT 1642.030000 2912.520000 1643.030000 2913.000000 ;
+ RECT 1642.030000 2917.960000 1643.030000 2918.440000 ;
+ RECT 1642.030000 2923.400000 1643.030000 2923.880000 ;
+ RECT 1632.720000 2923.400000 1633.820000 2923.880000 ;
+ RECT 1632.720000 2912.520000 1633.820000 2913.000000 ;
+ RECT 1632.720000 2917.960000 1633.820000 2918.440000 ;
+ RECT 1632.720000 2901.640000 1633.820000 2902.120000 ;
+ RECT 1632.720000 2907.080000 1633.820000 2907.560000 ;
+ RECT 1642.030000 2907.080000 1643.030000 2907.560000 ;
+ RECT 1642.030000 2901.640000 1643.030000 2902.120000 ;
+ RECT 1587.720000 2939.720000 1588.820000 2940.200000 ;
+ RECT 1587.720000 2934.280000 1588.820000 2934.760000 ;
+ RECT 1587.720000 2928.840000 1588.820000 2929.320000 ;
+ RECT 1587.720000 2923.400000 1588.820000 2923.880000 ;
+ RECT 1587.720000 2901.640000 1588.820000 2902.120000 ;
+ RECT 1587.720000 2907.080000 1588.820000 2907.560000 ;
+ RECT 1587.720000 2912.520000 1588.820000 2913.000000 ;
+ RECT 1587.720000 2917.960000 1588.820000 2918.440000 ;
+ RECT 1632.720000 2896.200000 1633.820000 2896.680000 ;
+ RECT 1632.720000 2890.760000 1633.820000 2891.240000 ;
+ RECT 1642.030000 2896.200000 1643.030000 2896.680000 ;
+ RECT 1642.030000 2890.760000 1643.030000 2891.240000 ;
+ RECT 1642.030000 2874.440000 1643.030000 2874.920000 ;
+ RECT 1642.030000 2879.880000 1643.030000 2880.360000 ;
+ RECT 1642.030000 2885.320000 1643.030000 2885.800000 ;
+ RECT 1632.720000 2885.320000 1633.820000 2885.800000 ;
+ RECT 1632.720000 2879.880000 1633.820000 2880.360000 ;
+ RECT 1632.720000 2874.440000 1633.820000 2874.920000 ;
+ RECT 1632.720000 2863.560000 1633.820000 2864.040000 ;
+ RECT 1632.720000 2869.000000 1633.820000 2869.480000 ;
+ RECT 1642.030000 2869.000000 1643.030000 2869.480000 ;
+ RECT 1642.030000 2863.560000 1643.030000 2864.040000 ;
+ RECT 1642.030000 2852.680000 1643.030000 2853.160000 ;
+ RECT 1642.030000 2858.120000 1643.030000 2858.600000 ;
+ RECT 1632.720000 2852.680000 1633.820000 2853.160000 ;
+ RECT 1632.720000 2858.120000 1633.820000 2858.600000 ;
+ RECT 1587.720000 2896.200000 1588.820000 2896.680000 ;
+ RECT 1587.720000 2890.760000 1588.820000 2891.240000 ;
+ RECT 1587.720000 2885.320000 1588.820000 2885.800000 ;
+ RECT 1587.720000 2879.880000 1588.820000 2880.360000 ;
+ RECT 1587.720000 2874.440000 1588.820000 2874.920000 ;
+ RECT 1587.720000 2852.680000 1588.820000 2853.160000 ;
+ RECT 1587.720000 2858.120000 1588.820000 2858.600000 ;
+ RECT 1587.720000 2863.560000 1588.820000 2864.040000 ;
+ RECT 1587.720000 2869.000000 1588.820000 2869.480000 ;
+ RECT 1632.720000 2847.240000 1633.820000 2847.720000 ;
+ RECT 1632.720000 2841.800000 1633.820000 2842.280000 ;
+ RECT 1642.030000 2847.240000 1643.030000 2847.720000 ;
+ RECT 1642.030000 2841.800000 1643.030000 2842.280000 ;
+ RECT 1632.720000 2830.920000 1633.820000 2831.400000 ;
+ RECT 1632.720000 2825.480000 1633.820000 2825.960000 ;
+ RECT 1642.030000 2830.920000 1643.030000 2831.400000 ;
+ RECT 1642.030000 2825.480000 1643.030000 2825.960000 ;
+ RECT 1632.720000 2836.360000 1633.820000 2836.840000 ;
+ RECT 1642.030000 2836.360000 1643.030000 2836.840000 ;
+ RECT 1642.030000 2814.600000 1643.030000 2815.080000 ;
+ RECT 1642.030000 2820.040000 1643.030000 2820.520000 ;
+ RECT 1632.720000 2814.600000 1633.820000 2815.080000 ;
+ RECT 1632.720000 2820.040000 1633.820000 2820.520000 ;
+ RECT 1632.720000 2803.720000 1633.820000 2804.200000 ;
+ RECT 1632.720000 2809.160000 1633.820000 2809.640000 ;
+ RECT 1642.030000 2809.160000 1643.030000 2809.640000 ;
+ RECT 1642.030000 2803.720000 1643.030000 2804.200000 ;
+ RECT 1587.720000 2847.240000 1588.820000 2847.720000 ;
+ RECT 1587.720000 2841.800000 1588.820000 2842.280000 ;
+ RECT 1587.720000 2836.360000 1588.820000 2836.840000 ;
+ RECT 1587.720000 2830.920000 1588.820000 2831.400000 ;
+ RECT 1587.720000 2825.480000 1588.820000 2825.960000 ;
+ RECT 1587.720000 2803.720000 1588.820000 2804.200000 ;
+ RECT 1587.720000 2809.160000 1588.820000 2809.640000 ;
+ RECT 1587.720000 2814.600000 1588.820000 2815.080000 ;
+ RECT 1587.720000 2820.040000 1588.820000 2820.520000 ;
+ RECT 1642.030000 2787.400000 1643.030000 2787.880000 ;
+ RECT 1642.030000 2792.840000 1643.030000 2793.320000 ;
+ RECT 1642.030000 2798.280000 1643.030000 2798.760000 ;
+ RECT 1632.720000 2798.280000 1633.820000 2798.760000 ;
+ RECT 1632.720000 2792.840000 1633.820000 2793.320000 ;
+ RECT 1632.720000 2787.400000 1633.820000 2787.880000 ;
+ RECT 1632.720000 2781.960000 1633.820000 2782.440000 ;
+ RECT 1632.720000 2776.520000 1633.820000 2777.000000 ;
+ RECT 1642.030000 2781.960000 1643.030000 2782.440000 ;
+ RECT 1642.030000 2776.520000 1643.030000 2777.000000 ;
+ RECT 1632.720000 2765.640000 1633.820000 2766.120000 ;
+ RECT 1632.720000 2771.080000 1633.820000 2771.560000 ;
+ RECT 1642.030000 2771.080000 1643.030000 2771.560000 ;
+ RECT 1642.030000 2765.640000 1643.030000 2766.120000 ;
+ RECT 1642.030000 2749.320000 1643.030000 2749.800000 ;
+ RECT 1642.030000 2754.760000 1643.030000 2755.240000 ;
+ RECT 1642.030000 2760.200000 1643.030000 2760.680000 ;
+ RECT 1632.720000 2760.200000 1633.820000 2760.680000 ;
+ RECT 1632.720000 2754.760000 1633.820000 2755.240000 ;
+ RECT 1632.720000 2749.320000 1633.820000 2749.800000 ;
+ RECT 1587.720000 2798.280000 1588.820000 2798.760000 ;
+ RECT 1587.720000 2792.840000 1588.820000 2793.320000 ;
+ RECT 1587.720000 2787.400000 1588.820000 2787.880000 ;
+ RECT 1587.720000 2781.960000 1588.820000 2782.440000 ;
+ RECT 1587.720000 2776.520000 1588.820000 2777.000000 ;
+ RECT 1587.720000 2765.640000 1588.820000 2766.120000 ;
+ RECT 1587.720000 2760.200000 1588.820000 2760.680000 ;
+ RECT 1587.720000 2754.760000 1588.820000 2755.240000 ;
+ RECT 1587.720000 2749.320000 1588.820000 2749.800000 ;
+ RECT 1587.720000 2771.080000 1588.820000 2771.560000 ;
+ RECT 1542.720000 2939.720000 1543.820000 2940.200000 ;
+ RECT 1542.720000 2934.280000 1543.820000 2934.760000 ;
+ RECT 1542.720000 2928.840000 1543.820000 2929.320000 ;
+ RECT 1497.720000 2939.720000 1498.820000 2940.200000 ;
+ RECT 1497.720000 2934.280000 1498.820000 2934.760000 ;
+ RECT 1497.720000 2928.840000 1498.820000 2929.320000 ;
+ RECT 1542.720000 2912.520000 1543.820000 2913.000000 ;
+ RECT 1542.720000 2907.080000 1543.820000 2907.560000 ;
+ RECT 1542.720000 2901.640000 1543.820000 2902.120000 ;
+ RECT 1542.720000 2917.960000 1543.820000 2918.440000 ;
+ RECT 1542.720000 2923.400000 1543.820000 2923.880000 ;
+ RECT 1497.720000 2923.400000 1498.820000 2923.880000 ;
+ RECT 1497.720000 2912.520000 1498.820000 2913.000000 ;
+ RECT 1497.720000 2907.080000 1498.820000 2907.560000 ;
+ RECT 1497.720000 2901.640000 1498.820000 2902.120000 ;
+ RECT 1497.720000 2917.960000 1498.820000 2918.440000 ;
+ RECT 1452.720000 2939.720000 1453.820000 2940.200000 ;
+ RECT 1448.590000 2939.720000 1449.590000 2940.200000 ;
+ RECT 1448.590000 2934.280000 1449.590000 2934.760000 ;
+ RECT 1452.720000 2934.280000 1453.820000 2934.760000 ;
+ RECT 1452.720000 2928.840000 1453.820000 2929.320000 ;
+ RECT 1448.590000 2928.840000 1449.590000 2929.320000 ;
+ RECT 1452.720000 2923.400000 1453.820000 2923.880000 ;
+ RECT 1452.720000 2917.960000 1453.820000 2918.440000 ;
+ RECT 1448.590000 2923.400000 1449.590000 2923.880000 ;
+ RECT 1448.590000 2917.960000 1449.590000 2918.440000 ;
+ RECT 1452.720000 2912.520000 1453.820000 2913.000000 ;
+ RECT 1448.590000 2912.520000 1449.590000 2913.000000 ;
+ RECT 1452.720000 2907.080000 1453.820000 2907.560000 ;
+ RECT 1448.590000 2907.080000 1449.590000 2907.560000 ;
+ RECT 1452.720000 2901.640000 1453.820000 2902.120000 ;
+ RECT 1448.590000 2901.640000 1449.590000 2902.120000 ;
+ RECT 1542.720000 2896.200000 1543.820000 2896.680000 ;
+ RECT 1542.720000 2890.760000 1543.820000 2891.240000 ;
+ RECT 1542.720000 2885.320000 1543.820000 2885.800000 ;
+ RECT 1542.720000 2879.880000 1543.820000 2880.360000 ;
+ RECT 1542.720000 2874.440000 1543.820000 2874.920000 ;
+ RECT 1497.720000 2896.200000 1498.820000 2896.680000 ;
+ RECT 1497.720000 2890.760000 1498.820000 2891.240000 ;
+ RECT 1497.720000 2885.320000 1498.820000 2885.800000 ;
+ RECT 1497.720000 2879.880000 1498.820000 2880.360000 ;
+ RECT 1497.720000 2874.440000 1498.820000 2874.920000 ;
+ RECT 1542.720000 2869.000000 1543.820000 2869.480000 ;
+ RECT 1542.720000 2863.560000 1543.820000 2864.040000 ;
+ RECT 1542.720000 2858.120000 1543.820000 2858.600000 ;
+ RECT 1542.720000 2852.680000 1543.820000 2853.160000 ;
+ RECT 1497.720000 2863.560000 1498.820000 2864.040000 ;
+ RECT 1497.720000 2858.120000 1498.820000 2858.600000 ;
+ RECT 1497.720000 2852.680000 1498.820000 2853.160000 ;
+ RECT 1497.720000 2869.000000 1498.820000 2869.480000 ;
+ RECT 1452.720000 2896.200000 1453.820000 2896.680000 ;
+ RECT 1448.590000 2896.200000 1449.590000 2896.680000 ;
+ RECT 1452.720000 2890.760000 1453.820000 2891.240000 ;
+ RECT 1448.590000 2890.760000 1449.590000 2891.240000 ;
+ RECT 1452.720000 2885.320000 1453.820000 2885.800000 ;
+ RECT 1448.590000 2885.320000 1449.590000 2885.800000 ;
+ RECT 1452.720000 2874.440000 1453.820000 2874.920000 ;
+ RECT 1448.590000 2874.440000 1449.590000 2874.920000 ;
+ RECT 1448.590000 2879.880000 1449.590000 2880.360000 ;
+ RECT 1452.720000 2879.880000 1453.820000 2880.360000 ;
+ RECT 1452.720000 2869.000000 1453.820000 2869.480000 ;
+ RECT 1448.590000 2869.000000 1449.590000 2869.480000 ;
+ RECT 1452.720000 2863.560000 1453.820000 2864.040000 ;
+ RECT 1448.590000 2863.560000 1449.590000 2864.040000 ;
+ RECT 1452.720000 2858.120000 1453.820000 2858.600000 ;
+ RECT 1448.590000 2858.120000 1449.590000 2858.600000 ;
+ RECT 1452.720000 2852.680000 1453.820000 2853.160000 ;
+ RECT 1448.590000 2852.680000 1449.590000 2853.160000 ;
+ RECT 1542.720000 2847.240000 1543.820000 2847.720000 ;
+ RECT 1542.720000 2841.800000 1543.820000 2842.280000 ;
+ RECT 1542.720000 2836.360000 1543.820000 2836.840000 ;
+ RECT 1542.720000 2830.920000 1543.820000 2831.400000 ;
+ RECT 1542.720000 2825.480000 1543.820000 2825.960000 ;
+ RECT 1497.720000 2847.240000 1498.820000 2847.720000 ;
+ RECT 1497.720000 2841.800000 1498.820000 2842.280000 ;
+ RECT 1497.720000 2836.360000 1498.820000 2836.840000 ;
+ RECT 1497.720000 2830.920000 1498.820000 2831.400000 ;
+ RECT 1497.720000 2825.480000 1498.820000 2825.960000 ;
+ RECT 1542.720000 2820.040000 1543.820000 2820.520000 ;
+ RECT 1542.720000 2814.600000 1543.820000 2815.080000 ;
+ RECT 1542.720000 2809.160000 1543.820000 2809.640000 ;
+ RECT 1542.720000 2803.720000 1543.820000 2804.200000 ;
+ RECT 1497.720000 2814.600000 1498.820000 2815.080000 ;
+ RECT 1497.720000 2809.160000 1498.820000 2809.640000 ;
+ RECT 1497.720000 2803.720000 1498.820000 2804.200000 ;
+ RECT 1497.720000 2820.040000 1498.820000 2820.520000 ;
+ RECT 1452.720000 2847.240000 1453.820000 2847.720000 ;
+ RECT 1448.590000 2847.240000 1449.590000 2847.720000 ;
+ RECT 1452.720000 2841.800000 1453.820000 2842.280000 ;
+ RECT 1448.590000 2841.800000 1449.590000 2842.280000 ;
+ RECT 1452.720000 2830.920000 1453.820000 2831.400000 ;
+ RECT 1448.590000 2830.920000 1449.590000 2831.400000 ;
+ RECT 1452.720000 2825.480000 1453.820000 2825.960000 ;
+ RECT 1448.590000 2825.480000 1449.590000 2825.960000 ;
+ RECT 1452.720000 2836.360000 1453.820000 2836.840000 ;
+ RECT 1448.590000 2836.360000 1449.590000 2836.840000 ;
+ RECT 1452.720000 2820.040000 1453.820000 2820.520000 ;
+ RECT 1448.590000 2820.040000 1449.590000 2820.520000 ;
+ RECT 1452.720000 2814.600000 1453.820000 2815.080000 ;
+ RECT 1448.590000 2814.600000 1449.590000 2815.080000 ;
+ RECT 1452.720000 2809.160000 1453.820000 2809.640000 ;
+ RECT 1448.590000 2809.160000 1449.590000 2809.640000 ;
+ RECT 1452.720000 2803.720000 1453.820000 2804.200000 ;
+ RECT 1448.590000 2803.720000 1449.590000 2804.200000 ;
+ RECT 1542.720000 2798.280000 1543.820000 2798.760000 ;
+ RECT 1542.720000 2792.840000 1543.820000 2793.320000 ;
+ RECT 1542.720000 2787.400000 1543.820000 2787.880000 ;
+ RECT 1542.720000 2781.960000 1543.820000 2782.440000 ;
+ RECT 1542.720000 2776.520000 1543.820000 2777.000000 ;
+ RECT 1497.720000 2798.280000 1498.820000 2798.760000 ;
+ RECT 1497.720000 2792.840000 1498.820000 2793.320000 ;
+ RECT 1497.720000 2787.400000 1498.820000 2787.880000 ;
+ RECT 1497.720000 2781.960000 1498.820000 2782.440000 ;
+ RECT 1497.720000 2776.520000 1498.820000 2777.000000 ;
+ RECT 1542.720000 2765.640000 1543.820000 2766.120000 ;
+ RECT 1542.720000 2749.320000 1543.820000 2749.800000 ;
+ RECT 1542.720000 2754.760000 1543.820000 2755.240000 ;
+ RECT 1542.720000 2760.200000 1543.820000 2760.680000 ;
+ RECT 1542.720000 2771.080000 1543.820000 2771.560000 ;
+ RECT 1497.720000 2749.320000 1498.820000 2749.800000 ;
+ RECT 1497.720000 2754.760000 1498.820000 2755.240000 ;
+ RECT 1497.720000 2760.200000 1498.820000 2760.680000 ;
+ RECT 1497.720000 2765.640000 1498.820000 2766.120000 ;
+ RECT 1497.720000 2771.080000 1498.820000 2771.560000 ;
+ RECT 1452.720000 2798.280000 1453.820000 2798.760000 ;
+ RECT 1452.720000 2792.840000 1453.820000 2793.320000 ;
+ RECT 1448.590000 2798.280000 1449.590000 2798.760000 ;
+ RECT 1448.590000 2792.840000 1449.590000 2793.320000 ;
+ RECT 1452.720000 2787.400000 1453.820000 2787.880000 ;
+ RECT 1448.590000 2787.400000 1449.590000 2787.880000 ;
+ RECT 1452.720000 2781.960000 1453.820000 2782.440000 ;
+ RECT 1448.590000 2781.960000 1449.590000 2782.440000 ;
+ RECT 1452.720000 2776.520000 1453.820000 2777.000000 ;
+ RECT 1448.590000 2776.520000 1449.590000 2777.000000 ;
+ RECT 1452.720000 2771.080000 1453.820000 2771.560000 ;
+ RECT 1448.590000 2771.080000 1449.590000 2771.560000 ;
+ RECT 1452.720000 2765.640000 1453.820000 2766.120000 ;
+ RECT 1448.590000 2765.640000 1449.590000 2766.120000 ;
+ RECT 1452.720000 2760.200000 1453.820000 2760.680000 ;
+ RECT 1448.590000 2760.200000 1449.590000 2760.680000 ;
+ RECT 1452.720000 2749.320000 1453.820000 2749.800000 ;
+ RECT 1448.590000 2749.320000 1449.590000 2749.800000 ;
+ RECT 1448.590000 2754.760000 1449.590000 2755.240000 ;
+ RECT 1452.720000 2754.760000 1453.820000 2755.240000 ;
+ RECT 1632.720000 2743.880000 1633.820000 2744.360000 ;
+ RECT 1632.720000 2738.440000 1633.820000 2738.920000 ;
+ RECT 1642.030000 2743.880000 1643.030000 2744.360000 ;
+ RECT 1642.030000 2738.440000 1643.030000 2738.920000 ;
+ RECT 1642.030000 2727.560000 1643.030000 2728.040000 ;
+ RECT 1642.030000 2733.000000 1643.030000 2733.480000 ;
+ RECT 1632.720000 2733.000000 1633.820000 2733.480000 ;
+ RECT 1632.720000 2727.560000 1633.820000 2728.040000 ;
+ RECT 1632.720000 2716.680000 1633.820000 2717.160000 ;
+ RECT 1632.720000 2722.120000 1633.820000 2722.600000 ;
+ RECT 1642.030000 2722.120000 1643.030000 2722.600000 ;
+ RECT 1642.030000 2716.680000 1643.030000 2717.160000 ;
+ RECT 1632.720000 2700.360000 1633.820000 2700.840000 ;
+ RECT 1632.720000 2705.800000 1633.820000 2706.280000 ;
+ RECT 1642.030000 2705.800000 1643.030000 2706.280000 ;
+ RECT 1642.030000 2700.360000 1643.030000 2700.840000 ;
+ RECT 1632.720000 2711.240000 1633.820000 2711.720000 ;
+ RECT 1642.030000 2711.240000 1643.030000 2711.720000 ;
+ RECT 1587.720000 2743.880000 1588.820000 2744.360000 ;
+ RECT 1587.720000 2738.440000 1588.820000 2738.920000 ;
+ RECT 1587.720000 2733.000000 1588.820000 2733.480000 ;
+ RECT 1587.720000 2727.560000 1588.820000 2728.040000 ;
+ RECT 1587.720000 2700.360000 1588.820000 2700.840000 ;
+ RECT 1587.720000 2705.800000 1588.820000 2706.280000 ;
+ RECT 1587.720000 2711.240000 1588.820000 2711.720000 ;
+ RECT 1587.720000 2716.680000 1588.820000 2717.160000 ;
+ RECT 1587.720000 2722.120000 1588.820000 2722.600000 ;
+ RECT 1642.030000 2689.480000 1643.030000 2689.960000 ;
+ RECT 1642.030000 2694.920000 1643.030000 2695.400000 ;
+ RECT 1632.720000 2694.920000 1633.820000 2695.400000 ;
+ RECT 1632.720000 2689.480000 1633.820000 2689.960000 ;
+ RECT 1632.720000 2684.040000 1633.820000 2684.520000 ;
+ RECT 1632.720000 2678.600000 1633.820000 2679.080000 ;
+ RECT 1642.030000 2684.040000 1643.030000 2684.520000 ;
+ RECT 1642.030000 2678.600000 1643.030000 2679.080000 ;
+ RECT 1642.030000 2662.280000 1643.030000 2662.760000 ;
+ RECT 1642.030000 2667.720000 1643.030000 2668.200000 ;
+ RECT 1642.030000 2673.160000 1643.030000 2673.640000 ;
+ RECT 1632.720000 2662.280000 1633.820000 2662.760000 ;
+ RECT 1632.720000 2667.720000 1633.820000 2668.200000 ;
+ RECT 1632.720000 2673.160000 1633.820000 2673.640000 ;
+ RECT 1632.720000 2651.400000 1633.820000 2651.880000 ;
+ RECT 1632.720000 2656.840000 1633.820000 2657.320000 ;
+ RECT 1642.030000 2656.840000 1643.030000 2657.320000 ;
+ RECT 1642.030000 2651.400000 1643.030000 2651.880000 ;
+ RECT 1587.720000 2694.920000 1588.820000 2695.400000 ;
+ RECT 1587.720000 2689.480000 1588.820000 2689.960000 ;
+ RECT 1587.720000 2684.040000 1588.820000 2684.520000 ;
+ RECT 1587.720000 2678.600000 1588.820000 2679.080000 ;
+ RECT 1587.720000 2651.400000 1588.820000 2651.880000 ;
+ RECT 1587.720000 2656.840000 1588.820000 2657.320000 ;
+ RECT 1587.720000 2662.280000 1588.820000 2662.760000 ;
+ RECT 1587.720000 2667.720000 1588.820000 2668.200000 ;
+ RECT 1587.720000 2673.160000 1588.820000 2673.640000 ;
+ RECT 1632.720000 2645.960000 1633.820000 2646.440000 ;
+ RECT 1632.720000 2640.520000 1633.820000 2641.000000 ;
+ RECT 1642.030000 2645.960000 1643.030000 2646.440000 ;
+ RECT 1642.030000 2640.520000 1643.030000 2641.000000 ;
+ RECT 1642.030000 2624.200000 1643.030000 2624.680000 ;
+ RECT 1642.030000 2629.640000 1643.030000 2630.120000 ;
+ RECT 1642.030000 2635.080000 1643.030000 2635.560000 ;
+ RECT 1632.720000 2635.080000 1633.820000 2635.560000 ;
+ RECT 1632.720000 2629.640000 1633.820000 2630.120000 ;
+ RECT 1632.720000 2624.200000 1633.820000 2624.680000 ;
+ RECT 1632.720000 2613.320000 1633.820000 2613.800000 ;
+ RECT 1632.720000 2618.760000 1633.820000 2619.240000 ;
+ RECT 1642.030000 2618.760000 1643.030000 2619.240000 ;
+ RECT 1642.030000 2613.320000 1643.030000 2613.800000 ;
+ RECT 1642.030000 2602.440000 1643.030000 2602.920000 ;
+ RECT 1642.030000 2607.880000 1643.030000 2608.360000 ;
+ RECT 1632.720000 2602.440000 1633.820000 2602.920000 ;
+ RECT 1632.720000 2607.880000 1633.820000 2608.360000 ;
+ RECT 1587.720000 2645.960000 1588.820000 2646.440000 ;
+ RECT 1587.720000 2640.520000 1588.820000 2641.000000 ;
+ RECT 1587.720000 2635.080000 1588.820000 2635.560000 ;
+ RECT 1587.720000 2629.640000 1588.820000 2630.120000 ;
+ RECT 1587.720000 2624.200000 1588.820000 2624.680000 ;
+ RECT 1587.720000 2602.440000 1588.820000 2602.920000 ;
+ RECT 1587.720000 2607.880000 1588.820000 2608.360000 ;
+ RECT 1587.720000 2613.320000 1588.820000 2613.800000 ;
+ RECT 1587.720000 2618.760000 1588.820000 2619.240000 ;
+ RECT 1632.720000 2597.000000 1633.820000 2597.480000 ;
+ RECT 1632.720000 2591.560000 1633.820000 2592.040000 ;
+ RECT 1642.030000 2597.000000 1643.030000 2597.480000 ;
+ RECT 1642.030000 2591.560000 1643.030000 2592.040000 ;
+ RECT 1632.720000 2580.680000 1633.820000 2581.160000 ;
+ RECT 1632.720000 2575.240000 1633.820000 2575.720000 ;
+ RECT 1642.030000 2580.680000 1643.030000 2581.160000 ;
+ RECT 1642.030000 2575.240000 1643.030000 2575.720000 ;
+ RECT 1632.720000 2586.120000 1633.820000 2586.600000 ;
+ RECT 1642.030000 2586.120000 1643.030000 2586.600000 ;
+ RECT 1642.030000 2564.360000 1643.030000 2564.840000 ;
+ RECT 1642.030000 2569.800000 1643.030000 2570.280000 ;
+ RECT 1632.720000 2569.800000 1633.820000 2570.280000 ;
+ RECT 1632.720000 2564.360000 1633.820000 2564.840000 ;
+ RECT 1632.720000 2558.920000 1633.820000 2559.400000 ;
+ RECT 1632.720000 2553.480000 1633.820000 2553.960000 ;
+ RECT 1642.030000 2558.920000 1643.030000 2559.400000 ;
+ RECT 1642.030000 2553.480000 1643.030000 2553.960000 ;
+ RECT 1587.720000 2597.000000 1588.820000 2597.480000 ;
+ RECT 1587.720000 2591.560000 1588.820000 2592.040000 ;
+ RECT 1587.720000 2586.120000 1588.820000 2586.600000 ;
+ RECT 1587.720000 2580.680000 1588.820000 2581.160000 ;
+ RECT 1587.720000 2575.240000 1588.820000 2575.720000 ;
+ RECT 1587.720000 2569.800000 1588.820000 2570.280000 ;
+ RECT 1587.720000 2564.360000 1588.820000 2564.840000 ;
+ RECT 1587.720000 2558.920000 1588.820000 2559.400000 ;
+ RECT 1587.720000 2553.480000 1588.820000 2553.960000 ;
+ RECT 1542.720000 2743.880000 1543.820000 2744.360000 ;
+ RECT 1542.720000 2738.440000 1543.820000 2738.920000 ;
+ RECT 1542.720000 2733.000000 1543.820000 2733.480000 ;
+ RECT 1542.720000 2727.560000 1543.820000 2728.040000 ;
+ RECT 1497.720000 2743.880000 1498.820000 2744.360000 ;
+ RECT 1497.720000 2738.440000 1498.820000 2738.920000 ;
+ RECT 1497.720000 2733.000000 1498.820000 2733.480000 ;
+ RECT 1497.720000 2727.560000 1498.820000 2728.040000 ;
+ RECT 1542.720000 2716.680000 1543.820000 2717.160000 ;
+ RECT 1542.720000 2711.240000 1543.820000 2711.720000 ;
+ RECT 1542.720000 2705.800000 1543.820000 2706.280000 ;
+ RECT 1542.720000 2700.360000 1543.820000 2700.840000 ;
+ RECT 1542.720000 2722.120000 1543.820000 2722.600000 ;
+ RECT 1497.720000 2711.240000 1498.820000 2711.720000 ;
+ RECT 1497.720000 2705.800000 1498.820000 2706.280000 ;
+ RECT 1497.720000 2700.360000 1498.820000 2700.840000 ;
+ RECT 1497.720000 2716.680000 1498.820000 2717.160000 ;
+ RECT 1497.720000 2722.120000 1498.820000 2722.600000 ;
+ RECT 1452.720000 2743.880000 1453.820000 2744.360000 ;
+ RECT 1448.590000 2743.880000 1449.590000 2744.360000 ;
+ RECT 1452.720000 2738.440000 1453.820000 2738.920000 ;
+ RECT 1448.590000 2738.440000 1449.590000 2738.920000 ;
+ RECT 1452.720000 2733.000000 1453.820000 2733.480000 ;
+ RECT 1448.590000 2733.000000 1449.590000 2733.480000 ;
+ RECT 1452.720000 2727.560000 1453.820000 2728.040000 ;
+ RECT 1448.590000 2727.560000 1449.590000 2728.040000 ;
+ RECT 1452.720000 2722.120000 1453.820000 2722.600000 ;
+ RECT 1448.590000 2722.120000 1449.590000 2722.600000 ;
+ RECT 1452.720000 2716.680000 1453.820000 2717.160000 ;
+ RECT 1448.590000 2716.680000 1449.590000 2717.160000 ;
+ RECT 1452.720000 2705.800000 1453.820000 2706.280000 ;
+ RECT 1448.590000 2705.800000 1449.590000 2706.280000 ;
+ RECT 1452.720000 2700.360000 1453.820000 2700.840000 ;
+ RECT 1448.590000 2700.360000 1449.590000 2700.840000 ;
+ RECT 1452.720000 2711.240000 1453.820000 2711.720000 ;
+ RECT 1448.590000 2711.240000 1449.590000 2711.720000 ;
+ RECT 1542.720000 2694.920000 1543.820000 2695.400000 ;
+ RECT 1542.720000 2689.480000 1543.820000 2689.960000 ;
+ RECT 1542.720000 2684.040000 1543.820000 2684.520000 ;
+ RECT 1542.720000 2678.600000 1543.820000 2679.080000 ;
+ RECT 1497.720000 2694.920000 1498.820000 2695.400000 ;
+ RECT 1497.720000 2689.480000 1498.820000 2689.960000 ;
+ RECT 1497.720000 2684.040000 1498.820000 2684.520000 ;
+ RECT 1497.720000 2678.600000 1498.820000 2679.080000 ;
+ RECT 1542.720000 2667.720000 1543.820000 2668.200000 ;
+ RECT 1542.720000 2662.280000 1543.820000 2662.760000 ;
+ RECT 1542.720000 2656.840000 1543.820000 2657.320000 ;
+ RECT 1542.720000 2651.400000 1543.820000 2651.880000 ;
+ RECT 1542.720000 2673.160000 1543.820000 2673.640000 ;
+ RECT 1497.720000 2662.280000 1498.820000 2662.760000 ;
+ RECT 1497.720000 2656.840000 1498.820000 2657.320000 ;
+ RECT 1497.720000 2651.400000 1498.820000 2651.880000 ;
+ RECT 1497.720000 2667.720000 1498.820000 2668.200000 ;
+ RECT 1497.720000 2673.160000 1498.820000 2673.640000 ;
+ RECT 1452.720000 2694.920000 1453.820000 2695.400000 ;
+ RECT 1448.590000 2694.920000 1449.590000 2695.400000 ;
+ RECT 1452.720000 2689.480000 1453.820000 2689.960000 ;
+ RECT 1448.590000 2689.480000 1449.590000 2689.960000 ;
+ RECT 1452.720000 2684.040000 1453.820000 2684.520000 ;
+ RECT 1448.590000 2684.040000 1449.590000 2684.520000 ;
+ RECT 1452.720000 2678.600000 1453.820000 2679.080000 ;
+ RECT 1448.590000 2678.600000 1449.590000 2679.080000 ;
+ RECT 1452.720000 2673.160000 1453.820000 2673.640000 ;
+ RECT 1452.720000 2667.720000 1453.820000 2668.200000 ;
+ RECT 1448.590000 2673.160000 1449.590000 2673.640000 ;
+ RECT 1448.590000 2667.720000 1449.590000 2668.200000 ;
+ RECT 1452.720000 2662.280000 1453.820000 2662.760000 ;
+ RECT 1448.590000 2662.280000 1449.590000 2662.760000 ;
+ RECT 1452.720000 2656.840000 1453.820000 2657.320000 ;
+ RECT 1448.590000 2656.840000 1449.590000 2657.320000 ;
+ RECT 1452.720000 2651.400000 1453.820000 2651.880000 ;
+ RECT 1448.590000 2651.400000 1449.590000 2651.880000 ;
+ RECT 1542.720000 2645.960000 1543.820000 2646.440000 ;
+ RECT 1542.720000 2640.520000 1543.820000 2641.000000 ;
+ RECT 1542.720000 2635.080000 1543.820000 2635.560000 ;
+ RECT 1542.720000 2629.640000 1543.820000 2630.120000 ;
+ RECT 1542.720000 2624.200000 1543.820000 2624.680000 ;
+ RECT 1497.720000 2645.960000 1498.820000 2646.440000 ;
+ RECT 1497.720000 2640.520000 1498.820000 2641.000000 ;
+ RECT 1497.720000 2635.080000 1498.820000 2635.560000 ;
+ RECT 1497.720000 2629.640000 1498.820000 2630.120000 ;
+ RECT 1497.720000 2624.200000 1498.820000 2624.680000 ;
+ RECT 1542.720000 2618.760000 1543.820000 2619.240000 ;
+ RECT 1542.720000 2613.320000 1543.820000 2613.800000 ;
+ RECT 1542.720000 2607.880000 1543.820000 2608.360000 ;
+ RECT 1542.720000 2602.440000 1543.820000 2602.920000 ;
+ RECT 1497.720000 2613.320000 1498.820000 2613.800000 ;
+ RECT 1497.720000 2607.880000 1498.820000 2608.360000 ;
+ RECT 1497.720000 2602.440000 1498.820000 2602.920000 ;
+ RECT 1497.720000 2618.760000 1498.820000 2619.240000 ;
+ RECT 1452.720000 2645.960000 1453.820000 2646.440000 ;
+ RECT 1448.590000 2645.960000 1449.590000 2646.440000 ;
+ RECT 1452.720000 2640.520000 1453.820000 2641.000000 ;
+ RECT 1448.590000 2640.520000 1449.590000 2641.000000 ;
+ RECT 1452.720000 2635.080000 1453.820000 2635.560000 ;
+ RECT 1448.590000 2635.080000 1449.590000 2635.560000 ;
+ RECT 1452.720000 2624.200000 1453.820000 2624.680000 ;
+ RECT 1448.590000 2624.200000 1449.590000 2624.680000 ;
+ RECT 1448.590000 2629.640000 1449.590000 2630.120000 ;
+ RECT 1452.720000 2629.640000 1453.820000 2630.120000 ;
+ RECT 1452.720000 2618.760000 1453.820000 2619.240000 ;
+ RECT 1448.590000 2618.760000 1449.590000 2619.240000 ;
+ RECT 1452.720000 2613.320000 1453.820000 2613.800000 ;
+ RECT 1448.590000 2613.320000 1449.590000 2613.800000 ;
+ RECT 1452.720000 2607.880000 1453.820000 2608.360000 ;
+ RECT 1448.590000 2607.880000 1449.590000 2608.360000 ;
+ RECT 1452.720000 2602.440000 1453.820000 2602.920000 ;
+ RECT 1448.590000 2602.440000 1449.590000 2602.920000 ;
+ RECT 1542.720000 2597.000000 1543.820000 2597.480000 ;
+ RECT 1542.720000 2591.560000 1543.820000 2592.040000 ;
+ RECT 1542.720000 2586.120000 1543.820000 2586.600000 ;
+ RECT 1542.720000 2580.680000 1543.820000 2581.160000 ;
+ RECT 1542.720000 2575.240000 1543.820000 2575.720000 ;
+ RECT 1497.720000 2597.000000 1498.820000 2597.480000 ;
+ RECT 1497.720000 2591.560000 1498.820000 2592.040000 ;
+ RECT 1497.720000 2586.120000 1498.820000 2586.600000 ;
+ RECT 1497.720000 2580.680000 1498.820000 2581.160000 ;
+ RECT 1497.720000 2575.240000 1498.820000 2575.720000 ;
+ RECT 1542.720000 2553.480000 1543.820000 2553.960000 ;
+ RECT 1542.720000 2558.920000 1543.820000 2559.400000 ;
+ RECT 1542.720000 2564.360000 1543.820000 2564.840000 ;
+ RECT 1542.720000 2569.800000 1543.820000 2570.280000 ;
+ RECT 1497.720000 2553.480000 1498.820000 2553.960000 ;
+ RECT 1497.720000 2558.920000 1498.820000 2559.400000 ;
+ RECT 1497.720000 2564.360000 1498.820000 2564.840000 ;
+ RECT 1497.720000 2569.800000 1498.820000 2570.280000 ;
+ RECT 1452.720000 2597.000000 1453.820000 2597.480000 ;
+ RECT 1448.590000 2597.000000 1449.590000 2597.480000 ;
+ RECT 1452.720000 2591.560000 1453.820000 2592.040000 ;
+ RECT 1448.590000 2591.560000 1449.590000 2592.040000 ;
+ RECT 1452.720000 2580.680000 1453.820000 2581.160000 ;
+ RECT 1448.590000 2580.680000 1449.590000 2581.160000 ;
+ RECT 1452.720000 2575.240000 1453.820000 2575.720000 ;
+ RECT 1448.590000 2575.240000 1449.590000 2575.720000 ;
+ RECT 1452.720000 2586.120000 1453.820000 2586.600000 ;
+ RECT 1448.590000 2586.120000 1449.590000 2586.600000 ;
+ RECT 1452.720000 2569.800000 1453.820000 2570.280000 ;
+ RECT 1448.590000 2569.800000 1449.590000 2570.280000 ;
+ RECT 1452.720000 2564.360000 1453.820000 2564.840000 ;
+ RECT 1448.590000 2564.360000 1449.590000 2564.840000 ;
+ RECT 1452.720000 2558.920000 1453.820000 2559.400000 ;
+ RECT 1452.720000 2553.480000 1453.820000 2553.960000 ;
+ RECT 1448.590000 2558.920000 1449.590000 2559.400000 ;
+ RECT 1448.590000 2553.480000 1449.590000 2553.960000 ;
+ RECT 1445.760000 2944.610000 1645.860000 2945.610000 ;
+ RECT 1445.760000 2551.470000 1645.860000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 2548.620000 1449.590000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 2948.140000 1449.590000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 2548.620000 1643.030000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 2948.140000 1643.030000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2551.470000 1446.760000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2551.470000 1645.860000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2944.610000 1446.760000 2945.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2944.610000 1645.860000 2945.610000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 2148.100000 1449.590000 2548.620000 ;
+ RECT 1642.030000 2148.100000 1643.030000 2548.620000 ;
+ RECT 1452.720000 2150.950000 1453.820000 2545.090000 ;
+ RECT 1497.720000 2150.950000 1498.820000 2545.090000 ;
+ RECT 1542.720000 2150.950000 1543.820000 2545.090000 ;
+ RECT 1587.720000 2150.950000 1588.820000 2545.090000 ;
+ RECT 1632.720000 2150.950000 1633.820000 2545.090000 ;
+ LAYER met3 ;
+ RECT 1632.720000 2539.200000 1633.820000 2539.680000 ;
+ RECT 1642.030000 2539.200000 1643.030000 2539.680000 ;
+ RECT 1642.030000 2533.760000 1643.030000 2534.240000 ;
+ RECT 1632.720000 2533.760000 1633.820000 2534.240000 ;
+ RECT 1632.720000 2528.320000 1633.820000 2528.800000 ;
+ RECT 1642.030000 2528.320000 1643.030000 2528.800000 ;
+ RECT 1642.030000 2512.000000 1643.030000 2512.480000 ;
+ RECT 1642.030000 2517.440000 1643.030000 2517.920000 ;
+ RECT 1642.030000 2522.880000 1643.030000 2523.360000 ;
+ RECT 1632.720000 2522.880000 1633.820000 2523.360000 ;
+ RECT 1632.720000 2512.000000 1633.820000 2512.480000 ;
+ RECT 1632.720000 2517.440000 1633.820000 2517.920000 ;
+ RECT 1632.720000 2501.120000 1633.820000 2501.600000 ;
+ RECT 1632.720000 2506.560000 1633.820000 2507.040000 ;
+ RECT 1642.030000 2506.560000 1643.030000 2507.040000 ;
+ RECT 1642.030000 2501.120000 1643.030000 2501.600000 ;
+ RECT 1587.720000 2539.200000 1588.820000 2539.680000 ;
+ RECT 1587.720000 2533.760000 1588.820000 2534.240000 ;
+ RECT 1587.720000 2528.320000 1588.820000 2528.800000 ;
+ RECT 1587.720000 2522.880000 1588.820000 2523.360000 ;
+ RECT 1587.720000 2501.120000 1588.820000 2501.600000 ;
+ RECT 1587.720000 2506.560000 1588.820000 2507.040000 ;
+ RECT 1587.720000 2512.000000 1588.820000 2512.480000 ;
+ RECT 1587.720000 2517.440000 1588.820000 2517.920000 ;
+ RECT 1632.720000 2495.680000 1633.820000 2496.160000 ;
+ RECT 1632.720000 2490.240000 1633.820000 2490.720000 ;
+ RECT 1642.030000 2495.680000 1643.030000 2496.160000 ;
+ RECT 1642.030000 2490.240000 1643.030000 2490.720000 ;
+ RECT 1642.030000 2473.920000 1643.030000 2474.400000 ;
+ RECT 1642.030000 2479.360000 1643.030000 2479.840000 ;
+ RECT 1642.030000 2484.800000 1643.030000 2485.280000 ;
+ RECT 1632.720000 2484.800000 1633.820000 2485.280000 ;
+ RECT 1632.720000 2479.360000 1633.820000 2479.840000 ;
+ RECT 1632.720000 2473.920000 1633.820000 2474.400000 ;
+ RECT 1632.720000 2463.040000 1633.820000 2463.520000 ;
+ RECT 1632.720000 2468.480000 1633.820000 2468.960000 ;
+ RECT 1642.030000 2468.480000 1643.030000 2468.960000 ;
+ RECT 1642.030000 2463.040000 1643.030000 2463.520000 ;
+ RECT 1642.030000 2452.160000 1643.030000 2452.640000 ;
+ RECT 1642.030000 2457.600000 1643.030000 2458.080000 ;
+ RECT 1632.720000 2452.160000 1633.820000 2452.640000 ;
+ RECT 1632.720000 2457.600000 1633.820000 2458.080000 ;
+ RECT 1587.720000 2495.680000 1588.820000 2496.160000 ;
+ RECT 1587.720000 2490.240000 1588.820000 2490.720000 ;
+ RECT 1587.720000 2484.800000 1588.820000 2485.280000 ;
+ RECT 1587.720000 2479.360000 1588.820000 2479.840000 ;
+ RECT 1587.720000 2473.920000 1588.820000 2474.400000 ;
+ RECT 1587.720000 2452.160000 1588.820000 2452.640000 ;
+ RECT 1587.720000 2457.600000 1588.820000 2458.080000 ;
+ RECT 1587.720000 2463.040000 1588.820000 2463.520000 ;
+ RECT 1587.720000 2468.480000 1588.820000 2468.960000 ;
+ RECT 1632.720000 2446.720000 1633.820000 2447.200000 ;
+ RECT 1632.720000 2441.280000 1633.820000 2441.760000 ;
+ RECT 1642.030000 2446.720000 1643.030000 2447.200000 ;
+ RECT 1642.030000 2441.280000 1643.030000 2441.760000 ;
+ RECT 1632.720000 2430.400000 1633.820000 2430.880000 ;
+ RECT 1632.720000 2424.960000 1633.820000 2425.440000 ;
+ RECT 1642.030000 2430.400000 1643.030000 2430.880000 ;
+ RECT 1642.030000 2424.960000 1643.030000 2425.440000 ;
+ RECT 1632.720000 2435.840000 1633.820000 2436.320000 ;
+ RECT 1642.030000 2435.840000 1643.030000 2436.320000 ;
+ RECT 1642.030000 2414.080000 1643.030000 2414.560000 ;
+ RECT 1642.030000 2419.520000 1643.030000 2420.000000 ;
+ RECT 1632.720000 2414.080000 1633.820000 2414.560000 ;
+ RECT 1632.720000 2419.520000 1633.820000 2420.000000 ;
+ RECT 1632.720000 2403.200000 1633.820000 2403.680000 ;
+ RECT 1632.720000 2408.640000 1633.820000 2409.120000 ;
+ RECT 1642.030000 2408.640000 1643.030000 2409.120000 ;
+ RECT 1642.030000 2403.200000 1643.030000 2403.680000 ;
+ RECT 1587.720000 2446.720000 1588.820000 2447.200000 ;
+ RECT 1587.720000 2441.280000 1588.820000 2441.760000 ;
+ RECT 1587.720000 2435.840000 1588.820000 2436.320000 ;
+ RECT 1587.720000 2430.400000 1588.820000 2430.880000 ;
+ RECT 1587.720000 2424.960000 1588.820000 2425.440000 ;
+ RECT 1587.720000 2403.200000 1588.820000 2403.680000 ;
+ RECT 1587.720000 2408.640000 1588.820000 2409.120000 ;
+ RECT 1587.720000 2414.080000 1588.820000 2414.560000 ;
+ RECT 1587.720000 2419.520000 1588.820000 2420.000000 ;
+ RECT 1642.030000 2386.880000 1643.030000 2387.360000 ;
+ RECT 1642.030000 2392.320000 1643.030000 2392.800000 ;
+ RECT 1642.030000 2397.760000 1643.030000 2398.240000 ;
+ RECT 1632.720000 2397.760000 1633.820000 2398.240000 ;
+ RECT 1632.720000 2392.320000 1633.820000 2392.800000 ;
+ RECT 1632.720000 2386.880000 1633.820000 2387.360000 ;
+ RECT 1632.720000 2381.440000 1633.820000 2381.920000 ;
+ RECT 1632.720000 2376.000000 1633.820000 2376.480000 ;
+ RECT 1642.030000 2381.440000 1643.030000 2381.920000 ;
+ RECT 1642.030000 2376.000000 1643.030000 2376.480000 ;
+ RECT 1632.720000 2365.120000 1633.820000 2365.600000 ;
+ RECT 1632.720000 2370.560000 1633.820000 2371.040000 ;
+ RECT 1642.030000 2370.560000 1643.030000 2371.040000 ;
+ RECT 1642.030000 2365.120000 1643.030000 2365.600000 ;
+ RECT 1642.030000 2348.800000 1643.030000 2349.280000 ;
+ RECT 1642.030000 2354.240000 1643.030000 2354.720000 ;
+ RECT 1642.030000 2359.680000 1643.030000 2360.160000 ;
+ RECT 1632.720000 2359.680000 1633.820000 2360.160000 ;
+ RECT 1632.720000 2354.240000 1633.820000 2354.720000 ;
+ RECT 1632.720000 2348.800000 1633.820000 2349.280000 ;
+ RECT 1587.720000 2397.760000 1588.820000 2398.240000 ;
+ RECT 1587.720000 2392.320000 1588.820000 2392.800000 ;
+ RECT 1587.720000 2386.880000 1588.820000 2387.360000 ;
+ RECT 1587.720000 2381.440000 1588.820000 2381.920000 ;
+ RECT 1587.720000 2376.000000 1588.820000 2376.480000 ;
+ RECT 1587.720000 2365.120000 1588.820000 2365.600000 ;
+ RECT 1587.720000 2359.680000 1588.820000 2360.160000 ;
+ RECT 1587.720000 2354.240000 1588.820000 2354.720000 ;
+ RECT 1587.720000 2348.800000 1588.820000 2349.280000 ;
+ RECT 1587.720000 2370.560000 1588.820000 2371.040000 ;
+ RECT 1542.720000 2539.200000 1543.820000 2539.680000 ;
+ RECT 1542.720000 2533.760000 1543.820000 2534.240000 ;
+ RECT 1542.720000 2528.320000 1543.820000 2528.800000 ;
+ RECT 1497.720000 2539.200000 1498.820000 2539.680000 ;
+ RECT 1497.720000 2533.760000 1498.820000 2534.240000 ;
+ RECT 1497.720000 2528.320000 1498.820000 2528.800000 ;
+ RECT 1542.720000 2512.000000 1543.820000 2512.480000 ;
+ RECT 1542.720000 2506.560000 1543.820000 2507.040000 ;
+ RECT 1542.720000 2501.120000 1543.820000 2501.600000 ;
+ RECT 1542.720000 2517.440000 1543.820000 2517.920000 ;
+ RECT 1542.720000 2522.880000 1543.820000 2523.360000 ;
+ RECT 1497.720000 2522.880000 1498.820000 2523.360000 ;
+ RECT 1497.720000 2512.000000 1498.820000 2512.480000 ;
+ RECT 1497.720000 2506.560000 1498.820000 2507.040000 ;
+ RECT 1497.720000 2501.120000 1498.820000 2501.600000 ;
+ RECT 1497.720000 2517.440000 1498.820000 2517.920000 ;
+ RECT 1452.720000 2539.200000 1453.820000 2539.680000 ;
+ RECT 1448.590000 2539.200000 1449.590000 2539.680000 ;
+ RECT 1448.590000 2533.760000 1449.590000 2534.240000 ;
+ RECT 1452.720000 2533.760000 1453.820000 2534.240000 ;
+ RECT 1452.720000 2528.320000 1453.820000 2528.800000 ;
+ RECT 1448.590000 2528.320000 1449.590000 2528.800000 ;
+ RECT 1452.720000 2522.880000 1453.820000 2523.360000 ;
+ RECT 1452.720000 2517.440000 1453.820000 2517.920000 ;
+ RECT 1448.590000 2522.880000 1449.590000 2523.360000 ;
+ RECT 1448.590000 2517.440000 1449.590000 2517.920000 ;
+ RECT 1452.720000 2512.000000 1453.820000 2512.480000 ;
+ RECT 1448.590000 2512.000000 1449.590000 2512.480000 ;
+ RECT 1452.720000 2506.560000 1453.820000 2507.040000 ;
+ RECT 1448.590000 2506.560000 1449.590000 2507.040000 ;
+ RECT 1452.720000 2501.120000 1453.820000 2501.600000 ;
+ RECT 1448.590000 2501.120000 1449.590000 2501.600000 ;
+ RECT 1542.720000 2495.680000 1543.820000 2496.160000 ;
+ RECT 1542.720000 2490.240000 1543.820000 2490.720000 ;
+ RECT 1542.720000 2484.800000 1543.820000 2485.280000 ;
+ RECT 1542.720000 2479.360000 1543.820000 2479.840000 ;
+ RECT 1542.720000 2473.920000 1543.820000 2474.400000 ;
+ RECT 1497.720000 2495.680000 1498.820000 2496.160000 ;
+ RECT 1497.720000 2490.240000 1498.820000 2490.720000 ;
+ RECT 1497.720000 2484.800000 1498.820000 2485.280000 ;
+ RECT 1497.720000 2479.360000 1498.820000 2479.840000 ;
+ RECT 1497.720000 2473.920000 1498.820000 2474.400000 ;
+ RECT 1542.720000 2468.480000 1543.820000 2468.960000 ;
+ RECT 1542.720000 2463.040000 1543.820000 2463.520000 ;
+ RECT 1542.720000 2457.600000 1543.820000 2458.080000 ;
+ RECT 1542.720000 2452.160000 1543.820000 2452.640000 ;
+ RECT 1497.720000 2463.040000 1498.820000 2463.520000 ;
+ RECT 1497.720000 2457.600000 1498.820000 2458.080000 ;
+ RECT 1497.720000 2452.160000 1498.820000 2452.640000 ;
+ RECT 1497.720000 2468.480000 1498.820000 2468.960000 ;
+ RECT 1452.720000 2495.680000 1453.820000 2496.160000 ;
+ RECT 1448.590000 2495.680000 1449.590000 2496.160000 ;
+ RECT 1452.720000 2490.240000 1453.820000 2490.720000 ;
+ RECT 1448.590000 2490.240000 1449.590000 2490.720000 ;
+ RECT 1452.720000 2484.800000 1453.820000 2485.280000 ;
+ RECT 1448.590000 2484.800000 1449.590000 2485.280000 ;
+ RECT 1452.720000 2473.920000 1453.820000 2474.400000 ;
+ RECT 1448.590000 2473.920000 1449.590000 2474.400000 ;
+ RECT 1448.590000 2479.360000 1449.590000 2479.840000 ;
+ RECT 1452.720000 2479.360000 1453.820000 2479.840000 ;
+ RECT 1452.720000 2468.480000 1453.820000 2468.960000 ;
+ RECT 1448.590000 2468.480000 1449.590000 2468.960000 ;
+ RECT 1452.720000 2463.040000 1453.820000 2463.520000 ;
+ RECT 1448.590000 2463.040000 1449.590000 2463.520000 ;
+ RECT 1452.720000 2457.600000 1453.820000 2458.080000 ;
+ RECT 1448.590000 2457.600000 1449.590000 2458.080000 ;
+ RECT 1452.720000 2452.160000 1453.820000 2452.640000 ;
+ RECT 1448.590000 2452.160000 1449.590000 2452.640000 ;
+ RECT 1542.720000 2446.720000 1543.820000 2447.200000 ;
+ RECT 1542.720000 2441.280000 1543.820000 2441.760000 ;
+ RECT 1542.720000 2435.840000 1543.820000 2436.320000 ;
+ RECT 1542.720000 2430.400000 1543.820000 2430.880000 ;
+ RECT 1542.720000 2424.960000 1543.820000 2425.440000 ;
+ RECT 1497.720000 2446.720000 1498.820000 2447.200000 ;
+ RECT 1497.720000 2441.280000 1498.820000 2441.760000 ;
+ RECT 1497.720000 2435.840000 1498.820000 2436.320000 ;
+ RECT 1497.720000 2430.400000 1498.820000 2430.880000 ;
+ RECT 1497.720000 2424.960000 1498.820000 2425.440000 ;
+ RECT 1542.720000 2419.520000 1543.820000 2420.000000 ;
+ RECT 1542.720000 2414.080000 1543.820000 2414.560000 ;
+ RECT 1542.720000 2408.640000 1543.820000 2409.120000 ;
+ RECT 1542.720000 2403.200000 1543.820000 2403.680000 ;
+ RECT 1497.720000 2414.080000 1498.820000 2414.560000 ;
+ RECT 1497.720000 2408.640000 1498.820000 2409.120000 ;
+ RECT 1497.720000 2403.200000 1498.820000 2403.680000 ;
+ RECT 1497.720000 2419.520000 1498.820000 2420.000000 ;
+ RECT 1452.720000 2446.720000 1453.820000 2447.200000 ;
+ RECT 1448.590000 2446.720000 1449.590000 2447.200000 ;
+ RECT 1452.720000 2441.280000 1453.820000 2441.760000 ;
+ RECT 1448.590000 2441.280000 1449.590000 2441.760000 ;
+ RECT 1452.720000 2430.400000 1453.820000 2430.880000 ;
+ RECT 1448.590000 2430.400000 1449.590000 2430.880000 ;
+ RECT 1452.720000 2424.960000 1453.820000 2425.440000 ;
+ RECT 1448.590000 2424.960000 1449.590000 2425.440000 ;
+ RECT 1452.720000 2435.840000 1453.820000 2436.320000 ;
+ RECT 1448.590000 2435.840000 1449.590000 2436.320000 ;
+ RECT 1452.720000 2419.520000 1453.820000 2420.000000 ;
+ RECT 1448.590000 2419.520000 1449.590000 2420.000000 ;
+ RECT 1452.720000 2414.080000 1453.820000 2414.560000 ;
+ RECT 1448.590000 2414.080000 1449.590000 2414.560000 ;
+ RECT 1452.720000 2408.640000 1453.820000 2409.120000 ;
+ RECT 1448.590000 2408.640000 1449.590000 2409.120000 ;
+ RECT 1452.720000 2403.200000 1453.820000 2403.680000 ;
+ RECT 1448.590000 2403.200000 1449.590000 2403.680000 ;
+ RECT 1542.720000 2397.760000 1543.820000 2398.240000 ;
+ RECT 1542.720000 2392.320000 1543.820000 2392.800000 ;
+ RECT 1542.720000 2386.880000 1543.820000 2387.360000 ;
+ RECT 1542.720000 2381.440000 1543.820000 2381.920000 ;
+ RECT 1542.720000 2376.000000 1543.820000 2376.480000 ;
+ RECT 1497.720000 2397.760000 1498.820000 2398.240000 ;
+ RECT 1497.720000 2392.320000 1498.820000 2392.800000 ;
+ RECT 1497.720000 2386.880000 1498.820000 2387.360000 ;
+ RECT 1497.720000 2381.440000 1498.820000 2381.920000 ;
+ RECT 1497.720000 2376.000000 1498.820000 2376.480000 ;
+ RECT 1542.720000 2365.120000 1543.820000 2365.600000 ;
+ RECT 1542.720000 2348.800000 1543.820000 2349.280000 ;
+ RECT 1542.720000 2354.240000 1543.820000 2354.720000 ;
+ RECT 1542.720000 2359.680000 1543.820000 2360.160000 ;
+ RECT 1542.720000 2370.560000 1543.820000 2371.040000 ;
+ RECT 1497.720000 2348.800000 1498.820000 2349.280000 ;
+ RECT 1497.720000 2354.240000 1498.820000 2354.720000 ;
+ RECT 1497.720000 2359.680000 1498.820000 2360.160000 ;
+ RECT 1497.720000 2365.120000 1498.820000 2365.600000 ;
+ RECT 1497.720000 2370.560000 1498.820000 2371.040000 ;
+ RECT 1452.720000 2397.760000 1453.820000 2398.240000 ;
+ RECT 1452.720000 2392.320000 1453.820000 2392.800000 ;
+ RECT 1448.590000 2397.760000 1449.590000 2398.240000 ;
+ RECT 1448.590000 2392.320000 1449.590000 2392.800000 ;
+ RECT 1452.720000 2386.880000 1453.820000 2387.360000 ;
+ RECT 1448.590000 2386.880000 1449.590000 2387.360000 ;
+ RECT 1452.720000 2381.440000 1453.820000 2381.920000 ;
+ RECT 1448.590000 2381.440000 1449.590000 2381.920000 ;
+ RECT 1452.720000 2376.000000 1453.820000 2376.480000 ;
+ RECT 1448.590000 2376.000000 1449.590000 2376.480000 ;
+ RECT 1452.720000 2370.560000 1453.820000 2371.040000 ;
+ RECT 1448.590000 2370.560000 1449.590000 2371.040000 ;
+ RECT 1452.720000 2365.120000 1453.820000 2365.600000 ;
+ RECT 1448.590000 2365.120000 1449.590000 2365.600000 ;
+ RECT 1452.720000 2359.680000 1453.820000 2360.160000 ;
+ RECT 1448.590000 2359.680000 1449.590000 2360.160000 ;
+ RECT 1452.720000 2348.800000 1453.820000 2349.280000 ;
+ RECT 1448.590000 2348.800000 1449.590000 2349.280000 ;
+ RECT 1448.590000 2354.240000 1449.590000 2354.720000 ;
+ RECT 1452.720000 2354.240000 1453.820000 2354.720000 ;
+ RECT 1632.720000 2343.360000 1633.820000 2343.840000 ;
+ RECT 1632.720000 2337.920000 1633.820000 2338.400000 ;
+ RECT 1642.030000 2343.360000 1643.030000 2343.840000 ;
+ RECT 1642.030000 2337.920000 1643.030000 2338.400000 ;
+ RECT 1642.030000 2327.040000 1643.030000 2327.520000 ;
+ RECT 1642.030000 2332.480000 1643.030000 2332.960000 ;
+ RECT 1632.720000 2332.480000 1633.820000 2332.960000 ;
+ RECT 1632.720000 2327.040000 1633.820000 2327.520000 ;
+ RECT 1632.720000 2316.160000 1633.820000 2316.640000 ;
+ RECT 1632.720000 2321.600000 1633.820000 2322.080000 ;
+ RECT 1642.030000 2321.600000 1643.030000 2322.080000 ;
+ RECT 1642.030000 2316.160000 1643.030000 2316.640000 ;
+ RECT 1632.720000 2299.840000 1633.820000 2300.320000 ;
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+ RECT 1642.030000 2305.280000 1643.030000 2305.760000 ;
+ RECT 1642.030000 2299.840000 1643.030000 2300.320000 ;
+ RECT 1632.720000 2310.720000 1633.820000 2311.200000 ;
+ RECT 1642.030000 2310.720000 1643.030000 2311.200000 ;
+ RECT 1587.720000 2343.360000 1588.820000 2343.840000 ;
+ RECT 1587.720000 2337.920000 1588.820000 2338.400000 ;
+ RECT 1587.720000 2332.480000 1588.820000 2332.960000 ;
+ RECT 1587.720000 2327.040000 1588.820000 2327.520000 ;
+ RECT 1587.720000 2299.840000 1588.820000 2300.320000 ;
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+ RECT 1587.720000 2310.720000 1588.820000 2311.200000 ;
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+ RECT 1642.030000 2288.960000 1643.030000 2289.440000 ;
+ RECT 1642.030000 2294.400000 1643.030000 2294.880000 ;
+ RECT 1632.720000 2294.400000 1633.820000 2294.880000 ;
+ RECT 1632.720000 2288.960000 1633.820000 2289.440000 ;
+ RECT 1632.720000 2283.520000 1633.820000 2284.000000 ;
+ RECT 1632.720000 2278.080000 1633.820000 2278.560000 ;
+ RECT 1642.030000 2283.520000 1643.030000 2284.000000 ;
+ RECT 1642.030000 2278.080000 1643.030000 2278.560000 ;
+ RECT 1642.030000 2261.760000 1643.030000 2262.240000 ;
+ RECT 1642.030000 2267.200000 1643.030000 2267.680000 ;
+ RECT 1642.030000 2272.640000 1643.030000 2273.120000 ;
+ RECT 1632.720000 2261.760000 1633.820000 2262.240000 ;
+ RECT 1632.720000 2267.200000 1633.820000 2267.680000 ;
+ RECT 1632.720000 2272.640000 1633.820000 2273.120000 ;
+ RECT 1632.720000 2250.880000 1633.820000 2251.360000 ;
+ RECT 1632.720000 2256.320000 1633.820000 2256.800000 ;
+ RECT 1642.030000 2256.320000 1643.030000 2256.800000 ;
+ RECT 1642.030000 2250.880000 1643.030000 2251.360000 ;
+ RECT 1587.720000 2294.400000 1588.820000 2294.880000 ;
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+ RECT 1587.720000 2283.520000 1588.820000 2284.000000 ;
+ RECT 1587.720000 2278.080000 1588.820000 2278.560000 ;
+ RECT 1587.720000 2250.880000 1588.820000 2251.360000 ;
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+ RECT 1587.720000 2261.760000 1588.820000 2262.240000 ;
+ RECT 1587.720000 2267.200000 1588.820000 2267.680000 ;
+ RECT 1587.720000 2272.640000 1588.820000 2273.120000 ;
+ RECT 1632.720000 2245.440000 1633.820000 2245.920000 ;
+ RECT 1632.720000 2240.000000 1633.820000 2240.480000 ;
+ RECT 1642.030000 2245.440000 1643.030000 2245.920000 ;
+ RECT 1642.030000 2240.000000 1643.030000 2240.480000 ;
+ RECT 1642.030000 2223.680000 1643.030000 2224.160000 ;
+ RECT 1642.030000 2229.120000 1643.030000 2229.600000 ;
+ RECT 1642.030000 2234.560000 1643.030000 2235.040000 ;
+ RECT 1632.720000 2234.560000 1633.820000 2235.040000 ;
+ RECT 1632.720000 2229.120000 1633.820000 2229.600000 ;
+ RECT 1632.720000 2223.680000 1633.820000 2224.160000 ;
+ RECT 1632.720000 2212.800000 1633.820000 2213.280000 ;
+ RECT 1632.720000 2218.240000 1633.820000 2218.720000 ;
+ RECT 1642.030000 2218.240000 1643.030000 2218.720000 ;
+ RECT 1642.030000 2212.800000 1643.030000 2213.280000 ;
+ RECT 1642.030000 2201.920000 1643.030000 2202.400000 ;
+ RECT 1642.030000 2207.360000 1643.030000 2207.840000 ;
+ RECT 1632.720000 2201.920000 1633.820000 2202.400000 ;
+ RECT 1632.720000 2207.360000 1633.820000 2207.840000 ;
+ RECT 1587.720000 2245.440000 1588.820000 2245.920000 ;
+ RECT 1587.720000 2240.000000 1588.820000 2240.480000 ;
+ RECT 1587.720000 2234.560000 1588.820000 2235.040000 ;
+ RECT 1587.720000 2229.120000 1588.820000 2229.600000 ;
+ RECT 1587.720000 2223.680000 1588.820000 2224.160000 ;
+ RECT 1587.720000 2201.920000 1588.820000 2202.400000 ;
+ RECT 1587.720000 2207.360000 1588.820000 2207.840000 ;
+ RECT 1587.720000 2212.800000 1588.820000 2213.280000 ;
+ RECT 1587.720000 2218.240000 1588.820000 2218.720000 ;
+ RECT 1632.720000 2196.480000 1633.820000 2196.960000 ;
+ RECT 1632.720000 2191.040000 1633.820000 2191.520000 ;
+ RECT 1642.030000 2196.480000 1643.030000 2196.960000 ;
+ RECT 1642.030000 2191.040000 1643.030000 2191.520000 ;
+ RECT 1632.720000 2180.160000 1633.820000 2180.640000 ;
+ RECT 1632.720000 2174.720000 1633.820000 2175.200000 ;
+ RECT 1642.030000 2180.160000 1643.030000 2180.640000 ;
+ RECT 1642.030000 2174.720000 1643.030000 2175.200000 ;
+ RECT 1632.720000 2185.600000 1633.820000 2186.080000 ;
+ RECT 1642.030000 2185.600000 1643.030000 2186.080000 ;
+ RECT 1642.030000 2163.840000 1643.030000 2164.320000 ;
+ RECT 1642.030000 2169.280000 1643.030000 2169.760000 ;
+ RECT 1632.720000 2169.280000 1633.820000 2169.760000 ;
+ RECT 1632.720000 2163.840000 1633.820000 2164.320000 ;
+ RECT 1632.720000 2158.400000 1633.820000 2158.880000 ;
+ RECT 1632.720000 2152.960000 1633.820000 2153.440000 ;
+ RECT 1642.030000 2158.400000 1643.030000 2158.880000 ;
+ RECT 1642.030000 2152.960000 1643.030000 2153.440000 ;
+ RECT 1587.720000 2196.480000 1588.820000 2196.960000 ;
+ RECT 1587.720000 2191.040000 1588.820000 2191.520000 ;
+ RECT 1587.720000 2185.600000 1588.820000 2186.080000 ;
+ RECT 1587.720000 2180.160000 1588.820000 2180.640000 ;
+ RECT 1587.720000 2174.720000 1588.820000 2175.200000 ;
+ RECT 1587.720000 2169.280000 1588.820000 2169.760000 ;
+ RECT 1587.720000 2163.840000 1588.820000 2164.320000 ;
+ RECT 1587.720000 2158.400000 1588.820000 2158.880000 ;
+ RECT 1587.720000 2152.960000 1588.820000 2153.440000 ;
+ RECT 1542.720000 2343.360000 1543.820000 2343.840000 ;
+ RECT 1542.720000 2337.920000 1543.820000 2338.400000 ;
+ RECT 1542.720000 2332.480000 1543.820000 2332.960000 ;
+ RECT 1542.720000 2327.040000 1543.820000 2327.520000 ;
+ RECT 1497.720000 2343.360000 1498.820000 2343.840000 ;
+ RECT 1497.720000 2337.920000 1498.820000 2338.400000 ;
+ RECT 1497.720000 2332.480000 1498.820000 2332.960000 ;
+ RECT 1497.720000 2327.040000 1498.820000 2327.520000 ;
+ RECT 1542.720000 2316.160000 1543.820000 2316.640000 ;
+ RECT 1542.720000 2310.720000 1543.820000 2311.200000 ;
+ RECT 1542.720000 2305.280000 1543.820000 2305.760000 ;
+ RECT 1542.720000 2299.840000 1543.820000 2300.320000 ;
+ RECT 1542.720000 2321.600000 1543.820000 2322.080000 ;
+ RECT 1497.720000 2310.720000 1498.820000 2311.200000 ;
+ RECT 1497.720000 2305.280000 1498.820000 2305.760000 ;
+ RECT 1497.720000 2299.840000 1498.820000 2300.320000 ;
+ RECT 1497.720000 2316.160000 1498.820000 2316.640000 ;
+ RECT 1497.720000 2321.600000 1498.820000 2322.080000 ;
+ RECT 1452.720000 2343.360000 1453.820000 2343.840000 ;
+ RECT 1448.590000 2343.360000 1449.590000 2343.840000 ;
+ RECT 1452.720000 2337.920000 1453.820000 2338.400000 ;
+ RECT 1448.590000 2337.920000 1449.590000 2338.400000 ;
+ RECT 1452.720000 2332.480000 1453.820000 2332.960000 ;
+ RECT 1448.590000 2332.480000 1449.590000 2332.960000 ;
+ RECT 1452.720000 2327.040000 1453.820000 2327.520000 ;
+ RECT 1448.590000 2327.040000 1449.590000 2327.520000 ;
+ RECT 1452.720000 2321.600000 1453.820000 2322.080000 ;
+ RECT 1448.590000 2321.600000 1449.590000 2322.080000 ;
+ RECT 1452.720000 2316.160000 1453.820000 2316.640000 ;
+ RECT 1448.590000 2316.160000 1449.590000 2316.640000 ;
+ RECT 1452.720000 2305.280000 1453.820000 2305.760000 ;
+ RECT 1448.590000 2305.280000 1449.590000 2305.760000 ;
+ RECT 1452.720000 2299.840000 1453.820000 2300.320000 ;
+ RECT 1448.590000 2299.840000 1449.590000 2300.320000 ;
+ RECT 1452.720000 2310.720000 1453.820000 2311.200000 ;
+ RECT 1448.590000 2310.720000 1449.590000 2311.200000 ;
+ RECT 1542.720000 2294.400000 1543.820000 2294.880000 ;
+ RECT 1542.720000 2288.960000 1543.820000 2289.440000 ;
+ RECT 1542.720000 2283.520000 1543.820000 2284.000000 ;
+ RECT 1542.720000 2278.080000 1543.820000 2278.560000 ;
+ RECT 1497.720000 2294.400000 1498.820000 2294.880000 ;
+ RECT 1497.720000 2288.960000 1498.820000 2289.440000 ;
+ RECT 1497.720000 2283.520000 1498.820000 2284.000000 ;
+ RECT 1497.720000 2278.080000 1498.820000 2278.560000 ;
+ RECT 1542.720000 2267.200000 1543.820000 2267.680000 ;
+ RECT 1542.720000 2261.760000 1543.820000 2262.240000 ;
+ RECT 1542.720000 2256.320000 1543.820000 2256.800000 ;
+ RECT 1542.720000 2250.880000 1543.820000 2251.360000 ;
+ RECT 1542.720000 2272.640000 1543.820000 2273.120000 ;
+ RECT 1497.720000 2261.760000 1498.820000 2262.240000 ;
+ RECT 1497.720000 2256.320000 1498.820000 2256.800000 ;
+ RECT 1497.720000 2250.880000 1498.820000 2251.360000 ;
+ RECT 1497.720000 2267.200000 1498.820000 2267.680000 ;
+ RECT 1497.720000 2272.640000 1498.820000 2273.120000 ;
+ RECT 1452.720000 2294.400000 1453.820000 2294.880000 ;
+ RECT 1448.590000 2294.400000 1449.590000 2294.880000 ;
+ RECT 1452.720000 2288.960000 1453.820000 2289.440000 ;
+ RECT 1448.590000 2288.960000 1449.590000 2289.440000 ;
+ RECT 1452.720000 2283.520000 1453.820000 2284.000000 ;
+ RECT 1448.590000 2283.520000 1449.590000 2284.000000 ;
+ RECT 1452.720000 2278.080000 1453.820000 2278.560000 ;
+ RECT 1448.590000 2278.080000 1449.590000 2278.560000 ;
+ RECT 1452.720000 2272.640000 1453.820000 2273.120000 ;
+ RECT 1452.720000 2267.200000 1453.820000 2267.680000 ;
+ RECT 1448.590000 2272.640000 1449.590000 2273.120000 ;
+ RECT 1448.590000 2267.200000 1449.590000 2267.680000 ;
+ RECT 1452.720000 2261.760000 1453.820000 2262.240000 ;
+ RECT 1448.590000 2261.760000 1449.590000 2262.240000 ;
+ RECT 1452.720000 2256.320000 1453.820000 2256.800000 ;
+ RECT 1448.590000 2256.320000 1449.590000 2256.800000 ;
+ RECT 1452.720000 2250.880000 1453.820000 2251.360000 ;
+ RECT 1448.590000 2250.880000 1449.590000 2251.360000 ;
+ RECT 1542.720000 2245.440000 1543.820000 2245.920000 ;
+ RECT 1542.720000 2240.000000 1543.820000 2240.480000 ;
+ RECT 1542.720000 2234.560000 1543.820000 2235.040000 ;
+ RECT 1542.720000 2229.120000 1543.820000 2229.600000 ;
+ RECT 1542.720000 2223.680000 1543.820000 2224.160000 ;
+ RECT 1497.720000 2245.440000 1498.820000 2245.920000 ;
+ RECT 1497.720000 2240.000000 1498.820000 2240.480000 ;
+ RECT 1497.720000 2234.560000 1498.820000 2235.040000 ;
+ RECT 1497.720000 2229.120000 1498.820000 2229.600000 ;
+ RECT 1497.720000 2223.680000 1498.820000 2224.160000 ;
+ RECT 1542.720000 2218.240000 1543.820000 2218.720000 ;
+ RECT 1542.720000 2212.800000 1543.820000 2213.280000 ;
+ RECT 1542.720000 2207.360000 1543.820000 2207.840000 ;
+ RECT 1542.720000 2201.920000 1543.820000 2202.400000 ;
+ RECT 1497.720000 2212.800000 1498.820000 2213.280000 ;
+ RECT 1497.720000 2207.360000 1498.820000 2207.840000 ;
+ RECT 1497.720000 2201.920000 1498.820000 2202.400000 ;
+ RECT 1497.720000 2218.240000 1498.820000 2218.720000 ;
+ RECT 1452.720000 2245.440000 1453.820000 2245.920000 ;
+ RECT 1448.590000 2245.440000 1449.590000 2245.920000 ;
+ RECT 1452.720000 2240.000000 1453.820000 2240.480000 ;
+ RECT 1448.590000 2240.000000 1449.590000 2240.480000 ;
+ RECT 1452.720000 2234.560000 1453.820000 2235.040000 ;
+ RECT 1448.590000 2234.560000 1449.590000 2235.040000 ;
+ RECT 1452.720000 2223.680000 1453.820000 2224.160000 ;
+ RECT 1448.590000 2223.680000 1449.590000 2224.160000 ;
+ RECT 1448.590000 2229.120000 1449.590000 2229.600000 ;
+ RECT 1452.720000 2229.120000 1453.820000 2229.600000 ;
+ RECT 1452.720000 2218.240000 1453.820000 2218.720000 ;
+ RECT 1448.590000 2218.240000 1449.590000 2218.720000 ;
+ RECT 1452.720000 2212.800000 1453.820000 2213.280000 ;
+ RECT 1448.590000 2212.800000 1449.590000 2213.280000 ;
+ RECT 1452.720000 2207.360000 1453.820000 2207.840000 ;
+ RECT 1448.590000 2207.360000 1449.590000 2207.840000 ;
+ RECT 1452.720000 2201.920000 1453.820000 2202.400000 ;
+ RECT 1448.590000 2201.920000 1449.590000 2202.400000 ;
+ RECT 1542.720000 2196.480000 1543.820000 2196.960000 ;
+ RECT 1542.720000 2191.040000 1543.820000 2191.520000 ;
+ RECT 1542.720000 2185.600000 1543.820000 2186.080000 ;
+ RECT 1542.720000 2180.160000 1543.820000 2180.640000 ;
+ RECT 1542.720000 2174.720000 1543.820000 2175.200000 ;
+ RECT 1497.720000 2196.480000 1498.820000 2196.960000 ;
+ RECT 1497.720000 2191.040000 1498.820000 2191.520000 ;
+ RECT 1497.720000 2185.600000 1498.820000 2186.080000 ;
+ RECT 1497.720000 2180.160000 1498.820000 2180.640000 ;
+ RECT 1497.720000 2174.720000 1498.820000 2175.200000 ;
+ RECT 1542.720000 2152.960000 1543.820000 2153.440000 ;
+ RECT 1542.720000 2158.400000 1543.820000 2158.880000 ;
+ RECT 1542.720000 2163.840000 1543.820000 2164.320000 ;
+ RECT 1542.720000 2169.280000 1543.820000 2169.760000 ;
+ RECT 1497.720000 2152.960000 1498.820000 2153.440000 ;
+ RECT 1497.720000 2158.400000 1498.820000 2158.880000 ;
+ RECT 1497.720000 2163.840000 1498.820000 2164.320000 ;
+ RECT 1497.720000 2169.280000 1498.820000 2169.760000 ;
+ RECT 1452.720000 2196.480000 1453.820000 2196.960000 ;
+ RECT 1448.590000 2196.480000 1449.590000 2196.960000 ;
+ RECT 1452.720000 2191.040000 1453.820000 2191.520000 ;
+ RECT 1448.590000 2191.040000 1449.590000 2191.520000 ;
+ RECT 1452.720000 2180.160000 1453.820000 2180.640000 ;
+ RECT 1448.590000 2180.160000 1449.590000 2180.640000 ;
+ RECT 1452.720000 2174.720000 1453.820000 2175.200000 ;
+ RECT 1448.590000 2174.720000 1449.590000 2175.200000 ;
+ RECT 1452.720000 2185.600000 1453.820000 2186.080000 ;
+ RECT 1448.590000 2185.600000 1449.590000 2186.080000 ;
+ RECT 1452.720000 2169.280000 1453.820000 2169.760000 ;
+ RECT 1448.590000 2169.280000 1449.590000 2169.760000 ;
+ RECT 1452.720000 2163.840000 1453.820000 2164.320000 ;
+ RECT 1448.590000 2163.840000 1449.590000 2164.320000 ;
+ RECT 1452.720000 2158.400000 1453.820000 2158.880000 ;
+ RECT 1452.720000 2152.960000 1453.820000 2153.440000 ;
+ RECT 1448.590000 2158.400000 1449.590000 2158.880000 ;
+ RECT 1448.590000 2152.960000 1449.590000 2153.440000 ;
+ RECT 1445.760000 2544.090000 1645.860000 2545.090000 ;
+ RECT 1445.760000 2150.950000 1645.860000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 2148.100000 1449.590000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 2547.620000 1449.590000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 2148.100000 1643.030000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 2547.620000 1643.030000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2150.950000 1446.760000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2150.950000 1645.860000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2544.090000 1446.760000 2545.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2544.090000 1645.860000 2545.090000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 1747.580000 1449.590000 2148.100000 ;
+ RECT 1642.030000 1747.580000 1643.030000 2148.100000 ;
+ RECT 1452.720000 1750.430000 1453.820000 2144.570000 ;
+ RECT 1497.720000 1750.430000 1498.820000 2144.570000 ;
+ RECT 1542.720000 1750.430000 1543.820000 2144.570000 ;
+ RECT 1587.720000 1750.430000 1588.820000 2144.570000 ;
+ RECT 1632.720000 1750.430000 1633.820000 2144.570000 ;
+ LAYER met3 ;
+ RECT 1632.720000 2138.680000 1633.820000 2139.160000 ;
+ RECT 1642.030000 2138.680000 1643.030000 2139.160000 ;
+ RECT 1642.030000 2133.240000 1643.030000 2133.720000 ;
+ RECT 1632.720000 2133.240000 1633.820000 2133.720000 ;
+ RECT 1632.720000 2127.800000 1633.820000 2128.280000 ;
+ RECT 1642.030000 2127.800000 1643.030000 2128.280000 ;
+ RECT 1642.030000 2111.480000 1643.030000 2111.960000 ;
+ RECT 1642.030000 2116.920000 1643.030000 2117.400000 ;
+ RECT 1642.030000 2122.360000 1643.030000 2122.840000 ;
+ RECT 1632.720000 2122.360000 1633.820000 2122.840000 ;
+ RECT 1632.720000 2111.480000 1633.820000 2111.960000 ;
+ RECT 1632.720000 2116.920000 1633.820000 2117.400000 ;
+ RECT 1632.720000 2100.600000 1633.820000 2101.080000 ;
+ RECT 1632.720000 2106.040000 1633.820000 2106.520000 ;
+ RECT 1642.030000 2106.040000 1643.030000 2106.520000 ;
+ RECT 1642.030000 2100.600000 1643.030000 2101.080000 ;
+ RECT 1587.720000 2138.680000 1588.820000 2139.160000 ;
+ RECT 1587.720000 2133.240000 1588.820000 2133.720000 ;
+ RECT 1587.720000 2127.800000 1588.820000 2128.280000 ;
+ RECT 1587.720000 2122.360000 1588.820000 2122.840000 ;
+ RECT 1587.720000 2100.600000 1588.820000 2101.080000 ;
+ RECT 1587.720000 2106.040000 1588.820000 2106.520000 ;
+ RECT 1587.720000 2111.480000 1588.820000 2111.960000 ;
+ RECT 1587.720000 2116.920000 1588.820000 2117.400000 ;
+ RECT 1632.720000 2095.160000 1633.820000 2095.640000 ;
+ RECT 1632.720000 2089.720000 1633.820000 2090.200000 ;
+ RECT 1642.030000 2095.160000 1643.030000 2095.640000 ;
+ RECT 1642.030000 2089.720000 1643.030000 2090.200000 ;
+ RECT 1642.030000 2073.400000 1643.030000 2073.880000 ;
+ RECT 1642.030000 2078.840000 1643.030000 2079.320000 ;
+ RECT 1642.030000 2084.280000 1643.030000 2084.760000 ;
+ RECT 1632.720000 2084.280000 1633.820000 2084.760000 ;
+ RECT 1632.720000 2078.840000 1633.820000 2079.320000 ;
+ RECT 1632.720000 2073.400000 1633.820000 2073.880000 ;
+ RECT 1632.720000 2062.520000 1633.820000 2063.000000 ;
+ RECT 1632.720000 2067.960000 1633.820000 2068.440000 ;
+ RECT 1642.030000 2067.960000 1643.030000 2068.440000 ;
+ RECT 1642.030000 2062.520000 1643.030000 2063.000000 ;
+ RECT 1642.030000 2051.640000 1643.030000 2052.120000 ;
+ RECT 1642.030000 2057.080000 1643.030000 2057.560000 ;
+ RECT 1632.720000 2051.640000 1633.820000 2052.120000 ;
+ RECT 1632.720000 2057.080000 1633.820000 2057.560000 ;
+ RECT 1587.720000 2095.160000 1588.820000 2095.640000 ;
+ RECT 1587.720000 2089.720000 1588.820000 2090.200000 ;
+ RECT 1587.720000 2084.280000 1588.820000 2084.760000 ;
+ RECT 1587.720000 2078.840000 1588.820000 2079.320000 ;
+ RECT 1587.720000 2073.400000 1588.820000 2073.880000 ;
+ RECT 1587.720000 2051.640000 1588.820000 2052.120000 ;
+ RECT 1587.720000 2057.080000 1588.820000 2057.560000 ;
+ RECT 1587.720000 2062.520000 1588.820000 2063.000000 ;
+ RECT 1587.720000 2067.960000 1588.820000 2068.440000 ;
+ RECT 1632.720000 2046.200000 1633.820000 2046.680000 ;
+ RECT 1632.720000 2040.760000 1633.820000 2041.240000 ;
+ RECT 1642.030000 2046.200000 1643.030000 2046.680000 ;
+ RECT 1642.030000 2040.760000 1643.030000 2041.240000 ;
+ RECT 1632.720000 2029.880000 1633.820000 2030.360000 ;
+ RECT 1632.720000 2024.440000 1633.820000 2024.920000 ;
+ RECT 1642.030000 2029.880000 1643.030000 2030.360000 ;
+ RECT 1642.030000 2024.440000 1643.030000 2024.920000 ;
+ RECT 1632.720000 2035.320000 1633.820000 2035.800000 ;
+ RECT 1642.030000 2035.320000 1643.030000 2035.800000 ;
+ RECT 1642.030000 2013.560000 1643.030000 2014.040000 ;
+ RECT 1642.030000 2019.000000 1643.030000 2019.480000 ;
+ RECT 1632.720000 2013.560000 1633.820000 2014.040000 ;
+ RECT 1632.720000 2019.000000 1633.820000 2019.480000 ;
+ RECT 1632.720000 2002.680000 1633.820000 2003.160000 ;
+ RECT 1632.720000 2008.120000 1633.820000 2008.600000 ;
+ RECT 1642.030000 2008.120000 1643.030000 2008.600000 ;
+ RECT 1642.030000 2002.680000 1643.030000 2003.160000 ;
+ RECT 1587.720000 2046.200000 1588.820000 2046.680000 ;
+ RECT 1587.720000 2040.760000 1588.820000 2041.240000 ;
+ RECT 1587.720000 2035.320000 1588.820000 2035.800000 ;
+ RECT 1587.720000 2029.880000 1588.820000 2030.360000 ;
+ RECT 1587.720000 2024.440000 1588.820000 2024.920000 ;
+ RECT 1587.720000 2002.680000 1588.820000 2003.160000 ;
+ RECT 1587.720000 2008.120000 1588.820000 2008.600000 ;
+ RECT 1587.720000 2013.560000 1588.820000 2014.040000 ;
+ RECT 1587.720000 2019.000000 1588.820000 2019.480000 ;
+ RECT 1642.030000 1986.360000 1643.030000 1986.840000 ;
+ RECT 1642.030000 1991.800000 1643.030000 1992.280000 ;
+ RECT 1642.030000 1997.240000 1643.030000 1997.720000 ;
+ RECT 1632.720000 1997.240000 1633.820000 1997.720000 ;
+ RECT 1632.720000 1991.800000 1633.820000 1992.280000 ;
+ RECT 1632.720000 1986.360000 1633.820000 1986.840000 ;
+ RECT 1632.720000 1980.920000 1633.820000 1981.400000 ;
+ RECT 1632.720000 1975.480000 1633.820000 1975.960000 ;
+ RECT 1642.030000 1980.920000 1643.030000 1981.400000 ;
+ RECT 1642.030000 1975.480000 1643.030000 1975.960000 ;
+ RECT 1632.720000 1964.600000 1633.820000 1965.080000 ;
+ RECT 1632.720000 1970.040000 1633.820000 1970.520000 ;
+ RECT 1642.030000 1970.040000 1643.030000 1970.520000 ;
+ RECT 1642.030000 1964.600000 1643.030000 1965.080000 ;
+ RECT 1642.030000 1948.280000 1643.030000 1948.760000 ;
+ RECT 1642.030000 1953.720000 1643.030000 1954.200000 ;
+ RECT 1642.030000 1959.160000 1643.030000 1959.640000 ;
+ RECT 1632.720000 1959.160000 1633.820000 1959.640000 ;
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+ RECT 1452.720000 1872.120000 1453.820000 1872.600000 ;
+ RECT 1452.720000 1866.680000 1453.820000 1867.160000 ;
+ RECT 1448.590000 1872.120000 1449.590000 1872.600000 ;
+ RECT 1448.590000 1866.680000 1449.590000 1867.160000 ;
+ RECT 1452.720000 1861.240000 1453.820000 1861.720000 ;
+ RECT 1448.590000 1861.240000 1449.590000 1861.720000 ;
+ RECT 1452.720000 1855.800000 1453.820000 1856.280000 ;
+ RECT 1448.590000 1855.800000 1449.590000 1856.280000 ;
+ RECT 1452.720000 1850.360000 1453.820000 1850.840000 ;
+ RECT 1448.590000 1850.360000 1449.590000 1850.840000 ;
+ RECT 1542.720000 1844.920000 1543.820000 1845.400000 ;
+ RECT 1542.720000 1839.480000 1543.820000 1839.960000 ;
+ RECT 1542.720000 1834.040000 1543.820000 1834.520000 ;
+ RECT 1542.720000 1828.600000 1543.820000 1829.080000 ;
+ RECT 1542.720000 1823.160000 1543.820000 1823.640000 ;
+ RECT 1497.720000 1844.920000 1498.820000 1845.400000 ;
+ RECT 1497.720000 1839.480000 1498.820000 1839.960000 ;
+ RECT 1497.720000 1834.040000 1498.820000 1834.520000 ;
+ RECT 1497.720000 1828.600000 1498.820000 1829.080000 ;
+ RECT 1497.720000 1823.160000 1498.820000 1823.640000 ;
+ RECT 1542.720000 1817.720000 1543.820000 1818.200000 ;
+ RECT 1542.720000 1812.280000 1543.820000 1812.760000 ;
+ RECT 1542.720000 1806.840000 1543.820000 1807.320000 ;
+ RECT 1542.720000 1801.400000 1543.820000 1801.880000 ;
+ RECT 1497.720000 1812.280000 1498.820000 1812.760000 ;
+ RECT 1497.720000 1806.840000 1498.820000 1807.320000 ;
+ RECT 1497.720000 1801.400000 1498.820000 1801.880000 ;
+ RECT 1497.720000 1817.720000 1498.820000 1818.200000 ;
+ RECT 1452.720000 1844.920000 1453.820000 1845.400000 ;
+ RECT 1448.590000 1844.920000 1449.590000 1845.400000 ;
+ RECT 1452.720000 1839.480000 1453.820000 1839.960000 ;
+ RECT 1448.590000 1839.480000 1449.590000 1839.960000 ;
+ RECT 1452.720000 1834.040000 1453.820000 1834.520000 ;
+ RECT 1448.590000 1834.040000 1449.590000 1834.520000 ;
+ RECT 1452.720000 1823.160000 1453.820000 1823.640000 ;
+ RECT 1448.590000 1823.160000 1449.590000 1823.640000 ;
+ RECT 1448.590000 1828.600000 1449.590000 1829.080000 ;
+ RECT 1452.720000 1828.600000 1453.820000 1829.080000 ;
+ RECT 1452.720000 1817.720000 1453.820000 1818.200000 ;
+ RECT 1448.590000 1817.720000 1449.590000 1818.200000 ;
+ RECT 1452.720000 1812.280000 1453.820000 1812.760000 ;
+ RECT 1448.590000 1812.280000 1449.590000 1812.760000 ;
+ RECT 1452.720000 1806.840000 1453.820000 1807.320000 ;
+ RECT 1448.590000 1806.840000 1449.590000 1807.320000 ;
+ RECT 1452.720000 1801.400000 1453.820000 1801.880000 ;
+ RECT 1448.590000 1801.400000 1449.590000 1801.880000 ;
+ RECT 1542.720000 1795.960000 1543.820000 1796.440000 ;
+ RECT 1542.720000 1790.520000 1543.820000 1791.000000 ;
+ RECT 1542.720000 1785.080000 1543.820000 1785.560000 ;
+ RECT 1542.720000 1779.640000 1543.820000 1780.120000 ;
+ RECT 1542.720000 1774.200000 1543.820000 1774.680000 ;
+ RECT 1497.720000 1795.960000 1498.820000 1796.440000 ;
+ RECT 1497.720000 1790.520000 1498.820000 1791.000000 ;
+ RECT 1497.720000 1785.080000 1498.820000 1785.560000 ;
+ RECT 1497.720000 1779.640000 1498.820000 1780.120000 ;
+ RECT 1497.720000 1774.200000 1498.820000 1774.680000 ;
+ RECT 1542.720000 1752.440000 1543.820000 1752.920000 ;
+ RECT 1542.720000 1757.880000 1543.820000 1758.360000 ;
+ RECT 1542.720000 1763.320000 1543.820000 1763.800000 ;
+ RECT 1542.720000 1768.760000 1543.820000 1769.240000 ;
+ RECT 1497.720000 1752.440000 1498.820000 1752.920000 ;
+ RECT 1497.720000 1757.880000 1498.820000 1758.360000 ;
+ RECT 1497.720000 1763.320000 1498.820000 1763.800000 ;
+ RECT 1497.720000 1768.760000 1498.820000 1769.240000 ;
+ RECT 1452.720000 1795.960000 1453.820000 1796.440000 ;
+ RECT 1448.590000 1795.960000 1449.590000 1796.440000 ;
+ RECT 1452.720000 1790.520000 1453.820000 1791.000000 ;
+ RECT 1448.590000 1790.520000 1449.590000 1791.000000 ;
+ RECT 1452.720000 1779.640000 1453.820000 1780.120000 ;
+ RECT 1448.590000 1779.640000 1449.590000 1780.120000 ;
+ RECT 1452.720000 1774.200000 1453.820000 1774.680000 ;
+ RECT 1448.590000 1774.200000 1449.590000 1774.680000 ;
+ RECT 1452.720000 1785.080000 1453.820000 1785.560000 ;
+ RECT 1448.590000 1785.080000 1449.590000 1785.560000 ;
+ RECT 1452.720000 1768.760000 1453.820000 1769.240000 ;
+ RECT 1448.590000 1768.760000 1449.590000 1769.240000 ;
+ RECT 1452.720000 1763.320000 1453.820000 1763.800000 ;
+ RECT 1448.590000 1763.320000 1449.590000 1763.800000 ;
+ RECT 1452.720000 1757.880000 1453.820000 1758.360000 ;
+ RECT 1452.720000 1752.440000 1453.820000 1752.920000 ;
+ RECT 1448.590000 1757.880000 1449.590000 1758.360000 ;
+ RECT 1448.590000 1752.440000 1449.590000 1752.920000 ;
+ RECT 1445.760000 2143.570000 1645.860000 2144.570000 ;
+ RECT 1445.760000 1750.430000 1645.860000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 1747.580000 1449.590000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 2147.100000 1449.590000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 1747.580000 1643.030000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 2147.100000 1643.030000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 1750.430000 1446.760000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 1750.430000 1645.860000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 2143.570000 1446.760000 2144.570000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 2143.570000 1645.860000 2144.570000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'DSP'
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 1347.060000 1449.590000 1747.580000 ;
+ RECT 1642.030000 1347.060000 1643.030000 1747.580000 ;
+ RECT 1452.720000 1349.910000 1453.820000 1744.050000 ;
+ RECT 1497.720000 1349.910000 1498.820000 1744.050000 ;
+ RECT 1542.720000 1349.910000 1543.820000 1744.050000 ;
+ RECT 1587.720000 1349.910000 1588.820000 1744.050000 ;
+ RECT 1632.720000 1349.910000 1633.820000 1744.050000 ;
+ LAYER met3 ;
+ RECT 1632.720000 1738.160000 1633.820000 1738.640000 ;
+ RECT 1642.030000 1738.160000 1643.030000 1738.640000 ;
+ RECT 1642.030000 1732.720000 1643.030000 1733.200000 ;
+ RECT 1632.720000 1732.720000 1633.820000 1733.200000 ;
+ RECT 1632.720000 1727.280000 1633.820000 1727.760000 ;
+ RECT 1642.030000 1727.280000 1643.030000 1727.760000 ;
+ RECT 1642.030000 1710.960000 1643.030000 1711.440000 ;
+ RECT 1642.030000 1716.400000 1643.030000 1716.880000 ;
+ RECT 1642.030000 1721.840000 1643.030000 1722.320000 ;
+ RECT 1632.720000 1721.840000 1633.820000 1722.320000 ;
+ RECT 1632.720000 1710.960000 1633.820000 1711.440000 ;
+ RECT 1632.720000 1716.400000 1633.820000 1716.880000 ;
+ RECT 1632.720000 1700.080000 1633.820000 1700.560000 ;
+ RECT 1632.720000 1705.520000 1633.820000 1706.000000 ;
+ RECT 1642.030000 1705.520000 1643.030000 1706.000000 ;
+ RECT 1642.030000 1700.080000 1643.030000 1700.560000 ;
+ RECT 1587.720000 1738.160000 1588.820000 1738.640000 ;
+ RECT 1587.720000 1732.720000 1588.820000 1733.200000 ;
+ RECT 1587.720000 1727.280000 1588.820000 1727.760000 ;
+ RECT 1587.720000 1721.840000 1588.820000 1722.320000 ;
+ RECT 1587.720000 1700.080000 1588.820000 1700.560000 ;
+ RECT 1587.720000 1705.520000 1588.820000 1706.000000 ;
+ RECT 1587.720000 1710.960000 1588.820000 1711.440000 ;
+ RECT 1587.720000 1716.400000 1588.820000 1716.880000 ;
+ RECT 1632.720000 1694.640000 1633.820000 1695.120000 ;
+ RECT 1632.720000 1689.200000 1633.820000 1689.680000 ;
+ RECT 1642.030000 1694.640000 1643.030000 1695.120000 ;
+ RECT 1642.030000 1689.200000 1643.030000 1689.680000 ;
+ RECT 1642.030000 1672.880000 1643.030000 1673.360000 ;
+ RECT 1642.030000 1678.320000 1643.030000 1678.800000 ;
+ RECT 1642.030000 1683.760000 1643.030000 1684.240000 ;
+ RECT 1632.720000 1683.760000 1633.820000 1684.240000 ;
+ RECT 1632.720000 1678.320000 1633.820000 1678.800000 ;
+ RECT 1632.720000 1672.880000 1633.820000 1673.360000 ;
+ RECT 1632.720000 1662.000000 1633.820000 1662.480000 ;
+ RECT 1632.720000 1667.440000 1633.820000 1667.920000 ;
+ RECT 1642.030000 1667.440000 1643.030000 1667.920000 ;
+ RECT 1642.030000 1662.000000 1643.030000 1662.480000 ;
+ RECT 1642.030000 1651.120000 1643.030000 1651.600000 ;
+ RECT 1642.030000 1656.560000 1643.030000 1657.040000 ;
+ RECT 1632.720000 1651.120000 1633.820000 1651.600000 ;
+ RECT 1632.720000 1656.560000 1633.820000 1657.040000 ;
+ RECT 1587.720000 1694.640000 1588.820000 1695.120000 ;
+ RECT 1587.720000 1689.200000 1588.820000 1689.680000 ;
+ RECT 1587.720000 1683.760000 1588.820000 1684.240000 ;
+ RECT 1587.720000 1678.320000 1588.820000 1678.800000 ;
+ RECT 1587.720000 1672.880000 1588.820000 1673.360000 ;
+ RECT 1587.720000 1651.120000 1588.820000 1651.600000 ;
+ RECT 1587.720000 1656.560000 1588.820000 1657.040000 ;
+ RECT 1587.720000 1662.000000 1588.820000 1662.480000 ;
+ RECT 1587.720000 1667.440000 1588.820000 1667.920000 ;
+ RECT 1632.720000 1645.680000 1633.820000 1646.160000 ;
+ RECT 1632.720000 1640.240000 1633.820000 1640.720000 ;
+ RECT 1642.030000 1645.680000 1643.030000 1646.160000 ;
+ RECT 1642.030000 1640.240000 1643.030000 1640.720000 ;
+ RECT 1632.720000 1629.360000 1633.820000 1629.840000 ;
+ RECT 1632.720000 1623.920000 1633.820000 1624.400000 ;
+ RECT 1642.030000 1629.360000 1643.030000 1629.840000 ;
+ RECT 1642.030000 1623.920000 1643.030000 1624.400000 ;
+ RECT 1632.720000 1634.800000 1633.820000 1635.280000 ;
+ RECT 1642.030000 1634.800000 1643.030000 1635.280000 ;
+ RECT 1642.030000 1613.040000 1643.030000 1613.520000 ;
+ RECT 1642.030000 1618.480000 1643.030000 1618.960000 ;
+ RECT 1632.720000 1613.040000 1633.820000 1613.520000 ;
+ RECT 1632.720000 1618.480000 1633.820000 1618.960000 ;
+ RECT 1632.720000 1602.160000 1633.820000 1602.640000 ;
+ RECT 1632.720000 1607.600000 1633.820000 1608.080000 ;
+ RECT 1642.030000 1607.600000 1643.030000 1608.080000 ;
+ RECT 1642.030000 1602.160000 1643.030000 1602.640000 ;
+ RECT 1587.720000 1645.680000 1588.820000 1646.160000 ;
+ RECT 1587.720000 1640.240000 1588.820000 1640.720000 ;
+ RECT 1587.720000 1634.800000 1588.820000 1635.280000 ;
+ RECT 1587.720000 1629.360000 1588.820000 1629.840000 ;
+ RECT 1587.720000 1623.920000 1588.820000 1624.400000 ;
+ RECT 1587.720000 1602.160000 1588.820000 1602.640000 ;
+ RECT 1587.720000 1607.600000 1588.820000 1608.080000 ;
+ RECT 1587.720000 1613.040000 1588.820000 1613.520000 ;
+ RECT 1587.720000 1618.480000 1588.820000 1618.960000 ;
+ RECT 1642.030000 1585.840000 1643.030000 1586.320000 ;
+ RECT 1642.030000 1591.280000 1643.030000 1591.760000 ;
+ RECT 1642.030000 1596.720000 1643.030000 1597.200000 ;
+ RECT 1632.720000 1596.720000 1633.820000 1597.200000 ;
+ RECT 1632.720000 1591.280000 1633.820000 1591.760000 ;
+ RECT 1632.720000 1585.840000 1633.820000 1586.320000 ;
+ RECT 1632.720000 1580.400000 1633.820000 1580.880000 ;
+ RECT 1632.720000 1574.960000 1633.820000 1575.440000 ;
+ RECT 1642.030000 1580.400000 1643.030000 1580.880000 ;
+ RECT 1642.030000 1574.960000 1643.030000 1575.440000 ;
+ RECT 1632.720000 1564.080000 1633.820000 1564.560000 ;
+ RECT 1632.720000 1569.520000 1633.820000 1570.000000 ;
+ RECT 1642.030000 1569.520000 1643.030000 1570.000000 ;
+ RECT 1642.030000 1564.080000 1643.030000 1564.560000 ;
+ RECT 1642.030000 1547.760000 1643.030000 1548.240000 ;
+ RECT 1642.030000 1553.200000 1643.030000 1553.680000 ;
+ RECT 1642.030000 1558.640000 1643.030000 1559.120000 ;
+ RECT 1632.720000 1558.640000 1633.820000 1559.120000 ;
+ RECT 1632.720000 1553.200000 1633.820000 1553.680000 ;
+ RECT 1632.720000 1547.760000 1633.820000 1548.240000 ;
+ RECT 1587.720000 1596.720000 1588.820000 1597.200000 ;
+ RECT 1587.720000 1591.280000 1588.820000 1591.760000 ;
+ RECT 1587.720000 1585.840000 1588.820000 1586.320000 ;
+ RECT 1587.720000 1580.400000 1588.820000 1580.880000 ;
+ RECT 1587.720000 1574.960000 1588.820000 1575.440000 ;
+ RECT 1587.720000 1564.080000 1588.820000 1564.560000 ;
+ RECT 1587.720000 1558.640000 1588.820000 1559.120000 ;
+ RECT 1587.720000 1553.200000 1588.820000 1553.680000 ;
+ RECT 1587.720000 1547.760000 1588.820000 1548.240000 ;
+ RECT 1587.720000 1569.520000 1588.820000 1570.000000 ;
+ RECT 1542.720000 1738.160000 1543.820000 1738.640000 ;
+ RECT 1542.720000 1732.720000 1543.820000 1733.200000 ;
+ RECT 1542.720000 1727.280000 1543.820000 1727.760000 ;
+ RECT 1497.720000 1738.160000 1498.820000 1738.640000 ;
+ RECT 1497.720000 1732.720000 1498.820000 1733.200000 ;
+ RECT 1497.720000 1727.280000 1498.820000 1727.760000 ;
+ RECT 1542.720000 1710.960000 1543.820000 1711.440000 ;
+ RECT 1542.720000 1705.520000 1543.820000 1706.000000 ;
+ RECT 1542.720000 1700.080000 1543.820000 1700.560000 ;
+ RECT 1542.720000 1716.400000 1543.820000 1716.880000 ;
+ RECT 1542.720000 1721.840000 1543.820000 1722.320000 ;
+ RECT 1497.720000 1721.840000 1498.820000 1722.320000 ;
+ RECT 1497.720000 1710.960000 1498.820000 1711.440000 ;
+ RECT 1497.720000 1705.520000 1498.820000 1706.000000 ;
+ RECT 1497.720000 1700.080000 1498.820000 1700.560000 ;
+ RECT 1497.720000 1716.400000 1498.820000 1716.880000 ;
+ RECT 1452.720000 1738.160000 1453.820000 1738.640000 ;
+ RECT 1448.590000 1738.160000 1449.590000 1738.640000 ;
+ RECT 1448.590000 1732.720000 1449.590000 1733.200000 ;
+ RECT 1452.720000 1732.720000 1453.820000 1733.200000 ;
+ RECT 1452.720000 1727.280000 1453.820000 1727.760000 ;
+ RECT 1448.590000 1727.280000 1449.590000 1727.760000 ;
+ RECT 1452.720000 1721.840000 1453.820000 1722.320000 ;
+ RECT 1452.720000 1716.400000 1453.820000 1716.880000 ;
+ RECT 1448.590000 1721.840000 1449.590000 1722.320000 ;
+ RECT 1448.590000 1716.400000 1449.590000 1716.880000 ;
+ RECT 1452.720000 1710.960000 1453.820000 1711.440000 ;
+ RECT 1448.590000 1710.960000 1449.590000 1711.440000 ;
+ RECT 1452.720000 1705.520000 1453.820000 1706.000000 ;
+ RECT 1448.590000 1705.520000 1449.590000 1706.000000 ;
+ RECT 1452.720000 1700.080000 1453.820000 1700.560000 ;
+ RECT 1448.590000 1700.080000 1449.590000 1700.560000 ;
+ RECT 1542.720000 1694.640000 1543.820000 1695.120000 ;
+ RECT 1542.720000 1689.200000 1543.820000 1689.680000 ;
+ RECT 1542.720000 1683.760000 1543.820000 1684.240000 ;
+ RECT 1542.720000 1678.320000 1543.820000 1678.800000 ;
+ RECT 1542.720000 1672.880000 1543.820000 1673.360000 ;
+ RECT 1497.720000 1694.640000 1498.820000 1695.120000 ;
+ RECT 1497.720000 1689.200000 1498.820000 1689.680000 ;
+ RECT 1497.720000 1683.760000 1498.820000 1684.240000 ;
+ RECT 1497.720000 1678.320000 1498.820000 1678.800000 ;
+ RECT 1497.720000 1672.880000 1498.820000 1673.360000 ;
+ RECT 1542.720000 1667.440000 1543.820000 1667.920000 ;
+ RECT 1542.720000 1662.000000 1543.820000 1662.480000 ;
+ RECT 1542.720000 1656.560000 1543.820000 1657.040000 ;
+ RECT 1542.720000 1651.120000 1543.820000 1651.600000 ;
+ RECT 1497.720000 1662.000000 1498.820000 1662.480000 ;
+ RECT 1497.720000 1656.560000 1498.820000 1657.040000 ;
+ RECT 1497.720000 1651.120000 1498.820000 1651.600000 ;
+ RECT 1497.720000 1667.440000 1498.820000 1667.920000 ;
+ RECT 1452.720000 1694.640000 1453.820000 1695.120000 ;
+ RECT 1448.590000 1694.640000 1449.590000 1695.120000 ;
+ RECT 1452.720000 1689.200000 1453.820000 1689.680000 ;
+ RECT 1448.590000 1689.200000 1449.590000 1689.680000 ;
+ RECT 1452.720000 1683.760000 1453.820000 1684.240000 ;
+ RECT 1448.590000 1683.760000 1449.590000 1684.240000 ;
+ RECT 1452.720000 1672.880000 1453.820000 1673.360000 ;
+ RECT 1448.590000 1672.880000 1449.590000 1673.360000 ;
+ RECT 1448.590000 1678.320000 1449.590000 1678.800000 ;
+ RECT 1452.720000 1678.320000 1453.820000 1678.800000 ;
+ RECT 1452.720000 1667.440000 1453.820000 1667.920000 ;
+ RECT 1448.590000 1667.440000 1449.590000 1667.920000 ;
+ RECT 1452.720000 1662.000000 1453.820000 1662.480000 ;
+ RECT 1448.590000 1662.000000 1449.590000 1662.480000 ;
+ RECT 1452.720000 1656.560000 1453.820000 1657.040000 ;
+ RECT 1448.590000 1656.560000 1449.590000 1657.040000 ;
+ RECT 1452.720000 1651.120000 1453.820000 1651.600000 ;
+ RECT 1448.590000 1651.120000 1449.590000 1651.600000 ;
+ RECT 1542.720000 1645.680000 1543.820000 1646.160000 ;
+ RECT 1542.720000 1640.240000 1543.820000 1640.720000 ;
+ RECT 1542.720000 1634.800000 1543.820000 1635.280000 ;
+ RECT 1542.720000 1629.360000 1543.820000 1629.840000 ;
+ RECT 1542.720000 1623.920000 1543.820000 1624.400000 ;
+ RECT 1497.720000 1645.680000 1498.820000 1646.160000 ;
+ RECT 1497.720000 1640.240000 1498.820000 1640.720000 ;
+ RECT 1497.720000 1634.800000 1498.820000 1635.280000 ;
+ RECT 1497.720000 1629.360000 1498.820000 1629.840000 ;
+ RECT 1497.720000 1623.920000 1498.820000 1624.400000 ;
+ RECT 1542.720000 1618.480000 1543.820000 1618.960000 ;
+ RECT 1542.720000 1613.040000 1543.820000 1613.520000 ;
+ RECT 1542.720000 1607.600000 1543.820000 1608.080000 ;
+ RECT 1542.720000 1602.160000 1543.820000 1602.640000 ;
+ RECT 1497.720000 1613.040000 1498.820000 1613.520000 ;
+ RECT 1497.720000 1607.600000 1498.820000 1608.080000 ;
+ RECT 1497.720000 1602.160000 1498.820000 1602.640000 ;
+ RECT 1497.720000 1618.480000 1498.820000 1618.960000 ;
+ RECT 1452.720000 1645.680000 1453.820000 1646.160000 ;
+ RECT 1448.590000 1645.680000 1449.590000 1646.160000 ;
+ RECT 1452.720000 1640.240000 1453.820000 1640.720000 ;
+ RECT 1448.590000 1640.240000 1449.590000 1640.720000 ;
+ RECT 1452.720000 1629.360000 1453.820000 1629.840000 ;
+ RECT 1448.590000 1629.360000 1449.590000 1629.840000 ;
+ RECT 1452.720000 1623.920000 1453.820000 1624.400000 ;
+ RECT 1448.590000 1623.920000 1449.590000 1624.400000 ;
+ RECT 1452.720000 1634.800000 1453.820000 1635.280000 ;
+ RECT 1448.590000 1634.800000 1449.590000 1635.280000 ;
+ RECT 1452.720000 1618.480000 1453.820000 1618.960000 ;
+ RECT 1448.590000 1618.480000 1449.590000 1618.960000 ;
+ RECT 1452.720000 1613.040000 1453.820000 1613.520000 ;
+ RECT 1448.590000 1613.040000 1449.590000 1613.520000 ;
+ RECT 1452.720000 1607.600000 1453.820000 1608.080000 ;
+ RECT 1448.590000 1607.600000 1449.590000 1608.080000 ;
+ RECT 1452.720000 1602.160000 1453.820000 1602.640000 ;
+ RECT 1448.590000 1602.160000 1449.590000 1602.640000 ;
+ RECT 1542.720000 1596.720000 1543.820000 1597.200000 ;
+ RECT 1542.720000 1591.280000 1543.820000 1591.760000 ;
+ RECT 1542.720000 1585.840000 1543.820000 1586.320000 ;
+ RECT 1542.720000 1580.400000 1543.820000 1580.880000 ;
+ RECT 1542.720000 1574.960000 1543.820000 1575.440000 ;
+ RECT 1497.720000 1596.720000 1498.820000 1597.200000 ;
+ RECT 1497.720000 1591.280000 1498.820000 1591.760000 ;
+ RECT 1497.720000 1585.840000 1498.820000 1586.320000 ;
+ RECT 1497.720000 1580.400000 1498.820000 1580.880000 ;
+ RECT 1497.720000 1574.960000 1498.820000 1575.440000 ;
+ RECT 1542.720000 1564.080000 1543.820000 1564.560000 ;
+ RECT 1542.720000 1547.760000 1543.820000 1548.240000 ;
+ RECT 1542.720000 1553.200000 1543.820000 1553.680000 ;
+ RECT 1542.720000 1558.640000 1543.820000 1559.120000 ;
+ RECT 1542.720000 1569.520000 1543.820000 1570.000000 ;
+ RECT 1497.720000 1547.760000 1498.820000 1548.240000 ;
+ RECT 1497.720000 1553.200000 1498.820000 1553.680000 ;
+ RECT 1497.720000 1558.640000 1498.820000 1559.120000 ;
+ RECT 1497.720000 1564.080000 1498.820000 1564.560000 ;
+ RECT 1497.720000 1569.520000 1498.820000 1570.000000 ;
+ RECT 1452.720000 1596.720000 1453.820000 1597.200000 ;
+ RECT 1452.720000 1591.280000 1453.820000 1591.760000 ;
+ RECT 1448.590000 1596.720000 1449.590000 1597.200000 ;
+ RECT 1448.590000 1591.280000 1449.590000 1591.760000 ;
+ RECT 1452.720000 1585.840000 1453.820000 1586.320000 ;
+ RECT 1448.590000 1585.840000 1449.590000 1586.320000 ;
+ RECT 1452.720000 1580.400000 1453.820000 1580.880000 ;
+ RECT 1448.590000 1580.400000 1449.590000 1580.880000 ;
+ RECT 1452.720000 1574.960000 1453.820000 1575.440000 ;
+ RECT 1448.590000 1574.960000 1449.590000 1575.440000 ;
+ RECT 1452.720000 1569.520000 1453.820000 1570.000000 ;
+ RECT 1448.590000 1569.520000 1449.590000 1570.000000 ;
+ RECT 1452.720000 1564.080000 1453.820000 1564.560000 ;
+ RECT 1448.590000 1564.080000 1449.590000 1564.560000 ;
+ RECT 1452.720000 1558.640000 1453.820000 1559.120000 ;
+ RECT 1448.590000 1558.640000 1449.590000 1559.120000 ;
+ RECT 1452.720000 1547.760000 1453.820000 1548.240000 ;
+ RECT 1448.590000 1547.760000 1449.590000 1548.240000 ;
+ RECT 1448.590000 1553.200000 1449.590000 1553.680000 ;
+ RECT 1452.720000 1553.200000 1453.820000 1553.680000 ;
+ RECT 1632.720000 1542.320000 1633.820000 1542.800000 ;
+ RECT 1632.720000 1536.880000 1633.820000 1537.360000 ;
+ RECT 1642.030000 1542.320000 1643.030000 1542.800000 ;
+ RECT 1642.030000 1536.880000 1643.030000 1537.360000 ;
+ RECT 1642.030000 1526.000000 1643.030000 1526.480000 ;
+ RECT 1642.030000 1531.440000 1643.030000 1531.920000 ;
+ RECT 1632.720000 1531.440000 1633.820000 1531.920000 ;
+ RECT 1632.720000 1526.000000 1633.820000 1526.480000 ;
+ RECT 1632.720000 1515.120000 1633.820000 1515.600000 ;
+ RECT 1632.720000 1520.560000 1633.820000 1521.040000 ;
+ RECT 1642.030000 1520.560000 1643.030000 1521.040000 ;
+ RECT 1642.030000 1515.120000 1643.030000 1515.600000 ;
+ RECT 1632.720000 1498.800000 1633.820000 1499.280000 ;
+ RECT 1632.720000 1504.240000 1633.820000 1504.720000 ;
+ RECT 1642.030000 1504.240000 1643.030000 1504.720000 ;
+ RECT 1642.030000 1498.800000 1643.030000 1499.280000 ;
+ RECT 1632.720000 1509.680000 1633.820000 1510.160000 ;
+ RECT 1642.030000 1509.680000 1643.030000 1510.160000 ;
+ RECT 1587.720000 1542.320000 1588.820000 1542.800000 ;
+ RECT 1587.720000 1536.880000 1588.820000 1537.360000 ;
+ RECT 1587.720000 1531.440000 1588.820000 1531.920000 ;
+ RECT 1587.720000 1526.000000 1588.820000 1526.480000 ;
+ RECT 1587.720000 1498.800000 1588.820000 1499.280000 ;
+ RECT 1587.720000 1504.240000 1588.820000 1504.720000 ;
+ RECT 1587.720000 1509.680000 1588.820000 1510.160000 ;
+ RECT 1587.720000 1515.120000 1588.820000 1515.600000 ;
+ RECT 1587.720000 1520.560000 1588.820000 1521.040000 ;
+ RECT 1642.030000 1487.920000 1643.030000 1488.400000 ;
+ RECT 1642.030000 1493.360000 1643.030000 1493.840000 ;
+ RECT 1632.720000 1493.360000 1633.820000 1493.840000 ;
+ RECT 1632.720000 1487.920000 1633.820000 1488.400000 ;
+ RECT 1632.720000 1482.480000 1633.820000 1482.960000 ;
+ RECT 1632.720000 1477.040000 1633.820000 1477.520000 ;
+ RECT 1642.030000 1482.480000 1643.030000 1482.960000 ;
+ RECT 1642.030000 1477.040000 1643.030000 1477.520000 ;
+ RECT 1642.030000 1460.720000 1643.030000 1461.200000 ;
+ RECT 1642.030000 1466.160000 1643.030000 1466.640000 ;
+ RECT 1642.030000 1471.600000 1643.030000 1472.080000 ;
+ RECT 1632.720000 1460.720000 1633.820000 1461.200000 ;
+ RECT 1632.720000 1466.160000 1633.820000 1466.640000 ;
+ RECT 1632.720000 1471.600000 1633.820000 1472.080000 ;
+ RECT 1632.720000 1449.840000 1633.820000 1450.320000 ;
+ RECT 1632.720000 1455.280000 1633.820000 1455.760000 ;
+ RECT 1642.030000 1455.280000 1643.030000 1455.760000 ;
+ RECT 1642.030000 1449.840000 1643.030000 1450.320000 ;
+ RECT 1587.720000 1493.360000 1588.820000 1493.840000 ;
+ RECT 1587.720000 1487.920000 1588.820000 1488.400000 ;
+ RECT 1587.720000 1482.480000 1588.820000 1482.960000 ;
+ RECT 1587.720000 1477.040000 1588.820000 1477.520000 ;
+ RECT 1587.720000 1449.840000 1588.820000 1450.320000 ;
+ RECT 1587.720000 1455.280000 1588.820000 1455.760000 ;
+ RECT 1587.720000 1460.720000 1588.820000 1461.200000 ;
+ RECT 1587.720000 1466.160000 1588.820000 1466.640000 ;
+ RECT 1587.720000 1471.600000 1588.820000 1472.080000 ;
+ RECT 1632.720000 1444.400000 1633.820000 1444.880000 ;
+ RECT 1632.720000 1438.960000 1633.820000 1439.440000 ;
+ RECT 1642.030000 1444.400000 1643.030000 1444.880000 ;
+ RECT 1642.030000 1438.960000 1643.030000 1439.440000 ;
+ RECT 1642.030000 1422.640000 1643.030000 1423.120000 ;
+ RECT 1642.030000 1428.080000 1643.030000 1428.560000 ;
+ RECT 1642.030000 1433.520000 1643.030000 1434.000000 ;
+ RECT 1632.720000 1433.520000 1633.820000 1434.000000 ;
+ RECT 1632.720000 1428.080000 1633.820000 1428.560000 ;
+ RECT 1632.720000 1422.640000 1633.820000 1423.120000 ;
+ RECT 1632.720000 1411.760000 1633.820000 1412.240000 ;
+ RECT 1632.720000 1417.200000 1633.820000 1417.680000 ;
+ RECT 1642.030000 1417.200000 1643.030000 1417.680000 ;
+ RECT 1642.030000 1411.760000 1643.030000 1412.240000 ;
+ RECT 1642.030000 1400.880000 1643.030000 1401.360000 ;
+ RECT 1642.030000 1406.320000 1643.030000 1406.800000 ;
+ RECT 1632.720000 1400.880000 1633.820000 1401.360000 ;
+ RECT 1632.720000 1406.320000 1633.820000 1406.800000 ;
+ RECT 1587.720000 1444.400000 1588.820000 1444.880000 ;
+ RECT 1587.720000 1438.960000 1588.820000 1439.440000 ;
+ RECT 1587.720000 1433.520000 1588.820000 1434.000000 ;
+ RECT 1587.720000 1428.080000 1588.820000 1428.560000 ;
+ RECT 1587.720000 1422.640000 1588.820000 1423.120000 ;
+ RECT 1587.720000 1400.880000 1588.820000 1401.360000 ;
+ RECT 1587.720000 1406.320000 1588.820000 1406.800000 ;
+ RECT 1587.720000 1411.760000 1588.820000 1412.240000 ;
+ RECT 1587.720000 1417.200000 1588.820000 1417.680000 ;
+ RECT 1632.720000 1395.440000 1633.820000 1395.920000 ;
+ RECT 1632.720000 1390.000000 1633.820000 1390.480000 ;
+ RECT 1642.030000 1395.440000 1643.030000 1395.920000 ;
+ RECT 1642.030000 1390.000000 1643.030000 1390.480000 ;
+ RECT 1632.720000 1379.120000 1633.820000 1379.600000 ;
+ RECT 1632.720000 1373.680000 1633.820000 1374.160000 ;
+ RECT 1642.030000 1379.120000 1643.030000 1379.600000 ;
+ RECT 1642.030000 1373.680000 1643.030000 1374.160000 ;
+ RECT 1632.720000 1384.560000 1633.820000 1385.040000 ;
+ RECT 1642.030000 1384.560000 1643.030000 1385.040000 ;
+ RECT 1642.030000 1362.800000 1643.030000 1363.280000 ;
+ RECT 1642.030000 1368.240000 1643.030000 1368.720000 ;
+ RECT 1632.720000 1368.240000 1633.820000 1368.720000 ;
+ RECT 1632.720000 1362.800000 1633.820000 1363.280000 ;
+ RECT 1632.720000 1357.360000 1633.820000 1357.840000 ;
+ RECT 1632.720000 1351.920000 1633.820000 1352.400000 ;
+ RECT 1642.030000 1357.360000 1643.030000 1357.840000 ;
+ RECT 1642.030000 1351.920000 1643.030000 1352.400000 ;
+ RECT 1587.720000 1395.440000 1588.820000 1395.920000 ;
+ RECT 1587.720000 1390.000000 1588.820000 1390.480000 ;
+ RECT 1587.720000 1384.560000 1588.820000 1385.040000 ;
+ RECT 1587.720000 1379.120000 1588.820000 1379.600000 ;
+ RECT 1587.720000 1373.680000 1588.820000 1374.160000 ;
+ RECT 1587.720000 1368.240000 1588.820000 1368.720000 ;
+ RECT 1587.720000 1362.800000 1588.820000 1363.280000 ;
+ RECT 1587.720000 1357.360000 1588.820000 1357.840000 ;
+ RECT 1587.720000 1351.920000 1588.820000 1352.400000 ;
+ RECT 1542.720000 1542.320000 1543.820000 1542.800000 ;
+ RECT 1542.720000 1536.880000 1543.820000 1537.360000 ;
+ RECT 1542.720000 1531.440000 1543.820000 1531.920000 ;
+ RECT 1542.720000 1526.000000 1543.820000 1526.480000 ;
+ RECT 1497.720000 1542.320000 1498.820000 1542.800000 ;
+ RECT 1497.720000 1536.880000 1498.820000 1537.360000 ;
+ RECT 1497.720000 1531.440000 1498.820000 1531.920000 ;
+ RECT 1497.720000 1526.000000 1498.820000 1526.480000 ;
+ RECT 1542.720000 1515.120000 1543.820000 1515.600000 ;
+ RECT 1542.720000 1509.680000 1543.820000 1510.160000 ;
+ RECT 1542.720000 1504.240000 1543.820000 1504.720000 ;
+ RECT 1542.720000 1498.800000 1543.820000 1499.280000 ;
+ RECT 1542.720000 1520.560000 1543.820000 1521.040000 ;
+ RECT 1497.720000 1509.680000 1498.820000 1510.160000 ;
+ RECT 1497.720000 1504.240000 1498.820000 1504.720000 ;
+ RECT 1497.720000 1498.800000 1498.820000 1499.280000 ;
+ RECT 1497.720000 1515.120000 1498.820000 1515.600000 ;
+ RECT 1497.720000 1520.560000 1498.820000 1521.040000 ;
+ RECT 1452.720000 1542.320000 1453.820000 1542.800000 ;
+ RECT 1448.590000 1542.320000 1449.590000 1542.800000 ;
+ RECT 1452.720000 1536.880000 1453.820000 1537.360000 ;
+ RECT 1448.590000 1536.880000 1449.590000 1537.360000 ;
+ RECT 1452.720000 1531.440000 1453.820000 1531.920000 ;
+ RECT 1448.590000 1531.440000 1449.590000 1531.920000 ;
+ RECT 1452.720000 1526.000000 1453.820000 1526.480000 ;
+ RECT 1448.590000 1526.000000 1449.590000 1526.480000 ;
+ RECT 1452.720000 1520.560000 1453.820000 1521.040000 ;
+ RECT 1448.590000 1520.560000 1449.590000 1521.040000 ;
+ RECT 1452.720000 1515.120000 1453.820000 1515.600000 ;
+ RECT 1448.590000 1515.120000 1449.590000 1515.600000 ;
+ RECT 1452.720000 1504.240000 1453.820000 1504.720000 ;
+ RECT 1448.590000 1504.240000 1449.590000 1504.720000 ;
+ RECT 1452.720000 1498.800000 1453.820000 1499.280000 ;
+ RECT 1448.590000 1498.800000 1449.590000 1499.280000 ;
+ RECT 1452.720000 1509.680000 1453.820000 1510.160000 ;
+ RECT 1448.590000 1509.680000 1449.590000 1510.160000 ;
+ RECT 1542.720000 1493.360000 1543.820000 1493.840000 ;
+ RECT 1542.720000 1487.920000 1543.820000 1488.400000 ;
+ RECT 1542.720000 1482.480000 1543.820000 1482.960000 ;
+ RECT 1542.720000 1477.040000 1543.820000 1477.520000 ;
+ RECT 1497.720000 1493.360000 1498.820000 1493.840000 ;
+ RECT 1497.720000 1487.920000 1498.820000 1488.400000 ;
+ RECT 1497.720000 1482.480000 1498.820000 1482.960000 ;
+ RECT 1497.720000 1477.040000 1498.820000 1477.520000 ;
+ RECT 1542.720000 1466.160000 1543.820000 1466.640000 ;
+ RECT 1542.720000 1460.720000 1543.820000 1461.200000 ;
+ RECT 1542.720000 1455.280000 1543.820000 1455.760000 ;
+ RECT 1542.720000 1449.840000 1543.820000 1450.320000 ;
+ RECT 1542.720000 1471.600000 1543.820000 1472.080000 ;
+ RECT 1497.720000 1460.720000 1498.820000 1461.200000 ;
+ RECT 1497.720000 1455.280000 1498.820000 1455.760000 ;
+ RECT 1497.720000 1449.840000 1498.820000 1450.320000 ;
+ RECT 1497.720000 1466.160000 1498.820000 1466.640000 ;
+ RECT 1497.720000 1471.600000 1498.820000 1472.080000 ;
+ RECT 1452.720000 1493.360000 1453.820000 1493.840000 ;
+ RECT 1448.590000 1493.360000 1449.590000 1493.840000 ;
+ RECT 1452.720000 1487.920000 1453.820000 1488.400000 ;
+ RECT 1448.590000 1487.920000 1449.590000 1488.400000 ;
+ RECT 1452.720000 1482.480000 1453.820000 1482.960000 ;
+ RECT 1448.590000 1482.480000 1449.590000 1482.960000 ;
+ RECT 1452.720000 1477.040000 1453.820000 1477.520000 ;
+ RECT 1448.590000 1477.040000 1449.590000 1477.520000 ;
+ RECT 1452.720000 1471.600000 1453.820000 1472.080000 ;
+ RECT 1452.720000 1466.160000 1453.820000 1466.640000 ;
+ RECT 1448.590000 1471.600000 1449.590000 1472.080000 ;
+ RECT 1448.590000 1466.160000 1449.590000 1466.640000 ;
+ RECT 1452.720000 1460.720000 1453.820000 1461.200000 ;
+ RECT 1448.590000 1460.720000 1449.590000 1461.200000 ;
+ RECT 1452.720000 1455.280000 1453.820000 1455.760000 ;
+ RECT 1448.590000 1455.280000 1449.590000 1455.760000 ;
+ RECT 1452.720000 1449.840000 1453.820000 1450.320000 ;
+ RECT 1448.590000 1449.840000 1449.590000 1450.320000 ;
+ RECT 1542.720000 1444.400000 1543.820000 1444.880000 ;
+ RECT 1542.720000 1438.960000 1543.820000 1439.440000 ;
+ RECT 1542.720000 1433.520000 1543.820000 1434.000000 ;
+ RECT 1542.720000 1428.080000 1543.820000 1428.560000 ;
+ RECT 1542.720000 1422.640000 1543.820000 1423.120000 ;
+ RECT 1497.720000 1444.400000 1498.820000 1444.880000 ;
+ RECT 1497.720000 1438.960000 1498.820000 1439.440000 ;
+ RECT 1497.720000 1433.520000 1498.820000 1434.000000 ;
+ RECT 1497.720000 1428.080000 1498.820000 1428.560000 ;
+ RECT 1497.720000 1422.640000 1498.820000 1423.120000 ;
+ RECT 1542.720000 1417.200000 1543.820000 1417.680000 ;
+ RECT 1542.720000 1411.760000 1543.820000 1412.240000 ;
+ RECT 1542.720000 1406.320000 1543.820000 1406.800000 ;
+ RECT 1542.720000 1400.880000 1543.820000 1401.360000 ;
+ RECT 1497.720000 1411.760000 1498.820000 1412.240000 ;
+ RECT 1497.720000 1406.320000 1498.820000 1406.800000 ;
+ RECT 1497.720000 1400.880000 1498.820000 1401.360000 ;
+ RECT 1497.720000 1417.200000 1498.820000 1417.680000 ;
+ RECT 1452.720000 1444.400000 1453.820000 1444.880000 ;
+ RECT 1448.590000 1444.400000 1449.590000 1444.880000 ;
+ RECT 1452.720000 1438.960000 1453.820000 1439.440000 ;
+ RECT 1448.590000 1438.960000 1449.590000 1439.440000 ;
+ RECT 1452.720000 1433.520000 1453.820000 1434.000000 ;
+ RECT 1448.590000 1433.520000 1449.590000 1434.000000 ;
+ RECT 1452.720000 1422.640000 1453.820000 1423.120000 ;
+ RECT 1448.590000 1422.640000 1449.590000 1423.120000 ;
+ RECT 1448.590000 1428.080000 1449.590000 1428.560000 ;
+ RECT 1452.720000 1428.080000 1453.820000 1428.560000 ;
+ RECT 1452.720000 1417.200000 1453.820000 1417.680000 ;
+ RECT 1448.590000 1417.200000 1449.590000 1417.680000 ;
+ RECT 1452.720000 1411.760000 1453.820000 1412.240000 ;
+ RECT 1448.590000 1411.760000 1449.590000 1412.240000 ;
+ RECT 1452.720000 1406.320000 1453.820000 1406.800000 ;
+ RECT 1448.590000 1406.320000 1449.590000 1406.800000 ;
+ RECT 1452.720000 1400.880000 1453.820000 1401.360000 ;
+ RECT 1448.590000 1400.880000 1449.590000 1401.360000 ;
+ RECT 1542.720000 1395.440000 1543.820000 1395.920000 ;
+ RECT 1542.720000 1390.000000 1543.820000 1390.480000 ;
+ RECT 1542.720000 1384.560000 1543.820000 1385.040000 ;
+ RECT 1542.720000 1379.120000 1543.820000 1379.600000 ;
+ RECT 1542.720000 1373.680000 1543.820000 1374.160000 ;
+ RECT 1497.720000 1395.440000 1498.820000 1395.920000 ;
+ RECT 1497.720000 1390.000000 1498.820000 1390.480000 ;
+ RECT 1497.720000 1384.560000 1498.820000 1385.040000 ;
+ RECT 1497.720000 1379.120000 1498.820000 1379.600000 ;
+ RECT 1497.720000 1373.680000 1498.820000 1374.160000 ;
+ RECT 1542.720000 1351.920000 1543.820000 1352.400000 ;
+ RECT 1542.720000 1357.360000 1543.820000 1357.840000 ;
+ RECT 1542.720000 1362.800000 1543.820000 1363.280000 ;
+ RECT 1542.720000 1368.240000 1543.820000 1368.720000 ;
+ RECT 1497.720000 1351.920000 1498.820000 1352.400000 ;
+ RECT 1497.720000 1357.360000 1498.820000 1357.840000 ;
+ RECT 1497.720000 1362.800000 1498.820000 1363.280000 ;
+ RECT 1497.720000 1368.240000 1498.820000 1368.720000 ;
+ RECT 1452.720000 1395.440000 1453.820000 1395.920000 ;
+ RECT 1448.590000 1395.440000 1449.590000 1395.920000 ;
+ RECT 1452.720000 1390.000000 1453.820000 1390.480000 ;
+ RECT 1448.590000 1390.000000 1449.590000 1390.480000 ;
+ RECT 1452.720000 1379.120000 1453.820000 1379.600000 ;
+ RECT 1448.590000 1379.120000 1449.590000 1379.600000 ;
+ RECT 1452.720000 1373.680000 1453.820000 1374.160000 ;
+ RECT 1448.590000 1373.680000 1449.590000 1374.160000 ;
+ RECT 1452.720000 1384.560000 1453.820000 1385.040000 ;
+ RECT 1448.590000 1384.560000 1449.590000 1385.040000 ;
+ RECT 1452.720000 1368.240000 1453.820000 1368.720000 ;
+ RECT 1448.590000 1368.240000 1449.590000 1368.720000 ;
+ RECT 1452.720000 1362.800000 1453.820000 1363.280000 ;
+ RECT 1448.590000 1362.800000 1449.590000 1363.280000 ;
+ RECT 1452.720000 1357.360000 1453.820000 1357.840000 ;
+ RECT 1452.720000 1351.920000 1453.820000 1352.400000 ;
+ RECT 1448.590000 1357.360000 1449.590000 1357.840000 ;
+ RECT 1448.590000 1351.920000 1449.590000 1352.400000 ;
+ RECT 1445.760000 1743.050000 1645.860000 1744.050000 ;
+ RECT 1445.760000 1349.910000 1645.860000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 1347.060000 1449.590000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1448.590000 1746.580000 1449.590000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 1347.060000 1643.030000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1642.030000 1746.580000 1643.030000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 1349.910000 1446.760000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 1349.910000 1645.860000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1445.760000 1743.050000 1446.760000 1744.050000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1644.860000 1743.050000 1645.860000 1744.050000 ;
+ END
+# end of P/G pin shape extracted from block 'DSP'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 3349.660000 1654.690000 3379.920000 ;
+ RECT 1847.130000 3349.660000 1848.130000 3379.920000 ;
+ RECT 1657.820000 3352.510000 1658.920000 3376.560000 ;
+ RECT 1702.820000 3352.510000 1703.920000 3376.560000 ;
+ RECT 1747.820000 3352.510000 1748.920000 3376.560000 ;
+ RECT 1792.820000 3352.510000 1793.920000 3376.560000 ;
+ RECT 1837.820000 3352.510000 1838.920000 3376.560000 ;
+ LAYER met3 ;
+ RECT 1847.130000 3365.400000 1848.130000 3365.880000 ;
+ RECT 1847.130000 3370.840000 1848.130000 3371.320000 ;
+ RECT 1837.820000 3370.840000 1838.920000 3371.320000 ;
+ RECT 1837.820000 3365.400000 1838.920000 3365.880000 ;
+ RECT 1792.820000 3365.400000 1793.920000 3365.880000 ;
+ RECT 1792.820000 3370.840000 1793.920000 3371.320000 ;
+ RECT 1702.820000 3365.400000 1703.920000 3365.880000 ;
+ RECT 1747.820000 3365.400000 1748.920000 3365.880000 ;
+ RECT 1747.820000 3370.840000 1748.920000 3371.320000 ;
+ RECT 1702.820000 3370.840000 1703.920000 3371.320000 ;
+ RECT 1653.690000 3365.400000 1654.690000 3365.880000 ;
+ RECT 1657.820000 3365.400000 1658.920000 3365.880000 ;
+ RECT 1657.820000 3370.840000 1658.920000 3371.320000 ;
+ RECT 1653.690000 3370.840000 1654.690000 3371.320000 ;
+ RECT 1847.130000 3354.520000 1848.130000 3355.000000 ;
+ RECT 1847.130000 3359.960000 1848.130000 3360.440000 ;
+ RECT 1837.820000 3359.960000 1838.920000 3360.440000 ;
+ RECT 1837.820000 3354.520000 1838.920000 3355.000000 ;
+ RECT 1792.820000 3354.520000 1793.920000 3355.000000 ;
+ RECT 1792.820000 3359.960000 1793.920000 3360.440000 ;
+ RECT 1702.820000 3354.520000 1703.920000 3355.000000 ;
+ RECT 1747.820000 3354.520000 1748.920000 3355.000000 ;
+ RECT 1747.820000 3359.960000 1748.920000 3360.440000 ;
+ RECT 1702.820000 3359.960000 1703.920000 3360.440000 ;
+ RECT 1653.690000 3359.960000 1654.690000 3360.440000 ;
+ RECT 1657.820000 3359.960000 1658.920000 3360.440000 ;
+ RECT 1653.690000 3354.520000 1654.690000 3355.000000 ;
+ RECT 1657.820000 3354.520000 1658.920000 3355.000000 ;
+ RECT 1650.860000 3375.560000 1850.960000 3376.560000 ;
+ RECT 1650.860000 3352.510000 1850.960000 3353.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 3349.660000 1654.690000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 3378.920000 1654.690000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 3349.660000 1848.130000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 3378.920000 1848.130000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 3352.510000 1651.860000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 3352.510000 1850.960000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 3375.560000 1651.860000 3376.560000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 3375.560000 1850.960000 3376.560000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 1349.910000 1838.920000 1543.280000 ;
+ RECT 1792.820000 1349.910000 1793.920000 1543.280000 ;
+ RECT 1847.130000 1347.060000 1848.130000 1547.320000 ;
+ RECT 1747.820000 1349.910000 1748.920000 1543.280000 ;
+ RECT 1702.820000 1349.910000 1703.920000 1543.280000 ;
+ RECT 1657.820000 1349.910000 1658.920000 1543.280000 ;
+ RECT 1653.690000 1347.060000 1654.690000 1547.320000 ;
+ LAYER met3 ;
+ RECT 1837.820000 1536.880000 1838.920000 1537.360000 ;
+ RECT 1847.130000 1536.880000 1848.130000 1537.360000 ;
+ RECT 1847.130000 1526.000000 1848.130000 1526.480000 ;
+ RECT 1847.130000 1531.440000 1848.130000 1531.920000 ;
+ RECT 1837.820000 1531.440000 1838.920000 1531.920000 ;
+ RECT 1837.820000 1526.000000 1838.920000 1526.480000 ;
+ RECT 1837.820000 1520.560000 1838.920000 1521.040000 ;
+ RECT 1837.820000 1515.120000 1838.920000 1515.600000 ;
+ RECT 1847.130000 1520.560000 1848.130000 1521.040000 ;
+ RECT 1847.130000 1515.120000 1848.130000 1515.600000 ;
+ RECT 1837.820000 1498.800000 1838.920000 1499.280000 ;
+ RECT 1837.820000 1504.240000 1838.920000 1504.720000 ;
+ RECT 1847.130000 1504.240000 1848.130000 1504.720000 ;
+ RECT 1847.130000 1498.800000 1848.130000 1499.280000 ;
+ RECT 1837.820000 1509.680000 1838.920000 1510.160000 ;
+ RECT 1847.130000 1509.680000 1848.130000 1510.160000 ;
+ RECT 1792.820000 1536.880000 1793.920000 1537.360000 ;
+ RECT 1792.820000 1531.440000 1793.920000 1531.920000 ;
+ RECT 1792.820000 1526.000000 1793.920000 1526.480000 ;
+ RECT 1792.820000 1520.560000 1793.920000 1521.040000 ;
+ RECT 1792.820000 1498.800000 1793.920000 1499.280000 ;
+ RECT 1792.820000 1504.240000 1793.920000 1504.720000 ;
+ RECT 1792.820000 1509.680000 1793.920000 1510.160000 ;
+ RECT 1792.820000 1515.120000 1793.920000 1515.600000 ;
+ RECT 1847.130000 1487.920000 1848.130000 1488.400000 ;
+ RECT 1847.130000 1493.360000 1848.130000 1493.840000 ;
+ RECT 1837.820000 1493.360000 1838.920000 1493.840000 ;
+ RECT 1837.820000 1487.920000 1838.920000 1488.400000 ;
+ RECT 1837.820000 1482.480000 1838.920000 1482.960000 ;
+ RECT 1837.820000 1477.040000 1838.920000 1477.520000 ;
+ RECT 1847.130000 1482.480000 1848.130000 1482.960000 ;
+ RECT 1847.130000 1477.040000 1848.130000 1477.520000 ;
+ RECT 1847.130000 1460.720000 1848.130000 1461.200000 ;
+ RECT 1847.130000 1466.160000 1848.130000 1466.640000 ;
+ RECT 1847.130000 1471.600000 1848.130000 1472.080000 ;
+ RECT 1837.820000 1466.160000 1838.920000 1466.640000 ;
+ RECT 1837.820000 1460.720000 1838.920000 1461.200000 ;
+ RECT 1837.820000 1471.600000 1838.920000 1472.080000 ;
+ RECT 1837.820000 1455.280000 1838.920000 1455.760000 ;
+ RECT 1837.820000 1449.840000 1838.920000 1450.320000 ;
+ RECT 1847.130000 1455.280000 1848.130000 1455.760000 ;
+ RECT 1847.130000 1449.840000 1848.130000 1450.320000 ;
+ RECT 1792.820000 1493.360000 1793.920000 1493.840000 ;
+ RECT 1792.820000 1487.920000 1793.920000 1488.400000 ;
+ RECT 1792.820000 1482.480000 1793.920000 1482.960000 ;
+ RECT 1792.820000 1477.040000 1793.920000 1477.520000 ;
+ RECT 1792.820000 1466.160000 1793.920000 1466.640000 ;
+ RECT 1792.820000 1460.720000 1793.920000 1461.200000 ;
+ RECT 1792.820000 1455.280000 1793.920000 1455.760000 ;
+ RECT 1792.820000 1449.840000 1793.920000 1450.320000 ;
+ RECT 1792.820000 1471.600000 1793.920000 1472.080000 ;
+ RECT 1747.820000 1536.880000 1748.920000 1537.360000 ;
+ RECT 1747.820000 1531.440000 1748.920000 1531.920000 ;
+ RECT 1747.820000 1526.000000 1748.920000 1526.480000 ;
+ RECT 1702.820000 1536.880000 1703.920000 1537.360000 ;
+ RECT 1702.820000 1531.440000 1703.920000 1531.920000 ;
+ RECT 1702.820000 1526.000000 1703.920000 1526.480000 ;
+ RECT 1747.820000 1509.680000 1748.920000 1510.160000 ;
+ RECT 1747.820000 1504.240000 1748.920000 1504.720000 ;
+ RECT 1747.820000 1498.800000 1748.920000 1499.280000 ;
+ RECT 1747.820000 1515.120000 1748.920000 1515.600000 ;
+ RECT 1747.820000 1520.560000 1748.920000 1521.040000 ;
+ RECT 1702.820000 1520.560000 1703.920000 1521.040000 ;
+ RECT 1702.820000 1509.680000 1703.920000 1510.160000 ;
+ RECT 1702.820000 1504.240000 1703.920000 1504.720000 ;
+ RECT 1702.820000 1498.800000 1703.920000 1499.280000 ;
+ RECT 1702.820000 1515.120000 1703.920000 1515.600000 ;
+ RECT 1657.820000 1536.880000 1658.920000 1537.360000 ;
+ RECT 1653.690000 1536.880000 1654.690000 1537.360000 ;
+ RECT 1653.690000 1531.440000 1654.690000 1531.920000 ;
+ RECT 1657.820000 1531.440000 1658.920000 1531.920000 ;
+ RECT 1657.820000 1526.000000 1658.920000 1526.480000 ;
+ RECT 1653.690000 1526.000000 1654.690000 1526.480000 ;
+ RECT 1657.820000 1520.560000 1658.920000 1521.040000 ;
+ RECT 1653.690000 1520.560000 1654.690000 1521.040000 ;
+ RECT 1657.820000 1515.120000 1658.920000 1515.600000 ;
+ RECT 1653.690000 1515.120000 1654.690000 1515.600000 ;
+ RECT 1657.820000 1504.240000 1658.920000 1504.720000 ;
+ RECT 1653.690000 1504.240000 1654.690000 1504.720000 ;
+ RECT 1657.820000 1498.800000 1658.920000 1499.280000 ;
+ RECT 1653.690000 1498.800000 1654.690000 1499.280000 ;
+ RECT 1657.820000 1509.680000 1658.920000 1510.160000 ;
+ RECT 1653.690000 1509.680000 1654.690000 1510.160000 ;
+ RECT 1747.820000 1493.360000 1748.920000 1493.840000 ;
+ RECT 1747.820000 1487.920000 1748.920000 1488.400000 ;
+ RECT 1747.820000 1482.480000 1748.920000 1482.960000 ;
+ RECT 1747.820000 1477.040000 1748.920000 1477.520000 ;
+ RECT 1702.820000 1493.360000 1703.920000 1493.840000 ;
+ RECT 1702.820000 1487.920000 1703.920000 1488.400000 ;
+ RECT 1702.820000 1482.480000 1703.920000 1482.960000 ;
+ RECT 1702.820000 1477.040000 1703.920000 1477.520000 ;
+ RECT 1747.820000 1466.160000 1748.920000 1466.640000 ;
+ RECT 1747.820000 1449.840000 1748.920000 1450.320000 ;
+ RECT 1747.820000 1455.280000 1748.920000 1455.760000 ;
+ RECT 1747.820000 1460.720000 1748.920000 1461.200000 ;
+ RECT 1747.820000 1471.600000 1748.920000 1472.080000 ;
+ RECT 1702.820000 1449.840000 1703.920000 1450.320000 ;
+ RECT 1702.820000 1455.280000 1703.920000 1455.760000 ;
+ RECT 1702.820000 1460.720000 1703.920000 1461.200000 ;
+ RECT 1702.820000 1466.160000 1703.920000 1466.640000 ;
+ RECT 1702.820000 1471.600000 1703.920000 1472.080000 ;
+ RECT 1657.820000 1493.360000 1658.920000 1493.840000 ;
+ RECT 1653.690000 1493.360000 1654.690000 1493.840000 ;
+ RECT 1657.820000 1487.920000 1658.920000 1488.400000 ;
+ RECT 1653.690000 1487.920000 1654.690000 1488.400000 ;
+ RECT 1657.820000 1482.480000 1658.920000 1482.960000 ;
+ RECT 1653.690000 1482.480000 1654.690000 1482.960000 ;
+ RECT 1657.820000 1477.040000 1658.920000 1477.520000 ;
+ RECT 1653.690000 1477.040000 1654.690000 1477.520000 ;
+ RECT 1657.820000 1471.600000 1658.920000 1472.080000 ;
+ RECT 1657.820000 1466.160000 1658.920000 1466.640000 ;
+ RECT 1653.690000 1471.600000 1654.690000 1472.080000 ;
+ RECT 1653.690000 1466.160000 1654.690000 1466.640000 ;
+ RECT 1657.820000 1460.720000 1658.920000 1461.200000 ;
+ RECT 1653.690000 1460.720000 1654.690000 1461.200000 ;
+ RECT 1657.820000 1455.280000 1658.920000 1455.760000 ;
+ RECT 1653.690000 1455.280000 1654.690000 1455.760000 ;
+ RECT 1657.820000 1449.840000 1658.920000 1450.320000 ;
+ RECT 1653.690000 1449.840000 1654.690000 1450.320000 ;
+ RECT 1837.820000 1444.400000 1838.920000 1444.880000 ;
+ RECT 1837.820000 1438.960000 1838.920000 1439.440000 ;
+ RECT 1847.130000 1444.400000 1848.130000 1444.880000 ;
+ RECT 1847.130000 1438.960000 1848.130000 1439.440000 ;
+ RECT 1847.130000 1422.640000 1848.130000 1423.120000 ;
+ RECT 1847.130000 1428.080000 1848.130000 1428.560000 ;
+ RECT 1847.130000 1433.520000 1848.130000 1434.000000 ;
+ RECT 1837.820000 1433.520000 1838.920000 1434.000000 ;
+ RECT 1837.820000 1428.080000 1838.920000 1428.560000 ;
+ RECT 1837.820000 1422.640000 1838.920000 1423.120000 ;
+ RECT 1837.820000 1411.760000 1838.920000 1412.240000 ;
+ RECT 1837.820000 1417.200000 1838.920000 1417.680000 ;
+ RECT 1847.130000 1417.200000 1848.130000 1417.680000 ;
+ RECT 1847.130000 1411.760000 1848.130000 1412.240000 ;
+ RECT 1847.130000 1400.880000 1848.130000 1401.360000 ;
+ RECT 1847.130000 1406.320000 1848.130000 1406.800000 ;
+ RECT 1837.820000 1400.880000 1838.920000 1401.360000 ;
+ RECT 1837.820000 1406.320000 1838.920000 1406.800000 ;
+ RECT 1792.820000 1444.400000 1793.920000 1444.880000 ;
+ RECT 1792.820000 1438.960000 1793.920000 1439.440000 ;
+ RECT 1792.820000 1433.520000 1793.920000 1434.000000 ;
+ RECT 1792.820000 1428.080000 1793.920000 1428.560000 ;
+ RECT 1792.820000 1422.640000 1793.920000 1423.120000 ;
+ RECT 1792.820000 1400.880000 1793.920000 1401.360000 ;
+ RECT 1792.820000 1406.320000 1793.920000 1406.800000 ;
+ RECT 1792.820000 1411.760000 1793.920000 1412.240000 ;
+ RECT 1792.820000 1417.200000 1793.920000 1417.680000 ;
+ RECT 1837.820000 1395.440000 1838.920000 1395.920000 ;
+ RECT 1837.820000 1390.000000 1838.920000 1390.480000 ;
+ RECT 1847.130000 1395.440000 1848.130000 1395.920000 ;
+ RECT 1847.130000 1390.000000 1848.130000 1390.480000 ;
+ RECT 1837.820000 1379.120000 1838.920000 1379.600000 ;
+ RECT 1837.820000 1373.680000 1838.920000 1374.160000 ;
+ RECT 1847.130000 1379.120000 1848.130000 1379.600000 ;
+ RECT 1847.130000 1373.680000 1848.130000 1374.160000 ;
+ RECT 1837.820000 1384.560000 1838.920000 1385.040000 ;
+ RECT 1847.130000 1384.560000 1848.130000 1385.040000 ;
+ RECT 1847.130000 1362.800000 1848.130000 1363.280000 ;
+ RECT 1847.130000 1368.240000 1848.130000 1368.720000 ;
+ RECT 1837.820000 1368.240000 1838.920000 1368.720000 ;
+ RECT 1837.820000 1362.800000 1838.920000 1363.280000 ;
+ RECT 1837.820000 1357.360000 1838.920000 1357.840000 ;
+ RECT 1837.820000 1351.920000 1838.920000 1352.400000 ;
+ RECT 1847.130000 1357.360000 1848.130000 1357.840000 ;
+ RECT 1847.130000 1351.920000 1848.130000 1352.400000 ;
+ RECT 1792.820000 1395.440000 1793.920000 1395.920000 ;
+ RECT 1792.820000 1390.000000 1793.920000 1390.480000 ;
+ RECT 1792.820000 1384.560000 1793.920000 1385.040000 ;
+ RECT 1792.820000 1379.120000 1793.920000 1379.600000 ;
+ RECT 1792.820000 1373.680000 1793.920000 1374.160000 ;
+ RECT 1792.820000 1368.240000 1793.920000 1368.720000 ;
+ RECT 1792.820000 1362.800000 1793.920000 1363.280000 ;
+ RECT 1792.820000 1357.360000 1793.920000 1357.840000 ;
+ RECT 1792.820000 1351.920000 1793.920000 1352.400000 ;
+ RECT 1747.820000 1444.400000 1748.920000 1444.880000 ;
+ RECT 1747.820000 1438.960000 1748.920000 1439.440000 ;
+ RECT 1747.820000 1433.520000 1748.920000 1434.000000 ;
+ RECT 1747.820000 1428.080000 1748.920000 1428.560000 ;
+ RECT 1747.820000 1422.640000 1748.920000 1423.120000 ;
+ RECT 1702.820000 1444.400000 1703.920000 1444.880000 ;
+ RECT 1702.820000 1438.960000 1703.920000 1439.440000 ;
+ RECT 1702.820000 1433.520000 1703.920000 1434.000000 ;
+ RECT 1702.820000 1428.080000 1703.920000 1428.560000 ;
+ RECT 1702.820000 1422.640000 1703.920000 1423.120000 ;
+ RECT 1747.820000 1417.200000 1748.920000 1417.680000 ;
+ RECT 1747.820000 1411.760000 1748.920000 1412.240000 ;
+ RECT 1747.820000 1406.320000 1748.920000 1406.800000 ;
+ RECT 1747.820000 1400.880000 1748.920000 1401.360000 ;
+ RECT 1702.820000 1411.760000 1703.920000 1412.240000 ;
+ RECT 1702.820000 1406.320000 1703.920000 1406.800000 ;
+ RECT 1702.820000 1400.880000 1703.920000 1401.360000 ;
+ RECT 1702.820000 1417.200000 1703.920000 1417.680000 ;
+ RECT 1657.820000 1444.400000 1658.920000 1444.880000 ;
+ RECT 1653.690000 1444.400000 1654.690000 1444.880000 ;
+ RECT 1657.820000 1438.960000 1658.920000 1439.440000 ;
+ RECT 1653.690000 1438.960000 1654.690000 1439.440000 ;
+ RECT 1657.820000 1433.520000 1658.920000 1434.000000 ;
+ RECT 1653.690000 1433.520000 1654.690000 1434.000000 ;
+ RECT 1657.820000 1422.640000 1658.920000 1423.120000 ;
+ RECT 1653.690000 1422.640000 1654.690000 1423.120000 ;
+ RECT 1653.690000 1428.080000 1654.690000 1428.560000 ;
+ RECT 1657.820000 1428.080000 1658.920000 1428.560000 ;
+ RECT 1657.820000 1417.200000 1658.920000 1417.680000 ;
+ RECT 1653.690000 1417.200000 1654.690000 1417.680000 ;
+ RECT 1657.820000 1411.760000 1658.920000 1412.240000 ;
+ RECT 1653.690000 1411.760000 1654.690000 1412.240000 ;
+ RECT 1657.820000 1406.320000 1658.920000 1406.800000 ;
+ RECT 1653.690000 1406.320000 1654.690000 1406.800000 ;
+ RECT 1657.820000 1400.880000 1658.920000 1401.360000 ;
+ RECT 1653.690000 1400.880000 1654.690000 1401.360000 ;
+ RECT 1747.820000 1395.440000 1748.920000 1395.920000 ;
+ RECT 1747.820000 1390.000000 1748.920000 1390.480000 ;
+ RECT 1747.820000 1384.560000 1748.920000 1385.040000 ;
+ RECT 1747.820000 1379.120000 1748.920000 1379.600000 ;
+ RECT 1747.820000 1373.680000 1748.920000 1374.160000 ;
+ RECT 1702.820000 1395.440000 1703.920000 1395.920000 ;
+ RECT 1702.820000 1390.000000 1703.920000 1390.480000 ;
+ RECT 1702.820000 1384.560000 1703.920000 1385.040000 ;
+ RECT 1702.820000 1379.120000 1703.920000 1379.600000 ;
+ RECT 1702.820000 1373.680000 1703.920000 1374.160000 ;
+ RECT 1747.820000 1351.920000 1748.920000 1352.400000 ;
+ RECT 1747.820000 1357.360000 1748.920000 1357.840000 ;
+ RECT 1747.820000 1362.800000 1748.920000 1363.280000 ;
+ RECT 1747.820000 1368.240000 1748.920000 1368.720000 ;
+ RECT 1702.820000 1351.920000 1703.920000 1352.400000 ;
+ RECT 1702.820000 1357.360000 1703.920000 1357.840000 ;
+ RECT 1702.820000 1362.800000 1703.920000 1363.280000 ;
+ RECT 1702.820000 1368.240000 1703.920000 1368.720000 ;
+ RECT 1657.820000 1395.440000 1658.920000 1395.920000 ;
+ RECT 1653.690000 1395.440000 1654.690000 1395.920000 ;
+ RECT 1657.820000 1390.000000 1658.920000 1390.480000 ;
+ RECT 1653.690000 1390.000000 1654.690000 1390.480000 ;
+ RECT 1657.820000 1379.120000 1658.920000 1379.600000 ;
+ RECT 1653.690000 1379.120000 1654.690000 1379.600000 ;
+ RECT 1657.820000 1373.680000 1658.920000 1374.160000 ;
+ RECT 1653.690000 1373.680000 1654.690000 1374.160000 ;
+ RECT 1657.820000 1384.560000 1658.920000 1385.040000 ;
+ RECT 1653.690000 1384.560000 1654.690000 1385.040000 ;
+ RECT 1657.820000 1368.240000 1658.920000 1368.720000 ;
+ RECT 1653.690000 1368.240000 1654.690000 1368.720000 ;
+ RECT 1657.820000 1362.800000 1658.920000 1363.280000 ;
+ RECT 1653.690000 1362.800000 1654.690000 1363.280000 ;
+ RECT 1657.820000 1357.360000 1658.920000 1357.840000 ;
+ RECT 1657.820000 1351.920000 1658.920000 1352.400000 ;
+ RECT 1653.690000 1357.360000 1654.690000 1357.840000 ;
+ RECT 1653.690000 1351.920000 1654.690000 1352.400000 ;
+ RECT 1650.860000 1542.280000 1850.960000 1543.280000 ;
+ RECT 1650.860000 1349.910000 1850.960000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 1347.060000 1654.690000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 1546.320000 1654.690000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 1347.060000 1848.130000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 1546.320000 1848.130000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1349.910000 1651.860000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1349.910000 1850.960000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1542.280000 1651.860000 1543.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1542.280000 1850.960000 1543.280000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 1149.650000 1838.920000 1343.020000 ;
+ RECT 1792.820000 1149.650000 1793.920000 1343.020000 ;
+ RECT 1847.130000 1146.800000 1848.130000 1347.060000 ;
+ RECT 1747.820000 1149.650000 1748.920000 1343.020000 ;
+ RECT 1702.820000 1149.650000 1703.920000 1343.020000 ;
+ RECT 1657.820000 1149.650000 1658.920000 1343.020000 ;
+ RECT 1653.690000 1146.800000 1654.690000 1347.060000 ;
+ LAYER met3 ;
+ RECT 1837.820000 1336.620000 1838.920000 1337.100000 ;
+ RECT 1847.130000 1336.620000 1848.130000 1337.100000 ;
+ RECT 1847.130000 1325.740000 1848.130000 1326.220000 ;
+ RECT 1847.130000 1331.180000 1848.130000 1331.660000 ;
+ RECT 1837.820000 1331.180000 1838.920000 1331.660000 ;
+ RECT 1837.820000 1325.740000 1838.920000 1326.220000 ;
+ RECT 1837.820000 1320.300000 1838.920000 1320.780000 ;
+ RECT 1837.820000 1314.860000 1838.920000 1315.340000 ;
+ RECT 1847.130000 1320.300000 1848.130000 1320.780000 ;
+ RECT 1847.130000 1314.860000 1848.130000 1315.340000 ;
+ RECT 1837.820000 1298.540000 1838.920000 1299.020000 ;
+ RECT 1837.820000 1303.980000 1838.920000 1304.460000 ;
+ RECT 1847.130000 1303.980000 1848.130000 1304.460000 ;
+ RECT 1847.130000 1298.540000 1848.130000 1299.020000 ;
+ RECT 1837.820000 1309.420000 1838.920000 1309.900000 ;
+ RECT 1847.130000 1309.420000 1848.130000 1309.900000 ;
+ RECT 1792.820000 1336.620000 1793.920000 1337.100000 ;
+ RECT 1792.820000 1331.180000 1793.920000 1331.660000 ;
+ RECT 1792.820000 1325.740000 1793.920000 1326.220000 ;
+ RECT 1792.820000 1320.300000 1793.920000 1320.780000 ;
+ RECT 1792.820000 1298.540000 1793.920000 1299.020000 ;
+ RECT 1792.820000 1303.980000 1793.920000 1304.460000 ;
+ RECT 1792.820000 1309.420000 1793.920000 1309.900000 ;
+ RECT 1792.820000 1314.860000 1793.920000 1315.340000 ;
+ RECT 1847.130000 1287.660000 1848.130000 1288.140000 ;
+ RECT 1847.130000 1293.100000 1848.130000 1293.580000 ;
+ RECT 1837.820000 1293.100000 1838.920000 1293.580000 ;
+ RECT 1837.820000 1287.660000 1838.920000 1288.140000 ;
+ RECT 1837.820000 1282.220000 1838.920000 1282.700000 ;
+ RECT 1837.820000 1276.780000 1838.920000 1277.260000 ;
+ RECT 1847.130000 1282.220000 1848.130000 1282.700000 ;
+ RECT 1847.130000 1276.780000 1848.130000 1277.260000 ;
+ RECT 1847.130000 1260.460000 1848.130000 1260.940000 ;
+ RECT 1847.130000 1265.900000 1848.130000 1266.380000 ;
+ RECT 1847.130000 1271.340000 1848.130000 1271.820000 ;
+ RECT 1837.820000 1265.900000 1838.920000 1266.380000 ;
+ RECT 1837.820000 1260.460000 1838.920000 1260.940000 ;
+ RECT 1837.820000 1271.340000 1838.920000 1271.820000 ;
+ RECT 1837.820000 1255.020000 1838.920000 1255.500000 ;
+ RECT 1837.820000 1249.580000 1838.920000 1250.060000 ;
+ RECT 1847.130000 1255.020000 1848.130000 1255.500000 ;
+ RECT 1847.130000 1249.580000 1848.130000 1250.060000 ;
+ RECT 1792.820000 1293.100000 1793.920000 1293.580000 ;
+ RECT 1792.820000 1287.660000 1793.920000 1288.140000 ;
+ RECT 1792.820000 1282.220000 1793.920000 1282.700000 ;
+ RECT 1792.820000 1276.780000 1793.920000 1277.260000 ;
+ RECT 1792.820000 1265.900000 1793.920000 1266.380000 ;
+ RECT 1792.820000 1260.460000 1793.920000 1260.940000 ;
+ RECT 1792.820000 1255.020000 1793.920000 1255.500000 ;
+ RECT 1792.820000 1249.580000 1793.920000 1250.060000 ;
+ RECT 1792.820000 1271.340000 1793.920000 1271.820000 ;
+ RECT 1747.820000 1336.620000 1748.920000 1337.100000 ;
+ RECT 1747.820000 1331.180000 1748.920000 1331.660000 ;
+ RECT 1747.820000 1325.740000 1748.920000 1326.220000 ;
+ RECT 1702.820000 1336.620000 1703.920000 1337.100000 ;
+ RECT 1702.820000 1331.180000 1703.920000 1331.660000 ;
+ RECT 1702.820000 1325.740000 1703.920000 1326.220000 ;
+ RECT 1747.820000 1309.420000 1748.920000 1309.900000 ;
+ RECT 1747.820000 1303.980000 1748.920000 1304.460000 ;
+ RECT 1747.820000 1298.540000 1748.920000 1299.020000 ;
+ RECT 1747.820000 1314.860000 1748.920000 1315.340000 ;
+ RECT 1747.820000 1320.300000 1748.920000 1320.780000 ;
+ RECT 1702.820000 1320.300000 1703.920000 1320.780000 ;
+ RECT 1702.820000 1309.420000 1703.920000 1309.900000 ;
+ RECT 1702.820000 1303.980000 1703.920000 1304.460000 ;
+ RECT 1702.820000 1298.540000 1703.920000 1299.020000 ;
+ RECT 1702.820000 1314.860000 1703.920000 1315.340000 ;
+ RECT 1657.820000 1336.620000 1658.920000 1337.100000 ;
+ RECT 1653.690000 1336.620000 1654.690000 1337.100000 ;
+ RECT 1653.690000 1331.180000 1654.690000 1331.660000 ;
+ RECT 1657.820000 1331.180000 1658.920000 1331.660000 ;
+ RECT 1657.820000 1325.740000 1658.920000 1326.220000 ;
+ RECT 1653.690000 1325.740000 1654.690000 1326.220000 ;
+ RECT 1657.820000 1320.300000 1658.920000 1320.780000 ;
+ RECT 1653.690000 1320.300000 1654.690000 1320.780000 ;
+ RECT 1657.820000 1314.860000 1658.920000 1315.340000 ;
+ RECT 1653.690000 1314.860000 1654.690000 1315.340000 ;
+ RECT 1657.820000 1303.980000 1658.920000 1304.460000 ;
+ RECT 1653.690000 1303.980000 1654.690000 1304.460000 ;
+ RECT 1657.820000 1298.540000 1658.920000 1299.020000 ;
+ RECT 1653.690000 1298.540000 1654.690000 1299.020000 ;
+ RECT 1657.820000 1309.420000 1658.920000 1309.900000 ;
+ RECT 1653.690000 1309.420000 1654.690000 1309.900000 ;
+ RECT 1747.820000 1293.100000 1748.920000 1293.580000 ;
+ RECT 1747.820000 1287.660000 1748.920000 1288.140000 ;
+ RECT 1747.820000 1282.220000 1748.920000 1282.700000 ;
+ RECT 1747.820000 1276.780000 1748.920000 1277.260000 ;
+ RECT 1702.820000 1293.100000 1703.920000 1293.580000 ;
+ RECT 1702.820000 1287.660000 1703.920000 1288.140000 ;
+ RECT 1702.820000 1282.220000 1703.920000 1282.700000 ;
+ RECT 1702.820000 1276.780000 1703.920000 1277.260000 ;
+ RECT 1747.820000 1265.900000 1748.920000 1266.380000 ;
+ RECT 1747.820000 1249.580000 1748.920000 1250.060000 ;
+ RECT 1747.820000 1255.020000 1748.920000 1255.500000 ;
+ RECT 1747.820000 1260.460000 1748.920000 1260.940000 ;
+ RECT 1747.820000 1271.340000 1748.920000 1271.820000 ;
+ RECT 1702.820000 1249.580000 1703.920000 1250.060000 ;
+ RECT 1702.820000 1255.020000 1703.920000 1255.500000 ;
+ RECT 1702.820000 1260.460000 1703.920000 1260.940000 ;
+ RECT 1702.820000 1265.900000 1703.920000 1266.380000 ;
+ RECT 1702.820000 1271.340000 1703.920000 1271.820000 ;
+ RECT 1657.820000 1293.100000 1658.920000 1293.580000 ;
+ RECT 1653.690000 1293.100000 1654.690000 1293.580000 ;
+ RECT 1657.820000 1287.660000 1658.920000 1288.140000 ;
+ RECT 1653.690000 1287.660000 1654.690000 1288.140000 ;
+ RECT 1657.820000 1282.220000 1658.920000 1282.700000 ;
+ RECT 1653.690000 1282.220000 1654.690000 1282.700000 ;
+ RECT 1657.820000 1276.780000 1658.920000 1277.260000 ;
+ RECT 1653.690000 1276.780000 1654.690000 1277.260000 ;
+ RECT 1657.820000 1271.340000 1658.920000 1271.820000 ;
+ RECT 1657.820000 1265.900000 1658.920000 1266.380000 ;
+ RECT 1653.690000 1271.340000 1654.690000 1271.820000 ;
+ RECT 1653.690000 1265.900000 1654.690000 1266.380000 ;
+ RECT 1657.820000 1260.460000 1658.920000 1260.940000 ;
+ RECT 1653.690000 1260.460000 1654.690000 1260.940000 ;
+ RECT 1657.820000 1255.020000 1658.920000 1255.500000 ;
+ RECT 1653.690000 1255.020000 1654.690000 1255.500000 ;
+ RECT 1657.820000 1249.580000 1658.920000 1250.060000 ;
+ RECT 1653.690000 1249.580000 1654.690000 1250.060000 ;
+ RECT 1837.820000 1244.140000 1838.920000 1244.620000 ;
+ RECT 1837.820000 1238.700000 1838.920000 1239.180000 ;
+ RECT 1847.130000 1244.140000 1848.130000 1244.620000 ;
+ RECT 1847.130000 1238.700000 1848.130000 1239.180000 ;
+ RECT 1847.130000 1222.380000 1848.130000 1222.860000 ;
+ RECT 1847.130000 1227.820000 1848.130000 1228.300000 ;
+ RECT 1847.130000 1233.260000 1848.130000 1233.740000 ;
+ RECT 1837.820000 1233.260000 1838.920000 1233.740000 ;
+ RECT 1837.820000 1227.820000 1838.920000 1228.300000 ;
+ RECT 1837.820000 1222.380000 1838.920000 1222.860000 ;
+ RECT 1837.820000 1211.500000 1838.920000 1211.980000 ;
+ RECT 1837.820000 1216.940000 1838.920000 1217.420000 ;
+ RECT 1847.130000 1216.940000 1848.130000 1217.420000 ;
+ RECT 1847.130000 1211.500000 1848.130000 1211.980000 ;
+ RECT 1847.130000 1200.620000 1848.130000 1201.100000 ;
+ RECT 1847.130000 1206.060000 1848.130000 1206.540000 ;
+ RECT 1837.820000 1200.620000 1838.920000 1201.100000 ;
+ RECT 1837.820000 1206.060000 1838.920000 1206.540000 ;
+ RECT 1792.820000 1244.140000 1793.920000 1244.620000 ;
+ RECT 1792.820000 1238.700000 1793.920000 1239.180000 ;
+ RECT 1792.820000 1233.260000 1793.920000 1233.740000 ;
+ RECT 1792.820000 1227.820000 1793.920000 1228.300000 ;
+ RECT 1792.820000 1222.380000 1793.920000 1222.860000 ;
+ RECT 1792.820000 1200.620000 1793.920000 1201.100000 ;
+ RECT 1792.820000 1206.060000 1793.920000 1206.540000 ;
+ RECT 1792.820000 1211.500000 1793.920000 1211.980000 ;
+ RECT 1792.820000 1216.940000 1793.920000 1217.420000 ;
+ RECT 1837.820000 1195.180000 1838.920000 1195.660000 ;
+ RECT 1837.820000 1189.740000 1838.920000 1190.220000 ;
+ RECT 1847.130000 1195.180000 1848.130000 1195.660000 ;
+ RECT 1847.130000 1189.740000 1848.130000 1190.220000 ;
+ RECT 1837.820000 1178.860000 1838.920000 1179.340000 ;
+ RECT 1837.820000 1173.420000 1838.920000 1173.900000 ;
+ RECT 1847.130000 1178.860000 1848.130000 1179.340000 ;
+ RECT 1847.130000 1173.420000 1848.130000 1173.900000 ;
+ RECT 1837.820000 1184.300000 1838.920000 1184.780000 ;
+ RECT 1847.130000 1184.300000 1848.130000 1184.780000 ;
+ RECT 1847.130000 1162.540000 1848.130000 1163.020000 ;
+ RECT 1847.130000 1167.980000 1848.130000 1168.460000 ;
+ RECT 1837.820000 1167.980000 1838.920000 1168.460000 ;
+ RECT 1837.820000 1162.540000 1838.920000 1163.020000 ;
+ RECT 1837.820000 1157.100000 1838.920000 1157.580000 ;
+ RECT 1837.820000 1151.660000 1838.920000 1152.140000 ;
+ RECT 1847.130000 1157.100000 1848.130000 1157.580000 ;
+ RECT 1847.130000 1151.660000 1848.130000 1152.140000 ;
+ RECT 1792.820000 1195.180000 1793.920000 1195.660000 ;
+ RECT 1792.820000 1189.740000 1793.920000 1190.220000 ;
+ RECT 1792.820000 1184.300000 1793.920000 1184.780000 ;
+ RECT 1792.820000 1178.860000 1793.920000 1179.340000 ;
+ RECT 1792.820000 1173.420000 1793.920000 1173.900000 ;
+ RECT 1792.820000 1167.980000 1793.920000 1168.460000 ;
+ RECT 1792.820000 1162.540000 1793.920000 1163.020000 ;
+ RECT 1792.820000 1157.100000 1793.920000 1157.580000 ;
+ RECT 1792.820000 1151.660000 1793.920000 1152.140000 ;
+ RECT 1747.820000 1244.140000 1748.920000 1244.620000 ;
+ RECT 1747.820000 1238.700000 1748.920000 1239.180000 ;
+ RECT 1747.820000 1233.260000 1748.920000 1233.740000 ;
+ RECT 1747.820000 1227.820000 1748.920000 1228.300000 ;
+ RECT 1747.820000 1222.380000 1748.920000 1222.860000 ;
+ RECT 1702.820000 1244.140000 1703.920000 1244.620000 ;
+ RECT 1702.820000 1238.700000 1703.920000 1239.180000 ;
+ RECT 1702.820000 1233.260000 1703.920000 1233.740000 ;
+ RECT 1702.820000 1227.820000 1703.920000 1228.300000 ;
+ RECT 1702.820000 1222.380000 1703.920000 1222.860000 ;
+ RECT 1747.820000 1216.940000 1748.920000 1217.420000 ;
+ RECT 1747.820000 1211.500000 1748.920000 1211.980000 ;
+ RECT 1747.820000 1206.060000 1748.920000 1206.540000 ;
+ RECT 1747.820000 1200.620000 1748.920000 1201.100000 ;
+ RECT 1702.820000 1211.500000 1703.920000 1211.980000 ;
+ RECT 1702.820000 1206.060000 1703.920000 1206.540000 ;
+ RECT 1702.820000 1200.620000 1703.920000 1201.100000 ;
+ RECT 1702.820000 1216.940000 1703.920000 1217.420000 ;
+ RECT 1657.820000 1244.140000 1658.920000 1244.620000 ;
+ RECT 1653.690000 1244.140000 1654.690000 1244.620000 ;
+ RECT 1657.820000 1238.700000 1658.920000 1239.180000 ;
+ RECT 1653.690000 1238.700000 1654.690000 1239.180000 ;
+ RECT 1657.820000 1233.260000 1658.920000 1233.740000 ;
+ RECT 1653.690000 1233.260000 1654.690000 1233.740000 ;
+ RECT 1657.820000 1222.380000 1658.920000 1222.860000 ;
+ RECT 1653.690000 1222.380000 1654.690000 1222.860000 ;
+ RECT 1653.690000 1227.820000 1654.690000 1228.300000 ;
+ RECT 1657.820000 1227.820000 1658.920000 1228.300000 ;
+ RECT 1657.820000 1216.940000 1658.920000 1217.420000 ;
+ RECT 1653.690000 1216.940000 1654.690000 1217.420000 ;
+ RECT 1657.820000 1211.500000 1658.920000 1211.980000 ;
+ RECT 1653.690000 1211.500000 1654.690000 1211.980000 ;
+ RECT 1657.820000 1206.060000 1658.920000 1206.540000 ;
+ RECT 1653.690000 1206.060000 1654.690000 1206.540000 ;
+ RECT 1657.820000 1200.620000 1658.920000 1201.100000 ;
+ RECT 1653.690000 1200.620000 1654.690000 1201.100000 ;
+ RECT 1747.820000 1195.180000 1748.920000 1195.660000 ;
+ RECT 1747.820000 1189.740000 1748.920000 1190.220000 ;
+ RECT 1747.820000 1184.300000 1748.920000 1184.780000 ;
+ RECT 1747.820000 1178.860000 1748.920000 1179.340000 ;
+ RECT 1747.820000 1173.420000 1748.920000 1173.900000 ;
+ RECT 1702.820000 1195.180000 1703.920000 1195.660000 ;
+ RECT 1702.820000 1189.740000 1703.920000 1190.220000 ;
+ RECT 1702.820000 1184.300000 1703.920000 1184.780000 ;
+ RECT 1702.820000 1178.860000 1703.920000 1179.340000 ;
+ RECT 1702.820000 1173.420000 1703.920000 1173.900000 ;
+ RECT 1747.820000 1151.660000 1748.920000 1152.140000 ;
+ RECT 1747.820000 1157.100000 1748.920000 1157.580000 ;
+ RECT 1747.820000 1162.540000 1748.920000 1163.020000 ;
+ RECT 1747.820000 1167.980000 1748.920000 1168.460000 ;
+ RECT 1702.820000 1151.660000 1703.920000 1152.140000 ;
+ RECT 1702.820000 1157.100000 1703.920000 1157.580000 ;
+ RECT 1702.820000 1162.540000 1703.920000 1163.020000 ;
+ RECT 1702.820000 1167.980000 1703.920000 1168.460000 ;
+ RECT 1657.820000 1195.180000 1658.920000 1195.660000 ;
+ RECT 1653.690000 1195.180000 1654.690000 1195.660000 ;
+ RECT 1657.820000 1189.740000 1658.920000 1190.220000 ;
+ RECT 1653.690000 1189.740000 1654.690000 1190.220000 ;
+ RECT 1657.820000 1178.860000 1658.920000 1179.340000 ;
+ RECT 1653.690000 1178.860000 1654.690000 1179.340000 ;
+ RECT 1657.820000 1173.420000 1658.920000 1173.900000 ;
+ RECT 1653.690000 1173.420000 1654.690000 1173.900000 ;
+ RECT 1657.820000 1184.300000 1658.920000 1184.780000 ;
+ RECT 1653.690000 1184.300000 1654.690000 1184.780000 ;
+ RECT 1657.820000 1167.980000 1658.920000 1168.460000 ;
+ RECT 1653.690000 1167.980000 1654.690000 1168.460000 ;
+ RECT 1657.820000 1162.540000 1658.920000 1163.020000 ;
+ RECT 1653.690000 1162.540000 1654.690000 1163.020000 ;
+ RECT 1657.820000 1157.100000 1658.920000 1157.580000 ;
+ RECT 1657.820000 1151.660000 1658.920000 1152.140000 ;
+ RECT 1653.690000 1157.100000 1654.690000 1157.580000 ;
+ RECT 1653.690000 1151.660000 1654.690000 1152.140000 ;
+ RECT 1650.860000 1342.020000 1850.960000 1343.020000 ;
+ RECT 1650.860000 1149.650000 1850.960000 1150.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 1146.800000 1654.690000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 1346.060000 1654.690000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 1146.800000 1848.130000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 1346.060000 1848.130000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1149.650000 1651.860000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1149.650000 1850.960000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1342.020000 1651.860000 1343.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1342.020000 1850.960000 1343.020000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 949.390000 1838.920000 1142.760000 ;
+ RECT 1792.820000 949.390000 1793.920000 1142.760000 ;
+ RECT 1847.130000 946.540000 1848.130000 1146.800000 ;
+ RECT 1747.820000 949.390000 1748.920000 1142.760000 ;
+ RECT 1702.820000 949.390000 1703.920000 1142.760000 ;
+ RECT 1657.820000 949.390000 1658.920000 1142.760000 ;
+ RECT 1653.690000 946.540000 1654.690000 1146.800000 ;
+ LAYER met3 ;
+ RECT 1837.820000 1136.360000 1838.920000 1136.840000 ;
+ RECT 1847.130000 1136.360000 1848.130000 1136.840000 ;
+ RECT 1847.130000 1125.480000 1848.130000 1125.960000 ;
+ RECT 1847.130000 1130.920000 1848.130000 1131.400000 ;
+ RECT 1837.820000 1130.920000 1838.920000 1131.400000 ;
+ RECT 1837.820000 1125.480000 1838.920000 1125.960000 ;
+ RECT 1837.820000 1120.040000 1838.920000 1120.520000 ;
+ RECT 1837.820000 1114.600000 1838.920000 1115.080000 ;
+ RECT 1847.130000 1120.040000 1848.130000 1120.520000 ;
+ RECT 1847.130000 1114.600000 1848.130000 1115.080000 ;
+ RECT 1837.820000 1098.280000 1838.920000 1098.760000 ;
+ RECT 1837.820000 1103.720000 1838.920000 1104.200000 ;
+ RECT 1847.130000 1103.720000 1848.130000 1104.200000 ;
+ RECT 1847.130000 1098.280000 1848.130000 1098.760000 ;
+ RECT 1837.820000 1109.160000 1838.920000 1109.640000 ;
+ RECT 1847.130000 1109.160000 1848.130000 1109.640000 ;
+ RECT 1792.820000 1136.360000 1793.920000 1136.840000 ;
+ RECT 1792.820000 1130.920000 1793.920000 1131.400000 ;
+ RECT 1792.820000 1125.480000 1793.920000 1125.960000 ;
+ RECT 1792.820000 1120.040000 1793.920000 1120.520000 ;
+ RECT 1792.820000 1098.280000 1793.920000 1098.760000 ;
+ RECT 1792.820000 1103.720000 1793.920000 1104.200000 ;
+ RECT 1792.820000 1109.160000 1793.920000 1109.640000 ;
+ RECT 1792.820000 1114.600000 1793.920000 1115.080000 ;
+ RECT 1847.130000 1087.400000 1848.130000 1087.880000 ;
+ RECT 1847.130000 1092.840000 1848.130000 1093.320000 ;
+ RECT 1837.820000 1092.840000 1838.920000 1093.320000 ;
+ RECT 1837.820000 1087.400000 1838.920000 1087.880000 ;
+ RECT 1837.820000 1081.960000 1838.920000 1082.440000 ;
+ RECT 1837.820000 1076.520000 1838.920000 1077.000000 ;
+ RECT 1847.130000 1081.960000 1848.130000 1082.440000 ;
+ RECT 1847.130000 1076.520000 1848.130000 1077.000000 ;
+ RECT 1847.130000 1060.200000 1848.130000 1060.680000 ;
+ RECT 1847.130000 1065.640000 1848.130000 1066.120000 ;
+ RECT 1847.130000 1071.080000 1848.130000 1071.560000 ;
+ RECT 1837.820000 1065.640000 1838.920000 1066.120000 ;
+ RECT 1837.820000 1060.200000 1838.920000 1060.680000 ;
+ RECT 1837.820000 1071.080000 1838.920000 1071.560000 ;
+ RECT 1837.820000 1054.760000 1838.920000 1055.240000 ;
+ RECT 1837.820000 1049.320000 1838.920000 1049.800000 ;
+ RECT 1847.130000 1054.760000 1848.130000 1055.240000 ;
+ RECT 1847.130000 1049.320000 1848.130000 1049.800000 ;
+ RECT 1792.820000 1092.840000 1793.920000 1093.320000 ;
+ RECT 1792.820000 1087.400000 1793.920000 1087.880000 ;
+ RECT 1792.820000 1081.960000 1793.920000 1082.440000 ;
+ RECT 1792.820000 1076.520000 1793.920000 1077.000000 ;
+ RECT 1792.820000 1065.640000 1793.920000 1066.120000 ;
+ RECT 1792.820000 1060.200000 1793.920000 1060.680000 ;
+ RECT 1792.820000 1054.760000 1793.920000 1055.240000 ;
+ RECT 1792.820000 1049.320000 1793.920000 1049.800000 ;
+ RECT 1792.820000 1071.080000 1793.920000 1071.560000 ;
+ RECT 1747.820000 1136.360000 1748.920000 1136.840000 ;
+ RECT 1747.820000 1130.920000 1748.920000 1131.400000 ;
+ RECT 1747.820000 1125.480000 1748.920000 1125.960000 ;
+ RECT 1702.820000 1136.360000 1703.920000 1136.840000 ;
+ RECT 1702.820000 1130.920000 1703.920000 1131.400000 ;
+ RECT 1702.820000 1125.480000 1703.920000 1125.960000 ;
+ RECT 1747.820000 1109.160000 1748.920000 1109.640000 ;
+ RECT 1747.820000 1103.720000 1748.920000 1104.200000 ;
+ RECT 1747.820000 1098.280000 1748.920000 1098.760000 ;
+ RECT 1747.820000 1114.600000 1748.920000 1115.080000 ;
+ RECT 1747.820000 1120.040000 1748.920000 1120.520000 ;
+ RECT 1702.820000 1120.040000 1703.920000 1120.520000 ;
+ RECT 1702.820000 1109.160000 1703.920000 1109.640000 ;
+ RECT 1702.820000 1103.720000 1703.920000 1104.200000 ;
+ RECT 1702.820000 1098.280000 1703.920000 1098.760000 ;
+ RECT 1702.820000 1114.600000 1703.920000 1115.080000 ;
+ RECT 1657.820000 1136.360000 1658.920000 1136.840000 ;
+ RECT 1653.690000 1136.360000 1654.690000 1136.840000 ;
+ RECT 1653.690000 1130.920000 1654.690000 1131.400000 ;
+ RECT 1657.820000 1130.920000 1658.920000 1131.400000 ;
+ RECT 1657.820000 1125.480000 1658.920000 1125.960000 ;
+ RECT 1653.690000 1125.480000 1654.690000 1125.960000 ;
+ RECT 1657.820000 1120.040000 1658.920000 1120.520000 ;
+ RECT 1653.690000 1120.040000 1654.690000 1120.520000 ;
+ RECT 1657.820000 1114.600000 1658.920000 1115.080000 ;
+ RECT 1653.690000 1114.600000 1654.690000 1115.080000 ;
+ RECT 1657.820000 1103.720000 1658.920000 1104.200000 ;
+ RECT 1653.690000 1103.720000 1654.690000 1104.200000 ;
+ RECT 1657.820000 1098.280000 1658.920000 1098.760000 ;
+ RECT 1653.690000 1098.280000 1654.690000 1098.760000 ;
+ RECT 1657.820000 1109.160000 1658.920000 1109.640000 ;
+ RECT 1653.690000 1109.160000 1654.690000 1109.640000 ;
+ RECT 1747.820000 1092.840000 1748.920000 1093.320000 ;
+ RECT 1747.820000 1087.400000 1748.920000 1087.880000 ;
+ RECT 1747.820000 1081.960000 1748.920000 1082.440000 ;
+ RECT 1747.820000 1076.520000 1748.920000 1077.000000 ;
+ RECT 1702.820000 1092.840000 1703.920000 1093.320000 ;
+ RECT 1702.820000 1087.400000 1703.920000 1087.880000 ;
+ RECT 1702.820000 1081.960000 1703.920000 1082.440000 ;
+ RECT 1702.820000 1076.520000 1703.920000 1077.000000 ;
+ RECT 1747.820000 1065.640000 1748.920000 1066.120000 ;
+ RECT 1747.820000 1049.320000 1748.920000 1049.800000 ;
+ RECT 1747.820000 1054.760000 1748.920000 1055.240000 ;
+ RECT 1747.820000 1060.200000 1748.920000 1060.680000 ;
+ RECT 1747.820000 1071.080000 1748.920000 1071.560000 ;
+ RECT 1702.820000 1049.320000 1703.920000 1049.800000 ;
+ RECT 1702.820000 1054.760000 1703.920000 1055.240000 ;
+ RECT 1702.820000 1060.200000 1703.920000 1060.680000 ;
+ RECT 1702.820000 1065.640000 1703.920000 1066.120000 ;
+ RECT 1702.820000 1071.080000 1703.920000 1071.560000 ;
+ RECT 1657.820000 1092.840000 1658.920000 1093.320000 ;
+ RECT 1653.690000 1092.840000 1654.690000 1093.320000 ;
+ RECT 1657.820000 1087.400000 1658.920000 1087.880000 ;
+ RECT 1653.690000 1087.400000 1654.690000 1087.880000 ;
+ RECT 1657.820000 1081.960000 1658.920000 1082.440000 ;
+ RECT 1653.690000 1081.960000 1654.690000 1082.440000 ;
+ RECT 1657.820000 1076.520000 1658.920000 1077.000000 ;
+ RECT 1653.690000 1076.520000 1654.690000 1077.000000 ;
+ RECT 1657.820000 1071.080000 1658.920000 1071.560000 ;
+ RECT 1657.820000 1065.640000 1658.920000 1066.120000 ;
+ RECT 1653.690000 1071.080000 1654.690000 1071.560000 ;
+ RECT 1653.690000 1065.640000 1654.690000 1066.120000 ;
+ RECT 1657.820000 1060.200000 1658.920000 1060.680000 ;
+ RECT 1653.690000 1060.200000 1654.690000 1060.680000 ;
+ RECT 1657.820000 1054.760000 1658.920000 1055.240000 ;
+ RECT 1653.690000 1054.760000 1654.690000 1055.240000 ;
+ RECT 1657.820000 1049.320000 1658.920000 1049.800000 ;
+ RECT 1653.690000 1049.320000 1654.690000 1049.800000 ;
+ RECT 1837.820000 1043.880000 1838.920000 1044.360000 ;
+ RECT 1837.820000 1038.440000 1838.920000 1038.920000 ;
+ RECT 1847.130000 1043.880000 1848.130000 1044.360000 ;
+ RECT 1847.130000 1038.440000 1848.130000 1038.920000 ;
+ RECT 1847.130000 1022.120000 1848.130000 1022.600000 ;
+ RECT 1847.130000 1027.560000 1848.130000 1028.040000 ;
+ RECT 1847.130000 1033.000000 1848.130000 1033.480000 ;
+ RECT 1837.820000 1033.000000 1838.920000 1033.480000 ;
+ RECT 1837.820000 1027.560000 1838.920000 1028.040000 ;
+ RECT 1837.820000 1022.120000 1838.920000 1022.600000 ;
+ RECT 1837.820000 1011.240000 1838.920000 1011.720000 ;
+ RECT 1837.820000 1016.680000 1838.920000 1017.160000 ;
+ RECT 1847.130000 1016.680000 1848.130000 1017.160000 ;
+ RECT 1847.130000 1011.240000 1848.130000 1011.720000 ;
+ RECT 1847.130000 1000.360000 1848.130000 1000.840000 ;
+ RECT 1847.130000 1005.800000 1848.130000 1006.280000 ;
+ RECT 1837.820000 1000.360000 1838.920000 1000.840000 ;
+ RECT 1837.820000 1005.800000 1838.920000 1006.280000 ;
+ RECT 1792.820000 1043.880000 1793.920000 1044.360000 ;
+ RECT 1792.820000 1038.440000 1793.920000 1038.920000 ;
+ RECT 1792.820000 1033.000000 1793.920000 1033.480000 ;
+ RECT 1792.820000 1027.560000 1793.920000 1028.040000 ;
+ RECT 1792.820000 1022.120000 1793.920000 1022.600000 ;
+ RECT 1792.820000 1000.360000 1793.920000 1000.840000 ;
+ RECT 1792.820000 1005.800000 1793.920000 1006.280000 ;
+ RECT 1792.820000 1011.240000 1793.920000 1011.720000 ;
+ RECT 1792.820000 1016.680000 1793.920000 1017.160000 ;
+ RECT 1837.820000 994.920000 1838.920000 995.400000 ;
+ RECT 1837.820000 989.480000 1838.920000 989.960000 ;
+ RECT 1847.130000 994.920000 1848.130000 995.400000 ;
+ RECT 1847.130000 989.480000 1848.130000 989.960000 ;
+ RECT 1837.820000 978.600000 1838.920000 979.080000 ;
+ RECT 1837.820000 973.160000 1838.920000 973.640000 ;
+ RECT 1847.130000 978.600000 1848.130000 979.080000 ;
+ RECT 1847.130000 973.160000 1848.130000 973.640000 ;
+ RECT 1837.820000 984.040000 1838.920000 984.520000 ;
+ RECT 1847.130000 984.040000 1848.130000 984.520000 ;
+ RECT 1847.130000 962.280000 1848.130000 962.760000 ;
+ RECT 1847.130000 967.720000 1848.130000 968.200000 ;
+ RECT 1837.820000 967.720000 1838.920000 968.200000 ;
+ RECT 1837.820000 962.280000 1838.920000 962.760000 ;
+ RECT 1837.820000 956.840000 1838.920000 957.320000 ;
+ RECT 1837.820000 951.400000 1838.920000 951.880000 ;
+ RECT 1847.130000 956.840000 1848.130000 957.320000 ;
+ RECT 1847.130000 951.400000 1848.130000 951.880000 ;
+ RECT 1792.820000 994.920000 1793.920000 995.400000 ;
+ RECT 1792.820000 989.480000 1793.920000 989.960000 ;
+ RECT 1792.820000 984.040000 1793.920000 984.520000 ;
+ RECT 1792.820000 978.600000 1793.920000 979.080000 ;
+ RECT 1792.820000 973.160000 1793.920000 973.640000 ;
+ RECT 1792.820000 967.720000 1793.920000 968.200000 ;
+ RECT 1792.820000 962.280000 1793.920000 962.760000 ;
+ RECT 1792.820000 956.840000 1793.920000 957.320000 ;
+ RECT 1792.820000 951.400000 1793.920000 951.880000 ;
+ RECT 1747.820000 1043.880000 1748.920000 1044.360000 ;
+ RECT 1747.820000 1038.440000 1748.920000 1038.920000 ;
+ RECT 1747.820000 1033.000000 1748.920000 1033.480000 ;
+ RECT 1747.820000 1027.560000 1748.920000 1028.040000 ;
+ RECT 1747.820000 1022.120000 1748.920000 1022.600000 ;
+ RECT 1702.820000 1043.880000 1703.920000 1044.360000 ;
+ RECT 1702.820000 1038.440000 1703.920000 1038.920000 ;
+ RECT 1702.820000 1033.000000 1703.920000 1033.480000 ;
+ RECT 1702.820000 1027.560000 1703.920000 1028.040000 ;
+ RECT 1702.820000 1022.120000 1703.920000 1022.600000 ;
+ RECT 1747.820000 1016.680000 1748.920000 1017.160000 ;
+ RECT 1747.820000 1011.240000 1748.920000 1011.720000 ;
+ RECT 1747.820000 1005.800000 1748.920000 1006.280000 ;
+ RECT 1747.820000 1000.360000 1748.920000 1000.840000 ;
+ RECT 1702.820000 1011.240000 1703.920000 1011.720000 ;
+ RECT 1702.820000 1005.800000 1703.920000 1006.280000 ;
+ RECT 1702.820000 1000.360000 1703.920000 1000.840000 ;
+ RECT 1702.820000 1016.680000 1703.920000 1017.160000 ;
+ RECT 1657.820000 1043.880000 1658.920000 1044.360000 ;
+ RECT 1653.690000 1043.880000 1654.690000 1044.360000 ;
+ RECT 1657.820000 1038.440000 1658.920000 1038.920000 ;
+ RECT 1653.690000 1038.440000 1654.690000 1038.920000 ;
+ RECT 1657.820000 1033.000000 1658.920000 1033.480000 ;
+ RECT 1653.690000 1033.000000 1654.690000 1033.480000 ;
+ RECT 1657.820000 1022.120000 1658.920000 1022.600000 ;
+ RECT 1653.690000 1022.120000 1654.690000 1022.600000 ;
+ RECT 1653.690000 1027.560000 1654.690000 1028.040000 ;
+ RECT 1657.820000 1027.560000 1658.920000 1028.040000 ;
+ RECT 1657.820000 1016.680000 1658.920000 1017.160000 ;
+ RECT 1653.690000 1016.680000 1654.690000 1017.160000 ;
+ RECT 1657.820000 1011.240000 1658.920000 1011.720000 ;
+ RECT 1653.690000 1011.240000 1654.690000 1011.720000 ;
+ RECT 1657.820000 1005.800000 1658.920000 1006.280000 ;
+ RECT 1653.690000 1005.800000 1654.690000 1006.280000 ;
+ RECT 1657.820000 1000.360000 1658.920000 1000.840000 ;
+ RECT 1653.690000 1000.360000 1654.690000 1000.840000 ;
+ RECT 1747.820000 994.920000 1748.920000 995.400000 ;
+ RECT 1747.820000 989.480000 1748.920000 989.960000 ;
+ RECT 1747.820000 984.040000 1748.920000 984.520000 ;
+ RECT 1747.820000 978.600000 1748.920000 979.080000 ;
+ RECT 1747.820000 973.160000 1748.920000 973.640000 ;
+ RECT 1702.820000 994.920000 1703.920000 995.400000 ;
+ RECT 1702.820000 989.480000 1703.920000 989.960000 ;
+ RECT 1702.820000 984.040000 1703.920000 984.520000 ;
+ RECT 1702.820000 978.600000 1703.920000 979.080000 ;
+ RECT 1702.820000 973.160000 1703.920000 973.640000 ;
+ RECT 1747.820000 951.400000 1748.920000 951.880000 ;
+ RECT 1747.820000 956.840000 1748.920000 957.320000 ;
+ RECT 1747.820000 962.280000 1748.920000 962.760000 ;
+ RECT 1747.820000 967.720000 1748.920000 968.200000 ;
+ RECT 1702.820000 951.400000 1703.920000 951.880000 ;
+ RECT 1702.820000 956.840000 1703.920000 957.320000 ;
+ RECT 1702.820000 962.280000 1703.920000 962.760000 ;
+ RECT 1702.820000 967.720000 1703.920000 968.200000 ;
+ RECT 1657.820000 994.920000 1658.920000 995.400000 ;
+ RECT 1653.690000 994.920000 1654.690000 995.400000 ;
+ RECT 1657.820000 989.480000 1658.920000 989.960000 ;
+ RECT 1653.690000 989.480000 1654.690000 989.960000 ;
+ RECT 1657.820000 978.600000 1658.920000 979.080000 ;
+ RECT 1653.690000 978.600000 1654.690000 979.080000 ;
+ RECT 1657.820000 973.160000 1658.920000 973.640000 ;
+ RECT 1653.690000 973.160000 1654.690000 973.640000 ;
+ RECT 1657.820000 984.040000 1658.920000 984.520000 ;
+ RECT 1653.690000 984.040000 1654.690000 984.520000 ;
+ RECT 1657.820000 967.720000 1658.920000 968.200000 ;
+ RECT 1653.690000 967.720000 1654.690000 968.200000 ;
+ RECT 1657.820000 962.280000 1658.920000 962.760000 ;
+ RECT 1653.690000 962.280000 1654.690000 962.760000 ;
+ RECT 1657.820000 956.840000 1658.920000 957.320000 ;
+ RECT 1657.820000 951.400000 1658.920000 951.880000 ;
+ RECT 1653.690000 956.840000 1654.690000 957.320000 ;
+ RECT 1653.690000 951.400000 1654.690000 951.880000 ;
+ RECT 1650.860000 1141.760000 1850.960000 1142.760000 ;
+ RECT 1650.860000 949.390000 1850.960000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 946.540000 1654.690000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 1145.800000 1654.690000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 946.540000 1848.130000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 1145.800000 1848.130000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 949.390000 1651.860000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 949.390000 1850.960000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1141.760000 1651.860000 1142.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1141.760000 1850.960000 1142.760000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 749.130000 1838.920000 942.500000 ;
+ RECT 1792.820000 749.130000 1793.920000 942.500000 ;
+ RECT 1847.130000 746.280000 1848.130000 946.540000 ;
+ RECT 1747.820000 749.130000 1748.920000 942.500000 ;
+ RECT 1702.820000 749.130000 1703.920000 942.500000 ;
+ RECT 1657.820000 749.130000 1658.920000 942.500000 ;
+ RECT 1653.690000 746.280000 1654.690000 946.540000 ;
+ LAYER met3 ;
+ RECT 1837.820000 936.100000 1838.920000 936.580000 ;
+ RECT 1847.130000 936.100000 1848.130000 936.580000 ;
+ RECT 1847.130000 925.220000 1848.130000 925.700000 ;
+ RECT 1847.130000 930.660000 1848.130000 931.140000 ;
+ RECT 1837.820000 930.660000 1838.920000 931.140000 ;
+ RECT 1837.820000 925.220000 1838.920000 925.700000 ;
+ RECT 1837.820000 919.780000 1838.920000 920.260000 ;
+ RECT 1837.820000 914.340000 1838.920000 914.820000 ;
+ RECT 1847.130000 919.780000 1848.130000 920.260000 ;
+ RECT 1847.130000 914.340000 1848.130000 914.820000 ;
+ RECT 1837.820000 898.020000 1838.920000 898.500000 ;
+ RECT 1837.820000 903.460000 1838.920000 903.940000 ;
+ RECT 1847.130000 903.460000 1848.130000 903.940000 ;
+ RECT 1847.130000 898.020000 1848.130000 898.500000 ;
+ RECT 1837.820000 908.900000 1838.920000 909.380000 ;
+ RECT 1847.130000 908.900000 1848.130000 909.380000 ;
+ RECT 1792.820000 936.100000 1793.920000 936.580000 ;
+ RECT 1792.820000 930.660000 1793.920000 931.140000 ;
+ RECT 1792.820000 925.220000 1793.920000 925.700000 ;
+ RECT 1792.820000 919.780000 1793.920000 920.260000 ;
+ RECT 1792.820000 898.020000 1793.920000 898.500000 ;
+ RECT 1792.820000 903.460000 1793.920000 903.940000 ;
+ RECT 1792.820000 908.900000 1793.920000 909.380000 ;
+ RECT 1792.820000 914.340000 1793.920000 914.820000 ;
+ RECT 1847.130000 887.140000 1848.130000 887.620000 ;
+ RECT 1847.130000 892.580000 1848.130000 893.060000 ;
+ RECT 1837.820000 892.580000 1838.920000 893.060000 ;
+ RECT 1837.820000 887.140000 1838.920000 887.620000 ;
+ RECT 1837.820000 881.700000 1838.920000 882.180000 ;
+ RECT 1837.820000 876.260000 1838.920000 876.740000 ;
+ RECT 1847.130000 881.700000 1848.130000 882.180000 ;
+ RECT 1847.130000 876.260000 1848.130000 876.740000 ;
+ RECT 1847.130000 859.940000 1848.130000 860.420000 ;
+ RECT 1847.130000 865.380000 1848.130000 865.860000 ;
+ RECT 1847.130000 870.820000 1848.130000 871.300000 ;
+ RECT 1837.820000 865.380000 1838.920000 865.860000 ;
+ RECT 1837.820000 859.940000 1838.920000 860.420000 ;
+ RECT 1837.820000 870.820000 1838.920000 871.300000 ;
+ RECT 1837.820000 854.500000 1838.920000 854.980000 ;
+ RECT 1837.820000 849.060000 1838.920000 849.540000 ;
+ RECT 1847.130000 854.500000 1848.130000 854.980000 ;
+ RECT 1847.130000 849.060000 1848.130000 849.540000 ;
+ RECT 1792.820000 892.580000 1793.920000 893.060000 ;
+ RECT 1792.820000 887.140000 1793.920000 887.620000 ;
+ RECT 1792.820000 881.700000 1793.920000 882.180000 ;
+ RECT 1792.820000 876.260000 1793.920000 876.740000 ;
+ RECT 1792.820000 865.380000 1793.920000 865.860000 ;
+ RECT 1792.820000 859.940000 1793.920000 860.420000 ;
+ RECT 1792.820000 854.500000 1793.920000 854.980000 ;
+ RECT 1792.820000 849.060000 1793.920000 849.540000 ;
+ RECT 1792.820000 870.820000 1793.920000 871.300000 ;
+ RECT 1747.820000 936.100000 1748.920000 936.580000 ;
+ RECT 1747.820000 930.660000 1748.920000 931.140000 ;
+ RECT 1747.820000 925.220000 1748.920000 925.700000 ;
+ RECT 1702.820000 936.100000 1703.920000 936.580000 ;
+ RECT 1702.820000 930.660000 1703.920000 931.140000 ;
+ RECT 1702.820000 925.220000 1703.920000 925.700000 ;
+ RECT 1747.820000 908.900000 1748.920000 909.380000 ;
+ RECT 1747.820000 903.460000 1748.920000 903.940000 ;
+ RECT 1747.820000 898.020000 1748.920000 898.500000 ;
+ RECT 1747.820000 914.340000 1748.920000 914.820000 ;
+ RECT 1747.820000 919.780000 1748.920000 920.260000 ;
+ RECT 1702.820000 919.780000 1703.920000 920.260000 ;
+ RECT 1702.820000 908.900000 1703.920000 909.380000 ;
+ RECT 1702.820000 903.460000 1703.920000 903.940000 ;
+ RECT 1702.820000 898.020000 1703.920000 898.500000 ;
+ RECT 1702.820000 914.340000 1703.920000 914.820000 ;
+ RECT 1657.820000 936.100000 1658.920000 936.580000 ;
+ RECT 1653.690000 936.100000 1654.690000 936.580000 ;
+ RECT 1653.690000 930.660000 1654.690000 931.140000 ;
+ RECT 1657.820000 930.660000 1658.920000 931.140000 ;
+ RECT 1657.820000 925.220000 1658.920000 925.700000 ;
+ RECT 1653.690000 925.220000 1654.690000 925.700000 ;
+ RECT 1657.820000 919.780000 1658.920000 920.260000 ;
+ RECT 1653.690000 919.780000 1654.690000 920.260000 ;
+ RECT 1657.820000 914.340000 1658.920000 914.820000 ;
+ RECT 1653.690000 914.340000 1654.690000 914.820000 ;
+ RECT 1657.820000 903.460000 1658.920000 903.940000 ;
+ RECT 1653.690000 903.460000 1654.690000 903.940000 ;
+ RECT 1657.820000 898.020000 1658.920000 898.500000 ;
+ RECT 1653.690000 898.020000 1654.690000 898.500000 ;
+ RECT 1657.820000 908.900000 1658.920000 909.380000 ;
+ RECT 1653.690000 908.900000 1654.690000 909.380000 ;
+ RECT 1747.820000 892.580000 1748.920000 893.060000 ;
+ RECT 1747.820000 887.140000 1748.920000 887.620000 ;
+ RECT 1747.820000 881.700000 1748.920000 882.180000 ;
+ RECT 1747.820000 876.260000 1748.920000 876.740000 ;
+ RECT 1702.820000 892.580000 1703.920000 893.060000 ;
+ RECT 1702.820000 887.140000 1703.920000 887.620000 ;
+ RECT 1702.820000 881.700000 1703.920000 882.180000 ;
+ RECT 1702.820000 876.260000 1703.920000 876.740000 ;
+ RECT 1747.820000 865.380000 1748.920000 865.860000 ;
+ RECT 1747.820000 849.060000 1748.920000 849.540000 ;
+ RECT 1747.820000 854.500000 1748.920000 854.980000 ;
+ RECT 1747.820000 859.940000 1748.920000 860.420000 ;
+ RECT 1747.820000 870.820000 1748.920000 871.300000 ;
+ RECT 1702.820000 849.060000 1703.920000 849.540000 ;
+ RECT 1702.820000 854.500000 1703.920000 854.980000 ;
+ RECT 1702.820000 859.940000 1703.920000 860.420000 ;
+ RECT 1702.820000 865.380000 1703.920000 865.860000 ;
+ RECT 1702.820000 870.820000 1703.920000 871.300000 ;
+ RECT 1657.820000 892.580000 1658.920000 893.060000 ;
+ RECT 1653.690000 892.580000 1654.690000 893.060000 ;
+ RECT 1657.820000 887.140000 1658.920000 887.620000 ;
+ RECT 1653.690000 887.140000 1654.690000 887.620000 ;
+ RECT 1657.820000 881.700000 1658.920000 882.180000 ;
+ RECT 1653.690000 881.700000 1654.690000 882.180000 ;
+ RECT 1657.820000 876.260000 1658.920000 876.740000 ;
+ RECT 1653.690000 876.260000 1654.690000 876.740000 ;
+ RECT 1657.820000 870.820000 1658.920000 871.300000 ;
+ RECT 1657.820000 865.380000 1658.920000 865.860000 ;
+ RECT 1653.690000 870.820000 1654.690000 871.300000 ;
+ RECT 1653.690000 865.380000 1654.690000 865.860000 ;
+ RECT 1657.820000 859.940000 1658.920000 860.420000 ;
+ RECT 1653.690000 859.940000 1654.690000 860.420000 ;
+ RECT 1657.820000 854.500000 1658.920000 854.980000 ;
+ RECT 1653.690000 854.500000 1654.690000 854.980000 ;
+ RECT 1657.820000 849.060000 1658.920000 849.540000 ;
+ RECT 1653.690000 849.060000 1654.690000 849.540000 ;
+ RECT 1837.820000 843.620000 1838.920000 844.100000 ;
+ RECT 1837.820000 838.180000 1838.920000 838.660000 ;
+ RECT 1847.130000 843.620000 1848.130000 844.100000 ;
+ RECT 1847.130000 838.180000 1848.130000 838.660000 ;
+ RECT 1847.130000 821.860000 1848.130000 822.340000 ;
+ RECT 1847.130000 827.300000 1848.130000 827.780000 ;
+ RECT 1847.130000 832.740000 1848.130000 833.220000 ;
+ RECT 1837.820000 832.740000 1838.920000 833.220000 ;
+ RECT 1837.820000 827.300000 1838.920000 827.780000 ;
+ RECT 1837.820000 821.860000 1838.920000 822.340000 ;
+ RECT 1837.820000 810.980000 1838.920000 811.460000 ;
+ RECT 1837.820000 816.420000 1838.920000 816.900000 ;
+ RECT 1847.130000 816.420000 1848.130000 816.900000 ;
+ RECT 1847.130000 810.980000 1848.130000 811.460000 ;
+ RECT 1847.130000 800.100000 1848.130000 800.580000 ;
+ RECT 1847.130000 805.540000 1848.130000 806.020000 ;
+ RECT 1837.820000 800.100000 1838.920000 800.580000 ;
+ RECT 1837.820000 805.540000 1838.920000 806.020000 ;
+ RECT 1792.820000 843.620000 1793.920000 844.100000 ;
+ RECT 1792.820000 838.180000 1793.920000 838.660000 ;
+ RECT 1792.820000 832.740000 1793.920000 833.220000 ;
+ RECT 1792.820000 827.300000 1793.920000 827.780000 ;
+ RECT 1792.820000 821.860000 1793.920000 822.340000 ;
+ RECT 1792.820000 800.100000 1793.920000 800.580000 ;
+ RECT 1792.820000 805.540000 1793.920000 806.020000 ;
+ RECT 1792.820000 810.980000 1793.920000 811.460000 ;
+ RECT 1792.820000 816.420000 1793.920000 816.900000 ;
+ RECT 1837.820000 794.660000 1838.920000 795.140000 ;
+ RECT 1837.820000 789.220000 1838.920000 789.700000 ;
+ RECT 1847.130000 794.660000 1848.130000 795.140000 ;
+ RECT 1847.130000 789.220000 1848.130000 789.700000 ;
+ RECT 1837.820000 778.340000 1838.920000 778.820000 ;
+ RECT 1837.820000 772.900000 1838.920000 773.380000 ;
+ RECT 1847.130000 778.340000 1848.130000 778.820000 ;
+ RECT 1847.130000 772.900000 1848.130000 773.380000 ;
+ RECT 1837.820000 783.780000 1838.920000 784.260000 ;
+ RECT 1847.130000 783.780000 1848.130000 784.260000 ;
+ RECT 1847.130000 762.020000 1848.130000 762.500000 ;
+ RECT 1847.130000 767.460000 1848.130000 767.940000 ;
+ RECT 1837.820000 767.460000 1838.920000 767.940000 ;
+ RECT 1837.820000 762.020000 1838.920000 762.500000 ;
+ RECT 1837.820000 756.580000 1838.920000 757.060000 ;
+ RECT 1837.820000 751.140000 1838.920000 751.620000 ;
+ RECT 1847.130000 756.580000 1848.130000 757.060000 ;
+ RECT 1847.130000 751.140000 1848.130000 751.620000 ;
+ RECT 1792.820000 794.660000 1793.920000 795.140000 ;
+ RECT 1792.820000 789.220000 1793.920000 789.700000 ;
+ RECT 1792.820000 783.780000 1793.920000 784.260000 ;
+ RECT 1792.820000 778.340000 1793.920000 778.820000 ;
+ RECT 1792.820000 772.900000 1793.920000 773.380000 ;
+ RECT 1792.820000 767.460000 1793.920000 767.940000 ;
+ RECT 1792.820000 762.020000 1793.920000 762.500000 ;
+ RECT 1792.820000 756.580000 1793.920000 757.060000 ;
+ RECT 1792.820000 751.140000 1793.920000 751.620000 ;
+ RECT 1747.820000 843.620000 1748.920000 844.100000 ;
+ RECT 1747.820000 838.180000 1748.920000 838.660000 ;
+ RECT 1747.820000 832.740000 1748.920000 833.220000 ;
+ RECT 1747.820000 827.300000 1748.920000 827.780000 ;
+ RECT 1747.820000 821.860000 1748.920000 822.340000 ;
+ RECT 1702.820000 843.620000 1703.920000 844.100000 ;
+ RECT 1702.820000 838.180000 1703.920000 838.660000 ;
+ RECT 1702.820000 832.740000 1703.920000 833.220000 ;
+ RECT 1702.820000 827.300000 1703.920000 827.780000 ;
+ RECT 1702.820000 821.860000 1703.920000 822.340000 ;
+ RECT 1747.820000 816.420000 1748.920000 816.900000 ;
+ RECT 1747.820000 810.980000 1748.920000 811.460000 ;
+ RECT 1747.820000 805.540000 1748.920000 806.020000 ;
+ RECT 1747.820000 800.100000 1748.920000 800.580000 ;
+ RECT 1702.820000 810.980000 1703.920000 811.460000 ;
+ RECT 1702.820000 805.540000 1703.920000 806.020000 ;
+ RECT 1702.820000 800.100000 1703.920000 800.580000 ;
+ RECT 1702.820000 816.420000 1703.920000 816.900000 ;
+ RECT 1657.820000 843.620000 1658.920000 844.100000 ;
+ RECT 1653.690000 843.620000 1654.690000 844.100000 ;
+ RECT 1657.820000 838.180000 1658.920000 838.660000 ;
+ RECT 1653.690000 838.180000 1654.690000 838.660000 ;
+ RECT 1657.820000 832.740000 1658.920000 833.220000 ;
+ RECT 1653.690000 832.740000 1654.690000 833.220000 ;
+ RECT 1657.820000 821.860000 1658.920000 822.340000 ;
+ RECT 1653.690000 821.860000 1654.690000 822.340000 ;
+ RECT 1653.690000 827.300000 1654.690000 827.780000 ;
+ RECT 1657.820000 827.300000 1658.920000 827.780000 ;
+ RECT 1657.820000 816.420000 1658.920000 816.900000 ;
+ RECT 1653.690000 816.420000 1654.690000 816.900000 ;
+ RECT 1657.820000 810.980000 1658.920000 811.460000 ;
+ RECT 1653.690000 810.980000 1654.690000 811.460000 ;
+ RECT 1657.820000 805.540000 1658.920000 806.020000 ;
+ RECT 1653.690000 805.540000 1654.690000 806.020000 ;
+ RECT 1657.820000 800.100000 1658.920000 800.580000 ;
+ RECT 1653.690000 800.100000 1654.690000 800.580000 ;
+ RECT 1747.820000 794.660000 1748.920000 795.140000 ;
+ RECT 1747.820000 789.220000 1748.920000 789.700000 ;
+ RECT 1747.820000 783.780000 1748.920000 784.260000 ;
+ RECT 1747.820000 778.340000 1748.920000 778.820000 ;
+ RECT 1747.820000 772.900000 1748.920000 773.380000 ;
+ RECT 1702.820000 794.660000 1703.920000 795.140000 ;
+ RECT 1702.820000 789.220000 1703.920000 789.700000 ;
+ RECT 1702.820000 783.780000 1703.920000 784.260000 ;
+ RECT 1702.820000 778.340000 1703.920000 778.820000 ;
+ RECT 1702.820000 772.900000 1703.920000 773.380000 ;
+ RECT 1747.820000 751.140000 1748.920000 751.620000 ;
+ RECT 1747.820000 756.580000 1748.920000 757.060000 ;
+ RECT 1747.820000 762.020000 1748.920000 762.500000 ;
+ RECT 1747.820000 767.460000 1748.920000 767.940000 ;
+ RECT 1702.820000 751.140000 1703.920000 751.620000 ;
+ RECT 1702.820000 756.580000 1703.920000 757.060000 ;
+ RECT 1702.820000 762.020000 1703.920000 762.500000 ;
+ RECT 1702.820000 767.460000 1703.920000 767.940000 ;
+ RECT 1657.820000 794.660000 1658.920000 795.140000 ;
+ RECT 1653.690000 794.660000 1654.690000 795.140000 ;
+ RECT 1657.820000 789.220000 1658.920000 789.700000 ;
+ RECT 1653.690000 789.220000 1654.690000 789.700000 ;
+ RECT 1657.820000 778.340000 1658.920000 778.820000 ;
+ RECT 1653.690000 778.340000 1654.690000 778.820000 ;
+ RECT 1657.820000 772.900000 1658.920000 773.380000 ;
+ RECT 1653.690000 772.900000 1654.690000 773.380000 ;
+ RECT 1657.820000 783.780000 1658.920000 784.260000 ;
+ RECT 1653.690000 783.780000 1654.690000 784.260000 ;
+ RECT 1657.820000 767.460000 1658.920000 767.940000 ;
+ RECT 1653.690000 767.460000 1654.690000 767.940000 ;
+ RECT 1657.820000 762.020000 1658.920000 762.500000 ;
+ RECT 1653.690000 762.020000 1654.690000 762.500000 ;
+ RECT 1657.820000 756.580000 1658.920000 757.060000 ;
+ RECT 1657.820000 751.140000 1658.920000 751.620000 ;
+ RECT 1653.690000 756.580000 1654.690000 757.060000 ;
+ RECT 1653.690000 751.140000 1654.690000 751.620000 ;
+ RECT 1650.860000 941.500000 1850.960000 942.500000 ;
+ RECT 1650.860000 749.130000 1850.960000 750.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 746.280000 1654.690000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 945.540000 1654.690000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 746.280000 1848.130000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 945.540000 1848.130000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 749.130000 1651.860000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 749.130000 1850.960000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 941.500000 1651.860000 942.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 941.500000 1850.960000 942.500000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 548.870000 1838.920000 742.240000 ;
+ RECT 1792.820000 548.870000 1793.920000 742.240000 ;
+ RECT 1847.130000 546.020000 1848.130000 746.280000 ;
+ RECT 1747.820000 548.870000 1748.920000 742.240000 ;
+ RECT 1702.820000 548.870000 1703.920000 742.240000 ;
+ RECT 1657.820000 548.870000 1658.920000 742.240000 ;
+ RECT 1653.690000 546.020000 1654.690000 746.280000 ;
+ LAYER met3 ;
+ RECT 1837.820000 735.840000 1838.920000 736.320000 ;
+ RECT 1847.130000 735.840000 1848.130000 736.320000 ;
+ RECT 1847.130000 724.960000 1848.130000 725.440000 ;
+ RECT 1847.130000 730.400000 1848.130000 730.880000 ;
+ RECT 1837.820000 730.400000 1838.920000 730.880000 ;
+ RECT 1837.820000 724.960000 1838.920000 725.440000 ;
+ RECT 1837.820000 719.520000 1838.920000 720.000000 ;
+ RECT 1837.820000 714.080000 1838.920000 714.560000 ;
+ RECT 1847.130000 719.520000 1848.130000 720.000000 ;
+ RECT 1847.130000 714.080000 1848.130000 714.560000 ;
+ RECT 1837.820000 697.760000 1838.920000 698.240000 ;
+ RECT 1837.820000 703.200000 1838.920000 703.680000 ;
+ RECT 1847.130000 703.200000 1848.130000 703.680000 ;
+ RECT 1847.130000 697.760000 1848.130000 698.240000 ;
+ RECT 1837.820000 708.640000 1838.920000 709.120000 ;
+ RECT 1847.130000 708.640000 1848.130000 709.120000 ;
+ RECT 1792.820000 735.840000 1793.920000 736.320000 ;
+ RECT 1792.820000 730.400000 1793.920000 730.880000 ;
+ RECT 1792.820000 724.960000 1793.920000 725.440000 ;
+ RECT 1792.820000 719.520000 1793.920000 720.000000 ;
+ RECT 1792.820000 697.760000 1793.920000 698.240000 ;
+ RECT 1792.820000 703.200000 1793.920000 703.680000 ;
+ RECT 1792.820000 708.640000 1793.920000 709.120000 ;
+ RECT 1792.820000 714.080000 1793.920000 714.560000 ;
+ RECT 1847.130000 686.880000 1848.130000 687.360000 ;
+ RECT 1847.130000 692.320000 1848.130000 692.800000 ;
+ RECT 1837.820000 692.320000 1838.920000 692.800000 ;
+ RECT 1837.820000 686.880000 1838.920000 687.360000 ;
+ RECT 1837.820000 681.440000 1838.920000 681.920000 ;
+ RECT 1837.820000 676.000000 1838.920000 676.480000 ;
+ RECT 1847.130000 681.440000 1848.130000 681.920000 ;
+ RECT 1847.130000 676.000000 1848.130000 676.480000 ;
+ RECT 1847.130000 659.680000 1848.130000 660.160000 ;
+ RECT 1847.130000 665.120000 1848.130000 665.600000 ;
+ RECT 1847.130000 670.560000 1848.130000 671.040000 ;
+ RECT 1837.820000 665.120000 1838.920000 665.600000 ;
+ RECT 1837.820000 659.680000 1838.920000 660.160000 ;
+ RECT 1837.820000 670.560000 1838.920000 671.040000 ;
+ RECT 1837.820000 654.240000 1838.920000 654.720000 ;
+ RECT 1837.820000 648.800000 1838.920000 649.280000 ;
+ RECT 1847.130000 654.240000 1848.130000 654.720000 ;
+ RECT 1847.130000 648.800000 1848.130000 649.280000 ;
+ RECT 1792.820000 692.320000 1793.920000 692.800000 ;
+ RECT 1792.820000 686.880000 1793.920000 687.360000 ;
+ RECT 1792.820000 681.440000 1793.920000 681.920000 ;
+ RECT 1792.820000 676.000000 1793.920000 676.480000 ;
+ RECT 1792.820000 665.120000 1793.920000 665.600000 ;
+ RECT 1792.820000 659.680000 1793.920000 660.160000 ;
+ RECT 1792.820000 654.240000 1793.920000 654.720000 ;
+ RECT 1792.820000 648.800000 1793.920000 649.280000 ;
+ RECT 1792.820000 670.560000 1793.920000 671.040000 ;
+ RECT 1747.820000 735.840000 1748.920000 736.320000 ;
+ RECT 1747.820000 730.400000 1748.920000 730.880000 ;
+ RECT 1747.820000 724.960000 1748.920000 725.440000 ;
+ RECT 1702.820000 735.840000 1703.920000 736.320000 ;
+ RECT 1702.820000 730.400000 1703.920000 730.880000 ;
+ RECT 1702.820000 724.960000 1703.920000 725.440000 ;
+ RECT 1747.820000 708.640000 1748.920000 709.120000 ;
+ RECT 1747.820000 703.200000 1748.920000 703.680000 ;
+ RECT 1747.820000 697.760000 1748.920000 698.240000 ;
+ RECT 1747.820000 714.080000 1748.920000 714.560000 ;
+ RECT 1747.820000 719.520000 1748.920000 720.000000 ;
+ RECT 1702.820000 719.520000 1703.920000 720.000000 ;
+ RECT 1702.820000 708.640000 1703.920000 709.120000 ;
+ RECT 1702.820000 703.200000 1703.920000 703.680000 ;
+ RECT 1702.820000 697.760000 1703.920000 698.240000 ;
+ RECT 1702.820000 714.080000 1703.920000 714.560000 ;
+ RECT 1657.820000 735.840000 1658.920000 736.320000 ;
+ RECT 1653.690000 735.840000 1654.690000 736.320000 ;
+ RECT 1653.690000 730.400000 1654.690000 730.880000 ;
+ RECT 1657.820000 730.400000 1658.920000 730.880000 ;
+ RECT 1657.820000 724.960000 1658.920000 725.440000 ;
+ RECT 1653.690000 724.960000 1654.690000 725.440000 ;
+ RECT 1657.820000 719.520000 1658.920000 720.000000 ;
+ RECT 1653.690000 719.520000 1654.690000 720.000000 ;
+ RECT 1657.820000 714.080000 1658.920000 714.560000 ;
+ RECT 1653.690000 714.080000 1654.690000 714.560000 ;
+ RECT 1657.820000 703.200000 1658.920000 703.680000 ;
+ RECT 1653.690000 703.200000 1654.690000 703.680000 ;
+ RECT 1657.820000 697.760000 1658.920000 698.240000 ;
+ RECT 1653.690000 697.760000 1654.690000 698.240000 ;
+ RECT 1657.820000 708.640000 1658.920000 709.120000 ;
+ RECT 1653.690000 708.640000 1654.690000 709.120000 ;
+ RECT 1747.820000 692.320000 1748.920000 692.800000 ;
+ RECT 1747.820000 686.880000 1748.920000 687.360000 ;
+ RECT 1747.820000 681.440000 1748.920000 681.920000 ;
+ RECT 1747.820000 676.000000 1748.920000 676.480000 ;
+ RECT 1702.820000 692.320000 1703.920000 692.800000 ;
+ RECT 1702.820000 686.880000 1703.920000 687.360000 ;
+ RECT 1702.820000 681.440000 1703.920000 681.920000 ;
+ RECT 1702.820000 676.000000 1703.920000 676.480000 ;
+ RECT 1747.820000 665.120000 1748.920000 665.600000 ;
+ RECT 1747.820000 648.800000 1748.920000 649.280000 ;
+ RECT 1747.820000 654.240000 1748.920000 654.720000 ;
+ RECT 1747.820000 659.680000 1748.920000 660.160000 ;
+ RECT 1747.820000 670.560000 1748.920000 671.040000 ;
+ RECT 1702.820000 648.800000 1703.920000 649.280000 ;
+ RECT 1702.820000 654.240000 1703.920000 654.720000 ;
+ RECT 1702.820000 659.680000 1703.920000 660.160000 ;
+ RECT 1702.820000 665.120000 1703.920000 665.600000 ;
+ RECT 1702.820000 670.560000 1703.920000 671.040000 ;
+ RECT 1657.820000 692.320000 1658.920000 692.800000 ;
+ RECT 1653.690000 692.320000 1654.690000 692.800000 ;
+ RECT 1657.820000 686.880000 1658.920000 687.360000 ;
+ RECT 1653.690000 686.880000 1654.690000 687.360000 ;
+ RECT 1657.820000 681.440000 1658.920000 681.920000 ;
+ RECT 1653.690000 681.440000 1654.690000 681.920000 ;
+ RECT 1657.820000 676.000000 1658.920000 676.480000 ;
+ RECT 1653.690000 676.000000 1654.690000 676.480000 ;
+ RECT 1657.820000 670.560000 1658.920000 671.040000 ;
+ RECT 1657.820000 665.120000 1658.920000 665.600000 ;
+ RECT 1653.690000 670.560000 1654.690000 671.040000 ;
+ RECT 1653.690000 665.120000 1654.690000 665.600000 ;
+ RECT 1657.820000 659.680000 1658.920000 660.160000 ;
+ RECT 1653.690000 659.680000 1654.690000 660.160000 ;
+ RECT 1657.820000 654.240000 1658.920000 654.720000 ;
+ RECT 1653.690000 654.240000 1654.690000 654.720000 ;
+ RECT 1657.820000 648.800000 1658.920000 649.280000 ;
+ RECT 1653.690000 648.800000 1654.690000 649.280000 ;
+ RECT 1837.820000 643.360000 1838.920000 643.840000 ;
+ RECT 1837.820000 637.920000 1838.920000 638.400000 ;
+ RECT 1847.130000 643.360000 1848.130000 643.840000 ;
+ RECT 1847.130000 637.920000 1848.130000 638.400000 ;
+ RECT 1847.130000 621.600000 1848.130000 622.080000 ;
+ RECT 1847.130000 627.040000 1848.130000 627.520000 ;
+ RECT 1847.130000 632.480000 1848.130000 632.960000 ;
+ RECT 1837.820000 632.480000 1838.920000 632.960000 ;
+ RECT 1837.820000 627.040000 1838.920000 627.520000 ;
+ RECT 1837.820000 621.600000 1838.920000 622.080000 ;
+ RECT 1837.820000 610.720000 1838.920000 611.200000 ;
+ RECT 1837.820000 616.160000 1838.920000 616.640000 ;
+ RECT 1847.130000 616.160000 1848.130000 616.640000 ;
+ RECT 1847.130000 610.720000 1848.130000 611.200000 ;
+ RECT 1847.130000 599.840000 1848.130000 600.320000 ;
+ RECT 1847.130000 605.280000 1848.130000 605.760000 ;
+ RECT 1837.820000 599.840000 1838.920000 600.320000 ;
+ RECT 1837.820000 605.280000 1838.920000 605.760000 ;
+ RECT 1792.820000 643.360000 1793.920000 643.840000 ;
+ RECT 1792.820000 637.920000 1793.920000 638.400000 ;
+ RECT 1792.820000 632.480000 1793.920000 632.960000 ;
+ RECT 1792.820000 627.040000 1793.920000 627.520000 ;
+ RECT 1792.820000 621.600000 1793.920000 622.080000 ;
+ RECT 1792.820000 599.840000 1793.920000 600.320000 ;
+ RECT 1792.820000 605.280000 1793.920000 605.760000 ;
+ RECT 1792.820000 610.720000 1793.920000 611.200000 ;
+ RECT 1792.820000 616.160000 1793.920000 616.640000 ;
+ RECT 1837.820000 594.400000 1838.920000 594.880000 ;
+ RECT 1837.820000 588.960000 1838.920000 589.440000 ;
+ RECT 1847.130000 594.400000 1848.130000 594.880000 ;
+ RECT 1847.130000 588.960000 1848.130000 589.440000 ;
+ RECT 1837.820000 578.080000 1838.920000 578.560000 ;
+ RECT 1837.820000 572.640000 1838.920000 573.120000 ;
+ RECT 1847.130000 578.080000 1848.130000 578.560000 ;
+ RECT 1847.130000 572.640000 1848.130000 573.120000 ;
+ RECT 1837.820000 583.520000 1838.920000 584.000000 ;
+ RECT 1847.130000 583.520000 1848.130000 584.000000 ;
+ RECT 1847.130000 561.760000 1848.130000 562.240000 ;
+ RECT 1847.130000 567.200000 1848.130000 567.680000 ;
+ RECT 1837.820000 567.200000 1838.920000 567.680000 ;
+ RECT 1837.820000 561.760000 1838.920000 562.240000 ;
+ RECT 1837.820000 556.320000 1838.920000 556.800000 ;
+ RECT 1837.820000 550.880000 1838.920000 551.360000 ;
+ RECT 1847.130000 556.320000 1848.130000 556.800000 ;
+ RECT 1847.130000 550.880000 1848.130000 551.360000 ;
+ RECT 1792.820000 594.400000 1793.920000 594.880000 ;
+ RECT 1792.820000 588.960000 1793.920000 589.440000 ;
+ RECT 1792.820000 583.520000 1793.920000 584.000000 ;
+ RECT 1792.820000 578.080000 1793.920000 578.560000 ;
+ RECT 1792.820000 572.640000 1793.920000 573.120000 ;
+ RECT 1792.820000 567.200000 1793.920000 567.680000 ;
+ RECT 1792.820000 561.760000 1793.920000 562.240000 ;
+ RECT 1792.820000 556.320000 1793.920000 556.800000 ;
+ RECT 1792.820000 550.880000 1793.920000 551.360000 ;
+ RECT 1747.820000 643.360000 1748.920000 643.840000 ;
+ RECT 1747.820000 637.920000 1748.920000 638.400000 ;
+ RECT 1747.820000 632.480000 1748.920000 632.960000 ;
+ RECT 1747.820000 627.040000 1748.920000 627.520000 ;
+ RECT 1747.820000 621.600000 1748.920000 622.080000 ;
+ RECT 1702.820000 643.360000 1703.920000 643.840000 ;
+ RECT 1702.820000 637.920000 1703.920000 638.400000 ;
+ RECT 1702.820000 632.480000 1703.920000 632.960000 ;
+ RECT 1702.820000 627.040000 1703.920000 627.520000 ;
+ RECT 1702.820000 621.600000 1703.920000 622.080000 ;
+ RECT 1747.820000 616.160000 1748.920000 616.640000 ;
+ RECT 1747.820000 610.720000 1748.920000 611.200000 ;
+ RECT 1747.820000 605.280000 1748.920000 605.760000 ;
+ RECT 1747.820000 599.840000 1748.920000 600.320000 ;
+ RECT 1702.820000 610.720000 1703.920000 611.200000 ;
+ RECT 1702.820000 605.280000 1703.920000 605.760000 ;
+ RECT 1702.820000 599.840000 1703.920000 600.320000 ;
+ RECT 1702.820000 616.160000 1703.920000 616.640000 ;
+ RECT 1657.820000 643.360000 1658.920000 643.840000 ;
+ RECT 1653.690000 643.360000 1654.690000 643.840000 ;
+ RECT 1657.820000 637.920000 1658.920000 638.400000 ;
+ RECT 1653.690000 637.920000 1654.690000 638.400000 ;
+ RECT 1657.820000 632.480000 1658.920000 632.960000 ;
+ RECT 1653.690000 632.480000 1654.690000 632.960000 ;
+ RECT 1657.820000 621.600000 1658.920000 622.080000 ;
+ RECT 1653.690000 621.600000 1654.690000 622.080000 ;
+ RECT 1653.690000 627.040000 1654.690000 627.520000 ;
+ RECT 1657.820000 627.040000 1658.920000 627.520000 ;
+ RECT 1657.820000 616.160000 1658.920000 616.640000 ;
+ RECT 1653.690000 616.160000 1654.690000 616.640000 ;
+ RECT 1657.820000 610.720000 1658.920000 611.200000 ;
+ RECT 1653.690000 610.720000 1654.690000 611.200000 ;
+ RECT 1657.820000 605.280000 1658.920000 605.760000 ;
+ RECT 1653.690000 605.280000 1654.690000 605.760000 ;
+ RECT 1657.820000 599.840000 1658.920000 600.320000 ;
+ RECT 1653.690000 599.840000 1654.690000 600.320000 ;
+ RECT 1747.820000 594.400000 1748.920000 594.880000 ;
+ RECT 1747.820000 588.960000 1748.920000 589.440000 ;
+ RECT 1747.820000 583.520000 1748.920000 584.000000 ;
+ RECT 1747.820000 578.080000 1748.920000 578.560000 ;
+ RECT 1747.820000 572.640000 1748.920000 573.120000 ;
+ RECT 1702.820000 594.400000 1703.920000 594.880000 ;
+ RECT 1702.820000 588.960000 1703.920000 589.440000 ;
+ RECT 1702.820000 583.520000 1703.920000 584.000000 ;
+ RECT 1702.820000 578.080000 1703.920000 578.560000 ;
+ RECT 1702.820000 572.640000 1703.920000 573.120000 ;
+ RECT 1747.820000 550.880000 1748.920000 551.360000 ;
+ RECT 1747.820000 556.320000 1748.920000 556.800000 ;
+ RECT 1747.820000 561.760000 1748.920000 562.240000 ;
+ RECT 1747.820000 567.200000 1748.920000 567.680000 ;
+ RECT 1702.820000 550.880000 1703.920000 551.360000 ;
+ RECT 1702.820000 556.320000 1703.920000 556.800000 ;
+ RECT 1702.820000 561.760000 1703.920000 562.240000 ;
+ RECT 1702.820000 567.200000 1703.920000 567.680000 ;
+ RECT 1657.820000 594.400000 1658.920000 594.880000 ;
+ RECT 1653.690000 594.400000 1654.690000 594.880000 ;
+ RECT 1657.820000 588.960000 1658.920000 589.440000 ;
+ RECT 1653.690000 588.960000 1654.690000 589.440000 ;
+ RECT 1657.820000 578.080000 1658.920000 578.560000 ;
+ RECT 1653.690000 578.080000 1654.690000 578.560000 ;
+ RECT 1657.820000 572.640000 1658.920000 573.120000 ;
+ RECT 1653.690000 572.640000 1654.690000 573.120000 ;
+ RECT 1657.820000 583.520000 1658.920000 584.000000 ;
+ RECT 1653.690000 583.520000 1654.690000 584.000000 ;
+ RECT 1657.820000 567.200000 1658.920000 567.680000 ;
+ RECT 1653.690000 567.200000 1654.690000 567.680000 ;
+ RECT 1657.820000 561.760000 1658.920000 562.240000 ;
+ RECT 1653.690000 561.760000 1654.690000 562.240000 ;
+ RECT 1657.820000 556.320000 1658.920000 556.800000 ;
+ RECT 1657.820000 550.880000 1658.920000 551.360000 ;
+ RECT 1653.690000 556.320000 1654.690000 556.800000 ;
+ RECT 1653.690000 550.880000 1654.690000 551.360000 ;
+ RECT 1650.860000 741.240000 1850.960000 742.240000 ;
+ RECT 1650.860000 548.870000 1850.960000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 546.020000 1654.690000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 745.280000 1654.690000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 546.020000 1848.130000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 745.280000 1848.130000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 548.870000 1651.860000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 548.870000 1850.960000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 741.240000 1651.860000 742.240000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 741.240000 1850.960000 742.240000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 348.610000 1838.920000 541.980000 ;
+ RECT 1792.820000 348.610000 1793.920000 541.980000 ;
+ RECT 1847.130000 345.760000 1848.130000 546.020000 ;
+ RECT 1747.820000 348.610000 1748.920000 541.980000 ;
+ RECT 1702.820000 348.610000 1703.920000 541.980000 ;
+ RECT 1657.820000 348.610000 1658.920000 541.980000 ;
+ RECT 1653.690000 345.760000 1654.690000 546.020000 ;
+ LAYER met3 ;
+ RECT 1837.820000 535.580000 1838.920000 536.060000 ;
+ RECT 1847.130000 535.580000 1848.130000 536.060000 ;
+ RECT 1847.130000 524.700000 1848.130000 525.180000 ;
+ RECT 1847.130000 530.140000 1848.130000 530.620000 ;
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+ RECT 1837.820000 519.260000 1838.920000 519.740000 ;
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+ RECT 1847.130000 513.820000 1848.130000 514.300000 ;
+ RECT 1837.820000 497.500000 1838.920000 497.980000 ;
+ RECT 1837.820000 502.940000 1838.920000 503.420000 ;
+ RECT 1847.130000 502.940000 1848.130000 503.420000 ;
+ RECT 1847.130000 497.500000 1848.130000 497.980000 ;
+ RECT 1837.820000 508.380000 1838.920000 508.860000 ;
+ RECT 1847.130000 508.380000 1848.130000 508.860000 ;
+ RECT 1792.820000 535.580000 1793.920000 536.060000 ;
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+ RECT 1847.130000 486.620000 1848.130000 487.100000 ;
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+ RECT 1837.820000 481.180000 1838.920000 481.660000 ;
+ RECT 1837.820000 475.740000 1838.920000 476.220000 ;
+ RECT 1847.130000 481.180000 1848.130000 481.660000 ;
+ RECT 1847.130000 475.740000 1848.130000 476.220000 ;
+ RECT 1847.130000 459.420000 1848.130000 459.900000 ;
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+ RECT 1847.130000 470.300000 1848.130000 470.780000 ;
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+ RECT 1837.820000 470.300000 1838.920000 470.780000 ;
+ RECT 1837.820000 453.980000 1838.920000 454.460000 ;
+ RECT 1837.820000 448.540000 1838.920000 449.020000 ;
+ RECT 1847.130000 453.980000 1848.130000 454.460000 ;
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+ RECT 1792.820000 492.060000 1793.920000 492.540000 ;
+ RECT 1792.820000 486.620000 1793.920000 487.100000 ;
+ RECT 1792.820000 481.180000 1793.920000 481.660000 ;
+ RECT 1792.820000 475.740000 1793.920000 476.220000 ;
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+ RECT 1792.820000 459.420000 1793.920000 459.900000 ;
+ RECT 1792.820000 453.980000 1793.920000 454.460000 ;
+ RECT 1792.820000 448.540000 1793.920000 449.020000 ;
+ RECT 1792.820000 470.300000 1793.920000 470.780000 ;
+ RECT 1747.820000 535.580000 1748.920000 536.060000 ;
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+ RECT 1747.820000 524.700000 1748.920000 525.180000 ;
+ RECT 1702.820000 535.580000 1703.920000 536.060000 ;
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+ RECT 1747.820000 508.380000 1748.920000 508.860000 ;
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+ RECT 1702.820000 508.380000 1703.920000 508.860000 ;
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+ RECT 1702.820000 497.500000 1703.920000 497.980000 ;
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+ RECT 1657.820000 535.580000 1658.920000 536.060000 ;
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+ RECT 1657.820000 519.260000 1658.920000 519.740000 ;
+ RECT 1653.690000 519.260000 1654.690000 519.740000 ;
+ RECT 1657.820000 513.820000 1658.920000 514.300000 ;
+ RECT 1653.690000 513.820000 1654.690000 514.300000 ;
+ RECT 1657.820000 502.940000 1658.920000 503.420000 ;
+ RECT 1653.690000 502.940000 1654.690000 503.420000 ;
+ RECT 1657.820000 497.500000 1658.920000 497.980000 ;
+ RECT 1653.690000 497.500000 1654.690000 497.980000 ;
+ RECT 1657.820000 508.380000 1658.920000 508.860000 ;
+ RECT 1653.690000 508.380000 1654.690000 508.860000 ;
+ RECT 1747.820000 492.060000 1748.920000 492.540000 ;
+ RECT 1747.820000 486.620000 1748.920000 487.100000 ;
+ RECT 1747.820000 481.180000 1748.920000 481.660000 ;
+ RECT 1747.820000 475.740000 1748.920000 476.220000 ;
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+ RECT 1702.820000 481.180000 1703.920000 481.660000 ;
+ RECT 1702.820000 475.740000 1703.920000 476.220000 ;
+ RECT 1747.820000 464.860000 1748.920000 465.340000 ;
+ RECT 1747.820000 448.540000 1748.920000 449.020000 ;
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+ RECT 1747.820000 459.420000 1748.920000 459.900000 ;
+ RECT 1747.820000 470.300000 1748.920000 470.780000 ;
+ RECT 1702.820000 448.540000 1703.920000 449.020000 ;
+ RECT 1702.820000 453.980000 1703.920000 454.460000 ;
+ RECT 1702.820000 459.420000 1703.920000 459.900000 ;
+ RECT 1702.820000 464.860000 1703.920000 465.340000 ;
+ RECT 1702.820000 470.300000 1703.920000 470.780000 ;
+ RECT 1657.820000 492.060000 1658.920000 492.540000 ;
+ RECT 1653.690000 492.060000 1654.690000 492.540000 ;
+ RECT 1657.820000 486.620000 1658.920000 487.100000 ;
+ RECT 1653.690000 486.620000 1654.690000 487.100000 ;
+ RECT 1657.820000 481.180000 1658.920000 481.660000 ;
+ RECT 1653.690000 481.180000 1654.690000 481.660000 ;
+ RECT 1657.820000 475.740000 1658.920000 476.220000 ;
+ RECT 1653.690000 475.740000 1654.690000 476.220000 ;
+ RECT 1657.820000 470.300000 1658.920000 470.780000 ;
+ RECT 1657.820000 464.860000 1658.920000 465.340000 ;
+ RECT 1653.690000 470.300000 1654.690000 470.780000 ;
+ RECT 1653.690000 464.860000 1654.690000 465.340000 ;
+ RECT 1657.820000 459.420000 1658.920000 459.900000 ;
+ RECT 1653.690000 459.420000 1654.690000 459.900000 ;
+ RECT 1657.820000 453.980000 1658.920000 454.460000 ;
+ RECT 1653.690000 453.980000 1654.690000 454.460000 ;
+ RECT 1657.820000 448.540000 1658.920000 449.020000 ;
+ RECT 1653.690000 448.540000 1654.690000 449.020000 ;
+ RECT 1837.820000 443.100000 1838.920000 443.580000 ;
+ RECT 1837.820000 437.660000 1838.920000 438.140000 ;
+ RECT 1847.130000 443.100000 1848.130000 443.580000 ;
+ RECT 1847.130000 437.660000 1848.130000 438.140000 ;
+ RECT 1847.130000 421.340000 1848.130000 421.820000 ;
+ RECT 1847.130000 426.780000 1848.130000 427.260000 ;
+ RECT 1847.130000 432.220000 1848.130000 432.700000 ;
+ RECT 1837.820000 432.220000 1838.920000 432.700000 ;
+ RECT 1837.820000 426.780000 1838.920000 427.260000 ;
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+ RECT 1837.820000 410.460000 1838.920000 410.940000 ;
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+ RECT 1847.130000 410.460000 1848.130000 410.940000 ;
+ RECT 1847.130000 399.580000 1848.130000 400.060000 ;
+ RECT 1847.130000 405.020000 1848.130000 405.500000 ;
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+ RECT 1792.820000 426.780000 1793.920000 427.260000 ;
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+ RECT 1792.820000 399.580000 1793.920000 400.060000 ;
+ RECT 1792.820000 405.020000 1793.920000 405.500000 ;
+ RECT 1792.820000 410.460000 1793.920000 410.940000 ;
+ RECT 1792.820000 415.900000 1793.920000 416.380000 ;
+ RECT 1837.820000 394.140000 1838.920000 394.620000 ;
+ RECT 1837.820000 388.700000 1838.920000 389.180000 ;
+ RECT 1847.130000 394.140000 1848.130000 394.620000 ;
+ RECT 1847.130000 388.700000 1848.130000 389.180000 ;
+ RECT 1837.820000 377.820000 1838.920000 378.300000 ;
+ RECT 1837.820000 372.380000 1838.920000 372.860000 ;
+ RECT 1847.130000 377.820000 1848.130000 378.300000 ;
+ RECT 1847.130000 372.380000 1848.130000 372.860000 ;
+ RECT 1837.820000 383.260000 1838.920000 383.740000 ;
+ RECT 1847.130000 383.260000 1848.130000 383.740000 ;
+ RECT 1847.130000 361.500000 1848.130000 361.980000 ;
+ RECT 1847.130000 366.940000 1848.130000 367.420000 ;
+ RECT 1837.820000 366.940000 1838.920000 367.420000 ;
+ RECT 1837.820000 361.500000 1838.920000 361.980000 ;
+ RECT 1837.820000 356.060000 1838.920000 356.540000 ;
+ RECT 1837.820000 350.620000 1838.920000 351.100000 ;
+ RECT 1847.130000 356.060000 1848.130000 356.540000 ;
+ RECT 1847.130000 350.620000 1848.130000 351.100000 ;
+ RECT 1792.820000 394.140000 1793.920000 394.620000 ;
+ RECT 1792.820000 388.700000 1793.920000 389.180000 ;
+ RECT 1792.820000 383.260000 1793.920000 383.740000 ;
+ RECT 1792.820000 377.820000 1793.920000 378.300000 ;
+ RECT 1792.820000 372.380000 1793.920000 372.860000 ;
+ RECT 1792.820000 366.940000 1793.920000 367.420000 ;
+ RECT 1792.820000 361.500000 1793.920000 361.980000 ;
+ RECT 1792.820000 356.060000 1793.920000 356.540000 ;
+ RECT 1792.820000 350.620000 1793.920000 351.100000 ;
+ RECT 1747.820000 443.100000 1748.920000 443.580000 ;
+ RECT 1747.820000 437.660000 1748.920000 438.140000 ;
+ RECT 1747.820000 432.220000 1748.920000 432.700000 ;
+ RECT 1747.820000 426.780000 1748.920000 427.260000 ;
+ RECT 1747.820000 421.340000 1748.920000 421.820000 ;
+ RECT 1702.820000 443.100000 1703.920000 443.580000 ;
+ RECT 1702.820000 437.660000 1703.920000 438.140000 ;
+ RECT 1702.820000 432.220000 1703.920000 432.700000 ;
+ RECT 1702.820000 426.780000 1703.920000 427.260000 ;
+ RECT 1702.820000 421.340000 1703.920000 421.820000 ;
+ RECT 1747.820000 415.900000 1748.920000 416.380000 ;
+ RECT 1747.820000 410.460000 1748.920000 410.940000 ;
+ RECT 1747.820000 405.020000 1748.920000 405.500000 ;
+ RECT 1747.820000 399.580000 1748.920000 400.060000 ;
+ RECT 1702.820000 410.460000 1703.920000 410.940000 ;
+ RECT 1702.820000 405.020000 1703.920000 405.500000 ;
+ RECT 1702.820000 399.580000 1703.920000 400.060000 ;
+ RECT 1702.820000 415.900000 1703.920000 416.380000 ;
+ RECT 1657.820000 443.100000 1658.920000 443.580000 ;
+ RECT 1653.690000 443.100000 1654.690000 443.580000 ;
+ RECT 1657.820000 437.660000 1658.920000 438.140000 ;
+ RECT 1653.690000 437.660000 1654.690000 438.140000 ;
+ RECT 1657.820000 432.220000 1658.920000 432.700000 ;
+ RECT 1653.690000 432.220000 1654.690000 432.700000 ;
+ RECT 1657.820000 421.340000 1658.920000 421.820000 ;
+ RECT 1653.690000 421.340000 1654.690000 421.820000 ;
+ RECT 1653.690000 426.780000 1654.690000 427.260000 ;
+ RECT 1657.820000 426.780000 1658.920000 427.260000 ;
+ RECT 1657.820000 415.900000 1658.920000 416.380000 ;
+ RECT 1653.690000 415.900000 1654.690000 416.380000 ;
+ RECT 1657.820000 410.460000 1658.920000 410.940000 ;
+ RECT 1653.690000 410.460000 1654.690000 410.940000 ;
+ RECT 1657.820000 405.020000 1658.920000 405.500000 ;
+ RECT 1653.690000 405.020000 1654.690000 405.500000 ;
+ RECT 1657.820000 399.580000 1658.920000 400.060000 ;
+ RECT 1653.690000 399.580000 1654.690000 400.060000 ;
+ RECT 1747.820000 394.140000 1748.920000 394.620000 ;
+ RECT 1747.820000 388.700000 1748.920000 389.180000 ;
+ RECT 1747.820000 383.260000 1748.920000 383.740000 ;
+ RECT 1747.820000 377.820000 1748.920000 378.300000 ;
+ RECT 1747.820000 372.380000 1748.920000 372.860000 ;
+ RECT 1702.820000 394.140000 1703.920000 394.620000 ;
+ RECT 1702.820000 388.700000 1703.920000 389.180000 ;
+ RECT 1702.820000 383.260000 1703.920000 383.740000 ;
+ RECT 1702.820000 377.820000 1703.920000 378.300000 ;
+ RECT 1702.820000 372.380000 1703.920000 372.860000 ;
+ RECT 1747.820000 350.620000 1748.920000 351.100000 ;
+ RECT 1747.820000 356.060000 1748.920000 356.540000 ;
+ RECT 1747.820000 361.500000 1748.920000 361.980000 ;
+ RECT 1747.820000 366.940000 1748.920000 367.420000 ;
+ RECT 1702.820000 350.620000 1703.920000 351.100000 ;
+ RECT 1702.820000 356.060000 1703.920000 356.540000 ;
+ RECT 1702.820000 361.500000 1703.920000 361.980000 ;
+ RECT 1702.820000 366.940000 1703.920000 367.420000 ;
+ RECT 1657.820000 394.140000 1658.920000 394.620000 ;
+ RECT 1653.690000 394.140000 1654.690000 394.620000 ;
+ RECT 1657.820000 388.700000 1658.920000 389.180000 ;
+ RECT 1653.690000 388.700000 1654.690000 389.180000 ;
+ RECT 1657.820000 377.820000 1658.920000 378.300000 ;
+ RECT 1653.690000 377.820000 1654.690000 378.300000 ;
+ RECT 1657.820000 372.380000 1658.920000 372.860000 ;
+ RECT 1653.690000 372.380000 1654.690000 372.860000 ;
+ RECT 1657.820000 383.260000 1658.920000 383.740000 ;
+ RECT 1653.690000 383.260000 1654.690000 383.740000 ;
+ RECT 1657.820000 366.940000 1658.920000 367.420000 ;
+ RECT 1653.690000 366.940000 1654.690000 367.420000 ;
+ RECT 1657.820000 361.500000 1658.920000 361.980000 ;
+ RECT 1653.690000 361.500000 1654.690000 361.980000 ;
+ RECT 1657.820000 356.060000 1658.920000 356.540000 ;
+ RECT 1657.820000 350.620000 1658.920000 351.100000 ;
+ RECT 1653.690000 356.060000 1654.690000 356.540000 ;
+ RECT 1653.690000 350.620000 1654.690000 351.100000 ;
+ RECT 1650.860000 540.980000 1850.960000 541.980000 ;
+ RECT 1650.860000 348.610000 1850.960000 349.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 345.760000 1654.690000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 545.020000 1654.690000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 345.760000 1848.130000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 545.020000 1848.130000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 348.610000 1651.860000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 348.610000 1850.960000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 540.980000 1651.860000 541.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 540.980000 1850.960000 541.980000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 148.350000 1838.920000 341.720000 ;
+ RECT 1792.820000 148.350000 1793.920000 341.720000 ;
+ RECT 1847.130000 145.500000 1848.130000 345.760000 ;
+ RECT 1747.820000 148.350000 1748.920000 341.720000 ;
+ RECT 1702.820000 148.350000 1703.920000 341.720000 ;
+ RECT 1657.820000 148.350000 1658.920000 341.720000 ;
+ RECT 1653.690000 145.500000 1654.690000 345.760000 ;
+ LAYER met3 ;
+ RECT 1837.820000 335.320000 1838.920000 335.800000 ;
+ RECT 1847.130000 335.320000 1848.130000 335.800000 ;
+ RECT 1847.130000 324.440000 1848.130000 324.920000 ;
+ RECT 1847.130000 329.880000 1848.130000 330.360000 ;
+ RECT 1837.820000 329.880000 1838.920000 330.360000 ;
+ RECT 1837.820000 324.440000 1838.920000 324.920000 ;
+ RECT 1837.820000 319.000000 1838.920000 319.480000 ;
+ RECT 1837.820000 313.560000 1838.920000 314.040000 ;
+ RECT 1847.130000 319.000000 1848.130000 319.480000 ;
+ RECT 1847.130000 313.560000 1848.130000 314.040000 ;
+ RECT 1837.820000 297.240000 1838.920000 297.720000 ;
+ RECT 1837.820000 302.680000 1838.920000 303.160000 ;
+ RECT 1847.130000 302.680000 1848.130000 303.160000 ;
+ RECT 1847.130000 297.240000 1848.130000 297.720000 ;
+ RECT 1837.820000 308.120000 1838.920000 308.600000 ;
+ RECT 1847.130000 308.120000 1848.130000 308.600000 ;
+ RECT 1792.820000 335.320000 1793.920000 335.800000 ;
+ RECT 1792.820000 329.880000 1793.920000 330.360000 ;
+ RECT 1792.820000 324.440000 1793.920000 324.920000 ;
+ RECT 1792.820000 319.000000 1793.920000 319.480000 ;
+ RECT 1792.820000 297.240000 1793.920000 297.720000 ;
+ RECT 1792.820000 302.680000 1793.920000 303.160000 ;
+ RECT 1792.820000 308.120000 1793.920000 308.600000 ;
+ RECT 1792.820000 313.560000 1793.920000 314.040000 ;
+ RECT 1847.130000 286.360000 1848.130000 286.840000 ;
+ RECT 1847.130000 291.800000 1848.130000 292.280000 ;
+ RECT 1837.820000 291.800000 1838.920000 292.280000 ;
+ RECT 1837.820000 286.360000 1838.920000 286.840000 ;
+ RECT 1837.820000 280.920000 1838.920000 281.400000 ;
+ RECT 1837.820000 275.480000 1838.920000 275.960000 ;
+ RECT 1847.130000 280.920000 1848.130000 281.400000 ;
+ RECT 1847.130000 275.480000 1848.130000 275.960000 ;
+ RECT 1847.130000 259.160000 1848.130000 259.640000 ;
+ RECT 1847.130000 264.600000 1848.130000 265.080000 ;
+ RECT 1847.130000 270.040000 1848.130000 270.520000 ;
+ RECT 1837.820000 264.600000 1838.920000 265.080000 ;
+ RECT 1837.820000 259.160000 1838.920000 259.640000 ;
+ RECT 1837.820000 270.040000 1838.920000 270.520000 ;
+ RECT 1837.820000 253.720000 1838.920000 254.200000 ;
+ RECT 1837.820000 248.280000 1838.920000 248.760000 ;
+ RECT 1847.130000 253.720000 1848.130000 254.200000 ;
+ RECT 1847.130000 248.280000 1848.130000 248.760000 ;
+ RECT 1792.820000 291.800000 1793.920000 292.280000 ;
+ RECT 1792.820000 286.360000 1793.920000 286.840000 ;
+ RECT 1792.820000 280.920000 1793.920000 281.400000 ;
+ RECT 1792.820000 275.480000 1793.920000 275.960000 ;
+ RECT 1792.820000 264.600000 1793.920000 265.080000 ;
+ RECT 1792.820000 259.160000 1793.920000 259.640000 ;
+ RECT 1792.820000 253.720000 1793.920000 254.200000 ;
+ RECT 1792.820000 248.280000 1793.920000 248.760000 ;
+ RECT 1792.820000 270.040000 1793.920000 270.520000 ;
+ RECT 1747.820000 335.320000 1748.920000 335.800000 ;
+ RECT 1747.820000 329.880000 1748.920000 330.360000 ;
+ RECT 1747.820000 324.440000 1748.920000 324.920000 ;
+ RECT 1702.820000 335.320000 1703.920000 335.800000 ;
+ RECT 1702.820000 329.880000 1703.920000 330.360000 ;
+ RECT 1702.820000 324.440000 1703.920000 324.920000 ;
+ RECT 1747.820000 308.120000 1748.920000 308.600000 ;
+ RECT 1747.820000 302.680000 1748.920000 303.160000 ;
+ RECT 1747.820000 297.240000 1748.920000 297.720000 ;
+ RECT 1747.820000 313.560000 1748.920000 314.040000 ;
+ RECT 1747.820000 319.000000 1748.920000 319.480000 ;
+ RECT 1702.820000 319.000000 1703.920000 319.480000 ;
+ RECT 1702.820000 308.120000 1703.920000 308.600000 ;
+ RECT 1702.820000 302.680000 1703.920000 303.160000 ;
+ RECT 1702.820000 297.240000 1703.920000 297.720000 ;
+ RECT 1702.820000 313.560000 1703.920000 314.040000 ;
+ RECT 1657.820000 335.320000 1658.920000 335.800000 ;
+ RECT 1653.690000 335.320000 1654.690000 335.800000 ;
+ RECT 1653.690000 329.880000 1654.690000 330.360000 ;
+ RECT 1657.820000 329.880000 1658.920000 330.360000 ;
+ RECT 1657.820000 324.440000 1658.920000 324.920000 ;
+ RECT 1653.690000 324.440000 1654.690000 324.920000 ;
+ RECT 1657.820000 319.000000 1658.920000 319.480000 ;
+ RECT 1653.690000 319.000000 1654.690000 319.480000 ;
+ RECT 1657.820000 313.560000 1658.920000 314.040000 ;
+ RECT 1653.690000 313.560000 1654.690000 314.040000 ;
+ RECT 1657.820000 302.680000 1658.920000 303.160000 ;
+ RECT 1653.690000 302.680000 1654.690000 303.160000 ;
+ RECT 1657.820000 297.240000 1658.920000 297.720000 ;
+ RECT 1653.690000 297.240000 1654.690000 297.720000 ;
+ RECT 1657.820000 308.120000 1658.920000 308.600000 ;
+ RECT 1653.690000 308.120000 1654.690000 308.600000 ;
+ RECT 1747.820000 291.800000 1748.920000 292.280000 ;
+ RECT 1747.820000 286.360000 1748.920000 286.840000 ;
+ RECT 1747.820000 280.920000 1748.920000 281.400000 ;
+ RECT 1747.820000 275.480000 1748.920000 275.960000 ;
+ RECT 1702.820000 291.800000 1703.920000 292.280000 ;
+ RECT 1702.820000 286.360000 1703.920000 286.840000 ;
+ RECT 1702.820000 280.920000 1703.920000 281.400000 ;
+ RECT 1702.820000 275.480000 1703.920000 275.960000 ;
+ RECT 1747.820000 264.600000 1748.920000 265.080000 ;
+ RECT 1747.820000 248.280000 1748.920000 248.760000 ;
+ RECT 1747.820000 253.720000 1748.920000 254.200000 ;
+ RECT 1747.820000 259.160000 1748.920000 259.640000 ;
+ RECT 1747.820000 270.040000 1748.920000 270.520000 ;
+ RECT 1702.820000 248.280000 1703.920000 248.760000 ;
+ RECT 1702.820000 253.720000 1703.920000 254.200000 ;
+ RECT 1702.820000 259.160000 1703.920000 259.640000 ;
+ RECT 1702.820000 264.600000 1703.920000 265.080000 ;
+ RECT 1702.820000 270.040000 1703.920000 270.520000 ;
+ RECT 1657.820000 291.800000 1658.920000 292.280000 ;
+ RECT 1653.690000 291.800000 1654.690000 292.280000 ;
+ RECT 1657.820000 286.360000 1658.920000 286.840000 ;
+ RECT 1653.690000 286.360000 1654.690000 286.840000 ;
+ RECT 1657.820000 280.920000 1658.920000 281.400000 ;
+ RECT 1653.690000 280.920000 1654.690000 281.400000 ;
+ RECT 1657.820000 275.480000 1658.920000 275.960000 ;
+ RECT 1653.690000 275.480000 1654.690000 275.960000 ;
+ RECT 1657.820000 270.040000 1658.920000 270.520000 ;
+ RECT 1657.820000 264.600000 1658.920000 265.080000 ;
+ RECT 1653.690000 270.040000 1654.690000 270.520000 ;
+ RECT 1653.690000 264.600000 1654.690000 265.080000 ;
+ RECT 1657.820000 259.160000 1658.920000 259.640000 ;
+ RECT 1653.690000 259.160000 1654.690000 259.640000 ;
+ RECT 1657.820000 253.720000 1658.920000 254.200000 ;
+ RECT 1653.690000 253.720000 1654.690000 254.200000 ;
+ RECT 1657.820000 248.280000 1658.920000 248.760000 ;
+ RECT 1653.690000 248.280000 1654.690000 248.760000 ;
+ RECT 1837.820000 242.840000 1838.920000 243.320000 ;
+ RECT 1837.820000 237.400000 1838.920000 237.880000 ;
+ RECT 1847.130000 242.840000 1848.130000 243.320000 ;
+ RECT 1847.130000 237.400000 1848.130000 237.880000 ;
+ RECT 1847.130000 221.080000 1848.130000 221.560000 ;
+ RECT 1847.130000 226.520000 1848.130000 227.000000 ;
+ RECT 1847.130000 231.960000 1848.130000 232.440000 ;
+ RECT 1837.820000 231.960000 1838.920000 232.440000 ;
+ RECT 1837.820000 226.520000 1838.920000 227.000000 ;
+ RECT 1837.820000 221.080000 1838.920000 221.560000 ;
+ RECT 1837.820000 210.200000 1838.920000 210.680000 ;
+ RECT 1837.820000 215.640000 1838.920000 216.120000 ;
+ RECT 1847.130000 215.640000 1848.130000 216.120000 ;
+ RECT 1847.130000 210.200000 1848.130000 210.680000 ;
+ RECT 1847.130000 199.320000 1848.130000 199.800000 ;
+ RECT 1847.130000 204.760000 1848.130000 205.240000 ;
+ RECT 1837.820000 199.320000 1838.920000 199.800000 ;
+ RECT 1837.820000 204.760000 1838.920000 205.240000 ;
+ RECT 1792.820000 242.840000 1793.920000 243.320000 ;
+ RECT 1792.820000 237.400000 1793.920000 237.880000 ;
+ RECT 1792.820000 231.960000 1793.920000 232.440000 ;
+ RECT 1792.820000 226.520000 1793.920000 227.000000 ;
+ RECT 1792.820000 221.080000 1793.920000 221.560000 ;
+ RECT 1792.820000 199.320000 1793.920000 199.800000 ;
+ RECT 1792.820000 204.760000 1793.920000 205.240000 ;
+ RECT 1792.820000 210.200000 1793.920000 210.680000 ;
+ RECT 1792.820000 215.640000 1793.920000 216.120000 ;
+ RECT 1837.820000 193.880000 1838.920000 194.360000 ;
+ RECT 1837.820000 188.440000 1838.920000 188.920000 ;
+ RECT 1847.130000 193.880000 1848.130000 194.360000 ;
+ RECT 1847.130000 188.440000 1848.130000 188.920000 ;
+ RECT 1837.820000 177.560000 1838.920000 178.040000 ;
+ RECT 1837.820000 172.120000 1838.920000 172.600000 ;
+ RECT 1847.130000 177.560000 1848.130000 178.040000 ;
+ RECT 1847.130000 172.120000 1848.130000 172.600000 ;
+ RECT 1837.820000 183.000000 1838.920000 183.480000 ;
+ RECT 1847.130000 183.000000 1848.130000 183.480000 ;
+ RECT 1847.130000 161.240000 1848.130000 161.720000 ;
+ RECT 1847.130000 166.680000 1848.130000 167.160000 ;
+ RECT 1837.820000 166.680000 1838.920000 167.160000 ;
+ RECT 1837.820000 161.240000 1838.920000 161.720000 ;
+ RECT 1837.820000 155.800000 1838.920000 156.280000 ;
+ RECT 1837.820000 150.360000 1838.920000 150.840000 ;
+ RECT 1847.130000 155.800000 1848.130000 156.280000 ;
+ RECT 1847.130000 150.360000 1848.130000 150.840000 ;
+ RECT 1792.820000 193.880000 1793.920000 194.360000 ;
+ RECT 1792.820000 188.440000 1793.920000 188.920000 ;
+ RECT 1792.820000 183.000000 1793.920000 183.480000 ;
+ RECT 1792.820000 177.560000 1793.920000 178.040000 ;
+ RECT 1792.820000 172.120000 1793.920000 172.600000 ;
+ RECT 1792.820000 166.680000 1793.920000 167.160000 ;
+ RECT 1792.820000 161.240000 1793.920000 161.720000 ;
+ RECT 1792.820000 155.800000 1793.920000 156.280000 ;
+ RECT 1792.820000 150.360000 1793.920000 150.840000 ;
+ RECT 1747.820000 242.840000 1748.920000 243.320000 ;
+ RECT 1747.820000 237.400000 1748.920000 237.880000 ;
+ RECT 1747.820000 231.960000 1748.920000 232.440000 ;
+ RECT 1747.820000 226.520000 1748.920000 227.000000 ;
+ RECT 1747.820000 221.080000 1748.920000 221.560000 ;
+ RECT 1702.820000 242.840000 1703.920000 243.320000 ;
+ RECT 1702.820000 237.400000 1703.920000 237.880000 ;
+ RECT 1702.820000 231.960000 1703.920000 232.440000 ;
+ RECT 1702.820000 226.520000 1703.920000 227.000000 ;
+ RECT 1702.820000 221.080000 1703.920000 221.560000 ;
+ RECT 1747.820000 215.640000 1748.920000 216.120000 ;
+ RECT 1747.820000 210.200000 1748.920000 210.680000 ;
+ RECT 1747.820000 204.760000 1748.920000 205.240000 ;
+ RECT 1747.820000 199.320000 1748.920000 199.800000 ;
+ RECT 1702.820000 210.200000 1703.920000 210.680000 ;
+ RECT 1702.820000 204.760000 1703.920000 205.240000 ;
+ RECT 1702.820000 199.320000 1703.920000 199.800000 ;
+ RECT 1702.820000 215.640000 1703.920000 216.120000 ;
+ RECT 1657.820000 242.840000 1658.920000 243.320000 ;
+ RECT 1653.690000 242.840000 1654.690000 243.320000 ;
+ RECT 1657.820000 237.400000 1658.920000 237.880000 ;
+ RECT 1653.690000 237.400000 1654.690000 237.880000 ;
+ RECT 1657.820000 231.960000 1658.920000 232.440000 ;
+ RECT 1653.690000 231.960000 1654.690000 232.440000 ;
+ RECT 1657.820000 221.080000 1658.920000 221.560000 ;
+ RECT 1653.690000 221.080000 1654.690000 221.560000 ;
+ RECT 1653.690000 226.520000 1654.690000 227.000000 ;
+ RECT 1657.820000 226.520000 1658.920000 227.000000 ;
+ RECT 1657.820000 215.640000 1658.920000 216.120000 ;
+ RECT 1653.690000 215.640000 1654.690000 216.120000 ;
+ RECT 1657.820000 210.200000 1658.920000 210.680000 ;
+ RECT 1653.690000 210.200000 1654.690000 210.680000 ;
+ RECT 1657.820000 204.760000 1658.920000 205.240000 ;
+ RECT 1653.690000 204.760000 1654.690000 205.240000 ;
+ RECT 1657.820000 199.320000 1658.920000 199.800000 ;
+ RECT 1653.690000 199.320000 1654.690000 199.800000 ;
+ RECT 1747.820000 193.880000 1748.920000 194.360000 ;
+ RECT 1747.820000 188.440000 1748.920000 188.920000 ;
+ RECT 1747.820000 183.000000 1748.920000 183.480000 ;
+ RECT 1747.820000 177.560000 1748.920000 178.040000 ;
+ RECT 1747.820000 172.120000 1748.920000 172.600000 ;
+ RECT 1702.820000 193.880000 1703.920000 194.360000 ;
+ RECT 1702.820000 188.440000 1703.920000 188.920000 ;
+ RECT 1702.820000 183.000000 1703.920000 183.480000 ;
+ RECT 1702.820000 177.560000 1703.920000 178.040000 ;
+ RECT 1702.820000 172.120000 1703.920000 172.600000 ;
+ RECT 1747.820000 150.360000 1748.920000 150.840000 ;
+ RECT 1747.820000 155.800000 1748.920000 156.280000 ;
+ RECT 1747.820000 161.240000 1748.920000 161.720000 ;
+ RECT 1747.820000 166.680000 1748.920000 167.160000 ;
+ RECT 1702.820000 150.360000 1703.920000 150.840000 ;
+ RECT 1702.820000 155.800000 1703.920000 156.280000 ;
+ RECT 1702.820000 161.240000 1703.920000 161.720000 ;
+ RECT 1702.820000 166.680000 1703.920000 167.160000 ;
+ RECT 1657.820000 193.880000 1658.920000 194.360000 ;
+ RECT 1653.690000 193.880000 1654.690000 194.360000 ;
+ RECT 1657.820000 188.440000 1658.920000 188.920000 ;
+ RECT 1653.690000 188.440000 1654.690000 188.920000 ;
+ RECT 1657.820000 177.560000 1658.920000 178.040000 ;
+ RECT 1653.690000 177.560000 1654.690000 178.040000 ;
+ RECT 1657.820000 172.120000 1658.920000 172.600000 ;
+ RECT 1653.690000 172.120000 1654.690000 172.600000 ;
+ RECT 1657.820000 183.000000 1658.920000 183.480000 ;
+ RECT 1653.690000 183.000000 1654.690000 183.480000 ;
+ RECT 1657.820000 166.680000 1658.920000 167.160000 ;
+ RECT 1653.690000 166.680000 1654.690000 167.160000 ;
+ RECT 1657.820000 161.240000 1658.920000 161.720000 ;
+ RECT 1653.690000 161.240000 1654.690000 161.720000 ;
+ RECT 1657.820000 155.800000 1658.920000 156.280000 ;
+ RECT 1657.820000 150.360000 1658.920000 150.840000 ;
+ RECT 1653.690000 155.800000 1654.690000 156.280000 ;
+ RECT 1653.690000 150.360000 1654.690000 150.840000 ;
+ RECT 1650.860000 340.720000 1850.960000 341.720000 ;
+ RECT 1650.860000 148.350000 1850.960000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 145.500000 1654.690000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 344.760000 1654.690000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 145.500000 1848.130000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 344.760000 1848.130000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 148.350000 1651.860000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 148.350000 1850.960000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 340.720000 1651.860000 341.720000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 340.720000 1850.960000 341.720000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 115.240000 1654.690000 145.500000 ;
+ RECT 1847.130000 115.240000 1848.130000 145.500000 ;
+ RECT 1657.820000 118.090000 1658.920000 142.140000 ;
+ RECT 1702.820000 118.090000 1703.920000 142.140000 ;
+ RECT 1747.820000 118.090000 1748.920000 142.140000 ;
+ RECT 1792.820000 118.090000 1793.920000 142.140000 ;
+ RECT 1837.820000 118.090000 1838.920000 142.140000 ;
+ LAYER met3 ;
+ RECT 1847.130000 130.980000 1848.130000 131.460000 ;
+ RECT 1847.130000 136.420000 1848.130000 136.900000 ;
+ RECT 1837.820000 136.420000 1838.920000 136.900000 ;
+ RECT 1837.820000 130.980000 1838.920000 131.460000 ;
+ RECT 1792.820000 130.980000 1793.920000 131.460000 ;
+ RECT 1792.820000 136.420000 1793.920000 136.900000 ;
+ RECT 1702.820000 130.980000 1703.920000 131.460000 ;
+ RECT 1747.820000 130.980000 1748.920000 131.460000 ;
+ RECT 1747.820000 136.420000 1748.920000 136.900000 ;
+ RECT 1702.820000 136.420000 1703.920000 136.900000 ;
+ RECT 1653.690000 130.980000 1654.690000 131.460000 ;
+ RECT 1657.820000 130.980000 1658.920000 131.460000 ;
+ RECT 1657.820000 136.420000 1658.920000 136.900000 ;
+ RECT 1653.690000 136.420000 1654.690000 136.900000 ;
+ RECT 1847.130000 120.100000 1848.130000 120.580000 ;
+ RECT 1847.130000 125.540000 1848.130000 126.020000 ;
+ RECT 1837.820000 125.540000 1838.920000 126.020000 ;
+ RECT 1837.820000 120.100000 1838.920000 120.580000 ;
+ RECT 1792.820000 120.100000 1793.920000 120.580000 ;
+ RECT 1792.820000 125.540000 1793.920000 126.020000 ;
+ RECT 1702.820000 120.100000 1703.920000 120.580000 ;
+ RECT 1747.820000 120.100000 1748.920000 120.580000 ;
+ RECT 1747.820000 125.540000 1748.920000 126.020000 ;
+ RECT 1702.820000 125.540000 1703.920000 126.020000 ;
+ RECT 1653.690000 125.540000 1654.690000 126.020000 ;
+ RECT 1657.820000 125.540000 1658.920000 126.020000 ;
+ RECT 1653.690000 120.100000 1654.690000 120.580000 ;
+ RECT 1657.820000 120.100000 1658.920000 120.580000 ;
+ RECT 1650.860000 141.140000 1850.960000 142.140000 ;
+ RECT 1650.860000 118.090000 1850.960000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 118.090000 1651.860000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 118.090000 1850.960000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 141.140000 1651.860000 142.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 141.140000 1850.960000 142.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 115.240000 1654.690000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 144.500000 1654.690000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 115.240000 1848.130000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 144.500000 1848.130000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 3152.250000 1838.920000 3345.620000 ;
+ RECT 1792.820000 3152.250000 1793.920000 3345.620000 ;
+ RECT 1847.130000 3149.400000 1848.130000 3349.660000 ;
+ RECT 1747.820000 3152.250000 1748.920000 3345.620000 ;
+ RECT 1702.820000 3152.250000 1703.920000 3345.620000 ;
+ RECT 1657.820000 3152.250000 1658.920000 3345.620000 ;
+ RECT 1653.690000 3149.400000 1654.690000 3349.660000 ;
+ LAYER met3 ;
+ RECT 1837.820000 3339.220000 1838.920000 3339.700000 ;
+ RECT 1847.130000 3339.220000 1848.130000 3339.700000 ;
+ RECT 1847.130000 3328.340000 1848.130000 3328.820000 ;
+ RECT 1847.130000 3333.780000 1848.130000 3334.260000 ;
+ RECT 1837.820000 3333.780000 1838.920000 3334.260000 ;
+ RECT 1837.820000 3328.340000 1838.920000 3328.820000 ;
+ RECT 1837.820000 3322.900000 1838.920000 3323.380000 ;
+ RECT 1837.820000 3317.460000 1838.920000 3317.940000 ;
+ RECT 1847.130000 3322.900000 1848.130000 3323.380000 ;
+ RECT 1847.130000 3317.460000 1848.130000 3317.940000 ;
+ RECT 1837.820000 3301.140000 1838.920000 3301.620000 ;
+ RECT 1837.820000 3306.580000 1838.920000 3307.060000 ;
+ RECT 1847.130000 3306.580000 1848.130000 3307.060000 ;
+ RECT 1847.130000 3301.140000 1848.130000 3301.620000 ;
+ RECT 1837.820000 3312.020000 1838.920000 3312.500000 ;
+ RECT 1847.130000 3312.020000 1848.130000 3312.500000 ;
+ RECT 1792.820000 3339.220000 1793.920000 3339.700000 ;
+ RECT 1792.820000 3333.780000 1793.920000 3334.260000 ;
+ RECT 1792.820000 3328.340000 1793.920000 3328.820000 ;
+ RECT 1792.820000 3322.900000 1793.920000 3323.380000 ;
+ RECT 1792.820000 3301.140000 1793.920000 3301.620000 ;
+ RECT 1792.820000 3306.580000 1793.920000 3307.060000 ;
+ RECT 1792.820000 3312.020000 1793.920000 3312.500000 ;
+ RECT 1792.820000 3317.460000 1793.920000 3317.940000 ;
+ RECT 1847.130000 3290.260000 1848.130000 3290.740000 ;
+ RECT 1847.130000 3295.700000 1848.130000 3296.180000 ;
+ RECT 1837.820000 3295.700000 1838.920000 3296.180000 ;
+ RECT 1837.820000 3290.260000 1838.920000 3290.740000 ;
+ RECT 1837.820000 3284.820000 1838.920000 3285.300000 ;
+ RECT 1837.820000 3279.380000 1838.920000 3279.860000 ;
+ RECT 1847.130000 3284.820000 1848.130000 3285.300000 ;
+ RECT 1847.130000 3279.380000 1848.130000 3279.860000 ;
+ RECT 1847.130000 3263.060000 1848.130000 3263.540000 ;
+ RECT 1847.130000 3268.500000 1848.130000 3268.980000 ;
+ RECT 1847.130000 3273.940000 1848.130000 3274.420000 ;
+ RECT 1837.820000 3268.500000 1838.920000 3268.980000 ;
+ RECT 1837.820000 3263.060000 1838.920000 3263.540000 ;
+ RECT 1837.820000 3273.940000 1838.920000 3274.420000 ;
+ RECT 1837.820000 3257.620000 1838.920000 3258.100000 ;
+ RECT 1837.820000 3252.180000 1838.920000 3252.660000 ;
+ RECT 1847.130000 3257.620000 1848.130000 3258.100000 ;
+ RECT 1847.130000 3252.180000 1848.130000 3252.660000 ;
+ RECT 1792.820000 3295.700000 1793.920000 3296.180000 ;
+ RECT 1792.820000 3290.260000 1793.920000 3290.740000 ;
+ RECT 1792.820000 3284.820000 1793.920000 3285.300000 ;
+ RECT 1792.820000 3279.380000 1793.920000 3279.860000 ;
+ RECT 1792.820000 3268.500000 1793.920000 3268.980000 ;
+ RECT 1792.820000 3263.060000 1793.920000 3263.540000 ;
+ RECT 1792.820000 3257.620000 1793.920000 3258.100000 ;
+ RECT 1792.820000 3252.180000 1793.920000 3252.660000 ;
+ RECT 1792.820000 3273.940000 1793.920000 3274.420000 ;
+ RECT 1747.820000 3339.220000 1748.920000 3339.700000 ;
+ RECT 1747.820000 3333.780000 1748.920000 3334.260000 ;
+ RECT 1747.820000 3328.340000 1748.920000 3328.820000 ;
+ RECT 1702.820000 3339.220000 1703.920000 3339.700000 ;
+ RECT 1702.820000 3333.780000 1703.920000 3334.260000 ;
+ RECT 1702.820000 3328.340000 1703.920000 3328.820000 ;
+ RECT 1747.820000 3312.020000 1748.920000 3312.500000 ;
+ RECT 1747.820000 3306.580000 1748.920000 3307.060000 ;
+ RECT 1747.820000 3301.140000 1748.920000 3301.620000 ;
+ RECT 1747.820000 3317.460000 1748.920000 3317.940000 ;
+ RECT 1747.820000 3322.900000 1748.920000 3323.380000 ;
+ RECT 1702.820000 3322.900000 1703.920000 3323.380000 ;
+ RECT 1702.820000 3312.020000 1703.920000 3312.500000 ;
+ RECT 1702.820000 3306.580000 1703.920000 3307.060000 ;
+ RECT 1702.820000 3301.140000 1703.920000 3301.620000 ;
+ RECT 1702.820000 3317.460000 1703.920000 3317.940000 ;
+ RECT 1657.820000 3339.220000 1658.920000 3339.700000 ;
+ RECT 1653.690000 3339.220000 1654.690000 3339.700000 ;
+ RECT 1653.690000 3333.780000 1654.690000 3334.260000 ;
+ RECT 1657.820000 3333.780000 1658.920000 3334.260000 ;
+ RECT 1657.820000 3328.340000 1658.920000 3328.820000 ;
+ RECT 1653.690000 3328.340000 1654.690000 3328.820000 ;
+ RECT 1657.820000 3322.900000 1658.920000 3323.380000 ;
+ RECT 1653.690000 3322.900000 1654.690000 3323.380000 ;
+ RECT 1657.820000 3317.460000 1658.920000 3317.940000 ;
+ RECT 1653.690000 3317.460000 1654.690000 3317.940000 ;
+ RECT 1657.820000 3306.580000 1658.920000 3307.060000 ;
+ RECT 1653.690000 3306.580000 1654.690000 3307.060000 ;
+ RECT 1657.820000 3301.140000 1658.920000 3301.620000 ;
+ RECT 1653.690000 3301.140000 1654.690000 3301.620000 ;
+ RECT 1657.820000 3312.020000 1658.920000 3312.500000 ;
+ RECT 1653.690000 3312.020000 1654.690000 3312.500000 ;
+ RECT 1747.820000 3295.700000 1748.920000 3296.180000 ;
+ RECT 1747.820000 3290.260000 1748.920000 3290.740000 ;
+ RECT 1747.820000 3284.820000 1748.920000 3285.300000 ;
+ RECT 1747.820000 3279.380000 1748.920000 3279.860000 ;
+ RECT 1702.820000 3295.700000 1703.920000 3296.180000 ;
+ RECT 1702.820000 3290.260000 1703.920000 3290.740000 ;
+ RECT 1702.820000 3284.820000 1703.920000 3285.300000 ;
+ RECT 1702.820000 3279.380000 1703.920000 3279.860000 ;
+ RECT 1747.820000 3268.500000 1748.920000 3268.980000 ;
+ RECT 1747.820000 3252.180000 1748.920000 3252.660000 ;
+ RECT 1747.820000 3257.620000 1748.920000 3258.100000 ;
+ RECT 1747.820000 3263.060000 1748.920000 3263.540000 ;
+ RECT 1747.820000 3273.940000 1748.920000 3274.420000 ;
+ RECT 1702.820000 3252.180000 1703.920000 3252.660000 ;
+ RECT 1702.820000 3257.620000 1703.920000 3258.100000 ;
+ RECT 1702.820000 3263.060000 1703.920000 3263.540000 ;
+ RECT 1702.820000 3268.500000 1703.920000 3268.980000 ;
+ RECT 1702.820000 3273.940000 1703.920000 3274.420000 ;
+ RECT 1657.820000 3295.700000 1658.920000 3296.180000 ;
+ RECT 1653.690000 3295.700000 1654.690000 3296.180000 ;
+ RECT 1657.820000 3290.260000 1658.920000 3290.740000 ;
+ RECT 1653.690000 3290.260000 1654.690000 3290.740000 ;
+ RECT 1657.820000 3284.820000 1658.920000 3285.300000 ;
+ RECT 1653.690000 3284.820000 1654.690000 3285.300000 ;
+ RECT 1657.820000 3279.380000 1658.920000 3279.860000 ;
+ RECT 1653.690000 3279.380000 1654.690000 3279.860000 ;
+ RECT 1657.820000 3273.940000 1658.920000 3274.420000 ;
+ RECT 1657.820000 3268.500000 1658.920000 3268.980000 ;
+ RECT 1653.690000 3273.940000 1654.690000 3274.420000 ;
+ RECT 1653.690000 3268.500000 1654.690000 3268.980000 ;
+ RECT 1657.820000 3263.060000 1658.920000 3263.540000 ;
+ RECT 1653.690000 3263.060000 1654.690000 3263.540000 ;
+ RECT 1657.820000 3257.620000 1658.920000 3258.100000 ;
+ RECT 1653.690000 3257.620000 1654.690000 3258.100000 ;
+ RECT 1657.820000 3252.180000 1658.920000 3252.660000 ;
+ RECT 1653.690000 3252.180000 1654.690000 3252.660000 ;
+ RECT 1837.820000 3246.740000 1838.920000 3247.220000 ;
+ RECT 1837.820000 3241.300000 1838.920000 3241.780000 ;
+ RECT 1847.130000 3246.740000 1848.130000 3247.220000 ;
+ RECT 1847.130000 3241.300000 1848.130000 3241.780000 ;
+ RECT 1847.130000 3224.980000 1848.130000 3225.460000 ;
+ RECT 1847.130000 3230.420000 1848.130000 3230.900000 ;
+ RECT 1847.130000 3235.860000 1848.130000 3236.340000 ;
+ RECT 1837.820000 3235.860000 1838.920000 3236.340000 ;
+ RECT 1837.820000 3230.420000 1838.920000 3230.900000 ;
+ RECT 1837.820000 3224.980000 1838.920000 3225.460000 ;
+ RECT 1837.820000 3214.100000 1838.920000 3214.580000 ;
+ RECT 1837.820000 3219.540000 1838.920000 3220.020000 ;
+ RECT 1847.130000 3219.540000 1848.130000 3220.020000 ;
+ RECT 1847.130000 3214.100000 1848.130000 3214.580000 ;
+ RECT 1847.130000 3203.220000 1848.130000 3203.700000 ;
+ RECT 1847.130000 3208.660000 1848.130000 3209.140000 ;
+ RECT 1837.820000 3203.220000 1838.920000 3203.700000 ;
+ RECT 1837.820000 3208.660000 1838.920000 3209.140000 ;
+ RECT 1792.820000 3246.740000 1793.920000 3247.220000 ;
+ RECT 1792.820000 3241.300000 1793.920000 3241.780000 ;
+ RECT 1792.820000 3235.860000 1793.920000 3236.340000 ;
+ RECT 1792.820000 3230.420000 1793.920000 3230.900000 ;
+ RECT 1792.820000 3224.980000 1793.920000 3225.460000 ;
+ RECT 1792.820000 3203.220000 1793.920000 3203.700000 ;
+ RECT 1792.820000 3208.660000 1793.920000 3209.140000 ;
+ RECT 1792.820000 3214.100000 1793.920000 3214.580000 ;
+ RECT 1792.820000 3219.540000 1793.920000 3220.020000 ;
+ RECT 1837.820000 3197.780000 1838.920000 3198.260000 ;
+ RECT 1837.820000 3192.340000 1838.920000 3192.820000 ;
+ RECT 1847.130000 3197.780000 1848.130000 3198.260000 ;
+ RECT 1847.130000 3192.340000 1848.130000 3192.820000 ;
+ RECT 1837.820000 3181.460000 1838.920000 3181.940000 ;
+ RECT 1837.820000 3176.020000 1838.920000 3176.500000 ;
+ RECT 1847.130000 3181.460000 1848.130000 3181.940000 ;
+ RECT 1847.130000 3176.020000 1848.130000 3176.500000 ;
+ RECT 1837.820000 3186.900000 1838.920000 3187.380000 ;
+ RECT 1847.130000 3186.900000 1848.130000 3187.380000 ;
+ RECT 1847.130000 3165.140000 1848.130000 3165.620000 ;
+ RECT 1847.130000 3170.580000 1848.130000 3171.060000 ;
+ RECT 1837.820000 3170.580000 1838.920000 3171.060000 ;
+ RECT 1837.820000 3165.140000 1838.920000 3165.620000 ;
+ RECT 1837.820000 3159.700000 1838.920000 3160.180000 ;
+ RECT 1837.820000 3154.260000 1838.920000 3154.740000 ;
+ RECT 1847.130000 3159.700000 1848.130000 3160.180000 ;
+ RECT 1847.130000 3154.260000 1848.130000 3154.740000 ;
+ RECT 1792.820000 3197.780000 1793.920000 3198.260000 ;
+ RECT 1792.820000 3192.340000 1793.920000 3192.820000 ;
+ RECT 1792.820000 3186.900000 1793.920000 3187.380000 ;
+ RECT 1792.820000 3181.460000 1793.920000 3181.940000 ;
+ RECT 1792.820000 3176.020000 1793.920000 3176.500000 ;
+ RECT 1792.820000 3170.580000 1793.920000 3171.060000 ;
+ RECT 1792.820000 3165.140000 1793.920000 3165.620000 ;
+ RECT 1792.820000 3159.700000 1793.920000 3160.180000 ;
+ RECT 1792.820000 3154.260000 1793.920000 3154.740000 ;
+ RECT 1747.820000 3246.740000 1748.920000 3247.220000 ;
+ RECT 1747.820000 3241.300000 1748.920000 3241.780000 ;
+ RECT 1747.820000 3235.860000 1748.920000 3236.340000 ;
+ RECT 1747.820000 3230.420000 1748.920000 3230.900000 ;
+ RECT 1747.820000 3224.980000 1748.920000 3225.460000 ;
+ RECT 1702.820000 3246.740000 1703.920000 3247.220000 ;
+ RECT 1702.820000 3241.300000 1703.920000 3241.780000 ;
+ RECT 1702.820000 3235.860000 1703.920000 3236.340000 ;
+ RECT 1702.820000 3230.420000 1703.920000 3230.900000 ;
+ RECT 1702.820000 3224.980000 1703.920000 3225.460000 ;
+ RECT 1747.820000 3219.540000 1748.920000 3220.020000 ;
+ RECT 1747.820000 3214.100000 1748.920000 3214.580000 ;
+ RECT 1747.820000 3208.660000 1748.920000 3209.140000 ;
+ RECT 1747.820000 3203.220000 1748.920000 3203.700000 ;
+ RECT 1702.820000 3214.100000 1703.920000 3214.580000 ;
+ RECT 1702.820000 3208.660000 1703.920000 3209.140000 ;
+ RECT 1702.820000 3203.220000 1703.920000 3203.700000 ;
+ RECT 1702.820000 3219.540000 1703.920000 3220.020000 ;
+ RECT 1657.820000 3246.740000 1658.920000 3247.220000 ;
+ RECT 1653.690000 3246.740000 1654.690000 3247.220000 ;
+ RECT 1657.820000 3241.300000 1658.920000 3241.780000 ;
+ RECT 1653.690000 3241.300000 1654.690000 3241.780000 ;
+ RECT 1657.820000 3235.860000 1658.920000 3236.340000 ;
+ RECT 1653.690000 3235.860000 1654.690000 3236.340000 ;
+ RECT 1657.820000 3224.980000 1658.920000 3225.460000 ;
+ RECT 1653.690000 3224.980000 1654.690000 3225.460000 ;
+ RECT 1653.690000 3230.420000 1654.690000 3230.900000 ;
+ RECT 1657.820000 3230.420000 1658.920000 3230.900000 ;
+ RECT 1657.820000 3219.540000 1658.920000 3220.020000 ;
+ RECT 1653.690000 3219.540000 1654.690000 3220.020000 ;
+ RECT 1657.820000 3214.100000 1658.920000 3214.580000 ;
+ RECT 1653.690000 3214.100000 1654.690000 3214.580000 ;
+ RECT 1657.820000 3208.660000 1658.920000 3209.140000 ;
+ RECT 1653.690000 3208.660000 1654.690000 3209.140000 ;
+ RECT 1657.820000 3203.220000 1658.920000 3203.700000 ;
+ RECT 1653.690000 3203.220000 1654.690000 3203.700000 ;
+ RECT 1747.820000 3197.780000 1748.920000 3198.260000 ;
+ RECT 1747.820000 3192.340000 1748.920000 3192.820000 ;
+ RECT 1747.820000 3186.900000 1748.920000 3187.380000 ;
+ RECT 1747.820000 3181.460000 1748.920000 3181.940000 ;
+ RECT 1747.820000 3176.020000 1748.920000 3176.500000 ;
+ RECT 1702.820000 3197.780000 1703.920000 3198.260000 ;
+ RECT 1702.820000 3192.340000 1703.920000 3192.820000 ;
+ RECT 1702.820000 3186.900000 1703.920000 3187.380000 ;
+ RECT 1702.820000 3181.460000 1703.920000 3181.940000 ;
+ RECT 1702.820000 3176.020000 1703.920000 3176.500000 ;
+ RECT 1747.820000 3154.260000 1748.920000 3154.740000 ;
+ RECT 1747.820000 3159.700000 1748.920000 3160.180000 ;
+ RECT 1747.820000 3165.140000 1748.920000 3165.620000 ;
+ RECT 1747.820000 3170.580000 1748.920000 3171.060000 ;
+ RECT 1702.820000 3154.260000 1703.920000 3154.740000 ;
+ RECT 1702.820000 3159.700000 1703.920000 3160.180000 ;
+ RECT 1702.820000 3165.140000 1703.920000 3165.620000 ;
+ RECT 1702.820000 3170.580000 1703.920000 3171.060000 ;
+ RECT 1657.820000 3197.780000 1658.920000 3198.260000 ;
+ RECT 1653.690000 3197.780000 1654.690000 3198.260000 ;
+ RECT 1657.820000 3192.340000 1658.920000 3192.820000 ;
+ RECT 1653.690000 3192.340000 1654.690000 3192.820000 ;
+ RECT 1657.820000 3181.460000 1658.920000 3181.940000 ;
+ RECT 1653.690000 3181.460000 1654.690000 3181.940000 ;
+ RECT 1657.820000 3176.020000 1658.920000 3176.500000 ;
+ RECT 1653.690000 3176.020000 1654.690000 3176.500000 ;
+ RECT 1657.820000 3186.900000 1658.920000 3187.380000 ;
+ RECT 1653.690000 3186.900000 1654.690000 3187.380000 ;
+ RECT 1657.820000 3170.580000 1658.920000 3171.060000 ;
+ RECT 1653.690000 3170.580000 1654.690000 3171.060000 ;
+ RECT 1657.820000 3165.140000 1658.920000 3165.620000 ;
+ RECT 1653.690000 3165.140000 1654.690000 3165.620000 ;
+ RECT 1657.820000 3159.700000 1658.920000 3160.180000 ;
+ RECT 1657.820000 3154.260000 1658.920000 3154.740000 ;
+ RECT 1653.690000 3159.700000 1654.690000 3160.180000 ;
+ RECT 1653.690000 3154.260000 1654.690000 3154.740000 ;
+ RECT 1650.860000 3344.620000 1850.960000 3345.620000 ;
+ RECT 1650.860000 3152.250000 1850.960000 3153.250000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 3149.400000 1654.690000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 3348.660000 1654.690000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 3149.400000 1848.130000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 3348.660000 1848.130000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 3152.250000 1651.860000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 3152.250000 1850.960000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 3344.620000 1651.860000 3345.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 3344.620000 1850.960000 3345.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 2951.990000 1838.920000 3145.360000 ;
+ RECT 1792.820000 2951.990000 1793.920000 3145.360000 ;
+ RECT 1847.130000 2949.140000 1848.130000 3149.400000 ;
+ RECT 1747.820000 2951.990000 1748.920000 3145.360000 ;
+ RECT 1702.820000 2951.990000 1703.920000 3145.360000 ;
+ RECT 1657.820000 2951.990000 1658.920000 3145.360000 ;
+ RECT 1653.690000 2949.140000 1654.690000 3149.400000 ;
+ LAYER met3 ;
+ RECT 1837.820000 3138.960000 1838.920000 3139.440000 ;
+ RECT 1847.130000 3138.960000 1848.130000 3139.440000 ;
+ RECT 1847.130000 3128.080000 1848.130000 3128.560000 ;
+ RECT 1847.130000 3133.520000 1848.130000 3134.000000 ;
+ RECT 1837.820000 3133.520000 1838.920000 3134.000000 ;
+ RECT 1837.820000 3128.080000 1838.920000 3128.560000 ;
+ RECT 1837.820000 3122.640000 1838.920000 3123.120000 ;
+ RECT 1837.820000 3117.200000 1838.920000 3117.680000 ;
+ RECT 1847.130000 3122.640000 1848.130000 3123.120000 ;
+ RECT 1847.130000 3117.200000 1848.130000 3117.680000 ;
+ RECT 1837.820000 3100.880000 1838.920000 3101.360000 ;
+ RECT 1837.820000 3106.320000 1838.920000 3106.800000 ;
+ RECT 1847.130000 3106.320000 1848.130000 3106.800000 ;
+ RECT 1847.130000 3100.880000 1848.130000 3101.360000 ;
+ RECT 1837.820000 3111.760000 1838.920000 3112.240000 ;
+ RECT 1847.130000 3111.760000 1848.130000 3112.240000 ;
+ RECT 1792.820000 3138.960000 1793.920000 3139.440000 ;
+ RECT 1792.820000 3133.520000 1793.920000 3134.000000 ;
+ RECT 1792.820000 3128.080000 1793.920000 3128.560000 ;
+ RECT 1792.820000 3122.640000 1793.920000 3123.120000 ;
+ RECT 1792.820000 3100.880000 1793.920000 3101.360000 ;
+ RECT 1792.820000 3106.320000 1793.920000 3106.800000 ;
+ RECT 1792.820000 3111.760000 1793.920000 3112.240000 ;
+ RECT 1792.820000 3117.200000 1793.920000 3117.680000 ;
+ RECT 1847.130000 3090.000000 1848.130000 3090.480000 ;
+ RECT 1847.130000 3095.440000 1848.130000 3095.920000 ;
+ RECT 1837.820000 3095.440000 1838.920000 3095.920000 ;
+ RECT 1837.820000 3090.000000 1838.920000 3090.480000 ;
+ RECT 1837.820000 3084.560000 1838.920000 3085.040000 ;
+ RECT 1837.820000 3079.120000 1838.920000 3079.600000 ;
+ RECT 1847.130000 3084.560000 1848.130000 3085.040000 ;
+ RECT 1847.130000 3079.120000 1848.130000 3079.600000 ;
+ RECT 1847.130000 3062.800000 1848.130000 3063.280000 ;
+ RECT 1847.130000 3068.240000 1848.130000 3068.720000 ;
+ RECT 1847.130000 3073.680000 1848.130000 3074.160000 ;
+ RECT 1837.820000 3068.240000 1838.920000 3068.720000 ;
+ RECT 1837.820000 3062.800000 1838.920000 3063.280000 ;
+ RECT 1837.820000 3073.680000 1838.920000 3074.160000 ;
+ RECT 1837.820000 3057.360000 1838.920000 3057.840000 ;
+ RECT 1837.820000 3051.920000 1838.920000 3052.400000 ;
+ RECT 1847.130000 3057.360000 1848.130000 3057.840000 ;
+ RECT 1847.130000 3051.920000 1848.130000 3052.400000 ;
+ RECT 1792.820000 3095.440000 1793.920000 3095.920000 ;
+ RECT 1792.820000 3090.000000 1793.920000 3090.480000 ;
+ RECT 1792.820000 3084.560000 1793.920000 3085.040000 ;
+ RECT 1792.820000 3079.120000 1793.920000 3079.600000 ;
+ RECT 1792.820000 3068.240000 1793.920000 3068.720000 ;
+ RECT 1792.820000 3062.800000 1793.920000 3063.280000 ;
+ RECT 1792.820000 3057.360000 1793.920000 3057.840000 ;
+ RECT 1792.820000 3051.920000 1793.920000 3052.400000 ;
+ RECT 1792.820000 3073.680000 1793.920000 3074.160000 ;
+ RECT 1747.820000 3138.960000 1748.920000 3139.440000 ;
+ RECT 1747.820000 3133.520000 1748.920000 3134.000000 ;
+ RECT 1747.820000 3128.080000 1748.920000 3128.560000 ;
+ RECT 1702.820000 3138.960000 1703.920000 3139.440000 ;
+ RECT 1702.820000 3133.520000 1703.920000 3134.000000 ;
+ RECT 1702.820000 3128.080000 1703.920000 3128.560000 ;
+ RECT 1747.820000 3111.760000 1748.920000 3112.240000 ;
+ RECT 1747.820000 3106.320000 1748.920000 3106.800000 ;
+ RECT 1747.820000 3100.880000 1748.920000 3101.360000 ;
+ RECT 1747.820000 3117.200000 1748.920000 3117.680000 ;
+ RECT 1747.820000 3122.640000 1748.920000 3123.120000 ;
+ RECT 1702.820000 3122.640000 1703.920000 3123.120000 ;
+ RECT 1702.820000 3111.760000 1703.920000 3112.240000 ;
+ RECT 1702.820000 3106.320000 1703.920000 3106.800000 ;
+ RECT 1702.820000 3100.880000 1703.920000 3101.360000 ;
+ RECT 1702.820000 3117.200000 1703.920000 3117.680000 ;
+ RECT 1657.820000 3138.960000 1658.920000 3139.440000 ;
+ RECT 1653.690000 3138.960000 1654.690000 3139.440000 ;
+ RECT 1653.690000 3133.520000 1654.690000 3134.000000 ;
+ RECT 1657.820000 3133.520000 1658.920000 3134.000000 ;
+ RECT 1657.820000 3128.080000 1658.920000 3128.560000 ;
+ RECT 1653.690000 3128.080000 1654.690000 3128.560000 ;
+ RECT 1657.820000 3122.640000 1658.920000 3123.120000 ;
+ RECT 1653.690000 3122.640000 1654.690000 3123.120000 ;
+ RECT 1657.820000 3117.200000 1658.920000 3117.680000 ;
+ RECT 1653.690000 3117.200000 1654.690000 3117.680000 ;
+ RECT 1657.820000 3106.320000 1658.920000 3106.800000 ;
+ RECT 1653.690000 3106.320000 1654.690000 3106.800000 ;
+ RECT 1657.820000 3100.880000 1658.920000 3101.360000 ;
+ RECT 1653.690000 3100.880000 1654.690000 3101.360000 ;
+ RECT 1657.820000 3111.760000 1658.920000 3112.240000 ;
+ RECT 1653.690000 3111.760000 1654.690000 3112.240000 ;
+ RECT 1747.820000 3095.440000 1748.920000 3095.920000 ;
+ RECT 1747.820000 3090.000000 1748.920000 3090.480000 ;
+ RECT 1747.820000 3084.560000 1748.920000 3085.040000 ;
+ RECT 1747.820000 3079.120000 1748.920000 3079.600000 ;
+ RECT 1702.820000 3095.440000 1703.920000 3095.920000 ;
+ RECT 1702.820000 3090.000000 1703.920000 3090.480000 ;
+ RECT 1702.820000 3084.560000 1703.920000 3085.040000 ;
+ RECT 1702.820000 3079.120000 1703.920000 3079.600000 ;
+ RECT 1747.820000 3068.240000 1748.920000 3068.720000 ;
+ RECT 1747.820000 3051.920000 1748.920000 3052.400000 ;
+ RECT 1747.820000 3057.360000 1748.920000 3057.840000 ;
+ RECT 1747.820000 3062.800000 1748.920000 3063.280000 ;
+ RECT 1747.820000 3073.680000 1748.920000 3074.160000 ;
+ RECT 1702.820000 3051.920000 1703.920000 3052.400000 ;
+ RECT 1702.820000 3057.360000 1703.920000 3057.840000 ;
+ RECT 1702.820000 3062.800000 1703.920000 3063.280000 ;
+ RECT 1702.820000 3068.240000 1703.920000 3068.720000 ;
+ RECT 1702.820000 3073.680000 1703.920000 3074.160000 ;
+ RECT 1657.820000 3095.440000 1658.920000 3095.920000 ;
+ RECT 1653.690000 3095.440000 1654.690000 3095.920000 ;
+ RECT 1657.820000 3090.000000 1658.920000 3090.480000 ;
+ RECT 1653.690000 3090.000000 1654.690000 3090.480000 ;
+ RECT 1657.820000 3084.560000 1658.920000 3085.040000 ;
+ RECT 1653.690000 3084.560000 1654.690000 3085.040000 ;
+ RECT 1657.820000 3079.120000 1658.920000 3079.600000 ;
+ RECT 1653.690000 3079.120000 1654.690000 3079.600000 ;
+ RECT 1657.820000 3073.680000 1658.920000 3074.160000 ;
+ RECT 1657.820000 3068.240000 1658.920000 3068.720000 ;
+ RECT 1653.690000 3073.680000 1654.690000 3074.160000 ;
+ RECT 1653.690000 3068.240000 1654.690000 3068.720000 ;
+ RECT 1657.820000 3062.800000 1658.920000 3063.280000 ;
+ RECT 1653.690000 3062.800000 1654.690000 3063.280000 ;
+ RECT 1657.820000 3057.360000 1658.920000 3057.840000 ;
+ RECT 1653.690000 3057.360000 1654.690000 3057.840000 ;
+ RECT 1657.820000 3051.920000 1658.920000 3052.400000 ;
+ RECT 1653.690000 3051.920000 1654.690000 3052.400000 ;
+ RECT 1837.820000 3046.480000 1838.920000 3046.960000 ;
+ RECT 1837.820000 3041.040000 1838.920000 3041.520000 ;
+ RECT 1847.130000 3046.480000 1848.130000 3046.960000 ;
+ RECT 1847.130000 3041.040000 1848.130000 3041.520000 ;
+ RECT 1847.130000 3024.720000 1848.130000 3025.200000 ;
+ RECT 1847.130000 3030.160000 1848.130000 3030.640000 ;
+ RECT 1847.130000 3035.600000 1848.130000 3036.080000 ;
+ RECT 1837.820000 3035.600000 1838.920000 3036.080000 ;
+ RECT 1837.820000 3030.160000 1838.920000 3030.640000 ;
+ RECT 1837.820000 3024.720000 1838.920000 3025.200000 ;
+ RECT 1837.820000 3013.840000 1838.920000 3014.320000 ;
+ RECT 1837.820000 3019.280000 1838.920000 3019.760000 ;
+ RECT 1847.130000 3019.280000 1848.130000 3019.760000 ;
+ RECT 1847.130000 3013.840000 1848.130000 3014.320000 ;
+ RECT 1847.130000 3002.960000 1848.130000 3003.440000 ;
+ RECT 1847.130000 3008.400000 1848.130000 3008.880000 ;
+ RECT 1837.820000 3002.960000 1838.920000 3003.440000 ;
+ RECT 1837.820000 3008.400000 1838.920000 3008.880000 ;
+ RECT 1792.820000 3046.480000 1793.920000 3046.960000 ;
+ RECT 1792.820000 3041.040000 1793.920000 3041.520000 ;
+ RECT 1792.820000 3035.600000 1793.920000 3036.080000 ;
+ RECT 1792.820000 3030.160000 1793.920000 3030.640000 ;
+ RECT 1792.820000 3024.720000 1793.920000 3025.200000 ;
+ RECT 1792.820000 3002.960000 1793.920000 3003.440000 ;
+ RECT 1792.820000 3008.400000 1793.920000 3008.880000 ;
+ RECT 1792.820000 3013.840000 1793.920000 3014.320000 ;
+ RECT 1792.820000 3019.280000 1793.920000 3019.760000 ;
+ RECT 1837.820000 2997.520000 1838.920000 2998.000000 ;
+ RECT 1837.820000 2992.080000 1838.920000 2992.560000 ;
+ RECT 1847.130000 2997.520000 1848.130000 2998.000000 ;
+ RECT 1847.130000 2992.080000 1848.130000 2992.560000 ;
+ RECT 1837.820000 2981.200000 1838.920000 2981.680000 ;
+ RECT 1837.820000 2975.760000 1838.920000 2976.240000 ;
+ RECT 1847.130000 2981.200000 1848.130000 2981.680000 ;
+ RECT 1847.130000 2975.760000 1848.130000 2976.240000 ;
+ RECT 1837.820000 2986.640000 1838.920000 2987.120000 ;
+ RECT 1847.130000 2986.640000 1848.130000 2987.120000 ;
+ RECT 1847.130000 2964.880000 1848.130000 2965.360000 ;
+ RECT 1847.130000 2970.320000 1848.130000 2970.800000 ;
+ RECT 1837.820000 2970.320000 1838.920000 2970.800000 ;
+ RECT 1837.820000 2964.880000 1838.920000 2965.360000 ;
+ RECT 1837.820000 2959.440000 1838.920000 2959.920000 ;
+ RECT 1837.820000 2954.000000 1838.920000 2954.480000 ;
+ RECT 1847.130000 2959.440000 1848.130000 2959.920000 ;
+ RECT 1847.130000 2954.000000 1848.130000 2954.480000 ;
+ RECT 1792.820000 2997.520000 1793.920000 2998.000000 ;
+ RECT 1792.820000 2992.080000 1793.920000 2992.560000 ;
+ RECT 1792.820000 2986.640000 1793.920000 2987.120000 ;
+ RECT 1792.820000 2981.200000 1793.920000 2981.680000 ;
+ RECT 1792.820000 2975.760000 1793.920000 2976.240000 ;
+ RECT 1792.820000 2970.320000 1793.920000 2970.800000 ;
+ RECT 1792.820000 2964.880000 1793.920000 2965.360000 ;
+ RECT 1792.820000 2959.440000 1793.920000 2959.920000 ;
+ RECT 1792.820000 2954.000000 1793.920000 2954.480000 ;
+ RECT 1747.820000 3046.480000 1748.920000 3046.960000 ;
+ RECT 1747.820000 3041.040000 1748.920000 3041.520000 ;
+ RECT 1747.820000 3035.600000 1748.920000 3036.080000 ;
+ RECT 1747.820000 3030.160000 1748.920000 3030.640000 ;
+ RECT 1747.820000 3024.720000 1748.920000 3025.200000 ;
+ RECT 1702.820000 3046.480000 1703.920000 3046.960000 ;
+ RECT 1702.820000 3041.040000 1703.920000 3041.520000 ;
+ RECT 1702.820000 3035.600000 1703.920000 3036.080000 ;
+ RECT 1702.820000 3030.160000 1703.920000 3030.640000 ;
+ RECT 1702.820000 3024.720000 1703.920000 3025.200000 ;
+ RECT 1747.820000 3019.280000 1748.920000 3019.760000 ;
+ RECT 1747.820000 3013.840000 1748.920000 3014.320000 ;
+ RECT 1747.820000 3008.400000 1748.920000 3008.880000 ;
+ RECT 1747.820000 3002.960000 1748.920000 3003.440000 ;
+ RECT 1702.820000 3013.840000 1703.920000 3014.320000 ;
+ RECT 1702.820000 3008.400000 1703.920000 3008.880000 ;
+ RECT 1702.820000 3002.960000 1703.920000 3003.440000 ;
+ RECT 1702.820000 3019.280000 1703.920000 3019.760000 ;
+ RECT 1657.820000 3046.480000 1658.920000 3046.960000 ;
+ RECT 1653.690000 3046.480000 1654.690000 3046.960000 ;
+ RECT 1657.820000 3041.040000 1658.920000 3041.520000 ;
+ RECT 1653.690000 3041.040000 1654.690000 3041.520000 ;
+ RECT 1657.820000 3035.600000 1658.920000 3036.080000 ;
+ RECT 1653.690000 3035.600000 1654.690000 3036.080000 ;
+ RECT 1657.820000 3024.720000 1658.920000 3025.200000 ;
+ RECT 1653.690000 3024.720000 1654.690000 3025.200000 ;
+ RECT 1653.690000 3030.160000 1654.690000 3030.640000 ;
+ RECT 1657.820000 3030.160000 1658.920000 3030.640000 ;
+ RECT 1657.820000 3019.280000 1658.920000 3019.760000 ;
+ RECT 1653.690000 3019.280000 1654.690000 3019.760000 ;
+ RECT 1657.820000 3013.840000 1658.920000 3014.320000 ;
+ RECT 1653.690000 3013.840000 1654.690000 3014.320000 ;
+ RECT 1657.820000 3008.400000 1658.920000 3008.880000 ;
+ RECT 1653.690000 3008.400000 1654.690000 3008.880000 ;
+ RECT 1657.820000 3002.960000 1658.920000 3003.440000 ;
+ RECT 1653.690000 3002.960000 1654.690000 3003.440000 ;
+ RECT 1747.820000 2997.520000 1748.920000 2998.000000 ;
+ RECT 1747.820000 2992.080000 1748.920000 2992.560000 ;
+ RECT 1747.820000 2986.640000 1748.920000 2987.120000 ;
+ RECT 1747.820000 2981.200000 1748.920000 2981.680000 ;
+ RECT 1747.820000 2975.760000 1748.920000 2976.240000 ;
+ RECT 1702.820000 2997.520000 1703.920000 2998.000000 ;
+ RECT 1702.820000 2992.080000 1703.920000 2992.560000 ;
+ RECT 1702.820000 2986.640000 1703.920000 2987.120000 ;
+ RECT 1702.820000 2981.200000 1703.920000 2981.680000 ;
+ RECT 1702.820000 2975.760000 1703.920000 2976.240000 ;
+ RECT 1747.820000 2954.000000 1748.920000 2954.480000 ;
+ RECT 1747.820000 2959.440000 1748.920000 2959.920000 ;
+ RECT 1747.820000 2964.880000 1748.920000 2965.360000 ;
+ RECT 1747.820000 2970.320000 1748.920000 2970.800000 ;
+ RECT 1702.820000 2954.000000 1703.920000 2954.480000 ;
+ RECT 1702.820000 2959.440000 1703.920000 2959.920000 ;
+ RECT 1702.820000 2964.880000 1703.920000 2965.360000 ;
+ RECT 1702.820000 2970.320000 1703.920000 2970.800000 ;
+ RECT 1657.820000 2997.520000 1658.920000 2998.000000 ;
+ RECT 1653.690000 2997.520000 1654.690000 2998.000000 ;
+ RECT 1657.820000 2992.080000 1658.920000 2992.560000 ;
+ RECT 1653.690000 2992.080000 1654.690000 2992.560000 ;
+ RECT 1657.820000 2981.200000 1658.920000 2981.680000 ;
+ RECT 1653.690000 2981.200000 1654.690000 2981.680000 ;
+ RECT 1657.820000 2975.760000 1658.920000 2976.240000 ;
+ RECT 1653.690000 2975.760000 1654.690000 2976.240000 ;
+ RECT 1657.820000 2986.640000 1658.920000 2987.120000 ;
+ RECT 1653.690000 2986.640000 1654.690000 2987.120000 ;
+ RECT 1657.820000 2970.320000 1658.920000 2970.800000 ;
+ RECT 1653.690000 2970.320000 1654.690000 2970.800000 ;
+ RECT 1657.820000 2964.880000 1658.920000 2965.360000 ;
+ RECT 1653.690000 2964.880000 1654.690000 2965.360000 ;
+ RECT 1657.820000 2959.440000 1658.920000 2959.920000 ;
+ RECT 1657.820000 2954.000000 1658.920000 2954.480000 ;
+ RECT 1653.690000 2959.440000 1654.690000 2959.920000 ;
+ RECT 1653.690000 2954.000000 1654.690000 2954.480000 ;
+ RECT 1650.860000 3144.360000 1850.960000 3145.360000 ;
+ RECT 1650.860000 2951.990000 1850.960000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 2949.140000 1654.690000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 3148.400000 1654.690000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 2949.140000 1848.130000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 3148.400000 1848.130000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2951.990000 1651.860000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2951.990000 1850.960000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 3144.360000 1651.860000 3145.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 3144.360000 1850.960000 3145.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 2751.730000 1838.920000 2945.100000 ;
+ RECT 1792.820000 2751.730000 1793.920000 2945.100000 ;
+ RECT 1847.130000 2748.880000 1848.130000 2949.140000 ;
+ RECT 1747.820000 2751.730000 1748.920000 2945.100000 ;
+ RECT 1702.820000 2751.730000 1703.920000 2945.100000 ;
+ RECT 1657.820000 2751.730000 1658.920000 2945.100000 ;
+ RECT 1653.690000 2748.880000 1654.690000 2949.140000 ;
+ LAYER met3 ;
+ RECT 1837.820000 2938.700000 1838.920000 2939.180000 ;
+ RECT 1847.130000 2938.700000 1848.130000 2939.180000 ;
+ RECT 1847.130000 2927.820000 1848.130000 2928.300000 ;
+ RECT 1847.130000 2933.260000 1848.130000 2933.740000 ;
+ RECT 1837.820000 2933.260000 1838.920000 2933.740000 ;
+ RECT 1837.820000 2927.820000 1838.920000 2928.300000 ;
+ RECT 1837.820000 2922.380000 1838.920000 2922.860000 ;
+ RECT 1837.820000 2916.940000 1838.920000 2917.420000 ;
+ RECT 1847.130000 2922.380000 1848.130000 2922.860000 ;
+ RECT 1847.130000 2916.940000 1848.130000 2917.420000 ;
+ RECT 1837.820000 2900.620000 1838.920000 2901.100000 ;
+ RECT 1837.820000 2906.060000 1838.920000 2906.540000 ;
+ RECT 1847.130000 2906.060000 1848.130000 2906.540000 ;
+ RECT 1847.130000 2900.620000 1848.130000 2901.100000 ;
+ RECT 1837.820000 2911.500000 1838.920000 2911.980000 ;
+ RECT 1847.130000 2911.500000 1848.130000 2911.980000 ;
+ RECT 1792.820000 2938.700000 1793.920000 2939.180000 ;
+ RECT 1792.820000 2933.260000 1793.920000 2933.740000 ;
+ RECT 1792.820000 2927.820000 1793.920000 2928.300000 ;
+ RECT 1792.820000 2922.380000 1793.920000 2922.860000 ;
+ RECT 1792.820000 2900.620000 1793.920000 2901.100000 ;
+ RECT 1792.820000 2906.060000 1793.920000 2906.540000 ;
+ RECT 1792.820000 2911.500000 1793.920000 2911.980000 ;
+ RECT 1792.820000 2916.940000 1793.920000 2917.420000 ;
+ RECT 1847.130000 2889.740000 1848.130000 2890.220000 ;
+ RECT 1847.130000 2895.180000 1848.130000 2895.660000 ;
+ RECT 1837.820000 2895.180000 1838.920000 2895.660000 ;
+ RECT 1837.820000 2889.740000 1838.920000 2890.220000 ;
+ RECT 1837.820000 2884.300000 1838.920000 2884.780000 ;
+ RECT 1837.820000 2878.860000 1838.920000 2879.340000 ;
+ RECT 1847.130000 2884.300000 1848.130000 2884.780000 ;
+ RECT 1847.130000 2878.860000 1848.130000 2879.340000 ;
+ RECT 1847.130000 2862.540000 1848.130000 2863.020000 ;
+ RECT 1847.130000 2867.980000 1848.130000 2868.460000 ;
+ RECT 1847.130000 2873.420000 1848.130000 2873.900000 ;
+ RECT 1837.820000 2867.980000 1838.920000 2868.460000 ;
+ RECT 1837.820000 2862.540000 1838.920000 2863.020000 ;
+ RECT 1837.820000 2873.420000 1838.920000 2873.900000 ;
+ RECT 1837.820000 2857.100000 1838.920000 2857.580000 ;
+ RECT 1837.820000 2851.660000 1838.920000 2852.140000 ;
+ RECT 1847.130000 2857.100000 1848.130000 2857.580000 ;
+ RECT 1847.130000 2851.660000 1848.130000 2852.140000 ;
+ RECT 1792.820000 2895.180000 1793.920000 2895.660000 ;
+ RECT 1792.820000 2889.740000 1793.920000 2890.220000 ;
+ RECT 1792.820000 2884.300000 1793.920000 2884.780000 ;
+ RECT 1792.820000 2878.860000 1793.920000 2879.340000 ;
+ RECT 1792.820000 2867.980000 1793.920000 2868.460000 ;
+ RECT 1792.820000 2862.540000 1793.920000 2863.020000 ;
+ RECT 1792.820000 2857.100000 1793.920000 2857.580000 ;
+ RECT 1792.820000 2851.660000 1793.920000 2852.140000 ;
+ RECT 1792.820000 2873.420000 1793.920000 2873.900000 ;
+ RECT 1747.820000 2938.700000 1748.920000 2939.180000 ;
+ RECT 1747.820000 2933.260000 1748.920000 2933.740000 ;
+ RECT 1747.820000 2927.820000 1748.920000 2928.300000 ;
+ RECT 1702.820000 2938.700000 1703.920000 2939.180000 ;
+ RECT 1702.820000 2933.260000 1703.920000 2933.740000 ;
+ RECT 1702.820000 2927.820000 1703.920000 2928.300000 ;
+ RECT 1747.820000 2911.500000 1748.920000 2911.980000 ;
+ RECT 1747.820000 2906.060000 1748.920000 2906.540000 ;
+ RECT 1747.820000 2900.620000 1748.920000 2901.100000 ;
+ RECT 1747.820000 2916.940000 1748.920000 2917.420000 ;
+ RECT 1747.820000 2922.380000 1748.920000 2922.860000 ;
+ RECT 1702.820000 2922.380000 1703.920000 2922.860000 ;
+ RECT 1702.820000 2911.500000 1703.920000 2911.980000 ;
+ RECT 1702.820000 2906.060000 1703.920000 2906.540000 ;
+ RECT 1702.820000 2900.620000 1703.920000 2901.100000 ;
+ RECT 1702.820000 2916.940000 1703.920000 2917.420000 ;
+ RECT 1657.820000 2938.700000 1658.920000 2939.180000 ;
+ RECT 1653.690000 2938.700000 1654.690000 2939.180000 ;
+ RECT 1653.690000 2933.260000 1654.690000 2933.740000 ;
+ RECT 1657.820000 2933.260000 1658.920000 2933.740000 ;
+ RECT 1657.820000 2927.820000 1658.920000 2928.300000 ;
+ RECT 1653.690000 2927.820000 1654.690000 2928.300000 ;
+ RECT 1657.820000 2922.380000 1658.920000 2922.860000 ;
+ RECT 1653.690000 2922.380000 1654.690000 2922.860000 ;
+ RECT 1657.820000 2916.940000 1658.920000 2917.420000 ;
+ RECT 1653.690000 2916.940000 1654.690000 2917.420000 ;
+ RECT 1657.820000 2906.060000 1658.920000 2906.540000 ;
+ RECT 1653.690000 2906.060000 1654.690000 2906.540000 ;
+ RECT 1657.820000 2900.620000 1658.920000 2901.100000 ;
+ RECT 1653.690000 2900.620000 1654.690000 2901.100000 ;
+ RECT 1657.820000 2911.500000 1658.920000 2911.980000 ;
+ RECT 1653.690000 2911.500000 1654.690000 2911.980000 ;
+ RECT 1747.820000 2895.180000 1748.920000 2895.660000 ;
+ RECT 1747.820000 2889.740000 1748.920000 2890.220000 ;
+ RECT 1747.820000 2884.300000 1748.920000 2884.780000 ;
+ RECT 1747.820000 2878.860000 1748.920000 2879.340000 ;
+ RECT 1702.820000 2895.180000 1703.920000 2895.660000 ;
+ RECT 1702.820000 2889.740000 1703.920000 2890.220000 ;
+ RECT 1702.820000 2884.300000 1703.920000 2884.780000 ;
+ RECT 1702.820000 2878.860000 1703.920000 2879.340000 ;
+ RECT 1747.820000 2867.980000 1748.920000 2868.460000 ;
+ RECT 1747.820000 2851.660000 1748.920000 2852.140000 ;
+ RECT 1747.820000 2857.100000 1748.920000 2857.580000 ;
+ RECT 1747.820000 2862.540000 1748.920000 2863.020000 ;
+ RECT 1747.820000 2873.420000 1748.920000 2873.900000 ;
+ RECT 1702.820000 2851.660000 1703.920000 2852.140000 ;
+ RECT 1702.820000 2857.100000 1703.920000 2857.580000 ;
+ RECT 1702.820000 2862.540000 1703.920000 2863.020000 ;
+ RECT 1702.820000 2867.980000 1703.920000 2868.460000 ;
+ RECT 1702.820000 2873.420000 1703.920000 2873.900000 ;
+ RECT 1657.820000 2895.180000 1658.920000 2895.660000 ;
+ RECT 1653.690000 2895.180000 1654.690000 2895.660000 ;
+ RECT 1657.820000 2889.740000 1658.920000 2890.220000 ;
+ RECT 1653.690000 2889.740000 1654.690000 2890.220000 ;
+ RECT 1657.820000 2884.300000 1658.920000 2884.780000 ;
+ RECT 1653.690000 2884.300000 1654.690000 2884.780000 ;
+ RECT 1657.820000 2878.860000 1658.920000 2879.340000 ;
+ RECT 1653.690000 2878.860000 1654.690000 2879.340000 ;
+ RECT 1657.820000 2873.420000 1658.920000 2873.900000 ;
+ RECT 1657.820000 2867.980000 1658.920000 2868.460000 ;
+ RECT 1653.690000 2873.420000 1654.690000 2873.900000 ;
+ RECT 1653.690000 2867.980000 1654.690000 2868.460000 ;
+ RECT 1657.820000 2862.540000 1658.920000 2863.020000 ;
+ RECT 1653.690000 2862.540000 1654.690000 2863.020000 ;
+ RECT 1657.820000 2857.100000 1658.920000 2857.580000 ;
+ RECT 1653.690000 2857.100000 1654.690000 2857.580000 ;
+ RECT 1657.820000 2851.660000 1658.920000 2852.140000 ;
+ RECT 1653.690000 2851.660000 1654.690000 2852.140000 ;
+ RECT 1837.820000 2846.220000 1838.920000 2846.700000 ;
+ RECT 1837.820000 2840.780000 1838.920000 2841.260000 ;
+ RECT 1847.130000 2846.220000 1848.130000 2846.700000 ;
+ RECT 1847.130000 2840.780000 1848.130000 2841.260000 ;
+ RECT 1847.130000 2824.460000 1848.130000 2824.940000 ;
+ RECT 1847.130000 2829.900000 1848.130000 2830.380000 ;
+ RECT 1847.130000 2835.340000 1848.130000 2835.820000 ;
+ RECT 1837.820000 2835.340000 1838.920000 2835.820000 ;
+ RECT 1837.820000 2829.900000 1838.920000 2830.380000 ;
+ RECT 1837.820000 2824.460000 1838.920000 2824.940000 ;
+ RECT 1837.820000 2813.580000 1838.920000 2814.060000 ;
+ RECT 1837.820000 2819.020000 1838.920000 2819.500000 ;
+ RECT 1847.130000 2819.020000 1848.130000 2819.500000 ;
+ RECT 1847.130000 2813.580000 1848.130000 2814.060000 ;
+ RECT 1847.130000 2802.700000 1848.130000 2803.180000 ;
+ RECT 1847.130000 2808.140000 1848.130000 2808.620000 ;
+ RECT 1837.820000 2802.700000 1838.920000 2803.180000 ;
+ RECT 1837.820000 2808.140000 1838.920000 2808.620000 ;
+ RECT 1792.820000 2846.220000 1793.920000 2846.700000 ;
+ RECT 1792.820000 2840.780000 1793.920000 2841.260000 ;
+ RECT 1792.820000 2835.340000 1793.920000 2835.820000 ;
+ RECT 1792.820000 2829.900000 1793.920000 2830.380000 ;
+ RECT 1792.820000 2824.460000 1793.920000 2824.940000 ;
+ RECT 1792.820000 2802.700000 1793.920000 2803.180000 ;
+ RECT 1792.820000 2808.140000 1793.920000 2808.620000 ;
+ RECT 1792.820000 2813.580000 1793.920000 2814.060000 ;
+ RECT 1792.820000 2819.020000 1793.920000 2819.500000 ;
+ RECT 1837.820000 2797.260000 1838.920000 2797.740000 ;
+ RECT 1837.820000 2791.820000 1838.920000 2792.300000 ;
+ RECT 1847.130000 2797.260000 1848.130000 2797.740000 ;
+ RECT 1847.130000 2791.820000 1848.130000 2792.300000 ;
+ RECT 1837.820000 2780.940000 1838.920000 2781.420000 ;
+ RECT 1837.820000 2775.500000 1838.920000 2775.980000 ;
+ RECT 1847.130000 2780.940000 1848.130000 2781.420000 ;
+ RECT 1847.130000 2775.500000 1848.130000 2775.980000 ;
+ RECT 1837.820000 2786.380000 1838.920000 2786.860000 ;
+ RECT 1847.130000 2786.380000 1848.130000 2786.860000 ;
+ RECT 1847.130000 2764.620000 1848.130000 2765.100000 ;
+ RECT 1847.130000 2770.060000 1848.130000 2770.540000 ;
+ RECT 1837.820000 2770.060000 1838.920000 2770.540000 ;
+ RECT 1837.820000 2764.620000 1838.920000 2765.100000 ;
+ RECT 1837.820000 2759.180000 1838.920000 2759.660000 ;
+ RECT 1837.820000 2753.740000 1838.920000 2754.220000 ;
+ RECT 1847.130000 2759.180000 1848.130000 2759.660000 ;
+ RECT 1847.130000 2753.740000 1848.130000 2754.220000 ;
+ RECT 1792.820000 2797.260000 1793.920000 2797.740000 ;
+ RECT 1792.820000 2791.820000 1793.920000 2792.300000 ;
+ RECT 1792.820000 2786.380000 1793.920000 2786.860000 ;
+ RECT 1792.820000 2780.940000 1793.920000 2781.420000 ;
+ RECT 1792.820000 2775.500000 1793.920000 2775.980000 ;
+ RECT 1792.820000 2770.060000 1793.920000 2770.540000 ;
+ RECT 1792.820000 2764.620000 1793.920000 2765.100000 ;
+ RECT 1792.820000 2759.180000 1793.920000 2759.660000 ;
+ RECT 1792.820000 2753.740000 1793.920000 2754.220000 ;
+ RECT 1747.820000 2846.220000 1748.920000 2846.700000 ;
+ RECT 1747.820000 2840.780000 1748.920000 2841.260000 ;
+ RECT 1747.820000 2835.340000 1748.920000 2835.820000 ;
+ RECT 1747.820000 2829.900000 1748.920000 2830.380000 ;
+ RECT 1747.820000 2824.460000 1748.920000 2824.940000 ;
+ RECT 1702.820000 2846.220000 1703.920000 2846.700000 ;
+ RECT 1702.820000 2840.780000 1703.920000 2841.260000 ;
+ RECT 1702.820000 2835.340000 1703.920000 2835.820000 ;
+ RECT 1702.820000 2829.900000 1703.920000 2830.380000 ;
+ RECT 1702.820000 2824.460000 1703.920000 2824.940000 ;
+ RECT 1747.820000 2819.020000 1748.920000 2819.500000 ;
+ RECT 1747.820000 2813.580000 1748.920000 2814.060000 ;
+ RECT 1747.820000 2808.140000 1748.920000 2808.620000 ;
+ RECT 1747.820000 2802.700000 1748.920000 2803.180000 ;
+ RECT 1702.820000 2813.580000 1703.920000 2814.060000 ;
+ RECT 1702.820000 2808.140000 1703.920000 2808.620000 ;
+ RECT 1702.820000 2802.700000 1703.920000 2803.180000 ;
+ RECT 1702.820000 2819.020000 1703.920000 2819.500000 ;
+ RECT 1657.820000 2846.220000 1658.920000 2846.700000 ;
+ RECT 1653.690000 2846.220000 1654.690000 2846.700000 ;
+ RECT 1657.820000 2840.780000 1658.920000 2841.260000 ;
+ RECT 1653.690000 2840.780000 1654.690000 2841.260000 ;
+ RECT 1657.820000 2835.340000 1658.920000 2835.820000 ;
+ RECT 1653.690000 2835.340000 1654.690000 2835.820000 ;
+ RECT 1657.820000 2824.460000 1658.920000 2824.940000 ;
+ RECT 1653.690000 2824.460000 1654.690000 2824.940000 ;
+ RECT 1653.690000 2829.900000 1654.690000 2830.380000 ;
+ RECT 1657.820000 2829.900000 1658.920000 2830.380000 ;
+ RECT 1657.820000 2819.020000 1658.920000 2819.500000 ;
+ RECT 1653.690000 2819.020000 1654.690000 2819.500000 ;
+ RECT 1657.820000 2813.580000 1658.920000 2814.060000 ;
+ RECT 1653.690000 2813.580000 1654.690000 2814.060000 ;
+ RECT 1657.820000 2808.140000 1658.920000 2808.620000 ;
+ RECT 1653.690000 2808.140000 1654.690000 2808.620000 ;
+ RECT 1657.820000 2802.700000 1658.920000 2803.180000 ;
+ RECT 1653.690000 2802.700000 1654.690000 2803.180000 ;
+ RECT 1747.820000 2797.260000 1748.920000 2797.740000 ;
+ RECT 1747.820000 2791.820000 1748.920000 2792.300000 ;
+ RECT 1747.820000 2786.380000 1748.920000 2786.860000 ;
+ RECT 1747.820000 2780.940000 1748.920000 2781.420000 ;
+ RECT 1747.820000 2775.500000 1748.920000 2775.980000 ;
+ RECT 1702.820000 2797.260000 1703.920000 2797.740000 ;
+ RECT 1702.820000 2791.820000 1703.920000 2792.300000 ;
+ RECT 1702.820000 2786.380000 1703.920000 2786.860000 ;
+ RECT 1702.820000 2780.940000 1703.920000 2781.420000 ;
+ RECT 1702.820000 2775.500000 1703.920000 2775.980000 ;
+ RECT 1747.820000 2753.740000 1748.920000 2754.220000 ;
+ RECT 1747.820000 2759.180000 1748.920000 2759.660000 ;
+ RECT 1747.820000 2764.620000 1748.920000 2765.100000 ;
+ RECT 1747.820000 2770.060000 1748.920000 2770.540000 ;
+ RECT 1702.820000 2753.740000 1703.920000 2754.220000 ;
+ RECT 1702.820000 2759.180000 1703.920000 2759.660000 ;
+ RECT 1702.820000 2764.620000 1703.920000 2765.100000 ;
+ RECT 1702.820000 2770.060000 1703.920000 2770.540000 ;
+ RECT 1657.820000 2797.260000 1658.920000 2797.740000 ;
+ RECT 1653.690000 2797.260000 1654.690000 2797.740000 ;
+ RECT 1657.820000 2791.820000 1658.920000 2792.300000 ;
+ RECT 1653.690000 2791.820000 1654.690000 2792.300000 ;
+ RECT 1657.820000 2780.940000 1658.920000 2781.420000 ;
+ RECT 1653.690000 2780.940000 1654.690000 2781.420000 ;
+ RECT 1657.820000 2775.500000 1658.920000 2775.980000 ;
+ RECT 1653.690000 2775.500000 1654.690000 2775.980000 ;
+ RECT 1657.820000 2786.380000 1658.920000 2786.860000 ;
+ RECT 1653.690000 2786.380000 1654.690000 2786.860000 ;
+ RECT 1657.820000 2770.060000 1658.920000 2770.540000 ;
+ RECT 1653.690000 2770.060000 1654.690000 2770.540000 ;
+ RECT 1657.820000 2764.620000 1658.920000 2765.100000 ;
+ RECT 1653.690000 2764.620000 1654.690000 2765.100000 ;
+ RECT 1657.820000 2759.180000 1658.920000 2759.660000 ;
+ RECT 1657.820000 2753.740000 1658.920000 2754.220000 ;
+ RECT 1653.690000 2759.180000 1654.690000 2759.660000 ;
+ RECT 1653.690000 2753.740000 1654.690000 2754.220000 ;
+ RECT 1650.860000 2944.100000 1850.960000 2945.100000 ;
+ RECT 1650.860000 2751.730000 1850.960000 2752.730000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 2748.880000 1654.690000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 2948.140000 1654.690000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 2748.880000 1848.130000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 2948.140000 1848.130000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2751.730000 1651.860000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2751.730000 1850.960000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2944.100000 1651.860000 2945.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2944.100000 1850.960000 2945.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 2551.470000 1838.920000 2744.840000 ;
+ RECT 1792.820000 2551.470000 1793.920000 2744.840000 ;
+ RECT 1847.130000 2548.620000 1848.130000 2748.880000 ;
+ RECT 1747.820000 2551.470000 1748.920000 2744.840000 ;
+ RECT 1702.820000 2551.470000 1703.920000 2744.840000 ;
+ RECT 1657.820000 2551.470000 1658.920000 2744.840000 ;
+ RECT 1653.690000 2548.620000 1654.690000 2748.880000 ;
+ LAYER met3 ;
+ RECT 1837.820000 2738.440000 1838.920000 2738.920000 ;
+ RECT 1847.130000 2738.440000 1848.130000 2738.920000 ;
+ RECT 1847.130000 2727.560000 1848.130000 2728.040000 ;
+ RECT 1847.130000 2733.000000 1848.130000 2733.480000 ;
+ RECT 1837.820000 2733.000000 1838.920000 2733.480000 ;
+ RECT 1837.820000 2727.560000 1838.920000 2728.040000 ;
+ RECT 1837.820000 2722.120000 1838.920000 2722.600000 ;
+ RECT 1837.820000 2716.680000 1838.920000 2717.160000 ;
+ RECT 1847.130000 2722.120000 1848.130000 2722.600000 ;
+ RECT 1847.130000 2716.680000 1848.130000 2717.160000 ;
+ RECT 1837.820000 2700.360000 1838.920000 2700.840000 ;
+ RECT 1837.820000 2705.800000 1838.920000 2706.280000 ;
+ RECT 1847.130000 2705.800000 1848.130000 2706.280000 ;
+ RECT 1847.130000 2700.360000 1848.130000 2700.840000 ;
+ RECT 1837.820000 2711.240000 1838.920000 2711.720000 ;
+ RECT 1847.130000 2711.240000 1848.130000 2711.720000 ;
+ RECT 1792.820000 2738.440000 1793.920000 2738.920000 ;
+ RECT 1792.820000 2733.000000 1793.920000 2733.480000 ;
+ RECT 1792.820000 2727.560000 1793.920000 2728.040000 ;
+ RECT 1792.820000 2722.120000 1793.920000 2722.600000 ;
+ RECT 1792.820000 2700.360000 1793.920000 2700.840000 ;
+ RECT 1792.820000 2705.800000 1793.920000 2706.280000 ;
+ RECT 1792.820000 2711.240000 1793.920000 2711.720000 ;
+ RECT 1792.820000 2716.680000 1793.920000 2717.160000 ;
+ RECT 1847.130000 2689.480000 1848.130000 2689.960000 ;
+ RECT 1847.130000 2694.920000 1848.130000 2695.400000 ;
+ RECT 1837.820000 2694.920000 1838.920000 2695.400000 ;
+ RECT 1837.820000 2689.480000 1838.920000 2689.960000 ;
+ RECT 1837.820000 2684.040000 1838.920000 2684.520000 ;
+ RECT 1837.820000 2678.600000 1838.920000 2679.080000 ;
+ RECT 1847.130000 2684.040000 1848.130000 2684.520000 ;
+ RECT 1847.130000 2678.600000 1848.130000 2679.080000 ;
+ RECT 1847.130000 2662.280000 1848.130000 2662.760000 ;
+ RECT 1847.130000 2667.720000 1848.130000 2668.200000 ;
+ RECT 1847.130000 2673.160000 1848.130000 2673.640000 ;
+ RECT 1837.820000 2667.720000 1838.920000 2668.200000 ;
+ RECT 1837.820000 2662.280000 1838.920000 2662.760000 ;
+ RECT 1837.820000 2673.160000 1838.920000 2673.640000 ;
+ RECT 1837.820000 2656.840000 1838.920000 2657.320000 ;
+ RECT 1837.820000 2651.400000 1838.920000 2651.880000 ;
+ RECT 1847.130000 2656.840000 1848.130000 2657.320000 ;
+ RECT 1847.130000 2651.400000 1848.130000 2651.880000 ;
+ RECT 1792.820000 2694.920000 1793.920000 2695.400000 ;
+ RECT 1792.820000 2689.480000 1793.920000 2689.960000 ;
+ RECT 1792.820000 2684.040000 1793.920000 2684.520000 ;
+ RECT 1792.820000 2678.600000 1793.920000 2679.080000 ;
+ RECT 1792.820000 2667.720000 1793.920000 2668.200000 ;
+ RECT 1792.820000 2662.280000 1793.920000 2662.760000 ;
+ RECT 1792.820000 2656.840000 1793.920000 2657.320000 ;
+ RECT 1792.820000 2651.400000 1793.920000 2651.880000 ;
+ RECT 1792.820000 2673.160000 1793.920000 2673.640000 ;
+ RECT 1747.820000 2738.440000 1748.920000 2738.920000 ;
+ RECT 1747.820000 2733.000000 1748.920000 2733.480000 ;
+ RECT 1747.820000 2727.560000 1748.920000 2728.040000 ;
+ RECT 1702.820000 2738.440000 1703.920000 2738.920000 ;
+ RECT 1702.820000 2733.000000 1703.920000 2733.480000 ;
+ RECT 1702.820000 2727.560000 1703.920000 2728.040000 ;
+ RECT 1747.820000 2711.240000 1748.920000 2711.720000 ;
+ RECT 1747.820000 2705.800000 1748.920000 2706.280000 ;
+ RECT 1747.820000 2700.360000 1748.920000 2700.840000 ;
+ RECT 1747.820000 2716.680000 1748.920000 2717.160000 ;
+ RECT 1747.820000 2722.120000 1748.920000 2722.600000 ;
+ RECT 1702.820000 2722.120000 1703.920000 2722.600000 ;
+ RECT 1702.820000 2711.240000 1703.920000 2711.720000 ;
+ RECT 1702.820000 2705.800000 1703.920000 2706.280000 ;
+ RECT 1702.820000 2700.360000 1703.920000 2700.840000 ;
+ RECT 1702.820000 2716.680000 1703.920000 2717.160000 ;
+ RECT 1657.820000 2738.440000 1658.920000 2738.920000 ;
+ RECT 1653.690000 2738.440000 1654.690000 2738.920000 ;
+ RECT 1653.690000 2733.000000 1654.690000 2733.480000 ;
+ RECT 1657.820000 2733.000000 1658.920000 2733.480000 ;
+ RECT 1657.820000 2727.560000 1658.920000 2728.040000 ;
+ RECT 1653.690000 2727.560000 1654.690000 2728.040000 ;
+ RECT 1657.820000 2722.120000 1658.920000 2722.600000 ;
+ RECT 1653.690000 2722.120000 1654.690000 2722.600000 ;
+ RECT 1657.820000 2716.680000 1658.920000 2717.160000 ;
+ RECT 1653.690000 2716.680000 1654.690000 2717.160000 ;
+ RECT 1657.820000 2705.800000 1658.920000 2706.280000 ;
+ RECT 1653.690000 2705.800000 1654.690000 2706.280000 ;
+ RECT 1657.820000 2700.360000 1658.920000 2700.840000 ;
+ RECT 1653.690000 2700.360000 1654.690000 2700.840000 ;
+ RECT 1657.820000 2711.240000 1658.920000 2711.720000 ;
+ RECT 1653.690000 2711.240000 1654.690000 2711.720000 ;
+ RECT 1747.820000 2694.920000 1748.920000 2695.400000 ;
+ RECT 1747.820000 2689.480000 1748.920000 2689.960000 ;
+ RECT 1747.820000 2684.040000 1748.920000 2684.520000 ;
+ RECT 1747.820000 2678.600000 1748.920000 2679.080000 ;
+ RECT 1702.820000 2694.920000 1703.920000 2695.400000 ;
+ RECT 1702.820000 2689.480000 1703.920000 2689.960000 ;
+ RECT 1702.820000 2684.040000 1703.920000 2684.520000 ;
+ RECT 1702.820000 2678.600000 1703.920000 2679.080000 ;
+ RECT 1747.820000 2667.720000 1748.920000 2668.200000 ;
+ RECT 1747.820000 2651.400000 1748.920000 2651.880000 ;
+ RECT 1747.820000 2656.840000 1748.920000 2657.320000 ;
+ RECT 1747.820000 2662.280000 1748.920000 2662.760000 ;
+ RECT 1747.820000 2673.160000 1748.920000 2673.640000 ;
+ RECT 1702.820000 2651.400000 1703.920000 2651.880000 ;
+ RECT 1702.820000 2656.840000 1703.920000 2657.320000 ;
+ RECT 1702.820000 2662.280000 1703.920000 2662.760000 ;
+ RECT 1702.820000 2667.720000 1703.920000 2668.200000 ;
+ RECT 1702.820000 2673.160000 1703.920000 2673.640000 ;
+ RECT 1657.820000 2694.920000 1658.920000 2695.400000 ;
+ RECT 1653.690000 2694.920000 1654.690000 2695.400000 ;
+ RECT 1657.820000 2689.480000 1658.920000 2689.960000 ;
+ RECT 1653.690000 2689.480000 1654.690000 2689.960000 ;
+ RECT 1657.820000 2684.040000 1658.920000 2684.520000 ;
+ RECT 1653.690000 2684.040000 1654.690000 2684.520000 ;
+ RECT 1657.820000 2678.600000 1658.920000 2679.080000 ;
+ RECT 1653.690000 2678.600000 1654.690000 2679.080000 ;
+ RECT 1657.820000 2673.160000 1658.920000 2673.640000 ;
+ RECT 1657.820000 2667.720000 1658.920000 2668.200000 ;
+ RECT 1653.690000 2673.160000 1654.690000 2673.640000 ;
+ RECT 1653.690000 2667.720000 1654.690000 2668.200000 ;
+ RECT 1657.820000 2662.280000 1658.920000 2662.760000 ;
+ RECT 1653.690000 2662.280000 1654.690000 2662.760000 ;
+ RECT 1657.820000 2656.840000 1658.920000 2657.320000 ;
+ RECT 1653.690000 2656.840000 1654.690000 2657.320000 ;
+ RECT 1657.820000 2651.400000 1658.920000 2651.880000 ;
+ RECT 1653.690000 2651.400000 1654.690000 2651.880000 ;
+ RECT 1837.820000 2645.960000 1838.920000 2646.440000 ;
+ RECT 1837.820000 2640.520000 1838.920000 2641.000000 ;
+ RECT 1847.130000 2645.960000 1848.130000 2646.440000 ;
+ RECT 1847.130000 2640.520000 1848.130000 2641.000000 ;
+ RECT 1847.130000 2624.200000 1848.130000 2624.680000 ;
+ RECT 1847.130000 2629.640000 1848.130000 2630.120000 ;
+ RECT 1847.130000 2635.080000 1848.130000 2635.560000 ;
+ RECT 1837.820000 2635.080000 1838.920000 2635.560000 ;
+ RECT 1837.820000 2629.640000 1838.920000 2630.120000 ;
+ RECT 1837.820000 2624.200000 1838.920000 2624.680000 ;
+ RECT 1837.820000 2613.320000 1838.920000 2613.800000 ;
+ RECT 1837.820000 2618.760000 1838.920000 2619.240000 ;
+ RECT 1847.130000 2618.760000 1848.130000 2619.240000 ;
+ RECT 1847.130000 2613.320000 1848.130000 2613.800000 ;
+ RECT 1847.130000 2602.440000 1848.130000 2602.920000 ;
+ RECT 1847.130000 2607.880000 1848.130000 2608.360000 ;
+ RECT 1837.820000 2602.440000 1838.920000 2602.920000 ;
+ RECT 1837.820000 2607.880000 1838.920000 2608.360000 ;
+ RECT 1792.820000 2645.960000 1793.920000 2646.440000 ;
+ RECT 1792.820000 2640.520000 1793.920000 2641.000000 ;
+ RECT 1792.820000 2635.080000 1793.920000 2635.560000 ;
+ RECT 1792.820000 2629.640000 1793.920000 2630.120000 ;
+ RECT 1792.820000 2624.200000 1793.920000 2624.680000 ;
+ RECT 1792.820000 2602.440000 1793.920000 2602.920000 ;
+ RECT 1792.820000 2607.880000 1793.920000 2608.360000 ;
+ RECT 1792.820000 2613.320000 1793.920000 2613.800000 ;
+ RECT 1792.820000 2618.760000 1793.920000 2619.240000 ;
+ RECT 1837.820000 2597.000000 1838.920000 2597.480000 ;
+ RECT 1837.820000 2591.560000 1838.920000 2592.040000 ;
+ RECT 1847.130000 2597.000000 1848.130000 2597.480000 ;
+ RECT 1847.130000 2591.560000 1848.130000 2592.040000 ;
+ RECT 1837.820000 2580.680000 1838.920000 2581.160000 ;
+ RECT 1837.820000 2575.240000 1838.920000 2575.720000 ;
+ RECT 1847.130000 2580.680000 1848.130000 2581.160000 ;
+ RECT 1847.130000 2575.240000 1848.130000 2575.720000 ;
+ RECT 1837.820000 2586.120000 1838.920000 2586.600000 ;
+ RECT 1847.130000 2586.120000 1848.130000 2586.600000 ;
+ RECT 1847.130000 2564.360000 1848.130000 2564.840000 ;
+ RECT 1847.130000 2569.800000 1848.130000 2570.280000 ;
+ RECT 1837.820000 2569.800000 1838.920000 2570.280000 ;
+ RECT 1837.820000 2564.360000 1838.920000 2564.840000 ;
+ RECT 1837.820000 2558.920000 1838.920000 2559.400000 ;
+ RECT 1837.820000 2553.480000 1838.920000 2553.960000 ;
+ RECT 1847.130000 2558.920000 1848.130000 2559.400000 ;
+ RECT 1847.130000 2553.480000 1848.130000 2553.960000 ;
+ RECT 1792.820000 2597.000000 1793.920000 2597.480000 ;
+ RECT 1792.820000 2591.560000 1793.920000 2592.040000 ;
+ RECT 1792.820000 2586.120000 1793.920000 2586.600000 ;
+ RECT 1792.820000 2580.680000 1793.920000 2581.160000 ;
+ RECT 1792.820000 2575.240000 1793.920000 2575.720000 ;
+ RECT 1792.820000 2569.800000 1793.920000 2570.280000 ;
+ RECT 1792.820000 2564.360000 1793.920000 2564.840000 ;
+ RECT 1792.820000 2558.920000 1793.920000 2559.400000 ;
+ RECT 1792.820000 2553.480000 1793.920000 2553.960000 ;
+ RECT 1747.820000 2645.960000 1748.920000 2646.440000 ;
+ RECT 1747.820000 2640.520000 1748.920000 2641.000000 ;
+ RECT 1747.820000 2635.080000 1748.920000 2635.560000 ;
+ RECT 1747.820000 2629.640000 1748.920000 2630.120000 ;
+ RECT 1747.820000 2624.200000 1748.920000 2624.680000 ;
+ RECT 1702.820000 2645.960000 1703.920000 2646.440000 ;
+ RECT 1702.820000 2640.520000 1703.920000 2641.000000 ;
+ RECT 1702.820000 2635.080000 1703.920000 2635.560000 ;
+ RECT 1702.820000 2629.640000 1703.920000 2630.120000 ;
+ RECT 1702.820000 2624.200000 1703.920000 2624.680000 ;
+ RECT 1747.820000 2618.760000 1748.920000 2619.240000 ;
+ RECT 1747.820000 2613.320000 1748.920000 2613.800000 ;
+ RECT 1747.820000 2607.880000 1748.920000 2608.360000 ;
+ RECT 1747.820000 2602.440000 1748.920000 2602.920000 ;
+ RECT 1702.820000 2613.320000 1703.920000 2613.800000 ;
+ RECT 1702.820000 2607.880000 1703.920000 2608.360000 ;
+ RECT 1702.820000 2602.440000 1703.920000 2602.920000 ;
+ RECT 1702.820000 2618.760000 1703.920000 2619.240000 ;
+ RECT 1657.820000 2645.960000 1658.920000 2646.440000 ;
+ RECT 1653.690000 2645.960000 1654.690000 2646.440000 ;
+ RECT 1657.820000 2640.520000 1658.920000 2641.000000 ;
+ RECT 1653.690000 2640.520000 1654.690000 2641.000000 ;
+ RECT 1657.820000 2635.080000 1658.920000 2635.560000 ;
+ RECT 1653.690000 2635.080000 1654.690000 2635.560000 ;
+ RECT 1657.820000 2624.200000 1658.920000 2624.680000 ;
+ RECT 1653.690000 2624.200000 1654.690000 2624.680000 ;
+ RECT 1653.690000 2629.640000 1654.690000 2630.120000 ;
+ RECT 1657.820000 2629.640000 1658.920000 2630.120000 ;
+ RECT 1657.820000 2618.760000 1658.920000 2619.240000 ;
+ RECT 1653.690000 2618.760000 1654.690000 2619.240000 ;
+ RECT 1657.820000 2613.320000 1658.920000 2613.800000 ;
+ RECT 1653.690000 2613.320000 1654.690000 2613.800000 ;
+ RECT 1657.820000 2607.880000 1658.920000 2608.360000 ;
+ RECT 1653.690000 2607.880000 1654.690000 2608.360000 ;
+ RECT 1657.820000 2602.440000 1658.920000 2602.920000 ;
+ RECT 1653.690000 2602.440000 1654.690000 2602.920000 ;
+ RECT 1747.820000 2597.000000 1748.920000 2597.480000 ;
+ RECT 1747.820000 2591.560000 1748.920000 2592.040000 ;
+ RECT 1747.820000 2586.120000 1748.920000 2586.600000 ;
+ RECT 1747.820000 2580.680000 1748.920000 2581.160000 ;
+ RECT 1747.820000 2575.240000 1748.920000 2575.720000 ;
+ RECT 1702.820000 2597.000000 1703.920000 2597.480000 ;
+ RECT 1702.820000 2591.560000 1703.920000 2592.040000 ;
+ RECT 1702.820000 2586.120000 1703.920000 2586.600000 ;
+ RECT 1702.820000 2580.680000 1703.920000 2581.160000 ;
+ RECT 1702.820000 2575.240000 1703.920000 2575.720000 ;
+ RECT 1747.820000 2553.480000 1748.920000 2553.960000 ;
+ RECT 1747.820000 2558.920000 1748.920000 2559.400000 ;
+ RECT 1747.820000 2564.360000 1748.920000 2564.840000 ;
+ RECT 1747.820000 2569.800000 1748.920000 2570.280000 ;
+ RECT 1702.820000 2553.480000 1703.920000 2553.960000 ;
+ RECT 1702.820000 2558.920000 1703.920000 2559.400000 ;
+ RECT 1702.820000 2564.360000 1703.920000 2564.840000 ;
+ RECT 1702.820000 2569.800000 1703.920000 2570.280000 ;
+ RECT 1657.820000 2597.000000 1658.920000 2597.480000 ;
+ RECT 1653.690000 2597.000000 1654.690000 2597.480000 ;
+ RECT 1657.820000 2591.560000 1658.920000 2592.040000 ;
+ RECT 1653.690000 2591.560000 1654.690000 2592.040000 ;
+ RECT 1657.820000 2580.680000 1658.920000 2581.160000 ;
+ RECT 1653.690000 2580.680000 1654.690000 2581.160000 ;
+ RECT 1657.820000 2575.240000 1658.920000 2575.720000 ;
+ RECT 1653.690000 2575.240000 1654.690000 2575.720000 ;
+ RECT 1657.820000 2586.120000 1658.920000 2586.600000 ;
+ RECT 1653.690000 2586.120000 1654.690000 2586.600000 ;
+ RECT 1657.820000 2569.800000 1658.920000 2570.280000 ;
+ RECT 1653.690000 2569.800000 1654.690000 2570.280000 ;
+ RECT 1657.820000 2564.360000 1658.920000 2564.840000 ;
+ RECT 1653.690000 2564.360000 1654.690000 2564.840000 ;
+ RECT 1657.820000 2558.920000 1658.920000 2559.400000 ;
+ RECT 1657.820000 2553.480000 1658.920000 2553.960000 ;
+ RECT 1653.690000 2558.920000 1654.690000 2559.400000 ;
+ RECT 1653.690000 2553.480000 1654.690000 2553.960000 ;
+ RECT 1650.860000 2743.840000 1850.960000 2744.840000 ;
+ RECT 1650.860000 2551.470000 1850.960000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 2548.620000 1654.690000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 2747.880000 1654.690000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 2548.620000 1848.130000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 2747.880000 1848.130000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2551.470000 1651.860000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2551.470000 1850.960000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2743.840000 1651.860000 2744.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2743.840000 1850.960000 2744.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 2351.210000 1838.920000 2544.580000 ;
+ RECT 1792.820000 2351.210000 1793.920000 2544.580000 ;
+ RECT 1847.130000 2348.360000 1848.130000 2548.620000 ;
+ RECT 1747.820000 2351.210000 1748.920000 2544.580000 ;
+ RECT 1702.820000 2351.210000 1703.920000 2544.580000 ;
+ RECT 1657.820000 2351.210000 1658.920000 2544.580000 ;
+ RECT 1653.690000 2348.360000 1654.690000 2548.620000 ;
+ LAYER met3 ;
+ RECT 1837.820000 2538.180000 1838.920000 2538.660000 ;
+ RECT 1847.130000 2538.180000 1848.130000 2538.660000 ;
+ RECT 1847.130000 2527.300000 1848.130000 2527.780000 ;
+ RECT 1847.130000 2532.740000 1848.130000 2533.220000 ;
+ RECT 1837.820000 2532.740000 1838.920000 2533.220000 ;
+ RECT 1837.820000 2527.300000 1838.920000 2527.780000 ;
+ RECT 1837.820000 2521.860000 1838.920000 2522.340000 ;
+ RECT 1837.820000 2516.420000 1838.920000 2516.900000 ;
+ RECT 1847.130000 2521.860000 1848.130000 2522.340000 ;
+ RECT 1847.130000 2516.420000 1848.130000 2516.900000 ;
+ RECT 1837.820000 2500.100000 1838.920000 2500.580000 ;
+ RECT 1837.820000 2505.540000 1838.920000 2506.020000 ;
+ RECT 1847.130000 2505.540000 1848.130000 2506.020000 ;
+ RECT 1847.130000 2500.100000 1848.130000 2500.580000 ;
+ RECT 1837.820000 2510.980000 1838.920000 2511.460000 ;
+ RECT 1847.130000 2510.980000 1848.130000 2511.460000 ;
+ RECT 1792.820000 2538.180000 1793.920000 2538.660000 ;
+ RECT 1792.820000 2532.740000 1793.920000 2533.220000 ;
+ RECT 1792.820000 2527.300000 1793.920000 2527.780000 ;
+ RECT 1792.820000 2521.860000 1793.920000 2522.340000 ;
+ RECT 1792.820000 2500.100000 1793.920000 2500.580000 ;
+ RECT 1792.820000 2505.540000 1793.920000 2506.020000 ;
+ RECT 1792.820000 2510.980000 1793.920000 2511.460000 ;
+ RECT 1792.820000 2516.420000 1793.920000 2516.900000 ;
+ RECT 1847.130000 2489.220000 1848.130000 2489.700000 ;
+ RECT 1847.130000 2494.660000 1848.130000 2495.140000 ;
+ RECT 1837.820000 2494.660000 1838.920000 2495.140000 ;
+ RECT 1837.820000 2489.220000 1838.920000 2489.700000 ;
+ RECT 1837.820000 2483.780000 1838.920000 2484.260000 ;
+ RECT 1837.820000 2478.340000 1838.920000 2478.820000 ;
+ RECT 1847.130000 2483.780000 1848.130000 2484.260000 ;
+ RECT 1847.130000 2478.340000 1848.130000 2478.820000 ;
+ RECT 1847.130000 2462.020000 1848.130000 2462.500000 ;
+ RECT 1847.130000 2467.460000 1848.130000 2467.940000 ;
+ RECT 1847.130000 2472.900000 1848.130000 2473.380000 ;
+ RECT 1837.820000 2467.460000 1838.920000 2467.940000 ;
+ RECT 1837.820000 2462.020000 1838.920000 2462.500000 ;
+ RECT 1837.820000 2472.900000 1838.920000 2473.380000 ;
+ RECT 1837.820000 2456.580000 1838.920000 2457.060000 ;
+ RECT 1837.820000 2451.140000 1838.920000 2451.620000 ;
+ RECT 1847.130000 2456.580000 1848.130000 2457.060000 ;
+ RECT 1847.130000 2451.140000 1848.130000 2451.620000 ;
+ RECT 1792.820000 2494.660000 1793.920000 2495.140000 ;
+ RECT 1792.820000 2489.220000 1793.920000 2489.700000 ;
+ RECT 1792.820000 2483.780000 1793.920000 2484.260000 ;
+ RECT 1792.820000 2478.340000 1793.920000 2478.820000 ;
+ RECT 1792.820000 2467.460000 1793.920000 2467.940000 ;
+ RECT 1792.820000 2462.020000 1793.920000 2462.500000 ;
+ RECT 1792.820000 2456.580000 1793.920000 2457.060000 ;
+ RECT 1792.820000 2451.140000 1793.920000 2451.620000 ;
+ RECT 1792.820000 2472.900000 1793.920000 2473.380000 ;
+ RECT 1747.820000 2538.180000 1748.920000 2538.660000 ;
+ RECT 1747.820000 2532.740000 1748.920000 2533.220000 ;
+ RECT 1747.820000 2527.300000 1748.920000 2527.780000 ;
+ RECT 1702.820000 2538.180000 1703.920000 2538.660000 ;
+ RECT 1702.820000 2532.740000 1703.920000 2533.220000 ;
+ RECT 1702.820000 2527.300000 1703.920000 2527.780000 ;
+ RECT 1747.820000 2510.980000 1748.920000 2511.460000 ;
+ RECT 1747.820000 2505.540000 1748.920000 2506.020000 ;
+ RECT 1747.820000 2500.100000 1748.920000 2500.580000 ;
+ RECT 1747.820000 2516.420000 1748.920000 2516.900000 ;
+ RECT 1747.820000 2521.860000 1748.920000 2522.340000 ;
+ RECT 1702.820000 2521.860000 1703.920000 2522.340000 ;
+ RECT 1702.820000 2510.980000 1703.920000 2511.460000 ;
+ RECT 1702.820000 2505.540000 1703.920000 2506.020000 ;
+ RECT 1702.820000 2500.100000 1703.920000 2500.580000 ;
+ RECT 1702.820000 2516.420000 1703.920000 2516.900000 ;
+ RECT 1657.820000 2538.180000 1658.920000 2538.660000 ;
+ RECT 1653.690000 2538.180000 1654.690000 2538.660000 ;
+ RECT 1653.690000 2532.740000 1654.690000 2533.220000 ;
+ RECT 1657.820000 2532.740000 1658.920000 2533.220000 ;
+ RECT 1657.820000 2527.300000 1658.920000 2527.780000 ;
+ RECT 1653.690000 2527.300000 1654.690000 2527.780000 ;
+ RECT 1657.820000 2521.860000 1658.920000 2522.340000 ;
+ RECT 1653.690000 2521.860000 1654.690000 2522.340000 ;
+ RECT 1657.820000 2516.420000 1658.920000 2516.900000 ;
+ RECT 1653.690000 2516.420000 1654.690000 2516.900000 ;
+ RECT 1657.820000 2505.540000 1658.920000 2506.020000 ;
+ RECT 1653.690000 2505.540000 1654.690000 2506.020000 ;
+ RECT 1657.820000 2500.100000 1658.920000 2500.580000 ;
+ RECT 1653.690000 2500.100000 1654.690000 2500.580000 ;
+ RECT 1657.820000 2510.980000 1658.920000 2511.460000 ;
+ RECT 1653.690000 2510.980000 1654.690000 2511.460000 ;
+ RECT 1747.820000 2494.660000 1748.920000 2495.140000 ;
+ RECT 1747.820000 2489.220000 1748.920000 2489.700000 ;
+ RECT 1747.820000 2483.780000 1748.920000 2484.260000 ;
+ RECT 1747.820000 2478.340000 1748.920000 2478.820000 ;
+ RECT 1702.820000 2494.660000 1703.920000 2495.140000 ;
+ RECT 1702.820000 2489.220000 1703.920000 2489.700000 ;
+ RECT 1702.820000 2483.780000 1703.920000 2484.260000 ;
+ RECT 1702.820000 2478.340000 1703.920000 2478.820000 ;
+ RECT 1747.820000 2467.460000 1748.920000 2467.940000 ;
+ RECT 1747.820000 2451.140000 1748.920000 2451.620000 ;
+ RECT 1747.820000 2456.580000 1748.920000 2457.060000 ;
+ RECT 1747.820000 2462.020000 1748.920000 2462.500000 ;
+ RECT 1747.820000 2472.900000 1748.920000 2473.380000 ;
+ RECT 1702.820000 2451.140000 1703.920000 2451.620000 ;
+ RECT 1702.820000 2456.580000 1703.920000 2457.060000 ;
+ RECT 1702.820000 2462.020000 1703.920000 2462.500000 ;
+ RECT 1702.820000 2467.460000 1703.920000 2467.940000 ;
+ RECT 1702.820000 2472.900000 1703.920000 2473.380000 ;
+ RECT 1657.820000 2494.660000 1658.920000 2495.140000 ;
+ RECT 1653.690000 2494.660000 1654.690000 2495.140000 ;
+ RECT 1657.820000 2489.220000 1658.920000 2489.700000 ;
+ RECT 1653.690000 2489.220000 1654.690000 2489.700000 ;
+ RECT 1657.820000 2483.780000 1658.920000 2484.260000 ;
+ RECT 1653.690000 2483.780000 1654.690000 2484.260000 ;
+ RECT 1657.820000 2478.340000 1658.920000 2478.820000 ;
+ RECT 1653.690000 2478.340000 1654.690000 2478.820000 ;
+ RECT 1657.820000 2472.900000 1658.920000 2473.380000 ;
+ RECT 1657.820000 2467.460000 1658.920000 2467.940000 ;
+ RECT 1653.690000 2472.900000 1654.690000 2473.380000 ;
+ RECT 1653.690000 2467.460000 1654.690000 2467.940000 ;
+ RECT 1657.820000 2462.020000 1658.920000 2462.500000 ;
+ RECT 1653.690000 2462.020000 1654.690000 2462.500000 ;
+ RECT 1657.820000 2456.580000 1658.920000 2457.060000 ;
+ RECT 1653.690000 2456.580000 1654.690000 2457.060000 ;
+ RECT 1657.820000 2451.140000 1658.920000 2451.620000 ;
+ RECT 1653.690000 2451.140000 1654.690000 2451.620000 ;
+ RECT 1837.820000 2445.700000 1838.920000 2446.180000 ;
+ RECT 1837.820000 2440.260000 1838.920000 2440.740000 ;
+ RECT 1847.130000 2445.700000 1848.130000 2446.180000 ;
+ RECT 1847.130000 2440.260000 1848.130000 2440.740000 ;
+ RECT 1847.130000 2423.940000 1848.130000 2424.420000 ;
+ RECT 1847.130000 2429.380000 1848.130000 2429.860000 ;
+ RECT 1847.130000 2434.820000 1848.130000 2435.300000 ;
+ RECT 1837.820000 2434.820000 1838.920000 2435.300000 ;
+ RECT 1837.820000 2429.380000 1838.920000 2429.860000 ;
+ RECT 1837.820000 2423.940000 1838.920000 2424.420000 ;
+ RECT 1837.820000 2413.060000 1838.920000 2413.540000 ;
+ RECT 1837.820000 2418.500000 1838.920000 2418.980000 ;
+ RECT 1847.130000 2418.500000 1848.130000 2418.980000 ;
+ RECT 1847.130000 2413.060000 1848.130000 2413.540000 ;
+ RECT 1847.130000 2402.180000 1848.130000 2402.660000 ;
+ RECT 1847.130000 2407.620000 1848.130000 2408.100000 ;
+ RECT 1837.820000 2402.180000 1838.920000 2402.660000 ;
+ RECT 1837.820000 2407.620000 1838.920000 2408.100000 ;
+ RECT 1792.820000 2445.700000 1793.920000 2446.180000 ;
+ RECT 1792.820000 2440.260000 1793.920000 2440.740000 ;
+ RECT 1792.820000 2434.820000 1793.920000 2435.300000 ;
+ RECT 1792.820000 2429.380000 1793.920000 2429.860000 ;
+ RECT 1792.820000 2423.940000 1793.920000 2424.420000 ;
+ RECT 1792.820000 2402.180000 1793.920000 2402.660000 ;
+ RECT 1792.820000 2407.620000 1793.920000 2408.100000 ;
+ RECT 1792.820000 2413.060000 1793.920000 2413.540000 ;
+ RECT 1792.820000 2418.500000 1793.920000 2418.980000 ;
+ RECT 1837.820000 2396.740000 1838.920000 2397.220000 ;
+ RECT 1837.820000 2391.300000 1838.920000 2391.780000 ;
+ RECT 1847.130000 2396.740000 1848.130000 2397.220000 ;
+ RECT 1847.130000 2391.300000 1848.130000 2391.780000 ;
+ RECT 1837.820000 2380.420000 1838.920000 2380.900000 ;
+ RECT 1837.820000 2374.980000 1838.920000 2375.460000 ;
+ RECT 1847.130000 2380.420000 1848.130000 2380.900000 ;
+ RECT 1847.130000 2374.980000 1848.130000 2375.460000 ;
+ RECT 1837.820000 2385.860000 1838.920000 2386.340000 ;
+ RECT 1847.130000 2385.860000 1848.130000 2386.340000 ;
+ RECT 1847.130000 2364.100000 1848.130000 2364.580000 ;
+ RECT 1847.130000 2369.540000 1848.130000 2370.020000 ;
+ RECT 1837.820000 2369.540000 1838.920000 2370.020000 ;
+ RECT 1837.820000 2364.100000 1838.920000 2364.580000 ;
+ RECT 1837.820000 2358.660000 1838.920000 2359.140000 ;
+ RECT 1837.820000 2353.220000 1838.920000 2353.700000 ;
+ RECT 1847.130000 2358.660000 1848.130000 2359.140000 ;
+ RECT 1847.130000 2353.220000 1848.130000 2353.700000 ;
+ RECT 1792.820000 2396.740000 1793.920000 2397.220000 ;
+ RECT 1792.820000 2391.300000 1793.920000 2391.780000 ;
+ RECT 1792.820000 2385.860000 1793.920000 2386.340000 ;
+ RECT 1792.820000 2380.420000 1793.920000 2380.900000 ;
+ RECT 1792.820000 2374.980000 1793.920000 2375.460000 ;
+ RECT 1792.820000 2369.540000 1793.920000 2370.020000 ;
+ RECT 1792.820000 2364.100000 1793.920000 2364.580000 ;
+ RECT 1792.820000 2358.660000 1793.920000 2359.140000 ;
+ RECT 1792.820000 2353.220000 1793.920000 2353.700000 ;
+ RECT 1747.820000 2445.700000 1748.920000 2446.180000 ;
+ RECT 1747.820000 2440.260000 1748.920000 2440.740000 ;
+ RECT 1747.820000 2434.820000 1748.920000 2435.300000 ;
+ RECT 1747.820000 2429.380000 1748.920000 2429.860000 ;
+ RECT 1747.820000 2423.940000 1748.920000 2424.420000 ;
+ RECT 1702.820000 2445.700000 1703.920000 2446.180000 ;
+ RECT 1702.820000 2440.260000 1703.920000 2440.740000 ;
+ RECT 1702.820000 2434.820000 1703.920000 2435.300000 ;
+ RECT 1702.820000 2429.380000 1703.920000 2429.860000 ;
+ RECT 1702.820000 2423.940000 1703.920000 2424.420000 ;
+ RECT 1747.820000 2418.500000 1748.920000 2418.980000 ;
+ RECT 1747.820000 2413.060000 1748.920000 2413.540000 ;
+ RECT 1747.820000 2407.620000 1748.920000 2408.100000 ;
+ RECT 1747.820000 2402.180000 1748.920000 2402.660000 ;
+ RECT 1702.820000 2413.060000 1703.920000 2413.540000 ;
+ RECT 1702.820000 2407.620000 1703.920000 2408.100000 ;
+ RECT 1702.820000 2402.180000 1703.920000 2402.660000 ;
+ RECT 1702.820000 2418.500000 1703.920000 2418.980000 ;
+ RECT 1657.820000 2445.700000 1658.920000 2446.180000 ;
+ RECT 1653.690000 2445.700000 1654.690000 2446.180000 ;
+ RECT 1657.820000 2440.260000 1658.920000 2440.740000 ;
+ RECT 1653.690000 2440.260000 1654.690000 2440.740000 ;
+ RECT 1657.820000 2434.820000 1658.920000 2435.300000 ;
+ RECT 1653.690000 2434.820000 1654.690000 2435.300000 ;
+ RECT 1657.820000 2423.940000 1658.920000 2424.420000 ;
+ RECT 1653.690000 2423.940000 1654.690000 2424.420000 ;
+ RECT 1653.690000 2429.380000 1654.690000 2429.860000 ;
+ RECT 1657.820000 2429.380000 1658.920000 2429.860000 ;
+ RECT 1657.820000 2418.500000 1658.920000 2418.980000 ;
+ RECT 1653.690000 2418.500000 1654.690000 2418.980000 ;
+ RECT 1657.820000 2413.060000 1658.920000 2413.540000 ;
+ RECT 1653.690000 2413.060000 1654.690000 2413.540000 ;
+ RECT 1657.820000 2407.620000 1658.920000 2408.100000 ;
+ RECT 1653.690000 2407.620000 1654.690000 2408.100000 ;
+ RECT 1657.820000 2402.180000 1658.920000 2402.660000 ;
+ RECT 1653.690000 2402.180000 1654.690000 2402.660000 ;
+ RECT 1747.820000 2396.740000 1748.920000 2397.220000 ;
+ RECT 1747.820000 2391.300000 1748.920000 2391.780000 ;
+ RECT 1747.820000 2385.860000 1748.920000 2386.340000 ;
+ RECT 1747.820000 2380.420000 1748.920000 2380.900000 ;
+ RECT 1747.820000 2374.980000 1748.920000 2375.460000 ;
+ RECT 1702.820000 2396.740000 1703.920000 2397.220000 ;
+ RECT 1702.820000 2391.300000 1703.920000 2391.780000 ;
+ RECT 1702.820000 2385.860000 1703.920000 2386.340000 ;
+ RECT 1702.820000 2380.420000 1703.920000 2380.900000 ;
+ RECT 1702.820000 2374.980000 1703.920000 2375.460000 ;
+ RECT 1747.820000 2353.220000 1748.920000 2353.700000 ;
+ RECT 1747.820000 2358.660000 1748.920000 2359.140000 ;
+ RECT 1747.820000 2364.100000 1748.920000 2364.580000 ;
+ RECT 1747.820000 2369.540000 1748.920000 2370.020000 ;
+ RECT 1702.820000 2353.220000 1703.920000 2353.700000 ;
+ RECT 1702.820000 2358.660000 1703.920000 2359.140000 ;
+ RECT 1702.820000 2364.100000 1703.920000 2364.580000 ;
+ RECT 1702.820000 2369.540000 1703.920000 2370.020000 ;
+ RECT 1657.820000 2396.740000 1658.920000 2397.220000 ;
+ RECT 1653.690000 2396.740000 1654.690000 2397.220000 ;
+ RECT 1657.820000 2391.300000 1658.920000 2391.780000 ;
+ RECT 1653.690000 2391.300000 1654.690000 2391.780000 ;
+ RECT 1657.820000 2380.420000 1658.920000 2380.900000 ;
+ RECT 1653.690000 2380.420000 1654.690000 2380.900000 ;
+ RECT 1657.820000 2374.980000 1658.920000 2375.460000 ;
+ RECT 1653.690000 2374.980000 1654.690000 2375.460000 ;
+ RECT 1657.820000 2385.860000 1658.920000 2386.340000 ;
+ RECT 1653.690000 2385.860000 1654.690000 2386.340000 ;
+ RECT 1657.820000 2369.540000 1658.920000 2370.020000 ;
+ RECT 1653.690000 2369.540000 1654.690000 2370.020000 ;
+ RECT 1657.820000 2364.100000 1658.920000 2364.580000 ;
+ RECT 1653.690000 2364.100000 1654.690000 2364.580000 ;
+ RECT 1657.820000 2358.660000 1658.920000 2359.140000 ;
+ RECT 1657.820000 2353.220000 1658.920000 2353.700000 ;
+ RECT 1653.690000 2358.660000 1654.690000 2359.140000 ;
+ RECT 1653.690000 2353.220000 1654.690000 2353.700000 ;
+ RECT 1650.860000 2543.580000 1850.960000 2544.580000 ;
+ RECT 1650.860000 2351.210000 1850.960000 2352.210000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 2348.360000 1654.690000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 2547.620000 1654.690000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 2348.360000 1848.130000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 2547.620000 1848.130000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2351.210000 1651.860000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2351.210000 1850.960000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2543.580000 1651.860000 2544.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2543.580000 1850.960000 2544.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 2150.950000 1838.920000 2344.320000 ;
+ RECT 1792.820000 2150.950000 1793.920000 2344.320000 ;
+ RECT 1847.130000 2148.100000 1848.130000 2348.360000 ;
+ RECT 1747.820000 2150.950000 1748.920000 2344.320000 ;
+ RECT 1702.820000 2150.950000 1703.920000 2344.320000 ;
+ RECT 1657.820000 2150.950000 1658.920000 2344.320000 ;
+ RECT 1653.690000 2148.100000 1654.690000 2348.360000 ;
+ LAYER met3 ;
+ RECT 1837.820000 2337.920000 1838.920000 2338.400000 ;
+ RECT 1847.130000 2337.920000 1848.130000 2338.400000 ;
+ RECT 1847.130000 2327.040000 1848.130000 2327.520000 ;
+ RECT 1847.130000 2332.480000 1848.130000 2332.960000 ;
+ RECT 1837.820000 2332.480000 1838.920000 2332.960000 ;
+ RECT 1837.820000 2327.040000 1838.920000 2327.520000 ;
+ RECT 1837.820000 2321.600000 1838.920000 2322.080000 ;
+ RECT 1837.820000 2316.160000 1838.920000 2316.640000 ;
+ RECT 1847.130000 2321.600000 1848.130000 2322.080000 ;
+ RECT 1847.130000 2316.160000 1848.130000 2316.640000 ;
+ RECT 1837.820000 2299.840000 1838.920000 2300.320000 ;
+ RECT 1837.820000 2305.280000 1838.920000 2305.760000 ;
+ RECT 1847.130000 2305.280000 1848.130000 2305.760000 ;
+ RECT 1847.130000 2299.840000 1848.130000 2300.320000 ;
+ RECT 1837.820000 2310.720000 1838.920000 2311.200000 ;
+ RECT 1847.130000 2310.720000 1848.130000 2311.200000 ;
+ RECT 1792.820000 2337.920000 1793.920000 2338.400000 ;
+ RECT 1792.820000 2332.480000 1793.920000 2332.960000 ;
+ RECT 1792.820000 2327.040000 1793.920000 2327.520000 ;
+ RECT 1792.820000 2321.600000 1793.920000 2322.080000 ;
+ RECT 1792.820000 2299.840000 1793.920000 2300.320000 ;
+ RECT 1792.820000 2305.280000 1793.920000 2305.760000 ;
+ RECT 1792.820000 2310.720000 1793.920000 2311.200000 ;
+ RECT 1792.820000 2316.160000 1793.920000 2316.640000 ;
+ RECT 1847.130000 2288.960000 1848.130000 2289.440000 ;
+ RECT 1847.130000 2294.400000 1848.130000 2294.880000 ;
+ RECT 1837.820000 2294.400000 1838.920000 2294.880000 ;
+ RECT 1837.820000 2288.960000 1838.920000 2289.440000 ;
+ RECT 1837.820000 2283.520000 1838.920000 2284.000000 ;
+ RECT 1837.820000 2278.080000 1838.920000 2278.560000 ;
+ RECT 1847.130000 2283.520000 1848.130000 2284.000000 ;
+ RECT 1847.130000 2278.080000 1848.130000 2278.560000 ;
+ RECT 1847.130000 2261.760000 1848.130000 2262.240000 ;
+ RECT 1847.130000 2267.200000 1848.130000 2267.680000 ;
+ RECT 1847.130000 2272.640000 1848.130000 2273.120000 ;
+ RECT 1837.820000 2267.200000 1838.920000 2267.680000 ;
+ RECT 1837.820000 2261.760000 1838.920000 2262.240000 ;
+ RECT 1837.820000 2272.640000 1838.920000 2273.120000 ;
+ RECT 1837.820000 2256.320000 1838.920000 2256.800000 ;
+ RECT 1837.820000 2250.880000 1838.920000 2251.360000 ;
+ RECT 1847.130000 2256.320000 1848.130000 2256.800000 ;
+ RECT 1847.130000 2250.880000 1848.130000 2251.360000 ;
+ RECT 1792.820000 2294.400000 1793.920000 2294.880000 ;
+ RECT 1792.820000 2288.960000 1793.920000 2289.440000 ;
+ RECT 1792.820000 2283.520000 1793.920000 2284.000000 ;
+ RECT 1792.820000 2278.080000 1793.920000 2278.560000 ;
+ RECT 1792.820000 2267.200000 1793.920000 2267.680000 ;
+ RECT 1792.820000 2261.760000 1793.920000 2262.240000 ;
+ RECT 1792.820000 2256.320000 1793.920000 2256.800000 ;
+ RECT 1792.820000 2250.880000 1793.920000 2251.360000 ;
+ RECT 1792.820000 2272.640000 1793.920000 2273.120000 ;
+ RECT 1747.820000 2337.920000 1748.920000 2338.400000 ;
+ RECT 1747.820000 2332.480000 1748.920000 2332.960000 ;
+ RECT 1747.820000 2327.040000 1748.920000 2327.520000 ;
+ RECT 1702.820000 2337.920000 1703.920000 2338.400000 ;
+ RECT 1702.820000 2332.480000 1703.920000 2332.960000 ;
+ RECT 1702.820000 2327.040000 1703.920000 2327.520000 ;
+ RECT 1747.820000 2310.720000 1748.920000 2311.200000 ;
+ RECT 1747.820000 2305.280000 1748.920000 2305.760000 ;
+ RECT 1747.820000 2299.840000 1748.920000 2300.320000 ;
+ RECT 1747.820000 2316.160000 1748.920000 2316.640000 ;
+ RECT 1747.820000 2321.600000 1748.920000 2322.080000 ;
+ RECT 1702.820000 2321.600000 1703.920000 2322.080000 ;
+ RECT 1702.820000 2310.720000 1703.920000 2311.200000 ;
+ RECT 1702.820000 2305.280000 1703.920000 2305.760000 ;
+ RECT 1702.820000 2299.840000 1703.920000 2300.320000 ;
+ RECT 1702.820000 2316.160000 1703.920000 2316.640000 ;
+ RECT 1657.820000 2337.920000 1658.920000 2338.400000 ;
+ RECT 1653.690000 2337.920000 1654.690000 2338.400000 ;
+ RECT 1653.690000 2332.480000 1654.690000 2332.960000 ;
+ RECT 1657.820000 2332.480000 1658.920000 2332.960000 ;
+ RECT 1657.820000 2327.040000 1658.920000 2327.520000 ;
+ RECT 1653.690000 2327.040000 1654.690000 2327.520000 ;
+ RECT 1657.820000 2321.600000 1658.920000 2322.080000 ;
+ RECT 1653.690000 2321.600000 1654.690000 2322.080000 ;
+ RECT 1657.820000 2316.160000 1658.920000 2316.640000 ;
+ RECT 1653.690000 2316.160000 1654.690000 2316.640000 ;
+ RECT 1657.820000 2305.280000 1658.920000 2305.760000 ;
+ RECT 1653.690000 2305.280000 1654.690000 2305.760000 ;
+ RECT 1657.820000 2299.840000 1658.920000 2300.320000 ;
+ RECT 1653.690000 2299.840000 1654.690000 2300.320000 ;
+ RECT 1657.820000 2310.720000 1658.920000 2311.200000 ;
+ RECT 1653.690000 2310.720000 1654.690000 2311.200000 ;
+ RECT 1747.820000 2294.400000 1748.920000 2294.880000 ;
+ RECT 1747.820000 2288.960000 1748.920000 2289.440000 ;
+ RECT 1747.820000 2283.520000 1748.920000 2284.000000 ;
+ RECT 1747.820000 2278.080000 1748.920000 2278.560000 ;
+ RECT 1702.820000 2294.400000 1703.920000 2294.880000 ;
+ RECT 1702.820000 2288.960000 1703.920000 2289.440000 ;
+ RECT 1702.820000 2283.520000 1703.920000 2284.000000 ;
+ RECT 1702.820000 2278.080000 1703.920000 2278.560000 ;
+ RECT 1747.820000 2267.200000 1748.920000 2267.680000 ;
+ RECT 1747.820000 2250.880000 1748.920000 2251.360000 ;
+ RECT 1747.820000 2256.320000 1748.920000 2256.800000 ;
+ RECT 1747.820000 2261.760000 1748.920000 2262.240000 ;
+ RECT 1747.820000 2272.640000 1748.920000 2273.120000 ;
+ RECT 1702.820000 2250.880000 1703.920000 2251.360000 ;
+ RECT 1702.820000 2256.320000 1703.920000 2256.800000 ;
+ RECT 1702.820000 2261.760000 1703.920000 2262.240000 ;
+ RECT 1702.820000 2267.200000 1703.920000 2267.680000 ;
+ RECT 1702.820000 2272.640000 1703.920000 2273.120000 ;
+ RECT 1657.820000 2294.400000 1658.920000 2294.880000 ;
+ RECT 1653.690000 2294.400000 1654.690000 2294.880000 ;
+ RECT 1657.820000 2288.960000 1658.920000 2289.440000 ;
+ RECT 1653.690000 2288.960000 1654.690000 2289.440000 ;
+ RECT 1657.820000 2283.520000 1658.920000 2284.000000 ;
+ RECT 1653.690000 2283.520000 1654.690000 2284.000000 ;
+ RECT 1657.820000 2278.080000 1658.920000 2278.560000 ;
+ RECT 1653.690000 2278.080000 1654.690000 2278.560000 ;
+ RECT 1657.820000 2272.640000 1658.920000 2273.120000 ;
+ RECT 1657.820000 2267.200000 1658.920000 2267.680000 ;
+ RECT 1653.690000 2272.640000 1654.690000 2273.120000 ;
+ RECT 1653.690000 2267.200000 1654.690000 2267.680000 ;
+ RECT 1657.820000 2261.760000 1658.920000 2262.240000 ;
+ RECT 1653.690000 2261.760000 1654.690000 2262.240000 ;
+ RECT 1657.820000 2256.320000 1658.920000 2256.800000 ;
+ RECT 1653.690000 2256.320000 1654.690000 2256.800000 ;
+ RECT 1657.820000 2250.880000 1658.920000 2251.360000 ;
+ RECT 1653.690000 2250.880000 1654.690000 2251.360000 ;
+ RECT 1837.820000 2245.440000 1838.920000 2245.920000 ;
+ RECT 1837.820000 2240.000000 1838.920000 2240.480000 ;
+ RECT 1847.130000 2245.440000 1848.130000 2245.920000 ;
+ RECT 1847.130000 2240.000000 1848.130000 2240.480000 ;
+ RECT 1847.130000 2223.680000 1848.130000 2224.160000 ;
+ RECT 1847.130000 2229.120000 1848.130000 2229.600000 ;
+ RECT 1847.130000 2234.560000 1848.130000 2235.040000 ;
+ RECT 1837.820000 2234.560000 1838.920000 2235.040000 ;
+ RECT 1837.820000 2229.120000 1838.920000 2229.600000 ;
+ RECT 1837.820000 2223.680000 1838.920000 2224.160000 ;
+ RECT 1837.820000 2212.800000 1838.920000 2213.280000 ;
+ RECT 1837.820000 2218.240000 1838.920000 2218.720000 ;
+ RECT 1847.130000 2218.240000 1848.130000 2218.720000 ;
+ RECT 1847.130000 2212.800000 1848.130000 2213.280000 ;
+ RECT 1847.130000 2201.920000 1848.130000 2202.400000 ;
+ RECT 1847.130000 2207.360000 1848.130000 2207.840000 ;
+ RECT 1837.820000 2201.920000 1838.920000 2202.400000 ;
+ RECT 1837.820000 2207.360000 1838.920000 2207.840000 ;
+ RECT 1792.820000 2245.440000 1793.920000 2245.920000 ;
+ RECT 1792.820000 2240.000000 1793.920000 2240.480000 ;
+ RECT 1792.820000 2234.560000 1793.920000 2235.040000 ;
+ RECT 1792.820000 2229.120000 1793.920000 2229.600000 ;
+ RECT 1792.820000 2223.680000 1793.920000 2224.160000 ;
+ RECT 1792.820000 2201.920000 1793.920000 2202.400000 ;
+ RECT 1792.820000 2207.360000 1793.920000 2207.840000 ;
+ RECT 1792.820000 2212.800000 1793.920000 2213.280000 ;
+ RECT 1792.820000 2218.240000 1793.920000 2218.720000 ;
+ RECT 1837.820000 2196.480000 1838.920000 2196.960000 ;
+ RECT 1837.820000 2191.040000 1838.920000 2191.520000 ;
+ RECT 1847.130000 2196.480000 1848.130000 2196.960000 ;
+ RECT 1847.130000 2191.040000 1848.130000 2191.520000 ;
+ RECT 1837.820000 2180.160000 1838.920000 2180.640000 ;
+ RECT 1837.820000 2174.720000 1838.920000 2175.200000 ;
+ RECT 1847.130000 2180.160000 1848.130000 2180.640000 ;
+ RECT 1847.130000 2174.720000 1848.130000 2175.200000 ;
+ RECT 1837.820000 2185.600000 1838.920000 2186.080000 ;
+ RECT 1847.130000 2185.600000 1848.130000 2186.080000 ;
+ RECT 1847.130000 2163.840000 1848.130000 2164.320000 ;
+ RECT 1847.130000 2169.280000 1848.130000 2169.760000 ;
+ RECT 1837.820000 2169.280000 1838.920000 2169.760000 ;
+ RECT 1837.820000 2163.840000 1838.920000 2164.320000 ;
+ RECT 1837.820000 2158.400000 1838.920000 2158.880000 ;
+ RECT 1837.820000 2152.960000 1838.920000 2153.440000 ;
+ RECT 1847.130000 2158.400000 1848.130000 2158.880000 ;
+ RECT 1847.130000 2152.960000 1848.130000 2153.440000 ;
+ RECT 1792.820000 2196.480000 1793.920000 2196.960000 ;
+ RECT 1792.820000 2191.040000 1793.920000 2191.520000 ;
+ RECT 1792.820000 2185.600000 1793.920000 2186.080000 ;
+ RECT 1792.820000 2180.160000 1793.920000 2180.640000 ;
+ RECT 1792.820000 2174.720000 1793.920000 2175.200000 ;
+ RECT 1792.820000 2169.280000 1793.920000 2169.760000 ;
+ RECT 1792.820000 2163.840000 1793.920000 2164.320000 ;
+ RECT 1792.820000 2158.400000 1793.920000 2158.880000 ;
+ RECT 1792.820000 2152.960000 1793.920000 2153.440000 ;
+ RECT 1747.820000 2245.440000 1748.920000 2245.920000 ;
+ RECT 1747.820000 2240.000000 1748.920000 2240.480000 ;
+ RECT 1747.820000 2234.560000 1748.920000 2235.040000 ;
+ RECT 1747.820000 2229.120000 1748.920000 2229.600000 ;
+ RECT 1747.820000 2223.680000 1748.920000 2224.160000 ;
+ RECT 1702.820000 2245.440000 1703.920000 2245.920000 ;
+ RECT 1702.820000 2240.000000 1703.920000 2240.480000 ;
+ RECT 1702.820000 2234.560000 1703.920000 2235.040000 ;
+ RECT 1702.820000 2229.120000 1703.920000 2229.600000 ;
+ RECT 1702.820000 2223.680000 1703.920000 2224.160000 ;
+ RECT 1747.820000 2218.240000 1748.920000 2218.720000 ;
+ RECT 1747.820000 2212.800000 1748.920000 2213.280000 ;
+ RECT 1747.820000 2207.360000 1748.920000 2207.840000 ;
+ RECT 1747.820000 2201.920000 1748.920000 2202.400000 ;
+ RECT 1702.820000 2212.800000 1703.920000 2213.280000 ;
+ RECT 1702.820000 2207.360000 1703.920000 2207.840000 ;
+ RECT 1702.820000 2201.920000 1703.920000 2202.400000 ;
+ RECT 1702.820000 2218.240000 1703.920000 2218.720000 ;
+ RECT 1657.820000 2245.440000 1658.920000 2245.920000 ;
+ RECT 1653.690000 2245.440000 1654.690000 2245.920000 ;
+ RECT 1657.820000 2240.000000 1658.920000 2240.480000 ;
+ RECT 1653.690000 2240.000000 1654.690000 2240.480000 ;
+ RECT 1657.820000 2234.560000 1658.920000 2235.040000 ;
+ RECT 1653.690000 2234.560000 1654.690000 2235.040000 ;
+ RECT 1657.820000 2223.680000 1658.920000 2224.160000 ;
+ RECT 1653.690000 2223.680000 1654.690000 2224.160000 ;
+ RECT 1653.690000 2229.120000 1654.690000 2229.600000 ;
+ RECT 1657.820000 2229.120000 1658.920000 2229.600000 ;
+ RECT 1657.820000 2218.240000 1658.920000 2218.720000 ;
+ RECT 1653.690000 2218.240000 1654.690000 2218.720000 ;
+ RECT 1657.820000 2212.800000 1658.920000 2213.280000 ;
+ RECT 1653.690000 2212.800000 1654.690000 2213.280000 ;
+ RECT 1657.820000 2207.360000 1658.920000 2207.840000 ;
+ RECT 1653.690000 2207.360000 1654.690000 2207.840000 ;
+ RECT 1657.820000 2201.920000 1658.920000 2202.400000 ;
+ RECT 1653.690000 2201.920000 1654.690000 2202.400000 ;
+ RECT 1747.820000 2196.480000 1748.920000 2196.960000 ;
+ RECT 1747.820000 2191.040000 1748.920000 2191.520000 ;
+ RECT 1747.820000 2185.600000 1748.920000 2186.080000 ;
+ RECT 1747.820000 2180.160000 1748.920000 2180.640000 ;
+ RECT 1747.820000 2174.720000 1748.920000 2175.200000 ;
+ RECT 1702.820000 2196.480000 1703.920000 2196.960000 ;
+ RECT 1702.820000 2191.040000 1703.920000 2191.520000 ;
+ RECT 1702.820000 2185.600000 1703.920000 2186.080000 ;
+ RECT 1702.820000 2180.160000 1703.920000 2180.640000 ;
+ RECT 1702.820000 2174.720000 1703.920000 2175.200000 ;
+ RECT 1747.820000 2152.960000 1748.920000 2153.440000 ;
+ RECT 1747.820000 2158.400000 1748.920000 2158.880000 ;
+ RECT 1747.820000 2163.840000 1748.920000 2164.320000 ;
+ RECT 1747.820000 2169.280000 1748.920000 2169.760000 ;
+ RECT 1702.820000 2152.960000 1703.920000 2153.440000 ;
+ RECT 1702.820000 2158.400000 1703.920000 2158.880000 ;
+ RECT 1702.820000 2163.840000 1703.920000 2164.320000 ;
+ RECT 1702.820000 2169.280000 1703.920000 2169.760000 ;
+ RECT 1657.820000 2196.480000 1658.920000 2196.960000 ;
+ RECT 1653.690000 2196.480000 1654.690000 2196.960000 ;
+ RECT 1657.820000 2191.040000 1658.920000 2191.520000 ;
+ RECT 1653.690000 2191.040000 1654.690000 2191.520000 ;
+ RECT 1657.820000 2180.160000 1658.920000 2180.640000 ;
+ RECT 1653.690000 2180.160000 1654.690000 2180.640000 ;
+ RECT 1657.820000 2174.720000 1658.920000 2175.200000 ;
+ RECT 1653.690000 2174.720000 1654.690000 2175.200000 ;
+ RECT 1657.820000 2185.600000 1658.920000 2186.080000 ;
+ RECT 1653.690000 2185.600000 1654.690000 2186.080000 ;
+ RECT 1657.820000 2169.280000 1658.920000 2169.760000 ;
+ RECT 1653.690000 2169.280000 1654.690000 2169.760000 ;
+ RECT 1657.820000 2163.840000 1658.920000 2164.320000 ;
+ RECT 1653.690000 2163.840000 1654.690000 2164.320000 ;
+ RECT 1657.820000 2158.400000 1658.920000 2158.880000 ;
+ RECT 1657.820000 2152.960000 1658.920000 2153.440000 ;
+ RECT 1653.690000 2158.400000 1654.690000 2158.880000 ;
+ RECT 1653.690000 2152.960000 1654.690000 2153.440000 ;
+ RECT 1650.860000 2343.320000 1850.960000 2344.320000 ;
+ RECT 1650.860000 2150.950000 1850.960000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 2148.100000 1654.690000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 2347.360000 1654.690000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 2148.100000 1848.130000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 2347.360000 1848.130000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2150.950000 1651.860000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2150.950000 1850.960000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2343.320000 1651.860000 2344.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2343.320000 1850.960000 2344.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 1950.690000 1838.920000 2144.060000 ;
+ RECT 1792.820000 1950.690000 1793.920000 2144.060000 ;
+ RECT 1847.130000 1947.840000 1848.130000 2148.100000 ;
+ RECT 1747.820000 1950.690000 1748.920000 2144.060000 ;
+ RECT 1702.820000 1950.690000 1703.920000 2144.060000 ;
+ RECT 1657.820000 1950.690000 1658.920000 2144.060000 ;
+ RECT 1653.690000 1947.840000 1654.690000 2148.100000 ;
+ LAYER met3 ;
+ RECT 1837.820000 2137.660000 1838.920000 2138.140000 ;
+ RECT 1847.130000 2137.660000 1848.130000 2138.140000 ;
+ RECT 1847.130000 2126.780000 1848.130000 2127.260000 ;
+ RECT 1847.130000 2132.220000 1848.130000 2132.700000 ;
+ RECT 1837.820000 2132.220000 1838.920000 2132.700000 ;
+ RECT 1837.820000 2126.780000 1838.920000 2127.260000 ;
+ RECT 1837.820000 2121.340000 1838.920000 2121.820000 ;
+ RECT 1837.820000 2115.900000 1838.920000 2116.380000 ;
+ RECT 1847.130000 2121.340000 1848.130000 2121.820000 ;
+ RECT 1847.130000 2115.900000 1848.130000 2116.380000 ;
+ RECT 1837.820000 2099.580000 1838.920000 2100.060000 ;
+ RECT 1837.820000 2105.020000 1838.920000 2105.500000 ;
+ RECT 1847.130000 2105.020000 1848.130000 2105.500000 ;
+ RECT 1847.130000 2099.580000 1848.130000 2100.060000 ;
+ RECT 1837.820000 2110.460000 1838.920000 2110.940000 ;
+ RECT 1847.130000 2110.460000 1848.130000 2110.940000 ;
+ RECT 1792.820000 2137.660000 1793.920000 2138.140000 ;
+ RECT 1792.820000 2132.220000 1793.920000 2132.700000 ;
+ RECT 1792.820000 2126.780000 1793.920000 2127.260000 ;
+ RECT 1792.820000 2121.340000 1793.920000 2121.820000 ;
+ RECT 1792.820000 2099.580000 1793.920000 2100.060000 ;
+ RECT 1792.820000 2105.020000 1793.920000 2105.500000 ;
+ RECT 1792.820000 2110.460000 1793.920000 2110.940000 ;
+ RECT 1792.820000 2115.900000 1793.920000 2116.380000 ;
+ RECT 1847.130000 2088.700000 1848.130000 2089.180000 ;
+ RECT 1847.130000 2094.140000 1848.130000 2094.620000 ;
+ RECT 1837.820000 2094.140000 1838.920000 2094.620000 ;
+ RECT 1837.820000 2088.700000 1838.920000 2089.180000 ;
+ RECT 1837.820000 2083.260000 1838.920000 2083.740000 ;
+ RECT 1837.820000 2077.820000 1838.920000 2078.300000 ;
+ RECT 1847.130000 2083.260000 1848.130000 2083.740000 ;
+ RECT 1847.130000 2077.820000 1848.130000 2078.300000 ;
+ RECT 1847.130000 2061.500000 1848.130000 2061.980000 ;
+ RECT 1847.130000 2066.940000 1848.130000 2067.420000 ;
+ RECT 1847.130000 2072.380000 1848.130000 2072.860000 ;
+ RECT 1837.820000 2066.940000 1838.920000 2067.420000 ;
+ RECT 1837.820000 2061.500000 1838.920000 2061.980000 ;
+ RECT 1837.820000 2072.380000 1838.920000 2072.860000 ;
+ RECT 1837.820000 2056.060000 1838.920000 2056.540000 ;
+ RECT 1837.820000 2050.620000 1838.920000 2051.100000 ;
+ RECT 1847.130000 2056.060000 1848.130000 2056.540000 ;
+ RECT 1847.130000 2050.620000 1848.130000 2051.100000 ;
+ RECT 1792.820000 2094.140000 1793.920000 2094.620000 ;
+ RECT 1792.820000 2088.700000 1793.920000 2089.180000 ;
+ RECT 1792.820000 2083.260000 1793.920000 2083.740000 ;
+ RECT 1792.820000 2077.820000 1793.920000 2078.300000 ;
+ RECT 1792.820000 2066.940000 1793.920000 2067.420000 ;
+ RECT 1792.820000 2061.500000 1793.920000 2061.980000 ;
+ RECT 1792.820000 2056.060000 1793.920000 2056.540000 ;
+ RECT 1792.820000 2050.620000 1793.920000 2051.100000 ;
+ RECT 1792.820000 2072.380000 1793.920000 2072.860000 ;
+ RECT 1747.820000 2137.660000 1748.920000 2138.140000 ;
+ RECT 1747.820000 2132.220000 1748.920000 2132.700000 ;
+ RECT 1747.820000 2126.780000 1748.920000 2127.260000 ;
+ RECT 1702.820000 2137.660000 1703.920000 2138.140000 ;
+ RECT 1702.820000 2132.220000 1703.920000 2132.700000 ;
+ RECT 1702.820000 2126.780000 1703.920000 2127.260000 ;
+ RECT 1747.820000 2110.460000 1748.920000 2110.940000 ;
+ RECT 1747.820000 2105.020000 1748.920000 2105.500000 ;
+ RECT 1747.820000 2099.580000 1748.920000 2100.060000 ;
+ RECT 1747.820000 2115.900000 1748.920000 2116.380000 ;
+ RECT 1747.820000 2121.340000 1748.920000 2121.820000 ;
+ RECT 1702.820000 2121.340000 1703.920000 2121.820000 ;
+ RECT 1702.820000 2110.460000 1703.920000 2110.940000 ;
+ RECT 1702.820000 2105.020000 1703.920000 2105.500000 ;
+ RECT 1702.820000 2099.580000 1703.920000 2100.060000 ;
+ RECT 1702.820000 2115.900000 1703.920000 2116.380000 ;
+ RECT 1657.820000 2137.660000 1658.920000 2138.140000 ;
+ RECT 1653.690000 2137.660000 1654.690000 2138.140000 ;
+ RECT 1653.690000 2132.220000 1654.690000 2132.700000 ;
+ RECT 1657.820000 2132.220000 1658.920000 2132.700000 ;
+ RECT 1657.820000 2126.780000 1658.920000 2127.260000 ;
+ RECT 1653.690000 2126.780000 1654.690000 2127.260000 ;
+ RECT 1657.820000 2121.340000 1658.920000 2121.820000 ;
+ RECT 1653.690000 2121.340000 1654.690000 2121.820000 ;
+ RECT 1657.820000 2115.900000 1658.920000 2116.380000 ;
+ RECT 1653.690000 2115.900000 1654.690000 2116.380000 ;
+ RECT 1657.820000 2105.020000 1658.920000 2105.500000 ;
+ RECT 1653.690000 2105.020000 1654.690000 2105.500000 ;
+ RECT 1657.820000 2099.580000 1658.920000 2100.060000 ;
+ RECT 1653.690000 2099.580000 1654.690000 2100.060000 ;
+ RECT 1657.820000 2110.460000 1658.920000 2110.940000 ;
+ RECT 1653.690000 2110.460000 1654.690000 2110.940000 ;
+ RECT 1747.820000 2094.140000 1748.920000 2094.620000 ;
+ RECT 1747.820000 2088.700000 1748.920000 2089.180000 ;
+ RECT 1747.820000 2083.260000 1748.920000 2083.740000 ;
+ RECT 1747.820000 2077.820000 1748.920000 2078.300000 ;
+ RECT 1702.820000 2094.140000 1703.920000 2094.620000 ;
+ RECT 1702.820000 2088.700000 1703.920000 2089.180000 ;
+ RECT 1702.820000 2083.260000 1703.920000 2083.740000 ;
+ RECT 1702.820000 2077.820000 1703.920000 2078.300000 ;
+ RECT 1747.820000 2066.940000 1748.920000 2067.420000 ;
+ RECT 1747.820000 2050.620000 1748.920000 2051.100000 ;
+ RECT 1747.820000 2056.060000 1748.920000 2056.540000 ;
+ RECT 1747.820000 2061.500000 1748.920000 2061.980000 ;
+ RECT 1747.820000 2072.380000 1748.920000 2072.860000 ;
+ RECT 1702.820000 2050.620000 1703.920000 2051.100000 ;
+ RECT 1702.820000 2056.060000 1703.920000 2056.540000 ;
+ RECT 1702.820000 2061.500000 1703.920000 2061.980000 ;
+ RECT 1702.820000 2066.940000 1703.920000 2067.420000 ;
+ RECT 1702.820000 2072.380000 1703.920000 2072.860000 ;
+ RECT 1657.820000 2094.140000 1658.920000 2094.620000 ;
+ RECT 1653.690000 2094.140000 1654.690000 2094.620000 ;
+ RECT 1657.820000 2088.700000 1658.920000 2089.180000 ;
+ RECT 1653.690000 2088.700000 1654.690000 2089.180000 ;
+ RECT 1657.820000 2083.260000 1658.920000 2083.740000 ;
+ RECT 1653.690000 2083.260000 1654.690000 2083.740000 ;
+ RECT 1657.820000 2077.820000 1658.920000 2078.300000 ;
+ RECT 1653.690000 2077.820000 1654.690000 2078.300000 ;
+ RECT 1657.820000 2072.380000 1658.920000 2072.860000 ;
+ RECT 1657.820000 2066.940000 1658.920000 2067.420000 ;
+ RECT 1653.690000 2072.380000 1654.690000 2072.860000 ;
+ RECT 1653.690000 2066.940000 1654.690000 2067.420000 ;
+ RECT 1657.820000 2061.500000 1658.920000 2061.980000 ;
+ RECT 1653.690000 2061.500000 1654.690000 2061.980000 ;
+ RECT 1657.820000 2056.060000 1658.920000 2056.540000 ;
+ RECT 1653.690000 2056.060000 1654.690000 2056.540000 ;
+ RECT 1657.820000 2050.620000 1658.920000 2051.100000 ;
+ RECT 1653.690000 2050.620000 1654.690000 2051.100000 ;
+ RECT 1837.820000 2045.180000 1838.920000 2045.660000 ;
+ RECT 1837.820000 2039.740000 1838.920000 2040.220000 ;
+ RECT 1847.130000 2045.180000 1848.130000 2045.660000 ;
+ RECT 1847.130000 2039.740000 1848.130000 2040.220000 ;
+ RECT 1847.130000 2023.420000 1848.130000 2023.900000 ;
+ RECT 1847.130000 2028.860000 1848.130000 2029.340000 ;
+ RECT 1847.130000 2034.300000 1848.130000 2034.780000 ;
+ RECT 1837.820000 2034.300000 1838.920000 2034.780000 ;
+ RECT 1837.820000 2028.860000 1838.920000 2029.340000 ;
+ RECT 1837.820000 2023.420000 1838.920000 2023.900000 ;
+ RECT 1837.820000 2012.540000 1838.920000 2013.020000 ;
+ RECT 1837.820000 2017.980000 1838.920000 2018.460000 ;
+ RECT 1847.130000 2017.980000 1848.130000 2018.460000 ;
+ RECT 1847.130000 2012.540000 1848.130000 2013.020000 ;
+ RECT 1847.130000 2001.660000 1848.130000 2002.140000 ;
+ RECT 1847.130000 2007.100000 1848.130000 2007.580000 ;
+ RECT 1837.820000 2001.660000 1838.920000 2002.140000 ;
+ RECT 1837.820000 2007.100000 1838.920000 2007.580000 ;
+ RECT 1792.820000 2045.180000 1793.920000 2045.660000 ;
+ RECT 1792.820000 2039.740000 1793.920000 2040.220000 ;
+ RECT 1792.820000 2034.300000 1793.920000 2034.780000 ;
+ RECT 1792.820000 2028.860000 1793.920000 2029.340000 ;
+ RECT 1792.820000 2023.420000 1793.920000 2023.900000 ;
+ RECT 1792.820000 2001.660000 1793.920000 2002.140000 ;
+ RECT 1792.820000 2007.100000 1793.920000 2007.580000 ;
+ RECT 1792.820000 2012.540000 1793.920000 2013.020000 ;
+ RECT 1792.820000 2017.980000 1793.920000 2018.460000 ;
+ RECT 1837.820000 1996.220000 1838.920000 1996.700000 ;
+ RECT 1837.820000 1990.780000 1838.920000 1991.260000 ;
+ RECT 1847.130000 1996.220000 1848.130000 1996.700000 ;
+ RECT 1847.130000 1990.780000 1848.130000 1991.260000 ;
+ RECT 1837.820000 1979.900000 1838.920000 1980.380000 ;
+ RECT 1837.820000 1974.460000 1838.920000 1974.940000 ;
+ RECT 1847.130000 1979.900000 1848.130000 1980.380000 ;
+ RECT 1847.130000 1974.460000 1848.130000 1974.940000 ;
+ RECT 1837.820000 1985.340000 1838.920000 1985.820000 ;
+ RECT 1847.130000 1985.340000 1848.130000 1985.820000 ;
+ RECT 1847.130000 1963.580000 1848.130000 1964.060000 ;
+ RECT 1847.130000 1969.020000 1848.130000 1969.500000 ;
+ RECT 1837.820000 1969.020000 1838.920000 1969.500000 ;
+ RECT 1837.820000 1963.580000 1838.920000 1964.060000 ;
+ RECT 1837.820000 1958.140000 1838.920000 1958.620000 ;
+ RECT 1837.820000 1952.700000 1838.920000 1953.180000 ;
+ RECT 1847.130000 1958.140000 1848.130000 1958.620000 ;
+ RECT 1847.130000 1952.700000 1848.130000 1953.180000 ;
+ RECT 1792.820000 1996.220000 1793.920000 1996.700000 ;
+ RECT 1792.820000 1990.780000 1793.920000 1991.260000 ;
+ RECT 1792.820000 1985.340000 1793.920000 1985.820000 ;
+ RECT 1792.820000 1979.900000 1793.920000 1980.380000 ;
+ RECT 1792.820000 1974.460000 1793.920000 1974.940000 ;
+ RECT 1792.820000 1969.020000 1793.920000 1969.500000 ;
+ RECT 1792.820000 1963.580000 1793.920000 1964.060000 ;
+ RECT 1792.820000 1958.140000 1793.920000 1958.620000 ;
+ RECT 1792.820000 1952.700000 1793.920000 1953.180000 ;
+ RECT 1747.820000 2045.180000 1748.920000 2045.660000 ;
+ RECT 1747.820000 2039.740000 1748.920000 2040.220000 ;
+ RECT 1747.820000 2034.300000 1748.920000 2034.780000 ;
+ RECT 1747.820000 2028.860000 1748.920000 2029.340000 ;
+ RECT 1747.820000 2023.420000 1748.920000 2023.900000 ;
+ RECT 1702.820000 2045.180000 1703.920000 2045.660000 ;
+ RECT 1702.820000 2039.740000 1703.920000 2040.220000 ;
+ RECT 1702.820000 2034.300000 1703.920000 2034.780000 ;
+ RECT 1702.820000 2028.860000 1703.920000 2029.340000 ;
+ RECT 1702.820000 2023.420000 1703.920000 2023.900000 ;
+ RECT 1747.820000 2017.980000 1748.920000 2018.460000 ;
+ RECT 1747.820000 2012.540000 1748.920000 2013.020000 ;
+ RECT 1747.820000 2007.100000 1748.920000 2007.580000 ;
+ RECT 1747.820000 2001.660000 1748.920000 2002.140000 ;
+ RECT 1702.820000 2012.540000 1703.920000 2013.020000 ;
+ RECT 1702.820000 2007.100000 1703.920000 2007.580000 ;
+ RECT 1702.820000 2001.660000 1703.920000 2002.140000 ;
+ RECT 1702.820000 2017.980000 1703.920000 2018.460000 ;
+ RECT 1657.820000 2045.180000 1658.920000 2045.660000 ;
+ RECT 1653.690000 2045.180000 1654.690000 2045.660000 ;
+ RECT 1657.820000 2039.740000 1658.920000 2040.220000 ;
+ RECT 1653.690000 2039.740000 1654.690000 2040.220000 ;
+ RECT 1657.820000 2034.300000 1658.920000 2034.780000 ;
+ RECT 1653.690000 2034.300000 1654.690000 2034.780000 ;
+ RECT 1657.820000 2023.420000 1658.920000 2023.900000 ;
+ RECT 1653.690000 2023.420000 1654.690000 2023.900000 ;
+ RECT 1653.690000 2028.860000 1654.690000 2029.340000 ;
+ RECT 1657.820000 2028.860000 1658.920000 2029.340000 ;
+ RECT 1657.820000 2017.980000 1658.920000 2018.460000 ;
+ RECT 1653.690000 2017.980000 1654.690000 2018.460000 ;
+ RECT 1657.820000 2012.540000 1658.920000 2013.020000 ;
+ RECT 1653.690000 2012.540000 1654.690000 2013.020000 ;
+ RECT 1657.820000 2007.100000 1658.920000 2007.580000 ;
+ RECT 1653.690000 2007.100000 1654.690000 2007.580000 ;
+ RECT 1657.820000 2001.660000 1658.920000 2002.140000 ;
+ RECT 1653.690000 2001.660000 1654.690000 2002.140000 ;
+ RECT 1747.820000 1996.220000 1748.920000 1996.700000 ;
+ RECT 1747.820000 1990.780000 1748.920000 1991.260000 ;
+ RECT 1747.820000 1985.340000 1748.920000 1985.820000 ;
+ RECT 1747.820000 1979.900000 1748.920000 1980.380000 ;
+ RECT 1747.820000 1974.460000 1748.920000 1974.940000 ;
+ RECT 1702.820000 1996.220000 1703.920000 1996.700000 ;
+ RECT 1702.820000 1990.780000 1703.920000 1991.260000 ;
+ RECT 1702.820000 1985.340000 1703.920000 1985.820000 ;
+ RECT 1702.820000 1979.900000 1703.920000 1980.380000 ;
+ RECT 1702.820000 1974.460000 1703.920000 1974.940000 ;
+ RECT 1747.820000 1952.700000 1748.920000 1953.180000 ;
+ RECT 1747.820000 1958.140000 1748.920000 1958.620000 ;
+ RECT 1747.820000 1963.580000 1748.920000 1964.060000 ;
+ RECT 1747.820000 1969.020000 1748.920000 1969.500000 ;
+ RECT 1702.820000 1952.700000 1703.920000 1953.180000 ;
+ RECT 1702.820000 1958.140000 1703.920000 1958.620000 ;
+ RECT 1702.820000 1963.580000 1703.920000 1964.060000 ;
+ RECT 1702.820000 1969.020000 1703.920000 1969.500000 ;
+ RECT 1657.820000 1996.220000 1658.920000 1996.700000 ;
+ RECT 1653.690000 1996.220000 1654.690000 1996.700000 ;
+ RECT 1657.820000 1990.780000 1658.920000 1991.260000 ;
+ RECT 1653.690000 1990.780000 1654.690000 1991.260000 ;
+ RECT 1657.820000 1979.900000 1658.920000 1980.380000 ;
+ RECT 1653.690000 1979.900000 1654.690000 1980.380000 ;
+ RECT 1657.820000 1974.460000 1658.920000 1974.940000 ;
+ RECT 1653.690000 1974.460000 1654.690000 1974.940000 ;
+ RECT 1657.820000 1985.340000 1658.920000 1985.820000 ;
+ RECT 1653.690000 1985.340000 1654.690000 1985.820000 ;
+ RECT 1657.820000 1969.020000 1658.920000 1969.500000 ;
+ RECT 1653.690000 1969.020000 1654.690000 1969.500000 ;
+ RECT 1657.820000 1963.580000 1658.920000 1964.060000 ;
+ RECT 1653.690000 1963.580000 1654.690000 1964.060000 ;
+ RECT 1657.820000 1958.140000 1658.920000 1958.620000 ;
+ RECT 1657.820000 1952.700000 1658.920000 1953.180000 ;
+ RECT 1653.690000 1958.140000 1654.690000 1958.620000 ;
+ RECT 1653.690000 1952.700000 1654.690000 1953.180000 ;
+ RECT 1650.860000 2143.060000 1850.960000 2144.060000 ;
+ RECT 1650.860000 1950.690000 1850.960000 1951.690000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 1947.840000 1654.690000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 2147.100000 1654.690000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 1947.840000 1848.130000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 2147.100000 1848.130000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1950.690000 1651.860000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1950.690000 1850.960000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 2143.060000 1651.860000 2144.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 2143.060000 1850.960000 2144.060000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 1750.430000 1838.920000 1943.800000 ;
+ RECT 1792.820000 1750.430000 1793.920000 1943.800000 ;
+ RECT 1847.130000 1747.580000 1848.130000 1947.840000 ;
+ RECT 1747.820000 1750.430000 1748.920000 1943.800000 ;
+ RECT 1702.820000 1750.430000 1703.920000 1943.800000 ;
+ RECT 1657.820000 1750.430000 1658.920000 1943.800000 ;
+ RECT 1653.690000 1747.580000 1654.690000 1947.840000 ;
+ LAYER met3 ;
+ RECT 1837.820000 1937.400000 1838.920000 1937.880000 ;
+ RECT 1847.130000 1937.400000 1848.130000 1937.880000 ;
+ RECT 1847.130000 1926.520000 1848.130000 1927.000000 ;
+ RECT 1847.130000 1931.960000 1848.130000 1932.440000 ;
+ RECT 1837.820000 1931.960000 1838.920000 1932.440000 ;
+ RECT 1837.820000 1926.520000 1838.920000 1927.000000 ;
+ RECT 1837.820000 1921.080000 1838.920000 1921.560000 ;
+ RECT 1837.820000 1915.640000 1838.920000 1916.120000 ;
+ RECT 1847.130000 1921.080000 1848.130000 1921.560000 ;
+ RECT 1847.130000 1915.640000 1848.130000 1916.120000 ;
+ RECT 1837.820000 1899.320000 1838.920000 1899.800000 ;
+ RECT 1837.820000 1904.760000 1838.920000 1905.240000 ;
+ RECT 1847.130000 1904.760000 1848.130000 1905.240000 ;
+ RECT 1847.130000 1899.320000 1848.130000 1899.800000 ;
+ RECT 1837.820000 1910.200000 1838.920000 1910.680000 ;
+ RECT 1847.130000 1910.200000 1848.130000 1910.680000 ;
+ RECT 1792.820000 1937.400000 1793.920000 1937.880000 ;
+ RECT 1792.820000 1931.960000 1793.920000 1932.440000 ;
+ RECT 1792.820000 1926.520000 1793.920000 1927.000000 ;
+ RECT 1792.820000 1921.080000 1793.920000 1921.560000 ;
+ RECT 1792.820000 1899.320000 1793.920000 1899.800000 ;
+ RECT 1792.820000 1904.760000 1793.920000 1905.240000 ;
+ RECT 1792.820000 1910.200000 1793.920000 1910.680000 ;
+ RECT 1792.820000 1915.640000 1793.920000 1916.120000 ;
+ RECT 1847.130000 1888.440000 1848.130000 1888.920000 ;
+ RECT 1847.130000 1893.880000 1848.130000 1894.360000 ;
+ RECT 1837.820000 1893.880000 1838.920000 1894.360000 ;
+ RECT 1837.820000 1888.440000 1838.920000 1888.920000 ;
+ RECT 1837.820000 1883.000000 1838.920000 1883.480000 ;
+ RECT 1837.820000 1877.560000 1838.920000 1878.040000 ;
+ RECT 1847.130000 1883.000000 1848.130000 1883.480000 ;
+ RECT 1847.130000 1877.560000 1848.130000 1878.040000 ;
+ RECT 1847.130000 1861.240000 1848.130000 1861.720000 ;
+ RECT 1847.130000 1866.680000 1848.130000 1867.160000 ;
+ RECT 1847.130000 1872.120000 1848.130000 1872.600000 ;
+ RECT 1837.820000 1866.680000 1838.920000 1867.160000 ;
+ RECT 1837.820000 1861.240000 1838.920000 1861.720000 ;
+ RECT 1837.820000 1872.120000 1838.920000 1872.600000 ;
+ RECT 1837.820000 1855.800000 1838.920000 1856.280000 ;
+ RECT 1837.820000 1850.360000 1838.920000 1850.840000 ;
+ RECT 1847.130000 1855.800000 1848.130000 1856.280000 ;
+ RECT 1847.130000 1850.360000 1848.130000 1850.840000 ;
+ RECT 1792.820000 1893.880000 1793.920000 1894.360000 ;
+ RECT 1792.820000 1888.440000 1793.920000 1888.920000 ;
+ RECT 1792.820000 1883.000000 1793.920000 1883.480000 ;
+ RECT 1792.820000 1877.560000 1793.920000 1878.040000 ;
+ RECT 1792.820000 1866.680000 1793.920000 1867.160000 ;
+ RECT 1792.820000 1861.240000 1793.920000 1861.720000 ;
+ RECT 1792.820000 1855.800000 1793.920000 1856.280000 ;
+ RECT 1792.820000 1850.360000 1793.920000 1850.840000 ;
+ RECT 1792.820000 1872.120000 1793.920000 1872.600000 ;
+ RECT 1747.820000 1937.400000 1748.920000 1937.880000 ;
+ RECT 1747.820000 1931.960000 1748.920000 1932.440000 ;
+ RECT 1747.820000 1926.520000 1748.920000 1927.000000 ;
+ RECT 1702.820000 1937.400000 1703.920000 1937.880000 ;
+ RECT 1702.820000 1931.960000 1703.920000 1932.440000 ;
+ RECT 1702.820000 1926.520000 1703.920000 1927.000000 ;
+ RECT 1747.820000 1910.200000 1748.920000 1910.680000 ;
+ RECT 1747.820000 1904.760000 1748.920000 1905.240000 ;
+ RECT 1747.820000 1899.320000 1748.920000 1899.800000 ;
+ RECT 1747.820000 1915.640000 1748.920000 1916.120000 ;
+ RECT 1747.820000 1921.080000 1748.920000 1921.560000 ;
+ RECT 1702.820000 1921.080000 1703.920000 1921.560000 ;
+ RECT 1702.820000 1910.200000 1703.920000 1910.680000 ;
+ RECT 1702.820000 1904.760000 1703.920000 1905.240000 ;
+ RECT 1702.820000 1899.320000 1703.920000 1899.800000 ;
+ RECT 1702.820000 1915.640000 1703.920000 1916.120000 ;
+ RECT 1657.820000 1937.400000 1658.920000 1937.880000 ;
+ RECT 1653.690000 1937.400000 1654.690000 1937.880000 ;
+ RECT 1653.690000 1931.960000 1654.690000 1932.440000 ;
+ RECT 1657.820000 1931.960000 1658.920000 1932.440000 ;
+ RECT 1657.820000 1926.520000 1658.920000 1927.000000 ;
+ RECT 1653.690000 1926.520000 1654.690000 1927.000000 ;
+ RECT 1657.820000 1921.080000 1658.920000 1921.560000 ;
+ RECT 1653.690000 1921.080000 1654.690000 1921.560000 ;
+ RECT 1657.820000 1915.640000 1658.920000 1916.120000 ;
+ RECT 1653.690000 1915.640000 1654.690000 1916.120000 ;
+ RECT 1657.820000 1904.760000 1658.920000 1905.240000 ;
+ RECT 1653.690000 1904.760000 1654.690000 1905.240000 ;
+ RECT 1657.820000 1899.320000 1658.920000 1899.800000 ;
+ RECT 1653.690000 1899.320000 1654.690000 1899.800000 ;
+ RECT 1657.820000 1910.200000 1658.920000 1910.680000 ;
+ RECT 1653.690000 1910.200000 1654.690000 1910.680000 ;
+ RECT 1747.820000 1893.880000 1748.920000 1894.360000 ;
+ RECT 1747.820000 1888.440000 1748.920000 1888.920000 ;
+ RECT 1747.820000 1883.000000 1748.920000 1883.480000 ;
+ RECT 1747.820000 1877.560000 1748.920000 1878.040000 ;
+ RECT 1702.820000 1893.880000 1703.920000 1894.360000 ;
+ RECT 1702.820000 1888.440000 1703.920000 1888.920000 ;
+ RECT 1702.820000 1883.000000 1703.920000 1883.480000 ;
+ RECT 1702.820000 1877.560000 1703.920000 1878.040000 ;
+ RECT 1747.820000 1866.680000 1748.920000 1867.160000 ;
+ RECT 1747.820000 1850.360000 1748.920000 1850.840000 ;
+ RECT 1747.820000 1855.800000 1748.920000 1856.280000 ;
+ RECT 1747.820000 1861.240000 1748.920000 1861.720000 ;
+ RECT 1747.820000 1872.120000 1748.920000 1872.600000 ;
+ RECT 1702.820000 1850.360000 1703.920000 1850.840000 ;
+ RECT 1702.820000 1855.800000 1703.920000 1856.280000 ;
+ RECT 1702.820000 1861.240000 1703.920000 1861.720000 ;
+ RECT 1702.820000 1866.680000 1703.920000 1867.160000 ;
+ RECT 1702.820000 1872.120000 1703.920000 1872.600000 ;
+ RECT 1657.820000 1893.880000 1658.920000 1894.360000 ;
+ RECT 1653.690000 1893.880000 1654.690000 1894.360000 ;
+ RECT 1657.820000 1888.440000 1658.920000 1888.920000 ;
+ RECT 1653.690000 1888.440000 1654.690000 1888.920000 ;
+ RECT 1657.820000 1883.000000 1658.920000 1883.480000 ;
+ RECT 1653.690000 1883.000000 1654.690000 1883.480000 ;
+ RECT 1657.820000 1877.560000 1658.920000 1878.040000 ;
+ RECT 1653.690000 1877.560000 1654.690000 1878.040000 ;
+ RECT 1657.820000 1872.120000 1658.920000 1872.600000 ;
+ RECT 1657.820000 1866.680000 1658.920000 1867.160000 ;
+ RECT 1653.690000 1872.120000 1654.690000 1872.600000 ;
+ RECT 1653.690000 1866.680000 1654.690000 1867.160000 ;
+ RECT 1657.820000 1861.240000 1658.920000 1861.720000 ;
+ RECT 1653.690000 1861.240000 1654.690000 1861.720000 ;
+ RECT 1657.820000 1855.800000 1658.920000 1856.280000 ;
+ RECT 1653.690000 1855.800000 1654.690000 1856.280000 ;
+ RECT 1657.820000 1850.360000 1658.920000 1850.840000 ;
+ RECT 1653.690000 1850.360000 1654.690000 1850.840000 ;
+ RECT 1837.820000 1844.920000 1838.920000 1845.400000 ;
+ RECT 1837.820000 1839.480000 1838.920000 1839.960000 ;
+ RECT 1847.130000 1844.920000 1848.130000 1845.400000 ;
+ RECT 1847.130000 1839.480000 1848.130000 1839.960000 ;
+ RECT 1847.130000 1823.160000 1848.130000 1823.640000 ;
+ RECT 1847.130000 1828.600000 1848.130000 1829.080000 ;
+ RECT 1847.130000 1834.040000 1848.130000 1834.520000 ;
+ RECT 1837.820000 1834.040000 1838.920000 1834.520000 ;
+ RECT 1837.820000 1828.600000 1838.920000 1829.080000 ;
+ RECT 1837.820000 1823.160000 1838.920000 1823.640000 ;
+ RECT 1837.820000 1812.280000 1838.920000 1812.760000 ;
+ RECT 1837.820000 1817.720000 1838.920000 1818.200000 ;
+ RECT 1847.130000 1817.720000 1848.130000 1818.200000 ;
+ RECT 1847.130000 1812.280000 1848.130000 1812.760000 ;
+ RECT 1847.130000 1801.400000 1848.130000 1801.880000 ;
+ RECT 1847.130000 1806.840000 1848.130000 1807.320000 ;
+ RECT 1837.820000 1801.400000 1838.920000 1801.880000 ;
+ RECT 1837.820000 1806.840000 1838.920000 1807.320000 ;
+ RECT 1792.820000 1844.920000 1793.920000 1845.400000 ;
+ RECT 1792.820000 1839.480000 1793.920000 1839.960000 ;
+ RECT 1792.820000 1834.040000 1793.920000 1834.520000 ;
+ RECT 1792.820000 1828.600000 1793.920000 1829.080000 ;
+ RECT 1792.820000 1823.160000 1793.920000 1823.640000 ;
+ RECT 1792.820000 1801.400000 1793.920000 1801.880000 ;
+ RECT 1792.820000 1806.840000 1793.920000 1807.320000 ;
+ RECT 1792.820000 1812.280000 1793.920000 1812.760000 ;
+ RECT 1792.820000 1817.720000 1793.920000 1818.200000 ;
+ RECT 1837.820000 1795.960000 1838.920000 1796.440000 ;
+ RECT 1837.820000 1790.520000 1838.920000 1791.000000 ;
+ RECT 1847.130000 1795.960000 1848.130000 1796.440000 ;
+ RECT 1847.130000 1790.520000 1848.130000 1791.000000 ;
+ RECT 1837.820000 1779.640000 1838.920000 1780.120000 ;
+ RECT 1837.820000 1774.200000 1838.920000 1774.680000 ;
+ RECT 1847.130000 1779.640000 1848.130000 1780.120000 ;
+ RECT 1847.130000 1774.200000 1848.130000 1774.680000 ;
+ RECT 1837.820000 1785.080000 1838.920000 1785.560000 ;
+ RECT 1847.130000 1785.080000 1848.130000 1785.560000 ;
+ RECT 1847.130000 1763.320000 1848.130000 1763.800000 ;
+ RECT 1847.130000 1768.760000 1848.130000 1769.240000 ;
+ RECT 1837.820000 1768.760000 1838.920000 1769.240000 ;
+ RECT 1837.820000 1763.320000 1838.920000 1763.800000 ;
+ RECT 1837.820000 1757.880000 1838.920000 1758.360000 ;
+ RECT 1837.820000 1752.440000 1838.920000 1752.920000 ;
+ RECT 1847.130000 1757.880000 1848.130000 1758.360000 ;
+ RECT 1847.130000 1752.440000 1848.130000 1752.920000 ;
+ RECT 1792.820000 1795.960000 1793.920000 1796.440000 ;
+ RECT 1792.820000 1790.520000 1793.920000 1791.000000 ;
+ RECT 1792.820000 1785.080000 1793.920000 1785.560000 ;
+ RECT 1792.820000 1779.640000 1793.920000 1780.120000 ;
+ RECT 1792.820000 1774.200000 1793.920000 1774.680000 ;
+ RECT 1792.820000 1768.760000 1793.920000 1769.240000 ;
+ RECT 1792.820000 1763.320000 1793.920000 1763.800000 ;
+ RECT 1792.820000 1757.880000 1793.920000 1758.360000 ;
+ RECT 1792.820000 1752.440000 1793.920000 1752.920000 ;
+ RECT 1747.820000 1844.920000 1748.920000 1845.400000 ;
+ RECT 1747.820000 1839.480000 1748.920000 1839.960000 ;
+ RECT 1747.820000 1834.040000 1748.920000 1834.520000 ;
+ RECT 1747.820000 1828.600000 1748.920000 1829.080000 ;
+ RECT 1747.820000 1823.160000 1748.920000 1823.640000 ;
+ RECT 1702.820000 1844.920000 1703.920000 1845.400000 ;
+ RECT 1702.820000 1839.480000 1703.920000 1839.960000 ;
+ RECT 1702.820000 1834.040000 1703.920000 1834.520000 ;
+ RECT 1702.820000 1828.600000 1703.920000 1829.080000 ;
+ RECT 1702.820000 1823.160000 1703.920000 1823.640000 ;
+ RECT 1747.820000 1817.720000 1748.920000 1818.200000 ;
+ RECT 1747.820000 1812.280000 1748.920000 1812.760000 ;
+ RECT 1747.820000 1806.840000 1748.920000 1807.320000 ;
+ RECT 1747.820000 1801.400000 1748.920000 1801.880000 ;
+ RECT 1702.820000 1812.280000 1703.920000 1812.760000 ;
+ RECT 1702.820000 1806.840000 1703.920000 1807.320000 ;
+ RECT 1702.820000 1801.400000 1703.920000 1801.880000 ;
+ RECT 1702.820000 1817.720000 1703.920000 1818.200000 ;
+ RECT 1657.820000 1844.920000 1658.920000 1845.400000 ;
+ RECT 1653.690000 1844.920000 1654.690000 1845.400000 ;
+ RECT 1657.820000 1839.480000 1658.920000 1839.960000 ;
+ RECT 1653.690000 1839.480000 1654.690000 1839.960000 ;
+ RECT 1657.820000 1834.040000 1658.920000 1834.520000 ;
+ RECT 1653.690000 1834.040000 1654.690000 1834.520000 ;
+ RECT 1657.820000 1823.160000 1658.920000 1823.640000 ;
+ RECT 1653.690000 1823.160000 1654.690000 1823.640000 ;
+ RECT 1653.690000 1828.600000 1654.690000 1829.080000 ;
+ RECT 1657.820000 1828.600000 1658.920000 1829.080000 ;
+ RECT 1657.820000 1817.720000 1658.920000 1818.200000 ;
+ RECT 1653.690000 1817.720000 1654.690000 1818.200000 ;
+ RECT 1657.820000 1812.280000 1658.920000 1812.760000 ;
+ RECT 1653.690000 1812.280000 1654.690000 1812.760000 ;
+ RECT 1657.820000 1806.840000 1658.920000 1807.320000 ;
+ RECT 1653.690000 1806.840000 1654.690000 1807.320000 ;
+ RECT 1657.820000 1801.400000 1658.920000 1801.880000 ;
+ RECT 1653.690000 1801.400000 1654.690000 1801.880000 ;
+ RECT 1747.820000 1795.960000 1748.920000 1796.440000 ;
+ RECT 1747.820000 1790.520000 1748.920000 1791.000000 ;
+ RECT 1747.820000 1785.080000 1748.920000 1785.560000 ;
+ RECT 1747.820000 1779.640000 1748.920000 1780.120000 ;
+ RECT 1747.820000 1774.200000 1748.920000 1774.680000 ;
+ RECT 1702.820000 1795.960000 1703.920000 1796.440000 ;
+ RECT 1702.820000 1790.520000 1703.920000 1791.000000 ;
+ RECT 1702.820000 1785.080000 1703.920000 1785.560000 ;
+ RECT 1702.820000 1779.640000 1703.920000 1780.120000 ;
+ RECT 1702.820000 1774.200000 1703.920000 1774.680000 ;
+ RECT 1747.820000 1752.440000 1748.920000 1752.920000 ;
+ RECT 1747.820000 1757.880000 1748.920000 1758.360000 ;
+ RECT 1747.820000 1763.320000 1748.920000 1763.800000 ;
+ RECT 1747.820000 1768.760000 1748.920000 1769.240000 ;
+ RECT 1702.820000 1752.440000 1703.920000 1752.920000 ;
+ RECT 1702.820000 1757.880000 1703.920000 1758.360000 ;
+ RECT 1702.820000 1763.320000 1703.920000 1763.800000 ;
+ RECT 1702.820000 1768.760000 1703.920000 1769.240000 ;
+ RECT 1657.820000 1795.960000 1658.920000 1796.440000 ;
+ RECT 1653.690000 1795.960000 1654.690000 1796.440000 ;
+ RECT 1657.820000 1790.520000 1658.920000 1791.000000 ;
+ RECT 1653.690000 1790.520000 1654.690000 1791.000000 ;
+ RECT 1657.820000 1779.640000 1658.920000 1780.120000 ;
+ RECT 1653.690000 1779.640000 1654.690000 1780.120000 ;
+ RECT 1657.820000 1774.200000 1658.920000 1774.680000 ;
+ RECT 1653.690000 1774.200000 1654.690000 1774.680000 ;
+ RECT 1657.820000 1785.080000 1658.920000 1785.560000 ;
+ RECT 1653.690000 1785.080000 1654.690000 1785.560000 ;
+ RECT 1657.820000 1768.760000 1658.920000 1769.240000 ;
+ RECT 1653.690000 1768.760000 1654.690000 1769.240000 ;
+ RECT 1657.820000 1763.320000 1658.920000 1763.800000 ;
+ RECT 1653.690000 1763.320000 1654.690000 1763.800000 ;
+ RECT 1657.820000 1757.880000 1658.920000 1758.360000 ;
+ RECT 1657.820000 1752.440000 1658.920000 1752.920000 ;
+ RECT 1653.690000 1757.880000 1654.690000 1758.360000 ;
+ RECT 1653.690000 1752.440000 1654.690000 1752.920000 ;
+ RECT 1650.860000 1942.800000 1850.960000 1943.800000 ;
+ RECT 1650.860000 1750.430000 1850.960000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 1747.580000 1654.690000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 1946.840000 1654.690000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 1747.580000 1848.130000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 1946.840000 1848.130000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1750.430000 1651.860000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1750.430000 1850.960000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1942.800000 1651.860000 1943.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1942.800000 1850.960000 1943.800000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 1837.820000 1550.170000 1838.920000 1743.540000 ;
+ RECT 1792.820000 1550.170000 1793.920000 1743.540000 ;
+ RECT 1847.130000 1547.320000 1848.130000 1747.580000 ;
+ RECT 1747.820000 1550.170000 1748.920000 1743.540000 ;
+ RECT 1702.820000 1550.170000 1703.920000 1743.540000 ;
+ RECT 1657.820000 1550.170000 1658.920000 1743.540000 ;
+ RECT 1653.690000 1547.320000 1654.690000 1747.580000 ;
+ LAYER met3 ;
+ RECT 1837.820000 1737.140000 1838.920000 1737.620000 ;
+ RECT 1847.130000 1737.140000 1848.130000 1737.620000 ;
+ RECT 1847.130000 1726.260000 1848.130000 1726.740000 ;
+ RECT 1847.130000 1731.700000 1848.130000 1732.180000 ;
+ RECT 1837.820000 1731.700000 1838.920000 1732.180000 ;
+ RECT 1837.820000 1726.260000 1838.920000 1726.740000 ;
+ RECT 1837.820000 1720.820000 1838.920000 1721.300000 ;
+ RECT 1837.820000 1715.380000 1838.920000 1715.860000 ;
+ RECT 1847.130000 1720.820000 1848.130000 1721.300000 ;
+ RECT 1847.130000 1715.380000 1848.130000 1715.860000 ;
+ RECT 1837.820000 1699.060000 1838.920000 1699.540000 ;
+ RECT 1837.820000 1704.500000 1838.920000 1704.980000 ;
+ RECT 1847.130000 1704.500000 1848.130000 1704.980000 ;
+ RECT 1847.130000 1699.060000 1848.130000 1699.540000 ;
+ RECT 1837.820000 1709.940000 1838.920000 1710.420000 ;
+ RECT 1847.130000 1709.940000 1848.130000 1710.420000 ;
+ RECT 1792.820000 1737.140000 1793.920000 1737.620000 ;
+ RECT 1792.820000 1731.700000 1793.920000 1732.180000 ;
+ RECT 1792.820000 1726.260000 1793.920000 1726.740000 ;
+ RECT 1792.820000 1720.820000 1793.920000 1721.300000 ;
+ RECT 1792.820000 1699.060000 1793.920000 1699.540000 ;
+ RECT 1792.820000 1704.500000 1793.920000 1704.980000 ;
+ RECT 1792.820000 1709.940000 1793.920000 1710.420000 ;
+ RECT 1792.820000 1715.380000 1793.920000 1715.860000 ;
+ RECT 1847.130000 1688.180000 1848.130000 1688.660000 ;
+ RECT 1847.130000 1693.620000 1848.130000 1694.100000 ;
+ RECT 1837.820000 1693.620000 1838.920000 1694.100000 ;
+ RECT 1837.820000 1688.180000 1838.920000 1688.660000 ;
+ RECT 1837.820000 1682.740000 1838.920000 1683.220000 ;
+ RECT 1837.820000 1677.300000 1838.920000 1677.780000 ;
+ RECT 1847.130000 1682.740000 1848.130000 1683.220000 ;
+ RECT 1847.130000 1677.300000 1848.130000 1677.780000 ;
+ RECT 1847.130000 1660.980000 1848.130000 1661.460000 ;
+ RECT 1847.130000 1666.420000 1848.130000 1666.900000 ;
+ RECT 1847.130000 1671.860000 1848.130000 1672.340000 ;
+ RECT 1837.820000 1666.420000 1838.920000 1666.900000 ;
+ RECT 1837.820000 1660.980000 1838.920000 1661.460000 ;
+ RECT 1837.820000 1671.860000 1838.920000 1672.340000 ;
+ RECT 1837.820000 1655.540000 1838.920000 1656.020000 ;
+ RECT 1837.820000 1650.100000 1838.920000 1650.580000 ;
+ RECT 1847.130000 1655.540000 1848.130000 1656.020000 ;
+ RECT 1847.130000 1650.100000 1848.130000 1650.580000 ;
+ RECT 1792.820000 1693.620000 1793.920000 1694.100000 ;
+ RECT 1792.820000 1688.180000 1793.920000 1688.660000 ;
+ RECT 1792.820000 1682.740000 1793.920000 1683.220000 ;
+ RECT 1792.820000 1677.300000 1793.920000 1677.780000 ;
+ RECT 1792.820000 1666.420000 1793.920000 1666.900000 ;
+ RECT 1792.820000 1660.980000 1793.920000 1661.460000 ;
+ RECT 1792.820000 1655.540000 1793.920000 1656.020000 ;
+ RECT 1792.820000 1650.100000 1793.920000 1650.580000 ;
+ RECT 1792.820000 1671.860000 1793.920000 1672.340000 ;
+ RECT 1747.820000 1737.140000 1748.920000 1737.620000 ;
+ RECT 1747.820000 1731.700000 1748.920000 1732.180000 ;
+ RECT 1747.820000 1726.260000 1748.920000 1726.740000 ;
+ RECT 1702.820000 1737.140000 1703.920000 1737.620000 ;
+ RECT 1702.820000 1731.700000 1703.920000 1732.180000 ;
+ RECT 1702.820000 1726.260000 1703.920000 1726.740000 ;
+ RECT 1747.820000 1709.940000 1748.920000 1710.420000 ;
+ RECT 1747.820000 1704.500000 1748.920000 1704.980000 ;
+ RECT 1747.820000 1699.060000 1748.920000 1699.540000 ;
+ RECT 1747.820000 1715.380000 1748.920000 1715.860000 ;
+ RECT 1747.820000 1720.820000 1748.920000 1721.300000 ;
+ RECT 1702.820000 1720.820000 1703.920000 1721.300000 ;
+ RECT 1702.820000 1709.940000 1703.920000 1710.420000 ;
+ RECT 1702.820000 1704.500000 1703.920000 1704.980000 ;
+ RECT 1702.820000 1699.060000 1703.920000 1699.540000 ;
+ RECT 1702.820000 1715.380000 1703.920000 1715.860000 ;
+ RECT 1657.820000 1737.140000 1658.920000 1737.620000 ;
+ RECT 1653.690000 1737.140000 1654.690000 1737.620000 ;
+ RECT 1653.690000 1731.700000 1654.690000 1732.180000 ;
+ RECT 1657.820000 1731.700000 1658.920000 1732.180000 ;
+ RECT 1657.820000 1726.260000 1658.920000 1726.740000 ;
+ RECT 1653.690000 1726.260000 1654.690000 1726.740000 ;
+ RECT 1657.820000 1720.820000 1658.920000 1721.300000 ;
+ RECT 1653.690000 1720.820000 1654.690000 1721.300000 ;
+ RECT 1657.820000 1715.380000 1658.920000 1715.860000 ;
+ RECT 1653.690000 1715.380000 1654.690000 1715.860000 ;
+ RECT 1657.820000 1704.500000 1658.920000 1704.980000 ;
+ RECT 1653.690000 1704.500000 1654.690000 1704.980000 ;
+ RECT 1657.820000 1699.060000 1658.920000 1699.540000 ;
+ RECT 1653.690000 1699.060000 1654.690000 1699.540000 ;
+ RECT 1657.820000 1709.940000 1658.920000 1710.420000 ;
+ RECT 1653.690000 1709.940000 1654.690000 1710.420000 ;
+ RECT 1747.820000 1693.620000 1748.920000 1694.100000 ;
+ RECT 1747.820000 1688.180000 1748.920000 1688.660000 ;
+ RECT 1747.820000 1682.740000 1748.920000 1683.220000 ;
+ RECT 1747.820000 1677.300000 1748.920000 1677.780000 ;
+ RECT 1702.820000 1693.620000 1703.920000 1694.100000 ;
+ RECT 1702.820000 1688.180000 1703.920000 1688.660000 ;
+ RECT 1702.820000 1682.740000 1703.920000 1683.220000 ;
+ RECT 1702.820000 1677.300000 1703.920000 1677.780000 ;
+ RECT 1747.820000 1666.420000 1748.920000 1666.900000 ;
+ RECT 1747.820000 1650.100000 1748.920000 1650.580000 ;
+ RECT 1747.820000 1655.540000 1748.920000 1656.020000 ;
+ RECT 1747.820000 1660.980000 1748.920000 1661.460000 ;
+ RECT 1747.820000 1671.860000 1748.920000 1672.340000 ;
+ RECT 1702.820000 1650.100000 1703.920000 1650.580000 ;
+ RECT 1702.820000 1655.540000 1703.920000 1656.020000 ;
+ RECT 1702.820000 1660.980000 1703.920000 1661.460000 ;
+ RECT 1702.820000 1666.420000 1703.920000 1666.900000 ;
+ RECT 1702.820000 1671.860000 1703.920000 1672.340000 ;
+ RECT 1657.820000 1693.620000 1658.920000 1694.100000 ;
+ RECT 1653.690000 1693.620000 1654.690000 1694.100000 ;
+ RECT 1657.820000 1688.180000 1658.920000 1688.660000 ;
+ RECT 1653.690000 1688.180000 1654.690000 1688.660000 ;
+ RECT 1657.820000 1682.740000 1658.920000 1683.220000 ;
+ RECT 1653.690000 1682.740000 1654.690000 1683.220000 ;
+ RECT 1657.820000 1677.300000 1658.920000 1677.780000 ;
+ RECT 1653.690000 1677.300000 1654.690000 1677.780000 ;
+ RECT 1657.820000 1671.860000 1658.920000 1672.340000 ;
+ RECT 1657.820000 1666.420000 1658.920000 1666.900000 ;
+ RECT 1653.690000 1671.860000 1654.690000 1672.340000 ;
+ RECT 1653.690000 1666.420000 1654.690000 1666.900000 ;
+ RECT 1657.820000 1660.980000 1658.920000 1661.460000 ;
+ RECT 1653.690000 1660.980000 1654.690000 1661.460000 ;
+ RECT 1657.820000 1655.540000 1658.920000 1656.020000 ;
+ RECT 1653.690000 1655.540000 1654.690000 1656.020000 ;
+ RECT 1657.820000 1650.100000 1658.920000 1650.580000 ;
+ RECT 1653.690000 1650.100000 1654.690000 1650.580000 ;
+ RECT 1837.820000 1644.660000 1838.920000 1645.140000 ;
+ RECT 1837.820000 1639.220000 1838.920000 1639.700000 ;
+ RECT 1847.130000 1644.660000 1848.130000 1645.140000 ;
+ RECT 1847.130000 1639.220000 1848.130000 1639.700000 ;
+ RECT 1847.130000 1622.900000 1848.130000 1623.380000 ;
+ RECT 1847.130000 1628.340000 1848.130000 1628.820000 ;
+ RECT 1847.130000 1633.780000 1848.130000 1634.260000 ;
+ RECT 1837.820000 1633.780000 1838.920000 1634.260000 ;
+ RECT 1837.820000 1628.340000 1838.920000 1628.820000 ;
+ RECT 1837.820000 1622.900000 1838.920000 1623.380000 ;
+ RECT 1837.820000 1612.020000 1838.920000 1612.500000 ;
+ RECT 1837.820000 1617.460000 1838.920000 1617.940000 ;
+ RECT 1847.130000 1617.460000 1848.130000 1617.940000 ;
+ RECT 1847.130000 1612.020000 1848.130000 1612.500000 ;
+ RECT 1847.130000 1601.140000 1848.130000 1601.620000 ;
+ RECT 1847.130000 1606.580000 1848.130000 1607.060000 ;
+ RECT 1837.820000 1601.140000 1838.920000 1601.620000 ;
+ RECT 1837.820000 1606.580000 1838.920000 1607.060000 ;
+ RECT 1792.820000 1644.660000 1793.920000 1645.140000 ;
+ RECT 1792.820000 1639.220000 1793.920000 1639.700000 ;
+ RECT 1792.820000 1633.780000 1793.920000 1634.260000 ;
+ RECT 1792.820000 1628.340000 1793.920000 1628.820000 ;
+ RECT 1792.820000 1622.900000 1793.920000 1623.380000 ;
+ RECT 1792.820000 1601.140000 1793.920000 1601.620000 ;
+ RECT 1792.820000 1606.580000 1793.920000 1607.060000 ;
+ RECT 1792.820000 1612.020000 1793.920000 1612.500000 ;
+ RECT 1792.820000 1617.460000 1793.920000 1617.940000 ;
+ RECT 1837.820000 1595.700000 1838.920000 1596.180000 ;
+ RECT 1837.820000 1590.260000 1838.920000 1590.740000 ;
+ RECT 1847.130000 1595.700000 1848.130000 1596.180000 ;
+ RECT 1847.130000 1590.260000 1848.130000 1590.740000 ;
+ RECT 1837.820000 1579.380000 1838.920000 1579.860000 ;
+ RECT 1837.820000 1573.940000 1838.920000 1574.420000 ;
+ RECT 1847.130000 1579.380000 1848.130000 1579.860000 ;
+ RECT 1847.130000 1573.940000 1848.130000 1574.420000 ;
+ RECT 1837.820000 1584.820000 1838.920000 1585.300000 ;
+ RECT 1847.130000 1584.820000 1848.130000 1585.300000 ;
+ RECT 1847.130000 1563.060000 1848.130000 1563.540000 ;
+ RECT 1847.130000 1568.500000 1848.130000 1568.980000 ;
+ RECT 1837.820000 1568.500000 1838.920000 1568.980000 ;
+ RECT 1837.820000 1563.060000 1838.920000 1563.540000 ;
+ RECT 1837.820000 1557.620000 1838.920000 1558.100000 ;
+ RECT 1837.820000 1552.180000 1838.920000 1552.660000 ;
+ RECT 1847.130000 1557.620000 1848.130000 1558.100000 ;
+ RECT 1847.130000 1552.180000 1848.130000 1552.660000 ;
+ RECT 1792.820000 1595.700000 1793.920000 1596.180000 ;
+ RECT 1792.820000 1590.260000 1793.920000 1590.740000 ;
+ RECT 1792.820000 1584.820000 1793.920000 1585.300000 ;
+ RECT 1792.820000 1579.380000 1793.920000 1579.860000 ;
+ RECT 1792.820000 1573.940000 1793.920000 1574.420000 ;
+ RECT 1792.820000 1568.500000 1793.920000 1568.980000 ;
+ RECT 1792.820000 1563.060000 1793.920000 1563.540000 ;
+ RECT 1792.820000 1557.620000 1793.920000 1558.100000 ;
+ RECT 1792.820000 1552.180000 1793.920000 1552.660000 ;
+ RECT 1747.820000 1644.660000 1748.920000 1645.140000 ;
+ RECT 1747.820000 1639.220000 1748.920000 1639.700000 ;
+ RECT 1747.820000 1633.780000 1748.920000 1634.260000 ;
+ RECT 1747.820000 1628.340000 1748.920000 1628.820000 ;
+ RECT 1747.820000 1622.900000 1748.920000 1623.380000 ;
+ RECT 1702.820000 1644.660000 1703.920000 1645.140000 ;
+ RECT 1702.820000 1639.220000 1703.920000 1639.700000 ;
+ RECT 1702.820000 1633.780000 1703.920000 1634.260000 ;
+ RECT 1702.820000 1628.340000 1703.920000 1628.820000 ;
+ RECT 1702.820000 1622.900000 1703.920000 1623.380000 ;
+ RECT 1747.820000 1617.460000 1748.920000 1617.940000 ;
+ RECT 1747.820000 1612.020000 1748.920000 1612.500000 ;
+ RECT 1747.820000 1606.580000 1748.920000 1607.060000 ;
+ RECT 1747.820000 1601.140000 1748.920000 1601.620000 ;
+ RECT 1702.820000 1612.020000 1703.920000 1612.500000 ;
+ RECT 1702.820000 1606.580000 1703.920000 1607.060000 ;
+ RECT 1702.820000 1601.140000 1703.920000 1601.620000 ;
+ RECT 1702.820000 1617.460000 1703.920000 1617.940000 ;
+ RECT 1657.820000 1644.660000 1658.920000 1645.140000 ;
+ RECT 1653.690000 1644.660000 1654.690000 1645.140000 ;
+ RECT 1657.820000 1639.220000 1658.920000 1639.700000 ;
+ RECT 1653.690000 1639.220000 1654.690000 1639.700000 ;
+ RECT 1657.820000 1633.780000 1658.920000 1634.260000 ;
+ RECT 1653.690000 1633.780000 1654.690000 1634.260000 ;
+ RECT 1657.820000 1622.900000 1658.920000 1623.380000 ;
+ RECT 1653.690000 1622.900000 1654.690000 1623.380000 ;
+ RECT 1653.690000 1628.340000 1654.690000 1628.820000 ;
+ RECT 1657.820000 1628.340000 1658.920000 1628.820000 ;
+ RECT 1657.820000 1617.460000 1658.920000 1617.940000 ;
+ RECT 1653.690000 1617.460000 1654.690000 1617.940000 ;
+ RECT 1657.820000 1612.020000 1658.920000 1612.500000 ;
+ RECT 1653.690000 1612.020000 1654.690000 1612.500000 ;
+ RECT 1657.820000 1606.580000 1658.920000 1607.060000 ;
+ RECT 1653.690000 1606.580000 1654.690000 1607.060000 ;
+ RECT 1657.820000 1601.140000 1658.920000 1601.620000 ;
+ RECT 1653.690000 1601.140000 1654.690000 1601.620000 ;
+ RECT 1747.820000 1595.700000 1748.920000 1596.180000 ;
+ RECT 1747.820000 1590.260000 1748.920000 1590.740000 ;
+ RECT 1747.820000 1584.820000 1748.920000 1585.300000 ;
+ RECT 1747.820000 1579.380000 1748.920000 1579.860000 ;
+ RECT 1747.820000 1573.940000 1748.920000 1574.420000 ;
+ RECT 1702.820000 1595.700000 1703.920000 1596.180000 ;
+ RECT 1702.820000 1590.260000 1703.920000 1590.740000 ;
+ RECT 1702.820000 1584.820000 1703.920000 1585.300000 ;
+ RECT 1702.820000 1579.380000 1703.920000 1579.860000 ;
+ RECT 1702.820000 1573.940000 1703.920000 1574.420000 ;
+ RECT 1747.820000 1552.180000 1748.920000 1552.660000 ;
+ RECT 1747.820000 1557.620000 1748.920000 1558.100000 ;
+ RECT 1747.820000 1563.060000 1748.920000 1563.540000 ;
+ RECT 1747.820000 1568.500000 1748.920000 1568.980000 ;
+ RECT 1702.820000 1552.180000 1703.920000 1552.660000 ;
+ RECT 1702.820000 1557.620000 1703.920000 1558.100000 ;
+ RECT 1702.820000 1563.060000 1703.920000 1563.540000 ;
+ RECT 1702.820000 1568.500000 1703.920000 1568.980000 ;
+ RECT 1657.820000 1595.700000 1658.920000 1596.180000 ;
+ RECT 1653.690000 1595.700000 1654.690000 1596.180000 ;
+ RECT 1657.820000 1590.260000 1658.920000 1590.740000 ;
+ RECT 1653.690000 1590.260000 1654.690000 1590.740000 ;
+ RECT 1657.820000 1579.380000 1658.920000 1579.860000 ;
+ RECT 1653.690000 1579.380000 1654.690000 1579.860000 ;
+ RECT 1657.820000 1573.940000 1658.920000 1574.420000 ;
+ RECT 1653.690000 1573.940000 1654.690000 1574.420000 ;
+ RECT 1657.820000 1584.820000 1658.920000 1585.300000 ;
+ RECT 1653.690000 1584.820000 1654.690000 1585.300000 ;
+ RECT 1657.820000 1568.500000 1658.920000 1568.980000 ;
+ RECT 1653.690000 1568.500000 1654.690000 1568.980000 ;
+ RECT 1657.820000 1563.060000 1658.920000 1563.540000 ;
+ RECT 1653.690000 1563.060000 1654.690000 1563.540000 ;
+ RECT 1657.820000 1557.620000 1658.920000 1558.100000 ;
+ RECT 1657.820000 1552.180000 1658.920000 1552.660000 ;
+ RECT 1653.690000 1557.620000 1654.690000 1558.100000 ;
+ RECT 1653.690000 1552.180000 1654.690000 1552.660000 ;
+ RECT 1650.860000 1742.540000 1850.960000 1743.540000 ;
+ RECT 1650.860000 1550.170000 1850.960000 1551.170000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 1547.320000 1654.690000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1653.690000 1746.580000 1654.690000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 1547.320000 1848.130000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1847.130000 1746.580000 1848.130000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1550.170000 1651.860000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1550.170000 1850.960000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1650.860000 1742.540000 1651.860000 1743.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1849.960000 1742.540000 1850.960000 1743.540000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'N_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 3349.660000 1854.790000 3379.920000 ;
+ RECT 2047.230000 3349.660000 2048.230000 3379.920000 ;
+ RECT 1857.920000 3352.510000 1859.020000 3376.560000 ;
+ RECT 1902.920000 3352.510000 1904.020000 3376.560000 ;
+ RECT 1947.920000 3352.510000 1949.020000 3376.560000 ;
+ RECT 1992.920000 3352.510000 1994.020000 3376.560000 ;
+ RECT 2037.920000 3352.510000 2039.020000 3376.560000 ;
+ LAYER met3 ;
+ RECT 2047.230000 3365.400000 2048.230000 3365.880000 ;
+ RECT 2047.230000 3370.840000 2048.230000 3371.320000 ;
+ RECT 2037.920000 3370.840000 2039.020000 3371.320000 ;
+ RECT 2037.920000 3365.400000 2039.020000 3365.880000 ;
+ RECT 1992.920000 3365.400000 1994.020000 3365.880000 ;
+ RECT 1992.920000 3370.840000 1994.020000 3371.320000 ;
+ RECT 1902.920000 3365.400000 1904.020000 3365.880000 ;
+ RECT 1947.920000 3365.400000 1949.020000 3365.880000 ;
+ RECT 1947.920000 3370.840000 1949.020000 3371.320000 ;
+ RECT 1902.920000 3370.840000 1904.020000 3371.320000 ;
+ RECT 1853.790000 3365.400000 1854.790000 3365.880000 ;
+ RECT 1857.920000 3365.400000 1859.020000 3365.880000 ;
+ RECT 1857.920000 3370.840000 1859.020000 3371.320000 ;
+ RECT 1853.790000 3370.840000 1854.790000 3371.320000 ;
+ RECT 2047.230000 3354.520000 2048.230000 3355.000000 ;
+ RECT 2047.230000 3359.960000 2048.230000 3360.440000 ;
+ RECT 2037.920000 3359.960000 2039.020000 3360.440000 ;
+ RECT 2037.920000 3354.520000 2039.020000 3355.000000 ;
+ RECT 1992.920000 3354.520000 1994.020000 3355.000000 ;
+ RECT 1992.920000 3359.960000 1994.020000 3360.440000 ;
+ RECT 1902.920000 3354.520000 1904.020000 3355.000000 ;
+ RECT 1947.920000 3354.520000 1949.020000 3355.000000 ;
+ RECT 1947.920000 3359.960000 1949.020000 3360.440000 ;
+ RECT 1902.920000 3359.960000 1904.020000 3360.440000 ;
+ RECT 1853.790000 3359.960000 1854.790000 3360.440000 ;
+ RECT 1857.920000 3359.960000 1859.020000 3360.440000 ;
+ RECT 1853.790000 3354.520000 1854.790000 3355.000000 ;
+ RECT 1857.920000 3354.520000 1859.020000 3355.000000 ;
+ RECT 1850.960000 3375.560000 2051.060000 3376.560000 ;
+ RECT 1850.960000 3352.510000 2051.060000 3353.510000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 3349.660000 1854.790000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 3378.920000 1854.790000 3379.920000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 3349.660000 2048.230000 3350.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 3378.920000 2048.230000 3379.920000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 3352.510000 1851.960000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 3352.510000 2051.060000 3353.510000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 3375.560000 1851.960000 3376.560000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 3375.560000 2051.060000 3376.560000 ;
+ END
+# end of P/G pin shape extracted from block 'N_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 1349.910000 2039.020000 1543.280000 ;
+ RECT 1992.920000 1349.910000 1994.020000 1543.280000 ;
+ RECT 2047.230000 1347.060000 2048.230000 1547.320000 ;
+ RECT 1947.920000 1349.910000 1949.020000 1543.280000 ;
+ RECT 1902.920000 1349.910000 1904.020000 1543.280000 ;
+ RECT 1857.920000 1349.910000 1859.020000 1543.280000 ;
+ RECT 1853.790000 1347.060000 1854.790000 1547.320000 ;
+ LAYER met3 ;
+ RECT 2037.920000 1536.880000 2039.020000 1537.360000 ;
+ RECT 2047.230000 1536.880000 2048.230000 1537.360000 ;
+ RECT 2047.230000 1526.000000 2048.230000 1526.480000 ;
+ RECT 2047.230000 1531.440000 2048.230000 1531.920000 ;
+ RECT 2037.920000 1531.440000 2039.020000 1531.920000 ;
+ RECT 2037.920000 1526.000000 2039.020000 1526.480000 ;
+ RECT 2037.920000 1520.560000 2039.020000 1521.040000 ;
+ RECT 2037.920000 1515.120000 2039.020000 1515.600000 ;
+ RECT 2047.230000 1520.560000 2048.230000 1521.040000 ;
+ RECT 2047.230000 1515.120000 2048.230000 1515.600000 ;
+ RECT 2037.920000 1498.800000 2039.020000 1499.280000 ;
+ RECT 2037.920000 1504.240000 2039.020000 1504.720000 ;
+ RECT 2047.230000 1504.240000 2048.230000 1504.720000 ;
+ RECT 2047.230000 1498.800000 2048.230000 1499.280000 ;
+ RECT 2037.920000 1509.680000 2039.020000 1510.160000 ;
+ RECT 2047.230000 1509.680000 2048.230000 1510.160000 ;
+ RECT 1992.920000 1536.880000 1994.020000 1537.360000 ;
+ RECT 1992.920000 1531.440000 1994.020000 1531.920000 ;
+ RECT 1992.920000 1526.000000 1994.020000 1526.480000 ;
+ RECT 1992.920000 1520.560000 1994.020000 1521.040000 ;
+ RECT 1992.920000 1498.800000 1994.020000 1499.280000 ;
+ RECT 1992.920000 1504.240000 1994.020000 1504.720000 ;
+ RECT 1992.920000 1509.680000 1994.020000 1510.160000 ;
+ RECT 1992.920000 1515.120000 1994.020000 1515.600000 ;
+ RECT 2047.230000 1487.920000 2048.230000 1488.400000 ;
+ RECT 2047.230000 1493.360000 2048.230000 1493.840000 ;
+ RECT 2037.920000 1493.360000 2039.020000 1493.840000 ;
+ RECT 2037.920000 1487.920000 2039.020000 1488.400000 ;
+ RECT 2037.920000 1482.480000 2039.020000 1482.960000 ;
+ RECT 2037.920000 1477.040000 2039.020000 1477.520000 ;
+ RECT 2047.230000 1482.480000 2048.230000 1482.960000 ;
+ RECT 2047.230000 1477.040000 2048.230000 1477.520000 ;
+ RECT 2047.230000 1460.720000 2048.230000 1461.200000 ;
+ RECT 2047.230000 1466.160000 2048.230000 1466.640000 ;
+ RECT 2047.230000 1471.600000 2048.230000 1472.080000 ;
+ RECT 2037.920000 1466.160000 2039.020000 1466.640000 ;
+ RECT 2037.920000 1460.720000 2039.020000 1461.200000 ;
+ RECT 2037.920000 1471.600000 2039.020000 1472.080000 ;
+ RECT 2037.920000 1455.280000 2039.020000 1455.760000 ;
+ RECT 2037.920000 1449.840000 2039.020000 1450.320000 ;
+ RECT 2047.230000 1455.280000 2048.230000 1455.760000 ;
+ RECT 2047.230000 1449.840000 2048.230000 1450.320000 ;
+ RECT 1992.920000 1493.360000 1994.020000 1493.840000 ;
+ RECT 1992.920000 1487.920000 1994.020000 1488.400000 ;
+ RECT 1992.920000 1482.480000 1994.020000 1482.960000 ;
+ RECT 1992.920000 1477.040000 1994.020000 1477.520000 ;
+ RECT 1992.920000 1466.160000 1994.020000 1466.640000 ;
+ RECT 1992.920000 1460.720000 1994.020000 1461.200000 ;
+ RECT 1992.920000 1455.280000 1994.020000 1455.760000 ;
+ RECT 1992.920000 1449.840000 1994.020000 1450.320000 ;
+ RECT 1992.920000 1471.600000 1994.020000 1472.080000 ;
+ RECT 1947.920000 1536.880000 1949.020000 1537.360000 ;
+ RECT 1947.920000 1531.440000 1949.020000 1531.920000 ;
+ RECT 1947.920000 1526.000000 1949.020000 1526.480000 ;
+ RECT 1902.920000 1536.880000 1904.020000 1537.360000 ;
+ RECT 1902.920000 1531.440000 1904.020000 1531.920000 ;
+ RECT 1902.920000 1526.000000 1904.020000 1526.480000 ;
+ RECT 1947.920000 1509.680000 1949.020000 1510.160000 ;
+ RECT 1947.920000 1504.240000 1949.020000 1504.720000 ;
+ RECT 1947.920000 1498.800000 1949.020000 1499.280000 ;
+ RECT 1947.920000 1515.120000 1949.020000 1515.600000 ;
+ RECT 1947.920000 1520.560000 1949.020000 1521.040000 ;
+ RECT 1902.920000 1520.560000 1904.020000 1521.040000 ;
+ RECT 1902.920000 1509.680000 1904.020000 1510.160000 ;
+ RECT 1902.920000 1504.240000 1904.020000 1504.720000 ;
+ RECT 1902.920000 1498.800000 1904.020000 1499.280000 ;
+ RECT 1902.920000 1515.120000 1904.020000 1515.600000 ;
+ RECT 1857.920000 1536.880000 1859.020000 1537.360000 ;
+ RECT 1853.790000 1536.880000 1854.790000 1537.360000 ;
+ RECT 1853.790000 1531.440000 1854.790000 1531.920000 ;
+ RECT 1857.920000 1531.440000 1859.020000 1531.920000 ;
+ RECT 1857.920000 1526.000000 1859.020000 1526.480000 ;
+ RECT 1853.790000 1526.000000 1854.790000 1526.480000 ;
+ RECT 1857.920000 1520.560000 1859.020000 1521.040000 ;
+ RECT 1853.790000 1520.560000 1854.790000 1521.040000 ;
+ RECT 1857.920000 1515.120000 1859.020000 1515.600000 ;
+ RECT 1853.790000 1515.120000 1854.790000 1515.600000 ;
+ RECT 1857.920000 1504.240000 1859.020000 1504.720000 ;
+ RECT 1853.790000 1504.240000 1854.790000 1504.720000 ;
+ RECT 1857.920000 1498.800000 1859.020000 1499.280000 ;
+ RECT 1853.790000 1498.800000 1854.790000 1499.280000 ;
+ RECT 1857.920000 1509.680000 1859.020000 1510.160000 ;
+ RECT 1853.790000 1509.680000 1854.790000 1510.160000 ;
+ RECT 1947.920000 1493.360000 1949.020000 1493.840000 ;
+ RECT 1947.920000 1487.920000 1949.020000 1488.400000 ;
+ RECT 1947.920000 1482.480000 1949.020000 1482.960000 ;
+ RECT 1947.920000 1477.040000 1949.020000 1477.520000 ;
+ RECT 1902.920000 1493.360000 1904.020000 1493.840000 ;
+ RECT 1902.920000 1487.920000 1904.020000 1488.400000 ;
+ RECT 1902.920000 1482.480000 1904.020000 1482.960000 ;
+ RECT 1902.920000 1477.040000 1904.020000 1477.520000 ;
+ RECT 1947.920000 1466.160000 1949.020000 1466.640000 ;
+ RECT 1947.920000 1449.840000 1949.020000 1450.320000 ;
+ RECT 1947.920000 1455.280000 1949.020000 1455.760000 ;
+ RECT 1947.920000 1460.720000 1949.020000 1461.200000 ;
+ RECT 1947.920000 1471.600000 1949.020000 1472.080000 ;
+ RECT 1902.920000 1449.840000 1904.020000 1450.320000 ;
+ RECT 1902.920000 1455.280000 1904.020000 1455.760000 ;
+ RECT 1902.920000 1460.720000 1904.020000 1461.200000 ;
+ RECT 1902.920000 1466.160000 1904.020000 1466.640000 ;
+ RECT 1902.920000 1471.600000 1904.020000 1472.080000 ;
+ RECT 1857.920000 1493.360000 1859.020000 1493.840000 ;
+ RECT 1853.790000 1493.360000 1854.790000 1493.840000 ;
+ RECT 1857.920000 1487.920000 1859.020000 1488.400000 ;
+ RECT 1853.790000 1487.920000 1854.790000 1488.400000 ;
+ RECT 1857.920000 1482.480000 1859.020000 1482.960000 ;
+ RECT 1853.790000 1482.480000 1854.790000 1482.960000 ;
+ RECT 1857.920000 1477.040000 1859.020000 1477.520000 ;
+ RECT 1853.790000 1477.040000 1854.790000 1477.520000 ;
+ RECT 1857.920000 1471.600000 1859.020000 1472.080000 ;
+ RECT 1857.920000 1466.160000 1859.020000 1466.640000 ;
+ RECT 1853.790000 1471.600000 1854.790000 1472.080000 ;
+ RECT 1853.790000 1466.160000 1854.790000 1466.640000 ;
+ RECT 1857.920000 1460.720000 1859.020000 1461.200000 ;
+ RECT 1853.790000 1460.720000 1854.790000 1461.200000 ;
+ RECT 1857.920000 1455.280000 1859.020000 1455.760000 ;
+ RECT 1853.790000 1455.280000 1854.790000 1455.760000 ;
+ RECT 1857.920000 1449.840000 1859.020000 1450.320000 ;
+ RECT 1853.790000 1449.840000 1854.790000 1450.320000 ;
+ RECT 2037.920000 1444.400000 2039.020000 1444.880000 ;
+ RECT 2037.920000 1438.960000 2039.020000 1439.440000 ;
+ RECT 2047.230000 1444.400000 2048.230000 1444.880000 ;
+ RECT 2047.230000 1438.960000 2048.230000 1439.440000 ;
+ RECT 2047.230000 1422.640000 2048.230000 1423.120000 ;
+ RECT 2047.230000 1428.080000 2048.230000 1428.560000 ;
+ RECT 2047.230000 1433.520000 2048.230000 1434.000000 ;
+ RECT 2037.920000 1433.520000 2039.020000 1434.000000 ;
+ RECT 2037.920000 1428.080000 2039.020000 1428.560000 ;
+ RECT 2037.920000 1422.640000 2039.020000 1423.120000 ;
+ RECT 2037.920000 1411.760000 2039.020000 1412.240000 ;
+ RECT 2037.920000 1417.200000 2039.020000 1417.680000 ;
+ RECT 2047.230000 1417.200000 2048.230000 1417.680000 ;
+ RECT 2047.230000 1411.760000 2048.230000 1412.240000 ;
+ RECT 2047.230000 1400.880000 2048.230000 1401.360000 ;
+ RECT 2047.230000 1406.320000 2048.230000 1406.800000 ;
+ RECT 2037.920000 1400.880000 2039.020000 1401.360000 ;
+ RECT 2037.920000 1406.320000 2039.020000 1406.800000 ;
+ RECT 1992.920000 1444.400000 1994.020000 1444.880000 ;
+ RECT 1992.920000 1438.960000 1994.020000 1439.440000 ;
+ RECT 1992.920000 1433.520000 1994.020000 1434.000000 ;
+ RECT 1992.920000 1428.080000 1994.020000 1428.560000 ;
+ RECT 1992.920000 1422.640000 1994.020000 1423.120000 ;
+ RECT 1992.920000 1400.880000 1994.020000 1401.360000 ;
+ RECT 1992.920000 1406.320000 1994.020000 1406.800000 ;
+ RECT 1992.920000 1411.760000 1994.020000 1412.240000 ;
+ RECT 1992.920000 1417.200000 1994.020000 1417.680000 ;
+ RECT 2037.920000 1395.440000 2039.020000 1395.920000 ;
+ RECT 2037.920000 1390.000000 2039.020000 1390.480000 ;
+ RECT 2047.230000 1395.440000 2048.230000 1395.920000 ;
+ RECT 2047.230000 1390.000000 2048.230000 1390.480000 ;
+ RECT 2037.920000 1379.120000 2039.020000 1379.600000 ;
+ RECT 2037.920000 1373.680000 2039.020000 1374.160000 ;
+ RECT 2047.230000 1379.120000 2048.230000 1379.600000 ;
+ RECT 2047.230000 1373.680000 2048.230000 1374.160000 ;
+ RECT 2037.920000 1384.560000 2039.020000 1385.040000 ;
+ RECT 2047.230000 1384.560000 2048.230000 1385.040000 ;
+ RECT 2047.230000 1362.800000 2048.230000 1363.280000 ;
+ RECT 2047.230000 1368.240000 2048.230000 1368.720000 ;
+ RECT 2037.920000 1368.240000 2039.020000 1368.720000 ;
+ RECT 2037.920000 1362.800000 2039.020000 1363.280000 ;
+ RECT 2037.920000 1357.360000 2039.020000 1357.840000 ;
+ RECT 2037.920000 1351.920000 2039.020000 1352.400000 ;
+ RECT 2047.230000 1357.360000 2048.230000 1357.840000 ;
+ RECT 2047.230000 1351.920000 2048.230000 1352.400000 ;
+ RECT 1992.920000 1395.440000 1994.020000 1395.920000 ;
+ RECT 1992.920000 1390.000000 1994.020000 1390.480000 ;
+ RECT 1992.920000 1384.560000 1994.020000 1385.040000 ;
+ RECT 1992.920000 1379.120000 1994.020000 1379.600000 ;
+ RECT 1992.920000 1373.680000 1994.020000 1374.160000 ;
+ RECT 1992.920000 1368.240000 1994.020000 1368.720000 ;
+ RECT 1992.920000 1362.800000 1994.020000 1363.280000 ;
+ RECT 1992.920000 1357.360000 1994.020000 1357.840000 ;
+ RECT 1992.920000 1351.920000 1994.020000 1352.400000 ;
+ RECT 1947.920000 1444.400000 1949.020000 1444.880000 ;
+ RECT 1947.920000 1438.960000 1949.020000 1439.440000 ;
+ RECT 1947.920000 1433.520000 1949.020000 1434.000000 ;
+ RECT 1947.920000 1428.080000 1949.020000 1428.560000 ;
+ RECT 1947.920000 1422.640000 1949.020000 1423.120000 ;
+ RECT 1902.920000 1444.400000 1904.020000 1444.880000 ;
+ RECT 1902.920000 1438.960000 1904.020000 1439.440000 ;
+ RECT 1902.920000 1433.520000 1904.020000 1434.000000 ;
+ RECT 1902.920000 1428.080000 1904.020000 1428.560000 ;
+ RECT 1902.920000 1422.640000 1904.020000 1423.120000 ;
+ RECT 1947.920000 1417.200000 1949.020000 1417.680000 ;
+ RECT 1947.920000 1411.760000 1949.020000 1412.240000 ;
+ RECT 1947.920000 1406.320000 1949.020000 1406.800000 ;
+ RECT 1947.920000 1400.880000 1949.020000 1401.360000 ;
+ RECT 1902.920000 1411.760000 1904.020000 1412.240000 ;
+ RECT 1902.920000 1406.320000 1904.020000 1406.800000 ;
+ RECT 1902.920000 1400.880000 1904.020000 1401.360000 ;
+ RECT 1902.920000 1417.200000 1904.020000 1417.680000 ;
+ RECT 1857.920000 1444.400000 1859.020000 1444.880000 ;
+ RECT 1853.790000 1444.400000 1854.790000 1444.880000 ;
+ RECT 1857.920000 1438.960000 1859.020000 1439.440000 ;
+ RECT 1853.790000 1438.960000 1854.790000 1439.440000 ;
+ RECT 1857.920000 1433.520000 1859.020000 1434.000000 ;
+ RECT 1853.790000 1433.520000 1854.790000 1434.000000 ;
+ RECT 1857.920000 1422.640000 1859.020000 1423.120000 ;
+ RECT 1853.790000 1422.640000 1854.790000 1423.120000 ;
+ RECT 1853.790000 1428.080000 1854.790000 1428.560000 ;
+ RECT 1857.920000 1428.080000 1859.020000 1428.560000 ;
+ RECT 1857.920000 1417.200000 1859.020000 1417.680000 ;
+ RECT 1853.790000 1417.200000 1854.790000 1417.680000 ;
+ RECT 1857.920000 1411.760000 1859.020000 1412.240000 ;
+ RECT 1853.790000 1411.760000 1854.790000 1412.240000 ;
+ RECT 1857.920000 1406.320000 1859.020000 1406.800000 ;
+ RECT 1853.790000 1406.320000 1854.790000 1406.800000 ;
+ RECT 1857.920000 1400.880000 1859.020000 1401.360000 ;
+ RECT 1853.790000 1400.880000 1854.790000 1401.360000 ;
+ RECT 1947.920000 1395.440000 1949.020000 1395.920000 ;
+ RECT 1947.920000 1390.000000 1949.020000 1390.480000 ;
+ RECT 1947.920000 1384.560000 1949.020000 1385.040000 ;
+ RECT 1947.920000 1379.120000 1949.020000 1379.600000 ;
+ RECT 1947.920000 1373.680000 1949.020000 1374.160000 ;
+ RECT 1902.920000 1395.440000 1904.020000 1395.920000 ;
+ RECT 1902.920000 1390.000000 1904.020000 1390.480000 ;
+ RECT 1902.920000 1384.560000 1904.020000 1385.040000 ;
+ RECT 1902.920000 1379.120000 1904.020000 1379.600000 ;
+ RECT 1902.920000 1373.680000 1904.020000 1374.160000 ;
+ RECT 1947.920000 1351.920000 1949.020000 1352.400000 ;
+ RECT 1947.920000 1357.360000 1949.020000 1357.840000 ;
+ RECT 1947.920000 1362.800000 1949.020000 1363.280000 ;
+ RECT 1947.920000 1368.240000 1949.020000 1368.720000 ;
+ RECT 1902.920000 1351.920000 1904.020000 1352.400000 ;
+ RECT 1902.920000 1357.360000 1904.020000 1357.840000 ;
+ RECT 1902.920000 1362.800000 1904.020000 1363.280000 ;
+ RECT 1902.920000 1368.240000 1904.020000 1368.720000 ;
+ RECT 1857.920000 1395.440000 1859.020000 1395.920000 ;
+ RECT 1853.790000 1395.440000 1854.790000 1395.920000 ;
+ RECT 1857.920000 1390.000000 1859.020000 1390.480000 ;
+ RECT 1853.790000 1390.000000 1854.790000 1390.480000 ;
+ RECT 1857.920000 1379.120000 1859.020000 1379.600000 ;
+ RECT 1853.790000 1379.120000 1854.790000 1379.600000 ;
+ RECT 1857.920000 1373.680000 1859.020000 1374.160000 ;
+ RECT 1853.790000 1373.680000 1854.790000 1374.160000 ;
+ RECT 1857.920000 1384.560000 1859.020000 1385.040000 ;
+ RECT 1853.790000 1384.560000 1854.790000 1385.040000 ;
+ RECT 1857.920000 1368.240000 1859.020000 1368.720000 ;
+ RECT 1853.790000 1368.240000 1854.790000 1368.720000 ;
+ RECT 1857.920000 1362.800000 1859.020000 1363.280000 ;
+ RECT 1853.790000 1362.800000 1854.790000 1363.280000 ;
+ RECT 1857.920000 1357.360000 1859.020000 1357.840000 ;
+ RECT 1857.920000 1351.920000 1859.020000 1352.400000 ;
+ RECT 1853.790000 1357.360000 1854.790000 1357.840000 ;
+ RECT 1853.790000 1351.920000 1854.790000 1352.400000 ;
+ RECT 1850.960000 1542.280000 2051.060000 1543.280000 ;
+ RECT 1850.960000 1349.910000 2051.060000 1350.910000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 1347.060000 1854.790000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 1546.320000 1854.790000 1547.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 1347.060000 2048.230000 1348.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 1546.320000 2048.230000 1547.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1349.910000 1851.960000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1349.910000 2051.060000 1350.910000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1542.280000 1851.960000 1543.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1542.280000 2051.060000 1543.280000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 1149.650000 2039.020000 1343.020000 ;
+ RECT 1992.920000 1149.650000 1994.020000 1343.020000 ;
+ RECT 2047.230000 1146.800000 2048.230000 1347.060000 ;
+ RECT 1947.920000 1149.650000 1949.020000 1343.020000 ;
+ RECT 1902.920000 1149.650000 1904.020000 1343.020000 ;
+ RECT 1857.920000 1149.650000 1859.020000 1343.020000 ;
+ RECT 1853.790000 1146.800000 1854.790000 1347.060000 ;
+ LAYER met3 ;
+ RECT 2037.920000 1336.620000 2039.020000 1337.100000 ;
+ RECT 2047.230000 1336.620000 2048.230000 1337.100000 ;
+ RECT 2047.230000 1325.740000 2048.230000 1326.220000 ;
+ RECT 2047.230000 1331.180000 2048.230000 1331.660000 ;
+ RECT 2037.920000 1331.180000 2039.020000 1331.660000 ;
+ RECT 2037.920000 1325.740000 2039.020000 1326.220000 ;
+ RECT 2037.920000 1320.300000 2039.020000 1320.780000 ;
+ RECT 2037.920000 1314.860000 2039.020000 1315.340000 ;
+ RECT 2047.230000 1320.300000 2048.230000 1320.780000 ;
+ RECT 2047.230000 1314.860000 2048.230000 1315.340000 ;
+ RECT 2037.920000 1298.540000 2039.020000 1299.020000 ;
+ RECT 2037.920000 1303.980000 2039.020000 1304.460000 ;
+ RECT 2047.230000 1303.980000 2048.230000 1304.460000 ;
+ RECT 2047.230000 1298.540000 2048.230000 1299.020000 ;
+ RECT 2037.920000 1309.420000 2039.020000 1309.900000 ;
+ RECT 2047.230000 1309.420000 2048.230000 1309.900000 ;
+ RECT 1992.920000 1336.620000 1994.020000 1337.100000 ;
+ RECT 1992.920000 1331.180000 1994.020000 1331.660000 ;
+ RECT 1992.920000 1325.740000 1994.020000 1326.220000 ;
+ RECT 1992.920000 1320.300000 1994.020000 1320.780000 ;
+ RECT 1992.920000 1298.540000 1994.020000 1299.020000 ;
+ RECT 1992.920000 1303.980000 1994.020000 1304.460000 ;
+ RECT 1992.920000 1309.420000 1994.020000 1309.900000 ;
+ RECT 1992.920000 1314.860000 1994.020000 1315.340000 ;
+ RECT 2047.230000 1287.660000 2048.230000 1288.140000 ;
+ RECT 2047.230000 1293.100000 2048.230000 1293.580000 ;
+ RECT 2037.920000 1293.100000 2039.020000 1293.580000 ;
+ RECT 2037.920000 1287.660000 2039.020000 1288.140000 ;
+ RECT 2037.920000 1282.220000 2039.020000 1282.700000 ;
+ RECT 2037.920000 1276.780000 2039.020000 1277.260000 ;
+ RECT 2047.230000 1282.220000 2048.230000 1282.700000 ;
+ RECT 2047.230000 1276.780000 2048.230000 1277.260000 ;
+ RECT 2047.230000 1260.460000 2048.230000 1260.940000 ;
+ RECT 2047.230000 1265.900000 2048.230000 1266.380000 ;
+ RECT 2047.230000 1271.340000 2048.230000 1271.820000 ;
+ RECT 2037.920000 1265.900000 2039.020000 1266.380000 ;
+ RECT 2037.920000 1260.460000 2039.020000 1260.940000 ;
+ RECT 2037.920000 1271.340000 2039.020000 1271.820000 ;
+ RECT 2037.920000 1255.020000 2039.020000 1255.500000 ;
+ RECT 2037.920000 1249.580000 2039.020000 1250.060000 ;
+ RECT 2047.230000 1255.020000 2048.230000 1255.500000 ;
+ RECT 2047.230000 1249.580000 2048.230000 1250.060000 ;
+ RECT 1992.920000 1293.100000 1994.020000 1293.580000 ;
+ RECT 1992.920000 1287.660000 1994.020000 1288.140000 ;
+ RECT 1992.920000 1282.220000 1994.020000 1282.700000 ;
+ RECT 1992.920000 1276.780000 1994.020000 1277.260000 ;
+ RECT 1992.920000 1265.900000 1994.020000 1266.380000 ;
+ RECT 1992.920000 1260.460000 1994.020000 1260.940000 ;
+ RECT 1992.920000 1255.020000 1994.020000 1255.500000 ;
+ RECT 1992.920000 1249.580000 1994.020000 1250.060000 ;
+ RECT 1992.920000 1271.340000 1994.020000 1271.820000 ;
+ RECT 1947.920000 1336.620000 1949.020000 1337.100000 ;
+ RECT 1947.920000 1331.180000 1949.020000 1331.660000 ;
+ RECT 1947.920000 1325.740000 1949.020000 1326.220000 ;
+ RECT 1902.920000 1336.620000 1904.020000 1337.100000 ;
+ RECT 1902.920000 1331.180000 1904.020000 1331.660000 ;
+ RECT 1902.920000 1325.740000 1904.020000 1326.220000 ;
+ RECT 1947.920000 1309.420000 1949.020000 1309.900000 ;
+ RECT 1947.920000 1303.980000 1949.020000 1304.460000 ;
+ RECT 1947.920000 1298.540000 1949.020000 1299.020000 ;
+ RECT 1947.920000 1314.860000 1949.020000 1315.340000 ;
+ RECT 1947.920000 1320.300000 1949.020000 1320.780000 ;
+ RECT 1902.920000 1320.300000 1904.020000 1320.780000 ;
+ RECT 1902.920000 1309.420000 1904.020000 1309.900000 ;
+ RECT 1902.920000 1303.980000 1904.020000 1304.460000 ;
+ RECT 1902.920000 1298.540000 1904.020000 1299.020000 ;
+ RECT 1902.920000 1314.860000 1904.020000 1315.340000 ;
+ RECT 1857.920000 1336.620000 1859.020000 1337.100000 ;
+ RECT 1853.790000 1336.620000 1854.790000 1337.100000 ;
+ RECT 1853.790000 1331.180000 1854.790000 1331.660000 ;
+ RECT 1857.920000 1331.180000 1859.020000 1331.660000 ;
+ RECT 1857.920000 1325.740000 1859.020000 1326.220000 ;
+ RECT 1853.790000 1325.740000 1854.790000 1326.220000 ;
+ RECT 1857.920000 1320.300000 1859.020000 1320.780000 ;
+ RECT 1853.790000 1320.300000 1854.790000 1320.780000 ;
+ RECT 1857.920000 1314.860000 1859.020000 1315.340000 ;
+ RECT 1853.790000 1314.860000 1854.790000 1315.340000 ;
+ RECT 1857.920000 1303.980000 1859.020000 1304.460000 ;
+ RECT 1853.790000 1303.980000 1854.790000 1304.460000 ;
+ RECT 1857.920000 1298.540000 1859.020000 1299.020000 ;
+ RECT 1853.790000 1298.540000 1854.790000 1299.020000 ;
+ RECT 1857.920000 1309.420000 1859.020000 1309.900000 ;
+ RECT 1853.790000 1309.420000 1854.790000 1309.900000 ;
+ RECT 1947.920000 1293.100000 1949.020000 1293.580000 ;
+ RECT 1947.920000 1287.660000 1949.020000 1288.140000 ;
+ RECT 1947.920000 1282.220000 1949.020000 1282.700000 ;
+ RECT 1947.920000 1276.780000 1949.020000 1277.260000 ;
+ RECT 1902.920000 1293.100000 1904.020000 1293.580000 ;
+ RECT 1902.920000 1287.660000 1904.020000 1288.140000 ;
+ RECT 1902.920000 1282.220000 1904.020000 1282.700000 ;
+ RECT 1902.920000 1276.780000 1904.020000 1277.260000 ;
+ RECT 1947.920000 1265.900000 1949.020000 1266.380000 ;
+ RECT 1947.920000 1249.580000 1949.020000 1250.060000 ;
+ RECT 1947.920000 1255.020000 1949.020000 1255.500000 ;
+ RECT 1947.920000 1260.460000 1949.020000 1260.940000 ;
+ RECT 1947.920000 1271.340000 1949.020000 1271.820000 ;
+ RECT 1902.920000 1249.580000 1904.020000 1250.060000 ;
+ RECT 1902.920000 1255.020000 1904.020000 1255.500000 ;
+ RECT 1902.920000 1260.460000 1904.020000 1260.940000 ;
+ RECT 1902.920000 1265.900000 1904.020000 1266.380000 ;
+ RECT 1902.920000 1271.340000 1904.020000 1271.820000 ;
+ RECT 1857.920000 1293.100000 1859.020000 1293.580000 ;
+ RECT 1853.790000 1293.100000 1854.790000 1293.580000 ;
+ RECT 1857.920000 1287.660000 1859.020000 1288.140000 ;
+ RECT 1853.790000 1287.660000 1854.790000 1288.140000 ;
+ RECT 1857.920000 1282.220000 1859.020000 1282.700000 ;
+ RECT 1853.790000 1282.220000 1854.790000 1282.700000 ;
+ RECT 1857.920000 1276.780000 1859.020000 1277.260000 ;
+ RECT 1853.790000 1276.780000 1854.790000 1277.260000 ;
+ RECT 1857.920000 1271.340000 1859.020000 1271.820000 ;
+ RECT 1857.920000 1265.900000 1859.020000 1266.380000 ;
+ RECT 1853.790000 1271.340000 1854.790000 1271.820000 ;
+ RECT 1853.790000 1265.900000 1854.790000 1266.380000 ;
+ RECT 1857.920000 1260.460000 1859.020000 1260.940000 ;
+ RECT 1853.790000 1260.460000 1854.790000 1260.940000 ;
+ RECT 1857.920000 1255.020000 1859.020000 1255.500000 ;
+ RECT 1853.790000 1255.020000 1854.790000 1255.500000 ;
+ RECT 1857.920000 1249.580000 1859.020000 1250.060000 ;
+ RECT 1853.790000 1249.580000 1854.790000 1250.060000 ;
+ RECT 2037.920000 1244.140000 2039.020000 1244.620000 ;
+ RECT 2037.920000 1238.700000 2039.020000 1239.180000 ;
+ RECT 2047.230000 1244.140000 2048.230000 1244.620000 ;
+ RECT 2047.230000 1238.700000 2048.230000 1239.180000 ;
+ RECT 2047.230000 1222.380000 2048.230000 1222.860000 ;
+ RECT 2047.230000 1227.820000 2048.230000 1228.300000 ;
+ RECT 2047.230000 1233.260000 2048.230000 1233.740000 ;
+ RECT 2037.920000 1233.260000 2039.020000 1233.740000 ;
+ RECT 2037.920000 1227.820000 2039.020000 1228.300000 ;
+ RECT 2037.920000 1222.380000 2039.020000 1222.860000 ;
+ RECT 2037.920000 1211.500000 2039.020000 1211.980000 ;
+ RECT 2037.920000 1216.940000 2039.020000 1217.420000 ;
+ RECT 2047.230000 1216.940000 2048.230000 1217.420000 ;
+ RECT 2047.230000 1211.500000 2048.230000 1211.980000 ;
+ RECT 2047.230000 1200.620000 2048.230000 1201.100000 ;
+ RECT 2047.230000 1206.060000 2048.230000 1206.540000 ;
+ RECT 2037.920000 1200.620000 2039.020000 1201.100000 ;
+ RECT 2037.920000 1206.060000 2039.020000 1206.540000 ;
+ RECT 1992.920000 1244.140000 1994.020000 1244.620000 ;
+ RECT 1992.920000 1238.700000 1994.020000 1239.180000 ;
+ RECT 1992.920000 1233.260000 1994.020000 1233.740000 ;
+ RECT 1992.920000 1227.820000 1994.020000 1228.300000 ;
+ RECT 1992.920000 1222.380000 1994.020000 1222.860000 ;
+ RECT 1992.920000 1200.620000 1994.020000 1201.100000 ;
+ RECT 1992.920000 1206.060000 1994.020000 1206.540000 ;
+ RECT 1992.920000 1211.500000 1994.020000 1211.980000 ;
+ RECT 1992.920000 1216.940000 1994.020000 1217.420000 ;
+ RECT 2037.920000 1195.180000 2039.020000 1195.660000 ;
+ RECT 2037.920000 1189.740000 2039.020000 1190.220000 ;
+ RECT 2047.230000 1195.180000 2048.230000 1195.660000 ;
+ RECT 2047.230000 1189.740000 2048.230000 1190.220000 ;
+ RECT 2037.920000 1178.860000 2039.020000 1179.340000 ;
+ RECT 2037.920000 1173.420000 2039.020000 1173.900000 ;
+ RECT 2047.230000 1178.860000 2048.230000 1179.340000 ;
+ RECT 2047.230000 1173.420000 2048.230000 1173.900000 ;
+ RECT 2037.920000 1184.300000 2039.020000 1184.780000 ;
+ RECT 2047.230000 1184.300000 2048.230000 1184.780000 ;
+ RECT 2047.230000 1162.540000 2048.230000 1163.020000 ;
+ RECT 2047.230000 1167.980000 2048.230000 1168.460000 ;
+ RECT 2037.920000 1167.980000 2039.020000 1168.460000 ;
+ RECT 2037.920000 1162.540000 2039.020000 1163.020000 ;
+ RECT 2037.920000 1157.100000 2039.020000 1157.580000 ;
+ RECT 2037.920000 1151.660000 2039.020000 1152.140000 ;
+ RECT 2047.230000 1157.100000 2048.230000 1157.580000 ;
+ RECT 2047.230000 1151.660000 2048.230000 1152.140000 ;
+ RECT 1992.920000 1195.180000 1994.020000 1195.660000 ;
+ RECT 1992.920000 1189.740000 1994.020000 1190.220000 ;
+ RECT 1992.920000 1184.300000 1994.020000 1184.780000 ;
+ RECT 1992.920000 1178.860000 1994.020000 1179.340000 ;
+ RECT 1992.920000 1173.420000 1994.020000 1173.900000 ;
+ RECT 1992.920000 1167.980000 1994.020000 1168.460000 ;
+ RECT 1992.920000 1162.540000 1994.020000 1163.020000 ;
+ RECT 1992.920000 1157.100000 1994.020000 1157.580000 ;
+ RECT 1992.920000 1151.660000 1994.020000 1152.140000 ;
+ RECT 1947.920000 1244.140000 1949.020000 1244.620000 ;
+ RECT 1947.920000 1238.700000 1949.020000 1239.180000 ;
+ RECT 1947.920000 1233.260000 1949.020000 1233.740000 ;
+ RECT 1947.920000 1227.820000 1949.020000 1228.300000 ;
+ RECT 1947.920000 1222.380000 1949.020000 1222.860000 ;
+ RECT 1902.920000 1244.140000 1904.020000 1244.620000 ;
+ RECT 1902.920000 1238.700000 1904.020000 1239.180000 ;
+ RECT 1902.920000 1233.260000 1904.020000 1233.740000 ;
+ RECT 1902.920000 1227.820000 1904.020000 1228.300000 ;
+ RECT 1902.920000 1222.380000 1904.020000 1222.860000 ;
+ RECT 1947.920000 1216.940000 1949.020000 1217.420000 ;
+ RECT 1947.920000 1211.500000 1949.020000 1211.980000 ;
+ RECT 1947.920000 1206.060000 1949.020000 1206.540000 ;
+ RECT 1947.920000 1200.620000 1949.020000 1201.100000 ;
+ RECT 1902.920000 1211.500000 1904.020000 1211.980000 ;
+ RECT 1902.920000 1206.060000 1904.020000 1206.540000 ;
+ RECT 1902.920000 1200.620000 1904.020000 1201.100000 ;
+ RECT 1902.920000 1216.940000 1904.020000 1217.420000 ;
+ RECT 1857.920000 1244.140000 1859.020000 1244.620000 ;
+ RECT 1853.790000 1244.140000 1854.790000 1244.620000 ;
+ RECT 1857.920000 1238.700000 1859.020000 1239.180000 ;
+ RECT 1853.790000 1238.700000 1854.790000 1239.180000 ;
+ RECT 1857.920000 1233.260000 1859.020000 1233.740000 ;
+ RECT 1853.790000 1233.260000 1854.790000 1233.740000 ;
+ RECT 1857.920000 1222.380000 1859.020000 1222.860000 ;
+ RECT 1853.790000 1222.380000 1854.790000 1222.860000 ;
+ RECT 1853.790000 1227.820000 1854.790000 1228.300000 ;
+ RECT 1857.920000 1227.820000 1859.020000 1228.300000 ;
+ RECT 1857.920000 1216.940000 1859.020000 1217.420000 ;
+ RECT 1853.790000 1216.940000 1854.790000 1217.420000 ;
+ RECT 1857.920000 1211.500000 1859.020000 1211.980000 ;
+ RECT 1853.790000 1211.500000 1854.790000 1211.980000 ;
+ RECT 1857.920000 1206.060000 1859.020000 1206.540000 ;
+ RECT 1853.790000 1206.060000 1854.790000 1206.540000 ;
+ RECT 1857.920000 1200.620000 1859.020000 1201.100000 ;
+ RECT 1853.790000 1200.620000 1854.790000 1201.100000 ;
+ RECT 1947.920000 1195.180000 1949.020000 1195.660000 ;
+ RECT 1947.920000 1189.740000 1949.020000 1190.220000 ;
+ RECT 1947.920000 1184.300000 1949.020000 1184.780000 ;
+ RECT 1947.920000 1178.860000 1949.020000 1179.340000 ;
+ RECT 1947.920000 1173.420000 1949.020000 1173.900000 ;
+ RECT 1902.920000 1195.180000 1904.020000 1195.660000 ;
+ RECT 1902.920000 1189.740000 1904.020000 1190.220000 ;
+ RECT 1902.920000 1184.300000 1904.020000 1184.780000 ;
+ RECT 1902.920000 1178.860000 1904.020000 1179.340000 ;
+ RECT 1902.920000 1173.420000 1904.020000 1173.900000 ;
+ RECT 1947.920000 1151.660000 1949.020000 1152.140000 ;
+ RECT 1947.920000 1157.100000 1949.020000 1157.580000 ;
+ RECT 1947.920000 1162.540000 1949.020000 1163.020000 ;
+ RECT 1947.920000 1167.980000 1949.020000 1168.460000 ;
+ RECT 1902.920000 1151.660000 1904.020000 1152.140000 ;
+ RECT 1902.920000 1157.100000 1904.020000 1157.580000 ;
+ RECT 1902.920000 1162.540000 1904.020000 1163.020000 ;
+ RECT 1902.920000 1167.980000 1904.020000 1168.460000 ;
+ RECT 1857.920000 1195.180000 1859.020000 1195.660000 ;
+ RECT 1853.790000 1195.180000 1854.790000 1195.660000 ;
+ RECT 1857.920000 1189.740000 1859.020000 1190.220000 ;
+ RECT 1853.790000 1189.740000 1854.790000 1190.220000 ;
+ RECT 1857.920000 1178.860000 1859.020000 1179.340000 ;
+ RECT 1853.790000 1178.860000 1854.790000 1179.340000 ;
+ RECT 1857.920000 1173.420000 1859.020000 1173.900000 ;
+ RECT 1853.790000 1173.420000 1854.790000 1173.900000 ;
+ RECT 1857.920000 1184.300000 1859.020000 1184.780000 ;
+ RECT 1853.790000 1184.300000 1854.790000 1184.780000 ;
+ RECT 1857.920000 1167.980000 1859.020000 1168.460000 ;
+ RECT 1853.790000 1167.980000 1854.790000 1168.460000 ;
+ RECT 1857.920000 1162.540000 1859.020000 1163.020000 ;
+ RECT 1853.790000 1162.540000 1854.790000 1163.020000 ;
+ RECT 1857.920000 1157.100000 1859.020000 1157.580000 ;
+ RECT 1857.920000 1151.660000 1859.020000 1152.140000 ;
+ RECT 1853.790000 1157.100000 1854.790000 1157.580000 ;
+ RECT 1853.790000 1151.660000 1854.790000 1152.140000 ;
+ RECT 1850.960000 1342.020000 2051.060000 1343.020000 ;
+ RECT 1850.960000 1149.650000 2051.060000 1150.650000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 1146.800000 1854.790000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 1346.060000 1854.790000 1347.060000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 1146.800000 2048.230000 1147.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 1346.060000 2048.230000 1347.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1149.650000 1851.960000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1149.650000 2051.060000 1150.650000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1342.020000 1851.960000 1343.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1342.020000 2051.060000 1343.020000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 949.390000 2039.020000 1142.760000 ;
+ RECT 1992.920000 949.390000 1994.020000 1142.760000 ;
+ RECT 2047.230000 946.540000 2048.230000 1146.800000 ;
+ RECT 1947.920000 949.390000 1949.020000 1142.760000 ;
+ RECT 1902.920000 949.390000 1904.020000 1142.760000 ;
+ RECT 1857.920000 949.390000 1859.020000 1142.760000 ;
+ RECT 1853.790000 946.540000 1854.790000 1146.800000 ;
+ LAYER met3 ;
+ RECT 2037.920000 1136.360000 2039.020000 1136.840000 ;
+ RECT 2047.230000 1136.360000 2048.230000 1136.840000 ;
+ RECT 2047.230000 1125.480000 2048.230000 1125.960000 ;
+ RECT 2047.230000 1130.920000 2048.230000 1131.400000 ;
+ RECT 2037.920000 1130.920000 2039.020000 1131.400000 ;
+ RECT 2037.920000 1125.480000 2039.020000 1125.960000 ;
+ RECT 2037.920000 1120.040000 2039.020000 1120.520000 ;
+ RECT 2037.920000 1114.600000 2039.020000 1115.080000 ;
+ RECT 2047.230000 1120.040000 2048.230000 1120.520000 ;
+ RECT 2047.230000 1114.600000 2048.230000 1115.080000 ;
+ RECT 2037.920000 1098.280000 2039.020000 1098.760000 ;
+ RECT 2037.920000 1103.720000 2039.020000 1104.200000 ;
+ RECT 2047.230000 1103.720000 2048.230000 1104.200000 ;
+ RECT 2047.230000 1098.280000 2048.230000 1098.760000 ;
+ RECT 2037.920000 1109.160000 2039.020000 1109.640000 ;
+ RECT 2047.230000 1109.160000 2048.230000 1109.640000 ;
+ RECT 1992.920000 1136.360000 1994.020000 1136.840000 ;
+ RECT 1992.920000 1130.920000 1994.020000 1131.400000 ;
+ RECT 1992.920000 1125.480000 1994.020000 1125.960000 ;
+ RECT 1992.920000 1120.040000 1994.020000 1120.520000 ;
+ RECT 1992.920000 1098.280000 1994.020000 1098.760000 ;
+ RECT 1992.920000 1103.720000 1994.020000 1104.200000 ;
+ RECT 1992.920000 1109.160000 1994.020000 1109.640000 ;
+ RECT 1992.920000 1114.600000 1994.020000 1115.080000 ;
+ RECT 2047.230000 1087.400000 2048.230000 1087.880000 ;
+ RECT 2047.230000 1092.840000 2048.230000 1093.320000 ;
+ RECT 2037.920000 1092.840000 2039.020000 1093.320000 ;
+ RECT 2037.920000 1087.400000 2039.020000 1087.880000 ;
+ RECT 2037.920000 1081.960000 2039.020000 1082.440000 ;
+ RECT 2037.920000 1076.520000 2039.020000 1077.000000 ;
+ RECT 2047.230000 1081.960000 2048.230000 1082.440000 ;
+ RECT 2047.230000 1076.520000 2048.230000 1077.000000 ;
+ RECT 2047.230000 1060.200000 2048.230000 1060.680000 ;
+ RECT 2047.230000 1065.640000 2048.230000 1066.120000 ;
+ RECT 2047.230000 1071.080000 2048.230000 1071.560000 ;
+ RECT 2037.920000 1065.640000 2039.020000 1066.120000 ;
+ RECT 2037.920000 1060.200000 2039.020000 1060.680000 ;
+ RECT 2037.920000 1071.080000 2039.020000 1071.560000 ;
+ RECT 2037.920000 1054.760000 2039.020000 1055.240000 ;
+ RECT 2037.920000 1049.320000 2039.020000 1049.800000 ;
+ RECT 2047.230000 1054.760000 2048.230000 1055.240000 ;
+ RECT 2047.230000 1049.320000 2048.230000 1049.800000 ;
+ RECT 1992.920000 1092.840000 1994.020000 1093.320000 ;
+ RECT 1992.920000 1087.400000 1994.020000 1087.880000 ;
+ RECT 1992.920000 1081.960000 1994.020000 1082.440000 ;
+ RECT 1992.920000 1076.520000 1994.020000 1077.000000 ;
+ RECT 1992.920000 1065.640000 1994.020000 1066.120000 ;
+ RECT 1992.920000 1060.200000 1994.020000 1060.680000 ;
+ RECT 1992.920000 1054.760000 1994.020000 1055.240000 ;
+ RECT 1992.920000 1049.320000 1994.020000 1049.800000 ;
+ RECT 1992.920000 1071.080000 1994.020000 1071.560000 ;
+ RECT 1947.920000 1136.360000 1949.020000 1136.840000 ;
+ RECT 1947.920000 1130.920000 1949.020000 1131.400000 ;
+ RECT 1947.920000 1125.480000 1949.020000 1125.960000 ;
+ RECT 1902.920000 1136.360000 1904.020000 1136.840000 ;
+ RECT 1902.920000 1130.920000 1904.020000 1131.400000 ;
+ RECT 1902.920000 1125.480000 1904.020000 1125.960000 ;
+ RECT 1947.920000 1109.160000 1949.020000 1109.640000 ;
+ RECT 1947.920000 1103.720000 1949.020000 1104.200000 ;
+ RECT 1947.920000 1098.280000 1949.020000 1098.760000 ;
+ RECT 1947.920000 1114.600000 1949.020000 1115.080000 ;
+ RECT 1947.920000 1120.040000 1949.020000 1120.520000 ;
+ RECT 1902.920000 1120.040000 1904.020000 1120.520000 ;
+ RECT 1902.920000 1109.160000 1904.020000 1109.640000 ;
+ RECT 1902.920000 1103.720000 1904.020000 1104.200000 ;
+ RECT 1902.920000 1098.280000 1904.020000 1098.760000 ;
+ RECT 1902.920000 1114.600000 1904.020000 1115.080000 ;
+ RECT 1857.920000 1136.360000 1859.020000 1136.840000 ;
+ RECT 1853.790000 1136.360000 1854.790000 1136.840000 ;
+ RECT 1853.790000 1130.920000 1854.790000 1131.400000 ;
+ RECT 1857.920000 1130.920000 1859.020000 1131.400000 ;
+ RECT 1857.920000 1125.480000 1859.020000 1125.960000 ;
+ RECT 1853.790000 1125.480000 1854.790000 1125.960000 ;
+ RECT 1857.920000 1120.040000 1859.020000 1120.520000 ;
+ RECT 1853.790000 1120.040000 1854.790000 1120.520000 ;
+ RECT 1857.920000 1114.600000 1859.020000 1115.080000 ;
+ RECT 1853.790000 1114.600000 1854.790000 1115.080000 ;
+ RECT 1857.920000 1103.720000 1859.020000 1104.200000 ;
+ RECT 1853.790000 1103.720000 1854.790000 1104.200000 ;
+ RECT 1857.920000 1098.280000 1859.020000 1098.760000 ;
+ RECT 1853.790000 1098.280000 1854.790000 1098.760000 ;
+ RECT 1857.920000 1109.160000 1859.020000 1109.640000 ;
+ RECT 1853.790000 1109.160000 1854.790000 1109.640000 ;
+ RECT 1947.920000 1092.840000 1949.020000 1093.320000 ;
+ RECT 1947.920000 1087.400000 1949.020000 1087.880000 ;
+ RECT 1947.920000 1081.960000 1949.020000 1082.440000 ;
+ RECT 1947.920000 1076.520000 1949.020000 1077.000000 ;
+ RECT 1902.920000 1092.840000 1904.020000 1093.320000 ;
+ RECT 1902.920000 1087.400000 1904.020000 1087.880000 ;
+ RECT 1902.920000 1081.960000 1904.020000 1082.440000 ;
+ RECT 1902.920000 1076.520000 1904.020000 1077.000000 ;
+ RECT 1947.920000 1065.640000 1949.020000 1066.120000 ;
+ RECT 1947.920000 1049.320000 1949.020000 1049.800000 ;
+ RECT 1947.920000 1054.760000 1949.020000 1055.240000 ;
+ RECT 1947.920000 1060.200000 1949.020000 1060.680000 ;
+ RECT 1947.920000 1071.080000 1949.020000 1071.560000 ;
+ RECT 1902.920000 1049.320000 1904.020000 1049.800000 ;
+ RECT 1902.920000 1054.760000 1904.020000 1055.240000 ;
+ RECT 1902.920000 1060.200000 1904.020000 1060.680000 ;
+ RECT 1902.920000 1065.640000 1904.020000 1066.120000 ;
+ RECT 1902.920000 1071.080000 1904.020000 1071.560000 ;
+ RECT 1857.920000 1092.840000 1859.020000 1093.320000 ;
+ RECT 1853.790000 1092.840000 1854.790000 1093.320000 ;
+ RECT 1857.920000 1087.400000 1859.020000 1087.880000 ;
+ RECT 1853.790000 1087.400000 1854.790000 1087.880000 ;
+ RECT 1857.920000 1081.960000 1859.020000 1082.440000 ;
+ RECT 1853.790000 1081.960000 1854.790000 1082.440000 ;
+ RECT 1857.920000 1076.520000 1859.020000 1077.000000 ;
+ RECT 1853.790000 1076.520000 1854.790000 1077.000000 ;
+ RECT 1857.920000 1071.080000 1859.020000 1071.560000 ;
+ RECT 1857.920000 1065.640000 1859.020000 1066.120000 ;
+ RECT 1853.790000 1071.080000 1854.790000 1071.560000 ;
+ RECT 1853.790000 1065.640000 1854.790000 1066.120000 ;
+ RECT 1857.920000 1060.200000 1859.020000 1060.680000 ;
+ RECT 1853.790000 1060.200000 1854.790000 1060.680000 ;
+ RECT 1857.920000 1054.760000 1859.020000 1055.240000 ;
+ RECT 1853.790000 1054.760000 1854.790000 1055.240000 ;
+ RECT 1857.920000 1049.320000 1859.020000 1049.800000 ;
+ RECT 1853.790000 1049.320000 1854.790000 1049.800000 ;
+ RECT 2037.920000 1043.880000 2039.020000 1044.360000 ;
+ RECT 2037.920000 1038.440000 2039.020000 1038.920000 ;
+ RECT 2047.230000 1043.880000 2048.230000 1044.360000 ;
+ RECT 2047.230000 1038.440000 2048.230000 1038.920000 ;
+ RECT 2047.230000 1022.120000 2048.230000 1022.600000 ;
+ RECT 2047.230000 1027.560000 2048.230000 1028.040000 ;
+ RECT 2047.230000 1033.000000 2048.230000 1033.480000 ;
+ RECT 2037.920000 1033.000000 2039.020000 1033.480000 ;
+ RECT 2037.920000 1027.560000 2039.020000 1028.040000 ;
+ RECT 2037.920000 1022.120000 2039.020000 1022.600000 ;
+ RECT 2037.920000 1011.240000 2039.020000 1011.720000 ;
+ RECT 2037.920000 1016.680000 2039.020000 1017.160000 ;
+ RECT 2047.230000 1016.680000 2048.230000 1017.160000 ;
+ RECT 2047.230000 1011.240000 2048.230000 1011.720000 ;
+ RECT 2047.230000 1000.360000 2048.230000 1000.840000 ;
+ RECT 2047.230000 1005.800000 2048.230000 1006.280000 ;
+ RECT 2037.920000 1000.360000 2039.020000 1000.840000 ;
+ RECT 2037.920000 1005.800000 2039.020000 1006.280000 ;
+ RECT 1992.920000 1043.880000 1994.020000 1044.360000 ;
+ RECT 1992.920000 1038.440000 1994.020000 1038.920000 ;
+ RECT 1992.920000 1033.000000 1994.020000 1033.480000 ;
+ RECT 1992.920000 1027.560000 1994.020000 1028.040000 ;
+ RECT 1992.920000 1022.120000 1994.020000 1022.600000 ;
+ RECT 1992.920000 1000.360000 1994.020000 1000.840000 ;
+ RECT 1992.920000 1005.800000 1994.020000 1006.280000 ;
+ RECT 1992.920000 1011.240000 1994.020000 1011.720000 ;
+ RECT 1992.920000 1016.680000 1994.020000 1017.160000 ;
+ RECT 2037.920000 994.920000 2039.020000 995.400000 ;
+ RECT 2037.920000 989.480000 2039.020000 989.960000 ;
+ RECT 2047.230000 994.920000 2048.230000 995.400000 ;
+ RECT 2047.230000 989.480000 2048.230000 989.960000 ;
+ RECT 2037.920000 978.600000 2039.020000 979.080000 ;
+ RECT 2037.920000 973.160000 2039.020000 973.640000 ;
+ RECT 2047.230000 978.600000 2048.230000 979.080000 ;
+ RECT 2047.230000 973.160000 2048.230000 973.640000 ;
+ RECT 2037.920000 984.040000 2039.020000 984.520000 ;
+ RECT 2047.230000 984.040000 2048.230000 984.520000 ;
+ RECT 2047.230000 962.280000 2048.230000 962.760000 ;
+ RECT 2047.230000 967.720000 2048.230000 968.200000 ;
+ RECT 2037.920000 967.720000 2039.020000 968.200000 ;
+ RECT 2037.920000 962.280000 2039.020000 962.760000 ;
+ RECT 2037.920000 956.840000 2039.020000 957.320000 ;
+ RECT 2037.920000 951.400000 2039.020000 951.880000 ;
+ RECT 2047.230000 956.840000 2048.230000 957.320000 ;
+ RECT 2047.230000 951.400000 2048.230000 951.880000 ;
+ RECT 1992.920000 994.920000 1994.020000 995.400000 ;
+ RECT 1992.920000 989.480000 1994.020000 989.960000 ;
+ RECT 1992.920000 984.040000 1994.020000 984.520000 ;
+ RECT 1992.920000 978.600000 1994.020000 979.080000 ;
+ RECT 1992.920000 973.160000 1994.020000 973.640000 ;
+ RECT 1992.920000 967.720000 1994.020000 968.200000 ;
+ RECT 1992.920000 962.280000 1994.020000 962.760000 ;
+ RECT 1992.920000 956.840000 1994.020000 957.320000 ;
+ RECT 1992.920000 951.400000 1994.020000 951.880000 ;
+ RECT 1947.920000 1043.880000 1949.020000 1044.360000 ;
+ RECT 1947.920000 1038.440000 1949.020000 1038.920000 ;
+ RECT 1947.920000 1033.000000 1949.020000 1033.480000 ;
+ RECT 1947.920000 1027.560000 1949.020000 1028.040000 ;
+ RECT 1947.920000 1022.120000 1949.020000 1022.600000 ;
+ RECT 1902.920000 1043.880000 1904.020000 1044.360000 ;
+ RECT 1902.920000 1038.440000 1904.020000 1038.920000 ;
+ RECT 1902.920000 1033.000000 1904.020000 1033.480000 ;
+ RECT 1902.920000 1027.560000 1904.020000 1028.040000 ;
+ RECT 1902.920000 1022.120000 1904.020000 1022.600000 ;
+ RECT 1947.920000 1016.680000 1949.020000 1017.160000 ;
+ RECT 1947.920000 1011.240000 1949.020000 1011.720000 ;
+ RECT 1947.920000 1005.800000 1949.020000 1006.280000 ;
+ RECT 1947.920000 1000.360000 1949.020000 1000.840000 ;
+ RECT 1902.920000 1011.240000 1904.020000 1011.720000 ;
+ RECT 1902.920000 1005.800000 1904.020000 1006.280000 ;
+ RECT 1902.920000 1000.360000 1904.020000 1000.840000 ;
+ RECT 1902.920000 1016.680000 1904.020000 1017.160000 ;
+ RECT 1857.920000 1043.880000 1859.020000 1044.360000 ;
+ RECT 1853.790000 1043.880000 1854.790000 1044.360000 ;
+ RECT 1857.920000 1038.440000 1859.020000 1038.920000 ;
+ RECT 1853.790000 1038.440000 1854.790000 1038.920000 ;
+ RECT 1857.920000 1033.000000 1859.020000 1033.480000 ;
+ RECT 1853.790000 1033.000000 1854.790000 1033.480000 ;
+ RECT 1857.920000 1022.120000 1859.020000 1022.600000 ;
+ RECT 1853.790000 1022.120000 1854.790000 1022.600000 ;
+ RECT 1853.790000 1027.560000 1854.790000 1028.040000 ;
+ RECT 1857.920000 1027.560000 1859.020000 1028.040000 ;
+ RECT 1857.920000 1016.680000 1859.020000 1017.160000 ;
+ RECT 1853.790000 1016.680000 1854.790000 1017.160000 ;
+ RECT 1857.920000 1011.240000 1859.020000 1011.720000 ;
+ RECT 1853.790000 1011.240000 1854.790000 1011.720000 ;
+ RECT 1857.920000 1005.800000 1859.020000 1006.280000 ;
+ RECT 1853.790000 1005.800000 1854.790000 1006.280000 ;
+ RECT 1857.920000 1000.360000 1859.020000 1000.840000 ;
+ RECT 1853.790000 1000.360000 1854.790000 1000.840000 ;
+ RECT 1947.920000 994.920000 1949.020000 995.400000 ;
+ RECT 1947.920000 989.480000 1949.020000 989.960000 ;
+ RECT 1947.920000 984.040000 1949.020000 984.520000 ;
+ RECT 1947.920000 978.600000 1949.020000 979.080000 ;
+ RECT 1947.920000 973.160000 1949.020000 973.640000 ;
+ RECT 1902.920000 994.920000 1904.020000 995.400000 ;
+ RECT 1902.920000 989.480000 1904.020000 989.960000 ;
+ RECT 1902.920000 984.040000 1904.020000 984.520000 ;
+ RECT 1902.920000 978.600000 1904.020000 979.080000 ;
+ RECT 1902.920000 973.160000 1904.020000 973.640000 ;
+ RECT 1947.920000 951.400000 1949.020000 951.880000 ;
+ RECT 1947.920000 956.840000 1949.020000 957.320000 ;
+ RECT 1947.920000 962.280000 1949.020000 962.760000 ;
+ RECT 1947.920000 967.720000 1949.020000 968.200000 ;
+ RECT 1902.920000 951.400000 1904.020000 951.880000 ;
+ RECT 1902.920000 956.840000 1904.020000 957.320000 ;
+ RECT 1902.920000 962.280000 1904.020000 962.760000 ;
+ RECT 1902.920000 967.720000 1904.020000 968.200000 ;
+ RECT 1857.920000 994.920000 1859.020000 995.400000 ;
+ RECT 1853.790000 994.920000 1854.790000 995.400000 ;
+ RECT 1857.920000 989.480000 1859.020000 989.960000 ;
+ RECT 1853.790000 989.480000 1854.790000 989.960000 ;
+ RECT 1857.920000 978.600000 1859.020000 979.080000 ;
+ RECT 1853.790000 978.600000 1854.790000 979.080000 ;
+ RECT 1857.920000 973.160000 1859.020000 973.640000 ;
+ RECT 1853.790000 973.160000 1854.790000 973.640000 ;
+ RECT 1857.920000 984.040000 1859.020000 984.520000 ;
+ RECT 1853.790000 984.040000 1854.790000 984.520000 ;
+ RECT 1857.920000 967.720000 1859.020000 968.200000 ;
+ RECT 1853.790000 967.720000 1854.790000 968.200000 ;
+ RECT 1857.920000 962.280000 1859.020000 962.760000 ;
+ RECT 1853.790000 962.280000 1854.790000 962.760000 ;
+ RECT 1857.920000 956.840000 1859.020000 957.320000 ;
+ RECT 1857.920000 951.400000 1859.020000 951.880000 ;
+ RECT 1853.790000 956.840000 1854.790000 957.320000 ;
+ RECT 1853.790000 951.400000 1854.790000 951.880000 ;
+ RECT 1850.960000 1141.760000 2051.060000 1142.760000 ;
+ RECT 1850.960000 949.390000 2051.060000 950.390000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 946.540000 1854.790000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 1145.800000 1854.790000 1146.800000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 946.540000 2048.230000 947.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 1145.800000 2048.230000 1146.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 949.390000 1851.960000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 949.390000 2051.060000 950.390000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1141.760000 1851.960000 1142.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1141.760000 2051.060000 1142.760000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 749.130000 2039.020000 942.500000 ;
+ RECT 1992.920000 749.130000 1994.020000 942.500000 ;
+ RECT 2047.230000 746.280000 2048.230000 946.540000 ;
+ RECT 1947.920000 749.130000 1949.020000 942.500000 ;
+ RECT 1902.920000 749.130000 1904.020000 942.500000 ;
+ RECT 1857.920000 749.130000 1859.020000 942.500000 ;
+ RECT 1853.790000 746.280000 1854.790000 946.540000 ;
+ LAYER met3 ;
+ RECT 2037.920000 936.100000 2039.020000 936.580000 ;
+ RECT 2047.230000 936.100000 2048.230000 936.580000 ;
+ RECT 2047.230000 925.220000 2048.230000 925.700000 ;
+ RECT 2047.230000 930.660000 2048.230000 931.140000 ;
+ RECT 2037.920000 930.660000 2039.020000 931.140000 ;
+ RECT 2037.920000 925.220000 2039.020000 925.700000 ;
+ RECT 2037.920000 919.780000 2039.020000 920.260000 ;
+ RECT 2037.920000 914.340000 2039.020000 914.820000 ;
+ RECT 2047.230000 919.780000 2048.230000 920.260000 ;
+ RECT 2047.230000 914.340000 2048.230000 914.820000 ;
+ RECT 2037.920000 898.020000 2039.020000 898.500000 ;
+ RECT 2037.920000 903.460000 2039.020000 903.940000 ;
+ RECT 2047.230000 903.460000 2048.230000 903.940000 ;
+ RECT 2047.230000 898.020000 2048.230000 898.500000 ;
+ RECT 2037.920000 908.900000 2039.020000 909.380000 ;
+ RECT 2047.230000 908.900000 2048.230000 909.380000 ;
+ RECT 1992.920000 936.100000 1994.020000 936.580000 ;
+ RECT 1992.920000 930.660000 1994.020000 931.140000 ;
+ RECT 1992.920000 925.220000 1994.020000 925.700000 ;
+ RECT 1992.920000 919.780000 1994.020000 920.260000 ;
+ RECT 1992.920000 898.020000 1994.020000 898.500000 ;
+ RECT 1992.920000 903.460000 1994.020000 903.940000 ;
+ RECT 1992.920000 908.900000 1994.020000 909.380000 ;
+ RECT 1992.920000 914.340000 1994.020000 914.820000 ;
+ RECT 2047.230000 887.140000 2048.230000 887.620000 ;
+ RECT 2047.230000 892.580000 2048.230000 893.060000 ;
+ RECT 2037.920000 892.580000 2039.020000 893.060000 ;
+ RECT 2037.920000 887.140000 2039.020000 887.620000 ;
+ RECT 2037.920000 881.700000 2039.020000 882.180000 ;
+ RECT 2037.920000 876.260000 2039.020000 876.740000 ;
+ RECT 2047.230000 881.700000 2048.230000 882.180000 ;
+ RECT 2047.230000 876.260000 2048.230000 876.740000 ;
+ RECT 2047.230000 859.940000 2048.230000 860.420000 ;
+ RECT 2047.230000 865.380000 2048.230000 865.860000 ;
+ RECT 2047.230000 870.820000 2048.230000 871.300000 ;
+ RECT 2037.920000 865.380000 2039.020000 865.860000 ;
+ RECT 2037.920000 859.940000 2039.020000 860.420000 ;
+ RECT 2037.920000 870.820000 2039.020000 871.300000 ;
+ RECT 2037.920000 854.500000 2039.020000 854.980000 ;
+ RECT 2037.920000 849.060000 2039.020000 849.540000 ;
+ RECT 2047.230000 854.500000 2048.230000 854.980000 ;
+ RECT 2047.230000 849.060000 2048.230000 849.540000 ;
+ RECT 1992.920000 892.580000 1994.020000 893.060000 ;
+ RECT 1992.920000 887.140000 1994.020000 887.620000 ;
+ RECT 1992.920000 881.700000 1994.020000 882.180000 ;
+ RECT 1992.920000 876.260000 1994.020000 876.740000 ;
+ RECT 1992.920000 865.380000 1994.020000 865.860000 ;
+ RECT 1992.920000 859.940000 1994.020000 860.420000 ;
+ RECT 1992.920000 854.500000 1994.020000 854.980000 ;
+ RECT 1992.920000 849.060000 1994.020000 849.540000 ;
+ RECT 1992.920000 870.820000 1994.020000 871.300000 ;
+ RECT 1947.920000 936.100000 1949.020000 936.580000 ;
+ RECT 1947.920000 930.660000 1949.020000 931.140000 ;
+ RECT 1947.920000 925.220000 1949.020000 925.700000 ;
+ RECT 1902.920000 936.100000 1904.020000 936.580000 ;
+ RECT 1902.920000 930.660000 1904.020000 931.140000 ;
+ RECT 1902.920000 925.220000 1904.020000 925.700000 ;
+ RECT 1947.920000 908.900000 1949.020000 909.380000 ;
+ RECT 1947.920000 903.460000 1949.020000 903.940000 ;
+ RECT 1947.920000 898.020000 1949.020000 898.500000 ;
+ RECT 1947.920000 914.340000 1949.020000 914.820000 ;
+ RECT 1947.920000 919.780000 1949.020000 920.260000 ;
+ RECT 1902.920000 919.780000 1904.020000 920.260000 ;
+ RECT 1902.920000 908.900000 1904.020000 909.380000 ;
+ RECT 1902.920000 903.460000 1904.020000 903.940000 ;
+ RECT 1902.920000 898.020000 1904.020000 898.500000 ;
+ RECT 1902.920000 914.340000 1904.020000 914.820000 ;
+ RECT 1857.920000 936.100000 1859.020000 936.580000 ;
+ RECT 1853.790000 936.100000 1854.790000 936.580000 ;
+ RECT 1853.790000 930.660000 1854.790000 931.140000 ;
+ RECT 1857.920000 930.660000 1859.020000 931.140000 ;
+ RECT 1857.920000 925.220000 1859.020000 925.700000 ;
+ RECT 1853.790000 925.220000 1854.790000 925.700000 ;
+ RECT 1857.920000 919.780000 1859.020000 920.260000 ;
+ RECT 1853.790000 919.780000 1854.790000 920.260000 ;
+ RECT 1857.920000 914.340000 1859.020000 914.820000 ;
+ RECT 1853.790000 914.340000 1854.790000 914.820000 ;
+ RECT 1857.920000 903.460000 1859.020000 903.940000 ;
+ RECT 1853.790000 903.460000 1854.790000 903.940000 ;
+ RECT 1857.920000 898.020000 1859.020000 898.500000 ;
+ RECT 1853.790000 898.020000 1854.790000 898.500000 ;
+ RECT 1857.920000 908.900000 1859.020000 909.380000 ;
+ RECT 1853.790000 908.900000 1854.790000 909.380000 ;
+ RECT 1947.920000 892.580000 1949.020000 893.060000 ;
+ RECT 1947.920000 887.140000 1949.020000 887.620000 ;
+ RECT 1947.920000 881.700000 1949.020000 882.180000 ;
+ RECT 1947.920000 876.260000 1949.020000 876.740000 ;
+ RECT 1902.920000 892.580000 1904.020000 893.060000 ;
+ RECT 1902.920000 887.140000 1904.020000 887.620000 ;
+ RECT 1902.920000 881.700000 1904.020000 882.180000 ;
+ RECT 1902.920000 876.260000 1904.020000 876.740000 ;
+ RECT 1947.920000 865.380000 1949.020000 865.860000 ;
+ RECT 1947.920000 849.060000 1949.020000 849.540000 ;
+ RECT 1947.920000 854.500000 1949.020000 854.980000 ;
+ RECT 1947.920000 859.940000 1949.020000 860.420000 ;
+ RECT 1947.920000 870.820000 1949.020000 871.300000 ;
+ RECT 1902.920000 849.060000 1904.020000 849.540000 ;
+ RECT 1902.920000 854.500000 1904.020000 854.980000 ;
+ RECT 1902.920000 859.940000 1904.020000 860.420000 ;
+ RECT 1902.920000 865.380000 1904.020000 865.860000 ;
+ RECT 1902.920000 870.820000 1904.020000 871.300000 ;
+ RECT 1857.920000 892.580000 1859.020000 893.060000 ;
+ RECT 1853.790000 892.580000 1854.790000 893.060000 ;
+ RECT 1857.920000 887.140000 1859.020000 887.620000 ;
+ RECT 1853.790000 887.140000 1854.790000 887.620000 ;
+ RECT 1857.920000 881.700000 1859.020000 882.180000 ;
+ RECT 1853.790000 881.700000 1854.790000 882.180000 ;
+ RECT 1857.920000 876.260000 1859.020000 876.740000 ;
+ RECT 1853.790000 876.260000 1854.790000 876.740000 ;
+ RECT 1857.920000 870.820000 1859.020000 871.300000 ;
+ RECT 1857.920000 865.380000 1859.020000 865.860000 ;
+ RECT 1853.790000 870.820000 1854.790000 871.300000 ;
+ RECT 1853.790000 865.380000 1854.790000 865.860000 ;
+ RECT 1857.920000 859.940000 1859.020000 860.420000 ;
+ RECT 1853.790000 859.940000 1854.790000 860.420000 ;
+ RECT 1857.920000 854.500000 1859.020000 854.980000 ;
+ RECT 1853.790000 854.500000 1854.790000 854.980000 ;
+ RECT 1857.920000 849.060000 1859.020000 849.540000 ;
+ RECT 1853.790000 849.060000 1854.790000 849.540000 ;
+ RECT 2037.920000 843.620000 2039.020000 844.100000 ;
+ RECT 2037.920000 838.180000 2039.020000 838.660000 ;
+ RECT 2047.230000 843.620000 2048.230000 844.100000 ;
+ RECT 2047.230000 838.180000 2048.230000 838.660000 ;
+ RECT 2047.230000 821.860000 2048.230000 822.340000 ;
+ RECT 2047.230000 827.300000 2048.230000 827.780000 ;
+ RECT 2047.230000 832.740000 2048.230000 833.220000 ;
+ RECT 2037.920000 832.740000 2039.020000 833.220000 ;
+ RECT 2037.920000 827.300000 2039.020000 827.780000 ;
+ RECT 2037.920000 821.860000 2039.020000 822.340000 ;
+ RECT 2037.920000 810.980000 2039.020000 811.460000 ;
+ RECT 2037.920000 816.420000 2039.020000 816.900000 ;
+ RECT 2047.230000 816.420000 2048.230000 816.900000 ;
+ RECT 2047.230000 810.980000 2048.230000 811.460000 ;
+ RECT 2047.230000 800.100000 2048.230000 800.580000 ;
+ RECT 2047.230000 805.540000 2048.230000 806.020000 ;
+ RECT 2037.920000 800.100000 2039.020000 800.580000 ;
+ RECT 2037.920000 805.540000 2039.020000 806.020000 ;
+ RECT 1992.920000 843.620000 1994.020000 844.100000 ;
+ RECT 1992.920000 838.180000 1994.020000 838.660000 ;
+ RECT 1992.920000 832.740000 1994.020000 833.220000 ;
+ RECT 1992.920000 827.300000 1994.020000 827.780000 ;
+ RECT 1992.920000 821.860000 1994.020000 822.340000 ;
+ RECT 1992.920000 800.100000 1994.020000 800.580000 ;
+ RECT 1992.920000 805.540000 1994.020000 806.020000 ;
+ RECT 1992.920000 810.980000 1994.020000 811.460000 ;
+ RECT 1992.920000 816.420000 1994.020000 816.900000 ;
+ RECT 2037.920000 794.660000 2039.020000 795.140000 ;
+ RECT 2037.920000 789.220000 2039.020000 789.700000 ;
+ RECT 2047.230000 794.660000 2048.230000 795.140000 ;
+ RECT 2047.230000 789.220000 2048.230000 789.700000 ;
+ RECT 2037.920000 778.340000 2039.020000 778.820000 ;
+ RECT 2037.920000 772.900000 2039.020000 773.380000 ;
+ RECT 2047.230000 778.340000 2048.230000 778.820000 ;
+ RECT 2047.230000 772.900000 2048.230000 773.380000 ;
+ RECT 2037.920000 783.780000 2039.020000 784.260000 ;
+ RECT 2047.230000 783.780000 2048.230000 784.260000 ;
+ RECT 2047.230000 762.020000 2048.230000 762.500000 ;
+ RECT 2047.230000 767.460000 2048.230000 767.940000 ;
+ RECT 2037.920000 767.460000 2039.020000 767.940000 ;
+ RECT 2037.920000 762.020000 2039.020000 762.500000 ;
+ RECT 2037.920000 756.580000 2039.020000 757.060000 ;
+ RECT 2037.920000 751.140000 2039.020000 751.620000 ;
+ RECT 2047.230000 756.580000 2048.230000 757.060000 ;
+ RECT 2047.230000 751.140000 2048.230000 751.620000 ;
+ RECT 1992.920000 794.660000 1994.020000 795.140000 ;
+ RECT 1992.920000 789.220000 1994.020000 789.700000 ;
+ RECT 1992.920000 783.780000 1994.020000 784.260000 ;
+ RECT 1992.920000 778.340000 1994.020000 778.820000 ;
+ RECT 1992.920000 772.900000 1994.020000 773.380000 ;
+ RECT 1992.920000 767.460000 1994.020000 767.940000 ;
+ RECT 1992.920000 762.020000 1994.020000 762.500000 ;
+ RECT 1992.920000 756.580000 1994.020000 757.060000 ;
+ RECT 1992.920000 751.140000 1994.020000 751.620000 ;
+ RECT 1947.920000 843.620000 1949.020000 844.100000 ;
+ RECT 1947.920000 838.180000 1949.020000 838.660000 ;
+ RECT 1947.920000 832.740000 1949.020000 833.220000 ;
+ RECT 1947.920000 827.300000 1949.020000 827.780000 ;
+ RECT 1947.920000 821.860000 1949.020000 822.340000 ;
+ RECT 1902.920000 843.620000 1904.020000 844.100000 ;
+ RECT 1902.920000 838.180000 1904.020000 838.660000 ;
+ RECT 1902.920000 832.740000 1904.020000 833.220000 ;
+ RECT 1902.920000 827.300000 1904.020000 827.780000 ;
+ RECT 1902.920000 821.860000 1904.020000 822.340000 ;
+ RECT 1947.920000 816.420000 1949.020000 816.900000 ;
+ RECT 1947.920000 810.980000 1949.020000 811.460000 ;
+ RECT 1947.920000 805.540000 1949.020000 806.020000 ;
+ RECT 1947.920000 800.100000 1949.020000 800.580000 ;
+ RECT 1902.920000 810.980000 1904.020000 811.460000 ;
+ RECT 1902.920000 805.540000 1904.020000 806.020000 ;
+ RECT 1902.920000 800.100000 1904.020000 800.580000 ;
+ RECT 1902.920000 816.420000 1904.020000 816.900000 ;
+ RECT 1857.920000 843.620000 1859.020000 844.100000 ;
+ RECT 1853.790000 843.620000 1854.790000 844.100000 ;
+ RECT 1857.920000 838.180000 1859.020000 838.660000 ;
+ RECT 1853.790000 838.180000 1854.790000 838.660000 ;
+ RECT 1857.920000 832.740000 1859.020000 833.220000 ;
+ RECT 1853.790000 832.740000 1854.790000 833.220000 ;
+ RECT 1857.920000 821.860000 1859.020000 822.340000 ;
+ RECT 1853.790000 821.860000 1854.790000 822.340000 ;
+ RECT 1853.790000 827.300000 1854.790000 827.780000 ;
+ RECT 1857.920000 827.300000 1859.020000 827.780000 ;
+ RECT 1857.920000 816.420000 1859.020000 816.900000 ;
+ RECT 1853.790000 816.420000 1854.790000 816.900000 ;
+ RECT 1857.920000 810.980000 1859.020000 811.460000 ;
+ RECT 1853.790000 810.980000 1854.790000 811.460000 ;
+ RECT 1857.920000 805.540000 1859.020000 806.020000 ;
+ RECT 1853.790000 805.540000 1854.790000 806.020000 ;
+ RECT 1857.920000 800.100000 1859.020000 800.580000 ;
+ RECT 1853.790000 800.100000 1854.790000 800.580000 ;
+ RECT 1947.920000 794.660000 1949.020000 795.140000 ;
+ RECT 1947.920000 789.220000 1949.020000 789.700000 ;
+ RECT 1947.920000 783.780000 1949.020000 784.260000 ;
+ RECT 1947.920000 778.340000 1949.020000 778.820000 ;
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+ RECT 1902.920000 794.660000 1904.020000 795.140000 ;
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+ RECT 1902.920000 783.780000 1904.020000 784.260000 ;
+ RECT 1902.920000 778.340000 1904.020000 778.820000 ;
+ RECT 1902.920000 772.900000 1904.020000 773.380000 ;
+ RECT 1947.920000 751.140000 1949.020000 751.620000 ;
+ RECT 1947.920000 756.580000 1949.020000 757.060000 ;
+ RECT 1947.920000 762.020000 1949.020000 762.500000 ;
+ RECT 1947.920000 767.460000 1949.020000 767.940000 ;
+ RECT 1902.920000 751.140000 1904.020000 751.620000 ;
+ RECT 1902.920000 756.580000 1904.020000 757.060000 ;
+ RECT 1902.920000 762.020000 1904.020000 762.500000 ;
+ RECT 1902.920000 767.460000 1904.020000 767.940000 ;
+ RECT 1857.920000 794.660000 1859.020000 795.140000 ;
+ RECT 1853.790000 794.660000 1854.790000 795.140000 ;
+ RECT 1857.920000 789.220000 1859.020000 789.700000 ;
+ RECT 1853.790000 789.220000 1854.790000 789.700000 ;
+ RECT 1857.920000 778.340000 1859.020000 778.820000 ;
+ RECT 1853.790000 778.340000 1854.790000 778.820000 ;
+ RECT 1857.920000 772.900000 1859.020000 773.380000 ;
+ RECT 1853.790000 772.900000 1854.790000 773.380000 ;
+ RECT 1857.920000 783.780000 1859.020000 784.260000 ;
+ RECT 1853.790000 783.780000 1854.790000 784.260000 ;
+ RECT 1857.920000 767.460000 1859.020000 767.940000 ;
+ RECT 1853.790000 767.460000 1854.790000 767.940000 ;
+ RECT 1857.920000 762.020000 1859.020000 762.500000 ;
+ RECT 1853.790000 762.020000 1854.790000 762.500000 ;
+ RECT 1857.920000 756.580000 1859.020000 757.060000 ;
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+ RECT 1853.790000 756.580000 1854.790000 757.060000 ;
+ RECT 1853.790000 751.140000 1854.790000 751.620000 ;
+ RECT 1850.960000 941.500000 2051.060000 942.500000 ;
+ RECT 1850.960000 749.130000 2051.060000 750.130000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 746.280000 1854.790000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 945.540000 1854.790000 946.540000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 746.280000 2048.230000 747.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 945.540000 2048.230000 946.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 749.130000 1851.960000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 749.130000 2051.060000 750.130000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 941.500000 1851.960000 942.500000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 941.500000 2051.060000 942.500000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
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+ RECT 1902.920000 548.870000 1904.020000 742.240000 ;
+ RECT 1857.920000 548.870000 1859.020000 742.240000 ;
+ RECT 1853.790000 546.020000 1854.790000 746.280000 ;
+ LAYER met3 ;
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+ RECT 1857.920000 594.400000 1859.020000 594.880000 ;
+ RECT 1853.790000 594.400000 1854.790000 594.880000 ;
+ RECT 1857.920000 588.960000 1859.020000 589.440000 ;
+ RECT 1853.790000 588.960000 1854.790000 589.440000 ;
+ RECT 1857.920000 578.080000 1859.020000 578.560000 ;
+ RECT 1853.790000 578.080000 1854.790000 578.560000 ;
+ RECT 1857.920000 572.640000 1859.020000 573.120000 ;
+ RECT 1853.790000 572.640000 1854.790000 573.120000 ;
+ RECT 1857.920000 583.520000 1859.020000 584.000000 ;
+ RECT 1853.790000 583.520000 1854.790000 584.000000 ;
+ RECT 1857.920000 567.200000 1859.020000 567.680000 ;
+ RECT 1853.790000 567.200000 1854.790000 567.680000 ;
+ RECT 1857.920000 561.760000 1859.020000 562.240000 ;
+ RECT 1853.790000 561.760000 1854.790000 562.240000 ;
+ RECT 1857.920000 556.320000 1859.020000 556.800000 ;
+ RECT 1857.920000 550.880000 1859.020000 551.360000 ;
+ RECT 1853.790000 556.320000 1854.790000 556.800000 ;
+ RECT 1853.790000 550.880000 1854.790000 551.360000 ;
+ RECT 1850.960000 741.240000 2051.060000 742.240000 ;
+ RECT 1850.960000 548.870000 2051.060000 549.870000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 546.020000 1854.790000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 745.280000 1854.790000 746.280000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 546.020000 2048.230000 547.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 745.280000 2048.230000 746.280000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 548.870000 1851.960000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 548.870000 2051.060000 549.870000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 741.240000 1851.960000 742.240000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 741.240000 2051.060000 742.240000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 348.610000 2039.020000 541.980000 ;
+ RECT 1992.920000 348.610000 1994.020000 541.980000 ;
+ RECT 2047.230000 345.760000 2048.230000 546.020000 ;
+ RECT 1947.920000 348.610000 1949.020000 541.980000 ;
+ RECT 1902.920000 348.610000 1904.020000 541.980000 ;
+ RECT 1857.920000 348.610000 1859.020000 541.980000 ;
+ RECT 1853.790000 345.760000 1854.790000 546.020000 ;
+ LAYER met3 ;
+ RECT 2037.920000 535.580000 2039.020000 536.060000 ;
+ RECT 2047.230000 535.580000 2048.230000 536.060000 ;
+ RECT 2047.230000 524.700000 2048.230000 525.180000 ;
+ RECT 2047.230000 530.140000 2048.230000 530.620000 ;
+ RECT 2037.920000 530.140000 2039.020000 530.620000 ;
+ RECT 2037.920000 524.700000 2039.020000 525.180000 ;
+ RECT 2037.920000 519.260000 2039.020000 519.740000 ;
+ RECT 2037.920000 513.820000 2039.020000 514.300000 ;
+ RECT 2047.230000 519.260000 2048.230000 519.740000 ;
+ RECT 2047.230000 513.820000 2048.230000 514.300000 ;
+ RECT 2037.920000 497.500000 2039.020000 497.980000 ;
+ RECT 2037.920000 502.940000 2039.020000 503.420000 ;
+ RECT 2047.230000 502.940000 2048.230000 503.420000 ;
+ RECT 2047.230000 497.500000 2048.230000 497.980000 ;
+ RECT 2037.920000 508.380000 2039.020000 508.860000 ;
+ RECT 2047.230000 508.380000 2048.230000 508.860000 ;
+ RECT 1992.920000 535.580000 1994.020000 536.060000 ;
+ RECT 1992.920000 530.140000 1994.020000 530.620000 ;
+ RECT 1992.920000 524.700000 1994.020000 525.180000 ;
+ RECT 1992.920000 519.260000 1994.020000 519.740000 ;
+ RECT 1992.920000 497.500000 1994.020000 497.980000 ;
+ RECT 1992.920000 502.940000 1994.020000 503.420000 ;
+ RECT 1992.920000 508.380000 1994.020000 508.860000 ;
+ RECT 1992.920000 513.820000 1994.020000 514.300000 ;
+ RECT 2047.230000 486.620000 2048.230000 487.100000 ;
+ RECT 2047.230000 492.060000 2048.230000 492.540000 ;
+ RECT 2037.920000 492.060000 2039.020000 492.540000 ;
+ RECT 2037.920000 486.620000 2039.020000 487.100000 ;
+ RECT 2037.920000 481.180000 2039.020000 481.660000 ;
+ RECT 2037.920000 475.740000 2039.020000 476.220000 ;
+ RECT 2047.230000 481.180000 2048.230000 481.660000 ;
+ RECT 2047.230000 475.740000 2048.230000 476.220000 ;
+ RECT 2047.230000 459.420000 2048.230000 459.900000 ;
+ RECT 2047.230000 464.860000 2048.230000 465.340000 ;
+ RECT 2047.230000 470.300000 2048.230000 470.780000 ;
+ RECT 2037.920000 464.860000 2039.020000 465.340000 ;
+ RECT 2037.920000 459.420000 2039.020000 459.900000 ;
+ RECT 2037.920000 470.300000 2039.020000 470.780000 ;
+ RECT 2037.920000 453.980000 2039.020000 454.460000 ;
+ RECT 2037.920000 448.540000 2039.020000 449.020000 ;
+ RECT 2047.230000 453.980000 2048.230000 454.460000 ;
+ RECT 2047.230000 448.540000 2048.230000 449.020000 ;
+ RECT 1992.920000 492.060000 1994.020000 492.540000 ;
+ RECT 1992.920000 486.620000 1994.020000 487.100000 ;
+ RECT 1992.920000 481.180000 1994.020000 481.660000 ;
+ RECT 1992.920000 475.740000 1994.020000 476.220000 ;
+ RECT 1992.920000 464.860000 1994.020000 465.340000 ;
+ RECT 1992.920000 459.420000 1994.020000 459.900000 ;
+ RECT 1992.920000 453.980000 1994.020000 454.460000 ;
+ RECT 1992.920000 448.540000 1994.020000 449.020000 ;
+ RECT 1992.920000 470.300000 1994.020000 470.780000 ;
+ RECT 1947.920000 535.580000 1949.020000 536.060000 ;
+ RECT 1947.920000 530.140000 1949.020000 530.620000 ;
+ RECT 1947.920000 524.700000 1949.020000 525.180000 ;
+ RECT 1902.920000 535.580000 1904.020000 536.060000 ;
+ RECT 1902.920000 530.140000 1904.020000 530.620000 ;
+ RECT 1902.920000 524.700000 1904.020000 525.180000 ;
+ RECT 1947.920000 508.380000 1949.020000 508.860000 ;
+ RECT 1947.920000 502.940000 1949.020000 503.420000 ;
+ RECT 1947.920000 497.500000 1949.020000 497.980000 ;
+ RECT 1947.920000 513.820000 1949.020000 514.300000 ;
+ RECT 1947.920000 519.260000 1949.020000 519.740000 ;
+ RECT 1902.920000 519.260000 1904.020000 519.740000 ;
+ RECT 1902.920000 508.380000 1904.020000 508.860000 ;
+ RECT 1902.920000 502.940000 1904.020000 503.420000 ;
+ RECT 1902.920000 497.500000 1904.020000 497.980000 ;
+ RECT 1902.920000 513.820000 1904.020000 514.300000 ;
+ RECT 1857.920000 535.580000 1859.020000 536.060000 ;
+ RECT 1853.790000 535.580000 1854.790000 536.060000 ;
+ RECT 1853.790000 530.140000 1854.790000 530.620000 ;
+ RECT 1857.920000 530.140000 1859.020000 530.620000 ;
+ RECT 1857.920000 524.700000 1859.020000 525.180000 ;
+ RECT 1853.790000 524.700000 1854.790000 525.180000 ;
+ RECT 1857.920000 519.260000 1859.020000 519.740000 ;
+ RECT 1853.790000 519.260000 1854.790000 519.740000 ;
+ RECT 1857.920000 513.820000 1859.020000 514.300000 ;
+ RECT 1853.790000 513.820000 1854.790000 514.300000 ;
+ RECT 1857.920000 502.940000 1859.020000 503.420000 ;
+ RECT 1853.790000 502.940000 1854.790000 503.420000 ;
+ RECT 1857.920000 497.500000 1859.020000 497.980000 ;
+ RECT 1853.790000 497.500000 1854.790000 497.980000 ;
+ RECT 1857.920000 508.380000 1859.020000 508.860000 ;
+ RECT 1853.790000 508.380000 1854.790000 508.860000 ;
+ RECT 1947.920000 492.060000 1949.020000 492.540000 ;
+ RECT 1947.920000 486.620000 1949.020000 487.100000 ;
+ RECT 1947.920000 481.180000 1949.020000 481.660000 ;
+ RECT 1947.920000 475.740000 1949.020000 476.220000 ;
+ RECT 1902.920000 492.060000 1904.020000 492.540000 ;
+ RECT 1902.920000 486.620000 1904.020000 487.100000 ;
+ RECT 1902.920000 481.180000 1904.020000 481.660000 ;
+ RECT 1902.920000 475.740000 1904.020000 476.220000 ;
+ RECT 1947.920000 464.860000 1949.020000 465.340000 ;
+ RECT 1947.920000 448.540000 1949.020000 449.020000 ;
+ RECT 1947.920000 453.980000 1949.020000 454.460000 ;
+ RECT 1947.920000 459.420000 1949.020000 459.900000 ;
+ RECT 1947.920000 470.300000 1949.020000 470.780000 ;
+ RECT 1902.920000 448.540000 1904.020000 449.020000 ;
+ RECT 1902.920000 453.980000 1904.020000 454.460000 ;
+ RECT 1902.920000 459.420000 1904.020000 459.900000 ;
+ RECT 1902.920000 464.860000 1904.020000 465.340000 ;
+ RECT 1902.920000 470.300000 1904.020000 470.780000 ;
+ RECT 1857.920000 492.060000 1859.020000 492.540000 ;
+ RECT 1853.790000 492.060000 1854.790000 492.540000 ;
+ RECT 1857.920000 486.620000 1859.020000 487.100000 ;
+ RECT 1853.790000 486.620000 1854.790000 487.100000 ;
+ RECT 1857.920000 481.180000 1859.020000 481.660000 ;
+ RECT 1853.790000 481.180000 1854.790000 481.660000 ;
+ RECT 1857.920000 475.740000 1859.020000 476.220000 ;
+ RECT 1853.790000 475.740000 1854.790000 476.220000 ;
+ RECT 1857.920000 470.300000 1859.020000 470.780000 ;
+ RECT 1857.920000 464.860000 1859.020000 465.340000 ;
+ RECT 1853.790000 470.300000 1854.790000 470.780000 ;
+ RECT 1853.790000 464.860000 1854.790000 465.340000 ;
+ RECT 1857.920000 459.420000 1859.020000 459.900000 ;
+ RECT 1853.790000 459.420000 1854.790000 459.900000 ;
+ RECT 1857.920000 453.980000 1859.020000 454.460000 ;
+ RECT 1853.790000 453.980000 1854.790000 454.460000 ;
+ RECT 1857.920000 448.540000 1859.020000 449.020000 ;
+ RECT 1853.790000 448.540000 1854.790000 449.020000 ;
+ RECT 2037.920000 443.100000 2039.020000 443.580000 ;
+ RECT 2037.920000 437.660000 2039.020000 438.140000 ;
+ RECT 2047.230000 443.100000 2048.230000 443.580000 ;
+ RECT 2047.230000 437.660000 2048.230000 438.140000 ;
+ RECT 2047.230000 421.340000 2048.230000 421.820000 ;
+ RECT 2047.230000 426.780000 2048.230000 427.260000 ;
+ RECT 2047.230000 432.220000 2048.230000 432.700000 ;
+ RECT 2037.920000 432.220000 2039.020000 432.700000 ;
+ RECT 2037.920000 426.780000 2039.020000 427.260000 ;
+ RECT 2037.920000 421.340000 2039.020000 421.820000 ;
+ RECT 2037.920000 410.460000 2039.020000 410.940000 ;
+ RECT 2037.920000 415.900000 2039.020000 416.380000 ;
+ RECT 2047.230000 415.900000 2048.230000 416.380000 ;
+ RECT 2047.230000 410.460000 2048.230000 410.940000 ;
+ RECT 2047.230000 399.580000 2048.230000 400.060000 ;
+ RECT 2047.230000 405.020000 2048.230000 405.500000 ;
+ RECT 2037.920000 399.580000 2039.020000 400.060000 ;
+ RECT 2037.920000 405.020000 2039.020000 405.500000 ;
+ RECT 1992.920000 443.100000 1994.020000 443.580000 ;
+ RECT 1992.920000 437.660000 1994.020000 438.140000 ;
+ RECT 1992.920000 432.220000 1994.020000 432.700000 ;
+ RECT 1992.920000 426.780000 1994.020000 427.260000 ;
+ RECT 1992.920000 421.340000 1994.020000 421.820000 ;
+ RECT 1992.920000 399.580000 1994.020000 400.060000 ;
+ RECT 1992.920000 405.020000 1994.020000 405.500000 ;
+ RECT 1992.920000 410.460000 1994.020000 410.940000 ;
+ RECT 1992.920000 415.900000 1994.020000 416.380000 ;
+ RECT 2037.920000 394.140000 2039.020000 394.620000 ;
+ RECT 2037.920000 388.700000 2039.020000 389.180000 ;
+ RECT 2047.230000 394.140000 2048.230000 394.620000 ;
+ RECT 2047.230000 388.700000 2048.230000 389.180000 ;
+ RECT 2037.920000 377.820000 2039.020000 378.300000 ;
+ RECT 2037.920000 372.380000 2039.020000 372.860000 ;
+ RECT 2047.230000 377.820000 2048.230000 378.300000 ;
+ RECT 2047.230000 372.380000 2048.230000 372.860000 ;
+ RECT 2037.920000 383.260000 2039.020000 383.740000 ;
+ RECT 2047.230000 383.260000 2048.230000 383.740000 ;
+ RECT 2047.230000 361.500000 2048.230000 361.980000 ;
+ RECT 2047.230000 366.940000 2048.230000 367.420000 ;
+ RECT 2037.920000 366.940000 2039.020000 367.420000 ;
+ RECT 2037.920000 361.500000 2039.020000 361.980000 ;
+ RECT 2037.920000 356.060000 2039.020000 356.540000 ;
+ RECT 2037.920000 350.620000 2039.020000 351.100000 ;
+ RECT 2047.230000 356.060000 2048.230000 356.540000 ;
+ RECT 2047.230000 350.620000 2048.230000 351.100000 ;
+ RECT 1992.920000 394.140000 1994.020000 394.620000 ;
+ RECT 1992.920000 388.700000 1994.020000 389.180000 ;
+ RECT 1992.920000 383.260000 1994.020000 383.740000 ;
+ RECT 1992.920000 377.820000 1994.020000 378.300000 ;
+ RECT 1992.920000 372.380000 1994.020000 372.860000 ;
+ RECT 1992.920000 366.940000 1994.020000 367.420000 ;
+ RECT 1992.920000 361.500000 1994.020000 361.980000 ;
+ RECT 1992.920000 356.060000 1994.020000 356.540000 ;
+ RECT 1992.920000 350.620000 1994.020000 351.100000 ;
+ RECT 1947.920000 443.100000 1949.020000 443.580000 ;
+ RECT 1947.920000 437.660000 1949.020000 438.140000 ;
+ RECT 1947.920000 432.220000 1949.020000 432.700000 ;
+ RECT 1947.920000 426.780000 1949.020000 427.260000 ;
+ RECT 1947.920000 421.340000 1949.020000 421.820000 ;
+ RECT 1902.920000 443.100000 1904.020000 443.580000 ;
+ RECT 1902.920000 437.660000 1904.020000 438.140000 ;
+ RECT 1902.920000 432.220000 1904.020000 432.700000 ;
+ RECT 1902.920000 426.780000 1904.020000 427.260000 ;
+ RECT 1902.920000 421.340000 1904.020000 421.820000 ;
+ RECT 1947.920000 415.900000 1949.020000 416.380000 ;
+ RECT 1947.920000 410.460000 1949.020000 410.940000 ;
+ RECT 1947.920000 405.020000 1949.020000 405.500000 ;
+ RECT 1947.920000 399.580000 1949.020000 400.060000 ;
+ RECT 1902.920000 410.460000 1904.020000 410.940000 ;
+ RECT 1902.920000 405.020000 1904.020000 405.500000 ;
+ RECT 1902.920000 399.580000 1904.020000 400.060000 ;
+ RECT 1902.920000 415.900000 1904.020000 416.380000 ;
+ RECT 1857.920000 443.100000 1859.020000 443.580000 ;
+ RECT 1853.790000 443.100000 1854.790000 443.580000 ;
+ RECT 1857.920000 437.660000 1859.020000 438.140000 ;
+ RECT 1853.790000 437.660000 1854.790000 438.140000 ;
+ RECT 1857.920000 432.220000 1859.020000 432.700000 ;
+ RECT 1853.790000 432.220000 1854.790000 432.700000 ;
+ RECT 1857.920000 421.340000 1859.020000 421.820000 ;
+ RECT 1853.790000 421.340000 1854.790000 421.820000 ;
+ RECT 1853.790000 426.780000 1854.790000 427.260000 ;
+ RECT 1857.920000 426.780000 1859.020000 427.260000 ;
+ RECT 1857.920000 415.900000 1859.020000 416.380000 ;
+ RECT 1853.790000 415.900000 1854.790000 416.380000 ;
+ RECT 1857.920000 410.460000 1859.020000 410.940000 ;
+ RECT 1853.790000 410.460000 1854.790000 410.940000 ;
+ RECT 1857.920000 405.020000 1859.020000 405.500000 ;
+ RECT 1853.790000 405.020000 1854.790000 405.500000 ;
+ RECT 1857.920000 399.580000 1859.020000 400.060000 ;
+ RECT 1853.790000 399.580000 1854.790000 400.060000 ;
+ RECT 1947.920000 394.140000 1949.020000 394.620000 ;
+ RECT 1947.920000 388.700000 1949.020000 389.180000 ;
+ RECT 1947.920000 383.260000 1949.020000 383.740000 ;
+ RECT 1947.920000 377.820000 1949.020000 378.300000 ;
+ RECT 1947.920000 372.380000 1949.020000 372.860000 ;
+ RECT 1902.920000 394.140000 1904.020000 394.620000 ;
+ RECT 1902.920000 388.700000 1904.020000 389.180000 ;
+ RECT 1902.920000 383.260000 1904.020000 383.740000 ;
+ RECT 1902.920000 377.820000 1904.020000 378.300000 ;
+ RECT 1902.920000 372.380000 1904.020000 372.860000 ;
+ RECT 1947.920000 350.620000 1949.020000 351.100000 ;
+ RECT 1947.920000 356.060000 1949.020000 356.540000 ;
+ RECT 1947.920000 361.500000 1949.020000 361.980000 ;
+ RECT 1947.920000 366.940000 1949.020000 367.420000 ;
+ RECT 1902.920000 350.620000 1904.020000 351.100000 ;
+ RECT 1902.920000 356.060000 1904.020000 356.540000 ;
+ RECT 1902.920000 361.500000 1904.020000 361.980000 ;
+ RECT 1902.920000 366.940000 1904.020000 367.420000 ;
+ RECT 1857.920000 394.140000 1859.020000 394.620000 ;
+ RECT 1853.790000 394.140000 1854.790000 394.620000 ;
+ RECT 1857.920000 388.700000 1859.020000 389.180000 ;
+ RECT 1853.790000 388.700000 1854.790000 389.180000 ;
+ RECT 1857.920000 377.820000 1859.020000 378.300000 ;
+ RECT 1853.790000 377.820000 1854.790000 378.300000 ;
+ RECT 1857.920000 372.380000 1859.020000 372.860000 ;
+ RECT 1853.790000 372.380000 1854.790000 372.860000 ;
+ RECT 1857.920000 383.260000 1859.020000 383.740000 ;
+ RECT 1853.790000 383.260000 1854.790000 383.740000 ;
+ RECT 1857.920000 366.940000 1859.020000 367.420000 ;
+ RECT 1853.790000 366.940000 1854.790000 367.420000 ;
+ RECT 1857.920000 361.500000 1859.020000 361.980000 ;
+ RECT 1853.790000 361.500000 1854.790000 361.980000 ;
+ RECT 1857.920000 356.060000 1859.020000 356.540000 ;
+ RECT 1857.920000 350.620000 1859.020000 351.100000 ;
+ RECT 1853.790000 356.060000 1854.790000 356.540000 ;
+ RECT 1853.790000 350.620000 1854.790000 351.100000 ;
+ RECT 1850.960000 540.980000 2051.060000 541.980000 ;
+ RECT 1850.960000 348.610000 2051.060000 349.610000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 345.760000 1854.790000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 545.020000 1854.790000 546.020000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 345.760000 2048.230000 346.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 545.020000 2048.230000 546.020000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 348.610000 1851.960000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 348.610000 2051.060000 349.610000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 540.980000 1851.960000 541.980000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 540.980000 2051.060000 541.980000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 148.350000 2039.020000 341.720000 ;
+ RECT 1992.920000 148.350000 1994.020000 341.720000 ;
+ RECT 2047.230000 145.500000 2048.230000 345.760000 ;
+ RECT 1947.920000 148.350000 1949.020000 341.720000 ;
+ RECT 1902.920000 148.350000 1904.020000 341.720000 ;
+ RECT 1857.920000 148.350000 1859.020000 341.720000 ;
+ RECT 1853.790000 145.500000 1854.790000 345.760000 ;
+ LAYER met3 ;
+ RECT 2037.920000 335.320000 2039.020000 335.800000 ;
+ RECT 2047.230000 335.320000 2048.230000 335.800000 ;
+ RECT 2047.230000 324.440000 2048.230000 324.920000 ;
+ RECT 2047.230000 329.880000 2048.230000 330.360000 ;
+ RECT 2037.920000 329.880000 2039.020000 330.360000 ;
+ RECT 2037.920000 324.440000 2039.020000 324.920000 ;
+ RECT 2037.920000 319.000000 2039.020000 319.480000 ;
+ RECT 2037.920000 313.560000 2039.020000 314.040000 ;
+ RECT 2047.230000 319.000000 2048.230000 319.480000 ;
+ RECT 2047.230000 313.560000 2048.230000 314.040000 ;
+ RECT 2037.920000 297.240000 2039.020000 297.720000 ;
+ RECT 2037.920000 302.680000 2039.020000 303.160000 ;
+ RECT 2047.230000 302.680000 2048.230000 303.160000 ;
+ RECT 2047.230000 297.240000 2048.230000 297.720000 ;
+ RECT 2037.920000 308.120000 2039.020000 308.600000 ;
+ RECT 2047.230000 308.120000 2048.230000 308.600000 ;
+ RECT 1992.920000 335.320000 1994.020000 335.800000 ;
+ RECT 1992.920000 329.880000 1994.020000 330.360000 ;
+ RECT 1992.920000 324.440000 1994.020000 324.920000 ;
+ RECT 1992.920000 319.000000 1994.020000 319.480000 ;
+ RECT 1992.920000 297.240000 1994.020000 297.720000 ;
+ RECT 1992.920000 302.680000 1994.020000 303.160000 ;
+ RECT 1992.920000 308.120000 1994.020000 308.600000 ;
+ RECT 1992.920000 313.560000 1994.020000 314.040000 ;
+ RECT 2047.230000 286.360000 2048.230000 286.840000 ;
+ RECT 2047.230000 291.800000 2048.230000 292.280000 ;
+ RECT 2037.920000 291.800000 2039.020000 292.280000 ;
+ RECT 2037.920000 286.360000 2039.020000 286.840000 ;
+ RECT 2037.920000 280.920000 2039.020000 281.400000 ;
+ RECT 2037.920000 275.480000 2039.020000 275.960000 ;
+ RECT 2047.230000 280.920000 2048.230000 281.400000 ;
+ RECT 2047.230000 275.480000 2048.230000 275.960000 ;
+ RECT 2047.230000 259.160000 2048.230000 259.640000 ;
+ RECT 2047.230000 264.600000 2048.230000 265.080000 ;
+ RECT 2047.230000 270.040000 2048.230000 270.520000 ;
+ RECT 2037.920000 264.600000 2039.020000 265.080000 ;
+ RECT 2037.920000 259.160000 2039.020000 259.640000 ;
+ RECT 2037.920000 270.040000 2039.020000 270.520000 ;
+ RECT 2037.920000 253.720000 2039.020000 254.200000 ;
+ RECT 2037.920000 248.280000 2039.020000 248.760000 ;
+ RECT 2047.230000 253.720000 2048.230000 254.200000 ;
+ RECT 2047.230000 248.280000 2048.230000 248.760000 ;
+ RECT 1992.920000 291.800000 1994.020000 292.280000 ;
+ RECT 1992.920000 286.360000 1994.020000 286.840000 ;
+ RECT 1992.920000 280.920000 1994.020000 281.400000 ;
+ RECT 1992.920000 275.480000 1994.020000 275.960000 ;
+ RECT 1992.920000 264.600000 1994.020000 265.080000 ;
+ RECT 1992.920000 259.160000 1994.020000 259.640000 ;
+ RECT 1992.920000 253.720000 1994.020000 254.200000 ;
+ RECT 1992.920000 248.280000 1994.020000 248.760000 ;
+ RECT 1992.920000 270.040000 1994.020000 270.520000 ;
+ RECT 1947.920000 335.320000 1949.020000 335.800000 ;
+ RECT 1947.920000 329.880000 1949.020000 330.360000 ;
+ RECT 1947.920000 324.440000 1949.020000 324.920000 ;
+ RECT 1902.920000 335.320000 1904.020000 335.800000 ;
+ RECT 1902.920000 329.880000 1904.020000 330.360000 ;
+ RECT 1902.920000 324.440000 1904.020000 324.920000 ;
+ RECT 1947.920000 308.120000 1949.020000 308.600000 ;
+ RECT 1947.920000 302.680000 1949.020000 303.160000 ;
+ RECT 1947.920000 297.240000 1949.020000 297.720000 ;
+ RECT 1947.920000 313.560000 1949.020000 314.040000 ;
+ RECT 1947.920000 319.000000 1949.020000 319.480000 ;
+ RECT 1902.920000 319.000000 1904.020000 319.480000 ;
+ RECT 1902.920000 308.120000 1904.020000 308.600000 ;
+ RECT 1902.920000 302.680000 1904.020000 303.160000 ;
+ RECT 1902.920000 297.240000 1904.020000 297.720000 ;
+ RECT 1902.920000 313.560000 1904.020000 314.040000 ;
+ RECT 1857.920000 335.320000 1859.020000 335.800000 ;
+ RECT 1853.790000 335.320000 1854.790000 335.800000 ;
+ RECT 1853.790000 329.880000 1854.790000 330.360000 ;
+ RECT 1857.920000 329.880000 1859.020000 330.360000 ;
+ RECT 1857.920000 324.440000 1859.020000 324.920000 ;
+ RECT 1853.790000 324.440000 1854.790000 324.920000 ;
+ RECT 1857.920000 319.000000 1859.020000 319.480000 ;
+ RECT 1853.790000 319.000000 1854.790000 319.480000 ;
+ RECT 1857.920000 313.560000 1859.020000 314.040000 ;
+ RECT 1853.790000 313.560000 1854.790000 314.040000 ;
+ RECT 1857.920000 302.680000 1859.020000 303.160000 ;
+ RECT 1853.790000 302.680000 1854.790000 303.160000 ;
+ RECT 1857.920000 297.240000 1859.020000 297.720000 ;
+ RECT 1853.790000 297.240000 1854.790000 297.720000 ;
+ RECT 1857.920000 308.120000 1859.020000 308.600000 ;
+ RECT 1853.790000 308.120000 1854.790000 308.600000 ;
+ RECT 1947.920000 291.800000 1949.020000 292.280000 ;
+ RECT 1947.920000 286.360000 1949.020000 286.840000 ;
+ RECT 1947.920000 280.920000 1949.020000 281.400000 ;
+ RECT 1947.920000 275.480000 1949.020000 275.960000 ;
+ RECT 1902.920000 291.800000 1904.020000 292.280000 ;
+ RECT 1902.920000 286.360000 1904.020000 286.840000 ;
+ RECT 1902.920000 280.920000 1904.020000 281.400000 ;
+ RECT 1902.920000 275.480000 1904.020000 275.960000 ;
+ RECT 1947.920000 264.600000 1949.020000 265.080000 ;
+ RECT 1947.920000 248.280000 1949.020000 248.760000 ;
+ RECT 1947.920000 253.720000 1949.020000 254.200000 ;
+ RECT 1947.920000 259.160000 1949.020000 259.640000 ;
+ RECT 1947.920000 270.040000 1949.020000 270.520000 ;
+ RECT 1902.920000 248.280000 1904.020000 248.760000 ;
+ RECT 1902.920000 253.720000 1904.020000 254.200000 ;
+ RECT 1902.920000 259.160000 1904.020000 259.640000 ;
+ RECT 1902.920000 264.600000 1904.020000 265.080000 ;
+ RECT 1902.920000 270.040000 1904.020000 270.520000 ;
+ RECT 1857.920000 291.800000 1859.020000 292.280000 ;
+ RECT 1853.790000 291.800000 1854.790000 292.280000 ;
+ RECT 1857.920000 286.360000 1859.020000 286.840000 ;
+ RECT 1853.790000 286.360000 1854.790000 286.840000 ;
+ RECT 1857.920000 280.920000 1859.020000 281.400000 ;
+ RECT 1853.790000 280.920000 1854.790000 281.400000 ;
+ RECT 1857.920000 275.480000 1859.020000 275.960000 ;
+ RECT 1853.790000 275.480000 1854.790000 275.960000 ;
+ RECT 1857.920000 270.040000 1859.020000 270.520000 ;
+ RECT 1857.920000 264.600000 1859.020000 265.080000 ;
+ RECT 1853.790000 270.040000 1854.790000 270.520000 ;
+ RECT 1853.790000 264.600000 1854.790000 265.080000 ;
+ RECT 1857.920000 259.160000 1859.020000 259.640000 ;
+ RECT 1853.790000 259.160000 1854.790000 259.640000 ;
+ RECT 1857.920000 253.720000 1859.020000 254.200000 ;
+ RECT 1853.790000 253.720000 1854.790000 254.200000 ;
+ RECT 1857.920000 248.280000 1859.020000 248.760000 ;
+ RECT 1853.790000 248.280000 1854.790000 248.760000 ;
+ RECT 2037.920000 242.840000 2039.020000 243.320000 ;
+ RECT 2037.920000 237.400000 2039.020000 237.880000 ;
+ RECT 2047.230000 242.840000 2048.230000 243.320000 ;
+ RECT 2047.230000 237.400000 2048.230000 237.880000 ;
+ RECT 2047.230000 221.080000 2048.230000 221.560000 ;
+ RECT 2047.230000 226.520000 2048.230000 227.000000 ;
+ RECT 2047.230000 231.960000 2048.230000 232.440000 ;
+ RECT 2037.920000 231.960000 2039.020000 232.440000 ;
+ RECT 2037.920000 226.520000 2039.020000 227.000000 ;
+ RECT 2037.920000 221.080000 2039.020000 221.560000 ;
+ RECT 2037.920000 210.200000 2039.020000 210.680000 ;
+ RECT 2037.920000 215.640000 2039.020000 216.120000 ;
+ RECT 2047.230000 215.640000 2048.230000 216.120000 ;
+ RECT 2047.230000 210.200000 2048.230000 210.680000 ;
+ RECT 2047.230000 199.320000 2048.230000 199.800000 ;
+ RECT 2047.230000 204.760000 2048.230000 205.240000 ;
+ RECT 2037.920000 199.320000 2039.020000 199.800000 ;
+ RECT 2037.920000 204.760000 2039.020000 205.240000 ;
+ RECT 1992.920000 242.840000 1994.020000 243.320000 ;
+ RECT 1992.920000 237.400000 1994.020000 237.880000 ;
+ RECT 1992.920000 231.960000 1994.020000 232.440000 ;
+ RECT 1992.920000 226.520000 1994.020000 227.000000 ;
+ RECT 1992.920000 221.080000 1994.020000 221.560000 ;
+ RECT 1992.920000 199.320000 1994.020000 199.800000 ;
+ RECT 1992.920000 204.760000 1994.020000 205.240000 ;
+ RECT 1992.920000 210.200000 1994.020000 210.680000 ;
+ RECT 1992.920000 215.640000 1994.020000 216.120000 ;
+ RECT 2037.920000 193.880000 2039.020000 194.360000 ;
+ RECT 2037.920000 188.440000 2039.020000 188.920000 ;
+ RECT 2047.230000 193.880000 2048.230000 194.360000 ;
+ RECT 2047.230000 188.440000 2048.230000 188.920000 ;
+ RECT 2037.920000 177.560000 2039.020000 178.040000 ;
+ RECT 2037.920000 172.120000 2039.020000 172.600000 ;
+ RECT 2047.230000 177.560000 2048.230000 178.040000 ;
+ RECT 2047.230000 172.120000 2048.230000 172.600000 ;
+ RECT 2037.920000 183.000000 2039.020000 183.480000 ;
+ RECT 2047.230000 183.000000 2048.230000 183.480000 ;
+ RECT 2047.230000 161.240000 2048.230000 161.720000 ;
+ RECT 2047.230000 166.680000 2048.230000 167.160000 ;
+ RECT 2037.920000 166.680000 2039.020000 167.160000 ;
+ RECT 2037.920000 161.240000 2039.020000 161.720000 ;
+ RECT 2037.920000 155.800000 2039.020000 156.280000 ;
+ RECT 2037.920000 150.360000 2039.020000 150.840000 ;
+ RECT 2047.230000 155.800000 2048.230000 156.280000 ;
+ RECT 2047.230000 150.360000 2048.230000 150.840000 ;
+ RECT 1992.920000 193.880000 1994.020000 194.360000 ;
+ RECT 1992.920000 188.440000 1994.020000 188.920000 ;
+ RECT 1992.920000 183.000000 1994.020000 183.480000 ;
+ RECT 1992.920000 177.560000 1994.020000 178.040000 ;
+ RECT 1992.920000 172.120000 1994.020000 172.600000 ;
+ RECT 1992.920000 166.680000 1994.020000 167.160000 ;
+ RECT 1992.920000 161.240000 1994.020000 161.720000 ;
+ RECT 1992.920000 155.800000 1994.020000 156.280000 ;
+ RECT 1992.920000 150.360000 1994.020000 150.840000 ;
+ RECT 1947.920000 242.840000 1949.020000 243.320000 ;
+ RECT 1947.920000 237.400000 1949.020000 237.880000 ;
+ RECT 1947.920000 231.960000 1949.020000 232.440000 ;
+ RECT 1947.920000 226.520000 1949.020000 227.000000 ;
+ RECT 1947.920000 221.080000 1949.020000 221.560000 ;
+ RECT 1902.920000 242.840000 1904.020000 243.320000 ;
+ RECT 1902.920000 237.400000 1904.020000 237.880000 ;
+ RECT 1902.920000 231.960000 1904.020000 232.440000 ;
+ RECT 1902.920000 226.520000 1904.020000 227.000000 ;
+ RECT 1902.920000 221.080000 1904.020000 221.560000 ;
+ RECT 1947.920000 215.640000 1949.020000 216.120000 ;
+ RECT 1947.920000 210.200000 1949.020000 210.680000 ;
+ RECT 1947.920000 204.760000 1949.020000 205.240000 ;
+ RECT 1947.920000 199.320000 1949.020000 199.800000 ;
+ RECT 1902.920000 210.200000 1904.020000 210.680000 ;
+ RECT 1902.920000 204.760000 1904.020000 205.240000 ;
+ RECT 1902.920000 199.320000 1904.020000 199.800000 ;
+ RECT 1902.920000 215.640000 1904.020000 216.120000 ;
+ RECT 1857.920000 242.840000 1859.020000 243.320000 ;
+ RECT 1853.790000 242.840000 1854.790000 243.320000 ;
+ RECT 1857.920000 237.400000 1859.020000 237.880000 ;
+ RECT 1853.790000 237.400000 1854.790000 237.880000 ;
+ RECT 1857.920000 231.960000 1859.020000 232.440000 ;
+ RECT 1853.790000 231.960000 1854.790000 232.440000 ;
+ RECT 1857.920000 221.080000 1859.020000 221.560000 ;
+ RECT 1853.790000 221.080000 1854.790000 221.560000 ;
+ RECT 1853.790000 226.520000 1854.790000 227.000000 ;
+ RECT 1857.920000 226.520000 1859.020000 227.000000 ;
+ RECT 1857.920000 215.640000 1859.020000 216.120000 ;
+ RECT 1853.790000 215.640000 1854.790000 216.120000 ;
+ RECT 1857.920000 210.200000 1859.020000 210.680000 ;
+ RECT 1853.790000 210.200000 1854.790000 210.680000 ;
+ RECT 1857.920000 204.760000 1859.020000 205.240000 ;
+ RECT 1853.790000 204.760000 1854.790000 205.240000 ;
+ RECT 1857.920000 199.320000 1859.020000 199.800000 ;
+ RECT 1853.790000 199.320000 1854.790000 199.800000 ;
+ RECT 1947.920000 193.880000 1949.020000 194.360000 ;
+ RECT 1947.920000 188.440000 1949.020000 188.920000 ;
+ RECT 1947.920000 183.000000 1949.020000 183.480000 ;
+ RECT 1947.920000 177.560000 1949.020000 178.040000 ;
+ RECT 1947.920000 172.120000 1949.020000 172.600000 ;
+ RECT 1902.920000 193.880000 1904.020000 194.360000 ;
+ RECT 1902.920000 188.440000 1904.020000 188.920000 ;
+ RECT 1902.920000 183.000000 1904.020000 183.480000 ;
+ RECT 1902.920000 177.560000 1904.020000 178.040000 ;
+ RECT 1902.920000 172.120000 1904.020000 172.600000 ;
+ RECT 1947.920000 150.360000 1949.020000 150.840000 ;
+ RECT 1947.920000 155.800000 1949.020000 156.280000 ;
+ RECT 1947.920000 161.240000 1949.020000 161.720000 ;
+ RECT 1947.920000 166.680000 1949.020000 167.160000 ;
+ RECT 1902.920000 150.360000 1904.020000 150.840000 ;
+ RECT 1902.920000 155.800000 1904.020000 156.280000 ;
+ RECT 1902.920000 161.240000 1904.020000 161.720000 ;
+ RECT 1902.920000 166.680000 1904.020000 167.160000 ;
+ RECT 1857.920000 193.880000 1859.020000 194.360000 ;
+ RECT 1853.790000 193.880000 1854.790000 194.360000 ;
+ RECT 1857.920000 188.440000 1859.020000 188.920000 ;
+ RECT 1853.790000 188.440000 1854.790000 188.920000 ;
+ RECT 1857.920000 177.560000 1859.020000 178.040000 ;
+ RECT 1853.790000 177.560000 1854.790000 178.040000 ;
+ RECT 1857.920000 172.120000 1859.020000 172.600000 ;
+ RECT 1853.790000 172.120000 1854.790000 172.600000 ;
+ RECT 1857.920000 183.000000 1859.020000 183.480000 ;
+ RECT 1853.790000 183.000000 1854.790000 183.480000 ;
+ RECT 1857.920000 166.680000 1859.020000 167.160000 ;
+ RECT 1853.790000 166.680000 1854.790000 167.160000 ;
+ RECT 1857.920000 161.240000 1859.020000 161.720000 ;
+ RECT 1853.790000 161.240000 1854.790000 161.720000 ;
+ RECT 1857.920000 155.800000 1859.020000 156.280000 ;
+ RECT 1857.920000 150.360000 1859.020000 150.840000 ;
+ RECT 1853.790000 155.800000 1854.790000 156.280000 ;
+ RECT 1853.790000 150.360000 1854.790000 150.840000 ;
+ RECT 1850.960000 340.720000 2051.060000 341.720000 ;
+ RECT 1850.960000 148.350000 2051.060000 149.350000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 145.500000 1854.790000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 344.760000 1854.790000 345.760000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 145.500000 2048.230000 146.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 344.760000 2048.230000 345.760000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 148.350000 1851.960000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 148.350000 2051.060000 149.350000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 340.720000 1851.960000 341.720000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 340.720000 2051.060000 341.720000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'S_term_single'
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 115.240000 1854.790000 145.500000 ;
+ RECT 2047.230000 115.240000 2048.230000 145.500000 ;
+ RECT 1857.920000 118.090000 1859.020000 142.140000 ;
+ RECT 1902.920000 118.090000 1904.020000 142.140000 ;
+ RECT 1947.920000 118.090000 1949.020000 142.140000 ;
+ RECT 1992.920000 118.090000 1994.020000 142.140000 ;
+ RECT 2037.920000 118.090000 2039.020000 142.140000 ;
+ LAYER met3 ;
+ RECT 2047.230000 130.980000 2048.230000 131.460000 ;
+ RECT 2047.230000 136.420000 2048.230000 136.900000 ;
+ RECT 2037.920000 136.420000 2039.020000 136.900000 ;
+ RECT 2037.920000 130.980000 2039.020000 131.460000 ;
+ RECT 1992.920000 130.980000 1994.020000 131.460000 ;
+ RECT 1992.920000 136.420000 1994.020000 136.900000 ;
+ RECT 1902.920000 130.980000 1904.020000 131.460000 ;
+ RECT 1947.920000 130.980000 1949.020000 131.460000 ;
+ RECT 1947.920000 136.420000 1949.020000 136.900000 ;
+ RECT 1902.920000 136.420000 1904.020000 136.900000 ;
+ RECT 1853.790000 130.980000 1854.790000 131.460000 ;
+ RECT 1857.920000 130.980000 1859.020000 131.460000 ;
+ RECT 1857.920000 136.420000 1859.020000 136.900000 ;
+ RECT 1853.790000 136.420000 1854.790000 136.900000 ;
+ RECT 2047.230000 120.100000 2048.230000 120.580000 ;
+ RECT 2047.230000 125.540000 2048.230000 126.020000 ;
+ RECT 2037.920000 125.540000 2039.020000 126.020000 ;
+ RECT 2037.920000 120.100000 2039.020000 120.580000 ;
+ RECT 1992.920000 120.100000 1994.020000 120.580000 ;
+ RECT 1992.920000 125.540000 1994.020000 126.020000 ;
+ RECT 1902.920000 120.100000 1904.020000 120.580000 ;
+ RECT 1947.920000 120.100000 1949.020000 120.580000 ;
+ RECT 1947.920000 125.540000 1949.020000 126.020000 ;
+ RECT 1902.920000 125.540000 1904.020000 126.020000 ;
+ RECT 1853.790000 125.540000 1854.790000 126.020000 ;
+ RECT 1857.920000 125.540000 1859.020000 126.020000 ;
+ RECT 1853.790000 120.100000 1854.790000 120.580000 ;
+ RECT 1857.920000 120.100000 1859.020000 120.580000 ;
+ RECT 1850.960000 141.140000 2051.060000 142.140000 ;
+ RECT 1850.960000 118.090000 2051.060000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 118.090000 1851.960000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 118.090000 2051.060000 119.090000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 141.140000 1851.960000 142.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 141.140000 2051.060000 142.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 115.240000 1854.790000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 144.500000 1854.790000 145.500000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 115.240000 2048.230000 116.240000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 144.500000 2048.230000 145.500000 ;
+ END
+# end of P/G pin shape extracted from block 'S_term_single'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 3152.250000 2039.020000 3345.620000 ;
+ RECT 1992.920000 3152.250000 1994.020000 3345.620000 ;
+ RECT 2047.230000 3149.400000 2048.230000 3349.660000 ;
+ RECT 1947.920000 3152.250000 1949.020000 3345.620000 ;
+ RECT 1902.920000 3152.250000 1904.020000 3345.620000 ;
+ RECT 1857.920000 3152.250000 1859.020000 3345.620000 ;
+ RECT 1853.790000 3149.400000 1854.790000 3349.660000 ;
+ LAYER met3 ;
+ RECT 2037.920000 3339.220000 2039.020000 3339.700000 ;
+ RECT 2047.230000 3339.220000 2048.230000 3339.700000 ;
+ RECT 2047.230000 3328.340000 2048.230000 3328.820000 ;
+ RECT 2047.230000 3333.780000 2048.230000 3334.260000 ;
+ RECT 2037.920000 3333.780000 2039.020000 3334.260000 ;
+ RECT 2037.920000 3328.340000 2039.020000 3328.820000 ;
+ RECT 2037.920000 3322.900000 2039.020000 3323.380000 ;
+ RECT 2037.920000 3317.460000 2039.020000 3317.940000 ;
+ RECT 2047.230000 3322.900000 2048.230000 3323.380000 ;
+ RECT 2047.230000 3317.460000 2048.230000 3317.940000 ;
+ RECT 2037.920000 3301.140000 2039.020000 3301.620000 ;
+ RECT 2037.920000 3306.580000 2039.020000 3307.060000 ;
+ RECT 2047.230000 3306.580000 2048.230000 3307.060000 ;
+ RECT 2047.230000 3301.140000 2048.230000 3301.620000 ;
+ RECT 2037.920000 3312.020000 2039.020000 3312.500000 ;
+ RECT 2047.230000 3312.020000 2048.230000 3312.500000 ;
+ RECT 1992.920000 3339.220000 1994.020000 3339.700000 ;
+ RECT 1992.920000 3333.780000 1994.020000 3334.260000 ;
+ RECT 1992.920000 3328.340000 1994.020000 3328.820000 ;
+ RECT 1992.920000 3322.900000 1994.020000 3323.380000 ;
+ RECT 1992.920000 3301.140000 1994.020000 3301.620000 ;
+ RECT 1992.920000 3306.580000 1994.020000 3307.060000 ;
+ RECT 1992.920000 3312.020000 1994.020000 3312.500000 ;
+ RECT 1992.920000 3317.460000 1994.020000 3317.940000 ;
+ RECT 2047.230000 3290.260000 2048.230000 3290.740000 ;
+ RECT 2047.230000 3295.700000 2048.230000 3296.180000 ;
+ RECT 2037.920000 3295.700000 2039.020000 3296.180000 ;
+ RECT 2037.920000 3290.260000 2039.020000 3290.740000 ;
+ RECT 2037.920000 3284.820000 2039.020000 3285.300000 ;
+ RECT 2037.920000 3279.380000 2039.020000 3279.860000 ;
+ RECT 2047.230000 3284.820000 2048.230000 3285.300000 ;
+ RECT 2047.230000 3279.380000 2048.230000 3279.860000 ;
+ RECT 2047.230000 3263.060000 2048.230000 3263.540000 ;
+ RECT 2047.230000 3268.500000 2048.230000 3268.980000 ;
+ RECT 2047.230000 3273.940000 2048.230000 3274.420000 ;
+ RECT 2037.920000 3268.500000 2039.020000 3268.980000 ;
+ RECT 2037.920000 3263.060000 2039.020000 3263.540000 ;
+ RECT 2037.920000 3273.940000 2039.020000 3274.420000 ;
+ RECT 2037.920000 3257.620000 2039.020000 3258.100000 ;
+ RECT 2037.920000 3252.180000 2039.020000 3252.660000 ;
+ RECT 2047.230000 3257.620000 2048.230000 3258.100000 ;
+ RECT 2047.230000 3252.180000 2048.230000 3252.660000 ;
+ RECT 1992.920000 3295.700000 1994.020000 3296.180000 ;
+ RECT 1992.920000 3290.260000 1994.020000 3290.740000 ;
+ RECT 1992.920000 3284.820000 1994.020000 3285.300000 ;
+ RECT 1992.920000 3279.380000 1994.020000 3279.860000 ;
+ RECT 1992.920000 3268.500000 1994.020000 3268.980000 ;
+ RECT 1992.920000 3263.060000 1994.020000 3263.540000 ;
+ RECT 1992.920000 3257.620000 1994.020000 3258.100000 ;
+ RECT 1992.920000 3252.180000 1994.020000 3252.660000 ;
+ RECT 1992.920000 3273.940000 1994.020000 3274.420000 ;
+ RECT 1947.920000 3339.220000 1949.020000 3339.700000 ;
+ RECT 1947.920000 3333.780000 1949.020000 3334.260000 ;
+ RECT 1947.920000 3328.340000 1949.020000 3328.820000 ;
+ RECT 1902.920000 3339.220000 1904.020000 3339.700000 ;
+ RECT 1902.920000 3333.780000 1904.020000 3334.260000 ;
+ RECT 1902.920000 3328.340000 1904.020000 3328.820000 ;
+ RECT 1947.920000 3312.020000 1949.020000 3312.500000 ;
+ RECT 1947.920000 3306.580000 1949.020000 3307.060000 ;
+ RECT 1947.920000 3301.140000 1949.020000 3301.620000 ;
+ RECT 1947.920000 3317.460000 1949.020000 3317.940000 ;
+ RECT 1947.920000 3322.900000 1949.020000 3323.380000 ;
+ RECT 1902.920000 3322.900000 1904.020000 3323.380000 ;
+ RECT 1902.920000 3312.020000 1904.020000 3312.500000 ;
+ RECT 1902.920000 3306.580000 1904.020000 3307.060000 ;
+ RECT 1902.920000 3301.140000 1904.020000 3301.620000 ;
+ RECT 1902.920000 3317.460000 1904.020000 3317.940000 ;
+ RECT 1857.920000 3339.220000 1859.020000 3339.700000 ;
+ RECT 1853.790000 3339.220000 1854.790000 3339.700000 ;
+ RECT 1853.790000 3333.780000 1854.790000 3334.260000 ;
+ RECT 1857.920000 3333.780000 1859.020000 3334.260000 ;
+ RECT 1857.920000 3328.340000 1859.020000 3328.820000 ;
+ RECT 1853.790000 3328.340000 1854.790000 3328.820000 ;
+ RECT 1857.920000 3322.900000 1859.020000 3323.380000 ;
+ RECT 1853.790000 3322.900000 1854.790000 3323.380000 ;
+ RECT 1857.920000 3317.460000 1859.020000 3317.940000 ;
+ RECT 1853.790000 3317.460000 1854.790000 3317.940000 ;
+ RECT 1857.920000 3306.580000 1859.020000 3307.060000 ;
+ RECT 1853.790000 3306.580000 1854.790000 3307.060000 ;
+ RECT 1857.920000 3301.140000 1859.020000 3301.620000 ;
+ RECT 1853.790000 3301.140000 1854.790000 3301.620000 ;
+ RECT 1857.920000 3312.020000 1859.020000 3312.500000 ;
+ RECT 1853.790000 3312.020000 1854.790000 3312.500000 ;
+ RECT 1947.920000 3295.700000 1949.020000 3296.180000 ;
+ RECT 1947.920000 3290.260000 1949.020000 3290.740000 ;
+ RECT 1947.920000 3284.820000 1949.020000 3285.300000 ;
+ RECT 1947.920000 3279.380000 1949.020000 3279.860000 ;
+ RECT 1902.920000 3295.700000 1904.020000 3296.180000 ;
+ RECT 1902.920000 3290.260000 1904.020000 3290.740000 ;
+ RECT 1902.920000 3284.820000 1904.020000 3285.300000 ;
+ RECT 1902.920000 3279.380000 1904.020000 3279.860000 ;
+ RECT 1947.920000 3268.500000 1949.020000 3268.980000 ;
+ RECT 1947.920000 3252.180000 1949.020000 3252.660000 ;
+ RECT 1947.920000 3257.620000 1949.020000 3258.100000 ;
+ RECT 1947.920000 3263.060000 1949.020000 3263.540000 ;
+ RECT 1947.920000 3273.940000 1949.020000 3274.420000 ;
+ RECT 1902.920000 3252.180000 1904.020000 3252.660000 ;
+ RECT 1902.920000 3257.620000 1904.020000 3258.100000 ;
+ RECT 1902.920000 3263.060000 1904.020000 3263.540000 ;
+ RECT 1902.920000 3268.500000 1904.020000 3268.980000 ;
+ RECT 1902.920000 3273.940000 1904.020000 3274.420000 ;
+ RECT 1857.920000 3295.700000 1859.020000 3296.180000 ;
+ RECT 1853.790000 3295.700000 1854.790000 3296.180000 ;
+ RECT 1857.920000 3290.260000 1859.020000 3290.740000 ;
+ RECT 1853.790000 3290.260000 1854.790000 3290.740000 ;
+ RECT 1857.920000 3284.820000 1859.020000 3285.300000 ;
+ RECT 1853.790000 3284.820000 1854.790000 3285.300000 ;
+ RECT 1857.920000 3279.380000 1859.020000 3279.860000 ;
+ RECT 1853.790000 3279.380000 1854.790000 3279.860000 ;
+ RECT 1857.920000 3273.940000 1859.020000 3274.420000 ;
+ RECT 1857.920000 3268.500000 1859.020000 3268.980000 ;
+ RECT 1853.790000 3273.940000 1854.790000 3274.420000 ;
+ RECT 1853.790000 3268.500000 1854.790000 3268.980000 ;
+ RECT 1857.920000 3263.060000 1859.020000 3263.540000 ;
+ RECT 1853.790000 3263.060000 1854.790000 3263.540000 ;
+ RECT 1857.920000 3257.620000 1859.020000 3258.100000 ;
+ RECT 1853.790000 3257.620000 1854.790000 3258.100000 ;
+ RECT 1857.920000 3252.180000 1859.020000 3252.660000 ;
+ RECT 1853.790000 3252.180000 1854.790000 3252.660000 ;
+ RECT 2037.920000 3246.740000 2039.020000 3247.220000 ;
+ RECT 2037.920000 3241.300000 2039.020000 3241.780000 ;
+ RECT 2047.230000 3246.740000 2048.230000 3247.220000 ;
+ RECT 2047.230000 3241.300000 2048.230000 3241.780000 ;
+ RECT 2047.230000 3224.980000 2048.230000 3225.460000 ;
+ RECT 2047.230000 3230.420000 2048.230000 3230.900000 ;
+ RECT 2047.230000 3235.860000 2048.230000 3236.340000 ;
+ RECT 2037.920000 3235.860000 2039.020000 3236.340000 ;
+ RECT 2037.920000 3230.420000 2039.020000 3230.900000 ;
+ RECT 2037.920000 3224.980000 2039.020000 3225.460000 ;
+ RECT 2037.920000 3214.100000 2039.020000 3214.580000 ;
+ RECT 2037.920000 3219.540000 2039.020000 3220.020000 ;
+ RECT 2047.230000 3219.540000 2048.230000 3220.020000 ;
+ RECT 2047.230000 3214.100000 2048.230000 3214.580000 ;
+ RECT 2047.230000 3203.220000 2048.230000 3203.700000 ;
+ RECT 2047.230000 3208.660000 2048.230000 3209.140000 ;
+ RECT 2037.920000 3203.220000 2039.020000 3203.700000 ;
+ RECT 2037.920000 3208.660000 2039.020000 3209.140000 ;
+ RECT 1992.920000 3246.740000 1994.020000 3247.220000 ;
+ RECT 1992.920000 3241.300000 1994.020000 3241.780000 ;
+ RECT 1992.920000 3235.860000 1994.020000 3236.340000 ;
+ RECT 1992.920000 3230.420000 1994.020000 3230.900000 ;
+ RECT 1992.920000 3224.980000 1994.020000 3225.460000 ;
+ RECT 1992.920000 3203.220000 1994.020000 3203.700000 ;
+ RECT 1992.920000 3208.660000 1994.020000 3209.140000 ;
+ RECT 1992.920000 3214.100000 1994.020000 3214.580000 ;
+ RECT 1992.920000 3219.540000 1994.020000 3220.020000 ;
+ RECT 2037.920000 3197.780000 2039.020000 3198.260000 ;
+ RECT 2037.920000 3192.340000 2039.020000 3192.820000 ;
+ RECT 2047.230000 3197.780000 2048.230000 3198.260000 ;
+ RECT 2047.230000 3192.340000 2048.230000 3192.820000 ;
+ RECT 2037.920000 3181.460000 2039.020000 3181.940000 ;
+ RECT 2037.920000 3176.020000 2039.020000 3176.500000 ;
+ RECT 2047.230000 3181.460000 2048.230000 3181.940000 ;
+ RECT 2047.230000 3176.020000 2048.230000 3176.500000 ;
+ RECT 2037.920000 3186.900000 2039.020000 3187.380000 ;
+ RECT 2047.230000 3186.900000 2048.230000 3187.380000 ;
+ RECT 2047.230000 3165.140000 2048.230000 3165.620000 ;
+ RECT 2047.230000 3170.580000 2048.230000 3171.060000 ;
+ RECT 2037.920000 3170.580000 2039.020000 3171.060000 ;
+ RECT 2037.920000 3165.140000 2039.020000 3165.620000 ;
+ RECT 2037.920000 3159.700000 2039.020000 3160.180000 ;
+ RECT 2037.920000 3154.260000 2039.020000 3154.740000 ;
+ RECT 2047.230000 3159.700000 2048.230000 3160.180000 ;
+ RECT 2047.230000 3154.260000 2048.230000 3154.740000 ;
+ RECT 1992.920000 3197.780000 1994.020000 3198.260000 ;
+ RECT 1992.920000 3192.340000 1994.020000 3192.820000 ;
+ RECT 1992.920000 3186.900000 1994.020000 3187.380000 ;
+ RECT 1992.920000 3181.460000 1994.020000 3181.940000 ;
+ RECT 1992.920000 3176.020000 1994.020000 3176.500000 ;
+ RECT 1992.920000 3170.580000 1994.020000 3171.060000 ;
+ RECT 1992.920000 3165.140000 1994.020000 3165.620000 ;
+ RECT 1992.920000 3159.700000 1994.020000 3160.180000 ;
+ RECT 1992.920000 3154.260000 1994.020000 3154.740000 ;
+ RECT 1947.920000 3246.740000 1949.020000 3247.220000 ;
+ RECT 1947.920000 3241.300000 1949.020000 3241.780000 ;
+ RECT 1947.920000 3235.860000 1949.020000 3236.340000 ;
+ RECT 1947.920000 3230.420000 1949.020000 3230.900000 ;
+ RECT 1947.920000 3224.980000 1949.020000 3225.460000 ;
+ RECT 1902.920000 3246.740000 1904.020000 3247.220000 ;
+ RECT 1902.920000 3241.300000 1904.020000 3241.780000 ;
+ RECT 1902.920000 3235.860000 1904.020000 3236.340000 ;
+ RECT 1902.920000 3230.420000 1904.020000 3230.900000 ;
+ RECT 1902.920000 3224.980000 1904.020000 3225.460000 ;
+ RECT 1947.920000 3219.540000 1949.020000 3220.020000 ;
+ RECT 1947.920000 3214.100000 1949.020000 3214.580000 ;
+ RECT 1947.920000 3208.660000 1949.020000 3209.140000 ;
+ RECT 1947.920000 3203.220000 1949.020000 3203.700000 ;
+ RECT 1902.920000 3214.100000 1904.020000 3214.580000 ;
+ RECT 1902.920000 3208.660000 1904.020000 3209.140000 ;
+ RECT 1902.920000 3203.220000 1904.020000 3203.700000 ;
+ RECT 1902.920000 3219.540000 1904.020000 3220.020000 ;
+ RECT 1857.920000 3246.740000 1859.020000 3247.220000 ;
+ RECT 1853.790000 3246.740000 1854.790000 3247.220000 ;
+ RECT 1857.920000 3241.300000 1859.020000 3241.780000 ;
+ RECT 1853.790000 3241.300000 1854.790000 3241.780000 ;
+ RECT 1857.920000 3235.860000 1859.020000 3236.340000 ;
+ RECT 1853.790000 3235.860000 1854.790000 3236.340000 ;
+ RECT 1857.920000 3224.980000 1859.020000 3225.460000 ;
+ RECT 1853.790000 3224.980000 1854.790000 3225.460000 ;
+ RECT 1853.790000 3230.420000 1854.790000 3230.900000 ;
+ RECT 1857.920000 3230.420000 1859.020000 3230.900000 ;
+ RECT 1857.920000 3219.540000 1859.020000 3220.020000 ;
+ RECT 1853.790000 3219.540000 1854.790000 3220.020000 ;
+ RECT 1857.920000 3214.100000 1859.020000 3214.580000 ;
+ RECT 1853.790000 3214.100000 1854.790000 3214.580000 ;
+ RECT 1857.920000 3208.660000 1859.020000 3209.140000 ;
+ RECT 1853.790000 3208.660000 1854.790000 3209.140000 ;
+ RECT 1857.920000 3203.220000 1859.020000 3203.700000 ;
+ RECT 1853.790000 3203.220000 1854.790000 3203.700000 ;
+ RECT 1947.920000 3197.780000 1949.020000 3198.260000 ;
+ RECT 1947.920000 3192.340000 1949.020000 3192.820000 ;
+ RECT 1947.920000 3186.900000 1949.020000 3187.380000 ;
+ RECT 1947.920000 3181.460000 1949.020000 3181.940000 ;
+ RECT 1947.920000 3176.020000 1949.020000 3176.500000 ;
+ RECT 1902.920000 3197.780000 1904.020000 3198.260000 ;
+ RECT 1902.920000 3192.340000 1904.020000 3192.820000 ;
+ RECT 1902.920000 3186.900000 1904.020000 3187.380000 ;
+ RECT 1902.920000 3181.460000 1904.020000 3181.940000 ;
+ RECT 1902.920000 3176.020000 1904.020000 3176.500000 ;
+ RECT 1947.920000 3154.260000 1949.020000 3154.740000 ;
+ RECT 1947.920000 3159.700000 1949.020000 3160.180000 ;
+ RECT 1947.920000 3165.140000 1949.020000 3165.620000 ;
+ RECT 1947.920000 3170.580000 1949.020000 3171.060000 ;
+ RECT 1902.920000 3154.260000 1904.020000 3154.740000 ;
+ RECT 1902.920000 3159.700000 1904.020000 3160.180000 ;
+ RECT 1902.920000 3165.140000 1904.020000 3165.620000 ;
+ RECT 1902.920000 3170.580000 1904.020000 3171.060000 ;
+ RECT 1857.920000 3197.780000 1859.020000 3198.260000 ;
+ RECT 1853.790000 3197.780000 1854.790000 3198.260000 ;
+ RECT 1857.920000 3192.340000 1859.020000 3192.820000 ;
+ RECT 1853.790000 3192.340000 1854.790000 3192.820000 ;
+ RECT 1857.920000 3181.460000 1859.020000 3181.940000 ;
+ RECT 1853.790000 3181.460000 1854.790000 3181.940000 ;
+ RECT 1857.920000 3176.020000 1859.020000 3176.500000 ;
+ RECT 1853.790000 3176.020000 1854.790000 3176.500000 ;
+ RECT 1857.920000 3186.900000 1859.020000 3187.380000 ;
+ RECT 1853.790000 3186.900000 1854.790000 3187.380000 ;
+ RECT 1857.920000 3170.580000 1859.020000 3171.060000 ;
+ RECT 1853.790000 3170.580000 1854.790000 3171.060000 ;
+ RECT 1857.920000 3165.140000 1859.020000 3165.620000 ;
+ RECT 1853.790000 3165.140000 1854.790000 3165.620000 ;
+ RECT 1857.920000 3159.700000 1859.020000 3160.180000 ;
+ RECT 1857.920000 3154.260000 1859.020000 3154.740000 ;
+ RECT 1853.790000 3159.700000 1854.790000 3160.180000 ;
+ RECT 1853.790000 3154.260000 1854.790000 3154.740000 ;
+ RECT 1850.960000 3344.620000 2051.060000 3345.620000 ;
+ RECT 1850.960000 3152.250000 2051.060000 3153.250000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 3149.400000 1854.790000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 3348.660000 1854.790000 3349.660000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 3149.400000 2048.230000 3150.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 3348.660000 2048.230000 3349.660000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 3152.250000 1851.960000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 3152.250000 2051.060000 3153.250000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 3344.620000 1851.960000 3345.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 3344.620000 2051.060000 3345.620000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 2951.990000 2039.020000 3145.360000 ;
+ RECT 1992.920000 2951.990000 1994.020000 3145.360000 ;
+ RECT 2047.230000 2949.140000 2048.230000 3149.400000 ;
+ RECT 1947.920000 2951.990000 1949.020000 3145.360000 ;
+ RECT 1902.920000 2951.990000 1904.020000 3145.360000 ;
+ RECT 1857.920000 2951.990000 1859.020000 3145.360000 ;
+ RECT 1853.790000 2949.140000 1854.790000 3149.400000 ;
+ LAYER met3 ;
+ RECT 2037.920000 3138.960000 2039.020000 3139.440000 ;
+ RECT 2047.230000 3138.960000 2048.230000 3139.440000 ;
+ RECT 2047.230000 3128.080000 2048.230000 3128.560000 ;
+ RECT 2047.230000 3133.520000 2048.230000 3134.000000 ;
+ RECT 2037.920000 3133.520000 2039.020000 3134.000000 ;
+ RECT 2037.920000 3128.080000 2039.020000 3128.560000 ;
+ RECT 2037.920000 3122.640000 2039.020000 3123.120000 ;
+ RECT 2037.920000 3117.200000 2039.020000 3117.680000 ;
+ RECT 2047.230000 3122.640000 2048.230000 3123.120000 ;
+ RECT 2047.230000 3117.200000 2048.230000 3117.680000 ;
+ RECT 2037.920000 3100.880000 2039.020000 3101.360000 ;
+ RECT 2037.920000 3106.320000 2039.020000 3106.800000 ;
+ RECT 2047.230000 3106.320000 2048.230000 3106.800000 ;
+ RECT 2047.230000 3100.880000 2048.230000 3101.360000 ;
+ RECT 2037.920000 3111.760000 2039.020000 3112.240000 ;
+ RECT 2047.230000 3111.760000 2048.230000 3112.240000 ;
+ RECT 1992.920000 3138.960000 1994.020000 3139.440000 ;
+ RECT 1992.920000 3133.520000 1994.020000 3134.000000 ;
+ RECT 1992.920000 3128.080000 1994.020000 3128.560000 ;
+ RECT 1992.920000 3122.640000 1994.020000 3123.120000 ;
+ RECT 1992.920000 3100.880000 1994.020000 3101.360000 ;
+ RECT 1992.920000 3106.320000 1994.020000 3106.800000 ;
+ RECT 1992.920000 3111.760000 1994.020000 3112.240000 ;
+ RECT 1992.920000 3117.200000 1994.020000 3117.680000 ;
+ RECT 2047.230000 3090.000000 2048.230000 3090.480000 ;
+ RECT 2047.230000 3095.440000 2048.230000 3095.920000 ;
+ RECT 2037.920000 3095.440000 2039.020000 3095.920000 ;
+ RECT 2037.920000 3090.000000 2039.020000 3090.480000 ;
+ RECT 2037.920000 3084.560000 2039.020000 3085.040000 ;
+ RECT 2037.920000 3079.120000 2039.020000 3079.600000 ;
+ RECT 2047.230000 3084.560000 2048.230000 3085.040000 ;
+ RECT 2047.230000 3079.120000 2048.230000 3079.600000 ;
+ RECT 2047.230000 3062.800000 2048.230000 3063.280000 ;
+ RECT 2047.230000 3068.240000 2048.230000 3068.720000 ;
+ RECT 2047.230000 3073.680000 2048.230000 3074.160000 ;
+ RECT 2037.920000 3068.240000 2039.020000 3068.720000 ;
+ RECT 2037.920000 3062.800000 2039.020000 3063.280000 ;
+ RECT 2037.920000 3073.680000 2039.020000 3074.160000 ;
+ RECT 2037.920000 3057.360000 2039.020000 3057.840000 ;
+ RECT 2037.920000 3051.920000 2039.020000 3052.400000 ;
+ RECT 2047.230000 3057.360000 2048.230000 3057.840000 ;
+ RECT 2047.230000 3051.920000 2048.230000 3052.400000 ;
+ RECT 1992.920000 3095.440000 1994.020000 3095.920000 ;
+ RECT 1992.920000 3090.000000 1994.020000 3090.480000 ;
+ RECT 1992.920000 3084.560000 1994.020000 3085.040000 ;
+ RECT 1992.920000 3079.120000 1994.020000 3079.600000 ;
+ RECT 1992.920000 3068.240000 1994.020000 3068.720000 ;
+ RECT 1992.920000 3062.800000 1994.020000 3063.280000 ;
+ RECT 1992.920000 3057.360000 1994.020000 3057.840000 ;
+ RECT 1992.920000 3051.920000 1994.020000 3052.400000 ;
+ RECT 1992.920000 3073.680000 1994.020000 3074.160000 ;
+ RECT 1947.920000 3138.960000 1949.020000 3139.440000 ;
+ RECT 1947.920000 3133.520000 1949.020000 3134.000000 ;
+ RECT 1947.920000 3128.080000 1949.020000 3128.560000 ;
+ RECT 1902.920000 3138.960000 1904.020000 3139.440000 ;
+ RECT 1902.920000 3133.520000 1904.020000 3134.000000 ;
+ RECT 1902.920000 3128.080000 1904.020000 3128.560000 ;
+ RECT 1947.920000 3111.760000 1949.020000 3112.240000 ;
+ RECT 1947.920000 3106.320000 1949.020000 3106.800000 ;
+ RECT 1947.920000 3100.880000 1949.020000 3101.360000 ;
+ RECT 1947.920000 3117.200000 1949.020000 3117.680000 ;
+ RECT 1947.920000 3122.640000 1949.020000 3123.120000 ;
+ RECT 1902.920000 3122.640000 1904.020000 3123.120000 ;
+ RECT 1902.920000 3111.760000 1904.020000 3112.240000 ;
+ RECT 1902.920000 3106.320000 1904.020000 3106.800000 ;
+ RECT 1902.920000 3100.880000 1904.020000 3101.360000 ;
+ RECT 1902.920000 3117.200000 1904.020000 3117.680000 ;
+ RECT 1857.920000 3138.960000 1859.020000 3139.440000 ;
+ RECT 1853.790000 3138.960000 1854.790000 3139.440000 ;
+ RECT 1853.790000 3133.520000 1854.790000 3134.000000 ;
+ RECT 1857.920000 3133.520000 1859.020000 3134.000000 ;
+ RECT 1857.920000 3128.080000 1859.020000 3128.560000 ;
+ RECT 1853.790000 3128.080000 1854.790000 3128.560000 ;
+ RECT 1857.920000 3122.640000 1859.020000 3123.120000 ;
+ RECT 1853.790000 3122.640000 1854.790000 3123.120000 ;
+ RECT 1857.920000 3117.200000 1859.020000 3117.680000 ;
+ RECT 1853.790000 3117.200000 1854.790000 3117.680000 ;
+ RECT 1857.920000 3106.320000 1859.020000 3106.800000 ;
+ RECT 1853.790000 3106.320000 1854.790000 3106.800000 ;
+ RECT 1857.920000 3100.880000 1859.020000 3101.360000 ;
+ RECT 1853.790000 3100.880000 1854.790000 3101.360000 ;
+ RECT 1857.920000 3111.760000 1859.020000 3112.240000 ;
+ RECT 1853.790000 3111.760000 1854.790000 3112.240000 ;
+ RECT 1947.920000 3095.440000 1949.020000 3095.920000 ;
+ RECT 1947.920000 3090.000000 1949.020000 3090.480000 ;
+ RECT 1947.920000 3084.560000 1949.020000 3085.040000 ;
+ RECT 1947.920000 3079.120000 1949.020000 3079.600000 ;
+ RECT 1902.920000 3095.440000 1904.020000 3095.920000 ;
+ RECT 1902.920000 3090.000000 1904.020000 3090.480000 ;
+ RECT 1902.920000 3084.560000 1904.020000 3085.040000 ;
+ RECT 1902.920000 3079.120000 1904.020000 3079.600000 ;
+ RECT 1947.920000 3068.240000 1949.020000 3068.720000 ;
+ RECT 1947.920000 3051.920000 1949.020000 3052.400000 ;
+ RECT 1947.920000 3057.360000 1949.020000 3057.840000 ;
+ RECT 1947.920000 3062.800000 1949.020000 3063.280000 ;
+ RECT 1947.920000 3073.680000 1949.020000 3074.160000 ;
+ RECT 1902.920000 3051.920000 1904.020000 3052.400000 ;
+ RECT 1902.920000 3057.360000 1904.020000 3057.840000 ;
+ RECT 1902.920000 3062.800000 1904.020000 3063.280000 ;
+ RECT 1902.920000 3068.240000 1904.020000 3068.720000 ;
+ RECT 1902.920000 3073.680000 1904.020000 3074.160000 ;
+ RECT 1857.920000 3095.440000 1859.020000 3095.920000 ;
+ RECT 1853.790000 3095.440000 1854.790000 3095.920000 ;
+ RECT 1857.920000 3090.000000 1859.020000 3090.480000 ;
+ RECT 1853.790000 3090.000000 1854.790000 3090.480000 ;
+ RECT 1857.920000 3084.560000 1859.020000 3085.040000 ;
+ RECT 1853.790000 3084.560000 1854.790000 3085.040000 ;
+ RECT 1857.920000 3079.120000 1859.020000 3079.600000 ;
+ RECT 1853.790000 3079.120000 1854.790000 3079.600000 ;
+ RECT 1857.920000 3073.680000 1859.020000 3074.160000 ;
+ RECT 1857.920000 3068.240000 1859.020000 3068.720000 ;
+ RECT 1853.790000 3073.680000 1854.790000 3074.160000 ;
+ RECT 1853.790000 3068.240000 1854.790000 3068.720000 ;
+ RECT 1857.920000 3062.800000 1859.020000 3063.280000 ;
+ RECT 1853.790000 3062.800000 1854.790000 3063.280000 ;
+ RECT 1857.920000 3057.360000 1859.020000 3057.840000 ;
+ RECT 1853.790000 3057.360000 1854.790000 3057.840000 ;
+ RECT 1857.920000 3051.920000 1859.020000 3052.400000 ;
+ RECT 1853.790000 3051.920000 1854.790000 3052.400000 ;
+ RECT 2037.920000 3046.480000 2039.020000 3046.960000 ;
+ RECT 2037.920000 3041.040000 2039.020000 3041.520000 ;
+ RECT 2047.230000 3046.480000 2048.230000 3046.960000 ;
+ RECT 2047.230000 3041.040000 2048.230000 3041.520000 ;
+ RECT 2047.230000 3024.720000 2048.230000 3025.200000 ;
+ RECT 2047.230000 3030.160000 2048.230000 3030.640000 ;
+ RECT 2047.230000 3035.600000 2048.230000 3036.080000 ;
+ RECT 2037.920000 3035.600000 2039.020000 3036.080000 ;
+ RECT 2037.920000 3030.160000 2039.020000 3030.640000 ;
+ RECT 2037.920000 3024.720000 2039.020000 3025.200000 ;
+ RECT 2037.920000 3013.840000 2039.020000 3014.320000 ;
+ RECT 2037.920000 3019.280000 2039.020000 3019.760000 ;
+ RECT 2047.230000 3019.280000 2048.230000 3019.760000 ;
+ RECT 2047.230000 3013.840000 2048.230000 3014.320000 ;
+ RECT 2047.230000 3002.960000 2048.230000 3003.440000 ;
+ RECT 2047.230000 3008.400000 2048.230000 3008.880000 ;
+ RECT 2037.920000 3002.960000 2039.020000 3003.440000 ;
+ RECT 2037.920000 3008.400000 2039.020000 3008.880000 ;
+ RECT 1992.920000 3046.480000 1994.020000 3046.960000 ;
+ RECT 1992.920000 3041.040000 1994.020000 3041.520000 ;
+ RECT 1992.920000 3035.600000 1994.020000 3036.080000 ;
+ RECT 1992.920000 3030.160000 1994.020000 3030.640000 ;
+ RECT 1992.920000 3024.720000 1994.020000 3025.200000 ;
+ RECT 1992.920000 3002.960000 1994.020000 3003.440000 ;
+ RECT 1992.920000 3008.400000 1994.020000 3008.880000 ;
+ RECT 1992.920000 3013.840000 1994.020000 3014.320000 ;
+ RECT 1992.920000 3019.280000 1994.020000 3019.760000 ;
+ RECT 2037.920000 2997.520000 2039.020000 2998.000000 ;
+ RECT 2037.920000 2992.080000 2039.020000 2992.560000 ;
+ RECT 2047.230000 2997.520000 2048.230000 2998.000000 ;
+ RECT 2047.230000 2992.080000 2048.230000 2992.560000 ;
+ RECT 2037.920000 2981.200000 2039.020000 2981.680000 ;
+ RECT 2037.920000 2975.760000 2039.020000 2976.240000 ;
+ RECT 2047.230000 2981.200000 2048.230000 2981.680000 ;
+ RECT 2047.230000 2975.760000 2048.230000 2976.240000 ;
+ RECT 2037.920000 2986.640000 2039.020000 2987.120000 ;
+ RECT 2047.230000 2986.640000 2048.230000 2987.120000 ;
+ RECT 2047.230000 2964.880000 2048.230000 2965.360000 ;
+ RECT 2047.230000 2970.320000 2048.230000 2970.800000 ;
+ RECT 2037.920000 2970.320000 2039.020000 2970.800000 ;
+ RECT 2037.920000 2964.880000 2039.020000 2965.360000 ;
+ RECT 2037.920000 2959.440000 2039.020000 2959.920000 ;
+ RECT 2037.920000 2954.000000 2039.020000 2954.480000 ;
+ RECT 2047.230000 2959.440000 2048.230000 2959.920000 ;
+ RECT 2047.230000 2954.000000 2048.230000 2954.480000 ;
+ RECT 1992.920000 2997.520000 1994.020000 2998.000000 ;
+ RECT 1992.920000 2992.080000 1994.020000 2992.560000 ;
+ RECT 1992.920000 2986.640000 1994.020000 2987.120000 ;
+ RECT 1992.920000 2981.200000 1994.020000 2981.680000 ;
+ RECT 1992.920000 2975.760000 1994.020000 2976.240000 ;
+ RECT 1992.920000 2970.320000 1994.020000 2970.800000 ;
+ RECT 1992.920000 2964.880000 1994.020000 2965.360000 ;
+ RECT 1992.920000 2959.440000 1994.020000 2959.920000 ;
+ RECT 1992.920000 2954.000000 1994.020000 2954.480000 ;
+ RECT 1947.920000 3046.480000 1949.020000 3046.960000 ;
+ RECT 1947.920000 3041.040000 1949.020000 3041.520000 ;
+ RECT 1947.920000 3035.600000 1949.020000 3036.080000 ;
+ RECT 1947.920000 3030.160000 1949.020000 3030.640000 ;
+ RECT 1947.920000 3024.720000 1949.020000 3025.200000 ;
+ RECT 1902.920000 3046.480000 1904.020000 3046.960000 ;
+ RECT 1902.920000 3041.040000 1904.020000 3041.520000 ;
+ RECT 1902.920000 3035.600000 1904.020000 3036.080000 ;
+ RECT 1902.920000 3030.160000 1904.020000 3030.640000 ;
+ RECT 1902.920000 3024.720000 1904.020000 3025.200000 ;
+ RECT 1947.920000 3019.280000 1949.020000 3019.760000 ;
+ RECT 1947.920000 3013.840000 1949.020000 3014.320000 ;
+ RECT 1947.920000 3008.400000 1949.020000 3008.880000 ;
+ RECT 1947.920000 3002.960000 1949.020000 3003.440000 ;
+ RECT 1902.920000 3013.840000 1904.020000 3014.320000 ;
+ RECT 1902.920000 3008.400000 1904.020000 3008.880000 ;
+ RECT 1902.920000 3002.960000 1904.020000 3003.440000 ;
+ RECT 1902.920000 3019.280000 1904.020000 3019.760000 ;
+ RECT 1857.920000 3046.480000 1859.020000 3046.960000 ;
+ RECT 1853.790000 3046.480000 1854.790000 3046.960000 ;
+ RECT 1857.920000 3041.040000 1859.020000 3041.520000 ;
+ RECT 1853.790000 3041.040000 1854.790000 3041.520000 ;
+ RECT 1857.920000 3035.600000 1859.020000 3036.080000 ;
+ RECT 1853.790000 3035.600000 1854.790000 3036.080000 ;
+ RECT 1857.920000 3024.720000 1859.020000 3025.200000 ;
+ RECT 1853.790000 3024.720000 1854.790000 3025.200000 ;
+ RECT 1853.790000 3030.160000 1854.790000 3030.640000 ;
+ RECT 1857.920000 3030.160000 1859.020000 3030.640000 ;
+ RECT 1857.920000 3019.280000 1859.020000 3019.760000 ;
+ RECT 1853.790000 3019.280000 1854.790000 3019.760000 ;
+ RECT 1857.920000 3013.840000 1859.020000 3014.320000 ;
+ RECT 1853.790000 3013.840000 1854.790000 3014.320000 ;
+ RECT 1857.920000 3008.400000 1859.020000 3008.880000 ;
+ RECT 1853.790000 3008.400000 1854.790000 3008.880000 ;
+ RECT 1857.920000 3002.960000 1859.020000 3003.440000 ;
+ RECT 1853.790000 3002.960000 1854.790000 3003.440000 ;
+ RECT 1947.920000 2997.520000 1949.020000 2998.000000 ;
+ RECT 1947.920000 2992.080000 1949.020000 2992.560000 ;
+ RECT 1947.920000 2986.640000 1949.020000 2987.120000 ;
+ RECT 1947.920000 2981.200000 1949.020000 2981.680000 ;
+ RECT 1947.920000 2975.760000 1949.020000 2976.240000 ;
+ RECT 1902.920000 2997.520000 1904.020000 2998.000000 ;
+ RECT 1902.920000 2992.080000 1904.020000 2992.560000 ;
+ RECT 1902.920000 2986.640000 1904.020000 2987.120000 ;
+ RECT 1902.920000 2981.200000 1904.020000 2981.680000 ;
+ RECT 1902.920000 2975.760000 1904.020000 2976.240000 ;
+ RECT 1947.920000 2954.000000 1949.020000 2954.480000 ;
+ RECT 1947.920000 2959.440000 1949.020000 2959.920000 ;
+ RECT 1947.920000 2964.880000 1949.020000 2965.360000 ;
+ RECT 1947.920000 2970.320000 1949.020000 2970.800000 ;
+ RECT 1902.920000 2954.000000 1904.020000 2954.480000 ;
+ RECT 1902.920000 2959.440000 1904.020000 2959.920000 ;
+ RECT 1902.920000 2964.880000 1904.020000 2965.360000 ;
+ RECT 1902.920000 2970.320000 1904.020000 2970.800000 ;
+ RECT 1857.920000 2997.520000 1859.020000 2998.000000 ;
+ RECT 1853.790000 2997.520000 1854.790000 2998.000000 ;
+ RECT 1857.920000 2992.080000 1859.020000 2992.560000 ;
+ RECT 1853.790000 2992.080000 1854.790000 2992.560000 ;
+ RECT 1857.920000 2981.200000 1859.020000 2981.680000 ;
+ RECT 1853.790000 2981.200000 1854.790000 2981.680000 ;
+ RECT 1857.920000 2975.760000 1859.020000 2976.240000 ;
+ RECT 1853.790000 2975.760000 1854.790000 2976.240000 ;
+ RECT 1857.920000 2986.640000 1859.020000 2987.120000 ;
+ RECT 1853.790000 2986.640000 1854.790000 2987.120000 ;
+ RECT 1857.920000 2970.320000 1859.020000 2970.800000 ;
+ RECT 1853.790000 2970.320000 1854.790000 2970.800000 ;
+ RECT 1857.920000 2964.880000 1859.020000 2965.360000 ;
+ RECT 1853.790000 2964.880000 1854.790000 2965.360000 ;
+ RECT 1857.920000 2959.440000 1859.020000 2959.920000 ;
+ RECT 1857.920000 2954.000000 1859.020000 2954.480000 ;
+ RECT 1853.790000 2959.440000 1854.790000 2959.920000 ;
+ RECT 1853.790000 2954.000000 1854.790000 2954.480000 ;
+ RECT 1850.960000 3144.360000 2051.060000 3145.360000 ;
+ RECT 1850.960000 2951.990000 2051.060000 2952.990000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 2949.140000 1854.790000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 3148.400000 1854.790000 3149.400000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 2949.140000 2048.230000 2950.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 3148.400000 2048.230000 3149.400000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2951.990000 1851.960000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2951.990000 2051.060000 2952.990000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 3144.360000 1851.960000 3145.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 3144.360000 2051.060000 3145.360000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 2751.730000 2039.020000 2945.100000 ;
+ RECT 1992.920000 2751.730000 1994.020000 2945.100000 ;
+ RECT 2047.230000 2748.880000 2048.230000 2949.140000 ;
+ RECT 1947.920000 2751.730000 1949.020000 2945.100000 ;
+ RECT 1902.920000 2751.730000 1904.020000 2945.100000 ;
+ RECT 1857.920000 2751.730000 1859.020000 2945.100000 ;
+ RECT 1853.790000 2748.880000 1854.790000 2949.140000 ;
+ LAYER met3 ;
+ RECT 2037.920000 2938.700000 2039.020000 2939.180000 ;
+ RECT 2047.230000 2938.700000 2048.230000 2939.180000 ;
+ RECT 2047.230000 2927.820000 2048.230000 2928.300000 ;
+ RECT 2047.230000 2933.260000 2048.230000 2933.740000 ;
+ RECT 2037.920000 2933.260000 2039.020000 2933.740000 ;
+ RECT 2037.920000 2927.820000 2039.020000 2928.300000 ;
+ RECT 2037.920000 2922.380000 2039.020000 2922.860000 ;
+ RECT 2037.920000 2916.940000 2039.020000 2917.420000 ;
+ RECT 2047.230000 2922.380000 2048.230000 2922.860000 ;
+ RECT 2047.230000 2916.940000 2048.230000 2917.420000 ;
+ RECT 2037.920000 2900.620000 2039.020000 2901.100000 ;
+ RECT 2037.920000 2906.060000 2039.020000 2906.540000 ;
+ RECT 2047.230000 2906.060000 2048.230000 2906.540000 ;
+ RECT 2047.230000 2900.620000 2048.230000 2901.100000 ;
+ RECT 2037.920000 2911.500000 2039.020000 2911.980000 ;
+ RECT 2047.230000 2911.500000 2048.230000 2911.980000 ;
+ RECT 1992.920000 2938.700000 1994.020000 2939.180000 ;
+ RECT 1992.920000 2933.260000 1994.020000 2933.740000 ;
+ RECT 1992.920000 2927.820000 1994.020000 2928.300000 ;
+ RECT 1992.920000 2922.380000 1994.020000 2922.860000 ;
+ RECT 1992.920000 2900.620000 1994.020000 2901.100000 ;
+ RECT 1992.920000 2906.060000 1994.020000 2906.540000 ;
+ RECT 1992.920000 2911.500000 1994.020000 2911.980000 ;
+ RECT 1992.920000 2916.940000 1994.020000 2917.420000 ;
+ RECT 2047.230000 2889.740000 2048.230000 2890.220000 ;
+ RECT 2047.230000 2895.180000 2048.230000 2895.660000 ;
+ RECT 2037.920000 2895.180000 2039.020000 2895.660000 ;
+ RECT 2037.920000 2889.740000 2039.020000 2890.220000 ;
+ RECT 2037.920000 2884.300000 2039.020000 2884.780000 ;
+ RECT 2037.920000 2878.860000 2039.020000 2879.340000 ;
+ RECT 2047.230000 2884.300000 2048.230000 2884.780000 ;
+ RECT 2047.230000 2878.860000 2048.230000 2879.340000 ;
+ RECT 2047.230000 2862.540000 2048.230000 2863.020000 ;
+ RECT 2047.230000 2867.980000 2048.230000 2868.460000 ;
+ RECT 2047.230000 2873.420000 2048.230000 2873.900000 ;
+ RECT 2037.920000 2867.980000 2039.020000 2868.460000 ;
+ RECT 2037.920000 2862.540000 2039.020000 2863.020000 ;
+ RECT 2037.920000 2873.420000 2039.020000 2873.900000 ;
+ RECT 2037.920000 2857.100000 2039.020000 2857.580000 ;
+ RECT 2037.920000 2851.660000 2039.020000 2852.140000 ;
+ RECT 2047.230000 2857.100000 2048.230000 2857.580000 ;
+ RECT 2047.230000 2851.660000 2048.230000 2852.140000 ;
+ RECT 1992.920000 2895.180000 1994.020000 2895.660000 ;
+ RECT 1992.920000 2889.740000 1994.020000 2890.220000 ;
+ RECT 1992.920000 2884.300000 1994.020000 2884.780000 ;
+ RECT 1992.920000 2878.860000 1994.020000 2879.340000 ;
+ RECT 1992.920000 2867.980000 1994.020000 2868.460000 ;
+ RECT 1992.920000 2862.540000 1994.020000 2863.020000 ;
+ RECT 1992.920000 2857.100000 1994.020000 2857.580000 ;
+ RECT 1992.920000 2851.660000 1994.020000 2852.140000 ;
+ RECT 1992.920000 2873.420000 1994.020000 2873.900000 ;
+ RECT 1947.920000 2938.700000 1949.020000 2939.180000 ;
+ RECT 1947.920000 2933.260000 1949.020000 2933.740000 ;
+ RECT 1947.920000 2927.820000 1949.020000 2928.300000 ;
+ RECT 1902.920000 2938.700000 1904.020000 2939.180000 ;
+ RECT 1902.920000 2933.260000 1904.020000 2933.740000 ;
+ RECT 1902.920000 2927.820000 1904.020000 2928.300000 ;
+ RECT 1947.920000 2911.500000 1949.020000 2911.980000 ;
+ RECT 1947.920000 2906.060000 1949.020000 2906.540000 ;
+ RECT 1947.920000 2900.620000 1949.020000 2901.100000 ;
+ RECT 1947.920000 2916.940000 1949.020000 2917.420000 ;
+ RECT 1947.920000 2922.380000 1949.020000 2922.860000 ;
+ RECT 1902.920000 2922.380000 1904.020000 2922.860000 ;
+ RECT 1902.920000 2911.500000 1904.020000 2911.980000 ;
+ RECT 1902.920000 2906.060000 1904.020000 2906.540000 ;
+ RECT 1902.920000 2900.620000 1904.020000 2901.100000 ;
+ RECT 1902.920000 2916.940000 1904.020000 2917.420000 ;
+ RECT 1857.920000 2938.700000 1859.020000 2939.180000 ;
+ RECT 1853.790000 2938.700000 1854.790000 2939.180000 ;
+ RECT 1853.790000 2933.260000 1854.790000 2933.740000 ;
+ RECT 1857.920000 2933.260000 1859.020000 2933.740000 ;
+ RECT 1857.920000 2927.820000 1859.020000 2928.300000 ;
+ RECT 1853.790000 2927.820000 1854.790000 2928.300000 ;
+ RECT 1857.920000 2922.380000 1859.020000 2922.860000 ;
+ RECT 1853.790000 2922.380000 1854.790000 2922.860000 ;
+ RECT 1857.920000 2916.940000 1859.020000 2917.420000 ;
+ RECT 1853.790000 2916.940000 1854.790000 2917.420000 ;
+ RECT 1857.920000 2906.060000 1859.020000 2906.540000 ;
+ RECT 1853.790000 2906.060000 1854.790000 2906.540000 ;
+ RECT 1857.920000 2900.620000 1859.020000 2901.100000 ;
+ RECT 1853.790000 2900.620000 1854.790000 2901.100000 ;
+ RECT 1857.920000 2911.500000 1859.020000 2911.980000 ;
+ RECT 1853.790000 2911.500000 1854.790000 2911.980000 ;
+ RECT 1947.920000 2895.180000 1949.020000 2895.660000 ;
+ RECT 1947.920000 2889.740000 1949.020000 2890.220000 ;
+ RECT 1947.920000 2884.300000 1949.020000 2884.780000 ;
+ RECT 1947.920000 2878.860000 1949.020000 2879.340000 ;
+ RECT 1902.920000 2895.180000 1904.020000 2895.660000 ;
+ RECT 1902.920000 2889.740000 1904.020000 2890.220000 ;
+ RECT 1902.920000 2884.300000 1904.020000 2884.780000 ;
+ RECT 1902.920000 2878.860000 1904.020000 2879.340000 ;
+ RECT 1947.920000 2867.980000 1949.020000 2868.460000 ;
+ RECT 1947.920000 2851.660000 1949.020000 2852.140000 ;
+ RECT 1947.920000 2857.100000 1949.020000 2857.580000 ;
+ RECT 1947.920000 2862.540000 1949.020000 2863.020000 ;
+ RECT 1947.920000 2873.420000 1949.020000 2873.900000 ;
+ RECT 1902.920000 2851.660000 1904.020000 2852.140000 ;
+ RECT 1902.920000 2857.100000 1904.020000 2857.580000 ;
+ RECT 1902.920000 2862.540000 1904.020000 2863.020000 ;
+ RECT 1902.920000 2867.980000 1904.020000 2868.460000 ;
+ RECT 1902.920000 2873.420000 1904.020000 2873.900000 ;
+ RECT 1857.920000 2895.180000 1859.020000 2895.660000 ;
+ RECT 1853.790000 2895.180000 1854.790000 2895.660000 ;
+ RECT 1857.920000 2889.740000 1859.020000 2890.220000 ;
+ RECT 1853.790000 2889.740000 1854.790000 2890.220000 ;
+ RECT 1857.920000 2884.300000 1859.020000 2884.780000 ;
+ RECT 1853.790000 2884.300000 1854.790000 2884.780000 ;
+ RECT 1857.920000 2878.860000 1859.020000 2879.340000 ;
+ RECT 1853.790000 2878.860000 1854.790000 2879.340000 ;
+ RECT 1857.920000 2873.420000 1859.020000 2873.900000 ;
+ RECT 1857.920000 2867.980000 1859.020000 2868.460000 ;
+ RECT 1853.790000 2873.420000 1854.790000 2873.900000 ;
+ RECT 1853.790000 2867.980000 1854.790000 2868.460000 ;
+ RECT 1857.920000 2862.540000 1859.020000 2863.020000 ;
+ RECT 1853.790000 2862.540000 1854.790000 2863.020000 ;
+ RECT 1857.920000 2857.100000 1859.020000 2857.580000 ;
+ RECT 1853.790000 2857.100000 1854.790000 2857.580000 ;
+ RECT 1857.920000 2851.660000 1859.020000 2852.140000 ;
+ RECT 1853.790000 2851.660000 1854.790000 2852.140000 ;
+ RECT 2037.920000 2846.220000 2039.020000 2846.700000 ;
+ RECT 2037.920000 2840.780000 2039.020000 2841.260000 ;
+ RECT 2047.230000 2846.220000 2048.230000 2846.700000 ;
+ RECT 2047.230000 2840.780000 2048.230000 2841.260000 ;
+ RECT 2047.230000 2824.460000 2048.230000 2824.940000 ;
+ RECT 2047.230000 2829.900000 2048.230000 2830.380000 ;
+ RECT 2047.230000 2835.340000 2048.230000 2835.820000 ;
+ RECT 2037.920000 2835.340000 2039.020000 2835.820000 ;
+ RECT 2037.920000 2829.900000 2039.020000 2830.380000 ;
+ RECT 2037.920000 2824.460000 2039.020000 2824.940000 ;
+ RECT 2037.920000 2813.580000 2039.020000 2814.060000 ;
+ RECT 2037.920000 2819.020000 2039.020000 2819.500000 ;
+ RECT 2047.230000 2819.020000 2048.230000 2819.500000 ;
+ RECT 2047.230000 2813.580000 2048.230000 2814.060000 ;
+ RECT 2047.230000 2802.700000 2048.230000 2803.180000 ;
+ RECT 2047.230000 2808.140000 2048.230000 2808.620000 ;
+ RECT 2037.920000 2802.700000 2039.020000 2803.180000 ;
+ RECT 2037.920000 2808.140000 2039.020000 2808.620000 ;
+ RECT 1992.920000 2846.220000 1994.020000 2846.700000 ;
+ RECT 1992.920000 2840.780000 1994.020000 2841.260000 ;
+ RECT 1992.920000 2835.340000 1994.020000 2835.820000 ;
+ RECT 1992.920000 2829.900000 1994.020000 2830.380000 ;
+ RECT 1992.920000 2824.460000 1994.020000 2824.940000 ;
+ RECT 1992.920000 2802.700000 1994.020000 2803.180000 ;
+ RECT 1992.920000 2808.140000 1994.020000 2808.620000 ;
+ RECT 1992.920000 2813.580000 1994.020000 2814.060000 ;
+ RECT 1992.920000 2819.020000 1994.020000 2819.500000 ;
+ RECT 2037.920000 2797.260000 2039.020000 2797.740000 ;
+ RECT 2037.920000 2791.820000 2039.020000 2792.300000 ;
+ RECT 2047.230000 2797.260000 2048.230000 2797.740000 ;
+ RECT 2047.230000 2791.820000 2048.230000 2792.300000 ;
+ RECT 2037.920000 2780.940000 2039.020000 2781.420000 ;
+ RECT 2037.920000 2775.500000 2039.020000 2775.980000 ;
+ RECT 2047.230000 2780.940000 2048.230000 2781.420000 ;
+ RECT 2047.230000 2775.500000 2048.230000 2775.980000 ;
+ RECT 2037.920000 2786.380000 2039.020000 2786.860000 ;
+ RECT 2047.230000 2786.380000 2048.230000 2786.860000 ;
+ RECT 2047.230000 2764.620000 2048.230000 2765.100000 ;
+ RECT 2047.230000 2770.060000 2048.230000 2770.540000 ;
+ RECT 2037.920000 2770.060000 2039.020000 2770.540000 ;
+ RECT 2037.920000 2764.620000 2039.020000 2765.100000 ;
+ RECT 2037.920000 2759.180000 2039.020000 2759.660000 ;
+ RECT 2037.920000 2753.740000 2039.020000 2754.220000 ;
+ RECT 2047.230000 2759.180000 2048.230000 2759.660000 ;
+ RECT 2047.230000 2753.740000 2048.230000 2754.220000 ;
+ RECT 1992.920000 2797.260000 1994.020000 2797.740000 ;
+ RECT 1992.920000 2791.820000 1994.020000 2792.300000 ;
+ RECT 1992.920000 2786.380000 1994.020000 2786.860000 ;
+ RECT 1992.920000 2780.940000 1994.020000 2781.420000 ;
+ RECT 1992.920000 2775.500000 1994.020000 2775.980000 ;
+ RECT 1992.920000 2770.060000 1994.020000 2770.540000 ;
+ RECT 1992.920000 2764.620000 1994.020000 2765.100000 ;
+ RECT 1992.920000 2759.180000 1994.020000 2759.660000 ;
+ RECT 1992.920000 2753.740000 1994.020000 2754.220000 ;
+ RECT 1947.920000 2846.220000 1949.020000 2846.700000 ;
+ RECT 1947.920000 2840.780000 1949.020000 2841.260000 ;
+ RECT 1947.920000 2835.340000 1949.020000 2835.820000 ;
+ RECT 1947.920000 2829.900000 1949.020000 2830.380000 ;
+ RECT 1947.920000 2824.460000 1949.020000 2824.940000 ;
+ RECT 1902.920000 2846.220000 1904.020000 2846.700000 ;
+ RECT 1902.920000 2840.780000 1904.020000 2841.260000 ;
+ RECT 1902.920000 2835.340000 1904.020000 2835.820000 ;
+ RECT 1902.920000 2829.900000 1904.020000 2830.380000 ;
+ RECT 1902.920000 2824.460000 1904.020000 2824.940000 ;
+ RECT 1947.920000 2819.020000 1949.020000 2819.500000 ;
+ RECT 1947.920000 2813.580000 1949.020000 2814.060000 ;
+ RECT 1947.920000 2808.140000 1949.020000 2808.620000 ;
+ RECT 1947.920000 2802.700000 1949.020000 2803.180000 ;
+ RECT 1902.920000 2813.580000 1904.020000 2814.060000 ;
+ RECT 1902.920000 2808.140000 1904.020000 2808.620000 ;
+ RECT 1902.920000 2802.700000 1904.020000 2803.180000 ;
+ RECT 1902.920000 2819.020000 1904.020000 2819.500000 ;
+ RECT 1857.920000 2846.220000 1859.020000 2846.700000 ;
+ RECT 1853.790000 2846.220000 1854.790000 2846.700000 ;
+ RECT 1857.920000 2840.780000 1859.020000 2841.260000 ;
+ RECT 1853.790000 2840.780000 1854.790000 2841.260000 ;
+ RECT 1857.920000 2835.340000 1859.020000 2835.820000 ;
+ RECT 1853.790000 2835.340000 1854.790000 2835.820000 ;
+ RECT 1857.920000 2824.460000 1859.020000 2824.940000 ;
+ RECT 1853.790000 2824.460000 1854.790000 2824.940000 ;
+ RECT 1853.790000 2829.900000 1854.790000 2830.380000 ;
+ RECT 1857.920000 2829.900000 1859.020000 2830.380000 ;
+ RECT 1857.920000 2819.020000 1859.020000 2819.500000 ;
+ RECT 1853.790000 2819.020000 1854.790000 2819.500000 ;
+ RECT 1857.920000 2813.580000 1859.020000 2814.060000 ;
+ RECT 1853.790000 2813.580000 1854.790000 2814.060000 ;
+ RECT 1857.920000 2808.140000 1859.020000 2808.620000 ;
+ RECT 1853.790000 2808.140000 1854.790000 2808.620000 ;
+ RECT 1857.920000 2802.700000 1859.020000 2803.180000 ;
+ RECT 1853.790000 2802.700000 1854.790000 2803.180000 ;
+ RECT 1947.920000 2797.260000 1949.020000 2797.740000 ;
+ RECT 1947.920000 2791.820000 1949.020000 2792.300000 ;
+ RECT 1947.920000 2786.380000 1949.020000 2786.860000 ;
+ RECT 1947.920000 2780.940000 1949.020000 2781.420000 ;
+ RECT 1947.920000 2775.500000 1949.020000 2775.980000 ;
+ RECT 1902.920000 2797.260000 1904.020000 2797.740000 ;
+ RECT 1902.920000 2791.820000 1904.020000 2792.300000 ;
+ RECT 1902.920000 2786.380000 1904.020000 2786.860000 ;
+ RECT 1902.920000 2780.940000 1904.020000 2781.420000 ;
+ RECT 1902.920000 2775.500000 1904.020000 2775.980000 ;
+ RECT 1947.920000 2753.740000 1949.020000 2754.220000 ;
+ RECT 1947.920000 2759.180000 1949.020000 2759.660000 ;
+ RECT 1947.920000 2764.620000 1949.020000 2765.100000 ;
+ RECT 1947.920000 2770.060000 1949.020000 2770.540000 ;
+ RECT 1902.920000 2753.740000 1904.020000 2754.220000 ;
+ RECT 1902.920000 2759.180000 1904.020000 2759.660000 ;
+ RECT 1902.920000 2764.620000 1904.020000 2765.100000 ;
+ RECT 1902.920000 2770.060000 1904.020000 2770.540000 ;
+ RECT 1857.920000 2797.260000 1859.020000 2797.740000 ;
+ RECT 1853.790000 2797.260000 1854.790000 2797.740000 ;
+ RECT 1857.920000 2791.820000 1859.020000 2792.300000 ;
+ RECT 1853.790000 2791.820000 1854.790000 2792.300000 ;
+ RECT 1857.920000 2780.940000 1859.020000 2781.420000 ;
+ RECT 1853.790000 2780.940000 1854.790000 2781.420000 ;
+ RECT 1857.920000 2775.500000 1859.020000 2775.980000 ;
+ RECT 1853.790000 2775.500000 1854.790000 2775.980000 ;
+ RECT 1857.920000 2786.380000 1859.020000 2786.860000 ;
+ RECT 1853.790000 2786.380000 1854.790000 2786.860000 ;
+ RECT 1857.920000 2770.060000 1859.020000 2770.540000 ;
+ RECT 1853.790000 2770.060000 1854.790000 2770.540000 ;
+ RECT 1857.920000 2764.620000 1859.020000 2765.100000 ;
+ RECT 1853.790000 2764.620000 1854.790000 2765.100000 ;
+ RECT 1857.920000 2759.180000 1859.020000 2759.660000 ;
+ RECT 1857.920000 2753.740000 1859.020000 2754.220000 ;
+ RECT 1853.790000 2759.180000 1854.790000 2759.660000 ;
+ RECT 1853.790000 2753.740000 1854.790000 2754.220000 ;
+ RECT 1850.960000 2944.100000 2051.060000 2945.100000 ;
+ RECT 1850.960000 2751.730000 2051.060000 2752.730000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 2748.880000 1854.790000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 2948.140000 1854.790000 2949.140000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 2748.880000 2048.230000 2749.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 2948.140000 2048.230000 2949.140000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2751.730000 1851.960000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2751.730000 2051.060000 2752.730000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2944.100000 1851.960000 2945.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2944.100000 2051.060000 2945.100000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 2551.470000 2039.020000 2744.840000 ;
+ RECT 1992.920000 2551.470000 1994.020000 2744.840000 ;
+ RECT 2047.230000 2548.620000 2048.230000 2748.880000 ;
+ RECT 1947.920000 2551.470000 1949.020000 2744.840000 ;
+ RECT 1902.920000 2551.470000 1904.020000 2744.840000 ;
+ RECT 1857.920000 2551.470000 1859.020000 2744.840000 ;
+ RECT 1853.790000 2548.620000 1854.790000 2748.880000 ;
+ LAYER met3 ;
+ RECT 2037.920000 2738.440000 2039.020000 2738.920000 ;
+ RECT 2047.230000 2738.440000 2048.230000 2738.920000 ;
+ RECT 2047.230000 2727.560000 2048.230000 2728.040000 ;
+ RECT 2047.230000 2733.000000 2048.230000 2733.480000 ;
+ RECT 2037.920000 2733.000000 2039.020000 2733.480000 ;
+ RECT 2037.920000 2727.560000 2039.020000 2728.040000 ;
+ RECT 2037.920000 2722.120000 2039.020000 2722.600000 ;
+ RECT 2037.920000 2716.680000 2039.020000 2717.160000 ;
+ RECT 2047.230000 2722.120000 2048.230000 2722.600000 ;
+ RECT 2047.230000 2716.680000 2048.230000 2717.160000 ;
+ RECT 2037.920000 2700.360000 2039.020000 2700.840000 ;
+ RECT 2037.920000 2705.800000 2039.020000 2706.280000 ;
+ RECT 2047.230000 2705.800000 2048.230000 2706.280000 ;
+ RECT 2047.230000 2700.360000 2048.230000 2700.840000 ;
+ RECT 2037.920000 2711.240000 2039.020000 2711.720000 ;
+ RECT 2047.230000 2711.240000 2048.230000 2711.720000 ;
+ RECT 1992.920000 2738.440000 1994.020000 2738.920000 ;
+ RECT 1992.920000 2733.000000 1994.020000 2733.480000 ;
+ RECT 1992.920000 2727.560000 1994.020000 2728.040000 ;
+ RECT 1992.920000 2722.120000 1994.020000 2722.600000 ;
+ RECT 1992.920000 2700.360000 1994.020000 2700.840000 ;
+ RECT 1992.920000 2705.800000 1994.020000 2706.280000 ;
+ RECT 1992.920000 2711.240000 1994.020000 2711.720000 ;
+ RECT 1992.920000 2716.680000 1994.020000 2717.160000 ;
+ RECT 2047.230000 2689.480000 2048.230000 2689.960000 ;
+ RECT 2047.230000 2694.920000 2048.230000 2695.400000 ;
+ RECT 2037.920000 2694.920000 2039.020000 2695.400000 ;
+ RECT 2037.920000 2689.480000 2039.020000 2689.960000 ;
+ RECT 2037.920000 2684.040000 2039.020000 2684.520000 ;
+ RECT 2037.920000 2678.600000 2039.020000 2679.080000 ;
+ RECT 2047.230000 2684.040000 2048.230000 2684.520000 ;
+ RECT 2047.230000 2678.600000 2048.230000 2679.080000 ;
+ RECT 2047.230000 2662.280000 2048.230000 2662.760000 ;
+ RECT 2047.230000 2667.720000 2048.230000 2668.200000 ;
+ RECT 2047.230000 2673.160000 2048.230000 2673.640000 ;
+ RECT 2037.920000 2667.720000 2039.020000 2668.200000 ;
+ RECT 2037.920000 2662.280000 2039.020000 2662.760000 ;
+ RECT 2037.920000 2673.160000 2039.020000 2673.640000 ;
+ RECT 2037.920000 2656.840000 2039.020000 2657.320000 ;
+ RECT 2037.920000 2651.400000 2039.020000 2651.880000 ;
+ RECT 2047.230000 2656.840000 2048.230000 2657.320000 ;
+ RECT 2047.230000 2651.400000 2048.230000 2651.880000 ;
+ RECT 1992.920000 2694.920000 1994.020000 2695.400000 ;
+ RECT 1992.920000 2689.480000 1994.020000 2689.960000 ;
+ RECT 1992.920000 2684.040000 1994.020000 2684.520000 ;
+ RECT 1992.920000 2678.600000 1994.020000 2679.080000 ;
+ RECT 1992.920000 2667.720000 1994.020000 2668.200000 ;
+ RECT 1992.920000 2662.280000 1994.020000 2662.760000 ;
+ RECT 1992.920000 2656.840000 1994.020000 2657.320000 ;
+ RECT 1992.920000 2651.400000 1994.020000 2651.880000 ;
+ RECT 1992.920000 2673.160000 1994.020000 2673.640000 ;
+ RECT 1947.920000 2738.440000 1949.020000 2738.920000 ;
+ RECT 1947.920000 2733.000000 1949.020000 2733.480000 ;
+ RECT 1947.920000 2727.560000 1949.020000 2728.040000 ;
+ RECT 1902.920000 2738.440000 1904.020000 2738.920000 ;
+ RECT 1902.920000 2733.000000 1904.020000 2733.480000 ;
+ RECT 1902.920000 2727.560000 1904.020000 2728.040000 ;
+ RECT 1947.920000 2711.240000 1949.020000 2711.720000 ;
+ RECT 1947.920000 2705.800000 1949.020000 2706.280000 ;
+ RECT 1947.920000 2700.360000 1949.020000 2700.840000 ;
+ RECT 1947.920000 2716.680000 1949.020000 2717.160000 ;
+ RECT 1947.920000 2722.120000 1949.020000 2722.600000 ;
+ RECT 1902.920000 2722.120000 1904.020000 2722.600000 ;
+ RECT 1902.920000 2711.240000 1904.020000 2711.720000 ;
+ RECT 1902.920000 2705.800000 1904.020000 2706.280000 ;
+ RECT 1902.920000 2700.360000 1904.020000 2700.840000 ;
+ RECT 1902.920000 2716.680000 1904.020000 2717.160000 ;
+ RECT 1857.920000 2738.440000 1859.020000 2738.920000 ;
+ RECT 1853.790000 2738.440000 1854.790000 2738.920000 ;
+ RECT 1853.790000 2733.000000 1854.790000 2733.480000 ;
+ RECT 1857.920000 2733.000000 1859.020000 2733.480000 ;
+ RECT 1857.920000 2727.560000 1859.020000 2728.040000 ;
+ RECT 1853.790000 2727.560000 1854.790000 2728.040000 ;
+ RECT 1857.920000 2722.120000 1859.020000 2722.600000 ;
+ RECT 1853.790000 2722.120000 1854.790000 2722.600000 ;
+ RECT 1857.920000 2716.680000 1859.020000 2717.160000 ;
+ RECT 1853.790000 2716.680000 1854.790000 2717.160000 ;
+ RECT 1857.920000 2705.800000 1859.020000 2706.280000 ;
+ RECT 1853.790000 2705.800000 1854.790000 2706.280000 ;
+ RECT 1857.920000 2700.360000 1859.020000 2700.840000 ;
+ RECT 1853.790000 2700.360000 1854.790000 2700.840000 ;
+ RECT 1857.920000 2711.240000 1859.020000 2711.720000 ;
+ RECT 1853.790000 2711.240000 1854.790000 2711.720000 ;
+ RECT 1947.920000 2694.920000 1949.020000 2695.400000 ;
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+ RECT 1947.920000 2684.040000 1949.020000 2684.520000 ;
+ RECT 1947.920000 2678.600000 1949.020000 2679.080000 ;
+ RECT 1902.920000 2694.920000 1904.020000 2695.400000 ;
+ RECT 1902.920000 2689.480000 1904.020000 2689.960000 ;
+ RECT 1902.920000 2684.040000 1904.020000 2684.520000 ;
+ RECT 1902.920000 2678.600000 1904.020000 2679.080000 ;
+ RECT 1947.920000 2667.720000 1949.020000 2668.200000 ;
+ RECT 1947.920000 2651.400000 1949.020000 2651.880000 ;
+ RECT 1947.920000 2656.840000 1949.020000 2657.320000 ;
+ RECT 1947.920000 2662.280000 1949.020000 2662.760000 ;
+ RECT 1947.920000 2673.160000 1949.020000 2673.640000 ;
+ RECT 1902.920000 2651.400000 1904.020000 2651.880000 ;
+ RECT 1902.920000 2656.840000 1904.020000 2657.320000 ;
+ RECT 1902.920000 2662.280000 1904.020000 2662.760000 ;
+ RECT 1902.920000 2667.720000 1904.020000 2668.200000 ;
+ RECT 1902.920000 2673.160000 1904.020000 2673.640000 ;
+ RECT 1857.920000 2694.920000 1859.020000 2695.400000 ;
+ RECT 1853.790000 2694.920000 1854.790000 2695.400000 ;
+ RECT 1857.920000 2689.480000 1859.020000 2689.960000 ;
+ RECT 1853.790000 2689.480000 1854.790000 2689.960000 ;
+ RECT 1857.920000 2684.040000 1859.020000 2684.520000 ;
+ RECT 1853.790000 2684.040000 1854.790000 2684.520000 ;
+ RECT 1857.920000 2678.600000 1859.020000 2679.080000 ;
+ RECT 1853.790000 2678.600000 1854.790000 2679.080000 ;
+ RECT 1857.920000 2673.160000 1859.020000 2673.640000 ;
+ RECT 1857.920000 2667.720000 1859.020000 2668.200000 ;
+ RECT 1853.790000 2673.160000 1854.790000 2673.640000 ;
+ RECT 1853.790000 2667.720000 1854.790000 2668.200000 ;
+ RECT 1857.920000 2662.280000 1859.020000 2662.760000 ;
+ RECT 1853.790000 2662.280000 1854.790000 2662.760000 ;
+ RECT 1857.920000 2656.840000 1859.020000 2657.320000 ;
+ RECT 1853.790000 2656.840000 1854.790000 2657.320000 ;
+ RECT 1857.920000 2651.400000 1859.020000 2651.880000 ;
+ RECT 1853.790000 2651.400000 1854.790000 2651.880000 ;
+ RECT 2037.920000 2645.960000 2039.020000 2646.440000 ;
+ RECT 2037.920000 2640.520000 2039.020000 2641.000000 ;
+ RECT 2047.230000 2645.960000 2048.230000 2646.440000 ;
+ RECT 2047.230000 2640.520000 2048.230000 2641.000000 ;
+ RECT 2047.230000 2624.200000 2048.230000 2624.680000 ;
+ RECT 2047.230000 2629.640000 2048.230000 2630.120000 ;
+ RECT 2047.230000 2635.080000 2048.230000 2635.560000 ;
+ RECT 2037.920000 2635.080000 2039.020000 2635.560000 ;
+ RECT 2037.920000 2629.640000 2039.020000 2630.120000 ;
+ RECT 2037.920000 2624.200000 2039.020000 2624.680000 ;
+ RECT 2037.920000 2613.320000 2039.020000 2613.800000 ;
+ RECT 2037.920000 2618.760000 2039.020000 2619.240000 ;
+ RECT 2047.230000 2618.760000 2048.230000 2619.240000 ;
+ RECT 2047.230000 2613.320000 2048.230000 2613.800000 ;
+ RECT 2047.230000 2602.440000 2048.230000 2602.920000 ;
+ RECT 2047.230000 2607.880000 2048.230000 2608.360000 ;
+ RECT 2037.920000 2602.440000 2039.020000 2602.920000 ;
+ RECT 2037.920000 2607.880000 2039.020000 2608.360000 ;
+ RECT 1992.920000 2645.960000 1994.020000 2646.440000 ;
+ RECT 1992.920000 2640.520000 1994.020000 2641.000000 ;
+ RECT 1992.920000 2635.080000 1994.020000 2635.560000 ;
+ RECT 1992.920000 2629.640000 1994.020000 2630.120000 ;
+ RECT 1992.920000 2624.200000 1994.020000 2624.680000 ;
+ RECT 1992.920000 2602.440000 1994.020000 2602.920000 ;
+ RECT 1992.920000 2607.880000 1994.020000 2608.360000 ;
+ RECT 1992.920000 2613.320000 1994.020000 2613.800000 ;
+ RECT 1992.920000 2618.760000 1994.020000 2619.240000 ;
+ RECT 2037.920000 2597.000000 2039.020000 2597.480000 ;
+ RECT 2037.920000 2591.560000 2039.020000 2592.040000 ;
+ RECT 2047.230000 2597.000000 2048.230000 2597.480000 ;
+ RECT 2047.230000 2591.560000 2048.230000 2592.040000 ;
+ RECT 2037.920000 2580.680000 2039.020000 2581.160000 ;
+ RECT 2037.920000 2575.240000 2039.020000 2575.720000 ;
+ RECT 2047.230000 2580.680000 2048.230000 2581.160000 ;
+ RECT 2047.230000 2575.240000 2048.230000 2575.720000 ;
+ RECT 2037.920000 2586.120000 2039.020000 2586.600000 ;
+ RECT 2047.230000 2586.120000 2048.230000 2586.600000 ;
+ RECT 2047.230000 2564.360000 2048.230000 2564.840000 ;
+ RECT 2047.230000 2569.800000 2048.230000 2570.280000 ;
+ RECT 2037.920000 2569.800000 2039.020000 2570.280000 ;
+ RECT 2037.920000 2564.360000 2039.020000 2564.840000 ;
+ RECT 2037.920000 2558.920000 2039.020000 2559.400000 ;
+ RECT 2037.920000 2553.480000 2039.020000 2553.960000 ;
+ RECT 2047.230000 2558.920000 2048.230000 2559.400000 ;
+ RECT 2047.230000 2553.480000 2048.230000 2553.960000 ;
+ RECT 1992.920000 2597.000000 1994.020000 2597.480000 ;
+ RECT 1992.920000 2591.560000 1994.020000 2592.040000 ;
+ RECT 1992.920000 2586.120000 1994.020000 2586.600000 ;
+ RECT 1992.920000 2580.680000 1994.020000 2581.160000 ;
+ RECT 1992.920000 2575.240000 1994.020000 2575.720000 ;
+ RECT 1992.920000 2569.800000 1994.020000 2570.280000 ;
+ RECT 1992.920000 2564.360000 1994.020000 2564.840000 ;
+ RECT 1992.920000 2558.920000 1994.020000 2559.400000 ;
+ RECT 1992.920000 2553.480000 1994.020000 2553.960000 ;
+ RECT 1947.920000 2645.960000 1949.020000 2646.440000 ;
+ RECT 1947.920000 2640.520000 1949.020000 2641.000000 ;
+ RECT 1947.920000 2635.080000 1949.020000 2635.560000 ;
+ RECT 1947.920000 2629.640000 1949.020000 2630.120000 ;
+ RECT 1947.920000 2624.200000 1949.020000 2624.680000 ;
+ RECT 1902.920000 2645.960000 1904.020000 2646.440000 ;
+ RECT 1902.920000 2640.520000 1904.020000 2641.000000 ;
+ RECT 1902.920000 2635.080000 1904.020000 2635.560000 ;
+ RECT 1902.920000 2629.640000 1904.020000 2630.120000 ;
+ RECT 1902.920000 2624.200000 1904.020000 2624.680000 ;
+ RECT 1947.920000 2618.760000 1949.020000 2619.240000 ;
+ RECT 1947.920000 2613.320000 1949.020000 2613.800000 ;
+ RECT 1947.920000 2607.880000 1949.020000 2608.360000 ;
+ RECT 1947.920000 2602.440000 1949.020000 2602.920000 ;
+ RECT 1902.920000 2613.320000 1904.020000 2613.800000 ;
+ RECT 1902.920000 2607.880000 1904.020000 2608.360000 ;
+ RECT 1902.920000 2602.440000 1904.020000 2602.920000 ;
+ RECT 1902.920000 2618.760000 1904.020000 2619.240000 ;
+ RECT 1857.920000 2645.960000 1859.020000 2646.440000 ;
+ RECT 1853.790000 2645.960000 1854.790000 2646.440000 ;
+ RECT 1857.920000 2640.520000 1859.020000 2641.000000 ;
+ RECT 1853.790000 2640.520000 1854.790000 2641.000000 ;
+ RECT 1857.920000 2635.080000 1859.020000 2635.560000 ;
+ RECT 1853.790000 2635.080000 1854.790000 2635.560000 ;
+ RECT 1857.920000 2624.200000 1859.020000 2624.680000 ;
+ RECT 1853.790000 2624.200000 1854.790000 2624.680000 ;
+ RECT 1853.790000 2629.640000 1854.790000 2630.120000 ;
+ RECT 1857.920000 2629.640000 1859.020000 2630.120000 ;
+ RECT 1857.920000 2618.760000 1859.020000 2619.240000 ;
+ RECT 1853.790000 2618.760000 1854.790000 2619.240000 ;
+ RECT 1857.920000 2613.320000 1859.020000 2613.800000 ;
+ RECT 1853.790000 2613.320000 1854.790000 2613.800000 ;
+ RECT 1857.920000 2607.880000 1859.020000 2608.360000 ;
+ RECT 1853.790000 2607.880000 1854.790000 2608.360000 ;
+ RECT 1857.920000 2602.440000 1859.020000 2602.920000 ;
+ RECT 1853.790000 2602.440000 1854.790000 2602.920000 ;
+ RECT 1947.920000 2597.000000 1949.020000 2597.480000 ;
+ RECT 1947.920000 2591.560000 1949.020000 2592.040000 ;
+ RECT 1947.920000 2586.120000 1949.020000 2586.600000 ;
+ RECT 1947.920000 2580.680000 1949.020000 2581.160000 ;
+ RECT 1947.920000 2575.240000 1949.020000 2575.720000 ;
+ RECT 1902.920000 2597.000000 1904.020000 2597.480000 ;
+ RECT 1902.920000 2591.560000 1904.020000 2592.040000 ;
+ RECT 1902.920000 2586.120000 1904.020000 2586.600000 ;
+ RECT 1902.920000 2580.680000 1904.020000 2581.160000 ;
+ RECT 1902.920000 2575.240000 1904.020000 2575.720000 ;
+ RECT 1947.920000 2553.480000 1949.020000 2553.960000 ;
+ RECT 1947.920000 2558.920000 1949.020000 2559.400000 ;
+ RECT 1947.920000 2564.360000 1949.020000 2564.840000 ;
+ RECT 1947.920000 2569.800000 1949.020000 2570.280000 ;
+ RECT 1902.920000 2553.480000 1904.020000 2553.960000 ;
+ RECT 1902.920000 2558.920000 1904.020000 2559.400000 ;
+ RECT 1902.920000 2564.360000 1904.020000 2564.840000 ;
+ RECT 1902.920000 2569.800000 1904.020000 2570.280000 ;
+ RECT 1857.920000 2597.000000 1859.020000 2597.480000 ;
+ RECT 1853.790000 2597.000000 1854.790000 2597.480000 ;
+ RECT 1857.920000 2591.560000 1859.020000 2592.040000 ;
+ RECT 1853.790000 2591.560000 1854.790000 2592.040000 ;
+ RECT 1857.920000 2580.680000 1859.020000 2581.160000 ;
+ RECT 1853.790000 2580.680000 1854.790000 2581.160000 ;
+ RECT 1857.920000 2575.240000 1859.020000 2575.720000 ;
+ RECT 1853.790000 2575.240000 1854.790000 2575.720000 ;
+ RECT 1857.920000 2586.120000 1859.020000 2586.600000 ;
+ RECT 1853.790000 2586.120000 1854.790000 2586.600000 ;
+ RECT 1857.920000 2569.800000 1859.020000 2570.280000 ;
+ RECT 1853.790000 2569.800000 1854.790000 2570.280000 ;
+ RECT 1857.920000 2564.360000 1859.020000 2564.840000 ;
+ RECT 1853.790000 2564.360000 1854.790000 2564.840000 ;
+ RECT 1857.920000 2558.920000 1859.020000 2559.400000 ;
+ RECT 1857.920000 2553.480000 1859.020000 2553.960000 ;
+ RECT 1853.790000 2558.920000 1854.790000 2559.400000 ;
+ RECT 1853.790000 2553.480000 1854.790000 2553.960000 ;
+ RECT 1850.960000 2743.840000 2051.060000 2744.840000 ;
+ RECT 1850.960000 2551.470000 2051.060000 2552.470000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 2548.620000 1854.790000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 2747.880000 1854.790000 2748.880000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 2548.620000 2048.230000 2549.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 2747.880000 2048.230000 2748.880000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2551.470000 1851.960000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2551.470000 2051.060000 2552.470000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2743.840000 1851.960000 2744.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2743.840000 2051.060000 2744.840000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 2351.210000 2039.020000 2544.580000 ;
+ RECT 1992.920000 2351.210000 1994.020000 2544.580000 ;
+ RECT 2047.230000 2348.360000 2048.230000 2548.620000 ;
+ RECT 1947.920000 2351.210000 1949.020000 2544.580000 ;
+ RECT 1902.920000 2351.210000 1904.020000 2544.580000 ;
+ RECT 1857.920000 2351.210000 1859.020000 2544.580000 ;
+ RECT 1853.790000 2348.360000 1854.790000 2548.620000 ;
+ LAYER met3 ;
+ RECT 2037.920000 2538.180000 2039.020000 2538.660000 ;
+ RECT 2047.230000 2538.180000 2048.230000 2538.660000 ;
+ RECT 2047.230000 2527.300000 2048.230000 2527.780000 ;
+ RECT 2047.230000 2532.740000 2048.230000 2533.220000 ;
+ RECT 2037.920000 2532.740000 2039.020000 2533.220000 ;
+ RECT 2037.920000 2527.300000 2039.020000 2527.780000 ;
+ RECT 2037.920000 2521.860000 2039.020000 2522.340000 ;
+ RECT 2037.920000 2516.420000 2039.020000 2516.900000 ;
+ RECT 2047.230000 2521.860000 2048.230000 2522.340000 ;
+ RECT 2047.230000 2516.420000 2048.230000 2516.900000 ;
+ RECT 2037.920000 2500.100000 2039.020000 2500.580000 ;
+ RECT 2037.920000 2505.540000 2039.020000 2506.020000 ;
+ RECT 2047.230000 2505.540000 2048.230000 2506.020000 ;
+ RECT 2047.230000 2500.100000 2048.230000 2500.580000 ;
+ RECT 2037.920000 2510.980000 2039.020000 2511.460000 ;
+ RECT 2047.230000 2510.980000 2048.230000 2511.460000 ;
+ RECT 1992.920000 2538.180000 1994.020000 2538.660000 ;
+ RECT 1992.920000 2532.740000 1994.020000 2533.220000 ;
+ RECT 1992.920000 2527.300000 1994.020000 2527.780000 ;
+ RECT 1992.920000 2521.860000 1994.020000 2522.340000 ;
+ RECT 1992.920000 2500.100000 1994.020000 2500.580000 ;
+ RECT 1992.920000 2505.540000 1994.020000 2506.020000 ;
+ RECT 1992.920000 2510.980000 1994.020000 2511.460000 ;
+ RECT 1992.920000 2516.420000 1994.020000 2516.900000 ;
+ RECT 2047.230000 2489.220000 2048.230000 2489.700000 ;
+ RECT 2047.230000 2494.660000 2048.230000 2495.140000 ;
+ RECT 2037.920000 2494.660000 2039.020000 2495.140000 ;
+ RECT 2037.920000 2489.220000 2039.020000 2489.700000 ;
+ RECT 2037.920000 2483.780000 2039.020000 2484.260000 ;
+ RECT 2037.920000 2478.340000 2039.020000 2478.820000 ;
+ RECT 2047.230000 2483.780000 2048.230000 2484.260000 ;
+ RECT 2047.230000 2478.340000 2048.230000 2478.820000 ;
+ RECT 2047.230000 2462.020000 2048.230000 2462.500000 ;
+ RECT 2047.230000 2467.460000 2048.230000 2467.940000 ;
+ RECT 2047.230000 2472.900000 2048.230000 2473.380000 ;
+ RECT 2037.920000 2467.460000 2039.020000 2467.940000 ;
+ RECT 2037.920000 2462.020000 2039.020000 2462.500000 ;
+ RECT 2037.920000 2472.900000 2039.020000 2473.380000 ;
+ RECT 2037.920000 2456.580000 2039.020000 2457.060000 ;
+ RECT 2037.920000 2451.140000 2039.020000 2451.620000 ;
+ RECT 2047.230000 2456.580000 2048.230000 2457.060000 ;
+ RECT 2047.230000 2451.140000 2048.230000 2451.620000 ;
+ RECT 1992.920000 2494.660000 1994.020000 2495.140000 ;
+ RECT 1992.920000 2489.220000 1994.020000 2489.700000 ;
+ RECT 1992.920000 2483.780000 1994.020000 2484.260000 ;
+ RECT 1992.920000 2478.340000 1994.020000 2478.820000 ;
+ RECT 1992.920000 2467.460000 1994.020000 2467.940000 ;
+ RECT 1992.920000 2462.020000 1994.020000 2462.500000 ;
+ RECT 1992.920000 2456.580000 1994.020000 2457.060000 ;
+ RECT 1992.920000 2451.140000 1994.020000 2451.620000 ;
+ RECT 1992.920000 2472.900000 1994.020000 2473.380000 ;
+ RECT 1947.920000 2538.180000 1949.020000 2538.660000 ;
+ RECT 1947.920000 2532.740000 1949.020000 2533.220000 ;
+ RECT 1947.920000 2527.300000 1949.020000 2527.780000 ;
+ RECT 1902.920000 2538.180000 1904.020000 2538.660000 ;
+ RECT 1902.920000 2532.740000 1904.020000 2533.220000 ;
+ RECT 1902.920000 2527.300000 1904.020000 2527.780000 ;
+ RECT 1947.920000 2510.980000 1949.020000 2511.460000 ;
+ RECT 1947.920000 2505.540000 1949.020000 2506.020000 ;
+ RECT 1947.920000 2500.100000 1949.020000 2500.580000 ;
+ RECT 1947.920000 2516.420000 1949.020000 2516.900000 ;
+ RECT 1947.920000 2521.860000 1949.020000 2522.340000 ;
+ RECT 1902.920000 2521.860000 1904.020000 2522.340000 ;
+ RECT 1902.920000 2510.980000 1904.020000 2511.460000 ;
+ RECT 1902.920000 2505.540000 1904.020000 2506.020000 ;
+ RECT 1902.920000 2500.100000 1904.020000 2500.580000 ;
+ RECT 1902.920000 2516.420000 1904.020000 2516.900000 ;
+ RECT 1857.920000 2538.180000 1859.020000 2538.660000 ;
+ RECT 1853.790000 2538.180000 1854.790000 2538.660000 ;
+ RECT 1853.790000 2532.740000 1854.790000 2533.220000 ;
+ RECT 1857.920000 2532.740000 1859.020000 2533.220000 ;
+ RECT 1857.920000 2527.300000 1859.020000 2527.780000 ;
+ RECT 1853.790000 2527.300000 1854.790000 2527.780000 ;
+ RECT 1857.920000 2521.860000 1859.020000 2522.340000 ;
+ RECT 1853.790000 2521.860000 1854.790000 2522.340000 ;
+ RECT 1857.920000 2516.420000 1859.020000 2516.900000 ;
+ RECT 1853.790000 2516.420000 1854.790000 2516.900000 ;
+ RECT 1857.920000 2505.540000 1859.020000 2506.020000 ;
+ RECT 1853.790000 2505.540000 1854.790000 2506.020000 ;
+ RECT 1857.920000 2500.100000 1859.020000 2500.580000 ;
+ RECT 1853.790000 2500.100000 1854.790000 2500.580000 ;
+ RECT 1857.920000 2510.980000 1859.020000 2511.460000 ;
+ RECT 1853.790000 2510.980000 1854.790000 2511.460000 ;
+ RECT 1947.920000 2494.660000 1949.020000 2495.140000 ;
+ RECT 1947.920000 2489.220000 1949.020000 2489.700000 ;
+ RECT 1947.920000 2483.780000 1949.020000 2484.260000 ;
+ RECT 1947.920000 2478.340000 1949.020000 2478.820000 ;
+ RECT 1902.920000 2494.660000 1904.020000 2495.140000 ;
+ RECT 1902.920000 2489.220000 1904.020000 2489.700000 ;
+ RECT 1902.920000 2483.780000 1904.020000 2484.260000 ;
+ RECT 1902.920000 2478.340000 1904.020000 2478.820000 ;
+ RECT 1947.920000 2467.460000 1949.020000 2467.940000 ;
+ RECT 1947.920000 2451.140000 1949.020000 2451.620000 ;
+ RECT 1947.920000 2456.580000 1949.020000 2457.060000 ;
+ RECT 1947.920000 2462.020000 1949.020000 2462.500000 ;
+ RECT 1947.920000 2472.900000 1949.020000 2473.380000 ;
+ RECT 1902.920000 2451.140000 1904.020000 2451.620000 ;
+ RECT 1902.920000 2456.580000 1904.020000 2457.060000 ;
+ RECT 1902.920000 2462.020000 1904.020000 2462.500000 ;
+ RECT 1902.920000 2467.460000 1904.020000 2467.940000 ;
+ RECT 1902.920000 2472.900000 1904.020000 2473.380000 ;
+ RECT 1857.920000 2494.660000 1859.020000 2495.140000 ;
+ RECT 1853.790000 2494.660000 1854.790000 2495.140000 ;
+ RECT 1857.920000 2489.220000 1859.020000 2489.700000 ;
+ RECT 1853.790000 2489.220000 1854.790000 2489.700000 ;
+ RECT 1857.920000 2483.780000 1859.020000 2484.260000 ;
+ RECT 1853.790000 2483.780000 1854.790000 2484.260000 ;
+ RECT 1857.920000 2478.340000 1859.020000 2478.820000 ;
+ RECT 1853.790000 2478.340000 1854.790000 2478.820000 ;
+ RECT 1857.920000 2472.900000 1859.020000 2473.380000 ;
+ RECT 1857.920000 2467.460000 1859.020000 2467.940000 ;
+ RECT 1853.790000 2472.900000 1854.790000 2473.380000 ;
+ RECT 1853.790000 2467.460000 1854.790000 2467.940000 ;
+ RECT 1857.920000 2462.020000 1859.020000 2462.500000 ;
+ RECT 1853.790000 2462.020000 1854.790000 2462.500000 ;
+ RECT 1857.920000 2456.580000 1859.020000 2457.060000 ;
+ RECT 1853.790000 2456.580000 1854.790000 2457.060000 ;
+ RECT 1857.920000 2451.140000 1859.020000 2451.620000 ;
+ RECT 1853.790000 2451.140000 1854.790000 2451.620000 ;
+ RECT 2037.920000 2445.700000 2039.020000 2446.180000 ;
+ RECT 2037.920000 2440.260000 2039.020000 2440.740000 ;
+ RECT 2047.230000 2445.700000 2048.230000 2446.180000 ;
+ RECT 2047.230000 2440.260000 2048.230000 2440.740000 ;
+ RECT 2047.230000 2423.940000 2048.230000 2424.420000 ;
+ RECT 2047.230000 2429.380000 2048.230000 2429.860000 ;
+ RECT 2047.230000 2434.820000 2048.230000 2435.300000 ;
+ RECT 2037.920000 2434.820000 2039.020000 2435.300000 ;
+ RECT 2037.920000 2429.380000 2039.020000 2429.860000 ;
+ RECT 2037.920000 2423.940000 2039.020000 2424.420000 ;
+ RECT 2037.920000 2413.060000 2039.020000 2413.540000 ;
+ RECT 2037.920000 2418.500000 2039.020000 2418.980000 ;
+ RECT 2047.230000 2418.500000 2048.230000 2418.980000 ;
+ RECT 2047.230000 2413.060000 2048.230000 2413.540000 ;
+ RECT 2047.230000 2402.180000 2048.230000 2402.660000 ;
+ RECT 2047.230000 2407.620000 2048.230000 2408.100000 ;
+ RECT 2037.920000 2402.180000 2039.020000 2402.660000 ;
+ RECT 2037.920000 2407.620000 2039.020000 2408.100000 ;
+ RECT 1992.920000 2445.700000 1994.020000 2446.180000 ;
+ RECT 1992.920000 2440.260000 1994.020000 2440.740000 ;
+ RECT 1992.920000 2434.820000 1994.020000 2435.300000 ;
+ RECT 1992.920000 2429.380000 1994.020000 2429.860000 ;
+ RECT 1992.920000 2423.940000 1994.020000 2424.420000 ;
+ RECT 1992.920000 2402.180000 1994.020000 2402.660000 ;
+ RECT 1992.920000 2407.620000 1994.020000 2408.100000 ;
+ RECT 1992.920000 2413.060000 1994.020000 2413.540000 ;
+ RECT 1992.920000 2418.500000 1994.020000 2418.980000 ;
+ RECT 2037.920000 2396.740000 2039.020000 2397.220000 ;
+ RECT 2037.920000 2391.300000 2039.020000 2391.780000 ;
+ RECT 2047.230000 2396.740000 2048.230000 2397.220000 ;
+ RECT 2047.230000 2391.300000 2048.230000 2391.780000 ;
+ RECT 2037.920000 2380.420000 2039.020000 2380.900000 ;
+ RECT 2037.920000 2374.980000 2039.020000 2375.460000 ;
+ RECT 2047.230000 2380.420000 2048.230000 2380.900000 ;
+ RECT 2047.230000 2374.980000 2048.230000 2375.460000 ;
+ RECT 2037.920000 2385.860000 2039.020000 2386.340000 ;
+ RECT 2047.230000 2385.860000 2048.230000 2386.340000 ;
+ RECT 2047.230000 2364.100000 2048.230000 2364.580000 ;
+ RECT 2047.230000 2369.540000 2048.230000 2370.020000 ;
+ RECT 2037.920000 2369.540000 2039.020000 2370.020000 ;
+ RECT 2037.920000 2364.100000 2039.020000 2364.580000 ;
+ RECT 2037.920000 2358.660000 2039.020000 2359.140000 ;
+ RECT 2037.920000 2353.220000 2039.020000 2353.700000 ;
+ RECT 2047.230000 2358.660000 2048.230000 2359.140000 ;
+ RECT 2047.230000 2353.220000 2048.230000 2353.700000 ;
+ RECT 1992.920000 2396.740000 1994.020000 2397.220000 ;
+ RECT 1992.920000 2391.300000 1994.020000 2391.780000 ;
+ RECT 1992.920000 2385.860000 1994.020000 2386.340000 ;
+ RECT 1992.920000 2380.420000 1994.020000 2380.900000 ;
+ RECT 1992.920000 2374.980000 1994.020000 2375.460000 ;
+ RECT 1992.920000 2369.540000 1994.020000 2370.020000 ;
+ RECT 1992.920000 2364.100000 1994.020000 2364.580000 ;
+ RECT 1992.920000 2358.660000 1994.020000 2359.140000 ;
+ RECT 1992.920000 2353.220000 1994.020000 2353.700000 ;
+ RECT 1947.920000 2445.700000 1949.020000 2446.180000 ;
+ RECT 1947.920000 2440.260000 1949.020000 2440.740000 ;
+ RECT 1947.920000 2434.820000 1949.020000 2435.300000 ;
+ RECT 1947.920000 2429.380000 1949.020000 2429.860000 ;
+ RECT 1947.920000 2423.940000 1949.020000 2424.420000 ;
+ RECT 1902.920000 2445.700000 1904.020000 2446.180000 ;
+ RECT 1902.920000 2440.260000 1904.020000 2440.740000 ;
+ RECT 1902.920000 2434.820000 1904.020000 2435.300000 ;
+ RECT 1902.920000 2429.380000 1904.020000 2429.860000 ;
+ RECT 1902.920000 2423.940000 1904.020000 2424.420000 ;
+ RECT 1947.920000 2418.500000 1949.020000 2418.980000 ;
+ RECT 1947.920000 2413.060000 1949.020000 2413.540000 ;
+ RECT 1947.920000 2407.620000 1949.020000 2408.100000 ;
+ RECT 1947.920000 2402.180000 1949.020000 2402.660000 ;
+ RECT 1902.920000 2413.060000 1904.020000 2413.540000 ;
+ RECT 1902.920000 2407.620000 1904.020000 2408.100000 ;
+ RECT 1902.920000 2402.180000 1904.020000 2402.660000 ;
+ RECT 1902.920000 2418.500000 1904.020000 2418.980000 ;
+ RECT 1857.920000 2445.700000 1859.020000 2446.180000 ;
+ RECT 1853.790000 2445.700000 1854.790000 2446.180000 ;
+ RECT 1857.920000 2440.260000 1859.020000 2440.740000 ;
+ RECT 1853.790000 2440.260000 1854.790000 2440.740000 ;
+ RECT 1857.920000 2434.820000 1859.020000 2435.300000 ;
+ RECT 1853.790000 2434.820000 1854.790000 2435.300000 ;
+ RECT 1857.920000 2423.940000 1859.020000 2424.420000 ;
+ RECT 1853.790000 2423.940000 1854.790000 2424.420000 ;
+ RECT 1853.790000 2429.380000 1854.790000 2429.860000 ;
+ RECT 1857.920000 2429.380000 1859.020000 2429.860000 ;
+ RECT 1857.920000 2418.500000 1859.020000 2418.980000 ;
+ RECT 1853.790000 2418.500000 1854.790000 2418.980000 ;
+ RECT 1857.920000 2413.060000 1859.020000 2413.540000 ;
+ RECT 1853.790000 2413.060000 1854.790000 2413.540000 ;
+ RECT 1857.920000 2407.620000 1859.020000 2408.100000 ;
+ RECT 1853.790000 2407.620000 1854.790000 2408.100000 ;
+ RECT 1857.920000 2402.180000 1859.020000 2402.660000 ;
+ RECT 1853.790000 2402.180000 1854.790000 2402.660000 ;
+ RECT 1947.920000 2396.740000 1949.020000 2397.220000 ;
+ RECT 1947.920000 2391.300000 1949.020000 2391.780000 ;
+ RECT 1947.920000 2385.860000 1949.020000 2386.340000 ;
+ RECT 1947.920000 2380.420000 1949.020000 2380.900000 ;
+ RECT 1947.920000 2374.980000 1949.020000 2375.460000 ;
+ RECT 1902.920000 2396.740000 1904.020000 2397.220000 ;
+ RECT 1902.920000 2391.300000 1904.020000 2391.780000 ;
+ RECT 1902.920000 2385.860000 1904.020000 2386.340000 ;
+ RECT 1902.920000 2380.420000 1904.020000 2380.900000 ;
+ RECT 1902.920000 2374.980000 1904.020000 2375.460000 ;
+ RECT 1947.920000 2353.220000 1949.020000 2353.700000 ;
+ RECT 1947.920000 2358.660000 1949.020000 2359.140000 ;
+ RECT 1947.920000 2364.100000 1949.020000 2364.580000 ;
+ RECT 1947.920000 2369.540000 1949.020000 2370.020000 ;
+ RECT 1902.920000 2353.220000 1904.020000 2353.700000 ;
+ RECT 1902.920000 2358.660000 1904.020000 2359.140000 ;
+ RECT 1902.920000 2364.100000 1904.020000 2364.580000 ;
+ RECT 1902.920000 2369.540000 1904.020000 2370.020000 ;
+ RECT 1857.920000 2396.740000 1859.020000 2397.220000 ;
+ RECT 1853.790000 2396.740000 1854.790000 2397.220000 ;
+ RECT 1857.920000 2391.300000 1859.020000 2391.780000 ;
+ RECT 1853.790000 2391.300000 1854.790000 2391.780000 ;
+ RECT 1857.920000 2380.420000 1859.020000 2380.900000 ;
+ RECT 1853.790000 2380.420000 1854.790000 2380.900000 ;
+ RECT 1857.920000 2374.980000 1859.020000 2375.460000 ;
+ RECT 1853.790000 2374.980000 1854.790000 2375.460000 ;
+ RECT 1857.920000 2385.860000 1859.020000 2386.340000 ;
+ RECT 1853.790000 2385.860000 1854.790000 2386.340000 ;
+ RECT 1857.920000 2369.540000 1859.020000 2370.020000 ;
+ RECT 1853.790000 2369.540000 1854.790000 2370.020000 ;
+ RECT 1857.920000 2364.100000 1859.020000 2364.580000 ;
+ RECT 1853.790000 2364.100000 1854.790000 2364.580000 ;
+ RECT 1857.920000 2358.660000 1859.020000 2359.140000 ;
+ RECT 1857.920000 2353.220000 1859.020000 2353.700000 ;
+ RECT 1853.790000 2358.660000 1854.790000 2359.140000 ;
+ RECT 1853.790000 2353.220000 1854.790000 2353.700000 ;
+ RECT 1850.960000 2543.580000 2051.060000 2544.580000 ;
+ RECT 1850.960000 2351.210000 2051.060000 2352.210000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 2348.360000 1854.790000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 2547.620000 1854.790000 2548.620000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 2348.360000 2048.230000 2349.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 2547.620000 2048.230000 2548.620000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2351.210000 1851.960000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2351.210000 2051.060000 2352.210000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2543.580000 1851.960000 2544.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2543.580000 2051.060000 2544.580000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 2150.950000 2039.020000 2344.320000 ;
+ RECT 1992.920000 2150.950000 1994.020000 2344.320000 ;
+ RECT 2047.230000 2148.100000 2048.230000 2348.360000 ;
+ RECT 1947.920000 2150.950000 1949.020000 2344.320000 ;
+ RECT 1902.920000 2150.950000 1904.020000 2344.320000 ;
+ RECT 1857.920000 2150.950000 1859.020000 2344.320000 ;
+ RECT 1853.790000 2148.100000 1854.790000 2348.360000 ;
+ LAYER met3 ;
+ RECT 2037.920000 2337.920000 2039.020000 2338.400000 ;
+ RECT 2047.230000 2337.920000 2048.230000 2338.400000 ;
+ RECT 2047.230000 2327.040000 2048.230000 2327.520000 ;
+ RECT 2047.230000 2332.480000 2048.230000 2332.960000 ;
+ RECT 2037.920000 2332.480000 2039.020000 2332.960000 ;
+ RECT 2037.920000 2327.040000 2039.020000 2327.520000 ;
+ RECT 2037.920000 2321.600000 2039.020000 2322.080000 ;
+ RECT 2037.920000 2316.160000 2039.020000 2316.640000 ;
+ RECT 2047.230000 2321.600000 2048.230000 2322.080000 ;
+ RECT 2047.230000 2316.160000 2048.230000 2316.640000 ;
+ RECT 2037.920000 2299.840000 2039.020000 2300.320000 ;
+ RECT 2037.920000 2305.280000 2039.020000 2305.760000 ;
+ RECT 2047.230000 2305.280000 2048.230000 2305.760000 ;
+ RECT 2047.230000 2299.840000 2048.230000 2300.320000 ;
+ RECT 2037.920000 2310.720000 2039.020000 2311.200000 ;
+ RECT 2047.230000 2310.720000 2048.230000 2311.200000 ;
+ RECT 1992.920000 2337.920000 1994.020000 2338.400000 ;
+ RECT 1992.920000 2332.480000 1994.020000 2332.960000 ;
+ RECT 1992.920000 2327.040000 1994.020000 2327.520000 ;
+ RECT 1992.920000 2321.600000 1994.020000 2322.080000 ;
+ RECT 1992.920000 2299.840000 1994.020000 2300.320000 ;
+ RECT 1992.920000 2305.280000 1994.020000 2305.760000 ;
+ RECT 1992.920000 2310.720000 1994.020000 2311.200000 ;
+ RECT 1992.920000 2316.160000 1994.020000 2316.640000 ;
+ RECT 2047.230000 2288.960000 2048.230000 2289.440000 ;
+ RECT 2047.230000 2294.400000 2048.230000 2294.880000 ;
+ RECT 2037.920000 2294.400000 2039.020000 2294.880000 ;
+ RECT 2037.920000 2288.960000 2039.020000 2289.440000 ;
+ RECT 2037.920000 2283.520000 2039.020000 2284.000000 ;
+ RECT 2037.920000 2278.080000 2039.020000 2278.560000 ;
+ RECT 2047.230000 2283.520000 2048.230000 2284.000000 ;
+ RECT 2047.230000 2278.080000 2048.230000 2278.560000 ;
+ RECT 2047.230000 2261.760000 2048.230000 2262.240000 ;
+ RECT 2047.230000 2267.200000 2048.230000 2267.680000 ;
+ RECT 2047.230000 2272.640000 2048.230000 2273.120000 ;
+ RECT 2037.920000 2267.200000 2039.020000 2267.680000 ;
+ RECT 2037.920000 2261.760000 2039.020000 2262.240000 ;
+ RECT 2037.920000 2272.640000 2039.020000 2273.120000 ;
+ RECT 2037.920000 2256.320000 2039.020000 2256.800000 ;
+ RECT 2037.920000 2250.880000 2039.020000 2251.360000 ;
+ RECT 2047.230000 2256.320000 2048.230000 2256.800000 ;
+ RECT 2047.230000 2250.880000 2048.230000 2251.360000 ;
+ RECT 1992.920000 2294.400000 1994.020000 2294.880000 ;
+ RECT 1992.920000 2288.960000 1994.020000 2289.440000 ;
+ RECT 1992.920000 2283.520000 1994.020000 2284.000000 ;
+ RECT 1992.920000 2278.080000 1994.020000 2278.560000 ;
+ RECT 1992.920000 2267.200000 1994.020000 2267.680000 ;
+ RECT 1992.920000 2261.760000 1994.020000 2262.240000 ;
+ RECT 1992.920000 2256.320000 1994.020000 2256.800000 ;
+ RECT 1992.920000 2250.880000 1994.020000 2251.360000 ;
+ RECT 1992.920000 2272.640000 1994.020000 2273.120000 ;
+ RECT 1947.920000 2337.920000 1949.020000 2338.400000 ;
+ RECT 1947.920000 2332.480000 1949.020000 2332.960000 ;
+ RECT 1947.920000 2327.040000 1949.020000 2327.520000 ;
+ RECT 1902.920000 2337.920000 1904.020000 2338.400000 ;
+ RECT 1902.920000 2332.480000 1904.020000 2332.960000 ;
+ RECT 1902.920000 2327.040000 1904.020000 2327.520000 ;
+ RECT 1947.920000 2310.720000 1949.020000 2311.200000 ;
+ RECT 1947.920000 2305.280000 1949.020000 2305.760000 ;
+ RECT 1947.920000 2299.840000 1949.020000 2300.320000 ;
+ RECT 1947.920000 2316.160000 1949.020000 2316.640000 ;
+ RECT 1947.920000 2321.600000 1949.020000 2322.080000 ;
+ RECT 1902.920000 2321.600000 1904.020000 2322.080000 ;
+ RECT 1902.920000 2310.720000 1904.020000 2311.200000 ;
+ RECT 1902.920000 2305.280000 1904.020000 2305.760000 ;
+ RECT 1902.920000 2299.840000 1904.020000 2300.320000 ;
+ RECT 1902.920000 2316.160000 1904.020000 2316.640000 ;
+ RECT 1857.920000 2337.920000 1859.020000 2338.400000 ;
+ RECT 1853.790000 2337.920000 1854.790000 2338.400000 ;
+ RECT 1853.790000 2332.480000 1854.790000 2332.960000 ;
+ RECT 1857.920000 2332.480000 1859.020000 2332.960000 ;
+ RECT 1857.920000 2327.040000 1859.020000 2327.520000 ;
+ RECT 1853.790000 2327.040000 1854.790000 2327.520000 ;
+ RECT 1857.920000 2321.600000 1859.020000 2322.080000 ;
+ RECT 1853.790000 2321.600000 1854.790000 2322.080000 ;
+ RECT 1857.920000 2316.160000 1859.020000 2316.640000 ;
+ RECT 1853.790000 2316.160000 1854.790000 2316.640000 ;
+ RECT 1857.920000 2305.280000 1859.020000 2305.760000 ;
+ RECT 1853.790000 2305.280000 1854.790000 2305.760000 ;
+ RECT 1857.920000 2299.840000 1859.020000 2300.320000 ;
+ RECT 1853.790000 2299.840000 1854.790000 2300.320000 ;
+ RECT 1857.920000 2310.720000 1859.020000 2311.200000 ;
+ RECT 1853.790000 2310.720000 1854.790000 2311.200000 ;
+ RECT 1947.920000 2294.400000 1949.020000 2294.880000 ;
+ RECT 1947.920000 2288.960000 1949.020000 2289.440000 ;
+ RECT 1947.920000 2283.520000 1949.020000 2284.000000 ;
+ RECT 1947.920000 2278.080000 1949.020000 2278.560000 ;
+ RECT 1902.920000 2294.400000 1904.020000 2294.880000 ;
+ RECT 1902.920000 2288.960000 1904.020000 2289.440000 ;
+ RECT 1902.920000 2283.520000 1904.020000 2284.000000 ;
+ RECT 1902.920000 2278.080000 1904.020000 2278.560000 ;
+ RECT 1947.920000 2267.200000 1949.020000 2267.680000 ;
+ RECT 1947.920000 2250.880000 1949.020000 2251.360000 ;
+ RECT 1947.920000 2256.320000 1949.020000 2256.800000 ;
+ RECT 1947.920000 2261.760000 1949.020000 2262.240000 ;
+ RECT 1947.920000 2272.640000 1949.020000 2273.120000 ;
+ RECT 1902.920000 2250.880000 1904.020000 2251.360000 ;
+ RECT 1902.920000 2256.320000 1904.020000 2256.800000 ;
+ RECT 1902.920000 2261.760000 1904.020000 2262.240000 ;
+ RECT 1902.920000 2267.200000 1904.020000 2267.680000 ;
+ RECT 1902.920000 2272.640000 1904.020000 2273.120000 ;
+ RECT 1857.920000 2294.400000 1859.020000 2294.880000 ;
+ RECT 1853.790000 2294.400000 1854.790000 2294.880000 ;
+ RECT 1857.920000 2288.960000 1859.020000 2289.440000 ;
+ RECT 1853.790000 2288.960000 1854.790000 2289.440000 ;
+ RECT 1857.920000 2283.520000 1859.020000 2284.000000 ;
+ RECT 1853.790000 2283.520000 1854.790000 2284.000000 ;
+ RECT 1857.920000 2278.080000 1859.020000 2278.560000 ;
+ RECT 1853.790000 2278.080000 1854.790000 2278.560000 ;
+ RECT 1857.920000 2272.640000 1859.020000 2273.120000 ;
+ RECT 1857.920000 2267.200000 1859.020000 2267.680000 ;
+ RECT 1853.790000 2272.640000 1854.790000 2273.120000 ;
+ RECT 1853.790000 2267.200000 1854.790000 2267.680000 ;
+ RECT 1857.920000 2261.760000 1859.020000 2262.240000 ;
+ RECT 1853.790000 2261.760000 1854.790000 2262.240000 ;
+ RECT 1857.920000 2256.320000 1859.020000 2256.800000 ;
+ RECT 1853.790000 2256.320000 1854.790000 2256.800000 ;
+ RECT 1857.920000 2250.880000 1859.020000 2251.360000 ;
+ RECT 1853.790000 2250.880000 1854.790000 2251.360000 ;
+ RECT 2037.920000 2245.440000 2039.020000 2245.920000 ;
+ RECT 2037.920000 2240.000000 2039.020000 2240.480000 ;
+ RECT 2047.230000 2245.440000 2048.230000 2245.920000 ;
+ RECT 2047.230000 2240.000000 2048.230000 2240.480000 ;
+ RECT 2047.230000 2223.680000 2048.230000 2224.160000 ;
+ RECT 2047.230000 2229.120000 2048.230000 2229.600000 ;
+ RECT 2047.230000 2234.560000 2048.230000 2235.040000 ;
+ RECT 2037.920000 2234.560000 2039.020000 2235.040000 ;
+ RECT 2037.920000 2229.120000 2039.020000 2229.600000 ;
+ RECT 2037.920000 2223.680000 2039.020000 2224.160000 ;
+ RECT 2037.920000 2212.800000 2039.020000 2213.280000 ;
+ RECT 2037.920000 2218.240000 2039.020000 2218.720000 ;
+ RECT 2047.230000 2218.240000 2048.230000 2218.720000 ;
+ RECT 2047.230000 2212.800000 2048.230000 2213.280000 ;
+ RECT 2047.230000 2201.920000 2048.230000 2202.400000 ;
+ RECT 2047.230000 2207.360000 2048.230000 2207.840000 ;
+ RECT 2037.920000 2201.920000 2039.020000 2202.400000 ;
+ RECT 2037.920000 2207.360000 2039.020000 2207.840000 ;
+ RECT 1992.920000 2245.440000 1994.020000 2245.920000 ;
+ RECT 1992.920000 2240.000000 1994.020000 2240.480000 ;
+ RECT 1992.920000 2234.560000 1994.020000 2235.040000 ;
+ RECT 1992.920000 2229.120000 1994.020000 2229.600000 ;
+ RECT 1992.920000 2223.680000 1994.020000 2224.160000 ;
+ RECT 1992.920000 2201.920000 1994.020000 2202.400000 ;
+ RECT 1992.920000 2207.360000 1994.020000 2207.840000 ;
+ RECT 1992.920000 2212.800000 1994.020000 2213.280000 ;
+ RECT 1992.920000 2218.240000 1994.020000 2218.720000 ;
+ RECT 2037.920000 2196.480000 2039.020000 2196.960000 ;
+ RECT 2037.920000 2191.040000 2039.020000 2191.520000 ;
+ RECT 2047.230000 2196.480000 2048.230000 2196.960000 ;
+ RECT 2047.230000 2191.040000 2048.230000 2191.520000 ;
+ RECT 2037.920000 2180.160000 2039.020000 2180.640000 ;
+ RECT 2037.920000 2174.720000 2039.020000 2175.200000 ;
+ RECT 2047.230000 2180.160000 2048.230000 2180.640000 ;
+ RECT 2047.230000 2174.720000 2048.230000 2175.200000 ;
+ RECT 2037.920000 2185.600000 2039.020000 2186.080000 ;
+ RECT 2047.230000 2185.600000 2048.230000 2186.080000 ;
+ RECT 2047.230000 2163.840000 2048.230000 2164.320000 ;
+ RECT 2047.230000 2169.280000 2048.230000 2169.760000 ;
+ RECT 2037.920000 2169.280000 2039.020000 2169.760000 ;
+ RECT 2037.920000 2163.840000 2039.020000 2164.320000 ;
+ RECT 2037.920000 2158.400000 2039.020000 2158.880000 ;
+ RECT 2037.920000 2152.960000 2039.020000 2153.440000 ;
+ RECT 2047.230000 2158.400000 2048.230000 2158.880000 ;
+ RECT 2047.230000 2152.960000 2048.230000 2153.440000 ;
+ RECT 1992.920000 2196.480000 1994.020000 2196.960000 ;
+ RECT 1992.920000 2191.040000 1994.020000 2191.520000 ;
+ RECT 1992.920000 2185.600000 1994.020000 2186.080000 ;
+ RECT 1992.920000 2180.160000 1994.020000 2180.640000 ;
+ RECT 1992.920000 2174.720000 1994.020000 2175.200000 ;
+ RECT 1992.920000 2169.280000 1994.020000 2169.760000 ;
+ RECT 1992.920000 2163.840000 1994.020000 2164.320000 ;
+ RECT 1992.920000 2158.400000 1994.020000 2158.880000 ;
+ RECT 1992.920000 2152.960000 1994.020000 2153.440000 ;
+ RECT 1947.920000 2245.440000 1949.020000 2245.920000 ;
+ RECT 1947.920000 2240.000000 1949.020000 2240.480000 ;
+ RECT 1947.920000 2234.560000 1949.020000 2235.040000 ;
+ RECT 1947.920000 2229.120000 1949.020000 2229.600000 ;
+ RECT 1947.920000 2223.680000 1949.020000 2224.160000 ;
+ RECT 1902.920000 2245.440000 1904.020000 2245.920000 ;
+ RECT 1902.920000 2240.000000 1904.020000 2240.480000 ;
+ RECT 1902.920000 2234.560000 1904.020000 2235.040000 ;
+ RECT 1902.920000 2229.120000 1904.020000 2229.600000 ;
+ RECT 1902.920000 2223.680000 1904.020000 2224.160000 ;
+ RECT 1947.920000 2218.240000 1949.020000 2218.720000 ;
+ RECT 1947.920000 2212.800000 1949.020000 2213.280000 ;
+ RECT 1947.920000 2207.360000 1949.020000 2207.840000 ;
+ RECT 1947.920000 2201.920000 1949.020000 2202.400000 ;
+ RECT 1902.920000 2212.800000 1904.020000 2213.280000 ;
+ RECT 1902.920000 2207.360000 1904.020000 2207.840000 ;
+ RECT 1902.920000 2201.920000 1904.020000 2202.400000 ;
+ RECT 1902.920000 2218.240000 1904.020000 2218.720000 ;
+ RECT 1857.920000 2245.440000 1859.020000 2245.920000 ;
+ RECT 1853.790000 2245.440000 1854.790000 2245.920000 ;
+ RECT 1857.920000 2240.000000 1859.020000 2240.480000 ;
+ RECT 1853.790000 2240.000000 1854.790000 2240.480000 ;
+ RECT 1857.920000 2234.560000 1859.020000 2235.040000 ;
+ RECT 1853.790000 2234.560000 1854.790000 2235.040000 ;
+ RECT 1857.920000 2223.680000 1859.020000 2224.160000 ;
+ RECT 1853.790000 2223.680000 1854.790000 2224.160000 ;
+ RECT 1853.790000 2229.120000 1854.790000 2229.600000 ;
+ RECT 1857.920000 2229.120000 1859.020000 2229.600000 ;
+ RECT 1857.920000 2218.240000 1859.020000 2218.720000 ;
+ RECT 1853.790000 2218.240000 1854.790000 2218.720000 ;
+ RECT 1857.920000 2212.800000 1859.020000 2213.280000 ;
+ RECT 1853.790000 2212.800000 1854.790000 2213.280000 ;
+ RECT 1857.920000 2207.360000 1859.020000 2207.840000 ;
+ RECT 1853.790000 2207.360000 1854.790000 2207.840000 ;
+ RECT 1857.920000 2201.920000 1859.020000 2202.400000 ;
+ RECT 1853.790000 2201.920000 1854.790000 2202.400000 ;
+ RECT 1947.920000 2196.480000 1949.020000 2196.960000 ;
+ RECT 1947.920000 2191.040000 1949.020000 2191.520000 ;
+ RECT 1947.920000 2185.600000 1949.020000 2186.080000 ;
+ RECT 1947.920000 2180.160000 1949.020000 2180.640000 ;
+ RECT 1947.920000 2174.720000 1949.020000 2175.200000 ;
+ RECT 1902.920000 2196.480000 1904.020000 2196.960000 ;
+ RECT 1902.920000 2191.040000 1904.020000 2191.520000 ;
+ RECT 1902.920000 2185.600000 1904.020000 2186.080000 ;
+ RECT 1902.920000 2180.160000 1904.020000 2180.640000 ;
+ RECT 1902.920000 2174.720000 1904.020000 2175.200000 ;
+ RECT 1947.920000 2152.960000 1949.020000 2153.440000 ;
+ RECT 1947.920000 2158.400000 1949.020000 2158.880000 ;
+ RECT 1947.920000 2163.840000 1949.020000 2164.320000 ;
+ RECT 1947.920000 2169.280000 1949.020000 2169.760000 ;
+ RECT 1902.920000 2152.960000 1904.020000 2153.440000 ;
+ RECT 1902.920000 2158.400000 1904.020000 2158.880000 ;
+ RECT 1902.920000 2163.840000 1904.020000 2164.320000 ;
+ RECT 1902.920000 2169.280000 1904.020000 2169.760000 ;
+ RECT 1857.920000 2196.480000 1859.020000 2196.960000 ;
+ RECT 1853.790000 2196.480000 1854.790000 2196.960000 ;
+ RECT 1857.920000 2191.040000 1859.020000 2191.520000 ;
+ RECT 1853.790000 2191.040000 1854.790000 2191.520000 ;
+ RECT 1857.920000 2180.160000 1859.020000 2180.640000 ;
+ RECT 1853.790000 2180.160000 1854.790000 2180.640000 ;
+ RECT 1857.920000 2174.720000 1859.020000 2175.200000 ;
+ RECT 1853.790000 2174.720000 1854.790000 2175.200000 ;
+ RECT 1857.920000 2185.600000 1859.020000 2186.080000 ;
+ RECT 1853.790000 2185.600000 1854.790000 2186.080000 ;
+ RECT 1857.920000 2169.280000 1859.020000 2169.760000 ;
+ RECT 1853.790000 2169.280000 1854.790000 2169.760000 ;
+ RECT 1857.920000 2163.840000 1859.020000 2164.320000 ;
+ RECT 1853.790000 2163.840000 1854.790000 2164.320000 ;
+ RECT 1857.920000 2158.400000 1859.020000 2158.880000 ;
+ RECT 1857.920000 2152.960000 1859.020000 2153.440000 ;
+ RECT 1853.790000 2158.400000 1854.790000 2158.880000 ;
+ RECT 1853.790000 2152.960000 1854.790000 2153.440000 ;
+ RECT 1850.960000 2343.320000 2051.060000 2344.320000 ;
+ RECT 1850.960000 2150.950000 2051.060000 2151.950000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 2148.100000 1854.790000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 2347.360000 1854.790000 2348.360000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 2148.100000 2048.230000 2149.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 2347.360000 2048.230000 2348.360000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2150.950000 1851.960000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2150.950000 2051.060000 2151.950000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2343.320000 1851.960000 2344.320000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2343.320000 2051.060000 2344.320000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 1950.690000 2039.020000 2144.060000 ;
+ RECT 1992.920000 1950.690000 1994.020000 2144.060000 ;
+ RECT 2047.230000 1947.840000 2048.230000 2148.100000 ;
+ RECT 1947.920000 1950.690000 1949.020000 2144.060000 ;
+ RECT 1902.920000 1950.690000 1904.020000 2144.060000 ;
+ RECT 1857.920000 1950.690000 1859.020000 2144.060000 ;
+ RECT 1853.790000 1947.840000 1854.790000 2148.100000 ;
+ LAYER met3 ;
+ RECT 2037.920000 2137.660000 2039.020000 2138.140000 ;
+ RECT 2047.230000 2137.660000 2048.230000 2138.140000 ;
+ RECT 2047.230000 2126.780000 2048.230000 2127.260000 ;
+ RECT 2047.230000 2132.220000 2048.230000 2132.700000 ;
+ RECT 2037.920000 2132.220000 2039.020000 2132.700000 ;
+ RECT 2037.920000 2126.780000 2039.020000 2127.260000 ;
+ RECT 2037.920000 2121.340000 2039.020000 2121.820000 ;
+ RECT 2037.920000 2115.900000 2039.020000 2116.380000 ;
+ RECT 2047.230000 2121.340000 2048.230000 2121.820000 ;
+ RECT 2047.230000 2115.900000 2048.230000 2116.380000 ;
+ RECT 2037.920000 2099.580000 2039.020000 2100.060000 ;
+ RECT 2037.920000 2105.020000 2039.020000 2105.500000 ;
+ RECT 2047.230000 2105.020000 2048.230000 2105.500000 ;
+ RECT 2047.230000 2099.580000 2048.230000 2100.060000 ;
+ RECT 2037.920000 2110.460000 2039.020000 2110.940000 ;
+ RECT 2047.230000 2110.460000 2048.230000 2110.940000 ;
+ RECT 1992.920000 2137.660000 1994.020000 2138.140000 ;
+ RECT 1992.920000 2132.220000 1994.020000 2132.700000 ;
+ RECT 1992.920000 2126.780000 1994.020000 2127.260000 ;
+ RECT 1992.920000 2121.340000 1994.020000 2121.820000 ;
+ RECT 1992.920000 2099.580000 1994.020000 2100.060000 ;
+ RECT 1992.920000 2105.020000 1994.020000 2105.500000 ;
+ RECT 1992.920000 2110.460000 1994.020000 2110.940000 ;
+ RECT 1992.920000 2115.900000 1994.020000 2116.380000 ;
+ RECT 2047.230000 2088.700000 2048.230000 2089.180000 ;
+ RECT 2047.230000 2094.140000 2048.230000 2094.620000 ;
+ RECT 2037.920000 2094.140000 2039.020000 2094.620000 ;
+ RECT 2037.920000 2088.700000 2039.020000 2089.180000 ;
+ RECT 2037.920000 2083.260000 2039.020000 2083.740000 ;
+ RECT 2037.920000 2077.820000 2039.020000 2078.300000 ;
+ RECT 2047.230000 2083.260000 2048.230000 2083.740000 ;
+ RECT 2047.230000 2077.820000 2048.230000 2078.300000 ;
+ RECT 2047.230000 2061.500000 2048.230000 2061.980000 ;
+ RECT 2047.230000 2066.940000 2048.230000 2067.420000 ;
+ RECT 2047.230000 2072.380000 2048.230000 2072.860000 ;
+ RECT 2037.920000 2066.940000 2039.020000 2067.420000 ;
+ RECT 2037.920000 2061.500000 2039.020000 2061.980000 ;
+ RECT 2037.920000 2072.380000 2039.020000 2072.860000 ;
+ RECT 2037.920000 2056.060000 2039.020000 2056.540000 ;
+ RECT 2037.920000 2050.620000 2039.020000 2051.100000 ;
+ RECT 2047.230000 2056.060000 2048.230000 2056.540000 ;
+ RECT 2047.230000 2050.620000 2048.230000 2051.100000 ;
+ RECT 1992.920000 2094.140000 1994.020000 2094.620000 ;
+ RECT 1992.920000 2088.700000 1994.020000 2089.180000 ;
+ RECT 1992.920000 2083.260000 1994.020000 2083.740000 ;
+ RECT 1992.920000 2077.820000 1994.020000 2078.300000 ;
+ RECT 1992.920000 2066.940000 1994.020000 2067.420000 ;
+ RECT 1992.920000 2061.500000 1994.020000 2061.980000 ;
+ RECT 1992.920000 2056.060000 1994.020000 2056.540000 ;
+ RECT 1992.920000 2050.620000 1994.020000 2051.100000 ;
+ RECT 1992.920000 2072.380000 1994.020000 2072.860000 ;
+ RECT 1947.920000 2137.660000 1949.020000 2138.140000 ;
+ RECT 1947.920000 2132.220000 1949.020000 2132.700000 ;
+ RECT 1947.920000 2126.780000 1949.020000 2127.260000 ;
+ RECT 1902.920000 2137.660000 1904.020000 2138.140000 ;
+ RECT 1902.920000 2132.220000 1904.020000 2132.700000 ;
+ RECT 1902.920000 2126.780000 1904.020000 2127.260000 ;
+ RECT 1947.920000 2110.460000 1949.020000 2110.940000 ;
+ RECT 1947.920000 2105.020000 1949.020000 2105.500000 ;
+ RECT 1947.920000 2099.580000 1949.020000 2100.060000 ;
+ RECT 1947.920000 2115.900000 1949.020000 2116.380000 ;
+ RECT 1947.920000 2121.340000 1949.020000 2121.820000 ;
+ RECT 1902.920000 2121.340000 1904.020000 2121.820000 ;
+ RECT 1902.920000 2110.460000 1904.020000 2110.940000 ;
+ RECT 1902.920000 2105.020000 1904.020000 2105.500000 ;
+ RECT 1902.920000 2099.580000 1904.020000 2100.060000 ;
+ RECT 1902.920000 2115.900000 1904.020000 2116.380000 ;
+ RECT 1857.920000 2137.660000 1859.020000 2138.140000 ;
+ RECT 1853.790000 2137.660000 1854.790000 2138.140000 ;
+ RECT 1853.790000 2132.220000 1854.790000 2132.700000 ;
+ RECT 1857.920000 2132.220000 1859.020000 2132.700000 ;
+ RECT 1857.920000 2126.780000 1859.020000 2127.260000 ;
+ RECT 1853.790000 2126.780000 1854.790000 2127.260000 ;
+ RECT 1857.920000 2121.340000 1859.020000 2121.820000 ;
+ RECT 1853.790000 2121.340000 1854.790000 2121.820000 ;
+ RECT 1857.920000 2115.900000 1859.020000 2116.380000 ;
+ RECT 1853.790000 2115.900000 1854.790000 2116.380000 ;
+ RECT 1857.920000 2105.020000 1859.020000 2105.500000 ;
+ RECT 1853.790000 2105.020000 1854.790000 2105.500000 ;
+ RECT 1857.920000 2099.580000 1859.020000 2100.060000 ;
+ RECT 1853.790000 2099.580000 1854.790000 2100.060000 ;
+ RECT 1857.920000 2110.460000 1859.020000 2110.940000 ;
+ RECT 1853.790000 2110.460000 1854.790000 2110.940000 ;
+ RECT 1947.920000 2094.140000 1949.020000 2094.620000 ;
+ RECT 1947.920000 2088.700000 1949.020000 2089.180000 ;
+ RECT 1947.920000 2083.260000 1949.020000 2083.740000 ;
+ RECT 1947.920000 2077.820000 1949.020000 2078.300000 ;
+ RECT 1902.920000 2094.140000 1904.020000 2094.620000 ;
+ RECT 1902.920000 2088.700000 1904.020000 2089.180000 ;
+ RECT 1902.920000 2083.260000 1904.020000 2083.740000 ;
+ RECT 1902.920000 2077.820000 1904.020000 2078.300000 ;
+ RECT 1947.920000 2066.940000 1949.020000 2067.420000 ;
+ RECT 1947.920000 2050.620000 1949.020000 2051.100000 ;
+ RECT 1947.920000 2056.060000 1949.020000 2056.540000 ;
+ RECT 1947.920000 2061.500000 1949.020000 2061.980000 ;
+ RECT 1947.920000 2072.380000 1949.020000 2072.860000 ;
+ RECT 1902.920000 2050.620000 1904.020000 2051.100000 ;
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+ RECT 1902.920000 2061.500000 1904.020000 2061.980000 ;
+ RECT 1902.920000 2066.940000 1904.020000 2067.420000 ;
+ RECT 1902.920000 2072.380000 1904.020000 2072.860000 ;
+ RECT 1857.920000 2094.140000 1859.020000 2094.620000 ;
+ RECT 1853.790000 2094.140000 1854.790000 2094.620000 ;
+ RECT 1857.920000 2088.700000 1859.020000 2089.180000 ;
+ RECT 1853.790000 2088.700000 1854.790000 2089.180000 ;
+ RECT 1857.920000 2083.260000 1859.020000 2083.740000 ;
+ RECT 1853.790000 2083.260000 1854.790000 2083.740000 ;
+ RECT 1857.920000 2077.820000 1859.020000 2078.300000 ;
+ RECT 1853.790000 2077.820000 1854.790000 2078.300000 ;
+ RECT 1857.920000 2072.380000 1859.020000 2072.860000 ;
+ RECT 1857.920000 2066.940000 1859.020000 2067.420000 ;
+ RECT 1853.790000 2072.380000 1854.790000 2072.860000 ;
+ RECT 1853.790000 2066.940000 1854.790000 2067.420000 ;
+ RECT 1857.920000 2061.500000 1859.020000 2061.980000 ;
+ RECT 1853.790000 2061.500000 1854.790000 2061.980000 ;
+ RECT 1857.920000 2056.060000 1859.020000 2056.540000 ;
+ RECT 1853.790000 2056.060000 1854.790000 2056.540000 ;
+ RECT 1857.920000 2050.620000 1859.020000 2051.100000 ;
+ RECT 1853.790000 2050.620000 1854.790000 2051.100000 ;
+ RECT 2037.920000 2045.180000 2039.020000 2045.660000 ;
+ RECT 2037.920000 2039.740000 2039.020000 2040.220000 ;
+ RECT 2047.230000 2045.180000 2048.230000 2045.660000 ;
+ RECT 2047.230000 2039.740000 2048.230000 2040.220000 ;
+ RECT 2047.230000 2023.420000 2048.230000 2023.900000 ;
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+ RECT 2037.920000 2034.300000 2039.020000 2034.780000 ;
+ RECT 2037.920000 2028.860000 2039.020000 2029.340000 ;
+ RECT 2037.920000 2023.420000 2039.020000 2023.900000 ;
+ RECT 2037.920000 2012.540000 2039.020000 2013.020000 ;
+ RECT 2037.920000 2017.980000 2039.020000 2018.460000 ;
+ RECT 2047.230000 2017.980000 2048.230000 2018.460000 ;
+ RECT 2047.230000 2012.540000 2048.230000 2013.020000 ;
+ RECT 2047.230000 2001.660000 2048.230000 2002.140000 ;
+ RECT 2047.230000 2007.100000 2048.230000 2007.580000 ;
+ RECT 2037.920000 2001.660000 2039.020000 2002.140000 ;
+ RECT 2037.920000 2007.100000 2039.020000 2007.580000 ;
+ RECT 1992.920000 2045.180000 1994.020000 2045.660000 ;
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+ RECT 1992.920000 2028.860000 1994.020000 2029.340000 ;
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+ RECT 1992.920000 2001.660000 1994.020000 2002.140000 ;
+ RECT 1992.920000 2007.100000 1994.020000 2007.580000 ;
+ RECT 1992.920000 2012.540000 1994.020000 2013.020000 ;
+ RECT 1992.920000 2017.980000 1994.020000 2018.460000 ;
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+ RECT 2037.920000 1979.900000 2039.020000 1980.380000 ;
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+ RECT 2047.230000 1979.900000 2048.230000 1980.380000 ;
+ RECT 2047.230000 1974.460000 2048.230000 1974.940000 ;
+ RECT 2037.920000 1985.340000 2039.020000 1985.820000 ;
+ RECT 2047.230000 1985.340000 2048.230000 1985.820000 ;
+ RECT 2047.230000 1963.580000 2048.230000 1964.060000 ;
+ RECT 2047.230000 1969.020000 2048.230000 1969.500000 ;
+ RECT 2037.920000 1969.020000 2039.020000 1969.500000 ;
+ RECT 2037.920000 1963.580000 2039.020000 1964.060000 ;
+ RECT 2037.920000 1958.140000 2039.020000 1958.620000 ;
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+ RECT 2047.230000 1958.140000 2048.230000 1958.620000 ;
+ RECT 2047.230000 1952.700000 2048.230000 1953.180000 ;
+ RECT 1992.920000 1996.220000 1994.020000 1996.700000 ;
+ RECT 1992.920000 1990.780000 1994.020000 1991.260000 ;
+ RECT 1992.920000 1985.340000 1994.020000 1985.820000 ;
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+ RECT 1947.920000 2017.980000 1949.020000 2018.460000 ;
+ RECT 1947.920000 2012.540000 1949.020000 2013.020000 ;
+ RECT 1947.920000 2007.100000 1949.020000 2007.580000 ;
+ RECT 1947.920000 2001.660000 1949.020000 2002.140000 ;
+ RECT 1902.920000 2012.540000 1904.020000 2013.020000 ;
+ RECT 1902.920000 2007.100000 1904.020000 2007.580000 ;
+ RECT 1902.920000 2001.660000 1904.020000 2002.140000 ;
+ RECT 1902.920000 2017.980000 1904.020000 2018.460000 ;
+ RECT 1857.920000 2045.180000 1859.020000 2045.660000 ;
+ RECT 1853.790000 2045.180000 1854.790000 2045.660000 ;
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+ RECT 1853.790000 2039.740000 1854.790000 2040.220000 ;
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+ RECT 1853.790000 2034.300000 1854.790000 2034.780000 ;
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+ RECT 1853.790000 2028.860000 1854.790000 2029.340000 ;
+ RECT 1857.920000 2028.860000 1859.020000 2029.340000 ;
+ RECT 1857.920000 2017.980000 1859.020000 2018.460000 ;
+ RECT 1853.790000 2017.980000 1854.790000 2018.460000 ;
+ RECT 1857.920000 2012.540000 1859.020000 2013.020000 ;
+ RECT 1853.790000 2012.540000 1854.790000 2013.020000 ;
+ RECT 1857.920000 2007.100000 1859.020000 2007.580000 ;
+ RECT 1853.790000 2007.100000 1854.790000 2007.580000 ;
+ RECT 1857.920000 2001.660000 1859.020000 2002.140000 ;
+ RECT 1853.790000 2001.660000 1854.790000 2002.140000 ;
+ RECT 1947.920000 1996.220000 1949.020000 1996.700000 ;
+ RECT 1947.920000 1990.780000 1949.020000 1991.260000 ;
+ RECT 1947.920000 1985.340000 1949.020000 1985.820000 ;
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+ RECT 1902.920000 1996.220000 1904.020000 1996.700000 ;
+ RECT 1902.920000 1990.780000 1904.020000 1991.260000 ;
+ RECT 1902.920000 1985.340000 1904.020000 1985.820000 ;
+ RECT 1902.920000 1979.900000 1904.020000 1980.380000 ;
+ RECT 1902.920000 1974.460000 1904.020000 1974.940000 ;
+ RECT 1947.920000 1952.700000 1949.020000 1953.180000 ;
+ RECT 1947.920000 1958.140000 1949.020000 1958.620000 ;
+ RECT 1947.920000 1963.580000 1949.020000 1964.060000 ;
+ RECT 1947.920000 1969.020000 1949.020000 1969.500000 ;
+ RECT 1902.920000 1952.700000 1904.020000 1953.180000 ;
+ RECT 1902.920000 1958.140000 1904.020000 1958.620000 ;
+ RECT 1902.920000 1963.580000 1904.020000 1964.060000 ;
+ RECT 1902.920000 1969.020000 1904.020000 1969.500000 ;
+ RECT 1857.920000 1996.220000 1859.020000 1996.700000 ;
+ RECT 1853.790000 1996.220000 1854.790000 1996.700000 ;
+ RECT 1857.920000 1990.780000 1859.020000 1991.260000 ;
+ RECT 1853.790000 1990.780000 1854.790000 1991.260000 ;
+ RECT 1857.920000 1979.900000 1859.020000 1980.380000 ;
+ RECT 1853.790000 1979.900000 1854.790000 1980.380000 ;
+ RECT 1857.920000 1974.460000 1859.020000 1974.940000 ;
+ RECT 1853.790000 1974.460000 1854.790000 1974.940000 ;
+ RECT 1857.920000 1985.340000 1859.020000 1985.820000 ;
+ RECT 1853.790000 1985.340000 1854.790000 1985.820000 ;
+ RECT 1857.920000 1969.020000 1859.020000 1969.500000 ;
+ RECT 1853.790000 1969.020000 1854.790000 1969.500000 ;
+ RECT 1857.920000 1963.580000 1859.020000 1964.060000 ;
+ RECT 1853.790000 1963.580000 1854.790000 1964.060000 ;
+ RECT 1857.920000 1958.140000 1859.020000 1958.620000 ;
+ RECT 1857.920000 1952.700000 1859.020000 1953.180000 ;
+ RECT 1853.790000 1958.140000 1854.790000 1958.620000 ;
+ RECT 1853.790000 1952.700000 1854.790000 1953.180000 ;
+ RECT 1850.960000 2143.060000 2051.060000 2144.060000 ;
+ RECT 1850.960000 1950.690000 2051.060000 1951.690000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 1947.840000 1854.790000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 2147.100000 1854.790000 2148.100000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 1947.840000 2048.230000 1948.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 2147.100000 2048.230000 2148.100000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1950.690000 1851.960000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1950.690000 2051.060000 1951.690000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 2143.060000 1851.960000 2144.060000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 2143.060000 2051.060000 2144.060000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
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+ RECT 1992.920000 1750.430000 1994.020000 1943.800000 ;
+ RECT 2047.230000 1747.580000 2048.230000 1947.840000 ;
+ RECT 1947.920000 1750.430000 1949.020000 1943.800000 ;
+ RECT 1902.920000 1750.430000 1904.020000 1943.800000 ;
+ RECT 1857.920000 1750.430000 1859.020000 1943.800000 ;
+ RECT 1853.790000 1747.580000 1854.790000 1947.840000 ;
+ LAYER met3 ;
+ RECT 2037.920000 1937.400000 2039.020000 1937.880000 ;
+ RECT 2047.230000 1937.400000 2048.230000 1937.880000 ;
+ RECT 2047.230000 1926.520000 2048.230000 1927.000000 ;
+ RECT 2047.230000 1931.960000 2048.230000 1932.440000 ;
+ RECT 2037.920000 1931.960000 2039.020000 1932.440000 ;
+ RECT 2037.920000 1926.520000 2039.020000 1927.000000 ;
+ RECT 2037.920000 1921.080000 2039.020000 1921.560000 ;
+ RECT 2037.920000 1915.640000 2039.020000 1916.120000 ;
+ RECT 2047.230000 1921.080000 2048.230000 1921.560000 ;
+ RECT 2047.230000 1915.640000 2048.230000 1916.120000 ;
+ RECT 2037.920000 1899.320000 2039.020000 1899.800000 ;
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+ RECT 2037.920000 1910.200000 2039.020000 1910.680000 ;
+ RECT 2047.230000 1910.200000 2048.230000 1910.680000 ;
+ RECT 1992.920000 1937.400000 1994.020000 1937.880000 ;
+ RECT 1992.920000 1931.960000 1994.020000 1932.440000 ;
+ RECT 1992.920000 1926.520000 1994.020000 1927.000000 ;
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+ RECT 1992.920000 1904.760000 1994.020000 1905.240000 ;
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+ RECT 2037.920000 1893.880000 2039.020000 1894.360000 ;
+ RECT 2037.920000 1888.440000 2039.020000 1888.920000 ;
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+ RECT 2047.230000 1877.560000 2048.230000 1878.040000 ;
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+ RECT 2037.920000 1866.680000 2039.020000 1867.160000 ;
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+ RECT 2047.230000 1850.360000 2048.230000 1850.840000 ;
+ RECT 1992.920000 1893.880000 1994.020000 1894.360000 ;
+ RECT 1992.920000 1888.440000 1994.020000 1888.920000 ;
+ RECT 1992.920000 1883.000000 1994.020000 1883.480000 ;
+ RECT 1992.920000 1877.560000 1994.020000 1878.040000 ;
+ RECT 1992.920000 1866.680000 1994.020000 1867.160000 ;
+ RECT 1992.920000 1861.240000 1994.020000 1861.720000 ;
+ RECT 1992.920000 1855.800000 1994.020000 1856.280000 ;
+ RECT 1992.920000 1850.360000 1994.020000 1850.840000 ;
+ RECT 1992.920000 1872.120000 1994.020000 1872.600000 ;
+ RECT 1947.920000 1937.400000 1949.020000 1937.880000 ;
+ RECT 1947.920000 1931.960000 1949.020000 1932.440000 ;
+ RECT 1947.920000 1926.520000 1949.020000 1927.000000 ;
+ RECT 1902.920000 1937.400000 1904.020000 1937.880000 ;
+ RECT 1902.920000 1931.960000 1904.020000 1932.440000 ;
+ RECT 1902.920000 1926.520000 1904.020000 1927.000000 ;
+ RECT 1947.920000 1910.200000 1949.020000 1910.680000 ;
+ RECT 1947.920000 1904.760000 1949.020000 1905.240000 ;
+ RECT 1947.920000 1899.320000 1949.020000 1899.800000 ;
+ RECT 1947.920000 1915.640000 1949.020000 1916.120000 ;
+ RECT 1947.920000 1921.080000 1949.020000 1921.560000 ;
+ RECT 1902.920000 1921.080000 1904.020000 1921.560000 ;
+ RECT 1902.920000 1910.200000 1904.020000 1910.680000 ;
+ RECT 1902.920000 1904.760000 1904.020000 1905.240000 ;
+ RECT 1902.920000 1899.320000 1904.020000 1899.800000 ;
+ RECT 1902.920000 1915.640000 1904.020000 1916.120000 ;
+ RECT 1857.920000 1937.400000 1859.020000 1937.880000 ;
+ RECT 1853.790000 1937.400000 1854.790000 1937.880000 ;
+ RECT 1853.790000 1931.960000 1854.790000 1932.440000 ;
+ RECT 1857.920000 1931.960000 1859.020000 1932.440000 ;
+ RECT 1857.920000 1926.520000 1859.020000 1927.000000 ;
+ RECT 1853.790000 1926.520000 1854.790000 1927.000000 ;
+ RECT 1857.920000 1921.080000 1859.020000 1921.560000 ;
+ RECT 1853.790000 1921.080000 1854.790000 1921.560000 ;
+ RECT 1857.920000 1915.640000 1859.020000 1916.120000 ;
+ RECT 1853.790000 1915.640000 1854.790000 1916.120000 ;
+ RECT 1857.920000 1904.760000 1859.020000 1905.240000 ;
+ RECT 1853.790000 1904.760000 1854.790000 1905.240000 ;
+ RECT 1857.920000 1899.320000 1859.020000 1899.800000 ;
+ RECT 1853.790000 1899.320000 1854.790000 1899.800000 ;
+ RECT 1857.920000 1910.200000 1859.020000 1910.680000 ;
+ RECT 1853.790000 1910.200000 1854.790000 1910.680000 ;
+ RECT 1947.920000 1893.880000 1949.020000 1894.360000 ;
+ RECT 1947.920000 1888.440000 1949.020000 1888.920000 ;
+ RECT 1947.920000 1883.000000 1949.020000 1883.480000 ;
+ RECT 1947.920000 1877.560000 1949.020000 1878.040000 ;
+ RECT 1902.920000 1893.880000 1904.020000 1894.360000 ;
+ RECT 1902.920000 1888.440000 1904.020000 1888.920000 ;
+ RECT 1902.920000 1883.000000 1904.020000 1883.480000 ;
+ RECT 1902.920000 1877.560000 1904.020000 1878.040000 ;
+ RECT 1947.920000 1866.680000 1949.020000 1867.160000 ;
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+ RECT 1947.920000 1861.240000 1949.020000 1861.720000 ;
+ RECT 1947.920000 1872.120000 1949.020000 1872.600000 ;
+ RECT 1902.920000 1850.360000 1904.020000 1850.840000 ;
+ RECT 1902.920000 1855.800000 1904.020000 1856.280000 ;
+ RECT 1902.920000 1861.240000 1904.020000 1861.720000 ;
+ RECT 1902.920000 1866.680000 1904.020000 1867.160000 ;
+ RECT 1902.920000 1872.120000 1904.020000 1872.600000 ;
+ RECT 1857.920000 1893.880000 1859.020000 1894.360000 ;
+ RECT 1853.790000 1893.880000 1854.790000 1894.360000 ;
+ RECT 1857.920000 1888.440000 1859.020000 1888.920000 ;
+ RECT 1853.790000 1888.440000 1854.790000 1888.920000 ;
+ RECT 1857.920000 1883.000000 1859.020000 1883.480000 ;
+ RECT 1853.790000 1883.000000 1854.790000 1883.480000 ;
+ RECT 1857.920000 1877.560000 1859.020000 1878.040000 ;
+ RECT 1853.790000 1877.560000 1854.790000 1878.040000 ;
+ RECT 1857.920000 1872.120000 1859.020000 1872.600000 ;
+ RECT 1857.920000 1866.680000 1859.020000 1867.160000 ;
+ RECT 1853.790000 1872.120000 1854.790000 1872.600000 ;
+ RECT 1853.790000 1866.680000 1854.790000 1867.160000 ;
+ RECT 1857.920000 1861.240000 1859.020000 1861.720000 ;
+ RECT 1853.790000 1861.240000 1854.790000 1861.720000 ;
+ RECT 1857.920000 1855.800000 1859.020000 1856.280000 ;
+ RECT 1853.790000 1855.800000 1854.790000 1856.280000 ;
+ RECT 1857.920000 1850.360000 1859.020000 1850.840000 ;
+ RECT 1853.790000 1850.360000 1854.790000 1850.840000 ;
+ RECT 2037.920000 1844.920000 2039.020000 1845.400000 ;
+ RECT 2037.920000 1839.480000 2039.020000 1839.960000 ;
+ RECT 2047.230000 1844.920000 2048.230000 1845.400000 ;
+ RECT 2047.230000 1839.480000 2048.230000 1839.960000 ;
+ RECT 2047.230000 1823.160000 2048.230000 1823.640000 ;
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+ RECT 2037.920000 1834.040000 2039.020000 1834.520000 ;
+ RECT 2037.920000 1828.600000 2039.020000 1829.080000 ;
+ RECT 2037.920000 1823.160000 2039.020000 1823.640000 ;
+ RECT 2037.920000 1812.280000 2039.020000 1812.760000 ;
+ RECT 2037.920000 1817.720000 2039.020000 1818.200000 ;
+ RECT 2047.230000 1817.720000 2048.230000 1818.200000 ;
+ RECT 2047.230000 1812.280000 2048.230000 1812.760000 ;
+ RECT 2047.230000 1801.400000 2048.230000 1801.880000 ;
+ RECT 2047.230000 1806.840000 2048.230000 1807.320000 ;
+ RECT 2037.920000 1801.400000 2039.020000 1801.880000 ;
+ RECT 2037.920000 1806.840000 2039.020000 1807.320000 ;
+ RECT 1992.920000 1844.920000 1994.020000 1845.400000 ;
+ RECT 1992.920000 1839.480000 1994.020000 1839.960000 ;
+ RECT 1992.920000 1834.040000 1994.020000 1834.520000 ;
+ RECT 1992.920000 1828.600000 1994.020000 1829.080000 ;
+ RECT 1992.920000 1823.160000 1994.020000 1823.640000 ;
+ RECT 1992.920000 1801.400000 1994.020000 1801.880000 ;
+ RECT 1992.920000 1806.840000 1994.020000 1807.320000 ;
+ RECT 1992.920000 1812.280000 1994.020000 1812.760000 ;
+ RECT 1992.920000 1817.720000 1994.020000 1818.200000 ;
+ RECT 2037.920000 1795.960000 2039.020000 1796.440000 ;
+ RECT 2037.920000 1790.520000 2039.020000 1791.000000 ;
+ RECT 2047.230000 1795.960000 2048.230000 1796.440000 ;
+ RECT 2047.230000 1790.520000 2048.230000 1791.000000 ;
+ RECT 2037.920000 1779.640000 2039.020000 1780.120000 ;
+ RECT 2037.920000 1774.200000 2039.020000 1774.680000 ;
+ RECT 2047.230000 1779.640000 2048.230000 1780.120000 ;
+ RECT 2047.230000 1774.200000 2048.230000 1774.680000 ;
+ RECT 2037.920000 1785.080000 2039.020000 1785.560000 ;
+ RECT 2047.230000 1785.080000 2048.230000 1785.560000 ;
+ RECT 2047.230000 1763.320000 2048.230000 1763.800000 ;
+ RECT 2047.230000 1768.760000 2048.230000 1769.240000 ;
+ RECT 2037.920000 1768.760000 2039.020000 1769.240000 ;
+ RECT 2037.920000 1763.320000 2039.020000 1763.800000 ;
+ RECT 2037.920000 1757.880000 2039.020000 1758.360000 ;
+ RECT 2037.920000 1752.440000 2039.020000 1752.920000 ;
+ RECT 2047.230000 1757.880000 2048.230000 1758.360000 ;
+ RECT 2047.230000 1752.440000 2048.230000 1752.920000 ;
+ RECT 1992.920000 1795.960000 1994.020000 1796.440000 ;
+ RECT 1992.920000 1790.520000 1994.020000 1791.000000 ;
+ RECT 1992.920000 1785.080000 1994.020000 1785.560000 ;
+ RECT 1992.920000 1779.640000 1994.020000 1780.120000 ;
+ RECT 1992.920000 1774.200000 1994.020000 1774.680000 ;
+ RECT 1992.920000 1768.760000 1994.020000 1769.240000 ;
+ RECT 1992.920000 1763.320000 1994.020000 1763.800000 ;
+ RECT 1992.920000 1757.880000 1994.020000 1758.360000 ;
+ RECT 1992.920000 1752.440000 1994.020000 1752.920000 ;
+ RECT 1947.920000 1844.920000 1949.020000 1845.400000 ;
+ RECT 1947.920000 1839.480000 1949.020000 1839.960000 ;
+ RECT 1947.920000 1834.040000 1949.020000 1834.520000 ;
+ RECT 1947.920000 1828.600000 1949.020000 1829.080000 ;
+ RECT 1947.920000 1823.160000 1949.020000 1823.640000 ;
+ RECT 1902.920000 1844.920000 1904.020000 1845.400000 ;
+ RECT 1902.920000 1839.480000 1904.020000 1839.960000 ;
+ RECT 1902.920000 1834.040000 1904.020000 1834.520000 ;
+ RECT 1902.920000 1828.600000 1904.020000 1829.080000 ;
+ RECT 1902.920000 1823.160000 1904.020000 1823.640000 ;
+ RECT 1947.920000 1817.720000 1949.020000 1818.200000 ;
+ RECT 1947.920000 1812.280000 1949.020000 1812.760000 ;
+ RECT 1947.920000 1806.840000 1949.020000 1807.320000 ;
+ RECT 1947.920000 1801.400000 1949.020000 1801.880000 ;
+ RECT 1902.920000 1812.280000 1904.020000 1812.760000 ;
+ RECT 1902.920000 1806.840000 1904.020000 1807.320000 ;
+ RECT 1902.920000 1801.400000 1904.020000 1801.880000 ;
+ RECT 1902.920000 1817.720000 1904.020000 1818.200000 ;
+ RECT 1857.920000 1844.920000 1859.020000 1845.400000 ;
+ RECT 1853.790000 1844.920000 1854.790000 1845.400000 ;
+ RECT 1857.920000 1839.480000 1859.020000 1839.960000 ;
+ RECT 1853.790000 1839.480000 1854.790000 1839.960000 ;
+ RECT 1857.920000 1834.040000 1859.020000 1834.520000 ;
+ RECT 1853.790000 1834.040000 1854.790000 1834.520000 ;
+ RECT 1857.920000 1823.160000 1859.020000 1823.640000 ;
+ RECT 1853.790000 1823.160000 1854.790000 1823.640000 ;
+ RECT 1853.790000 1828.600000 1854.790000 1829.080000 ;
+ RECT 1857.920000 1828.600000 1859.020000 1829.080000 ;
+ RECT 1857.920000 1817.720000 1859.020000 1818.200000 ;
+ RECT 1853.790000 1817.720000 1854.790000 1818.200000 ;
+ RECT 1857.920000 1812.280000 1859.020000 1812.760000 ;
+ RECT 1853.790000 1812.280000 1854.790000 1812.760000 ;
+ RECT 1857.920000 1806.840000 1859.020000 1807.320000 ;
+ RECT 1853.790000 1806.840000 1854.790000 1807.320000 ;
+ RECT 1857.920000 1801.400000 1859.020000 1801.880000 ;
+ RECT 1853.790000 1801.400000 1854.790000 1801.880000 ;
+ RECT 1947.920000 1795.960000 1949.020000 1796.440000 ;
+ RECT 1947.920000 1790.520000 1949.020000 1791.000000 ;
+ RECT 1947.920000 1785.080000 1949.020000 1785.560000 ;
+ RECT 1947.920000 1779.640000 1949.020000 1780.120000 ;
+ RECT 1947.920000 1774.200000 1949.020000 1774.680000 ;
+ RECT 1902.920000 1795.960000 1904.020000 1796.440000 ;
+ RECT 1902.920000 1790.520000 1904.020000 1791.000000 ;
+ RECT 1902.920000 1785.080000 1904.020000 1785.560000 ;
+ RECT 1902.920000 1779.640000 1904.020000 1780.120000 ;
+ RECT 1902.920000 1774.200000 1904.020000 1774.680000 ;
+ RECT 1947.920000 1752.440000 1949.020000 1752.920000 ;
+ RECT 1947.920000 1757.880000 1949.020000 1758.360000 ;
+ RECT 1947.920000 1763.320000 1949.020000 1763.800000 ;
+ RECT 1947.920000 1768.760000 1949.020000 1769.240000 ;
+ RECT 1902.920000 1752.440000 1904.020000 1752.920000 ;
+ RECT 1902.920000 1757.880000 1904.020000 1758.360000 ;
+ RECT 1902.920000 1763.320000 1904.020000 1763.800000 ;
+ RECT 1902.920000 1768.760000 1904.020000 1769.240000 ;
+ RECT 1857.920000 1795.960000 1859.020000 1796.440000 ;
+ RECT 1853.790000 1795.960000 1854.790000 1796.440000 ;
+ RECT 1857.920000 1790.520000 1859.020000 1791.000000 ;
+ RECT 1853.790000 1790.520000 1854.790000 1791.000000 ;
+ RECT 1857.920000 1779.640000 1859.020000 1780.120000 ;
+ RECT 1853.790000 1779.640000 1854.790000 1780.120000 ;
+ RECT 1857.920000 1774.200000 1859.020000 1774.680000 ;
+ RECT 1853.790000 1774.200000 1854.790000 1774.680000 ;
+ RECT 1857.920000 1785.080000 1859.020000 1785.560000 ;
+ RECT 1853.790000 1785.080000 1854.790000 1785.560000 ;
+ RECT 1857.920000 1768.760000 1859.020000 1769.240000 ;
+ RECT 1853.790000 1768.760000 1854.790000 1769.240000 ;
+ RECT 1857.920000 1763.320000 1859.020000 1763.800000 ;
+ RECT 1853.790000 1763.320000 1854.790000 1763.800000 ;
+ RECT 1857.920000 1757.880000 1859.020000 1758.360000 ;
+ RECT 1857.920000 1752.440000 1859.020000 1752.920000 ;
+ RECT 1853.790000 1757.880000 1854.790000 1758.360000 ;
+ RECT 1853.790000 1752.440000 1854.790000 1752.920000 ;
+ RECT 1850.960000 1942.800000 2051.060000 1943.800000 ;
+ RECT 1850.960000 1750.430000 2051.060000 1751.430000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 1747.580000 1854.790000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 1946.840000 1854.790000 1947.840000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 1747.580000 2048.230000 1748.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 1946.840000 2048.230000 1947.840000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1750.430000 1851.960000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1750.430000 2051.060000 1751.430000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1942.800000 1851.960000 1943.800000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1942.800000 2051.060000 1943.800000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+
+# P/G pin shape extracted from block 'LUT4AB'
+ PORT
+ LAYER met4 ;
+ RECT 2037.920000 1550.170000 2039.020000 1743.540000 ;
+ RECT 1992.920000 1550.170000 1994.020000 1743.540000 ;
+ RECT 2047.230000 1547.320000 2048.230000 1747.580000 ;
+ RECT 1947.920000 1550.170000 1949.020000 1743.540000 ;
+ RECT 1902.920000 1550.170000 1904.020000 1743.540000 ;
+ RECT 1857.920000 1550.170000 1859.020000 1743.540000 ;
+ RECT 1853.790000 1547.320000 1854.790000 1747.580000 ;
+ LAYER met3 ;
+ RECT 2037.920000 1737.140000 2039.020000 1737.620000 ;
+ RECT 2047.230000 1737.140000 2048.230000 1737.620000 ;
+ RECT 2047.230000 1726.260000 2048.230000 1726.740000 ;
+ RECT 2047.230000 1731.700000 2048.230000 1732.180000 ;
+ RECT 2037.920000 1731.700000 2039.020000 1732.180000 ;
+ RECT 2037.920000 1726.260000 2039.020000 1726.740000 ;
+ RECT 2037.920000 1720.820000 2039.020000 1721.300000 ;
+ RECT 2037.920000 1715.380000 2039.020000 1715.860000 ;
+ RECT 2047.230000 1720.820000 2048.230000 1721.300000 ;
+ RECT 2047.230000 1715.380000 2048.230000 1715.860000 ;
+ RECT 2037.920000 1699.060000 2039.020000 1699.540000 ;
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+ RECT 2047.230000 1704.500000 2048.230000 1704.980000 ;
+ RECT 2047.230000 1699.060000 2048.230000 1699.540000 ;
+ RECT 2037.920000 1709.940000 2039.020000 1710.420000 ;
+ RECT 2047.230000 1709.940000 2048.230000 1710.420000 ;
+ RECT 1992.920000 1737.140000 1994.020000 1737.620000 ;
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+ RECT 1992.920000 1726.260000 1994.020000 1726.740000 ;
+ RECT 1992.920000 1720.820000 1994.020000 1721.300000 ;
+ RECT 1992.920000 1699.060000 1994.020000 1699.540000 ;
+ RECT 1992.920000 1704.500000 1994.020000 1704.980000 ;
+ RECT 1992.920000 1709.940000 1994.020000 1710.420000 ;
+ RECT 1992.920000 1715.380000 1994.020000 1715.860000 ;
+ RECT 2047.230000 1688.180000 2048.230000 1688.660000 ;
+ RECT 2047.230000 1693.620000 2048.230000 1694.100000 ;
+ RECT 2037.920000 1693.620000 2039.020000 1694.100000 ;
+ RECT 2037.920000 1688.180000 2039.020000 1688.660000 ;
+ RECT 2037.920000 1682.740000 2039.020000 1683.220000 ;
+ RECT 2037.920000 1677.300000 2039.020000 1677.780000 ;
+ RECT 2047.230000 1682.740000 2048.230000 1683.220000 ;
+ RECT 2047.230000 1677.300000 2048.230000 1677.780000 ;
+ RECT 2047.230000 1660.980000 2048.230000 1661.460000 ;
+ RECT 2047.230000 1666.420000 2048.230000 1666.900000 ;
+ RECT 2047.230000 1671.860000 2048.230000 1672.340000 ;
+ RECT 2037.920000 1666.420000 2039.020000 1666.900000 ;
+ RECT 2037.920000 1660.980000 2039.020000 1661.460000 ;
+ RECT 2037.920000 1671.860000 2039.020000 1672.340000 ;
+ RECT 2037.920000 1655.540000 2039.020000 1656.020000 ;
+ RECT 2037.920000 1650.100000 2039.020000 1650.580000 ;
+ RECT 2047.230000 1655.540000 2048.230000 1656.020000 ;
+ RECT 2047.230000 1650.100000 2048.230000 1650.580000 ;
+ RECT 1992.920000 1693.620000 1994.020000 1694.100000 ;
+ RECT 1992.920000 1688.180000 1994.020000 1688.660000 ;
+ RECT 1992.920000 1682.740000 1994.020000 1683.220000 ;
+ RECT 1992.920000 1677.300000 1994.020000 1677.780000 ;
+ RECT 1992.920000 1666.420000 1994.020000 1666.900000 ;
+ RECT 1992.920000 1660.980000 1994.020000 1661.460000 ;
+ RECT 1992.920000 1655.540000 1994.020000 1656.020000 ;
+ RECT 1992.920000 1650.100000 1994.020000 1650.580000 ;
+ RECT 1992.920000 1671.860000 1994.020000 1672.340000 ;
+ RECT 1947.920000 1737.140000 1949.020000 1737.620000 ;
+ RECT 1947.920000 1731.700000 1949.020000 1732.180000 ;
+ RECT 1947.920000 1726.260000 1949.020000 1726.740000 ;
+ RECT 1902.920000 1737.140000 1904.020000 1737.620000 ;
+ RECT 1902.920000 1731.700000 1904.020000 1732.180000 ;
+ RECT 1902.920000 1726.260000 1904.020000 1726.740000 ;
+ RECT 1947.920000 1709.940000 1949.020000 1710.420000 ;
+ RECT 1947.920000 1704.500000 1949.020000 1704.980000 ;
+ RECT 1947.920000 1699.060000 1949.020000 1699.540000 ;
+ RECT 1947.920000 1715.380000 1949.020000 1715.860000 ;
+ RECT 1947.920000 1720.820000 1949.020000 1721.300000 ;
+ RECT 1902.920000 1720.820000 1904.020000 1721.300000 ;
+ RECT 1902.920000 1709.940000 1904.020000 1710.420000 ;
+ RECT 1902.920000 1704.500000 1904.020000 1704.980000 ;
+ RECT 1902.920000 1699.060000 1904.020000 1699.540000 ;
+ RECT 1902.920000 1715.380000 1904.020000 1715.860000 ;
+ RECT 1857.920000 1737.140000 1859.020000 1737.620000 ;
+ RECT 1853.790000 1737.140000 1854.790000 1737.620000 ;
+ RECT 1853.790000 1731.700000 1854.790000 1732.180000 ;
+ RECT 1857.920000 1731.700000 1859.020000 1732.180000 ;
+ RECT 1857.920000 1726.260000 1859.020000 1726.740000 ;
+ RECT 1853.790000 1726.260000 1854.790000 1726.740000 ;
+ RECT 1857.920000 1720.820000 1859.020000 1721.300000 ;
+ RECT 1853.790000 1720.820000 1854.790000 1721.300000 ;
+ RECT 1857.920000 1715.380000 1859.020000 1715.860000 ;
+ RECT 1853.790000 1715.380000 1854.790000 1715.860000 ;
+ RECT 1857.920000 1704.500000 1859.020000 1704.980000 ;
+ RECT 1853.790000 1704.500000 1854.790000 1704.980000 ;
+ RECT 1857.920000 1699.060000 1859.020000 1699.540000 ;
+ RECT 1853.790000 1699.060000 1854.790000 1699.540000 ;
+ RECT 1857.920000 1709.940000 1859.020000 1710.420000 ;
+ RECT 1853.790000 1709.940000 1854.790000 1710.420000 ;
+ RECT 1947.920000 1693.620000 1949.020000 1694.100000 ;
+ RECT 1947.920000 1688.180000 1949.020000 1688.660000 ;
+ RECT 1947.920000 1682.740000 1949.020000 1683.220000 ;
+ RECT 1947.920000 1677.300000 1949.020000 1677.780000 ;
+ RECT 1902.920000 1693.620000 1904.020000 1694.100000 ;
+ RECT 1902.920000 1688.180000 1904.020000 1688.660000 ;
+ RECT 1902.920000 1682.740000 1904.020000 1683.220000 ;
+ RECT 1902.920000 1677.300000 1904.020000 1677.780000 ;
+ RECT 1947.920000 1666.420000 1949.020000 1666.900000 ;
+ RECT 1947.920000 1650.100000 1949.020000 1650.580000 ;
+ RECT 1947.920000 1655.540000 1949.020000 1656.020000 ;
+ RECT 1947.920000 1660.980000 1949.020000 1661.460000 ;
+ RECT 1947.920000 1671.860000 1949.020000 1672.340000 ;
+ RECT 1902.920000 1650.100000 1904.020000 1650.580000 ;
+ RECT 1902.920000 1655.540000 1904.020000 1656.020000 ;
+ RECT 1902.920000 1660.980000 1904.020000 1661.460000 ;
+ RECT 1902.920000 1666.420000 1904.020000 1666.900000 ;
+ RECT 1902.920000 1671.860000 1904.020000 1672.340000 ;
+ RECT 1857.920000 1693.620000 1859.020000 1694.100000 ;
+ RECT 1853.790000 1693.620000 1854.790000 1694.100000 ;
+ RECT 1857.920000 1688.180000 1859.020000 1688.660000 ;
+ RECT 1853.790000 1688.180000 1854.790000 1688.660000 ;
+ RECT 1857.920000 1682.740000 1859.020000 1683.220000 ;
+ RECT 1853.790000 1682.740000 1854.790000 1683.220000 ;
+ RECT 1857.920000 1677.300000 1859.020000 1677.780000 ;
+ RECT 1853.790000 1677.300000 1854.790000 1677.780000 ;
+ RECT 1857.920000 1671.860000 1859.020000 1672.340000 ;
+ RECT 1857.920000 1666.420000 1859.020000 1666.900000 ;
+ RECT 1853.790000 1671.860000 1854.790000 1672.340000 ;
+ RECT 1853.790000 1666.420000 1854.790000 1666.900000 ;
+ RECT 1857.920000 1660.980000 1859.020000 1661.460000 ;
+ RECT 1853.790000 1660.980000 1854.790000 1661.460000 ;
+ RECT 1857.920000 1655.540000 1859.020000 1656.020000 ;
+ RECT 1853.790000 1655.540000 1854.790000 1656.020000 ;
+ RECT 1857.920000 1650.100000 1859.020000 1650.580000 ;
+ RECT 1853.790000 1650.100000 1854.790000 1650.580000 ;
+ RECT 2037.920000 1644.660000 2039.020000 1645.140000 ;
+ RECT 2037.920000 1639.220000 2039.020000 1639.700000 ;
+ RECT 2047.230000 1644.660000 2048.230000 1645.140000 ;
+ RECT 2047.230000 1639.220000 2048.230000 1639.700000 ;
+ RECT 2047.230000 1622.900000 2048.230000 1623.380000 ;
+ RECT 2047.230000 1628.340000 2048.230000 1628.820000 ;
+ RECT 2047.230000 1633.780000 2048.230000 1634.260000 ;
+ RECT 2037.920000 1633.780000 2039.020000 1634.260000 ;
+ RECT 2037.920000 1628.340000 2039.020000 1628.820000 ;
+ RECT 2037.920000 1622.900000 2039.020000 1623.380000 ;
+ RECT 2037.920000 1612.020000 2039.020000 1612.500000 ;
+ RECT 2037.920000 1617.460000 2039.020000 1617.940000 ;
+ RECT 2047.230000 1617.460000 2048.230000 1617.940000 ;
+ RECT 2047.230000 1612.020000 2048.230000 1612.500000 ;
+ RECT 2047.230000 1601.140000 2048.230000 1601.620000 ;
+ RECT 2047.230000 1606.580000 2048.230000 1607.060000 ;
+ RECT 2037.920000 1601.140000 2039.020000 1601.620000 ;
+ RECT 2037.920000 1606.580000 2039.020000 1607.060000 ;
+ RECT 1992.920000 1644.660000 1994.020000 1645.140000 ;
+ RECT 1992.920000 1639.220000 1994.020000 1639.700000 ;
+ RECT 1992.920000 1633.780000 1994.020000 1634.260000 ;
+ RECT 1992.920000 1628.340000 1994.020000 1628.820000 ;
+ RECT 1992.920000 1622.900000 1994.020000 1623.380000 ;
+ RECT 1992.920000 1601.140000 1994.020000 1601.620000 ;
+ RECT 1992.920000 1606.580000 1994.020000 1607.060000 ;
+ RECT 1992.920000 1612.020000 1994.020000 1612.500000 ;
+ RECT 1992.920000 1617.460000 1994.020000 1617.940000 ;
+ RECT 2037.920000 1595.700000 2039.020000 1596.180000 ;
+ RECT 2037.920000 1590.260000 2039.020000 1590.740000 ;
+ RECT 2047.230000 1595.700000 2048.230000 1596.180000 ;
+ RECT 2047.230000 1590.260000 2048.230000 1590.740000 ;
+ RECT 2037.920000 1579.380000 2039.020000 1579.860000 ;
+ RECT 2037.920000 1573.940000 2039.020000 1574.420000 ;
+ RECT 2047.230000 1579.380000 2048.230000 1579.860000 ;
+ RECT 2047.230000 1573.940000 2048.230000 1574.420000 ;
+ RECT 2037.920000 1584.820000 2039.020000 1585.300000 ;
+ RECT 2047.230000 1584.820000 2048.230000 1585.300000 ;
+ RECT 2047.230000 1563.060000 2048.230000 1563.540000 ;
+ RECT 2047.230000 1568.500000 2048.230000 1568.980000 ;
+ RECT 2037.920000 1568.500000 2039.020000 1568.980000 ;
+ RECT 2037.920000 1563.060000 2039.020000 1563.540000 ;
+ RECT 2037.920000 1557.620000 2039.020000 1558.100000 ;
+ RECT 2037.920000 1552.180000 2039.020000 1552.660000 ;
+ RECT 2047.230000 1557.620000 2048.230000 1558.100000 ;
+ RECT 2047.230000 1552.180000 2048.230000 1552.660000 ;
+ RECT 1992.920000 1595.700000 1994.020000 1596.180000 ;
+ RECT 1992.920000 1590.260000 1994.020000 1590.740000 ;
+ RECT 1992.920000 1584.820000 1994.020000 1585.300000 ;
+ RECT 1992.920000 1579.380000 1994.020000 1579.860000 ;
+ RECT 1992.920000 1573.940000 1994.020000 1574.420000 ;
+ RECT 1992.920000 1568.500000 1994.020000 1568.980000 ;
+ RECT 1992.920000 1563.060000 1994.020000 1563.540000 ;
+ RECT 1992.920000 1557.620000 1994.020000 1558.100000 ;
+ RECT 1992.920000 1552.180000 1994.020000 1552.660000 ;
+ RECT 1947.920000 1644.660000 1949.020000 1645.140000 ;
+ RECT 1947.920000 1639.220000 1949.020000 1639.700000 ;
+ RECT 1947.920000 1633.780000 1949.020000 1634.260000 ;
+ RECT 1947.920000 1628.340000 1949.020000 1628.820000 ;
+ RECT 1947.920000 1622.900000 1949.020000 1623.380000 ;
+ RECT 1902.920000 1644.660000 1904.020000 1645.140000 ;
+ RECT 1902.920000 1639.220000 1904.020000 1639.700000 ;
+ RECT 1902.920000 1633.780000 1904.020000 1634.260000 ;
+ RECT 1902.920000 1628.340000 1904.020000 1628.820000 ;
+ RECT 1902.920000 1622.900000 1904.020000 1623.380000 ;
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+ END
+ PORT
+ LAYER met4 ;
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+ END
+ PORT
+ LAYER met4 ;
+ RECT 1853.790000 1746.580000 1854.790000 1747.580000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 1547.320000 2048.230000 1548.320000 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 2047.230000 1746.580000 2048.230000 1747.580000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1550.170000 1851.960000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1550.170000 2051.060000 1551.170000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 1850.960000 1742.540000 1851.960000 1743.540000 ;
+ END
+ PORT
+ LAYER met3 ;
+ RECT 2050.060000 1742.540000 2051.060000 1743.540000 ;
+ END
+# end of P/G pin shape extracted from block 'LUT4AB'
+
+ END vccd1
+ OBS
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+ RECT 2696.380000 3384.150000 2716.990000 3387.550000 ;
+ RECT 2194.930000 3384.150000 2694.040000 3434.080000 ;
+ RECT 2055.190000 3379.120000 2156.870000 3434.080000 ;
+ RECT 2050.130000 3379.120000 2051.990000 3438.080000 ;
+ RECT 1855.090000 3379.120000 2046.930000 3434.080000 ;
+ RECT 1850.030000 3379.120000 1851.890000 3438.080000 ;
+ RECT 1654.990000 3379.120000 1846.830000 3434.080000 ;
+ RECT 1650.590000 3379.120000 1651.790000 3438.080000 ;
+ RECT 1449.890000 3379.120000 1641.730000 3434.080000 ;
+ RECT 1445.660000 3379.120000 1446.690000 3434.080000 ;
+ RECT 1244.790000 3379.120000 1436.630000 3434.080000 ;
+ RECT 1239.730000 3379.120000 1241.590000 3438.080000 ;
+ RECT 1044.690000 3379.120000 1236.530000 3434.080000 ;
+ RECT 1039.630000 3379.120000 1041.490000 3438.080000 ;
+ RECT 844.590000 3379.120000 1036.430000 3434.080000 ;
+ RECT 839.530000 3379.120000 841.390000 3438.080000 ;
+ RECT 644.490000 3379.120000 836.330000 3434.080000 ;
+ RECT 639.430000 3379.120000 641.290000 3438.080000 ;
+ RECT 444.390000 3379.120000 636.230000 3434.080000 ;
+ RECT 439.330000 3379.120000 441.190000 3438.080000 ;
+ RECT 244.290000 3379.120000 436.130000 3434.080000 ;
+ RECT 1243.490000 3376.860000 1436.630000 3379.120000 ;
+ RECT 1238.430000 3376.860000 1241.890000 3379.120000 ;
+ RECT 1442.670000 3375.260000 1444.060000 3434.080000 ;
+ RECT 1439.830000 3375.260000 1441.070000 3434.080000 ;
+ RECT 838.230000 3375.260000 841.390000 3379.120000 ;
+ RECT 644.490000 3375.260000 836.630000 3379.120000 ;
+ RECT 2160.070000 3373.260000 2184.900000 3434.080000 ;
+ RECT 2050.130000 3373.260000 2156.870000 3379.120000 ;
+ RECT 1850.030000 3373.260000 2046.930000 3379.120000 ;
+ RECT 1644.930000 3373.260000 1648.990000 3438.080000 ;
+ RECT 1439.830000 3373.260000 1444.060000 3375.260000 ;
+ RECT 1038.330000 3373.260000 1041.490000 3379.120000 ;
+ RECT 644.490000 3373.260000 841.390000 3375.260000 ;
+ RECT 444.390000 3373.260000 641.290000 3379.120000 ;
+ RECT 244.290000 3373.260000 441.190000 3379.120000 ;
+ RECT 239.230000 3373.260000 241.090000 3438.080000 ;
+ RECT 2158.470000 3370.540000 2184.900000 3373.260000 ;
+ RECT 2050.100000 3370.540000 2156.870000 3373.260000 ;
+ RECT 1850.000000 3370.540000 2046.930000 3373.260000 ;
+ RECT 1650.590000 3370.540000 1846.830000 3379.120000 ;
+ RECT 1643.330000 3370.540000 1648.990000 3373.260000 ;
+ RECT 1445.660000 3370.540000 1641.730000 3379.120000 ;
+ RECT 1438.230000 3370.540000 1444.060000 3373.260000 ;
+ RECT 1238.430000 3370.540000 1436.630000 3376.860000 ;
+ RECT 1044.690000 3370.540000 1236.830000 3379.120000 ;
+ RECT 1038.330000 3370.540000 1043.090000 3373.260000 ;
+ RECT 844.590000 3370.540000 1036.730000 3379.120000 ;
+ RECT 644.490000 3370.540000 842.990000 3373.260000 ;
+ RECT 444.390000 3370.540000 641.590000 3373.260000 ;
+ RECT 244.290000 3370.540000 442.790000 3373.260000 ;
+ RECT 239.230000 3370.540000 242.690000 3373.260000 ;
+ RECT 1850.000000 3352.210000 2047.120000 3370.540000 ;
+ RECT 1650.590000 3352.210000 1847.020000 3370.540000 ;
+ RECT 1445.660000 3352.210000 1648.990000 3370.540000 ;
+ RECT 1238.430000 3352.210000 1444.060000 3370.540000 ;
+ RECT 1038.330000 3352.210000 1236.830000 3370.540000 ;
+ RECT 643.190000 3352.210000 1036.730000 3370.540000 ;
+ RECT 157.420000 3351.330000 162.650000 3434.080000 ;
+ RECT 2050.100000 3350.960000 2184.900000 3370.540000 ;
+ RECT 1850.000000 3350.960000 2048.270000 3352.210000 ;
+ RECT 643.190000 3350.960000 1648.990000 3352.210000 ;
+ RECT 239.230000 3350.960000 641.590000 3370.540000 ;
+ RECT 1850.030000 3350.750000 2048.270000 3350.960000 ;
+ RECT 1650.590000 3350.750000 1848.170000 3352.210000 ;
+ RECT 643.190000 3350.750000 841.390000 3350.960000 ;
+ RECT 1650.590000 3350.610000 1848.430000 3350.750000 ;
+ RECT 1643.330000 3350.610000 1648.990000 3350.960000 ;
+ RECT 2050.130000 3350.460000 2184.900000 3350.960000 ;
+ RECT 1850.030000 3350.460000 2048.530000 3350.750000 ;
+ RECT 1643.330000 3350.460000 1848.430000 3350.610000 ;
+ RECT 1243.190000 3350.460000 1446.690000 3350.960000 ;
+ RECT 1043.090000 3350.460000 1241.590000 3350.960000 ;
+ RECT 842.990000 3350.460000 1041.490000 3350.960000 ;
+ RECT 642.890000 3350.460000 841.390000 3350.750000 ;
+ RECT 442.790000 3350.460000 641.290000 3350.960000 ;
+ RECT 239.230000 3350.460000 441.190000 3350.960000 ;
+ RECT 2050.130000 3349.860000 2051.990000 3350.460000 ;
+ RECT 1850.030000 3349.860000 1851.890000 3350.460000 ;
+ RECT 1449.890000 3349.860000 1641.730000 3350.960000 ;
+ RECT 1439.830000 3349.860000 1446.690000 3350.460000 ;
+ RECT 1239.730000 3349.860000 1241.590000 3350.460000 ;
+ RECT 1039.630000 3349.860000 1041.490000 3350.460000 ;
+ RECT 839.530000 3349.860000 841.390000 3350.460000 ;
+ RECT 639.430000 3349.860000 641.290000 3350.460000 ;
+ RECT 439.330000 3349.860000 441.190000 3350.460000 ;
+ RECT 164.250000 3348.860000 236.030000 3434.080000 ;
+ RECT 157.420000 3348.860000 161.050000 3351.330000 ;
+ RECT 2160.070000 3345.650000 2184.900000 3350.460000 ;
+ RECT 239.230000 3345.650000 241.090000 3350.460000 ;
+ RECT 157.420000 3153.450000 236.030000 3348.860000 ;
+ RECT 157.420000 3152.090000 162.650000 3153.450000 ;
+ RECT 157.420000 3145.390000 161.050000 3152.090000 ;
+ RECT 2718.390000 2980.640000 2723.620000 3389.780000 ;
+ RECT 2719.790000 2976.370000 2723.620000 2980.640000 ;
+ RECT 157.420000 2951.830000 162.650000 3145.390000 ;
+ RECT 157.420000 2945.160000 161.050000 2951.830000 ;
+ RECT 157.420000 2751.560000 162.650000 2945.160000 ;
+ RECT 157.420000 2745.080000 161.050000 2751.560000 ;
+ RECT 157.420000 2551.310000 162.650000 2745.080000 ;
+ RECT 1644.930000 2545.530000 1651.790000 3350.460000 ;
+ RECT 1439.830000 2545.530000 1643.330000 3349.860000 ;
+ RECT 9.300000 2545.440000 154.020000 3434.080000 ;
+ RECT 157.420000 2544.610000 161.050000 2551.310000 ;
+ RECT 9.300000 2544.360000 152.870000 2545.440000 ;
+ RECT 1647.830000 2543.280000 1651.790000 2545.530000 ;
+ RECT 1644.930000 2543.280000 1646.230000 2545.530000 ;
+ RECT 1445.660000 2543.280000 1643.330000 2545.530000 ;
+ RECT 1439.830000 2543.280000 1444.060000 2545.530000 ;
+ RECT 157.420000 2351.050000 162.650000 2544.610000 ;
+ RECT 157.420000 2344.350000 161.050000 2351.050000 ;
+ RECT 157.420000 2150.710000 162.650000 2344.350000 ;
+ RECT 1644.930000 2145.010000 1651.790000 2543.280000 ;
+ RECT 1439.830000 2145.010000 1643.330000 2543.280000 ;
+ RECT 157.420000 2144.230000 161.050000 2150.710000 ;
+ RECT 1647.830000 2143.010000 1651.790000 2145.010000 ;
+ RECT 1644.930000 2143.010000 1646.230000 2145.010000 ;
+ RECT 1445.660000 2142.760000 1643.330000 2145.010000 ;
+ RECT 1439.830000 2142.760000 1444.060000 2145.010000 ;
+ RECT 9.300000 1952.480000 154.020000 2544.360000 ;
+ RECT 9.300000 1951.400000 152.870000 1952.480000 ;
+ RECT 157.420000 1950.530000 162.650000 2144.230000 ;
+ RECT 157.420000 1943.830000 161.050000 1950.530000 ;
+ RECT 157.420000 1750.270000 162.650000 1943.830000 ;
+ RECT 1644.930000 1744.450000 1651.790000 2143.010000 ;
+ RECT 1439.830000 1744.450000 1643.330000 2142.760000 ;
+ RECT 157.420000 1743.570000 161.050000 1750.270000 ;
+ RECT 1647.830000 1742.240000 1651.790000 1744.450000 ;
+ RECT 1644.930000 1742.240000 1646.230000 1744.450000 ;
+ RECT 1445.660000 1742.240000 1643.330000 1744.450000 ;
+ RECT 1439.830000 1742.240000 1444.060000 1744.450000 ;
+ RECT 157.420000 1550.010000 162.650000 1743.570000 ;
+ RECT 157.420000 1543.380000 161.050000 1550.010000 ;
+ RECT 157.420000 1349.750000 162.650000 1543.380000 ;
+ RECT 1644.930000 1343.970000 1651.790000 1742.240000 ;
+ RECT 1439.830000 1343.970000 1643.330000 1742.240000 ;
+ RECT 157.420000 1343.300000 161.050000 1349.750000 ;
+ RECT 1647.830000 1341.720000 1651.790000 1343.970000 ;
+ RECT 1644.930000 1341.720000 1646.230000 1343.970000 ;
+ RECT 1445.660000 1341.720000 1643.330000 1343.970000 ;
+ RECT 1439.830000 1341.720000 1444.060000 1343.970000 ;
+ RECT 157.420000 1149.490000 162.650000 1343.300000 ;
+ RECT 157.420000 1142.790000 161.050000 1149.490000 ;
+ RECT 9.300000 1141.920000 154.020000 1951.400000 ;
+ RECT 9.300000 1140.840000 152.870000 1141.920000 ;
+ RECT 157.420000 949.230000 162.650000 1142.790000 ;
+ RECT 157.420000 942.530000 161.050000 949.230000 ;
+ RECT 157.420000 748.930000 162.650000 942.530000 ;
+ RECT 157.420000 742.450000 161.050000 748.930000 ;
+ RECT 9.300000 548.960000 154.020000 1140.840000 ;
+ RECT 157.420000 548.710000 162.650000 742.450000 ;
+ RECT 9.300000 547.880000 152.870000 548.960000 ;
+ RECT 157.420000 542.010000 161.050000 548.710000 ;
+ RECT 2718.390000 461.230000 2723.620000 2976.370000 ;
+ RECT 2719.790000 457.800000 2723.620000 461.230000 ;
+ RECT 2194.930000 457.800000 2716.990000 3384.150000 ;
+ RECT 157.420000 348.450000 162.650000 542.010000 ;
+ RECT 157.420000 341.750000 161.050000 348.450000 ;
+ RECT 157.420000 153.860000 162.650000 341.750000 ;
+ RECT 2158.470000 148.190000 2184.900000 3345.650000 ;
+ RECT 2048.530000 145.300000 2051.990000 3349.860000 ;
+ RECT 1848.430000 145.300000 1851.890000 3349.860000 ;
+ RECT 1439.830000 145.300000 1643.330000 1341.720000 ;
+ RECT 1239.730000 145.300000 1243.190000 3349.860000 ;
+ RECT 1039.630000 145.300000 1043.090000 3349.860000 ;
+ RECT 839.530000 145.300000 842.990000 3349.860000 ;
+ RECT 639.430000 145.300000 642.890000 3349.860000 ;
+ RECT 439.330000 145.300000 442.790000 3349.860000 ;
+ RECT 239.230000 145.300000 242.690000 3345.650000 ;
+ RECT 2160.070000 144.700000 2184.900000 148.190000 ;
+ RECT 2050.130000 144.200000 2051.990000 145.300000 ;
+ RECT 1850.030000 144.200000 1851.890000 145.300000 ;
+ RECT 1449.890000 144.200000 1641.730000 145.300000 ;
+ RECT 1439.830000 144.200000 1446.690000 145.300000 ;
+ RECT 1239.730000 144.200000 1241.590000 145.300000 ;
+ RECT 1039.630000 144.200000 1041.490000 145.300000 ;
+ RECT 839.530000 144.200000 841.390000 145.300000 ;
+ RECT 639.430000 144.200000 641.290000 145.300000 ;
+ RECT 439.330000 144.200000 441.190000 145.300000 ;
+ RECT 239.230000 144.200000 241.090000 145.300000 ;
+ RECT 2048.530000 144.040000 2051.990000 144.200000 ;
+ RECT 1848.430000 144.040000 1851.890000 144.200000 ;
+ RECT 1644.930000 144.040000 1651.790000 1341.720000 ;
+ RECT 1439.830000 144.040000 1643.330000 144.200000 ;
+ RECT 1239.730000 144.040000 1243.190000 144.200000 ;
+ RECT 1039.630000 144.040000 1043.090000 144.200000 ;
+ RECT 839.530000 144.040000 842.990000 144.200000 ;
+ RECT 639.430000 144.040000 642.890000 144.200000 ;
+ RECT 439.330000 144.040000 442.790000 144.200000 ;
+ RECT 1644.930000 142.440000 1648.990000 144.040000 ;
+ RECT 2049.870000 123.600000 2051.990000 144.040000 ;
+ RECT 1849.770000 123.600000 1851.890000 144.040000 ;
+ RECT 1039.630000 123.600000 1041.790000 144.040000 ;
+ RECT 839.530000 123.600000 841.690000 144.040000 ;
+ RECT 639.430000 123.600000 641.590000 144.040000 ;
+ RECT 439.330000 123.600000 441.490000 144.040000 ;
+ RECT 239.230000 123.600000 242.690000 144.200000 ;
+ RECT 1445.660000 120.880000 1643.330000 144.040000 ;
+ RECT 2158.470000 116.040000 2184.900000 144.700000 ;
+ RECT 1449.890000 116.040000 1643.330000 120.880000 ;
+ RECT 1445.660000 116.040000 1448.290000 120.880000 ;
+ RECT 1239.730000 116.040000 1241.890000 144.040000 ;
+ RECT 2160.070000 110.940000 2184.900000 116.040000 ;
+ RECT 2050.130000 110.940000 2051.990000 123.600000 ;
+ RECT 1850.030000 110.940000 1851.890000 123.600000 ;
+ RECT 1650.590000 110.940000 1651.790000 144.040000 ;
+ RECT 1647.830000 110.940000 1648.990000 142.440000 ;
+ RECT 1644.930000 110.940000 1646.230000 142.440000 ;
+ RECT 1445.660000 110.940000 1446.690000 116.040000 ;
+ RECT 1442.670000 110.940000 1444.060000 144.040000 ;
+ RECT 1439.830000 110.940000 1441.070000 144.040000 ;
+ RECT 1239.730000 110.940000 1241.590000 116.040000 ;
+ RECT 1039.630000 110.940000 1041.490000 123.600000 ;
+ RECT 839.530000 110.940000 841.390000 123.600000 ;
+ RECT 639.430000 110.940000 641.290000 123.600000 ;
+ RECT 439.330000 110.940000 441.190000 123.600000 ;
+ RECT 239.230000 110.940000 241.090000 123.600000 ;
+ RECT 157.420000 110.940000 161.050000 153.860000 ;
+ RECT 2158.470000 109.140000 2184.900000 110.940000 ;
+ RECT 2055.190000 109.140000 2156.870000 3350.460000 ;
+ RECT 2048.530000 109.140000 2053.590000 110.940000 ;
+ RECT 1855.090000 109.140000 2046.930000 3350.460000 ;
+ RECT 1848.430000 109.140000 1853.230000 110.940000 ;
+ RECT 1654.990000 109.140000 1846.830000 3350.460000 ;
+ RECT 1647.830000 109.140000 1653.390000 110.940000 ;
+ RECT 1643.330000 109.140000 1646.230000 110.940000 ;
+ RECT 1449.890000 109.140000 1641.730000 116.040000 ;
+ RECT 1438.230000 109.140000 1448.290000 110.940000 ;
+ RECT 1244.790000 109.140000 1436.630000 3350.460000 ;
+ RECT 1238.430000 109.140000 1243.190000 110.940000 ;
+ RECT 1044.690000 109.140000 1236.530000 3350.460000 ;
+ RECT 1038.330000 109.140000 1043.090000 110.940000 ;
+ RECT 844.590000 109.140000 1036.430000 3350.460000 ;
+ RECT 838.230000 109.140000 842.990000 110.940000 ;
+ RECT 644.490000 109.140000 836.330000 3350.460000 ;
+ RECT 638.130000 109.140000 642.890000 110.940000 ;
+ RECT 444.390000 109.140000 636.230000 3350.460000 ;
+ RECT 438.030000 109.140000 442.790000 110.940000 ;
+ RECT 244.290000 109.140000 436.130000 3350.460000 ;
+ RECT 237.630000 109.140000 242.690000 110.940000 ;
+ RECT 164.250000 109.140000 236.030000 3153.450000 ;
+ RECT 157.420000 109.140000 162.650000 110.940000 ;
+ RECT 2194.930000 56.830000 2723.620000 457.800000 ;
+ RECT 2696.010000 53.430000 2723.620000 56.830000 ;
+ RECT 2699.410000 38.960000 2723.620000 53.430000 ;
+ RECT 2719.790000 33.960000 2723.620000 38.960000 ;
+ RECT 2699.410000 33.960000 2716.990000 38.960000 ;
+ RECT 2696.010000 33.960000 2697.810000 53.430000 ;
+ RECT 2188.300000 33.960000 2192.130000 3438.080000 ;
+ RECT 2718.390000 32.160000 2723.620000 33.960000 ;
+ RECT 2696.010000 32.160000 2716.990000 33.960000 ;
+ RECT 2194.930000 32.160000 2694.410000 56.830000 ;
+ RECT 2188.300000 32.160000 2193.530000 33.960000 ;
+ RECT 2834.340000 5.700000 2834.740000 3434.080000 ;
+ RECT 2727.020000 5.700000 2830.740000 3434.080000 ;
+ RECT 2725.220000 5.700000 2725.420000 3434.080000 ;
+ RECT 2186.500000 5.700000 2186.700000 3434.080000 ;
+ RECT 157.420000 5.700000 2184.900000 109.140000 ;
+ RECT 155.620000 5.700000 155.820000 3434.080000 ;
+ RECT 9.300000 5.700000 154.020000 547.880000 ;
+ RECT 5.300000 5.700000 5.700000 3434.080000 ;
+ RECT 2838.340000 1.700000 2840.040000 3438.080000 ;
+ RECT 2725.220000 1.700000 2834.740000 5.700000 ;
+ RECT 2188.300000 1.700000 2723.620000 32.160000 ;
+ RECT 157.420000 1.700000 2186.700000 5.700000 ;
+ RECT 5.300000 1.700000 155.820000 5.700000 ;
+ RECT 0.000000 1.700000 1.700000 3438.080000 ;
+ RECT 0.000000 0.000000 2840.040000 1.700000 ;
+ END
+END eFPGA_top
+
+END LIBRARY
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 5006ced..94d926d 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -39,14 +39,15 @@
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_NET) "inst_eFPGA_top.wb_clk_i"
+#set ::env(CLOCK_NET) "mprj.clk"
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "40"
## Internal Macros
### Macro PDN Connections
-set ::env(FP_PDN_MACRO_HOOKS) "\
- mprj vccd1 vssd1"
+#set ::env(FP_PDN_MACRO_HOOKS) "\
+# inst_eFPGA_top vccd1 vssd1"
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
@@ -54,13 +55,21 @@
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
+ ../verilog/rtl/eFPGA_top.v"
+
+# $script_dir/../../verilog/rtl/user_proj_example.v"
set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/user_proj_example.lef"
+ $script_dir/../../lef/eFPGA_top.lef"
set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/user_proj_example.gds"
+ $script_dir/../../gds/eFPGA_top.gds"
+
+#set ::env(EXTRA_LEFS) "\
+# $script_dir/../../lef/user_proj_example.lef"
+
+#set ::env(EXTRA_GDS_FILES) "\
+# $script_dir/../../gds/user_proj_example.gds"
set ::env(GLB_RT_MAXLAYER) 5
@@ -83,3 +92,16 @@
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION) 0
set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(MAGIC_DRC_USE_GDS) 0
+set ::env(ROUTING_CORES) 12
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+set ::env(VDD_PIN) "vccd1"
+set ::env(GND_PIN) "vssd1"
+#set ::env(GLB_RT_OBS) "met4 60 60 2860 3460, met5 60 60 2860 3460"
+#set ::env(MACRO_BLOCKAGES_LAYER) "li1 met1 met2 met3 met4 met5"
+#set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
+#set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "0"
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+#set ::env(FP_PDN_MACROS) 1
+
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..88e12b6 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+inst_eFPGA_top 40 40 R0
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
index 8797dcd..267d91c 120000
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -1 +1 @@
-../../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
+../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
diff --git a/verilog/rtl/eFPGA_top.v b/verilog/rtl/eFPGA_top.v
new file mode 100644
index 0000000..4916401
--- /dev/null
+++ b/verilog/rtl/eFPGA_top.v
@@ -0,0 +1,139121 @@
+/*
+###############################################################
+# Generated by: Cadence Innovus 19.11-s128_1
+# OS: Linux x86_64(Host ID cspc083)
+# Generated on: Mon Nov 15 10:24:26 2021
+# Design: eFPGA_top
+# Command: saveNetlist OUTPUTs/eFPGA_top.v
+###############################################################
+*/
+/* Generated by Yosys 0.9+4052 (git sha1 d061b0e, gcc 8.3.1 -fPIC -Os) */
+module eFPGA_top (
+ wb_clk_i,
+ wbs_stb_i,
+ wbs_cyc_i,
+ wbs_we_i,
+ wbs_dat_i,
+ wbs_adr_i,
+ wbs_dat_o,
+ la_data_out,
+ io_in,
+ io_out,
+ io_oeb,
+ user_clock2);
+ input wb_clk_i;
+ input wbs_stb_i;
+ input wbs_cyc_i;
+ input wbs_we_i;
+ input [31:0] wbs_dat_i;
+ input [31:0] wbs_adr_i;
+ output [31:0] wbs_dat_o;
+ output [6:0] la_data_out;
+ input [37:0] io_in;
+ output [37:0] io_out;
+ output [37:0] io_oeb;
+ input user_clock2;
+
+ // Internal wires
+ wire FE_OFN185_FE_OFN72_la_data_out_3;
+ wire FE_OFN184_FE_OFN72_la_data_out_3;
+ wire FE_OFN183_FE_OFN70_la_data_out_4;
+ wire FE_OFN182_FE_OFN70_la_data_out_4;
+ wire CTS_41;
+ wire CTS_40;
+ wire CTS_39;
+ wire CTS_38;
+ wire CTS_37;
+ wire CTS_36;
+ wire CTS_29;
+ wire CTS_35;
+ wire CTS_34;
+ wire CTS_33;
+ wire CTS_32;
+ wire CTS_31;
+ wire CTS_23;
+ wire CTS_25;
+ wire CTS_30;
+ wire CTS_28;
+ wire CTS_27;
+ wire CTS_20;
+ wire CTS_18;
+ wire CTS_16;
+ wire CTS_22;
+ wire CTS_19;
+ wire CTS_17;
+ wire CTS_26;
+ wire CTS_24;
+ wire CTS_21;
+ wire CTS_11;
+ wire CTS_10;
+ wire CTS_9;
+ wire CTS_13;
+ wire CTS_15;
+ wire CTS_6;
+ wire CTS_5;
+ wire CTS_8;
+ wire CTS_14;
+ wire CTS_12;
+ wire CTS_7;
+ wire CTS_4;
+ wire CTS_2;
+ wire CTS_1;
+ wire CTS_3;
+ wire FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30;
+ wire FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29;
+ wire FE_OFN177_1599;
+ wire FE_OFN176_Inst_eFPGA_Tile_X0Y12_A_O_top;
+ wire FE_OFN175_Inst_eFPGA_Tile_X0Y12_A_O_top;
+ wire FE_OFN174_Inst_eFPGA_Tile_X0Y12_A_O_top;
+ wire FE_OFN173_Inst_eFPGA_Tile_X0Y12_A_O_top;
+ wire FE_OFN172_Inst_Frame_Select_0_FrameStrobe_O_3;
+ wire FE_OFN171_Inst_Frame_Select_0_FrameStrobe_O_2;
+ wire FE_OFN170_Inst_Frame_Select_0_FrameStrobe_O_1;
+ wire FE_OFN169_Inst_Frame_Select_0_FrameStrobe_O_0;
+ wire FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9;
+ wire FE_OFN167_Config_inst_ConfigFSM_inst_WriteData_9;
+ wire FE_OFN166_Config_inst_ConfigFSM_inst_WriteData_8;
+ wire FE_OFN165_Config_inst_ConfigFSM_inst_WriteData_8;
+ wire FE_OFN164_Config_inst_ConfigFSM_inst_WriteData_7;
+ wire FE_OFN163_Config_inst_ConfigFSM_inst_WriteData_7;
+ wire FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6;
+ wire FE_OFN161_Config_inst_ConfigFSM_inst_WriteData_6;
+ wire FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5;
+ wire FE_OFN159_Config_inst_ConfigFSM_inst_WriteData_5;
+ wire FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4;
+ wire FE_OFN157_Config_inst_ConfigFSM_inst_WriteData_4;
+ wire FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3;
+ wire FE_OFN155_Config_inst_ConfigFSM_inst_WriteData_3;
+ wire FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31;
+ wire FE_OFN153_Config_inst_ConfigFSM_inst_WriteData_31;
+ wire FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30;
+ wire FE_OFN151_Config_inst_ConfigFSM_inst_WriteData_30;
+ wire FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2;
+ wire FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29;
+ wire FE_OFN148_Config_inst_ConfigFSM_inst_WriteData_29;
+ wire FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28;
+ wire FE_OFN146_Config_inst_ConfigFSM_inst_WriteData_28;
+ wire FE_OFN145_Config_inst_ConfigFSM_inst_WriteData_27;
+ wire FE_OFN144_Config_inst_ConfigFSM_inst_WriteData_27;
+ wire FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26;
+ wire FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25;
+ wire FE_OFN141_Config_inst_ConfigFSM_inst_WriteData_24;
+ wire FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24;
+ wire FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23;
+ wire FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22;
+ wire FE_OFN137_Config_inst_ConfigFSM_inst_WriteData_22;
+ wire FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21;
+ wire FE_OFN135_Config_inst_ConfigFSM_inst_WriteData_21;
+ wire FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20;
+ wire FE_OFN133_Config_inst_ConfigFSM_inst_WriteData_20;
+ wire FE_OFN132_Config_inst_ConfigFSM_inst_WriteData_1;
+ wire FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1;
+ wire FE_OFN130_Config_inst_ConfigFSM_inst_WriteData_19;
+ wire FE_OFN129_Config_inst_ConfigFSM_inst_WriteData_19;
+ wire FE_OFN128_Config_inst_ConfigFSM_inst_WriteData_18;
+ wire FE_OFN127_Config_inst_ConfigFSM_inst_WriteData_18;
+ wire FE_OFN126_Config_inst_ConfigFSM_inst_WriteData_17;
+ wire FE_OFN125_Config_inst_ConfigFSM_inst_WriteData_17;
+ wire FE_OFN124_Config_inst_ConfigFSM_inst_WriteData_16;
+ wire FE_OFN123_Config_inst_ConfigFSM_inst_WriteData_16;
+ wire FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15;
+ wire FE_OFN121_Config_inst_ConfigFSM_inst_WriteData_15;
+ wire FE_OFN120_Config_inst_ConfigFSM_inst_WriteData_14;
+ wire FE_OFN119_Config_inst_ConfigFSM_inst_WriteData_14;
+ wire FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13;
+ wire FE_OFN117_Config_inst_ConfigFSM_inst_WriteData_13;
+ wire FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12;
+ wire FE_OFN115_Config_inst_ConfigFSM_inst_WriteData_12;
+ wire FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11;
+ wire FE_OFN113_Config_inst_ConfigFSM_inst_WriteData_11;
+ wire FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10;
+ wire FE_OFN111_Config_inst_ConfigFSM_inst_WriteData_10;
+ wire FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0;
+ wire FE_OFN109_wbs_dat_o_0;
+ wire FE_OFN108_wbs_dat_o_1;
+ wire FE_OFN107_wbs_dat_o_2;
+ wire FE_OFN106_wbs_dat_o_3;
+ wire FE_OFN105_wbs_dat_o_4;
+ wire FE_OFN104_wbs_dat_o_5;
+ wire FE_OFN103_wbs_dat_o_6;
+ wire FE_OFN102_wbs_dat_o_7;
+ wire FE_OFN101_wbs_dat_o_8;
+ wire FE_OFN100_wbs_dat_o_9;
+ wire FE_OFN99_wbs_dat_o_10;
+ wire FE_OFN98_wbs_dat_o_11;
+ wire FE_OFN97_wbs_dat_o_12;
+ wire FE_OFN96_wbs_dat_o_13;
+ wire FE_OFN95_wbs_dat_o_14;
+ wire FE_OFN94_wbs_dat_o_15;
+ wire FE_OFN93_wbs_dat_o_16;
+ wire FE_OFN92_wbs_dat_o_17;
+ wire FE_OFN91_wbs_dat_o_18;
+ wire FE_OFN90_wbs_dat_o_19;
+ wire FE_OFN89_wbs_dat_o_20;
+ wire FE_OFN88_wbs_dat_o_21;
+ wire FE_OFN87_wbs_dat_o_22;
+ wire FE_OFN86_wbs_dat_o_23;
+ wire FE_OFN85_wbs_dat_o_24;
+ wire FE_OFN84_wbs_dat_o_25;
+ wire FE_OFN83_wbs_dat_o_26;
+ wire FE_OFN82_wbs_dat_o_27;
+ wire FE_OFN81_wbs_dat_o_28;
+ wire FE_OFN80_wbs_dat_o_29;
+ wire FE_OFN79_wbs_dat_o_30;
+ wire FE_OFN78_wbs_dat_o_31;
+ wire FE_OFN77_wb_clk_i;
+ wire FE_OFN76_wb_clk_i;
+ wire FE_OFN75_la_data_out_0;
+ wire FE_OFN74_la_data_out_0;
+ wire FE_OFN72_la_data_out_3;
+ wire FE_OFN70_la_data_out_4;
+ wire FE_OFN69_io_out_0;
+ wire FE_OFN68_io_out_1;
+ wire FE_OFN67_io_out_2;
+ wire FE_OFN66_io_out_3;
+ wire FE_OFN65_io_out_4;
+ wire FE_OFN64_io_out_5;
+ wire FE_RN_1;
+ wire FE_OFN62_io_out_6;
+ wire FE_OFN61_io_out_6;
+ wire FE_OFN60_io_oeb_0;
+ wire FE_OFN59_io_oeb_1;
+ wire FE_OFN58_io_oeb_2;
+ wire FE_OFN57_io_oeb_3;
+ wire FE_OFN56_io_oeb_4;
+ wire FE_OFN55_io_oeb_5;
+ wire FE_OFN54_io_oeb_6;
+ wire FE_OFN53_io_in_7;
+ wire FE_OFN52_io_in_7;
+ wire FE_OFN51_io_in_8;
+ wire FE_OFN50_io_in_8;
+ wire FE_OFN49_io_in_9;
+ wire FE_OFN48_io_in_9;
+ wire FE_OFN47_io_in_10;
+ wire FE_OFN46_io_in_10;
+ wire FE_OFN45_io_in_11;
+ wire FE_OFN44_io_in_11;
+ wire FE_OFN43_io_in_12;
+ wire FE_OFN42_io_in_12;
+ wire FE_OFN41_io_in_13;
+ wire FE_OFN40_io_in_13;
+ wire FE_OFN39_io_in_14;
+ wire FE_OFN38_io_in_14;
+ wire FE_OFN37_io_in_15;
+ wire FE_OFN36_io_in_15;
+ wire FE_OFN35_io_in_17;
+ wire FE_OFN34_io_in_17;
+ wire FE_OFN33_Config_inst_Inst_bitbang_s_data_sample_2;
+ wire FE_OFN32_Config_inst_Inst_bitbang_s_data_sample_1;
+ wire FE_OFN31_Config_inst_Inst_bitbang_s_clk_sample_2;
+ wire FE_OFN30_Config_inst_Inst_bitbang_s_clk_sample_2;
+ wire FE_OFN29_Config_inst_Inst_bitbang_s_clk_sample_2;
+ wire FE_OFN28_Config_inst_Inst_bitbang_active;
+ wire FE_OFN27_Config_inst_INST_config_UART_RxLocal;
+ wire FE_OFN26_Config_inst_INST_config_UART_RxLocal;
+ wire FE_OFN25_Config_inst_INST_config_UART_RxLocal;
+ wire FE_OFN24_Config_inst_INST_config_UART_RxLocal;
+ wire FE_OFN23_1925;
+ wire FE_OFN22_1920;
+ wire FE_OFN21_1915;
+ wire FE_OFN20_1851;
+ wire FE_OFN19_1849;
+ wire FE_OFN18_1847;
+ wire FE_OFN17_1845;
+ wire FE_OFN16_1840;
+ wire FE_OFN15_1838;
+ wire FE_OFN14_1834;
+ wire FE_OFN13_1831;
+ wire FE_OFN12_1829;
+ wire FE_OFN11_1827;
+ wire FE_OFN10_1825;
+ wire FE_OFN9_1823;
+ wire FE_OFN8_1818;
+ wire FE_OFN7_1816;
+ wire FE_OFN6_1814;
+ wire FE_OFN5_1525;
+ wire FE_OFN4_1509;
+ wire FE_OFN3_1493;
+ wire FE_OFN2_1332;
+ wire FE_OFN1_1190;
+ wire FE_OFN0_1174;
+ wire _0000_;
+ wire _0001_;
+ wire _0003_;
+ wire _0011_;
+ wire _0012_;
+ wire _0013_;
+ wire _0014_;
+ wire _0015_;
+ wire _0017_;
+ wire _0018_;
+ wire _0019_;
+ wire _0020_;
+ wire _0023_;
+ wire _0024_;
+ wire _0026_;
+ wire _0027_;
+ wire _0028_;
+ wire _0029_;
+ wire _0030_;
+ wire _0031_;
+ wire _0032_;
+ wire _0033_;
+ wire _0034_;
+ wire _0035_;
+ wire _0036_;
+ wire _0037_;
+ wire _0041_;
+ wire _0042_;
+ wire _0043_;
+ wire _0044_;
+ wire _0045_;
+ wire _0046_;
+ wire _0047_;
+ wire _0048_;
+ wire _0049_;
+ wire _0050_;
+ wire _0051_;
+ wire _0052_;
+ wire _0053_;
+ wire _0054_;
+ wire _0055_;
+ wire _0056_;
+ wire _0058_;
+ wire _0059_;
+ wire _0060_;
+ wire _0061_;
+ wire _0062_;
+ wire _0063_;
+ wire _0064_;
+ wire _0065_;
+ wire _0066_;
+ wire _0067_;
+ wire _0068_;
+ wire _0069_;
+ wire _0070_;
+ wire _0071_;
+ wire _0072_;
+ wire _0073_;
+ wire _0074_;
+ wire _0075_;
+ wire _0076_;
+ wire _0077_;
+ wire _0078_;
+ wire _0079_;
+ wire _0080_;
+ wire _0081_;
+ wire _0082_;
+ wire _0083_;
+ wire _0084_;
+ wire _0085_;
+ wire _0086_;
+ wire _0087_;
+ wire _0088_;
+ wire _0089_;
+ wire _0090_;
+ wire _0091_;
+ wire _0092_;
+ wire _0093_;
+ wire _0094_;
+ wire _0095_;
+ wire _0096_;
+ wire _0097_;
+ wire _0099_;
+ wire _0100_;
+ wire _0101_;
+ wire _0102_;
+ wire _0103_;
+ wire _0104_;
+ wire _0105_;
+ wire _0106_;
+ wire _0107_;
+ wire _0108_;
+ wire _0109_;
+ wire _0110_;
+ wire _0111_;
+ wire _0112_;
+ wire _0113_;
+ wire _0114_;
+ wire _0115_;
+ wire _0116_;
+ wire _0117_;
+ wire _0118_;
+ wire _0119_;
+ wire _0120_;
+ wire _0121_;
+ wire _0122_;
+ wire _0123_;
+ wire _0124_;
+ wire _0125_;
+ wire _0127_;
+ wire _0128_;
+ wire _0129_;
+ wire _0130_;
+ wire _0131_;
+ wire _0132_;
+ wire _0134_;
+ wire _0135_;
+ wire _0136_;
+ wire _0137_;
+ wire _0138_;
+ wire _0139_;
+ wire _0140_;
+ wire _0141_;
+ wire _0175_;
+ wire _0176_;
+ wire _0177_;
+ wire _0178_;
+ wire _0179_;
+ wire _0180_;
+ wire _0181_;
+ wire _0182_;
+ wire _0183_;
+ wire _0184_;
+ wire _0185_;
+ wire _0186_;
+ wire _0187_;
+ wire _0188_;
+ wire _0189_;
+ wire _0190_;
+ wire _0191_;
+ wire _0192_;
+ wire _0193_;
+ wire _0194_;
+ wire _0195_;
+ wire _0196_;
+ wire _0197_;
+ wire _0198_;
+ wire _0199_;
+ wire _0200_;
+ wire _0201_;
+ wire _0202_;
+ wire _0203_;
+ wire _0204_;
+ wire _0205_;
+ wire _0206_;
+ wire _0207_;
+ wire _0208_;
+ wire _0209_;
+ wire _0210_;
+ wire _0211_;
+ wire _0212_;
+ wire _0213_;
+ wire _0214_;
+ wire _0215_;
+ wire _0216_;
+ wire _0217_;
+ wire _0218_;
+ wire _0219_;
+ wire _0220_;
+ wire _0221_;
+ wire _0222_;
+ wire _0223_;
+ wire _0224_;
+ wire _0225_;
+ wire _0226_;
+ wire _0227_;
+ wire _0228_;
+ wire _0229_;
+ wire _0230_;
+ wire _0231_;
+ wire _0232_;
+ wire _0233_;
+ wire _0251_;
+ wire _0252_;
+ wire _0253_;
+ wire _0254_;
+ wire _0255_;
+ wire _0256_;
+ wire _0257_;
+ wire _0258_;
+ wire _0259_;
+ wire _0260_;
+ wire _0261_;
+ wire _0262_;
+ wire _0263_;
+ wire _0264_;
+ wire _0265_;
+ wire _0270_;
+ wire _0271_;
+ wire _0272_;
+ wire _0273_;
+ wire _0274_;
+ wire _0275_;
+ wire _0276_;
+ wire _0277_;
+ wire _0278_;
+ wire _0279_;
+ wire _0280_;
+ wire _0281_;
+ wire _0282_;
+ wire _0283_;
+ wire _0284_;
+ wire _0285_;
+ wire _0286_;
+ wire _0287_;
+ wire _0288_;
+ wire _0289_;
+ wire _0290_;
+ wire _0291_;
+ wire _0292_;
+ wire _0293_;
+ wire _0294_;
+ wire _0295_;
+ wire _0296_;
+ wire _0297_;
+ wire _0298_;
+ wire _0299_;
+ wire _0300_;
+ wire _0301_;
+ wire _0302_;
+ wire _0303_;
+ wire _0304_;
+ wire _0305_;
+ wire _0306_;
+ wire _0307_;
+ wire _0308_;
+ wire _0309_;
+ wire _0310_;
+ wire _0311_;
+ wire _0312_;
+ wire _0313_;
+ wire _0314_;
+ wire _0315_;
+ wire _0316_;
+ wire _0317_;
+ wire _0318_;
+ wire _0319_;
+ wire _0320_;
+ wire _0321_;
+ wire _0322_;
+ wire _0323_;
+ wire _0324_;
+ wire _0325_;
+ wire _0326_;
+ wire _0327_;
+ wire _0328_;
+ wire _0329_;
+ wire _0330_;
+ wire _0331_;
+ wire _0332_;
+ wire _0333_;
+ wire _0334_;
+ wire _0335_;
+ wire _0336_;
+ wire _0337_;
+ wire _0338_;
+ wire _0339_;
+ wire _0340_;
+ wire _0341_;
+ wire _0342_;
+ wire _0343_;
+ wire _0344_;
+ wire _0345_;
+ wire _0346_;
+ wire _0347_;
+ wire _0348_;
+ wire _0349_;
+ wire _0350_;
+ wire _0351_;
+ wire _0352_;
+ wire _0353_;
+ wire _0354_;
+ wire _0355_;
+ wire _0356_;
+ wire _0357_;
+ wire _0358_;
+ wire _0359_;
+ wire _0360_;
+ wire _0361_;
+ wire _0362_;
+ wire _0363_;
+ wire _0364_;
+ wire _0365_;
+ wire _0366_;
+ wire _0367_;
+ wire _0368_;
+ wire _0369_;
+ wire _0370_;
+ wire _0371_;
+ wire _0372_;
+ wire _0373_;
+ wire _0374_;
+ wire _0375_;
+ wire _0376_;
+ wire _0377_;
+ wire _0378_;
+ wire _0379_;
+ wire _0380_;
+ wire _0381_;
+ wire _0382_;
+ wire _0383_;
+ wire _0384_;
+ wire _0385_;
+ wire _0386_;
+ wire _0387_;
+ wire _0388_;
+ wire _0389_;
+ wire _0390_;
+ wire _0391_;
+ wire _0392_;
+ wire _0393_;
+ wire _0394_;
+ wire _0395_;
+ wire _0396_;
+ wire _0397_;
+ wire _0398_;
+ wire _0399_;
+ wire _0400_;
+ wire _0401_;
+ wire _0402_;
+ wire _0403_;
+ wire _0404_;
+ wire _0405_;
+ wire _0406_;
+ wire _0407_;
+ wire _0408_;
+ wire _0409_;
+ wire _0410_;
+ wire _0411_;
+ wire _0412_;
+ wire _0413_;
+ wire _0414_;
+ wire _0415_;
+ wire _0416_;
+ wire _0417_;
+ wire _0418_;
+ wire _0419_;
+ wire _0420_;
+ wire _0421_;
+ wire _0422_;
+ wire _0423_;
+ wire _0424_;
+ wire _0425_;
+ wire _0426_;
+ wire _0427_;
+ wire _0428_;
+ wire _0429_;
+ wire _0430_;
+ wire _0431_;
+ wire _0432_;
+ wire _0433_;
+ wire _0434_;
+ wire _0435_;
+ wire _0436_;
+ wire _0437_;
+ wire _0438_;
+ wire _0439_;
+ wire _0440_;
+ wire _0441_;
+ wire _0442_;
+ wire _0443_;
+ wire _0444_;
+ wire _0445_;
+ wire _0446_;
+ wire _0447_;
+ wire _0448_;
+ wire _0449_;
+ wire _0450_;
+ wire _0451_;
+ wire _0452_;
+ wire _0453_;
+ wire _0454_;
+ wire _0455_;
+ wire _0456_;
+ wire _0457_;
+ wire _0458_;
+ wire _0459_;
+ wire _0460_;
+ wire _0461_;
+ wire _0462_;
+ wire _0463_;
+ wire _0464_;
+ wire _0465_;
+ wire _0466_;
+ wire _0467_;
+ wire _0468_;
+ wire _0469_;
+ wire _0470_;
+ wire _0471_;
+ wire _0472_;
+ wire _0473_;
+ wire _0474_;
+ wire _0475_;
+ wire _0476_;
+ wire _0477_;
+ wire _0478_;
+ wire _0479_;
+ wire _0480_;
+ wire _0481_;
+ wire _0482_;
+ wire _0483_;
+ wire _0484_;
+ wire _0485_;
+ wire _0486_;
+ wire _0487_;
+ wire _0488_;
+ wire _0489_;
+ wire _0490_;
+ wire _0491_;
+ wire _0492_;
+ wire _0493_;
+ wire _0494_;
+ wire _0495_;
+ wire _0496_;
+ wire _0497_;
+ wire _0498_;
+ wire _0499_;
+ wire _0500_;
+ wire _0501_;
+ wire _0502_;
+ wire _0503_;
+ wire _0504_;
+ wire _0505_;
+ wire _0506_;
+ wire _0507_;
+ wire _0508_;
+ wire _0509_;
+ wire _0510_;
+ wire _0511_;
+ wire _0512_;
+ wire _0513_;
+ wire _0514_;
+ wire _0515_;
+ wire _0516_;
+ wire _0517_;
+ wire _0518_;
+ wire _0519_;
+ wire _0520_;
+ wire _0521_;
+ wire _0522_;
+ wire _0523_;
+ wire _0524_;
+ wire _0525_;
+ wire _0526_;
+ wire _0527_;
+ wire _0528_;
+ wire _0529_;
+ wire _0530_;
+ wire _0531_;
+ wire _0532_;
+ wire _0533_;
+ wire _0534_;
+ wire _0535_;
+ wire _0536_;
+ wire _0537_;
+ wire _0538_;
+ wire _0539_;
+ wire _0540_;
+ wire _0541_;
+ wire _0542_;
+ wire _0543_;
+ wire _0544_;
+ wire _0545_;
+ wire _0546_;
+ wire _0547_;
+ wire _0548_;
+ wire _0549_;
+ wire _0550_;
+ wire _0551_;
+ wire _0552_;
+ wire _0553_;
+ wire _0554_;
+ wire _0555_;
+ wire _0556_;
+ wire _0557_;
+ wire _0558_;
+ wire _0559_;
+ wire _0560_;
+ wire _0561_;
+ wire _0562_;
+ wire _0563_;
+ wire _0564_;
+ wire _0565_;
+ wire _0566_;
+ wire _0567_;
+ wire _0568_;
+ wire _0569_;
+ wire _0570_;
+ wire _0571_;
+ wire _0572_;
+ wire _0573_;
+ wire _0574_;
+ wire _0575_;
+ wire _0576_;
+ wire _0577_;
+ wire _0578_;
+ wire _0579_;
+ wire _0580_;
+ wire _0581_;
+ wire _0582_;
+ wire _0583_;
+ wire _0584_;
+ wire _0585_;
+ wire _0586_;
+ wire _0587_;
+ wire _0588_;
+ wire _0589_;
+ wire _0590_;
+ wire _0591_;
+ wire _0592_;
+ wire _0593_;
+ wire _0594_;
+ wire _0595_;
+ wire _0596_;
+ wire _0597_;
+ wire _0598_;
+ wire _0599_;
+ wire _0600_;
+ wire _0601_;
+ wire _0602_;
+ wire _0603_;
+ wire _0604_;
+ wire _0605_;
+ wire _0606_;
+ wire _0607_;
+ wire _0608_;
+ wire _0609_;
+ wire _0610_;
+ wire _0611_;
+ wire _0612_;
+ wire _0613_;
+ wire _0614_;
+ wire _0615_;
+ wire _0616_;
+ wire _0617_;
+ wire _0618_;
+ wire _0619_;
+ wire _0620_;
+ wire _0621_;
+ wire _0622_;
+ wire _0623_;
+ wire _0624_;
+ wire _0625_;
+ wire _0626_;
+ wire _0627_;
+ wire _0628_;
+ wire _0629_;
+ wire _0630_;
+ wire _0631_;
+ wire _0632_;
+ wire _0633_;
+ wire _0634_;
+ wire _0635_;
+ wire _0636_;
+ wire _0637_;
+ wire _0638_;
+ wire _0639_;
+ wire _0640_;
+ wire _0641_;
+ wire _0642_;
+ wire _0643_;
+ wire _0644_;
+ wire _0645_;
+ wire _0646_;
+ wire _0647_;
+ wire _0648_;
+ wire _0649_;
+ wire _0650_;
+ wire _0651_;
+ wire _0652_;
+ wire _0653_;
+ wire _0654_;
+ wire _0655_;
+ wire _0656_;
+ wire _0657_;
+ wire _0658_;
+ wire _0659_;
+ wire _0660_;
+ wire _0661_;
+ wire _0662_;
+ wire _0663_;
+ wire _0664_;
+ wire _0665_;
+ wire _0666_;
+ wire _0667_;
+ wire _0668_;
+ wire _0669_;
+ wire _0670_;
+ wire _0671_;
+ wire _0672_;
+ wire _0673_;
+ wire _0674_;
+ wire _0675_;
+ wire _0676_;
+ wire _0677_;
+ wire _0678_;
+ wire _0679_;
+ wire _0680_;
+ wire _0681_;
+ wire _0682_;
+ wire _0683_;
+ wire _0684_;
+ wire _0685_;
+ wire _0686_;
+ wire _0687_;
+ wire _0688_;
+ wire _0689_;
+ wire _0690_;
+ wire _0691_;
+ wire _0692_;
+ wire _0693_;
+ wire _0694_;
+ wire _0695_;
+ wire _0696_;
+ wire _0697_;
+ wire _0698_;
+ wire _0699_;
+ wire _0700_;
+ wire _0701_;
+ wire _0702_;
+ wire _0703_;
+ wire _0704_;
+ wire _0705_;
+ wire _0706_;
+ wire _0707_;
+ wire _0708_;
+ wire _0709_;
+ wire _0710_;
+ wire _0711_;
+ wire _0712_;
+ wire _0713_;
+ wire _0714_;
+ wire _0715_;
+ wire _0716_;
+ wire _0717_;
+ wire _0718_;
+ wire _0719_;
+ wire _0720_;
+ wire _0721_;
+ wire _0722_;
+ wire _0723_;
+ wire _0724_;
+ wire _0725_;
+ wire _0726_;
+ wire _0727_;
+ wire _0728_;
+ wire _0729_;
+ wire _0730_;
+ wire _0731_;
+ wire _0732_;
+ wire _0733_;
+ wire _0734_;
+ wire _0735_;
+ wire _0736_;
+ wire _0737_;
+ wire _0738_;
+ wire _0739_;
+ wire _0740_;
+ wire _0741_;
+ wire _0742_;
+ wire _0743_;
+ wire _0744_;
+ wire _0745_;
+ wire _0746_;
+ wire _0747_;
+ wire _0748_;
+ wire _0749_;
+ wire _0750_;
+ wire _0751_;
+ wire _0752_;
+ wire _0753_;
+ wire _0754_;
+ wire _0755_;
+ wire _0756_;
+ wire _0757_;
+ wire _0758_;
+ wire _0759_;
+ wire _0760_;
+ wire _0761_;
+ wire _0762_;
+ wire _0763_;
+ wire _0764_;
+ wire _0765_;
+ wire _0766_;
+ wire _0767_;
+ wire _0768_;
+ wire _0769_;
+ wire _0770_;
+ wire _0771_;
+ wire _0772_;
+ wire _0773_;
+ wire _0774_;
+ wire _0775_;
+ wire _0776_;
+ wire _0777_;
+ wire _0778_;
+ wire _0779_;
+ wire _0780_;
+ wire _0781_;
+ wire _0782_;
+ wire _0783_;
+ wire _0784_;
+ wire _0785_;
+ wire _0786_;
+ wire _0787_;
+ wire _0788_;
+ wire _0789_;
+ wire _0790_;
+ wire _0791_;
+ wire _0792_;
+ wire _0793_;
+ wire _0794_;
+ wire _0795_;
+ wire _0796_;
+ wire _0797_;
+ wire _0798_;
+ wire _0799_;
+ wire _0800_;
+ wire _0801_;
+ wire _0802_;
+ wire _0803_;
+ wire _0804_;
+ wire _0805_;
+ wire _0806_;
+ wire _0807_;
+ wire _0808_;
+ wire _0809_;
+ wire _0810_;
+ wire _0811_;
+ wire _0812_;
+ wire _0813_;
+ wire _0814_;
+ wire _0815_;
+ wire _0816_;
+ wire _0817_;
+ wire _0818_;
+ wire _0819_;
+ wire _0820_;
+ wire _0821_;
+ wire _0822_;
+ wire _0823_;
+ wire _0824_;
+ wire _0825_;
+ wire _0826_;
+ wire _0827_;
+ wire _0828_;
+ wire _0829_;
+ wire _0830_;
+ wire _0831_;
+ wire _0832_;
+ wire _0833_;
+ wire _0834_;
+ wire _0835_;
+ wire _0836_;
+ wire _0837_;
+ wire _0838_;
+ wire _0839_;
+ wire _0840_;
+ wire _0841_;
+ wire _0842_;
+ wire _0843_;
+ wire _0844_;
+ wire _0845_;
+ wire _0846_;
+ wire _0847_;
+ wire _0848_;
+ wire _0849_;
+ wire _0850_;
+ wire _0851_;
+ wire _0852_;
+ wire _0853_;
+ wire _0854_;
+ wire _0855_;
+ wire _0856_;
+ wire _0857_;
+ wire _0858_;
+ wire _0859_;
+ wire _0860_;
+ wire _0861_;
+ wire _0862_;
+ wire _0863_;
+ wire _0864_;
+ wire _0865_;
+ wire _0866_;
+ wire _0867_;
+ wire _0869_;
+ wire _0870_;
+ wire _0871_;
+ wire _0872_;
+ wire _0874_;
+ wire _0877_;
+ wire _0879_;
+ wire _0880_;
+ wire _0881_;
+ wire _0882_;
+ wire _0883_;
+ wire _0884_;
+ wire _0885_;
+ wire _0886_;
+ wire _0887_;
+ wire _0888_;
+ wire _0889_;
+ wire _0890_;
+ wire _0891_;
+ wire _0892_;
+ wire _0893_;
+ wire _0894_;
+ wire _0895_;
+ wire _0896_;
+ wire _0897_;
+ wire _0898_;
+ wire _0899_;
+ wire _0900_;
+ wire _0901_;
+ wire _0902_;
+ wire _0903_;
+ wire _0904_;
+ wire _0905_;
+ wire _0906_;
+ wire _0907_;
+ wire _0910_;
+ wire _0911_;
+ wire _0912_;
+ wire _0913_;
+ wire _0915_;
+ wire _0916_;
+ wire _0917_;
+ wire _0918_;
+ wire _0920_;
+ wire _0921_;
+ wire _0922_;
+ wire _0923_;
+ wire _0924_;
+ wire _0925_;
+ wire _0926_;
+ wire _0927_;
+ wire _0928_;
+ wire _0929_;
+ wire _0930_;
+ wire _0931_;
+ wire _0932_;
+ wire _0933_;
+ wire _0934_;
+ wire _0935_;
+ wire _0936_;
+ wire _0938_;
+ wire _0939_;
+ wire _0940_;
+ wire _0941_;
+ wire _0942_;
+ wire _0943_;
+ wire _0944_;
+ wire _0945_;
+ wire _0946_;
+ wire _0947_;
+ wire _0948_;
+ wire _0949_;
+ wire _0950_;
+ wire _0951_;
+ wire _0952_;
+ wire _0953_;
+ wire _0954_;
+ wire _0955_;
+ wire _0956_;
+ wire _0957_;
+ wire _0958_;
+ wire _0959_;
+ wire _0961_;
+ wire _0962_;
+ wire _0963_;
+ wire _0964_;
+ wire _0965_;
+ wire _0966_;
+ wire _0967_;
+ wire _0968_;
+ wire _0969_;
+ wire _0970_;
+ wire _0971_;
+ wire _0972_;
+ wire _0973_;
+ wire _0974_;
+ wire _0975_;
+ wire _0976_;
+ wire _0977_;
+ wire _0978_;
+ wire _0979_;
+ wire _0980_;
+ wire _0981_;
+ wire _0982_;
+ wire _0983_;
+ wire _0984_;
+ wire _0985_;
+ wire _0986_;
+ wire _0987_;
+ wire _0988_;
+ wire _0989_;
+ wire _0990_;
+ wire _0991_;
+ wire _0992_;
+ wire _0993_;
+ wire _0994_;
+ wire _0995_;
+ wire _0996_;
+ wire _0997_;
+ wire _0999_;
+ wire _1002_;
+ wire _1004_;
+ wire _1005_;
+ wire _1006_;
+ wire _1007_;
+ wire _1008_;
+ wire _1009_;
+ wire _1010_;
+ wire _1011_;
+ wire _1012_;
+ wire _1013_;
+ wire _1014_;
+ wire _1018_;
+ wire _1019_;
+ wire _1020_;
+ wire _1021_;
+ wire _1022_;
+ wire _1023_;
+ wire _1024_;
+ wire _1025_;
+ wire _1027_;
+ wire _1028_;
+ wire _1029_;
+ wire _1030_;
+ wire _1031_;
+ wire _1032_;
+ wire _1033_;
+ wire _1034_;
+ wire _1035_;
+ wire _1036_;
+ wire _1037_;
+ wire _1038_;
+ wire _1039_;
+ wire _1040_;
+ wire _1041_;
+ wire _1042_;
+ wire _1043_;
+ wire _1044_;
+ wire _1045_;
+ wire _1047_;
+ wire _1048_;
+ wire _1049_;
+ wire _1050_;
+ wire _1052_;
+ wire _1054_;
+ wire _1056_;
+ wire _1060_;
+ wire _1061_;
+ wire _1066_;
+ wire _1067_;
+ wire _1071_;
+ wire _1072_;
+ wire _1078_;
+ wire _1079_;
+ wire _1081_;
+ wire _1082_;
+ wire _1084_;
+ wire _1085_;
+ wire _1086_;
+ wire _1087_;
+ wire _1088_;
+ wire _1090_;
+ wire _1091_;
+ wire _1092_;
+ wire _1093_;
+ wire _1094_;
+ wire _1095_;
+ wire _1096_;
+ wire _1098_;
+ wire _1099_;
+ wire _1100_;
+ wire _1101_;
+ wire _1102_;
+ wire _1103_;
+ wire _1104_;
+ wire _1105_;
+ wire _1106_;
+ wire _1107_;
+ wire _1108_;
+ wire _1110_;
+ wire _1111_;
+ wire _1112_;
+ wire _1113_;
+ wire _1114_;
+ wire _1116_;
+ wire _1117_;
+ wire _1118_;
+ wire _1119_;
+ wire _1120_;
+ wire _1121_;
+ wire _1122_;
+ wire _1123_;
+ wire _1124_;
+ wire _1125_;
+ wire _1127_;
+ wire _1129_;
+ wire _1131_;
+ wire _1132_;
+ wire _1133_;
+ wire _1134_;
+ wire _1135_;
+ wire _1136_;
+ wire _1137_;
+ wire _1138_;
+ wire _1139_;
+ wire _1141_;
+ wire _1142_;
+ wire _1143_;
+ wire _1144_;
+ wire _1145_;
+ wire _1146_;
+ wire _1147_;
+ wire _1148_;
+ wire _1149_;
+ wire _1150_;
+ wire _1151_;
+ wire _1152_;
+ wire _1153_;
+ wire _1154_;
+ wire _1155_;
+ wire _1156_;
+ wire _1157_;
+ wire _1158_;
+ wire _1160_;
+ wire _1161_;
+ wire _1162_;
+ wire _1163_;
+ wire _1165_;
+ wire _1166_;
+ wire _1167_;
+ wire _1168_;
+ wire _1169_;
+ wire _1170_;
+ wire _1171_;
+ wire _1172_;
+ wire _1173_;
+ wire _1174_;
+ wire _1175_;
+ wire _1176_;
+ wire _1177_;
+ wire _1178_;
+ wire _1179_;
+ wire _1180_;
+ wire _1181_;
+ wire _1182_;
+ wire _1183_;
+ wire _1184_;
+ wire _1185_;
+ wire _1186_;
+ wire _1187_;
+ wire _1189_;
+ wire _1190_;
+ wire _1195_;
+ wire _1263_;
+ wire _1264_;
+ wire _1267_;
+ wire _1280_;
+ wire _1281_;
+ wire _1284_;
+ wire _1297_;
+ wire _1298_;
+ wire _1301_;
+ wire _1314_;
+ wire _1315_;
+ wire _1318_;
+ wire _1331_;
+ wire _1332_;
+ wire _1336_;
+ wire _1380_;
+ wire _1383_;
+ wire _1396_;
+ wire _1399_;
+ wire _1412_;
+ wire _1413_;
+ wire _1416_;
+ wire _1429_;
+ wire _1432_;
+ wire _1445_;
+ wire _1449_;
+ wire _1493_;
+ wire _1496_;
+ wire _1509_;
+ wire _1512_;
+ wire _1525_;
+ wire _1528_;
+ wire _1559_;
+ wire _1560_;
+ wire _1561_;
+ wire _1562_;
+ wire _1563_;
+ wire _1564_;
+ wire _1565_;
+ wire _1566_;
+ wire _1567_;
+ wire _1569_;
+ wire _1570_;
+ wire _1573_;
+ wire _1599_;
+ wire _1602_;
+ wire _1615_;
+ wire _1617_;
+ wire _1628_;
+ wire _1630_;
+ wire _1632_;
+ wire _1633_;
+ wire _1635_;
+ wire _1636_;
+ wire _1637_;
+ wire _1638_;
+ wire _1639_;
+ wire _1640_;
+ wire _1641_;
+ wire _1642_;
+ wire _1643_;
+ wire _1644_;
+ wire _1645_;
+ wire _1646_;
+ wire _1647_;
+ wire _1648_;
+ wire _1649_;
+ wire _1650_;
+ wire _1651_;
+ wire _1652_;
+ wire _1653_;
+ wire _1654_;
+ wire _1655_;
+ wire _1656_;
+ wire _1657_;
+ wire _1658_;
+ wire _1659_;
+ wire _1662_;
+ wire _1671_;
+ wire _1672_;
+ wire _1673_;
+ wire _1674_;
+ wire _1675_;
+ wire _1676_;
+ wire _1678_;
+ wire _1679_;
+ wire _1680_;
+ wire _1681_;
+ wire _1682_;
+ wire _1683_;
+ wire _1684_;
+ wire _1685_;
+ wire _1686_;
+ wire _1687_;
+ wire _1688_;
+ wire _1689_;
+ wire _1690_;
+ wire _1691_;
+ wire _1692_;
+ wire _1693_;
+ wire _1694_;
+ wire _1695_;
+ wire _1696_;
+ wire _1697_;
+ wire _1698_;
+ wire _1699_;
+ wire _1700_;
+ wire _1701_;
+ wire _1702_;
+ wire _1720_;
+ wire _1723_;
+ wire _1736_;
+ wire _1739_;
+ wire _1741_;
+ wire _1743_;
+ wire _1748_;
+ wire _1749_;
+ wire _1750_;
+ wire _1751_;
+ wire _1752_;
+ wire _1753_;
+ wire _1754_;
+ wire _1787_;
+ wire _1790_;
+ wire _1792_;
+ wire _1793_;
+ wire _1794_;
+ wire _1795_;
+ wire _1796_;
+ wire _1797_;
+ wire _1798_;
+ wire _1799_;
+ wire _1800_;
+ wire _1801_;
+ wire _1802_;
+ wire _1803_;
+ wire _1804_;
+ wire _1805_;
+ wire _1806_;
+ wire _1808_;
+ wire _1809_;
+ wire _1810_;
+ wire _1812_;
+ wire _1814_;
+ wire _1816_;
+ wire _1818_;
+ wire _1820_;
+ wire _1823_;
+ wire _1825_;
+ wire _1827_;
+ wire _1829_;
+ wire _1831_;
+ wire _1834_;
+ wire _1836_;
+ wire _1838_;
+ wire _1840_;
+ wire _1842_;
+ wire _1845_;
+ wire _1847_;
+ wire _1849_;
+ wire _1851_;
+ wire _1853_;
+ wire _1854_;
+ wire _1855_;
+ wire _1860_;
+ wire _1861_;
+ wire _1862_;
+ wire _1867_;
+ wire _1868_;
+ wire _1873_;
+ wire _1874_;
+ wire _1880_;
+ wire _1904_;
+ wire _1909_;
+ wire _1914_;
+ wire _1915_;
+ wire _1920_;
+ wire _1925_;
+ wire _1932_;
+ wire _1933_;
+ wire _1934_;
+ wire _1935_;
+ wire _1936_;
+ wire _1937_;
+ wire _1938_;
+ wire _1939_;
+ wire _1940_;
+ wire _1941_;
+ wire _1942_;
+ wire _1943_;
+ wire _1944_;
+ wire _1945_;
+ wire _1946_;
+ wire _1947_;
+ wire _1948_;
+ wire _1949_;
+ wire _1950_;
+ wire _1951_;
+ wire _1952_;
+ wire _1953_;
+ wire _1954_;
+ wire _1955_;
+ wire _1956_;
+ wire _1957_;
+ wire _1958_;
+ wire _1959_;
+ wire _1960_;
+ wire _1961_;
+ wire _1962_;
+ wire _1963_;
+ wire _1964_;
+ wire _1965_;
+ wire _1966_;
+ wire _1967_;
+ wire _1968_;
+ wire _1969_;
+ wire _1970_;
+ wire _1971_;
+ wire _1972_;
+ wire _1973_;
+ wire _1974_;
+ wire _1975_;
+ wire _1976_;
+ wire _1977_;
+ wire _1978_;
+ wire _1979_;
+ wire _1980_;
+ wire _1981_;
+ wire _1982_;
+ wire _1983_;
+ wire _1984_;
+ wire _1985_;
+ wire _1986_;
+ wire _1987_;
+ wire _1988_;
+ wire _1989_;
+ wire _1990_;
+ wire _1991_;
+ wire _1992_;
+ wire _1993_;
+ wire _1994_;
+ wire _1995_;
+ wire _1996_;
+ wire \Config_inst.BitBangWriteData[0] ;
+ wire \Config_inst.BitBangWriteData[10] ;
+ wire \Config_inst.BitBangWriteData[11] ;
+ wire \Config_inst.BitBangWriteData[12] ;
+ wire \Config_inst.BitBangWriteData[13] ;
+ wire \Config_inst.BitBangWriteData[14] ;
+ wire \Config_inst.BitBangWriteData[15] ;
+ wire \Config_inst.BitBangWriteData[16] ;
+ wire \Config_inst.BitBangWriteData[17] ;
+ wire \Config_inst.BitBangWriteData[18] ;
+ wire \Config_inst.BitBangWriteData[19] ;
+ wire \Config_inst.BitBangWriteData[1] ;
+ wire \Config_inst.BitBangWriteData[20] ;
+ wire \Config_inst.BitBangWriteData[21] ;
+ wire \Config_inst.BitBangWriteData[22] ;
+ wire \Config_inst.BitBangWriteData[23] ;
+ wire \Config_inst.BitBangWriteData[24] ;
+ wire \Config_inst.BitBangWriteData[25] ;
+ wire \Config_inst.BitBangWriteData[26] ;
+ wire \Config_inst.BitBangWriteData[27] ;
+ wire \Config_inst.BitBangWriteData[28] ;
+ wire \Config_inst.BitBangWriteData[29] ;
+ wire \Config_inst.BitBangWriteData[2] ;
+ wire \Config_inst.BitBangWriteData[30] ;
+ wire \Config_inst.BitBangWriteData[31] ;
+ wire \Config_inst.BitBangWriteData[3] ;
+ wire \Config_inst.BitBangWriteData[4] ;
+ wire \Config_inst.BitBangWriteData[5] ;
+ wire \Config_inst.BitBangWriteData[6] ;
+ wire \Config_inst.BitBangWriteData[7] ;
+ wire \Config_inst.BitBangWriteData[8] ;
+ wire \Config_inst.BitBangWriteData[9] ;
+ wire \Config_inst.BitBangWriteStrobe ;
+ wire \Config_inst.CLK ;
+ wire \Config_inst.Command[0] ;
+ wire \Config_inst.Command[1] ;
+ wire \Config_inst.Command[2] ;
+ wire \Config_inst.Command[3] ;
+ wire \Config_inst.Command[4] ;
+ wire \Config_inst.Command[5] ;
+ wire \Config_inst.Command[6] ;
+ wire \Config_inst.Command[7] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[0] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[10] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[11] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[12] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[13] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[14] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[15] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[16] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[17] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[18] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[19] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[1] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[27] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[28] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[29] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[2] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[30] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[31] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[3] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[4] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[5] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[6] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[7] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[8] ;
+ wire \Config_inst.ConfigFSM_inst.FrameAddressRegister[9] ;
+ wire \Config_inst.ConfigFSM_inst.FrameShiftState[0] ;
+ wire \Config_inst.ConfigFSM_inst.FrameShiftState[1] ;
+ wire \Config_inst.ConfigFSM_inst.FrameShiftState[2] ;
+ wire \Config_inst.ConfigFSM_inst.FrameShiftState[3] ;
+ wire \Config_inst.ConfigFSM_inst.FrameShiftState[4] ;
+ wire \Config_inst.ConfigFSM_inst.FrameStrobe ;
+ wire \Config_inst.ConfigFSM_inst.LongFrameStrobe ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[0] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[10] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[11] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[12] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[13] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[14] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[15] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[16] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[17] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[18] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[19] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[1] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[20] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[21] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[22] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[23] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[24] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[25] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[26] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[27] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[28] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[29] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[2] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[30] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[31] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[3] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[4] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[5] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[6] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[7] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[8] ;
+ wire \Config_inst.ConfigFSM_inst.WriteData[9] ;
+ wire \Config_inst.ConfigFSM_inst.oldFrameStrobe ;
+ wire \Config_inst.ConfigFSM_inst.old_reset ;
+ wire \Config_inst.ConfigFSM_inst.state[0] ;
+ wire \Config_inst.ConfigFSM_inst.state[1] ;
+ wire \Config_inst.INST_config_UART.ByteWriteStrobe ;
+ wire \Config_inst.INST_config_UART.CRCReg[0] ;
+ wire \Config_inst.INST_config_UART.CRCReg[10] ;
+ wire \Config_inst.INST_config_UART.CRCReg[11] ;
+ wire \Config_inst.INST_config_UART.CRCReg[12] ;
+ wire \Config_inst.INST_config_UART.CRCReg[13] ;
+ wire \Config_inst.INST_config_UART.CRCReg[14] ;
+ wire \Config_inst.INST_config_UART.CRCReg[15] ;
+ wire \Config_inst.INST_config_UART.CRCReg[16] ;
+ wire \Config_inst.INST_config_UART.CRCReg[17] ;
+ wire \Config_inst.INST_config_UART.CRCReg[18] ;
+ wire \Config_inst.INST_config_UART.CRCReg[19] ;
+ wire \Config_inst.INST_config_UART.CRCReg[1] ;
+ wire \Config_inst.INST_config_UART.CRCReg[2] ;
+ wire \Config_inst.INST_config_UART.CRCReg[3] ;
+ wire \Config_inst.INST_config_UART.CRCReg[4] ;
+ wire \Config_inst.INST_config_UART.CRCReg[5] ;
+ wire \Config_inst.INST_config_UART.CRCReg[6] ;
+ wire \Config_inst.INST_config_UART.CRCReg[7] ;
+ wire \Config_inst.INST_config_UART.CRCReg[8] ;
+ wire \Config_inst.INST_config_UART.CRCReg[9] ;
+ wire \Config_inst.INST_config_UART.ComCount[0] ;
+ wire \Config_inst.INST_config_UART.ComCount[10] ;
+ wire \Config_inst.INST_config_UART.ComCount[11] ;
+ wire \Config_inst.INST_config_UART.ComCount[1] ;
+ wire \Config_inst.INST_config_UART.ComCount[2] ;
+ wire \Config_inst.INST_config_UART.ComCount[3] ;
+ wire \Config_inst.INST_config_UART.ComCount[4] ;
+ wire \Config_inst.INST_config_UART.ComCount[5] ;
+ wire \Config_inst.INST_config_UART.ComCount[6] ;
+ wire \Config_inst.INST_config_UART.ComCount[7] ;
+ wire \Config_inst.INST_config_UART.ComCount[8] ;
+ wire \Config_inst.INST_config_UART.ComCount[9] ;
+ wire \Config_inst.INST_config_UART.ComState[0] ;
+ wire \Config_inst.INST_config_UART.ComState[1] ;
+ wire \Config_inst.INST_config_UART.ComState[2] ;
+ wire \Config_inst.INST_config_UART.ComState[3] ;
+ wire \Config_inst.INST_config_UART.ComTick ;
+ wire \Config_inst.INST_config_UART.Data_Reg[0] ;
+ wire \Config_inst.INST_config_UART.Data_Reg[1] ;
+ wire \Config_inst.INST_config_UART.Data_Reg[2] ;
+ wire \Config_inst.INST_config_UART.Data_Reg[3] ;
+ wire \Config_inst.INST_config_UART.Data_Reg[4] ;
+ wire \Config_inst.INST_config_UART.Data_Reg[5] ;
+ wire \Config_inst.INST_config_UART.Data_Reg[6] ;
+ wire \Config_inst.INST_config_UART.Data_Reg[7] ;
+ wire \Config_inst.INST_config_UART.GetWordState[0] ;
+ wire \Config_inst.INST_config_UART.GetWordState[1] ;
+ wire \Config_inst.INST_config_UART.HexData[0] ;
+ wire \Config_inst.INST_config_UART.HexData[1] ;
+ wire \Config_inst.INST_config_UART.HexData[2] ;
+ wire \Config_inst.INST_config_UART.HexData[3] ;
+ wire \Config_inst.INST_config_UART.HexData[4] ;
+ wire \Config_inst.INST_config_UART.HexData[5] ;
+ wire \Config_inst.INST_config_UART.HexData[6] ;
+ wire \Config_inst.INST_config_UART.HexData[7] ;
+ wire \Config_inst.INST_config_UART.HexWriteStrobe ;
+ wire \Config_inst.INST_config_UART.HighReg[0] ;
+ wire \Config_inst.INST_config_UART.HighReg[1] ;
+ wire \Config_inst.INST_config_UART.HighReg[2] ;
+ wire \Config_inst.INST_config_UART.HighReg[3] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[0] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[10] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[11] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[12] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[13] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[14] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[15] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[16] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[17] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[18] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[19] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[1] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[20] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[21] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[22] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[23] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[2] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[3] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[4] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[5] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[6] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[7] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[8] ;
+ wire \Config_inst.INST_config_UART.ID_Reg[9] ;
+ wire \Config_inst.INST_config_UART.LocalWriteStrobe ;
+ wire \Config_inst.INST_config_UART.PresentState[0] ;
+ wire \Config_inst.INST_config_UART.PresentState[1] ;
+ wire \Config_inst.INST_config_UART.PresentState[2] ;
+ wire \Config_inst.INST_config_UART.ReceiveLED ;
+ wire \Config_inst.INST_config_UART.ReceiveState ;
+ wire \Config_inst.INST_config_UART.ReceivedByte[0] ;
+ wire \Config_inst.INST_config_UART.ReceivedByte[1] ;
+ wire \Config_inst.INST_config_UART.ReceivedByte[2] ;
+ wire \Config_inst.INST_config_UART.ReceivedByte[3] ;
+ wire \Config_inst.INST_config_UART.ReceivedByte[4] ;
+ wire \Config_inst.INST_config_UART.ReceivedByte[5] ;
+ wire \Config_inst.INST_config_UART.ReceivedByte[6] ;
+ wire \Config_inst.INST_config_UART.ReceivedByte[7] ;
+ wire \Config_inst.INST_config_UART.ReceivedWord[0] ;
+ wire \Config_inst.INST_config_UART.ReceivedWord[1] ;
+ wire \Config_inst.INST_config_UART.ReceivedWord[2] ;
+ wire \Config_inst.INST_config_UART.ReceivedWord[3] ;
+ wire \Config_inst.INST_config_UART.ReceivedWord[4] ;
+ wire \Config_inst.INST_config_UART.ReceivedWord[5] ;
+ wire \Config_inst.INST_config_UART.ReceivedWord[6] ;
+ wire \Config_inst.INST_config_UART.ReceivedWord[7] ;
+ wire \Config_inst.INST_config_UART.RxLocal ;
+ wire \Config_inst.INST_config_UART.TimeToSend ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[0] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[10] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[11] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[12] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[13] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[14] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[1] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[2] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[3] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[4] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[5] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[6] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[7] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[8] ;
+ wire \Config_inst.INST_config_UART.TimeToSendCounter[9] ;
+ wire \Config_inst.INST_config_UART.WriteData[0] ;
+ wire \Config_inst.INST_config_UART.WriteData[10] ;
+ wire \Config_inst.INST_config_UART.WriteData[11] ;
+ wire \Config_inst.INST_config_UART.WriteData[12] ;
+ wire \Config_inst.INST_config_UART.WriteData[13] ;
+ wire \Config_inst.INST_config_UART.WriteData[14] ;
+ wire \Config_inst.INST_config_UART.WriteData[15] ;
+ wire \Config_inst.INST_config_UART.WriteData[16] ;
+ wire \Config_inst.INST_config_UART.WriteData[17] ;
+ wire \Config_inst.INST_config_UART.WriteData[18] ;
+ wire \Config_inst.INST_config_UART.WriteData[19] ;
+ wire \Config_inst.INST_config_UART.WriteData[1] ;
+ wire \Config_inst.INST_config_UART.WriteData[20] ;
+ wire \Config_inst.INST_config_UART.WriteData[21] ;
+ wire \Config_inst.INST_config_UART.WriteData[22] ;
+ wire \Config_inst.INST_config_UART.WriteData[23] ;
+ wire \Config_inst.INST_config_UART.WriteData[24] ;
+ wire \Config_inst.INST_config_UART.WriteData[25] ;
+ wire \Config_inst.INST_config_UART.WriteData[26] ;
+ wire \Config_inst.INST_config_UART.WriteData[27] ;
+ wire \Config_inst.INST_config_UART.WriteData[28] ;
+ wire \Config_inst.INST_config_UART.WriteData[29] ;
+ wire \Config_inst.INST_config_UART.WriteData[2] ;
+ wire \Config_inst.INST_config_UART.WriteData[30] ;
+ wire \Config_inst.INST_config_UART.WriteData[31] ;
+ wire \Config_inst.INST_config_UART.WriteData[3] ;
+ wire \Config_inst.INST_config_UART.WriteData[4] ;
+ wire \Config_inst.INST_config_UART.WriteData[5] ;
+ wire \Config_inst.INST_config_UART.WriteData[6] ;
+ wire \Config_inst.INST_config_UART.WriteData[7] ;
+ wire \Config_inst.INST_config_UART.WriteData[8] ;
+ wire \Config_inst.INST_config_UART.WriteData[9] ;
+ wire \Config_inst.INST_config_UART.WriteStrobe ;
+ wire \Config_inst.INST_config_UART.blink[0] ;
+ wire \Config_inst.INST_config_UART.blink[10] ;
+ wire \Config_inst.INST_config_UART.blink[11] ;
+ wire \Config_inst.INST_config_UART.blink[12] ;
+ wire \Config_inst.INST_config_UART.blink[13] ;
+ wire \Config_inst.INST_config_UART.blink[14] ;
+ wire \Config_inst.INST_config_UART.blink[15] ;
+ wire \Config_inst.INST_config_UART.blink[16] ;
+ wire \Config_inst.INST_config_UART.blink[17] ;
+ wire \Config_inst.INST_config_UART.blink[18] ;
+ wire \Config_inst.INST_config_UART.blink[19] ;
+ wire \Config_inst.INST_config_UART.blink[1] ;
+ wire \Config_inst.INST_config_UART.blink[20] ;
+ wire \Config_inst.INST_config_UART.blink[21] ;
+ wire \Config_inst.INST_config_UART.blink[22] ;
+ wire \Config_inst.INST_config_UART.blink[2] ;
+ wire \Config_inst.INST_config_UART.blink[3] ;
+ wire \Config_inst.INST_config_UART.blink[4] ;
+ wire \Config_inst.INST_config_UART.blink[5] ;
+ wire \Config_inst.INST_config_UART.blink[6] ;
+ wire \Config_inst.INST_config_UART.blink[7] ;
+ wire \Config_inst.INST_config_UART.blink[8] ;
+ wire \Config_inst.INST_config_UART.blink[9] ;
+ wire \Config_inst.Inst_bitbang.active ;
+ wire \Config_inst.Inst_bitbang.local_strobe ;
+ wire \Config_inst.Inst_bitbang.old_local_strobe ;
+ wire \Config_inst.Inst_bitbang.s_clk_sample[0] ;
+ wire \Config_inst.Inst_bitbang.s_clk_sample[1] ;
+ wire \Config_inst.Inst_bitbang.s_clk_sample[2] ;
+ wire \Config_inst.Inst_bitbang.s_clk_sample[3] ;
+ wire \Config_inst.Inst_bitbang.s_data_sample[0] ;
+ wire \Config_inst.Inst_bitbang.s_data_sample[1] ;
+ wire \Config_inst.Inst_bitbang.s_data_sample[2] ;
+ wire \Config_inst.Inst_bitbang.s_data_sample[3] ;
+ wire \Config_inst.Inst_bitbang.serial_control[0] ;
+ wire \Config_inst.Inst_bitbang.serial_control[10] ;
+ wire \Config_inst.Inst_bitbang.serial_control[11] ;
+ wire \Config_inst.Inst_bitbang.serial_control[12] ;
+ wire \Config_inst.Inst_bitbang.serial_control[13] ;
+ wire \Config_inst.Inst_bitbang.serial_control[14] ;
+ wire \Config_inst.Inst_bitbang.serial_control[15] ;
+ wire \Config_inst.Inst_bitbang.serial_control[1] ;
+ wire \Config_inst.Inst_bitbang.serial_control[2] ;
+ wire \Config_inst.Inst_bitbang.serial_control[3] ;
+ wire \Config_inst.Inst_bitbang.serial_control[4] ;
+ wire \Config_inst.Inst_bitbang.serial_control[5] ;
+ wire \Config_inst.Inst_bitbang.serial_control[6] ;
+ wire \Config_inst.Inst_bitbang.serial_control[7] ;
+ wire \Config_inst.Inst_bitbang.serial_control[8] ;
+ wire \Config_inst.Inst_bitbang.serial_control[9] ;
+ wire \Config_inst.Inst_bitbang.serial_data[0] ;
+ wire \Config_inst.Inst_bitbang.serial_data[10] ;
+ wire \Config_inst.Inst_bitbang.serial_data[11] ;
+ wire \Config_inst.Inst_bitbang.serial_data[12] ;
+ wire \Config_inst.Inst_bitbang.serial_data[13] ;
+ wire \Config_inst.Inst_bitbang.serial_data[14] ;
+ wire \Config_inst.Inst_bitbang.serial_data[15] ;
+ wire \Config_inst.Inst_bitbang.serial_data[16] ;
+ wire \Config_inst.Inst_bitbang.serial_data[17] ;
+ wire \Config_inst.Inst_bitbang.serial_data[18] ;
+ wire \Config_inst.Inst_bitbang.serial_data[19] ;
+ wire \Config_inst.Inst_bitbang.serial_data[1] ;
+ wire \Config_inst.Inst_bitbang.serial_data[20] ;
+ wire \Config_inst.Inst_bitbang.serial_data[21] ;
+ wire \Config_inst.Inst_bitbang.serial_data[22] ;
+ wire \Config_inst.Inst_bitbang.serial_data[23] ;
+ wire \Config_inst.Inst_bitbang.serial_data[24] ;
+ wire \Config_inst.Inst_bitbang.serial_data[25] ;
+ wire \Config_inst.Inst_bitbang.serial_data[26] ;
+ wire \Config_inst.Inst_bitbang.serial_data[27] ;
+ wire \Config_inst.Inst_bitbang.serial_data[28] ;
+ wire \Config_inst.Inst_bitbang.serial_data[29] ;
+ wire \Config_inst.Inst_bitbang.serial_data[2] ;
+ wire \Config_inst.Inst_bitbang.serial_data[30] ;
+ wire \Config_inst.Inst_bitbang.serial_data[31] ;
+ wire \Config_inst.Inst_bitbang.serial_data[3] ;
+ wire \Config_inst.Inst_bitbang.serial_data[4] ;
+ wire \Config_inst.Inst_bitbang.serial_data[5] ;
+ wire \Config_inst.Inst_bitbang.serial_data[6] ;
+ wire \Config_inst.Inst_bitbang.serial_data[7] ;
+ wire \Config_inst.Inst_bitbang.serial_data[8] ;
+ wire \Config_inst.Inst_bitbang.serial_data[9] ;
+ wire \Config_inst.SelfWriteData[0] ;
+ wire \Config_inst.SelfWriteData[10] ;
+ wire \Config_inst.SelfWriteData[11] ;
+ wire \Config_inst.SelfWriteData[12] ;
+ wire \Config_inst.SelfWriteData[13] ;
+ wire \Config_inst.SelfWriteData[14] ;
+ wire \Config_inst.SelfWriteData[15] ;
+ wire \Config_inst.SelfWriteData[16] ;
+ wire \Config_inst.SelfWriteData[17] ;
+ wire \Config_inst.SelfWriteData[18] ;
+ wire \Config_inst.SelfWriteData[19] ;
+ wire \Config_inst.SelfWriteData[1] ;
+ wire \Config_inst.SelfWriteData[20] ;
+ wire \Config_inst.SelfWriteData[21] ;
+ wire \Config_inst.SelfWriteData[22] ;
+ wire \Config_inst.SelfWriteData[23] ;
+ wire \Config_inst.SelfWriteData[24] ;
+ wire \Config_inst.SelfWriteData[25] ;
+ wire \Config_inst.SelfWriteData[26] ;
+ wire \Config_inst.SelfWriteData[27] ;
+ wire \Config_inst.SelfWriteData[28] ;
+ wire \Config_inst.SelfWriteData[29] ;
+ wire \Config_inst.SelfWriteData[2] ;
+ wire \Config_inst.SelfWriteData[30] ;
+ wire \Config_inst.SelfWriteData[31] ;
+ wire \Config_inst.SelfWriteData[3] ;
+ wire \Config_inst.SelfWriteData[4] ;
+ wire \Config_inst.SelfWriteData[5] ;
+ wire \Config_inst.SelfWriteData[6] ;
+ wire \Config_inst.SelfWriteData[7] ;
+ wire \Config_inst.SelfWriteData[8] ;
+ wire \Config_inst.SelfWriteData[9] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_0.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_1.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_10.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_11.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_12.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_13.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_14.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_15.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_2.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_3.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_4.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_5.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_6.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_7.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_8.FrameData_O[9] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[0] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[10] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[11] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[12] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[13] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[14] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[15] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[16] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[17] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[18] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[19] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[1] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[20] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[21] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[22] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[23] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[24] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[25] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[26] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[27] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[28] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[29] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[2] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[30] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[31] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[3] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[4] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[5] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[6] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[7] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[8] ;
+ wire \Inst_Frame_Data_Reg_9.FrameData_O[9] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_0.FrameStrobe_O[9] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_1.FrameStrobe_O[9] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_10.FrameStrobe_O[9] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_2.FrameStrobe_O[9] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_3.FrameStrobe_O[9] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_4.FrameStrobe_O[9] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_5.FrameStrobe_O[9] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_6.FrameStrobe_O[9] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_7.FrameStrobe_O[9] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_8.FrameStrobe_O[9] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[0] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[10] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[11] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[12] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[13] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[14] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[15] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[16] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[17] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[18] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[19] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[1] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[2] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[3] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[4] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[5] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[6] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[7] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[8] ;
+ wire \Inst_Frame_Select_9.FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y10_A_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y10_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y10_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y10_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y10_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y10_B_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y10_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y10_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y10_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y10_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y10_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y10_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y10_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y10_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y11_A_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y11_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y11_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y11_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y11_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y11_B_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y11_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y11_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y11_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y11_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y11_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y11_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y11_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y12_A_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y12_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y12_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y12_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y12_B_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y12_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y12_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y12_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y12_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y12_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y12_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y12_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y12_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y13_A_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y13_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y13_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y13_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y13_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y13_B_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y13_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y13_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y13_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y13_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y13_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y13_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y13_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y14_A_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y14_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y14_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y14_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y14_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y14_B_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y14_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y14_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y14_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y14_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y14_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y14_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y14_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y14_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y15_A_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y15_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y15_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y15_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y15_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y15_B_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y15_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y15_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y15_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y15_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y15_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y15_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y15_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y16_A_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y16_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y16_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y16_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y16_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y16_B_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y16_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y16_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y16_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y16_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y16_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y16_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y16_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y16_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y1_A_I_top ;
+ wire \Inst_eFPGA.Tile_X0Y1_A_T_top ;
+ wire \Inst_eFPGA.Tile_X0Y1_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y1_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y1_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y1_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y1_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y1_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y1_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y1_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y1_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y1_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y1_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y2_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y2_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y2_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y2_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y2_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y2_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y2_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y2_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y2_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y2_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y2_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y2_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y3_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y3_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y3_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y3_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y3_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y3_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y3_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y3_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y3_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y3_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y3_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y4_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y4_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y4_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y4_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y4_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y4_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y4_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y4_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y4_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y4_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y4_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y4_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y5_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y5_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y5_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y5_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y5_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y5_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y5_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y5_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y5_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y5_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y5_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y6_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y6_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y6_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y6_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y6_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y6_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y6_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y6_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y6_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y6_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y6_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y6_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y7_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y7_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y7_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y7_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y7_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y7_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y7_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y7_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y7_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y7_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y8_A_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y8_A_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y8_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y8_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y8_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y8_B_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y8_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y8_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y8_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y8_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y8_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y8_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y8_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y8_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X0Y9_A_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y9_A_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y9_A_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y9_A_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y9_B_O_top ;
+ wire \Inst_eFPGA.Tile_X0Y9_B_config_C_bit0 ;
+ wire \Inst_eFPGA.Tile_X0Y9_B_config_C_bit1 ;
+ wire \Inst_eFPGA.Tile_X0Y9_B_config_C_bit2 ;
+ wire \Inst_eFPGA.Tile_X0Y9_B_config_C_bit3 ;
+ wire \Inst_eFPGA.Tile_X0Y9_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y9_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X0Y9_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X0Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y0_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y0_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y10_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y10_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y10_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y10_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y10_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y10_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y10_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y10_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y11_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y11_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y11_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y11_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y11_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y11_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y11_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y12_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y12_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y12_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y12_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y12_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y12_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y12_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y12_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y13_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y13_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y13_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y13_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y13_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y13_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y13_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y14_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y14_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y14_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y14_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y14_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y14_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y14_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y14_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y15_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y15_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y15_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y15_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y15_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y15_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y15_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y16_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y16_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y16_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y16_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y16_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y16_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y16_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y16_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y17_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y17_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y1_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y1_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y1_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y1_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y1_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y1_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y1_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y2_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y2_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y2_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y2_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y2_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y2_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y2_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y2_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y3_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y3_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y3_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y3_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y3_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y3_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y3_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y4_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y4_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y4_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y4_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y4_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y4_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y4_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y4_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y5_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y5_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y5_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y5_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y5_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y5_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y5_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y6_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y6_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y6_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y6_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y6_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y6_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y6_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y6_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y7_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y7_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y7_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y7_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y7_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y7_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y7_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y8_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y8_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y8_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y8_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y8_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y8_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y8_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y8_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y9_Config_accessC_bit0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_Config_accessC_bit1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_Config_accessC_bit2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_Config_accessC_bit3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_C_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_C_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_C_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_C_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y9_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I0 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I1 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I2 ;
+ wire \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I3 ;
+ wire \Inst_eFPGA.Tile_X10Y9_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y9_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X10Y9_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y9_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X10Y9_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y0_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y0_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y0_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y10_Co ;
+ wire \Inst_eFPGA.Tile_X1Y10_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y10_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y10_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y10_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y10_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y10_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y10_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y10_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y10_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y10_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y10_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y11_Co ;
+ wire \Inst_eFPGA.Tile_X1Y11_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y11_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y11_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y11_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y11_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y11_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y11_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y11_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y11_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y11_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y12_Co ;
+ wire \Inst_eFPGA.Tile_X1Y12_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y12_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y12_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y12_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y12_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y12_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y12_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y12_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y12_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y12_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y12_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y13_Co ;
+ wire \Inst_eFPGA.Tile_X1Y13_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y13_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y13_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y13_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y13_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y13_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y13_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y13_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y13_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y13_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y14_Co ;
+ wire \Inst_eFPGA.Tile_X1Y14_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y14_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y14_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y14_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y14_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y14_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y14_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y14_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y14_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y14_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y14_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y15_Co ;
+ wire \Inst_eFPGA.Tile_X1Y15_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y15_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y15_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y15_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y15_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y15_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y15_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y15_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y15_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y15_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y16_Co ;
+ wire \Inst_eFPGA.Tile_X1Y16_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y16_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y16_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y16_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y16_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y16_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y16_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y16_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y16_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y16_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y16_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y17_Co ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y17_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y17_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y17_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y1_Co ;
+ wire \Inst_eFPGA.Tile_X1Y1_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y1_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y1_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y1_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y1_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y1_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y1_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y1_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y1_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y1_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y2_Co ;
+ wire \Inst_eFPGA.Tile_X1Y2_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y2_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y2_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y2_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y2_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y2_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y2_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y2_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y2_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y2_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y2_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y3_Co ;
+ wire \Inst_eFPGA.Tile_X1Y3_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y3_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y3_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y3_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y3_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y3_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y3_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y3_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y3_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y3_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y4_Co ;
+ wire \Inst_eFPGA.Tile_X1Y4_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y4_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y4_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y4_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y4_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y4_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y4_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y4_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y4_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y4_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y4_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y5_Co ;
+ wire \Inst_eFPGA.Tile_X1Y5_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y5_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y5_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y5_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y5_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y5_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y5_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y5_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y5_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y5_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y6_Co ;
+ wire \Inst_eFPGA.Tile_X1Y6_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y6_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y6_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y6_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y6_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y6_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y6_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y6_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y6_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y6_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y6_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y7_Co ;
+ wire \Inst_eFPGA.Tile_X1Y7_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y7_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y7_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y7_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y7_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y7_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y7_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y7_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y7_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y7_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y8_Co ;
+ wire \Inst_eFPGA.Tile_X1Y8_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y8_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y8_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y8_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y8_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y8_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y8_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y8_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y8_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y8_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y8_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y9_Co ;
+ wire \Inst_eFPGA.Tile_X1Y9_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y9_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y9_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y9_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y9_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y9_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y9_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X1Y9_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y9_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X1Y9_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y0_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y0_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y0_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y10_Co ;
+ wire \Inst_eFPGA.Tile_X2Y10_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y10_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y10_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y10_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y10_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y10_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y10_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y10_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y10_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y10_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y10_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y11_Co ;
+ wire \Inst_eFPGA.Tile_X2Y11_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y11_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y11_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y11_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y11_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y11_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y11_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y11_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y11_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y11_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y12_Co ;
+ wire \Inst_eFPGA.Tile_X2Y12_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y12_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y12_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y12_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y12_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y12_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y12_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y12_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y12_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y12_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y12_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y13_Co ;
+ wire \Inst_eFPGA.Tile_X2Y13_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y13_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y13_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y13_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y13_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y13_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y13_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y13_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y13_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y13_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y14_Co ;
+ wire \Inst_eFPGA.Tile_X2Y14_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y14_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y14_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y14_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y14_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y14_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y14_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y14_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y14_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y14_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y14_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y15_Co ;
+ wire \Inst_eFPGA.Tile_X2Y15_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y15_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y15_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y15_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y15_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y15_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y15_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y15_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y15_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y15_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y16_Co ;
+ wire \Inst_eFPGA.Tile_X2Y16_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y16_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y16_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y16_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y16_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y16_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y16_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y16_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y16_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y16_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y16_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y17_Co ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y17_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y17_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y17_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y1_Co ;
+ wire \Inst_eFPGA.Tile_X2Y1_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y1_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y1_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y1_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y1_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y1_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y1_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y1_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y1_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y1_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y2_Co ;
+ wire \Inst_eFPGA.Tile_X2Y2_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y2_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y2_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y2_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y2_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y2_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y2_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y2_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y2_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y2_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y2_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y3_Co ;
+ wire \Inst_eFPGA.Tile_X2Y3_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y3_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y3_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y3_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y3_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y3_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y3_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y3_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y3_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y3_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y4_Co ;
+ wire \Inst_eFPGA.Tile_X2Y4_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y4_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y4_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y4_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y4_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y4_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y4_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y4_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y4_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y4_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y4_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y5_Co ;
+ wire \Inst_eFPGA.Tile_X2Y5_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y5_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y5_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y5_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y5_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y5_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y5_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y5_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y5_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y5_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y6_Co ;
+ wire \Inst_eFPGA.Tile_X2Y6_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y6_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y6_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y6_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y6_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y6_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y6_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y6_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y6_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y6_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y6_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y7_Co ;
+ wire \Inst_eFPGA.Tile_X2Y7_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y7_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y7_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y7_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y7_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y7_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y7_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y7_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y7_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y7_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y8_Co ;
+ wire \Inst_eFPGA.Tile_X2Y8_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y8_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y8_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y8_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y8_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y8_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y8_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y8_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y8_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y8_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y8_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y9_Co ;
+ wire \Inst_eFPGA.Tile_X2Y9_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y9_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y9_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y9_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y9_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y9_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y9_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X2Y9_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y9_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X2Y9_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y0_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y0_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y0_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y10_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y10_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y10_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y10_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y10_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y10_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y10_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y10_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y10_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y10_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y10_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y11_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y11_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y11_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y11_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y11_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y11_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y11_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y11_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y11_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y12_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y12_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y12_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y12_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y12_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y12_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y12_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y12_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y12_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y12_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y13_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y13_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y13_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y13_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y13_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y13_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y13_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y13_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y13_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y14_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y14_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y14_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y14_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y14_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y14_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y14_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y14_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y14_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y14_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y15_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y15_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y15_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y15_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y15_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y15_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y15_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y15_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y15_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y16_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y16_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y16_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y16_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y16_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y16_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y16_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y16_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y16_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y16_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y17_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y17_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y17_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y1_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y1_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y1_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y1_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y1_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y1_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y1_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y1_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y1_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y1_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y2_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y2_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y2_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y2_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y2_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y2_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y2_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y2_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y2_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y2_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y3_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y3_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y3_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y3_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y3_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y3_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y3_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y3_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y3_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y4_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y4_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y4_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y4_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y4_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y4_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y4_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y4_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y4_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y4_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y5_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y5_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y5_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y5_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y5_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y5_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y5_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y5_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y5_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y6_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y6_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y6_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y6_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y6_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y6_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y6_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y6_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y6_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y6_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y7_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y7_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y7_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y7_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y7_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y7_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y7_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y7_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y7_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y8_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y8_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y8_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y8_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y8_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y8_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y8_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y8_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y8_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y8_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y9_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y9_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y9_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y9_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y9_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y9_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X3Y9_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y9_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X3Y9_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y0_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y0_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y0_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y10_Co ;
+ wire \Inst_eFPGA.Tile_X4Y10_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y10_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y10_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y10_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y10_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y10_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y10_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y10_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y10_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y10_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y10_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y11_Co ;
+ wire \Inst_eFPGA.Tile_X4Y11_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y11_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y11_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y11_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y11_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y11_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y11_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y11_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y11_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y11_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y12_Co ;
+ wire \Inst_eFPGA.Tile_X4Y12_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y12_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y12_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y12_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y12_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y12_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y12_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y12_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y12_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y12_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y12_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y13_Co ;
+ wire \Inst_eFPGA.Tile_X4Y13_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y13_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y13_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y13_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y13_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y13_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y13_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y13_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y13_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y13_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y14_Co ;
+ wire \Inst_eFPGA.Tile_X4Y14_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y14_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y14_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y14_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y14_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y14_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y14_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y14_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y14_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y14_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y14_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y15_Co ;
+ wire \Inst_eFPGA.Tile_X4Y15_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y15_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y15_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y15_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y15_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y15_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y15_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y15_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y15_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y15_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y16_Co ;
+ wire \Inst_eFPGA.Tile_X4Y16_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y16_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y16_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y16_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y16_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y16_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y16_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y16_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y16_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y16_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y16_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y17_Co ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y17_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y17_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y17_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y1_Co ;
+ wire \Inst_eFPGA.Tile_X4Y1_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y1_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y1_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y1_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y1_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y1_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y1_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y1_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y1_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y1_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y2_Co ;
+ wire \Inst_eFPGA.Tile_X4Y2_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y2_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y2_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y2_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y2_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y2_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y2_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y2_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y2_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y2_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y2_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y3_Co ;
+ wire \Inst_eFPGA.Tile_X4Y3_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y3_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y3_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y3_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y3_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y3_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y3_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y3_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y3_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y3_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y4_Co ;
+ wire \Inst_eFPGA.Tile_X4Y4_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y4_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y4_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y4_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y4_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y4_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y4_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y4_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y4_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y4_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y4_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y5_Co ;
+ wire \Inst_eFPGA.Tile_X4Y5_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y5_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y5_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y5_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y5_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y5_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y5_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y5_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y5_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y5_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y6_Co ;
+ wire \Inst_eFPGA.Tile_X4Y6_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y6_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y6_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y6_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y6_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y6_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y6_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y6_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y6_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y6_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y6_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y7_Co ;
+ wire \Inst_eFPGA.Tile_X4Y7_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y7_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y7_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y7_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y7_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y7_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y7_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y7_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y7_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y7_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y8_Co ;
+ wire \Inst_eFPGA.Tile_X4Y8_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y8_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y8_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y8_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y8_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y8_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y8_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y8_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y8_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y8_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y8_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y9_Co ;
+ wire \Inst_eFPGA.Tile_X4Y9_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y9_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y9_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y9_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y9_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y9_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y9_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X4Y9_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y9_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X4Y9_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y0_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y0_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y0_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y10_Co ;
+ wire \Inst_eFPGA.Tile_X5Y10_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y10_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y10_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y10_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y10_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y10_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y10_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y10_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y10_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y10_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y10_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y11_Co ;
+ wire \Inst_eFPGA.Tile_X5Y11_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y11_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y11_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y11_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y11_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y11_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y11_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y11_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y11_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y11_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y12_Co ;
+ wire \Inst_eFPGA.Tile_X5Y12_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y12_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y12_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y12_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y12_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y12_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y12_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y12_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y12_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y12_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y12_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y13_Co ;
+ wire \Inst_eFPGA.Tile_X5Y13_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y13_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y13_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y13_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y13_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y13_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y13_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y13_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y13_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y13_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y14_Co ;
+ wire \Inst_eFPGA.Tile_X5Y14_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y14_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y14_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y14_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y14_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y14_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y14_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y14_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y14_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y14_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y14_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y15_Co ;
+ wire \Inst_eFPGA.Tile_X5Y15_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y15_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y15_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y15_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y15_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y15_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y15_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y15_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y15_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y15_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y16_Co ;
+ wire \Inst_eFPGA.Tile_X5Y16_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y16_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y16_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y16_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y16_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y16_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y16_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y16_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y16_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y16_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y16_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y17_Co ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y17_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y17_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y17_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y1_Co ;
+ wire \Inst_eFPGA.Tile_X5Y1_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y1_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y1_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y1_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y1_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y1_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y1_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y1_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y1_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y1_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y2_Co ;
+ wire \Inst_eFPGA.Tile_X5Y2_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y2_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y2_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y2_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y2_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y2_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y2_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y2_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y2_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y2_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y2_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y3_Co ;
+ wire \Inst_eFPGA.Tile_X5Y3_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y3_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y3_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y3_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y3_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y3_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y3_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y3_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y3_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y3_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y4_Co ;
+ wire \Inst_eFPGA.Tile_X5Y4_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y4_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y4_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y4_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y4_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y4_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y4_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y4_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y4_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y4_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y4_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y5_Co ;
+ wire \Inst_eFPGA.Tile_X5Y5_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y5_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y5_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y5_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y5_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y5_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y5_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y5_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y5_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y5_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y6_Co ;
+ wire \Inst_eFPGA.Tile_X5Y6_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y6_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y6_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y6_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y6_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y6_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y6_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y6_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y6_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y6_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y6_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y7_Co ;
+ wire \Inst_eFPGA.Tile_X5Y7_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y7_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y7_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y7_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y7_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y7_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y7_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y7_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y7_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y7_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y8_Co ;
+ wire \Inst_eFPGA.Tile_X5Y8_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y8_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y8_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y8_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y8_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y8_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y8_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y8_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y8_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y8_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y8_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y9_Co ;
+ wire \Inst_eFPGA.Tile_X5Y9_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y9_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y9_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y9_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y9_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y9_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y9_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X5Y9_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y9_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X5Y9_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y0_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y0_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y0_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y10_Co ;
+ wire \Inst_eFPGA.Tile_X6Y10_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y10_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y10_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y10_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y10_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y10_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y10_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y10_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y10_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y10_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y10_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y11_Co ;
+ wire \Inst_eFPGA.Tile_X6Y11_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y11_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y11_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y11_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y11_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y11_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y11_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y11_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y11_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y11_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y12_Co ;
+ wire \Inst_eFPGA.Tile_X6Y12_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y12_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y12_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y12_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y12_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y12_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y12_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y12_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y12_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y12_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y12_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y13_Co ;
+ wire \Inst_eFPGA.Tile_X6Y13_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y13_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y13_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y13_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y13_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y13_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y13_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y13_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y13_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y13_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y14_Co ;
+ wire \Inst_eFPGA.Tile_X6Y14_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y14_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y14_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y14_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y14_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y14_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y14_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y14_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y14_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y14_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y14_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y15_Co ;
+ wire \Inst_eFPGA.Tile_X6Y15_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y15_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y15_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y15_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y15_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y15_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y15_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y15_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y15_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y15_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y16_Co ;
+ wire \Inst_eFPGA.Tile_X6Y16_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y16_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y16_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y16_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y16_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y16_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y16_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y16_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y16_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y16_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y16_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y17_Co ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y17_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y17_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y17_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y1_Co ;
+ wire \Inst_eFPGA.Tile_X6Y1_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y1_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y1_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y1_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y1_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y1_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y1_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y1_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y1_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y1_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y2_Co ;
+ wire \Inst_eFPGA.Tile_X6Y2_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y2_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y2_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y2_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y2_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y2_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y2_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y2_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y2_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y2_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y2_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y3_Co ;
+ wire \Inst_eFPGA.Tile_X6Y3_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y3_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y3_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y3_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y3_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y3_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y3_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y3_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y3_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y3_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y4_Co ;
+ wire \Inst_eFPGA.Tile_X6Y4_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y4_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y4_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y4_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y4_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y4_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y4_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y4_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y4_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y4_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y4_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y5_Co ;
+ wire \Inst_eFPGA.Tile_X6Y5_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y5_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y5_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y5_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y5_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y5_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y5_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y5_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y5_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y5_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y6_Co ;
+ wire \Inst_eFPGA.Tile_X6Y6_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y6_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y6_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y6_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y6_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y6_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y6_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y6_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y6_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y6_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y6_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y7_Co ;
+ wire \Inst_eFPGA.Tile_X6Y7_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y7_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y7_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y7_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y7_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y7_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y7_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y7_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y7_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y7_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y8_Co ;
+ wire \Inst_eFPGA.Tile_X6Y8_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y8_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y8_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y8_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y8_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y8_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y8_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y8_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y8_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y8_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y8_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y9_Co ;
+ wire \Inst_eFPGA.Tile_X6Y9_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y9_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y9_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y9_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y9_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y9_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y9_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X6Y9_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y9_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X6Y9_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y0_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y0_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y0_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X7Y10_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y10_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y10_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y10_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y10_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y10_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y10_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y11_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y11_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y11_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y11_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X7Y11_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y11_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y11_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y12_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y12_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y12_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y12_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y12_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y12_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y13_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y13_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y13_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y13_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X7Y13_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y13_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y13_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y14_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y14_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y14_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y14_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y14_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y14_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y15_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y15_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y15_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y15_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X7Y15_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y15_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y15_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y16_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y16_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y16_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y16_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y16_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y16_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y17_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y17_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y17_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X7Y1_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y1_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y1_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y1_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y1_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X7Y1_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y1_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y1_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y2_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y2_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y2_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y2_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y2_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y2_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y3_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y3_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y3_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y3_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X7Y3_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y3_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y3_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y4_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y4_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y4_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y4_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y4_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y4_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y5_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y5_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y5_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y5_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X7Y5_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y5_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y5_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y6_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y6_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y6_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y6_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y6_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y6_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y7_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y7_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y7_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y7_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X7Y7_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y7_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y7_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y8_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y8_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y8_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y8_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y8_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y8_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y9_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y9_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y9_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y9_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X7Y9_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y9_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X7Y9_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y0_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y0_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y0_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y10_Co ;
+ wire \Inst_eFPGA.Tile_X8Y10_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y10_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y10_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y10_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y10_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y10_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y10_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y10_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y10_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y10_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y10_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y11_Co ;
+ wire \Inst_eFPGA.Tile_X8Y11_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y11_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y11_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y11_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y11_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y11_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y11_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y11_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y11_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y11_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y12_Co ;
+ wire \Inst_eFPGA.Tile_X8Y12_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y12_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y12_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y12_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y12_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y12_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y12_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y12_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y12_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y12_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y12_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y13_Co ;
+ wire \Inst_eFPGA.Tile_X8Y13_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y13_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y13_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y13_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y13_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y13_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y13_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y13_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y13_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y13_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y14_Co ;
+ wire \Inst_eFPGA.Tile_X8Y14_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y14_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y14_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y14_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y14_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y14_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y14_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y14_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y14_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y14_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y14_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y15_Co ;
+ wire \Inst_eFPGA.Tile_X8Y15_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y15_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y15_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y15_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y15_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y15_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y15_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y15_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y15_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y15_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y16_Co ;
+ wire \Inst_eFPGA.Tile_X8Y16_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y16_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y16_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y16_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y16_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y16_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y16_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y16_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y16_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y16_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y16_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y17_Co ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y17_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y17_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y17_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y1_Co ;
+ wire \Inst_eFPGA.Tile_X8Y1_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y1_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y1_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y1_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y1_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y1_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y1_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y1_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y1_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y1_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y2_Co ;
+ wire \Inst_eFPGA.Tile_X8Y2_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y2_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y2_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y2_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y2_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y2_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y2_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y2_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y2_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y2_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y2_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y3_Co ;
+ wire \Inst_eFPGA.Tile_X8Y3_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y3_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y3_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y3_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y3_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y3_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y3_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y3_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y3_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y3_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y4_Co ;
+ wire \Inst_eFPGA.Tile_X8Y4_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y4_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y4_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y4_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y4_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y4_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y4_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y4_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y4_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y4_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y4_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y5_Co ;
+ wire \Inst_eFPGA.Tile_X8Y5_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y5_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y5_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y5_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y5_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y5_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y5_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y5_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y5_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y5_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y6_Co ;
+ wire \Inst_eFPGA.Tile_X8Y6_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y6_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y6_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y6_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y6_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y6_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y6_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y6_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y6_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y6_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y6_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y7_Co ;
+ wire \Inst_eFPGA.Tile_X8Y7_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y7_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y7_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y7_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y7_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y7_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y7_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y7_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y7_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y7_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y8_Co ;
+ wire \Inst_eFPGA.Tile_X8Y8_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y8_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y8_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y8_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y8_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y8_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y8_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y8_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y8_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y8_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y8_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y9_Co ;
+ wire \Inst_eFPGA.Tile_X8Y9_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y9_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y9_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y9_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y9_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y9_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y9_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X8Y9_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y9_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X8Y9_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y0_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y0_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y0_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y10_Co ;
+ wire \Inst_eFPGA.Tile_X9Y10_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y10_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y10_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y10_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y10_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y10_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y10_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y10_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y10_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y10_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y10_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y11_Co ;
+ wire \Inst_eFPGA.Tile_X9Y11_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y11_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y11_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y11_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y11_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y11_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y11_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y11_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y11_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y11_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y11_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y12_Co ;
+ wire \Inst_eFPGA.Tile_X9Y12_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y12_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y12_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y12_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y12_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y12_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y12_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y12_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y12_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y12_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y12_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y13_Co ;
+ wire \Inst_eFPGA.Tile_X9Y13_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y13_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y13_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y13_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y13_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y13_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y13_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y13_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y13_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y13_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y13_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y14_Co ;
+ wire \Inst_eFPGA.Tile_X9Y14_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y14_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y14_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y14_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y14_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y14_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y14_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y14_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y14_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y14_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y14_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y15_Co ;
+ wire \Inst_eFPGA.Tile_X9Y15_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y15_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y15_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y15_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y15_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y15_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y15_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y15_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y15_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y15_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y15_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y16_Co ;
+ wire \Inst_eFPGA.Tile_X9Y16_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y16_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y16_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y16_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y16_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y16_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y16_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y16_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y16_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y16_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y16_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y17_Co ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y17_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y17_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y17_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y1_Co ;
+ wire \Inst_eFPGA.Tile_X9Y1_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y1_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y1_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y1_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y1_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y1_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y1_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y1_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y1_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y1_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y1_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y2_Co ;
+ wire \Inst_eFPGA.Tile_X9Y2_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y2_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y2_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y2_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y2_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y2_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y2_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y2_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y2_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y2_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y2_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y3_Co ;
+ wire \Inst_eFPGA.Tile_X9Y3_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y3_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y3_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y3_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y3_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y3_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y3_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y3_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y3_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y3_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y3_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y4_Co ;
+ wire \Inst_eFPGA.Tile_X9Y4_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y4_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y4_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y4_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y4_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y4_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y4_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y4_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y4_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y4_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y4_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y5_Co ;
+ wire \Inst_eFPGA.Tile_X9Y5_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y5_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y5_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y5_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y5_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y5_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y5_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y5_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y5_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y5_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y5_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y6_Co ;
+ wire \Inst_eFPGA.Tile_X9Y6_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y6_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y6_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y6_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y6_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y6_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y6_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y6_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y6_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y6_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y6_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y7_Co ;
+ wire \Inst_eFPGA.Tile_X9Y7_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y7_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y7_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y7_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y7_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y7_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y7_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y7_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y7_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y7_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y7_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y8_Co ;
+ wire \Inst_eFPGA.Tile_X9Y8_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y8_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y8_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y8_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y8_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y8_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y8_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y8_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y8_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y8_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y8_WW4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y9_Co ;
+ wire \Inst_eFPGA.Tile_X9Y9_E1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y9_E6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y9_EE4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[20] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[21] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[22] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[23] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[24] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[25] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[26] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[27] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[28] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[29] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[30] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[31] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameData_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[10] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[11] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[12] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[13] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[14] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[15] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[16] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[17] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[18] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[19] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[8] ;
+ wire \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[9] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y9_N4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y9_NN4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y9_S4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y9_SS4BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y9_UserCLKo ;
+ wire \Inst_eFPGA.Tile_X9Y9_W1BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W1BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W1BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W1BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEGb[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEGb[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEGb[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEGb[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEGb[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEGb[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEGb[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W2BEGb[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y9_W6BEG[9] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[0] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[10] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[11] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[12] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[13] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[14] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[15] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[1] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[2] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[3] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[4] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[5] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[6] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[7] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[8] ;
+ wire \Inst_eFPGA.Tile_X9Y9_WW4BEG[9] ;
+ wire config_strobe_reg1;
+ wire config_strobe_reg2;
+ wire config_strobe_reg3;
+ wire fabric_strobe_reg1;
+ wire fabric_strobe_reg2;
+ wire fabric_strobe_reg3;
+ wire latch_config_strobe;
+ wire latch_fabric_strobe;
+ wire \to_fabric_addr.A1 ;
+ wire \to_fabric_io_0.A1 ;
+ wire \to_fabric_io_1.A1 ;
+ wire \to_fabric_io_10.A1 ;
+ wire \to_fabric_io_11.A1 ;
+ wire \to_fabric_io_12.A1 ;
+ wire \to_fabric_io_13.A1 ;
+ wire \to_fabric_io_14.A1 ;
+ wire \to_fabric_io_15.A1 ;
+ wire \to_fabric_io_2.A1 ;
+ wire \to_fabric_io_3.A1 ;
+ wire \to_fabric_io_4.A1 ;
+ wire \to_fabric_io_5.A1 ;
+ wire \to_fabric_io_6.A1 ;
+ wire \to_fabric_io_7.A1 ;
+ wire \to_fabric_io_8.A1 ;
+ wire \to_fabric_io_9.A1 ;
+
+ assign la_data_out[1] = io_in[5] ;
+ assign io_out[6] = FE_RN_1 ;
+
+ sky130_fd_sc_hd__inv_2 FE_OFC185_FE_OFN72_la_data_out_3 (.A(FE_OFN184_FE_OFN72_la_data_out_3),
+ .Y(FE_OFN185_FE_OFN72_la_data_out_3));
+ sky130_fd_sc_hd__inv_2 FE_OFC184_FE_OFN72_la_data_out_3 (.A(FE_OFN72_la_data_out_3),
+ .Y(FE_OFN184_FE_OFN72_la_data_out_3));
+ sky130_fd_sc_hd__inv_2 FE_OFC183_FE_OFN70_la_data_out_4 (.A(FE_OFN182_FE_OFN70_la_data_out_4),
+ .Y(FE_OFN183_FE_OFN70_la_data_out_4));
+ sky130_fd_sc_hd__inv_2 FE_OFC182_FE_OFN70_la_data_out_4 (.A(FE_OFN70_la_data_out_4),
+ .Y(FE_OFN182_FE_OFN70_la_data_out_4));
+ sky130_fd_sc_hd__xnor2_1 FE_RC_5_0 (.A(_1628_),
+ .B(_1750_),
+ .Y(_0176_));
+ sky130_fd_sc_hd__or3_2 FE_RC_4_0 (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[2] ),
+ .B(_1101_),
+ .C(\Config_inst.ConfigFSM_inst.FrameShiftState[3] ),
+ .X(_1331_));
+ sky130_fd_sc_hd__o21a_1 FE_RC_3_0 (.A1(_1098_),
+ .A2(_1099_),
+ .B1(_0011_),
+ .X(_1187_));
+ sky130_fd_sc_hd__xnor2_1 FE_RC_2_0 (.A(_0968_),
+ .B(_0027_),
+ .Y(_0970_));
+ sky130_fd_sc_hd__xor2_1 FE_RC_1_0 (.A(\Config_inst.INST_config_UART.CRCReg[5] ),
+ .B(_0035_),
+ .X(_0961_));
+ sky130_fd_sc_hd__xnor2_1 FE_RC_0_0 (.A(\Config_inst.Command[1] ),
+ .B(\Config_inst.Command[0] ),
+ .Y(_1678_));
+ sky130_fd_sc_hd__clkinv_16 CTS_cpc_drv_inv_00160 (.A(CTS_41),
+ .Y(CTS_40));
+ sky130_fd_sc_hd__clkinv_4 CTS_cpc_drv_inv_00159 (.A(CTS_17),
+ .Y(CTS_41));
+ sky130_fd_sc_hd__clkinv_16 CTS_cpc_drv_inv_00154 (.A(CTS_39),
+ .Y(CTS_38));
+ sky130_fd_sc_hd__clkinv_4 CTS_cpc_drv_inv_00153 (.A(CTS_26),
+ .Y(CTS_39));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_a_inv_00121 (.A(CTS_29),
+ .Y(CTS_35));
+ sky130_fd_sc_hd__clkinv_4 CTS_ccl_a_inv_00124 (.A(\Config_inst.CLK ),
+ .Y(CTS_29));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_a_inv_00076 (.A(CTS_23),
+ .Y(CTS_25));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_a_inv_00066 (.A(CTS_23),
+ .Y(CTS_30));
+ sky130_fd_sc_hd__clkinv_4 CTS_ccl_inv_00104 (.A(CTS_31),
+ .Y(CTS_23));
+ sky130_fd_sc_hd__clkinv_4 CTS_cdb_inv_00148 (.A(CTS_32),
+ .Y(CTS_31));
+ sky130_fd_sc_hd__clkinv_4 CTS_cdb_inv_00147 (.A(CTS_33),
+ .Y(CTS_32));
+ sky130_fd_sc_hd__clkinv_4 CTS_ccl_a_inv_00078 (.A(CTS_20),
+ .Y(CTS_18));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_a_inv_00070 (.A(CTS_20),
+ .Y(CTS_16));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_a_inv_00046 (.A(CTS_20),
+ .Y(CTS_22));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_a_inv_00044 (.A(CTS_20),
+ .Y(CTS_19));
+ sky130_fd_sc_hd__clkinv_16 CTS_cfo_inv_00143 (.A(CTS_27),
+ .Y(CTS_20));
+ sky130_fd_sc_hd__clkinv_8 CTS_cfo_inv_00144 (.A(CTS_28),
+ .Y(CTS_27));
+ sky130_fd_sc_hd__clkinv_4 CTS_ccl_a_inv_00074 (.A(CTS_28),
+ .Y(CTS_17));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_a_inv_00068 (.A(CTS_28),
+ .Y(CTS_26));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_inv_00102 (.A(CTS_33),
+ .Y(CTS_28));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_inv_00111 (.A(CTS_34),
+ .Y(CTS_33));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_inv_00118 (.A(\Config_inst.CLK ),
+ .Y(CTS_34));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_a_inv_00064 (.A(CTS_11),
+ .Y(CTS_10));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_a_inv_00054 (.A(CTS_11),
+ .Y(CTS_9));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_a_inv_00050 (.A(CTS_11),
+ .Y(CTS_13));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_a_inv_00048 (.A(CTS_11),
+ .Y(CTS_15));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_inv_00106 (.A(CTS_21),
+ .Y(CTS_11));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_a_inv_00072 (.A(CTS_6),
+ .Y(CTS_5));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_a_inv_00060 (.A(CTS_6),
+ .Y(CTS_8));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_a_inv_00056 (.A(CTS_6),
+ .Y(CTS_14));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_inv_00105 (.A(CTS_21),
+ .Y(CTS_6));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_a_inv_00052 (.A(CTS_4),
+ .Y(CTS_2));
+ sky130_fd_sc_hd__clkinv_4 CTS_cdb_inv_00146 (.A(CTS_7),
+ .Y(CTS_4));
+ sky130_fd_sc_hd__clkinv_4 CTS_cdb_inv_00145 (.A(CTS_12),
+ .Y(CTS_7));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_a_inv_00062 (.A(CTS_12),
+ .Y(CTS_1));
+ sky130_fd_sc_hd__clkinv_8 CTS_ccl_a_inv_00058 (.A(CTS_12),
+ .Y(CTS_3));
+ sky130_fd_sc_hd__clkinv_4 CTS_ccl_inv_00103 (.A(CTS_21),
+ .Y(CTS_12));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_inv_00110 (.A(CTS_24),
+ .Y(CTS_21));
+ sky130_fd_sc_hd__clkinv_16 CTS_ccl_inv_00117 (.A(\Config_inst.CLK ),
+ .Y(CTS_24));
+ sky130_fd_sc_hd__clkinv_16 CTS_cid_inv_00131 (.A(CTS_37),
+ .Y(CTS_36));
+ sky130_fd_sc_hd__clkinv_16 CTS_cid_inv_00132 (.A(_1976_),
+ .Y(CTS_37));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30 (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[30] ),
+ .X(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29 (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[29] ),
+ .X(FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29));
+ sky130_fd_sc_hd__buf_2 FE_OFC177_1599 (.A(_1599_),
+ .X(FE_OFN177_1599));
+ sky130_fd_sc_hd__inv_2 FE_OFC176_Inst_eFPGA_Tile_X0Y12_A_O_top (.A(FE_OFN175_Inst_eFPGA_Tile_X0Y12_A_O_top),
+ .Y(FE_OFN176_Inst_eFPGA_Tile_X0Y12_A_O_top));
+ sky130_fd_sc_hd__inv_2 FE_OFC175_Inst_eFPGA_Tile_X0Y12_A_O_top (.A(FE_OFN174_Inst_eFPGA_Tile_X0Y12_A_O_top),
+ .Y(FE_OFN175_Inst_eFPGA_Tile_X0Y12_A_O_top));
+ sky130_fd_sc_hd__inv_2 FE_OFC174_Inst_eFPGA_Tile_X0Y12_A_O_top (.A(FE_OFN173_Inst_eFPGA_Tile_X0Y12_A_O_top),
+ .Y(FE_OFN174_Inst_eFPGA_Tile_X0Y12_A_O_top));
+ sky130_fd_sc_hd__inv_2 FE_OFC173_Inst_eFPGA_Tile_X0Y12_A_O_top (.A(\Inst_eFPGA.Tile_X0Y12_A_O_top ),
+ .Y(FE_OFN173_Inst_eFPGA_Tile_X0Y12_A_O_top));
+ sky130_fd_sc_hd__buf_2 FE_OFC172_Inst_Frame_Select_0_FrameStrobe_O_3 (.A(\Inst_Frame_Select_0.FrameStrobe_O[3] ),
+ .X(FE_OFN172_Inst_Frame_Select_0_FrameStrobe_O_3));
+ sky130_fd_sc_hd__buf_2 FE_OFC171_Inst_Frame_Select_0_FrameStrobe_O_2 (.A(\Inst_Frame_Select_0.FrameStrobe_O[2] ),
+ .X(FE_OFN171_Inst_Frame_Select_0_FrameStrobe_O_2));
+ sky130_fd_sc_hd__buf_2 FE_OFC170_Inst_Frame_Select_0_FrameStrobe_O_1 (.A(\Inst_Frame_Select_0.FrameStrobe_O[1] ),
+ .X(FE_OFN170_Inst_Frame_Select_0_FrameStrobe_O_1));
+ sky130_fd_sc_hd__buf_2 FE_OFC169_Inst_Frame_Select_0_FrameStrobe_O_0 (.A(\Inst_Frame_Select_0.FrameStrobe_O[0] ),
+ .X(FE_OFN169_Inst_Frame_Select_0_FrameStrobe_O_0));
+ sky130_fd_sc_hd__inv_4 FE_OFC168_Config_inst_ConfigFSM_inst_WriteData_9 (.A(FE_OFN167_Config_inst_ConfigFSM_inst_WriteData_9),
+ .Y(FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9));
+ sky130_fd_sc_hd__inv_2 FE_OFC167_Config_inst_ConfigFSM_inst_WriteData_9 (.A(\Config_inst.ConfigFSM_inst.WriteData[9] ),
+ .Y(FE_OFN167_Config_inst_ConfigFSM_inst_WriteData_9));
+ sky130_fd_sc_hd__buf_4 FE_OFC166_Config_inst_ConfigFSM_inst_WriteData_8 (.A(\Config_inst.ConfigFSM_inst.WriteData[8] ),
+ .X(FE_OFN166_Config_inst_ConfigFSM_inst_WriteData_8));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC165_Config_inst_ConfigFSM_inst_WriteData_8 (.A(\Config_inst.ConfigFSM_inst.WriteData[8] ),
+ .X(FE_OFN165_Config_inst_ConfigFSM_inst_WriteData_8));
+ sky130_fd_sc_hd__buf_4 FE_OFC164_Config_inst_ConfigFSM_inst_WriteData_7 (.A(\Config_inst.ConfigFSM_inst.WriteData[7] ),
+ .X(FE_OFN164_Config_inst_ConfigFSM_inst_WriteData_7));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC163_Config_inst_ConfigFSM_inst_WriteData_7 (.A(\Config_inst.ConfigFSM_inst.WriteData[7] ),
+ .X(FE_OFN163_Config_inst_ConfigFSM_inst_WriteData_7));
+ sky130_fd_sc_hd__inv_4 FE_OFC162_Config_inst_ConfigFSM_inst_WriteData_6 (.A(FE_OFN161_Config_inst_ConfigFSM_inst_WriteData_6),
+ .Y(FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6));
+ sky130_fd_sc_hd__inv_2 FE_OFC161_Config_inst_ConfigFSM_inst_WriteData_6 (.A(\Config_inst.ConfigFSM_inst.WriteData[6] ),
+ .Y(FE_OFN161_Config_inst_ConfigFSM_inst_WriteData_6));
+ sky130_fd_sc_hd__inv_4 FE_OFC160_Config_inst_ConfigFSM_inst_WriteData_5 (.A(FE_OFN159_Config_inst_ConfigFSM_inst_WriteData_5),
+ .Y(FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5));
+ sky130_fd_sc_hd__inv_2 FE_OFC159_Config_inst_ConfigFSM_inst_WriteData_5 (.A(\Config_inst.ConfigFSM_inst.WriteData[5] ),
+ .Y(FE_OFN159_Config_inst_ConfigFSM_inst_WriteData_5));
+ sky130_fd_sc_hd__inv_4 FE_OFC158_Config_inst_ConfigFSM_inst_WriteData_4 (.A(FE_OFN157_Config_inst_ConfigFSM_inst_WriteData_4),
+ .Y(FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4));
+ sky130_fd_sc_hd__inv_2 FE_OFC157_Config_inst_ConfigFSM_inst_WriteData_4 (.A(\Config_inst.ConfigFSM_inst.WriteData[4] ),
+ .Y(FE_OFN157_Config_inst_ConfigFSM_inst_WriteData_4));
+ sky130_fd_sc_hd__inv_4 FE_OFC156_Config_inst_ConfigFSM_inst_WriteData_3 (.A(FE_OFN155_Config_inst_ConfigFSM_inst_WriteData_3),
+ .Y(FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3));
+ sky130_fd_sc_hd__inv_2 FE_OFC155_Config_inst_ConfigFSM_inst_WriteData_3 (.A(\Config_inst.ConfigFSM_inst.WriteData[3] ),
+ .Y(FE_OFN155_Config_inst_ConfigFSM_inst_WriteData_3));
+ sky130_fd_sc_hd__buf_4 FE_OFC154_Config_inst_ConfigFSM_inst_WriteData_31 (.A(\Config_inst.ConfigFSM_inst.WriteData[31] ),
+ .X(FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC153_Config_inst_ConfigFSM_inst_WriteData_31 (.A(\Config_inst.ConfigFSM_inst.WriteData[31] ),
+ .X(FE_OFN153_Config_inst_ConfigFSM_inst_WriteData_31));
+ sky130_fd_sc_hd__buf_4 FE_OFC152_Config_inst_ConfigFSM_inst_WriteData_30 (.A(\Config_inst.ConfigFSM_inst.WriteData[30] ),
+ .X(FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC151_Config_inst_ConfigFSM_inst_WriteData_30 (.A(\Config_inst.ConfigFSM_inst.WriteData[30] ),
+ .X(FE_OFN151_Config_inst_ConfigFSM_inst_WriteData_30));
+ sky130_fd_sc_hd__buf_4 FE_OFC150_Config_inst_ConfigFSM_inst_WriteData_2 (.A(\Config_inst.ConfigFSM_inst.WriteData[2] ),
+ .X(FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2));
+ sky130_fd_sc_hd__buf_4 FE_OFC149_Config_inst_ConfigFSM_inst_WriteData_29 (.A(\Config_inst.ConfigFSM_inst.WriteData[29] ),
+ .X(FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC148_Config_inst_ConfigFSM_inst_WriteData_29 (.A(\Config_inst.ConfigFSM_inst.WriteData[29] ),
+ .X(FE_OFN148_Config_inst_ConfigFSM_inst_WriteData_29));
+ sky130_fd_sc_hd__buf_4 FE_OFC147_Config_inst_ConfigFSM_inst_WriteData_28 (.A(\Config_inst.ConfigFSM_inst.WriteData[28] ),
+ .X(FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC146_Config_inst_ConfigFSM_inst_WriteData_28 (.A(\Config_inst.ConfigFSM_inst.WriteData[28] ),
+ .X(FE_OFN146_Config_inst_ConfigFSM_inst_WriteData_28));
+ sky130_fd_sc_hd__buf_4 FE_OFC145_Config_inst_ConfigFSM_inst_WriteData_27 (.A(\Config_inst.ConfigFSM_inst.WriteData[27] ),
+ .X(FE_OFN145_Config_inst_ConfigFSM_inst_WriteData_27));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC144_Config_inst_ConfigFSM_inst_WriteData_27 (.A(\Config_inst.ConfigFSM_inst.WriteData[27] ),
+ .X(FE_OFN144_Config_inst_ConfigFSM_inst_WriteData_27));
+ sky130_fd_sc_hd__buf_4 FE_OFC143_Config_inst_ConfigFSM_inst_WriteData_26 (.A(\Config_inst.ConfigFSM_inst.WriteData[26] ),
+ .X(FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26));
+ sky130_fd_sc_hd__buf_4 FE_OFC142_Config_inst_ConfigFSM_inst_WriteData_25 (.A(\Config_inst.ConfigFSM_inst.WriteData[25] ),
+ .X(FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC141_Config_inst_ConfigFSM_inst_WriteData_24 (.A(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24),
+ .X(FE_OFN141_Config_inst_ConfigFSM_inst_WriteData_24));
+ sky130_fd_sc_hd__buf_4 FE_OFC140_Config_inst_ConfigFSM_inst_WriteData_24 (.A(\Config_inst.ConfigFSM_inst.WriteData[24] ),
+ .X(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24));
+ sky130_fd_sc_hd__buf_4 FE_OFC139_Config_inst_ConfigFSM_inst_WriteData_23 (.A(\Config_inst.ConfigFSM_inst.WriteData[23] ),
+ .X(FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23));
+ sky130_fd_sc_hd__inv_4 FE_OFC138_Config_inst_ConfigFSM_inst_WriteData_22 (.A(FE_OFN137_Config_inst_ConfigFSM_inst_WriteData_22),
+ .Y(FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22));
+ sky130_fd_sc_hd__inv_2 FE_OFC137_Config_inst_ConfigFSM_inst_WriteData_22 (.A(\Config_inst.ConfigFSM_inst.WriteData[22] ),
+ .Y(FE_OFN137_Config_inst_ConfigFSM_inst_WriteData_22));
+ sky130_fd_sc_hd__inv_4 FE_OFC136_Config_inst_ConfigFSM_inst_WriteData_21 (.A(FE_OFN135_Config_inst_ConfigFSM_inst_WriteData_21),
+ .Y(FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21));
+ sky130_fd_sc_hd__inv_2 FE_OFC135_Config_inst_ConfigFSM_inst_WriteData_21 (.A(\Config_inst.ConfigFSM_inst.WriteData[21] ),
+ .Y(FE_OFN135_Config_inst_ConfigFSM_inst_WriteData_21));
+ sky130_fd_sc_hd__inv_4 FE_OFC134_Config_inst_ConfigFSM_inst_WriteData_20 (.A(FE_OFN133_Config_inst_ConfigFSM_inst_WriteData_20),
+ .Y(FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20));
+ sky130_fd_sc_hd__inv_2 FE_OFC133_Config_inst_ConfigFSM_inst_WriteData_20 (.A(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .Y(FE_OFN133_Config_inst_ConfigFSM_inst_WriteData_20));
+ sky130_fd_sc_hd__buf_4 FE_OFC132_Config_inst_ConfigFSM_inst_WriteData_1 (.A(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .X(FE_OFN132_Config_inst_ConfigFSM_inst_WriteData_1));
+ sky130_fd_sc_hd__buf_4 FE_OFC131_Config_inst_ConfigFSM_inst_WriteData_1 (.A(\Config_inst.ConfigFSM_inst.WriteData[1] ),
+ .X(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1));
+ sky130_fd_sc_hd__buf_4 FE_OFC130_Config_inst_ConfigFSM_inst_WriteData_19 (.A(\Config_inst.ConfigFSM_inst.WriteData[19] ),
+ .X(FE_OFN130_Config_inst_ConfigFSM_inst_WriteData_19));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC129_Config_inst_ConfigFSM_inst_WriteData_19 (.A(\Config_inst.ConfigFSM_inst.WriteData[19] ),
+ .X(FE_OFN129_Config_inst_ConfigFSM_inst_WriteData_19));
+ sky130_fd_sc_hd__buf_4 FE_OFC128_Config_inst_ConfigFSM_inst_WriteData_18 (.A(\Config_inst.ConfigFSM_inst.WriteData[18] ),
+ .X(FE_OFN128_Config_inst_ConfigFSM_inst_WriteData_18));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC127_Config_inst_ConfigFSM_inst_WriteData_18 (.A(\Config_inst.ConfigFSM_inst.WriteData[18] ),
+ .X(FE_OFN127_Config_inst_ConfigFSM_inst_WriteData_18));
+ sky130_fd_sc_hd__buf_4 FE_OFC126_Config_inst_ConfigFSM_inst_WriteData_17 (.A(\Config_inst.ConfigFSM_inst.WriteData[17] ),
+ .X(FE_OFN126_Config_inst_ConfigFSM_inst_WriteData_17));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC125_Config_inst_ConfigFSM_inst_WriteData_17 (.A(\Config_inst.ConfigFSM_inst.WriteData[17] ),
+ .X(FE_OFN125_Config_inst_ConfigFSM_inst_WriteData_17));
+ sky130_fd_sc_hd__buf_4 FE_OFC124_Config_inst_ConfigFSM_inst_WriteData_16 (.A(\Config_inst.ConfigFSM_inst.WriteData[16] ),
+ .X(FE_OFN124_Config_inst_ConfigFSM_inst_WriteData_16));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC123_Config_inst_ConfigFSM_inst_WriteData_16 (.A(\Config_inst.ConfigFSM_inst.WriteData[16] ),
+ .X(FE_OFN123_Config_inst_ConfigFSM_inst_WriteData_16));
+ sky130_fd_sc_hd__inv_4 FE_OFC122_Config_inst_ConfigFSM_inst_WriteData_15 (.A(FE_OFN121_Config_inst_ConfigFSM_inst_WriteData_15),
+ .Y(FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15));
+ sky130_fd_sc_hd__inv_2 FE_OFC121_Config_inst_ConfigFSM_inst_WriteData_15 (.A(\Config_inst.ConfigFSM_inst.WriteData[15] ),
+ .Y(FE_OFN121_Config_inst_ConfigFSM_inst_WriteData_15));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC120_Config_inst_ConfigFSM_inst_WriteData_14 (.A(\Config_inst.ConfigFSM_inst.WriteData[14] ),
+ .X(FE_OFN120_Config_inst_ConfigFSM_inst_WriteData_14));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC119_Config_inst_ConfigFSM_inst_WriteData_14 (.A(\Config_inst.ConfigFSM_inst.WriteData[14] ),
+ .X(FE_OFN119_Config_inst_ConfigFSM_inst_WriteData_14));
+ sky130_fd_sc_hd__inv_4 FE_OFC118_Config_inst_ConfigFSM_inst_WriteData_13 (.A(FE_OFN117_Config_inst_ConfigFSM_inst_WriteData_13),
+ .Y(FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13));
+ sky130_fd_sc_hd__inv_2 FE_OFC117_Config_inst_ConfigFSM_inst_WriteData_13 (.A(\Config_inst.ConfigFSM_inst.WriteData[13] ),
+ .Y(FE_OFN117_Config_inst_ConfigFSM_inst_WriteData_13));
+ sky130_fd_sc_hd__buf_4 FE_OFC116_Config_inst_ConfigFSM_inst_WriteData_12 (.A(\Config_inst.ConfigFSM_inst.WriteData[12] ),
+ .X(FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC115_Config_inst_ConfigFSM_inst_WriteData_12 (.A(\Config_inst.ConfigFSM_inst.WriteData[12] ),
+ .X(FE_OFN115_Config_inst_ConfigFSM_inst_WriteData_12));
+ sky130_fd_sc_hd__inv_4 FE_OFC114_Config_inst_ConfigFSM_inst_WriteData_11 (.A(FE_OFN113_Config_inst_ConfigFSM_inst_WriteData_11),
+ .Y(FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11));
+ sky130_fd_sc_hd__inv_2 FE_OFC113_Config_inst_ConfigFSM_inst_WriteData_11 (.A(\Config_inst.ConfigFSM_inst.WriteData[11] ),
+ .Y(FE_OFN113_Config_inst_ConfigFSM_inst_WriteData_11));
+ sky130_fd_sc_hd__inv_4 FE_OFC112_Config_inst_ConfigFSM_inst_WriteData_10 (.A(FE_OFN111_Config_inst_ConfigFSM_inst_WriteData_10),
+ .Y(FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10));
+ sky130_fd_sc_hd__inv_2 FE_OFC111_Config_inst_ConfigFSM_inst_WriteData_10 (.A(\Config_inst.ConfigFSM_inst.WriteData[10] ),
+ .Y(FE_OFN111_Config_inst_ConfigFSM_inst_WriteData_10));
+ sky130_fd_sc_hd__buf_4 FE_OFC110_Config_inst_ConfigFSM_inst_WriteData_0 (.A(\Config_inst.ConfigFSM_inst.WriteData[0] ),
+ .X(FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0));
+ sky130_fd_sc_hd__buf_8 FE_OFC109_wbs_dat_o_0 (.A(FE_OFN109_wbs_dat_o_0),
+ .X(wbs_dat_o[0]));
+ sky130_fd_sc_hd__buf_8 FE_OFC108_wbs_dat_o_1 (.A(FE_OFN108_wbs_dat_o_1),
+ .X(wbs_dat_o[1]));
+ sky130_fd_sc_hd__buf_8 FE_OFC107_wbs_dat_o_2 (.A(FE_OFN107_wbs_dat_o_2),
+ .X(wbs_dat_o[2]));
+ sky130_fd_sc_hd__buf_8 FE_OFC106_wbs_dat_o_3 (.A(FE_OFN106_wbs_dat_o_3),
+ .X(wbs_dat_o[3]));
+ sky130_fd_sc_hd__buf_8 FE_OFC105_wbs_dat_o_4 (.A(FE_OFN105_wbs_dat_o_4),
+ .X(wbs_dat_o[4]));
+ sky130_fd_sc_hd__buf_8 FE_OFC104_wbs_dat_o_5 (.A(FE_OFN104_wbs_dat_o_5),
+ .X(wbs_dat_o[5]));
+ sky130_fd_sc_hd__buf_8 FE_OFC103_wbs_dat_o_6 (.A(FE_OFN103_wbs_dat_o_6),
+ .X(wbs_dat_o[6]));
+ sky130_fd_sc_hd__buf_8 FE_OFC102_wbs_dat_o_7 (.A(FE_OFN102_wbs_dat_o_7),
+ .X(wbs_dat_o[7]));
+ sky130_fd_sc_hd__buf_8 FE_OFC101_wbs_dat_o_8 (.A(FE_OFN101_wbs_dat_o_8),
+ .X(wbs_dat_o[8]));
+ sky130_fd_sc_hd__buf_8 FE_OFC100_wbs_dat_o_9 (.A(FE_OFN100_wbs_dat_o_9),
+ .X(wbs_dat_o[9]));
+ sky130_fd_sc_hd__buf_8 FE_OFC99_wbs_dat_o_10 (.A(FE_OFN99_wbs_dat_o_10),
+ .X(wbs_dat_o[10]));
+ sky130_fd_sc_hd__buf_8 FE_OFC98_wbs_dat_o_11 (.A(FE_OFN98_wbs_dat_o_11),
+ .X(wbs_dat_o[11]));
+ sky130_fd_sc_hd__buf_8 FE_OFC97_wbs_dat_o_12 (.A(FE_OFN97_wbs_dat_o_12),
+ .X(wbs_dat_o[12]));
+ sky130_fd_sc_hd__buf_8 FE_OFC96_wbs_dat_o_13 (.A(FE_OFN96_wbs_dat_o_13),
+ .X(wbs_dat_o[13]));
+ sky130_fd_sc_hd__buf_8 FE_OFC95_wbs_dat_o_14 (.A(FE_OFN95_wbs_dat_o_14),
+ .X(wbs_dat_o[14]));
+ sky130_fd_sc_hd__buf_8 FE_OFC94_wbs_dat_o_15 (.A(FE_OFN94_wbs_dat_o_15),
+ .X(wbs_dat_o[15]));
+ sky130_fd_sc_hd__buf_8 FE_OFC93_wbs_dat_o_16 (.A(FE_OFN93_wbs_dat_o_16),
+ .X(wbs_dat_o[16]));
+ sky130_fd_sc_hd__buf_8 FE_OFC92_wbs_dat_o_17 (.A(FE_OFN92_wbs_dat_o_17),
+ .X(wbs_dat_o[17]));
+ sky130_fd_sc_hd__buf_8 FE_OFC91_wbs_dat_o_18 (.A(FE_OFN91_wbs_dat_o_18),
+ .X(wbs_dat_o[18]));
+ sky130_fd_sc_hd__buf_8 FE_OFC90_wbs_dat_o_19 (.A(FE_OFN90_wbs_dat_o_19),
+ .X(wbs_dat_o[19]));
+ sky130_fd_sc_hd__buf_8 FE_OFC89_wbs_dat_o_20 (.A(FE_OFN89_wbs_dat_o_20),
+ .X(wbs_dat_o[20]));
+ sky130_fd_sc_hd__buf_8 FE_OFC88_wbs_dat_o_21 (.A(FE_OFN88_wbs_dat_o_21),
+ .X(wbs_dat_o[21]));
+ sky130_fd_sc_hd__buf_8 FE_OFC87_wbs_dat_o_22 (.A(FE_OFN87_wbs_dat_o_22),
+ .X(wbs_dat_o[22]));
+ sky130_fd_sc_hd__buf_8 FE_OFC86_wbs_dat_o_23 (.A(FE_OFN86_wbs_dat_o_23),
+ .X(wbs_dat_o[23]));
+ sky130_fd_sc_hd__buf_8 FE_OFC85_wbs_dat_o_24 (.A(FE_OFN85_wbs_dat_o_24),
+ .X(wbs_dat_o[24]));
+ sky130_fd_sc_hd__buf_8 FE_OFC84_wbs_dat_o_25 (.A(FE_OFN84_wbs_dat_o_25),
+ .X(wbs_dat_o[25]));
+ sky130_fd_sc_hd__buf_8 FE_OFC83_wbs_dat_o_26 (.A(FE_OFN83_wbs_dat_o_26),
+ .X(wbs_dat_o[26]));
+ sky130_fd_sc_hd__buf_8 FE_OFC82_wbs_dat_o_27 (.A(FE_OFN82_wbs_dat_o_27),
+ .X(wbs_dat_o[27]));
+ sky130_fd_sc_hd__buf_8 FE_OFC81_wbs_dat_o_28 (.A(FE_OFN81_wbs_dat_o_28),
+ .X(wbs_dat_o[28]));
+ sky130_fd_sc_hd__buf_8 FE_OFC80_wbs_dat_o_29 (.A(FE_OFN80_wbs_dat_o_29),
+ .X(wbs_dat_o[29]));
+ sky130_fd_sc_hd__buf_8 FE_OFC79_wbs_dat_o_30 (.A(FE_OFN79_wbs_dat_o_30),
+ .X(wbs_dat_o[30]));
+ sky130_fd_sc_hd__buf_8 FE_OFC78_wbs_dat_o_31 (.A(FE_OFN78_wbs_dat_o_31),
+ .X(wbs_dat_o[31]));
+ sky130_fd_sc_hd__inv_2 FE_OFC77_wb_clk_i (.A(FE_OFN76_wb_clk_i),
+ .Y(FE_OFN77_wb_clk_i));
+ sky130_fd_sc_hd__inv_6 FE_OFC76_wb_clk_i (.A(wb_clk_i),
+ .Y(FE_OFN76_wb_clk_i));
+ sky130_fd_sc_hd__buf_8 FE_OFC75_la_data_out_0 (.A(FE_OFN75_la_data_out_0),
+ .X(la_data_out[0]));
+ sky130_fd_sc_hd__buf_4 FE_OFC74_la_data_out_0 (.A(FE_OFN74_la_data_out_0),
+ .X(FE_OFN75_la_data_out_0));
+ sky130_fd_sc_hd__buf_8 FE_OFC73_la_data_out_3 (.A(FE_OFN185_FE_OFN72_la_data_out_3),
+ .X(la_data_out[3]));
+ sky130_fd_sc_hd__buf_8 FE_OFC71_la_data_out_4 (.A(FE_OFN183_FE_OFN70_la_data_out_4),
+ .X(la_data_out[4]));
+ sky130_fd_sc_hd__buf_8 FE_OFC69_io_out_0 (.A(FE_OFN69_io_out_0),
+ .X(io_out[0]));
+ sky130_fd_sc_hd__buf_8 FE_OFC68_io_out_1 (.A(FE_OFN68_io_out_1),
+ .X(io_out[1]));
+ sky130_fd_sc_hd__buf_8 FE_OFC67_io_out_2 (.A(FE_OFN67_io_out_2),
+ .X(io_out[2]));
+ sky130_fd_sc_hd__buf_8 FE_OFC66_io_out_3 (.A(FE_OFN66_io_out_3),
+ .X(io_out[3]));
+ sky130_fd_sc_hd__buf_8 FE_OFC65_io_out_4 (.A(FE_OFN65_io_out_4),
+ .X(io_out[4]));
+ sky130_fd_sc_hd__buf_8 FE_OFC64_io_out_5 (.A(FE_OFN64_io_out_5),
+ .X(io_out[5]));
+ sky130_fd_sc_hd__buf_8 FE_OFC63_io_out_6 (.A(FE_OFN62_io_out_6),
+ .X(la_data_out[2]));
+ sky130_fd_sc_hd__buf_8 FE_OFC62_io_out_6 (.A(FE_OFN62_io_out_6),
+ .X(FE_RN_1));
+ sky130_fd_sc_hd__buf_8 FE_OFC61_io_out_6 (.A(FE_OFN61_io_out_6),
+ .X(FE_OFN62_io_out_6));
+ sky130_fd_sc_hd__buf_8 FE_OFC60_io_oeb_0 (.A(FE_OFN60_io_oeb_0),
+ .X(io_oeb[0]));
+ sky130_fd_sc_hd__buf_8 FE_OFC59_io_oeb_1 (.A(FE_OFN59_io_oeb_1),
+ .X(io_oeb[1]));
+ sky130_fd_sc_hd__buf_8 FE_OFC58_io_oeb_2 (.A(FE_OFN58_io_oeb_2),
+ .X(io_oeb[2]));
+ sky130_fd_sc_hd__buf_8 FE_OFC57_io_oeb_3 (.A(FE_OFN57_io_oeb_3),
+ .X(io_oeb[3]));
+ sky130_fd_sc_hd__buf_8 FE_OFC56_io_oeb_4 (.A(FE_OFN56_io_oeb_4),
+ .X(io_oeb[4]));
+ sky130_fd_sc_hd__buf_8 FE_OFC55_io_oeb_5 (.A(FE_OFN55_io_oeb_5),
+ .X(io_oeb[5]));
+ sky130_fd_sc_hd__buf_8 FE_OFC54_io_oeb_6 (.A(FE_OFN54_io_oeb_6),
+ .X(io_oeb[6]));
+ sky130_fd_sc_hd__inv_2 FE_OFC53_io_in_7 (.A(FE_OFN52_io_in_7),
+ .Y(FE_OFN53_io_in_7));
+ sky130_fd_sc_hd__inv_2 FE_OFC52_io_in_7 (.A(io_in[7]),
+ .Y(FE_OFN52_io_in_7));
+ sky130_fd_sc_hd__inv_2 FE_OFC51_io_in_8 (.A(FE_OFN50_io_in_8),
+ .Y(FE_OFN51_io_in_8));
+ sky130_fd_sc_hd__inv_2 FE_OFC50_io_in_8 (.A(io_in[8]),
+ .Y(FE_OFN50_io_in_8));
+ sky130_fd_sc_hd__inv_2 FE_OFC49_io_in_9 (.A(FE_OFN48_io_in_9),
+ .Y(FE_OFN49_io_in_9));
+ sky130_fd_sc_hd__inv_2 FE_OFC48_io_in_9 (.A(io_in[9]),
+ .Y(FE_OFN48_io_in_9));
+ sky130_fd_sc_hd__inv_2 FE_OFC47_io_in_10 (.A(FE_OFN46_io_in_10),
+ .Y(FE_OFN47_io_in_10));
+ sky130_fd_sc_hd__inv_2 FE_OFC46_io_in_10 (.A(io_in[10]),
+ .Y(FE_OFN46_io_in_10));
+ sky130_fd_sc_hd__inv_4 FE_OFC45_io_in_11 (.A(FE_OFN44_io_in_11),
+ .Y(FE_OFN45_io_in_11));
+ sky130_fd_sc_hd__inv_4 FE_OFC44_io_in_11 (.A(io_in[11]),
+ .Y(FE_OFN44_io_in_11));
+ sky130_fd_sc_hd__inv_4 FE_OFC43_io_in_12 (.A(FE_OFN42_io_in_12),
+ .Y(FE_OFN43_io_in_12));
+ sky130_fd_sc_hd__inv_4 FE_OFC42_io_in_12 (.A(io_in[12]),
+ .Y(FE_OFN42_io_in_12));
+ sky130_fd_sc_hd__inv_2 FE_OFC41_io_in_13 (.A(FE_OFN40_io_in_13),
+ .Y(FE_OFN41_io_in_13));
+ sky130_fd_sc_hd__inv_4 FE_OFC40_io_in_13 (.A(io_in[13]),
+ .Y(FE_OFN40_io_in_13));
+ sky130_fd_sc_hd__clkinv_2 FE_OFC39_io_in_14 (.A(FE_OFN38_io_in_14),
+ .Y(FE_OFN39_io_in_14));
+ sky130_fd_sc_hd__inv_2 FE_OFC38_io_in_14 (.A(io_in[14]),
+ .Y(FE_OFN38_io_in_14));
+ sky130_fd_sc_hd__inv_2 FE_OFC37_io_in_15 (.A(FE_OFN36_io_in_15),
+ .Y(FE_OFN37_io_in_15));
+ sky130_fd_sc_hd__inv_2 FE_OFC36_io_in_15 (.A(io_in[15]),
+ .Y(FE_OFN36_io_in_15));
+ sky130_fd_sc_hd__inv_2 FE_OFC35_io_in_17 (.A(FE_OFN34_io_in_17),
+ .Y(FE_OFN35_io_in_17));
+ sky130_fd_sc_hd__inv_2 FE_OFC34_io_in_17 (.A(io_in[17]),
+ .Y(FE_OFN34_io_in_17));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC33_Config_inst_Inst_bitbang_s_data_sample_2 (.A(\Config_inst.Inst_bitbang.s_data_sample[2] ),
+ .X(FE_OFN33_Config_inst_Inst_bitbang_s_data_sample_2));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC32_Config_inst_Inst_bitbang_s_data_sample_1 (.A(\Config_inst.Inst_bitbang.s_data_sample[1] ),
+ .X(FE_OFN32_Config_inst_Inst_bitbang_s_data_sample_1));
+ sky130_fd_sc_hd__inv_6 FE_OFC31_Config_inst_Inst_bitbang_s_clk_sample_2 (.A(FE_OFN30_Config_inst_Inst_bitbang_s_clk_sample_2),
+ .Y(FE_OFN31_Config_inst_Inst_bitbang_s_clk_sample_2));
+ sky130_fd_sc_hd__inv_2 FE_OFC30_Config_inst_Inst_bitbang_s_clk_sample_2 (.A(FE_OFN29_Config_inst_Inst_bitbang_s_clk_sample_2),
+ .Y(FE_OFN30_Config_inst_Inst_bitbang_s_clk_sample_2));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC29_Config_inst_Inst_bitbang_s_clk_sample_2 (.A(\Config_inst.Inst_bitbang.s_clk_sample[2] ),
+ .X(FE_OFN29_Config_inst_Inst_bitbang_s_clk_sample_2));
+ sky130_fd_sc_hd__clkbuf_4 FE_OFC28_Config_inst_Inst_bitbang_active (.A(\Config_inst.Inst_bitbang.active ),
+ .X(FE_OFN28_Config_inst_Inst_bitbang_active));
+ sky130_fd_sc_hd__inv_2 FE_OFC27_Config_inst_INST_config_UART_RxLocal (.A(FE_OFN26_Config_inst_INST_config_UART_RxLocal),
+ .Y(FE_OFN27_Config_inst_INST_config_UART_RxLocal));
+ sky130_fd_sc_hd__inv_2 FE_OFC26_Config_inst_INST_config_UART_RxLocal (.A(FE_OFN25_Config_inst_INST_config_UART_RxLocal),
+ .Y(FE_OFN26_Config_inst_INST_config_UART_RxLocal));
+ sky130_fd_sc_hd__inv_2 FE_OFC25_Config_inst_INST_config_UART_RxLocal (.A(FE_OFN24_Config_inst_INST_config_UART_RxLocal),
+ .Y(FE_OFN25_Config_inst_INST_config_UART_RxLocal));
+ sky130_fd_sc_hd__inv_6 FE_OFC24_Config_inst_INST_config_UART_RxLocal (.A(\Config_inst.INST_config_UART.RxLocal ),
+ .Y(FE_OFN24_Config_inst_INST_config_UART_RxLocal));
+ sky130_fd_sc_hd__buf_2 FE_OFC23_1925 (.A(_1925_),
+ .X(FE_OFN23_1925));
+ sky130_fd_sc_hd__buf_2 FE_OFC22_1920 (.A(_1920_),
+ .X(FE_OFN22_1920));
+ sky130_fd_sc_hd__buf_2 FE_OFC21_1915 (.A(_1915_),
+ .X(FE_OFN21_1915));
+ sky130_fd_sc_hd__buf_4 FE_OFC20_1851 (.A(_1851_),
+ .X(FE_OFN20_1851));
+ sky130_fd_sc_hd__buf_6 FE_OFC19_1849 (.A(_1849_),
+ .X(FE_OFN19_1849));
+ sky130_fd_sc_hd__buf_4 FE_OFC18_1847 (.A(_1847_),
+ .X(FE_OFN18_1847));
+ sky130_fd_sc_hd__buf_4 FE_OFC17_1845 (.A(_1845_),
+ .X(FE_OFN17_1845));
+ sky130_fd_sc_hd__buf_4 FE_OFC16_1840 (.A(_1840_),
+ .X(FE_OFN16_1840));
+ sky130_fd_sc_hd__buf_4 FE_OFC15_1838 (.A(_1838_),
+ .X(FE_OFN15_1838));
+ sky130_fd_sc_hd__buf_6 FE_OFC14_1834 (.A(_1834_),
+ .X(FE_OFN14_1834));
+ sky130_fd_sc_hd__buf_4 FE_OFC13_1831 (.A(_1831_),
+ .X(FE_OFN13_1831));
+ sky130_fd_sc_hd__buf_4 FE_OFC12_1829 (.A(_1829_),
+ .X(FE_OFN12_1829));
+ sky130_fd_sc_hd__buf_6 FE_OFC11_1827 (.A(_1827_),
+ .X(FE_OFN11_1827));
+ sky130_fd_sc_hd__buf_6 FE_OFC10_1825 (.A(_1825_),
+ .X(FE_OFN10_1825));
+ sky130_fd_sc_hd__buf_6 FE_OFC9_1823 (.A(_1823_),
+ .X(FE_OFN9_1823));
+ sky130_fd_sc_hd__buf_4 FE_OFC8_1818 (.A(_1818_),
+ .X(FE_OFN8_1818));
+ sky130_fd_sc_hd__buf_4 FE_OFC7_1816 (.A(_1816_),
+ .X(FE_OFN7_1816));
+ sky130_fd_sc_hd__buf_6 FE_OFC6_1814 (.A(_1814_),
+ .X(FE_OFN6_1814));
+ sky130_fd_sc_hd__buf_2 FE_OFC5_1525 (.A(_1525_),
+ .X(FE_OFN5_1525));
+ sky130_fd_sc_hd__buf_2 FE_OFC4_1509 (.A(_1509_),
+ .X(FE_OFN4_1509));
+ sky130_fd_sc_hd__buf_2 FE_OFC3_1493 (.A(_1493_),
+ .X(FE_OFN3_1493));
+ sky130_fd_sc_hd__buf_2 FE_OFC2_1332 (.A(_1332_),
+ .X(FE_OFN2_1332));
+ sky130_fd_sc_hd__buf_2 FE_OFC1_1190 (.A(_1190_),
+ .X(FE_OFN1_1190));
+ sky130_fd_sc_hd__buf_4 FE_OFC0_1174 (.A(_1174_),
+ .X(FE_OFN0_1174));
+ sky130_fd_sc_hd__or4_1 _1997_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[7] ),
+ .B(\Config_inst.INST_config_UART.TimeToSendCounter[6] ),
+ .C(\Config_inst.INST_config_UART.TimeToSendCounter[8] ),
+ .D(\Config_inst.INST_config_UART.TimeToSendCounter[5] ),
+ .X(_0896_));
+ sky130_fd_sc_hd__or3_1 _1998_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[4] ),
+ .B(\Config_inst.INST_config_UART.TimeToSendCounter[1] ),
+ .C(\Config_inst.INST_config_UART.TimeToSendCounter[0] ),
+ .X(_0897_));
+ sky130_fd_sc_hd__or3_1 _1999_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[3] ),
+ .B(\Config_inst.INST_config_UART.TimeToSendCounter[2] ),
+ .C(_0897_),
+ .X(_0898_));
+ sky130_fd_sc_hd__or4_1 _2000_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[10] ),
+ .B(\Config_inst.INST_config_UART.TimeToSendCounter[9] ),
+ .C(_0896_),
+ .D(_0898_),
+ .X(_0899_));
+ sky130_fd_sc_hd__or2_2 _2001_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[11] ),
+ .B(_0899_),
+ .X(_0900_));
+ sky130_fd_sc_hd__or2_2 _2002_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[12] ),
+ .B(_0900_),
+ .X(_0901_));
+ sky130_fd_sc_hd__inv_2 _2003_ (.A(_0901_),
+ .Y(_0902_));
+ sky130_fd_sc_hd__and2b_1 _2004_ (.A_N(\Config_inst.INST_config_UART.TimeToSendCounter[13] ),
+ .B(\Config_inst.INST_config_UART.TimeToSendCounter[14] ),
+ .X(_0903_));
+ sky130_fd_sc_hd__inv_2 _2005_ (.A(\Config_inst.INST_config_UART.ComState[1] ),
+ .Y(_0904_));
+ sky130_fd_sc_hd__inv_2 _2006_ (.A(\Config_inst.INST_config_UART.ComState[3] ),
+ .Y(_0905_));
+ sky130_fd_sc_hd__or4_1 _2007_ (.A(_0904_),
+ .B(\Config_inst.INST_config_UART.ComState[0] ),
+ .C(_0905_),
+ .D(\Config_inst.INST_config_UART.ComState[2] ),
+ .X(_0906_));
+ sky130_fd_sc_hd__inv_2 _2008_ (.A(_0906_),
+ .Y(_0907_));
+ sky130_fd_sc_hd__or3_1 _2011_ (.A(\Config_inst.INST_config_UART.PresentState[1] ),
+ .B(\Config_inst.INST_config_UART.PresentState[0] ),
+ .C(\Config_inst.INST_config_UART.PresentState[2] ),
+ .X(_0910_));
+ sky130_fd_sc_hd__inv_2 _2012_ (.A(_0910_),
+ .Y(_0911_));
+ sky130_fd_sc_hd__or2_2 _2013_ (.A(_0907_),
+ .B(_0911_),
+ .X(_0912_));
+ sky130_fd_sc_hd__inv_2 _2014_ (.A(_0912_),
+ .Y(_0913_));
+ sky130_fd_sc_hd__o221a_2 _2016_ (.A1(\Config_inst.INST_config_UART.TimeToSendCounter[13] ),
+ .A2(_0902_),
+ .B1(_0901_),
+ .B2(_0903_),
+ .C1(_0913_),
+ .X(_0132_));
+ sky130_fd_sc_hd__inv_2 _2017_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[12] ),
+ .Y(_0915_));
+ sky130_fd_sc_hd__or3_1 _2018_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[13] ),
+ .B(_0901_),
+ .C(\Config_inst.INST_config_UART.TimeToSendCounter[14] ),
+ .X(_0916_));
+ sky130_fd_sc_hd__inv_2 _2019_ (.A(_0916_),
+ .Y(_0917_));
+ sky130_fd_sc_hd__nor2_1 _2020_ (.A(_0900_),
+ .B(_0917_),
+ .Y(_0918_));
+ sky130_fd_sc_hd__o221a_2 _2021_ (.A1(_0915_),
+ .A2(_0900_),
+ .B1(\Config_inst.INST_config_UART.TimeToSendCounter[12] ),
+ .B2(_0918_),
+ .C1(_0913_),
+ .X(_0131_));
+ sky130_fd_sc_hd__a21oi_1 _2023_ (.A1(\Config_inst.INST_config_UART.TimeToSendCounter[11] ),
+ .A2(_0899_),
+ .B1(_0918_),
+ .Y(_0920_));
+ sky130_fd_sc_hd__nor2_1 _2024_ (.A(_0912_),
+ .B(_0920_),
+ .Y(_0130_));
+ sky130_fd_sc_hd__inv_2 _2025_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[10] ),
+ .Y(_0921_));
+ sky130_fd_sc_hd__or2_2 _2026_ (.A(_0898_),
+ .B(_0917_),
+ .X(_0922_));
+ sky130_fd_sc_hd__or2_2 _2027_ (.A(_0896_),
+ .B(_0922_),
+ .X(_0923_));
+ sky130_fd_sc_hd__or2_2 _2028_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[9] ),
+ .B(_0923_),
+ .X(_0924_));
+ sky130_fd_sc_hd__inv_2 _2029_ (.A(_0924_),
+ .Y(_0925_));
+ sky130_fd_sc_hd__o221a_2 _2030_ (.A1(_0921_),
+ .A2(_0924_),
+ .B1(\Config_inst.INST_config_UART.TimeToSendCounter[10] ),
+ .B2(_0925_),
+ .C1(_0913_),
+ .X(_0129_));
+ sky130_fd_sc_hd__and2_1 _2031_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[9] ),
+ .B(_0923_),
+ .X(_0926_));
+ sky130_fd_sc_hd__o21a_1 _2032_ (.A1(_0925_),
+ .A2(_0926_),
+ .B1(_0913_),
+ .X(_0128_));
+ sky130_fd_sc_hd__inv_2 _2033_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[8] ),
+ .Y(_0927_));
+ sky130_fd_sc_hd__or2_2 _2034_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[5] ),
+ .B(_0922_),
+ .X(_0928_));
+ sky130_fd_sc_hd__nor3_1 _2035_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[7] ),
+ .B(\Config_inst.INST_config_UART.TimeToSendCounter[6] ),
+ .C(_0928_),
+ .Y(_0929_));
+ sky130_fd_sc_hd__o211ai_1 _2036_ (.A1(_0927_),
+ .A2(_0929_),
+ .B1(_0913_),
+ .C1(_0923_),
+ .Y(_0127_));
+ sky130_fd_sc_hd__o21a_1 _2037_ (.A1(\Config_inst.INST_config_UART.TimeToSendCounter[6] ),
+ .A2(_0928_),
+ .B1(\Config_inst.INST_config_UART.TimeToSendCounter[7] ),
+ .X(_0930_));
+ sky130_fd_sc_hd__or3_1 _2038_ (.A(_0912_),
+ .B(_0929_),
+ .C(_0930_),
+ .X(_0931_));
+ sky130_fd_sc_hd__inv_2 _2040_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[6] ),
+ .Y(_0932_));
+ sky130_fd_sc_hd__inv_2 _2041_ (.A(_0928_),
+ .Y(_0933_));
+ sky130_fd_sc_hd__o22a_1 _2042_ (.A1(\Config_inst.INST_config_UART.TimeToSendCounter[6] ),
+ .A2(_0928_),
+ .B1(_0932_),
+ .B2(_0933_),
+ .X(_0934_));
+ sky130_fd_sc_hd__nor2_1 _2043_ (.A(_0912_),
+ .B(_0934_),
+ .Y(_0125_));
+ sky130_fd_sc_hd__and2_1 _2044_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[5] ),
+ .B(_0922_),
+ .X(_0935_));
+ sky130_fd_sc_hd__o21a_1 _2045_ (.A1(_0933_),
+ .A2(_0935_),
+ .B1(_0913_),
+ .X(_0124_));
+ sky130_fd_sc_hd__inv_2 _2046_ (.A(_0922_),
+ .Y(_0936_));
+ sky130_fd_sc_hd__or2_2 _2048_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[0] ),
+ .B(_0917_),
+ .X(_0938_));
+ sky130_fd_sc_hd__or2_2 _2049_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[1] ),
+ .B(_0938_),
+ .X(_0939_));
+ sky130_fd_sc_hd__o31a_1 _2050_ (.A1(\Config_inst.INST_config_UART.TimeToSendCounter[2] ),
+ .A2(_0939_),
+ .A3(\Config_inst.INST_config_UART.TimeToSendCounter[3] ),
+ .B1(\Config_inst.INST_config_UART.TimeToSendCounter[4] ),
+ .X(_0940_));
+ sky130_fd_sc_hd__o21a_1 _2051_ (.A1(_0936_),
+ .A2(_0940_),
+ .B1(_0913_),
+ .X(_0123_));
+ sky130_fd_sc_hd__o21ai_1 _2052_ (.A1(\Config_inst.INST_config_UART.TimeToSendCounter[2] ),
+ .A2(_0939_),
+ .B1(\Config_inst.INST_config_UART.TimeToSendCounter[3] ),
+ .Y(_0941_));
+ sky130_fd_sc_hd__o311a_1 _2053_ (.A1(\Config_inst.INST_config_UART.TimeToSendCounter[3] ),
+ .A2(\Config_inst.INST_config_UART.TimeToSendCounter[2] ),
+ .A3(_0939_),
+ .B1(_0913_),
+ .C1(_0941_),
+ .X(_0942_));
+ sky130_fd_sc_hd__inv_2 _2054_ (.A(_0942_),
+ .Y(_0122_));
+ sky130_fd_sc_hd__inv_2 _2055_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[2] ),
+ .Y(_0943_));
+ sky130_fd_sc_hd__inv_2 _2056_ (.A(_0939_),
+ .Y(_0944_));
+ sky130_fd_sc_hd__o22a_1 _2057_ (.A1(\Config_inst.INST_config_UART.TimeToSendCounter[2] ),
+ .A2(_0939_),
+ .B1(_0943_),
+ .B2(_0944_),
+ .X(_0945_));
+ sky130_fd_sc_hd__nor2_1 _2058_ (.A(_0912_),
+ .B(_0945_),
+ .Y(_0121_));
+ sky130_fd_sc_hd__and2_1 _2059_ (.A(\Config_inst.INST_config_UART.TimeToSendCounter[1] ),
+ .B(_0938_),
+ .X(_0946_));
+ sky130_fd_sc_hd__o21a_1 _2060_ (.A1(_0944_),
+ .A2(_0946_),
+ .B1(_0913_),
+ .X(_0120_));
+ sky130_fd_sc_hd__nor2_1 _2061_ (.A(_0912_),
+ .B(_0938_),
+ .Y(_0119_));
+ sky130_fd_sc_hd__inv_2 _2062_ (.A(\Config_inst.INST_config_UART.CRCReg[18] ),
+ .Y(_0947_));
+ sky130_fd_sc_hd__inv_2 _2063_ (.A(\Config_inst.INST_config_UART.CRCReg[11] ),
+ .Y(_0948_));
+ sky130_fd_sc_hd__inv_2 _2064_ (.A(\Config_inst.INST_config_UART.CRCReg[7] ),
+ .Y(_0949_));
+ sky130_fd_sc_hd__inv_2 _2065_ (.A(_0037_),
+ .Y(_0950_));
+ sky130_fd_sc_hd__o22a_1 _2066_ (.A1(_0949_),
+ .A2(_0950_),
+ .B1(\Config_inst.INST_config_UART.CRCReg[7] ),
+ .B2(_0037_),
+ .X(_0951_));
+ sky130_fd_sc_hd__inv_2 _2067_ (.A(_0951_),
+ .Y(_0952_));
+ sky130_fd_sc_hd__inv_2 _2068_ (.A(\Config_inst.INST_config_UART.CRCReg[6] ),
+ .Y(_0953_));
+ sky130_fd_sc_hd__inv_2 _2069_ (.A(_0036_),
+ .Y(_0954_));
+ sky130_fd_sc_hd__a22o_1 _2070_ (.A1(\Config_inst.INST_config_UART.CRCReg[6] ),
+ .A2(_0036_),
+ .B1(_0953_),
+ .B2(_0954_),
+ .X(_0955_));
+ sky130_fd_sc_hd__or2_2 _2071_ (.A(_0952_),
+ .B(_0955_),
+ .X(_0956_));
+ sky130_fd_sc_hd__inv_2 _2072_ (.A(\Config_inst.INST_config_UART.CRCReg[4] ),
+ .Y(_0957_));
+ sky130_fd_sc_hd__inv_2 _2073_ (.A(_0034_),
+ .Y(_0958_));
+ sky130_fd_sc_hd__o22a_1 _2074_ (.A1(_0957_),
+ .A2(_0958_),
+ .B1(\Config_inst.INST_config_UART.CRCReg[4] ),
+ .B2(_0034_),
+ .X(_0959_));
+ sky130_fd_sc_hd__inv_2 _2077_ (.A(_0033_),
+ .Y(_0962_));
+ sky130_fd_sc_hd__nor2_1 _2078_ (.A(\Config_inst.INST_config_UART.CRCReg[3] ),
+ .B(_0962_),
+ .Y(_0963_));
+ sky130_fd_sc_hd__a21oi_1 _2079_ (.A1(\Config_inst.INST_config_UART.CRCReg[3] ),
+ .A2(_0962_),
+ .B1(_0963_),
+ .Y(_0964_));
+ sky130_fd_sc_hd__inv_2 _2080_ (.A(\Config_inst.INST_config_UART.CRCReg[2] ),
+ .Y(_0965_));
+ sky130_fd_sc_hd__a2bb2o_1 _2081_ (.A1_N(_0965_),
+ .A2_N(_0031_),
+ .B1(_0965_),
+ .B2(_0031_),
+ .X(_0966_));
+ sky130_fd_sc_hd__inv_2 _2082_ (.A(_0966_),
+ .Y(_0967_));
+ sky130_fd_sc_hd__inv_2 _2083_ (.A(\Config_inst.INST_config_UART.CRCReg[1] ),
+ .Y(_0968_));
+ sky130_fd_sc_hd__inv_2 _2084_ (.A(\Config_inst.INST_config_UART.CRCReg[0] ),
+ .Y(_0969_));
+ sky130_fd_sc_hd__or3_1 _2086_ (.A(_0969_),
+ .B(_0029_),
+ .C(_0970_),
+ .X(_0971_));
+ sky130_fd_sc_hd__o21ai_1 _2087_ (.A1(_0968_),
+ .A2(_0027_),
+ .B1(_0971_),
+ .Y(_0972_));
+ sky130_fd_sc_hd__or3_1 _2088_ (.A(_0965_),
+ .B(_0031_),
+ .C(_0963_),
+ .X(_0973_));
+ sky130_fd_sc_hd__a21bo_2 _2089_ (.A1(\Config_inst.INST_config_UART.CRCReg[3] ),
+ .A2(_0962_),
+ .B1_N(_0973_),
+ .X(_0974_));
+ sky130_fd_sc_hd__a31o_2 _2090_ (.A1(_0964_),
+ .A2(_0967_),
+ .A3(_0972_),
+ .B1(_0974_),
+ .X(_0975_));
+ sky130_fd_sc_hd__and4b_1 _2091_ (.A_N(_0956_),
+ .B(_0959_),
+ .C(_0961_),
+ .D(_0975_),
+ .X(_0976_));
+ sky130_fd_sc_hd__a22o_1 _2092_ (.A1(\Config_inst.INST_config_UART.CRCReg[5] ),
+ .A2(_0035_),
+ .B1(\Config_inst.INST_config_UART.CRCReg[4] ),
+ .B2(_0034_),
+ .X(_0977_));
+ sky130_fd_sc_hd__o21ai_1 _2093_ (.A1(\Config_inst.INST_config_UART.CRCReg[5] ),
+ .A2(_0035_),
+ .B1(_0977_),
+ .Y(_0978_));
+ sky130_fd_sc_hd__a211o_1 _2094_ (.A1(_0949_),
+ .A2(_0950_),
+ .B1(_0953_),
+ .C1(_0954_),
+ .X(_0979_));
+ sky130_fd_sc_hd__o221ai_1 _2095_ (.A1(_0949_),
+ .A2(_0950_),
+ .B1(_0956_),
+ .B2(_0978_),
+ .C1(_0979_),
+ .Y(_0980_));
+ sky130_fd_sc_hd__o21ai_1 _2096_ (.A1(_0976_),
+ .A2(_0980_),
+ .B1(_0003_),
+ .Y(_0981_));
+ sky130_fd_sc_hd__inv_2 _2097_ (.A(_0981_),
+ .Y(_0982_));
+ sky130_fd_sc_hd__and3_1 _2098_ (.A(\Config_inst.INST_config_UART.CRCReg[9] ),
+ .B(\Config_inst.INST_config_UART.CRCReg[8] ),
+ .C(_0982_),
+ .X(_0983_));
+ sky130_fd_sc_hd__nand2_1 _2099_ (.A(\Config_inst.INST_config_UART.CRCReg[10] ),
+ .B(_0983_),
+ .Y(_0984_));
+ sky130_fd_sc_hd__or2_2 _2100_ (.A(_0948_),
+ .B(_0984_),
+ .X(_0985_));
+ sky130_fd_sc_hd__inv_2 _2101_ (.A(\Config_inst.INST_config_UART.CRCReg[14] ),
+ .Y(_0986_));
+ sky130_fd_sc_hd__inv_2 _2102_ (.A(\Config_inst.INST_config_UART.CRCReg[13] ),
+ .Y(_0987_));
+ sky130_fd_sc_hd__inv_2 _2103_ (.A(\Config_inst.INST_config_UART.CRCReg[15] ),
+ .Y(_0988_));
+ sky130_fd_sc_hd__inv_2 _2104_ (.A(\Config_inst.INST_config_UART.CRCReg[12] ),
+ .Y(_0989_));
+ sky130_fd_sc_hd__or4_1 _2105_ (.A(_0986_),
+ .B(_0987_),
+ .C(_0988_),
+ .D(_0989_),
+ .X(_0990_));
+ sky130_fd_sc_hd__or2_2 _2106_ (.A(_0985_),
+ .B(_0990_),
+ .X(_0991_));
+ sky130_fd_sc_hd__inv_2 _2107_ (.A(\Config_inst.INST_config_UART.CRCReg[16] ),
+ .Y(_0992_));
+ sky130_fd_sc_hd__or3b_2 _2108_ (.A(_0991_),
+ .B(_0992_),
+ .C_N(\Config_inst.INST_config_UART.CRCReg[17] ),
+ .X(_0993_));
+ sky130_fd_sc_hd__or2_2 _2109_ (.A(_0947_),
+ .B(_0993_),
+ .X(_0994_));
+ sky130_fd_sc_hd__inv_2 _2110_ (.A(_0994_),
+ .Y(_0995_));
+ sky130_fd_sc_hd__inv_2 _2111_ (.A(\Config_inst.INST_config_UART.CRCReg[19] ),
+ .Y(_0996_));
+ sky130_fd_sc_hd__inv_2 _2112_ (.A(\Config_inst.INST_config_UART.PresentState[2] ),
+ .Y(_0997_));
+ sky130_fd_sc_hd__or3_1 _2114_ (.A(\Config_inst.INST_config_UART.PresentState[1] ),
+ .B(\Config_inst.INST_config_UART.PresentState[0] ),
+ .C(_0997_),
+ .X(_0999_));
+ sky130_fd_sc_hd__o221a_2 _2117_ (.A1(\Config_inst.INST_config_UART.CRCReg[19] ),
+ .A2(_0995_),
+ .B1(_0996_),
+ .B2(_0994_),
+ .C1(_0999_),
+ .X(_0118_));
+ sky130_fd_sc_hd__inv_2 _2118_ (.A(_0999_),
+ .Y(_1002_));
+ sky130_fd_sc_hd__a211oi_1 _2120_ (.A1(_0947_),
+ .A2(_0993_),
+ .B1(_1002_),
+ .C1(_0995_),
+ .Y(_0117_));
+ sky130_fd_sc_hd__inv_2 _2121_ (.A(_0991_),
+ .Y(_1004_));
+ sky130_fd_sc_hd__or3_1 _2122_ (.A(_0992_),
+ .B(_1004_),
+ .C(\Config_inst.INST_config_UART.CRCReg[17] ),
+ .X(_1005_));
+ sky130_fd_sc_hd__o2111a_1 _2123_ (.A1(\Config_inst.INST_config_UART.CRCReg[17] ),
+ .A2(\Config_inst.INST_config_UART.CRCReg[16] ),
+ .B1(_0999_),
+ .C1(_0993_),
+ .D1(_1005_),
+ .X(_0116_));
+ sky130_fd_sc_hd__o22a_1 _2124_ (.A1(_0992_),
+ .A2(_1004_),
+ .B1(\Config_inst.INST_config_UART.CRCReg[16] ),
+ .B2(_0991_),
+ .X(_1006_));
+ sky130_fd_sc_hd__nor2_1 _2125_ (.A(_1002_),
+ .B(_1006_),
+ .Y(_0115_));
+ sky130_fd_sc_hd__or2_2 _2126_ (.A(_0989_),
+ .B(_0985_),
+ .X(_1007_));
+ sky130_fd_sc_hd__or2_2 _2127_ (.A(_0987_),
+ .B(_1007_),
+ .X(_1008_));
+ sky130_fd_sc_hd__or2_2 _2128_ (.A(_0986_),
+ .B(_1008_),
+ .X(_1009_));
+ sky130_fd_sc_hd__a211oi_1 _2129_ (.A1(_0988_),
+ .A2(_1009_),
+ .B1(_1002_),
+ .C1(_1004_),
+ .Y(_0114_));
+ sky130_fd_sc_hd__inv_2 _2130_ (.A(_1008_),
+ .Y(_1010_));
+ sky130_fd_sc_hd__o211a_2 _2131_ (.A1(\Config_inst.INST_config_UART.CRCReg[14] ),
+ .A2(_1010_),
+ .B1(_1009_),
+ .C1(_0999_),
+ .X(_0113_));
+ sky130_fd_sc_hd__a211oi_1 _2132_ (.A1(_0987_),
+ .A2(_1007_),
+ .B1(_1002_),
+ .C1(_1010_),
+ .Y(_0112_));
+ sky130_fd_sc_hd__inv_2 _2133_ (.A(_0985_),
+ .Y(_1011_));
+ sky130_fd_sc_hd__o211a_2 _2134_ (.A1(\Config_inst.INST_config_UART.CRCReg[12] ),
+ .A2(_1011_),
+ .B1(_1007_),
+ .C1(_0999_),
+ .X(_0111_));
+ sky130_fd_sc_hd__a211oi_1 _2135_ (.A1(_0948_),
+ .A2(_0984_),
+ .B1(_1002_),
+ .C1(_1011_),
+ .Y(_0110_));
+ sky130_fd_sc_hd__o211a_2 _2136_ (.A1(\Config_inst.INST_config_UART.CRCReg[10] ),
+ .A2(_0983_),
+ .B1(_0984_),
+ .C1(_0999_),
+ .X(_0109_));
+ sky130_fd_sc_hd__inv_2 _2137_ (.A(\Config_inst.INST_config_UART.CRCReg[9] ),
+ .Y(_1012_));
+ sky130_fd_sc_hd__inv_2 _2138_ (.A(\Config_inst.INST_config_UART.CRCReg[8] ),
+ .Y(_1013_));
+ sky130_fd_sc_hd__or2_2 _2139_ (.A(_1013_),
+ .B(_0981_),
+ .X(_1014_));
+ sky130_fd_sc_hd__a211oi_1 _2140_ (.A1(_1012_),
+ .A2(_1014_),
+ .B1(_0983_),
+ .C1(_1002_),
+ .Y(_0108_));
+ sky130_fd_sc_hd__o211a_2 _2142_ (.A1(\Config_inst.INST_config_UART.CRCReg[8] ),
+ .A2(_0982_),
+ .B1(_0999_),
+ .C1(_1014_),
+ .X(_0107_));
+ sky130_fd_sc_hd__inv_2 _2145_ (.A(_0961_),
+ .Y(_1018_));
+ sky130_fd_sc_hd__inv_2 _2146_ (.A(_0959_),
+ .Y(_1019_));
+ sky130_fd_sc_hd__inv_2 _2147_ (.A(_0975_),
+ .Y(_1020_));
+ sky130_fd_sc_hd__o31a_1 _2148_ (.A1(_1018_),
+ .A2(_1019_),
+ .A3(_1020_),
+ .B1(_0978_),
+ .X(_1021_));
+ sky130_fd_sc_hd__or2_2 _2149_ (.A(_0955_),
+ .B(_1021_),
+ .X(_1022_));
+ sky130_fd_sc_hd__o21ai_1 _2150_ (.A1(_0953_),
+ .A2(_0954_),
+ .B1(_1022_),
+ .Y(_1023_));
+ sky130_fd_sc_hd__inv_2 _2151_ (.A(_1023_),
+ .Y(_1024_));
+ sky130_fd_sc_hd__inv_2 _2152_ (.A(_0003_),
+ .Y(_1025_));
+ sky130_fd_sc_hd__a221o_1 _2154_ (.A1(_0951_),
+ .A2(_1024_),
+ .B1(_0952_),
+ .B2(_1023_),
+ .C1(_1025_),
+ .X(_1027_));
+ sky130_fd_sc_hd__o211a_2 _2155_ (.A1(_0003_),
+ .A2(\Config_inst.INST_config_UART.CRCReg[7] ),
+ .B1(_0999_),
+ .C1(_1027_),
+ .X(_0106_));
+ sky130_fd_sc_hd__inv_2 _2156_ (.A(_1022_),
+ .Y(_1028_));
+ sky130_fd_sc_hd__and2_1 _2157_ (.A(_0955_),
+ .B(_1021_),
+ .X(_1029_));
+ sky130_fd_sc_hd__o32a_1 _2158_ (.A1(_1025_),
+ .A2(_1028_),
+ .A3(_1029_),
+ .B1(_0003_),
+ .B2(_0953_),
+ .X(_1030_));
+ sky130_fd_sc_hd__nor2_1 _2159_ (.A(_1002_),
+ .B(_1030_),
+ .Y(_0105_));
+ sky130_fd_sc_hd__o22a_1 _2160_ (.A1(_0957_),
+ .A2(_0958_),
+ .B1(_1020_),
+ .B2(_1019_),
+ .X(_1031_));
+ sky130_fd_sc_hd__inv_2 _2161_ (.A(_1031_),
+ .Y(_1032_));
+ sky130_fd_sc_hd__a221o_1 _2162_ (.A1(_0961_),
+ .A2(_1031_),
+ .B1(_1018_),
+ .B2(_1032_),
+ .C1(_1025_),
+ .X(_1033_));
+ sky130_fd_sc_hd__o211a_2 _2163_ (.A1(_0003_),
+ .A2(\Config_inst.INST_config_UART.CRCReg[5] ),
+ .B1(_0999_),
+ .C1(_1033_),
+ .X(_0104_));
+ sky130_fd_sc_hd__o22a_1 _2164_ (.A1(_1020_),
+ .A2(_1019_),
+ .B1(_0975_),
+ .B2(_0959_),
+ .X(_1034_));
+ sky130_fd_sc_hd__o221a_2 _2165_ (.A1(_0003_),
+ .A2(\Config_inst.INST_config_UART.CRCReg[4] ),
+ .B1(_1025_),
+ .B2(_1034_),
+ .C1(_0999_),
+ .X(_0103_));
+ sky130_fd_sc_hd__inv_2 _2166_ (.A(_0972_),
+ .Y(_1035_));
+ sky130_fd_sc_hd__o22a_1 _2167_ (.A1(_0965_),
+ .A2(_0031_),
+ .B1(_1035_),
+ .B2(_0966_),
+ .X(_1036_));
+ sky130_fd_sc_hd__o21ai_1 _2168_ (.A1(_0964_),
+ .A2(_1036_),
+ .B1(_0003_),
+ .Y(_1037_));
+ sky130_fd_sc_hd__a21o_1 _2169_ (.A1(_0964_),
+ .A2(_1036_),
+ .B1(_1037_),
+ .X(_1038_));
+ sky130_fd_sc_hd__o211a_2 _2170_ (.A1(_0003_),
+ .A2(\Config_inst.INST_config_UART.CRCReg[3] ),
+ .B1(_0999_),
+ .C1(_1038_),
+ .X(_0102_));
+ sky130_fd_sc_hd__o22a_1 _2171_ (.A1(_1035_),
+ .A2(_0966_),
+ .B1(_0972_),
+ .B2(_0967_),
+ .X(_1039_));
+ sky130_fd_sc_hd__o221a_2 _2172_ (.A1(_0003_),
+ .A2(\Config_inst.INST_config_UART.CRCReg[2] ),
+ .B1(_1025_),
+ .B2(_1039_),
+ .C1(_0999_),
+ .X(_0101_));
+ sky130_fd_sc_hd__inv_2 _2173_ (.A(_0971_),
+ .Y(_1040_));
+ sky130_fd_sc_hd__o21a_1 _2174_ (.A1(_0969_),
+ .A2(_0029_),
+ .B1(_0970_),
+ .X(_1041_));
+ sky130_fd_sc_hd__o32a_1 _2175_ (.A1(_1025_),
+ .A2(_1040_),
+ .A3(_1041_),
+ .B1(_0003_),
+ .B2(_0968_),
+ .X(_1042_));
+ sky130_fd_sc_hd__nor2_1 _2176_ (.A(_1002_),
+ .B(_1042_),
+ .Y(_0100_));
+ sky130_fd_sc_hd__o21ai_1 _2177_ (.A1(_1025_),
+ .A2(_0029_),
+ .B1(_0969_),
+ .Y(_1043_));
+ sky130_fd_sc_hd__o311a_1 _2178_ (.A1(_0969_),
+ .A2(_0029_),
+ .A3(_1025_),
+ .B1(_0999_),
+ .C1(_1043_),
+ .X(_0099_));
+ sky130_fd_sc_hd__inv_2 _2179_ (.A(\Config_inst.INST_config_UART.GetWordState[0] ),
+ .Y(_1044_));
+ sky130_fd_sc_hd__inv_2 _2180_ (.A(\Config_inst.INST_config_UART.ByteWriteStrobe ),
+ .Y(_1045_));
+ sky130_fd_sc_hd__inv_2 _2182_ (.A(\Config_inst.INST_config_UART.GetWordState[1] ),
+ .Y(_1047_));
+ sky130_fd_sc_hd__o21a_1 _2183_ (.A1(_1044_),
+ .A2(_1045_),
+ .B1(_1047_),
+ .X(_1048_));
+ sky130_fd_sc_hd__inv_2 _2184_ (.A(\Config_inst.INST_config_UART.PresentState[0] ),
+ .Y(_1049_));
+ sky130_fd_sc_hd__or3_2 _2185_ (.A(\Config_inst.INST_config_UART.PresentState[1] ),
+ .B(_1049_),
+ .C(_0997_),
+ .X(_1050_));
+ sky130_fd_sc_hd__or3_1 _2187_ (.A(_1047_),
+ .B(_1044_),
+ .C(_1045_),
+ .X(_1052_));
+ sky130_fd_sc_hd__and3b_1 _2189_ (.A_N(_1048_),
+ .B(_1050_),
+ .C(_1052_),
+ .X(_1054_));
+ sky130_fd_sc_hd__o221a_2 _2192_ (.A1(_1044_),
+ .A2(_1045_),
+ .B1(\Config_inst.INST_config_UART.GetWordState[0] ),
+ .B2(\Config_inst.INST_config_UART.ByteWriteStrobe ),
+ .C1(_1050_),
+ .X(_0097_));
+ sky130_fd_sc_hd__inv_2 _2193_ (.A(_1052_),
+ .Y(_1056_));
+ sky130_fd_sc_hd__o221a_2 _2196_ (.A1(\Config_inst.INST_config_UART.WriteData[7] ),
+ .A2(_1056_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[7] ),
+ .B2(_1052_),
+ .C1(_1050_),
+ .X(_0096_));
+ sky130_fd_sc_hd__o221a_2 _2197_ (.A1(\Config_inst.INST_config_UART.WriteData[6] ),
+ .A2(_1056_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[6] ),
+ .B2(_1052_),
+ .C1(_1050_),
+ .X(_0095_));
+ sky130_fd_sc_hd__o221a_2 _2198_ (.A1(\Config_inst.INST_config_UART.WriteData[5] ),
+ .A2(_1056_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[5] ),
+ .B2(_1052_),
+ .C1(_1050_),
+ .X(_0094_));
+ sky130_fd_sc_hd__o221a_2 _2199_ (.A1(\Config_inst.INST_config_UART.WriteData[4] ),
+ .A2(_1056_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[4] ),
+ .B2(_1052_),
+ .C1(_1050_),
+ .X(_0093_));
+ sky130_fd_sc_hd__o221a_2 _2202_ (.A1(\Config_inst.INST_config_UART.WriteData[3] ),
+ .A2(_1056_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[3] ),
+ .B2(_1052_),
+ .C1(_1050_),
+ .X(_0092_));
+ sky130_fd_sc_hd__o221a_2 _2203_ (.A1(\Config_inst.INST_config_UART.WriteData[2] ),
+ .A2(_1056_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[2] ),
+ .B2(_1052_),
+ .C1(_1050_),
+ .X(_0091_));
+ sky130_fd_sc_hd__o221a_2 _2204_ (.A1(\Config_inst.INST_config_UART.WriteData[1] ),
+ .A2(_1056_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[1] ),
+ .B2(_1052_),
+ .C1(_1050_),
+ .X(_0090_));
+ sky130_fd_sc_hd__o221a_2 _2205_ (.A1(\Config_inst.INST_config_UART.WriteData[0] ),
+ .A2(_1056_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[0] ),
+ .B2(_1052_),
+ .C1(_1050_),
+ .X(_0089_));
+ sky130_fd_sc_hd__or3_1 _2206_ (.A(_1047_),
+ .B(\Config_inst.INST_config_UART.GetWordState[0] ),
+ .C(_1045_),
+ .X(_1060_));
+ sky130_fd_sc_hd__inv_2 _2207_ (.A(_1060_),
+ .Y(_1061_));
+ sky130_fd_sc_hd__o221a_2 _2210_ (.A1(\Config_inst.INST_config_UART.WriteData[15] ),
+ .A2(_1061_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[7] ),
+ .B2(_1060_),
+ .C1(_1050_),
+ .X(_0088_));
+ sky130_fd_sc_hd__o221a_2 _2212_ (.A1(\Config_inst.INST_config_UART.WriteData[14] ),
+ .A2(_1061_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[6] ),
+ .B2(_1060_),
+ .C1(_1050_),
+ .X(_0087_));
+ sky130_fd_sc_hd__o221a_2 _2213_ (.A1(\Config_inst.INST_config_UART.WriteData[13] ),
+ .A2(_1061_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[5] ),
+ .B2(_1060_),
+ .C1(_1050_),
+ .X(_0086_));
+ sky130_fd_sc_hd__o221a_2 _2214_ (.A1(\Config_inst.INST_config_UART.WriteData[12] ),
+ .A2(_1061_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[4] ),
+ .B2(_1060_),
+ .C1(_1050_),
+ .X(_0085_));
+ sky130_fd_sc_hd__o221a_2 _2215_ (.A1(\Config_inst.INST_config_UART.WriteData[11] ),
+ .A2(_1061_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[3] ),
+ .B2(_1060_),
+ .C1(_1050_),
+ .X(_0084_));
+ sky130_fd_sc_hd__o221a_2 _2216_ (.A1(\Config_inst.INST_config_UART.WriteData[10] ),
+ .A2(_1061_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[2] ),
+ .B2(_1060_),
+ .C1(_1050_),
+ .X(_0083_));
+ sky130_fd_sc_hd__o221a_2 _2218_ (.A1(\Config_inst.INST_config_UART.WriteData[9] ),
+ .A2(_1061_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[1] ),
+ .B2(_1060_),
+ .C1(_1050_),
+ .X(_0082_));
+ sky130_fd_sc_hd__o221a_2 _2219_ (.A1(\Config_inst.INST_config_UART.WriteData[8] ),
+ .A2(_1061_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[0] ),
+ .B2(_1060_),
+ .C1(_1050_),
+ .X(_0081_));
+ sky130_fd_sc_hd__or3_1 _2220_ (.A(\Config_inst.INST_config_UART.GetWordState[1] ),
+ .B(_1044_),
+ .C(_1045_),
+ .X(_1066_));
+ sky130_fd_sc_hd__inv_2 _2221_ (.A(_1066_),
+ .Y(_1067_));
+ sky130_fd_sc_hd__o221a_2 _2224_ (.A1(\Config_inst.INST_config_UART.WriteData[23] ),
+ .A2(_1067_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[7] ),
+ .B2(_1066_),
+ .C1(_1050_),
+ .X(_0080_));
+ sky130_fd_sc_hd__o221a_2 _2225_ (.A1(\Config_inst.INST_config_UART.WriteData[22] ),
+ .A2(_1067_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[6] ),
+ .B2(_1066_),
+ .C1(_1050_),
+ .X(_0079_));
+ sky130_fd_sc_hd__o221a_2 _2226_ (.A1(\Config_inst.INST_config_UART.WriteData[21] ),
+ .A2(_1067_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[5] ),
+ .B2(_1066_),
+ .C1(_1050_),
+ .X(_0078_));
+ sky130_fd_sc_hd__o221a_2 _2228_ (.A1(\Config_inst.INST_config_UART.WriteData[20] ),
+ .A2(_1067_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[4] ),
+ .B2(_1066_),
+ .C1(_1050_),
+ .X(_0077_));
+ sky130_fd_sc_hd__o221a_2 _2229_ (.A1(\Config_inst.INST_config_UART.WriteData[19] ),
+ .A2(_1067_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[3] ),
+ .B2(_1066_),
+ .C1(_1050_),
+ .X(_0076_));
+ sky130_fd_sc_hd__o221a_2 _2230_ (.A1(\Config_inst.INST_config_UART.WriteData[18] ),
+ .A2(_1067_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[2] ),
+ .B2(_1066_),
+ .C1(_1050_),
+ .X(_0075_));
+ sky130_fd_sc_hd__o221a_2 _2231_ (.A1(\Config_inst.INST_config_UART.WriteData[17] ),
+ .A2(_1067_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[1] ),
+ .B2(_1066_),
+ .C1(_1050_),
+ .X(_0074_));
+ sky130_fd_sc_hd__o221a_2 _2232_ (.A1(\Config_inst.INST_config_UART.WriteData[16] ),
+ .A2(_1067_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[0] ),
+ .B2(_1066_),
+ .C1(_1050_),
+ .X(_0073_));
+ sky130_fd_sc_hd__or3_1 _2233_ (.A(\Config_inst.INST_config_UART.GetWordState[1] ),
+ .B(\Config_inst.INST_config_UART.GetWordState[0] ),
+ .C(_1045_),
+ .X(_1071_));
+ sky130_fd_sc_hd__inv_2 _2234_ (.A(_1071_),
+ .Y(_1072_));
+ sky130_fd_sc_hd__o221a_2 _2238_ (.A1(\Config_inst.INST_config_UART.WriteData[31] ),
+ .A2(_1072_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[7] ),
+ .B2(_1071_),
+ .C1(_1050_),
+ .X(_0072_));
+ sky130_fd_sc_hd__o221a_2 _2239_ (.A1(\Config_inst.INST_config_UART.WriteData[30] ),
+ .A2(_1072_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[6] ),
+ .B2(_1071_),
+ .C1(_1050_),
+ .X(_0071_));
+ sky130_fd_sc_hd__o221a_2 _2240_ (.A1(\Config_inst.INST_config_UART.WriteData[29] ),
+ .A2(_1072_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[5] ),
+ .B2(_1071_),
+ .C1(_1050_),
+ .X(_0070_));
+ sky130_fd_sc_hd__o221a_2 _2241_ (.A1(\Config_inst.INST_config_UART.WriteData[28] ),
+ .A2(_1072_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[4] ),
+ .B2(_1071_),
+ .C1(_1050_),
+ .X(_0069_));
+ sky130_fd_sc_hd__o221a_2 _2242_ (.A1(\Config_inst.INST_config_UART.WriteData[27] ),
+ .A2(_1072_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[3] ),
+ .B2(_1071_),
+ .C1(_1050_),
+ .X(_0068_));
+ sky130_fd_sc_hd__o221a_2 _2243_ (.A1(\Config_inst.INST_config_UART.WriteData[26] ),
+ .A2(_1072_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[2] ),
+ .B2(_1071_),
+ .C1(_1050_),
+ .X(_0067_));
+ sky130_fd_sc_hd__o221a_2 _2244_ (.A1(\Config_inst.INST_config_UART.WriteData[25] ),
+ .A2(_1072_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[1] ),
+ .B2(_1071_),
+ .C1(_1050_),
+ .X(_0895_));
+ sky130_fd_sc_hd__o221a_2 _2245_ (.A1(\Config_inst.INST_config_UART.WriteData[24] ),
+ .A2(_1072_),
+ .B1(\Config_inst.INST_config_UART.ReceivedByte[0] ),
+ .B2(_1071_),
+ .C1(_1050_),
+ .X(_0894_));
+ sky130_fd_sc_hd__inv_2 _2248_ (.A(\Config_inst.ConfigFSM_inst.state[1] ),
+ .Y(_1078_));
+ sky130_fd_sc_hd__inv_2 _2249_ (.A(\Config_inst.ConfigFSM_inst.state[0] ),
+ .Y(_1079_));
+ sky130_fd_sc_hd__nor2_1 _2251_ (.A(_1078_),
+ .B(_1079_),
+ .Y(_1081_));
+ sky130_fd_sc_hd__o21ba_2 _2252_ (.A1(_0011_),
+ .A2(_1081_),
+ .B1_N(_0019_),
+ .X(_1082_));
+ sky130_fd_sc_hd__inv_2 _2254_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[0] ),
+ .Y(_1084_));
+ sky130_fd_sc_hd__or2_2 _2255_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[4] ),
+ .B(\Config_inst.ConfigFSM_inst.FrameShiftState[3] ),
+ .X(_1085_));
+ sky130_fd_sc_hd__or4_1 _2256_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[2] ),
+ .B(\Config_inst.ConfigFSM_inst.FrameShiftState[1] ),
+ .C(_1084_),
+ .D(_1085_),
+ .X(_1086_));
+ sky130_fd_sc_hd__inv_2 _2257_ (.A(_1082_),
+ .Y(_1087_));
+ sky130_fd_sc_hd__a31o_2 _2258_ (.A1(\Config_inst.ConfigFSM_inst.state[1] ),
+ .A2(_1079_),
+ .A3(_1086_),
+ .B1(_1087_),
+ .X(_1088_));
+ sky130_fd_sc_hd__nor2_1 _2260_ (.A(_1079_),
+ .B(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .Y(_1090_));
+ sky130_fd_sc_hd__inv_2 _2261_ (.A(\Config_inst.INST_config_UART.PresentState[1] ),
+ .Y(_1091_));
+ sky130_fd_sc_hd__or2_2 _2262_ (.A(_1091_),
+ .B(\Config_inst.INST_config_UART.PresentState[0] ),
+ .X(_1092_));
+ sky130_fd_sc_hd__or2_2 _2263_ (.A(_0997_),
+ .B(_1092_),
+ .X(_1093_));
+ sky130_fd_sc_hd__inv_2 _2264_ (.A(_1093_),
+ .Y(FE_OFN74_la_data_out_0));
+ sky130_fd_sc_hd__or2_2 _2265_ (.A(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .B(FE_OFN74_la_data_out_0),
+ .X(_1094_));
+ sky130_fd_sc_hd__or2b_1 _2267_ (.A(\Config_inst.ConfigFSM_inst.old_reset ),
+ .B_N(_1094_),
+ .X(_1095_));
+ sky130_fd_sc_hd__o221a_2 _2268_ (.A1(\Config_inst.ConfigFSM_inst.state[1] ),
+ .A2(_1082_),
+ .B1(_1088_),
+ .B2(_1090_),
+ .C1(_1095_),
+ .X(_0893_));
+ sky130_fd_sc_hd__inv_2 _2269_ (.A(_1095_),
+ .Y(_1096_));
+ sky130_fd_sc_hd__a221oi_1 _2270_ (.A1(\Config_inst.ConfigFSM_inst.state[0] ),
+ .A2(_1082_),
+ .B1(_1079_),
+ .B2(_1088_),
+ .C1(_1096_),
+ .Y(_0892_));
+ sky130_fd_sc_hd__inv_2 _2272_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[3] ),
+ .Y(_1098_));
+ sky130_fd_sc_hd__inv_2 _2273_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[2] ),
+ .Y(_1099_));
+ sky130_fd_sc_hd__nor2_1 _2274_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[1] ),
+ .B(\Config_inst.ConfigFSM_inst.FrameShiftState[0] ),
+ .Y(_1100_));
+ sky130_fd_sc_hd__inv_2 _2275_ (.A(_0011_),
+ .Y(_1101_));
+ sky130_fd_sc_hd__o32a_1 _2276_ (.A1(\Config_inst.ConfigFSM_inst.state[1] ),
+ .A2(_1079_),
+ .A3(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .B1(_1078_),
+ .B2(\Config_inst.ConfigFSM_inst.state[0] ),
+ .X(_1102_));
+ sky130_fd_sc_hd__or2_2 _2277_ (.A(_1101_),
+ .B(_1102_),
+ .X(_1103_));
+ sky130_fd_sc_hd__inv_2 _2278_ (.A(_1103_),
+ .Y(_1104_));
+ sky130_fd_sc_hd__and3_1 _2279_ (.A(_1099_),
+ .B(_1100_),
+ .C(_1104_),
+ .X(_1105_));
+ sky130_fd_sc_hd__nand2_1 _2280_ (.A(_1098_),
+ .B(_1105_),
+ .Y(_1106_));
+ sky130_fd_sc_hd__inv_2 _2281_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[4] ),
+ .Y(_1107_));
+ sky130_fd_sc_hd__inv_2 _2282_ (.A(_1106_),
+ .Y(_1108_));
+ sky130_fd_sc_hd__or4_1 _2284_ (.A(\Config_inst.ConfigFSM_inst.state[1] ),
+ .B(_1079_),
+ .C(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .D(_1101_),
+ .X(_1110_));
+ sky130_fd_sc_hd__o221a_2 _2285_ (.A1(\Config_inst.ConfigFSM_inst.FrameShiftState[4] ),
+ .A2(_1106_),
+ .B1(_1107_),
+ .B2(_1108_),
+ .C1(_1110_),
+ .X(_1111_));
+ sky130_fd_sc_hd__nor2_1 _2286_ (.A(_1096_),
+ .B(_1111_),
+ .Y(_0891_));
+ sky130_fd_sc_hd__nor2_1 _2287_ (.A(_1098_),
+ .B(_1105_),
+ .Y(_1112_));
+ sky130_fd_sc_hd__and2_1 _2288_ (.A(_1095_),
+ .B(_1110_),
+ .X(_1113_));
+ sky130_fd_sc_hd__o21a_1 _2289_ (.A1(_1108_),
+ .A2(_1112_),
+ .B1(_1113_),
+ .X(_0890_));
+ sky130_fd_sc_hd__or3_1 _2290_ (.A(_1078_),
+ .B(\Config_inst.ConfigFSM_inst.state[0] ),
+ .C(_1101_),
+ .X(_1114_));
+ sky130_fd_sc_hd__o32a_1 _2292_ (.A1(\Config_inst.ConfigFSM_inst.FrameShiftState[1] ),
+ .A2(\Config_inst.ConfigFSM_inst.FrameShiftState[0] ),
+ .A3(\Config_inst.ConfigFSM_inst.FrameShiftState[2] ),
+ .B1(_1099_),
+ .B2(_1100_),
+ .X(_1116_));
+ sky130_fd_sc_hd__o22a_1 _2293_ (.A1(_1099_),
+ .A2(_1104_),
+ .B1(_1114_),
+ .B2(_1116_),
+ .X(_1117_));
+ sky130_fd_sc_hd__nor2_1 _2294_ (.A(_1096_),
+ .B(_1117_),
+ .Y(_0889_));
+ sky130_fd_sc_hd__inv_2 _2295_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[1] ),
+ .Y(_1118_));
+ sky130_fd_sc_hd__o21ai_1 _2296_ (.A1(\Config_inst.ConfigFSM_inst.FrameShiftState[0] ),
+ .A2(_1103_),
+ .B1(_1118_),
+ .Y(_1119_));
+ sky130_fd_sc_hd__o311a_1 _2297_ (.A1(\Config_inst.ConfigFSM_inst.FrameShiftState[0] ),
+ .A2(_1103_),
+ .A3(_1118_),
+ .B1(_1113_),
+ .C1(_1119_),
+ .X(_0888_));
+ sky130_fd_sc_hd__a221oi_1 _2298_ (.A1(_1084_),
+ .A2(_1114_),
+ .B1(\Config_inst.ConfigFSM_inst.FrameShiftState[0] ),
+ .B2(_1104_),
+ .C1(_1096_),
+ .Y(_0887_));
+ sky130_fd_sc_hd__nand2_1 _2299_ (.A(\Config_inst.Inst_bitbang.serial_control[15] ),
+ .B(\Config_inst.Inst_bitbang.serial_control[14] ),
+ .Y(_1120_));
+ sky130_fd_sc_hd__nand4b_1 _2300_ (.A_N(\Config_inst.Inst_bitbang.serial_control[10] ),
+ .B(\Config_inst.Inst_bitbang.serial_control[12] ),
+ .C(\Config_inst.Inst_bitbang.serial_control[11] ),
+ .D(\Config_inst.Inst_bitbang.serial_control[13] ),
+ .Y(_1121_));
+ sky130_fd_sc_hd__nand3b_1 _2301_ (.A_N(\Config_inst.Inst_bitbang.serial_control[1] ),
+ .B(\Config_inst.Inst_bitbang.serial_control[4] ),
+ .C(\Config_inst.Inst_bitbang.serial_control[5] ),
+ .Y(_1122_));
+ sky130_fd_sc_hd__or4bb_1 _2302_ (.A(\Config_inst.Inst_bitbang.serial_control[6] ),
+ .B(\Config_inst.Inst_bitbang.serial_control[8] ),
+ .C_N(\Config_inst.Inst_bitbang.serial_control[7] ),
+ .D_N(\Config_inst.Inst_bitbang.serial_control[9] ),
+ .X(_1123_));
+ sky130_fd_sc_hd__or4_1 _2303_ (.A(_1120_),
+ .B(_1121_),
+ .C(_1122_),
+ .D(_1123_),
+ .X(_1124_));
+ sky130_fd_sc_hd__or4b_2 _2304_ (.A(\Config_inst.Inst_bitbang.serial_control[3] ),
+ .B(\Config_inst.Inst_bitbang.serial_control[2] ),
+ .C(_1124_),
+ .D_N(\Config_inst.Inst_bitbang.serial_control[0] ),
+ .X(_1125_));
+ sky130_fd_sc_hd__inv_2 _2306_ (.A(_1125_),
+ .Y(_1127_));
+ sky130_fd_sc_hd__or4_1 _2309_ (.A(\Config_inst.Inst_bitbang.serial_control[3] ),
+ .B(\Config_inst.Inst_bitbang.serial_control[2] ),
+ .C(\Config_inst.Inst_bitbang.serial_control[0] ),
+ .D(_1124_),
+ .X(_1129_));
+ sky130_fd_sc_hd__o21a_1 _2310_ (.A1(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .A2(_1127_),
+ .B1(_1129_),
+ .X(_0886_));
+ sky130_fd_sc_hd__or2_2 _2312_ (.A(\Config_inst.INST_config_UART.ComState[1] ),
+ .B(\Config_inst.INST_config_UART.ComState[0] ),
+ .X(_1131_));
+ sky130_fd_sc_hd__or3_1 _2313_ (.A(\Config_inst.INST_config_UART.ComState[3] ),
+ .B(\Config_inst.INST_config_UART.ComState[2] ),
+ .C(_1131_),
+ .X(_1132_));
+ sky130_fd_sc_hd__inv_2 _2314_ (.A(_1132_),
+ .Y(_1133_));
+ sky130_fd_sc_hd__or3_1 _2316_ (.A(\Config_inst.INST_config_UART.ComCount[1] ),
+ .B(\Config_inst.INST_config_UART.ComCount[0] ),
+ .C(\Config_inst.INST_config_UART.ComCount[2] ),
+ .X(_1134_));
+ sky130_fd_sc_hd__or3_1 _2317_ (.A(\Config_inst.INST_config_UART.ComCount[3] ),
+ .B(_1134_),
+ .C(\Config_inst.INST_config_UART.ComCount[4] ),
+ .X(_1135_));
+ sky130_fd_sc_hd__or3_1 _2318_ (.A(\Config_inst.INST_config_UART.ComCount[5] ),
+ .B(_1135_),
+ .C(\Config_inst.INST_config_UART.ComCount[6] ),
+ .X(_1136_));
+ sky130_fd_sc_hd__or2_2 _2319_ (.A(\Config_inst.INST_config_UART.ComCount[7] ),
+ .B(_1136_),
+ .X(_1137_));
+ sky130_fd_sc_hd__inv_2 _2320_ (.A(_1137_),
+ .Y(_1138_));
+ sky130_fd_sc_hd__and2_1 _2321_ (.A(\Config_inst.INST_config_UART.ComCount[7] ),
+ .B(_1136_),
+ .X(_1139_));
+ sky130_fd_sc_hd__o21a_1 _2323_ (.A1(_1138_),
+ .A2(_1139_),
+ .B1(_1132_),
+ .X(_0885_));
+ sky130_fd_sc_hd__o21ai_1 _2324_ (.A1(\Config_inst.INST_config_UART.ComCount[5] ),
+ .A2(_1135_),
+ .B1(\Config_inst.INST_config_UART.ComCount[6] ),
+ .Y(_1141_));
+ sky130_fd_sc_hd__or2_2 _2325_ (.A(\Config_inst.INST_config_UART.ComCount[8] ),
+ .B(_1137_),
+ .X(_1142_));
+ sky130_fd_sc_hd__or2_2 _2326_ (.A(\Config_inst.INST_config_UART.ComCount[9] ),
+ .B(_1142_),
+ .X(_1143_));
+ sky130_fd_sc_hd__or4_1 _2327_ (.A(\Config_inst.INST_config_UART.ComCount[10] ),
+ .B(_1143_),
+ .C(\Config_inst.INST_config_UART.ComCount[11] ),
+ .D(_1133_),
+ .X(_1144_));
+ sky130_fd_sc_hd__inv_2 _2328_ (.A(_1144_),
+ .Y(_0874_));
+ sky130_fd_sc_hd__a31oi_1 _2329_ (.A1(_1132_),
+ .A2(_1136_),
+ .A3(_1141_),
+ .B1(_0874_),
+ .Y(_0884_));
+ sky130_fd_sc_hd__a2bb2oi_1 _2330_ (.A1_N(\Config_inst.INST_config_UART.ComCount[5] ),
+ .A2_N(_1135_),
+ .B1(\Config_inst.INST_config_UART.ComCount[5] ),
+ .B2(_1135_),
+ .Y(_1145_));
+ sky130_fd_sc_hd__nor2_1 _2331_ (.A(_1133_),
+ .B(_1145_),
+ .Y(_0883_));
+ sky130_fd_sc_hd__o21ai_1 _2332_ (.A1(\Config_inst.INST_config_UART.ComCount[3] ),
+ .A2(_1134_),
+ .B1(\Config_inst.INST_config_UART.ComCount[4] ),
+ .Y(_1146_));
+ sky130_fd_sc_hd__a31oi_1 _2333_ (.A1(_1132_),
+ .A2(_1135_),
+ .A3(_1146_),
+ .B1(_0874_),
+ .Y(_0882_));
+ sky130_fd_sc_hd__inv_2 _2334_ (.A(\Config_inst.INST_config_UART.ComCount[3] ),
+ .Y(_1147_));
+ sky130_fd_sc_hd__inv_2 _2335_ (.A(_1134_),
+ .Y(_1148_));
+ sky130_fd_sc_hd__o22a_1 _2336_ (.A1(\Config_inst.INST_config_UART.ComCount[3] ),
+ .A2(_1134_),
+ .B1(_1147_),
+ .B2(_1148_),
+ .X(_1149_));
+ sky130_fd_sc_hd__nor2_1 _2337_ (.A(_1133_),
+ .B(_1149_),
+ .Y(_0881_));
+ sky130_fd_sc_hd__inv_2 _2338_ (.A(\Config_inst.INST_config_UART.ComCount[0] ),
+ .Y(_1150_));
+ sky130_fd_sc_hd__o21a_1 _2339_ (.A1(_1150_),
+ .A2(_1133_),
+ .B1(_1144_),
+ .X(_0880_));
+ sky130_fd_sc_hd__or4_1 _2340_ (.A(\Config_inst.INST_config_UART.CRCReg[3] ),
+ .B(\Config_inst.INST_config_UART.CRCReg[2] ),
+ .C(\Config_inst.INST_config_UART.CRCReg[1] ),
+ .D(\Config_inst.INST_config_UART.CRCReg[0] ),
+ .X(_1151_));
+ sky130_fd_sc_hd__or4_1 _2341_ (.A(\Config_inst.INST_config_UART.CRCReg[7] ),
+ .B(\Config_inst.INST_config_UART.CRCReg[6] ),
+ .C(\Config_inst.INST_config_UART.CRCReg[5] ),
+ .D(\Config_inst.INST_config_UART.CRCReg[4] ),
+ .X(_1152_));
+ sky130_fd_sc_hd__or2_2 _2342_ (.A(\Config_inst.INST_config_UART.CRCReg[19] ),
+ .B(_0947_),
+ .X(_1153_));
+ sky130_fd_sc_hd__or4_1 _2343_ (.A(_1012_),
+ .B(_1013_),
+ .C(_0948_),
+ .D(\Config_inst.INST_config_UART.CRCReg[10] ),
+ .X(_1154_));
+ sky130_fd_sc_hd__or4_1 _2344_ (.A(\Config_inst.INST_config_UART.CRCReg[17] ),
+ .B(\Config_inst.INST_config_UART.CRCReg[16] ),
+ .C(_1153_),
+ .D(_1154_),
+ .X(_1155_));
+ sky130_fd_sc_hd__or4_1 _2345_ (.A(_1151_),
+ .B(_1152_),
+ .C(_0990_),
+ .D(_1155_),
+ .X(_1156_));
+ sky130_fd_sc_hd__a31o_2 _2346_ (.A1(\Config_inst.INST_config_UART.blink[22] ),
+ .A2(_0911_),
+ .A3(_1156_),
+ .B1(FE_OFN74_la_data_out_0),
+ .X(_0879_));
+ sky130_fd_sc_hd__inv_2 _2347_ (.A(\Config_inst.INST_config_UART.ComTick ),
+ .Y(_1157_));
+ sky130_fd_sc_hd__or2_2 _2348_ (.A(_1157_),
+ .B(_0906_),
+ .X(_1158_));
+ sky130_fd_sc_hd__or2_2 _2350_ (.A(_1093_),
+ .B(_1158_),
+ .X(_1160_));
+ sky130_fd_sc_hd__inv_2 _2351_ (.A(_1160_),
+ .Y(_1161_));
+ sky130_fd_sc_hd__nor2_1 _2353_ (.A(_0912_),
+ .B(_0916_),
+ .Y(_0877_));
+ sky130_fd_sc_hd__or4bb_1 _2354_ (.A(\Config_inst.INST_config_UART.ReceivedWord[7] ),
+ .B(\Config_inst.INST_config_UART.ReceivedWord[6] ),
+ .C_N(\Config_inst.INST_config_UART.ReceivedWord[5] ),
+ .D_N(\Config_inst.INST_config_UART.ReceivedWord[4] ),
+ .X(_1162_));
+ sky130_fd_sc_hd__or2_2 _2355_ (.A(\Config_inst.INST_config_UART.ReceivedWord[3] ),
+ .B(_1162_),
+ .X(_1163_));
+ sky130_fd_sc_hd__or4b_2 _2357_ (.A(\Config_inst.INST_config_UART.ReceivedWord[4] ),
+ .B(\Config_inst.INST_config_UART.ReceivedWord[3] ),
+ .C(\Config_inst.INST_config_UART.ReceivedWord[7] ),
+ .D_N(\Config_inst.INST_config_UART.ReceivedWord[6] ),
+ .X(_1165_));
+ sky130_fd_sc_hd__nor2_1 _2358_ (.A(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .B(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .Y(_1166_));
+ sky130_fd_sc_hd__inv_2 _2359_ (.A(\Config_inst.INST_config_UART.ReceivedWord[3] ),
+ .Y(_0032_));
+ sky130_fd_sc_hd__or4_1 _2360_ (.A(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .B(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .C(_0032_),
+ .D(_1162_),
+ .X(_1167_));
+ sky130_fd_sc_hd__inv_2 _2361_ (.A(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .Y(_0030_));
+ sky130_fd_sc_hd__a211o_1 _2362_ (.A1(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .A2(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .B1(_0030_),
+ .C1(_1165_),
+ .X(_1168_));
+ sky130_fd_sc_hd__o311a_1 _2363_ (.A1(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .A2(_1165_),
+ .A3(_1166_),
+ .B1(_1167_),
+ .C1(_1168_),
+ .X(_1169_));
+ sky130_fd_sc_hd__a21o_1 _2365_ (.A1(_1163_),
+ .A2(_1169_),
+ .B1(_1158_),
+ .X(_1170_));
+ sky130_fd_sc_hd__or2_2 _2366_ (.A(\Config_inst.INST_config_UART.ReceiveState ),
+ .B(_1170_),
+ .X(_1171_));
+ sky130_fd_sc_hd__inv_2 _2367_ (.A(_1171_),
+ .Y(_1172_));
+ sky130_fd_sc_hd__or2_2 _2369_ (.A(_1093_),
+ .B(_1170_),
+ .X(_1173_));
+ sky130_fd_sc_hd__or2_2 _2371_ (.A(_1101_),
+ .B(_1086_),
+ .X(_1174_));
+ sky130_fd_sc_hd__inv_8 _2372_ (.A(FE_OFN0_1174),
+ .Y(_1175_));
+ sky130_fd_sc_hd__and4_1 _2373_ (.A(\Config_inst.ConfigFSM_inst.state[1] ),
+ .B(_1079_),
+ .C(_1095_),
+ .D(_1175_),
+ .X(_1176_));
+ sky130_fd_sc_hd__o31a_1 _2375_ (.A1(\Config_inst.INST_config_UART.ComCount[10] ),
+ .A2(_1143_),
+ .A3(\Config_inst.INST_config_UART.ComCount[11] ),
+ .B1(_1132_),
+ .X(_1177_));
+ sky130_fd_sc_hd__o211a_2 _2376_ (.A1(\Config_inst.INST_config_UART.ComCount[10] ),
+ .A2(_1143_),
+ .B1(\Config_inst.INST_config_UART.ComCount[11] ),
+ .C1(_1177_),
+ .X(_0872_));
+ sky130_fd_sc_hd__inv_2 _2377_ (.A(_1177_),
+ .Y(_1178_));
+ sky130_fd_sc_hd__inv_2 _2378_ (.A(\Config_inst.INST_config_UART.ComCount[10] ),
+ .Y(_1179_));
+ sky130_fd_sc_hd__inv_2 _2379_ (.A(_1143_),
+ .Y(_1180_));
+ sky130_fd_sc_hd__o22a_1 _2380_ (.A1(\Config_inst.INST_config_UART.ComCount[10] ),
+ .A2(_1143_),
+ .B1(_1179_),
+ .B2(_1180_),
+ .X(_1181_));
+ sky130_fd_sc_hd__nor2_1 _2381_ (.A(_1178_),
+ .B(_1181_),
+ .Y(_0871_));
+ sky130_fd_sc_hd__and2_1 _2382_ (.A(\Config_inst.INST_config_UART.ComCount[9] ),
+ .B(_1142_),
+ .X(_1182_));
+ sky130_fd_sc_hd__o21a_1 _2383_ (.A1(_1180_),
+ .A2(_1182_),
+ .B1(_1177_),
+ .X(_0870_));
+ sky130_fd_sc_hd__nand2_1 _2384_ (.A(\Config_inst.INST_config_UART.ComCount[8] ),
+ .B(_1137_),
+ .Y(_1183_));
+ sky130_fd_sc_hd__a21oi_1 _2385_ (.A1(_1142_),
+ .A2(_1183_),
+ .B1(_1178_),
+ .Y(_0869_));
+ sky130_fd_sc_hd__o21a_1 _2386_ (.A1(\Config_inst.INST_config_UART.ComCount[1] ),
+ .A2(\Config_inst.INST_config_UART.ComCount[0] ),
+ .B1(\Config_inst.INST_config_UART.ComCount[2] ),
+ .X(_1184_));
+ sky130_fd_sc_hd__or3_1 _2387_ (.A(_1148_),
+ .B(_1184_),
+ .C(_1178_),
+ .X(_1185_));
+ sky130_fd_sc_hd__inv_2 _2389_ (.A(\Config_inst.INST_config_UART.ComCount[1] ),
+ .Y(_1186_));
+ sky130_fd_sc_hd__a221o_1 _2390_ (.A1(_1186_),
+ .A2(_1150_),
+ .B1(\Config_inst.INST_config_UART.ComCount[1] ),
+ .B2(\Config_inst.INST_config_UART.ComCount[0] ),
+ .C1(_1178_),
+ .X(_0867_));
+ sky130_fd_sc_hd__or4_2 _2393_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[4] ),
+ .B(_1101_),
+ .C(_1118_),
+ .D(_1084_),
+ .X(_1189_));
+ sky130_fd_sc_hd__or2_2 _2394_ (.A(_1187_),
+ .B(_1189_),
+ .X(_1190_));
+ sky130_fd_sc_hd__inv_2 _2399_ (.A(FE_OFN1_1190),
+ .Y(_1195_));
+ sky130_fd_sc_hd__a22o_1 _2402_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[31] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN153_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1195_),
+ .X(_0866_));
+ sky130_fd_sc_hd__a22o_1 _2405_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[30] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN151_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1195_),
+ .X(_0865_));
+ sky130_fd_sc_hd__a22o_1 _2408_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[29] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN148_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1195_),
+ .X(_0864_));
+ sky130_fd_sc_hd__a22o_1 _2411_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[28] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN146_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1195_),
+ .X(_0863_));
+ sky130_fd_sc_hd__a22o_1 _2414_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[27] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN144_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1195_),
+ .X(_0862_));
+ sky130_fd_sc_hd__a22o_1 _2418_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[26] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[26] ),
+ .B2(_1195_),
+ .X(_0861_));
+ sky130_fd_sc_hd__a22o_1 _2420_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[25] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[25] ),
+ .B2(_1195_),
+ .X(_0860_));
+ sky130_fd_sc_hd__a22o_1 _2422_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[24] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1195_),
+ .X(_0859_));
+ sky130_fd_sc_hd__a22o_1 _2424_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[23] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[23] ),
+ .B2(_1195_),
+ .X(_0858_));
+ sky130_fd_sc_hd__a22o_1 _2426_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[22] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[22] ),
+ .B2(_1195_),
+ .X(_0857_));
+ sky130_fd_sc_hd__a22o_1 _2430_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[21] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[21] ),
+ .B2(_1195_),
+ .X(_0856_));
+ sky130_fd_sc_hd__a22o_1 _2432_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[20] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .B2(_1195_),
+ .X(_0855_));
+ sky130_fd_sc_hd__a22o_1 _2435_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[19] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN129_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1195_),
+ .X(_0854_));
+ sky130_fd_sc_hd__a22o_1 _2438_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[18] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN127_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1195_),
+ .X(_0853_));
+ sky130_fd_sc_hd__a22o_1 _2441_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[17] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN125_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1195_),
+ .X(_0852_));
+ sky130_fd_sc_hd__a22o_1 _2446_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[16] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN123_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1195_),
+ .X(_0851_));
+ sky130_fd_sc_hd__a22o_1 _2449_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[15] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[15] ),
+ .B2(_1195_),
+ .X(_0850_));
+ sky130_fd_sc_hd__a22o_1 _2452_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[14] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN119_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1195_),
+ .X(_0849_));
+ sky130_fd_sc_hd__a22o_1 _2455_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[13] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[13] ),
+ .B2(_1195_),
+ .X(_0848_));
+ sky130_fd_sc_hd__a22o_1 _2458_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[12] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN115_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1195_),
+ .X(_0847_));
+ sky130_fd_sc_hd__a22o_1 _2463_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[11] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[11] ),
+ .B2(_1195_),
+ .X(_0846_));
+ sky130_fd_sc_hd__a22o_1 _2466_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[10] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[10] ),
+ .B2(_1195_),
+ .X(_0845_));
+ sky130_fd_sc_hd__a22o_1 _2469_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[9] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[9] ),
+ .B2(_1195_),
+ .X(_0844_));
+ sky130_fd_sc_hd__a22o_1 _2472_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[8] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN165_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1195_),
+ .X(_0843_));
+ sky130_fd_sc_hd__a22o_1 _2475_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[7] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN163_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1195_),
+ .X(_0842_));
+ sky130_fd_sc_hd__a22o_1 _2480_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[6] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[6] ),
+ .B2(_1195_),
+ .X(_0841_));
+ sky130_fd_sc_hd__a22o_1 _2483_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[5] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[5] ),
+ .B2(_1195_),
+ .X(_0840_));
+ sky130_fd_sc_hd__a22o_1 _2486_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[4] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[4] ),
+ .B2(_1195_),
+ .X(_0839_));
+ sky130_fd_sc_hd__a22o_1 _2489_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[3] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[3] ),
+ .B2(_1195_),
+ .X(_0838_));
+ sky130_fd_sc_hd__a22o_1 _2492_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[2] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[2] ),
+ .B2(_1195_),
+ .X(_0837_));
+ sky130_fd_sc_hd__a22o_1 _2495_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[1] ),
+ .A2(FE_OFN1_1190),
+ .B1(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1195_),
+ .X(_0836_));
+ sky130_fd_sc_hd__a22o_1 _2498_ (.A1(\Inst_Frame_Data_Reg_14.FrameData_O[0] ),
+ .A2(FE_OFN1_1190),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[0] ),
+ .B2(_1195_),
+ .X(_0835_));
+ sky130_fd_sc_hd__or4_2 _2499_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[4] ),
+ .B(_1101_),
+ .C(_1118_),
+ .D(\Config_inst.ConfigFSM_inst.FrameShiftState[0] ),
+ .X(_1263_));
+ sky130_fd_sc_hd__or2_4 _2500_ (.A(_1187_),
+ .B(_1263_),
+ .X(_1264_));
+ sky130_fd_sc_hd__inv_2 _2503_ (.A(_1264_),
+ .Y(_1267_));
+ sky130_fd_sc_hd__a22o_1 _2506_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[31] ),
+ .A2(_1264_),
+ .B1(FE_OFN153_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1267_),
+ .X(_0834_));
+ sky130_fd_sc_hd__a22o_1 _2507_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[30] ),
+ .A2(_1264_),
+ .B1(FE_OFN151_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1267_),
+ .X(_0833_));
+ sky130_fd_sc_hd__a22o_1 _2508_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[29] ),
+ .A2(_1264_),
+ .B1(FE_OFN148_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1267_),
+ .X(_0832_));
+ sky130_fd_sc_hd__a22o_1 _2509_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[28] ),
+ .A2(_1264_),
+ .B1(FE_OFN146_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1267_),
+ .X(_0831_));
+ sky130_fd_sc_hd__a22o_1 _2510_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[27] ),
+ .A2(_1264_),
+ .B1(FE_OFN144_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1267_),
+ .X(_0830_));
+ sky130_fd_sc_hd__a22o_1 _2513_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[26] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[26] ),
+ .B2(_1267_),
+ .X(_0829_));
+ sky130_fd_sc_hd__a22o_1 _2514_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[25] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[25] ),
+ .B2(_1267_),
+ .X(_0828_));
+ sky130_fd_sc_hd__a22o_1 _2515_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[24] ),
+ .A2(_1264_),
+ .B1(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1267_),
+ .X(_0827_));
+ sky130_fd_sc_hd__a22o_1 _2516_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[23] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[23] ),
+ .B2(_1267_),
+ .X(_0826_));
+ sky130_fd_sc_hd__a22o_1 _2517_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[22] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[22] ),
+ .B2(_1267_),
+ .X(_0825_));
+ sky130_fd_sc_hd__a22o_1 _2520_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[21] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[21] ),
+ .B2(_1267_),
+ .X(_0824_));
+ sky130_fd_sc_hd__a22o_1 _2521_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[20] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .B2(_1267_),
+ .X(_0823_));
+ sky130_fd_sc_hd__a22o_1 _2522_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[19] ),
+ .A2(_1264_),
+ .B1(FE_OFN129_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1267_),
+ .X(_0822_));
+ sky130_fd_sc_hd__a22o_1 _2523_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[18] ),
+ .A2(_1264_),
+ .B1(FE_OFN127_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1267_),
+ .X(_0821_));
+ sky130_fd_sc_hd__a22o_1 _2524_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[17] ),
+ .A2(_1264_),
+ .B1(FE_OFN125_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1267_),
+ .X(_0820_));
+ sky130_fd_sc_hd__a22o_1 _2527_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[16] ),
+ .A2(_1264_),
+ .B1(FE_OFN123_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1267_),
+ .X(_0819_));
+ sky130_fd_sc_hd__a22o_1 _2528_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[15] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[15] ),
+ .B2(_1267_),
+ .X(_0818_));
+ sky130_fd_sc_hd__a22o_1 _2529_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[14] ),
+ .A2(_1264_),
+ .B1(FE_OFN119_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1267_),
+ .X(_0817_));
+ sky130_fd_sc_hd__a22o_1 _2530_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[13] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[13] ),
+ .B2(_1267_),
+ .X(_0816_));
+ sky130_fd_sc_hd__a22o_1 _2531_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[12] ),
+ .A2(_1264_),
+ .B1(FE_OFN115_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1267_),
+ .X(_0815_));
+ sky130_fd_sc_hd__a22o_1 _2534_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[11] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[11] ),
+ .B2(_1267_),
+ .X(_0814_));
+ sky130_fd_sc_hd__a22o_1 _2535_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[10] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[10] ),
+ .B2(_1267_),
+ .X(_0813_));
+ sky130_fd_sc_hd__a22o_1 _2536_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[9] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[9] ),
+ .B2(_1267_),
+ .X(_0812_));
+ sky130_fd_sc_hd__a22o_1 _2537_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[8] ),
+ .A2(_1264_),
+ .B1(FE_OFN165_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1267_),
+ .X(_0811_));
+ sky130_fd_sc_hd__a22o_1 _2538_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[7] ),
+ .A2(_1264_),
+ .B1(FE_OFN163_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1267_),
+ .X(_0810_));
+ sky130_fd_sc_hd__a22o_1 _2541_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[6] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[6] ),
+ .B2(_1267_),
+ .X(_0809_));
+ sky130_fd_sc_hd__a22o_1 _2542_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[5] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[5] ),
+ .B2(_1267_),
+ .X(_0808_));
+ sky130_fd_sc_hd__a22o_1 _2543_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[4] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[4] ),
+ .B2(_1267_),
+ .X(_0807_));
+ sky130_fd_sc_hd__a22o_1 _2544_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[3] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[3] ),
+ .B2(_1267_),
+ .X(_0806_));
+ sky130_fd_sc_hd__a22o_1 _2545_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[2] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[2] ),
+ .B2(_1267_),
+ .X(_0805_));
+ sky130_fd_sc_hd__a22o_1 _2546_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[1] ),
+ .A2(_1264_),
+ .B1(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1267_),
+ .X(_0804_));
+ sky130_fd_sc_hd__a22o_1 _2547_ (.A1(\Inst_Frame_Data_Reg_13.FrameData_O[0] ),
+ .A2(_1264_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[0] ),
+ .B2(_1267_),
+ .X(_0803_));
+ sky130_fd_sc_hd__or4_1 _2548_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[1] ),
+ .B(_1084_),
+ .C(\Config_inst.ConfigFSM_inst.FrameShiftState[4] ),
+ .D(_1101_),
+ .X(_1280_));
+ sky130_fd_sc_hd__or2_4 _2549_ (.A(_1187_),
+ .B(_1280_),
+ .X(_1281_));
+ sky130_fd_sc_hd__inv_2 _2552_ (.A(_1281_),
+ .Y(_1284_));
+ sky130_fd_sc_hd__a22o_1 _2555_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[31] ),
+ .A2(_1281_),
+ .B1(FE_OFN153_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1284_),
+ .X(_0802_));
+ sky130_fd_sc_hd__a22o_1 _2556_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[30] ),
+ .A2(_1281_),
+ .B1(FE_OFN151_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1284_),
+ .X(_0801_));
+ sky130_fd_sc_hd__a22o_1 _2557_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[29] ),
+ .A2(_1281_),
+ .B1(FE_OFN148_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1284_),
+ .X(_0800_));
+ sky130_fd_sc_hd__a22o_1 _2558_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[28] ),
+ .A2(_1281_),
+ .B1(FE_OFN146_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1284_),
+ .X(_0799_));
+ sky130_fd_sc_hd__a22o_1 _2559_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[27] ),
+ .A2(_1281_),
+ .B1(FE_OFN144_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1284_),
+ .X(_0798_));
+ sky130_fd_sc_hd__a22o_1 _2562_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[26] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[26] ),
+ .B2(_1284_),
+ .X(_0797_));
+ sky130_fd_sc_hd__a22o_1 _2563_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[25] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[25] ),
+ .B2(_1284_),
+ .X(_0796_));
+ sky130_fd_sc_hd__a22o_1 _2564_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[24] ),
+ .A2(_1281_),
+ .B1(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1284_),
+ .X(_0795_));
+ sky130_fd_sc_hd__a22o_1 _2565_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[23] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[23] ),
+ .B2(_1284_),
+ .X(_0794_));
+ sky130_fd_sc_hd__a22o_1 _2566_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[22] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[22] ),
+ .B2(_1284_),
+ .X(_0793_));
+ sky130_fd_sc_hd__a22o_1 _2569_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[21] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[21] ),
+ .B2(_1284_),
+ .X(_0792_));
+ sky130_fd_sc_hd__a22o_1 _2570_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[20] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .B2(_1284_),
+ .X(_0791_));
+ sky130_fd_sc_hd__a22o_1 _2571_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[19] ),
+ .A2(_1281_),
+ .B1(FE_OFN129_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1284_),
+ .X(_0790_));
+ sky130_fd_sc_hd__a22o_1 _2572_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[18] ),
+ .A2(_1281_),
+ .B1(FE_OFN127_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1284_),
+ .X(_0789_));
+ sky130_fd_sc_hd__a22o_1 _2573_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[17] ),
+ .A2(_1281_),
+ .B1(FE_OFN125_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1284_),
+ .X(_0788_));
+ sky130_fd_sc_hd__a22o_1 _2576_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[16] ),
+ .A2(_1281_),
+ .B1(FE_OFN123_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1284_),
+ .X(_0787_));
+ sky130_fd_sc_hd__a22o_1 _2577_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[15] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[15] ),
+ .B2(_1284_),
+ .X(_0786_));
+ sky130_fd_sc_hd__a22o_1 _2578_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[14] ),
+ .A2(_1281_),
+ .B1(FE_OFN119_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1284_),
+ .X(_0785_));
+ sky130_fd_sc_hd__a22o_1 _2579_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[13] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[13] ),
+ .B2(_1284_),
+ .X(_0784_));
+ sky130_fd_sc_hd__a22o_1 _2580_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[12] ),
+ .A2(_1281_),
+ .B1(FE_OFN115_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1284_),
+ .X(_0783_));
+ sky130_fd_sc_hd__a22o_1 _2583_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[11] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[11] ),
+ .B2(_1284_),
+ .X(_0782_));
+ sky130_fd_sc_hd__a22o_1 _2584_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[10] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[10] ),
+ .B2(_1284_),
+ .X(_0781_));
+ sky130_fd_sc_hd__a22o_1 _2585_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[9] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[9] ),
+ .B2(_1284_),
+ .X(_0780_));
+ sky130_fd_sc_hd__a22o_1 _2586_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[8] ),
+ .A2(_1281_),
+ .B1(FE_OFN165_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1284_),
+ .X(_0779_));
+ sky130_fd_sc_hd__a22o_1 _2587_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[7] ),
+ .A2(_1281_),
+ .B1(FE_OFN163_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1284_),
+ .X(_0778_));
+ sky130_fd_sc_hd__a22o_1 _2590_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[6] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[6] ),
+ .B2(_1284_),
+ .X(_0777_));
+ sky130_fd_sc_hd__a22o_1 _2591_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[5] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[5] ),
+ .B2(_1284_),
+ .X(_0776_));
+ sky130_fd_sc_hd__a22o_1 _2592_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[4] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[4] ),
+ .B2(_1284_),
+ .X(_0775_));
+ sky130_fd_sc_hd__a22o_1 _2593_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[3] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[3] ),
+ .B2(_1284_),
+ .X(_0774_));
+ sky130_fd_sc_hd__a22o_1 _2594_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[2] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[2] ),
+ .B2(_1284_),
+ .X(_0773_));
+ sky130_fd_sc_hd__a22o_1 _2595_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[1] ),
+ .A2(_1281_),
+ .B1(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1284_),
+ .X(_0772_));
+ sky130_fd_sc_hd__a22o_1 _2596_ (.A1(\Inst_Frame_Data_Reg_12.FrameData_O[0] ),
+ .A2(_1281_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[0] ),
+ .B2(_1284_),
+ .X(_0771_));
+ sky130_fd_sc_hd__or4_2 _2597_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[1] ),
+ .B(\Config_inst.ConfigFSM_inst.FrameShiftState[0] ),
+ .C(\Config_inst.ConfigFSM_inst.FrameShiftState[4] ),
+ .D(_1101_),
+ .X(_1297_));
+ sky130_fd_sc_hd__or2_4 _2598_ (.A(_1187_),
+ .B(_1297_),
+ .X(_1298_));
+ sky130_fd_sc_hd__inv_2 _2601_ (.A(_1298_),
+ .Y(_1301_));
+ sky130_fd_sc_hd__a22o_1 _2604_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[31] ),
+ .A2(_1298_),
+ .B1(FE_OFN153_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1301_),
+ .X(_0770_));
+ sky130_fd_sc_hd__a22o_1 _2605_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[30] ),
+ .A2(_1298_),
+ .B1(FE_OFN151_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1301_),
+ .X(_0769_));
+ sky130_fd_sc_hd__a22o_1 _2606_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[29] ),
+ .A2(_1298_),
+ .B1(FE_OFN148_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1301_),
+ .X(_0768_));
+ sky130_fd_sc_hd__a22o_1 _2607_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[28] ),
+ .A2(_1298_),
+ .B1(FE_OFN146_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1301_),
+ .X(_0767_));
+ sky130_fd_sc_hd__a22o_1 _2608_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[27] ),
+ .A2(_1298_),
+ .B1(FE_OFN144_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1301_),
+ .X(_0766_));
+ sky130_fd_sc_hd__a22o_1 _2611_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[26] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[26] ),
+ .B2(_1301_),
+ .X(_0765_));
+ sky130_fd_sc_hd__a22o_1 _2612_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[25] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[25] ),
+ .B2(_1301_),
+ .X(_0764_));
+ sky130_fd_sc_hd__a22o_1 _2613_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[24] ),
+ .A2(_1298_),
+ .B1(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1301_),
+ .X(_0763_));
+ sky130_fd_sc_hd__a22o_1 _2614_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[23] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[23] ),
+ .B2(_1301_),
+ .X(_0762_));
+ sky130_fd_sc_hd__a22o_1 _2615_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[22] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[22] ),
+ .B2(_1301_),
+ .X(_0761_));
+ sky130_fd_sc_hd__a22o_1 _2618_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[21] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[21] ),
+ .B2(_1301_),
+ .X(_0760_));
+ sky130_fd_sc_hd__a22o_1 _2619_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[20] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .B2(_1301_),
+ .X(_0759_));
+ sky130_fd_sc_hd__a22o_1 _2620_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[19] ),
+ .A2(_1298_),
+ .B1(FE_OFN129_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1301_),
+ .X(_0758_));
+ sky130_fd_sc_hd__a22o_1 _2621_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[18] ),
+ .A2(_1298_),
+ .B1(FE_OFN127_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1301_),
+ .X(_0757_));
+ sky130_fd_sc_hd__a22o_1 _2622_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[17] ),
+ .A2(_1298_),
+ .B1(FE_OFN125_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1301_),
+ .X(_0756_));
+ sky130_fd_sc_hd__a22o_1 _2625_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[16] ),
+ .A2(_1298_),
+ .B1(FE_OFN123_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1301_),
+ .X(_0755_));
+ sky130_fd_sc_hd__a22o_1 _2626_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[15] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[15] ),
+ .B2(_1301_),
+ .X(_0754_));
+ sky130_fd_sc_hd__a22o_1 _2627_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[14] ),
+ .A2(_1298_),
+ .B1(FE_OFN119_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1301_),
+ .X(_0753_));
+ sky130_fd_sc_hd__a22o_1 _2628_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[13] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[13] ),
+ .B2(_1301_),
+ .X(_0752_));
+ sky130_fd_sc_hd__a22o_1 _2629_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[12] ),
+ .A2(_1298_),
+ .B1(FE_OFN115_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1301_),
+ .X(_0751_));
+ sky130_fd_sc_hd__a22o_1 _2632_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[11] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[11] ),
+ .B2(_1301_),
+ .X(_0750_));
+ sky130_fd_sc_hd__a22o_1 _2633_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[10] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[10] ),
+ .B2(_1301_),
+ .X(_0749_));
+ sky130_fd_sc_hd__a22o_1 _2634_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[9] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[9] ),
+ .B2(_1301_),
+ .X(_0748_));
+ sky130_fd_sc_hd__a22o_1 _2635_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[8] ),
+ .A2(_1298_),
+ .B1(FE_OFN165_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1301_),
+ .X(_0747_));
+ sky130_fd_sc_hd__a22o_1 _2636_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[7] ),
+ .A2(_1298_),
+ .B1(FE_OFN163_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1301_),
+ .X(_0746_));
+ sky130_fd_sc_hd__a22o_1 _2639_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[6] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[6] ),
+ .B2(_1301_),
+ .X(_0745_));
+ sky130_fd_sc_hd__a22o_1 _2640_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[5] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[5] ),
+ .B2(_1301_),
+ .X(_0744_));
+ sky130_fd_sc_hd__a22o_1 _2641_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[4] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[4] ),
+ .B2(_1301_),
+ .X(_0743_));
+ sky130_fd_sc_hd__a22o_1 _2642_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[3] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[3] ),
+ .B2(_1301_),
+ .X(_0742_));
+ sky130_fd_sc_hd__a22o_1 _2643_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[2] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[2] ),
+ .B2(_1301_),
+ .X(_0741_));
+ sky130_fd_sc_hd__a22o_1 _2644_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[1] ),
+ .A2(_1298_),
+ .B1(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1301_),
+ .X(_0740_));
+ sky130_fd_sc_hd__a22o_1 _2645_ (.A1(\Inst_Frame_Data_Reg_11.FrameData_O[0] ),
+ .A2(_1298_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[0] ),
+ .B2(_1301_),
+ .X(_0739_));
+ sky130_fd_sc_hd__a211o_1 _2646_ (.A1(_1098_),
+ .A2(_0011_),
+ .B1(\Config_inst.ConfigFSM_inst.FrameShiftState[2] ),
+ .C1(_1101_),
+ .X(_1314_));
+ sky130_fd_sc_hd__or2_2 _2647_ (.A(_1189_),
+ .B(_1314_),
+ .X(_1315_));
+ sky130_fd_sc_hd__inv_2 _2650_ (.A(_1315_),
+ .Y(_1318_));
+ sky130_fd_sc_hd__a22o_1 _2653_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[31] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[31] ),
+ .B2(_1318_),
+ .X(_0738_));
+ sky130_fd_sc_hd__a22o_1 _2654_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[30] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[30] ),
+ .B2(_1318_),
+ .X(_0737_));
+ sky130_fd_sc_hd__a22o_1 _2655_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[29] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[29] ),
+ .B2(_1318_),
+ .X(_0736_));
+ sky130_fd_sc_hd__a22o_1 _2656_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[28] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[28] ),
+ .B2(_1318_),
+ .X(_0735_));
+ sky130_fd_sc_hd__a22o_1 _2657_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[27] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[27] ),
+ .B2(_1318_),
+ .X(_0734_));
+ sky130_fd_sc_hd__a22o_1 _2660_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[26] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[26] ),
+ .B2(_1318_),
+ .X(_0733_));
+ sky130_fd_sc_hd__a22o_1 _2661_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[25] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[25] ),
+ .B2(_1318_),
+ .X(_0732_));
+ sky130_fd_sc_hd__a22o_1 _2662_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[24] ),
+ .A2(_1315_),
+ .B1(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1318_),
+ .X(_0731_));
+ sky130_fd_sc_hd__a22o_1 _2663_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[23] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[23] ),
+ .B2(_1318_),
+ .X(_0730_));
+ sky130_fd_sc_hd__a22o_1 _2664_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[22] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[22] ),
+ .B2(_1318_),
+ .X(_0729_));
+ sky130_fd_sc_hd__a22o_1 _2667_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[21] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[21] ),
+ .B2(_1318_),
+ .X(_0728_));
+ sky130_fd_sc_hd__a22o_1 _2668_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[20] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .B2(_1318_),
+ .X(_0727_));
+ sky130_fd_sc_hd__a22o_1 _2669_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[19] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[19] ),
+ .B2(_1318_),
+ .X(_0726_));
+ sky130_fd_sc_hd__a22o_1 _2670_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[18] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[18] ),
+ .B2(_1318_),
+ .X(_0725_));
+ sky130_fd_sc_hd__a22o_1 _2671_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[17] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[17] ),
+ .B2(_1318_),
+ .X(_0724_));
+ sky130_fd_sc_hd__a22o_1 _2674_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[16] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[16] ),
+ .B2(_1318_),
+ .X(_0723_));
+ sky130_fd_sc_hd__a22o_1 _2675_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[15] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[15] ),
+ .B2(_1318_),
+ .X(_0722_));
+ sky130_fd_sc_hd__a22o_1 _2676_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[14] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[14] ),
+ .B2(_1318_),
+ .X(_0721_));
+ sky130_fd_sc_hd__a22o_1 _2677_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[13] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[13] ),
+ .B2(_1318_),
+ .X(_0720_));
+ sky130_fd_sc_hd__a22o_1 _2678_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[12] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[12] ),
+ .B2(_1318_),
+ .X(_0719_));
+ sky130_fd_sc_hd__a22o_1 _2681_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[11] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[11] ),
+ .B2(_1318_),
+ .X(_0718_));
+ sky130_fd_sc_hd__a22o_1 _2682_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[10] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[10] ),
+ .B2(_1318_),
+ .X(_0717_));
+ sky130_fd_sc_hd__a22o_1 _2683_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[9] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[9] ),
+ .B2(_1318_),
+ .X(_0716_));
+ sky130_fd_sc_hd__a22o_1 _2684_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[8] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[8] ),
+ .B2(_1318_),
+ .X(_0715_));
+ sky130_fd_sc_hd__a22o_1 _2685_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[7] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[7] ),
+ .B2(_1318_),
+ .X(_0714_));
+ sky130_fd_sc_hd__a22o_1 _2688_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[6] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[6] ),
+ .B2(_1318_),
+ .X(_0713_));
+ sky130_fd_sc_hd__a22o_1 _2689_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[5] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[5] ),
+ .B2(_1318_),
+ .X(_0712_));
+ sky130_fd_sc_hd__a22o_1 _2690_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[4] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[4] ),
+ .B2(_1318_),
+ .X(_0711_));
+ sky130_fd_sc_hd__a22o_1 _2691_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[3] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[3] ),
+ .B2(_1318_),
+ .X(_0710_));
+ sky130_fd_sc_hd__a22o_1 _2692_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[2] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[2] ),
+ .B2(_1318_),
+ .X(_0709_));
+ sky130_fd_sc_hd__a22o_1 _2693_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[1] ),
+ .A2(_1315_),
+ .B1(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1318_),
+ .X(_0708_));
+ sky130_fd_sc_hd__a22o_1 _2694_ (.A1(\Inst_Frame_Data_Reg_10.FrameData_O[0] ),
+ .A2(_1315_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[0] ),
+ .B2(_1318_),
+ .X(_0707_));
+ sky130_fd_sc_hd__or2_2 _2696_ (.A(_1263_),
+ .B(_1331_),
+ .X(_1332_));
+ sky130_fd_sc_hd__inv_2 _2700_ (.A(FE_OFN2_1332),
+ .Y(_1336_));
+ sky130_fd_sc_hd__a22o_1 _2703_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[31] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1336_),
+ .X(_0706_));
+ sky130_fd_sc_hd__a22o_1 _2705_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[30] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1336_),
+ .X(_0705_));
+ sky130_fd_sc_hd__a22o_1 _2707_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[29] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1336_),
+ .X(_0704_));
+ sky130_fd_sc_hd__a22o_1 _2709_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[28] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1336_),
+ .X(_0703_));
+ sky130_fd_sc_hd__a22o_1 _2711_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[27] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN145_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1336_),
+ .X(_0702_));
+ sky130_fd_sc_hd__a22o_1 _2715_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[26] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26),
+ .B2(_1336_),
+ .X(_0701_));
+ sky130_fd_sc_hd__a22o_1 _2717_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[25] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25),
+ .B2(_1336_),
+ .X(_0700_));
+ sky130_fd_sc_hd__a22o_1 _2719_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[24] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN141_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1336_),
+ .X(_0699_));
+ sky130_fd_sc_hd__a22o_1 _2721_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[23] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23),
+ .B2(_1336_),
+ .X(_0698_));
+ sky130_fd_sc_hd__a22o_1 _2723_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[22] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22),
+ .B2(_1336_),
+ .X(_0697_));
+ sky130_fd_sc_hd__a22o_1 _2727_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[21] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21),
+ .B2(_1336_),
+ .X(_0696_));
+ sky130_fd_sc_hd__a22o_1 _2729_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[20] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20),
+ .B2(_1336_),
+ .X(_0695_));
+ sky130_fd_sc_hd__a22o_1 _2731_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[19] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN130_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1336_),
+ .X(_0694_));
+ sky130_fd_sc_hd__a22o_1 _2733_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[18] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN128_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1336_),
+ .X(_0693_));
+ sky130_fd_sc_hd__a22o_1 _2735_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[17] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN126_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1336_),
+ .X(_0692_));
+ sky130_fd_sc_hd__a22o_1 _2739_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[16] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN124_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1336_),
+ .X(_0691_));
+ sky130_fd_sc_hd__a22o_1 _2741_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[15] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15),
+ .B2(_1336_),
+ .X(_0690_));
+ sky130_fd_sc_hd__a22o_1 _2743_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[14] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN120_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1336_),
+ .X(_0689_));
+ sky130_fd_sc_hd__a22o_1 _2745_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[13] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13),
+ .B2(_1336_),
+ .X(_0688_));
+ sky130_fd_sc_hd__a22o_1 _2747_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[12] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1336_),
+ .X(_0687_));
+ sky130_fd_sc_hd__a22o_1 _2751_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[11] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11),
+ .B2(_1336_),
+ .X(_0686_));
+ sky130_fd_sc_hd__a22o_1 _2753_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[10] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10),
+ .B2(_1336_),
+ .X(_0685_));
+ sky130_fd_sc_hd__a22o_1 _2755_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[9] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9),
+ .B2(_1336_),
+ .X(_0684_));
+ sky130_fd_sc_hd__a22o_1 _2757_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[8] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN166_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1336_),
+ .X(_0683_));
+ sky130_fd_sc_hd__a22o_1 _2759_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[7] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN164_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1336_),
+ .X(_0682_));
+ sky130_fd_sc_hd__a22o_1 _2763_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[6] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6),
+ .B2(_1336_),
+ .X(_0681_));
+ sky130_fd_sc_hd__a22o_1 _2765_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[5] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5),
+ .B2(_1336_),
+ .X(_0680_));
+ sky130_fd_sc_hd__a22o_1 _2767_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[4] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4),
+ .B2(_1336_),
+ .X(_0679_));
+ sky130_fd_sc_hd__a22o_1 _2769_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[3] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3),
+ .B2(_1336_),
+ .X(_0678_));
+ sky130_fd_sc_hd__a22o_1 _2771_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[2] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2),
+ .B2(_1336_),
+ .X(_0677_));
+ sky130_fd_sc_hd__a22o_1 _2773_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[1] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN132_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1336_),
+ .X(_0676_));
+ sky130_fd_sc_hd__a22o_1 _2775_ (.A1(\Inst_Frame_Data_Reg_1.FrameData_O[0] ),
+ .A2(FE_OFN2_1332),
+ .B1(FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0),
+ .B2(_1336_),
+ .X(_0675_));
+ sky130_fd_sc_hd__or2_2 _2776_ (.A(_1280_),
+ .B(_1314_),
+ .X(_1380_));
+ sky130_fd_sc_hd__inv_2 _2779_ (.A(_1380_),
+ .Y(_1383_));
+ sky130_fd_sc_hd__a22o_1 _2782_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[31] ),
+ .A2(_1380_),
+ .B1(FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1383_),
+ .X(_0674_));
+ sky130_fd_sc_hd__a22o_1 _2783_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[30] ),
+ .A2(_1380_),
+ .B1(FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1383_),
+ .X(_0673_));
+ sky130_fd_sc_hd__a22o_1 _2784_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[29] ),
+ .A2(_1380_),
+ .B1(FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1383_),
+ .X(_0672_));
+ sky130_fd_sc_hd__a22o_1 _2785_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[28] ),
+ .A2(_1380_),
+ .B1(FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1383_),
+ .X(_0671_));
+ sky130_fd_sc_hd__a22o_1 _2786_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[27] ),
+ .A2(_1380_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[27] ),
+ .B2(_1383_),
+ .X(_0670_));
+ sky130_fd_sc_hd__a22o_1 _2789_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[26] ),
+ .A2(_1380_),
+ .B1(FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26),
+ .B2(_1383_),
+ .X(_0669_));
+ sky130_fd_sc_hd__a22o_1 _2790_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[25] ),
+ .A2(_1380_),
+ .B1(FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25),
+ .B2(_1383_),
+ .X(_0668_));
+ sky130_fd_sc_hd__a22o_1 _2791_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[24] ),
+ .A2(_1380_),
+ .B1(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1383_),
+ .X(_0667_));
+ sky130_fd_sc_hd__a22o_1 _2792_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[23] ),
+ .A2(_1380_),
+ .B1(FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23),
+ .B2(_1383_),
+ .X(_0666_));
+ sky130_fd_sc_hd__a22o_1 _2793_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[22] ),
+ .A2(_1380_),
+ .B1(FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22),
+ .B2(_1383_),
+ .X(_0665_));
+ sky130_fd_sc_hd__a22o_1 _2796_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[21] ),
+ .A2(_1380_),
+ .B1(FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21),
+ .B2(_1383_),
+ .X(_0664_));
+ sky130_fd_sc_hd__a22o_1 _2797_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[20] ),
+ .A2(_1380_),
+ .B1(FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20),
+ .B2(_1383_),
+ .X(_0663_));
+ sky130_fd_sc_hd__a22o_1 _2798_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[19] ),
+ .A2(_1380_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[19] ),
+ .B2(_1383_),
+ .X(_0662_));
+ sky130_fd_sc_hd__a22o_1 _2799_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[18] ),
+ .A2(_1380_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[18] ),
+ .B2(_1383_),
+ .X(_0661_));
+ sky130_fd_sc_hd__a22o_1 _2800_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[17] ),
+ .A2(_1380_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[17] ),
+ .B2(_1383_),
+ .X(_0660_));
+ sky130_fd_sc_hd__a22o_1 _2803_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[16] ),
+ .A2(_1380_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[16] ),
+ .B2(_1383_),
+ .X(_0659_));
+ sky130_fd_sc_hd__a22o_1 _2804_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[15] ),
+ .A2(_1380_),
+ .B1(FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15),
+ .B2(_1383_),
+ .X(_0658_));
+ sky130_fd_sc_hd__a22o_1 _2805_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[14] ),
+ .A2(_1380_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[14] ),
+ .B2(_1383_),
+ .X(_0657_));
+ sky130_fd_sc_hd__a22o_1 _2806_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[13] ),
+ .A2(_1380_),
+ .B1(FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13),
+ .B2(_1383_),
+ .X(_0656_));
+ sky130_fd_sc_hd__a22o_1 _2807_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[12] ),
+ .A2(_1380_),
+ .B1(FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1383_),
+ .X(_0655_));
+ sky130_fd_sc_hd__a22o_1 _2810_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[11] ),
+ .A2(_1380_),
+ .B1(FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11),
+ .B2(_1383_),
+ .X(_0654_));
+ sky130_fd_sc_hd__a22o_1 _2811_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[10] ),
+ .A2(_1380_),
+ .B1(FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10),
+ .B2(_1383_),
+ .X(_0653_));
+ sky130_fd_sc_hd__a22o_1 _2812_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[9] ),
+ .A2(_1380_),
+ .B1(FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9),
+ .B2(_1383_),
+ .X(_0652_));
+ sky130_fd_sc_hd__a22o_1 _2813_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[8] ),
+ .A2(_1380_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[8] ),
+ .B2(_1383_),
+ .X(_0651_));
+ sky130_fd_sc_hd__a22o_1 _2814_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[7] ),
+ .A2(_1380_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[7] ),
+ .B2(_1383_),
+ .X(_0650_));
+ sky130_fd_sc_hd__a22o_1 _2817_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[6] ),
+ .A2(_1380_),
+ .B1(FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6),
+ .B2(_1383_),
+ .X(_0649_));
+ sky130_fd_sc_hd__a22o_1 _2818_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[5] ),
+ .A2(_1380_),
+ .B1(FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5),
+ .B2(_1383_),
+ .X(_0648_));
+ sky130_fd_sc_hd__a22o_1 _2819_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[4] ),
+ .A2(_1380_),
+ .B1(FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4),
+ .B2(_1383_),
+ .X(_0647_));
+ sky130_fd_sc_hd__a22o_1 _2820_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[3] ),
+ .A2(_1380_),
+ .B1(FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3),
+ .B2(_1383_),
+ .X(_0646_));
+ sky130_fd_sc_hd__a22o_1 _2821_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[2] ),
+ .A2(_1380_),
+ .B1(FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2),
+ .B2(_1383_),
+ .X(_0645_));
+ sky130_fd_sc_hd__a22o_1 _2822_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[1] ),
+ .A2(_1380_),
+ .B1(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1383_),
+ .X(_0644_));
+ sky130_fd_sc_hd__a22o_1 _2823_ (.A1(\Inst_Frame_Data_Reg_8.FrameData_O[0] ),
+ .A2(_1380_),
+ .B1(FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0),
+ .B2(_1383_),
+ .X(_0643_));
+ sky130_fd_sc_hd__or2_2 _2824_ (.A(_1297_),
+ .B(_1314_),
+ .X(_1396_));
+ sky130_fd_sc_hd__inv_2 _2827_ (.A(_1396_),
+ .Y(_1399_));
+ sky130_fd_sc_hd__a22o_1 _2830_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[31] ),
+ .A2(_1396_),
+ .B1(FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1399_),
+ .X(_0642_));
+ sky130_fd_sc_hd__a22o_1 _2831_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[30] ),
+ .A2(_1396_),
+ .B1(FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1399_),
+ .X(_0641_));
+ sky130_fd_sc_hd__a22o_1 _2832_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[29] ),
+ .A2(_1396_),
+ .B1(FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1399_),
+ .X(_0640_));
+ sky130_fd_sc_hd__a22o_1 _2833_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[28] ),
+ .A2(_1396_),
+ .B1(FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1399_),
+ .X(_0639_));
+ sky130_fd_sc_hd__a22o_1 _2834_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[27] ),
+ .A2(_1396_),
+ .B1(FE_OFN145_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1399_),
+ .X(_0638_));
+ sky130_fd_sc_hd__a22o_1 _2837_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[26] ),
+ .A2(_1396_),
+ .B1(FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26),
+ .B2(_1399_),
+ .X(_0637_));
+ sky130_fd_sc_hd__a22o_1 _2838_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[25] ),
+ .A2(_1396_),
+ .B1(FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25),
+ .B2(_1399_),
+ .X(_0636_));
+ sky130_fd_sc_hd__a22o_1 _2839_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[24] ),
+ .A2(_1396_),
+ .B1(FE_OFN141_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1399_),
+ .X(_0635_));
+ sky130_fd_sc_hd__a22o_1 _2840_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[23] ),
+ .A2(_1396_),
+ .B1(FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23),
+ .B2(_1399_),
+ .X(_0634_));
+ sky130_fd_sc_hd__a22o_1 _2841_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[22] ),
+ .A2(_1396_),
+ .B1(FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22),
+ .B2(_1399_),
+ .X(_0633_));
+ sky130_fd_sc_hd__a22o_1 _2844_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[21] ),
+ .A2(_1396_),
+ .B1(FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21),
+ .B2(_1399_),
+ .X(_0632_));
+ sky130_fd_sc_hd__a22o_1 _2845_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[20] ),
+ .A2(_1396_),
+ .B1(FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20),
+ .B2(_1399_),
+ .X(_0631_));
+ sky130_fd_sc_hd__a22o_1 _2846_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[19] ),
+ .A2(_1396_),
+ .B1(FE_OFN130_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1399_),
+ .X(_0630_));
+ sky130_fd_sc_hd__a22o_1 _2847_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[18] ),
+ .A2(_1396_),
+ .B1(FE_OFN128_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1399_),
+ .X(_0629_));
+ sky130_fd_sc_hd__a22o_1 _2848_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[17] ),
+ .A2(_1396_),
+ .B1(FE_OFN126_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1399_),
+ .X(_0628_));
+ sky130_fd_sc_hd__a22o_1 _2851_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[16] ),
+ .A2(_1396_),
+ .B1(FE_OFN124_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1399_),
+ .X(_0627_));
+ sky130_fd_sc_hd__a22o_1 _2852_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[15] ),
+ .A2(_1396_),
+ .B1(FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15),
+ .B2(_1399_),
+ .X(_0626_));
+ sky130_fd_sc_hd__a22o_1 _2853_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[14] ),
+ .A2(_1396_),
+ .B1(FE_OFN120_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1399_),
+ .X(_0625_));
+ sky130_fd_sc_hd__a22o_1 _2854_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[13] ),
+ .A2(_1396_),
+ .B1(FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13),
+ .B2(_1399_),
+ .X(_0624_));
+ sky130_fd_sc_hd__a22o_1 _2855_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[12] ),
+ .A2(_1396_),
+ .B1(FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1399_),
+ .X(_0623_));
+ sky130_fd_sc_hd__a22o_1 _2858_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[11] ),
+ .A2(_1396_),
+ .B1(FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11),
+ .B2(_1399_),
+ .X(_0622_));
+ sky130_fd_sc_hd__a22o_1 _2859_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[10] ),
+ .A2(_1396_),
+ .B1(FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10),
+ .B2(_1399_),
+ .X(_0621_));
+ sky130_fd_sc_hd__a22o_1 _2860_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[9] ),
+ .A2(_1396_),
+ .B1(FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9),
+ .B2(_1399_),
+ .X(_0620_));
+ sky130_fd_sc_hd__a22o_1 _2861_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[8] ),
+ .A2(_1396_),
+ .B1(FE_OFN166_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1399_),
+ .X(_0619_));
+ sky130_fd_sc_hd__a22o_1 _2862_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[7] ),
+ .A2(_1396_),
+ .B1(FE_OFN164_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1399_),
+ .X(_0618_));
+ sky130_fd_sc_hd__a22o_1 _2865_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[6] ),
+ .A2(_1396_),
+ .B1(FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6),
+ .B2(_1399_),
+ .X(_0617_));
+ sky130_fd_sc_hd__a22o_1 _2866_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[5] ),
+ .A2(_1396_),
+ .B1(FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5),
+ .B2(_1399_),
+ .X(_0616_));
+ sky130_fd_sc_hd__a22o_1 _2867_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[4] ),
+ .A2(_1396_),
+ .B1(FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4),
+ .B2(_1399_),
+ .X(_0615_));
+ sky130_fd_sc_hd__a22o_1 _2868_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[3] ),
+ .A2(_1396_),
+ .B1(FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3),
+ .B2(_1399_),
+ .X(_0614_));
+ sky130_fd_sc_hd__a22o_1 _2869_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[2] ),
+ .A2(_1396_),
+ .B1(FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2),
+ .B2(_1399_),
+ .X(_0613_));
+ sky130_fd_sc_hd__a22o_1 _2870_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[1] ),
+ .A2(_1396_),
+ .B1(FE_OFN132_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1399_),
+ .X(_0612_));
+ sky130_fd_sc_hd__a22o_1 _2871_ (.A1(\Inst_Frame_Data_Reg_7.FrameData_O[0] ),
+ .A2(_1396_),
+ .B1(FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0),
+ .B2(_1399_),
+ .X(_0611_));
+ sky130_fd_sc_hd__a211o_2 _2872_ (.A1(_1099_),
+ .A2(_0011_),
+ .B1(\Config_inst.ConfigFSM_inst.FrameShiftState[3] ),
+ .C1(_1101_),
+ .X(_1412_));
+ sky130_fd_sc_hd__or2_2 _2873_ (.A(_1189_),
+ .B(_1412_),
+ .X(_1413_));
+ sky130_fd_sc_hd__inv_2 _2876_ (.A(_1413_),
+ .Y(_1416_));
+ sky130_fd_sc_hd__a22o_1 _2879_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[31] ),
+ .A2(_1413_),
+ .B1(FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1416_),
+ .X(_0610_));
+ sky130_fd_sc_hd__a22o_1 _2880_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[30] ),
+ .A2(_1413_),
+ .B1(FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1416_),
+ .X(_0609_));
+ sky130_fd_sc_hd__a22o_1 _2881_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[29] ),
+ .A2(_1413_),
+ .B1(FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1416_),
+ .X(_0608_));
+ sky130_fd_sc_hd__a22o_1 _2882_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[28] ),
+ .A2(_1413_),
+ .B1(FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1416_),
+ .X(_0607_));
+ sky130_fd_sc_hd__a22o_1 _2883_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[27] ),
+ .A2(_1413_),
+ .B1(FE_OFN145_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1416_),
+ .X(_0606_));
+ sky130_fd_sc_hd__a22o_1 _2886_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[26] ),
+ .A2(_1413_),
+ .B1(FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26),
+ .B2(_1416_),
+ .X(_0605_));
+ sky130_fd_sc_hd__a22o_1 _2887_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[25] ),
+ .A2(_1413_),
+ .B1(FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25),
+ .B2(_1416_),
+ .X(_0604_));
+ sky130_fd_sc_hd__a22o_1 _2888_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[24] ),
+ .A2(_1413_),
+ .B1(FE_OFN141_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1416_),
+ .X(_0603_));
+ sky130_fd_sc_hd__a22o_1 _2889_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[23] ),
+ .A2(_1413_),
+ .B1(FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23),
+ .B2(_1416_),
+ .X(_0602_));
+ sky130_fd_sc_hd__a22o_1 _2890_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[22] ),
+ .A2(_1413_),
+ .B1(FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22),
+ .B2(_1416_),
+ .X(_0601_));
+ sky130_fd_sc_hd__a22o_1 _2893_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[21] ),
+ .A2(_1413_),
+ .B1(FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21),
+ .B2(_1416_),
+ .X(_0600_));
+ sky130_fd_sc_hd__a22o_1 _2894_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[20] ),
+ .A2(_1413_),
+ .B1(FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20),
+ .B2(_1416_),
+ .X(_0599_));
+ sky130_fd_sc_hd__a22o_1 _2895_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[19] ),
+ .A2(_1413_),
+ .B1(FE_OFN130_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1416_),
+ .X(_0598_));
+ sky130_fd_sc_hd__a22o_1 _2896_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[18] ),
+ .A2(_1413_),
+ .B1(FE_OFN128_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1416_),
+ .X(_0597_));
+ sky130_fd_sc_hd__a22o_1 _2897_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[17] ),
+ .A2(_1413_),
+ .B1(FE_OFN126_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1416_),
+ .X(_0596_));
+ sky130_fd_sc_hd__a22o_1 _2900_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[16] ),
+ .A2(_1413_),
+ .B1(FE_OFN124_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1416_),
+ .X(_0595_));
+ sky130_fd_sc_hd__a22o_1 _2901_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[15] ),
+ .A2(_1413_),
+ .B1(FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15),
+ .B2(_1416_),
+ .X(_0594_));
+ sky130_fd_sc_hd__a22o_1 _2902_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[14] ),
+ .A2(_1413_),
+ .B1(FE_OFN120_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1416_),
+ .X(_0593_));
+ sky130_fd_sc_hd__a22o_1 _2903_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[13] ),
+ .A2(_1413_),
+ .B1(FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13),
+ .B2(_1416_),
+ .X(_0592_));
+ sky130_fd_sc_hd__a22o_1 _2904_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[12] ),
+ .A2(_1413_),
+ .B1(FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1416_),
+ .X(_0591_));
+ sky130_fd_sc_hd__a22o_1 _2907_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[11] ),
+ .A2(_1413_),
+ .B1(FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11),
+ .B2(_1416_),
+ .X(_0590_));
+ sky130_fd_sc_hd__a22o_1 _2908_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[10] ),
+ .A2(_1413_),
+ .B1(FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10),
+ .B2(_1416_),
+ .X(_0589_));
+ sky130_fd_sc_hd__a22o_1 _2909_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[9] ),
+ .A2(_1413_),
+ .B1(FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9),
+ .B2(_1416_),
+ .X(_0588_));
+ sky130_fd_sc_hd__a22o_1 _2910_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[8] ),
+ .A2(_1413_),
+ .B1(FE_OFN166_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1416_),
+ .X(_0587_));
+ sky130_fd_sc_hd__a22o_1 _2911_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[7] ),
+ .A2(_1413_),
+ .B1(FE_OFN164_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1416_),
+ .X(_0586_));
+ sky130_fd_sc_hd__a22o_1 _2914_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[6] ),
+ .A2(_1413_),
+ .B1(FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6),
+ .B2(_1416_),
+ .X(_0585_));
+ sky130_fd_sc_hd__a22o_1 _2915_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[5] ),
+ .A2(_1413_),
+ .B1(FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5),
+ .B2(_1416_),
+ .X(_0584_));
+ sky130_fd_sc_hd__a22o_1 _2916_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[4] ),
+ .A2(_1413_),
+ .B1(FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4),
+ .B2(_1416_),
+ .X(_0583_));
+ sky130_fd_sc_hd__a22o_1 _2917_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[3] ),
+ .A2(_1413_),
+ .B1(FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3),
+ .B2(_1416_),
+ .X(_0582_));
+ sky130_fd_sc_hd__a22o_1 _2918_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[2] ),
+ .A2(_1413_),
+ .B1(FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2),
+ .B2(_1416_),
+ .X(_0581_));
+ sky130_fd_sc_hd__a22o_1 _2919_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[1] ),
+ .A2(_1413_),
+ .B1(FE_OFN132_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1416_),
+ .X(_0580_));
+ sky130_fd_sc_hd__a22o_1 _2920_ (.A1(\Inst_Frame_Data_Reg_6.FrameData_O[0] ),
+ .A2(_1413_),
+ .B1(FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0),
+ .B2(_1416_),
+ .X(_0579_));
+ sky130_fd_sc_hd__or2_4 _2921_ (.A(_1263_),
+ .B(_1412_),
+ .X(_1429_));
+ sky130_fd_sc_hd__inv_2 _2924_ (.A(_1429_),
+ .Y(_1432_));
+ sky130_fd_sc_hd__a22o_1 _2927_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[31] ),
+ .A2(_1429_),
+ .B1(FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1432_),
+ .X(_0578_));
+ sky130_fd_sc_hd__a22o_1 _2928_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[30] ),
+ .A2(_1429_),
+ .B1(FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1432_),
+ .X(_0577_));
+ sky130_fd_sc_hd__a22o_1 _2929_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[29] ),
+ .A2(_1429_),
+ .B1(FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1432_),
+ .X(_0576_));
+ sky130_fd_sc_hd__a22o_1 _2930_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[28] ),
+ .A2(_1429_),
+ .B1(FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1432_),
+ .X(_0575_));
+ sky130_fd_sc_hd__a22o_1 _2931_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[27] ),
+ .A2(_1429_),
+ .B1(FE_OFN145_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1432_),
+ .X(_0574_));
+ sky130_fd_sc_hd__a22o_1 _2934_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[26] ),
+ .A2(_1429_),
+ .B1(FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26),
+ .B2(_1432_),
+ .X(_0573_));
+ sky130_fd_sc_hd__a22o_1 _2935_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[25] ),
+ .A2(_1429_),
+ .B1(FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25),
+ .B2(_1432_),
+ .X(_0572_));
+ sky130_fd_sc_hd__a22o_1 _2936_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[24] ),
+ .A2(_1429_),
+ .B1(FE_OFN141_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1432_),
+ .X(_0571_));
+ sky130_fd_sc_hd__a22o_1 _2937_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[23] ),
+ .A2(_1429_),
+ .B1(FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23),
+ .B2(_1432_),
+ .X(_0570_));
+ sky130_fd_sc_hd__a22o_1 _2938_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[22] ),
+ .A2(_1429_),
+ .B1(FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22),
+ .B2(_1432_),
+ .X(_0569_));
+ sky130_fd_sc_hd__a22o_1 _2941_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[21] ),
+ .A2(_1429_),
+ .B1(FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21),
+ .B2(_1432_),
+ .X(_0568_));
+ sky130_fd_sc_hd__a22o_1 _2942_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[20] ),
+ .A2(_1429_),
+ .B1(FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20),
+ .B2(_1432_),
+ .X(_0567_));
+ sky130_fd_sc_hd__a22o_1 _2943_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[19] ),
+ .A2(_1429_),
+ .B1(FE_OFN130_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1432_),
+ .X(_0566_));
+ sky130_fd_sc_hd__a22o_1 _2944_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[18] ),
+ .A2(_1429_),
+ .B1(FE_OFN128_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1432_),
+ .X(_0565_));
+ sky130_fd_sc_hd__a22o_1 _2945_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[17] ),
+ .A2(_1429_),
+ .B1(FE_OFN126_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1432_),
+ .X(_0564_));
+ sky130_fd_sc_hd__a22o_1 _2948_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[16] ),
+ .A2(_1429_),
+ .B1(FE_OFN124_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1432_),
+ .X(_0563_));
+ sky130_fd_sc_hd__a22o_1 _2949_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[15] ),
+ .A2(_1429_),
+ .B1(FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15),
+ .B2(_1432_),
+ .X(_0562_));
+ sky130_fd_sc_hd__a22o_1 _2950_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[14] ),
+ .A2(_1429_),
+ .B1(FE_OFN120_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1432_),
+ .X(_0561_));
+ sky130_fd_sc_hd__a22o_1 _2951_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[13] ),
+ .A2(_1429_),
+ .B1(FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13),
+ .B2(_1432_),
+ .X(_0560_));
+ sky130_fd_sc_hd__a22o_1 _2952_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[12] ),
+ .A2(_1429_),
+ .B1(FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1432_),
+ .X(_0559_));
+ sky130_fd_sc_hd__a22o_1 _2955_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[11] ),
+ .A2(_1429_),
+ .B1(FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11),
+ .B2(_1432_),
+ .X(_0558_));
+ sky130_fd_sc_hd__a22o_1 _2956_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[10] ),
+ .A2(_1429_),
+ .B1(FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10),
+ .B2(_1432_),
+ .X(_0557_));
+ sky130_fd_sc_hd__a22o_1 _2957_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[9] ),
+ .A2(_1429_),
+ .B1(FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9),
+ .B2(_1432_),
+ .X(_0556_));
+ sky130_fd_sc_hd__a22o_1 _2958_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[8] ),
+ .A2(_1429_),
+ .B1(FE_OFN166_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1432_),
+ .X(_0555_));
+ sky130_fd_sc_hd__a22o_1 _2959_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[7] ),
+ .A2(_1429_),
+ .B1(FE_OFN164_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1432_),
+ .X(_0554_));
+ sky130_fd_sc_hd__a22o_1 _2962_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[6] ),
+ .A2(_1429_),
+ .B1(FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6),
+ .B2(_1432_),
+ .X(_0553_));
+ sky130_fd_sc_hd__a22o_1 _2963_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[5] ),
+ .A2(_1429_),
+ .B1(FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5),
+ .B2(_1432_),
+ .X(_0552_));
+ sky130_fd_sc_hd__a22o_1 _2964_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[4] ),
+ .A2(_1429_),
+ .B1(FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4),
+ .B2(_1432_),
+ .X(_0551_));
+ sky130_fd_sc_hd__a22o_1 _2965_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[3] ),
+ .A2(_1429_),
+ .B1(FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3),
+ .B2(_1432_),
+ .X(_0550_));
+ sky130_fd_sc_hd__a22o_1 _2966_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[2] ),
+ .A2(_1429_),
+ .B1(FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2),
+ .B2(_1432_),
+ .X(_0549_));
+ sky130_fd_sc_hd__a22o_1 _2967_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[1] ),
+ .A2(_1429_),
+ .B1(FE_OFN132_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1432_),
+ .X(_0548_));
+ sky130_fd_sc_hd__a22o_1 _2968_ (.A1(\Inst_Frame_Data_Reg_5.FrameData_O[0] ),
+ .A2(_1429_),
+ .B1(FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0),
+ .B2(_1432_),
+ .X(_0547_));
+ sky130_fd_sc_hd__or2_4 _2969_ (.A(_1280_),
+ .B(_1412_),
+ .X(_1445_));
+ sky130_fd_sc_hd__inv_2 _2973_ (.A(_1445_),
+ .Y(_1449_));
+ sky130_fd_sc_hd__a22o_1 _2976_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[31] ),
+ .A2(_1445_),
+ .B1(FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1449_),
+ .X(_0546_));
+ sky130_fd_sc_hd__a22o_1 _2978_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[30] ),
+ .A2(_1445_),
+ .B1(FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1449_),
+ .X(_0545_));
+ sky130_fd_sc_hd__a22o_1 _2980_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[29] ),
+ .A2(_1445_),
+ .B1(FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1449_),
+ .X(_0544_));
+ sky130_fd_sc_hd__a22o_1 _2982_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[28] ),
+ .A2(_1445_),
+ .B1(FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1449_),
+ .X(_0543_));
+ sky130_fd_sc_hd__a22o_1 _2984_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[27] ),
+ .A2(_1445_),
+ .B1(FE_OFN145_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1449_),
+ .X(_0542_));
+ sky130_fd_sc_hd__a22o_1 _2988_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[26] ),
+ .A2(_1445_),
+ .B1(FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26),
+ .B2(_1449_),
+ .X(_0541_));
+ sky130_fd_sc_hd__a22o_1 _2990_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[25] ),
+ .A2(_1445_),
+ .B1(FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25),
+ .B2(_1449_),
+ .X(_0540_));
+ sky130_fd_sc_hd__a22o_1 _2992_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[24] ),
+ .A2(_1445_),
+ .B1(FE_OFN141_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1449_),
+ .X(_0539_));
+ sky130_fd_sc_hd__a22o_1 _2994_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[23] ),
+ .A2(_1445_),
+ .B1(FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23),
+ .B2(_1449_),
+ .X(_0538_));
+ sky130_fd_sc_hd__a22o_1 _2996_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[22] ),
+ .A2(_1445_),
+ .B1(FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22),
+ .B2(_1449_),
+ .X(_0537_));
+ sky130_fd_sc_hd__a22o_1 _3000_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[21] ),
+ .A2(_1445_),
+ .B1(FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21),
+ .B2(_1449_),
+ .X(_0536_));
+ sky130_fd_sc_hd__a22o_1 _3002_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[20] ),
+ .A2(_1445_),
+ .B1(FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20),
+ .B2(_1449_),
+ .X(_0535_));
+ sky130_fd_sc_hd__a22o_1 _3004_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[19] ),
+ .A2(_1445_),
+ .B1(FE_OFN130_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1449_),
+ .X(_0534_));
+ sky130_fd_sc_hd__a22o_1 _3006_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[18] ),
+ .A2(_1445_),
+ .B1(FE_OFN128_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1449_),
+ .X(_0533_));
+ sky130_fd_sc_hd__a22o_1 _3008_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[17] ),
+ .A2(_1445_),
+ .B1(FE_OFN126_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1449_),
+ .X(_0532_));
+ sky130_fd_sc_hd__a22o_1 _3012_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[16] ),
+ .A2(_1445_),
+ .B1(FE_OFN124_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1449_),
+ .X(_0531_));
+ sky130_fd_sc_hd__a22o_1 _3014_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[15] ),
+ .A2(_1445_),
+ .B1(FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15),
+ .B2(_1449_),
+ .X(_0530_));
+ sky130_fd_sc_hd__a22o_1 _3016_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[14] ),
+ .A2(_1445_),
+ .B1(FE_OFN120_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1449_),
+ .X(_0529_));
+ sky130_fd_sc_hd__a22o_1 _3018_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[13] ),
+ .A2(_1445_),
+ .B1(FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13),
+ .B2(_1449_),
+ .X(_0528_));
+ sky130_fd_sc_hd__a22o_1 _3020_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[12] ),
+ .A2(_1445_),
+ .B1(FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1449_),
+ .X(_0527_));
+ sky130_fd_sc_hd__a22o_1 _3024_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[11] ),
+ .A2(_1445_),
+ .B1(FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11),
+ .B2(_1449_),
+ .X(_0526_));
+ sky130_fd_sc_hd__a22o_1 _3026_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[10] ),
+ .A2(_1445_),
+ .B1(FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10),
+ .B2(_1449_),
+ .X(_0525_));
+ sky130_fd_sc_hd__a22o_1 _3028_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[9] ),
+ .A2(_1445_),
+ .B1(FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9),
+ .B2(_1449_),
+ .X(_0524_));
+ sky130_fd_sc_hd__a22o_1 _3030_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[8] ),
+ .A2(_1445_),
+ .B1(FE_OFN166_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1449_),
+ .X(_0523_));
+ sky130_fd_sc_hd__a22o_1 _3032_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[7] ),
+ .A2(_1445_),
+ .B1(FE_OFN164_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1449_),
+ .X(_0522_));
+ sky130_fd_sc_hd__a22o_1 _3036_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[6] ),
+ .A2(_1445_),
+ .B1(FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6),
+ .B2(_1449_),
+ .X(_0521_));
+ sky130_fd_sc_hd__a22o_1 _3038_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[5] ),
+ .A2(_1445_),
+ .B1(FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5),
+ .B2(_1449_),
+ .X(_0520_));
+ sky130_fd_sc_hd__a22o_1 _3040_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[4] ),
+ .A2(_1445_),
+ .B1(FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4),
+ .B2(_1449_),
+ .X(_0519_));
+ sky130_fd_sc_hd__a22o_1 _3042_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[3] ),
+ .A2(_1445_),
+ .B1(FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3),
+ .B2(_1449_),
+ .X(_0518_));
+ sky130_fd_sc_hd__a22o_1 _3044_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[2] ),
+ .A2(_1445_),
+ .B1(FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2),
+ .B2(_1449_),
+ .X(_0517_));
+ sky130_fd_sc_hd__a22o_1 _3046_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[1] ),
+ .A2(_1445_),
+ .B1(FE_OFN132_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1449_),
+ .X(_0516_));
+ sky130_fd_sc_hd__a22o_1 _3048_ (.A1(\Inst_Frame_Data_Reg_4.FrameData_O[0] ),
+ .A2(_1445_),
+ .B1(FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0),
+ .B2(_1449_),
+ .X(_0515_));
+ sky130_fd_sc_hd__or2_2 _3049_ (.A(_1297_),
+ .B(_1412_),
+ .X(_1493_));
+ sky130_fd_sc_hd__inv_2 _3052_ (.A(FE_OFN3_1493),
+ .Y(_1496_));
+ sky130_fd_sc_hd__a22o_1 _3055_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[31] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1496_),
+ .X(_0514_));
+ sky130_fd_sc_hd__a22o_1 _3056_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[30] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1496_),
+ .X(_0513_));
+ sky130_fd_sc_hd__a22o_1 _3057_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[29] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1496_),
+ .X(_0512_));
+ sky130_fd_sc_hd__a22o_1 _3058_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[28] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1496_),
+ .X(_0511_));
+ sky130_fd_sc_hd__a22o_1 _3059_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[27] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN145_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1496_),
+ .X(_0510_));
+ sky130_fd_sc_hd__a22o_1 _3062_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[26] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26),
+ .B2(_1496_),
+ .X(_0509_));
+ sky130_fd_sc_hd__a22o_1 _3063_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[25] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25),
+ .B2(_1496_),
+ .X(_0508_));
+ sky130_fd_sc_hd__a22o_1 _3064_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[24] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN141_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1496_),
+ .X(_0507_));
+ sky130_fd_sc_hd__a22o_1 _3065_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[23] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23),
+ .B2(_1496_),
+ .X(_0506_));
+ sky130_fd_sc_hd__a22o_1 _3066_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[22] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22),
+ .B2(_1496_),
+ .X(_0505_));
+ sky130_fd_sc_hd__a22o_1 _3069_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[21] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21),
+ .B2(_1496_),
+ .X(_0504_));
+ sky130_fd_sc_hd__a22o_1 _3070_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[20] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20),
+ .B2(_1496_),
+ .X(_0503_));
+ sky130_fd_sc_hd__a22o_1 _3071_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[19] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN130_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1496_),
+ .X(_0502_));
+ sky130_fd_sc_hd__a22o_1 _3072_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[18] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN128_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1496_),
+ .X(_0501_));
+ sky130_fd_sc_hd__a22o_1 _3073_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[17] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN126_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1496_),
+ .X(_0500_));
+ sky130_fd_sc_hd__a22o_1 _3076_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[16] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN124_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1496_),
+ .X(_0499_));
+ sky130_fd_sc_hd__a22o_1 _3077_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[15] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15),
+ .B2(_1496_),
+ .X(_0498_));
+ sky130_fd_sc_hd__a22o_1 _3078_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[14] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN120_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1496_),
+ .X(_0497_));
+ sky130_fd_sc_hd__a22o_1 _3079_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[13] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13),
+ .B2(_1496_),
+ .X(_0496_));
+ sky130_fd_sc_hd__a22o_1 _3080_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[12] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1496_),
+ .X(_0495_));
+ sky130_fd_sc_hd__a22o_1 _3083_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[11] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11),
+ .B2(_1496_),
+ .X(_0494_));
+ sky130_fd_sc_hd__a22o_1 _3084_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[10] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10),
+ .B2(_1496_),
+ .X(_0493_));
+ sky130_fd_sc_hd__a22o_1 _3085_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[9] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9),
+ .B2(_1496_),
+ .X(_0492_));
+ sky130_fd_sc_hd__a22o_1 _3086_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[8] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN166_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1496_),
+ .X(_0491_));
+ sky130_fd_sc_hd__a22o_1 _3087_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[7] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN164_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1496_),
+ .X(_0490_));
+ sky130_fd_sc_hd__a22o_1 _3090_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[6] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6),
+ .B2(_1496_),
+ .X(_0489_));
+ sky130_fd_sc_hd__a22o_1 _3091_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[5] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5),
+ .B2(_1496_),
+ .X(_0488_));
+ sky130_fd_sc_hd__a22o_1 _3092_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[4] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4),
+ .B2(_1496_),
+ .X(_0487_));
+ sky130_fd_sc_hd__a22o_1 _3093_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[3] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3),
+ .B2(_1496_),
+ .X(_0486_));
+ sky130_fd_sc_hd__a22o_1 _3094_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[2] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2),
+ .B2(_1496_),
+ .X(_0485_));
+ sky130_fd_sc_hd__a22o_1 _3095_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[1] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN132_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1496_),
+ .X(_0484_));
+ sky130_fd_sc_hd__a22o_1 _3096_ (.A1(\Inst_Frame_Data_Reg_3.FrameData_O[0] ),
+ .A2(FE_OFN3_1493),
+ .B1(FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0),
+ .B2(_1496_),
+ .X(_0483_));
+ sky130_fd_sc_hd__or2_2 _3097_ (.A(_1189_),
+ .B(_1331_),
+ .X(_1509_));
+ sky130_fd_sc_hd__inv_2 _3100_ (.A(FE_OFN4_1509),
+ .Y(_1512_));
+ sky130_fd_sc_hd__a22o_1 _3103_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[31] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1512_),
+ .X(_0482_));
+ sky130_fd_sc_hd__a22o_1 _3104_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[30] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1512_),
+ .X(_0481_));
+ sky130_fd_sc_hd__a22o_1 _3105_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[29] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1512_),
+ .X(_0480_));
+ sky130_fd_sc_hd__a22o_1 _3106_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[28] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1512_),
+ .X(_0479_));
+ sky130_fd_sc_hd__a22o_1 _3107_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[27] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN145_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1512_),
+ .X(_0478_));
+ sky130_fd_sc_hd__a22o_1 _3110_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[26] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26),
+ .B2(_1512_),
+ .X(_0477_));
+ sky130_fd_sc_hd__a22o_1 _3111_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[25] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25),
+ .B2(_1512_),
+ .X(_0476_));
+ sky130_fd_sc_hd__a22o_1 _3112_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[24] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN141_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1512_),
+ .X(_0475_));
+ sky130_fd_sc_hd__a22o_1 _3113_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[23] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23),
+ .B2(_1512_),
+ .X(_0474_));
+ sky130_fd_sc_hd__a22o_1 _3114_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[22] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22),
+ .B2(_1512_),
+ .X(_0473_));
+ sky130_fd_sc_hd__a22o_1 _3117_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[21] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21),
+ .B2(_1512_),
+ .X(_0472_));
+ sky130_fd_sc_hd__a22o_1 _3118_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[20] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20),
+ .B2(_1512_),
+ .X(_0471_));
+ sky130_fd_sc_hd__a22o_1 _3119_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[19] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN130_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1512_),
+ .X(_0470_));
+ sky130_fd_sc_hd__a22o_1 _3120_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[18] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN128_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1512_),
+ .X(_0469_));
+ sky130_fd_sc_hd__a22o_1 _3121_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[17] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN126_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1512_),
+ .X(_0468_));
+ sky130_fd_sc_hd__a22o_1 _3124_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[16] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN124_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1512_),
+ .X(_0467_));
+ sky130_fd_sc_hd__a22o_1 _3125_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[15] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15),
+ .B2(_1512_),
+ .X(_0466_));
+ sky130_fd_sc_hd__a22o_1 _3126_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[14] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN120_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1512_),
+ .X(_0465_));
+ sky130_fd_sc_hd__a22o_1 _3127_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[13] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13),
+ .B2(_1512_),
+ .X(_0464_));
+ sky130_fd_sc_hd__a22o_1 _3128_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[12] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1512_),
+ .X(_0463_));
+ sky130_fd_sc_hd__a22o_1 _3131_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[11] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11),
+ .B2(_1512_),
+ .X(_0462_));
+ sky130_fd_sc_hd__a22o_1 _3132_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[10] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10),
+ .B2(_1512_),
+ .X(_0461_));
+ sky130_fd_sc_hd__a22o_1 _3133_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[9] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9),
+ .B2(_1512_),
+ .X(_0460_));
+ sky130_fd_sc_hd__a22o_1 _3134_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[8] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN166_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1512_),
+ .X(_0459_));
+ sky130_fd_sc_hd__a22o_1 _3135_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[7] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN164_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1512_),
+ .X(_0458_));
+ sky130_fd_sc_hd__a22o_1 _3138_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[6] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6),
+ .B2(_1512_),
+ .X(_0457_));
+ sky130_fd_sc_hd__a22o_1 _3139_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[5] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5),
+ .B2(_1512_),
+ .X(_0456_));
+ sky130_fd_sc_hd__a22o_1 _3140_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[4] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4),
+ .B2(_1512_),
+ .X(_0455_));
+ sky130_fd_sc_hd__a22o_1 _3141_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[3] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3),
+ .B2(_1512_),
+ .X(_0454_));
+ sky130_fd_sc_hd__a22o_1 _3142_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[2] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2),
+ .B2(_1512_),
+ .X(_0453_));
+ sky130_fd_sc_hd__a22o_1 _3143_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[1] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN132_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1512_),
+ .X(_0452_));
+ sky130_fd_sc_hd__a22o_1 _3144_ (.A1(\Inst_Frame_Data_Reg_2.FrameData_O[0] ),
+ .A2(FE_OFN4_1509),
+ .B1(FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0),
+ .B2(_1512_),
+ .X(_0451_));
+ sky130_fd_sc_hd__or4_2 _3145_ (.A(\Config_inst.ConfigFSM_inst.FrameShiftState[1] ),
+ .B(\Config_inst.ConfigFSM_inst.FrameShiftState[0] ),
+ .C(_1107_),
+ .D(_1331_),
+ .X(_1525_));
+ sky130_fd_sc_hd__inv_2 _3148_ (.A(FE_OFN5_1525),
+ .Y(_1528_));
+ sky130_fd_sc_hd__a22o_1 _3151_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[31] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN153_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1528_),
+ .X(_0450_));
+ sky130_fd_sc_hd__a22o_1 _3152_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[30] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN151_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1528_),
+ .X(_0449_));
+ sky130_fd_sc_hd__a22o_1 _3153_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[29] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN148_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1528_),
+ .X(_0448_));
+ sky130_fd_sc_hd__a22o_1 _3154_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[28] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN146_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1528_),
+ .X(_0447_));
+ sky130_fd_sc_hd__a22o_1 _3155_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[27] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN144_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1528_),
+ .X(_0446_));
+ sky130_fd_sc_hd__a22o_1 _3158_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[26] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[26] ),
+ .B2(_1528_),
+ .X(_0445_));
+ sky130_fd_sc_hd__a22o_1 _3159_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[25] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[25] ),
+ .B2(_1528_),
+ .X(_0444_));
+ sky130_fd_sc_hd__a22o_1 _3160_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[24] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1528_),
+ .X(_0443_));
+ sky130_fd_sc_hd__a22o_1 _3161_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[23] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[23] ),
+ .B2(_1528_),
+ .X(_0442_));
+ sky130_fd_sc_hd__a22o_1 _3162_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[22] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[22] ),
+ .B2(_1528_),
+ .X(_0441_));
+ sky130_fd_sc_hd__a22o_1 _3165_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[21] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[21] ),
+ .B2(_1528_),
+ .X(_0440_));
+ sky130_fd_sc_hd__a22o_1 _3166_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[20] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .B2(_1528_),
+ .X(_0439_));
+ sky130_fd_sc_hd__a22o_1 _3167_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[19] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN129_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1528_),
+ .X(_0438_));
+ sky130_fd_sc_hd__a22o_1 _3168_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[18] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN127_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1528_),
+ .X(_0437_));
+ sky130_fd_sc_hd__a22o_1 _3169_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[17] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN125_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1528_),
+ .X(_0436_));
+ sky130_fd_sc_hd__a22o_1 _3172_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[16] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN123_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1528_),
+ .X(_0435_));
+ sky130_fd_sc_hd__a22o_1 _3173_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[15] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[15] ),
+ .B2(_1528_),
+ .X(_0434_));
+ sky130_fd_sc_hd__a22o_1 _3174_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[14] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN119_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1528_),
+ .X(_0433_));
+ sky130_fd_sc_hd__a22o_1 _3175_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[13] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[13] ),
+ .B2(_1528_),
+ .X(_0432_));
+ sky130_fd_sc_hd__a22o_1 _3176_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[12] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN115_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1528_),
+ .X(_0431_));
+ sky130_fd_sc_hd__a22o_1 _3179_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[11] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[11] ),
+ .B2(_1528_),
+ .X(_0430_));
+ sky130_fd_sc_hd__a22o_1 _3180_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[10] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[10] ),
+ .B2(_1528_),
+ .X(_0429_));
+ sky130_fd_sc_hd__a22o_1 _3181_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[9] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[9] ),
+ .B2(_1528_),
+ .X(_0428_));
+ sky130_fd_sc_hd__a22o_1 _3182_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[8] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN165_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1528_),
+ .X(_0427_));
+ sky130_fd_sc_hd__a22o_1 _3183_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[7] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN163_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1528_),
+ .X(_0426_));
+ sky130_fd_sc_hd__a22o_1 _3186_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[6] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[6] ),
+ .B2(_1528_),
+ .X(_0425_));
+ sky130_fd_sc_hd__a22o_1 _3187_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[5] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[5] ),
+ .B2(_1528_),
+ .X(_0424_));
+ sky130_fd_sc_hd__a22o_1 _3188_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[4] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[4] ),
+ .B2(_1528_),
+ .X(_0423_));
+ sky130_fd_sc_hd__a22o_1 _3189_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[3] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[3] ),
+ .B2(_1528_),
+ .X(_0422_));
+ sky130_fd_sc_hd__a22o_1 _3190_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[2] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[2] ),
+ .B2(_1528_),
+ .X(_0421_));
+ sky130_fd_sc_hd__a22o_1 _3191_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[1] ),
+ .A2(FE_OFN5_1525),
+ .B1(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1528_),
+ .X(_0420_));
+ sky130_fd_sc_hd__a22o_1 _3192_ (.A1(\Inst_Frame_Data_Reg_15.FrameData_O[0] ),
+ .A2(FE_OFN5_1525),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[0] ),
+ .B2(_1528_),
+ .X(_0419_));
+ sky130_fd_sc_hd__a22o_1 _3197_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[31] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN154_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1175_),
+ .X(_0418_));
+ sky130_fd_sc_hd__a22o_1 _3198_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[30] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN152_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1175_),
+ .X(_0417_));
+ sky130_fd_sc_hd__a22o_1 _3199_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[29] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN149_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1175_),
+ .X(_0416_));
+ sky130_fd_sc_hd__a22o_1 _3200_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[28] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN147_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1175_),
+ .X(_0415_));
+ sky130_fd_sc_hd__a22o_1 _3201_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[27] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN145_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1175_),
+ .X(_0414_));
+ sky130_fd_sc_hd__a22o_1 _3204_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[26] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN143_Config_inst_ConfigFSM_inst_WriteData_26),
+ .B2(_1175_),
+ .X(_0413_));
+ sky130_fd_sc_hd__a22o_1 _3205_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[25] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN142_Config_inst_ConfigFSM_inst_WriteData_25),
+ .B2(_1175_),
+ .X(_0412_));
+ sky130_fd_sc_hd__a22o_1 _3206_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[24] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN141_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1175_),
+ .X(_0411_));
+ sky130_fd_sc_hd__a22o_1 _3207_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[23] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN139_Config_inst_ConfigFSM_inst_WriteData_23),
+ .B2(_1175_),
+ .X(_0410_));
+ sky130_fd_sc_hd__a22o_1 _3208_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[22] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN138_Config_inst_ConfigFSM_inst_WriteData_22),
+ .B2(_1175_),
+ .X(_0409_));
+ sky130_fd_sc_hd__a22o_1 _3211_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[21] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN136_Config_inst_ConfigFSM_inst_WriteData_21),
+ .B2(_1175_),
+ .X(_0408_));
+ sky130_fd_sc_hd__a22o_1 _3212_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[20] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN134_Config_inst_ConfigFSM_inst_WriteData_20),
+ .B2(_1175_),
+ .X(_0407_));
+ sky130_fd_sc_hd__a22o_1 _3213_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[19] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN130_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1175_),
+ .X(_0406_));
+ sky130_fd_sc_hd__a22o_1 _3214_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[18] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN128_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1175_),
+ .X(_0405_));
+ sky130_fd_sc_hd__a22o_1 _3215_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[17] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN126_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1175_),
+ .X(_0404_));
+ sky130_fd_sc_hd__a22o_1 _3218_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[16] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN124_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1175_),
+ .X(_0403_));
+ sky130_fd_sc_hd__a22o_1 _3219_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[15] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN122_Config_inst_ConfigFSM_inst_WriteData_15),
+ .B2(_1175_),
+ .X(_0402_));
+ sky130_fd_sc_hd__a22o_1 _3220_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[14] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN120_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1175_),
+ .X(_0401_));
+ sky130_fd_sc_hd__a22o_1 _3221_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[13] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN118_Config_inst_ConfigFSM_inst_WriteData_13),
+ .B2(_1175_),
+ .X(_0400_));
+ sky130_fd_sc_hd__a22o_1 _3222_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[12] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN116_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1175_),
+ .X(_0399_));
+ sky130_fd_sc_hd__a22o_1 _3225_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[11] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN114_Config_inst_ConfigFSM_inst_WriteData_11),
+ .B2(_1175_),
+ .X(_0398_));
+ sky130_fd_sc_hd__a22o_1 _3226_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[10] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN112_Config_inst_ConfigFSM_inst_WriteData_10),
+ .B2(_1175_),
+ .X(_0397_));
+ sky130_fd_sc_hd__a22o_1 _3227_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[9] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN168_Config_inst_ConfigFSM_inst_WriteData_9),
+ .B2(_1175_),
+ .X(_0396_));
+ sky130_fd_sc_hd__a22o_1 _3228_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[8] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN166_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1175_),
+ .X(_0395_));
+ sky130_fd_sc_hd__a22o_1 _3229_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[7] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN164_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1175_),
+ .X(_0394_));
+ sky130_fd_sc_hd__a22o_1 _3232_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[6] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN162_Config_inst_ConfigFSM_inst_WriteData_6),
+ .B2(_1175_),
+ .X(_0393_));
+ sky130_fd_sc_hd__a22o_1 _3233_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[5] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN160_Config_inst_ConfigFSM_inst_WriteData_5),
+ .B2(_1175_),
+ .X(_0392_));
+ sky130_fd_sc_hd__a22o_1 _3234_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[4] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN158_Config_inst_ConfigFSM_inst_WriteData_4),
+ .B2(_1175_),
+ .X(_0391_));
+ sky130_fd_sc_hd__a22o_1 _3235_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[3] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN156_Config_inst_ConfigFSM_inst_WriteData_3),
+ .B2(_1175_),
+ .X(_0390_));
+ sky130_fd_sc_hd__a22o_1 _3236_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[2] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN150_Config_inst_ConfigFSM_inst_WriteData_2),
+ .B2(_1175_),
+ .X(_0389_));
+ sky130_fd_sc_hd__a22o_1 _3237_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[1] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN132_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1175_),
+ .X(_0388_));
+ sky130_fd_sc_hd__a22o_1 _3238_ (.A1(\Inst_Frame_Data_Reg_0.FrameData_O[0] ),
+ .A2(FE_OFN0_1174),
+ .B1(FE_OFN110_Config_inst_ConfigFSM_inst_WriteData_0),
+ .B2(_1175_),
+ .X(_0387_));
+ sky130_fd_sc_hd__a22o_1 _3241_ (.A1(\Config_inst.INST_config_UART.HexData[7] ),
+ .A2(_1171_),
+ .B1(\Config_inst.INST_config_UART.HighReg[3] ),
+ .B2(_1172_),
+ .X(_0386_));
+ sky130_fd_sc_hd__a22o_1 _3242_ (.A1(\Config_inst.INST_config_UART.HexData[6] ),
+ .A2(_1171_),
+ .B1(\Config_inst.INST_config_UART.HighReg[2] ),
+ .B2(_1172_),
+ .X(_0385_));
+ sky130_fd_sc_hd__a22o_1 _3243_ (.A1(\Config_inst.INST_config_UART.HexData[5] ),
+ .A2(_1171_),
+ .B1(\Config_inst.INST_config_UART.HighReg[1] ),
+ .B2(_1172_),
+ .X(_0384_));
+ sky130_fd_sc_hd__a22o_1 _3244_ (.A1(\Config_inst.INST_config_UART.HexData[4] ),
+ .A2(_1171_),
+ .B1(\Config_inst.INST_config_UART.HighReg[0] ),
+ .B2(_1172_),
+ .X(_0383_));
+ sky130_fd_sc_hd__a2bb2o_1 _3245_ (.A1_N(_1169_),
+ .A2_N(_1171_),
+ .B1(\Config_inst.INST_config_UART.HexData[3] ),
+ .B2(_1171_),
+ .X(_0382_));
+ sky130_fd_sc_hd__inv_2 _3247_ (.A(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .Y(_0028_));
+ sky130_fd_sc_hd__inv_2 _3249_ (.A(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .Y(_0026_));
+ sky130_fd_sc_hd__or4_1 _3250_ (.A(_0028_),
+ .B(_0026_),
+ .C(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .D(_1165_),
+ .X(_1559_));
+ sky130_fd_sc_hd__o211a_2 _3251_ (.A1(_0030_),
+ .A2(_1163_),
+ .B1(_1168_),
+ .C1(_1559_),
+ .X(_0024_));
+ sky130_fd_sc_hd__inv_2 _3252_ (.A(_0024_),
+ .Y(_1560_));
+ sky130_fd_sc_hd__a22o_1 _3253_ (.A1(\Config_inst.INST_config_UART.HexData[2] ),
+ .A2(_1171_),
+ .B1(_1172_),
+ .B2(_1560_),
+ .X(_0381_));
+ sky130_fd_sc_hd__a211o_1 _3254_ (.A1(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .A2(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .B1(_1166_),
+ .C1(_1165_),
+ .X(_1561_));
+ sky130_fd_sc_hd__o21ai_1 _3255_ (.A1(_0026_),
+ .A2(_1163_),
+ .B1(_1561_),
+ .Y(_1562_));
+ sky130_fd_sc_hd__a22o_1 _3256_ (.A1(\Config_inst.INST_config_UART.HexData[1] ),
+ .A2(_1171_),
+ .B1(_1172_),
+ .B2(_1562_),
+ .X(_0380_));
+ sky130_fd_sc_hd__nor2_1 _3257_ (.A(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .B(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .Y(_1563_));
+ sky130_fd_sc_hd__and2_1 _3258_ (.A(_1163_),
+ .B(_1167_),
+ .X(_1564_));
+ sky130_fd_sc_hd__o32a_1 _3259_ (.A1(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .A2(_1563_),
+ .A3(_1165_),
+ .B1(_0028_),
+ .B2(_1564_),
+ .X(_1565_));
+ sky130_fd_sc_hd__inv_2 _3261_ (.A(_1565_),
+ .Y(_1566_));
+ sky130_fd_sc_hd__a22o_1 _3262_ (.A1(\Config_inst.INST_config_UART.HexData[0] ),
+ .A2(_1171_),
+ .B1(_1172_),
+ .B2(_1566_),
+ .X(_0379_));
+ sky130_fd_sc_hd__nand2b_1 _3263_ (.A_N(_1170_),
+ .B(\Config_inst.INST_config_UART.ReceiveState ),
+ .Y(_1567_));
+ sky130_fd_sc_hd__a2bb2o_1 _3265_ (.A1_N(_1169_),
+ .A2_N(_1567_),
+ .B1(\Config_inst.INST_config_UART.HighReg[3] ),
+ .B2(_1567_),
+ .X(_0378_));
+ sky130_fd_sc_hd__a2bb2o_1 _3266_ (.A1_N(_0024_),
+ .A2_N(_1567_),
+ .B1(\Config_inst.INST_config_UART.HighReg[2] ),
+ .B2(_1567_),
+ .X(_0377_));
+ sky130_fd_sc_hd__inv_2 _3267_ (.A(_1562_),
+ .Y(_0023_));
+ sky130_fd_sc_hd__a2bb2o_1 _3268_ (.A1_N(_0023_),
+ .A2_N(_1567_),
+ .B1(\Config_inst.INST_config_UART.HighReg[1] ),
+ .B2(_1567_),
+ .X(_0376_));
+ sky130_fd_sc_hd__a2bb2o_1 _3269_ (.A1_N(_1565_),
+ .A2_N(_1567_),
+ .B1(\Config_inst.INST_config_UART.HighReg[0] ),
+ .B2(_1567_),
+ .X(_0375_));
+ sky130_fd_sc_hd__inv_2 _3270_ (.A(\Config_inst.Inst_bitbang.s_clk_sample[3] ),
+ .Y(_1569_));
+ sky130_fd_sc_hd__nand2_2 _3271_ (.A(FE_OFN31_Config_inst_Inst_bitbang_s_clk_sample_2),
+ .B(_1569_),
+ .Y(_1570_));
+ sky130_fd_sc_hd__inv_2 _3274_ (.A(_1570_),
+ .Y(_1573_));
+ sky130_fd_sc_hd__a22o_1 _3277_ (.A1(\Config_inst.Inst_bitbang.serial_data[31] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[30] ),
+ .B2(_1573_),
+ .X(_0374_));
+ sky130_fd_sc_hd__a22o_1 _3278_ (.A1(\Config_inst.Inst_bitbang.serial_data[30] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[29] ),
+ .B2(_1573_),
+ .X(_0373_));
+ sky130_fd_sc_hd__a22o_1 _3279_ (.A1(\Config_inst.Inst_bitbang.serial_data[29] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[28] ),
+ .B2(_1573_),
+ .X(_0372_));
+ sky130_fd_sc_hd__a22o_1 _3280_ (.A1(\Config_inst.Inst_bitbang.serial_data[28] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[27] ),
+ .B2(_1573_),
+ .X(_0371_));
+ sky130_fd_sc_hd__a22o_1 _3281_ (.A1(\Config_inst.Inst_bitbang.serial_data[27] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[26] ),
+ .B2(_1573_),
+ .X(_0370_));
+ sky130_fd_sc_hd__a22o_1 _3284_ (.A1(\Config_inst.Inst_bitbang.serial_data[26] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[25] ),
+ .B2(_1573_),
+ .X(_0369_));
+ sky130_fd_sc_hd__a22o_1 _3285_ (.A1(\Config_inst.Inst_bitbang.serial_data[25] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[24] ),
+ .B2(_1573_),
+ .X(_0368_));
+ sky130_fd_sc_hd__a22o_1 _3286_ (.A1(\Config_inst.Inst_bitbang.serial_data[24] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[23] ),
+ .B2(_1573_),
+ .X(_0367_));
+ sky130_fd_sc_hd__a22o_1 _3287_ (.A1(\Config_inst.Inst_bitbang.serial_data[23] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[22] ),
+ .B2(_1573_),
+ .X(_0366_));
+ sky130_fd_sc_hd__a22o_1 _3288_ (.A1(\Config_inst.Inst_bitbang.serial_data[22] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[21] ),
+ .B2(_1573_),
+ .X(_0365_));
+ sky130_fd_sc_hd__a22o_1 _3291_ (.A1(\Config_inst.Inst_bitbang.serial_data[21] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[20] ),
+ .B2(_1573_),
+ .X(_0364_));
+ sky130_fd_sc_hd__a22o_1 _3292_ (.A1(\Config_inst.Inst_bitbang.serial_data[20] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[19] ),
+ .B2(_1573_),
+ .X(_0363_));
+ sky130_fd_sc_hd__a22o_1 _3293_ (.A1(\Config_inst.Inst_bitbang.serial_data[19] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[18] ),
+ .B2(_1573_),
+ .X(_0362_));
+ sky130_fd_sc_hd__a22o_1 _3294_ (.A1(\Config_inst.Inst_bitbang.serial_data[18] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[17] ),
+ .B2(_1573_),
+ .X(_0361_));
+ sky130_fd_sc_hd__a22o_1 _3295_ (.A1(\Config_inst.Inst_bitbang.serial_data[17] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[16] ),
+ .B2(_1573_),
+ .X(_0360_));
+ sky130_fd_sc_hd__a22o_1 _3298_ (.A1(\Config_inst.Inst_bitbang.serial_data[16] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[15] ),
+ .B2(_1573_),
+ .X(_0359_));
+ sky130_fd_sc_hd__a22o_1 _3299_ (.A1(\Config_inst.Inst_bitbang.serial_data[15] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[14] ),
+ .B2(_1573_),
+ .X(_0358_));
+ sky130_fd_sc_hd__a22o_1 _3300_ (.A1(\Config_inst.Inst_bitbang.serial_data[14] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[13] ),
+ .B2(_1573_),
+ .X(_0357_));
+ sky130_fd_sc_hd__a22o_1 _3301_ (.A1(\Config_inst.Inst_bitbang.serial_data[13] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[12] ),
+ .B2(_1573_),
+ .X(_0356_));
+ sky130_fd_sc_hd__a22o_1 _3302_ (.A1(\Config_inst.Inst_bitbang.serial_data[12] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[11] ),
+ .B2(_1573_),
+ .X(_0355_));
+ sky130_fd_sc_hd__a22o_1 _3305_ (.A1(\Config_inst.Inst_bitbang.serial_data[11] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[10] ),
+ .B2(_1573_),
+ .X(_0354_));
+ sky130_fd_sc_hd__a22o_1 _3306_ (.A1(\Config_inst.Inst_bitbang.serial_data[10] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[9] ),
+ .B2(_1573_),
+ .X(_0353_));
+ sky130_fd_sc_hd__a22o_1 _3307_ (.A1(\Config_inst.Inst_bitbang.serial_data[9] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[8] ),
+ .B2(_1573_),
+ .X(_0352_));
+ sky130_fd_sc_hd__a22o_1 _3308_ (.A1(\Config_inst.Inst_bitbang.serial_data[8] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[7] ),
+ .B2(_1573_),
+ .X(_0351_));
+ sky130_fd_sc_hd__a22o_1 _3309_ (.A1(\Config_inst.Inst_bitbang.serial_data[7] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[6] ),
+ .B2(_1573_),
+ .X(_0350_));
+ sky130_fd_sc_hd__a22o_1 _3312_ (.A1(\Config_inst.Inst_bitbang.serial_data[6] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[5] ),
+ .B2(_1573_),
+ .X(_0349_));
+ sky130_fd_sc_hd__a22o_1 _3313_ (.A1(\Config_inst.Inst_bitbang.serial_data[5] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[4] ),
+ .B2(_1573_),
+ .X(_0348_));
+ sky130_fd_sc_hd__a22o_1 _3314_ (.A1(\Config_inst.Inst_bitbang.serial_data[4] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[3] ),
+ .B2(_1573_),
+ .X(_0347_));
+ sky130_fd_sc_hd__a22o_1 _3315_ (.A1(\Config_inst.Inst_bitbang.serial_data[3] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[2] ),
+ .B2(_1573_),
+ .X(_0346_));
+ sky130_fd_sc_hd__a22o_1 _3316_ (.A1(\Config_inst.Inst_bitbang.serial_data[2] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[1] ),
+ .B2(_1573_),
+ .X(_0345_));
+ sky130_fd_sc_hd__a22o_1 _3317_ (.A1(\Config_inst.Inst_bitbang.serial_data[1] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[0] ),
+ .B2(_1573_),
+ .X(_0344_));
+ sky130_fd_sc_hd__a22o_1 _3318_ (.A1(\Config_inst.Inst_bitbang.serial_data[0] ),
+ .A2(_1570_),
+ .B1(\Config_inst.Inst_bitbang.s_data_sample[3] ),
+ .B2(_1573_),
+ .X(_0343_));
+ sky130_fd_sc_hd__a22o_1 _3321_ (.A1(\Config_inst.BitBangWriteData[31] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[31] ),
+ .B2(_1127_),
+ .X(_0342_));
+ sky130_fd_sc_hd__a22o_1 _3322_ (.A1(\Config_inst.BitBangWriteData[30] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[30] ),
+ .B2(_1127_),
+ .X(_0341_));
+ sky130_fd_sc_hd__a22o_1 _3323_ (.A1(\Config_inst.BitBangWriteData[29] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[29] ),
+ .B2(_1127_),
+ .X(_0340_));
+ sky130_fd_sc_hd__a22o_1 _3326_ (.A1(\Config_inst.BitBangWriteData[28] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[28] ),
+ .B2(_1127_),
+ .X(_0339_));
+ sky130_fd_sc_hd__a22o_1 _3327_ (.A1(\Config_inst.BitBangWriteData[27] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[27] ),
+ .B2(_1127_),
+ .X(_0338_));
+ sky130_fd_sc_hd__a22o_1 _3329_ (.A1(\Config_inst.BitBangWriteData[26] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[26] ),
+ .B2(_1127_),
+ .X(_0337_));
+ sky130_fd_sc_hd__a22o_1 _3330_ (.A1(\Config_inst.BitBangWriteData[25] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[25] ),
+ .B2(_1127_),
+ .X(_0336_));
+ sky130_fd_sc_hd__a22o_1 _3331_ (.A1(\Config_inst.BitBangWriteData[24] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[24] ),
+ .B2(_1127_),
+ .X(_0335_));
+ sky130_fd_sc_hd__a22o_1 _3333_ (.A1(\Config_inst.BitBangWriteData[23] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[23] ),
+ .B2(_1127_),
+ .X(_0334_));
+ sky130_fd_sc_hd__a22o_1 _3334_ (.A1(\Config_inst.BitBangWriteData[22] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[22] ),
+ .B2(_1127_),
+ .X(_0333_));
+ sky130_fd_sc_hd__a22o_1 _3336_ (.A1(\Config_inst.BitBangWriteData[21] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[21] ),
+ .B2(_1127_),
+ .X(_0332_));
+ sky130_fd_sc_hd__a22o_1 _3337_ (.A1(\Config_inst.BitBangWriteData[20] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[20] ),
+ .B2(_1127_),
+ .X(_0331_));
+ sky130_fd_sc_hd__a22o_1 _3338_ (.A1(\Config_inst.BitBangWriteData[19] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[19] ),
+ .B2(_1127_),
+ .X(_0330_));
+ sky130_fd_sc_hd__a22o_1 _3340_ (.A1(\Config_inst.BitBangWriteData[18] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[18] ),
+ .B2(_1127_),
+ .X(_0329_));
+ sky130_fd_sc_hd__a22o_1 _3341_ (.A1(\Config_inst.BitBangWriteData[17] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[17] ),
+ .B2(_1127_),
+ .X(_0328_));
+ sky130_fd_sc_hd__a22o_1 _3343_ (.A1(\Config_inst.BitBangWriteData[16] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[16] ),
+ .B2(_1127_),
+ .X(_0327_));
+ sky130_fd_sc_hd__a22o_1 _3344_ (.A1(\Config_inst.BitBangWriteData[15] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[15] ),
+ .B2(_1127_),
+ .X(_0326_));
+ sky130_fd_sc_hd__a22o_1 _3345_ (.A1(\Config_inst.BitBangWriteData[14] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[14] ),
+ .B2(_1127_),
+ .X(_0325_));
+ sky130_fd_sc_hd__a22o_1 _3347_ (.A1(\Config_inst.BitBangWriteData[13] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[13] ),
+ .B2(_1127_),
+ .X(_0324_));
+ sky130_fd_sc_hd__a22o_1 _3348_ (.A1(\Config_inst.BitBangWriteData[12] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[12] ),
+ .B2(_1127_),
+ .X(_0323_));
+ sky130_fd_sc_hd__a22o_1 _3350_ (.A1(\Config_inst.BitBangWriteData[11] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[11] ),
+ .B2(_1127_),
+ .X(_0322_));
+ sky130_fd_sc_hd__a22o_1 _3351_ (.A1(\Config_inst.BitBangWriteData[10] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[10] ),
+ .B2(_1127_),
+ .X(_0321_));
+ sky130_fd_sc_hd__a22o_1 _3352_ (.A1(\Config_inst.BitBangWriteData[9] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[9] ),
+ .B2(_1127_),
+ .X(_0320_));
+ sky130_fd_sc_hd__a22o_1 _3354_ (.A1(\Config_inst.BitBangWriteData[8] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[8] ),
+ .B2(_1127_),
+ .X(_0319_));
+ sky130_fd_sc_hd__a22o_1 _3355_ (.A1(\Config_inst.BitBangWriteData[7] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[7] ),
+ .B2(_1127_),
+ .X(_0318_));
+ sky130_fd_sc_hd__a22o_1 _3357_ (.A1(\Config_inst.BitBangWriteData[6] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[6] ),
+ .B2(_1127_),
+ .X(_0317_));
+ sky130_fd_sc_hd__a22o_1 _3358_ (.A1(\Config_inst.BitBangWriteData[5] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[5] ),
+ .B2(_1127_),
+ .X(_0316_));
+ sky130_fd_sc_hd__a22o_1 _3359_ (.A1(\Config_inst.BitBangWriteData[4] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[4] ),
+ .B2(_1127_),
+ .X(_0315_));
+ sky130_fd_sc_hd__a22o_1 _3360_ (.A1(\Config_inst.BitBangWriteData[3] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[3] ),
+ .B2(_1127_),
+ .X(_0314_));
+ sky130_fd_sc_hd__a22o_1 _3361_ (.A1(\Config_inst.BitBangWriteData[2] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[2] ),
+ .B2(_1127_),
+ .X(_0313_));
+ sky130_fd_sc_hd__a22o_1 _3362_ (.A1(\Config_inst.BitBangWriteData[1] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[1] ),
+ .B2(_1127_),
+ .X(_0312_));
+ sky130_fd_sc_hd__a22o_1 _3363_ (.A1(\Config_inst.BitBangWriteData[0] ),
+ .A2(_1125_),
+ .B1(\Config_inst.Inst_bitbang.serial_data[0] ),
+ .B2(_1127_),
+ .X(_0311_));
+ sky130_fd_sc_hd__or2_2 _3364_ (.A(_1096_),
+ .B(_1110_),
+ .X(_1599_));
+ sky130_fd_sc_hd__inv_2 _3367_ (.A(FE_OFN177_1599),
+ .Y(_1602_));
+ sky130_fd_sc_hd__a22o_1 _3369_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[31] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN153_Config_inst_ConfigFSM_inst_WriteData_31),
+ .B2(_1602_),
+ .X(_0310_));
+ sky130_fd_sc_hd__a22o_1 _3372_ (.A1(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN151_Config_inst_ConfigFSM_inst_WriteData_30),
+ .B2(_1602_),
+ .X(_0309_));
+ sky130_fd_sc_hd__a22o_1 _3374_ (.A1(FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN148_Config_inst_ConfigFSM_inst_WriteData_29),
+ .B2(_1602_),
+ .X(_0308_));
+ sky130_fd_sc_hd__a22o_1 _3375_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[28] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN146_Config_inst_ConfigFSM_inst_WriteData_28),
+ .B2(_1602_),
+ .X(_0307_));
+ sky130_fd_sc_hd__a22o_1 _3376_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[27] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN144_Config_inst_ConfigFSM_inst_WriteData_27),
+ .B2(_1602_),
+ .X(_0306_));
+ sky130_fd_sc_hd__a22o_1 _3379_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[19] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN129_Config_inst_ConfigFSM_inst_WriteData_19),
+ .B2(_1602_),
+ .X(_0305_));
+ sky130_fd_sc_hd__a22o_1 _3380_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[18] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN127_Config_inst_ConfigFSM_inst_WriteData_18),
+ .B2(_1602_),
+ .X(_0304_));
+ sky130_fd_sc_hd__a22o_1 _3381_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[17] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN125_Config_inst_ConfigFSM_inst_WriteData_17),
+ .B2(_1602_),
+ .X(_0303_));
+ sky130_fd_sc_hd__a22o_1 _3382_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[16] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN123_Config_inst_ConfigFSM_inst_WriteData_16),
+ .B2(_1602_),
+ .X(_0302_));
+ sky130_fd_sc_hd__a22o_1 _3383_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[15] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[15] ),
+ .B2(_1602_),
+ .X(_0301_));
+ sky130_fd_sc_hd__a22o_1 _3386_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[14] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN119_Config_inst_ConfigFSM_inst_WriteData_14),
+ .B2(_1602_),
+ .X(_0300_));
+ sky130_fd_sc_hd__a22o_1 _3387_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[13] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[13] ),
+ .B2(_1602_),
+ .X(_0299_));
+ sky130_fd_sc_hd__a22o_1 _3388_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[12] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN115_Config_inst_ConfigFSM_inst_WriteData_12),
+ .B2(_1602_),
+ .X(_0298_));
+ sky130_fd_sc_hd__a22o_1 _3389_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[11] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[11] ),
+ .B2(_1602_),
+ .X(_0297_));
+ sky130_fd_sc_hd__a22o_1 _3390_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[10] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[10] ),
+ .B2(_1602_),
+ .X(_0296_));
+ sky130_fd_sc_hd__a22o_1 _3393_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[9] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[9] ),
+ .B2(_1602_),
+ .X(_0295_));
+ sky130_fd_sc_hd__a22o_1 _3394_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[8] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN165_Config_inst_ConfigFSM_inst_WriteData_8),
+ .B2(_1602_),
+ .X(_0294_));
+ sky130_fd_sc_hd__a22o_1 _3395_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[7] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN163_Config_inst_ConfigFSM_inst_WriteData_7),
+ .B2(_1602_),
+ .X(_0293_));
+ sky130_fd_sc_hd__a22o_1 _3396_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[6] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[6] ),
+ .B2(_1602_),
+ .X(_0292_));
+ sky130_fd_sc_hd__a22o_1 _3397_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[5] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[5] ),
+ .B2(_1602_),
+ .X(_0291_));
+ sky130_fd_sc_hd__a22o_1 _3400_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[4] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[4] ),
+ .B2(_1602_),
+ .X(_0290_));
+ sky130_fd_sc_hd__a22o_1 _3401_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[3] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[3] ),
+ .B2(_1602_),
+ .X(_0289_));
+ sky130_fd_sc_hd__a22o_1 _3402_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[2] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[2] ),
+ .B2(_1602_),
+ .X(_0288_));
+ sky130_fd_sc_hd__a22o_1 _3403_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[1] ),
+ .A2(FE_OFN177_1599),
+ .B1(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1602_),
+ .X(_0287_));
+ sky130_fd_sc_hd__a22o_1 _3404_ (.A1(\Config_inst.ConfigFSM_inst.FrameAddressRegister[0] ),
+ .A2(FE_OFN177_1599),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[0] ),
+ .B2(_1602_),
+ .X(_0286_));
+ sky130_fd_sc_hd__or2_2 _3405_ (.A(FE_OFN31_Config_inst_Inst_bitbang_s_clk_sample_2),
+ .B(_1569_),
+ .X(_1615_));
+ sky130_fd_sc_hd__inv_2 _3407_ (.A(_1615_),
+ .Y(_1617_));
+ sky130_fd_sc_hd__a22o_1 _3409_ (.A1(\Config_inst.Inst_bitbang.serial_control[15] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[14] ),
+ .B2(_1617_),
+ .X(_0285_));
+ sky130_fd_sc_hd__a22o_1 _3410_ (.A1(\Config_inst.Inst_bitbang.serial_control[14] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[13] ),
+ .B2(_1617_),
+ .X(_0284_));
+ sky130_fd_sc_hd__a22o_1 _3411_ (.A1(\Config_inst.Inst_bitbang.serial_control[13] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[12] ),
+ .B2(_1617_),
+ .X(_0283_));
+ sky130_fd_sc_hd__a22o_1 _3412_ (.A1(\Config_inst.Inst_bitbang.serial_control[12] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[11] ),
+ .B2(_1617_),
+ .X(_0282_));
+ sky130_fd_sc_hd__a22o_1 _3413_ (.A1(\Config_inst.Inst_bitbang.serial_control[11] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[10] ),
+ .B2(_1617_),
+ .X(_0281_));
+ sky130_fd_sc_hd__a22o_1 _3416_ (.A1(\Config_inst.Inst_bitbang.serial_control[10] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[9] ),
+ .B2(_1617_),
+ .X(_0280_));
+ sky130_fd_sc_hd__a22o_1 _3417_ (.A1(\Config_inst.Inst_bitbang.serial_control[9] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[8] ),
+ .B2(_1617_),
+ .X(_0279_));
+ sky130_fd_sc_hd__a22o_1 _3418_ (.A1(\Config_inst.Inst_bitbang.serial_control[8] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[7] ),
+ .B2(_1617_),
+ .X(_0278_));
+ sky130_fd_sc_hd__a22o_1 _3419_ (.A1(\Config_inst.Inst_bitbang.serial_control[7] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[6] ),
+ .B2(_1617_),
+ .X(_0277_));
+ sky130_fd_sc_hd__a22o_1 _3420_ (.A1(\Config_inst.Inst_bitbang.serial_control[6] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[5] ),
+ .B2(_1617_),
+ .X(_0276_));
+ sky130_fd_sc_hd__a22o_1 _3423_ (.A1(\Config_inst.Inst_bitbang.serial_control[5] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[4] ),
+ .B2(_1617_),
+ .X(_0275_));
+ sky130_fd_sc_hd__a22o_1 _3424_ (.A1(\Config_inst.Inst_bitbang.serial_control[4] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[3] ),
+ .B2(_1617_),
+ .X(_0274_));
+ sky130_fd_sc_hd__a22o_1 _3425_ (.A1(\Config_inst.Inst_bitbang.serial_control[3] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[2] ),
+ .B2(_1617_),
+ .X(_0273_));
+ sky130_fd_sc_hd__a22o_1 _3426_ (.A1(\Config_inst.Inst_bitbang.serial_control[2] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[1] ),
+ .B2(_1617_),
+ .X(_0272_));
+ sky130_fd_sc_hd__a22o_1 _3427_ (.A1(\Config_inst.Inst_bitbang.serial_control[1] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.serial_control[0] ),
+ .B2(_1617_),
+ .X(_0271_));
+ sky130_fd_sc_hd__a22o_1 _3428_ (.A1(\Config_inst.Inst_bitbang.serial_control[0] ),
+ .A2(_1615_),
+ .B1(\Config_inst.Inst_bitbang.s_data_sample[3] ),
+ .B2(_1617_),
+ .X(_0270_));
+ sky130_fd_sc_hd__inv_2 _3434_ (.A(\Config_inst.INST_config_UART.ComState[2] ),
+ .Y(_1628_));
+ sky130_fd_sc_hd__inv_2 _3436_ (.A(\Config_inst.INST_config_UART.ComState[0] ),
+ .Y(_1630_));
+ sky130_fd_sc_hd__a22o_1 _3438_ (.A1(\Config_inst.INST_config_UART.ComState[1] ),
+ .A2(_1630_),
+ .B1(\Config_inst.INST_config_UART.ComState[3] ),
+ .B2(_0904_),
+ .X(_1632_));
+ sky130_fd_sc_hd__inv_2 _3439_ (.A(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .Y(_0043_));
+ sky130_fd_sc_hd__o21a_1 _3440_ (.A1(_0905_),
+ .A2(\Config_inst.INST_config_UART.ComState[1] ),
+ .B1(\Config_inst.INST_config_UART.ComState[0] ),
+ .X(_1633_));
+ sky130_fd_sc_hd__a2bb2o_1 _3442_ (.A1_N(\Config_inst.INST_config_UART.ComState[2] ),
+ .A2_N(_1633_),
+ .B1(_0905_),
+ .B2(\Config_inst.INST_config_UART.ComTick ),
+ .X(_1635_));
+ sky130_fd_sc_hd__o21ai_1 _3443_ (.A1(_0043_),
+ .A2(_1132_),
+ .B1(_1635_),
+ .Y(_1636_));
+ sky130_fd_sc_hd__a31o_2 _3444_ (.A1(_1628_),
+ .A2(_1157_),
+ .A3(_1632_),
+ .B1(_1636_),
+ .X(_1637_));
+ sky130_fd_sc_hd__or4_1 _3445_ (.A(\Config_inst.INST_config_UART.ComState[3] ),
+ .B(\Config_inst.INST_config_UART.ComState[2] ),
+ .C(\Config_inst.INST_config_UART.ComState[0] ),
+ .D(_1637_),
+ .X(_1638_));
+ sky130_fd_sc_hd__mux2_2 _3446_ (.A0(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .A1(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .S(_1638_),
+ .X(_1639_));
+ sky130_fd_sc_hd__or2_2 _3448_ (.A(_0904_),
+ .B(_1630_),
+ .X(_1640_));
+ sky130_fd_sc_hd__a2111o_1 _3449_ (.A1(_1131_),
+ .A2(_1640_),
+ .B1(\Config_inst.INST_config_UART.ComState[3] ),
+ .C1(\Config_inst.INST_config_UART.ComState[2] ),
+ .D1(_1636_),
+ .X(_1641_));
+ sky130_fd_sc_hd__mux2_2 _3450_ (.A0(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .A1(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .S(_1641_),
+ .X(_1642_));
+ sky130_fd_sc_hd__or3_1 _3452_ (.A(\Config_inst.INST_config_UART.ComState[3] ),
+ .B(_1131_),
+ .C(_1636_),
+ .X(_1643_));
+ sky130_fd_sc_hd__mux2_2 _3453_ (.A0(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .A1(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .S(_1643_),
+ .X(_1644_));
+ sky130_fd_sc_hd__and4_1 _3455_ (.A(_0905_),
+ .B(\Config_inst.INST_config_UART.ComState[2] ),
+ .C(_0904_),
+ .D(\Config_inst.INST_config_UART.ComState[0] ),
+ .X(_1645_));
+ sky130_fd_sc_hd__o21bai_1 _3456_ (.A1(_1133_),
+ .A2(_1645_),
+ .B1_N(_1636_),
+ .Y(_1646_));
+ sky130_fd_sc_hd__mux2_2 _3457_ (.A0(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .A1(\Config_inst.INST_config_UART.ReceivedWord[3] ),
+ .S(_1646_),
+ .X(_1647_));
+ sky130_fd_sc_hd__or4_1 _3459_ (.A(_0904_),
+ .B(\Config_inst.INST_config_UART.ComState[0] ),
+ .C(\Config_inst.INST_config_UART.ComState[3] ),
+ .D(_1628_),
+ .X(_1648_));
+ sky130_fd_sc_hd__inv_2 _3460_ (.A(_1648_),
+ .Y(_0041_));
+ sky130_fd_sc_hd__o21ai_1 _3461_ (.A1(\Config_inst.INST_config_UART.ComTick ),
+ .A2(_1648_),
+ .B1(_0015_),
+ .Y(_1649_));
+ sky130_fd_sc_hd__inv_2 _3462_ (.A(_1649_),
+ .Y(_1650_));
+ sky130_fd_sc_hd__a32o_1 _3463_ (.A1(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .A2(_0041_),
+ .A3(_1650_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[4] ),
+ .B2(_1649_),
+ .X(_0265_));
+ sky130_fd_sc_hd__or3_1 _3464_ (.A(_0905_),
+ .B(\Config_inst.INST_config_UART.ComState[2] ),
+ .C(_1131_),
+ .X(_1651_));
+ sky130_fd_sc_hd__inv_2 _3466_ (.A(_1651_),
+ .Y(_1652_));
+ sky130_fd_sc_hd__a21oi_1 _3467_ (.A1(_1157_),
+ .A2(_1652_),
+ .B1(_0014_),
+ .Y(_1653_));
+ sky130_fd_sc_hd__inv_2 _3468_ (.A(_1653_),
+ .Y(_1654_));
+ sky130_fd_sc_hd__a32o_1 _3469_ (.A1(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .A2(_1652_),
+ .A3(_1653_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[6] ),
+ .B2(_1654_),
+ .X(_0264_));
+ sky130_fd_sc_hd__or3_1 _3470_ (.A(\Config_inst.INST_config_UART.ComState[3] ),
+ .B(_1628_),
+ .C(_1640_),
+ .X(_1655_));
+ sky130_fd_sc_hd__inv_2 _3472_ (.A(_1655_),
+ .Y(_1656_));
+ sky130_fd_sc_hd__a21oi_1 _3473_ (.A1(_1157_),
+ .A2(_1656_),
+ .B1(_0013_),
+ .Y(_1657_));
+ sky130_fd_sc_hd__inv_2 _3474_ (.A(_1657_),
+ .Y(_1658_));
+ sky130_fd_sc_hd__a32o_1 _3475_ (.A1(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .A2(_1656_),
+ .A3(_1657_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[5] ),
+ .B2(_1658_),
+ .X(_0263_));
+ sky130_fd_sc_hd__or4_1 _3476_ (.A(\Config_inst.INST_config_UART.PresentState[1] ),
+ .B(_1049_),
+ .C(\Config_inst.INST_config_UART.PresentState[2] ),
+ .D(_1158_),
+ .X(_1659_));
+ sky130_fd_sc_hd__inv_2 _3479_ (.A(_1659_),
+ .Y(_1662_));
+ sky130_fd_sc_hd__a22o_1 _3481_ (.A1(\Config_inst.INST_config_UART.ID_Reg[23] ),
+ .A2(_1659_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[7] ),
+ .B2(_1662_),
+ .X(_0262_));
+ sky130_fd_sc_hd__a22o_1 _3483_ (.A1(\Config_inst.INST_config_UART.ID_Reg[22] ),
+ .A2(_1659_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[6] ),
+ .B2(_1662_),
+ .X(_0261_));
+ sky130_fd_sc_hd__a22o_1 _3485_ (.A1(\Config_inst.INST_config_UART.ID_Reg[21] ),
+ .A2(_1659_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[5] ),
+ .B2(_1662_),
+ .X(_0260_));
+ sky130_fd_sc_hd__a22o_1 _3487_ (.A1(\Config_inst.INST_config_UART.ID_Reg[20] ),
+ .A2(_1659_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[4] ),
+ .B2(_1662_),
+ .X(_0259_));
+ sky130_fd_sc_hd__a22o_1 _3489_ (.A1(\Config_inst.INST_config_UART.ID_Reg[19] ),
+ .A2(_1659_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[3] ),
+ .B2(_1662_),
+ .X(_0258_));
+ sky130_fd_sc_hd__a22o_1 _3491_ (.A1(\Config_inst.INST_config_UART.ID_Reg[18] ),
+ .A2(_1659_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .B2(_1662_),
+ .X(_0257_));
+ sky130_fd_sc_hd__a22o_1 _3493_ (.A1(\Config_inst.INST_config_UART.ID_Reg[17] ),
+ .A2(_1659_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .B2(_1662_),
+ .X(_0256_));
+ sky130_fd_sc_hd__a22o_1 _3495_ (.A1(\Config_inst.INST_config_UART.ID_Reg[16] ),
+ .A2(_1659_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .B2(_1662_),
+ .X(_0255_));
+ sky130_fd_sc_hd__and3_1 _3496_ (.A(_0904_),
+ .B(\Config_inst.INST_config_UART.ComState[0] ),
+ .C(_1628_),
+ .X(_1671_));
+ sky130_fd_sc_hd__nand2_1 _3497_ (.A(\Config_inst.INST_config_UART.ComState[3] ),
+ .B(_1671_),
+ .Y(_1672_));
+ sky130_fd_sc_hd__inv_2 _3498_ (.A(_1672_),
+ .Y(_0042_));
+ sky130_fd_sc_hd__o21ai_1 _3499_ (.A1(\Config_inst.INST_config_UART.ComTick ),
+ .A2(_1672_),
+ .B1(_0012_),
+ .Y(_1673_));
+ sky130_fd_sc_hd__inv_2 _3500_ (.A(_1673_),
+ .Y(_1674_));
+ sky130_fd_sc_hd__a32o_1 _3501_ (.A1(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .A2(_0042_),
+ .A3(_1674_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[7] ),
+ .B2(_1673_),
+ .X(_0254_));
+ sky130_fd_sc_hd__or2_2 _3502_ (.A(_1091_),
+ .B(_1049_),
+ .X(_1675_));
+ sky130_fd_sc_hd__o21a_1 _3503_ (.A1(\Config_inst.INST_config_UART.PresentState[2] ),
+ .A2(_1675_),
+ .B1(_0999_),
+ .X(_1676_));
+ sky130_fd_sc_hd__or4bb_1 _3506_ (.A(\Config_inst.INST_config_UART.ID_Reg[14] ),
+ .B(\Config_inst.INST_config_UART.ID_Reg[12] ),
+ .C_N(\Config_inst.INST_config_UART.ID_Reg[13] ),
+ .D_N(\Config_inst.INST_config_UART.ID_Reg[11] ),
+ .X(_1679_));
+ sky130_fd_sc_hd__or4b_2 _3507_ (.A(\Config_inst.INST_config_UART.ID_Reg[10] ),
+ .B(_1679_),
+ .C(\Config_inst.INST_config_UART.ID_Reg[8] ),
+ .D_N(\Config_inst.INST_config_UART.ID_Reg[9] ),
+ .X(_1680_));
+ sky130_fd_sc_hd__or4_1 _3508_ (.A(\Config_inst.INST_config_UART.ID_Reg[21] ),
+ .B(\Config_inst.INST_config_UART.ID_Reg[20] ),
+ .C(\Config_inst.INST_config_UART.ID_Reg[19] ),
+ .D(\Config_inst.INST_config_UART.ID_Reg[18] ),
+ .X(_1681_));
+ sky130_fd_sc_hd__nand4_1 _3509_ (.A(\Config_inst.INST_config_UART.ID_Reg[5] ),
+ .B(\Config_inst.INST_config_UART.ID_Reg[4] ),
+ .C(\Config_inst.INST_config_UART.ID_Reg[3] ),
+ .D(\Config_inst.INST_config_UART.ID_Reg[2] ),
+ .Y(_1682_));
+ sky130_fd_sc_hd__or4bb_1 _3510_ (.A(\Config_inst.INST_config_UART.ID_Reg[17] ),
+ .B(\Config_inst.INST_config_UART.ID_Reg[16] ),
+ .C_N(\Config_inst.INST_config_UART.ID_Reg[7] ),
+ .D_N(\Config_inst.INST_config_UART.ID_Reg[6] ),
+ .X(_1683_));
+ sky130_fd_sc_hd__or4b_2 _3511_ (.A(\Config_inst.Command[4] ),
+ .B(\Config_inst.Command[3] ),
+ .C(\Config_inst.Command[2] ),
+ .D_N(\Config_inst.INST_config_UART.ID_Reg[15] ),
+ .X(_1684_));
+ sky130_fd_sc_hd__inv_2 _3512_ (.A(\Config_inst.INST_config_UART.ID_Reg[0] ),
+ .Y(_1685_));
+ sky130_fd_sc_hd__or4b_2 _3513_ (.A(\Config_inst.Command[5] ),
+ .B(_1685_),
+ .C(\Config_inst.Command[6] ),
+ .D_N(\Config_inst.INST_config_UART.ID_Reg[1] ),
+ .X(_1686_));
+ sky130_fd_sc_hd__or4_1 _3514_ (.A(_1682_),
+ .B(_1683_),
+ .C(_1684_),
+ .D(_1686_),
+ .X(_1687_));
+ sky130_fd_sc_hd__or4_1 _3515_ (.A(\Config_inst.INST_config_UART.ID_Reg[23] ),
+ .B(\Config_inst.INST_config_UART.ID_Reg[22] ),
+ .C(_1681_),
+ .D(_1687_),
+ .X(_1688_));
+ sky130_fd_sc_hd__or4_1 _3516_ (.A(_1050_),
+ .B(_1678_),
+ .C(_1680_),
+ .D(_1688_),
+ .X(_1689_));
+ sky130_fd_sc_hd__o21a_1 _3517_ (.A1(\Config_inst.INST_config_UART.TimeToSend ),
+ .A2(_1676_),
+ .B1(_1689_),
+ .X(_1690_));
+ sky130_fd_sc_hd__nor2_1 _3518_ (.A(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .B(_1132_),
+ .Y(_1691_));
+ sky130_fd_sc_hd__inv_2 _3519_ (.A(_1158_),
+ .Y(_1692_));
+ sky130_fd_sc_hd__o32a_1 _3520_ (.A1(\Config_inst.INST_config_UART.PresentState[1] ),
+ .A2(_1049_),
+ .A3(\Config_inst.INST_config_UART.PresentState[2] ),
+ .B1(\Config_inst.INST_config_UART.PresentState[2] ),
+ .B2(_1092_),
+ .X(_1693_));
+ sky130_fd_sc_hd__and2_1 _3521_ (.A(_1676_),
+ .B(_1693_),
+ .X(_1694_));
+ sky130_fd_sc_hd__o21a_1 _3522_ (.A1(_1692_),
+ .A2(_1694_),
+ .B1(_1093_),
+ .X(_1695_));
+ sky130_fd_sc_hd__o22a_1 _3523_ (.A1(\Config_inst.INST_config_UART.TimeToSend ),
+ .A2(_1695_),
+ .B1(_0997_),
+ .B2(_1675_),
+ .X(_1696_));
+ sky130_fd_sc_hd__o21ai_1 _3524_ (.A1(_0910_),
+ .A2(_1691_),
+ .B1(_1696_),
+ .Y(_1697_));
+ sky130_fd_sc_hd__o22ai_1 _3525_ (.A1(_1690_),
+ .A2(_1697_),
+ .B1(_0997_),
+ .B2(_1696_),
+ .Y(_0253_));
+ sky130_fd_sc_hd__o21a_1 _3526_ (.A1(\Config_inst.INST_config_UART.TimeToSend ),
+ .A2(_1693_),
+ .B1(_1689_),
+ .X(_1698_));
+ sky130_fd_sc_hd__mux2_2 _3527_ (.A0(_1698_),
+ .A1(_1091_),
+ .S(_1697_),
+ .X(_1699_));
+ sky130_fd_sc_hd__inv_2 _3528_ (.A(_1699_),
+ .Y(_0252_));
+ sky130_fd_sc_hd__o21a_1 _3529_ (.A1(\Config_inst.INST_config_UART.PresentState[2] ),
+ .A2(_1092_),
+ .B1(_0999_),
+ .X(_1700_));
+ sky130_fd_sc_hd__o221a_2 _3530_ (.A1(_0997_),
+ .A2(_1675_),
+ .B1(\Config_inst.INST_config_UART.TimeToSend ),
+ .B2(_1700_),
+ .C1(_0910_),
+ .X(_1701_));
+ sky130_fd_sc_hd__mux2_2 _3531_ (.A0(_1701_),
+ .A1(_1049_),
+ .S(_1697_),
+ .X(_1702_));
+ sky130_fd_sc_hd__inv_2 _3532_ (.A(_1702_),
+ .Y(_0251_));
+ sky130_fd_sc_hd__or2_2 _3567_ (.A(_1263_),
+ .B(_1314_),
+ .X(_1720_));
+ sky130_fd_sc_hd__inv_2 _3570_ (.A(_1720_),
+ .Y(_1723_));
+ sky130_fd_sc_hd__a22o_1 _3573_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[31] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[31] ),
+ .B2(_1723_),
+ .X(_0233_));
+ sky130_fd_sc_hd__a22o_1 _3574_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[30] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[30] ),
+ .B2(_1723_),
+ .X(_0232_));
+ sky130_fd_sc_hd__a22o_1 _3575_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[29] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[29] ),
+ .B2(_1723_),
+ .X(_0231_));
+ sky130_fd_sc_hd__a22o_1 _3576_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[28] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[28] ),
+ .B2(_1723_),
+ .X(_0230_));
+ sky130_fd_sc_hd__a22o_1 _3577_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[27] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[27] ),
+ .B2(_1723_),
+ .X(_0229_));
+ sky130_fd_sc_hd__a22o_1 _3580_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[26] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[26] ),
+ .B2(_1723_),
+ .X(_0228_));
+ sky130_fd_sc_hd__a22o_1 _3581_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[25] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[25] ),
+ .B2(_1723_),
+ .X(_0227_));
+ sky130_fd_sc_hd__a22o_1 _3582_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[24] ),
+ .A2(_1720_),
+ .B1(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B2(_1723_),
+ .X(_0226_));
+ sky130_fd_sc_hd__a22o_1 _3583_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[23] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[23] ),
+ .B2(_1723_),
+ .X(_0225_));
+ sky130_fd_sc_hd__a22o_1 _3584_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[22] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[22] ),
+ .B2(_1723_),
+ .X(_0224_));
+ sky130_fd_sc_hd__a22o_1 _3587_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[21] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[21] ),
+ .B2(_1723_),
+ .X(_0223_));
+ sky130_fd_sc_hd__a22o_1 _3588_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[20] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .B2(_1723_),
+ .X(_0222_));
+ sky130_fd_sc_hd__a22o_1 _3589_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[19] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[19] ),
+ .B2(_1723_),
+ .X(_0221_));
+ sky130_fd_sc_hd__a22o_1 _3590_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[18] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[18] ),
+ .B2(_1723_),
+ .X(_0220_));
+ sky130_fd_sc_hd__a22o_1 _3591_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[17] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[17] ),
+ .B2(_1723_),
+ .X(_0219_));
+ sky130_fd_sc_hd__a22o_1 _3594_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[16] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[16] ),
+ .B2(_1723_),
+ .X(_0218_));
+ sky130_fd_sc_hd__a22o_1 _3595_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[15] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[15] ),
+ .B2(_1723_),
+ .X(_0217_));
+ sky130_fd_sc_hd__a22o_1 _3596_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[14] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[14] ),
+ .B2(_1723_),
+ .X(_0216_));
+ sky130_fd_sc_hd__a22o_1 _3597_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[13] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[13] ),
+ .B2(_1723_),
+ .X(_0215_));
+ sky130_fd_sc_hd__a22o_1 _3598_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[12] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[12] ),
+ .B2(_1723_),
+ .X(_0214_));
+ sky130_fd_sc_hd__a22o_1 _3601_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[11] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[11] ),
+ .B2(_1723_),
+ .X(_0213_));
+ sky130_fd_sc_hd__a22o_1 _3602_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[10] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[10] ),
+ .B2(_1723_),
+ .X(_0212_));
+ sky130_fd_sc_hd__a22o_1 _3603_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[9] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[9] ),
+ .B2(_1723_),
+ .X(_0211_));
+ sky130_fd_sc_hd__a22o_1 _3604_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[8] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[8] ),
+ .B2(_1723_),
+ .X(_0210_));
+ sky130_fd_sc_hd__a22o_1 _3605_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[7] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[7] ),
+ .B2(_1723_),
+ .X(_0209_));
+ sky130_fd_sc_hd__a22o_1 _3608_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[6] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[6] ),
+ .B2(_1723_),
+ .X(_0208_));
+ sky130_fd_sc_hd__a22o_1 _3609_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[5] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[5] ),
+ .B2(_1723_),
+ .X(_0207_));
+ sky130_fd_sc_hd__a22o_1 _3610_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[4] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[4] ),
+ .B2(_1723_),
+ .X(_0206_));
+ sky130_fd_sc_hd__a22o_1 _3611_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[3] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[3] ),
+ .B2(_1723_),
+ .X(_0205_));
+ sky130_fd_sc_hd__a22o_1 _3612_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[2] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[2] ),
+ .B2(_1723_),
+ .X(_0204_));
+ sky130_fd_sc_hd__a22o_1 _3613_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[1] ),
+ .A2(_1720_),
+ .B1(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .B2(_1723_),
+ .X(_0203_));
+ sky130_fd_sc_hd__a22o_1 _3614_ (.A1(\Inst_Frame_Data_Reg_9.FrameData_O[0] ),
+ .A2(_1720_),
+ .B1(\Config_inst.ConfigFSM_inst.WriteData[0] ),
+ .B2(_1723_),
+ .X(_0202_));
+ sky130_fd_sc_hd__or3_1 _3615_ (.A(\Config_inst.INST_config_UART.PresentState[2] ),
+ .B(_1675_),
+ .C(_1158_),
+ .X(_1736_));
+ sky130_fd_sc_hd__inv_2 _3618_ (.A(_1736_),
+ .Y(_1739_));
+ sky130_fd_sc_hd__a22o_1 _3620_ (.A1(\Config_inst.INST_config_UART.ID_Reg[7] ),
+ .A2(_1736_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[7] ),
+ .B2(_1739_),
+ .X(_0201_));
+ sky130_fd_sc_hd__a22o_1 _3621_ (.A1(\Config_inst.INST_config_UART.ID_Reg[6] ),
+ .A2(_1736_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[6] ),
+ .B2(_1739_),
+ .X(_0200_));
+ sky130_fd_sc_hd__a22o_1 _3622_ (.A1(\Config_inst.INST_config_UART.ID_Reg[5] ),
+ .A2(_1736_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[5] ),
+ .B2(_1739_),
+ .X(_0199_));
+ sky130_fd_sc_hd__a22o_1 _3623_ (.A1(\Config_inst.INST_config_UART.ID_Reg[4] ),
+ .A2(_1736_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[4] ),
+ .B2(_1739_),
+ .X(_0198_));
+ sky130_fd_sc_hd__a22o_1 _3624_ (.A1(\Config_inst.INST_config_UART.ID_Reg[3] ),
+ .A2(_1736_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[3] ),
+ .B2(_1739_),
+ .X(_0197_));
+ sky130_fd_sc_hd__a22o_1 _3625_ (.A1(\Config_inst.INST_config_UART.ID_Reg[2] ),
+ .A2(_1736_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .B2(_1739_),
+ .X(_0196_));
+ sky130_fd_sc_hd__a22o_1 _3626_ (.A1(\Config_inst.INST_config_UART.ID_Reg[1] ),
+ .A2(_1736_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .B2(_1739_),
+ .X(_0195_));
+ sky130_fd_sc_hd__a22o_1 _3627_ (.A1(\Config_inst.INST_config_UART.ID_Reg[0] ),
+ .A2(_1736_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .B2(_1739_),
+ .X(_0194_));
+ sky130_fd_sc_hd__or2_2 _3628_ (.A(_0999_),
+ .B(_1158_),
+ .X(_1741_));
+ sky130_fd_sc_hd__inv_2 _3630_ (.A(_1741_),
+ .Y(_1743_));
+ sky130_fd_sc_hd__a22o_1 _3632_ (.A1(\Config_inst.Command[7] ),
+ .A2(_1741_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[7] ),
+ .B2(_1743_),
+ .X(_0193_));
+ sky130_fd_sc_hd__a22o_1 _3633_ (.A1(\Config_inst.Command[6] ),
+ .A2(_1741_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[6] ),
+ .B2(_1743_),
+ .X(_0192_));
+ sky130_fd_sc_hd__a22o_1 _3634_ (.A1(\Config_inst.Command[5] ),
+ .A2(_1741_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[5] ),
+ .B2(_1743_),
+ .X(_0191_));
+ sky130_fd_sc_hd__a22o_1 _3635_ (.A1(\Config_inst.Command[4] ),
+ .A2(_1741_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[4] ),
+ .B2(_1743_),
+ .X(_0190_));
+ sky130_fd_sc_hd__a22o_1 _3636_ (.A1(\Config_inst.Command[3] ),
+ .A2(_1741_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[3] ),
+ .B2(_1743_),
+ .X(_0189_));
+ sky130_fd_sc_hd__a22o_1 _3637_ (.A1(\Config_inst.Command[2] ),
+ .A2(_1741_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .B2(_1743_),
+ .X(_0188_));
+ sky130_fd_sc_hd__a22o_1 _3638_ (.A1(\Config_inst.Command[1] ),
+ .A2(_1741_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .B2(_1743_),
+ .X(_0187_));
+ sky130_fd_sc_hd__a22o_1 _3639_ (.A1(\Config_inst.Command[0] ),
+ .A2(_1741_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .B2(_1743_),
+ .X(_0186_));
+ sky130_fd_sc_hd__a22o_1 _3644_ (.A1(\Config_inst.INST_config_UART.Data_Reg[7] ),
+ .A2(_1160_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[7] ),
+ .B2(_1161_),
+ .X(_0185_));
+ sky130_fd_sc_hd__a22o_1 _3645_ (.A1(\Config_inst.INST_config_UART.Data_Reg[6] ),
+ .A2(_1160_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[6] ),
+ .B2(_1161_),
+ .X(_0184_));
+ sky130_fd_sc_hd__a22o_1 _3646_ (.A1(\Config_inst.INST_config_UART.Data_Reg[5] ),
+ .A2(_1160_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[5] ),
+ .B2(_1161_),
+ .X(_0183_));
+ sky130_fd_sc_hd__a22o_1 _3647_ (.A1(\Config_inst.INST_config_UART.Data_Reg[4] ),
+ .A2(_1160_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[4] ),
+ .B2(_1161_),
+ .X(_0182_));
+ sky130_fd_sc_hd__a22o_1 _3648_ (.A1(\Config_inst.INST_config_UART.Data_Reg[3] ),
+ .A2(_1160_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[3] ),
+ .B2(_1161_),
+ .X(_0181_));
+ sky130_fd_sc_hd__a22o_1 _3649_ (.A1(\Config_inst.INST_config_UART.Data_Reg[2] ),
+ .A2(_1160_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .B2(_1161_),
+ .X(_0180_));
+ sky130_fd_sc_hd__a22o_1 _3650_ (.A1(\Config_inst.INST_config_UART.Data_Reg[1] ),
+ .A2(_1160_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .B2(_1161_),
+ .X(_0179_));
+ sky130_fd_sc_hd__a22o_1 _3651_ (.A1(\Config_inst.INST_config_UART.Data_Reg[0] ),
+ .A2(_1160_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .B2(_1161_),
+ .X(_0178_));
+ sky130_fd_sc_hd__nor2_1 _3652_ (.A(_1637_),
+ .B(_1671_),
+ .Y(_1748_));
+ sky130_fd_sc_hd__nor2_1 _3653_ (.A(_1652_),
+ .B(_1656_),
+ .Y(_1749_));
+ sky130_fd_sc_hd__o22ai_1 _3654_ (.A1(_0905_),
+ .A2(_1748_),
+ .B1(_1637_),
+ .B2(_1749_),
+ .Y(_0177_));
+ sky130_fd_sc_hd__nor2_1 _3655_ (.A(_1636_),
+ .B(_1640_),
+ .Y(_1750_));
+ sky130_fd_sc_hd__a31oi_1 _3657_ (.A1(_1131_),
+ .A2(_1640_),
+ .A3(_0905_),
+ .B1(_1671_),
+ .Y(_1751_));
+ sky130_fd_sc_hd__mux2_2 _3658_ (.A0(_1751_),
+ .A1(_0904_),
+ .S(_1637_),
+ .X(_1752_));
+ sky130_fd_sc_hd__inv_2 _3659_ (.A(_1752_),
+ .Y(_0175_));
+ sky130_fd_sc_hd__nor2_1 _3660_ (.A(\Config_inst.INST_config_UART.ComState[0] ),
+ .B(_0907_),
+ .Y(_1753_));
+ sky130_fd_sc_hd__mux2_2 _3661_ (.A0(_1753_),
+ .A1(\Config_inst.INST_config_UART.ComState[0] ),
+ .S(_1637_),
+ .X(_1754_));
+ sky130_fd_sc_hd__or3_1 _3727_ (.A(\Config_inst.INST_config_UART.PresentState[2] ),
+ .B(_1092_),
+ .C(_1158_),
+ .X(_1787_));
+ sky130_fd_sc_hd__inv_2 _3730_ (.A(_1787_),
+ .Y(_1790_));
+ sky130_fd_sc_hd__a22o_1 _3732_ (.A1(\Config_inst.INST_config_UART.ID_Reg[15] ),
+ .A2(_1787_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[7] ),
+ .B2(_1790_),
+ .X(_0141_));
+ sky130_fd_sc_hd__a22o_1 _3733_ (.A1(\Config_inst.INST_config_UART.ID_Reg[14] ),
+ .A2(_1787_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[6] ),
+ .B2(_1790_),
+ .X(_0140_));
+ sky130_fd_sc_hd__a22o_1 _3734_ (.A1(\Config_inst.INST_config_UART.ID_Reg[13] ),
+ .A2(_1787_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[5] ),
+ .B2(_1790_),
+ .X(_0139_));
+ sky130_fd_sc_hd__a22o_1 _3735_ (.A1(\Config_inst.INST_config_UART.ID_Reg[12] ),
+ .A2(_1787_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[4] ),
+ .B2(_1790_),
+ .X(_0138_));
+ sky130_fd_sc_hd__a22o_1 _3736_ (.A1(\Config_inst.INST_config_UART.ID_Reg[11] ),
+ .A2(_1787_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[3] ),
+ .B2(_1790_),
+ .X(_0137_));
+ sky130_fd_sc_hd__a22o_1 _3737_ (.A1(\Config_inst.INST_config_UART.ID_Reg[10] ),
+ .A2(_1787_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[2] ),
+ .B2(_1790_),
+ .X(_0136_));
+ sky130_fd_sc_hd__a22o_1 _3738_ (.A1(\Config_inst.INST_config_UART.ID_Reg[9] ),
+ .A2(_1787_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[1] ),
+ .B2(_1790_),
+ .X(_0135_));
+ sky130_fd_sc_hd__a22o_1 _3739_ (.A1(\Config_inst.INST_config_UART.ID_Reg[8] ),
+ .A2(_1787_),
+ .B1(\Config_inst.INST_config_UART.ReceivedWord[0] ),
+ .B2(_1790_),
+ .X(_0134_));
+ sky130_fd_sc_hd__inv_2 _3740_ (.A(\Config_inst.INST_config_UART.blink[0] ),
+ .Y(_0044_));
+ sky130_fd_sc_hd__and2b_1 _3741_ (.A_N(config_strobe_reg2),
+ .B(config_strobe_reg3),
+ .X(_1792_));
+ sky130_fd_sc_hd__nor2_1 _3743_ (.A(\Config_inst.ConfigFSM_inst.state[1] ),
+ .B(\Config_inst.ConfigFSM_inst.state[0] ),
+ .Y(_0018_));
+ sky130_fd_sc_hd__or2_2 _3744_ (.A(_1081_),
+ .B(_0018_),
+ .X(_1793_));
+ sky130_fd_sc_hd__or4bb_1 _3746_ (.A(\Config_inst.ConfigFSM_inst.WriteData[8] ),
+ .B(\Config_inst.ConfigFSM_inst.WriteData[10] ),
+ .C_N(\Config_inst.ConfigFSM_inst.WriteData[9] ),
+ .D_N(\Config_inst.ConfigFSM_inst.WriteData[11] ),
+ .X(_1794_));
+ sky130_fd_sc_hd__nand4_1 _3747_ (.A(\Config_inst.ConfigFSM_inst.WriteData[15] ),
+ .B(\Config_inst.ConfigFSM_inst.WriteData[14] ),
+ .C(\Config_inst.ConfigFSM_inst.WriteData[13] ),
+ .D(\Config_inst.ConfigFSM_inst.WriteData[12] ),
+ .Y(_1795_));
+ sky130_fd_sc_hd__or4b_2 _3748_ (.A(\Config_inst.ConfigFSM_inst.WriteData[3] ),
+ .B(\Config_inst.ConfigFSM_inst.WriteData[2] ),
+ .C(FE_OFN131_Config_inst_ConfigFSM_inst_WriteData_1),
+ .D_N(\Config_inst.ConfigFSM_inst.WriteData[0] ),
+ .X(_1796_));
+ sky130_fd_sc_hd__nand4b_1 _3749_ (.A_N(\Config_inst.ConfigFSM_inst.WriteData[6] ),
+ .B(\Config_inst.ConfigFSM_inst.WriteData[7] ),
+ .C(\Config_inst.ConfigFSM_inst.WriteData[5] ),
+ .D(\Config_inst.ConfigFSM_inst.WriteData[4] ),
+ .Y(_1797_));
+ sky130_fd_sc_hd__or4_1 _3750_ (.A(_1794_),
+ .B(_1795_),
+ .C(_1796_),
+ .D(_1797_),
+ .X(_1798_));
+ sky130_fd_sc_hd__or4bb_1 _3751_ (.A(FE_OFN140_Config_inst_ConfigFSM_inst_WriteData_24),
+ .B(\Config_inst.ConfigFSM_inst.WriteData[26] ),
+ .C_N(\Config_inst.ConfigFSM_inst.WriteData[25] ),
+ .D_N(\Config_inst.ConfigFSM_inst.WriteData[27] ),
+ .X(_1799_));
+ sky130_fd_sc_hd__nand4_1 _3752_ (.A(\Config_inst.ConfigFSM_inst.WriteData[31] ),
+ .B(\Config_inst.ConfigFSM_inst.WriteData[30] ),
+ .C(\Config_inst.ConfigFSM_inst.WriteData[29] ),
+ .D(\Config_inst.ConfigFSM_inst.WriteData[28] ),
+ .Y(_1800_));
+ sky130_fd_sc_hd__or4_1 _3753_ (.A(\Config_inst.ConfigFSM_inst.WriteData[19] ),
+ .B(\Config_inst.ConfigFSM_inst.WriteData[18] ),
+ .C(\Config_inst.ConfigFSM_inst.WriteData[17] ),
+ .D(\Config_inst.ConfigFSM_inst.WriteData[16] ),
+ .X(_1801_));
+ sky130_fd_sc_hd__nand4b_1 _3754_ (.A_N(\Config_inst.ConfigFSM_inst.WriteData[22] ),
+ .B(\Config_inst.ConfigFSM_inst.WriteData[23] ),
+ .C(\Config_inst.ConfigFSM_inst.WriteData[21] ),
+ .D(\Config_inst.ConfigFSM_inst.WriteData[20] ),
+ .Y(_1802_));
+ sky130_fd_sc_hd__or4_1 _3755_ (.A(_1799_),
+ .B(_1800_),
+ .C(_1801_),
+ .D(_1802_),
+ .X(_1803_));
+ sky130_fd_sc_hd__o21a_1 _3756_ (.A1(_1798_),
+ .A2(_1803_),
+ .B1(_0011_),
+ .X(_0017_));
+ sky130_fd_sc_hd__nor2_1 _3757_ (.A(\Config_inst.INST_config_UART.ReceiveState ),
+ .B(_1173_),
+ .Y(_0020_));
+ sky130_fd_sc_hd__or2_2 _3758_ (.A(\Config_inst.ConfigFSM_inst.oldFrameStrobe ),
+ .B(\Config_inst.ConfigFSM_inst.FrameStrobe ),
+ .X(_1804_));
+ sky130_fd_sc_hd__nor2_2 _3760_ (.A(latch_fabric_strobe),
+ .B(fabric_strobe_reg2),
+ .Y(_0001_));
+ sky130_fd_sc_hd__nor2_2 _3761_ (.A(config_strobe_reg2),
+ .B(latch_config_strobe),
+ .Y(_0000_));
+ sky130_fd_sc_hd__and2b_2 _3762_ (.A_N(fabric_strobe_reg2),
+ .B(fabric_strobe_reg3),
+ .X(_1805_));
+ sky130_fd_sc_hd__inv_8 _3764_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[0] ),
+ .Y(_1806_));
+ sky130_fd_sc_hd__inv_2 _3766_ (.A(\Config_inst.ConfigFSM_inst.LongFrameStrobe ),
+ .Y(_1808_));
+ sky130_fd_sc_hd__or4_4 _3767_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[31] ),
+ .B(_1808_),
+ .C(\Config_inst.ConfigFSM_inst.FrameAddressRegister[28] ),
+ .D(\Config_inst.ConfigFSM_inst.FrameAddressRegister[27] ),
+ .X(_1809_));
+ sky130_fd_sc_hd__or3_2 _3768_ (.A(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30),
+ .B(FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29),
+ .C(_1809_),
+ .X(_1810_));
+ sky130_fd_sc_hd__nor2_1 _3770_ (.A(_1806_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__inv_8 _3771_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[1] ),
+ .Y(_1812_));
+ sky130_fd_sc_hd__nor2_1 _3773_ (.A(_1812_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__inv_2 _3774_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[2] ),
+ .Y(_1814_));
+ sky130_fd_sc_hd__nor2_1 _3776_ (.A(_1814_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__inv_2 _3777_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[3] ),
+ .Y(_1816_));
+ sky130_fd_sc_hd__nor2_1 _3779_ (.A(_1816_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__inv_2 _3780_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[4] ),
+ .Y(_1818_));
+ sky130_fd_sc_hd__nor2_1 _3782_ (.A(_1818_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__inv_8 _3783_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[5] ),
+ .Y(_1820_));
+ sky130_fd_sc_hd__nor2_2 _3786_ (.A(_1820_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__inv_2 _3787_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[6] ),
+ .Y(_1823_));
+ sky130_fd_sc_hd__nor2_2 _3789_ (.A(_1823_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__inv_2 _3790_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[7] ),
+ .Y(_1825_));
+ sky130_fd_sc_hd__nor2_1 _3792_ (.A(_1825_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__inv_2 _3793_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[8] ),
+ .Y(_1827_));
+ sky130_fd_sc_hd__nor2_1 _3795_ (.A(_1827_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__inv_2 _3796_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[9] ),
+ .Y(_1829_));
+ sky130_fd_sc_hd__nor2_2 _3798_ (.A(_1829_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__inv_2 _3799_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[10] ),
+ .Y(_1831_));
+ sky130_fd_sc_hd__nor2_1 _3802_ (.A(_1831_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__inv_2 _3803_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[11] ),
+ .Y(_1834_));
+ sky130_fd_sc_hd__nor2_2 _3805_ (.A(_1834_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__inv_8 _3806_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[12] ),
+ .Y(_1836_));
+ sky130_fd_sc_hd__nor2_2 _3808_ (.A(_1836_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__inv_2 _3809_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[13] ),
+ .Y(_1838_));
+ sky130_fd_sc_hd__nor2_2 _3811_ (.A(_1838_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__inv_2 _3812_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[14] ),
+ .Y(_1840_));
+ sky130_fd_sc_hd__nor2_2 _3814_ (.A(_1840_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__inv_8 _3815_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[15] ),
+ .Y(_1842_));
+ sky130_fd_sc_hd__nor2_1 _3818_ (.A(_1842_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__inv_2 _3819_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[16] ),
+ .Y(_1845_));
+ sky130_fd_sc_hd__nor2_1 _3821_ (.A(_1845_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__inv_4 _3822_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[17] ),
+ .Y(_1847_));
+ sky130_fd_sc_hd__nor2_2 _3824_ (.A(_1847_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__inv_2 _3825_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[18] ),
+ .Y(_1849_));
+ sky130_fd_sc_hd__nor2_1 _3827_ (.A(_1849_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__inv_4 _3828_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[19] ),
+ .Y(_1851_));
+ sky130_fd_sc_hd__nor2_1 _3830_ (.A(_1851_),
+ .B(_1810_),
+ .Y(\Inst_Frame_Select_0.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__inv_2 _3831_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[27] ),
+ .Y(_1853_));
+ sky130_fd_sc_hd__or4_2 _3832_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[31] ),
+ .B(_1808_),
+ .C(\Config_inst.ConfigFSM_inst.FrameAddressRegister[28] ),
+ .D(_1853_),
+ .X(_1854_));
+ sky130_fd_sc_hd__or3_2 _3833_ (.A(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30),
+ .B(FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29),
+ .C(_1854_),
+ .X(_1855_));
+ sky130_fd_sc_hd__nor2_1 _3835_ (.A(_1806_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__nor2_1 _3836_ (.A(_1812_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__nor2_1 _3837_ (.A(_1814_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__nor2_1 _3838_ (.A(_1816_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__nor2_1 _3839_ (.A(_1818_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__nor2_1 _3841_ (.A(_1820_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__nor2_1 _3842_ (.A(_1823_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__nor2_1 _3843_ (.A(_1825_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__nor2_1 _3844_ (.A(_1827_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__nor2_1 _3845_ (.A(_1829_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__nor2_1 _3847_ (.A(_1831_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__nor2_1 _3848_ (.A(_1834_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__nor2_1 _3849_ (.A(_1836_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__nor2_1 _3850_ (.A(_1838_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__nor2_1 _3851_ (.A(_1840_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__nor2_1 _3853_ (.A(_1842_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__nor2_1 _3854_ (.A(_1845_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__nor2_1 _3855_ (.A(_1847_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__nor2_1 _3856_ (.A(_1849_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__nor2_1 _3857_ (.A(_1851_),
+ .B(_1855_),
+ .Y(\Inst_Frame_Select_1.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__inv_2 _3858_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[28] ),
+ .Y(_1860_));
+ sky130_fd_sc_hd__or4_4 _3859_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[31] ),
+ .B(_1808_),
+ .C(_1860_),
+ .D(\Config_inst.ConfigFSM_inst.FrameAddressRegister[27] ),
+ .X(_1861_));
+ sky130_fd_sc_hd__or3_2 _3860_ (.A(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30),
+ .B(FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29),
+ .C(_1861_),
+ .X(_1862_));
+ sky130_fd_sc_hd__nor2_1 _3862_ (.A(_1806_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__nor2_1 _3863_ (.A(_1812_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__nor2_1 _3864_ (.A(_1814_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__nor2_1 _3865_ (.A(_1816_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__nor2_1 _3866_ (.A(_1818_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__nor2_1 _3868_ (.A(_1820_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__nor2_1 _3869_ (.A(_1823_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__nor2_1 _3870_ (.A(_1825_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__nor2_1 _3871_ (.A(_1827_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__nor2_1 _3872_ (.A(_1829_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__nor2_1 _3874_ (.A(_1831_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__nor2_1 _3875_ (.A(_1834_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__nor2_1 _3876_ (.A(_1836_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__nor2_1 _3877_ (.A(_1838_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__nor2_1 _3878_ (.A(_1840_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__nor2_1 _3880_ (.A(_1842_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__nor2_1 _3881_ (.A(_1845_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__nor2_1 _3882_ (.A(_1847_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__nor2_1 _3883_ (.A(_1849_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__nor2_1 _3884_ (.A(_1851_),
+ .B(_1862_),
+ .Y(\Inst_Frame_Select_2.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__or4_2 _3885_ (.A(\Config_inst.ConfigFSM_inst.FrameAddressRegister[31] ),
+ .B(_1808_),
+ .C(_1860_),
+ .D(_1853_),
+ .X(_1867_));
+ sky130_fd_sc_hd__or3_2 _3886_ (.A(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30),
+ .B(FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29),
+ .C(_1867_),
+ .X(_1868_));
+ sky130_fd_sc_hd__nor2_1 _3888_ (.A(_1806_),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__nor2_1 _3889_ (.A(_1812_),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__nor2_1 _3890_ (.A(FE_OFN6_1814),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__nor2_1 _3891_ (.A(_1816_),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__nor2_1 _3892_ (.A(FE_OFN8_1818),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__nor2_1 _3894_ (.A(_1820_),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__nor2_1 _3895_ (.A(FE_OFN9_1823),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__nor2_1 _3896_ (.A(FE_OFN10_1825),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__nor2_1 _3897_ (.A(FE_OFN11_1827),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__nor2_1 _3898_ (.A(FE_OFN12_1829),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__nor2_1 _3900_ (.A(FE_OFN13_1831),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__nor2_1 _3901_ (.A(FE_OFN14_1834),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__nor2_1 _3902_ (.A(_1836_),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__nor2_1 _3903_ (.A(FE_OFN15_1838),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__nor2_1 _3904_ (.A(_1840_),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__nor2_1 _3906_ (.A(_1842_),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__nor2_1 _3907_ (.A(_1845_),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__nor2_1 _3908_ (.A(_1847_),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__nor2_1 _3909_ (.A(FE_OFN19_1849),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__nor2_1 _3910_ (.A(_1851_),
+ .B(_1868_),
+ .Y(\Inst_Frame_Select_3.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__inv_2 _3911_ (.A(FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29),
+ .Y(_1873_));
+ sky130_fd_sc_hd__or3_2 _3912_ (.A(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30),
+ .B(_1873_),
+ .C(_1809_),
+ .X(_1874_));
+ sky130_fd_sc_hd__nor2_1 _3914_ (.A(_1806_),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__nor2_1 _3915_ (.A(_1812_),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__nor2_1 _3916_ (.A(FE_OFN6_1814),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__nor2_1 _3917_ (.A(FE_OFN7_1816),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__nor2_1 _3918_ (.A(FE_OFN8_1818),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__nor2_1 _3920_ (.A(_1820_),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__nor2_1 _3921_ (.A(FE_OFN9_1823),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__nor2_1 _3922_ (.A(FE_OFN10_1825),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__nor2_1 _3923_ (.A(FE_OFN11_1827),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__nor2_1 _3924_ (.A(FE_OFN12_1829),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__nor2_1 _3926_ (.A(FE_OFN13_1831),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__nor2_1 _3927_ (.A(FE_OFN14_1834),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__nor2_1 _3928_ (.A(_1836_),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__nor2_1 _3929_ (.A(FE_OFN15_1838),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__nor2_1 _3930_ (.A(FE_OFN16_1840),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__nor2_1 _3932_ (.A(_1842_),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__nor2_1 _3933_ (.A(FE_OFN17_1845),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__nor2_1 _3934_ (.A(FE_OFN18_1847),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__nor2_1 _3935_ (.A(FE_OFN19_1849),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__nor2_1 _3936_ (.A(FE_OFN20_1851),
+ .B(_1874_),
+ .Y(\Inst_Frame_Select_4.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__or3_2 _3938_ (.A(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30),
+ .B(_1873_),
+ .C(_1854_),
+ .X(_1880_));
+ sky130_fd_sc_hd__nor2_1 _3940_ (.A(_1806_),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__nor2_1 _3942_ (.A(_1812_),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__nor2_1 _3944_ (.A(FE_OFN6_1814),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__nor2_1 _3946_ (.A(FE_OFN7_1816),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__nor2_1 _3948_ (.A(FE_OFN8_1818),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__nor2_1 _3951_ (.A(_1820_),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__nor2_1 _3953_ (.A(FE_OFN9_1823),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__nor2_1 _3955_ (.A(FE_OFN10_1825),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__nor2_1 _3957_ (.A(FE_OFN11_1827),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__nor2_1 _3959_ (.A(FE_OFN12_1829),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__nor2_1 _3962_ (.A(FE_OFN13_1831),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__nor2_1 _3964_ (.A(FE_OFN14_1834),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__nor2_1 _3966_ (.A(_1836_),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__nor2_1 _3968_ (.A(FE_OFN15_1838),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__nor2_1 _3970_ (.A(FE_OFN16_1840),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__nor2_1 _3973_ (.A(_1842_),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__nor2_1 _3975_ (.A(FE_OFN17_1845),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__nor2_1 _3977_ (.A(FE_OFN18_1847),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__nor2_1 _3979_ (.A(FE_OFN19_1849),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__nor2_1 _3981_ (.A(FE_OFN20_1851),
+ .B(_1880_),
+ .Y(\Inst_Frame_Select_5.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__or3_4 _3982_ (.A(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30),
+ .B(_1873_),
+ .C(_1861_),
+ .X(_1904_));
+ sky130_fd_sc_hd__nor2_1 _3984_ (.A(_1806_),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__nor2_1 _3985_ (.A(_1812_),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__nor2_1 _3986_ (.A(FE_OFN6_1814),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__nor2_1 _3987_ (.A(FE_OFN7_1816),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__nor2_1 _3988_ (.A(FE_OFN8_1818),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__nor2_1 _3990_ (.A(_1820_),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__nor2_1 _3991_ (.A(FE_OFN9_1823),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__nor2_1 _3992_ (.A(FE_OFN10_1825),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__nor2_1 _3993_ (.A(FE_OFN11_1827),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__nor2_1 _3994_ (.A(FE_OFN12_1829),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__nor2_1 _3996_ (.A(FE_OFN13_1831),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__nor2_1 _3997_ (.A(FE_OFN14_1834),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__nor2_1 _3998_ (.A(_1836_),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__nor2_1 _3999_ (.A(FE_OFN15_1838),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__nor2_1 _4000_ (.A(FE_OFN16_1840),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__nor2_1 _4002_ (.A(_1842_),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__nor2_1 _4003_ (.A(FE_OFN17_1845),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__nor2_1 _4004_ (.A(FE_OFN18_1847),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__nor2_1 _4005_ (.A(FE_OFN19_1849),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__nor2_1 _4006_ (.A(FE_OFN20_1851),
+ .B(_1904_),
+ .Y(\Inst_Frame_Select_6.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__or3_4 _4007_ (.A(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30),
+ .B(_1873_),
+ .C(_1867_),
+ .X(_1909_));
+ sky130_fd_sc_hd__nor2_1 _4009_ (.A(_1806_),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__nor2_1 _4010_ (.A(_1812_),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__nor2_1 _4011_ (.A(FE_OFN6_1814),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__nor2_1 _4012_ (.A(FE_OFN7_1816),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__nor2_1 _4013_ (.A(FE_OFN8_1818),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__nor2_1 _4015_ (.A(_1820_),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__nor2_1 _4016_ (.A(FE_OFN9_1823),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__nor2_1 _4017_ (.A(FE_OFN10_1825),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__nor2_1 _4018_ (.A(FE_OFN11_1827),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__nor2_1 _4019_ (.A(FE_OFN12_1829),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__nor2_1 _4021_ (.A(FE_OFN13_1831),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__nor2_1 _4022_ (.A(FE_OFN14_1834),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__nor2_1 _4023_ (.A(_1836_),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__nor2_1 _4024_ (.A(FE_OFN15_1838),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__nor2_1 _4025_ (.A(FE_OFN16_1840),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__nor2_1 _4027_ (.A(_1842_),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__nor2_1 _4028_ (.A(FE_OFN17_1845),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__nor2_1 _4029_ (.A(FE_OFN18_1847),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__nor2_1 _4030_ (.A(FE_OFN19_1849),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__nor2_1 _4031_ (.A(FE_OFN20_1851),
+ .B(_1909_),
+ .Y(\Inst_Frame_Select_7.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__inv_2 _4032_ (.A(FE_OFN180_Config_inst_ConfigFSM_inst_FrameAddressRegister_30),
+ .Y(_1914_));
+ sky130_fd_sc_hd__or3_2 _4033_ (.A(_1914_),
+ .B(FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29),
+ .C(_1809_),
+ .X(_1915_));
+ sky130_fd_sc_hd__nor2_1 _4035_ (.A(_1806_),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__nor2_1 _4036_ (.A(_1812_),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__nor2_1 _4037_ (.A(FE_OFN6_1814),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__nor2_1 _4038_ (.A(FE_OFN7_1816),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__nor2_1 _4039_ (.A(FE_OFN8_1818),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__nor2_1 _4041_ (.A(_1820_),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__nor2_1 _4042_ (.A(FE_OFN9_1823),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__nor2_1 _4043_ (.A(FE_OFN10_1825),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__nor2_1 _4044_ (.A(FE_OFN11_1827),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__nor2_1 _4045_ (.A(FE_OFN12_1829),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__nor2_1 _4047_ (.A(FE_OFN13_1831),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__nor2_1 _4048_ (.A(FE_OFN14_1834),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__nor2_1 _4049_ (.A(_1836_),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__nor2_1 _4050_ (.A(FE_OFN15_1838),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__nor2_1 _4051_ (.A(FE_OFN16_1840),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__nor2_1 _4053_ (.A(_1842_),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__nor2_1 _4054_ (.A(FE_OFN17_1845),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__nor2_1 _4055_ (.A(FE_OFN18_1847),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__nor2_1 _4056_ (.A(FE_OFN19_1849),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__nor2_1 _4057_ (.A(FE_OFN20_1851),
+ .B(FE_OFN21_1915),
+ .Y(\Inst_Frame_Select_8.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__or3_2 _4058_ (.A(_1914_),
+ .B(FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29),
+ .C(_1854_),
+ .X(_1920_));
+ sky130_fd_sc_hd__nor2_1 _4060_ (.A(_1806_),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__nor2_1 _4061_ (.A(_1812_),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__nor2_1 _4062_ (.A(FE_OFN6_1814),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__nor2_1 _4063_ (.A(FE_OFN7_1816),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__nor2_1 _4064_ (.A(FE_OFN8_1818),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__nor2_1 _4066_ (.A(_1820_),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__nor2_1 _4067_ (.A(FE_OFN9_1823),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__nor2_1 _4068_ (.A(FE_OFN10_1825),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__nor2_1 _4069_ (.A(FE_OFN11_1827),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__nor2_1 _4070_ (.A(FE_OFN12_1829),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__nor2_1 _4072_ (.A(FE_OFN13_1831),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__nor2_1 _4073_ (.A(FE_OFN14_1834),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__nor2_1 _4074_ (.A(_1836_),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__nor2_1 _4075_ (.A(FE_OFN15_1838),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__nor2_1 _4076_ (.A(FE_OFN16_1840),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__nor2_1 _4078_ (.A(_1842_),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__nor2_1 _4079_ (.A(FE_OFN17_1845),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__nor2_1 _4080_ (.A(FE_OFN18_1847),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__nor2_1 _4081_ (.A(FE_OFN19_1849),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__nor2_1 _4082_ (.A(FE_OFN20_1851),
+ .B(FE_OFN22_1920),
+ .Y(\Inst_Frame_Select_9.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__or3_2 _4083_ (.A(_1914_),
+ .B(FE_OFN179_Config_inst_ConfigFSM_inst_FrameAddressRegister_29),
+ .C(_1861_),
+ .X(_1925_));
+ sky130_fd_sc_hd__nor2_2 _4085_ (.A(_1806_),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[0] ));
+ sky130_fd_sc_hd__nor2_2 _4086_ (.A(_1812_),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[1] ));
+ sky130_fd_sc_hd__nor2_2 _4087_ (.A(FE_OFN6_1814),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[2] ));
+ sky130_fd_sc_hd__nor2_1 _4088_ (.A(FE_OFN7_1816),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[3] ));
+ sky130_fd_sc_hd__nor2_2 _4089_ (.A(FE_OFN8_1818),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[4] ));
+ sky130_fd_sc_hd__nor2_2 _4091_ (.A(_1820_),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[5] ));
+ sky130_fd_sc_hd__nor2_2 _4092_ (.A(FE_OFN9_1823),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[6] ));
+ sky130_fd_sc_hd__nor2_1 _4093_ (.A(FE_OFN10_1825),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[7] ));
+ sky130_fd_sc_hd__nor2_1 _4094_ (.A(FE_OFN11_1827),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[8] ));
+ sky130_fd_sc_hd__nor2_1 _4095_ (.A(FE_OFN12_1829),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[9] ));
+ sky130_fd_sc_hd__nor2_2 _4097_ (.A(FE_OFN13_1831),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[10] ));
+ sky130_fd_sc_hd__nor2_2 _4098_ (.A(FE_OFN14_1834),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[11] ));
+ sky130_fd_sc_hd__nor2_1 _4099_ (.A(_1836_),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[12] ));
+ sky130_fd_sc_hd__nor2_1 _4100_ (.A(FE_OFN15_1838),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[13] ));
+ sky130_fd_sc_hd__nor2_1 _4101_ (.A(FE_OFN16_1840),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[14] ));
+ sky130_fd_sc_hd__nor2_2 _4103_ (.A(_1842_),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[15] ));
+ sky130_fd_sc_hd__nor2_2 _4104_ (.A(FE_OFN17_1845),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[16] ));
+ sky130_fd_sc_hd__nor2_1 _4105_ (.A(FE_OFN18_1847),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[17] ));
+ sky130_fd_sc_hd__nor2_1 _4106_ (.A(FE_OFN19_1849),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[18] ));
+ sky130_fd_sc_hd__nor2_1 _4107_ (.A(FE_OFN20_1851),
+ .B(FE_OFN23_1925),
+ .Y(\Inst_Frame_Select_10.FrameStrobe_O[19] ));
+ sky130_fd_sc_hd__and2b_1 _4112_ (.A_N(\Config_inst.Inst_bitbang.old_local_strobe ),
+ .B(\Config_inst.Inst_bitbang.local_strobe ),
+ .X(_1932_));
+ sky130_fd_sc_hd__a2bb2oi_2 _4114_ (.A1_N(\Config_inst.INST_config_UART.ReceiveLED ),
+ .A2_N(\Config_inst.BitBangWriteStrobe ),
+ .B1(\Config_inst.INST_config_UART.ReceiveLED ),
+ .B2(\Config_inst.BitBangWriteStrobe ),
+ .Y(FE_OFN61_io_out_6));
+ sky130_fd_sc_hd__or2_2 _4115_ (.A(\Config_inst.INST_config_UART.blink[0] ),
+ .B(\Config_inst.INST_config_UART.blink[1] ),
+ .X(_1933_));
+ sky130_fd_sc_hd__a21bo_2 _4116_ (.A1(\Config_inst.INST_config_UART.blink[0] ),
+ .A2(\Config_inst.INST_config_UART.blink[1] ),
+ .B1_N(_1933_),
+ .X(_0055_));
+ sky130_fd_sc_hd__or2_2 _4117_ (.A(\Config_inst.INST_config_UART.blink[2] ),
+ .B(_1933_),
+ .X(_1934_));
+ sky130_fd_sc_hd__a21bo_2 _4118_ (.A1(\Config_inst.INST_config_UART.blink[2] ),
+ .A2(_1933_),
+ .B1_N(_1934_),
+ .X(_0059_));
+ sky130_fd_sc_hd__or2_2 _4119_ (.A(\Config_inst.INST_config_UART.blink[3] ),
+ .B(_1934_),
+ .X(_1935_));
+ sky130_fd_sc_hd__a21bo_2 _4120_ (.A1(\Config_inst.INST_config_UART.blink[3] ),
+ .A2(_1934_),
+ .B1_N(_1935_),
+ .X(_0060_));
+ sky130_fd_sc_hd__or2_2 _4121_ (.A(\Config_inst.INST_config_UART.blink[4] ),
+ .B(_1935_),
+ .X(_1936_));
+ sky130_fd_sc_hd__a21bo_2 _4122_ (.A1(\Config_inst.INST_config_UART.blink[4] ),
+ .A2(_1935_),
+ .B1_N(_1936_),
+ .X(_0061_));
+ sky130_fd_sc_hd__or3_1 _4123_ (.A(\Config_inst.INST_config_UART.blink[4] ),
+ .B(\Config_inst.INST_config_UART.blink[5] ),
+ .C(_1935_),
+ .X(_1937_));
+ sky130_fd_sc_hd__a21bo_2 _4124_ (.A1(\Config_inst.INST_config_UART.blink[5] ),
+ .A2(_1936_),
+ .B1_N(_1937_),
+ .X(_0062_));
+ sky130_fd_sc_hd__or2_2 _4125_ (.A(\Config_inst.INST_config_UART.blink[6] ),
+ .B(_1937_),
+ .X(_1938_));
+ sky130_fd_sc_hd__a21bo_2 _4126_ (.A1(\Config_inst.INST_config_UART.blink[6] ),
+ .A2(_1937_),
+ .B1_N(_1938_),
+ .X(_0063_));
+ sky130_fd_sc_hd__or2_2 _4127_ (.A(\Config_inst.INST_config_UART.blink[7] ),
+ .B(_1938_),
+ .X(_1939_));
+ sky130_fd_sc_hd__a21bo_2 _4128_ (.A1(\Config_inst.INST_config_UART.blink[7] ),
+ .A2(_1938_),
+ .B1_N(_1939_),
+ .X(_0064_));
+ sky130_fd_sc_hd__nor2_1 _4129_ (.A(\Config_inst.INST_config_UART.blink[8] ),
+ .B(_1939_),
+ .Y(_1940_));
+ sky130_fd_sc_hd__a21o_1 _4130_ (.A1(\Config_inst.INST_config_UART.blink[8] ),
+ .A2(_1939_),
+ .B1(_1940_),
+ .X(_0065_));
+ sky130_fd_sc_hd__inv_2 _4131_ (.A(\Config_inst.INST_config_UART.blink[9] ),
+ .Y(_1941_));
+ sky130_fd_sc_hd__or3_1 _4132_ (.A(\Config_inst.INST_config_UART.blink[8] ),
+ .B(\Config_inst.INST_config_UART.blink[9] ),
+ .C(_1939_),
+ .X(_1942_));
+ sky130_fd_sc_hd__o21ai_1 _4133_ (.A1(_1941_),
+ .A2(_1940_),
+ .B1(_1942_),
+ .Y(_0066_));
+ sky130_fd_sc_hd__or2_2 _4134_ (.A(\Config_inst.INST_config_UART.blink[10] ),
+ .B(_1942_),
+ .X(_1943_));
+ sky130_fd_sc_hd__a21bo_2 _4135_ (.A1(\Config_inst.INST_config_UART.blink[10] ),
+ .A2(_1942_),
+ .B1_N(_1943_),
+ .X(_0045_));
+ sky130_fd_sc_hd__or2_2 _4136_ (.A(\Config_inst.INST_config_UART.blink[10] ),
+ .B(\Config_inst.INST_config_UART.blink[11] ),
+ .X(_1944_));
+ sky130_fd_sc_hd__or4_1 _4137_ (.A(\Config_inst.INST_config_UART.blink[8] ),
+ .B(\Config_inst.INST_config_UART.blink[9] ),
+ .C(_1944_),
+ .D(_1939_),
+ .X(_1945_));
+ sky130_fd_sc_hd__a21bo_2 _4138_ (.A1(\Config_inst.INST_config_UART.blink[11] ),
+ .A2(_1943_),
+ .B1_N(_1945_),
+ .X(_0046_));
+ sky130_fd_sc_hd__or2_2 _4139_ (.A(\Config_inst.INST_config_UART.blink[12] ),
+ .B(_1945_),
+ .X(_1946_));
+ sky130_fd_sc_hd__a21bo_2 _4140_ (.A1(\Config_inst.INST_config_UART.blink[12] ),
+ .A2(_1945_),
+ .B1_N(_1946_),
+ .X(_0047_));
+ sky130_fd_sc_hd__or3_1 _4141_ (.A(\Config_inst.INST_config_UART.blink[12] ),
+ .B(\Config_inst.INST_config_UART.blink[13] ),
+ .C(_1945_),
+ .X(_1947_));
+ sky130_fd_sc_hd__a21bo_2 _4142_ (.A1(\Config_inst.INST_config_UART.blink[13] ),
+ .A2(_1946_),
+ .B1_N(_1947_),
+ .X(_0048_));
+ sky130_fd_sc_hd__or2_2 _4143_ (.A(\Config_inst.INST_config_UART.blink[14] ),
+ .B(_1947_),
+ .X(_1948_));
+ sky130_fd_sc_hd__a21bo_2 _4144_ (.A1(\Config_inst.INST_config_UART.blink[14] ),
+ .A2(_1947_),
+ .B1_N(_1948_),
+ .X(_0049_));
+ sky130_fd_sc_hd__or3_1 _4145_ (.A(\Config_inst.INST_config_UART.blink[14] ),
+ .B(\Config_inst.INST_config_UART.blink[15] ),
+ .C(_1947_),
+ .X(_1949_));
+ sky130_fd_sc_hd__a21bo_2 _4146_ (.A1(\Config_inst.INST_config_UART.blink[15] ),
+ .A2(_1948_),
+ .B1_N(_1949_),
+ .X(_0050_));
+ sky130_fd_sc_hd__or2_2 _4147_ (.A(\Config_inst.INST_config_UART.blink[16] ),
+ .B(_1949_),
+ .X(_1950_));
+ sky130_fd_sc_hd__a21bo_2 _4148_ (.A1(\Config_inst.INST_config_UART.blink[16] ),
+ .A2(_1949_),
+ .B1_N(_1950_),
+ .X(_0051_));
+ sky130_fd_sc_hd__or3_1 _4149_ (.A(\Config_inst.INST_config_UART.blink[16] ),
+ .B(\Config_inst.INST_config_UART.blink[17] ),
+ .C(_1949_),
+ .X(_1951_));
+ sky130_fd_sc_hd__a21bo_2 _4150_ (.A1(\Config_inst.INST_config_UART.blink[17] ),
+ .A2(_1950_),
+ .B1_N(_1951_),
+ .X(_0052_));
+ sky130_fd_sc_hd__or2_2 _4151_ (.A(\Config_inst.INST_config_UART.blink[18] ),
+ .B(_1951_),
+ .X(_1952_));
+ sky130_fd_sc_hd__a21bo_2 _4152_ (.A1(\Config_inst.INST_config_UART.blink[18] ),
+ .A2(_1951_),
+ .B1_N(_1952_),
+ .X(_0053_));
+ sky130_fd_sc_hd__or2_2 _4153_ (.A(\Config_inst.INST_config_UART.blink[19] ),
+ .B(_1952_),
+ .X(_1953_));
+ sky130_fd_sc_hd__a21bo_2 _4154_ (.A1(\Config_inst.INST_config_UART.blink[19] ),
+ .A2(_1952_),
+ .B1_N(_1953_),
+ .X(_0054_));
+ sky130_fd_sc_hd__a2bb2o_1 _4155_ (.A1_N(\Config_inst.INST_config_UART.blink[20] ),
+ .A2_N(_1953_),
+ .B1(\Config_inst.INST_config_UART.blink[20] ),
+ .B2(_1953_),
+ .X(_0056_));
+ sky130_fd_sc_hd__or3_1 _4156_ (.A(\Config_inst.INST_config_UART.blink[20] ),
+ .B(\Config_inst.INST_config_UART.blink[21] ),
+ .C(_1953_),
+ .X(_1954_));
+ sky130_fd_sc_hd__inv_2 _4157_ (.A(_1954_),
+ .Y(_1955_));
+ sky130_fd_sc_hd__o21a_1 _4158_ (.A1(\Config_inst.INST_config_UART.blink[20] ),
+ .A2(_1953_),
+ .B1(\Config_inst.INST_config_UART.blink[21] ),
+ .X(_1956_));
+ sky130_fd_sc_hd__or2_2 _4159_ (.A(_1955_),
+ .B(_1956_),
+ .X(_1957_));
+ sky130_fd_sc_hd__inv_2 _4161_ (.A(\Config_inst.INST_config_UART.blink[22] ),
+ .Y(_1958_));
+ sky130_fd_sc_hd__o22a_1 _4162_ (.A1(\Config_inst.INST_config_UART.blink[22] ),
+ .A2(_1955_),
+ .B1(_1958_),
+ .B2(_1954_),
+ .X(_0058_));
+ sky130_fd_sc_hd__o21a_1 _4163_ (.A1(\Config_inst.INST_config_UART.TimeToSendCounter[13] ),
+ .A2(_0901_),
+ .B1(\Config_inst.INST_config_UART.TimeToSendCounter[14] ),
+ .X(_1959_));
+ sky130_fd_sc_hd__or2_2 _4164_ (.A(_0912_),
+ .B(_1959_),
+ .X(_1960_));
+ sky130_fd_sc_hd__conb_1 _4166_ (.HI(FE_OFN60_io_oeb_0));
+ sky130_fd_sc_hd__conb_1 _4167_ (.HI(FE_OFN59_io_oeb_1));
+ sky130_fd_sc_hd__conb_1 _4168_ (.HI(FE_OFN58_io_oeb_2));
+ sky130_fd_sc_hd__conb_1 _4169_ (.HI(FE_OFN57_io_oeb_3));
+ sky130_fd_sc_hd__conb_1 _4170_ (.HI(FE_OFN56_io_oeb_4));
+ sky130_fd_sc_hd__conb_1 _4171_ (.HI(FE_OFN55_io_oeb_5));
+ sky130_fd_sc_hd__conb_1 _4172_ (.LO(_1996_));
+ sky130_fd_sc_hd__conb_1 _4173_ (.LO(FE_OFN54_io_oeb_6));
+ sky130_fd_sc_hd__conb_1 _4174_ (.LO(FE_OFN69_io_out_0));
+ sky130_fd_sc_hd__conb_1 _4175_ (.LO(FE_OFN68_io_out_1));
+ sky130_fd_sc_hd__conb_1 _4176_ (.LO(FE_OFN67_io_out_2));
+ sky130_fd_sc_hd__conb_1 _4177_ (.LO(FE_OFN66_io_out_3));
+ sky130_fd_sc_hd__conb_1 _4178_ (.LO(FE_OFN65_io_out_4));
+ sky130_fd_sc_hd__conb_1 _4179_ (.LO(FE_OFN64_io_out_5));
+ sky130_fd_sc_hd__conb_1 _4180_ (.LO(FE_OFN93_wbs_dat_o_16));
+ sky130_fd_sc_hd__conb_1 _4181_ (.LO(FE_OFN92_wbs_dat_o_17));
+ sky130_fd_sc_hd__conb_1 _4182_ (.LO(FE_OFN91_wbs_dat_o_18));
+ sky130_fd_sc_hd__conb_1 _4183_ (.LO(FE_OFN90_wbs_dat_o_19));
+ sky130_fd_sc_hd__conb_1 _4184_ (.LO(FE_OFN89_wbs_dat_o_20));
+ sky130_fd_sc_hd__conb_1 _4185_ (.LO(FE_OFN88_wbs_dat_o_21));
+ sky130_fd_sc_hd__conb_1 _4186_ (.LO(FE_OFN87_wbs_dat_o_22));
+ sky130_fd_sc_hd__conb_1 _4187_ (.LO(FE_OFN86_wbs_dat_o_23));
+ sky130_fd_sc_hd__conb_1 _4188_ (.LO(FE_OFN85_wbs_dat_o_24));
+ sky130_fd_sc_hd__conb_1 _4189_ (.LO(FE_OFN84_wbs_dat_o_25));
+ sky130_fd_sc_hd__conb_1 _4190_ (.LO(FE_OFN83_wbs_dat_o_26));
+ sky130_fd_sc_hd__conb_1 _4191_ (.LO(FE_OFN82_wbs_dat_o_27));
+ sky130_fd_sc_hd__conb_1 _4192_ (.LO(FE_OFN81_wbs_dat_o_28));
+ sky130_fd_sc_hd__conb_1 _4193_ (.LO(FE_OFN80_wbs_dat_o_29));
+ sky130_fd_sc_hd__conb_1 _4194_ (.LO(FE_OFN79_wbs_dat_o_30));
+ sky130_fd_sc_hd__conb_1 _4195_ (.LO(FE_OFN78_wbs_dat_o_31));
+ sky130_fd_sc_hd__conb_1 _4196_ (.LO(FE_OFN94_wbs_dat_o_15));
+ sky130_fd_sc_hd__conb_1 _4197_ (.LO(FE_OFN95_wbs_dat_o_14));
+ sky130_fd_sc_hd__conb_1 _4198_ (.LO(FE_OFN96_wbs_dat_o_13));
+ sky130_fd_sc_hd__conb_1 _4199_ (.LO(FE_OFN97_wbs_dat_o_12));
+ sky130_fd_sc_hd__conb_1 _4200_ (.LO(FE_OFN98_wbs_dat_o_11));
+ sky130_fd_sc_hd__conb_1 _4201_ (.LO(FE_OFN99_wbs_dat_o_10));
+ sky130_fd_sc_hd__conb_1 _4202_ (.LO(FE_OFN100_wbs_dat_o_9));
+ sky130_fd_sc_hd__conb_1 _4203_ (.LO(FE_OFN101_wbs_dat_o_8));
+ sky130_fd_sc_hd__conb_1 _4204_ (.LO(FE_OFN102_wbs_dat_o_7));
+ sky130_fd_sc_hd__conb_1 _4205_ (.LO(FE_OFN103_wbs_dat_o_6));
+ sky130_fd_sc_hd__conb_1 _4206_ (.LO(FE_OFN104_wbs_dat_o_5));
+ sky130_fd_sc_hd__conb_1 _4207_ (.LO(FE_OFN105_wbs_dat_o_4));
+ sky130_fd_sc_hd__conb_1 _4208_ (.LO(FE_OFN106_wbs_dat_o_3));
+ sky130_fd_sc_hd__conb_1 _4209_ (.LO(FE_OFN107_wbs_dat_o_2));
+ sky130_fd_sc_hd__conb_1 _4210_ (.LO(FE_OFN108_wbs_dat_o_1));
+ sky130_fd_sc_hd__conb_1 _4211_ (.LO(FE_OFN109_wbs_dat_o_0));
+ sky130_fd_sc_hd__mux2_1 _4298_ (.A0(_1161_),
+ .A1(_0020_),
+ .S(\Config_inst.Command[7] ),
+ .X(_0003_));
+ sky130_fd_sc_hd__mux2_1 _4299_ (.A0(\Config_inst.INST_config_UART.LocalWriteStrobe ),
+ .A1(\Config_inst.INST_config_UART.HexWriteStrobe ),
+ .S(\Config_inst.Command[7] ),
+ .X(_1961_));
+ sky130_fd_sc_hd__mux2_1 _4300_ (.A0(_0028_),
+ .A1(_1565_),
+ .S(\Config_inst.Command[7] ),
+ .X(_0029_));
+ sky130_fd_sc_hd__mux2_1 _4301_ (.A0(_0030_),
+ .A1(_0024_),
+ .S(\Config_inst.Command[7] ),
+ .X(_0031_));
+ sky130_fd_sc_hd__mux2_1 _4302_ (.A0(_1793_),
+ .A1(_0017_),
+ .S(_0018_),
+ .X(_0019_));
+ sky130_fd_sc_hd__mux2_1 _4303_ (.A0(_0032_),
+ .A1(_1169_),
+ .S(\Config_inst.Command[7] ),
+ .X(_0033_));
+ sky130_fd_sc_hd__mux2_1 _4304_ (.A0(\Config_inst.INST_config_UART.ReceivedWord[4] ),
+ .A1(\Config_inst.INST_config_UART.HighReg[0] ),
+ .S(\Config_inst.Command[7] ),
+ .X(_0034_));
+ sky130_fd_sc_hd__mux2_1 _4305_ (.A0(\Config_inst.INST_config_UART.ReceivedWord[6] ),
+ .A1(\Config_inst.INST_config_UART.HighReg[2] ),
+ .S(\Config_inst.Command[7] ),
+ .X(_0036_));
+ sky130_fd_sc_hd__mux2_1 _4306_ (.A0(_0026_),
+ .A1(_0023_),
+ .S(\Config_inst.Command[7] ),
+ .X(_0027_));
+ sky130_fd_sc_hd__mux2_1 _4307_ (.A0(\Config_inst.INST_config_UART.ReceivedWord[7] ),
+ .A1(\Config_inst.INST_config_UART.HighReg[3] ),
+ .S(\Config_inst.Command[7] ),
+ .X(_0037_));
+ sky130_fd_sc_hd__mux2_1 _4308_ (.A0(_0042_),
+ .A1(_0043_),
+ .S(_1133_),
+ .X(_0012_));
+ sky130_fd_sc_hd__mux2_1 _4309_ (.A0(_1655_),
+ .A1(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .S(_1133_),
+ .X(_0013_));
+ sky130_fd_sc_hd__mux2_1 _4310_ (.A0(_1651_),
+ .A1(FE_OFN27_Config_inst_INST_config_UART_RxLocal),
+ .S(_1133_),
+ .X(_0014_));
+ sky130_fd_sc_hd__mux2_1 _4311_ (.A0(_0041_),
+ .A1(_0043_),
+ .S(_1133_),
+ .X(_0015_));
+ sky130_fd_sc_hd__mux2_1 _4312_ (.A0(_1792_),
+ .A1(\Config_inst.BitBangWriteStrobe ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1962_));
+ sky130_fd_sc_hd__mux2_1 _4313_ (.A0(_1962_),
+ .A1(\Config_inst.INST_config_UART.WriteStrobe ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(_0011_));
+ sky130_fd_sc_hd__mux2_1 _4314_ (.A0(\Config_inst.SelfWriteData[0] ),
+ .A1(\Config_inst.BitBangWriteData[0] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1995_));
+ sky130_fd_sc_hd__mux2_4 _4315_ (.A0(_1995_),
+ .A1(\Config_inst.INST_config_UART.WriteData[0] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[0] ));
+ sky130_fd_sc_hd__mux2_1 _4316_ (.A0(\Config_inst.SelfWriteData[1] ),
+ .A1(\Config_inst.BitBangWriteData[1] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1963_));
+ sky130_fd_sc_hd__mux2_1 _4317_ (.A0(_1963_),
+ .A1(\Config_inst.INST_config_UART.WriteData[1] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[1] ));
+ sky130_fd_sc_hd__mux2_1 _4318_ (.A0(\Config_inst.SelfWriteData[2] ),
+ .A1(\Config_inst.BitBangWriteData[2] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1964_));
+ sky130_fd_sc_hd__mux2_4 _4319_ (.A0(_1964_),
+ .A1(\Config_inst.INST_config_UART.WriteData[2] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[2] ));
+ sky130_fd_sc_hd__mux2_1 _4320_ (.A0(\Config_inst.SelfWriteData[3] ),
+ .A1(\Config_inst.BitBangWriteData[3] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1965_));
+ sky130_fd_sc_hd__mux2_4 _4321_ (.A0(_1965_),
+ .A1(\Config_inst.INST_config_UART.WriteData[3] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[3] ));
+ sky130_fd_sc_hd__mux2_1 _4322_ (.A0(\Config_inst.SelfWriteData[4] ),
+ .A1(\Config_inst.BitBangWriteData[4] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1994_));
+ sky130_fd_sc_hd__mux2_4 _4323_ (.A0(_1994_),
+ .A1(\Config_inst.INST_config_UART.WriteData[4] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[4] ));
+ sky130_fd_sc_hd__mux2_1 _4324_ (.A0(\Config_inst.SelfWriteData[5] ),
+ .A1(\Config_inst.BitBangWriteData[5] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1993_));
+ sky130_fd_sc_hd__mux2_4 _4325_ (.A0(_1993_),
+ .A1(\Config_inst.INST_config_UART.WriteData[5] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[5] ));
+ sky130_fd_sc_hd__mux2_1 _4326_ (.A0(\Config_inst.SelfWriteData[6] ),
+ .A1(\Config_inst.BitBangWriteData[6] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1966_));
+ sky130_fd_sc_hd__mux2_4 _4327_ (.A0(_1966_),
+ .A1(\Config_inst.INST_config_UART.WriteData[6] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[6] ));
+ sky130_fd_sc_hd__mux2_1 _4328_ (.A0(\Config_inst.SelfWriteData[7] ),
+ .A1(\Config_inst.BitBangWriteData[7] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1992_));
+ sky130_fd_sc_hd__mux2_2 _4329_ (.A0(_1992_),
+ .A1(\Config_inst.INST_config_UART.WriteData[7] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[7] ));
+ sky130_fd_sc_hd__mux2_1 _4330_ (.A0(\Config_inst.SelfWriteData[8] ),
+ .A1(\Config_inst.BitBangWriteData[8] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1967_));
+ sky130_fd_sc_hd__mux2_2 _4331_ (.A0(_1967_),
+ .A1(\Config_inst.INST_config_UART.WriteData[8] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[8] ));
+ sky130_fd_sc_hd__mux2_1 _4332_ (.A0(\Config_inst.SelfWriteData[9] ),
+ .A1(\Config_inst.BitBangWriteData[9] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1991_));
+ sky130_fd_sc_hd__mux2_4 _4333_ (.A0(_1991_),
+ .A1(\Config_inst.INST_config_UART.WriteData[9] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[9] ));
+ sky130_fd_sc_hd__mux2_1 _4334_ (.A0(\Config_inst.SelfWriteData[10] ),
+ .A1(\Config_inst.BitBangWriteData[10] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1968_));
+ sky130_fd_sc_hd__mux2_4 _4335_ (.A0(_1968_),
+ .A1(\Config_inst.INST_config_UART.WriteData[10] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[10] ));
+ sky130_fd_sc_hd__mux2_1 _4336_ (.A0(\Config_inst.SelfWriteData[11] ),
+ .A1(\Config_inst.BitBangWriteData[11] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1990_));
+ sky130_fd_sc_hd__mux2_4 _4337_ (.A0(_1990_),
+ .A1(\Config_inst.INST_config_UART.WriteData[11] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[11] ));
+ sky130_fd_sc_hd__mux2_1 _4338_ (.A0(\Config_inst.SelfWriteData[12] ),
+ .A1(\Config_inst.BitBangWriteData[12] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1989_));
+ sky130_fd_sc_hd__mux2_2 _4339_ (.A0(_1989_),
+ .A1(\Config_inst.INST_config_UART.WriteData[12] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[12] ));
+ sky130_fd_sc_hd__mux2_1 _4340_ (.A0(\Config_inst.SelfWriteData[13] ),
+ .A1(\Config_inst.BitBangWriteData[13] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1988_));
+ sky130_fd_sc_hd__mux2_4 _4341_ (.A0(_1988_),
+ .A1(\Config_inst.INST_config_UART.WriteData[13] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[13] ));
+ sky130_fd_sc_hd__mux2_1 _4342_ (.A0(\Config_inst.SelfWriteData[14] ),
+ .A1(\Config_inst.BitBangWriteData[14] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1987_));
+ sky130_fd_sc_hd__mux2_2 _4343_ (.A0(_1987_),
+ .A1(\Config_inst.INST_config_UART.WriteData[14] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[14] ));
+ sky130_fd_sc_hd__mux2_1 _4344_ (.A0(\Config_inst.SelfWriteData[15] ),
+ .A1(\Config_inst.BitBangWriteData[15] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1986_));
+ sky130_fd_sc_hd__mux2_4 _4345_ (.A0(_1986_),
+ .A1(\Config_inst.INST_config_UART.WriteData[15] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[15] ));
+ sky130_fd_sc_hd__mux2_1 _4346_ (.A0(\Config_inst.SelfWriteData[16] ),
+ .A1(\Config_inst.BitBangWriteData[16] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1969_));
+ sky130_fd_sc_hd__mux2_2 _4347_ (.A0(_1969_),
+ .A1(\Config_inst.INST_config_UART.WriteData[16] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[16] ));
+ sky130_fd_sc_hd__mux2_1 _4348_ (.A0(\Config_inst.SelfWriteData[17] ),
+ .A1(\Config_inst.BitBangWriteData[17] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1970_));
+ sky130_fd_sc_hd__mux2_2 _4349_ (.A0(_1970_),
+ .A1(\Config_inst.INST_config_UART.WriteData[17] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[17] ));
+ sky130_fd_sc_hd__mux2_1 _4350_ (.A0(\Config_inst.SelfWriteData[18] ),
+ .A1(\Config_inst.BitBangWriteData[18] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1971_));
+ sky130_fd_sc_hd__mux2_2 _4351_ (.A0(_1971_),
+ .A1(\Config_inst.INST_config_UART.WriteData[18] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[18] ));
+ sky130_fd_sc_hd__mux2_1 _4352_ (.A0(\Config_inst.SelfWriteData[19] ),
+ .A1(\Config_inst.BitBangWriteData[19] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1972_));
+ sky130_fd_sc_hd__mux2_2 _4353_ (.A0(_1972_),
+ .A1(\Config_inst.INST_config_UART.WriteData[19] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[19] ));
+ sky130_fd_sc_hd__mux2_1 _4354_ (.A0(\Config_inst.SelfWriteData[20] ),
+ .A1(\Config_inst.BitBangWriteData[20] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1977_));
+ sky130_fd_sc_hd__mux2_4 _4355_ (.A0(_1977_),
+ .A1(\Config_inst.INST_config_UART.WriteData[20] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[20] ));
+ sky130_fd_sc_hd__mux2_1 _4356_ (.A0(\Config_inst.SelfWriteData[21] ),
+ .A1(\Config_inst.BitBangWriteData[21] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1985_));
+ sky130_fd_sc_hd__mux2_4 _4357_ (.A0(_1985_),
+ .A1(\Config_inst.INST_config_UART.WriteData[21] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[21] ));
+ sky130_fd_sc_hd__mux2_1 _4358_ (.A0(\Config_inst.SelfWriteData[22] ),
+ .A1(\Config_inst.BitBangWriteData[22] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1973_));
+ sky130_fd_sc_hd__mux2_4 _4359_ (.A0(_1973_),
+ .A1(\Config_inst.INST_config_UART.WriteData[22] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[22] ));
+ sky130_fd_sc_hd__mux2_1 _4360_ (.A0(\Config_inst.SelfWriteData[23] ),
+ .A1(\Config_inst.BitBangWriteData[23] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1984_));
+ sky130_fd_sc_hd__mux2_4 _4361_ (.A0(_1984_),
+ .A1(\Config_inst.INST_config_UART.WriteData[23] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[23] ));
+ sky130_fd_sc_hd__mux2_1 _4362_ (.A0(\Config_inst.SelfWriteData[24] ),
+ .A1(\Config_inst.BitBangWriteData[24] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1974_));
+ sky130_fd_sc_hd__mux2_1 _4363_ (.A0(_1974_),
+ .A1(\Config_inst.INST_config_UART.WriteData[24] ),
+ .S(FE_OFN75_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[24] ));
+ sky130_fd_sc_hd__mux2_1 _4364_ (.A0(\Config_inst.SelfWriteData[25] ),
+ .A1(\Config_inst.BitBangWriteData[25] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1983_));
+ sky130_fd_sc_hd__mux2_4 _4365_ (.A0(_1983_),
+ .A1(\Config_inst.INST_config_UART.WriteData[25] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[25] ));
+ sky130_fd_sc_hd__mux2_1 _4366_ (.A0(\Config_inst.SelfWriteData[26] ),
+ .A1(\Config_inst.BitBangWriteData[26] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1975_));
+ sky130_fd_sc_hd__mux2_4 _4367_ (.A0(_1975_),
+ .A1(\Config_inst.INST_config_UART.WriteData[26] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[26] ));
+ sky130_fd_sc_hd__mux2_1 _4368_ (.A0(\Config_inst.SelfWriteData[27] ),
+ .A1(\Config_inst.BitBangWriteData[27] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1982_));
+ sky130_fd_sc_hd__mux2_2 _4369_ (.A0(_1982_),
+ .A1(\Config_inst.INST_config_UART.WriteData[27] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[27] ));
+ sky130_fd_sc_hd__mux2_1 _4370_ (.A0(\Config_inst.SelfWriteData[28] ),
+ .A1(\Config_inst.BitBangWriteData[28] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1981_));
+ sky130_fd_sc_hd__mux2_2 _4371_ (.A0(_1981_),
+ .A1(\Config_inst.INST_config_UART.WriteData[28] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[28] ));
+ sky130_fd_sc_hd__mux2_1 _4372_ (.A0(\Config_inst.SelfWriteData[29] ),
+ .A1(\Config_inst.BitBangWriteData[29] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1980_));
+ sky130_fd_sc_hd__mux2_2 _4373_ (.A0(_1980_),
+ .A1(\Config_inst.INST_config_UART.WriteData[29] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[29] ));
+ sky130_fd_sc_hd__mux2_1 _4374_ (.A0(\Config_inst.SelfWriteData[30] ),
+ .A1(\Config_inst.BitBangWriteData[30] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1979_));
+ sky130_fd_sc_hd__mux2_2 _4375_ (.A0(_1979_),
+ .A1(\Config_inst.INST_config_UART.WriteData[30] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[30] ));
+ sky130_fd_sc_hd__mux2_1 _4376_ (.A0(\Config_inst.SelfWriteData[31] ),
+ .A1(\Config_inst.BitBangWriteData[31] ),
+ .S(FE_OFN28_Config_inst_Inst_bitbang_active),
+ .X(_1978_));
+ sky130_fd_sc_hd__mux2_2 _4377_ (.A0(_1978_),
+ .A1(\Config_inst.INST_config_UART.WriteData[31] ),
+ .S(FE_OFN74_la_data_out_0),
+ .X(\Config_inst.ConfigFSM_inst.WriteData[31] ));
+ sky130_fd_sc_hd__mux2_1 _4378_ (.A0(\Config_inst.INST_config_UART.Data_Reg[0] ),
+ .A1(\Config_inst.INST_config_UART.HexData[0] ),
+ .S(\Config_inst.Command[7] ),
+ .X(\Config_inst.INST_config_UART.ReceivedByte[0] ));
+ sky130_fd_sc_hd__mux2_1 _4379_ (.A0(\Config_inst.INST_config_UART.Data_Reg[1] ),
+ .A1(\Config_inst.INST_config_UART.HexData[1] ),
+ .S(\Config_inst.Command[7] ),
+ .X(\Config_inst.INST_config_UART.ReceivedByte[1] ));
+ sky130_fd_sc_hd__mux2_1 _4380_ (.A0(\Config_inst.INST_config_UART.Data_Reg[2] ),
+ .A1(\Config_inst.INST_config_UART.HexData[2] ),
+ .S(\Config_inst.Command[7] ),
+ .X(\Config_inst.INST_config_UART.ReceivedByte[2] ));
+ sky130_fd_sc_hd__mux2_1 _4381_ (.A0(\Config_inst.INST_config_UART.Data_Reg[3] ),
+ .A1(\Config_inst.INST_config_UART.HexData[3] ),
+ .S(\Config_inst.Command[7] ),
+ .X(\Config_inst.INST_config_UART.ReceivedByte[3] ));
+ sky130_fd_sc_hd__mux2_1 _4382_ (.A0(\Config_inst.INST_config_UART.Data_Reg[4] ),
+ .A1(\Config_inst.INST_config_UART.HexData[4] ),
+ .S(\Config_inst.Command[7] ),
+ .X(\Config_inst.INST_config_UART.ReceivedByte[4] ));
+ sky130_fd_sc_hd__mux2_1 _4383_ (.A0(\Config_inst.INST_config_UART.Data_Reg[5] ),
+ .A1(\Config_inst.INST_config_UART.HexData[5] ),
+ .S(\Config_inst.Command[7] ),
+ .X(\Config_inst.INST_config_UART.ReceivedByte[5] ));
+ sky130_fd_sc_hd__mux2_1 _4384_ (.A0(\Config_inst.INST_config_UART.Data_Reg[6] ),
+ .A1(\Config_inst.INST_config_UART.HexData[6] ),
+ .S(\Config_inst.Command[7] ),
+ .X(\Config_inst.INST_config_UART.ReceivedByte[6] ));
+ sky130_fd_sc_hd__mux2_1 _4385_ (.A0(\Config_inst.INST_config_UART.Data_Reg[7] ),
+ .A1(\Config_inst.INST_config_UART.HexData[7] ),
+ .S(\Config_inst.Command[7] ),
+ .X(\Config_inst.INST_config_UART.ReceivedByte[7] ));
+ sky130_fd_sc_hd__mux2_1 _4386_ (.A0(\Config_inst.INST_config_UART.ReceivedWord[5] ),
+ .A1(\Config_inst.INST_config_UART.HighReg[1] ),
+ .S(\Config_inst.Command[7] ),
+ .X(_0035_));
+ sky130_fd_sc_hd__mux2_8 _4387_ (.A0(FE_OFN77_wb_clk_i),
+ .A1(user_clock2),
+ .S(io_in[2]),
+ .X(_1976_));
+ sky130_fd_sc_hd__mux2_8 _4388_ (.A0(io_in[0]),
+ .A1(CTS_36),
+ .S(io_in[1]),
+ .X(\Config_inst.CLK ));
+ sky130_fd_sc_hd__mux2_1 _4389_ (.A0(FE_OFN53_io_in_7),
+ .A1(\to_fabric_io_0.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y16_B_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y16_B_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4390_ (.A0(FE_OFN51_io_in_8),
+ .A1(\to_fabric_io_1.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y16_A_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y16_A_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4391_ (.A0(FE_OFN49_io_in_9),
+ .A1(\to_fabric_io_2.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y15_B_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y15_B_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4392_ (.A0(FE_OFN47_io_in_10),
+ .A1(\to_fabric_io_3.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y15_A_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y15_A_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4393_ (.A0(FE_OFN45_io_in_11),
+ .A1(\to_fabric_io_4.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y14_B_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y14_B_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4394_ (.A0(FE_OFN43_io_in_12),
+ .A1(\to_fabric_io_5.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y14_A_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y14_A_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4395_ (.A0(FE_OFN41_io_in_13),
+ .A1(\to_fabric_io_6.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y13_B_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y13_B_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4396_ (.A0(FE_OFN39_io_in_14),
+ .A1(\to_fabric_io_7.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y13_A_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y13_A_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4397_ (.A0(FE_OFN37_io_in_15),
+ .A1(\to_fabric_io_8.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y12_B_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y12_B_O_top ));
+ sky130_fd_sc_hd__mux2_4 _4398_ (.A0(io_in[16]),
+ .A1(\to_fabric_io_9.A1 ),
+ .S(FE_OFN183_FE_OFN70_la_data_out_4),
+ .X(\Inst_eFPGA.Tile_X0Y12_A_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4399_ (.A0(FE_OFN35_io_in_17),
+ .A1(\to_fabric_io_10.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y11_B_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y11_B_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4400_ (.A0(io_in[18]),
+ .A1(\to_fabric_io_11.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y11_A_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y11_A_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4401_ (.A0(io_in[19]),
+ .A1(\to_fabric_io_12.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y10_B_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y10_B_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4402_ (.A0(io_in[20]),
+ .A1(\to_fabric_io_13.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y10_A_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y10_A_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4403_ (.A0(io_in[21]),
+ .A1(\to_fabric_io_14.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y9_B_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y9_B_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4404_ (.A0(io_in[22]),
+ .A1(\to_fabric_io_15.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y9_A_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y9_A_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4405_ (.A0(io_in[23]),
+ .A1(\to_fabric_addr.A1 ),
+ .S(\Inst_eFPGA.Tile_X0Y8_B_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y8_B_O_top ));
+ sky130_fd_sc_hd__mux2_1 _4406_ (.A0(io_in[24]),
+ .A1(_1805_),
+ .S(\Inst_eFPGA.Tile_X0Y8_A_config_C_bit3 ),
+ .X(\Inst_eFPGA.Tile_X0Y8_A_O_top ));
+ sky130_fd_sc_hd__dfxtp_2 _4407_ (.CLK(CTS_9),
+ .D(latch_fabric_strobe),
+ .Q(fabric_strobe_reg1));
+ sky130_fd_sc_hd__dfxtp_2 _4408_ (.CLK(CTS_9),
+ .D(fabric_strobe_reg1),
+ .Q(fabric_strobe_reg2));
+ sky130_fd_sc_hd__dfxtp_2 _4409_ (.CLK(CTS_9),
+ .D(fabric_strobe_reg2),
+ .Q(fabric_strobe_reg3));
+ sky130_fd_sc_hd__dfxtp_2 _4410_ (.CLK(CTS_15),
+ .D(latch_config_strobe),
+ .Q(config_strobe_reg1));
+ sky130_fd_sc_hd__dfxtp_2 _4411_ (.CLK(CTS_15),
+ .D(config_strobe_reg1),
+ .Q(config_strobe_reg2));
+ sky130_fd_sc_hd__dfxtp_2 _4412_ (.CLK(CTS_15),
+ .D(config_strobe_reg2),
+ .Q(config_strobe_reg3));
+ sky130_fd_sc_hd__dfxtp_2 _4413_ (.CLK(CTS_1),
+ .D(_1804_),
+ .Q(\Config_inst.ConfigFSM_inst.LongFrameStrobe ));
+ sky130_fd_sc_hd__dfxtp_2 _4414_ (.CLK(CTS_1),
+ .D(\Config_inst.ConfigFSM_inst.FrameStrobe ),
+ .Q(\Config_inst.ConfigFSM_inst.oldFrameStrobe ));
+ sky130_fd_sc_hd__dfxtp_2 _4415_ (.CLK(CTS_10),
+ .D(_1094_),
+ .Q(\Config_inst.ConfigFSM_inst.old_reset ));
+ sky130_fd_sc_hd__dfxtp_2 _4416_ (.CLK(CTS_15),
+ .D(_1932_),
+ .Q(\Config_inst.BitBangWriteStrobe ));
+ sky130_fd_sc_hd__dfxtp_2 _4417_ (.CLK(CTS_15),
+ .D(_1127_),
+ .Q(\Config_inst.Inst_bitbang.local_strobe ));
+ sky130_fd_sc_hd__dfxtp_2 _4418_ (.CLK(CTS_15),
+ .D(\Config_inst.Inst_bitbang.local_strobe ),
+ .Q(\Config_inst.Inst_bitbang.old_local_strobe ));
+ sky130_fd_sc_hd__dfxtp_2 _4419_ (.CLK(CTS_18),
+ .D(io_in[4]),
+ .Q(\Config_inst.Inst_bitbang.s_data_sample[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4420_ (.CLK(CTS_18),
+ .D(\Config_inst.Inst_bitbang.s_data_sample[0] ),
+ .Q(\Config_inst.Inst_bitbang.s_data_sample[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4421_ (.CLK(CTS_30),
+ .D(FE_OFN32_Config_inst_Inst_bitbang_s_data_sample_1),
+ .Q(\Config_inst.Inst_bitbang.s_data_sample[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4422_ (.CLK(CTS_2),
+ .D(FE_OFN33_Config_inst_Inst_bitbang_s_data_sample_2),
+ .Q(\Config_inst.Inst_bitbang.s_data_sample[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4423_ (.CLK(CTS_18),
+ .D(io_in[3]),
+ .Q(\Config_inst.Inst_bitbang.s_clk_sample[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4424_ (.CLK(CTS_18),
+ .D(\Config_inst.Inst_bitbang.s_clk_sample[0] ),
+ .Q(\Config_inst.Inst_bitbang.s_clk_sample[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4425_ (.CLK(CTS_18),
+ .D(\Config_inst.Inst_bitbang.s_clk_sample[1] ),
+ .Q(\Config_inst.Inst_bitbang.s_clk_sample[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4426_ (.CLK(CTS_1),
+ .D(FE_OFN31_Config_inst_Inst_bitbang_s_clk_sample_2),
+ .Q(\Config_inst.Inst_bitbang.s_clk_sample[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4427_ (.CLK(CTS_15),
+ .D(_1056_),
+ .Q(\Config_inst.INST_config_UART.WriteStrobe ));
+ sky130_fd_sc_hd__dfxtp_2 _4428_ (.CLK(CTS_15),
+ .D(_1961_),
+ .Q(\Config_inst.INST_config_UART.ByteWriteStrobe ));
+ sky130_fd_sc_hd__dfxtp_2 _4429_ (.CLK(CTS_13),
+ .D(_0044_),
+ .Q(\Config_inst.INST_config_UART.blink[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4430_ (.CLK(CTS_13),
+ .D(_0055_),
+ .Q(\Config_inst.INST_config_UART.blink[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4431_ (.CLK(CTS_10),
+ .D(_0059_),
+ .Q(\Config_inst.INST_config_UART.blink[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4432_ (.CLK(CTS_13),
+ .D(_0060_),
+ .Q(\Config_inst.INST_config_UART.blink[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4433_ (.CLK(CTS_13),
+ .D(_0061_),
+ .Q(\Config_inst.INST_config_UART.blink[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4434_ (.CLK(CTS_13),
+ .D(_0062_),
+ .Q(\Config_inst.INST_config_UART.blink[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4435_ (.CLK(CTS_13),
+ .D(_0063_),
+ .Q(\Config_inst.INST_config_UART.blink[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4436_ (.CLK(CTS_10),
+ .D(_0064_),
+ .Q(\Config_inst.INST_config_UART.blink[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4437_ (.CLK(CTS_10),
+ .D(_0065_),
+ .Q(\Config_inst.INST_config_UART.blink[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4438_ (.CLK(CTS_13),
+ .D(_0066_),
+ .Q(\Config_inst.INST_config_UART.blink[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4439_ (.CLK(CTS_13),
+ .D(_0045_),
+ .Q(\Config_inst.INST_config_UART.blink[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4440_ (.CLK(CTS_10),
+ .D(_0046_),
+ .Q(\Config_inst.INST_config_UART.blink[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4441_ (.CLK(CTS_10),
+ .D(_0047_),
+ .Q(\Config_inst.INST_config_UART.blink[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4442_ (.CLK(CTS_10),
+ .D(_0048_),
+ .Q(\Config_inst.INST_config_UART.blink[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4443_ (.CLK(CTS_10),
+ .D(_0049_),
+ .Q(\Config_inst.INST_config_UART.blink[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4444_ (.CLK(CTS_10),
+ .D(_0050_),
+ .Q(\Config_inst.INST_config_UART.blink[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4445_ (.CLK(CTS_10),
+ .D(_0051_),
+ .Q(\Config_inst.INST_config_UART.blink[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4446_ (.CLK(CTS_10),
+ .D(_0052_),
+ .Q(\Config_inst.INST_config_UART.blink[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4447_ (.CLK(CTS_10),
+ .D(_0053_),
+ .Q(\Config_inst.INST_config_UART.blink[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4448_ (.CLK(CTS_10),
+ .D(_0054_),
+ .Q(\Config_inst.INST_config_UART.blink[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4449_ (.CLK(CTS_10),
+ .D(_0056_),
+ .Q(\Config_inst.INST_config_UART.blink[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4450_ (.CLK(CTS_10),
+ .D(_1957_),
+ .Q(\Config_inst.INST_config_UART.blink[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4451_ (.CLK(CTS_10),
+ .D(_0058_),
+ .Q(\Config_inst.INST_config_UART.blink[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4452_ (.CLK(CTS_18),
+ .D(io_in[5]),
+ .Q(\Config_inst.INST_config_UART.RxLocal ));
+ sky130_fd_sc_hd__dfxtp_2 _4453_ (.CLK(CTS_15),
+ .D(_0134_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4454_ (.CLK(CTS_15),
+ .D(_0135_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4455_ (.CLK(CTS_15),
+ .D(_0136_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4456_ (.CLK(CTS_15),
+ .D(_0137_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4457_ (.CLK(CTS_15),
+ .D(_0138_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4458_ (.CLK(CTS_15),
+ .D(_0139_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4459_ (.CLK(CTS_15),
+ .D(_0140_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4460_ (.CLK(CTS_15),
+ .D(_0141_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4461_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[0] ),
+ .Q(\Config_inst.SelfWriteData[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4462_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[1] ),
+ .Q(\Config_inst.SelfWriteData[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4463_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[2] ),
+ .Q(\Config_inst.SelfWriteData[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4464_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[3] ),
+ .Q(\Config_inst.SelfWriteData[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4465_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[4] ),
+ .Q(\Config_inst.SelfWriteData[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4466_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[5] ),
+ .Q(\Config_inst.SelfWriteData[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4467_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[6] ),
+ .Q(\Config_inst.SelfWriteData[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4468_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[7] ),
+ .Q(\Config_inst.SelfWriteData[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4469_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[8] ),
+ .Q(\Config_inst.SelfWriteData[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4470_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[9] ),
+ .Q(\Config_inst.SelfWriteData[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4471_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[10] ),
+ .Q(\Config_inst.SelfWriteData[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4472_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[11] ),
+ .Q(\Config_inst.SelfWriteData[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4473_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[12] ),
+ .Q(\Config_inst.SelfWriteData[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4474_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[13] ),
+ .Q(\Config_inst.SelfWriteData[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4475_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[14] ),
+ .Q(\Config_inst.SelfWriteData[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4476_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[15] ),
+ .Q(\Config_inst.SelfWriteData[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4477_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[16] ),
+ .Q(\Config_inst.SelfWriteData[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4478_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[17] ),
+ .Q(\Config_inst.SelfWriteData[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4479_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[18] ),
+ .Q(\Config_inst.SelfWriteData[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4480_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[19] ),
+ .Q(\Config_inst.SelfWriteData[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4481_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[20] ),
+ .Q(\Config_inst.SelfWriteData[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4482_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[21] ),
+ .Q(\Config_inst.SelfWriteData[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4483_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[22] ),
+ .Q(\Config_inst.SelfWriteData[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4484_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[23] ),
+ .Q(\Config_inst.SelfWriteData[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4485_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[24] ),
+ .Q(\Config_inst.SelfWriteData[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4486_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[25] ),
+ .Q(\Config_inst.SelfWriteData[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4487_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[26] ),
+ .Q(\Config_inst.SelfWriteData[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4488_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[27] ),
+ .Q(\Config_inst.SelfWriteData[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4489_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[28] ),
+ .Q(\Config_inst.SelfWriteData[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4490_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[29] ),
+ .Q(\Config_inst.SelfWriteData[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4491_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[30] ),
+ .Q(\Config_inst.SelfWriteData[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4492_ (.CLK(wb_clk_i),
+ .D(\Config_inst.SelfWriteData[31] ),
+ .Q(\Config_inst.SelfWriteData[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4493_ (.CLK(CTS_10),
+ .D(_1754_),
+ .Q(\Config_inst.INST_config_UART.ComState[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4494_ (.CLK(CTS_10),
+ .D(_0175_),
+ .Q(\Config_inst.INST_config_UART.ComState[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4495_ (.CLK(CTS_10),
+ .D(_0176_),
+ .Q(\Config_inst.INST_config_UART.ComState[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4496_ (.CLK(CTS_10),
+ .D(_0177_),
+ .Q(\Config_inst.INST_config_UART.ComState[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4497_ (.CLK(CTS_15),
+ .D(_0178_),
+ .Q(\Config_inst.INST_config_UART.Data_Reg[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4498_ (.CLK(CTS_15),
+ .D(_0179_),
+ .Q(\Config_inst.INST_config_UART.Data_Reg[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4499_ (.CLK(CTS_15),
+ .D(_0180_),
+ .Q(\Config_inst.INST_config_UART.Data_Reg[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4500_ (.CLK(CTS_15),
+ .D(_0181_),
+ .Q(\Config_inst.INST_config_UART.Data_Reg[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4501_ (.CLK(CTS_15),
+ .D(_0182_),
+ .Q(\Config_inst.INST_config_UART.Data_Reg[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4502_ (.CLK(CTS_15),
+ .D(_0183_),
+ .Q(\Config_inst.INST_config_UART.Data_Reg[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4503_ (.CLK(CTS_15),
+ .D(_0184_),
+ .Q(\Config_inst.INST_config_UART.Data_Reg[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4504_ (.CLK(CTS_15),
+ .D(_0185_),
+ .Q(\Config_inst.INST_config_UART.Data_Reg[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4505_ (.CLK(CTS_15),
+ .D(_0186_),
+ .Q(\Config_inst.Command[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4506_ (.CLK(CTS_15),
+ .D(_0187_),
+ .Q(\Config_inst.Command[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4507_ (.CLK(CTS_15),
+ .D(_0188_),
+ .Q(\Config_inst.Command[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4508_ (.CLK(CTS_15),
+ .D(_0189_),
+ .Q(\Config_inst.Command[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4509_ (.CLK(CTS_15),
+ .D(_0190_),
+ .Q(\Config_inst.Command[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4510_ (.CLK(CTS_15),
+ .D(_0191_),
+ .Q(\Config_inst.Command[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4511_ (.CLK(CTS_15),
+ .D(_0192_),
+ .Q(\Config_inst.Command[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4512_ (.CLK(CTS_15),
+ .D(_0193_),
+ .Q(\Config_inst.Command[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4513_ (.CLK(CTS_15),
+ .D(_0194_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4514_ (.CLK(CTS_15),
+ .D(_0195_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4515_ (.CLK(CTS_15),
+ .D(_0196_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4516_ (.CLK(CTS_15),
+ .D(_0197_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4517_ (.CLK(CTS_15),
+ .D(_0198_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4518_ (.CLK(CTS_15),
+ .D(_0199_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4519_ (.CLK(CTS_15),
+ .D(_0200_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4520_ (.CLK(CTS_15),
+ .D(_0201_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4521_ (.CLK(CTS_13),
+ .D(_0202_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4522_ (.CLK(CTS_13),
+ .D(_0203_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4523_ (.CLK(CTS_13),
+ .D(_0204_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4524_ (.CLK(CTS_13),
+ .D(_0205_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4525_ (.CLK(CTS_13),
+ .D(_0206_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4526_ (.CLK(CTS_13),
+ .D(_0207_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4527_ (.CLK(CTS_13),
+ .D(_0208_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4528_ (.CLK(CTS_13),
+ .D(_0209_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4529_ (.CLK(CTS_13),
+ .D(_0210_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4530_ (.CLK(CTS_13),
+ .D(_0211_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4531_ (.CLK(CTS_13),
+ .D(_0212_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4532_ (.CLK(CTS_13),
+ .D(_0213_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4533_ (.CLK(CTS_13),
+ .D(_0214_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4534_ (.CLK(CTS_13),
+ .D(_0215_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4535_ (.CLK(CTS_13),
+ .D(_0216_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4536_ (.CLK(CTS_13),
+ .D(_0217_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4537_ (.CLK(CTS_13),
+ .D(_0218_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4538_ (.CLK(CTS_13),
+ .D(_0219_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4539_ (.CLK(CTS_13),
+ .D(_0220_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4540_ (.CLK(CTS_13),
+ .D(_0221_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4541_ (.CLK(CTS_13),
+ .D(_0222_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4542_ (.CLK(CTS_13),
+ .D(_0223_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4543_ (.CLK(CTS_13),
+ .D(_0224_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4544_ (.CLK(CTS_13),
+ .D(_0225_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4545_ (.CLK(CTS_13),
+ .D(_0226_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4546_ (.CLK(CTS_13),
+ .D(_0227_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4547_ (.CLK(CTS_13),
+ .D(_0228_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4548_ (.CLK(CTS_13),
+ .D(_0229_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4549_ (.CLK(CTS_13),
+ .D(_0230_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4550_ (.CLK(CTS_13),
+ .D(_0231_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4551_ (.CLK(CTS_13),
+ .D(_0232_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4552_ (.CLK(CTS_13),
+ .D(_0233_),
+ .Q(\Inst_Frame_Data_Reg_9.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4553_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_0.A1 ),
+ .Q(\to_fabric_io_0.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4554_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_1.A1 ),
+ .Q(\to_fabric_io_1.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4555_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_2.A1 ),
+ .Q(\to_fabric_io_2.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4556_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_3.A1 ),
+ .Q(\to_fabric_io_3.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4557_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_4.A1 ),
+ .Q(\to_fabric_io_4.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4558_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_5.A1 ),
+ .Q(\to_fabric_io_5.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4559_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_6.A1 ),
+ .Q(\to_fabric_io_6.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4560_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_7.A1 ),
+ .Q(\to_fabric_io_7.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4561_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_8.A1 ),
+ .Q(\to_fabric_io_8.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4562_ (.CLK(FE_OFN77_wb_clk_i),
+ .D(\to_fabric_io_9.A1 ),
+ .Q(\to_fabric_io_9.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4563_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_10.A1 ),
+ .Q(\to_fabric_io_10.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4564_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_11.A1 ),
+ .Q(\to_fabric_io_11.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4565_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_12.A1 ),
+ .Q(\to_fabric_io_12.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4566_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_13.A1 ),
+ .Q(\to_fabric_io_13.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4567_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_14.A1 ),
+ .Q(\to_fabric_io_14.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4568_ (.CLK(wb_clk_i),
+ .D(\to_fabric_io_15.A1 ),
+ .Q(\to_fabric_io_15.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4569_ (.CLK(wb_clk_i),
+ .D(\to_fabric_addr.A1 ),
+ .Q(\to_fabric_addr.A1 ));
+ sky130_fd_sc_hd__dfxtp_2 _4570_ (.CLK(CTS_15),
+ .D(_0251_),
+ .Q(\Config_inst.INST_config_UART.PresentState[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4571_ (.CLK(CTS_15),
+ .D(_0252_),
+ .Q(\Config_inst.INST_config_UART.PresentState[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4572_ (.CLK(CTS_10),
+ .D(_0253_),
+ .Q(\Config_inst.INST_config_UART.PresentState[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4573_ (.CLK(CTS_10),
+ .D(_0254_),
+ .Q(\Config_inst.INST_config_UART.ReceivedWord[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4574_ (.CLK(CTS_15),
+ .D(_0255_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4575_ (.CLK(CTS_15),
+ .D(_0256_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4576_ (.CLK(CTS_15),
+ .D(_0257_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4577_ (.CLK(CTS_15),
+ .D(_0258_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4578_ (.CLK(CTS_15),
+ .D(_0259_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4579_ (.CLK(CTS_15),
+ .D(_0260_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4580_ (.CLK(CTS_15),
+ .D(_0261_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4581_ (.CLK(CTS_15),
+ .D(_0262_),
+ .Q(\Config_inst.INST_config_UART.ID_Reg[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4582_ (.CLK(CTS_15),
+ .D(_0263_),
+ .Q(\Config_inst.INST_config_UART.ReceivedWord[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4583_ (.CLK(CTS_10),
+ .D(_0264_),
+ .Q(\Config_inst.INST_config_UART.ReceivedWord[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4584_ (.CLK(CTS_10),
+ .D(_0265_),
+ .Q(\Config_inst.INST_config_UART.ReceivedWord[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4585_ (.CLK(CTS_15),
+ .D(_1647_),
+ .Q(\Config_inst.INST_config_UART.ReceivedWord[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4586_ (.CLK(CTS_15),
+ .D(_1644_),
+ .Q(\Config_inst.INST_config_UART.ReceivedWord[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4587_ (.CLK(CTS_15),
+ .D(_1642_),
+ .Q(\Config_inst.INST_config_UART.ReceivedWord[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4588_ (.CLK(CTS_15),
+ .D(_1639_),
+ .Q(\Config_inst.INST_config_UART.ReceivedWord[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4589_ (.CLK(CTS_3),
+ .D(_0270_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4590_ (.CLK(CTS_1),
+ .D(_0271_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4591_ (.CLK(CTS_1),
+ .D(_0272_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4592_ (.CLK(CTS_1),
+ .D(_0273_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4593_ (.CLK(CTS_1),
+ .D(_0274_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4594_ (.CLK(CTS_1),
+ .D(_0275_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4595_ (.CLK(CTS_1),
+ .D(_0276_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4596_ (.CLK(CTS_1),
+ .D(_0277_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4597_ (.CLK(CTS_1),
+ .D(_0278_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4598_ (.CLK(CTS_1),
+ .D(_0279_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4599_ (.CLK(CTS_1),
+ .D(_0280_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4600_ (.CLK(CTS_1),
+ .D(_0281_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4601_ (.CLK(CTS_1),
+ .D(_0282_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4602_ (.CLK(CTS_1),
+ .D(_0283_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4603_ (.CLK(CTS_1),
+ .D(_0284_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4604_ (.CLK(CTS_1),
+ .D(_0285_),
+ .Q(\Config_inst.Inst_bitbang.serial_control[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4605_ (.CLK(CTS_2),
+ .D(_0286_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4606_ (.CLK(CTS_2),
+ .D(_0287_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4607_ (.CLK(CTS_2),
+ .D(_0288_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4608_ (.CLK(CTS_2),
+ .D(_0289_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4609_ (.CLK(CTS_2),
+ .D(_0290_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4610_ (.CLK(CTS_2),
+ .D(_0291_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4611_ (.CLK(CTS_2),
+ .D(_0292_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4612_ (.CLK(CTS_2),
+ .D(_0293_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4613_ (.CLK(CTS_2),
+ .D(_0294_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4614_ (.CLK(CTS_2),
+ .D(_0295_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4615_ (.CLK(CTS_2),
+ .D(_0296_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4616_ (.CLK(CTS_2),
+ .D(_0297_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4617_ (.CLK(CTS_2),
+ .D(_0298_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4618_ (.CLK(CTS_2),
+ .D(_0299_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4619_ (.CLK(CTS_2),
+ .D(_0300_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4620_ (.CLK(CTS_2),
+ .D(_0301_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4621_ (.CLK(CTS_2),
+ .D(_0302_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4622_ (.CLK(CTS_2),
+ .D(_0303_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4623_ (.CLK(CTS_2),
+ .D(_0304_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4624_ (.CLK(CTS_2),
+ .D(_0305_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4625_ (.CLK(CTS_2),
+ .D(_0306_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4626_ (.CLK(CTS_2),
+ .D(_0307_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4627_ (.CLK(CTS_2),
+ .D(_0308_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4628_ (.CLK(CTS_2),
+ .D(_0309_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4629_ (.CLK(CTS_2),
+ .D(_0310_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameAddressRegister[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4630_ (.CLK(CTS_3),
+ .D(_0311_),
+ .Q(\Config_inst.BitBangWriteData[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4631_ (.CLK(CTS_3),
+ .D(_0312_),
+ .Q(\Config_inst.BitBangWriteData[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4632_ (.CLK(CTS_3),
+ .D(_0313_),
+ .Q(\Config_inst.BitBangWriteData[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4633_ (.CLK(CTS_3),
+ .D(_0314_),
+ .Q(\Config_inst.BitBangWriteData[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4634_ (.CLK(CTS_15),
+ .D(_0315_),
+ .Q(\Config_inst.BitBangWriteData[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4635_ (.CLK(CTS_15),
+ .D(_0316_),
+ .Q(\Config_inst.BitBangWriteData[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4636_ (.CLK(CTS_15),
+ .D(_0317_),
+ .Q(\Config_inst.BitBangWriteData[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4637_ (.CLK(CTS_15),
+ .D(_0318_),
+ .Q(\Config_inst.BitBangWriteData[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4638_ (.CLK(CTS_3),
+ .D(_0319_),
+ .Q(\Config_inst.BitBangWriteData[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4639_ (.CLK(CTS_3),
+ .D(_0320_),
+ .Q(\Config_inst.BitBangWriteData[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4640_ (.CLK(CTS_3),
+ .D(_0321_),
+ .Q(\Config_inst.BitBangWriteData[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4641_ (.CLK(CTS_3),
+ .D(_0322_),
+ .Q(\Config_inst.BitBangWriteData[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4642_ (.CLK(CTS_3),
+ .D(_0323_),
+ .Q(\Config_inst.BitBangWriteData[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4643_ (.CLK(CTS_3),
+ .D(_0324_),
+ .Q(\Config_inst.BitBangWriteData[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4644_ (.CLK(CTS_3),
+ .D(_0325_),
+ .Q(\Config_inst.BitBangWriteData[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4645_ (.CLK(CTS_3),
+ .D(_0326_),
+ .Q(\Config_inst.BitBangWriteData[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4646_ (.CLK(CTS_3),
+ .D(_0327_),
+ .Q(\Config_inst.BitBangWriteData[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4647_ (.CLK(CTS_3),
+ .D(_0328_),
+ .Q(\Config_inst.BitBangWriteData[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4648_ (.CLK(CTS_3),
+ .D(_0329_),
+ .Q(\Config_inst.BitBangWriteData[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4649_ (.CLK(CTS_3),
+ .D(_0330_),
+ .Q(\Config_inst.BitBangWriteData[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4650_ (.CLK(CTS_3),
+ .D(_0331_),
+ .Q(\Config_inst.BitBangWriteData[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4651_ (.CLK(CTS_3),
+ .D(_0332_),
+ .Q(\Config_inst.BitBangWriteData[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4652_ (.CLK(CTS_3),
+ .D(_0333_),
+ .Q(\Config_inst.BitBangWriteData[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4653_ (.CLK(CTS_3),
+ .D(_0334_),
+ .Q(\Config_inst.BitBangWriteData[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4654_ (.CLK(CTS_3),
+ .D(_0335_),
+ .Q(\Config_inst.BitBangWriteData[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4655_ (.CLK(CTS_3),
+ .D(_0336_),
+ .Q(\Config_inst.BitBangWriteData[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4656_ (.CLK(CTS_3),
+ .D(_0337_),
+ .Q(\Config_inst.BitBangWriteData[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4657_ (.CLK(CTS_3),
+ .D(_0338_),
+ .Q(\Config_inst.BitBangWriteData[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4658_ (.CLK(CTS_3),
+ .D(_0339_),
+ .Q(\Config_inst.BitBangWriteData[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4659_ (.CLK(CTS_15),
+ .D(_0340_),
+ .Q(\Config_inst.BitBangWriteData[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4660_ (.CLK(CTS_15),
+ .D(_0341_),
+ .Q(\Config_inst.BitBangWriteData[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4661_ (.CLK(CTS_15),
+ .D(_0342_),
+ .Q(\Config_inst.BitBangWriteData[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4662_ (.CLK(CTS_3),
+ .D(_0343_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4663_ (.CLK(CTS_3),
+ .D(_0344_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4664_ (.CLK(CTS_3),
+ .D(_0345_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4665_ (.CLK(CTS_3),
+ .D(_0346_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4666_ (.CLK(CTS_3),
+ .D(_0347_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4667_ (.CLK(CTS_3),
+ .D(_0348_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4668_ (.CLK(CTS_3),
+ .D(_0349_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4669_ (.CLK(CTS_3),
+ .D(_0350_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4670_ (.CLK(CTS_3),
+ .D(_0351_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4671_ (.CLK(CTS_3),
+ .D(_0352_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4672_ (.CLK(CTS_3),
+ .D(_0353_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4673_ (.CLK(CTS_3),
+ .D(_0354_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4674_ (.CLK(CTS_3),
+ .D(_0355_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4675_ (.CLK(CTS_3),
+ .D(_0356_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4676_ (.CLK(CTS_3),
+ .D(_0357_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4677_ (.CLK(CTS_3),
+ .D(_0358_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4678_ (.CLK(CTS_3),
+ .D(_0359_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4679_ (.CLK(CTS_3),
+ .D(_0360_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4680_ (.CLK(CTS_3),
+ .D(_0361_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4681_ (.CLK(CTS_3),
+ .D(_0362_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4682_ (.CLK(CTS_3),
+ .D(_0363_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4683_ (.CLK(CTS_3),
+ .D(_0364_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4684_ (.CLK(CTS_3),
+ .D(_0365_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4685_ (.CLK(CTS_3),
+ .D(_0366_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4686_ (.CLK(CTS_3),
+ .D(_0367_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4687_ (.CLK(CTS_3),
+ .D(_0368_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4688_ (.CLK(CTS_3),
+ .D(_0369_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4689_ (.CLK(CTS_3),
+ .D(_0370_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4690_ (.CLK(CTS_15),
+ .D(_0371_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4691_ (.CLK(CTS_15),
+ .D(_0372_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4692_ (.CLK(CTS_15),
+ .D(_0373_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4693_ (.CLK(CTS_15),
+ .D(_0374_),
+ .Q(\Config_inst.Inst_bitbang.serial_data[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4694_ (.CLK(CTS_15),
+ .D(_0375_),
+ .Q(\Config_inst.INST_config_UART.HighReg[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4695_ (.CLK(CTS_15),
+ .D(_0376_),
+ .Q(\Config_inst.INST_config_UART.HighReg[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4696_ (.CLK(CTS_15),
+ .D(_0377_),
+ .Q(\Config_inst.INST_config_UART.HighReg[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4697_ (.CLK(CTS_15),
+ .D(_0378_),
+ .Q(\Config_inst.INST_config_UART.HighReg[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4698_ (.CLK(CTS_15),
+ .D(_0379_),
+ .Q(\Config_inst.INST_config_UART.HexData[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4699_ (.CLK(CTS_15),
+ .D(_0380_),
+ .Q(\Config_inst.INST_config_UART.HexData[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4700_ (.CLK(CTS_15),
+ .D(_0381_),
+ .Q(\Config_inst.INST_config_UART.HexData[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4701_ (.CLK(CTS_15),
+ .D(_0382_),
+ .Q(\Config_inst.INST_config_UART.HexData[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4702_ (.CLK(CTS_15),
+ .D(_0383_),
+ .Q(\Config_inst.INST_config_UART.HexData[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4703_ (.CLK(CTS_15),
+ .D(_0384_),
+ .Q(\Config_inst.INST_config_UART.HexData[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4704_ (.CLK(CTS_15),
+ .D(_0385_),
+ .Q(\Config_inst.INST_config_UART.HexData[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4705_ (.CLK(CTS_15),
+ .D(_0386_),
+ .Q(\Config_inst.INST_config_UART.HexData[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4706_ (.CLK(CTS_8),
+ .D(_0387_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4707_ (.CLK(CTS_8),
+ .D(_0388_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4708_ (.CLK(CTS_8),
+ .D(_0389_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4709_ (.CLK(CTS_8),
+ .D(_0390_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4710_ (.CLK(CTS_8),
+ .D(_0391_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4711_ (.CLK(CTS_8),
+ .D(_0392_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4712_ (.CLK(CTS_8),
+ .D(_0393_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4713_ (.CLK(CTS_8),
+ .D(_0394_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4714_ (.CLK(CTS_8),
+ .D(_0395_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4715_ (.CLK(CTS_8),
+ .D(_0396_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4716_ (.CLK(CTS_8),
+ .D(_0397_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4717_ (.CLK(CTS_8),
+ .D(_0398_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4718_ (.CLK(CTS_8),
+ .D(_0399_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4719_ (.CLK(CTS_8),
+ .D(_0400_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4720_ (.CLK(CTS_8),
+ .D(_0401_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4721_ (.CLK(CTS_8),
+ .D(_0402_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4722_ (.CLK(CTS_8),
+ .D(_0403_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4723_ (.CLK(CTS_8),
+ .D(_0404_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4724_ (.CLK(CTS_8),
+ .D(_0405_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4725_ (.CLK(CTS_8),
+ .D(_0406_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4726_ (.CLK(CTS_8),
+ .D(_0407_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4727_ (.CLK(CTS_8),
+ .D(_0408_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4728_ (.CLK(CTS_8),
+ .D(_0409_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4729_ (.CLK(CTS_8),
+ .D(_0410_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4730_ (.CLK(CTS_8),
+ .D(_0411_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4731_ (.CLK(CTS_8),
+ .D(_0412_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4732_ (.CLK(CTS_8),
+ .D(_0413_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4733_ (.CLK(CTS_8),
+ .D(_0414_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4734_ (.CLK(CTS_8),
+ .D(_0415_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4735_ (.CLK(CTS_8),
+ .D(_0416_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4736_ (.CLK(CTS_8),
+ .D(_0417_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4737_ (.CLK(CTS_8),
+ .D(_0418_),
+ .Q(\Inst_Frame_Data_Reg_0.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4738_ (.CLK(CTS_2),
+ .D(_0419_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4739_ (.CLK(CTS_2),
+ .D(_0420_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4740_ (.CLK(CTS_2),
+ .D(_0421_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4741_ (.CLK(CTS_2),
+ .D(_0422_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4742_ (.CLK(CTS_2),
+ .D(_0423_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4743_ (.CLK(CTS_2),
+ .D(_0424_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4744_ (.CLK(CTS_2),
+ .D(_0425_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4745_ (.CLK(CTS_2),
+ .D(_0426_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4746_ (.CLK(CTS_2),
+ .D(_0427_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4747_ (.CLK(CTS_2),
+ .D(_0428_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4748_ (.CLK(CTS_2),
+ .D(_0429_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4749_ (.CLK(CTS_2),
+ .D(_0430_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4750_ (.CLK(CTS_2),
+ .D(_0431_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4751_ (.CLK(CTS_2),
+ .D(_0432_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4752_ (.CLK(CTS_2),
+ .D(_0433_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4753_ (.CLK(CTS_2),
+ .D(_0434_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4754_ (.CLK(CTS_2),
+ .D(_0435_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4755_ (.CLK(CTS_2),
+ .D(_0436_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4756_ (.CLK(CTS_2),
+ .D(_0437_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4757_ (.CLK(CTS_2),
+ .D(_0438_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4758_ (.CLK(CTS_2),
+ .D(_0439_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4759_ (.CLK(CTS_2),
+ .D(_0440_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4760_ (.CLK(CTS_2),
+ .D(_0441_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4761_ (.CLK(CTS_2),
+ .D(_0442_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4762_ (.CLK(CTS_2),
+ .D(_0443_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4763_ (.CLK(CTS_2),
+ .D(_0444_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4764_ (.CLK(CTS_2),
+ .D(_0445_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4765_ (.CLK(CTS_2),
+ .D(_0446_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4766_ (.CLK(CTS_2),
+ .D(_0447_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4767_ (.CLK(CTS_2),
+ .D(_0448_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4768_ (.CLK(CTS_2),
+ .D(_0449_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4769_ (.CLK(CTS_2),
+ .D(_0450_),
+ .Q(\Inst_Frame_Data_Reg_15.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4770_ (.CLK(CTS_8),
+ .D(_0451_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4771_ (.CLK(CTS_8),
+ .D(_0452_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4772_ (.CLK(CTS_8),
+ .D(_0453_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4773_ (.CLK(CTS_8),
+ .D(_0454_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4774_ (.CLK(CTS_8),
+ .D(_0455_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4775_ (.CLK(CTS_8),
+ .D(_0456_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4776_ (.CLK(CTS_8),
+ .D(_0457_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4777_ (.CLK(CTS_8),
+ .D(_0458_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4778_ (.CLK(CTS_8),
+ .D(_0459_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4779_ (.CLK(CTS_8),
+ .D(_0460_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4780_ (.CLK(CTS_8),
+ .D(_0461_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4781_ (.CLK(CTS_8),
+ .D(_0462_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4782_ (.CLK(CTS_8),
+ .D(_0463_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4783_ (.CLK(CTS_8),
+ .D(_0464_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4784_ (.CLK(CTS_8),
+ .D(_0465_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4785_ (.CLK(CTS_8),
+ .D(_0466_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4786_ (.CLK(CTS_8),
+ .D(_0467_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4787_ (.CLK(CTS_8),
+ .D(_0468_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4788_ (.CLK(CTS_8),
+ .D(_0469_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4789_ (.CLK(CTS_8),
+ .D(_0470_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4790_ (.CLK(CTS_8),
+ .D(_0471_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4791_ (.CLK(CTS_8),
+ .D(_0472_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4792_ (.CLK(CTS_8),
+ .D(_0473_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4793_ (.CLK(CTS_8),
+ .D(_0474_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4794_ (.CLK(CTS_8),
+ .D(_0475_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4795_ (.CLK(CTS_8),
+ .D(_0476_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4796_ (.CLK(CTS_8),
+ .D(_0477_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4797_ (.CLK(CTS_8),
+ .D(_0478_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4798_ (.CLK(CTS_8),
+ .D(_0479_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4799_ (.CLK(CTS_8),
+ .D(_0480_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4800_ (.CLK(CTS_8),
+ .D(_0481_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4801_ (.CLK(CTS_8),
+ .D(_0482_),
+ .Q(\Inst_Frame_Data_Reg_2.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4802_ (.CLK(CTS_14),
+ .D(_0483_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4803_ (.CLK(CTS_14),
+ .D(_0484_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4804_ (.CLK(CTS_14),
+ .D(_0485_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4805_ (.CLK(CTS_14),
+ .D(_0486_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4806_ (.CLK(CTS_14),
+ .D(_0487_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4807_ (.CLK(CTS_14),
+ .D(_0488_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4808_ (.CLK(CTS_14),
+ .D(_0489_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4809_ (.CLK(CTS_14),
+ .D(_0490_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4810_ (.CLK(CTS_14),
+ .D(_0491_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4811_ (.CLK(CTS_14),
+ .D(_0492_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4812_ (.CLK(CTS_14),
+ .D(_0493_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4813_ (.CLK(CTS_14),
+ .D(_0494_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4814_ (.CLK(CTS_14),
+ .D(_0495_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4815_ (.CLK(CTS_14),
+ .D(_0496_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4816_ (.CLK(CTS_14),
+ .D(_0497_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4817_ (.CLK(CTS_14),
+ .D(_0498_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4818_ (.CLK(CTS_14),
+ .D(_0499_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4819_ (.CLK(CTS_14),
+ .D(_0500_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4820_ (.CLK(CTS_14),
+ .D(_0501_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4821_ (.CLK(CTS_14),
+ .D(_0502_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4822_ (.CLK(CTS_14),
+ .D(_0503_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4823_ (.CLK(CTS_14),
+ .D(_0504_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4824_ (.CLK(CTS_14),
+ .D(_0505_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4825_ (.CLK(CTS_14),
+ .D(_0506_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4826_ (.CLK(CTS_14),
+ .D(_0507_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4827_ (.CLK(CTS_14),
+ .D(_0508_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4828_ (.CLK(CTS_14),
+ .D(_0509_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4829_ (.CLK(CTS_14),
+ .D(_0510_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4830_ (.CLK(CTS_14),
+ .D(_0511_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4831_ (.CLK(CTS_14),
+ .D(_0512_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4832_ (.CLK(CTS_14),
+ .D(_0513_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4833_ (.CLK(CTS_14),
+ .D(_0514_),
+ .Q(\Inst_Frame_Data_Reg_3.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4834_ (.CLK(CTS_14),
+ .D(_0515_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4835_ (.CLK(CTS_14),
+ .D(_0516_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4836_ (.CLK(CTS_14),
+ .D(_0517_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4837_ (.CLK(CTS_14),
+ .D(_0518_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4838_ (.CLK(CTS_14),
+ .D(_0519_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4839_ (.CLK(CTS_14),
+ .D(_0520_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4840_ (.CLK(CTS_14),
+ .D(_0521_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4841_ (.CLK(CTS_14),
+ .D(_0522_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4842_ (.CLK(CTS_14),
+ .D(_0523_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4843_ (.CLK(CTS_14),
+ .D(_0524_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4844_ (.CLK(CTS_14),
+ .D(_0525_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4845_ (.CLK(CTS_14),
+ .D(_0526_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4846_ (.CLK(CTS_14),
+ .D(_0527_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4847_ (.CLK(CTS_14),
+ .D(_0528_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4848_ (.CLK(CTS_14),
+ .D(_0529_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4849_ (.CLK(CTS_14),
+ .D(_0530_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4850_ (.CLK(CTS_14),
+ .D(_0531_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4851_ (.CLK(CTS_14),
+ .D(_0532_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4852_ (.CLK(CTS_14),
+ .D(_0533_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4853_ (.CLK(CTS_14),
+ .D(_0534_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4854_ (.CLK(CTS_14),
+ .D(_0535_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4855_ (.CLK(CTS_14),
+ .D(_0536_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4856_ (.CLK(CTS_14),
+ .D(_0537_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4857_ (.CLK(CTS_14),
+ .D(_0538_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4858_ (.CLK(CTS_14),
+ .D(_0539_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4859_ (.CLK(CTS_14),
+ .D(_0540_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4860_ (.CLK(CTS_14),
+ .D(_0541_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4861_ (.CLK(CTS_14),
+ .D(_0542_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4862_ (.CLK(CTS_14),
+ .D(_0543_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4863_ (.CLK(CTS_14),
+ .D(_0544_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4864_ (.CLK(CTS_14),
+ .D(_0545_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4865_ (.CLK(CTS_14),
+ .D(_0546_),
+ .Q(\Inst_Frame_Data_Reg_4.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4866_ (.CLK(CTS_9),
+ .D(_0547_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4867_ (.CLK(CTS_9),
+ .D(_0548_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4868_ (.CLK(CTS_9),
+ .D(_0549_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4869_ (.CLK(CTS_9),
+ .D(_0550_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4870_ (.CLK(CTS_9),
+ .D(_0551_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4871_ (.CLK(CTS_9),
+ .D(_0552_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4872_ (.CLK(CTS_9),
+ .D(_0553_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4873_ (.CLK(CTS_9),
+ .D(_0554_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4874_ (.CLK(CTS_9),
+ .D(_0555_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4875_ (.CLK(CTS_9),
+ .D(_0556_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4876_ (.CLK(CTS_9),
+ .D(_0557_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4877_ (.CLK(CTS_9),
+ .D(_0558_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4878_ (.CLK(CTS_9),
+ .D(_0559_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4879_ (.CLK(CTS_9),
+ .D(_0560_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4880_ (.CLK(CTS_9),
+ .D(_0561_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4881_ (.CLK(CTS_9),
+ .D(_0562_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4882_ (.CLK(CTS_9),
+ .D(_0563_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4883_ (.CLK(CTS_9),
+ .D(_0564_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4884_ (.CLK(CTS_9),
+ .D(_0565_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4885_ (.CLK(CTS_9),
+ .D(_0566_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4886_ (.CLK(CTS_9),
+ .D(_0567_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4887_ (.CLK(CTS_9),
+ .D(_0568_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4888_ (.CLK(CTS_9),
+ .D(_0569_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4889_ (.CLK(CTS_9),
+ .D(_0570_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4890_ (.CLK(CTS_9),
+ .D(_0571_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4891_ (.CLK(CTS_9),
+ .D(_0572_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4892_ (.CLK(CTS_9),
+ .D(_0573_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4893_ (.CLK(CTS_9),
+ .D(_0574_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4894_ (.CLK(CTS_9),
+ .D(_0575_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4895_ (.CLK(CTS_9),
+ .D(_0576_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4896_ (.CLK(CTS_9),
+ .D(_0577_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4897_ (.CLK(CTS_9),
+ .D(_0578_),
+ .Q(\Inst_Frame_Data_Reg_5.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4898_ (.CLK(CTS_9),
+ .D(_0579_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4899_ (.CLK(CTS_9),
+ .D(_0580_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4900_ (.CLK(CTS_9),
+ .D(_0581_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4901_ (.CLK(CTS_9),
+ .D(_0582_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4902_ (.CLK(CTS_9),
+ .D(_0583_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4903_ (.CLK(CTS_9),
+ .D(_0584_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4904_ (.CLK(CTS_9),
+ .D(_0585_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4905_ (.CLK(CTS_9),
+ .D(_0586_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4906_ (.CLK(CTS_9),
+ .D(_0587_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4907_ (.CLK(CTS_9),
+ .D(_0588_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4908_ (.CLK(CTS_9),
+ .D(_0589_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4909_ (.CLK(CTS_9),
+ .D(_0590_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4910_ (.CLK(CTS_9),
+ .D(_0591_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4911_ (.CLK(CTS_9),
+ .D(_0592_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4912_ (.CLK(CTS_9),
+ .D(_0593_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4913_ (.CLK(CTS_9),
+ .D(_0594_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4914_ (.CLK(CTS_9),
+ .D(_0595_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4915_ (.CLK(CTS_9),
+ .D(_0596_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4916_ (.CLK(CTS_9),
+ .D(_0597_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4917_ (.CLK(CTS_9),
+ .D(_0598_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4918_ (.CLK(CTS_9),
+ .D(_0599_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4919_ (.CLK(CTS_9),
+ .D(_0600_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4920_ (.CLK(CTS_9),
+ .D(_0601_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4921_ (.CLK(CTS_9),
+ .D(_0602_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4922_ (.CLK(CTS_9),
+ .D(_0603_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4923_ (.CLK(CTS_9),
+ .D(_0604_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4924_ (.CLK(CTS_9),
+ .D(_0605_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4925_ (.CLK(CTS_9),
+ .D(_0606_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4926_ (.CLK(CTS_9),
+ .D(_0607_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4927_ (.CLK(CTS_9),
+ .D(_0608_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4928_ (.CLK(CTS_9),
+ .D(_0609_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4929_ (.CLK(CTS_9),
+ .D(_0610_),
+ .Q(\Inst_Frame_Data_Reg_6.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4930_ (.CLK(CTS_9),
+ .D(_0611_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4931_ (.CLK(CTS_9),
+ .D(_0612_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4932_ (.CLK(CTS_9),
+ .D(_0613_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4933_ (.CLK(CTS_9),
+ .D(_0614_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4934_ (.CLK(CTS_9),
+ .D(_0615_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4935_ (.CLK(CTS_9),
+ .D(_0616_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4936_ (.CLK(CTS_9),
+ .D(_0617_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4937_ (.CLK(CTS_9),
+ .D(_0618_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4938_ (.CLK(CTS_9),
+ .D(_0619_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4939_ (.CLK(CTS_9),
+ .D(_0620_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4940_ (.CLK(CTS_9),
+ .D(_0621_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4941_ (.CLK(CTS_9),
+ .D(_0622_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4942_ (.CLK(CTS_9),
+ .D(_0623_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4943_ (.CLK(CTS_9),
+ .D(_0624_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4944_ (.CLK(CTS_9),
+ .D(_0625_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4945_ (.CLK(CTS_9),
+ .D(_0626_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4946_ (.CLK(CTS_9),
+ .D(_0627_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4947_ (.CLK(CTS_9),
+ .D(_0628_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4948_ (.CLK(CTS_9),
+ .D(_0629_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4949_ (.CLK(CTS_9),
+ .D(_0630_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4950_ (.CLK(CTS_9),
+ .D(_0631_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4951_ (.CLK(CTS_9),
+ .D(_0632_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4952_ (.CLK(CTS_9),
+ .D(_0633_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4953_ (.CLK(CTS_9),
+ .D(_0634_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4954_ (.CLK(CTS_9),
+ .D(_0635_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4955_ (.CLK(CTS_9),
+ .D(_0636_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4956_ (.CLK(CTS_9),
+ .D(_0637_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4957_ (.CLK(CTS_9),
+ .D(_0638_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4958_ (.CLK(CTS_9),
+ .D(_0639_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4959_ (.CLK(CTS_9),
+ .D(_0640_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4960_ (.CLK(CTS_9),
+ .D(_0641_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4961_ (.CLK(CTS_9),
+ .D(_0642_),
+ .Q(\Inst_Frame_Data_Reg_7.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4962_ (.CLK(CTS_13),
+ .D(_0643_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4963_ (.CLK(CTS_13),
+ .D(_0644_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4964_ (.CLK(CTS_13),
+ .D(_0645_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4965_ (.CLK(CTS_13),
+ .D(_0646_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4966_ (.CLK(CTS_13),
+ .D(_0647_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4967_ (.CLK(CTS_13),
+ .D(_0648_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _4968_ (.CLK(CTS_13),
+ .D(_0649_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _4969_ (.CLK(CTS_13),
+ .D(_0650_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _4970_ (.CLK(CTS_13),
+ .D(_0651_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _4971_ (.CLK(CTS_13),
+ .D(_0652_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _4972_ (.CLK(CTS_13),
+ .D(_0653_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _4973_ (.CLK(CTS_13),
+ .D(_0654_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _4974_ (.CLK(CTS_13),
+ .D(_0655_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _4975_ (.CLK(CTS_13),
+ .D(_0656_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _4976_ (.CLK(CTS_13),
+ .D(_0657_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _4977_ (.CLK(CTS_13),
+ .D(_0658_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _4978_ (.CLK(CTS_13),
+ .D(_0659_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _4979_ (.CLK(CTS_13),
+ .D(_0660_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _4980_ (.CLK(CTS_13),
+ .D(_0661_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _4981_ (.CLK(CTS_13),
+ .D(_0662_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _4982_ (.CLK(CTS_13),
+ .D(_0663_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _4983_ (.CLK(CTS_13),
+ .D(_0664_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _4984_ (.CLK(CTS_13),
+ .D(_0665_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _4985_ (.CLK(CTS_13),
+ .D(_0666_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _4986_ (.CLK(CTS_13),
+ .D(_0667_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _4987_ (.CLK(CTS_13),
+ .D(_0668_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _4988_ (.CLK(CTS_13),
+ .D(_0669_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _4989_ (.CLK(CTS_13),
+ .D(_0670_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _4990_ (.CLK(CTS_13),
+ .D(_0671_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _4991_ (.CLK(CTS_13),
+ .D(_0672_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _4992_ (.CLK(CTS_13),
+ .D(_0673_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _4993_ (.CLK(CTS_13),
+ .D(_0674_),
+ .Q(\Inst_Frame_Data_Reg_8.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _4994_ (.CLK(CTS_8),
+ .D(_0675_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _4995_ (.CLK(CTS_8),
+ .D(_0676_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _4996_ (.CLK(CTS_8),
+ .D(_0677_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _4997_ (.CLK(CTS_8),
+ .D(_0678_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _4998_ (.CLK(CTS_8),
+ .D(_0679_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _4999_ (.CLK(CTS_8),
+ .D(_0680_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _5000_ (.CLK(CTS_8),
+ .D(_0681_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _5001_ (.CLK(CTS_8),
+ .D(_0682_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _5002_ (.CLK(CTS_8),
+ .D(_0683_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _5003_ (.CLK(CTS_8),
+ .D(_0684_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _5004_ (.CLK(CTS_8),
+ .D(_0685_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _5005_ (.CLK(CTS_8),
+ .D(_0686_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _5006_ (.CLK(CTS_8),
+ .D(_0687_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _5007_ (.CLK(CTS_8),
+ .D(_0688_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _5008_ (.CLK(CTS_8),
+ .D(_0689_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _5009_ (.CLK(CTS_8),
+ .D(_0690_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _5010_ (.CLK(CTS_8),
+ .D(_0691_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _5011_ (.CLK(CTS_8),
+ .D(_0692_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _5012_ (.CLK(CTS_8),
+ .D(_0693_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _5013_ (.CLK(CTS_8),
+ .D(_0694_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _5014_ (.CLK(CTS_8),
+ .D(_0695_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _5015_ (.CLK(CTS_8),
+ .D(_0696_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _5016_ (.CLK(CTS_8),
+ .D(_0697_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _5017_ (.CLK(CTS_8),
+ .D(_0698_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _5018_ (.CLK(CTS_8),
+ .D(_0699_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _5019_ (.CLK(CTS_8),
+ .D(_0700_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _5020_ (.CLK(CTS_8),
+ .D(_0701_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _5021_ (.CLK(CTS_8),
+ .D(_0702_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _5022_ (.CLK(CTS_8),
+ .D(_0703_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _5023_ (.CLK(CTS_8),
+ .D(_0704_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _5024_ (.CLK(CTS_8),
+ .D(_0705_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _5025_ (.CLK(CTS_8),
+ .D(_0706_),
+ .Q(\Inst_Frame_Data_Reg_1.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _5026_ (.CLK(CTS_15),
+ .D(_0707_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5027_ (.CLK(CTS_15),
+ .D(_0708_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5028_ (.CLK(CTS_15),
+ .D(_0709_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _5029_ (.CLK(CTS_15),
+ .D(_0710_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _5030_ (.CLK(CTS_15),
+ .D(_0711_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _5031_ (.CLK(CTS_15),
+ .D(_0712_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _5032_ (.CLK(CTS_15),
+ .D(_0713_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _5033_ (.CLK(CTS_15),
+ .D(_0714_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _5034_ (.CLK(CTS_15),
+ .D(_0715_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _5035_ (.CLK(CTS_10),
+ .D(_0716_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _5036_ (.CLK(CTS_10),
+ .D(_0717_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _5037_ (.CLK(CTS_10),
+ .D(_0718_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _5038_ (.CLK(CTS_10),
+ .D(_0719_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _5039_ (.CLK(CTS_10),
+ .D(_0720_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _5040_ (.CLK(CTS_10),
+ .D(_0721_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _5041_ (.CLK(CTS_10),
+ .D(_0722_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _5042_ (.CLK(CTS_10),
+ .D(_0723_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _5043_ (.CLK(CTS_10),
+ .D(_0724_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _5044_ (.CLK(CTS_10),
+ .D(_0725_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _5045_ (.CLK(CTS_10),
+ .D(_0726_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _5046_ (.CLK(CTS_10),
+ .D(_0727_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _5047_ (.CLK(CTS_10),
+ .D(_0728_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _5048_ (.CLK(CTS_10),
+ .D(_0729_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _5049_ (.CLK(CTS_10),
+ .D(_0730_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _5050_ (.CLK(CTS_10),
+ .D(_0731_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _5051_ (.CLK(CTS_10),
+ .D(_0732_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _5052_ (.CLK(CTS_10),
+ .D(_0733_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _5053_ (.CLK(CTS_10),
+ .D(_0734_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _5054_ (.CLK(CTS_10),
+ .D(_0735_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _5055_ (.CLK(CTS_10),
+ .D(_0736_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _5056_ (.CLK(CTS_10),
+ .D(_0737_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _5057_ (.CLK(CTS_10),
+ .D(_0738_),
+ .Q(\Inst_Frame_Data_Reg_10.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _5058_ (.CLK(CTS_1),
+ .D(_0739_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5059_ (.CLK(CTS_1),
+ .D(_0740_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5060_ (.CLK(CTS_1),
+ .D(_0741_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _5061_ (.CLK(CTS_1),
+ .D(_0742_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _5062_ (.CLK(CTS_1),
+ .D(_0743_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _5063_ (.CLK(CTS_1),
+ .D(_0744_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _5064_ (.CLK(CTS_1),
+ .D(_0745_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _5065_ (.CLK(CTS_1),
+ .D(_0746_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _5066_ (.CLK(CTS_1),
+ .D(_0747_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _5067_ (.CLK(CTS_1),
+ .D(_0748_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _5068_ (.CLK(CTS_1),
+ .D(_0749_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _5069_ (.CLK(CTS_1),
+ .D(_0750_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _5070_ (.CLK(CTS_3),
+ .D(_0751_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _5071_ (.CLK(CTS_1),
+ .D(_0752_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _5072_ (.CLK(CTS_3),
+ .D(_0753_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _5073_ (.CLK(CTS_3),
+ .D(_0754_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _5074_ (.CLK(CTS_3),
+ .D(_0755_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _5075_ (.CLK(CTS_3),
+ .D(_0756_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _5076_ (.CLK(CTS_3),
+ .D(_0757_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _5077_ (.CLK(CTS_3),
+ .D(_0758_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _5078_ (.CLK(CTS_3),
+ .D(_0759_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _5079_ (.CLK(CTS_3),
+ .D(_0760_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _5080_ (.CLK(CTS_3),
+ .D(_0761_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _5081_ (.CLK(CTS_3),
+ .D(_0762_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _5082_ (.CLK(CTS_3),
+ .D(_0763_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _5083_ (.CLK(CTS_3),
+ .D(_0764_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _5084_ (.CLK(CTS_3),
+ .D(_0765_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _5085_ (.CLK(CTS_3),
+ .D(_0766_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _5086_ (.CLK(CTS_3),
+ .D(_0767_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _5087_ (.CLK(CTS_3),
+ .D(_0768_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _5088_ (.CLK(CTS_3),
+ .D(_0769_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _5089_ (.CLK(CTS_3),
+ .D(_0770_),
+ .Q(\Inst_Frame_Data_Reg_11.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _5090_ (.CLK(CTS_1),
+ .D(_0771_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5091_ (.CLK(CTS_1),
+ .D(_0772_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5092_ (.CLK(CTS_1),
+ .D(_0773_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _5093_ (.CLK(CTS_1),
+ .D(_0774_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _5094_ (.CLK(CTS_1),
+ .D(_0775_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _5095_ (.CLK(CTS_1),
+ .D(_0776_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _5096_ (.CLK(CTS_1),
+ .D(_0777_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _5097_ (.CLK(CTS_1),
+ .D(_0778_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _5098_ (.CLK(CTS_1),
+ .D(_0779_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _5099_ (.CLK(CTS_1),
+ .D(_0780_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _5100_ (.CLK(CTS_1),
+ .D(_0781_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _5101_ (.CLK(CTS_1),
+ .D(_0782_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _5102_ (.CLK(CTS_1),
+ .D(_0783_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _5103_ (.CLK(CTS_1),
+ .D(_0784_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _5104_ (.CLK(CTS_1),
+ .D(_0785_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _5105_ (.CLK(CTS_1),
+ .D(_0786_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _5106_ (.CLK(CTS_1),
+ .D(_0787_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _5107_ (.CLK(CTS_1),
+ .D(_0788_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _5108_ (.CLK(CTS_1),
+ .D(_0789_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _5109_ (.CLK(CTS_1),
+ .D(_0790_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _5110_ (.CLK(CTS_1),
+ .D(_0791_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _5111_ (.CLK(CTS_1),
+ .D(_0792_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _5112_ (.CLK(CTS_1),
+ .D(_0793_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _5113_ (.CLK(CTS_1),
+ .D(_0794_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _5114_ (.CLK(CTS_1),
+ .D(_0795_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _5115_ (.CLK(CTS_1),
+ .D(_0796_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _5116_ (.CLK(CTS_1),
+ .D(_0797_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _5117_ (.CLK(CTS_1),
+ .D(_0798_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _5118_ (.CLK(CTS_1),
+ .D(_0799_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _5119_ (.CLK(CTS_1),
+ .D(_0800_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _5120_ (.CLK(CTS_1),
+ .D(_0801_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _5121_ (.CLK(CTS_1),
+ .D(_0802_),
+ .Q(\Inst_Frame_Data_Reg_12.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _5122_ (.CLK(CTS_1),
+ .D(_0803_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5123_ (.CLK(CTS_1),
+ .D(_0804_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5124_ (.CLK(CTS_1),
+ .D(_0805_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _5125_ (.CLK(CTS_1),
+ .D(_0806_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _5126_ (.CLK(CTS_1),
+ .D(_0807_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _5127_ (.CLK(CTS_1),
+ .D(_0808_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _5128_ (.CLK(CTS_1),
+ .D(_0809_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _5129_ (.CLK(CTS_1),
+ .D(_0810_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _5130_ (.CLK(CTS_1),
+ .D(_0811_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _5131_ (.CLK(CTS_1),
+ .D(_0812_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _5132_ (.CLK(CTS_1),
+ .D(_0813_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _5133_ (.CLK(CTS_1),
+ .D(_0814_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _5134_ (.CLK(CTS_1),
+ .D(_0815_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _5135_ (.CLK(CTS_1),
+ .D(_0816_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _5136_ (.CLK(CTS_1),
+ .D(_0817_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _5137_ (.CLK(CTS_1),
+ .D(_0818_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _5138_ (.CLK(CTS_1),
+ .D(_0819_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _5139_ (.CLK(CTS_1),
+ .D(_0820_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _5140_ (.CLK(CTS_1),
+ .D(_0821_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _5141_ (.CLK(CTS_1),
+ .D(_0822_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _5142_ (.CLK(CTS_1),
+ .D(_0823_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _5143_ (.CLK(CTS_1),
+ .D(_0824_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _5144_ (.CLK(CTS_1),
+ .D(_0825_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _5145_ (.CLK(CTS_1),
+ .D(_0826_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _5146_ (.CLK(CTS_1),
+ .D(_0827_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _5147_ (.CLK(CTS_1),
+ .D(_0828_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _5148_ (.CLK(CTS_1),
+ .D(_0829_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _5149_ (.CLK(CTS_1),
+ .D(_0830_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _5150_ (.CLK(CTS_1),
+ .D(_0831_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _5151_ (.CLK(CTS_1),
+ .D(_0832_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _5152_ (.CLK(CTS_1),
+ .D(_0833_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _5153_ (.CLK(CTS_1),
+ .D(_0834_),
+ .Q(\Inst_Frame_Data_Reg_13.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _5154_ (.CLK(CTS_2),
+ .D(_0835_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5155_ (.CLK(CTS_2),
+ .D(_0836_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5156_ (.CLK(CTS_2),
+ .D(_0837_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _5157_ (.CLK(CTS_2),
+ .D(_0838_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _5158_ (.CLK(CTS_2),
+ .D(_0839_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _5159_ (.CLK(CTS_2),
+ .D(_0840_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _5160_ (.CLK(CTS_2),
+ .D(_0841_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _5161_ (.CLK(CTS_2),
+ .D(_0842_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _5162_ (.CLK(CTS_2),
+ .D(_0843_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _5163_ (.CLK(CTS_2),
+ .D(_0844_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _5164_ (.CLK(CTS_2),
+ .D(_0845_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _5165_ (.CLK(CTS_2),
+ .D(_0846_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _5166_ (.CLK(CTS_2),
+ .D(_0847_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _5167_ (.CLK(CTS_2),
+ .D(_0848_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _5168_ (.CLK(CTS_2),
+ .D(_0849_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _5169_ (.CLK(CTS_2),
+ .D(_0850_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _5170_ (.CLK(CTS_2),
+ .D(_0851_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _5171_ (.CLK(CTS_2),
+ .D(_0852_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _5172_ (.CLK(CTS_2),
+ .D(_0853_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _5173_ (.CLK(CTS_2),
+ .D(_0854_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _5174_ (.CLK(CTS_2),
+ .D(_0855_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _5175_ (.CLK(CTS_2),
+ .D(_0856_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _5176_ (.CLK(CTS_2),
+ .D(_0857_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _5177_ (.CLK(CTS_2),
+ .D(_0858_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _5178_ (.CLK(CTS_2),
+ .D(_0859_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _5179_ (.CLK(CTS_2),
+ .D(_0860_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _5180_ (.CLK(CTS_2),
+ .D(_0861_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _5181_ (.CLK(CTS_2),
+ .D(_0862_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _5182_ (.CLK(CTS_2),
+ .D(_0863_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _5183_ (.CLK(CTS_2),
+ .D(_0864_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _5184_ (.CLK(CTS_2),
+ .D(_0865_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _5185_ (.CLK(CTS_2),
+ .D(_0866_),
+ .Q(\Inst_Frame_Data_Reg_14.FrameData_O[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _5186_ (.CLK(CTS_10),
+ .D(_0867_),
+ .Q(\Config_inst.INST_config_UART.ComCount[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5187_ (.CLK(CTS_10),
+ .D(_1185_),
+ .Q(\Config_inst.INST_config_UART.ComCount[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _5188_ (.CLK(CTS_10),
+ .D(_0869_),
+ .Q(\Config_inst.INST_config_UART.ComCount[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _5189_ (.CLK(CTS_10),
+ .D(_0870_),
+ .Q(\Config_inst.INST_config_UART.ComCount[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _5190_ (.CLK(CTS_10),
+ .D(_0871_),
+ .Q(\Config_inst.INST_config_UART.ComCount[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _5191_ (.CLK(CTS_10),
+ .D(_0872_),
+ .Q(\Config_inst.INST_config_UART.ComCount[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _5192_ (.CLK(CTS_1),
+ .D(_1176_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameStrobe ));
+ sky130_fd_sc_hd__dfxtp_2 _5193_ (.CLK(CTS_10),
+ .D(_0874_),
+ .Q(\Config_inst.INST_config_UART.ComTick ));
+ sky130_fd_sc_hd__dfxtp_2 _5194_ (.CLK(CTS_15),
+ .D(_1173_),
+ .Q(\Config_inst.INST_config_UART.ReceiveState ));
+ sky130_fd_sc_hd__dfxtp_2 _5195_ (.CLK(CTS_15),
+ .D(_1172_),
+ .Q(\Config_inst.INST_config_UART.HexWriteStrobe ));
+ sky130_fd_sc_hd__dfxtp_2 _5196_ (.CLK(CTS_10),
+ .D(_0877_),
+ .Q(\Config_inst.INST_config_UART.TimeToSend ));
+ sky130_fd_sc_hd__dfxtp_2 _5197_ (.CLK(CTS_15),
+ .D(_1161_),
+ .Q(\Config_inst.INST_config_UART.LocalWriteStrobe ));
+ sky130_fd_sc_hd__dfxtp_2 _5198_ (.CLK(CTS_10),
+ .D(_0879_),
+ .Q(\Config_inst.INST_config_UART.ReceiveLED ));
+ sky130_fd_sc_hd__dfxtp_2 _5199_ (.CLK(CTS_10),
+ .D(_0880_),
+ .Q(\Config_inst.INST_config_UART.ComCount[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5200_ (.CLK(CTS_10),
+ .D(_0881_),
+ .Q(\Config_inst.INST_config_UART.ComCount[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _5201_ (.CLK(CTS_10),
+ .D(_0882_),
+ .Q(\Config_inst.INST_config_UART.ComCount[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _5202_ (.CLK(CTS_10),
+ .D(_0883_),
+ .Q(\Config_inst.INST_config_UART.ComCount[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _5203_ (.CLK(CTS_10),
+ .D(_0884_),
+ .Q(\Config_inst.INST_config_UART.ComCount[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _5204_ (.CLK(CTS_10),
+ .D(_0885_),
+ .Q(\Config_inst.INST_config_UART.ComCount[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _5205_ (.CLK(CTS_3),
+ .D(_0886_),
+ .Q(\Config_inst.Inst_bitbang.active ));
+ sky130_fd_sc_hd__dfxtp_2 _5206_ (.CLK(CTS_13),
+ .D(_0887_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameShiftState[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5207_ (.CLK(CTS_13),
+ .D(_0888_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameShiftState[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5208_ (.CLK(CTS_13),
+ .D(_0889_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameShiftState[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _5209_ (.CLK(CTS_13),
+ .D(_0890_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameShiftState[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _5210_ (.CLK(CTS_13),
+ .D(_0891_),
+ .Q(\Config_inst.ConfigFSM_inst.FrameShiftState[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _5211_ (.CLK(CTS_13),
+ .D(_0892_),
+ .Q(\Config_inst.ConfigFSM_inst.state[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5212_ (.CLK(CTS_10),
+ .D(_0893_),
+ .Q(\Config_inst.ConfigFSM_inst.state[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5213_ (.CLK(CTS_3),
+ .D(_0894_),
+ .Q(\Config_inst.INST_config_UART.WriteData[24] ));
+ sky130_fd_sc_hd__dfxtp_2 _5214_ (.CLK(CTS_3),
+ .D(_0895_),
+ .Q(\Config_inst.INST_config_UART.WriteData[25] ));
+ sky130_fd_sc_hd__dfxtp_2 _5215_ (.CLK(CTS_3),
+ .D(_0067_),
+ .Q(\Config_inst.INST_config_UART.WriteData[26] ));
+ sky130_fd_sc_hd__dfxtp_2 _5216_ (.CLK(CTS_3),
+ .D(_0068_),
+ .Q(\Config_inst.INST_config_UART.WriteData[27] ));
+ sky130_fd_sc_hd__dfxtp_2 _5217_ (.CLK(CTS_15),
+ .D(_0069_),
+ .Q(\Config_inst.INST_config_UART.WriteData[28] ));
+ sky130_fd_sc_hd__dfxtp_2 _5218_ (.CLK(CTS_15),
+ .D(_0070_),
+ .Q(\Config_inst.INST_config_UART.WriteData[29] ));
+ sky130_fd_sc_hd__dfxtp_2 _5219_ (.CLK(CTS_15),
+ .D(_0071_),
+ .Q(\Config_inst.INST_config_UART.WriteData[30] ));
+ sky130_fd_sc_hd__dfxtp_2 _5220_ (.CLK(CTS_15),
+ .D(_0072_),
+ .Q(\Config_inst.INST_config_UART.WriteData[31] ));
+ sky130_fd_sc_hd__dfxtp_2 _5221_ (.CLK(CTS_3),
+ .D(_0073_),
+ .Q(\Config_inst.INST_config_UART.WriteData[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _5222_ (.CLK(CTS_3),
+ .D(_0074_),
+ .Q(\Config_inst.INST_config_UART.WriteData[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _5223_ (.CLK(CTS_3),
+ .D(_0075_),
+ .Q(\Config_inst.INST_config_UART.WriteData[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _5224_ (.CLK(CTS_3),
+ .D(_0076_),
+ .Q(\Config_inst.INST_config_UART.WriteData[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _5225_ (.CLK(CTS_3),
+ .D(_0077_),
+ .Q(\Config_inst.INST_config_UART.WriteData[20] ));
+ sky130_fd_sc_hd__dfxtp_2 _5226_ (.CLK(CTS_3),
+ .D(_0078_),
+ .Q(\Config_inst.INST_config_UART.WriteData[21] ));
+ sky130_fd_sc_hd__dfxtp_2 _5227_ (.CLK(CTS_3),
+ .D(_0079_),
+ .Q(\Config_inst.INST_config_UART.WriteData[22] ));
+ sky130_fd_sc_hd__dfxtp_2 _5228_ (.CLK(CTS_3),
+ .D(_0080_),
+ .Q(\Config_inst.INST_config_UART.WriteData[23] ));
+ sky130_fd_sc_hd__dfxtp_2 _5229_ (.CLK(CTS_3),
+ .D(_0081_),
+ .Q(\Config_inst.INST_config_UART.WriteData[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _5230_ (.CLK(CTS_3),
+ .D(_0082_),
+ .Q(\Config_inst.INST_config_UART.WriteData[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _5231_ (.CLK(CTS_3),
+ .D(_0083_),
+ .Q(\Config_inst.INST_config_UART.WriteData[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _5232_ (.CLK(CTS_3),
+ .D(_0084_),
+ .Q(\Config_inst.INST_config_UART.WriteData[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _5233_ (.CLK(CTS_3),
+ .D(_0085_),
+ .Q(\Config_inst.INST_config_UART.WriteData[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _5234_ (.CLK(CTS_3),
+ .D(_0086_),
+ .Q(\Config_inst.INST_config_UART.WriteData[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _5235_ (.CLK(CTS_3),
+ .D(_0087_),
+ .Q(\Config_inst.INST_config_UART.WriteData[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _5236_ (.CLK(CTS_3),
+ .D(_0088_),
+ .Q(\Config_inst.INST_config_UART.WriteData[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _5237_ (.CLK(CTS_3),
+ .D(_0089_),
+ .Q(\Config_inst.INST_config_UART.WriteData[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5238_ (.CLK(CTS_3),
+ .D(_0090_),
+ .Q(\Config_inst.INST_config_UART.WriteData[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5239_ (.CLK(CTS_3),
+ .D(_0091_),
+ .Q(\Config_inst.INST_config_UART.WriteData[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _5240_ (.CLK(CTS_3),
+ .D(_0092_),
+ .Q(\Config_inst.INST_config_UART.WriteData[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _5241_ (.CLK(CTS_15),
+ .D(_0093_),
+ .Q(\Config_inst.INST_config_UART.WriteData[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _5242_ (.CLK(CTS_15),
+ .D(_0094_),
+ .Q(\Config_inst.INST_config_UART.WriteData[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _5243_ (.CLK(CTS_15),
+ .D(_0095_),
+ .Q(\Config_inst.INST_config_UART.WriteData[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _5244_ (.CLK(CTS_15),
+ .D(_0096_),
+ .Q(\Config_inst.INST_config_UART.WriteData[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _5245_ (.CLK(CTS_3),
+ .D(_0097_),
+ .Q(\Config_inst.INST_config_UART.GetWordState[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5246_ (.CLK(CTS_3),
+ .D(_1054_),
+ .Q(\Config_inst.INST_config_UART.GetWordState[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5247_ (.CLK(CTS_10),
+ .D(_0099_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5248_ (.CLK(CTS_10),
+ .D(_0100_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5249_ (.CLK(CTS_10),
+ .D(_0101_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _5250_ (.CLK(CTS_15),
+ .D(_0102_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _5251_ (.CLK(CTS_10),
+ .D(_0103_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _5252_ (.CLK(CTS_15),
+ .D(_0104_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _5253_ (.CLK(CTS_10),
+ .D(_0105_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _5254_ (.CLK(CTS_10),
+ .D(_0106_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _5255_ (.CLK(CTS_10),
+ .D(_0107_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _5256_ (.CLK(CTS_10),
+ .D(_0108_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _5257_ (.CLK(CTS_10),
+ .D(_0109_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _5258_ (.CLK(CTS_10),
+ .D(_0110_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _5259_ (.CLK(CTS_10),
+ .D(_0111_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _5260_ (.CLK(CTS_10),
+ .D(_0112_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _5261_ (.CLK(CTS_10),
+ .D(_0113_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[14] ));
+ sky130_fd_sc_hd__dfxtp_2 _5262_ (.CLK(CTS_10),
+ .D(_0114_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[15] ));
+ sky130_fd_sc_hd__dfxtp_2 _5263_ (.CLK(CTS_10),
+ .D(_0115_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[16] ));
+ sky130_fd_sc_hd__dfxtp_2 _5264_ (.CLK(CTS_10),
+ .D(_0116_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[17] ));
+ sky130_fd_sc_hd__dfxtp_2 _5265_ (.CLK(CTS_10),
+ .D(_0117_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[18] ));
+ sky130_fd_sc_hd__dfxtp_2 _5266_ (.CLK(CTS_10),
+ .D(_0118_),
+ .Q(\Config_inst.INST_config_UART.CRCReg[19] ));
+ sky130_fd_sc_hd__dfxtp_2 _5267_ (.CLK(CTS_10),
+ .D(_0119_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[0] ));
+ sky130_fd_sc_hd__dfxtp_2 _5268_ (.CLK(CTS_10),
+ .D(_0120_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[1] ));
+ sky130_fd_sc_hd__dfxtp_2 _5269_ (.CLK(CTS_10),
+ .D(_0121_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[2] ));
+ sky130_fd_sc_hd__dfxtp_2 _5270_ (.CLK(CTS_10),
+ .D(_0122_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[3] ));
+ sky130_fd_sc_hd__dfxtp_2 _5271_ (.CLK(CTS_10),
+ .D(_0123_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[4] ));
+ sky130_fd_sc_hd__dfxtp_2 _5272_ (.CLK(CTS_10),
+ .D(_0124_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[5] ));
+ sky130_fd_sc_hd__dfxtp_2 _5273_ (.CLK(CTS_10),
+ .D(_0125_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[6] ));
+ sky130_fd_sc_hd__dfxtp_2 _5274_ (.CLK(CTS_10),
+ .D(_0931_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[7] ));
+ sky130_fd_sc_hd__dfxtp_2 _5275_ (.CLK(CTS_10),
+ .D(_0127_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[8] ));
+ sky130_fd_sc_hd__dfxtp_2 _5276_ (.CLK(CTS_10),
+ .D(_0128_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[9] ));
+ sky130_fd_sc_hd__dfxtp_2 _5277_ (.CLK(CTS_10),
+ .D(_0129_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[10] ));
+ sky130_fd_sc_hd__dfxtp_2 _5278_ (.CLK(CTS_10),
+ .D(_0130_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[11] ));
+ sky130_fd_sc_hd__dfxtp_2 _5279_ (.CLK(CTS_10),
+ .D(_0131_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[12] ));
+ sky130_fd_sc_hd__dfxtp_2 _5280_ (.CLK(CTS_10),
+ .D(_0132_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[13] ));
+ sky130_fd_sc_hd__dfxtp_2 _5281_ (.CLK(CTS_10),
+ .D(_1960_),
+ .Q(\Config_inst.INST_config_UART.TimeToSendCounter[14] ));
+ sky130_fd_sc_hd__dlxbp_1 _5282_ (.D(_0001_),
+ .GATE(_0001_),
+ .Q(latch_fabric_strobe),
+ .Q_N());
+ sky130_fd_sc_hd__dlxbp_1 _5283_ (.D(_0000_),
+ .GATE(_0000_),
+ .Q(latch_config_strobe),
+ .Q_N());
+ BlockRAM_1KB Inst_BlockRAM_0 (.C5(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_C_O2 ),
+ .C4(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_C_O3 ),
+ .C3(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O0 ),
+ .C2(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O1 ),
+ .C1(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O2 ),
+ .C0(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O3 ),
+ .wr_data({ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O3 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O3 }),
+ .wr_addr({ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O3 }),
+ .rd_data({ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I3 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I3 }),
+ .rd_addr({ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O3 }),
+ .clk(CTS_30));
+ BlockRAM_1KB Inst_BlockRAM_1 (.C5(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_C_O2 ),
+ .C4(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_C_O3 ),
+ .C3(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O0 ),
+ .C2(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O1 ),
+ .C1(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O2 ),
+ .C0(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O3 ),
+ .wr_data({ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O3 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O3 }),
+ .wr_addr({ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O3 }),
+ .rd_data({ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I3 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I3 }),
+ .rd_addr({ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O3 }),
+ .clk(CTS_25));
+ BlockRAM_1KB Inst_BlockRAM_2 (.C5(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_C_O2 ),
+ .C4(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_C_O3 ),
+ .C3(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O0 ),
+ .C2(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O1 ),
+ .C1(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O2 ),
+ .C0(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O3 ),
+ .wr_data({ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O3 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O3 }),
+ .wr_addr({ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O3 }),
+ .rd_data({ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I3 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I3 }),
+ .rd_addr({ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O3 }),
+ .clk(CTS_22));
+ BlockRAM_1KB Inst_BlockRAM_3 (.C5(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_C_O2 ),
+ .C4(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_C_O3 ),
+ .C3(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O0 ),
+ .C2(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O1 ),
+ .C1(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O2 ),
+ .C0(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O3 ),
+ .wr_data({ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O3 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O3 }),
+ .wr_addr({ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O3 }),
+ .rd_data({ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I3 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I3 }),
+ .rd_addr({ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O3 }),
+ .clk(CTS_19));
+ BlockRAM_1KB Inst_BlockRAM_4 (.C5(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_C_O2 ),
+ .C4(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_C_O3 ),
+ .C3(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O0 ),
+ .C2(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O1 ),
+ .C1(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O2 ),
+ .C0(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O3 ),
+ .wr_data({ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O3 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O3 }),
+ .wr_addr({ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O3 }),
+ .rd_data({ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I3 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I3 }),
+ .rd_addr({ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O3 }),
+ .clk(CTS_16));
+ BlockRAM_1KB Inst_BlockRAM_5 (.C5(FE_OFN72_la_data_out_3),
+ .C4(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_C_O3 ),
+ .C3(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O0 ),
+ .C2(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O1 ),
+ .C1(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O2 ),
+ .C0(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O3 ),
+ .wr_data({ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O3 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O3 }),
+ .wr_addr({ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O3 }),
+ .rd_data({ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I3 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I3 }),
+ .rd_addr({ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O3 }),
+ .clk(CTS_38));
+ BlockRAM_1KB Inst_BlockRAM_6 (.C5(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_C_O2 ),
+ .C4(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_C_O3 ),
+ .C3(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O0 ),
+ .C2(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O1 ),
+ .C1(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O2 ),
+ .C0(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O3 ),
+ .wr_data({ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O3 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O3 }),
+ .wr_addr({ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O3 }),
+ .rd_data({ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I3 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I3 }),
+ .rd_addr({ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O3 }),
+ .clk(CTS_40));
+ BlockRAM_1KB Inst_BlockRAM_7 (.C5(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_C_O2 ),
+ .C4(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_C_O3 ),
+ .C3(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O0 ),
+ .C2(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O1 ),
+ .C1(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O2 ),
+ .C0(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O3 ),
+ .wr_data({ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O3 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O0 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O1 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O2 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O3 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O0 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O1 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O2 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O3 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O0 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O1 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O2 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O3 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O0 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O1 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O2 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O3 }),
+ .wr_addr({ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O3 }),
+ .rd_data({ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I3 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I0 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I1 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I2 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I3 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I0 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I1 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I2 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I3 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I0 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I1 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I2 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I3 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I0 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I1 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I2 ,
+ \Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I3 }),
+ .rd_addr({ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O0 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O1 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O2 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O3 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O0 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O1 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O2 ,
+ \Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O3 }),
+ .clk(CTS_5));
+ W_IO \Inst_eFPGA.Tile_X0Y10_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_9.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_9.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y10_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y10_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y10_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y10_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y10_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y10_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y10_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y10_A_config_C_bit0 ),
+ .B_O_top(\Inst_eFPGA.Tile_X0Y10_B_O_top ),
+ .B_T_top(io_oeb[19]),
+ .B_I_top(io_out[19]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y11_UserCLKo ),
+ .A_O_top(\Inst_eFPGA.Tile_X0Y10_A_O_top ),
+ .A_T_top(io_oeb[20]),
+ .A_I_top(io_out[20]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y10_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y10_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y11_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_10.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_10.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y11_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y11_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y11_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y11_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y11_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y11_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y11_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y11_A_config_C_bit0 ),
+ .B_O_top(\Inst_eFPGA.Tile_X0Y11_B_O_top ),
+ .B_T_top(io_oeb[17]),
+ .B_I_top(io_out[17]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y12_UserCLKo ),
+ .A_O_top(\Inst_eFPGA.Tile_X0Y11_A_O_top ),
+ .A_T_top(io_oeb[18]),
+ .A_I_top(io_out[18]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y11_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y11_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y12_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_11.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_11.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y12_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y12_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y12_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y12_B_config_C_bit0 ),
+ .A_config_C_bit3(FE_OFN70_la_data_out_4),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y12_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y12_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y12_A_config_C_bit0 ),
+ .B_O_top(\Inst_eFPGA.Tile_X0Y12_B_O_top ),
+ .B_T_top(io_oeb[15]),
+ .B_I_top(io_out[15]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y13_UserCLKo ),
+ .A_O_top(FE_OFN176_Inst_eFPGA_Tile_X0Y12_A_O_top),
+ .A_T_top(io_oeb[16]),
+ .A_I_top(io_out[16]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y12_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y12_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y13_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_12.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_12.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y13_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y13_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y13_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y13_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y13_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y13_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y13_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y13_A_config_C_bit0 ),
+ .B_O_top(\Inst_eFPGA.Tile_X0Y13_B_O_top ),
+ .B_T_top(io_oeb[13]),
+ .B_I_top(io_out[13]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y14_UserCLKo ),
+ .A_O_top(\Inst_eFPGA.Tile_X0Y13_A_O_top ),
+ .A_T_top(io_oeb[14]),
+ .A_I_top(io_out[14]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y13_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y13_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y14_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_13.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_13.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y14_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y14_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y14_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y14_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y14_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y14_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y14_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y14_A_config_C_bit0 ),
+ .B_O_top(\Inst_eFPGA.Tile_X0Y14_B_O_top ),
+ .B_T_top(io_oeb[11]),
+ .B_I_top(io_out[11]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y15_UserCLKo ),
+ .A_O_top(\Inst_eFPGA.Tile_X0Y14_A_O_top ),
+ .A_T_top(io_oeb[12]),
+ .A_I_top(io_out[12]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y14_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y14_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y15_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_14.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_14.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y15_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y15_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y15_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y15_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y15_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y15_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y15_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y15_A_config_C_bit0 ),
+ .B_O_top(\Inst_eFPGA.Tile_X0Y15_B_O_top ),
+ .B_T_top(io_oeb[9]),
+ .B_I_top(io_out[9]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y16_UserCLKo ),
+ .A_O_top(\Inst_eFPGA.Tile_X0Y15_A_O_top ),
+ .A_T_top(io_oeb[10]),
+ .A_I_top(io_out[10]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y15_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y15_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y16_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_0.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_0.FrameStrobe_O[4] ,
+ FE_OFN172_Inst_Frame_Select_0_FrameStrobe_O_3,
+ FE_OFN171_Inst_Frame_Select_0_FrameStrobe_O_2,
+ FE_OFN170_Inst_Frame_Select_0_FrameStrobe_O_1,
+ FE_OFN169_Inst_Frame_Select_0_FrameStrobe_O_0 }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_15.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_15.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y16_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y16_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y16_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y16_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y16_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y16_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y16_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y16_A_config_C_bit0 ),
+ .B_O_top(\Inst_eFPGA.Tile_X0Y16_B_O_top ),
+ .B_T_top(io_oeb[7]),
+ .B_I_top(io_out[7]),
+ .UserCLK(CTS_2),
+ .A_O_top(\Inst_eFPGA.Tile_X0Y16_A_O_top ),
+ .A_T_top(io_oeb[8]),
+ .A_I_top(io_out[8]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y16_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y16_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y1_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_0.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_0.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y1_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y1_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y1_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y1_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y1_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y1_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y1_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y1_A_config_C_bit0 ),
+ .B_O_top(io_in[37]),
+ .B_T_top(io_oeb[37]),
+ .B_I_top(io_out[37]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y2_UserCLKo ),
+ .A_O_top(_1996_),
+ .A_T_top(\Inst_eFPGA.Tile_X0Y1_A_T_top ),
+ .A_I_top(\Inst_eFPGA.Tile_X0Y1_A_I_top ),
+ .W6END({ \Inst_eFPGA.Tile_X1Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y1_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y1_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y2_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_1.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_1.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y2_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y2_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y2_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y2_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y2_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y2_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y2_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y2_A_config_C_bit0 ),
+ .B_O_top(io_in[35]),
+ .B_T_top(io_oeb[35]),
+ .B_I_top(io_out[35]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y3_UserCLKo ),
+ .A_O_top(io_in[36]),
+ .A_T_top(io_oeb[36]),
+ .A_I_top(io_out[36]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y2_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y2_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y3_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_2.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_2.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y3_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y3_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y3_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y3_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y3_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y3_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y3_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y3_A_config_C_bit0 ),
+ .B_O_top(io_in[33]),
+ .B_T_top(io_oeb[33]),
+ .B_I_top(io_out[33]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y4_UserCLKo ),
+ .A_O_top(io_in[34]),
+ .A_T_top(io_oeb[34]),
+ .A_I_top(io_out[34]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y3_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y3_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y4_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_3.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_3.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y4_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y4_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y4_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y4_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y4_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y4_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y4_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y4_A_config_C_bit0 ),
+ .B_O_top(io_in[31]),
+ .B_T_top(io_oeb[31]),
+ .B_I_top(io_out[31]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y5_UserCLKo ),
+ .A_O_top(io_in[32]),
+ .A_T_top(io_oeb[32]),
+ .A_I_top(io_out[32]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y4_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y4_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y5_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_4.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_4.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y5_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y5_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y5_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y5_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y5_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y5_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y5_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y5_A_config_C_bit0 ),
+ .B_O_top(io_in[29]),
+ .B_T_top(io_oeb[29]),
+ .B_I_top(io_out[29]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y6_UserCLKo ),
+ .A_O_top(io_in[30]),
+ .A_T_top(io_oeb[30]),
+ .A_I_top(io_out[30]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y5_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y5_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y6_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_5.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_5.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y6_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y6_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y6_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y6_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y6_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y6_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y6_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y6_A_config_C_bit0 ),
+ .B_O_top(io_in[27]),
+ .B_T_top(io_oeb[27]),
+ .B_I_top(io_out[27]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y7_UserCLKo ),
+ .A_O_top(io_in[28]),
+ .A_T_top(io_oeb[28]),
+ .A_I_top(io_out[28]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y6_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y6_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y7_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_6.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_6.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y7_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y7_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y7_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y7_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y7_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y7_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y7_A_config_C_bit1 ),
+ .A_config_C_bit0(la_data_out[6]),
+ .B_O_top(io_in[25]),
+ .B_T_top(io_oeb[25]),
+ .B_I_top(io_out[25]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y8_UserCLKo ),
+ .A_O_top(io_in[26]),
+ .A_T_top(io_oeb[26]),
+ .A_I_top(io_out[26]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y7_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y7_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y8_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_7.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_7.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y8_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y8_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y8_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y8_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y8_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y8_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y8_A_config_C_bit1 ),
+ .A_config_C_bit0(\Inst_eFPGA.Tile_X0Y8_A_config_C_bit0 ),
+ .B_O_top(\Inst_eFPGA.Tile_X0Y8_B_O_top ),
+ .B_T_top(io_oeb[23]),
+ .B_I_top(io_out[23]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y9_UserCLKo ),
+ .A_O_top(\Inst_eFPGA.Tile_X0Y8_A_O_top ),
+ .A_T_top(io_oeb[24]),
+ .A_I_top(io_out[24]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y8_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y8_UserCLKo ));
+ W_IO \Inst_eFPGA.Tile_X0Y9_W_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X0Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[0] }),
+ .FrameData({ \Inst_Frame_Data_Reg_8.FrameData_O[31] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[30] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[29] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[28] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[27] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[26] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[25] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[24] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[23] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[22] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[21] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[20] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[19] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[18] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[17] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[16] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[15] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[14] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[13] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[12] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[11] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[10] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[9] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[8] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[7] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[6] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[5] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[4] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[3] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[2] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[1] ,
+ \Inst_Frame_Data_Reg_8.FrameData_O[0] }),
+ .B_config_C_bit3(\Inst_eFPGA.Tile_X0Y9_B_config_C_bit3 ),
+ .B_config_C_bit2(\Inst_eFPGA.Tile_X0Y9_B_config_C_bit2 ),
+ .B_config_C_bit1(\Inst_eFPGA.Tile_X0Y9_B_config_C_bit1 ),
+ .B_config_C_bit0(\Inst_eFPGA.Tile_X0Y9_B_config_C_bit0 ),
+ .A_config_C_bit3(\Inst_eFPGA.Tile_X0Y9_A_config_C_bit3 ),
+ .A_config_C_bit2(\Inst_eFPGA.Tile_X0Y9_A_config_C_bit2 ),
+ .A_config_C_bit1(\Inst_eFPGA.Tile_X0Y9_A_config_C_bit1 ),
+ .A_config_C_bit0(la_data_out[5]),
+ .B_O_top(\Inst_eFPGA.Tile_X0Y9_B_O_top ),
+ .B_T_top(io_oeb[21]),
+ .B_I_top(io_out[21]),
+ .UserCLK(\Inst_eFPGA.Tile_X0Y10_UserCLKo ),
+ .A_O_top(\Inst_eFPGA.Tile_X0Y9_A_O_top ),
+ .A_T_top(io_oeb[22]),
+ .A_I_top(io_out[22]),
+ .W6END({ \Inst_eFPGA.Tile_X1Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X1Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X1Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X1Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X1Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_W1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X0Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X0Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X0Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X0Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X0Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y9_E1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X0Y9_UserCLKo ));
+ N_term_RAM_IO \Inst_eFPGA.Tile_X10Y0_N_term_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y0_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y0_S1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y0_UserCLKo ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y1_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y10_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y10_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y10_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y10_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y10_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y10_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y11_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y10_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y10_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y11_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y11_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y11_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y11_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y11_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y11_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y11_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y12_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y11_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y11_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y12_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y12_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y12_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y12_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y12_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y12_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y12_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y13_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y12_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y12_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y13_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y13_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y13_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y13_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y13_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y13_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y13_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y14_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y13_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y13_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y14_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y14_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y14_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y14_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y14_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y14_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y14_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y15_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y14_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y14_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y15_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y15_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y15_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y15_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y15_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y15_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y15_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y16_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y15_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y15_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y16_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y16_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y16_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y16_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y16_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y16_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y16_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y17_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y16_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y17_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y16_UserCLKo ));
+ S_term_RAM_IO \Inst_eFPGA.Tile_X10Y17_S_term_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y17_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_10.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[4] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[3] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[2] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[1] ,
+ \Inst_Frame_Select_10.FrameStrobe_O[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_S1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y17_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y17_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y17_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y17_UserCLKo ),
+ .UserCLK(CTS_35));
+ RAM_IO \Inst_eFPGA.Tile_X10Y1_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y1_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y1_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y1_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y1_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y1_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y1_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y2_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y1_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y0_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y0_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y0_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y1_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y2_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y2_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y2_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y2_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y2_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y2_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y2_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y3_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y2_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y2_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y3_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y3_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y3_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y3_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y3_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y3_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y3_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y4_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y3_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y3_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y4_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y4_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y4_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y4_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y4_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y4_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y4_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y5_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y4_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y4_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y5_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y5_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y5_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y5_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y5_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y5_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(FE_OFN72_la_data_out_3),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y5_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y6_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y5_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y5_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y6_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y6_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y6_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y6_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y6_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y6_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y6_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y7_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y6_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y6_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y7_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y7_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y7_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y7_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y7_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y7_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y7_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y8_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y7_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y7_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y8_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y8_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y8_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y8_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y8_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y8_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y8_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y9_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y8_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y8_UserCLKo ));
+ RAM_IO \Inst_eFPGA.Tile_X10Y9_RAM_IO (.FrameStrobe_O({ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X10Y10_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X10Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X10Y9_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X9Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[0] }),
+ .Config_accessC_bit3(\Inst_eFPGA.Tile_X10Y9_Config_accessC_bit3 ),
+ .Config_accessC_bit2(\Inst_eFPGA.Tile_X10Y9_Config_accessC_bit2 ),
+ .Config_accessC_bit1(\Inst_eFPGA.Tile_X10Y9_Config_accessC_bit1 ),
+ .Config_accessC_bit0(\Inst_eFPGA.Tile_X10Y9_Config_accessC_bit0 ),
+ .FAB2RAM_C_O3(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_C_O3 ),
+ .FAB2RAM_C_O2(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_C_O2 ),
+ .FAB2RAM_C_O1(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_C_O1 ),
+ .FAB2RAM_C_O0(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_C_O0 ),
+ .FAB2RAM_A1_O3(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O3 ),
+ .FAB2RAM_A1_O2(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O2 ),
+ .FAB2RAM_A1_O1(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O1 ),
+ .FAB2RAM_A1_O0(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_A1_O0 ),
+ .FAB2RAM_A0_O3(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O3 ),
+ .FAB2RAM_A0_O2(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O2 ),
+ .FAB2RAM_A0_O1(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O1 ),
+ .FAB2RAM_A0_O0(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_A0_O0 ),
+ .FAB2RAM_D3_O3(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O3 ),
+ .FAB2RAM_D3_O2(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O2 ),
+ .FAB2RAM_D3_O1(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O1 ),
+ .FAB2RAM_D3_O0(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D3_O0 ),
+ .FAB2RAM_D2_O3(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O3 ),
+ .FAB2RAM_D2_O2(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O2 ),
+ .FAB2RAM_D2_O1(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O1 ),
+ .FAB2RAM_D2_O0(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D2_O0 ),
+ .FAB2RAM_D1_O3(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O3 ),
+ .FAB2RAM_D1_O2(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O2 ),
+ .FAB2RAM_D1_O1(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O1 ),
+ .FAB2RAM_D1_O0(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D1_O0 ),
+ .FAB2RAM_D0_O3(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O3 ),
+ .FAB2RAM_D0_O2(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O2 ),
+ .FAB2RAM_D0_O1(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O1 ),
+ .FAB2RAM_D0_O0(\Inst_eFPGA.Tile_X10Y9_FAB2RAM_D0_O0 ),
+ .RAM2FAB_D3_I3(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I3 ),
+ .RAM2FAB_D3_I2(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I2 ),
+ .RAM2FAB_D3_I1(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I1 ),
+ .RAM2FAB_D3_I0(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D3_I0 ),
+ .RAM2FAB_D2_I3(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I3 ),
+ .RAM2FAB_D2_I2(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I2 ),
+ .RAM2FAB_D2_I1(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I1 ),
+ .RAM2FAB_D2_I0(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D2_I0 ),
+ .RAM2FAB_D1_I3(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I3 ),
+ .RAM2FAB_D1_I2(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I2 ),
+ .RAM2FAB_D1_I1(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I1 ),
+ .RAM2FAB_D1_I0(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D1_I0 ),
+ .UserCLK(\Inst_eFPGA.Tile_X10Y10_UserCLKo ),
+ .RAM2FAB_D0_I3(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I3 ),
+ .RAM2FAB_D0_I2(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I2 ),
+ .RAM2FAB_D0_I1(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I1 ),
+ .RAM2FAB_D0_I0(\Inst_eFPGA.Tile_X10Y9_RAM2FAB_D0_I0 ),
+ .W6BEG({ \Inst_eFPGA.Tile_X10Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X10Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X10Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X10Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X10Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_W1BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X10Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X10Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X10Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X10Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_S1BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X10Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X10Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X10Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X10Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X9Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X9Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X9Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X9Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X9Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_E1BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X10Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X10Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X10Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X10Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_N1BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X10Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X10Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X10Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X10Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X10Y9_UserCLKo ));
+ N_term_single \Inst_eFPGA.Tile_X1Y0_N_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y0_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y0_S1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y1_Co ),
+ .N4END({ \Inst_eFPGA.Tile_X1Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y0_UserCLKo ),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y10_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y10_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y11_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y10_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y10_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y10_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y10_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y11_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y10_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y10_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y11_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y11_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y12_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y11_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y11_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y11_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y11_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y12_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y11_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y11_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y12_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y12_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y13_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y12_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y12_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y12_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y12_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y13_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y12_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y12_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y13_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y13_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y14_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y13_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y13_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y13_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y13_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y14_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y13_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y13_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y14_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y14_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y15_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y14_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y14_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y14_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y14_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y15_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y14_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y14_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y15_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y15_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y16_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y15_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y15_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y15_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y15_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y16_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y15_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y15_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y16_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y16_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y17_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y16_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y16_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y16_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y16_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y17_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y17_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y16_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y16_UserCLKo ));
+ S_term_single \Inst_eFPGA.Tile_X1Y17_S_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y17_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_1.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[4] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[3] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[2] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[1] ,
+ \Inst_Frame_Select_1.FrameStrobe_O[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_S1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y17_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y17_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y17_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y17_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y17_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y17_UserCLKo ),
+ .UserCLK(CTS_35));
+ LUT4AB \Inst_eFPGA.Tile_X1Y1_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y1_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y2_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y0_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y0_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y0_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y0_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y1_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y1_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y1_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y1_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y2_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y1_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y2_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y2_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y3_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y2_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y2_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y2_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y2_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y3_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y2_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y2_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y3_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y3_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y4_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y3_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y3_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y3_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y3_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y4_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y3_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y3_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y4_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y4_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y5_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y4_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y4_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y4_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y4_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y5_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y4_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y4_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y5_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y5_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y6_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y5_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y5_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y5_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y5_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y6_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y5_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y5_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y6_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y6_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y7_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y6_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y6_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y6_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y6_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y7_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y6_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y6_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y7_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y7_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y8_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y7_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y7_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y7_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y7_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y8_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y7_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y7_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y8_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y8_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y9_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y8_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y8_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y8_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y8_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y9_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y8_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y8_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X1Y9_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X1Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X0Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X0Y9_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X1Y10_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X2Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X2Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X2Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X2Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X2Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X1Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X1Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X1Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X1Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X1Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X1Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X1Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X1Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X1Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X1Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X1Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X1Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X1Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X1Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X1Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X0Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y9_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X0Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y9_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X0Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X0Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y9_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X0Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X0Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X0Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X0Y9_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X1Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X1Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X1Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X1Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X1Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X1Y10_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X1Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X1Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X1Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X1Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X1Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X1Y9_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X1Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X1Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X1Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X1Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X1Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X1Y9_UserCLKo ));
+ N_term_single \Inst_eFPGA.Tile_X2Y0_N_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y0_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y0_S1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y1_Co ),
+ .N4END({ \Inst_eFPGA.Tile_X2Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y0_UserCLKo ),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y10_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y10_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y11_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y10_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y11_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y10_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y10_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y11_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y11_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y12_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y11_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y12_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y11_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y11_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y12_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y12_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y13_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y12_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y13_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y12_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y12_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y13_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y13_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y14_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y13_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y14_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y13_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y13_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y14_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y14_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y15_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y14_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y15_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y14_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y14_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y15_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y15_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y16_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y15_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y16_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y15_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y15_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y16_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y16_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y17_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y16_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y17_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y17_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y16_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y16_UserCLKo ));
+ S_term_single \Inst_eFPGA.Tile_X2Y17_S_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y17_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_2.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[4] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[3] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[2] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[1] ,
+ \Inst_Frame_Select_2.FrameStrobe_O[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_S1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y17_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y17_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y17_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y17_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y17_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y17_UserCLKo ),
+ .UserCLK(CTS_35));
+ LUT4AB \Inst_eFPGA.Tile_X2Y1_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y1_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y2_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y0_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y0_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y0_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y0_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y1_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y2_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y1_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y2_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y2_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y3_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y2_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y3_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y2_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y2_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y3_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y3_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y4_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y3_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y4_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y3_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y3_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y4_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y4_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y5_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y4_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y5_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y4_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y4_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y5_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y5_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y6_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y5_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y6_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y5_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y5_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y6_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y6_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y7_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y6_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y7_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y6_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y6_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y7_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y7_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y8_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y7_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y8_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y7_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y7_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y8_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y8_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y9_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y8_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y9_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y8_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y8_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X2Y9_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X2Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X1Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X1Y9_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X2Y10_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X3Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X3Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X3Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X3Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X3Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X2Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X2Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X2Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X2Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X2Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X2Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X2Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X2Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X2Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X2Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X2Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X2Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X2Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X2Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X2Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X1Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X1Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X1Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X1Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X1Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X1Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X1Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X1Y9_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X2Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X2Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X2Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X2Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X2Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X2Y10_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X2Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X2Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X2Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X2Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X2Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X2Y9_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X2Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X2Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X2Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X2Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X2Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X2Y9_UserCLKo ));
+ N_term_single2 \Inst_eFPGA.Tile_X3Y0_N_term_single2 (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y0_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y0_S1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y0_UserCLKo ),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y1_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y10_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y10_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y11_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y10_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y10_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y11_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y11_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y12_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y11_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y11_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y12_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y12_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y13_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y12_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y12_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y13_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y13_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y14_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y13_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y13_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y14_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y14_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y15_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y14_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y14_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y15_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y15_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y16_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y15_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y15_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y16_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y16_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y17_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y16_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y17_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y16_UserCLKo ));
+ S_term_single2 \Inst_eFPGA.Tile_X3Y17_S_term_single2 (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y17_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_3.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[4] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[3] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[2] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[1] ,
+ \Inst_Frame_Select_3.FrameStrobe_O[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_S4BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_SS4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_S1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y17_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y17_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y17_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y17_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y17_UserCLKo ),
+ .UserCLK(CTS_35));
+ RegFile \Inst_eFPGA.Tile_X3Y1_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y1_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y2_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y0_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y0_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y0_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y0_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y1_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y1_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y2_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y2_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y3_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y2_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y2_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y3_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y3_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y4_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y3_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y3_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y4_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y4_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y5_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y4_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y4_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y5_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y5_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y6_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y5_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y5_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y6_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y6_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y7_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y6_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y6_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y7_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y7_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y8_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y7_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y7_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y8_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y8_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y9_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y8_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y8_UserCLKo ));
+ RegFile \Inst_eFPGA.Tile_X3Y9_RegFile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X3Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X2Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X2Y9_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X3Y10_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X4Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X4Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X4Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X4Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X4Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X3Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X3Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X3Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X3Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X3Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X3Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X3Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X3Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X3Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X3Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X3Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X3Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X3Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X3Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X3Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X2Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X2Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X2Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X2Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X2Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X2Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X2Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X2Y9_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X3Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X3Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X3Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X3Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X3Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_E1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X3Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X3Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X3Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X3Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X3Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_N1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X3Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X3Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X3Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X3Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X3Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X3Y9_UserCLKo ));
+ N_term_single \Inst_eFPGA.Tile_X4Y0_N_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y0_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y0_S1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y1_Co ),
+ .N4END({ \Inst_eFPGA.Tile_X4Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y0_UserCLKo ),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y10_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y10_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y11_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y10_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y11_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y10_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y10_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y11_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y11_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y12_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y11_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y12_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y11_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y11_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y12_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y12_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y13_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y12_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y13_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y12_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y12_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y13_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y13_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y14_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y13_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y14_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y13_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y13_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y14_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y14_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y15_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y14_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y15_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y14_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y14_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y15_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y15_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y16_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y15_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y16_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y15_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y15_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y16_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y16_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y17_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y16_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y17_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y17_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y16_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y16_UserCLKo ));
+ S_term_single \Inst_eFPGA.Tile_X4Y17_S_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y17_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_4.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[4] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[3] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[2] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[1] ,
+ \Inst_Frame_Select_4.FrameStrobe_O[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_S1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y17_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y17_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y17_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y17_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y17_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y17_UserCLKo ),
+ .UserCLK(CTS_35));
+ LUT4AB \Inst_eFPGA.Tile_X4Y1_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y1_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y2_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y0_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y0_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y0_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y0_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y1_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y2_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y1_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y2_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y2_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y3_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y2_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y3_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y2_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y2_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y3_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y3_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y4_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y3_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y4_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y3_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y3_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y4_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y4_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y5_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y4_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y5_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y4_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y4_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y5_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y5_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y6_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y5_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y6_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y5_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y5_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y6_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y6_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y7_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y6_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y7_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y6_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y6_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y7_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y7_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y8_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y7_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y8_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y7_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y7_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y8_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y8_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y9_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y8_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y9_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y8_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y8_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X4Y9_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X4Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X3Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X3Y9_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X4Y10_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X5Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X5Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X5Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X5Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X5Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X4Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X4Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X4Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X4Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X4Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X4Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X4Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X4Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X4Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X4Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X4Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X4Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X4Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X4Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X4Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X3Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X3Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X3Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X3Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X3Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X3Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X3Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X3Y9_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X4Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X4Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X4Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X4Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X4Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X4Y10_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X4Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X4Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X4Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X4Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X4Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X4Y9_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X4Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X4Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X4Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X4Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X4Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X4Y9_UserCLKo ));
+ N_term_single \Inst_eFPGA.Tile_X5Y0_N_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y0_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y0_S1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y1_Co ),
+ .N4END({ \Inst_eFPGA.Tile_X5Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y0_UserCLKo ),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y10_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y10_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y11_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y10_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y11_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y10_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y10_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y11_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y11_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y12_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y11_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y12_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y11_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y11_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y12_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y12_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y13_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y12_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y13_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y12_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y12_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y13_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y13_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y14_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y13_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y14_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y13_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y13_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y14_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y14_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y15_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y14_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y15_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y14_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y14_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y15_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y15_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y16_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y15_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y16_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y15_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y15_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y16_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y16_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y17_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y16_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y17_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y17_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y16_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y16_UserCLKo ));
+ S_term_single \Inst_eFPGA.Tile_X5Y17_S_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y17_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_5.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[4] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[3] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[2] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[1] ,
+ \Inst_Frame_Select_5.FrameStrobe_O[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_S1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y17_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y17_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y17_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y17_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y17_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y17_UserCLKo ),
+ .UserCLK(CTS_35));
+ LUT4AB \Inst_eFPGA.Tile_X5Y1_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y1_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y2_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y0_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y0_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y0_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y0_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y1_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y2_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y1_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y2_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y2_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y3_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y2_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y3_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y2_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y2_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y3_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y3_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y4_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y3_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y4_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y3_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y3_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y4_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y4_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y5_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y4_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y5_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y4_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y4_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y5_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y5_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y6_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y5_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y6_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y5_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y5_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y6_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y6_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y7_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y6_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y7_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y6_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y6_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y7_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y7_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y8_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y7_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y8_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y7_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y7_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y8_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y8_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y9_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y8_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y9_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y8_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y8_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X5Y9_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X5Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X4Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X4Y9_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X5Y10_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X6Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X6Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X6Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X6Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X6Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X5Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X5Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X5Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X5Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X5Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X5Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X5Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X5Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X5Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X5Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X5Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X5Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X5Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X5Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X5Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X4Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X4Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X4Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X4Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X4Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X4Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X4Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X4Y9_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X5Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X5Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X5Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X5Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X5Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X5Y10_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X5Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X5Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X5Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X5Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X5Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X5Y9_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X5Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X5Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X5Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X5Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X5Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X5Y9_UserCLKo ));
+ N_term_single \Inst_eFPGA.Tile_X6Y0_N_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y0_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y0_S1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y1_Co ),
+ .N4END({ \Inst_eFPGA.Tile_X6Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y0_UserCLKo ),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y10_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y10_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y11_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y10_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y11_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y10_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y10_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y11_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y11_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y12_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y11_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y12_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y11_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y11_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y12_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y12_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y13_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y12_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y13_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y12_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y12_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y13_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y13_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y14_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y13_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y14_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y13_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y13_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y14_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y14_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y15_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y14_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y15_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y14_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y14_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y15_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y15_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y16_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y15_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y16_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y15_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y15_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y16_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y16_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y17_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y16_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y17_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y17_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y16_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y16_UserCLKo ));
+ S_term_single \Inst_eFPGA.Tile_X6Y17_S_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y17_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_6.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[4] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[3] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[2] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[1] ,
+ \Inst_Frame_Select_6.FrameStrobe_O[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_S1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y17_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y17_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y17_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y17_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y17_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y17_UserCLKo ),
+ .UserCLK(CTS_35));
+ LUT4AB \Inst_eFPGA.Tile_X6Y1_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y1_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y2_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y0_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y0_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y0_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y0_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y1_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y2_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y1_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y2_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y2_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y3_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y2_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y3_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y2_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y2_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y3_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y3_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y4_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y3_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y4_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y3_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y3_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y4_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y4_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y5_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y4_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y5_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y4_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y4_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y5_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y5_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y6_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y5_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y6_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y5_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y5_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y6_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y6_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y7_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y6_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y7_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y6_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y6_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y7_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y7_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y8_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y7_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y8_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y7_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y7_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y8_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y8_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y9_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y8_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y9_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y8_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y8_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X6Y9_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X6Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X5Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X5Y9_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X6Y10_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X7Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X7Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X7Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X7Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X7Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X6Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X6Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X6Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X6Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X6Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X6Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X6Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X6Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X6Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X6Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X6Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X6Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X6Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X6Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X6Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X5Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X5Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X5Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X5Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X5Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X5Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X5Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X5Y9_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X6Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X6Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X6Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X6Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X6Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X6Y10_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X6Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X6Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X6Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X6Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X6Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X6Y9_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X6Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X6Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X6Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X6Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X6Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X6Y9_UserCLKo ));
+ N_term_DSP \Inst_eFPGA.Tile_X7Y0_N_term_DSP (.FrameStrobe_O({ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y0_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X7Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X7Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X7Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X7Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X7Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y0_S1BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X7Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X7Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X7Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X7Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X7Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X7Y0_UserCLKo ),
+ .UserCLK(\Inst_eFPGA.Tile_X7Y1_UserCLKo ));
+ DSP \Inst_eFPGA.Tile_X7Y11_X7Y12_DSP_tile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[0] }),
+ .bot_FrameData_O({ \Inst_eFPGA.Tile_X7Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[0] }),
+ .bot_FrameData({ \Inst_eFPGA.Tile_X6Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y12_FrameData_O[0] }),
+ .top_FrameData_O({ \Inst_eFPGA.Tile_X7Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[0] }),
+ .top_FrameData({ \Inst_eFPGA.Tile_X6Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y11_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X7Y13_UserCLKo ),
+ .bot_NN4END({ \Inst_eFPGA.Tile_X7Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[0] }),
+ .bot_N4END({ \Inst_eFPGA.Tile_X7Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[0] }),
+ .bot_N2END({ \Inst_eFPGA.Tile_X7Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[0] }),
+ .bot_N2MID({ \Inst_eFPGA.Tile_X7Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[0] }),
+ .bot_N1END({ \Inst_eFPGA.Tile_X7Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_N1BEG[0] }),
+ .bot_SS4BEG({ \Inst_eFPGA.Tile_X7Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[0] }),
+ .bot_S4BEG({ \Inst_eFPGA.Tile_X7Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[0] }),
+ .bot_S2BEGb({ \Inst_eFPGA.Tile_X7Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[0] }),
+ .bot_S2BEG({ \Inst_eFPGA.Tile_X7Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[0] }),
+ .bot_S1BEG({ \Inst_eFPGA.Tile_X7Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_S1BEG[0] }),
+ .bot_W6END({ \Inst_eFPGA.Tile_X8Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[0] }),
+ .bot_WW4END({ \Inst_eFPGA.Tile_X8Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[0] }),
+ .bot_W2END({ \Inst_eFPGA.Tile_X8Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[0] }),
+ .bot_W2MID({ \Inst_eFPGA.Tile_X8Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[0] }),
+ .bot_W1END({ \Inst_eFPGA.Tile_X8Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_W1BEG[0] }),
+ .bot_W6BEG({ \Inst_eFPGA.Tile_X7Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_W6BEG[0] }),
+ .bot_WW4BEG({ \Inst_eFPGA.Tile_X7Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_WW4BEG[0] }),
+ .bot_W2BEGb({ \Inst_eFPGA.Tile_X7Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEGb[0] }),
+ .bot_W2BEG({ \Inst_eFPGA.Tile_X7Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_W2BEG[0] }),
+ .bot_W1BEG({ \Inst_eFPGA.Tile_X7Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_W1BEG[0] }),
+ .bot_E6END({ \Inst_eFPGA.Tile_X6Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_E6BEG[0] }),
+ .bot_EE4END({ \Inst_eFPGA.Tile_X6Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_EE4BEG[0] }),
+ .bot_E2END({ \Inst_eFPGA.Tile_X6Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEGb[0] }),
+ .bot_E2MID({ \Inst_eFPGA.Tile_X6Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_E2BEG[0] }),
+ .bot_E1END({ \Inst_eFPGA.Tile_X6Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y12_E1BEG[0] }),
+ .bot_E6BEG({ \Inst_eFPGA.Tile_X7Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[0] }),
+ .bot_EE4BEG({ \Inst_eFPGA.Tile_X7Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[0] }),
+ .bot_E2BEGb({ \Inst_eFPGA.Tile_X7Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[0] }),
+ .bot_E2BEG({ \Inst_eFPGA.Tile_X7Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[0] }),
+ .bot_E1BEG({ \Inst_eFPGA.Tile_X7Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_E1BEG[0] }),
+ .top_W6END({ \Inst_eFPGA.Tile_X8Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[0] }),
+ .top_WW4END({ \Inst_eFPGA.Tile_X8Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[0] }),
+ .top_W2END({ \Inst_eFPGA.Tile_X8Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[0] }),
+ .top_W2MID({ \Inst_eFPGA.Tile_X8Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[0] }),
+ .top_W1END({ \Inst_eFPGA.Tile_X8Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_W1BEG[0] }),
+ .top_W6BEG({ \Inst_eFPGA.Tile_X7Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_W6BEG[0] }),
+ .top_WW4BEG({ \Inst_eFPGA.Tile_X7Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_WW4BEG[0] }),
+ .top_W2BEGb({ \Inst_eFPGA.Tile_X7Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEGb[0] }),
+ .top_W2BEG({ \Inst_eFPGA.Tile_X7Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_W2BEG[0] }),
+ .top_W1BEG({ \Inst_eFPGA.Tile_X7Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_W1BEG[0] }),
+ .top_E6END({ \Inst_eFPGA.Tile_X6Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_E6BEG[0] }),
+ .top_EE4END({ \Inst_eFPGA.Tile_X6Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_EE4BEG[0] }),
+ .top_E2END({ \Inst_eFPGA.Tile_X6Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEGb[0] }),
+ .top_E2MID({ \Inst_eFPGA.Tile_X6Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_E2BEG[0] }),
+ .top_E1END({ \Inst_eFPGA.Tile_X6Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y11_E1BEG[0] }),
+ .top_E6BEG({ \Inst_eFPGA.Tile_X7Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[0] }),
+ .top_EE4BEG({ \Inst_eFPGA.Tile_X7Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[0] }),
+ .top_E2BEGb({ \Inst_eFPGA.Tile_X7Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[0] }),
+ .top_E2BEG({ \Inst_eFPGA.Tile_X7Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[0] }),
+ .top_E1BEG({ \Inst_eFPGA.Tile_X7Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_E1BEG[0] }),
+ .top_SS4END({ \Inst_eFPGA.Tile_X7Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[0] }),
+ .top_S4END({ \Inst_eFPGA.Tile_X7Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[0] }),
+ .top_S2END({ \Inst_eFPGA.Tile_X7Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[0] }),
+ .top_S2MID({ \Inst_eFPGA.Tile_X7Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[0] }),
+ .top_S1END({ \Inst_eFPGA.Tile_X7Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_S1BEG[0] }),
+ .top_NN4BEG({ \Inst_eFPGA.Tile_X7Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[0] }),
+ .top_N4BEG({ \Inst_eFPGA.Tile_X7Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[0] }),
+ .top_N2BEGb({ \Inst_eFPGA.Tile_X7Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[0] }),
+ .top_N2BEG({ \Inst_eFPGA.Tile_X7Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[0] }),
+ .top_N1BEG({ \Inst_eFPGA.Tile_X7Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X7Y11_UserCLKo ));
+ DSP \Inst_eFPGA.Tile_X7Y13_X7Y14_DSP_tile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[0] }),
+ .bot_FrameData_O({ \Inst_eFPGA.Tile_X7Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[0] }),
+ .bot_FrameData({ \Inst_eFPGA.Tile_X6Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y14_FrameData_O[0] }),
+ .top_FrameData_O({ \Inst_eFPGA.Tile_X7Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[0] }),
+ .top_FrameData({ \Inst_eFPGA.Tile_X6Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y13_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X7Y15_UserCLKo ),
+ .bot_NN4END({ \Inst_eFPGA.Tile_X7Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[0] }),
+ .bot_N4END({ \Inst_eFPGA.Tile_X7Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[0] }),
+ .bot_N2END({ \Inst_eFPGA.Tile_X7Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[0] }),
+ .bot_N2MID({ \Inst_eFPGA.Tile_X7Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[0] }),
+ .bot_N1END({ \Inst_eFPGA.Tile_X7Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_N1BEG[0] }),
+ .bot_SS4BEG({ \Inst_eFPGA.Tile_X7Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[0] }),
+ .bot_S4BEG({ \Inst_eFPGA.Tile_X7Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[0] }),
+ .bot_S2BEGb({ \Inst_eFPGA.Tile_X7Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[0] }),
+ .bot_S2BEG({ \Inst_eFPGA.Tile_X7Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[0] }),
+ .bot_S1BEG({ \Inst_eFPGA.Tile_X7Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_S1BEG[0] }),
+ .bot_W6END({ \Inst_eFPGA.Tile_X8Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[0] }),
+ .bot_WW4END({ \Inst_eFPGA.Tile_X8Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[0] }),
+ .bot_W2END({ \Inst_eFPGA.Tile_X8Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[0] }),
+ .bot_W2MID({ \Inst_eFPGA.Tile_X8Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[0] }),
+ .bot_W1END({ \Inst_eFPGA.Tile_X8Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_W1BEG[0] }),
+ .bot_W6BEG({ \Inst_eFPGA.Tile_X7Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_W6BEG[0] }),
+ .bot_WW4BEG({ \Inst_eFPGA.Tile_X7Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_WW4BEG[0] }),
+ .bot_W2BEGb({ \Inst_eFPGA.Tile_X7Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEGb[0] }),
+ .bot_W2BEG({ \Inst_eFPGA.Tile_X7Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_W2BEG[0] }),
+ .bot_W1BEG({ \Inst_eFPGA.Tile_X7Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_W1BEG[0] }),
+ .bot_E6END({ \Inst_eFPGA.Tile_X6Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_E6BEG[0] }),
+ .bot_EE4END({ \Inst_eFPGA.Tile_X6Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_EE4BEG[0] }),
+ .bot_E2END({ \Inst_eFPGA.Tile_X6Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEGb[0] }),
+ .bot_E2MID({ \Inst_eFPGA.Tile_X6Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_E2BEG[0] }),
+ .bot_E1END({ \Inst_eFPGA.Tile_X6Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y14_E1BEG[0] }),
+ .bot_E6BEG({ \Inst_eFPGA.Tile_X7Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[0] }),
+ .bot_EE4BEG({ \Inst_eFPGA.Tile_X7Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[0] }),
+ .bot_E2BEGb({ \Inst_eFPGA.Tile_X7Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[0] }),
+ .bot_E2BEG({ \Inst_eFPGA.Tile_X7Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[0] }),
+ .bot_E1BEG({ \Inst_eFPGA.Tile_X7Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_E1BEG[0] }),
+ .top_W6END({ \Inst_eFPGA.Tile_X8Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[0] }),
+ .top_WW4END({ \Inst_eFPGA.Tile_X8Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[0] }),
+ .top_W2END({ \Inst_eFPGA.Tile_X8Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[0] }),
+ .top_W2MID({ \Inst_eFPGA.Tile_X8Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[0] }),
+ .top_W1END({ \Inst_eFPGA.Tile_X8Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_W1BEG[0] }),
+ .top_W6BEG({ \Inst_eFPGA.Tile_X7Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_W6BEG[0] }),
+ .top_WW4BEG({ \Inst_eFPGA.Tile_X7Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_WW4BEG[0] }),
+ .top_W2BEGb({ \Inst_eFPGA.Tile_X7Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEGb[0] }),
+ .top_W2BEG({ \Inst_eFPGA.Tile_X7Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_W2BEG[0] }),
+ .top_W1BEG({ \Inst_eFPGA.Tile_X7Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_W1BEG[0] }),
+ .top_E6END({ \Inst_eFPGA.Tile_X6Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_E6BEG[0] }),
+ .top_EE4END({ \Inst_eFPGA.Tile_X6Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_EE4BEG[0] }),
+ .top_E2END({ \Inst_eFPGA.Tile_X6Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEGb[0] }),
+ .top_E2MID({ \Inst_eFPGA.Tile_X6Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_E2BEG[0] }),
+ .top_E1END({ \Inst_eFPGA.Tile_X6Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y13_E1BEG[0] }),
+ .top_E6BEG({ \Inst_eFPGA.Tile_X7Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[0] }),
+ .top_EE4BEG({ \Inst_eFPGA.Tile_X7Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[0] }),
+ .top_E2BEGb({ \Inst_eFPGA.Tile_X7Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[0] }),
+ .top_E2BEG({ \Inst_eFPGA.Tile_X7Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[0] }),
+ .top_E1BEG({ \Inst_eFPGA.Tile_X7Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_E1BEG[0] }),
+ .top_SS4END({ \Inst_eFPGA.Tile_X7Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_SS4BEG[0] }),
+ .top_S4END({ \Inst_eFPGA.Tile_X7Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_S4BEG[0] }),
+ .top_S2END({ \Inst_eFPGA.Tile_X7Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEGb[0] }),
+ .top_S2MID({ \Inst_eFPGA.Tile_X7Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_S2BEG[0] }),
+ .top_S1END({ \Inst_eFPGA.Tile_X7Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_S1BEG[0] }),
+ .top_NN4BEG({ \Inst_eFPGA.Tile_X7Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_NN4BEG[0] }),
+ .top_N4BEG({ \Inst_eFPGA.Tile_X7Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_N4BEG[0] }),
+ .top_N2BEGb({ \Inst_eFPGA.Tile_X7Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEGb[0] }),
+ .top_N2BEG({ \Inst_eFPGA.Tile_X7Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_N2BEG[0] }),
+ .top_N1BEG({ \Inst_eFPGA.Tile_X7Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X7Y13_UserCLKo ));
+ DSP \Inst_eFPGA.Tile_X7Y15_X7Y16_DSP_tile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[0] }),
+ .bot_FrameData_O({ \Inst_eFPGA.Tile_X7Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[0] }),
+ .bot_FrameData({ \Inst_eFPGA.Tile_X6Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y16_FrameData_O[0] }),
+ .top_FrameData_O({ \Inst_eFPGA.Tile_X7Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[0] }),
+ .top_FrameData({ \Inst_eFPGA.Tile_X6Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y15_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X7Y17_UserCLKo ),
+ .bot_NN4END({ \Inst_eFPGA.Tile_X7Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[0] }),
+ .bot_N4END({ \Inst_eFPGA.Tile_X7Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[0] }),
+ .bot_N2END({ \Inst_eFPGA.Tile_X7Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[0] }),
+ .bot_N2MID({ \Inst_eFPGA.Tile_X7Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[0] }),
+ .bot_N1END({ \Inst_eFPGA.Tile_X7Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y17_N1BEG[0] }),
+ .bot_SS4BEG({ \Inst_eFPGA.Tile_X7Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[0] }),
+ .bot_S4BEG({ \Inst_eFPGA.Tile_X7Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[0] }),
+ .bot_S2BEGb({ \Inst_eFPGA.Tile_X7Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[0] }),
+ .bot_S2BEG({ \Inst_eFPGA.Tile_X7Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[0] }),
+ .bot_S1BEG({ \Inst_eFPGA.Tile_X7Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_S1BEG[0] }),
+ .bot_W6END({ \Inst_eFPGA.Tile_X8Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[0] }),
+ .bot_WW4END({ \Inst_eFPGA.Tile_X8Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[0] }),
+ .bot_W2END({ \Inst_eFPGA.Tile_X8Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[0] }),
+ .bot_W2MID({ \Inst_eFPGA.Tile_X8Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[0] }),
+ .bot_W1END({ \Inst_eFPGA.Tile_X8Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_W1BEG[0] }),
+ .bot_W6BEG({ \Inst_eFPGA.Tile_X7Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_W6BEG[0] }),
+ .bot_WW4BEG({ \Inst_eFPGA.Tile_X7Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_WW4BEG[0] }),
+ .bot_W2BEGb({ \Inst_eFPGA.Tile_X7Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEGb[0] }),
+ .bot_W2BEG({ \Inst_eFPGA.Tile_X7Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_W2BEG[0] }),
+ .bot_W1BEG({ \Inst_eFPGA.Tile_X7Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_W1BEG[0] }),
+ .bot_E6END({ \Inst_eFPGA.Tile_X6Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_E6BEG[0] }),
+ .bot_EE4END({ \Inst_eFPGA.Tile_X6Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_EE4BEG[0] }),
+ .bot_E2END({ \Inst_eFPGA.Tile_X6Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEGb[0] }),
+ .bot_E2MID({ \Inst_eFPGA.Tile_X6Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_E2BEG[0] }),
+ .bot_E1END({ \Inst_eFPGA.Tile_X6Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y16_E1BEG[0] }),
+ .bot_E6BEG({ \Inst_eFPGA.Tile_X7Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[0] }),
+ .bot_EE4BEG({ \Inst_eFPGA.Tile_X7Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[0] }),
+ .bot_E2BEGb({ \Inst_eFPGA.Tile_X7Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[0] }),
+ .bot_E2BEG({ \Inst_eFPGA.Tile_X7Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[0] }),
+ .bot_E1BEG({ \Inst_eFPGA.Tile_X7Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_E1BEG[0] }),
+ .top_W6END({ \Inst_eFPGA.Tile_X8Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[0] }),
+ .top_WW4END({ \Inst_eFPGA.Tile_X8Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[0] }),
+ .top_W2END({ \Inst_eFPGA.Tile_X8Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[0] }),
+ .top_W2MID({ \Inst_eFPGA.Tile_X8Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[0] }),
+ .top_W1END({ \Inst_eFPGA.Tile_X8Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_W1BEG[0] }),
+ .top_W6BEG({ \Inst_eFPGA.Tile_X7Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_W6BEG[0] }),
+ .top_WW4BEG({ \Inst_eFPGA.Tile_X7Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_WW4BEG[0] }),
+ .top_W2BEGb({ \Inst_eFPGA.Tile_X7Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEGb[0] }),
+ .top_W2BEG({ \Inst_eFPGA.Tile_X7Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_W2BEG[0] }),
+ .top_W1BEG({ \Inst_eFPGA.Tile_X7Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_W1BEG[0] }),
+ .top_E6END({ \Inst_eFPGA.Tile_X6Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_E6BEG[0] }),
+ .top_EE4END({ \Inst_eFPGA.Tile_X6Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_EE4BEG[0] }),
+ .top_E2END({ \Inst_eFPGA.Tile_X6Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEGb[0] }),
+ .top_E2MID({ \Inst_eFPGA.Tile_X6Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_E2BEG[0] }),
+ .top_E1END({ \Inst_eFPGA.Tile_X6Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y15_E1BEG[0] }),
+ .top_E6BEG({ \Inst_eFPGA.Tile_X7Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[0] }),
+ .top_EE4BEG({ \Inst_eFPGA.Tile_X7Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[0] }),
+ .top_E2BEGb({ \Inst_eFPGA.Tile_X7Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[0] }),
+ .top_E2BEG({ \Inst_eFPGA.Tile_X7Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[0] }),
+ .top_E1BEG({ \Inst_eFPGA.Tile_X7Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_E1BEG[0] }),
+ .top_SS4END({ \Inst_eFPGA.Tile_X7Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_SS4BEG[0] }),
+ .top_S4END({ \Inst_eFPGA.Tile_X7Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_S4BEG[0] }),
+ .top_S2END({ \Inst_eFPGA.Tile_X7Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEGb[0] }),
+ .top_S2MID({ \Inst_eFPGA.Tile_X7Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_S2BEG[0] }),
+ .top_S1END({ \Inst_eFPGA.Tile_X7Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_S1BEG[0] }),
+ .top_NN4BEG({ \Inst_eFPGA.Tile_X7Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_NN4BEG[0] }),
+ .top_N4BEG({ \Inst_eFPGA.Tile_X7Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_N4BEG[0] }),
+ .top_N2BEGb({ \Inst_eFPGA.Tile_X7Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEGb[0] }),
+ .top_N2BEG({ \Inst_eFPGA.Tile_X7Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_N2BEG[0] }),
+ .top_N1BEG({ \Inst_eFPGA.Tile_X7Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X7Y15_UserCLKo ));
+ S_term_DSP \Inst_eFPGA.Tile_X7Y17_S_term_DSP (.FrameStrobe_O({ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y17_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_7.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[4] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[3] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[2] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[1] ,
+ \Inst_Frame_Select_7.FrameStrobe_O[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X7Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_S4BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X7Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_SS4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X7Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X7Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X7Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_S1BEG[0] }),
+ .NN4BEG({ \Inst_eFPGA.Tile_X7Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y17_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X7Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y17_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X7Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X7Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y17_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X7Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y17_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X7Y17_UserCLKo ),
+ .UserCLK(CTS_35));
+ DSP \Inst_eFPGA.Tile_X7Y1_X7Y2_DSP_tile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[0] }),
+ .bot_FrameData_O({ \Inst_eFPGA.Tile_X7Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[0] }),
+ .bot_FrameData({ \Inst_eFPGA.Tile_X6Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y2_FrameData_O[0] }),
+ .top_FrameData_O({ \Inst_eFPGA.Tile_X7Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[0] }),
+ .top_FrameData({ \Inst_eFPGA.Tile_X6Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y1_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X7Y3_UserCLKo ),
+ .bot_NN4END({ \Inst_eFPGA.Tile_X7Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[0] }),
+ .bot_N4END({ \Inst_eFPGA.Tile_X7Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[0] }),
+ .bot_N2END({ \Inst_eFPGA.Tile_X7Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[0] }),
+ .bot_N2MID({ \Inst_eFPGA.Tile_X7Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[0] }),
+ .bot_N1END({ \Inst_eFPGA.Tile_X7Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_N1BEG[0] }),
+ .bot_SS4BEG({ \Inst_eFPGA.Tile_X7Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[0] }),
+ .bot_S4BEG({ \Inst_eFPGA.Tile_X7Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[0] }),
+ .bot_S2BEGb({ \Inst_eFPGA.Tile_X7Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[0] }),
+ .bot_S2BEG({ \Inst_eFPGA.Tile_X7Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[0] }),
+ .bot_S1BEG({ \Inst_eFPGA.Tile_X7Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_S1BEG[0] }),
+ .bot_W6END({ \Inst_eFPGA.Tile_X8Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[0] }),
+ .bot_WW4END({ \Inst_eFPGA.Tile_X8Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[0] }),
+ .bot_W2END({ \Inst_eFPGA.Tile_X8Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[0] }),
+ .bot_W2MID({ \Inst_eFPGA.Tile_X8Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[0] }),
+ .bot_W1END({ \Inst_eFPGA.Tile_X8Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_W1BEG[0] }),
+ .bot_W6BEG({ \Inst_eFPGA.Tile_X7Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_W6BEG[0] }),
+ .bot_WW4BEG({ \Inst_eFPGA.Tile_X7Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_WW4BEG[0] }),
+ .bot_W2BEGb({ \Inst_eFPGA.Tile_X7Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEGb[0] }),
+ .bot_W2BEG({ \Inst_eFPGA.Tile_X7Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_W2BEG[0] }),
+ .bot_W1BEG({ \Inst_eFPGA.Tile_X7Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_W1BEG[0] }),
+ .bot_E6END({ \Inst_eFPGA.Tile_X6Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_E6BEG[0] }),
+ .bot_EE4END({ \Inst_eFPGA.Tile_X6Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_EE4BEG[0] }),
+ .bot_E2END({ \Inst_eFPGA.Tile_X6Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEGb[0] }),
+ .bot_E2MID({ \Inst_eFPGA.Tile_X6Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_E2BEG[0] }),
+ .bot_E1END({ \Inst_eFPGA.Tile_X6Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y2_E1BEG[0] }),
+ .bot_E6BEG({ \Inst_eFPGA.Tile_X7Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[0] }),
+ .bot_EE4BEG({ \Inst_eFPGA.Tile_X7Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[0] }),
+ .bot_E2BEGb({ \Inst_eFPGA.Tile_X7Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[0] }),
+ .bot_E2BEG({ \Inst_eFPGA.Tile_X7Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[0] }),
+ .bot_E1BEG({ \Inst_eFPGA.Tile_X7Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_E1BEG[0] }),
+ .top_W6END({ \Inst_eFPGA.Tile_X8Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[0] }),
+ .top_WW4END({ \Inst_eFPGA.Tile_X8Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[0] }),
+ .top_W2END({ \Inst_eFPGA.Tile_X8Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[0] }),
+ .top_W2MID({ \Inst_eFPGA.Tile_X8Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[0] }),
+ .top_W1END({ \Inst_eFPGA.Tile_X8Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_W1BEG[0] }),
+ .top_W6BEG({ \Inst_eFPGA.Tile_X7Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_W6BEG[0] }),
+ .top_WW4BEG({ \Inst_eFPGA.Tile_X7Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_WW4BEG[0] }),
+ .top_W2BEGb({ \Inst_eFPGA.Tile_X7Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEGb[0] }),
+ .top_W2BEG({ \Inst_eFPGA.Tile_X7Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_W2BEG[0] }),
+ .top_W1BEG({ \Inst_eFPGA.Tile_X7Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_W1BEG[0] }),
+ .top_E6END({ \Inst_eFPGA.Tile_X6Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_E6BEG[0] }),
+ .top_EE4END({ \Inst_eFPGA.Tile_X6Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_EE4BEG[0] }),
+ .top_E2END({ \Inst_eFPGA.Tile_X6Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEGb[0] }),
+ .top_E2MID({ \Inst_eFPGA.Tile_X6Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_E2BEG[0] }),
+ .top_E1END({ \Inst_eFPGA.Tile_X6Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y1_E1BEG[0] }),
+ .top_E6BEG({ \Inst_eFPGA.Tile_X7Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[0] }),
+ .top_EE4BEG({ \Inst_eFPGA.Tile_X7Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[0] }),
+ .top_E2BEGb({ \Inst_eFPGA.Tile_X7Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[0] }),
+ .top_E2BEG({ \Inst_eFPGA.Tile_X7Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[0] }),
+ .top_E1BEG({ \Inst_eFPGA.Tile_X7Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_E1BEG[0] }),
+ .top_SS4END({ \Inst_eFPGA.Tile_X7Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y0_SS4BEG[0] }),
+ .top_S4END({ \Inst_eFPGA.Tile_X7Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y0_S4BEG[0] }),
+ .top_S2END({ \Inst_eFPGA.Tile_X7Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEGb[0] }),
+ .top_S2MID({ \Inst_eFPGA.Tile_X7Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y0_S2BEG[0] }),
+ .top_S1END({ \Inst_eFPGA.Tile_X7Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y0_S1BEG[0] }),
+ .top_NN4BEG({ \Inst_eFPGA.Tile_X7Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_NN4BEG[0] }),
+ .top_N4BEG({ \Inst_eFPGA.Tile_X7Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_N4BEG[0] }),
+ .top_N2BEGb({ \Inst_eFPGA.Tile_X7Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEGb[0] }),
+ .top_N2BEG({ \Inst_eFPGA.Tile_X7Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_N2BEG[0] }),
+ .top_N1BEG({ \Inst_eFPGA.Tile_X7Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X7Y1_UserCLKo ));
+ DSP \Inst_eFPGA.Tile_X7Y3_X7Y4_DSP_tile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[0] }),
+ .bot_FrameData_O({ \Inst_eFPGA.Tile_X7Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[0] }),
+ .bot_FrameData({ \Inst_eFPGA.Tile_X6Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y4_FrameData_O[0] }),
+ .top_FrameData_O({ \Inst_eFPGA.Tile_X7Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[0] }),
+ .top_FrameData({ \Inst_eFPGA.Tile_X6Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y3_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X7Y5_UserCLKo ),
+ .bot_NN4END({ \Inst_eFPGA.Tile_X7Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[0] }),
+ .bot_N4END({ \Inst_eFPGA.Tile_X7Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[0] }),
+ .bot_N2END({ \Inst_eFPGA.Tile_X7Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[0] }),
+ .bot_N2MID({ \Inst_eFPGA.Tile_X7Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[0] }),
+ .bot_N1END({ \Inst_eFPGA.Tile_X7Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_N1BEG[0] }),
+ .bot_SS4BEG({ \Inst_eFPGA.Tile_X7Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[0] }),
+ .bot_S4BEG({ \Inst_eFPGA.Tile_X7Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[0] }),
+ .bot_S2BEGb({ \Inst_eFPGA.Tile_X7Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[0] }),
+ .bot_S2BEG({ \Inst_eFPGA.Tile_X7Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[0] }),
+ .bot_S1BEG({ \Inst_eFPGA.Tile_X7Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_S1BEG[0] }),
+ .bot_W6END({ \Inst_eFPGA.Tile_X8Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[0] }),
+ .bot_WW4END({ \Inst_eFPGA.Tile_X8Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[0] }),
+ .bot_W2END({ \Inst_eFPGA.Tile_X8Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[0] }),
+ .bot_W2MID({ \Inst_eFPGA.Tile_X8Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[0] }),
+ .bot_W1END({ \Inst_eFPGA.Tile_X8Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_W1BEG[0] }),
+ .bot_W6BEG({ \Inst_eFPGA.Tile_X7Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_W6BEG[0] }),
+ .bot_WW4BEG({ \Inst_eFPGA.Tile_X7Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_WW4BEG[0] }),
+ .bot_W2BEGb({ \Inst_eFPGA.Tile_X7Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEGb[0] }),
+ .bot_W2BEG({ \Inst_eFPGA.Tile_X7Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_W2BEG[0] }),
+ .bot_W1BEG({ \Inst_eFPGA.Tile_X7Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_W1BEG[0] }),
+ .bot_E6END({ \Inst_eFPGA.Tile_X6Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_E6BEG[0] }),
+ .bot_EE4END({ \Inst_eFPGA.Tile_X6Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_EE4BEG[0] }),
+ .bot_E2END({ \Inst_eFPGA.Tile_X6Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEGb[0] }),
+ .bot_E2MID({ \Inst_eFPGA.Tile_X6Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_E2BEG[0] }),
+ .bot_E1END({ \Inst_eFPGA.Tile_X6Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y4_E1BEG[0] }),
+ .bot_E6BEG({ \Inst_eFPGA.Tile_X7Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[0] }),
+ .bot_EE4BEG({ \Inst_eFPGA.Tile_X7Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[0] }),
+ .bot_E2BEGb({ \Inst_eFPGA.Tile_X7Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[0] }),
+ .bot_E2BEG({ \Inst_eFPGA.Tile_X7Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[0] }),
+ .bot_E1BEG({ \Inst_eFPGA.Tile_X7Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_E1BEG[0] }),
+ .top_W6END({ \Inst_eFPGA.Tile_X8Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[0] }),
+ .top_WW4END({ \Inst_eFPGA.Tile_X8Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[0] }),
+ .top_W2END({ \Inst_eFPGA.Tile_X8Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[0] }),
+ .top_W2MID({ \Inst_eFPGA.Tile_X8Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[0] }),
+ .top_W1END({ \Inst_eFPGA.Tile_X8Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_W1BEG[0] }),
+ .top_W6BEG({ \Inst_eFPGA.Tile_X7Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_W6BEG[0] }),
+ .top_WW4BEG({ \Inst_eFPGA.Tile_X7Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_WW4BEG[0] }),
+ .top_W2BEGb({ \Inst_eFPGA.Tile_X7Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEGb[0] }),
+ .top_W2BEG({ \Inst_eFPGA.Tile_X7Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_W2BEG[0] }),
+ .top_W1BEG({ \Inst_eFPGA.Tile_X7Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_W1BEG[0] }),
+ .top_E6END({ \Inst_eFPGA.Tile_X6Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_E6BEG[0] }),
+ .top_EE4END({ \Inst_eFPGA.Tile_X6Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_EE4BEG[0] }),
+ .top_E2END({ \Inst_eFPGA.Tile_X6Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEGb[0] }),
+ .top_E2MID({ \Inst_eFPGA.Tile_X6Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_E2BEG[0] }),
+ .top_E1END({ \Inst_eFPGA.Tile_X6Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y3_E1BEG[0] }),
+ .top_E6BEG({ \Inst_eFPGA.Tile_X7Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[0] }),
+ .top_EE4BEG({ \Inst_eFPGA.Tile_X7Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[0] }),
+ .top_E2BEGb({ \Inst_eFPGA.Tile_X7Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[0] }),
+ .top_E2BEG({ \Inst_eFPGA.Tile_X7Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[0] }),
+ .top_E1BEG({ \Inst_eFPGA.Tile_X7Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_E1BEG[0] }),
+ .top_SS4END({ \Inst_eFPGA.Tile_X7Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_SS4BEG[0] }),
+ .top_S4END({ \Inst_eFPGA.Tile_X7Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_S4BEG[0] }),
+ .top_S2END({ \Inst_eFPGA.Tile_X7Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEGb[0] }),
+ .top_S2MID({ \Inst_eFPGA.Tile_X7Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_S2BEG[0] }),
+ .top_S1END({ \Inst_eFPGA.Tile_X7Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_S1BEG[0] }),
+ .top_NN4BEG({ \Inst_eFPGA.Tile_X7Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_NN4BEG[0] }),
+ .top_N4BEG({ \Inst_eFPGA.Tile_X7Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_N4BEG[0] }),
+ .top_N2BEGb({ \Inst_eFPGA.Tile_X7Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEGb[0] }),
+ .top_N2BEG({ \Inst_eFPGA.Tile_X7Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_N2BEG[0] }),
+ .top_N1BEG({ \Inst_eFPGA.Tile_X7Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X7Y3_UserCLKo ));
+ DSP \Inst_eFPGA.Tile_X7Y5_X7Y6_DSP_tile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[0] }),
+ .bot_FrameData_O({ \Inst_eFPGA.Tile_X7Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[0] }),
+ .bot_FrameData({ \Inst_eFPGA.Tile_X6Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y6_FrameData_O[0] }),
+ .top_FrameData_O({ \Inst_eFPGA.Tile_X7Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[0] }),
+ .top_FrameData({ \Inst_eFPGA.Tile_X6Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y5_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X7Y7_UserCLKo ),
+ .bot_NN4END({ \Inst_eFPGA.Tile_X7Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[0] }),
+ .bot_N4END({ \Inst_eFPGA.Tile_X7Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[0] }),
+ .bot_N2END({ \Inst_eFPGA.Tile_X7Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[0] }),
+ .bot_N2MID({ \Inst_eFPGA.Tile_X7Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[0] }),
+ .bot_N1END({ \Inst_eFPGA.Tile_X7Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_N1BEG[0] }),
+ .bot_SS4BEG({ \Inst_eFPGA.Tile_X7Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[0] }),
+ .bot_S4BEG({ \Inst_eFPGA.Tile_X7Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[0] }),
+ .bot_S2BEGb({ \Inst_eFPGA.Tile_X7Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[0] }),
+ .bot_S2BEG({ \Inst_eFPGA.Tile_X7Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[0] }),
+ .bot_S1BEG({ \Inst_eFPGA.Tile_X7Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_S1BEG[0] }),
+ .bot_W6END({ \Inst_eFPGA.Tile_X8Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[0] }),
+ .bot_WW4END({ \Inst_eFPGA.Tile_X8Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[0] }),
+ .bot_W2END({ \Inst_eFPGA.Tile_X8Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[0] }),
+ .bot_W2MID({ \Inst_eFPGA.Tile_X8Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[0] }),
+ .bot_W1END({ \Inst_eFPGA.Tile_X8Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_W1BEG[0] }),
+ .bot_W6BEG({ \Inst_eFPGA.Tile_X7Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_W6BEG[0] }),
+ .bot_WW4BEG({ \Inst_eFPGA.Tile_X7Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_WW4BEG[0] }),
+ .bot_W2BEGb({ \Inst_eFPGA.Tile_X7Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEGb[0] }),
+ .bot_W2BEG({ \Inst_eFPGA.Tile_X7Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_W2BEG[0] }),
+ .bot_W1BEG({ \Inst_eFPGA.Tile_X7Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_W1BEG[0] }),
+ .bot_E6END({ \Inst_eFPGA.Tile_X6Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_E6BEG[0] }),
+ .bot_EE4END({ \Inst_eFPGA.Tile_X6Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_EE4BEG[0] }),
+ .bot_E2END({ \Inst_eFPGA.Tile_X6Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEGb[0] }),
+ .bot_E2MID({ \Inst_eFPGA.Tile_X6Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_E2BEG[0] }),
+ .bot_E1END({ \Inst_eFPGA.Tile_X6Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y6_E1BEG[0] }),
+ .bot_E6BEG({ \Inst_eFPGA.Tile_X7Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[0] }),
+ .bot_EE4BEG({ \Inst_eFPGA.Tile_X7Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[0] }),
+ .bot_E2BEGb({ \Inst_eFPGA.Tile_X7Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[0] }),
+ .bot_E2BEG({ \Inst_eFPGA.Tile_X7Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[0] }),
+ .bot_E1BEG({ \Inst_eFPGA.Tile_X7Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_E1BEG[0] }),
+ .top_W6END({ \Inst_eFPGA.Tile_X8Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[0] }),
+ .top_WW4END({ \Inst_eFPGA.Tile_X8Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[0] }),
+ .top_W2END({ \Inst_eFPGA.Tile_X8Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[0] }),
+ .top_W2MID({ \Inst_eFPGA.Tile_X8Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[0] }),
+ .top_W1END({ \Inst_eFPGA.Tile_X8Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_W1BEG[0] }),
+ .top_W6BEG({ \Inst_eFPGA.Tile_X7Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_W6BEG[0] }),
+ .top_WW4BEG({ \Inst_eFPGA.Tile_X7Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_WW4BEG[0] }),
+ .top_W2BEGb({ \Inst_eFPGA.Tile_X7Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEGb[0] }),
+ .top_W2BEG({ \Inst_eFPGA.Tile_X7Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_W2BEG[0] }),
+ .top_W1BEG({ \Inst_eFPGA.Tile_X7Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_W1BEG[0] }),
+ .top_E6END({ \Inst_eFPGA.Tile_X6Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_E6BEG[0] }),
+ .top_EE4END({ \Inst_eFPGA.Tile_X6Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_EE4BEG[0] }),
+ .top_E2END({ \Inst_eFPGA.Tile_X6Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEGb[0] }),
+ .top_E2MID({ \Inst_eFPGA.Tile_X6Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_E2BEG[0] }),
+ .top_E1END({ \Inst_eFPGA.Tile_X6Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y5_E1BEG[0] }),
+ .top_E6BEG({ \Inst_eFPGA.Tile_X7Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[0] }),
+ .top_EE4BEG({ \Inst_eFPGA.Tile_X7Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[0] }),
+ .top_E2BEGb({ \Inst_eFPGA.Tile_X7Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[0] }),
+ .top_E2BEG({ \Inst_eFPGA.Tile_X7Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[0] }),
+ .top_E1BEG({ \Inst_eFPGA.Tile_X7Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_E1BEG[0] }),
+ .top_SS4END({ \Inst_eFPGA.Tile_X7Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_SS4BEG[0] }),
+ .top_S4END({ \Inst_eFPGA.Tile_X7Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_S4BEG[0] }),
+ .top_S2END({ \Inst_eFPGA.Tile_X7Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEGb[0] }),
+ .top_S2MID({ \Inst_eFPGA.Tile_X7Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_S2BEG[0] }),
+ .top_S1END({ \Inst_eFPGA.Tile_X7Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_S1BEG[0] }),
+ .top_NN4BEG({ \Inst_eFPGA.Tile_X7Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_NN4BEG[0] }),
+ .top_N4BEG({ \Inst_eFPGA.Tile_X7Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_N4BEG[0] }),
+ .top_N2BEGb({ \Inst_eFPGA.Tile_X7Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEGb[0] }),
+ .top_N2BEG({ \Inst_eFPGA.Tile_X7Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_N2BEG[0] }),
+ .top_N1BEG({ \Inst_eFPGA.Tile_X7Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X7Y5_UserCLKo ));
+ DSP \Inst_eFPGA.Tile_X7Y7_X7Y8_DSP_tile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[0] }),
+ .bot_FrameData_O({ \Inst_eFPGA.Tile_X7Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[0] }),
+ .bot_FrameData({ \Inst_eFPGA.Tile_X6Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y8_FrameData_O[0] }),
+ .top_FrameData_O({ \Inst_eFPGA.Tile_X7Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[0] }),
+ .top_FrameData({ \Inst_eFPGA.Tile_X6Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y7_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X7Y9_UserCLKo ),
+ .bot_NN4END({ \Inst_eFPGA.Tile_X7Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[0] }),
+ .bot_N4END({ \Inst_eFPGA.Tile_X7Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[0] }),
+ .bot_N2END({ \Inst_eFPGA.Tile_X7Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[0] }),
+ .bot_N2MID({ \Inst_eFPGA.Tile_X7Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[0] }),
+ .bot_N1END({ \Inst_eFPGA.Tile_X7Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_N1BEG[0] }),
+ .bot_SS4BEG({ \Inst_eFPGA.Tile_X7Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[0] }),
+ .bot_S4BEG({ \Inst_eFPGA.Tile_X7Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[0] }),
+ .bot_S2BEGb({ \Inst_eFPGA.Tile_X7Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[0] }),
+ .bot_S2BEG({ \Inst_eFPGA.Tile_X7Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[0] }),
+ .bot_S1BEG({ \Inst_eFPGA.Tile_X7Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_S1BEG[0] }),
+ .bot_W6END({ \Inst_eFPGA.Tile_X8Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[0] }),
+ .bot_WW4END({ \Inst_eFPGA.Tile_X8Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[0] }),
+ .bot_W2END({ \Inst_eFPGA.Tile_X8Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[0] }),
+ .bot_W2MID({ \Inst_eFPGA.Tile_X8Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[0] }),
+ .bot_W1END({ \Inst_eFPGA.Tile_X8Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_W1BEG[0] }),
+ .bot_W6BEG({ \Inst_eFPGA.Tile_X7Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_W6BEG[0] }),
+ .bot_WW4BEG({ \Inst_eFPGA.Tile_X7Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_WW4BEG[0] }),
+ .bot_W2BEGb({ \Inst_eFPGA.Tile_X7Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEGb[0] }),
+ .bot_W2BEG({ \Inst_eFPGA.Tile_X7Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_W2BEG[0] }),
+ .bot_W1BEG({ \Inst_eFPGA.Tile_X7Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_W1BEG[0] }),
+ .bot_E6END({ \Inst_eFPGA.Tile_X6Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_E6BEG[0] }),
+ .bot_EE4END({ \Inst_eFPGA.Tile_X6Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_EE4BEG[0] }),
+ .bot_E2END({ \Inst_eFPGA.Tile_X6Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEGb[0] }),
+ .bot_E2MID({ \Inst_eFPGA.Tile_X6Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_E2BEG[0] }),
+ .bot_E1END({ \Inst_eFPGA.Tile_X6Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y8_E1BEG[0] }),
+ .bot_E6BEG({ \Inst_eFPGA.Tile_X7Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[0] }),
+ .bot_EE4BEG({ \Inst_eFPGA.Tile_X7Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[0] }),
+ .bot_E2BEGb({ \Inst_eFPGA.Tile_X7Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[0] }),
+ .bot_E2BEG({ \Inst_eFPGA.Tile_X7Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[0] }),
+ .bot_E1BEG({ \Inst_eFPGA.Tile_X7Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_E1BEG[0] }),
+ .top_W6END({ \Inst_eFPGA.Tile_X8Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[0] }),
+ .top_WW4END({ \Inst_eFPGA.Tile_X8Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[0] }),
+ .top_W2END({ \Inst_eFPGA.Tile_X8Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[0] }),
+ .top_W2MID({ \Inst_eFPGA.Tile_X8Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[0] }),
+ .top_W1END({ \Inst_eFPGA.Tile_X8Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_W1BEG[0] }),
+ .top_W6BEG({ \Inst_eFPGA.Tile_X7Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_W6BEG[0] }),
+ .top_WW4BEG({ \Inst_eFPGA.Tile_X7Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_WW4BEG[0] }),
+ .top_W2BEGb({ \Inst_eFPGA.Tile_X7Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEGb[0] }),
+ .top_W2BEG({ \Inst_eFPGA.Tile_X7Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_W2BEG[0] }),
+ .top_W1BEG({ \Inst_eFPGA.Tile_X7Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_W1BEG[0] }),
+ .top_E6END({ \Inst_eFPGA.Tile_X6Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_E6BEG[0] }),
+ .top_EE4END({ \Inst_eFPGA.Tile_X6Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_EE4BEG[0] }),
+ .top_E2END({ \Inst_eFPGA.Tile_X6Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEGb[0] }),
+ .top_E2MID({ \Inst_eFPGA.Tile_X6Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_E2BEG[0] }),
+ .top_E1END({ \Inst_eFPGA.Tile_X6Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y7_E1BEG[0] }),
+ .top_E6BEG({ \Inst_eFPGA.Tile_X7Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[0] }),
+ .top_EE4BEG({ \Inst_eFPGA.Tile_X7Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[0] }),
+ .top_E2BEGb({ \Inst_eFPGA.Tile_X7Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[0] }),
+ .top_E2BEG({ \Inst_eFPGA.Tile_X7Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[0] }),
+ .top_E1BEG({ \Inst_eFPGA.Tile_X7Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_E1BEG[0] }),
+ .top_SS4END({ \Inst_eFPGA.Tile_X7Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_SS4BEG[0] }),
+ .top_S4END({ \Inst_eFPGA.Tile_X7Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_S4BEG[0] }),
+ .top_S2END({ \Inst_eFPGA.Tile_X7Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEGb[0] }),
+ .top_S2MID({ \Inst_eFPGA.Tile_X7Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_S2BEG[0] }),
+ .top_S1END({ \Inst_eFPGA.Tile_X7Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_S1BEG[0] }),
+ .top_NN4BEG({ \Inst_eFPGA.Tile_X7Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_NN4BEG[0] }),
+ .top_N4BEG({ \Inst_eFPGA.Tile_X7Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_N4BEG[0] }),
+ .top_N2BEGb({ \Inst_eFPGA.Tile_X7Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEGb[0] }),
+ .top_N2BEG({ \Inst_eFPGA.Tile_X7Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_N2BEG[0] }),
+ .top_N1BEG({ \Inst_eFPGA.Tile_X7Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X7Y7_UserCLKo ));
+ DSP \Inst_eFPGA.Tile_X7Y9_X7Y10_DSP_tile (.FrameStrobe_O({ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameStrobe_O[0] }),
+ .bot_FrameData_O({ \Inst_eFPGA.Tile_X7Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[0] }),
+ .bot_FrameData({ \Inst_eFPGA.Tile_X6Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y10_FrameData_O[0] }),
+ .top_FrameData_O({ \Inst_eFPGA.Tile_X7Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[0] }),
+ .top_FrameData({ \Inst_eFPGA.Tile_X6Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X6Y9_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X7Y11_UserCLKo ),
+ .bot_NN4END({ \Inst_eFPGA.Tile_X7Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_NN4BEG[0] }),
+ .bot_N4END({ \Inst_eFPGA.Tile_X7Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_N4BEG[0] }),
+ .bot_N2END({ \Inst_eFPGA.Tile_X7Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEGb[0] }),
+ .bot_N2MID({ \Inst_eFPGA.Tile_X7Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_N2BEG[0] }),
+ .bot_N1END({ \Inst_eFPGA.Tile_X7Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_N1BEG[0] }),
+ .bot_SS4BEG({ \Inst_eFPGA.Tile_X7Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_SS4BEG[0] }),
+ .bot_S4BEG({ \Inst_eFPGA.Tile_X7Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_S4BEG[0] }),
+ .bot_S2BEGb({ \Inst_eFPGA.Tile_X7Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEGb[0] }),
+ .bot_S2BEG({ \Inst_eFPGA.Tile_X7Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_S2BEG[0] }),
+ .bot_S1BEG({ \Inst_eFPGA.Tile_X7Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_S1BEG[0] }),
+ .bot_W6END({ \Inst_eFPGA.Tile_X8Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[0] }),
+ .bot_WW4END({ \Inst_eFPGA.Tile_X8Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[0] }),
+ .bot_W2END({ \Inst_eFPGA.Tile_X8Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[0] }),
+ .bot_W2MID({ \Inst_eFPGA.Tile_X8Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[0] }),
+ .bot_W1END({ \Inst_eFPGA.Tile_X8Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_W1BEG[0] }),
+ .bot_W6BEG({ \Inst_eFPGA.Tile_X7Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_W6BEG[0] }),
+ .bot_WW4BEG({ \Inst_eFPGA.Tile_X7Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_WW4BEG[0] }),
+ .bot_W2BEGb({ \Inst_eFPGA.Tile_X7Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEGb[0] }),
+ .bot_W2BEG({ \Inst_eFPGA.Tile_X7Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_W2BEG[0] }),
+ .bot_W1BEG({ \Inst_eFPGA.Tile_X7Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_W1BEG[0] }),
+ .bot_E6END({ \Inst_eFPGA.Tile_X6Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_E6BEG[0] }),
+ .bot_EE4END({ \Inst_eFPGA.Tile_X6Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_EE4BEG[0] }),
+ .bot_E2END({ \Inst_eFPGA.Tile_X6Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEGb[0] }),
+ .bot_E2MID({ \Inst_eFPGA.Tile_X6Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_E2BEG[0] }),
+ .bot_E1END({ \Inst_eFPGA.Tile_X6Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y10_E1BEG[0] }),
+ .bot_E6BEG({ \Inst_eFPGA.Tile_X7Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[0] }),
+ .bot_EE4BEG({ \Inst_eFPGA.Tile_X7Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[0] }),
+ .bot_E2BEGb({ \Inst_eFPGA.Tile_X7Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[0] }),
+ .bot_E2BEG({ \Inst_eFPGA.Tile_X7Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[0] }),
+ .bot_E1BEG({ \Inst_eFPGA.Tile_X7Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_E1BEG[0] }),
+ .top_W6END({ \Inst_eFPGA.Tile_X8Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[0] }),
+ .top_WW4END({ \Inst_eFPGA.Tile_X8Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[0] }),
+ .top_W2END({ \Inst_eFPGA.Tile_X8Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[0] }),
+ .top_W2MID({ \Inst_eFPGA.Tile_X8Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[0] }),
+ .top_W1END({ \Inst_eFPGA.Tile_X8Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_W1BEG[0] }),
+ .top_W6BEG({ \Inst_eFPGA.Tile_X7Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_W6BEG[0] }),
+ .top_WW4BEG({ \Inst_eFPGA.Tile_X7Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_WW4BEG[0] }),
+ .top_W2BEGb({ \Inst_eFPGA.Tile_X7Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEGb[0] }),
+ .top_W2BEG({ \Inst_eFPGA.Tile_X7Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_W2BEG[0] }),
+ .top_W1BEG({ \Inst_eFPGA.Tile_X7Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_W1BEG[0] }),
+ .top_E6END({ \Inst_eFPGA.Tile_X6Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_E6BEG[0] }),
+ .top_EE4END({ \Inst_eFPGA.Tile_X6Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_EE4BEG[0] }),
+ .top_E2END({ \Inst_eFPGA.Tile_X6Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEGb[0] }),
+ .top_E2MID({ \Inst_eFPGA.Tile_X6Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_E2BEG[0] }),
+ .top_E1END({ \Inst_eFPGA.Tile_X6Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X6Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X6Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X6Y9_E1BEG[0] }),
+ .top_E6BEG({ \Inst_eFPGA.Tile_X7Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[0] }),
+ .top_EE4BEG({ \Inst_eFPGA.Tile_X7Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[0] }),
+ .top_E2BEGb({ \Inst_eFPGA.Tile_X7Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[0] }),
+ .top_E2BEG({ \Inst_eFPGA.Tile_X7Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[0] }),
+ .top_E1BEG({ \Inst_eFPGA.Tile_X7Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_E1BEG[0] }),
+ .top_SS4END({ \Inst_eFPGA.Tile_X7Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_SS4BEG[0] }),
+ .top_S4END({ \Inst_eFPGA.Tile_X7Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_S4BEG[0] }),
+ .top_S2END({ \Inst_eFPGA.Tile_X7Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEGb[0] }),
+ .top_S2MID({ \Inst_eFPGA.Tile_X7Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_S2BEG[0] }),
+ .top_S1END({ \Inst_eFPGA.Tile_X7Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_S1BEG[0] }),
+ .top_NN4BEG({ \Inst_eFPGA.Tile_X7Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_NN4BEG[0] }),
+ .top_N4BEG({ \Inst_eFPGA.Tile_X7Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_N4BEG[0] }),
+ .top_N2BEGb({ \Inst_eFPGA.Tile_X7Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEGb[0] }),
+ .top_N2BEG({ \Inst_eFPGA.Tile_X7Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_N2BEG[0] }),
+ .top_N1BEG({ \Inst_eFPGA.Tile_X7Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X7Y9_UserCLKo ));
+ N_term_single \Inst_eFPGA.Tile_X8Y0_N_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y0_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y0_S1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y1_Co ),
+ .N4END({ \Inst_eFPGA.Tile_X8Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y0_UserCLKo ),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y10_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y10_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y11_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y10_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y11_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y10_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y10_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y11_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y11_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y12_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y11_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y12_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y11_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y11_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y12_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y12_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y13_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y12_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y13_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y12_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y12_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y13_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y13_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y14_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y13_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y14_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y13_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y13_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y14_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y14_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y15_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y14_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y15_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y14_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y14_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y15_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y15_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y16_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y15_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y16_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y15_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y15_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y16_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y16_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y17_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y16_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y17_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y17_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y16_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y16_UserCLKo ));
+ S_term_single \Inst_eFPGA.Tile_X8Y17_S_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y17_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_8.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[4] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[3] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[2] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[1] ,
+ \Inst_Frame_Select_8.FrameStrobe_O[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_S1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y17_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y17_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y17_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y17_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y17_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y17_UserCLKo ),
+ .UserCLK(CTS_35));
+ LUT4AB \Inst_eFPGA.Tile_X8Y1_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y1_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y2_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y0_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y0_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y0_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y0_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y1_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y2_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y1_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y2_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y2_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y3_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y2_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y3_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y2_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y2_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y3_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y3_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y4_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y3_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y4_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y3_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y3_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y4_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y4_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y5_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y4_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y5_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y4_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y4_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y5_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y5_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y6_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y5_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y6_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y5_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y5_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y6_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y6_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y7_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y6_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y7_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y6_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y6_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y7_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y7_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y8_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y7_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y8_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y7_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y7_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y8_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y8_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y9_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y8_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y9_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y8_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y8_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X8Y9_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X8Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X7Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X7Y9_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X8Y10_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X9Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X9Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X9Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X9Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X9Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X8Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X8Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X8Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X8Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X8Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X8Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X8Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X8Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X8Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X8Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X8Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X8Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X8Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X8Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X8Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X7Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X7Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X7Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X7Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X7Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X7Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X7Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X7Y9_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X8Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X8Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X8Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X8Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X8Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X8Y10_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X8Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X8Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X8Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X8Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X8Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X8Y9_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X8Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X8Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X8Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X8Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X8Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X8Y9_UserCLKo ));
+ N_term_single \Inst_eFPGA.Tile_X9Y0_N_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y0_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y0_S1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y1_Co ),
+ .N4END({ \Inst_eFPGA.Tile_X9Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[0] }),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y0_UserCLKo ),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y10_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y10_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y10_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y11_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y10_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y10_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y10_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y10_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y10_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y10_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y10_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y10_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y10_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y10_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y10_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y10_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y11_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y10_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y10_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y11_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y11_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y11_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y11_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y12_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y11_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y11_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y11_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y11_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y11_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y11_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y10_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y10_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y10_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y10_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y10_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y11_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y11_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y11_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y11_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y11_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y11_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y12_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y11_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y11_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y11_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y11_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y11_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y11_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y11_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y12_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y12_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y12_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y12_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y13_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y12_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y12_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y12_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y12_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y12_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y12_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y11_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y11_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y11_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y11_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y11_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y11_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y11_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y11_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y12_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y12_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y12_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y12_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y12_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y12_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y13_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y12_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y12_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y12_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y12_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y12_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y12_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y12_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y13_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y13_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y13_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y13_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y14_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y13_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y13_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y13_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y13_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y13_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y13_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y12_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y12_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y12_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y12_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y12_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y12_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y12_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y12_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y13_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y13_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y13_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y13_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y13_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y13_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y14_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y13_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y13_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y13_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y13_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y13_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y13_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y13_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y14_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y14_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y14_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y14_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y15_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y14_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y14_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y14_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y14_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y14_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y14_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y13_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y13_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y13_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y13_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y13_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y13_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y13_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y13_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y14_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y14_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y14_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y14_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y14_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y14_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y15_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y14_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y14_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y14_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y14_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y14_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y14_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y14_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y15_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y15_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y15_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y15_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y16_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y15_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y15_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y15_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y15_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y15_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y15_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y14_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y14_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y14_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y14_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y14_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y14_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y14_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y14_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y15_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y15_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y15_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y15_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y15_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y15_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y16_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y15_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y15_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y15_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y15_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y15_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y15_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y15_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y16_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y16_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y16_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y16_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y17_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y16_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y16_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y16_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y16_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y16_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y16_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y15_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y15_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y15_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y15_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y15_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y15_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y15_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y15_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y16_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y16_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y16_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y16_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y16_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y16_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y17_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y17_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y16_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y16_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y16_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y16_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y16_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y16_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y16_UserCLKo ));
+ S_term_single \Inst_eFPGA.Tile_X9Y17_S_term_single (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y17_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_Frame_Select_9.FrameStrobe_O[19] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[18] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[17] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[16] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[15] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[14] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[13] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[12] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[11] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[10] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[9] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[8] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[7] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[6] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[5] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[4] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[3] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[2] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[1] ,
+ \Inst_Frame_Select_9.FrameStrobe_O[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y16_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y16_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y16_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y16_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y16_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y16_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y16_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y16_S1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y17_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y17_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y17_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y17_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y17_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y17_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y17_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y17_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y17_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y17_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y17_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y17_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y17_UserCLKo ),
+ .UserCLK(CTS_35));
+ LUT4AB \Inst_eFPGA.Tile_X9Y1_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y1_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y1_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y1_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y2_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y1_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y1_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y1_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y1_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y1_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y1_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y0_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y0_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y0_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y0_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y0_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y0_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y0_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y0_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y0_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y0_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y0_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y1_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y1_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y1_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y1_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y1_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y1_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y2_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y1_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y1_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y1_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y1_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y1_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y1_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y1_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y2_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y2_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y2_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y2_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y3_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y2_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y2_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y2_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y2_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y2_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y2_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y1_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y1_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y1_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y1_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y1_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y1_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y1_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y1_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y2_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y2_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y2_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y2_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y2_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y2_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y3_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y2_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y2_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y2_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y2_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y2_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y2_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y2_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y3_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y3_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y3_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y3_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y4_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y3_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y3_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y3_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y3_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y3_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y3_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y2_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y2_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y2_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y2_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y2_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y2_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y2_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y2_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y3_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y3_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y3_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y3_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y3_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y3_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y4_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y3_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y3_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y3_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y3_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y3_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y3_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y3_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y4_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y4_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y4_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y4_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y5_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y4_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y4_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y4_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y4_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y4_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y4_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y3_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y3_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y3_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y3_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y3_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y3_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y3_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y3_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y4_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y4_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y4_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y4_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y4_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y4_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y5_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y4_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y4_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y4_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y4_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y4_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y4_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y4_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y5_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y5_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y5_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y5_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y6_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y5_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y5_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y5_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y5_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y5_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y5_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y4_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y4_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y4_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y4_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y4_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y4_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y4_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y4_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y5_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y5_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y5_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y5_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y5_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y5_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y6_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y5_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y5_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y5_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y5_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y5_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y5_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y5_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y6_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y6_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y6_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y6_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y7_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y6_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y6_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y6_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y6_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y6_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y6_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y5_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y5_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y5_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y5_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y5_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y5_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y5_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y5_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y6_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y6_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y6_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y6_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y6_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y6_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y7_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y6_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y6_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y6_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y6_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y6_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y6_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y6_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y7_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y7_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y7_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y7_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y8_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y7_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y7_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y7_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y7_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y7_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y7_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y6_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y6_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y6_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y6_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y6_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y6_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y6_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y6_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y7_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y7_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y7_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y7_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y7_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y7_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y8_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y7_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y7_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y7_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y7_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y7_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y7_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y7_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y8_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y8_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y8_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y8_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y9_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y8_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y8_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y8_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y8_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y8_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y8_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y7_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y7_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y7_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y7_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y7_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y7_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y7_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y7_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y8_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y8_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y8_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y8_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y8_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y8_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y9_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y8_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y8_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y8_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y8_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y8_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y8_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y8_UserCLKo ));
+ LUT4AB \Inst_eFPGA.Tile_X9Y9_LUT4AB (.FrameStrobe_O({ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameStrobe_O[0] }),
+ .FrameStrobe({ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[19] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[18] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[17] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[16] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[15] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[14] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[13] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[12] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[11] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[10] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[9] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[8] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[7] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[6] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[5] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[4] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[3] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[2] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[1] ,
+ \Inst_eFPGA.Tile_X9Y10_FrameStrobe_O[0] }),
+ .FrameData_O({ \Inst_eFPGA.Tile_X9Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X9Y9_FrameData_O[0] }),
+ .FrameData({ \Inst_eFPGA.Tile_X8Y9_FrameData_O[31] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[30] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[29] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[28] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[27] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[26] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[25] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[24] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[23] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[22] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[21] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[20] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[19] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[18] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[17] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[16] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[15] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[14] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[13] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[12] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[11] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[10] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[9] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[8] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[7] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[6] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[5] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[4] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[3] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[2] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[1] ,
+ \Inst_eFPGA.Tile_X8Y9_FrameData_O[0] }),
+ .UserCLK(\Inst_eFPGA.Tile_X9Y10_UserCLKo ),
+ .W6END({ \Inst_eFPGA.Tile_X10Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_W6BEG[0] }),
+ .WW4END({ \Inst_eFPGA.Tile_X10Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_WW4BEG[0] }),
+ .W2END({ \Inst_eFPGA.Tile_X10Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEGb[0] }),
+ .W2MID({ \Inst_eFPGA.Tile_X10Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_W2BEG[0] }),
+ .W1END({ \Inst_eFPGA.Tile_X10Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X10Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X10Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X10Y9_W1BEG[0] }),
+ .W6BEG({ \Inst_eFPGA.Tile_X9Y9_W6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_W6BEG[0] }),
+ .WW4BEG({ \Inst_eFPGA.Tile_X9Y9_WW4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_WW4BEG[0] }),
+ .W2BEGb({ \Inst_eFPGA.Tile_X9Y9_W2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEGb[0] }),
+ .W2BEG({ \Inst_eFPGA.Tile_X9Y9_W2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_W2BEG[0] }),
+ .W1BEG({ \Inst_eFPGA.Tile_X9Y9_W1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_W1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_W1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_W1BEG[0] }),
+ .SS4END({ \Inst_eFPGA.Tile_X9Y8_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_SS4BEG[0] }),
+ .S4END({ \Inst_eFPGA.Tile_X9Y8_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_S4BEG[0] }),
+ .S2END({ \Inst_eFPGA.Tile_X9Y8_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEGb[0] }),
+ .S2MID({ \Inst_eFPGA.Tile_X9Y8_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_S2BEG[0] }),
+ .S1END({ \Inst_eFPGA.Tile_X9Y8_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y8_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y8_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y8_S1BEG[0] }),
+ .SS4BEG({ \Inst_eFPGA.Tile_X9Y9_SS4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_SS4BEG[0] }),
+ .S4BEG({ \Inst_eFPGA.Tile_X9Y9_S4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_S4BEG[0] }),
+ .S2BEGb({ \Inst_eFPGA.Tile_X9Y9_S2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEGb[0] }),
+ .S2BEG({ \Inst_eFPGA.Tile_X9Y9_S2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_S2BEG[0] }),
+ .S1BEG({ \Inst_eFPGA.Tile_X9Y9_S1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_S1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_S1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_S1BEG[0] }),
+ .E6END({ \Inst_eFPGA.Tile_X8Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_E6BEG[0] }),
+ .EE4END({ \Inst_eFPGA.Tile_X8Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_EE4BEG[0] }),
+ .E2END({ \Inst_eFPGA.Tile_X8Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEGb[0] }),
+ .E2MID({ \Inst_eFPGA.Tile_X8Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_E2BEG[0] }),
+ .E1END({ \Inst_eFPGA.Tile_X8Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X8Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X8Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X8Y9_E1BEG[0] }),
+ .E6BEG({ \Inst_eFPGA.Tile_X9Y9_E6BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_E6BEG[0] }),
+ .EE4BEG({ \Inst_eFPGA.Tile_X9Y9_EE4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_EE4BEG[0] }),
+ .E2BEGb({ \Inst_eFPGA.Tile_X9Y9_E2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEGb[0] }),
+ .E2BEG({ \Inst_eFPGA.Tile_X9Y9_E2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_E2BEG[0] }),
+ .E1BEG({ \Inst_eFPGA.Tile_X9Y9_E1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_E1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_E1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_E1BEG[0] }),
+ .Ci(\Inst_eFPGA.Tile_X9Y10_Co ),
+ .NN4END({ \Inst_eFPGA.Tile_X9Y10_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_NN4BEG[0] }),
+ .N4END({ \Inst_eFPGA.Tile_X9Y10_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_N4BEG[0] }),
+ .N2END({ \Inst_eFPGA.Tile_X9Y10_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEGb[0] }),
+ .N2MID({ \Inst_eFPGA.Tile_X9Y10_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_N2BEG[0] }),
+ .N1END({ \Inst_eFPGA.Tile_X9Y10_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y10_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y10_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y10_N1BEG[0] }),
+ .Co(\Inst_eFPGA.Tile_X9Y9_Co ),
+ .NN4BEG({ \Inst_eFPGA.Tile_X9Y9_NN4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_NN4BEG[0] }),
+ .N4BEG({ \Inst_eFPGA.Tile_X9Y9_N4BEG[15] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[14] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[13] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[12] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[11] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[10] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[9] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[8] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_N4BEG[0] }),
+ .N2BEGb({ \Inst_eFPGA.Tile_X9Y9_N2BEGb[7] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[6] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[5] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[4] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[3] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[2] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[1] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEGb[0] }),
+ .N2BEG({ \Inst_eFPGA.Tile_X9Y9_N2BEG[7] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[6] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[5] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[4] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_N2BEG[0] }),
+ .N1BEG({ \Inst_eFPGA.Tile_X9Y9_N1BEG[3] ,
+ \Inst_eFPGA.Tile_X9Y9_N1BEG[2] ,
+ \Inst_eFPGA.Tile_X9Y9_N1BEG[1] ,
+ \Inst_eFPGA.Tile_X9Y9_N1BEG[0] }),
+ .UserCLKo(\Inst_eFPGA.Tile_X9Y9_UserCLKo ));
+endmodule
+
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..a9756b4 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -1,123 +1,102 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_project_wrapper
- *
- * This wrapper enumerates all of the pins available to the
- * user for the user project.
- *
- * An example user project is provided in this wrapper. The
- * example should be removed and replaced with the actual
- * user project.
- *
- *-------------------------------------------------------------
- */
-
-module user_project_wrapper #(
- parameter BITS = 32
-) (
-`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
-`endif
-
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
-
- // IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb,
-
- // Analog (direct connection to GPIO pad---use with caution)
- // Note that analog I/O is not available on the 7 lowest-numbered
- // GPIO pads, and so the analog_io indexing is offset from the
- // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
- inout [`MPRJ_IO_PADS-10:0] analog_io,
-
- // Independent clock (on independent integer divider)
- input user_clock2,
-
- // User maskable interrupt signals
- output [2:0] user_irq
-);
-
-/*--------------------------------------*/
-/* User project is instantiated here */
-/*--------------------------------------*/
-
-user_proj_example mprj (
-`ifdef USE_POWER_PINS
- .vccd1(vccd1), // User area 1 1.8V power
- .vssd1(vssd1), // User area 1 digital ground
-`endif
-
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
-
- // Logic Analyzer
-
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
-
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
-
- // IRQ
- .irq(user_irq)
-);
-
-endmodule // user_project_wrapper
-
-`default_nettype wire
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper. The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+ parameter BITS = 32
+) (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-1:0] io_in,
+ output [`MPRJ_IO_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+ // Analog (direct connection to GPIO pad---use with caution)
+ // Note that analog I/O is not available on the 7 lowest-numbered
+ // GPIO pads, and so the analog_io indexing is offset from the
+ // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+ inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+eFPGA_top inst_eFPGA_top (
+ .wb_clk_i(wb_clk_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_o(wbs_dat_o),
+ .la_data_out(la_data_out[6:0]),
+ .io_in(io_in[37:7]),
+ .io_out(io_out[37:7]),
+ .io_oeb(io_oeb[37:7]),
+ .user_clock2(user_clock2)
+);
+
+endmodule // user_project_wrapper
+
+`default_nettype wire
\ No newline at end of file
